1 /*
2 
3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef NRF54H20_ENGA_TYPES_H
36 #define NRF54H20_ENGA_TYPES_H
37 
38 #ifdef __cplusplus
39     extern "C" {
40 #endif
41 
42 #include <stdint.h>
43 #include "compiler_abstraction.h"
44 
45 
46 /* ============================================ Include required type specifiers ============================================= */
47 
48 #ifndef __I
49   #ifdef __cplusplus
50     #define __I     volatile                         /*!< Defines 'read only' permissions                                      */
51   #else
52     #define __I     volatile const                   /*!< Defines 'read only' permissions                                      */
53   #endif
54 #endif
55 #ifndef __O
56   #define __O     volatile                           /*!< Defines 'write only' permissions                                     */
57 #endif
58 #ifndef __IO
59   #define __IO    volatile                           /*!< Defines 'read / write' permissions                                   */
60 #endif
61 
62 /* The following defines should be used for structure members */
63 #ifndef __IM
64   #define __IM     volatile const                    /*!< Defines 'read only' structure member permissions                     */
65 #endif
66 #ifndef __OM
67   #define __OM     volatile                          /*!< Defines 'write only' structure member permissions                    */
68 #endif
69 #ifndef __IOM
70   #define __IOM    volatile                          /*!< Defines 'read / write' structure member permissions                  */
71 #endif
72 
73 
74 /* ========================================= Start of section using anonymous unions ========================================= */
75 
76 #include "compiler_abstraction.h"
77 
78 #if defined (__CC_ARM)
79   #pragma push
80   #pragma anon_unions
81 #elif defined (__ICCARM__)
82   #pragma language=extended
83 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84   #pragma clang diagnostic push
85   #pragma clang diagnostic ignored "-Wc11-extensions"
86   #pragma clang diagnostic ignored "-Wreserved-id-macro"
87   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
88   #pragma clang diagnostic ignored "-Wnested-anon-types"
89 #elif defined (__GNUC__)
90   /* anonymous unions are enabled by default */
91 #elif defined (__TMS470__)
92   /* anonymous unions are enabled by default */
93 #elif defined (__TASKING__)
94   #pragma warning 586
95 #elif defined (__CSMC__)
96   /* anonymous unions are enabled by default */
97 #else
98   #warning Unsupported compiler type
99 #endif
100 
101 /* =========================================================================================================================== */
102 /* ================                                    Peripherals Section                                    ================ */
103 /* =========================================================================================================================== */
104 
105 
106 /* =========================================================================================================================== */
107 /* ================                                            AAR                                            ================ */
108 /* =========================================================================================================================== */
109 
110 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
111 
112 /* ====================================================== Struct AAR_IN ====================================================== */
113 /**
114   * @brief IN [AAR_IN] IN EasyDMA channel
115   */
116 typedef struct {
117   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Input pointer                                         */
118 } NRF_AAR_IN_Type;                                   /*!< Size = 4 (0x004)                                                     */
119 
120 /* AAR_IN_PTR: Input pointer */
121   #define AAR_IN_PTR_ResetValue (0x00000000UL)       /*!< Reset value of PTR register.                                         */
122 
123 /* PTR @Bits 0..31 : Points to a job list containing AAR data structure */
124   #define AAR_IN_PTR_PTR_Pos (0UL)                   /*!< Position of PTR field.                                               */
125   #define AAR_IN_PTR_PTR_Msk (0xFFFFFFFFUL << AAR_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                  */
126 
127 
128 /* ======================================================= Struct AAR ======================================================== */
129 /**
130   * @brief Accelerated Address Resolver
131   */
132   typedef struct {                                   /*!< AAR Structure                                                        */
133     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified in
134                                                                          the IRK data structure*/
135     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop resolving addresses                              */
136     __IM uint32_t RESERVED[30];
137     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
138     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
139     __IM uint32_t RESERVED1[30];
140     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000100) Address resolution procedure complete                 */
141     __IOM uint32_t EVENTS_RESOLVED;                  /*!< (@ 0x00000104) Address resolved                                      */
142     __IOM uint32_t EVENTS_NOTRESOLVED;               /*!< (@ 0x00000108) Address not resolved                                  */
143     __IM uint32_t RESERVED2[29];
144     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000180) Publish configuration for event END                   */
145     __IOM uint32_t PUBLISH_RESOLVED;                 /*!< (@ 0x00000184) Publish configuration for event RESOLVED              */
146     __IOM uint32_t PUBLISH_NOTRESOLVED;              /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED           */
147     __IM uint32_t RESERVED3[94];
148     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
149     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
150     __IM uint32_t RESERVED4[61];
151     __IM uint32_t STATUS;                            /*!< (@ 0x00000400) Resolution status                                     */
152     __IM uint32_t RESERVED5[63];
153     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable AAR                                            */
154     __IM uint32_t RESERVED6[11];
155     __IOM NRF_AAR_IN_Type IN;                        /*!< (@ 0x00000530) IN EasyDMA channel                                    */
156   } NRF_AAR_Type;                                    /*!< Size = 1332 (0x534)                                                  */
157 
158 /* AAR_TASKS_START: Start resolving addresses based on IRKs specified in the IRK data structure */
159   #define AAR_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
160 
161 /* TASKS_START @Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
162   #define AAR_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
163   #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
164   #define AAR_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
165   #define AAR_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
166   #define AAR_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
167 
168 
169 /* AAR_TASKS_STOP: Stop resolving addresses */
170   #define AAR_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
171 
172 /* TASKS_STOP @Bit 0 : Stop resolving addresses */
173   #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
174   #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
175   #define AAR_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
176   #define AAR_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
177   #define AAR_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
178 
179 
180 /* AAR_SUBSCRIBE_START: Subscribe configuration for task START */
181   #define AAR_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */
182 
183 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
184   #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
185   #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
186   #define AAR_SUBSCRIBE_START_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
187   #define AAR_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
188 
189 /* EN @Bit 31 : (unspecified) */
190   #define AAR_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
191   #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
192   #define AAR_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
193   #define AAR_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
194   #define AAR_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
195   #define AAR_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
196 
197 
198 /* AAR_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
199   #define AAR_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */
200 
201 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
202   #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
203   #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
204   #define AAR_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
205   #define AAR_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
206 
207 /* EN @Bit 31 : (unspecified) */
208   #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
209   #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
210   #define AAR_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
211   #define AAR_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
212   #define AAR_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
213   #define AAR_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
214 
215 
216 /* AAR_EVENTS_END: Address resolution procedure complete */
217   #define AAR_EVENTS_END_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_END register.                                  */
218 
219 /* EVENTS_END @Bit 0 : Address resolution procedure complete */
220   #define AAR_EVENTS_END_EVENTS_END_Pos (0UL)        /*!< Position of EVENTS_END field.                                        */
221   #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.            */
222   #define AAR_EVENTS_END_EVENTS_END_Min (0x0UL)      /*!< Min enumerator value of EVENTS_END field.                            */
223   #define AAR_EVENTS_END_EVENTS_END_Max (0x1UL)      /*!< Max enumerator value of EVENTS_END field.                            */
224   #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                              */
225   #define AAR_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                     */
226 
227 
228 /* AAR_EVENTS_RESOLVED: Address resolved */
229   #define AAR_EVENTS_RESOLVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESOLVED register.                          */
230 
231 /* EVENTS_RESOLVED @Bit 0 : Address resolved */
232   #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field.                                */
233   #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of
234                                                                             EVENTS_RESOLVED field.*/
235   #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESOLVED field.                  */
236   #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESOLVED field.                  */
237   #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0x0UL) /*!< Event not generated                                    */
238   #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (0x1UL) /*!< Event generated                                           */
239 
240 
241 /* AAR_EVENTS_NOTRESOLVED: Address not resolved */
242   #define AAR_EVENTS_NOTRESOLVED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_NOTRESOLVED register.                    */
243 
244 /* EVENTS_NOTRESOLVED @Bit 0 : Address not resolved */
245   #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field.                       */
246   #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask
247                                                                             of EVENTS_NOTRESOLVED field.*/
248   #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Min (0x0UL) /*!< Min enumerator value of EVENTS_NOTRESOLVED field.         */
249   #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Max (0x1UL) /*!< Max enumerator value of EVENTS_NOTRESOLVED field.         */
250   #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0x0UL) /*!< Event not generated                              */
251   #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (0x1UL) /*!< Event generated                                     */
252 
253 
254 /* AAR_PUBLISH_END: Publish configuration for event END */
255   #define AAR_PUBLISH_END_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_END register.                                 */
256 
257 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
258   #define AAR_PUBLISH_END_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
259   #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
260   #define AAR_PUBLISH_END_CHIDX_Min (0x0UL)          /*!< Min value of CHIDX field.                                            */
261   #define AAR_PUBLISH_END_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */
262 
263 /* EN @Bit 31 : (unspecified) */
264   #define AAR_PUBLISH_END_EN_Pos (31UL)              /*!< Position of EN field.                                                */
265   #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                  */
266   #define AAR_PUBLISH_END_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
267   #define AAR_PUBLISH_END_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
268   #define AAR_PUBLISH_END_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
269   #define AAR_PUBLISH_END_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */
270 
271 
272 /* AAR_PUBLISH_RESOLVED: Publish configuration for event RESOLVED */
273   #define AAR_PUBLISH_RESOLVED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESOLVED register.                        */
274 
275 /* CHIDX @Bits 0..7 : DPPI channel that event RESOLVED will publish to */
276   #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
277   #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
278   #define AAR_PUBLISH_RESOLVED_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
279   #define AAR_PUBLISH_RESOLVED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
280 
281 /* EN @Bit 31 : (unspecified) */
282   #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
283   #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field.                        */
284   #define AAR_PUBLISH_RESOLVED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
285   #define AAR_PUBLISH_RESOLVED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
286   #define AAR_PUBLISH_RESOLVED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
287   #define AAR_PUBLISH_RESOLVED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
288 
289 
290 /* AAR_PUBLISH_NOTRESOLVED: Publish configuration for event NOTRESOLVED */
291   #define AAR_PUBLISH_NOTRESOLVED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_NOTRESOLVED register.                  */
292 
293 /* CHIDX @Bits 0..7 : DPPI channel that event NOTRESOLVED will publish to */
294   #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
295   #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
296   #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
297   #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
298 
299 /* EN @Bit 31 : (unspecified) */
300   #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL)      /*!< Position of EN field.                                                */
301   #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field.                  */
302   #define AAR_PUBLISH_NOTRESOLVED_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
303   #define AAR_PUBLISH_NOTRESOLVED_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
304   #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
305   #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
306 
307 
308 /* AAR_INTENSET: Enable interrupt */
309   #define AAR_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
310 
311 /* END @Bit 0 : Write '1' to enable interrupt for event END */
312   #define AAR_INTENSET_END_Pos (0UL)                 /*!< Position of END field.                                               */
313   #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field.                                     */
314   #define AAR_INTENSET_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
315   #define AAR_INTENSET_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
316   #define AAR_INTENSET_END_Set (0x1UL)               /*!< Enable                                                               */
317   #define AAR_INTENSET_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
318   #define AAR_INTENSET_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
319 
320 /* RESOLVED @Bit 1 : Write '1' to enable interrupt for event RESOLVED */
321   #define AAR_INTENSET_RESOLVED_Pos (1UL)            /*!< Position of RESOLVED field.                                          */
322   #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field.                      */
323   #define AAR_INTENSET_RESOLVED_Min (0x0UL)          /*!< Min enumerator value of RESOLVED field.                              */
324   #define AAR_INTENSET_RESOLVED_Max (0x1UL)          /*!< Max enumerator value of RESOLVED field.                              */
325   #define AAR_INTENSET_RESOLVED_Set (0x1UL)          /*!< Enable                                                               */
326   #define AAR_INTENSET_RESOLVED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
327   #define AAR_INTENSET_RESOLVED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
328 
329 /* NOTRESOLVED @Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
330   #define AAR_INTENSET_NOTRESOLVED_Pos (2UL)         /*!< Position of NOTRESOLVED field.                                       */
331   #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field.             */
332   #define AAR_INTENSET_NOTRESOLVED_Min (0x0UL)       /*!< Min enumerator value of NOTRESOLVED field.                           */
333   #define AAR_INTENSET_NOTRESOLVED_Max (0x1UL)       /*!< Max enumerator value of NOTRESOLVED field.                           */
334   #define AAR_INTENSET_NOTRESOLVED_Set (0x1UL)       /*!< Enable                                                               */
335   #define AAR_INTENSET_NOTRESOLVED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
336   #define AAR_INTENSET_NOTRESOLVED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
337 
338 
339 /* AAR_INTENCLR: Disable interrupt */
340   #define AAR_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
341 
342 /* END @Bit 0 : Write '1' to disable interrupt for event END */
343   #define AAR_INTENCLR_END_Pos (0UL)                 /*!< Position of END field.                                               */
344   #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field.                                     */
345   #define AAR_INTENCLR_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
346   #define AAR_INTENCLR_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
347   #define AAR_INTENCLR_END_Clear (0x1UL)             /*!< Disable                                                              */
348   #define AAR_INTENCLR_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
349   #define AAR_INTENCLR_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
350 
351 /* RESOLVED @Bit 1 : Write '1' to disable interrupt for event RESOLVED */
352   #define AAR_INTENCLR_RESOLVED_Pos (1UL)            /*!< Position of RESOLVED field.                                          */
353   #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field.                      */
354   #define AAR_INTENCLR_RESOLVED_Min (0x0UL)          /*!< Min enumerator value of RESOLVED field.                              */
355   #define AAR_INTENCLR_RESOLVED_Max (0x1UL)          /*!< Max enumerator value of RESOLVED field.                              */
356   #define AAR_INTENCLR_RESOLVED_Clear (0x1UL)        /*!< Disable                                                              */
357   #define AAR_INTENCLR_RESOLVED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
358   #define AAR_INTENCLR_RESOLVED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
359 
360 /* NOTRESOLVED @Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
361   #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL)         /*!< Position of NOTRESOLVED field.                                       */
362   #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field.             */
363   #define AAR_INTENCLR_NOTRESOLVED_Min (0x0UL)       /*!< Min enumerator value of NOTRESOLVED field.                           */
364   #define AAR_INTENCLR_NOTRESOLVED_Max (0x1UL)       /*!< Max enumerator value of NOTRESOLVED field.                           */
365   #define AAR_INTENCLR_NOTRESOLVED_Clear (0x1UL)     /*!< Disable                                                              */
366   #define AAR_INTENCLR_NOTRESOLVED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
367   #define AAR_INTENCLR_NOTRESOLVED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
368 
369 
370 /* AAR_STATUS: Resolution status */
371   #define AAR_STATUS_ResetValue (0x00000000UL)       /*!< Reset value of STATUS register.                                      */
372 
373 /* STATUS @Bits 0..3 : The IRK that was used last time an address was resolved */
374   #define AAR_STATUS_STATUS_Pos (0UL)                /*!< Position of STATUS field.                                            */
375   #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field.                                */
376   #define AAR_STATUS_STATUS_Min (0x0UL)              /*!< Min value of STATUS field.                                           */
377   #define AAR_STATUS_STATUS_Max (0xFUL)              /*!< Max size of STATUS field.                                            */
378 
379 
380 /* AAR_ENABLE: Enable AAR */
381   #define AAR_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */
382 
383 /* ENABLE @Bits 0..1 : Enable or disable AAR */
384   #define AAR_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
385   #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
386   #define AAR_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
387   #define AAR_ENABLE_ENABLE_Max (0x3UL)              /*!< Max enumerator value of ENABLE field.                                */
388   #define AAR_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disable                                                              */
389   #define AAR_ENABLE_ENABLE_Enabled (0x3UL)          /*!< Enable                                                               */
390 
391 
392 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
393 
394 /* =========================================================================================================================== */
395 /* ================                                            ABB                                            ================ */
396 /* =========================================================================================================================== */
397 
398 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
399 /* ======================================================= Struct ABB ======================================================== */
400 /**
401   * @brief ABB peripheral
402   */
403   typedef struct {                                   /*!< ABB Structure                                                        */
404     __IM uint32_t RESERVED[256];
405     __IM uint32_t STATUS;                            /*!< (@ 0x00000400) ABB status                                            */
406     __IM uint32_t RESERVED1[31];
407     __IOM uint32_t MODE;                             /*!< (@ 0x00000480) ABB control                                           */
408   } NRF_ABB_Type;                                    /*!< Size = 1156 (0x484)                                                  */
409 
410 /* ABB_STATUS: ABB status */
411   #define ABB_STATUS_ResetValue (0x00000000UL)       /*!< Reset value of STATUS register.                                      */
412 
413 /* OPPOINT @Bits 0..1 : The current ABB operating point */
414   #define ABB_STATUS_OPPOINT_Pos (0UL)               /*!< Position of OPPOINT field.                                           */
415   #define ABB_STATUS_OPPOINT_Msk (0x3UL << ABB_STATUS_OPPOINT_Pos) /*!< Bit mask of OPPOINT field.                             */
416   #define ABB_STATUS_OPPOINT_Min (0x0UL)             /*!< Min enumerator value of OPPOINT field.                               */
417   #define ABB_STATUS_OPPOINT_Max (0x3UL)             /*!< Max enumerator value of OPPOINT field.                               */
418   #define ABB_STATUS_OPPOINT_OpPoint0V4 (0x0UL)      /*!< Operating point 0.4V                                                 */
419   #define ABB_STATUS_OPPOINT_OpPoint0V5 (0x1UL)      /*!< Operating point 0.5V                                                 */
420   #define ABB_STATUS_OPPOINT_OpPoint0V6 (0x2UL)      /*!< Operating point 0.6V                                                 */
421   #define ABB_STATUS_OPPOINT_OpPoint0V8 (0x3UL)      /*!< Operating point 0.8V                                                 */
422 
423 /* EN @Bit 4 : The ABB enable status. */
424   #define ABB_STATUS_EN_Pos (4UL)                    /*!< Position of EN field.                                                */
425   #define ABB_STATUS_EN_Msk (0x1UL << ABB_STATUS_EN_Pos) /*!< Bit mask of EN field.                                            */
426   #define ABB_STATUS_EN_Min (0x0UL)                  /*!< Min enumerator value of EN field.                                    */
427   #define ABB_STATUS_EN_Max (0x1UL)                  /*!< Max enumerator value of EN field.                                    */
428   #define ABB_STATUS_EN_Disabled (0x0UL)             /*!< ABB disabled                                                         */
429   #define ABB_STATUS_EN_Enabled (0x1UL)              /*!< ABB enabled                                                          */
430 
431 /* LOCKED @Bit 5 : The ABB lock status. */
432   #define ABB_STATUS_LOCKED_Pos (5UL)                /*!< Position of LOCKED field.                                            */
433   #define ABB_STATUS_LOCKED_Msk (0x1UL << ABB_STATUS_LOCKED_Pos) /*!< Bit mask of LOCKED field.                                */
434   #define ABB_STATUS_LOCKED_Min (0x0UL)              /*!< Min enumerator value of LOCKED field.                                */
435   #define ABB_STATUS_LOCKED_Max (0x1UL)              /*!< Max enumerator value of LOCKED field.                                */
436   #define ABB_STATUS_LOCKED_NotLocked (0x0UL)        /*!< Not locked                                                           */
437   #define ABB_STATUS_LOCKED_Locked (0x1UL)           /*!< Locked.                                                              */
438 
439 
440 /* ABB_MODE: ABB control */
441   #define ABB_MODE_ResetValue (0x00000000UL)         /*!< Reset value of MODE register.                                        */
442 
443 /* OPPOINT @Bits 0..2 : The ABB operating point. */
444   #define ABB_MODE_OPPOINT_Pos (0UL)                 /*!< Position of OPPOINT field.                                           */
445   #define ABB_MODE_OPPOINT_Msk (0x7UL << ABB_MODE_OPPOINT_Pos) /*!< Bit mask of OPPOINT field.                                 */
446   #define ABB_MODE_OPPOINT_Min (0x0UL)               /*!< Min enumerator value of OPPOINT field.                               */
447   #define ABB_MODE_OPPOINT_Max (0x4UL)               /*!< Max enumerator value of OPPOINT field.                               */
448   #define ABB_MODE_OPPOINT_Auto (0x0UL)              /*!< The peripheral controls the operating point automatically based on
449                                                           request from the master ABB controller.*/
450   #define ABB_MODE_OPPOINT_OpPoint0V4 (0x1UL)        /*!< Force the operating point to 0.4V                                    */
451   #define ABB_MODE_OPPOINT_OpPoint0V5 (0x2UL)        /*!< Force the operating point to 0.5V                                    */
452   #define ABB_MODE_OPPOINT_OpPoint0V6 (0x3UL)        /*!< Force the operating point to 0.6V                                    */
453   #define ABB_MODE_OPPOINT_OpPoint0V8 (0x4UL)        /*!< Force the operating point to 0.8V                                    */
454 
455 /* ABBEN @Bits 4..5 : Enable ABB. */
456   #define ABB_MODE_ABBEN_Pos (4UL)                   /*!< Position of ABBEN field.                                             */
457   #define ABB_MODE_ABBEN_Msk (0x3UL << ABB_MODE_ABBEN_Pos) /*!< Bit mask of ABBEN field.                                       */
458   #define ABB_MODE_ABBEN_Min (0x0UL)                 /*!< Min enumerator value of ABBEN field.                                 */
459   #define ABB_MODE_ABBEN_Max (0x2UL)                 /*!< Max enumerator value of ABBEN field.                                 */
460   #define ABB_MODE_ABBEN_Auto (0x0UL)                /*!< The peripheral controls the ABB enable automatically based on
461                                                           request.*/
462   #define ABB_MODE_ABBEN_Enable (0x1UL)              /*!< Force enable ABB                                                     */
463   #define ABB_MODE_ABBEN_Disable (0x2UL)             /*!< Force disable ABB                                                    */
464 
465 
466 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
467 
468 /* =========================================================================================================================== */
469 /* ================                                         ATBFUNNEL                                         ================ */
470 /* =========================================================================================================================== */
471 
472 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
473 /* ==================================================== Struct ATBFUNNEL ===================================================== */
474 /**
475   * @brief ATB funnel module
476   */
477   typedef struct {                                   /*!< ATBFUNNEL Structure                                                  */
478     __IOM uint32_t CTRLREG;                          /*!< (@ 0x00000000) The IDFILTER0 register enables the programming of ID
479                                                                          filtering for master port 0.*/
480     __IOM uint32_t PRIORITYCTRLREG;                  /*!< (@ 0x00000004) The Priority_Ctrl_Reg register defines the order in
481                                                                          which inputs are selected. Each 3-bit field is a
482                                                                          priority for each particular slave interface.*/
483     __IM uint32_t RESERVED[953];
484     __IOM uint32_t ITATBDATA0;                       /*!< (@ 0x00000EEC) The ITATBDATA0 register performs different functions
485                                                                          depending on whether the access is a read or a write.*/
486     __IOM uint32_t ITATBCTR2;                        /*!< (@ 0x00000EF0) The ITATBCTR2 register performs different functions
487                                                                          depending on whether the access is a read or a write.*/
488     __IOM uint32_t ITATBCTR1;                        /*!< (@ 0x00000EF4) The ITATBCTR1 register performs different functions
489                                                                          depending on whether the access is a read or a write.*/
490     __IOM uint32_t ITATBCTR0;                        /*!< (@ 0x00000EF8) The ITATBCTR0 register performs different functions
491                                                                          depending on whether the access is a read or a write.*/
492     __IM uint32_t RESERVED1;
493     __IOM uint32_t ITCTRL;                           /*!< (@ 0x00000F00) The ITCTRL register enables the component to switch
494                                                                          from a functional mode, which is the default behavior,
495                                                                          to integration mode where the inputs and outputs of the
496                                                                          component can be directly controlled for the purposes
497                                                                          of integration testing and topology detection.*/
498     __IM uint32_t RESERVED2[39];
499     __IOM uint32_t CLAIMSET;                         /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate
500                                                                          application and debugger access to trace unit
501                                                                          functionality. The claim tags have no effect on the
502                                                                          operation of the component. The CLAIMSET register sets
503                                                                          bits in the claim tag, and determines the number of
504                                                                          claim bits implemented.*/
505     __IOM uint32_t CLAIMCLR;                         /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate
506                                                                          application and debugger access to trace unit
507                                                                          functionality. The claim tags have no effect on the
508                                                                          operation of the component. The CLAIMCLR register sets
509                                                                          the bits in the claim tag to 0 and determines the
510                                                                          current value of the claim tag.*/
511     __IM uint32_t RESERVED3[2];
512     __IOM uint32_t LAR;                              /*!< (@ 0x00000FB0) This is used to enable write access to device
513                                                                          registers.*/
514     __IOM uint32_t LSR;                              /*!< (@ 0x00000FB4) This indicates the status of the lock control
515                                                                          mechanism. This lock prevents accidental writes by code
516                                                                          under debug. Accesses to the extended stimulus port
517                                                                          registers are not affected by the lock mechanism. This
518                                                                          register must always be present although there might
519                                                                          not be any lock access control mechanism. The lock
520                                                                          mechanism, where present and locked, must block write
521                                                                          accesses to any control register, except the Lock
522                                                                          Access Register. For most components this covers all
523                                                                          registers except for the Lock Access Register.*/
524     __IOM uint32_t AUTHSTATUS;                       /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the
525                                                                          system*/
526     __IM uint32_t RESERVED4[3];
527     __IM uint32_t DEVID;                             /*!< (@ 0x00000FC8) Indicates the capabilities of the component.          */
528     __IM uint32_t DEVTYPE;                           /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with
529                                                                          information about the component when the Part Number
530                                                                          field is not recognized. The debugger can then report
531                                                                          this information.*/
532     __IOM uint32_t PIDR4;                            /*!< (@ 0x00000FD0) Coresight peripheral identification registers.        */
533     __IM uint32_t RESERVED5[3];
534     __IOM uint32_t PIDR0;                            /*!< (@ 0x00000FE0) Coresight peripheral identification registers.        */
535     __IOM uint32_t PIDR1;                            /*!< (@ 0x00000FE4) Coresight peripheral identification registers.        */
536     __IOM uint32_t PIDR2;                            /*!< (@ 0x00000FE8) Coresight peripheral identification registers.        */
537     __IOM uint32_t PIDR3;                            /*!< (@ 0x00000FEC) Coresight peripheral identification registers.        */
538     __IOM uint32_t CIDR0;                            /*!< (@ 0x00000FF0) Coresight component identification registers.         */
539     __IOM uint32_t CIDR1;                            /*!< (@ 0x00000FF4) Coresight component identification registers.         */
540     __IOM uint32_t CIDR2;                            /*!< (@ 0x00000FF8) Coresight component identification registers.         */
541     __IOM uint32_t CIDR3;                            /*!< (@ 0x00000FFC) Coresight component identification registers.         */
542   } NRF_ATBFUNNEL_Type;                              /*!< Size = 4096 (0x1000)                                                 */
543 
544 /* ATBFUNNEL_CTRLREG: The IDFILTER0 register enables the programming of ID filtering for master port 0. */
545   #define ATBFUNNEL_CTRLREG_ResetValue (0x00000000UL) /*!< Reset value of CTRLREG register.                                    */
546 
547 /* ENS0 @Bit 0 : Enable slave port 0. */
548   #define ATBFUNNEL_CTRLREG_ENS0_Pos (0UL)           /*!< Position of ENS0 field.                                              */
549   #define ATBFUNNEL_CTRLREG_ENS0_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS0_Pos) /*!< Bit mask of ENS0 field.                        */
550   #define ATBFUNNEL_CTRLREG_ENS0_Min (0x0UL)         /*!< Min enumerator value of ENS0 field.                                  */
551   #define ATBFUNNEL_CTRLREG_ENS0_Max (0x1UL)         /*!< Max enumerator value of ENS0 field.                                  */
552   #define ATBFUNNEL_CTRLREG_ENS0_Disabled (0x0UL)    /*!< Slave port disabled. This excludes the port from the priority
553                                                           selection scheme.*/
554   #define ATBFUNNEL_CTRLREG_ENS0_Enabled (0x1UL)     /*!< Slave port enabled.                                                  */
555 
556 /* ENS1 @Bit 1 : Enable slave port 1. */
557   #define ATBFUNNEL_CTRLREG_ENS1_Pos (1UL)           /*!< Position of ENS1 field.                                              */
558   #define ATBFUNNEL_CTRLREG_ENS1_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS1_Pos) /*!< Bit mask of ENS1 field.                        */
559   #define ATBFUNNEL_CTRLREG_ENS1_Min (0x0UL)         /*!< Min enumerator value of ENS1 field.                                  */
560   #define ATBFUNNEL_CTRLREG_ENS1_Max (0x1UL)         /*!< Max enumerator value of ENS1 field.                                  */
561   #define ATBFUNNEL_CTRLREG_ENS1_Disabled (0x0UL)    /*!< Slave port disabled. This excludes the port from the priority
562                                                           selection scheme.*/
563   #define ATBFUNNEL_CTRLREG_ENS1_Enabled (0x1UL)     /*!< Slave port enabled.                                                  */
564 
565 /* ENS2 @Bit 2 : Enable slave port 2. */
566   #define ATBFUNNEL_CTRLREG_ENS2_Pos (2UL)           /*!< Position of ENS2 field.                                              */
567   #define ATBFUNNEL_CTRLREG_ENS2_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS2_Pos) /*!< Bit mask of ENS2 field.                        */
568   #define ATBFUNNEL_CTRLREG_ENS2_Min (0x0UL)         /*!< Min enumerator value of ENS2 field.                                  */
569   #define ATBFUNNEL_CTRLREG_ENS2_Max (0x1UL)         /*!< Max enumerator value of ENS2 field.                                  */
570   #define ATBFUNNEL_CTRLREG_ENS2_Disabled (0x0UL)    /*!< Slave port disabled. This excludes the port from the priority
571                                                           selection scheme.*/
572   #define ATBFUNNEL_CTRLREG_ENS2_Enabled (0x1UL)     /*!< Slave port enabled.                                                  */
573 
574 /* ENS3 @Bit 3 : Enable slave port 3. */
575   #define ATBFUNNEL_CTRLREG_ENS3_Pos (3UL)           /*!< Position of ENS3 field.                                              */
576   #define ATBFUNNEL_CTRLREG_ENS3_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS3_Pos) /*!< Bit mask of ENS3 field.                        */
577   #define ATBFUNNEL_CTRLREG_ENS3_Min (0x0UL)         /*!< Min enumerator value of ENS3 field.                                  */
578   #define ATBFUNNEL_CTRLREG_ENS3_Max (0x1UL)         /*!< Max enumerator value of ENS3 field.                                  */
579   #define ATBFUNNEL_CTRLREG_ENS3_Disabled (0x0UL)    /*!< Slave port disabled. This excludes the port from the priority
580                                                           selection scheme.*/
581   #define ATBFUNNEL_CTRLREG_ENS3_Enabled (0x1UL)     /*!< Slave port enabled.                                                  */
582 
583 /* ENS4 @Bit 4 : Enable slave port 4. */
584   #define ATBFUNNEL_CTRLREG_ENS4_Pos (4UL)           /*!< Position of ENS4 field.                                              */
585   #define ATBFUNNEL_CTRLREG_ENS4_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS4_Pos) /*!< Bit mask of ENS4 field.                        */
586   #define ATBFUNNEL_CTRLREG_ENS4_Min (0x0UL)         /*!< Min enumerator value of ENS4 field.                                  */
587   #define ATBFUNNEL_CTRLREG_ENS4_Max (0x1UL)         /*!< Max enumerator value of ENS4 field.                                  */
588   #define ATBFUNNEL_CTRLREG_ENS4_Disabled (0x0UL)    /*!< Slave port disabled. This excludes the port from the priority
589                                                           selection scheme.*/
590   #define ATBFUNNEL_CTRLREG_ENS4_Enabled (0x1UL)     /*!< Slave port enabled.                                                  */
591 
592 /* ENS5 @Bit 5 : Enable slave port 5. */
593   #define ATBFUNNEL_CTRLREG_ENS5_Pos (5UL)           /*!< Position of ENS5 field.                                              */
594   #define ATBFUNNEL_CTRLREG_ENS5_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS5_Pos) /*!< Bit mask of ENS5 field.                        */
595   #define ATBFUNNEL_CTRLREG_ENS5_Min (0x0UL)         /*!< Min enumerator value of ENS5 field.                                  */
596   #define ATBFUNNEL_CTRLREG_ENS5_Max (0x1UL)         /*!< Max enumerator value of ENS5 field.                                  */
597   #define ATBFUNNEL_CTRLREG_ENS5_Disabled (0x0UL)    /*!< Slave port disabled. This excludes the port from the priority
598                                                           selection scheme.*/
599   #define ATBFUNNEL_CTRLREG_ENS5_Enabled (0x1UL)     /*!< Slave port enabled.                                                  */
600 
601 /* ENS6 @Bit 6 : Enable slave port 6. */
602   #define ATBFUNNEL_CTRLREG_ENS6_Pos (6UL)           /*!< Position of ENS6 field.                                              */
603   #define ATBFUNNEL_CTRLREG_ENS6_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS6_Pos) /*!< Bit mask of ENS6 field.                        */
604   #define ATBFUNNEL_CTRLREG_ENS6_Min (0x0UL)         /*!< Min enumerator value of ENS6 field.                                  */
605   #define ATBFUNNEL_CTRLREG_ENS6_Max (0x1UL)         /*!< Max enumerator value of ENS6 field.                                  */
606   #define ATBFUNNEL_CTRLREG_ENS6_Disabled (0x0UL)    /*!< Slave port disabled. This excludes the port from the priority
607                                                           selection scheme.*/
608   #define ATBFUNNEL_CTRLREG_ENS6_Enabled (0x1UL)     /*!< Slave port enabled.                                                  */
609 
610 /* ENS7 @Bit 7 : Enable slave port 7. */
611   #define ATBFUNNEL_CTRLREG_ENS7_Pos (7UL)           /*!< Position of ENS7 field.                                              */
612   #define ATBFUNNEL_CTRLREG_ENS7_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS7_Pos) /*!< Bit mask of ENS7 field.                        */
613   #define ATBFUNNEL_CTRLREG_ENS7_Min (0x0UL)         /*!< Min enumerator value of ENS7 field.                                  */
614   #define ATBFUNNEL_CTRLREG_ENS7_Max (0x1UL)         /*!< Max enumerator value of ENS7 field.                                  */
615   #define ATBFUNNEL_CTRLREG_ENS7_Disabled (0x0UL)    /*!< Slave port disabled. This excludes the port from the priority
616                                                           selection scheme.*/
617   #define ATBFUNNEL_CTRLREG_ENS7_Enabled (0x1UL)     /*!< Slave port enabled.                                                  */
618 
619 /* HT @Bits 8..11 : Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this
620                     setting to minimize switching. When a source has nothing to transmit, then another source is selected
621                     irrespective of the minimum number of transactions. The ATB funnel holds for the minimum hold time and one
622                     additional transaction. The actual hold time is the register value plus 1. The maximum value that can be
623                     entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. */
624 
625   #define ATBFUNNEL_CTRLREG_HT_Pos (8UL)             /*!< Position of HT field.                                                */
626   #define ATBFUNNEL_CTRLREG_HT_Msk (0xFUL << ATBFUNNEL_CTRLREG_HT_Pos) /*!< Bit mask of HT field.                              */
627   #define ATBFUNNEL_CTRLREG_HT_Min (0x0UL)           /*!< Min value of HT field.                                               */
628   #define ATBFUNNEL_CTRLREG_HT_Max (0xEUL)           /*!< Max size of HT field.                                                */
629 
630 
631 /* ATBFUNNEL_PRIORITYCTRLREG: The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is
632                                a priority for each particular slave interface. */
633 
634   #define ATBFUNNEL_PRIORITYCTRLREG_ResetValue (0x00000000UL) /*!< Reset value of PRIORITYCTRLREG register.                    */
635 
636 /* PRIPORT0 @Bits 0..2 : Priority value of port number 0. */
637   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Pos (0UL) /*!< Position of PRIPORT0 field.                                        */
638   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Pos) /*!< Bit mask of PRIPORT0
639                                                                             field.*/
640   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Min (0x0UL) /*!< Min value of PRIPORT0 field.                                     */
641   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Max (0x7UL) /*!< Max size of PRIPORT0 field.                                      */
642 
643 /* PRIPORT1 @Bits 3..5 : Priority value of port number 1. */
644   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Pos (3UL) /*!< Position of PRIPORT1 field.                                        */
645   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Pos) /*!< Bit mask of PRIPORT1
646                                                                             field.*/
647   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Min (0x0UL) /*!< Min value of PRIPORT1 field.                                     */
648   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Max (0x7UL) /*!< Max size of PRIPORT1 field.                                      */
649 
650 /* PRIPORT2 @Bits 6..8 : Priority value of port number 2. */
651   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Pos (6UL) /*!< Position of PRIPORT2 field.                                        */
652   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Pos) /*!< Bit mask of PRIPORT2
653                                                                             field.*/
654   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Min (0x0UL) /*!< Min value of PRIPORT2 field.                                     */
655   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Max (0x7UL) /*!< Max size of PRIPORT2 field.                                      */
656 
657 /* PRIPORT3 @Bits 9..11 : Priority value of port number 3. */
658   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Pos (9UL) /*!< Position of PRIPORT3 field.                                        */
659   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Pos) /*!< Bit mask of PRIPORT3
660                                                                             field.*/
661   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Min (0x0UL) /*!< Min value of PRIPORT3 field.                                     */
662   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Max (0x7UL) /*!< Max size of PRIPORT3 field.                                      */
663 
664 /* PRIPORT4 @Bits 12..14 : Priority value of port number 4. */
665   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Pos (12UL) /*!< Position of PRIPORT4 field.                                       */
666   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Pos) /*!< Bit mask of PRIPORT4
667                                                                             field.*/
668   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Min (0x0UL) /*!< Min value of PRIPORT4 field.                                     */
669   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Max (0x7UL) /*!< Max size of PRIPORT4 field.                                      */
670 
671 /* PRIPORT5 @Bits 15..17 : Priority value of port number 5. */
672   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Pos (15UL) /*!< Position of PRIPORT5 field.                                       */
673   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Pos) /*!< Bit mask of PRIPORT5
674                                                                             field.*/
675   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Min (0x0UL) /*!< Min value of PRIPORT5 field.                                     */
676   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Max (0x7UL) /*!< Max size of PRIPORT5 field.                                      */
677 
678 /* PRIPORT6 @Bits 18..20 : Priority value of port number 6. */
679   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Pos (18UL) /*!< Position of PRIPORT6 field.                                       */
680   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Pos) /*!< Bit mask of PRIPORT6
681                                                                             field.*/
682   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Min (0x0UL) /*!< Min value of PRIPORT6 field.                                     */
683   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Max (0x7UL) /*!< Max size of PRIPORT6 field.                                      */
684 
685 /* PRIPORT7 @Bits 21..23 : Priority value of port number 7. */
686   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Pos (21UL) /*!< Position of PRIPORT7 field.                                       */
687   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Pos) /*!< Bit mask of PRIPORT7
688                                                                             field.*/
689   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Min (0x0UL) /*!< Min value of PRIPORT7 field.                                     */
690   #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Max (0x7UL) /*!< Max size of PRIPORT7 field.                                      */
691 
692 
693 /* ATBFUNNEL_ITATBDATA0: The ITATBDATA0 register performs different functions depending on whether the access is a read or a
694                           write. */
695 
696   #define ATBFUNNEL_ITATBDATA0_ResetValue (0x00000000UL) /*!< Reset value of ITATBDATA0 register.                              */
697 
698 /* ATDATA0 @Bit 0 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
699                     corresponding atdatam pin of the enabled port. */
700 
701   #define ATBFUNNEL_ITATBDATA0_ATDATA0_Pos (0UL)     /*!< Position of ATDATA0 field.                                           */
702   #define ATBFUNNEL_ITATBDATA0_ATDATA0_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA0_Pos) /*!< Bit mask of ATDATA0 field.         */
703   #define ATBFUNNEL_ITATBDATA0_ATDATA0_Min (0x0UL)   /*!< Min enumerator value of ATDATA0 field.                               */
704   #define ATBFUNNEL_ITATBDATA0_ATDATA0_Max (0x1UL)   /*!< Max enumerator value of ATDATA0 field.                               */
705   #define ATBFUNNEL_ITATBDATA0_ATDATA0_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
706   #define ATBFUNNEL_ITATBDATA0_ATDATA0_High (0x1UL)  /*!< Pin is logic 1.                                                      */
707 
708 /* ATDATA1 @Bit 1 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
709                     corresponding atdatam pin of the enabled port. */
710 
711   #define ATBFUNNEL_ITATBDATA0_ATDATA1_Pos (1UL)     /*!< Position of ATDATA1 field.                                           */
712   #define ATBFUNNEL_ITATBDATA0_ATDATA1_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA1_Pos) /*!< Bit mask of ATDATA1 field.         */
713   #define ATBFUNNEL_ITATBDATA0_ATDATA1_Min (0x0UL)   /*!< Min enumerator value of ATDATA1 field.                               */
714   #define ATBFUNNEL_ITATBDATA0_ATDATA1_Max (0x1UL)   /*!< Max enumerator value of ATDATA1 field.                               */
715   #define ATBFUNNEL_ITATBDATA0_ATDATA1_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
716   #define ATBFUNNEL_ITATBDATA0_ATDATA1_High (0x1UL)  /*!< Pin is logic 1.                                                      */
717 
718 /* ATDATA2 @Bit 2 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
719                     corresponding atdatam pin of the enabled port. */
720 
721   #define ATBFUNNEL_ITATBDATA0_ATDATA2_Pos (2UL)     /*!< Position of ATDATA2 field.                                           */
722   #define ATBFUNNEL_ITATBDATA0_ATDATA2_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA2_Pos) /*!< Bit mask of ATDATA2 field.         */
723   #define ATBFUNNEL_ITATBDATA0_ATDATA2_Min (0x0UL)   /*!< Min enumerator value of ATDATA2 field.                               */
724   #define ATBFUNNEL_ITATBDATA0_ATDATA2_Max (0x1UL)   /*!< Max enumerator value of ATDATA2 field.                               */
725   #define ATBFUNNEL_ITATBDATA0_ATDATA2_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
726   #define ATBFUNNEL_ITATBDATA0_ATDATA2_High (0x1UL)  /*!< Pin is logic 1.                                                      */
727 
728 /* ATDATA3 @Bit 3 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
729                     corresponding atdatam pin of the enabled port. */
730 
731   #define ATBFUNNEL_ITATBDATA0_ATDATA3_Pos (3UL)     /*!< Position of ATDATA3 field.                                           */
732   #define ATBFUNNEL_ITATBDATA0_ATDATA3_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA3_Pos) /*!< Bit mask of ATDATA3 field.         */
733   #define ATBFUNNEL_ITATBDATA0_ATDATA3_Min (0x0UL)   /*!< Min enumerator value of ATDATA3 field.                               */
734   #define ATBFUNNEL_ITATBDATA0_ATDATA3_Max (0x1UL)   /*!< Max enumerator value of ATDATA3 field.                               */
735   #define ATBFUNNEL_ITATBDATA0_ATDATA3_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
736   #define ATBFUNNEL_ITATBDATA0_ATDATA3_High (0x1UL)  /*!< Pin is logic 1.                                                      */
737 
738 /* ATDATA4 @Bit 4 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
739                     corresponding atdatam pin of the enabled port. */
740 
741   #define ATBFUNNEL_ITATBDATA0_ATDATA4_Pos (4UL)     /*!< Position of ATDATA4 field.                                           */
742   #define ATBFUNNEL_ITATBDATA0_ATDATA4_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA4_Pos) /*!< Bit mask of ATDATA4 field.         */
743   #define ATBFUNNEL_ITATBDATA0_ATDATA4_Min (0x0UL)   /*!< Min enumerator value of ATDATA4 field.                               */
744   #define ATBFUNNEL_ITATBDATA0_ATDATA4_Max (0x1UL)   /*!< Max enumerator value of ATDATA4 field.                               */
745   #define ATBFUNNEL_ITATBDATA0_ATDATA4_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
746   #define ATBFUNNEL_ITATBDATA0_ATDATA4_High (0x1UL)  /*!< Pin is logic 1.                                                      */
747 
748 /* ATDATA5 @Bit 5 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
749                     corresponding atdatam pin of the enabled port. */
750 
751   #define ATBFUNNEL_ITATBDATA0_ATDATA5_Pos (5UL)     /*!< Position of ATDATA5 field.                                           */
752   #define ATBFUNNEL_ITATBDATA0_ATDATA5_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA5_Pos) /*!< Bit mask of ATDATA5 field.         */
753   #define ATBFUNNEL_ITATBDATA0_ATDATA5_Min (0x0UL)   /*!< Min enumerator value of ATDATA5 field.                               */
754   #define ATBFUNNEL_ITATBDATA0_ATDATA5_Max (0x1UL)   /*!< Max enumerator value of ATDATA5 field.                               */
755   #define ATBFUNNEL_ITATBDATA0_ATDATA5_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
756   #define ATBFUNNEL_ITATBDATA0_ATDATA5_High (0x1UL)  /*!< Pin is logic 1.                                                      */
757 
758 /* ATDATA6 @Bit 6 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
759                     corresponding atdatam pin of the enabled port. */
760 
761   #define ATBFUNNEL_ITATBDATA0_ATDATA6_Pos (6UL)     /*!< Position of ATDATA6 field.                                           */
762   #define ATBFUNNEL_ITATBDATA0_ATDATA6_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA6_Pos) /*!< Bit mask of ATDATA6 field.         */
763   #define ATBFUNNEL_ITATBDATA0_ATDATA6_Min (0x0UL)   /*!< Min enumerator value of ATDATA6 field.                               */
764   #define ATBFUNNEL_ITATBDATA0_ATDATA6_Max (0x1UL)   /*!< Max enumerator value of ATDATA6 field.                               */
765   #define ATBFUNNEL_ITATBDATA0_ATDATA6_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
766   #define ATBFUNNEL_ITATBDATA0_ATDATA6_High (0x1UL)  /*!< Pin is logic 1.                                                      */
767 
768 /* ATDATA7 @Bit 7 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
769                     corresponding atdatam pin of the enabled port. */
770 
771   #define ATBFUNNEL_ITATBDATA0_ATDATA7_Pos (7UL)     /*!< Position of ATDATA7 field.                                           */
772   #define ATBFUNNEL_ITATBDATA0_ATDATA7_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA7_Pos) /*!< Bit mask of ATDATA7 field.         */
773   #define ATBFUNNEL_ITATBDATA0_ATDATA7_Min (0x0UL)   /*!< Min enumerator value of ATDATA7 field.                               */
774   #define ATBFUNNEL_ITATBDATA0_ATDATA7_Max (0x1UL)   /*!< Max enumerator value of ATDATA7 field.                               */
775   #define ATBFUNNEL_ITATBDATA0_ATDATA7_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
776   #define ATBFUNNEL_ITATBDATA0_ATDATA7_High (0x1UL)  /*!< Pin is logic 1.                                                      */
777 
778 /* ATDATA8 @Bit 8 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
779                     corresponding atdatam pin of the enabled port. */
780 
781   #define ATBFUNNEL_ITATBDATA0_ATDATA8_Pos (8UL)     /*!< Position of ATDATA8 field.                                           */
782   #define ATBFUNNEL_ITATBDATA0_ATDATA8_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA8_Pos) /*!< Bit mask of ATDATA8 field.         */
783   #define ATBFUNNEL_ITATBDATA0_ATDATA8_Min (0x0UL)   /*!< Min enumerator value of ATDATA8 field.                               */
784   #define ATBFUNNEL_ITATBDATA0_ATDATA8_Max (0x1UL)   /*!< Max enumerator value of ATDATA8 field.                               */
785   #define ATBFUNNEL_ITATBDATA0_ATDATA8_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
786   #define ATBFUNNEL_ITATBDATA0_ATDATA8_High (0x1UL)  /*!< Pin is logic 1.                                                      */
787 
788 /* ATDATA9 @Bit 9 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
789                     corresponding atdatam pin of the enabled port. */
790 
791   #define ATBFUNNEL_ITATBDATA0_ATDATA9_Pos (9UL)     /*!< Position of ATDATA9 field.                                           */
792   #define ATBFUNNEL_ITATBDATA0_ATDATA9_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA9_Pos) /*!< Bit mask of ATDATA9 field.         */
793   #define ATBFUNNEL_ITATBDATA0_ATDATA9_Min (0x0UL)   /*!< Min enumerator value of ATDATA9 field.                               */
794   #define ATBFUNNEL_ITATBDATA0_ATDATA9_Max (0x1UL)   /*!< Max enumerator value of ATDATA9 field.                               */
795   #define ATBFUNNEL_ITATBDATA0_ATDATA9_Low (0x0UL)   /*!< Pin is logic 0.                                                      */
796   #define ATBFUNNEL_ITATBDATA0_ATDATA9_High (0x1UL)  /*!< Pin is logic 1.                                                      */
797 
798 /* ATDATA10 @Bit 10 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
799                       corresponding atdatam pin of the enabled port. */
800 
801   #define ATBFUNNEL_ITATBDATA0_ATDATA10_Pos (10UL)   /*!< Position of ATDATA10 field.                                          */
802   #define ATBFUNNEL_ITATBDATA0_ATDATA10_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA10_Pos) /*!< Bit mask of ATDATA10 field.      */
803   #define ATBFUNNEL_ITATBDATA0_ATDATA10_Min (0x0UL)  /*!< Min enumerator value of ATDATA10 field.                              */
804   #define ATBFUNNEL_ITATBDATA0_ATDATA10_Max (0x1UL)  /*!< Max enumerator value of ATDATA10 field.                              */
805   #define ATBFUNNEL_ITATBDATA0_ATDATA10_Low (0x0UL)  /*!< Pin is logic 0.                                                      */
806   #define ATBFUNNEL_ITATBDATA0_ATDATA10_High (0x1UL) /*!< Pin is logic 1.                                                      */
807 
808 /* ATDATA11 @Bit 11 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
809                       corresponding atdatam pin of the enabled port. */
810 
811   #define ATBFUNNEL_ITATBDATA0_ATDATA11_Pos (11UL)   /*!< Position of ATDATA11 field.                                          */
812   #define ATBFUNNEL_ITATBDATA0_ATDATA11_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA11_Pos) /*!< Bit mask of ATDATA11 field.      */
813   #define ATBFUNNEL_ITATBDATA0_ATDATA11_Min (0x0UL)  /*!< Min enumerator value of ATDATA11 field.                              */
814   #define ATBFUNNEL_ITATBDATA0_ATDATA11_Max (0x1UL)  /*!< Max enumerator value of ATDATA11 field.                              */
815   #define ATBFUNNEL_ITATBDATA0_ATDATA11_Low (0x0UL)  /*!< Pin is logic 0.                                                      */
816   #define ATBFUNNEL_ITATBDATA0_ATDATA11_High (0x1UL) /*!< Pin is logic 1.                                                      */
817 
818 /* ATDATA12 @Bit 12 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
819                       corresponding atdatam pin of the enabled port. */
820 
821   #define ATBFUNNEL_ITATBDATA0_ATDATA12_Pos (12UL)   /*!< Position of ATDATA12 field.                                          */
822   #define ATBFUNNEL_ITATBDATA0_ATDATA12_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA12_Pos) /*!< Bit mask of ATDATA12 field.      */
823   #define ATBFUNNEL_ITATBDATA0_ATDATA12_Min (0x0UL)  /*!< Min enumerator value of ATDATA12 field.                              */
824   #define ATBFUNNEL_ITATBDATA0_ATDATA12_Max (0x1UL)  /*!< Max enumerator value of ATDATA12 field.                              */
825   #define ATBFUNNEL_ITATBDATA0_ATDATA12_Low (0x0UL)  /*!< Pin is logic 0.                                                      */
826   #define ATBFUNNEL_ITATBDATA0_ATDATA12_High (0x1UL) /*!< Pin is logic 1.                                                      */
827 
828 /* ATDATA13 @Bit 13 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
829                       corresponding atdatam pin of the enabled port. */
830 
831   #define ATBFUNNEL_ITATBDATA0_ATDATA13_Pos (13UL)   /*!< Position of ATDATA13 field.                                          */
832   #define ATBFUNNEL_ITATBDATA0_ATDATA13_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA13_Pos) /*!< Bit mask of ATDATA13 field.      */
833   #define ATBFUNNEL_ITATBDATA0_ATDATA13_Min (0x0UL)  /*!< Min enumerator value of ATDATA13 field.                              */
834   #define ATBFUNNEL_ITATBDATA0_ATDATA13_Max (0x1UL)  /*!< Max enumerator value of ATDATA13 field.                              */
835   #define ATBFUNNEL_ITATBDATA0_ATDATA13_Low (0x0UL)  /*!< Pin is logic 0.                                                      */
836   #define ATBFUNNEL_ITATBDATA0_ATDATA13_High (0x1UL) /*!< Pin is logic 1.                                                      */
837 
838 /* ATDATA14 @Bit 14 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
839                       corresponding atdatam pin of the enabled port. */
840 
841   #define ATBFUNNEL_ITATBDATA0_ATDATA14_Pos (14UL)   /*!< Position of ATDATA14 field.                                          */
842   #define ATBFUNNEL_ITATBDATA0_ATDATA14_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA14_Pos) /*!< Bit mask of ATDATA14 field.      */
843   #define ATBFUNNEL_ITATBDATA0_ATDATA14_Min (0x0UL)  /*!< Min enumerator value of ATDATA14 field.                              */
844   #define ATBFUNNEL_ITATBDATA0_ATDATA14_Max (0x1UL)  /*!< Max enumerator value of ATDATA14 field.                              */
845   #define ATBFUNNEL_ITATBDATA0_ATDATA14_Low (0x0UL)  /*!< Pin is logic 0.                                                      */
846   #define ATBFUNNEL_ITATBDATA0_ATDATA14_High (0x1UL) /*!< Pin is logic 1.                                                      */
847 
848 /* ATDATA15 @Bit 15 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
849                       corresponding atdatam pin of the enabled port. */
850 
851   #define ATBFUNNEL_ITATBDATA0_ATDATA15_Pos (15UL)   /*!< Position of ATDATA15 field.                                          */
852   #define ATBFUNNEL_ITATBDATA0_ATDATA15_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA15_Pos) /*!< Bit mask of ATDATA15 field.      */
853   #define ATBFUNNEL_ITATBDATA0_ATDATA15_Min (0x0UL)  /*!< Min enumerator value of ATDATA15 field.                              */
854   #define ATBFUNNEL_ITATBDATA0_ATDATA15_Max (0x1UL)  /*!< Max enumerator value of ATDATA15 field.                              */
855   #define ATBFUNNEL_ITATBDATA0_ATDATA15_Low (0x0UL)  /*!< Pin is logic 0.                                                      */
856   #define ATBFUNNEL_ITATBDATA0_ATDATA15_High (0x1UL) /*!< Pin is logic 1.                                                      */
857 
858 /* ATDATA16 @Bit 16 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
859                       corresponding atdatam pin of the enabled port. */
860 
861   #define ATBFUNNEL_ITATBDATA0_ATDATA16_Pos (16UL)   /*!< Position of ATDATA16 field.                                          */
862   #define ATBFUNNEL_ITATBDATA0_ATDATA16_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA16_Pos) /*!< Bit mask of ATDATA16 field.      */
863   #define ATBFUNNEL_ITATBDATA0_ATDATA16_Min (0x0UL)  /*!< Min enumerator value of ATDATA16 field.                              */
864   #define ATBFUNNEL_ITATBDATA0_ATDATA16_Max (0x1UL)  /*!< Max enumerator value of ATDATA16 field.                              */
865   #define ATBFUNNEL_ITATBDATA0_ATDATA16_Low (0x0UL)  /*!< Pin is logic 0.                                                      */
866   #define ATBFUNNEL_ITATBDATA0_ATDATA16_High (0x1UL) /*!< Pin is logic 1.                                                      */
867 
868 
869 /* ATBFUNNEL_ITATBCTR2: The ITATBCTR2 register performs different functions depending on whether the access is a read or a
870                          write. */
871 
872   #define ATBFUNNEL_ITATBCTR2_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR2 register.                                */
873 
874 /* ATREADY @Bit 0 : A read access returns the value of atreadym. A write access outputs the data to afvalids[n], where the value
875                     of the CTRLREG at 0x000 defines n. */
876 
877   #define ATBFUNNEL_ITATBCTR2_ATREADY_Pos (0UL)      /*!< Position of ATREADY field.                                           */
878   #define ATBFUNNEL_ITATBCTR2_ATREADY_Msk (0x1UL << ATBFUNNEL_ITATBCTR2_ATREADY_Pos) /*!< Bit mask of ATREADY field.           */
879   #define ATBFUNNEL_ITATBCTR2_ATREADY_Min (0x0UL)    /*!< Min enumerator value of ATREADY field.                               */
880   #define ATBFUNNEL_ITATBCTR2_ATREADY_Max (0x1UL)    /*!< Max enumerator value of ATREADY field.                               */
881   #define ATBFUNNEL_ITATBCTR2_ATREADY_Low (0x0UL)    /*!< Pin is logic 0.                                                      */
882   #define ATBFUNNEL_ITATBCTR2_ATREADY_High (0x1UL)   /*!< Pin is logic 1.                                                      */
883 
884 /* AFVALID @Bit 1 : A read access returns the value of afvalidm. A write access outputs the data to atreadys[n], where the value
885                     of the CTRLREG at 0x000 defines n. */
886 
887   #define ATBFUNNEL_ITATBCTR2_AFVALID_Pos (1UL)      /*!< Position of AFVALID field.                                           */
888   #define ATBFUNNEL_ITATBCTR2_AFVALID_Msk (0x1UL << ATBFUNNEL_ITATBCTR2_AFVALID_Pos) /*!< Bit mask of AFVALID field.           */
889   #define ATBFUNNEL_ITATBCTR2_AFVALID_Min (0x0UL)    /*!< Min enumerator value of AFVALID field.                               */
890   #define ATBFUNNEL_ITATBCTR2_AFVALID_Max (0x1UL)    /*!< Max enumerator value of AFVALID field.                               */
891   #define ATBFUNNEL_ITATBCTR2_AFVALID_Low (0x0UL)    /*!< Pin is logic 0.                                                      */
892   #define ATBFUNNEL_ITATBCTR2_AFVALID_High (0x1UL)   /*!< Pin is logic 1.                                                      */
893 
894 
895 /* ATBFUNNEL_ITATBCTR1: The ITATBCTR1 register performs different functions depending on whether the access is a read or a
896                          write. */
897 
898   #define ATBFUNNEL_ITATBCTR1_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR1 register.                                */
899 
900 /* ATVALIDM0 @Bits 0..6 : A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000
901                           defines n. A write outputs the value to the atidm port. */
902 
903   #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Pos (0UL)    /*!< Position of ATVALIDM0 field.                                         */
904   #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Msk (0x7FUL << ATBFUNNEL_ITATBCTR1_ATVALIDM0_Pos) /*!< Bit mask of ATVALIDM0 field.    */
905   #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Min (0x0UL)  /*!< Min enumerator value of ATVALIDM0 field.                             */
906   #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Max (0x1UL)  /*!< Max enumerator value of ATVALIDM0 field.                             */
907   #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Low (0x00UL) /*!< Pin is logic 0.                                                      */
908   #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_High (0x01UL) /*!< Pin is logic 1.                                                     */
909 
910 
911 /* ATBFUNNEL_ITATBCTR0: The ITATBCTR0 register performs different functions depending on whether the access is a read or a
912                          write. */
913 
914   #define ATBFUNNEL_ITATBCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR0 register.                                */
915 
916 /* ATVALID @Bit 0 : A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n. A
917                     write outputs the value to atvalidm. */
918 
919   #define ATBFUNNEL_ITATBCTR0_ATVALID_Pos (0UL)      /*!< Position of ATVALID field.                                           */
920   #define ATBFUNNEL_ITATBCTR0_ATVALID_Msk (0x1UL << ATBFUNNEL_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field.           */
921   #define ATBFUNNEL_ITATBCTR0_ATVALID_Min (0x0UL)    /*!< Min enumerator value of ATVALID field.                               */
922   #define ATBFUNNEL_ITATBCTR0_ATVALID_Max (0x1UL)    /*!< Max enumerator value of ATVALID field.                               */
923   #define ATBFUNNEL_ITATBCTR0_ATVALID_Low (0x0UL)    /*!< Pin is logic 0.                                                      */
924   #define ATBFUNNEL_ITATBCTR0_ATVALID_High (0x1UL)   /*!< Pin is logic 1.                                                      */
925 
926 /* AFREADY @Bit 2 : A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. A
927                     write outputs the value to afreadym. */
928 
929   #define ATBFUNNEL_ITATBCTR0_AFREADY_Pos (2UL)      /*!< Position of AFREADY field.                                           */
930   #define ATBFUNNEL_ITATBCTR0_AFREADY_Msk (0x1UL << ATBFUNNEL_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field.           */
931   #define ATBFUNNEL_ITATBCTR0_AFREADY_Min (0x0UL)    /*!< Min enumerator value of AFREADY field.                               */
932   #define ATBFUNNEL_ITATBCTR0_AFREADY_Max (0x1UL)    /*!< Max enumerator value of AFREADY field.                               */
933   #define ATBFUNNEL_ITATBCTR0_AFREADY_Low (0x0UL)    /*!< Pin is logic 0.                                                      */
934   #define ATBFUNNEL_ITATBCTR0_AFREADY_High (0x1UL)   /*!< Pin is logic 1.                                                      */
935 
936 /* ATBYTES @Bits 8..9 : A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n.
937                         A write outputs the value to atbytesm. */
938 
939   #define ATBFUNNEL_ITATBCTR0_ATBYTES_Pos (8UL)      /*!< Position of ATBYTES field.                                           */
940   #define ATBFUNNEL_ITATBCTR0_ATBYTES_Msk (0x3UL << ATBFUNNEL_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field.           */
941   #define ATBFUNNEL_ITATBCTR0_ATBYTES_Min (0x0UL)    /*!< Min enumerator value of ATBYTES field.                               */
942   #define ATBFUNNEL_ITATBCTR0_ATBYTES_Max (0x1UL)    /*!< Max enumerator value of ATBYTES field.                               */
943   #define ATBFUNNEL_ITATBCTR0_ATBYTES_Low (0x0UL)    /*!< Pin is logic 0.                                                      */
944   #define ATBFUNNEL_ITATBCTR0_ATBYTES_High (0x1UL)   /*!< Pin is logic 1.                                                      */
945 
946 
947 /* ATBFUNNEL_ITCTRL: The ITCTRL register enables the component to switch from a functional mode, which is the default behavior,
948                       to integration mode where the inputs and outputs of the component can be directly controlled for the
949                       purposes of integration testing and topology detection. */
950 
951   #define ATBFUNNEL_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register.                                      */
952 
953 /* IME @Bit 0 : Integration Mode Enable. */
954   #define ATBFUNNEL_ITCTRL_IME_Pos (0UL)             /*!< Position of IME field.                                               */
955   #define ATBFUNNEL_ITCTRL_IME_Msk (0x1UL << ATBFUNNEL_ITCTRL_IME_Pos) /*!< Bit mask of IME field.                             */
956   #define ATBFUNNEL_ITCTRL_IME_Min (0x0UL)           /*!< Min enumerator value of IME field.                                   */
957   #define ATBFUNNEL_ITCTRL_IME_Max (0x1UL)           /*!< Max enumerator value of IME field.                                   */
958   #define ATBFUNNEL_ITCTRL_IME_Disabled (0x0UL)      /*!< Integration mode disabled.                                           */
959   #define ATBFUNNEL_ITCTRL_IME_Enabled (0x1UL)       /*!< Integration mode enabled.                                            */
960 
961 
962 /* ATBFUNNEL_CLAIMSET: Software can use the claim tag to coordinate application and debugger access to trace unit functionality.
963                         The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the
964                         claim tag, and determines the number of claim bits implemented. */
965 
966   #define ATBFUNNEL_CLAIMSET_ResetValue (0x00000000UL) /*!< Reset value of CLAIMSET register.                                  */
967 
968 /* BIT0 @Bit 0 : Set claim bit 0 and check if bit is implemented or not. */
969   #define ATBFUNNEL_CLAIMSET_BIT0_Pos (0UL)          /*!< Position of BIT0 field.                                              */
970   #define ATBFUNNEL_CLAIMSET_BIT0_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT0_Pos) /*!< Bit mask of BIT0 field.                      */
971   #define ATBFUNNEL_CLAIMSET_BIT0_Min (0x0UL)        /*!< Min enumerator value of BIT0 field.                                  */
972   #define ATBFUNNEL_CLAIMSET_BIT0_Max (0x1UL)        /*!< Max enumerator value of BIT0 field.                                  */
973   #define ATBFUNNEL_CLAIMSET_BIT0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented.                                  */
974   #define ATBFUNNEL_CLAIMSET_BIT0_Implemented (0x1UL) /*!< Claim bit 0 is implemented.                                         */
975   #define ATBFUNNEL_CLAIMSET_BIT0_Set (0x1UL)        /*!< Set claim bit 0.                                                     */
976 
977 /* BIT1 @Bit 1 : Set claim bit 1 and check if bit is implemented or not. */
978   #define ATBFUNNEL_CLAIMSET_BIT1_Pos (1UL)          /*!< Position of BIT1 field.                                              */
979   #define ATBFUNNEL_CLAIMSET_BIT1_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT1_Pos) /*!< Bit mask of BIT1 field.                      */
980   #define ATBFUNNEL_CLAIMSET_BIT1_Min (0x0UL)        /*!< Min enumerator value of BIT1 field.                                  */
981   #define ATBFUNNEL_CLAIMSET_BIT1_Max (0x1UL)        /*!< Max enumerator value of BIT1 field.                                  */
982   #define ATBFUNNEL_CLAIMSET_BIT1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented.                                  */
983   #define ATBFUNNEL_CLAIMSET_BIT1_Implemented (0x1UL) /*!< Claim bit 1 is implemented.                                         */
984   #define ATBFUNNEL_CLAIMSET_BIT1_Set (0x1UL)        /*!< Set claim bit 1.                                                     */
985 
986 /* BIT2 @Bit 2 : Set claim bit 2 and check if bit is implemented or not. */
987   #define ATBFUNNEL_CLAIMSET_BIT2_Pos (2UL)          /*!< Position of BIT2 field.                                              */
988   #define ATBFUNNEL_CLAIMSET_BIT2_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT2_Pos) /*!< Bit mask of BIT2 field.                      */
989   #define ATBFUNNEL_CLAIMSET_BIT2_Min (0x0UL)        /*!< Min enumerator value of BIT2 field.                                  */
990   #define ATBFUNNEL_CLAIMSET_BIT2_Max (0x1UL)        /*!< Max enumerator value of BIT2 field.                                  */
991   #define ATBFUNNEL_CLAIMSET_BIT2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented.                                  */
992   #define ATBFUNNEL_CLAIMSET_BIT2_Implemented (0x1UL) /*!< Claim bit 2 is implemented.                                         */
993   #define ATBFUNNEL_CLAIMSET_BIT2_Set (0x1UL)        /*!< Set claim bit 2.                                                     */
994 
995 /* BIT3 @Bit 3 : Set claim bit 3 and check if bit is implemented or not. */
996   #define ATBFUNNEL_CLAIMSET_BIT3_Pos (3UL)          /*!< Position of BIT3 field.                                              */
997   #define ATBFUNNEL_CLAIMSET_BIT3_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT3_Pos) /*!< Bit mask of BIT3 field.                      */
998   #define ATBFUNNEL_CLAIMSET_BIT3_Min (0x0UL)        /*!< Min enumerator value of BIT3 field.                                  */
999   #define ATBFUNNEL_CLAIMSET_BIT3_Max (0x1UL)        /*!< Max enumerator value of BIT3 field.                                  */
1000   #define ATBFUNNEL_CLAIMSET_BIT3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented.                                  */
1001   #define ATBFUNNEL_CLAIMSET_BIT3_Implemented (0x1UL) /*!< Claim bit 3 is implemented.                                         */
1002   #define ATBFUNNEL_CLAIMSET_BIT3_Set (0x1UL)        /*!< Set claim bit 3.                                                     */
1003 
1004 
1005 /* ATBFUNNEL_CLAIMCLR: Software can use the claim tag to coordinate application and debugger access to trace unit functionality.
1006                         The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in
1007                         the claim tag to 0 and determines the current value of the claim tag. */
1008 
1009   #define ATBFUNNEL_CLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of CLAIMCLR register.                                  */
1010 
1011 /* BIT0 @Bit 0 : Read or clear claim bit 0. */
1012   #define ATBFUNNEL_CLAIMCLR_BIT0_Pos (0UL)          /*!< Position of BIT0 field.                                              */
1013   #define ATBFUNNEL_CLAIMCLR_BIT0_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT0_Pos) /*!< Bit mask of BIT0 field.                      */
1014   #define ATBFUNNEL_CLAIMCLR_BIT0_Min (0x0UL)        /*!< Min enumerator value of BIT0 field.                                  */
1015   #define ATBFUNNEL_CLAIMCLR_BIT0_Max (0x1UL)        /*!< Max enumerator value of BIT0 field.                                  */
1016   #define ATBFUNNEL_CLAIMCLR_BIT0_Cleared (0x0UL)    /*!< Claim bit 0 is not set.                                              */
1017   #define ATBFUNNEL_CLAIMCLR_BIT0_Set (0x1UL)        /*!< Claim bit 0 is set.                                                  */
1018   #define ATBFUNNEL_CLAIMCLR_BIT0_Clear (0x1UL)      /*!< Clear claim bit 0.                                                   */
1019 
1020 /* BIT1 @Bit 1 : Read or clear claim bit 1. */
1021   #define ATBFUNNEL_CLAIMCLR_BIT1_Pos (1UL)          /*!< Position of BIT1 field.                                              */
1022   #define ATBFUNNEL_CLAIMCLR_BIT1_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT1_Pos) /*!< Bit mask of BIT1 field.                      */
1023   #define ATBFUNNEL_CLAIMCLR_BIT1_Min (0x0UL)        /*!< Min enumerator value of BIT1 field.                                  */
1024   #define ATBFUNNEL_CLAIMCLR_BIT1_Max (0x1UL)        /*!< Max enumerator value of BIT1 field.                                  */
1025   #define ATBFUNNEL_CLAIMCLR_BIT1_Cleared (0x0UL)    /*!< Claim bit 1 is not set.                                              */
1026   #define ATBFUNNEL_CLAIMCLR_BIT1_Set (0x1UL)        /*!< Claim bit 1 is set.                                                  */
1027   #define ATBFUNNEL_CLAIMCLR_BIT1_Clear (0x1UL)      /*!< Clear claim bit 1.                                                   */
1028 
1029 /* BIT2 @Bit 2 : Read or clear claim bit 2. */
1030   #define ATBFUNNEL_CLAIMCLR_BIT2_Pos (2UL)          /*!< Position of BIT2 field.                                              */
1031   #define ATBFUNNEL_CLAIMCLR_BIT2_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT2_Pos) /*!< Bit mask of BIT2 field.                      */
1032   #define ATBFUNNEL_CLAIMCLR_BIT2_Min (0x0UL)        /*!< Min enumerator value of BIT2 field.                                  */
1033   #define ATBFUNNEL_CLAIMCLR_BIT2_Max (0x1UL)        /*!< Max enumerator value of BIT2 field.                                  */
1034   #define ATBFUNNEL_CLAIMCLR_BIT2_Cleared (0x0UL)    /*!< Claim bit 2 is not set.                                              */
1035   #define ATBFUNNEL_CLAIMCLR_BIT2_Set (0x1UL)        /*!< Claim bit 2 is set.                                                  */
1036   #define ATBFUNNEL_CLAIMCLR_BIT2_Clear (0x1UL)      /*!< Clear claim bit 2.                                                   */
1037 
1038 /* BIT3 @Bit 3 : Read or clear claim bit 3. */
1039   #define ATBFUNNEL_CLAIMCLR_BIT3_Pos (3UL)          /*!< Position of BIT3 field.                                              */
1040   #define ATBFUNNEL_CLAIMCLR_BIT3_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT3_Pos) /*!< Bit mask of BIT3 field.                      */
1041   #define ATBFUNNEL_CLAIMCLR_BIT3_Min (0x0UL)        /*!< Min enumerator value of BIT3 field.                                  */
1042   #define ATBFUNNEL_CLAIMCLR_BIT3_Max (0x1UL)        /*!< Max enumerator value of BIT3 field.                                  */
1043   #define ATBFUNNEL_CLAIMCLR_BIT3_Cleared (0x0UL)    /*!< Claim bit 3 is not set.                                              */
1044   #define ATBFUNNEL_CLAIMCLR_BIT3_Set (0x1UL)        /*!< Claim bit 3 is set.                                                  */
1045   #define ATBFUNNEL_CLAIMCLR_BIT3_Clear (0x1UL)      /*!< Clear claim bit 3.                                                   */
1046 
1047 
1048 /* ATBFUNNEL_LAR: This is used to enable write access to device registers. */
1049   #define ATBFUNNEL_LAR_ResetValue (0x00000000UL)    /*!< Reset value of LAR register.                                         */
1050 
1051 /* ACCESS @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access.
1052                         */
1053 
1054   #define ATBFUNNEL_LAR_ACCESS_Pos (0UL)             /*!< Position of ACCESS field.                                            */
1055   #define ATBFUNNEL_LAR_ACCESS_Msk (0xFFFFFFFFUL << ATBFUNNEL_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field.                   */
1056   #define ATBFUNNEL_LAR_ACCESS_Min (0xC5ACCE55UL)    /*!< Min enumerator value of ACCESS field.                                */
1057   #define ATBFUNNEL_LAR_ACCESS_Max (0xC5ACCE55UL)    /*!< Max enumerator value of ACCESS field.                                */
1058   #define ATBFUNNEL_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface.                                           */
1059 
1060 
1061 /* ATBFUNNEL_LSR: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under
1062                    debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register
1063                    must always be present although there might not be any lock access control mechanism. The lock mechanism,
1064                    where present and locked, must block write accesses to any control register, except the Lock Access Register.
1065                    For most components this covers all registers except for the Lock Access Register. */
1066 
1067   #define ATBFUNNEL_LSR_ResetValue (0x00000000UL)    /*!< Reset value of LSR register.                                         */
1068 
1069 /* PRESENT @Bit 0 : Indicates that a lock control mechanism exists for this device. */
1070   #define ATBFUNNEL_LSR_PRESENT_Pos (0UL)            /*!< Position of PRESENT field.                                           */
1071   #define ATBFUNNEL_LSR_PRESENT_Msk (0x1UL << ATBFUNNEL_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field.                       */
1072   #define ATBFUNNEL_LSR_PRESENT_Min (0x0UL)          /*!< Min enumerator value of PRESENT field.                               */
1073   #define ATBFUNNEL_LSR_PRESENT_Max (0x1UL)          /*!< Max enumerator value of PRESENT field.                               */
1074   #define ATBFUNNEL_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register
1075                                                             are ignored.*/
1076   #define ATBFUNNEL_LSR_PRESENT_Implemented (0x1UL)  /*!< Lock control mechanism is present.                                   */
1077 
1078 /* LOCKED @Bit 1 : Returns the current status of the Lock. */
1079   #define ATBFUNNEL_LSR_LOCKED_Pos (1UL)             /*!< Position of LOCKED field.                                            */
1080   #define ATBFUNNEL_LSR_LOCKED_Msk (0x1UL << ATBFUNNEL_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field.                          */
1081   #define ATBFUNNEL_LSR_LOCKED_Min (0x0UL)           /*!< Min enumerator value of LOCKED field.                                */
1082   #define ATBFUNNEL_LSR_LOCKED_Max (0x1UL)           /*!< Max enumerator value of LOCKED field.                                */
1083   #define ATBFUNNEL_LSR_LOCKED_UnLocked (0x0UL)      /*!< Write access is allowed to this device.                              */
1084   #define ATBFUNNEL_LSR_LOCKED_Locked (0x1UL)        /*!< Write access to the component is blocked. All writes to control
1085                                                           registers are ignored. Reads are permitted.*/
1086 
1087 /* TYPE @Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */
1088   #define ATBFUNNEL_LSR_TYPE_Pos (2UL)               /*!< Position of TYPE field.                                              */
1089   #define ATBFUNNEL_LSR_TYPE_Msk (0x1UL << ATBFUNNEL_LSR_TYPE_Pos) /*!< Bit mask of TYPE field.                                */
1090   #define ATBFUNNEL_LSR_TYPE_Min (0x0UL)             /*!< Min enumerator value of TYPE field.                                  */
1091   #define ATBFUNNEL_LSR_TYPE_Max (0x1UL)             /*!< Max enumerator value of TYPE field.                                  */
1092   #define ATBFUNNEL_LSR_TYPE_Bits32 (0x0UL)          /*!< This component implements a 32-bit Lock Access Register.             */
1093   #define ATBFUNNEL_LSR_TYPE_Bits8 (0x1UL)           /*!< This component implements an 8-bit Lock Access Register.             */
1094 
1095 
1096 /* ATBFUNNEL_AUTHSTATUS: Indicates the current level of tracing permitted by the system */
1097   #define ATBFUNNEL_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register.                              */
1098 
1099 /* NSID @Bits 0..1 : Non-secure Invasive Debug */
1100   #define ATBFUNNEL_AUTHSTATUS_NSID_Pos (0UL)        /*!< Position of NSID field.                                              */
1101   #define ATBFUNNEL_AUTHSTATUS_NSID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field.                  */
1102   #define ATBFUNNEL_AUTHSTATUS_NSID_Min (0x0UL)      /*!< Min enumerator value of NSID field.                                  */
1103   #define ATBFUNNEL_AUTHSTATUS_NSID_Max (0x1UL)      /*!< Max enumerator value of NSID field.                                  */
1104   #define ATBFUNNEL_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                */
1105   #define ATBFUNNEL_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented.                                       */
1106 
1107 /* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */
1108   #define ATBFUNNEL_AUTHSTATUS_NSNID_Pos (2UL)       /*!< Position of NSNID field.                                             */
1109   #define ATBFUNNEL_AUTHSTATUS_NSNID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field.               */
1110   #define ATBFUNNEL_AUTHSTATUS_NSNID_Min (0x0UL)     /*!< Min enumerator value of NSNID field.                                 */
1111   #define ATBFUNNEL_AUTHSTATUS_NSNID_Max (0x1UL)     /*!< Max enumerator value of NSNID field.                                 */
1112   #define ATBFUNNEL_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                               */
1113   #define ATBFUNNEL_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented.                                      */
1114 
1115 /* SID @Bits 4..5 : Secure Invasive Debug */
1116   #define ATBFUNNEL_AUTHSTATUS_SID_Pos (4UL)         /*!< Position of SID field.                                               */
1117   #define ATBFUNNEL_AUTHSTATUS_SID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field.                     */
1118   #define ATBFUNNEL_AUTHSTATUS_SID_Min (0x0UL)       /*!< Min enumerator value of SID field.                                   */
1119   #define ATBFUNNEL_AUTHSTATUS_SID_Max (0x1UL)       /*!< Max enumerator value of SID field.                                   */
1120   #define ATBFUNNEL_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                 */
1121   #define ATBFUNNEL_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented.                                        */
1122 
1123 /* SNID @Bits 6..7 : Secure Non-Invasive Debug */
1124   #define ATBFUNNEL_AUTHSTATUS_SNID_Pos (6UL)        /*!< Position of SNID field.                                              */
1125   #define ATBFUNNEL_AUTHSTATUS_SNID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field.                  */
1126   #define ATBFUNNEL_AUTHSTATUS_SNID_Min (0x0UL)      /*!< Min enumerator value of SNID field.                                  */
1127   #define ATBFUNNEL_AUTHSTATUS_SNID_Max (0x1UL)      /*!< Max enumerator value of SNID field.                                  */
1128   #define ATBFUNNEL_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                */
1129   #define ATBFUNNEL_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented.                                       */
1130 
1131 
1132 /* ATBFUNNEL_DEVID: Indicates the capabilities of the component. */
1133   #define ATBFUNNEL_DEVID_ResetValue (0x00000000UL)  /*!< Reset value of DEVID register.                                       */
1134 
1135 /* PORTCOUNT @Bits 0..3 : Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. */
1136   #define ATBFUNNEL_DEVID_PORTCOUNT_Pos (0UL)        /*!< Position of PORTCOUNT field.                                         */
1137   #define ATBFUNNEL_DEVID_PORTCOUNT_Msk (0xFUL << ATBFUNNEL_DEVID_PORTCOUNT_Pos) /*!< Bit mask of PORTCOUNT field.             */
1138   #define ATBFUNNEL_DEVID_PORTCOUNT_Min (0x2UL)      /*!< Min value of PORTCOUNT field.                                        */
1139   #define ATBFUNNEL_DEVID_PORTCOUNT_Max (0x8UL)      /*!< Max size of PORTCOUNT field.                                         */
1140 
1141 
1142 /* ATBFUNNEL_DEVTYPE: The DEVTYPE register provides a debugger with information about the component when the Part Number field
1143                        is not recognized. The debugger can then report this information. */
1144 
1145   #define ATBFUNNEL_DEVTYPE_ResetValue (0x00000000UL) /*!< Reset value of DEVTYPE register.                                    */
1146 
1147 /* MAJOR @Bits 0..3 : The main type of the component */
1148   #define ATBFUNNEL_DEVTYPE_MAJOR_Pos (0UL)          /*!< Position of MAJOR field.                                             */
1149   #define ATBFUNNEL_DEVTYPE_MAJOR_Msk (0xFUL << ATBFUNNEL_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field.                     */
1150   #define ATBFUNNEL_DEVTYPE_MAJOR_Min (0x2UL)        /*!< Min enumerator value of MAJOR field.                                 */
1151   #define ATBFUNNEL_DEVTYPE_MAJOR_Max (0x2UL)        /*!< Max enumerator value of MAJOR field.                                 */
1152   #define ATBFUNNEL_DEVTYPE_MAJOR_InputOutputDevice (0x2UL) /*!< Indicates that this component has ATB inputs and outputs.     */
1153 
1154 /* SUB @Bits 4..7 : The sub-type of the component */
1155   #define ATBFUNNEL_DEVTYPE_SUB_Pos (4UL)            /*!< Position of SUB field.                                               */
1156   #define ATBFUNNEL_DEVTYPE_SUB_Msk (0xFUL << ATBFUNNEL_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field.                           */
1157   #define ATBFUNNEL_DEVTYPE_SUB_Min (0x1UL)          /*!< Min enumerator value of SUB field.                                   */
1158   #define ATBFUNNEL_DEVTYPE_SUB_Max (0x1UL)          /*!< Max enumerator value of SUB field.                                   */
1159   #define ATBFUNNEL_DEVTYPE_SUB_Replicator (0x1UL)   /*!< This component arbitrates ATB inputs mapping to ATB outputs.         */
1160 
1161 
1162 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
1163 
1164 /* =========================================================================================================================== */
1165 /* ================                                       ATBREPLICATOR                                       ================ */
1166 /* =========================================================================================================================== */
1167 
1168 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
1169 /* ================================================== Struct ATBREPLICATOR =================================================== */
1170 /**
1171   * @brief ATB Replicator module
1172   */
1173   typedef struct {                                   /*!< ATBREPLICATOR Structure                                              */
1174     __IOM uint32_t IDFILTER0;                        /*!< (@ 0x00000000) The IDFILTER0 register enables the programming of ID
1175                                                                          filtering for master port 0.*/
1176     __IOM uint32_t IDFILTER1;                        /*!< (@ 0x00000004) The IDFILTER1 register enables the programming of ID
1177                                                                          filtering for master port 1.*/
1178     __IM uint32_t RESERVED[956];
1179     __IOM uint32_t ITATBCTR1;                        /*!< (@ 0x00000EF8) The ITATBCTR1 register returns the value of the
1180                                                                          atreadym0, atreadym1, and atvalids inputs in
1181                                                                          integration mode.*/
1182     __IOM uint32_t ITATBCTR0;                        /*!< (@ 0x00000EFC) The ITATBCTR0 register controls the value of the
1183                                                                          atvalidm0, atvalidm1, and atreadys outputs in
1184                                                                          integration mode.*/
1185     __IOM uint32_t ITCTRL;                           /*!< (@ 0x00000F00) The ITCTRL register enables the component to switch
1186                                                                          from a functional mode, which is the default behavior,
1187                                                                          to integration mode where the inputs and outputs of the
1188                                                                          component can be directly controlled for the purposes
1189                                                                          of integration testing and topology detection.*/
1190     __IM uint32_t RESERVED1[39];
1191     __IOM uint32_t CLAIMSET;                         /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate
1192                                                                          application and debugger access to trace unit
1193                                                                          functionality. The claim tags have no effect on the
1194                                                                          operation of the component. The CLAIMSET register sets
1195                                                                          bits in the claim tag, and determines the number of
1196                                                                          claim bits implemented.*/
1197     __IOM uint32_t CLAIMCLR;                         /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate
1198                                                                          application and debugger access to trace unit
1199                                                                          functionality. The claim tags have no effect on the
1200                                                                          operation of the component. The CLAIMCLR register sets
1201                                                                          the bits in the claim tag to 0 and determines the
1202                                                                          current value of the claim tag.*/
1203     __IM uint32_t RESERVED2[2];
1204     __IOM uint32_t LAR;                              /*!< (@ 0x00000FB0) This is used to enable write access to device
1205                                                                          registers.*/
1206     __IOM uint32_t LSR;                              /*!< (@ 0x00000FB4) This indicates the status of the lock control
1207                                                                          mechanism. This lock prevents accidental writes by code
1208                                                                          under debug. Accesses to the extended stimulus port
1209                                                                          registers are not affected by the lock mechanism. This
1210                                                                          register must always be present although there might
1211                                                                          not be any lock access control mechanism. The lock
1212                                                                          mechanism, where present and locked, must block write
1213                                                                          accesses to any control register, except the Lock
1214                                                                          Access Register. For most components this covers all
1215                                                                          registers except for the Lock Access Register.*/
1216     __IOM uint32_t AUTHSTATUS;                       /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the
1217                                                                          system*/
1218     __IM uint32_t RESERVED3[3];
1219     __IM uint32_t DEVID;                             /*!< (@ 0x00000FC8) Indicates the capabilities of the component.          */
1220     __IM uint32_t DEVTYPE;                           /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with
1221                                                                          information about the component when the Part Number
1222                                                                          field is not recognized. The debugger can then report
1223                                                                          this information.*/
1224     __IOM uint32_t PIDR4;                            /*!< (@ 0x00000FD0) Coresight peripheral identification registers.        */
1225     __IM uint32_t RESERVED4[3];
1226     __IOM uint32_t PIDR0;                            /*!< (@ 0x00000FE0) Coresight peripheral identification registers.        */
1227     __IOM uint32_t PIDR1;                            /*!< (@ 0x00000FE4) Coresight peripheral identification registers.        */
1228     __IOM uint32_t PIDR2;                            /*!< (@ 0x00000FE8) Coresight peripheral identification registers.        */
1229     __IOM uint32_t PIDR3;                            /*!< (@ 0x00000FEC) Coresight peripheral identification registers.        */
1230     __IOM uint32_t CIDR0;                            /*!< (@ 0x00000FF0) Coresight component identification registers.         */
1231     __IOM uint32_t CIDR1;                            /*!< (@ 0x00000FF4) Coresight component identification registers.         */
1232     __IOM uint32_t CIDR2;                            /*!< (@ 0x00000FF8) Coresight component identification registers.         */
1233     __IOM uint32_t CIDR3;                            /*!< (@ 0x00000FFC) Coresight component identification registers.         */
1234   } NRF_ATBREPLICATOR_Type;                          /*!< Size = 4096 (0x1000)                                                 */
1235 
1236 /* ATBREPLICATOR_IDFILTER0: The IDFILTER0 register enables the programming of ID filtering for master port 0. */
1237   #define ATBREPLICATOR_IDFILTER0_ResetValue (0x00000000UL) /*!< Reset value of IDFILTER0 register.                            */
1238 
1239 /* ID0_00_0F @Bit 0 : Enable or disable ID filtering for IDs 0x00_0x0F. */
1240   #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Pos (0UL) /*!< Position of ID0_00_0F field.                                        */
1241   #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_00_0F_Pos) /*!< Bit mask of ID0_00_0F
1242                                                                             field.*/
1243   #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Min (0x0UL) /*!< Min enumerator value of ID0_00_0F field.                          */
1244   #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Max (0x1UL) /*!< Max enumerator value of ID0_00_0F field.                          */
1245   #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1246                                                                      port 0.*/
1247   #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1248 
1249 /* ID0_10_1F @Bit 1 : Enable or disable ID filtering for IDs 0x10_0x1F. */
1250   #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Pos (1UL) /*!< Position of ID0_10_1F field.                                        */
1251   #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_10_1F_Pos) /*!< Bit mask of ID0_10_1F
1252                                                                             field.*/
1253   #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Min (0x0UL) /*!< Min enumerator value of ID0_10_1F field.                          */
1254   #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Max (0x1UL) /*!< Max enumerator value of ID0_10_1F field.                          */
1255   #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1256                                                                      port 0.*/
1257   #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1258 
1259 /* ID0_20_2F @Bit 2 : Enable or disable ID filtering for IDs 0x20_0x2F. */
1260   #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Pos (2UL) /*!< Position of ID0_20_2F field.                                        */
1261   #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_20_2F_Pos) /*!< Bit mask of ID0_20_2F
1262                                                                             field.*/
1263   #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Min (0x0UL) /*!< Min enumerator value of ID0_20_2F field.                          */
1264   #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Max (0x1UL) /*!< Max enumerator value of ID0_20_2F field.                          */
1265   #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1266                                                                      port 0.*/
1267   #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1268 
1269 /* ID0_30_3F @Bit 3 : Enable or disable ID filtering for IDs 0x30_0x3F. */
1270   #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Pos (3UL) /*!< Position of ID0_30_3F field.                                        */
1271   #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_30_3F_Pos) /*!< Bit mask of ID0_30_3F
1272                                                                             field.*/
1273   #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Min (0x0UL) /*!< Min enumerator value of ID0_30_3F field.                          */
1274   #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Max (0x1UL) /*!< Max enumerator value of ID0_30_3F field.                          */
1275   #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1276                                                                      port 0.*/
1277   #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1278 
1279 /* ID0_40_4F @Bit 4 : Enable or disable ID filtering for IDs 0x40_0x4F. */
1280   #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Pos (4UL) /*!< Position of ID0_40_4F field.                                        */
1281   #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_40_4F_Pos) /*!< Bit mask of ID0_40_4F
1282                                                                             field.*/
1283   #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Min (0x0UL) /*!< Min enumerator value of ID0_40_4F field.                          */
1284   #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Max (0x1UL) /*!< Max enumerator value of ID0_40_4F field.                          */
1285   #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1286                                                                      port 0.*/
1287   #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1288 
1289 /* ID0_50_5F @Bit 5 : Enable or disable ID filtering for IDs 0x50_0x5F. */
1290   #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Pos (5UL) /*!< Position of ID0_50_5F field.                                        */
1291   #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_50_5F_Pos) /*!< Bit mask of ID0_50_5F
1292                                                                             field.*/
1293   #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Min (0x0UL) /*!< Min enumerator value of ID0_50_5F field.                          */
1294   #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Max (0x1UL) /*!< Max enumerator value of ID0_50_5F field.                          */
1295   #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1296                                                                      port 0.*/
1297   #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1298 
1299 /* ID0_60_6F @Bit 6 : Enable or disable ID filtering for IDs 0x60_0x6F. */
1300   #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Pos (6UL) /*!< Position of ID0_60_6F field.                                        */
1301   #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_60_6F_Pos) /*!< Bit mask of ID0_60_6F
1302                                                                             field.*/
1303   #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Min (0x0UL) /*!< Min enumerator value of ID0_60_6F field.                          */
1304   #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Max (0x1UL) /*!< Max enumerator value of ID0_60_6F field.                          */
1305   #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1306                                                                      port 0.*/
1307   #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1308 
1309 /* ID0_70_7F @Bit 7 : Enable or disable ID filtering for IDs 0x70_0x7F. */
1310   #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Pos (7UL) /*!< Position of ID0_70_7F field.                                        */
1311   #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_70_7F_Pos) /*!< Bit mask of ID0_70_7F
1312                                                                             field.*/
1313   #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Min (0x0UL) /*!< Min enumerator value of ID0_70_7F field.                          */
1314   #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Max (0x1UL) /*!< Max enumerator value of ID0_70_7F field.                          */
1315   #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1316                                                                      port 0.*/
1317   #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1318 
1319 
1320 /* ATBREPLICATOR_IDFILTER1: The IDFILTER1 register enables the programming of ID filtering for master port 1. */
1321   #define ATBREPLICATOR_IDFILTER1_ResetValue (0x00000000UL) /*!< Reset value of IDFILTER1 register.                            */
1322 
1323 /* ID1_00_0F @Bit 0 : Enable or disable ID filtering for IDs 0x00_0x0F. */
1324   #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Pos (0UL) /*!< Position of ID1_00_0F field.                                        */
1325   #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_00_0F_Pos) /*!< Bit mask of ID1_00_0F
1326                                                                             field.*/
1327   #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Min (0x0UL) /*!< Min enumerator value of ID1_00_0F field.                          */
1328   #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Max (0x1UL) /*!< Max enumerator value of ID1_00_0F field.                          */
1329   #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1330                                                                      port 1.*/
1331   #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1332 
1333 /* ID1_10_1F @Bit 1 : Enable or disable ID filtering for IDs 0x10_0x1F. */
1334   #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Pos (1UL) /*!< Position of ID1_10_1F field.                                        */
1335   #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_10_1F_Pos) /*!< Bit mask of ID1_10_1F
1336                                                                             field.*/
1337   #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Min (0x0UL) /*!< Min enumerator value of ID1_10_1F field.                          */
1338   #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Max (0x1UL) /*!< Max enumerator value of ID1_10_1F field.                          */
1339   #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1340                                                                      port 1.*/
1341   #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1342 
1343 /* ID1_20_2F @Bit 2 : Enable or disable ID filtering for IDs 0x20_0x2F. */
1344   #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Pos (2UL) /*!< Position of ID1_20_2F field.                                        */
1345   #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_20_2F_Pos) /*!< Bit mask of ID1_20_2F
1346                                                                             field.*/
1347   #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Min (0x0UL) /*!< Min enumerator value of ID1_20_2F field.                          */
1348   #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Max (0x1UL) /*!< Max enumerator value of ID1_20_2F field.                          */
1349   #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1350                                                                      port 1.*/
1351   #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1352 
1353 /* ID1_30_3F @Bit 3 : Enable or disable ID filtering for IDs 0x30_0x3F. */
1354   #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Pos (3UL) /*!< Position of ID1_30_3F field.                                        */
1355   #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_30_3F_Pos) /*!< Bit mask of ID1_30_3F
1356                                                                             field.*/
1357   #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Min (0x0UL) /*!< Min enumerator value of ID1_30_3F field.                          */
1358   #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Max (0x1UL) /*!< Max enumerator value of ID1_30_3F field.                          */
1359   #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1360                                                                      port 1.*/
1361   #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1362 
1363 /* ID1_40_4F @Bit 4 : Enable or disable ID filtering for IDs 0x40_0x4F. */
1364   #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Pos (4UL) /*!< Position of ID1_40_4F field.                                        */
1365   #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_40_4F_Pos) /*!< Bit mask of ID1_40_4F
1366                                                                             field.*/
1367   #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Min (0x0UL) /*!< Min enumerator value of ID1_40_4F field.                          */
1368   #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Max (0x1UL) /*!< Max enumerator value of ID1_40_4F field.                          */
1369   #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1370                                                                      port 1.*/
1371   #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1372 
1373 /* ID1_50_5F @Bit 5 : Enable or disable ID filtering for IDs 0x50_0x5F. */
1374   #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Pos (5UL) /*!< Position of ID1_50_5F field.                                        */
1375   #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_50_5F_Pos) /*!< Bit mask of ID1_50_5F
1376                                                                             field.*/
1377   #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Min (0x0UL) /*!< Min enumerator value of ID1_50_5F field.                          */
1378   #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Max (0x1UL) /*!< Max enumerator value of ID1_50_5F field.                          */
1379   #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1380                                                                      port 1.*/
1381   #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1382 
1383 /* ID1_60_6F @Bit 6 : Enable or disable ID filtering for IDs 0x60_0x6F. */
1384   #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Pos (6UL) /*!< Position of ID1_60_6F field.                                        */
1385   #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_60_6F_Pos) /*!< Bit mask of ID1_60_6F
1386                                                                             field.*/
1387   #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Min (0x0UL) /*!< Min enumerator value of ID1_60_6F field.                          */
1388   #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Max (0x1UL) /*!< Max enumerator value of ID1_60_6F field.                          */
1389   #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1390                                                                      port 1.*/
1391   #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1392 
1393 /* ID1_70_7F @Bit 7 : Enable or disable ID filtering for IDs 0x70_0x7F. */
1394   #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Pos (7UL) /*!< Position of ID1_70_7F field.                                        */
1395   #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_70_7F_Pos) /*!< Bit mask of ID1_70_7F
1396                                                                             field.*/
1397   #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Min (0x0UL) /*!< Min enumerator value of ID1_70_7F field.                          */
1398   #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Max (0x1UL) /*!< Max enumerator value of ID1_70_7F field.                          */
1399   #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master
1400                                                                      port 1.*/
1401   #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */
1402 
1403 
1404 /* ATBREPLICATOR_ITATBCTR1: The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in
1405                              integration mode. */
1406 
1407   #define ATBREPLICATOR_ITATBCTR1_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR1 register.                            */
1408 
1409 /* ATREADYM0 @Bit 0 : Reads the value of the atreadym0 input. */
1410   #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Pos (0UL) /*!< Position of ATREADYM0 field.                                        */
1411   #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATREADYM0_Pos) /*!< Bit mask of ATREADYM0
1412                                                                             field.*/
1413   #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Min (0x0UL) /*!< Min enumerator value of ATREADYM0 field.                          */
1414   #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Max (0x1UL) /*!< Max enumerator value of ATREADYM0 field.                          */
1415   #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Low (0x0UL) /*!< Pin is logic 0.                                                   */
1416   #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_High (0x1UL) /*!< Pin is logic 1.                                                  */
1417 
1418 /* ATREADYM1 @Bit 1 : Reads the value of the atreadym1 input. */
1419   #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Pos (1UL) /*!< Position of ATREADYM1 field.                                        */
1420   #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATREADYM1_Pos) /*!< Bit mask of ATREADYM1
1421                                                                             field.*/
1422   #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Min (0x0UL) /*!< Min enumerator value of ATREADYM1 field.                          */
1423   #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Max (0x1UL) /*!< Max enumerator value of ATREADYM1 field.                          */
1424   #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Low (0x0UL) /*!< Pin is logic 0.                                                   */
1425   #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_High (0x1UL) /*!< Pin is logic 1.                                                  */
1426 
1427 /* ATVALIDS @Bit 3 : Reads the value of the atvalids input. */
1428   #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Pos (3UL) /*!< Position of ATVALIDS field.                                          */
1429   #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATVALIDS_Pos) /*!< Bit mask of ATVALIDS field.*/
1430   #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Min (0x0UL) /*!< Min enumerator value of ATVALIDS field.                            */
1431   #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Max (0x1UL) /*!< Max enumerator value of ATVALIDS field.                            */
1432   #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Low (0x0UL) /*!< Pin is logic 0.                                                    */
1433   #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_High (0x1UL) /*!< Pin is logic 1.                                                   */
1434 
1435 
1436 /* ATBREPLICATOR_ITATBCTR0: The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in
1437                              integration mode. */
1438 
1439   #define ATBREPLICATOR_ITATBCTR0_ResetValue (0x00000000UL) /*!< Reset value of ITATBCTR0 register.                            */
1440 
1441 /* ATVALIDM0 @Bit 0 : Sets the value of the atvalidm0 output. */
1442   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Pos (0UL) /*!< Position of ATVALIDM0 field.                                        */
1443   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Pos) /*!< Bit mask of ATVALIDM0
1444                                                                             field.*/
1445   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Min (0x0UL) /*!< Min enumerator value of ATVALIDM0 field.                          */
1446   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Max (0x1UL) /*!< Max enumerator value of ATVALIDM0 field.                          */
1447   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Low (0x0UL) /*!< Pin is logic 0.                                                   */
1448   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_High (0x1UL) /*!< Pin is logic 1.                                                  */
1449 
1450 /* ATVALIDM1 @Bit 2 : Sets the value of the atvalidm1 output. */
1451   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Pos (2UL) /*!< Position of ATVALIDM1 field.                                        */
1452   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Pos) /*!< Bit mask of ATVALIDM1
1453                                                                             field.*/
1454   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Min (0x0UL) /*!< Min enumerator value of ATVALIDM1 field.                          */
1455   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Max (0x1UL) /*!< Max enumerator value of ATVALIDM1 field.                          */
1456   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Low (0x0UL) /*!< Pin is logic 0.                                                   */
1457   #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_High (0x1UL) /*!< Pin is logic 1.                                                  */
1458 
1459 /* ATREADYS @Bit 3 : Sets the value of the atreadys output. */
1460   #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Pos (3UL) /*!< Position of ATREADYS field.                                          */
1461   #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATREADYS_Pos) /*!< Bit mask of ATREADYS field.*/
1462   #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Min (0x0UL) /*!< Min enumerator value of ATREADYS field.                            */
1463   #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Max (0x1UL) /*!< Max enumerator value of ATREADYS field.                            */
1464   #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Low (0x0UL) /*!< Pin is logic 0.                                                    */
1465   #define ATBREPLICATOR_ITATBCTR0_ATREADYS_High (0x1UL) /*!< Pin is logic 1.                                                   */
1466 
1467 
1468 /* ATBREPLICATOR_ITCTRL: The ITCTRL register enables the component to switch from a functional mode, which is the default
1469                           behavior, to integration mode where the inputs and outputs of the component can be directly controlled
1470                           for the purposes of integration testing and topology detection. */
1471 
1472   #define ATBREPLICATOR_ITCTRL_ResetValue (0x00000000UL) /*!< Reset value of ITCTRL register.                                  */
1473 
1474 /* IME @Bit 0 : Integration Mode Enable. */
1475   #define ATBREPLICATOR_ITCTRL_IME_Pos (0UL)         /*!< Position of IME field.                                               */
1476   #define ATBREPLICATOR_ITCTRL_IME_Msk (0x1UL << ATBREPLICATOR_ITCTRL_IME_Pos) /*!< Bit mask of IME field.                     */
1477   #define ATBREPLICATOR_ITCTRL_IME_Min (0x0UL)       /*!< Min enumerator value of IME field.                                   */
1478   #define ATBREPLICATOR_ITCTRL_IME_Max (0x1UL)       /*!< Max enumerator value of IME field.                                   */
1479   #define ATBREPLICATOR_ITCTRL_IME_Disabled (0x0UL)  /*!< Integration mode disabled.                                           */
1480   #define ATBREPLICATOR_ITCTRL_IME_Enabled (0x1UL)   /*!< Integration mode enabled.                                            */
1481 
1482 
1483 /* ATBREPLICATOR_CLAIMSET: Software can use the claim tag to coordinate application and debugger access to trace unit
1484                             functionality. The claim tags have no effect on the operation of the component. The CLAIMSET
1485                             register sets bits in the claim tag, and determines the number of claim bits implemented. */
1486 
1487   #define ATBREPLICATOR_CLAIMSET_ResetValue (0x00000000UL) /*!< Reset value of CLAIMSET register.                              */
1488 
1489 /* BIT0 @Bit 0 : Set claim bit 0 and check if bit is implemented or not. */
1490   #define ATBREPLICATOR_CLAIMSET_BIT0_Pos (0UL)      /*!< Position of BIT0 field.                                              */
1491   #define ATBREPLICATOR_CLAIMSET_BIT0_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT0_Pos) /*!< Bit mask of BIT0 field.              */
1492   #define ATBREPLICATOR_CLAIMSET_BIT0_Min (0x0UL)    /*!< Min enumerator value of BIT0 field.                                  */
1493   #define ATBREPLICATOR_CLAIMSET_BIT0_Max (0x1UL)    /*!< Max enumerator value of BIT0 field.                                  */
1494   #define ATBREPLICATOR_CLAIMSET_BIT0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented.                              */
1495   #define ATBREPLICATOR_CLAIMSET_BIT0_Implemented (0x1UL) /*!< Claim bit 0 is implemented.                                     */
1496   #define ATBREPLICATOR_CLAIMSET_BIT0_Set (0x1UL)    /*!< Set claim bit 0.                                                     */
1497 
1498 /* BIT1 @Bit 1 : Set claim bit 1 and check if bit is implemented or not. */
1499   #define ATBREPLICATOR_CLAIMSET_BIT1_Pos (1UL)      /*!< Position of BIT1 field.                                              */
1500   #define ATBREPLICATOR_CLAIMSET_BIT1_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT1_Pos) /*!< Bit mask of BIT1 field.              */
1501   #define ATBREPLICATOR_CLAIMSET_BIT1_Min (0x0UL)    /*!< Min enumerator value of BIT1 field.                                  */
1502   #define ATBREPLICATOR_CLAIMSET_BIT1_Max (0x1UL)    /*!< Max enumerator value of BIT1 field.                                  */
1503   #define ATBREPLICATOR_CLAIMSET_BIT1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented.                              */
1504   #define ATBREPLICATOR_CLAIMSET_BIT1_Implemented (0x1UL) /*!< Claim bit 1 is implemented.                                     */
1505   #define ATBREPLICATOR_CLAIMSET_BIT1_Set (0x1UL)    /*!< Set claim bit 1.                                                     */
1506 
1507 /* BIT2 @Bit 2 : Set claim bit 2 and check if bit is implemented or not. */
1508   #define ATBREPLICATOR_CLAIMSET_BIT2_Pos (2UL)      /*!< Position of BIT2 field.                                              */
1509   #define ATBREPLICATOR_CLAIMSET_BIT2_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT2_Pos) /*!< Bit mask of BIT2 field.              */
1510   #define ATBREPLICATOR_CLAIMSET_BIT2_Min (0x0UL)    /*!< Min enumerator value of BIT2 field.                                  */
1511   #define ATBREPLICATOR_CLAIMSET_BIT2_Max (0x1UL)    /*!< Max enumerator value of BIT2 field.                                  */
1512   #define ATBREPLICATOR_CLAIMSET_BIT2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented.                              */
1513   #define ATBREPLICATOR_CLAIMSET_BIT2_Implemented (0x1UL) /*!< Claim bit 2 is implemented.                                     */
1514   #define ATBREPLICATOR_CLAIMSET_BIT2_Set (0x1UL)    /*!< Set claim bit 2.                                                     */
1515 
1516 /* BIT3 @Bit 3 : Set claim bit 3 and check if bit is implemented or not. */
1517   #define ATBREPLICATOR_CLAIMSET_BIT3_Pos (3UL)      /*!< Position of BIT3 field.                                              */
1518   #define ATBREPLICATOR_CLAIMSET_BIT3_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT3_Pos) /*!< Bit mask of BIT3 field.              */
1519   #define ATBREPLICATOR_CLAIMSET_BIT3_Min (0x0UL)    /*!< Min enumerator value of BIT3 field.                                  */
1520   #define ATBREPLICATOR_CLAIMSET_BIT3_Max (0x1UL)    /*!< Max enumerator value of BIT3 field.                                  */
1521   #define ATBREPLICATOR_CLAIMSET_BIT3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented.                              */
1522   #define ATBREPLICATOR_CLAIMSET_BIT3_Implemented (0x1UL) /*!< Claim bit 3 is implemented.                                     */
1523   #define ATBREPLICATOR_CLAIMSET_BIT3_Set (0x1UL)    /*!< Set claim bit 3.                                                     */
1524 
1525 
1526 /* ATBREPLICATOR_CLAIMCLR: Software can use the claim tag to coordinate application and debugger access to trace unit
1527                             functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR
1528                             register sets the bits in the claim tag to 0 and determines the current value of the claim tag. */
1529 
1530   #define ATBREPLICATOR_CLAIMCLR_ResetValue (0x00000000UL) /*!< Reset value of CLAIMCLR register.                              */
1531 
1532 /* BIT0 @Bit 0 : Read or clear claim bit 0. */
1533   #define ATBREPLICATOR_CLAIMCLR_BIT0_Pos (0UL)      /*!< Position of BIT0 field.                                              */
1534   #define ATBREPLICATOR_CLAIMCLR_BIT0_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT0_Pos) /*!< Bit mask of BIT0 field.              */
1535   #define ATBREPLICATOR_CLAIMCLR_BIT0_Min (0x0UL)    /*!< Min enumerator value of BIT0 field.                                  */
1536   #define ATBREPLICATOR_CLAIMCLR_BIT0_Max (0x1UL)    /*!< Max enumerator value of BIT0 field.                                  */
1537   #define ATBREPLICATOR_CLAIMCLR_BIT0_Cleared (0x0UL) /*!< Claim bit 0 is not set.                                             */
1538   #define ATBREPLICATOR_CLAIMCLR_BIT0_Set (0x1UL)    /*!< Claim bit 0 is set.                                                  */
1539   #define ATBREPLICATOR_CLAIMCLR_BIT0_Clear (0x1UL)  /*!< Clear claim bit 0.                                                   */
1540 
1541 /* BIT1 @Bit 1 : Read or clear claim bit 1. */
1542   #define ATBREPLICATOR_CLAIMCLR_BIT1_Pos (1UL)      /*!< Position of BIT1 field.                                              */
1543   #define ATBREPLICATOR_CLAIMCLR_BIT1_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT1_Pos) /*!< Bit mask of BIT1 field.              */
1544   #define ATBREPLICATOR_CLAIMCLR_BIT1_Min (0x0UL)    /*!< Min enumerator value of BIT1 field.                                  */
1545   #define ATBREPLICATOR_CLAIMCLR_BIT1_Max (0x1UL)    /*!< Max enumerator value of BIT1 field.                                  */
1546   #define ATBREPLICATOR_CLAIMCLR_BIT1_Cleared (0x0UL) /*!< Claim bit 1 is not set.                                             */
1547   #define ATBREPLICATOR_CLAIMCLR_BIT1_Set (0x1UL)    /*!< Claim bit 1 is set.                                                  */
1548   #define ATBREPLICATOR_CLAIMCLR_BIT1_Clear (0x1UL)  /*!< Clear claim bit 1.                                                   */
1549 
1550 /* BIT2 @Bit 2 : Read or clear claim bit 2. */
1551   #define ATBREPLICATOR_CLAIMCLR_BIT2_Pos (2UL)      /*!< Position of BIT2 field.                                              */
1552   #define ATBREPLICATOR_CLAIMCLR_BIT2_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT2_Pos) /*!< Bit mask of BIT2 field.              */
1553   #define ATBREPLICATOR_CLAIMCLR_BIT2_Min (0x0UL)    /*!< Min enumerator value of BIT2 field.                                  */
1554   #define ATBREPLICATOR_CLAIMCLR_BIT2_Max (0x1UL)    /*!< Max enumerator value of BIT2 field.                                  */
1555   #define ATBREPLICATOR_CLAIMCLR_BIT2_Cleared (0x0UL) /*!< Claim bit 2 is not set.                                             */
1556   #define ATBREPLICATOR_CLAIMCLR_BIT2_Set (0x1UL)    /*!< Claim bit 2 is set.                                                  */
1557   #define ATBREPLICATOR_CLAIMCLR_BIT2_Clear (0x1UL)  /*!< Clear claim bit 2.                                                   */
1558 
1559 /* BIT3 @Bit 3 : Read or clear claim bit 3. */
1560   #define ATBREPLICATOR_CLAIMCLR_BIT3_Pos (3UL)      /*!< Position of BIT3 field.                                              */
1561   #define ATBREPLICATOR_CLAIMCLR_BIT3_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT3_Pos) /*!< Bit mask of BIT3 field.              */
1562   #define ATBREPLICATOR_CLAIMCLR_BIT3_Min (0x0UL)    /*!< Min enumerator value of BIT3 field.                                  */
1563   #define ATBREPLICATOR_CLAIMCLR_BIT3_Max (0x1UL)    /*!< Max enumerator value of BIT3 field.                                  */
1564   #define ATBREPLICATOR_CLAIMCLR_BIT3_Cleared (0x0UL) /*!< Claim bit 3 is not set.                                             */
1565   #define ATBREPLICATOR_CLAIMCLR_BIT3_Set (0x1UL)    /*!< Claim bit 3 is set.                                                  */
1566   #define ATBREPLICATOR_CLAIMCLR_BIT3_Clear (0x1UL)  /*!< Clear claim bit 3.                                                   */
1567 
1568 
1569 /* ATBREPLICATOR_LAR: This is used to enable write access to device registers. */
1570   #define ATBREPLICATOR_LAR_ResetValue (0x00000000UL) /*!< Reset value of LAR register.                                        */
1571 
1572 /* ACCESS @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access.
1573                         */
1574 
1575   #define ATBREPLICATOR_LAR_ACCESS_Pos (0UL)         /*!< Position of ACCESS field.                                            */
1576   #define ATBREPLICATOR_LAR_ACCESS_Msk (0xFFFFFFFFUL << ATBREPLICATOR_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field.           */
1577   #define ATBREPLICATOR_LAR_ACCESS_Min (0xC5ACCE55UL) /*!< Min enumerator value of ACCESS field.                               */
1578   #define ATBREPLICATOR_LAR_ACCESS_Max (0xC5ACCE55UL) /*!< Max enumerator value of ACCESS field.                               */
1579   #define ATBREPLICATOR_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface.                                       */
1580 
1581 
1582 /* ATBREPLICATOR_LSR: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code
1583                        under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism.
1584                        This register must always be present although there might not be any lock access control mechanism. The
1585                        lock mechanism, where present and locked, must block write accesses to any control register, except the
1586                        Lock Access Register. For most components this covers all registers except for the Lock Access Register.
1587                        */
1588 
1589   #define ATBREPLICATOR_LSR_ResetValue (0x00000000UL) /*!< Reset value of LSR register.                                        */
1590 
1591 /* PRESENT @Bit 0 : Indicates that a lock control mechanism exists for this device. */
1592   #define ATBREPLICATOR_LSR_PRESENT_Pos (0UL)        /*!< Position of PRESENT field.                                           */
1593   #define ATBREPLICATOR_LSR_PRESENT_Msk (0x1UL << ATBREPLICATOR_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field.               */
1594   #define ATBREPLICATOR_LSR_PRESENT_Min (0x0UL)      /*!< Min enumerator value of PRESENT field.                               */
1595   #define ATBREPLICATOR_LSR_PRESENT_Max (0x1UL)      /*!< Max enumerator value of PRESENT field.                               */
1596   #define ATBREPLICATOR_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access
1597                                                                 Register are ignored.*/
1598   #define ATBREPLICATOR_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present.                                */
1599 
1600 /* LOCKED @Bit 1 : Returns the current status of the Lock. */
1601   #define ATBREPLICATOR_LSR_LOCKED_Pos (1UL)         /*!< Position of LOCKED field.                                            */
1602   #define ATBREPLICATOR_LSR_LOCKED_Msk (0x1UL << ATBREPLICATOR_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field.                  */
1603   #define ATBREPLICATOR_LSR_LOCKED_Min (0x0UL)       /*!< Min enumerator value of LOCKED field.                                */
1604   #define ATBREPLICATOR_LSR_LOCKED_Max (0x1UL)       /*!< Max enumerator value of LOCKED field.                                */
1605   #define ATBREPLICATOR_LSR_LOCKED_UnLocked (0x0UL)  /*!< Write access is allowed to this device.                              */
1606   #define ATBREPLICATOR_LSR_LOCKED_Locked (0x1UL)    /*!< Write access to the component is blocked. All writes to control
1607                                                           registers are ignored. Reads are permitted.*/
1608 
1609 /* TYPE @Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */
1610   #define ATBREPLICATOR_LSR_TYPE_Pos (2UL)           /*!< Position of TYPE field.                                              */
1611   #define ATBREPLICATOR_LSR_TYPE_Msk (0x1UL << ATBREPLICATOR_LSR_TYPE_Pos) /*!< Bit mask of TYPE field.                        */
1612   #define ATBREPLICATOR_LSR_TYPE_Min (0x0UL)         /*!< Min enumerator value of TYPE field.                                  */
1613   #define ATBREPLICATOR_LSR_TYPE_Max (0x1UL)         /*!< Max enumerator value of TYPE field.                                  */
1614   #define ATBREPLICATOR_LSR_TYPE_Bits32 (0x0UL)      /*!< This component implements a 32-bit Lock Access Register.             */
1615   #define ATBREPLICATOR_LSR_TYPE_Bits8 (0x1UL)       /*!< This component implements an 8-bit Lock Access Register.             */
1616 
1617 
1618 /* ATBREPLICATOR_AUTHSTATUS: Indicates the current level of tracing permitted by the system */
1619   #define ATBREPLICATOR_AUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of AUTHSTATUS register.                          */
1620 
1621 /* NSID @Bits 0..1 : Non-secure Invasive Debug */
1622   #define ATBREPLICATOR_AUTHSTATUS_NSID_Pos (0UL)    /*!< Position of NSID field.                                              */
1623   #define ATBREPLICATOR_AUTHSTATUS_NSID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field.          */
1624   #define ATBREPLICATOR_AUTHSTATUS_NSID_Min (0x0UL)  /*!< Min enumerator value of NSID field.                                  */
1625   #define ATBREPLICATOR_AUTHSTATUS_NSID_Max (0x1UL)  /*!< Max enumerator value of NSID field.                                  */
1626   #define ATBREPLICATOR_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented.                            */
1627   #define ATBREPLICATOR_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented.                                   */
1628 
1629 /* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */
1630   #define ATBREPLICATOR_AUTHSTATUS_NSNID_Pos (2UL)   /*!< Position of NSNID field.                                             */
1631   #define ATBREPLICATOR_AUTHSTATUS_NSNID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field.       */
1632   #define ATBREPLICATOR_AUTHSTATUS_NSNID_Min (0x0UL) /*!< Min enumerator value of NSNID field.                                 */
1633   #define ATBREPLICATOR_AUTHSTATUS_NSNID_Max (0x1UL) /*!< Max enumerator value of NSNID field.                                 */
1634   #define ATBREPLICATOR_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                           */
1635   #define ATBREPLICATOR_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented.                                  */
1636 
1637 /* SID @Bits 4..5 : Secure Invasive Debug */
1638   #define ATBREPLICATOR_AUTHSTATUS_SID_Pos (4UL)     /*!< Position of SID field.                                               */
1639   #define ATBREPLICATOR_AUTHSTATUS_SID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field.             */
1640   #define ATBREPLICATOR_AUTHSTATUS_SID_Min (0x0UL)   /*!< Min enumerator value of SID field.                                   */
1641   #define ATBREPLICATOR_AUTHSTATUS_SID_Max (0x1UL)   /*!< Max enumerator value of SID field.                                   */
1642   #define ATBREPLICATOR_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented.                             */
1643   #define ATBREPLICATOR_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented.                                    */
1644 
1645 /* SNID @Bits 6..7 : Secure Non-Invasive Debug */
1646   #define ATBREPLICATOR_AUTHSTATUS_SNID_Pos (6UL)    /*!< Position of SNID field.                                              */
1647   #define ATBREPLICATOR_AUTHSTATUS_SNID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field.          */
1648   #define ATBREPLICATOR_AUTHSTATUS_SNID_Min (0x0UL)  /*!< Min enumerator value of SNID field.                                  */
1649   #define ATBREPLICATOR_AUTHSTATUS_SNID_Max (0x1UL)  /*!< Max enumerator value of SNID field.                                  */
1650   #define ATBREPLICATOR_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                            */
1651   #define ATBREPLICATOR_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented.                                   */
1652 
1653 
1654 /* ATBREPLICATOR_DEVID: Indicates the capabilities of the component. */
1655   #define ATBREPLICATOR_DEVID_ResetValue (0x00000000UL) /*!< Reset value of DEVID register.                                    */
1656 
1657 /* PORTNUM @Bits 0..3 : Indicates the number of master ports implemented. */
1658   #define ATBREPLICATOR_DEVID_PORTNUM_Pos (0UL)      /*!< Position of PORTNUM field.                                           */
1659   #define ATBREPLICATOR_DEVID_PORTNUM_Msk (0xFUL << ATBREPLICATOR_DEVID_PORTNUM_Pos) /*!< Bit mask of PORTNUM field.           */
1660   #define ATBREPLICATOR_DEVID_PORTNUM_Min (0x0UL)    /*!< Min value of PORTNUM field.                                          */
1661   #define ATBREPLICATOR_DEVID_PORTNUM_Max (0xFUL)    /*!< Max size of PORTNUM field.                                           */
1662 
1663 
1664 /* ATBREPLICATOR_DEVTYPE: The DEVTYPE register provides a debugger with information about the component when the Part Number
1665                            field is not recognized. The debugger can then report this information. */
1666 
1667   #define ATBREPLICATOR_DEVTYPE_ResetValue (0x00000000UL) /*!< Reset value of DEVTYPE register.                                */
1668 
1669 /* MAJOR @Bits 0..3 : The main type of the component */
1670   #define ATBREPLICATOR_DEVTYPE_MAJOR_Pos (0UL)      /*!< Position of MAJOR field.                                             */
1671   #define ATBREPLICATOR_DEVTYPE_MAJOR_Msk (0xFUL << ATBREPLICATOR_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field.             */
1672   #define ATBREPLICATOR_DEVTYPE_MAJOR_Min (0x2UL)    /*!< Min enumerator value of MAJOR field.                                 */
1673   #define ATBREPLICATOR_DEVTYPE_MAJOR_Max (0x2UL)    /*!< Max enumerator value of MAJOR field.                                 */
1674   #define ATBREPLICATOR_DEVTYPE_MAJOR_InputOutputDevice (0x2UL) /*!< Indicates that this component has ATB inputs and outputs. */
1675 
1676 /* SUB @Bits 4..7 : The sub-type of the component */
1677   #define ATBREPLICATOR_DEVTYPE_SUB_Pos (4UL)        /*!< Position of SUB field.                                               */
1678   #define ATBREPLICATOR_DEVTYPE_SUB_Msk (0xFUL << ATBREPLICATOR_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field.                   */
1679   #define ATBREPLICATOR_DEVTYPE_SUB_Min (0x2UL)      /*!< Min enumerator value of SUB field.                                   */
1680   #define ATBREPLICATOR_DEVTYPE_SUB_Max (0x2UL)      /*!< Max enumerator value of SUB field.                                   */
1681   #define ATBREPLICATOR_DEVTYPE_SUB_Replicator (0x2UL) /*!< Indicates that this component replicates trace from a single source
1682                                                             to multiple targets.*/
1683 
1684 
1685 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
1686 
1687 /* =========================================================================================================================== */
1688 /* ================                                         BELLBOARD                                         ================ */
1689 /* =========================================================================================================================== */
1690 
1691 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
1692 /* ==================================================== Struct BELLBOARD ===================================================== */
1693 /**
1694   * @brief BELLBOARD APB registers
1695   */
1696   typedef struct {                                   /*!< BELLBOARD Structure                                                  */
1697     __OM uint32_t TASKS_TRIGGER[32];                 /*!< (@ 0x00000000) Task TRIGGER[n]                                       */
1698     __IM uint32_t RESERVED[32];
1699     __IOM uint32_t EVENTS_TRIGGERED[32];             /*!< (@ 0x00000100) Event TRIGGERED[n]                                    */
1700     __IM uint32_t RESERVED1[96];
1701     __IOM uint32_t INTEN0;                           /*!< (@ 0x00000300) Enable or disable interrupt                           */
1702     __IOM uint32_t INTENSET0;                        /*!< (@ 0x00000304) Enable interrupt                                      */
1703     __IOM uint32_t INTENCLR0;                        /*!< (@ 0x00000308) Disable interrupt                                     */
1704     __IM uint32_t INTPEND0;                          /*!< (@ 0x0000030C) Pending interrupts                                    */
1705     __IOM uint32_t INTEN1;                           /*!< (@ 0x00000310) Enable or disable interrupt                           */
1706     __IOM uint32_t INTENSET1;                        /*!< (@ 0x00000314) Enable interrupt                                      */
1707     __IOM uint32_t INTENCLR1;                        /*!< (@ 0x00000318) Disable interrupt                                     */
1708     __IM uint32_t INTPEND1;                          /*!< (@ 0x0000031C) Pending interrupts                                    */
1709     __IOM uint32_t INTEN2;                           /*!< (@ 0x00000320) Enable or disable interrupt                           */
1710     __IOM uint32_t INTENSET2;                        /*!< (@ 0x00000324) Enable interrupt                                      */
1711     __IOM uint32_t INTENCLR2;                        /*!< (@ 0x00000328) Disable interrupt                                     */
1712     __IM uint32_t INTPEND2;                          /*!< (@ 0x0000032C) Pending interrupts                                    */
1713     __IOM uint32_t INTEN3;                           /*!< (@ 0x00000330) Enable or disable interrupt                           */
1714     __IOM uint32_t INTENSET3;                        /*!< (@ 0x00000334) Enable interrupt                                      */
1715     __IOM uint32_t INTENCLR3;                        /*!< (@ 0x00000338) Disable interrupt                                     */
1716     __IM uint32_t INTPEND3;                          /*!< (@ 0x0000033C) Pending interrupts                                    */
1717     __IOM uint32_t INTEN4;                           /*!< (@ 0x00000340) Enable or disable interrupt                           */
1718     __IOM uint32_t INTENSET4;                        /*!< (@ 0x00000344) Enable interrupt                                      */
1719     __IOM uint32_t INTENCLR4;                        /*!< (@ 0x00000348) Disable interrupt                                     */
1720     __IM uint32_t INTPEND4;                          /*!< (@ 0x0000034C) Pending interrupts                                    */
1721     __IOM uint32_t INTEN5;                           /*!< (@ 0x00000350) Enable or disable interrupt                           */
1722     __IOM uint32_t INTENSET5;                        /*!< (@ 0x00000354) Enable interrupt                                      */
1723     __IOM uint32_t INTENCLR5;                        /*!< (@ 0x00000358) Disable interrupt                                     */
1724     __IM uint32_t INTPEND5;                          /*!< (@ 0x0000035C) Pending interrupts                                    */
1725     __IOM uint32_t INTEN6;                           /*!< (@ 0x00000360) Enable or disable interrupt                           */
1726     __IOM uint32_t INTENSET6;                        /*!< (@ 0x00000364) Enable interrupt                                      */
1727     __IOM uint32_t INTENCLR6;                        /*!< (@ 0x00000368) Disable interrupt                                     */
1728     __IM uint32_t INTPEND6;                          /*!< (@ 0x0000036C) Pending interrupts                                    */
1729     __IOM uint32_t INTEN7;                           /*!< (@ 0x00000370) Enable or disable interrupt                           */
1730     __IOM uint32_t INTENSET7;                        /*!< (@ 0x00000374) Enable interrupt                                      */
1731     __IOM uint32_t INTENCLR7;                        /*!< (@ 0x00000378) Disable interrupt                                     */
1732     __IM uint32_t INTPEND7;                          /*!< (@ 0x0000037C) Pending interrupts                                    */
1733   } NRF_BELLBOARD_Type;                              /*!< Size = 896 (0x380)                                                   */
1734 
1735 /* BELLBOARD_TASKS_TRIGGER: Task TRIGGER[n] */
1736   #define BELLBOARD_TASKS_TRIGGER_MaxCount (32UL)    /*!< Max size of TASKS_TRIGGER[32] array.                                 */
1737   #define BELLBOARD_TASKS_TRIGGER_MaxIndex (31UL)    /*!< Max index of TASKS_TRIGGER[32] array.                                */
1738   #define BELLBOARD_TASKS_TRIGGER_MinIndex (0UL)     /*!< Min index of TASKS_TRIGGER[32] array.                                */
1739   #define BELLBOARD_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register.                    */
1740 
1741 /* TASKS_TRIGGER @Bit 0 : Task TRIGGER[n] */
1742   #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field.                                */
1743   #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of
1744                                                                             TASKS_TRIGGER field.*/
1745   #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field.                  */
1746   #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field.                  */
1747   #define BELLBOARD_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task                                              */
1748 
1749 
1750 /* BELLBOARD_EVENTS_TRIGGERED: Event TRIGGERED[n] */
1751   #define BELLBOARD_EVENTS_TRIGGERED_MaxCount (32UL) /*!< Max size of EVENTS_TRIGGERED[32] array.                              */
1752   #define BELLBOARD_EVENTS_TRIGGERED_MaxIndex (31UL) /*!< Max index of EVENTS_TRIGGERED[32] array.                             */
1753   #define BELLBOARD_EVENTS_TRIGGERED_MinIndex (0UL)  /*!< Min index of EVENTS_TRIGGERED[32] array.                             */
1754   #define BELLBOARD_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[32] register.              */
1755 
1756 /* EVENTS_TRIGGERED @Bit 0 : Event TRIGGERED[n] */
1757   #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field.                       */
1758   #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit
1759                                                                             mask of EVENTS_TRIGGERED field.*/
1760   #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field.         */
1761   #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field.         */
1762   #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated                            */
1763   #define BELLBOARD_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated                                   */
1764 
1765 
1766 /* BELLBOARD_INTEN0: Enable or disable interrupt */
1767   #define BELLBOARD_INTEN0_ResetValue (0x00000000UL) /*!< Reset value of INTEN0 register.                                      */
1768 
1769 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
1770   #define BELLBOARD_INTEN0_TRIGGERED0_Pos (0UL)      /*!< Position of TRIGGERED0 field.                                        */
1771   #define BELLBOARD_INTEN0_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.        */
1772   #define BELLBOARD_INTEN0_TRIGGERED0_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED0 field.                            */
1773   #define BELLBOARD_INTEN0_TRIGGERED0_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED0 field.                            */
1774   #define BELLBOARD_INTEN0_TRIGGERED0_Disabled (0x0UL) /*!< Disable                                                            */
1775   #define BELLBOARD_INTEN0_TRIGGERED0_Enabled (0x1UL) /*!< Enable                                                              */
1776 
1777 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
1778   #define BELLBOARD_INTEN0_TRIGGERED1_Pos (1UL)      /*!< Position of TRIGGERED1 field.                                        */
1779   #define BELLBOARD_INTEN0_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.        */
1780   #define BELLBOARD_INTEN0_TRIGGERED1_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED1 field.                            */
1781   #define BELLBOARD_INTEN0_TRIGGERED1_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED1 field.                            */
1782   #define BELLBOARD_INTEN0_TRIGGERED1_Disabled (0x0UL) /*!< Disable                                                            */
1783   #define BELLBOARD_INTEN0_TRIGGERED1_Enabled (0x1UL) /*!< Enable                                                              */
1784 
1785 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
1786   #define BELLBOARD_INTEN0_TRIGGERED2_Pos (2UL)      /*!< Position of TRIGGERED2 field.                                        */
1787   #define BELLBOARD_INTEN0_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.        */
1788   #define BELLBOARD_INTEN0_TRIGGERED2_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED2 field.                            */
1789   #define BELLBOARD_INTEN0_TRIGGERED2_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED2 field.                            */
1790   #define BELLBOARD_INTEN0_TRIGGERED2_Disabled (0x0UL) /*!< Disable                                                            */
1791   #define BELLBOARD_INTEN0_TRIGGERED2_Enabled (0x1UL) /*!< Enable                                                              */
1792 
1793 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
1794   #define BELLBOARD_INTEN0_TRIGGERED3_Pos (3UL)      /*!< Position of TRIGGERED3 field.                                        */
1795   #define BELLBOARD_INTEN0_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.        */
1796   #define BELLBOARD_INTEN0_TRIGGERED3_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED3 field.                            */
1797   #define BELLBOARD_INTEN0_TRIGGERED3_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED3 field.                            */
1798   #define BELLBOARD_INTEN0_TRIGGERED3_Disabled (0x0UL) /*!< Disable                                                            */
1799   #define BELLBOARD_INTEN0_TRIGGERED3_Enabled (0x1UL) /*!< Enable                                                              */
1800 
1801 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
1802   #define BELLBOARD_INTEN0_TRIGGERED4_Pos (4UL)      /*!< Position of TRIGGERED4 field.                                        */
1803   #define BELLBOARD_INTEN0_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.        */
1804   #define BELLBOARD_INTEN0_TRIGGERED4_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED4 field.                            */
1805   #define BELLBOARD_INTEN0_TRIGGERED4_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED4 field.                            */
1806   #define BELLBOARD_INTEN0_TRIGGERED4_Disabled (0x0UL) /*!< Disable                                                            */
1807   #define BELLBOARD_INTEN0_TRIGGERED4_Enabled (0x1UL) /*!< Enable                                                              */
1808 
1809 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
1810   #define BELLBOARD_INTEN0_TRIGGERED5_Pos (5UL)      /*!< Position of TRIGGERED5 field.                                        */
1811   #define BELLBOARD_INTEN0_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.        */
1812   #define BELLBOARD_INTEN0_TRIGGERED5_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED5 field.                            */
1813   #define BELLBOARD_INTEN0_TRIGGERED5_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED5 field.                            */
1814   #define BELLBOARD_INTEN0_TRIGGERED5_Disabled (0x0UL) /*!< Disable                                                            */
1815   #define BELLBOARD_INTEN0_TRIGGERED5_Enabled (0x1UL) /*!< Enable                                                              */
1816 
1817 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
1818   #define BELLBOARD_INTEN0_TRIGGERED6_Pos (6UL)      /*!< Position of TRIGGERED6 field.                                        */
1819   #define BELLBOARD_INTEN0_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.        */
1820   #define BELLBOARD_INTEN0_TRIGGERED6_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED6 field.                            */
1821   #define BELLBOARD_INTEN0_TRIGGERED6_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED6 field.                            */
1822   #define BELLBOARD_INTEN0_TRIGGERED6_Disabled (0x0UL) /*!< Disable                                                            */
1823   #define BELLBOARD_INTEN0_TRIGGERED6_Enabled (0x1UL) /*!< Enable                                                              */
1824 
1825 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
1826   #define BELLBOARD_INTEN0_TRIGGERED7_Pos (7UL)      /*!< Position of TRIGGERED7 field.                                        */
1827   #define BELLBOARD_INTEN0_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.        */
1828   #define BELLBOARD_INTEN0_TRIGGERED7_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED7 field.                            */
1829   #define BELLBOARD_INTEN0_TRIGGERED7_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED7 field.                            */
1830   #define BELLBOARD_INTEN0_TRIGGERED7_Disabled (0x0UL) /*!< Disable                                                            */
1831   #define BELLBOARD_INTEN0_TRIGGERED7_Enabled (0x1UL) /*!< Enable                                                              */
1832 
1833 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
1834   #define BELLBOARD_INTEN0_TRIGGERED8_Pos (8UL)      /*!< Position of TRIGGERED8 field.                                        */
1835   #define BELLBOARD_INTEN0_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.        */
1836   #define BELLBOARD_INTEN0_TRIGGERED8_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED8 field.                            */
1837   #define BELLBOARD_INTEN0_TRIGGERED8_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED8 field.                            */
1838   #define BELLBOARD_INTEN0_TRIGGERED8_Disabled (0x0UL) /*!< Disable                                                            */
1839   #define BELLBOARD_INTEN0_TRIGGERED8_Enabled (0x1UL) /*!< Enable                                                              */
1840 
1841 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
1842   #define BELLBOARD_INTEN0_TRIGGERED9_Pos (9UL)      /*!< Position of TRIGGERED9 field.                                        */
1843   #define BELLBOARD_INTEN0_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.        */
1844   #define BELLBOARD_INTEN0_TRIGGERED9_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED9 field.                            */
1845   #define BELLBOARD_INTEN0_TRIGGERED9_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED9 field.                            */
1846   #define BELLBOARD_INTEN0_TRIGGERED9_Disabled (0x0UL) /*!< Disable                                                            */
1847   #define BELLBOARD_INTEN0_TRIGGERED9_Enabled (0x1UL) /*!< Enable                                                              */
1848 
1849 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
1850   #define BELLBOARD_INTEN0_TRIGGERED10_Pos (10UL)    /*!< Position of TRIGGERED10 field.                                       */
1851   #define BELLBOARD_INTEN0_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.     */
1852   #define BELLBOARD_INTEN0_TRIGGERED10_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED10 field.                           */
1853   #define BELLBOARD_INTEN0_TRIGGERED10_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED10 field.                           */
1854   #define BELLBOARD_INTEN0_TRIGGERED10_Disabled (0x0UL) /*!< Disable                                                           */
1855   #define BELLBOARD_INTEN0_TRIGGERED10_Enabled (0x1UL) /*!< Enable                                                             */
1856 
1857 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
1858   #define BELLBOARD_INTEN0_TRIGGERED11_Pos (11UL)    /*!< Position of TRIGGERED11 field.                                       */
1859   #define BELLBOARD_INTEN0_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.     */
1860   #define BELLBOARD_INTEN0_TRIGGERED11_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED11 field.                           */
1861   #define BELLBOARD_INTEN0_TRIGGERED11_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED11 field.                           */
1862   #define BELLBOARD_INTEN0_TRIGGERED11_Disabled (0x0UL) /*!< Disable                                                           */
1863   #define BELLBOARD_INTEN0_TRIGGERED11_Enabled (0x1UL) /*!< Enable                                                             */
1864 
1865 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
1866   #define BELLBOARD_INTEN0_TRIGGERED12_Pos (12UL)    /*!< Position of TRIGGERED12 field.                                       */
1867   #define BELLBOARD_INTEN0_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.     */
1868   #define BELLBOARD_INTEN0_TRIGGERED12_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED12 field.                           */
1869   #define BELLBOARD_INTEN0_TRIGGERED12_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED12 field.                           */
1870   #define BELLBOARD_INTEN0_TRIGGERED12_Disabled (0x0UL) /*!< Disable                                                           */
1871   #define BELLBOARD_INTEN0_TRIGGERED12_Enabled (0x1UL) /*!< Enable                                                             */
1872 
1873 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
1874   #define BELLBOARD_INTEN0_TRIGGERED13_Pos (13UL)    /*!< Position of TRIGGERED13 field.                                       */
1875   #define BELLBOARD_INTEN0_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.     */
1876   #define BELLBOARD_INTEN0_TRIGGERED13_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED13 field.                           */
1877   #define BELLBOARD_INTEN0_TRIGGERED13_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED13 field.                           */
1878   #define BELLBOARD_INTEN0_TRIGGERED13_Disabled (0x0UL) /*!< Disable                                                           */
1879   #define BELLBOARD_INTEN0_TRIGGERED13_Enabled (0x1UL) /*!< Enable                                                             */
1880 
1881 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
1882   #define BELLBOARD_INTEN0_TRIGGERED14_Pos (14UL)    /*!< Position of TRIGGERED14 field.                                       */
1883   #define BELLBOARD_INTEN0_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.     */
1884   #define BELLBOARD_INTEN0_TRIGGERED14_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED14 field.                           */
1885   #define BELLBOARD_INTEN0_TRIGGERED14_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED14 field.                           */
1886   #define BELLBOARD_INTEN0_TRIGGERED14_Disabled (0x0UL) /*!< Disable                                                           */
1887   #define BELLBOARD_INTEN0_TRIGGERED14_Enabled (0x1UL) /*!< Enable                                                             */
1888 
1889 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
1890   #define BELLBOARD_INTEN0_TRIGGERED15_Pos (15UL)    /*!< Position of TRIGGERED15 field.                                       */
1891   #define BELLBOARD_INTEN0_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.     */
1892   #define BELLBOARD_INTEN0_TRIGGERED15_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED15 field.                           */
1893   #define BELLBOARD_INTEN0_TRIGGERED15_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED15 field.                           */
1894   #define BELLBOARD_INTEN0_TRIGGERED15_Disabled (0x0UL) /*!< Disable                                                           */
1895   #define BELLBOARD_INTEN0_TRIGGERED15_Enabled (0x1UL) /*!< Enable                                                             */
1896 
1897 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
1898   #define BELLBOARD_INTEN0_TRIGGERED16_Pos (16UL)    /*!< Position of TRIGGERED16 field.                                       */
1899   #define BELLBOARD_INTEN0_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.     */
1900   #define BELLBOARD_INTEN0_TRIGGERED16_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED16 field.                           */
1901   #define BELLBOARD_INTEN0_TRIGGERED16_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED16 field.                           */
1902   #define BELLBOARD_INTEN0_TRIGGERED16_Disabled (0x0UL) /*!< Disable                                                           */
1903   #define BELLBOARD_INTEN0_TRIGGERED16_Enabled (0x1UL) /*!< Enable                                                             */
1904 
1905 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
1906   #define BELLBOARD_INTEN0_TRIGGERED17_Pos (17UL)    /*!< Position of TRIGGERED17 field.                                       */
1907   #define BELLBOARD_INTEN0_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.     */
1908   #define BELLBOARD_INTEN0_TRIGGERED17_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED17 field.                           */
1909   #define BELLBOARD_INTEN0_TRIGGERED17_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED17 field.                           */
1910   #define BELLBOARD_INTEN0_TRIGGERED17_Disabled (0x0UL) /*!< Disable                                                           */
1911   #define BELLBOARD_INTEN0_TRIGGERED17_Enabled (0x1UL) /*!< Enable                                                             */
1912 
1913 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
1914   #define BELLBOARD_INTEN0_TRIGGERED18_Pos (18UL)    /*!< Position of TRIGGERED18 field.                                       */
1915   #define BELLBOARD_INTEN0_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.     */
1916   #define BELLBOARD_INTEN0_TRIGGERED18_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED18 field.                           */
1917   #define BELLBOARD_INTEN0_TRIGGERED18_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED18 field.                           */
1918   #define BELLBOARD_INTEN0_TRIGGERED18_Disabled (0x0UL) /*!< Disable                                                           */
1919   #define BELLBOARD_INTEN0_TRIGGERED18_Enabled (0x1UL) /*!< Enable                                                             */
1920 
1921 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
1922   #define BELLBOARD_INTEN0_TRIGGERED19_Pos (19UL)    /*!< Position of TRIGGERED19 field.                                       */
1923   #define BELLBOARD_INTEN0_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.     */
1924   #define BELLBOARD_INTEN0_TRIGGERED19_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED19 field.                           */
1925   #define BELLBOARD_INTEN0_TRIGGERED19_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED19 field.                           */
1926   #define BELLBOARD_INTEN0_TRIGGERED19_Disabled (0x0UL) /*!< Disable                                                           */
1927   #define BELLBOARD_INTEN0_TRIGGERED19_Enabled (0x1UL) /*!< Enable                                                             */
1928 
1929 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
1930   #define BELLBOARD_INTEN0_TRIGGERED20_Pos (20UL)    /*!< Position of TRIGGERED20 field.                                       */
1931   #define BELLBOARD_INTEN0_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.     */
1932   #define BELLBOARD_INTEN0_TRIGGERED20_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED20 field.                           */
1933   #define BELLBOARD_INTEN0_TRIGGERED20_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED20 field.                           */
1934   #define BELLBOARD_INTEN0_TRIGGERED20_Disabled (0x0UL) /*!< Disable                                                           */
1935   #define BELLBOARD_INTEN0_TRIGGERED20_Enabled (0x1UL) /*!< Enable                                                             */
1936 
1937 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
1938   #define BELLBOARD_INTEN0_TRIGGERED21_Pos (21UL)    /*!< Position of TRIGGERED21 field.                                       */
1939   #define BELLBOARD_INTEN0_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.     */
1940   #define BELLBOARD_INTEN0_TRIGGERED21_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED21 field.                           */
1941   #define BELLBOARD_INTEN0_TRIGGERED21_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED21 field.                           */
1942   #define BELLBOARD_INTEN0_TRIGGERED21_Disabled (0x0UL) /*!< Disable                                                           */
1943   #define BELLBOARD_INTEN0_TRIGGERED21_Enabled (0x1UL) /*!< Enable                                                             */
1944 
1945 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
1946   #define BELLBOARD_INTEN0_TRIGGERED22_Pos (22UL)    /*!< Position of TRIGGERED22 field.                                       */
1947   #define BELLBOARD_INTEN0_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.     */
1948   #define BELLBOARD_INTEN0_TRIGGERED22_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED22 field.                           */
1949   #define BELLBOARD_INTEN0_TRIGGERED22_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED22 field.                           */
1950   #define BELLBOARD_INTEN0_TRIGGERED22_Disabled (0x0UL) /*!< Disable                                                           */
1951   #define BELLBOARD_INTEN0_TRIGGERED22_Enabled (0x1UL) /*!< Enable                                                             */
1952 
1953 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
1954   #define BELLBOARD_INTEN0_TRIGGERED23_Pos (23UL)    /*!< Position of TRIGGERED23 field.                                       */
1955   #define BELLBOARD_INTEN0_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.     */
1956   #define BELLBOARD_INTEN0_TRIGGERED23_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED23 field.                           */
1957   #define BELLBOARD_INTEN0_TRIGGERED23_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED23 field.                           */
1958   #define BELLBOARD_INTEN0_TRIGGERED23_Disabled (0x0UL) /*!< Disable                                                           */
1959   #define BELLBOARD_INTEN0_TRIGGERED23_Enabled (0x1UL) /*!< Enable                                                             */
1960 
1961 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
1962   #define BELLBOARD_INTEN0_TRIGGERED24_Pos (24UL)    /*!< Position of TRIGGERED24 field.                                       */
1963   #define BELLBOARD_INTEN0_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.     */
1964   #define BELLBOARD_INTEN0_TRIGGERED24_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED24 field.                           */
1965   #define BELLBOARD_INTEN0_TRIGGERED24_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED24 field.                           */
1966   #define BELLBOARD_INTEN0_TRIGGERED24_Disabled (0x0UL) /*!< Disable                                                           */
1967   #define BELLBOARD_INTEN0_TRIGGERED24_Enabled (0x1UL) /*!< Enable                                                             */
1968 
1969 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
1970   #define BELLBOARD_INTEN0_TRIGGERED25_Pos (25UL)    /*!< Position of TRIGGERED25 field.                                       */
1971   #define BELLBOARD_INTEN0_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.     */
1972   #define BELLBOARD_INTEN0_TRIGGERED25_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED25 field.                           */
1973   #define BELLBOARD_INTEN0_TRIGGERED25_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED25 field.                           */
1974   #define BELLBOARD_INTEN0_TRIGGERED25_Disabled (0x0UL) /*!< Disable                                                           */
1975   #define BELLBOARD_INTEN0_TRIGGERED25_Enabled (0x1UL) /*!< Enable                                                             */
1976 
1977 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
1978   #define BELLBOARD_INTEN0_TRIGGERED26_Pos (26UL)    /*!< Position of TRIGGERED26 field.                                       */
1979   #define BELLBOARD_INTEN0_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.     */
1980   #define BELLBOARD_INTEN0_TRIGGERED26_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED26 field.                           */
1981   #define BELLBOARD_INTEN0_TRIGGERED26_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED26 field.                           */
1982   #define BELLBOARD_INTEN0_TRIGGERED26_Disabled (0x0UL) /*!< Disable                                                           */
1983   #define BELLBOARD_INTEN0_TRIGGERED26_Enabled (0x1UL) /*!< Enable                                                             */
1984 
1985 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
1986   #define BELLBOARD_INTEN0_TRIGGERED27_Pos (27UL)    /*!< Position of TRIGGERED27 field.                                       */
1987   #define BELLBOARD_INTEN0_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.     */
1988   #define BELLBOARD_INTEN0_TRIGGERED27_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED27 field.                           */
1989   #define BELLBOARD_INTEN0_TRIGGERED27_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED27 field.                           */
1990   #define BELLBOARD_INTEN0_TRIGGERED27_Disabled (0x0UL) /*!< Disable                                                           */
1991   #define BELLBOARD_INTEN0_TRIGGERED27_Enabled (0x1UL) /*!< Enable                                                             */
1992 
1993 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
1994   #define BELLBOARD_INTEN0_TRIGGERED28_Pos (28UL)    /*!< Position of TRIGGERED28 field.                                       */
1995   #define BELLBOARD_INTEN0_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.     */
1996   #define BELLBOARD_INTEN0_TRIGGERED28_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED28 field.                           */
1997   #define BELLBOARD_INTEN0_TRIGGERED28_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED28 field.                           */
1998   #define BELLBOARD_INTEN0_TRIGGERED28_Disabled (0x0UL) /*!< Disable                                                           */
1999   #define BELLBOARD_INTEN0_TRIGGERED28_Enabled (0x1UL) /*!< Enable                                                             */
2000 
2001 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
2002   #define BELLBOARD_INTEN0_TRIGGERED29_Pos (29UL)    /*!< Position of TRIGGERED29 field.                                       */
2003   #define BELLBOARD_INTEN0_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.     */
2004   #define BELLBOARD_INTEN0_TRIGGERED29_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED29 field.                           */
2005   #define BELLBOARD_INTEN0_TRIGGERED29_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED29 field.                           */
2006   #define BELLBOARD_INTEN0_TRIGGERED29_Disabled (0x0UL) /*!< Disable                                                           */
2007   #define BELLBOARD_INTEN0_TRIGGERED29_Enabled (0x1UL) /*!< Enable                                                             */
2008 
2009 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
2010   #define BELLBOARD_INTEN0_TRIGGERED30_Pos (30UL)    /*!< Position of TRIGGERED30 field.                                       */
2011   #define BELLBOARD_INTEN0_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.     */
2012   #define BELLBOARD_INTEN0_TRIGGERED30_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED30 field.                           */
2013   #define BELLBOARD_INTEN0_TRIGGERED30_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED30 field.                           */
2014   #define BELLBOARD_INTEN0_TRIGGERED30_Disabled (0x0UL) /*!< Disable                                                           */
2015   #define BELLBOARD_INTEN0_TRIGGERED30_Enabled (0x1UL) /*!< Enable                                                             */
2016 
2017 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
2018   #define BELLBOARD_INTEN0_TRIGGERED31_Pos (31UL)    /*!< Position of TRIGGERED31 field.                                       */
2019   #define BELLBOARD_INTEN0_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN0_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.     */
2020   #define BELLBOARD_INTEN0_TRIGGERED31_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED31 field.                           */
2021   #define BELLBOARD_INTEN0_TRIGGERED31_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED31 field.                           */
2022   #define BELLBOARD_INTEN0_TRIGGERED31_Disabled (0x0UL) /*!< Disable                                                           */
2023   #define BELLBOARD_INTEN0_TRIGGERED31_Enabled (0x1UL) /*!< Enable                                                             */
2024 
2025 
2026 /* BELLBOARD_INTENSET0: Enable interrupt */
2027   #define BELLBOARD_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register.                                */
2028 
2029 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
2030   #define BELLBOARD_INTENSET0_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
2031   #define BELLBOARD_INTENSET0_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
2032   #define BELLBOARD_INTENSET0_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
2033   #define BELLBOARD_INTENSET0_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
2034   #define BELLBOARD_INTENSET0_TRIGGERED0_Set (0x1UL) /*!< Enable                                                               */
2035   #define BELLBOARD_INTENSET0_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2036   #define BELLBOARD_INTENSET0_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2037 
2038 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
2039   #define BELLBOARD_INTENSET0_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
2040   #define BELLBOARD_INTENSET0_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
2041   #define BELLBOARD_INTENSET0_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
2042   #define BELLBOARD_INTENSET0_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
2043   #define BELLBOARD_INTENSET0_TRIGGERED1_Set (0x1UL) /*!< Enable                                                               */
2044   #define BELLBOARD_INTENSET0_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2045   #define BELLBOARD_INTENSET0_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2046 
2047 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
2048   #define BELLBOARD_INTENSET0_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
2049   #define BELLBOARD_INTENSET0_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
2050   #define BELLBOARD_INTENSET0_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
2051   #define BELLBOARD_INTENSET0_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
2052   #define BELLBOARD_INTENSET0_TRIGGERED2_Set (0x1UL) /*!< Enable                                                               */
2053   #define BELLBOARD_INTENSET0_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2054   #define BELLBOARD_INTENSET0_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2055 
2056 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
2057   #define BELLBOARD_INTENSET0_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
2058   #define BELLBOARD_INTENSET0_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
2059   #define BELLBOARD_INTENSET0_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
2060   #define BELLBOARD_INTENSET0_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
2061   #define BELLBOARD_INTENSET0_TRIGGERED3_Set (0x1UL) /*!< Enable                                                               */
2062   #define BELLBOARD_INTENSET0_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2063   #define BELLBOARD_INTENSET0_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2064 
2065 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
2066   #define BELLBOARD_INTENSET0_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
2067   #define BELLBOARD_INTENSET0_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
2068   #define BELLBOARD_INTENSET0_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
2069   #define BELLBOARD_INTENSET0_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
2070   #define BELLBOARD_INTENSET0_TRIGGERED4_Set (0x1UL) /*!< Enable                                                               */
2071   #define BELLBOARD_INTENSET0_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2072   #define BELLBOARD_INTENSET0_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2073 
2074 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
2075   #define BELLBOARD_INTENSET0_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
2076   #define BELLBOARD_INTENSET0_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
2077   #define BELLBOARD_INTENSET0_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
2078   #define BELLBOARD_INTENSET0_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
2079   #define BELLBOARD_INTENSET0_TRIGGERED5_Set (0x1UL) /*!< Enable                                                               */
2080   #define BELLBOARD_INTENSET0_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2081   #define BELLBOARD_INTENSET0_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2082 
2083 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
2084   #define BELLBOARD_INTENSET0_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
2085   #define BELLBOARD_INTENSET0_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
2086   #define BELLBOARD_INTENSET0_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
2087   #define BELLBOARD_INTENSET0_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
2088   #define BELLBOARD_INTENSET0_TRIGGERED6_Set (0x1UL) /*!< Enable                                                               */
2089   #define BELLBOARD_INTENSET0_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2090   #define BELLBOARD_INTENSET0_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2091 
2092 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
2093   #define BELLBOARD_INTENSET0_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
2094   #define BELLBOARD_INTENSET0_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
2095   #define BELLBOARD_INTENSET0_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
2096   #define BELLBOARD_INTENSET0_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
2097   #define BELLBOARD_INTENSET0_TRIGGERED7_Set (0x1UL) /*!< Enable                                                               */
2098   #define BELLBOARD_INTENSET0_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2099   #define BELLBOARD_INTENSET0_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2100 
2101 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
2102   #define BELLBOARD_INTENSET0_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
2103   #define BELLBOARD_INTENSET0_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
2104   #define BELLBOARD_INTENSET0_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
2105   #define BELLBOARD_INTENSET0_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
2106   #define BELLBOARD_INTENSET0_TRIGGERED8_Set (0x1UL) /*!< Enable                                                               */
2107   #define BELLBOARD_INTENSET0_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2108   #define BELLBOARD_INTENSET0_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2109 
2110 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
2111   #define BELLBOARD_INTENSET0_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
2112   #define BELLBOARD_INTENSET0_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
2113   #define BELLBOARD_INTENSET0_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
2114   #define BELLBOARD_INTENSET0_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
2115   #define BELLBOARD_INTENSET0_TRIGGERED9_Set (0x1UL) /*!< Enable                                                               */
2116   #define BELLBOARD_INTENSET0_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2117   #define BELLBOARD_INTENSET0_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2118 
2119 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
2120   #define BELLBOARD_INTENSET0_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
2121   #define BELLBOARD_INTENSET0_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
2122                                                                             field.*/
2123   #define BELLBOARD_INTENSET0_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
2124   #define BELLBOARD_INTENSET0_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
2125   #define BELLBOARD_INTENSET0_TRIGGERED10_Set (0x1UL) /*!< Enable                                                              */
2126   #define BELLBOARD_INTENSET0_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2127   #define BELLBOARD_INTENSET0_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2128 
2129 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
2130   #define BELLBOARD_INTENSET0_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
2131   #define BELLBOARD_INTENSET0_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
2132                                                                             field.*/
2133   #define BELLBOARD_INTENSET0_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
2134   #define BELLBOARD_INTENSET0_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
2135   #define BELLBOARD_INTENSET0_TRIGGERED11_Set (0x1UL) /*!< Enable                                                              */
2136   #define BELLBOARD_INTENSET0_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2137   #define BELLBOARD_INTENSET0_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2138 
2139 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
2140   #define BELLBOARD_INTENSET0_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
2141   #define BELLBOARD_INTENSET0_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
2142                                                                             field.*/
2143   #define BELLBOARD_INTENSET0_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
2144   #define BELLBOARD_INTENSET0_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
2145   #define BELLBOARD_INTENSET0_TRIGGERED12_Set (0x1UL) /*!< Enable                                                              */
2146   #define BELLBOARD_INTENSET0_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2147   #define BELLBOARD_INTENSET0_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2148 
2149 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
2150   #define BELLBOARD_INTENSET0_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
2151   #define BELLBOARD_INTENSET0_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
2152                                                                             field.*/
2153   #define BELLBOARD_INTENSET0_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
2154   #define BELLBOARD_INTENSET0_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
2155   #define BELLBOARD_INTENSET0_TRIGGERED13_Set (0x1UL) /*!< Enable                                                              */
2156   #define BELLBOARD_INTENSET0_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2157   #define BELLBOARD_INTENSET0_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2158 
2159 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
2160   #define BELLBOARD_INTENSET0_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
2161   #define BELLBOARD_INTENSET0_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
2162                                                                             field.*/
2163   #define BELLBOARD_INTENSET0_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
2164   #define BELLBOARD_INTENSET0_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
2165   #define BELLBOARD_INTENSET0_TRIGGERED14_Set (0x1UL) /*!< Enable                                                              */
2166   #define BELLBOARD_INTENSET0_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2167   #define BELLBOARD_INTENSET0_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2168 
2169 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
2170   #define BELLBOARD_INTENSET0_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
2171   #define BELLBOARD_INTENSET0_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
2172                                                                             field.*/
2173   #define BELLBOARD_INTENSET0_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
2174   #define BELLBOARD_INTENSET0_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
2175   #define BELLBOARD_INTENSET0_TRIGGERED15_Set (0x1UL) /*!< Enable                                                              */
2176   #define BELLBOARD_INTENSET0_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2177   #define BELLBOARD_INTENSET0_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2178 
2179 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
2180   #define BELLBOARD_INTENSET0_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
2181   #define BELLBOARD_INTENSET0_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
2182                                                                             field.*/
2183   #define BELLBOARD_INTENSET0_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
2184   #define BELLBOARD_INTENSET0_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
2185   #define BELLBOARD_INTENSET0_TRIGGERED16_Set (0x1UL) /*!< Enable                                                              */
2186   #define BELLBOARD_INTENSET0_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2187   #define BELLBOARD_INTENSET0_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2188 
2189 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
2190   #define BELLBOARD_INTENSET0_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
2191   #define BELLBOARD_INTENSET0_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
2192                                                                             field.*/
2193   #define BELLBOARD_INTENSET0_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
2194   #define BELLBOARD_INTENSET0_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
2195   #define BELLBOARD_INTENSET0_TRIGGERED17_Set (0x1UL) /*!< Enable                                                              */
2196   #define BELLBOARD_INTENSET0_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2197   #define BELLBOARD_INTENSET0_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2198 
2199 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
2200   #define BELLBOARD_INTENSET0_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
2201   #define BELLBOARD_INTENSET0_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
2202                                                                             field.*/
2203   #define BELLBOARD_INTENSET0_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
2204   #define BELLBOARD_INTENSET0_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
2205   #define BELLBOARD_INTENSET0_TRIGGERED18_Set (0x1UL) /*!< Enable                                                              */
2206   #define BELLBOARD_INTENSET0_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2207   #define BELLBOARD_INTENSET0_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2208 
2209 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
2210   #define BELLBOARD_INTENSET0_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
2211   #define BELLBOARD_INTENSET0_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
2212                                                                             field.*/
2213   #define BELLBOARD_INTENSET0_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
2214   #define BELLBOARD_INTENSET0_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
2215   #define BELLBOARD_INTENSET0_TRIGGERED19_Set (0x1UL) /*!< Enable                                                              */
2216   #define BELLBOARD_INTENSET0_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2217   #define BELLBOARD_INTENSET0_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2218 
2219 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
2220   #define BELLBOARD_INTENSET0_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
2221   #define BELLBOARD_INTENSET0_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
2222                                                                             field.*/
2223   #define BELLBOARD_INTENSET0_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
2224   #define BELLBOARD_INTENSET0_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
2225   #define BELLBOARD_INTENSET0_TRIGGERED20_Set (0x1UL) /*!< Enable                                                              */
2226   #define BELLBOARD_INTENSET0_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2227   #define BELLBOARD_INTENSET0_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2228 
2229 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
2230   #define BELLBOARD_INTENSET0_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
2231   #define BELLBOARD_INTENSET0_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
2232                                                                             field.*/
2233   #define BELLBOARD_INTENSET0_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
2234   #define BELLBOARD_INTENSET0_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
2235   #define BELLBOARD_INTENSET0_TRIGGERED21_Set (0x1UL) /*!< Enable                                                              */
2236   #define BELLBOARD_INTENSET0_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2237   #define BELLBOARD_INTENSET0_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2238 
2239 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
2240   #define BELLBOARD_INTENSET0_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
2241   #define BELLBOARD_INTENSET0_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
2242                                                                             field.*/
2243   #define BELLBOARD_INTENSET0_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
2244   #define BELLBOARD_INTENSET0_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
2245   #define BELLBOARD_INTENSET0_TRIGGERED22_Set (0x1UL) /*!< Enable                                                              */
2246   #define BELLBOARD_INTENSET0_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2247   #define BELLBOARD_INTENSET0_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2248 
2249 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
2250   #define BELLBOARD_INTENSET0_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
2251   #define BELLBOARD_INTENSET0_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
2252                                                                             field.*/
2253   #define BELLBOARD_INTENSET0_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
2254   #define BELLBOARD_INTENSET0_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
2255   #define BELLBOARD_INTENSET0_TRIGGERED23_Set (0x1UL) /*!< Enable                                                              */
2256   #define BELLBOARD_INTENSET0_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2257   #define BELLBOARD_INTENSET0_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2258 
2259 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
2260   #define BELLBOARD_INTENSET0_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
2261   #define BELLBOARD_INTENSET0_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
2262                                                                             field.*/
2263   #define BELLBOARD_INTENSET0_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
2264   #define BELLBOARD_INTENSET0_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
2265   #define BELLBOARD_INTENSET0_TRIGGERED24_Set (0x1UL) /*!< Enable                                                              */
2266   #define BELLBOARD_INTENSET0_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2267   #define BELLBOARD_INTENSET0_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2268 
2269 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
2270   #define BELLBOARD_INTENSET0_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
2271   #define BELLBOARD_INTENSET0_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
2272                                                                             field.*/
2273   #define BELLBOARD_INTENSET0_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
2274   #define BELLBOARD_INTENSET0_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
2275   #define BELLBOARD_INTENSET0_TRIGGERED25_Set (0x1UL) /*!< Enable                                                              */
2276   #define BELLBOARD_INTENSET0_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2277   #define BELLBOARD_INTENSET0_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2278 
2279 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
2280   #define BELLBOARD_INTENSET0_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
2281   #define BELLBOARD_INTENSET0_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
2282                                                                             field.*/
2283   #define BELLBOARD_INTENSET0_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
2284   #define BELLBOARD_INTENSET0_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
2285   #define BELLBOARD_INTENSET0_TRIGGERED26_Set (0x1UL) /*!< Enable                                                              */
2286   #define BELLBOARD_INTENSET0_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2287   #define BELLBOARD_INTENSET0_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2288 
2289 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
2290   #define BELLBOARD_INTENSET0_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
2291   #define BELLBOARD_INTENSET0_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
2292                                                                             field.*/
2293   #define BELLBOARD_INTENSET0_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
2294   #define BELLBOARD_INTENSET0_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
2295   #define BELLBOARD_INTENSET0_TRIGGERED27_Set (0x1UL) /*!< Enable                                                              */
2296   #define BELLBOARD_INTENSET0_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2297   #define BELLBOARD_INTENSET0_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2298 
2299 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
2300   #define BELLBOARD_INTENSET0_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
2301   #define BELLBOARD_INTENSET0_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
2302                                                                             field.*/
2303   #define BELLBOARD_INTENSET0_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
2304   #define BELLBOARD_INTENSET0_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
2305   #define BELLBOARD_INTENSET0_TRIGGERED28_Set (0x1UL) /*!< Enable                                                              */
2306   #define BELLBOARD_INTENSET0_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2307   #define BELLBOARD_INTENSET0_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2308 
2309 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
2310   #define BELLBOARD_INTENSET0_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
2311   #define BELLBOARD_INTENSET0_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
2312                                                                             field.*/
2313   #define BELLBOARD_INTENSET0_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
2314   #define BELLBOARD_INTENSET0_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
2315   #define BELLBOARD_INTENSET0_TRIGGERED29_Set (0x1UL) /*!< Enable                                                              */
2316   #define BELLBOARD_INTENSET0_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2317   #define BELLBOARD_INTENSET0_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2318 
2319 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
2320   #define BELLBOARD_INTENSET0_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
2321   #define BELLBOARD_INTENSET0_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
2322                                                                             field.*/
2323   #define BELLBOARD_INTENSET0_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
2324   #define BELLBOARD_INTENSET0_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
2325   #define BELLBOARD_INTENSET0_TRIGGERED30_Set (0x1UL) /*!< Enable                                                              */
2326   #define BELLBOARD_INTENSET0_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2327   #define BELLBOARD_INTENSET0_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2328 
2329 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
2330   #define BELLBOARD_INTENSET0_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
2331   #define BELLBOARD_INTENSET0_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET0_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
2332                                                                             field.*/
2333   #define BELLBOARD_INTENSET0_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
2334   #define BELLBOARD_INTENSET0_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
2335   #define BELLBOARD_INTENSET0_TRIGGERED31_Set (0x1UL) /*!< Enable                                                              */
2336   #define BELLBOARD_INTENSET0_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2337   #define BELLBOARD_INTENSET0_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2338 
2339 
2340 /* BELLBOARD_INTENCLR0: Disable interrupt */
2341   #define BELLBOARD_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register.                                */
2342 
2343 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
2344   #define BELLBOARD_INTENCLR0_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
2345   #define BELLBOARD_INTENCLR0_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
2346   #define BELLBOARD_INTENCLR0_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
2347   #define BELLBOARD_INTENCLR0_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
2348   #define BELLBOARD_INTENCLR0_TRIGGERED0_Clear (0x1UL) /*!< Disable                                                            */
2349   #define BELLBOARD_INTENCLR0_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2350   #define BELLBOARD_INTENCLR0_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2351 
2352 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
2353   #define BELLBOARD_INTENCLR0_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
2354   #define BELLBOARD_INTENCLR0_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
2355   #define BELLBOARD_INTENCLR0_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
2356   #define BELLBOARD_INTENCLR0_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
2357   #define BELLBOARD_INTENCLR0_TRIGGERED1_Clear (0x1UL) /*!< Disable                                                            */
2358   #define BELLBOARD_INTENCLR0_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2359   #define BELLBOARD_INTENCLR0_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2360 
2361 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
2362   #define BELLBOARD_INTENCLR0_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
2363   #define BELLBOARD_INTENCLR0_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
2364   #define BELLBOARD_INTENCLR0_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
2365   #define BELLBOARD_INTENCLR0_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
2366   #define BELLBOARD_INTENCLR0_TRIGGERED2_Clear (0x1UL) /*!< Disable                                                            */
2367   #define BELLBOARD_INTENCLR0_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2368   #define BELLBOARD_INTENCLR0_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2369 
2370 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
2371   #define BELLBOARD_INTENCLR0_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
2372   #define BELLBOARD_INTENCLR0_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
2373   #define BELLBOARD_INTENCLR0_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
2374   #define BELLBOARD_INTENCLR0_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
2375   #define BELLBOARD_INTENCLR0_TRIGGERED3_Clear (0x1UL) /*!< Disable                                                            */
2376   #define BELLBOARD_INTENCLR0_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2377   #define BELLBOARD_INTENCLR0_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2378 
2379 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
2380   #define BELLBOARD_INTENCLR0_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
2381   #define BELLBOARD_INTENCLR0_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
2382   #define BELLBOARD_INTENCLR0_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
2383   #define BELLBOARD_INTENCLR0_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
2384   #define BELLBOARD_INTENCLR0_TRIGGERED4_Clear (0x1UL) /*!< Disable                                                            */
2385   #define BELLBOARD_INTENCLR0_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2386   #define BELLBOARD_INTENCLR0_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2387 
2388 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
2389   #define BELLBOARD_INTENCLR0_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
2390   #define BELLBOARD_INTENCLR0_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
2391   #define BELLBOARD_INTENCLR0_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
2392   #define BELLBOARD_INTENCLR0_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
2393   #define BELLBOARD_INTENCLR0_TRIGGERED5_Clear (0x1UL) /*!< Disable                                                            */
2394   #define BELLBOARD_INTENCLR0_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2395   #define BELLBOARD_INTENCLR0_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2396 
2397 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
2398   #define BELLBOARD_INTENCLR0_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
2399   #define BELLBOARD_INTENCLR0_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
2400   #define BELLBOARD_INTENCLR0_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
2401   #define BELLBOARD_INTENCLR0_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
2402   #define BELLBOARD_INTENCLR0_TRIGGERED6_Clear (0x1UL) /*!< Disable                                                            */
2403   #define BELLBOARD_INTENCLR0_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2404   #define BELLBOARD_INTENCLR0_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2405 
2406 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
2407   #define BELLBOARD_INTENCLR0_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
2408   #define BELLBOARD_INTENCLR0_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
2409   #define BELLBOARD_INTENCLR0_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
2410   #define BELLBOARD_INTENCLR0_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
2411   #define BELLBOARD_INTENCLR0_TRIGGERED7_Clear (0x1UL) /*!< Disable                                                            */
2412   #define BELLBOARD_INTENCLR0_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2413   #define BELLBOARD_INTENCLR0_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2414 
2415 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
2416   #define BELLBOARD_INTENCLR0_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
2417   #define BELLBOARD_INTENCLR0_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
2418   #define BELLBOARD_INTENCLR0_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
2419   #define BELLBOARD_INTENCLR0_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
2420   #define BELLBOARD_INTENCLR0_TRIGGERED8_Clear (0x1UL) /*!< Disable                                                            */
2421   #define BELLBOARD_INTENCLR0_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2422   #define BELLBOARD_INTENCLR0_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2423 
2424 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
2425   #define BELLBOARD_INTENCLR0_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
2426   #define BELLBOARD_INTENCLR0_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
2427   #define BELLBOARD_INTENCLR0_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
2428   #define BELLBOARD_INTENCLR0_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
2429   #define BELLBOARD_INTENCLR0_TRIGGERED9_Clear (0x1UL) /*!< Disable                                                            */
2430   #define BELLBOARD_INTENCLR0_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
2431   #define BELLBOARD_INTENCLR0_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
2432 
2433 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
2434   #define BELLBOARD_INTENCLR0_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
2435   #define BELLBOARD_INTENCLR0_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
2436                                                                             field.*/
2437   #define BELLBOARD_INTENCLR0_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
2438   #define BELLBOARD_INTENCLR0_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
2439   #define BELLBOARD_INTENCLR0_TRIGGERED10_Clear (0x1UL) /*!< Disable                                                           */
2440   #define BELLBOARD_INTENCLR0_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2441   #define BELLBOARD_INTENCLR0_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2442 
2443 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
2444   #define BELLBOARD_INTENCLR0_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
2445   #define BELLBOARD_INTENCLR0_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
2446                                                                             field.*/
2447   #define BELLBOARD_INTENCLR0_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
2448   #define BELLBOARD_INTENCLR0_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
2449   #define BELLBOARD_INTENCLR0_TRIGGERED11_Clear (0x1UL) /*!< Disable                                                           */
2450   #define BELLBOARD_INTENCLR0_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2451   #define BELLBOARD_INTENCLR0_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2452 
2453 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
2454   #define BELLBOARD_INTENCLR0_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
2455   #define BELLBOARD_INTENCLR0_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
2456                                                                             field.*/
2457   #define BELLBOARD_INTENCLR0_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
2458   #define BELLBOARD_INTENCLR0_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
2459   #define BELLBOARD_INTENCLR0_TRIGGERED12_Clear (0x1UL) /*!< Disable                                                           */
2460   #define BELLBOARD_INTENCLR0_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2461   #define BELLBOARD_INTENCLR0_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2462 
2463 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
2464   #define BELLBOARD_INTENCLR0_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
2465   #define BELLBOARD_INTENCLR0_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
2466                                                                             field.*/
2467   #define BELLBOARD_INTENCLR0_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
2468   #define BELLBOARD_INTENCLR0_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
2469   #define BELLBOARD_INTENCLR0_TRIGGERED13_Clear (0x1UL) /*!< Disable                                                           */
2470   #define BELLBOARD_INTENCLR0_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2471   #define BELLBOARD_INTENCLR0_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2472 
2473 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
2474   #define BELLBOARD_INTENCLR0_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
2475   #define BELLBOARD_INTENCLR0_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
2476                                                                             field.*/
2477   #define BELLBOARD_INTENCLR0_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
2478   #define BELLBOARD_INTENCLR0_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
2479   #define BELLBOARD_INTENCLR0_TRIGGERED14_Clear (0x1UL) /*!< Disable                                                           */
2480   #define BELLBOARD_INTENCLR0_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2481   #define BELLBOARD_INTENCLR0_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2482 
2483 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
2484   #define BELLBOARD_INTENCLR0_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
2485   #define BELLBOARD_INTENCLR0_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
2486                                                                             field.*/
2487   #define BELLBOARD_INTENCLR0_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
2488   #define BELLBOARD_INTENCLR0_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
2489   #define BELLBOARD_INTENCLR0_TRIGGERED15_Clear (0x1UL) /*!< Disable                                                           */
2490   #define BELLBOARD_INTENCLR0_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2491   #define BELLBOARD_INTENCLR0_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2492 
2493 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
2494   #define BELLBOARD_INTENCLR0_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
2495   #define BELLBOARD_INTENCLR0_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
2496                                                                             field.*/
2497   #define BELLBOARD_INTENCLR0_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
2498   #define BELLBOARD_INTENCLR0_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
2499   #define BELLBOARD_INTENCLR0_TRIGGERED16_Clear (0x1UL) /*!< Disable                                                           */
2500   #define BELLBOARD_INTENCLR0_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2501   #define BELLBOARD_INTENCLR0_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2502 
2503 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
2504   #define BELLBOARD_INTENCLR0_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
2505   #define BELLBOARD_INTENCLR0_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
2506                                                                             field.*/
2507   #define BELLBOARD_INTENCLR0_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
2508   #define BELLBOARD_INTENCLR0_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
2509   #define BELLBOARD_INTENCLR0_TRIGGERED17_Clear (0x1UL) /*!< Disable                                                           */
2510   #define BELLBOARD_INTENCLR0_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2511   #define BELLBOARD_INTENCLR0_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2512 
2513 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
2514   #define BELLBOARD_INTENCLR0_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
2515   #define BELLBOARD_INTENCLR0_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
2516                                                                             field.*/
2517   #define BELLBOARD_INTENCLR0_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
2518   #define BELLBOARD_INTENCLR0_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
2519   #define BELLBOARD_INTENCLR0_TRIGGERED18_Clear (0x1UL) /*!< Disable                                                           */
2520   #define BELLBOARD_INTENCLR0_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2521   #define BELLBOARD_INTENCLR0_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2522 
2523 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
2524   #define BELLBOARD_INTENCLR0_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
2525   #define BELLBOARD_INTENCLR0_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
2526                                                                             field.*/
2527   #define BELLBOARD_INTENCLR0_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
2528   #define BELLBOARD_INTENCLR0_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
2529   #define BELLBOARD_INTENCLR0_TRIGGERED19_Clear (0x1UL) /*!< Disable                                                           */
2530   #define BELLBOARD_INTENCLR0_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2531   #define BELLBOARD_INTENCLR0_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2532 
2533 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
2534   #define BELLBOARD_INTENCLR0_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
2535   #define BELLBOARD_INTENCLR0_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
2536                                                                             field.*/
2537   #define BELLBOARD_INTENCLR0_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
2538   #define BELLBOARD_INTENCLR0_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
2539   #define BELLBOARD_INTENCLR0_TRIGGERED20_Clear (0x1UL) /*!< Disable                                                           */
2540   #define BELLBOARD_INTENCLR0_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2541   #define BELLBOARD_INTENCLR0_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2542 
2543 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
2544   #define BELLBOARD_INTENCLR0_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
2545   #define BELLBOARD_INTENCLR0_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
2546                                                                             field.*/
2547   #define BELLBOARD_INTENCLR0_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
2548   #define BELLBOARD_INTENCLR0_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
2549   #define BELLBOARD_INTENCLR0_TRIGGERED21_Clear (0x1UL) /*!< Disable                                                           */
2550   #define BELLBOARD_INTENCLR0_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2551   #define BELLBOARD_INTENCLR0_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2552 
2553 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
2554   #define BELLBOARD_INTENCLR0_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
2555   #define BELLBOARD_INTENCLR0_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
2556                                                                             field.*/
2557   #define BELLBOARD_INTENCLR0_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
2558   #define BELLBOARD_INTENCLR0_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
2559   #define BELLBOARD_INTENCLR0_TRIGGERED22_Clear (0x1UL) /*!< Disable                                                           */
2560   #define BELLBOARD_INTENCLR0_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2561   #define BELLBOARD_INTENCLR0_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2562 
2563 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
2564   #define BELLBOARD_INTENCLR0_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
2565   #define BELLBOARD_INTENCLR0_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
2566                                                                             field.*/
2567   #define BELLBOARD_INTENCLR0_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
2568   #define BELLBOARD_INTENCLR0_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
2569   #define BELLBOARD_INTENCLR0_TRIGGERED23_Clear (0x1UL) /*!< Disable                                                           */
2570   #define BELLBOARD_INTENCLR0_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2571   #define BELLBOARD_INTENCLR0_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2572 
2573 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
2574   #define BELLBOARD_INTENCLR0_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
2575   #define BELLBOARD_INTENCLR0_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
2576                                                                             field.*/
2577   #define BELLBOARD_INTENCLR0_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
2578   #define BELLBOARD_INTENCLR0_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
2579   #define BELLBOARD_INTENCLR0_TRIGGERED24_Clear (0x1UL) /*!< Disable                                                           */
2580   #define BELLBOARD_INTENCLR0_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2581   #define BELLBOARD_INTENCLR0_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2582 
2583 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
2584   #define BELLBOARD_INTENCLR0_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
2585   #define BELLBOARD_INTENCLR0_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
2586                                                                             field.*/
2587   #define BELLBOARD_INTENCLR0_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
2588   #define BELLBOARD_INTENCLR0_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
2589   #define BELLBOARD_INTENCLR0_TRIGGERED25_Clear (0x1UL) /*!< Disable                                                           */
2590   #define BELLBOARD_INTENCLR0_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2591   #define BELLBOARD_INTENCLR0_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2592 
2593 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
2594   #define BELLBOARD_INTENCLR0_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
2595   #define BELLBOARD_INTENCLR0_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
2596                                                                             field.*/
2597   #define BELLBOARD_INTENCLR0_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
2598   #define BELLBOARD_INTENCLR0_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
2599   #define BELLBOARD_INTENCLR0_TRIGGERED26_Clear (0x1UL) /*!< Disable                                                           */
2600   #define BELLBOARD_INTENCLR0_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2601   #define BELLBOARD_INTENCLR0_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2602 
2603 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
2604   #define BELLBOARD_INTENCLR0_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
2605   #define BELLBOARD_INTENCLR0_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
2606                                                                             field.*/
2607   #define BELLBOARD_INTENCLR0_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
2608   #define BELLBOARD_INTENCLR0_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
2609   #define BELLBOARD_INTENCLR0_TRIGGERED27_Clear (0x1UL) /*!< Disable                                                           */
2610   #define BELLBOARD_INTENCLR0_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2611   #define BELLBOARD_INTENCLR0_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2612 
2613 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
2614   #define BELLBOARD_INTENCLR0_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
2615   #define BELLBOARD_INTENCLR0_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
2616                                                                             field.*/
2617   #define BELLBOARD_INTENCLR0_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
2618   #define BELLBOARD_INTENCLR0_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
2619   #define BELLBOARD_INTENCLR0_TRIGGERED28_Clear (0x1UL) /*!< Disable                                                           */
2620   #define BELLBOARD_INTENCLR0_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2621   #define BELLBOARD_INTENCLR0_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2622 
2623 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
2624   #define BELLBOARD_INTENCLR0_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
2625   #define BELLBOARD_INTENCLR0_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
2626                                                                             field.*/
2627   #define BELLBOARD_INTENCLR0_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
2628   #define BELLBOARD_INTENCLR0_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
2629   #define BELLBOARD_INTENCLR0_TRIGGERED29_Clear (0x1UL) /*!< Disable                                                           */
2630   #define BELLBOARD_INTENCLR0_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2631   #define BELLBOARD_INTENCLR0_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2632 
2633 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
2634   #define BELLBOARD_INTENCLR0_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
2635   #define BELLBOARD_INTENCLR0_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
2636                                                                             field.*/
2637   #define BELLBOARD_INTENCLR0_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
2638   #define BELLBOARD_INTENCLR0_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
2639   #define BELLBOARD_INTENCLR0_TRIGGERED30_Clear (0x1UL) /*!< Disable                                                           */
2640   #define BELLBOARD_INTENCLR0_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2641   #define BELLBOARD_INTENCLR0_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2642 
2643 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
2644   #define BELLBOARD_INTENCLR0_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
2645   #define BELLBOARD_INTENCLR0_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR0_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
2646                                                                             field.*/
2647   #define BELLBOARD_INTENCLR0_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
2648   #define BELLBOARD_INTENCLR0_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
2649   #define BELLBOARD_INTENCLR0_TRIGGERED31_Clear (0x1UL) /*!< Disable                                                           */
2650   #define BELLBOARD_INTENCLR0_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
2651   #define BELLBOARD_INTENCLR0_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
2652 
2653 
2654 /* BELLBOARD_INTPEND0: Pending interrupts */
2655   #define BELLBOARD_INTPEND0_ResetValue (0x00000000UL) /*!< Reset value of INTPEND0 register.                                  */
2656 
2657 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
2658   #define BELLBOARD_INTPEND0_TRIGGERED0_Pos (0UL)    /*!< Position of TRIGGERED0 field.                                        */
2659   #define BELLBOARD_INTPEND0_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.    */
2660   #define BELLBOARD_INTPEND0_TRIGGERED0_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED0 field.                            */
2661   #define BELLBOARD_INTPEND0_TRIGGERED0_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED0 field.                            */
2662   #define BELLBOARD_INTPEND0_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending                                              */
2663   #define BELLBOARD_INTPEND0_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending                                                     */
2664 
2665 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
2666   #define BELLBOARD_INTPEND0_TRIGGERED1_Pos (1UL)    /*!< Position of TRIGGERED1 field.                                        */
2667   #define BELLBOARD_INTPEND0_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.    */
2668   #define BELLBOARD_INTPEND0_TRIGGERED1_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED1 field.                            */
2669   #define BELLBOARD_INTPEND0_TRIGGERED1_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED1 field.                            */
2670   #define BELLBOARD_INTPEND0_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending                                              */
2671   #define BELLBOARD_INTPEND0_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending                                                     */
2672 
2673 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
2674   #define BELLBOARD_INTPEND0_TRIGGERED2_Pos (2UL)    /*!< Position of TRIGGERED2 field.                                        */
2675   #define BELLBOARD_INTPEND0_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.    */
2676   #define BELLBOARD_INTPEND0_TRIGGERED2_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED2 field.                            */
2677   #define BELLBOARD_INTPEND0_TRIGGERED2_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED2 field.                            */
2678   #define BELLBOARD_INTPEND0_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending                                              */
2679   #define BELLBOARD_INTPEND0_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending                                                     */
2680 
2681 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
2682   #define BELLBOARD_INTPEND0_TRIGGERED3_Pos (3UL)    /*!< Position of TRIGGERED3 field.                                        */
2683   #define BELLBOARD_INTPEND0_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.    */
2684   #define BELLBOARD_INTPEND0_TRIGGERED3_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED3 field.                            */
2685   #define BELLBOARD_INTPEND0_TRIGGERED3_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED3 field.                            */
2686   #define BELLBOARD_INTPEND0_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending                                              */
2687   #define BELLBOARD_INTPEND0_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending                                                     */
2688 
2689 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
2690   #define BELLBOARD_INTPEND0_TRIGGERED4_Pos (4UL)    /*!< Position of TRIGGERED4 field.                                        */
2691   #define BELLBOARD_INTPEND0_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.    */
2692   #define BELLBOARD_INTPEND0_TRIGGERED4_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED4 field.                            */
2693   #define BELLBOARD_INTPEND0_TRIGGERED4_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED4 field.                            */
2694   #define BELLBOARD_INTPEND0_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending                                              */
2695   #define BELLBOARD_INTPEND0_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending                                                     */
2696 
2697 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
2698   #define BELLBOARD_INTPEND0_TRIGGERED5_Pos (5UL)    /*!< Position of TRIGGERED5 field.                                        */
2699   #define BELLBOARD_INTPEND0_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.    */
2700   #define BELLBOARD_INTPEND0_TRIGGERED5_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED5 field.                            */
2701   #define BELLBOARD_INTPEND0_TRIGGERED5_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED5 field.                            */
2702   #define BELLBOARD_INTPEND0_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending                                              */
2703   #define BELLBOARD_INTPEND0_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending                                                     */
2704 
2705 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
2706   #define BELLBOARD_INTPEND0_TRIGGERED6_Pos (6UL)    /*!< Position of TRIGGERED6 field.                                        */
2707   #define BELLBOARD_INTPEND0_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.    */
2708   #define BELLBOARD_INTPEND0_TRIGGERED6_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED6 field.                            */
2709   #define BELLBOARD_INTPEND0_TRIGGERED6_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED6 field.                            */
2710   #define BELLBOARD_INTPEND0_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending                                              */
2711   #define BELLBOARD_INTPEND0_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending                                                     */
2712 
2713 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
2714   #define BELLBOARD_INTPEND0_TRIGGERED7_Pos (7UL)    /*!< Position of TRIGGERED7 field.                                        */
2715   #define BELLBOARD_INTPEND0_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.    */
2716   #define BELLBOARD_INTPEND0_TRIGGERED7_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED7 field.                            */
2717   #define BELLBOARD_INTPEND0_TRIGGERED7_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED7 field.                            */
2718   #define BELLBOARD_INTPEND0_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending                                              */
2719   #define BELLBOARD_INTPEND0_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending                                                     */
2720 
2721 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
2722   #define BELLBOARD_INTPEND0_TRIGGERED8_Pos (8UL)    /*!< Position of TRIGGERED8 field.                                        */
2723   #define BELLBOARD_INTPEND0_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.    */
2724   #define BELLBOARD_INTPEND0_TRIGGERED8_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED8 field.                            */
2725   #define BELLBOARD_INTPEND0_TRIGGERED8_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED8 field.                            */
2726   #define BELLBOARD_INTPEND0_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending                                              */
2727   #define BELLBOARD_INTPEND0_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending                                                     */
2728 
2729 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
2730   #define BELLBOARD_INTPEND0_TRIGGERED9_Pos (9UL)    /*!< Position of TRIGGERED9 field.                                        */
2731   #define BELLBOARD_INTPEND0_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.    */
2732   #define BELLBOARD_INTPEND0_TRIGGERED9_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED9 field.                            */
2733   #define BELLBOARD_INTPEND0_TRIGGERED9_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED9 field.                            */
2734   #define BELLBOARD_INTPEND0_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending                                              */
2735   #define BELLBOARD_INTPEND0_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending                                                     */
2736 
2737 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
2738   #define BELLBOARD_INTPEND0_TRIGGERED10_Pos (10UL)  /*!< Position of TRIGGERED10 field.                                       */
2739   #define BELLBOARD_INTPEND0_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
2740   #define BELLBOARD_INTPEND0_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                           */
2741   #define BELLBOARD_INTPEND0_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                           */
2742   #define BELLBOARD_INTPEND0_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                             */
2743   #define BELLBOARD_INTPEND0_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending                                                    */
2744 
2745 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
2746   #define BELLBOARD_INTPEND0_TRIGGERED11_Pos (11UL)  /*!< Position of TRIGGERED11 field.                                       */
2747   #define BELLBOARD_INTPEND0_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
2748   #define BELLBOARD_INTPEND0_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                           */
2749   #define BELLBOARD_INTPEND0_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                           */
2750   #define BELLBOARD_INTPEND0_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                             */
2751   #define BELLBOARD_INTPEND0_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending                                                    */
2752 
2753 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
2754   #define BELLBOARD_INTPEND0_TRIGGERED12_Pos (12UL)  /*!< Position of TRIGGERED12 field.                                       */
2755   #define BELLBOARD_INTPEND0_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
2756   #define BELLBOARD_INTPEND0_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                           */
2757   #define BELLBOARD_INTPEND0_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                           */
2758   #define BELLBOARD_INTPEND0_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                             */
2759   #define BELLBOARD_INTPEND0_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending                                                    */
2760 
2761 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
2762   #define BELLBOARD_INTPEND0_TRIGGERED13_Pos (13UL)  /*!< Position of TRIGGERED13 field.                                       */
2763   #define BELLBOARD_INTPEND0_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
2764   #define BELLBOARD_INTPEND0_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                           */
2765   #define BELLBOARD_INTPEND0_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                           */
2766   #define BELLBOARD_INTPEND0_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                             */
2767   #define BELLBOARD_INTPEND0_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending                                                    */
2768 
2769 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
2770   #define BELLBOARD_INTPEND0_TRIGGERED14_Pos (14UL)  /*!< Position of TRIGGERED14 field.                                       */
2771   #define BELLBOARD_INTPEND0_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
2772   #define BELLBOARD_INTPEND0_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                           */
2773   #define BELLBOARD_INTPEND0_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                           */
2774   #define BELLBOARD_INTPEND0_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                             */
2775   #define BELLBOARD_INTPEND0_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending                                                    */
2776 
2777 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
2778   #define BELLBOARD_INTPEND0_TRIGGERED15_Pos (15UL)  /*!< Position of TRIGGERED15 field.                                       */
2779   #define BELLBOARD_INTPEND0_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
2780   #define BELLBOARD_INTPEND0_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                           */
2781   #define BELLBOARD_INTPEND0_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                           */
2782   #define BELLBOARD_INTPEND0_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                             */
2783   #define BELLBOARD_INTPEND0_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending                                                    */
2784 
2785 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
2786   #define BELLBOARD_INTPEND0_TRIGGERED16_Pos (16UL)  /*!< Position of TRIGGERED16 field.                                       */
2787   #define BELLBOARD_INTPEND0_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */
2788   #define BELLBOARD_INTPEND0_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                           */
2789   #define BELLBOARD_INTPEND0_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                           */
2790   #define BELLBOARD_INTPEND0_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                             */
2791   #define BELLBOARD_INTPEND0_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending                                                    */
2792 
2793 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
2794   #define BELLBOARD_INTPEND0_TRIGGERED17_Pos (17UL)  /*!< Position of TRIGGERED17 field.                                       */
2795   #define BELLBOARD_INTPEND0_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */
2796   #define BELLBOARD_INTPEND0_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                           */
2797   #define BELLBOARD_INTPEND0_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                           */
2798   #define BELLBOARD_INTPEND0_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                             */
2799   #define BELLBOARD_INTPEND0_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending                                                    */
2800 
2801 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
2802   #define BELLBOARD_INTPEND0_TRIGGERED18_Pos (18UL)  /*!< Position of TRIGGERED18 field.                                       */
2803   #define BELLBOARD_INTPEND0_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */
2804   #define BELLBOARD_INTPEND0_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                           */
2805   #define BELLBOARD_INTPEND0_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                           */
2806   #define BELLBOARD_INTPEND0_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                             */
2807   #define BELLBOARD_INTPEND0_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending                                                    */
2808 
2809 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
2810   #define BELLBOARD_INTPEND0_TRIGGERED19_Pos (19UL)  /*!< Position of TRIGGERED19 field.                                       */
2811   #define BELLBOARD_INTPEND0_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */
2812   #define BELLBOARD_INTPEND0_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                           */
2813   #define BELLBOARD_INTPEND0_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                           */
2814   #define BELLBOARD_INTPEND0_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                             */
2815   #define BELLBOARD_INTPEND0_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending                                                    */
2816 
2817 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
2818   #define BELLBOARD_INTPEND0_TRIGGERED20_Pos (20UL)  /*!< Position of TRIGGERED20 field.                                       */
2819   #define BELLBOARD_INTPEND0_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */
2820   #define BELLBOARD_INTPEND0_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                           */
2821   #define BELLBOARD_INTPEND0_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                           */
2822   #define BELLBOARD_INTPEND0_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                             */
2823   #define BELLBOARD_INTPEND0_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending                                                    */
2824 
2825 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
2826   #define BELLBOARD_INTPEND0_TRIGGERED21_Pos (21UL)  /*!< Position of TRIGGERED21 field.                                       */
2827   #define BELLBOARD_INTPEND0_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */
2828   #define BELLBOARD_INTPEND0_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                           */
2829   #define BELLBOARD_INTPEND0_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                           */
2830   #define BELLBOARD_INTPEND0_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                             */
2831   #define BELLBOARD_INTPEND0_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending                                                    */
2832 
2833 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
2834   #define BELLBOARD_INTPEND0_TRIGGERED22_Pos (22UL)  /*!< Position of TRIGGERED22 field.                                       */
2835   #define BELLBOARD_INTPEND0_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */
2836   #define BELLBOARD_INTPEND0_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                           */
2837   #define BELLBOARD_INTPEND0_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                           */
2838   #define BELLBOARD_INTPEND0_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                             */
2839   #define BELLBOARD_INTPEND0_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending                                                    */
2840 
2841 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
2842   #define BELLBOARD_INTPEND0_TRIGGERED23_Pos (23UL)  /*!< Position of TRIGGERED23 field.                                       */
2843   #define BELLBOARD_INTPEND0_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */
2844   #define BELLBOARD_INTPEND0_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                           */
2845   #define BELLBOARD_INTPEND0_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                           */
2846   #define BELLBOARD_INTPEND0_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                             */
2847   #define BELLBOARD_INTPEND0_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending                                                    */
2848 
2849 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
2850   #define BELLBOARD_INTPEND0_TRIGGERED24_Pos (24UL)  /*!< Position of TRIGGERED24 field.                                       */
2851   #define BELLBOARD_INTPEND0_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */
2852   #define BELLBOARD_INTPEND0_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                           */
2853   #define BELLBOARD_INTPEND0_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                           */
2854   #define BELLBOARD_INTPEND0_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                             */
2855   #define BELLBOARD_INTPEND0_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending                                                    */
2856 
2857 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
2858   #define BELLBOARD_INTPEND0_TRIGGERED25_Pos (25UL)  /*!< Position of TRIGGERED25 field.                                       */
2859   #define BELLBOARD_INTPEND0_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */
2860   #define BELLBOARD_INTPEND0_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                           */
2861   #define BELLBOARD_INTPEND0_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                           */
2862   #define BELLBOARD_INTPEND0_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                             */
2863   #define BELLBOARD_INTPEND0_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending                                                    */
2864 
2865 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
2866   #define BELLBOARD_INTPEND0_TRIGGERED26_Pos (26UL)  /*!< Position of TRIGGERED26 field.                                       */
2867   #define BELLBOARD_INTPEND0_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */
2868   #define BELLBOARD_INTPEND0_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                           */
2869   #define BELLBOARD_INTPEND0_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                           */
2870   #define BELLBOARD_INTPEND0_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                             */
2871   #define BELLBOARD_INTPEND0_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending                                                    */
2872 
2873 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
2874   #define BELLBOARD_INTPEND0_TRIGGERED27_Pos (27UL)  /*!< Position of TRIGGERED27 field.                                       */
2875   #define BELLBOARD_INTPEND0_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */
2876   #define BELLBOARD_INTPEND0_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                           */
2877   #define BELLBOARD_INTPEND0_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                           */
2878   #define BELLBOARD_INTPEND0_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                             */
2879   #define BELLBOARD_INTPEND0_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending                                                    */
2880 
2881 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
2882   #define BELLBOARD_INTPEND0_TRIGGERED28_Pos (28UL)  /*!< Position of TRIGGERED28 field.                                       */
2883   #define BELLBOARD_INTPEND0_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */
2884   #define BELLBOARD_INTPEND0_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                           */
2885   #define BELLBOARD_INTPEND0_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                           */
2886   #define BELLBOARD_INTPEND0_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                             */
2887   #define BELLBOARD_INTPEND0_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending                                                    */
2888 
2889 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
2890   #define BELLBOARD_INTPEND0_TRIGGERED29_Pos (29UL)  /*!< Position of TRIGGERED29 field.                                       */
2891   #define BELLBOARD_INTPEND0_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */
2892   #define BELLBOARD_INTPEND0_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                           */
2893   #define BELLBOARD_INTPEND0_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                           */
2894   #define BELLBOARD_INTPEND0_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                             */
2895   #define BELLBOARD_INTPEND0_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending                                                    */
2896 
2897 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
2898   #define BELLBOARD_INTPEND0_TRIGGERED30_Pos (30UL)  /*!< Position of TRIGGERED30 field.                                       */
2899   #define BELLBOARD_INTPEND0_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */
2900   #define BELLBOARD_INTPEND0_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                           */
2901   #define BELLBOARD_INTPEND0_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                           */
2902   #define BELLBOARD_INTPEND0_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                             */
2903   #define BELLBOARD_INTPEND0_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending                                                    */
2904 
2905 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
2906   #define BELLBOARD_INTPEND0_TRIGGERED31_Pos (31UL)  /*!< Position of TRIGGERED31 field.                                       */
2907   #define BELLBOARD_INTPEND0_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND0_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */
2908   #define BELLBOARD_INTPEND0_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                           */
2909   #define BELLBOARD_INTPEND0_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                           */
2910   #define BELLBOARD_INTPEND0_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                             */
2911   #define BELLBOARD_INTPEND0_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending                                                    */
2912 
2913 
2914 /* BELLBOARD_INTEN1: Enable or disable interrupt */
2915   #define BELLBOARD_INTEN1_ResetValue (0x00000000UL) /*!< Reset value of INTEN1 register.                                      */
2916 
2917 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
2918   #define BELLBOARD_INTEN1_TRIGGERED0_Pos (0UL)      /*!< Position of TRIGGERED0 field.                                        */
2919   #define BELLBOARD_INTEN1_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.        */
2920   #define BELLBOARD_INTEN1_TRIGGERED0_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED0 field.                            */
2921   #define BELLBOARD_INTEN1_TRIGGERED0_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED0 field.                            */
2922   #define BELLBOARD_INTEN1_TRIGGERED0_Disabled (0x0UL) /*!< Disable                                                            */
2923   #define BELLBOARD_INTEN1_TRIGGERED0_Enabled (0x1UL) /*!< Enable                                                              */
2924 
2925 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
2926   #define BELLBOARD_INTEN1_TRIGGERED1_Pos (1UL)      /*!< Position of TRIGGERED1 field.                                        */
2927   #define BELLBOARD_INTEN1_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.        */
2928   #define BELLBOARD_INTEN1_TRIGGERED1_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED1 field.                            */
2929   #define BELLBOARD_INTEN1_TRIGGERED1_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED1 field.                            */
2930   #define BELLBOARD_INTEN1_TRIGGERED1_Disabled (0x0UL) /*!< Disable                                                            */
2931   #define BELLBOARD_INTEN1_TRIGGERED1_Enabled (0x1UL) /*!< Enable                                                              */
2932 
2933 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
2934   #define BELLBOARD_INTEN1_TRIGGERED2_Pos (2UL)      /*!< Position of TRIGGERED2 field.                                        */
2935   #define BELLBOARD_INTEN1_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.        */
2936   #define BELLBOARD_INTEN1_TRIGGERED2_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED2 field.                            */
2937   #define BELLBOARD_INTEN1_TRIGGERED2_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED2 field.                            */
2938   #define BELLBOARD_INTEN1_TRIGGERED2_Disabled (0x0UL) /*!< Disable                                                            */
2939   #define BELLBOARD_INTEN1_TRIGGERED2_Enabled (0x1UL) /*!< Enable                                                              */
2940 
2941 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
2942   #define BELLBOARD_INTEN1_TRIGGERED3_Pos (3UL)      /*!< Position of TRIGGERED3 field.                                        */
2943   #define BELLBOARD_INTEN1_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.        */
2944   #define BELLBOARD_INTEN1_TRIGGERED3_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED3 field.                            */
2945   #define BELLBOARD_INTEN1_TRIGGERED3_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED3 field.                            */
2946   #define BELLBOARD_INTEN1_TRIGGERED3_Disabled (0x0UL) /*!< Disable                                                            */
2947   #define BELLBOARD_INTEN1_TRIGGERED3_Enabled (0x1UL) /*!< Enable                                                              */
2948 
2949 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
2950   #define BELLBOARD_INTEN1_TRIGGERED4_Pos (4UL)      /*!< Position of TRIGGERED4 field.                                        */
2951   #define BELLBOARD_INTEN1_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.        */
2952   #define BELLBOARD_INTEN1_TRIGGERED4_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED4 field.                            */
2953   #define BELLBOARD_INTEN1_TRIGGERED4_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED4 field.                            */
2954   #define BELLBOARD_INTEN1_TRIGGERED4_Disabled (0x0UL) /*!< Disable                                                            */
2955   #define BELLBOARD_INTEN1_TRIGGERED4_Enabled (0x1UL) /*!< Enable                                                              */
2956 
2957 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
2958   #define BELLBOARD_INTEN1_TRIGGERED5_Pos (5UL)      /*!< Position of TRIGGERED5 field.                                        */
2959   #define BELLBOARD_INTEN1_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.        */
2960   #define BELLBOARD_INTEN1_TRIGGERED5_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED5 field.                            */
2961   #define BELLBOARD_INTEN1_TRIGGERED5_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED5 field.                            */
2962   #define BELLBOARD_INTEN1_TRIGGERED5_Disabled (0x0UL) /*!< Disable                                                            */
2963   #define BELLBOARD_INTEN1_TRIGGERED5_Enabled (0x1UL) /*!< Enable                                                              */
2964 
2965 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
2966   #define BELLBOARD_INTEN1_TRIGGERED6_Pos (6UL)      /*!< Position of TRIGGERED6 field.                                        */
2967   #define BELLBOARD_INTEN1_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.        */
2968   #define BELLBOARD_INTEN1_TRIGGERED6_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED6 field.                            */
2969   #define BELLBOARD_INTEN1_TRIGGERED6_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED6 field.                            */
2970   #define BELLBOARD_INTEN1_TRIGGERED6_Disabled (0x0UL) /*!< Disable                                                            */
2971   #define BELLBOARD_INTEN1_TRIGGERED6_Enabled (0x1UL) /*!< Enable                                                              */
2972 
2973 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
2974   #define BELLBOARD_INTEN1_TRIGGERED7_Pos (7UL)      /*!< Position of TRIGGERED7 field.                                        */
2975   #define BELLBOARD_INTEN1_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.        */
2976   #define BELLBOARD_INTEN1_TRIGGERED7_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED7 field.                            */
2977   #define BELLBOARD_INTEN1_TRIGGERED7_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED7 field.                            */
2978   #define BELLBOARD_INTEN1_TRIGGERED7_Disabled (0x0UL) /*!< Disable                                                            */
2979   #define BELLBOARD_INTEN1_TRIGGERED7_Enabled (0x1UL) /*!< Enable                                                              */
2980 
2981 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
2982   #define BELLBOARD_INTEN1_TRIGGERED8_Pos (8UL)      /*!< Position of TRIGGERED8 field.                                        */
2983   #define BELLBOARD_INTEN1_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.        */
2984   #define BELLBOARD_INTEN1_TRIGGERED8_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED8 field.                            */
2985   #define BELLBOARD_INTEN1_TRIGGERED8_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED8 field.                            */
2986   #define BELLBOARD_INTEN1_TRIGGERED8_Disabled (0x0UL) /*!< Disable                                                            */
2987   #define BELLBOARD_INTEN1_TRIGGERED8_Enabled (0x1UL) /*!< Enable                                                              */
2988 
2989 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
2990   #define BELLBOARD_INTEN1_TRIGGERED9_Pos (9UL)      /*!< Position of TRIGGERED9 field.                                        */
2991   #define BELLBOARD_INTEN1_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.        */
2992   #define BELLBOARD_INTEN1_TRIGGERED9_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED9 field.                            */
2993   #define BELLBOARD_INTEN1_TRIGGERED9_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED9 field.                            */
2994   #define BELLBOARD_INTEN1_TRIGGERED9_Disabled (0x0UL) /*!< Disable                                                            */
2995   #define BELLBOARD_INTEN1_TRIGGERED9_Enabled (0x1UL) /*!< Enable                                                              */
2996 
2997 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
2998   #define BELLBOARD_INTEN1_TRIGGERED10_Pos (10UL)    /*!< Position of TRIGGERED10 field.                                       */
2999   #define BELLBOARD_INTEN1_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.     */
3000   #define BELLBOARD_INTEN1_TRIGGERED10_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED10 field.                           */
3001   #define BELLBOARD_INTEN1_TRIGGERED10_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED10 field.                           */
3002   #define BELLBOARD_INTEN1_TRIGGERED10_Disabled (0x0UL) /*!< Disable                                                           */
3003   #define BELLBOARD_INTEN1_TRIGGERED10_Enabled (0x1UL) /*!< Enable                                                             */
3004 
3005 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
3006   #define BELLBOARD_INTEN1_TRIGGERED11_Pos (11UL)    /*!< Position of TRIGGERED11 field.                                       */
3007   #define BELLBOARD_INTEN1_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.     */
3008   #define BELLBOARD_INTEN1_TRIGGERED11_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED11 field.                           */
3009   #define BELLBOARD_INTEN1_TRIGGERED11_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED11 field.                           */
3010   #define BELLBOARD_INTEN1_TRIGGERED11_Disabled (0x0UL) /*!< Disable                                                           */
3011   #define BELLBOARD_INTEN1_TRIGGERED11_Enabled (0x1UL) /*!< Enable                                                             */
3012 
3013 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
3014   #define BELLBOARD_INTEN1_TRIGGERED12_Pos (12UL)    /*!< Position of TRIGGERED12 field.                                       */
3015   #define BELLBOARD_INTEN1_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.     */
3016   #define BELLBOARD_INTEN1_TRIGGERED12_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED12 field.                           */
3017   #define BELLBOARD_INTEN1_TRIGGERED12_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED12 field.                           */
3018   #define BELLBOARD_INTEN1_TRIGGERED12_Disabled (0x0UL) /*!< Disable                                                           */
3019   #define BELLBOARD_INTEN1_TRIGGERED12_Enabled (0x1UL) /*!< Enable                                                             */
3020 
3021 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
3022   #define BELLBOARD_INTEN1_TRIGGERED13_Pos (13UL)    /*!< Position of TRIGGERED13 field.                                       */
3023   #define BELLBOARD_INTEN1_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.     */
3024   #define BELLBOARD_INTEN1_TRIGGERED13_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED13 field.                           */
3025   #define BELLBOARD_INTEN1_TRIGGERED13_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED13 field.                           */
3026   #define BELLBOARD_INTEN1_TRIGGERED13_Disabled (0x0UL) /*!< Disable                                                           */
3027   #define BELLBOARD_INTEN1_TRIGGERED13_Enabled (0x1UL) /*!< Enable                                                             */
3028 
3029 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
3030   #define BELLBOARD_INTEN1_TRIGGERED14_Pos (14UL)    /*!< Position of TRIGGERED14 field.                                       */
3031   #define BELLBOARD_INTEN1_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.     */
3032   #define BELLBOARD_INTEN1_TRIGGERED14_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED14 field.                           */
3033   #define BELLBOARD_INTEN1_TRIGGERED14_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED14 field.                           */
3034   #define BELLBOARD_INTEN1_TRIGGERED14_Disabled (0x0UL) /*!< Disable                                                           */
3035   #define BELLBOARD_INTEN1_TRIGGERED14_Enabled (0x1UL) /*!< Enable                                                             */
3036 
3037 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
3038   #define BELLBOARD_INTEN1_TRIGGERED15_Pos (15UL)    /*!< Position of TRIGGERED15 field.                                       */
3039   #define BELLBOARD_INTEN1_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.     */
3040   #define BELLBOARD_INTEN1_TRIGGERED15_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED15 field.                           */
3041   #define BELLBOARD_INTEN1_TRIGGERED15_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED15 field.                           */
3042   #define BELLBOARD_INTEN1_TRIGGERED15_Disabled (0x0UL) /*!< Disable                                                           */
3043   #define BELLBOARD_INTEN1_TRIGGERED15_Enabled (0x1UL) /*!< Enable                                                             */
3044 
3045 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
3046   #define BELLBOARD_INTEN1_TRIGGERED16_Pos (16UL)    /*!< Position of TRIGGERED16 field.                                       */
3047   #define BELLBOARD_INTEN1_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.     */
3048   #define BELLBOARD_INTEN1_TRIGGERED16_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED16 field.                           */
3049   #define BELLBOARD_INTEN1_TRIGGERED16_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED16 field.                           */
3050   #define BELLBOARD_INTEN1_TRIGGERED16_Disabled (0x0UL) /*!< Disable                                                           */
3051   #define BELLBOARD_INTEN1_TRIGGERED16_Enabled (0x1UL) /*!< Enable                                                             */
3052 
3053 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
3054   #define BELLBOARD_INTEN1_TRIGGERED17_Pos (17UL)    /*!< Position of TRIGGERED17 field.                                       */
3055   #define BELLBOARD_INTEN1_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.     */
3056   #define BELLBOARD_INTEN1_TRIGGERED17_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED17 field.                           */
3057   #define BELLBOARD_INTEN1_TRIGGERED17_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED17 field.                           */
3058   #define BELLBOARD_INTEN1_TRIGGERED17_Disabled (0x0UL) /*!< Disable                                                           */
3059   #define BELLBOARD_INTEN1_TRIGGERED17_Enabled (0x1UL) /*!< Enable                                                             */
3060 
3061 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
3062   #define BELLBOARD_INTEN1_TRIGGERED18_Pos (18UL)    /*!< Position of TRIGGERED18 field.                                       */
3063   #define BELLBOARD_INTEN1_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.     */
3064   #define BELLBOARD_INTEN1_TRIGGERED18_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED18 field.                           */
3065   #define BELLBOARD_INTEN1_TRIGGERED18_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED18 field.                           */
3066   #define BELLBOARD_INTEN1_TRIGGERED18_Disabled (0x0UL) /*!< Disable                                                           */
3067   #define BELLBOARD_INTEN1_TRIGGERED18_Enabled (0x1UL) /*!< Enable                                                             */
3068 
3069 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
3070   #define BELLBOARD_INTEN1_TRIGGERED19_Pos (19UL)    /*!< Position of TRIGGERED19 field.                                       */
3071   #define BELLBOARD_INTEN1_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.     */
3072   #define BELLBOARD_INTEN1_TRIGGERED19_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED19 field.                           */
3073   #define BELLBOARD_INTEN1_TRIGGERED19_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED19 field.                           */
3074   #define BELLBOARD_INTEN1_TRIGGERED19_Disabled (0x0UL) /*!< Disable                                                           */
3075   #define BELLBOARD_INTEN1_TRIGGERED19_Enabled (0x1UL) /*!< Enable                                                             */
3076 
3077 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
3078   #define BELLBOARD_INTEN1_TRIGGERED20_Pos (20UL)    /*!< Position of TRIGGERED20 field.                                       */
3079   #define BELLBOARD_INTEN1_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.     */
3080   #define BELLBOARD_INTEN1_TRIGGERED20_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED20 field.                           */
3081   #define BELLBOARD_INTEN1_TRIGGERED20_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED20 field.                           */
3082   #define BELLBOARD_INTEN1_TRIGGERED20_Disabled (0x0UL) /*!< Disable                                                           */
3083   #define BELLBOARD_INTEN1_TRIGGERED20_Enabled (0x1UL) /*!< Enable                                                             */
3084 
3085 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
3086   #define BELLBOARD_INTEN1_TRIGGERED21_Pos (21UL)    /*!< Position of TRIGGERED21 field.                                       */
3087   #define BELLBOARD_INTEN1_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.     */
3088   #define BELLBOARD_INTEN1_TRIGGERED21_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED21 field.                           */
3089   #define BELLBOARD_INTEN1_TRIGGERED21_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED21 field.                           */
3090   #define BELLBOARD_INTEN1_TRIGGERED21_Disabled (0x0UL) /*!< Disable                                                           */
3091   #define BELLBOARD_INTEN1_TRIGGERED21_Enabled (0x1UL) /*!< Enable                                                             */
3092 
3093 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
3094   #define BELLBOARD_INTEN1_TRIGGERED22_Pos (22UL)    /*!< Position of TRIGGERED22 field.                                       */
3095   #define BELLBOARD_INTEN1_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.     */
3096   #define BELLBOARD_INTEN1_TRIGGERED22_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED22 field.                           */
3097   #define BELLBOARD_INTEN1_TRIGGERED22_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED22 field.                           */
3098   #define BELLBOARD_INTEN1_TRIGGERED22_Disabled (0x0UL) /*!< Disable                                                           */
3099   #define BELLBOARD_INTEN1_TRIGGERED22_Enabled (0x1UL) /*!< Enable                                                             */
3100 
3101 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
3102   #define BELLBOARD_INTEN1_TRIGGERED23_Pos (23UL)    /*!< Position of TRIGGERED23 field.                                       */
3103   #define BELLBOARD_INTEN1_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.     */
3104   #define BELLBOARD_INTEN1_TRIGGERED23_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED23 field.                           */
3105   #define BELLBOARD_INTEN1_TRIGGERED23_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED23 field.                           */
3106   #define BELLBOARD_INTEN1_TRIGGERED23_Disabled (0x0UL) /*!< Disable                                                           */
3107   #define BELLBOARD_INTEN1_TRIGGERED23_Enabled (0x1UL) /*!< Enable                                                             */
3108 
3109 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
3110   #define BELLBOARD_INTEN1_TRIGGERED24_Pos (24UL)    /*!< Position of TRIGGERED24 field.                                       */
3111   #define BELLBOARD_INTEN1_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.     */
3112   #define BELLBOARD_INTEN1_TRIGGERED24_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED24 field.                           */
3113   #define BELLBOARD_INTEN1_TRIGGERED24_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED24 field.                           */
3114   #define BELLBOARD_INTEN1_TRIGGERED24_Disabled (0x0UL) /*!< Disable                                                           */
3115   #define BELLBOARD_INTEN1_TRIGGERED24_Enabled (0x1UL) /*!< Enable                                                             */
3116 
3117 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
3118   #define BELLBOARD_INTEN1_TRIGGERED25_Pos (25UL)    /*!< Position of TRIGGERED25 field.                                       */
3119   #define BELLBOARD_INTEN1_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.     */
3120   #define BELLBOARD_INTEN1_TRIGGERED25_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED25 field.                           */
3121   #define BELLBOARD_INTEN1_TRIGGERED25_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED25 field.                           */
3122   #define BELLBOARD_INTEN1_TRIGGERED25_Disabled (0x0UL) /*!< Disable                                                           */
3123   #define BELLBOARD_INTEN1_TRIGGERED25_Enabled (0x1UL) /*!< Enable                                                             */
3124 
3125 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
3126   #define BELLBOARD_INTEN1_TRIGGERED26_Pos (26UL)    /*!< Position of TRIGGERED26 field.                                       */
3127   #define BELLBOARD_INTEN1_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.     */
3128   #define BELLBOARD_INTEN1_TRIGGERED26_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED26 field.                           */
3129   #define BELLBOARD_INTEN1_TRIGGERED26_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED26 field.                           */
3130   #define BELLBOARD_INTEN1_TRIGGERED26_Disabled (0x0UL) /*!< Disable                                                           */
3131   #define BELLBOARD_INTEN1_TRIGGERED26_Enabled (0x1UL) /*!< Enable                                                             */
3132 
3133 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
3134   #define BELLBOARD_INTEN1_TRIGGERED27_Pos (27UL)    /*!< Position of TRIGGERED27 field.                                       */
3135   #define BELLBOARD_INTEN1_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.     */
3136   #define BELLBOARD_INTEN1_TRIGGERED27_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED27 field.                           */
3137   #define BELLBOARD_INTEN1_TRIGGERED27_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED27 field.                           */
3138   #define BELLBOARD_INTEN1_TRIGGERED27_Disabled (0x0UL) /*!< Disable                                                           */
3139   #define BELLBOARD_INTEN1_TRIGGERED27_Enabled (0x1UL) /*!< Enable                                                             */
3140 
3141 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
3142   #define BELLBOARD_INTEN1_TRIGGERED28_Pos (28UL)    /*!< Position of TRIGGERED28 field.                                       */
3143   #define BELLBOARD_INTEN1_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.     */
3144   #define BELLBOARD_INTEN1_TRIGGERED28_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED28 field.                           */
3145   #define BELLBOARD_INTEN1_TRIGGERED28_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED28 field.                           */
3146   #define BELLBOARD_INTEN1_TRIGGERED28_Disabled (0x0UL) /*!< Disable                                                           */
3147   #define BELLBOARD_INTEN1_TRIGGERED28_Enabled (0x1UL) /*!< Enable                                                             */
3148 
3149 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
3150   #define BELLBOARD_INTEN1_TRIGGERED29_Pos (29UL)    /*!< Position of TRIGGERED29 field.                                       */
3151   #define BELLBOARD_INTEN1_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.     */
3152   #define BELLBOARD_INTEN1_TRIGGERED29_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED29 field.                           */
3153   #define BELLBOARD_INTEN1_TRIGGERED29_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED29 field.                           */
3154   #define BELLBOARD_INTEN1_TRIGGERED29_Disabled (0x0UL) /*!< Disable                                                           */
3155   #define BELLBOARD_INTEN1_TRIGGERED29_Enabled (0x1UL) /*!< Enable                                                             */
3156 
3157 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
3158   #define BELLBOARD_INTEN1_TRIGGERED30_Pos (30UL)    /*!< Position of TRIGGERED30 field.                                       */
3159   #define BELLBOARD_INTEN1_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.     */
3160   #define BELLBOARD_INTEN1_TRIGGERED30_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED30 field.                           */
3161   #define BELLBOARD_INTEN1_TRIGGERED30_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED30 field.                           */
3162   #define BELLBOARD_INTEN1_TRIGGERED30_Disabled (0x0UL) /*!< Disable                                                           */
3163   #define BELLBOARD_INTEN1_TRIGGERED30_Enabled (0x1UL) /*!< Enable                                                             */
3164 
3165 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
3166   #define BELLBOARD_INTEN1_TRIGGERED31_Pos (31UL)    /*!< Position of TRIGGERED31 field.                                       */
3167   #define BELLBOARD_INTEN1_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN1_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.     */
3168   #define BELLBOARD_INTEN1_TRIGGERED31_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED31 field.                           */
3169   #define BELLBOARD_INTEN1_TRIGGERED31_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED31 field.                           */
3170   #define BELLBOARD_INTEN1_TRIGGERED31_Disabled (0x0UL) /*!< Disable                                                           */
3171   #define BELLBOARD_INTEN1_TRIGGERED31_Enabled (0x1UL) /*!< Enable                                                             */
3172 
3173 
3174 /* BELLBOARD_INTENSET1: Enable interrupt */
3175   #define BELLBOARD_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register.                                */
3176 
3177 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
3178   #define BELLBOARD_INTENSET1_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
3179   #define BELLBOARD_INTENSET1_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
3180   #define BELLBOARD_INTENSET1_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
3181   #define BELLBOARD_INTENSET1_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
3182   #define BELLBOARD_INTENSET1_TRIGGERED0_Set (0x1UL) /*!< Enable                                                               */
3183   #define BELLBOARD_INTENSET1_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3184   #define BELLBOARD_INTENSET1_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3185 
3186 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
3187   #define BELLBOARD_INTENSET1_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
3188   #define BELLBOARD_INTENSET1_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
3189   #define BELLBOARD_INTENSET1_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
3190   #define BELLBOARD_INTENSET1_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
3191   #define BELLBOARD_INTENSET1_TRIGGERED1_Set (0x1UL) /*!< Enable                                                               */
3192   #define BELLBOARD_INTENSET1_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3193   #define BELLBOARD_INTENSET1_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3194 
3195 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
3196   #define BELLBOARD_INTENSET1_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
3197   #define BELLBOARD_INTENSET1_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
3198   #define BELLBOARD_INTENSET1_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
3199   #define BELLBOARD_INTENSET1_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
3200   #define BELLBOARD_INTENSET1_TRIGGERED2_Set (0x1UL) /*!< Enable                                                               */
3201   #define BELLBOARD_INTENSET1_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3202   #define BELLBOARD_INTENSET1_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3203 
3204 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
3205   #define BELLBOARD_INTENSET1_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
3206   #define BELLBOARD_INTENSET1_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
3207   #define BELLBOARD_INTENSET1_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
3208   #define BELLBOARD_INTENSET1_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
3209   #define BELLBOARD_INTENSET1_TRIGGERED3_Set (0x1UL) /*!< Enable                                                               */
3210   #define BELLBOARD_INTENSET1_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3211   #define BELLBOARD_INTENSET1_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3212 
3213 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
3214   #define BELLBOARD_INTENSET1_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
3215   #define BELLBOARD_INTENSET1_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
3216   #define BELLBOARD_INTENSET1_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
3217   #define BELLBOARD_INTENSET1_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
3218   #define BELLBOARD_INTENSET1_TRIGGERED4_Set (0x1UL) /*!< Enable                                                               */
3219   #define BELLBOARD_INTENSET1_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3220   #define BELLBOARD_INTENSET1_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3221 
3222 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
3223   #define BELLBOARD_INTENSET1_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
3224   #define BELLBOARD_INTENSET1_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
3225   #define BELLBOARD_INTENSET1_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
3226   #define BELLBOARD_INTENSET1_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
3227   #define BELLBOARD_INTENSET1_TRIGGERED5_Set (0x1UL) /*!< Enable                                                               */
3228   #define BELLBOARD_INTENSET1_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3229   #define BELLBOARD_INTENSET1_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3230 
3231 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
3232   #define BELLBOARD_INTENSET1_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
3233   #define BELLBOARD_INTENSET1_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
3234   #define BELLBOARD_INTENSET1_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
3235   #define BELLBOARD_INTENSET1_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
3236   #define BELLBOARD_INTENSET1_TRIGGERED6_Set (0x1UL) /*!< Enable                                                               */
3237   #define BELLBOARD_INTENSET1_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3238   #define BELLBOARD_INTENSET1_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3239 
3240 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
3241   #define BELLBOARD_INTENSET1_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
3242   #define BELLBOARD_INTENSET1_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
3243   #define BELLBOARD_INTENSET1_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
3244   #define BELLBOARD_INTENSET1_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
3245   #define BELLBOARD_INTENSET1_TRIGGERED7_Set (0x1UL) /*!< Enable                                                               */
3246   #define BELLBOARD_INTENSET1_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3247   #define BELLBOARD_INTENSET1_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3248 
3249 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
3250   #define BELLBOARD_INTENSET1_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
3251   #define BELLBOARD_INTENSET1_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
3252   #define BELLBOARD_INTENSET1_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
3253   #define BELLBOARD_INTENSET1_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
3254   #define BELLBOARD_INTENSET1_TRIGGERED8_Set (0x1UL) /*!< Enable                                                               */
3255   #define BELLBOARD_INTENSET1_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3256   #define BELLBOARD_INTENSET1_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3257 
3258 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
3259   #define BELLBOARD_INTENSET1_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
3260   #define BELLBOARD_INTENSET1_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
3261   #define BELLBOARD_INTENSET1_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
3262   #define BELLBOARD_INTENSET1_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
3263   #define BELLBOARD_INTENSET1_TRIGGERED9_Set (0x1UL) /*!< Enable                                                               */
3264   #define BELLBOARD_INTENSET1_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3265   #define BELLBOARD_INTENSET1_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3266 
3267 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
3268   #define BELLBOARD_INTENSET1_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
3269   #define BELLBOARD_INTENSET1_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
3270                                                                             field.*/
3271   #define BELLBOARD_INTENSET1_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
3272   #define BELLBOARD_INTENSET1_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
3273   #define BELLBOARD_INTENSET1_TRIGGERED10_Set (0x1UL) /*!< Enable                                                              */
3274   #define BELLBOARD_INTENSET1_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3275   #define BELLBOARD_INTENSET1_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3276 
3277 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
3278   #define BELLBOARD_INTENSET1_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
3279   #define BELLBOARD_INTENSET1_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
3280                                                                             field.*/
3281   #define BELLBOARD_INTENSET1_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
3282   #define BELLBOARD_INTENSET1_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
3283   #define BELLBOARD_INTENSET1_TRIGGERED11_Set (0x1UL) /*!< Enable                                                              */
3284   #define BELLBOARD_INTENSET1_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3285   #define BELLBOARD_INTENSET1_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3286 
3287 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
3288   #define BELLBOARD_INTENSET1_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
3289   #define BELLBOARD_INTENSET1_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
3290                                                                             field.*/
3291   #define BELLBOARD_INTENSET1_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
3292   #define BELLBOARD_INTENSET1_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
3293   #define BELLBOARD_INTENSET1_TRIGGERED12_Set (0x1UL) /*!< Enable                                                              */
3294   #define BELLBOARD_INTENSET1_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3295   #define BELLBOARD_INTENSET1_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3296 
3297 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
3298   #define BELLBOARD_INTENSET1_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
3299   #define BELLBOARD_INTENSET1_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
3300                                                                             field.*/
3301   #define BELLBOARD_INTENSET1_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
3302   #define BELLBOARD_INTENSET1_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
3303   #define BELLBOARD_INTENSET1_TRIGGERED13_Set (0x1UL) /*!< Enable                                                              */
3304   #define BELLBOARD_INTENSET1_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3305   #define BELLBOARD_INTENSET1_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3306 
3307 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
3308   #define BELLBOARD_INTENSET1_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
3309   #define BELLBOARD_INTENSET1_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
3310                                                                             field.*/
3311   #define BELLBOARD_INTENSET1_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
3312   #define BELLBOARD_INTENSET1_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
3313   #define BELLBOARD_INTENSET1_TRIGGERED14_Set (0x1UL) /*!< Enable                                                              */
3314   #define BELLBOARD_INTENSET1_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3315   #define BELLBOARD_INTENSET1_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3316 
3317 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
3318   #define BELLBOARD_INTENSET1_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
3319   #define BELLBOARD_INTENSET1_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
3320                                                                             field.*/
3321   #define BELLBOARD_INTENSET1_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
3322   #define BELLBOARD_INTENSET1_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
3323   #define BELLBOARD_INTENSET1_TRIGGERED15_Set (0x1UL) /*!< Enable                                                              */
3324   #define BELLBOARD_INTENSET1_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3325   #define BELLBOARD_INTENSET1_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3326 
3327 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
3328   #define BELLBOARD_INTENSET1_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
3329   #define BELLBOARD_INTENSET1_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
3330                                                                             field.*/
3331   #define BELLBOARD_INTENSET1_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
3332   #define BELLBOARD_INTENSET1_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
3333   #define BELLBOARD_INTENSET1_TRIGGERED16_Set (0x1UL) /*!< Enable                                                              */
3334   #define BELLBOARD_INTENSET1_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3335   #define BELLBOARD_INTENSET1_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3336 
3337 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
3338   #define BELLBOARD_INTENSET1_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
3339   #define BELLBOARD_INTENSET1_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
3340                                                                             field.*/
3341   #define BELLBOARD_INTENSET1_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
3342   #define BELLBOARD_INTENSET1_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
3343   #define BELLBOARD_INTENSET1_TRIGGERED17_Set (0x1UL) /*!< Enable                                                              */
3344   #define BELLBOARD_INTENSET1_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3345   #define BELLBOARD_INTENSET1_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3346 
3347 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
3348   #define BELLBOARD_INTENSET1_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
3349   #define BELLBOARD_INTENSET1_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
3350                                                                             field.*/
3351   #define BELLBOARD_INTENSET1_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
3352   #define BELLBOARD_INTENSET1_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
3353   #define BELLBOARD_INTENSET1_TRIGGERED18_Set (0x1UL) /*!< Enable                                                              */
3354   #define BELLBOARD_INTENSET1_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3355   #define BELLBOARD_INTENSET1_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3356 
3357 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
3358   #define BELLBOARD_INTENSET1_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
3359   #define BELLBOARD_INTENSET1_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
3360                                                                             field.*/
3361   #define BELLBOARD_INTENSET1_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
3362   #define BELLBOARD_INTENSET1_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
3363   #define BELLBOARD_INTENSET1_TRIGGERED19_Set (0x1UL) /*!< Enable                                                              */
3364   #define BELLBOARD_INTENSET1_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3365   #define BELLBOARD_INTENSET1_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3366 
3367 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
3368   #define BELLBOARD_INTENSET1_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
3369   #define BELLBOARD_INTENSET1_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
3370                                                                             field.*/
3371   #define BELLBOARD_INTENSET1_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
3372   #define BELLBOARD_INTENSET1_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
3373   #define BELLBOARD_INTENSET1_TRIGGERED20_Set (0x1UL) /*!< Enable                                                              */
3374   #define BELLBOARD_INTENSET1_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3375   #define BELLBOARD_INTENSET1_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3376 
3377 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
3378   #define BELLBOARD_INTENSET1_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
3379   #define BELLBOARD_INTENSET1_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
3380                                                                             field.*/
3381   #define BELLBOARD_INTENSET1_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
3382   #define BELLBOARD_INTENSET1_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
3383   #define BELLBOARD_INTENSET1_TRIGGERED21_Set (0x1UL) /*!< Enable                                                              */
3384   #define BELLBOARD_INTENSET1_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3385   #define BELLBOARD_INTENSET1_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3386 
3387 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
3388   #define BELLBOARD_INTENSET1_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
3389   #define BELLBOARD_INTENSET1_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
3390                                                                             field.*/
3391   #define BELLBOARD_INTENSET1_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
3392   #define BELLBOARD_INTENSET1_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
3393   #define BELLBOARD_INTENSET1_TRIGGERED22_Set (0x1UL) /*!< Enable                                                              */
3394   #define BELLBOARD_INTENSET1_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3395   #define BELLBOARD_INTENSET1_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3396 
3397 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
3398   #define BELLBOARD_INTENSET1_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
3399   #define BELLBOARD_INTENSET1_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
3400                                                                             field.*/
3401   #define BELLBOARD_INTENSET1_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
3402   #define BELLBOARD_INTENSET1_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
3403   #define BELLBOARD_INTENSET1_TRIGGERED23_Set (0x1UL) /*!< Enable                                                              */
3404   #define BELLBOARD_INTENSET1_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3405   #define BELLBOARD_INTENSET1_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3406 
3407 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
3408   #define BELLBOARD_INTENSET1_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
3409   #define BELLBOARD_INTENSET1_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
3410                                                                             field.*/
3411   #define BELLBOARD_INTENSET1_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
3412   #define BELLBOARD_INTENSET1_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
3413   #define BELLBOARD_INTENSET1_TRIGGERED24_Set (0x1UL) /*!< Enable                                                              */
3414   #define BELLBOARD_INTENSET1_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3415   #define BELLBOARD_INTENSET1_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3416 
3417 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
3418   #define BELLBOARD_INTENSET1_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
3419   #define BELLBOARD_INTENSET1_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
3420                                                                             field.*/
3421   #define BELLBOARD_INTENSET1_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
3422   #define BELLBOARD_INTENSET1_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
3423   #define BELLBOARD_INTENSET1_TRIGGERED25_Set (0x1UL) /*!< Enable                                                              */
3424   #define BELLBOARD_INTENSET1_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3425   #define BELLBOARD_INTENSET1_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3426 
3427 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
3428   #define BELLBOARD_INTENSET1_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
3429   #define BELLBOARD_INTENSET1_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
3430                                                                             field.*/
3431   #define BELLBOARD_INTENSET1_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
3432   #define BELLBOARD_INTENSET1_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
3433   #define BELLBOARD_INTENSET1_TRIGGERED26_Set (0x1UL) /*!< Enable                                                              */
3434   #define BELLBOARD_INTENSET1_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3435   #define BELLBOARD_INTENSET1_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3436 
3437 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
3438   #define BELLBOARD_INTENSET1_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
3439   #define BELLBOARD_INTENSET1_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
3440                                                                             field.*/
3441   #define BELLBOARD_INTENSET1_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
3442   #define BELLBOARD_INTENSET1_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
3443   #define BELLBOARD_INTENSET1_TRIGGERED27_Set (0x1UL) /*!< Enable                                                              */
3444   #define BELLBOARD_INTENSET1_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3445   #define BELLBOARD_INTENSET1_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3446 
3447 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
3448   #define BELLBOARD_INTENSET1_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
3449   #define BELLBOARD_INTENSET1_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
3450                                                                             field.*/
3451   #define BELLBOARD_INTENSET1_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
3452   #define BELLBOARD_INTENSET1_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
3453   #define BELLBOARD_INTENSET1_TRIGGERED28_Set (0x1UL) /*!< Enable                                                              */
3454   #define BELLBOARD_INTENSET1_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3455   #define BELLBOARD_INTENSET1_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3456 
3457 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
3458   #define BELLBOARD_INTENSET1_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
3459   #define BELLBOARD_INTENSET1_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
3460                                                                             field.*/
3461   #define BELLBOARD_INTENSET1_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
3462   #define BELLBOARD_INTENSET1_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
3463   #define BELLBOARD_INTENSET1_TRIGGERED29_Set (0x1UL) /*!< Enable                                                              */
3464   #define BELLBOARD_INTENSET1_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3465   #define BELLBOARD_INTENSET1_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3466 
3467 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
3468   #define BELLBOARD_INTENSET1_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
3469   #define BELLBOARD_INTENSET1_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
3470                                                                             field.*/
3471   #define BELLBOARD_INTENSET1_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
3472   #define BELLBOARD_INTENSET1_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
3473   #define BELLBOARD_INTENSET1_TRIGGERED30_Set (0x1UL) /*!< Enable                                                              */
3474   #define BELLBOARD_INTENSET1_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3475   #define BELLBOARD_INTENSET1_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3476 
3477 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
3478   #define BELLBOARD_INTENSET1_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
3479   #define BELLBOARD_INTENSET1_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET1_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
3480                                                                             field.*/
3481   #define BELLBOARD_INTENSET1_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
3482   #define BELLBOARD_INTENSET1_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
3483   #define BELLBOARD_INTENSET1_TRIGGERED31_Set (0x1UL) /*!< Enable                                                              */
3484   #define BELLBOARD_INTENSET1_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3485   #define BELLBOARD_INTENSET1_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3486 
3487 
3488 /* BELLBOARD_INTENCLR1: Disable interrupt */
3489   #define BELLBOARD_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register.                                */
3490 
3491 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
3492   #define BELLBOARD_INTENCLR1_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
3493   #define BELLBOARD_INTENCLR1_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
3494   #define BELLBOARD_INTENCLR1_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
3495   #define BELLBOARD_INTENCLR1_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
3496   #define BELLBOARD_INTENCLR1_TRIGGERED0_Clear (0x1UL) /*!< Disable                                                            */
3497   #define BELLBOARD_INTENCLR1_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3498   #define BELLBOARD_INTENCLR1_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3499 
3500 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
3501   #define BELLBOARD_INTENCLR1_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
3502   #define BELLBOARD_INTENCLR1_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
3503   #define BELLBOARD_INTENCLR1_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
3504   #define BELLBOARD_INTENCLR1_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
3505   #define BELLBOARD_INTENCLR1_TRIGGERED1_Clear (0x1UL) /*!< Disable                                                            */
3506   #define BELLBOARD_INTENCLR1_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3507   #define BELLBOARD_INTENCLR1_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3508 
3509 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
3510   #define BELLBOARD_INTENCLR1_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
3511   #define BELLBOARD_INTENCLR1_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
3512   #define BELLBOARD_INTENCLR1_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
3513   #define BELLBOARD_INTENCLR1_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
3514   #define BELLBOARD_INTENCLR1_TRIGGERED2_Clear (0x1UL) /*!< Disable                                                            */
3515   #define BELLBOARD_INTENCLR1_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3516   #define BELLBOARD_INTENCLR1_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3517 
3518 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
3519   #define BELLBOARD_INTENCLR1_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
3520   #define BELLBOARD_INTENCLR1_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
3521   #define BELLBOARD_INTENCLR1_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
3522   #define BELLBOARD_INTENCLR1_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
3523   #define BELLBOARD_INTENCLR1_TRIGGERED3_Clear (0x1UL) /*!< Disable                                                            */
3524   #define BELLBOARD_INTENCLR1_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3525   #define BELLBOARD_INTENCLR1_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3526 
3527 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
3528   #define BELLBOARD_INTENCLR1_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
3529   #define BELLBOARD_INTENCLR1_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
3530   #define BELLBOARD_INTENCLR1_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
3531   #define BELLBOARD_INTENCLR1_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
3532   #define BELLBOARD_INTENCLR1_TRIGGERED4_Clear (0x1UL) /*!< Disable                                                            */
3533   #define BELLBOARD_INTENCLR1_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3534   #define BELLBOARD_INTENCLR1_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3535 
3536 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
3537   #define BELLBOARD_INTENCLR1_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
3538   #define BELLBOARD_INTENCLR1_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
3539   #define BELLBOARD_INTENCLR1_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
3540   #define BELLBOARD_INTENCLR1_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
3541   #define BELLBOARD_INTENCLR1_TRIGGERED5_Clear (0x1UL) /*!< Disable                                                            */
3542   #define BELLBOARD_INTENCLR1_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3543   #define BELLBOARD_INTENCLR1_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3544 
3545 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
3546   #define BELLBOARD_INTENCLR1_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
3547   #define BELLBOARD_INTENCLR1_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
3548   #define BELLBOARD_INTENCLR1_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
3549   #define BELLBOARD_INTENCLR1_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
3550   #define BELLBOARD_INTENCLR1_TRIGGERED6_Clear (0x1UL) /*!< Disable                                                            */
3551   #define BELLBOARD_INTENCLR1_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3552   #define BELLBOARD_INTENCLR1_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3553 
3554 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
3555   #define BELLBOARD_INTENCLR1_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
3556   #define BELLBOARD_INTENCLR1_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
3557   #define BELLBOARD_INTENCLR1_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
3558   #define BELLBOARD_INTENCLR1_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
3559   #define BELLBOARD_INTENCLR1_TRIGGERED7_Clear (0x1UL) /*!< Disable                                                            */
3560   #define BELLBOARD_INTENCLR1_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3561   #define BELLBOARD_INTENCLR1_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3562 
3563 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
3564   #define BELLBOARD_INTENCLR1_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
3565   #define BELLBOARD_INTENCLR1_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
3566   #define BELLBOARD_INTENCLR1_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
3567   #define BELLBOARD_INTENCLR1_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
3568   #define BELLBOARD_INTENCLR1_TRIGGERED8_Clear (0x1UL) /*!< Disable                                                            */
3569   #define BELLBOARD_INTENCLR1_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3570   #define BELLBOARD_INTENCLR1_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3571 
3572 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
3573   #define BELLBOARD_INTENCLR1_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
3574   #define BELLBOARD_INTENCLR1_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
3575   #define BELLBOARD_INTENCLR1_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
3576   #define BELLBOARD_INTENCLR1_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
3577   #define BELLBOARD_INTENCLR1_TRIGGERED9_Clear (0x1UL) /*!< Disable                                                            */
3578   #define BELLBOARD_INTENCLR1_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
3579   #define BELLBOARD_INTENCLR1_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
3580 
3581 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
3582   #define BELLBOARD_INTENCLR1_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
3583   #define BELLBOARD_INTENCLR1_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
3584                                                                             field.*/
3585   #define BELLBOARD_INTENCLR1_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
3586   #define BELLBOARD_INTENCLR1_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
3587   #define BELLBOARD_INTENCLR1_TRIGGERED10_Clear (0x1UL) /*!< Disable                                                           */
3588   #define BELLBOARD_INTENCLR1_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3589   #define BELLBOARD_INTENCLR1_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3590 
3591 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
3592   #define BELLBOARD_INTENCLR1_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
3593   #define BELLBOARD_INTENCLR1_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
3594                                                                             field.*/
3595   #define BELLBOARD_INTENCLR1_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
3596   #define BELLBOARD_INTENCLR1_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
3597   #define BELLBOARD_INTENCLR1_TRIGGERED11_Clear (0x1UL) /*!< Disable                                                           */
3598   #define BELLBOARD_INTENCLR1_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3599   #define BELLBOARD_INTENCLR1_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3600 
3601 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
3602   #define BELLBOARD_INTENCLR1_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
3603   #define BELLBOARD_INTENCLR1_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
3604                                                                             field.*/
3605   #define BELLBOARD_INTENCLR1_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
3606   #define BELLBOARD_INTENCLR1_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
3607   #define BELLBOARD_INTENCLR1_TRIGGERED12_Clear (0x1UL) /*!< Disable                                                           */
3608   #define BELLBOARD_INTENCLR1_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3609   #define BELLBOARD_INTENCLR1_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3610 
3611 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
3612   #define BELLBOARD_INTENCLR1_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
3613   #define BELLBOARD_INTENCLR1_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
3614                                                                             field.*/
3615   #define BELLBOARD_INTENCLR1_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
3616   #define BELLBOARD_INTENCLR1_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
3617   #define BELLBOARD_INTENCLR1_TRIGGERED13_Clear (0x1UL) /*!< Disable                                                           */
3618   #define BELLBOARD_INTENCLR1_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3619   #define BELLBOARD_INTENCLR1_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3620 
3621 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
3622   #define BELLBOARD_INTENCLR1_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
3623   #define BELLBOARD_INTENCLR1_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
3624                                                                             field.*/
3625   #define BELLBOARD_INTENCLR1_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
3626   #define BELLBOARD_INTENCLR1_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
3627   #define BELLBOARD_INTENCLR1_TRIGGERED14_Clear (0x1UL) /*!< Disable                                                           */
3628   #define BELLBOARD_INTENCLR1_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3629   #define BELLBOARD_INTENCLR1_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3630 
3631 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
3632   #define BELLBOARD_INTENCLR1_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
3633   #define BELLBOARD_INTENCLR1_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
3634                                                                             field.*/
3635   #define BELLBOARD_INTENCLR1_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
3636   #define BELLBOARD_INTENCLR1_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
3637   #define BELLBOARD_INTENCLR1_TRIGGERED15_Clear (0x1UL) /*!< Disable                                                           */
3638   #define BELLBOARD_INTENCLR1_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3639   #define BELLBOARD_INTENCLR1_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3640 
3641 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
3642   #define BELLBOARD_INTENCLR1_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
3643   #define BELLBOARD_INTENCLR1_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
3644                                                                             field.*/
3645   #define BELLBOARD_INTENCLR1_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
3646   #define BELLBOARD_INTENCLR1_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
3647   #define BELLBOARD_INTENCLR1_TRIGGERED16_Clear (0x1UL) /*!< Disable                                                           */
3648   #define BELLBOARD_INTENCLR1_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3649   #define BELLBOARD_INTENCLR1_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3650 
3651 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
3652   #define BELLBOARD_INTENCLR1_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
3653   #define BELLBOARD_INTENCLR1_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
3654                                                                             field.*/
3655   #define BELLBOARD_INTENCLR1_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
3656   #define BELLBOARD_INTENCLR1_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
3657   #define BELLBOARD_INTENCLR1_TRIGGERED17_Clear (0x1UL) /*!< Disable                                                           */
3658   #define BELLBOARD_INTENCLR1_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3659   #define BELLBOARD_INTENCLR1_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3660 
3661 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
3662   #define BELLBOARD_INTENCLR1_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
3663   #define BELLBOARD_INTENCLR1_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
3664                                                                             field.*/
3665   #define BELLBOARD_INTENCLR1_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
3666   #define BELLBOARD_INTENCLR1_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
3667   #define BELLBOARD_INTENCLR1_TRIGGERED18_Clear (0x1UL) /*!< Disable                                                           */
3668   #define BELLBOARD_INTENCLR1_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3669   #define BELLBOARD_INTENCLR1_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3670 
3671 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
3672   #define BELLBOARD_INTENCLR1_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
3673   #define BELLBOARD_INTENCLR1_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
3674                                                                             field.*/
3675   #define BELLBOARD_INTENCLR1_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
3676   #define BELLBOARD_INTENCLR1_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
3677   #define BELLBOARD_INTENCLR1_TRIGGERED19_Clear (0x1UL) /*!< Disable                                                           */
3678   #define BELLBOARD_INTENCLR1_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3679   #define BELLBOARD_INTENCLR1_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3680 
3681 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
3682   #define BELLBOARD_INTENCLR1_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
3683   #define BELLBOARD_INTENCLR1_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
3684                                                                             field.*/
3685   #define BELLBOARD_INTENCLR1_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
3686   #define BELLBOARD_INTENCLR1_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
3687   #define BELLBOARD_INTENCLR1_TRIGGERED20_Clear (0x1UL) /*!< Disable                                                           */
3688   #define BELLBOARD_INTENCLR1_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3689   #define BELLBOARD_INTENCLR1_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3690 
3691 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
3692   #define BELLBOARD_INTENCLR1_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
3693   #define BELLBOARD_INTENCLR1_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
3694                                                                             field.*/
3695   #define BELLBOARD_INTENCLR1_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
3696   #define BELLBOARD_INTENCLR1_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
3697   #define BELLBOARD_INTENCLR1_TRIGGERED21_Clear (0x1UL) /*!< Disable                                                           */
3698   #define BELLBOARD_INTENCLR1_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3699   #define BELLBOARD_INTENCLR1_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3700 
3701 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
3702   #define BELLBOARD_INTENCLR1_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
3703   #define BELLBOARD_INTENCLR1_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
3704                                                                             field.*/
3705   #define BELLBOARD_INTENCLR1_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
3706   #define BELLBOARD_INTENCLR1_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
3707   #define BELLBOARD_INTENCLR1_TRIGGERED22_Clear (0x1UL) /*!< Disable                                                           */
3708   #define BELLBOARD_INTENCLR1_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3709   #define BELLBOARD_INTENCLR1_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3710 
3711 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
3712   #define BELLBOARD_INTENCLR1_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
3713   #define BELLBOARD_INTENCLR1_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
3714                                                                             field.*/
3715   #define BELLBOARD_INTENCLR1_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
3716   #define BELLBOARD_INTENCLR1_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
3717   #define BELLBOARD_INTENCLR1_TRIGGERED23_Clear (0x1UL) /*!< Disable                                                           */
3718   #define BELLBOARD_INTENCLR1_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3719   #define BELLBOARD_INTENCLR1_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3720 
3721 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
3722   #define BELLBOARD_INTENCLR1_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
3723   #define BELLBOARD_INTENCLR1_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
3724                                                                             field.*/
3725   #define BELLBOARD_INTENCLR1_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
3726   #define BELLBOARD_INTENCLR1_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
3727   #define BELLBOARD_INTENCLR1_TRIGGERED24_Clear (0x1UL) /*!< Disable                                                           */
3728   #define BELLBOARD_INTENCLR1_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3729   #define BELLBOARD_INTENCLR1_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3730 
3731 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
3732   #define BELLBOARD_INTENCLR1_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
3733   #define BELLBOARD_INTENCLR1_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
3734                                                                             field.*/
3735   #define BELLBOARD_INTENCLR1_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
3736   #define BELLBOARD_INTENCLR1_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
3737   #define BELLBOARD_INTENCLR1_TRIGGERED25_Clear (0x1UL) /*!< Disable                                                           */
3738   #define BELLBOARD_INTENCLR1_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3739   #define BELLBOARD_INTENCLR1_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3740 
3741 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
3742   #define BELLBOARD_INTENCLR1_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
3743   #define BELLBOARD_INTENCLR1_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
3744                                                                             field.*/
3745   #define BELLBOARD_INTENCLR1_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
3746   #define BELLBOARD_INTENCLR1_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
3747   #define BELLBOARD_INTENCLR1_TRIGGERED26_Clear (0x1UL) /*!< Disable                                                           */
3748   #define BELLBOARD_INTENCLR1_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3749   #define BELLBOARD_INTENCLR1_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3750 
3751 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
3752   #define BELLBOARD_INTENCLR1_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
3753   #define BELLBOARD_INTENCLR1_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
3754                                                                             field.*/
3755   #define BELLBOARD_INTENCLR1_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
3756   #define BELLBOARD_INTENCLR1_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
3757   #define BELLBOARD_INTENCLR1_TRIGGERED27_Clear (0x1UL) /*!< Disable                                                           */
3758   #define BELLBOARD_INTENCLR1_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3759   #define BELLBOARD_INTENCLR1_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3760 
3761 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
3762   #define BELLBOARD_INTENCLR1_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
3763   #define BELLBOARD_INTENCLR1_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
3764                                                                             field.*/
3765   #define BELLBOARD_INTENCLR1_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
3766   #define BELLBOARD_INTENCLR1_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
3767   #define BELLBOARD_INTENCLR1_TRIGGERED28_Clear (0x1UL) /*!< Disable                                                           */
3768   #define BELLBOARD_INTENCLR1_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3769   #define BELLBOARD_INTENCLR1_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3770 
3771 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
3772   #define BELLBOARD_INTENCLR1_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
3773   #define BELLBOARD_INTENCLR1_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
3774                                                                             field.*/
3775   #define BELLBOARD_INTENCLR1_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
3776   #define BELLBOARD_INTENCLR1_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
3777   #define BELLBOARD_INTENCLR1_TRIGGERED29_Clear (0x1UL) /*!< Disable                                                           */
3778   #define BELLBOARD_INTENCLR1_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3779   #define BELLBOARD_INTENCLR1_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3780 
3781 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
3782   #define BELLBOARD_INTENCLR1_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
3783   #define BELLBOARD_INTENCLR1_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
3784                                                                             field.*/
3785   #define BELLBOARD_INTENCLR1_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
3786   #define BELLBOARD_INTENCLR1_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
3787   #define BELLBOARD_INTENCLR1_TRIGGERED30_Clear (0x1UL) /*!< Disable                                                           */
3788   #define BELLBOARD_INTENCLR1_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3789   #define BELLBOARD_INTENCLR1_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3790 
3791 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
3792   #define BELLBOARD_INTENCLR1_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
3793   #define BELLBOARD_INTENCLR1_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR1_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
3794                                                                             field.*/
3795   #define BELLBOARD_INTENCLR1_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
3796   #define BELLBOARD_INTENCLR1_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
3797   #define BELLBOARD_INTENCLR1_TRIGGERED31_Clear (0x1UL) /*!< Disable                                                           */
3798   #define BELLBOARD_INTENCLR1_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
3799   #define BELLBOARD_INTENCLR1_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
3800 
3801 
3802 /* BELLBOARD_INTPEND1: Pending interrupts */
3803   #define BELLBOARD_INTPEND1_ResetValue (0x00000000UL) /*!< Reset value of INTPEND1 register.                                  */
3804 
3805 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
3806   #define BELLBOARD_INTPEND1_TRIGGERED0_Pos (0UL)    /*!< Position of TRIGGERED0 field.                                        */
3807   #define BELLBOARD_INTPEND1_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.    */
3808   #define BELLBOARD_INTPEND1_TRIGGERED0_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED0 field.                            */
3809   #define BELLBOARD_INTPEND1_TRIGGERED0_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED0 field.                            */
3810   #define BELLBOARD_INTPEND1_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending                                              */
3811   #define BELLBOARD_INTPEND1_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending                                                     */
3812 
3813 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
3814   #define BELLBOARD_INTPEND1_TRIGGERED1_Pos (1UL)    /*!< Position of TRIGGERED1 field.                                        */
3815   #define BELLBOARD_INTPEND1_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.    */
3816   #define BELLBOARD_INTPEND1_TRIGGERED1_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED1 field.                            */
3817   #define BELLBOARD_INTPEND1_TRIGGERED1_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED1 field.                            */
3818   #define BELLBOARD_INTPEND1_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending                                              */
3819   #define BELLBOARD_INTPEND1_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending                                                     */
3820 
3821 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
3822   #define BELLBOARD_INTPEND1_TRIGGERED2_Pos (2UL)    /*!< Position of TRIGGERED2 field.                                        */
3823   #define BELLBOARD_INTPEND1_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.    */
3824   #define BELLBOARD_INTPEND1_TRIGGERED2_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED2 field.                            */
3825   #define BELLBOARD_INTPEND1_TRIGGERED2_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED2 field.                            */
3826   #define BELLBOARD_INTPEND1_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending                                              */
3827   #define BELLBOARD_INTPEND1_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending                                                     */
3828 
3829 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
3830   #define BELLBOARD_INTPEND1_TRIGGERED3_Pos (3UL)    /*!< Position of TRIGGERED3 field.                                        */
3831   #define BELLBOARD_INTPEND1_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.    */
3832   #define BELLBOARD_INTPEND1_TRIGGERED3_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED3 field.                            */
3833   #define BELLBOARD_INTPEND1_TRIGGERED3_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED3 field.                            */
3834   #define BELLBOARD_INTPEND1_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending                                              */
3835   #define BELLBOARD_INTPEND1_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending                                                     */
3836 
3837 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
3838   #define BELLBOARD_INTPEND1_TRIGGERED4_Pos (4UL)    /*!< Position of TRIGGERED4 field.                                        */
3839   #define BELLBOARD_INTPEND1_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.    */
3840   #define BELLBOARD_INTPEND1_TRIGGERED4_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED4 field.                            */
3841   #define BELLBOARD_INTPEND1_TRIGGERED4_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED4 field.                            */
3842   #define BELLBOARD_INTPEND1_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending                                              */
3843   #define BELLBOARD_INTPEND1_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending                                                     */
3844 
3845 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
3846   #define BELLBOARD_INTPEND1_TRIGGERED5_Pos (5UL)    /*!< Position of TRIGGERED5 field.                                        */
3847   #define BELLBOARD_INTPEND1_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.    */
3848   #define BELLBOARD_INTPEND1_TRIGGERED5_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED5 field.                            */
3849   #define BELLBOARD_INTPEND1_TRIGGERED5_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED5 field.                            */
3850   #define BELLBOARD_INTPEND1_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending                                              */
3851   #define BELLBOARD_INTPEND1_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending                                                     */
3852 
3853 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
3854   #define BELLBOARD_INTPEND1_TRIGGERED6_Pos (6UL)    /*!< Position of TRIGGERED6 field.                                        */
3855   #define BELLBOARD_INTPEND1_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.    */
3856   #define BELLBOARD_INTPEND1_TRIGGERED6_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED6 field.                            */
3857   #define BELLBOARD_INTPEND1_TRIGGERED6_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED6 field.                            */
3858   #define BELLBOARD_INTPEND1_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending                                              */
3859   #define BELLBOARD_INTPEND1_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending                                                     */
3860 
3861 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
3862   #define BELLBOARD_INTPEND1_TRIGGERED7_Pos (7UL)    /*!< Position of TRIGGERED7 field.                                        */
3863   #define BELLBOARD_INTPEND1_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.    */
3864   #define BELLBOARD_INTPEND1_TRIGGERED7_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED7 field.                            */
3865   #define BELLBOARD_INTPEND1_TRIGGERED7_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED7 field.                            */
3866   #define BELLBOARD_INTPEND1_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending                                              */
3867   #define BELLBOARD_INTPEND1_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending                                                     */
3868 
3869 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
3870   #define BELLBOARD_INTPEND1_TRIGGERED8_Pos (8UL)    /*!< Position of TRIGGERED8 field.                                        */
3871   #define BELLBOARD_INTPEND1_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.    */
3872   #define BELLBOARD_INTPEND1_TRIGGERED8_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED8 field.                            */
3873   #define BELLBOARD_INTPEND1_TRIGGERED8_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED8 field.                            */
3874   #define BELLBOARD_INTPEND1_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending                                              */
3875   #define BELLBOARD_INTPEND1_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending                                                     */
3876 
3877 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
3878   #define BELLBOARD_INTPEND1_TRIGGERED9_Pos (9UL)    /*!< Position of TRIGGERED9 field.                                        */
3879   #define BELLBOARD_INTPEND1_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.    */
3880   #define BELLBOARD_INTPEND1_TRIGGERED9_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED9 field.                            */
3881   #define BELLBOARD_INTPEND1_TRIGGERED9_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED9 field.                            */
3882   #define BELLBOARD_INTPEND1_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending                                              */
3883   #define BELLBOARD_INTPEND1_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending                                                     */
3884 
3885 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
3886   #define BELLBOARD_INTPEND1_TRIGGERED10_Pos (10UL)  /*!< Position of TRIGGERED10 field.                                       */
3887   #define BELLBOARD_INTPEND1_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
3888   #define BELLBOARD_INTPEND1_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                           */
3889   #define BELLBOARD_INTPEND1_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                           */
3890   #define BELLBOARD_INTPEND1_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                             */
3891   #define BELLBOARD_INTPEND1_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending                                                    */
3892 
3893 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
3894   #define BELLBOARD_INTPEND1_TRIGGERED11_Pos (11UL)  /*!< Position of TRIGGERED11 field.                                       */
3895   #define BELLBOARD_INTPEND1_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
3896   #define BELLBOARD_INTPEND1_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                           */
3897   #define BELLBOARD_INTPEND1_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                           */
3898   #define BELLBOARD_INTPEND1_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                             */
3899   #define BELLBOARD_INTPEND1_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending                                                    */
3900 
3901 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
3902   #define BELLBOARD_INTPEND1_TRIGGERED12_Pos (12UL)  /*!< Position of TRIGGERED12 field.                                       */
3903   #define BELLBOARD_INTPEND1_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
3904   #define BELLBOARD_INTPEND1_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                           */
3905   #define BELLBOARD_INTPEND1_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                           */
3906   #define BELLBOARD_INTPEND1_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                             */
3907   #define BELLBOARD_INTPEND1_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending                                                    */
3908 
3909 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
3910   #define BELLBOARD_INTPEND1_TRIGGERED13_Pos (13UL)  /*!< Position of TRIGGERED13 field.                                       */
3911   #define BELLBOARD_INTPEND1_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
3912   #define BELLBOARD_INTPEND1_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                           */
3913   #define BELLBOARD_INTPEND1_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                           */
3914   #define BELLBOARD_INTPEND1_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                             */
3915   #define BELLBOARD_INTPEND1_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending                                                    */
3916 
3917 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
3918   #define BELLBOARD_INTPEND1_TRIGGERED14_Pos (14UL)  /*!< Position of TRIGGERED14 field.                                       */
3919   #define BELLBOARD_INTPEND1_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
3920   #define BELLBOARD_INTPEND1_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                           */
3921   #define BELLBOARD_INTPEND1_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                           */
3922   #define BELLBOARD_INTPEND1_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                             */
3923   #define BELLBOARD_INTPEND1_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending                                                    */
3924 
3925 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
3926   #define BELLBOARD_INTPEND1_TRIGGERED15_Pos (15UL)  /*!< Position of TRIGGERED15 field.                                       */
3927   #define BELLBOARD_INTPEND1_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
3928   #define BELLBOARD_INTPEND1_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                           */
3929   #define BELLBOARD_INTPEND1_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                           */
3930   #define BELLBOARD_INTPEND1_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                             */
3931   #define BELLBOARD_INTPEND1_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending                                                    */
3932 
3933 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
3934   #define BELLBOARD_INTPEND1_TRIGGERED16_Pos (16UL)  /*!< Position of TRIGGERED16 field.                                       */
3935   #define BELLBOARD_INTPEND1_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */
3936   #define BELLBOARD_INTPEND1_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                           */
3937   #define BELLBOARD_INTPEND1_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                           */
3938   #define BELLBOARD_INTPEND1_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                             */
3939   #define BELLBOARD_INTPEND1_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending                                                    */
3940 
3941 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
3942   #define BELLBOARD_INTPEND1_TRIGGERED17_Pos (17UL)  /*!< Position of TRIGGERED17 field.                                       */
3943   #define BELLBOARD_INTPEND1_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */
3944   #define BELLBOARD_INTPEND1_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                           */
3945   #define BELLBOARD_INTPEND1_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                           */
3946   #define BELLBOARD_INTPEND1_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                             */
3947   #define BELLBOARD_INTPEND1_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending                                                    */
3948 
3949 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
3950   #define BELLBOARD_INTPEND1_TRIGGERED18_Pos (18UL)  /*!< Position of TRIGGERED18 field.                                       */
3951   #define BELLBOARD_INTPEND1_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */
3952   #define BELLBOARD_INTPEND1_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                           */
3953   #define BELLBOARD_INTPEND1_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                           */
3954   #define BELLBOARD_INTPEND1_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                             */
3955   #define BELLBOARD_INTPEND1_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending                                                    */
3956 
3957 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
3958   #define BELLBOARD_INTPEND1_TRIGGERED19_Pos (19UL)  /*!< Position of TRIGGERED19 field.                                       */
3959   #define BELLBOARD_INTPEND1_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */
3960   #define BELLBOARD_INTPEND1_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                           */
3961   #define BELLBOARD_INTPEND1_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                           */
3962   #define BELLBOARD_INTPEND1_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                             */
3963   #define BELLBOARD_INTPEND1_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending                                                    */
3964 
3965 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
3966   #define BELLBOARD_INTPEND1_TRIGGERED20_Pos (20UL)  /*!< Position of TRIGGERED20 field.                                       */
3967   #define BELLBOARD_INTPEND1_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */
3968   #define BELLBOARD_INTPEND1_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                           */
3969   #define BELLBOARD_INTPEND1_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                           */
3970   #define BELLBOARD_INTPEND1_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                             */
3971   #define BELLBOARD_INTPEND1_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending                                                    */
3972 
3973 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
3974   #define BELLBOARD_INTPEND1_TRIGGERED21_Pos (21UL)  /*!< Position of TRIGGERED21 field.                                       */
3975   #define BELLBOARD_INTPEND1_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */
3976   #define BELLBOARD_INTPEND1_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                           */
3977   #define BELLBOARD_INTPEND1_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                           */
3978   #define BELLBOARD_INTPEND1_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                             */
3979   #define BELLBOARD_INTPEND1_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending                                                    */
3980 
3981 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
3982   #define BELLBOARD_INTPEND1_TRIGGERED22_Pos (22UL)  /*!< Position of TRIGGERED22 field.                                       */
3983   #define BELLBOARD_INTPEND1_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */
3984   #define BELLBOARD_INTPEND1_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                           */
3985   #define BELLBOARD_INTPEND1_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                           */
3986   #define BELLBOARD_INTPEND1_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                             */
3987   #define BELLBOARD_INTPEND1_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending                                                    */
3988 
3989 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
3990   #define BELLBOARD_INTPEND1_TRIGGERED23_Pos (23UL)  /*!< Position of TRIGGERED23 field.                                       */
3991   #define BELLBOARD_INTPEND1_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */
3992   #define BELLBOARD_INTPEND1_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                           */
3993   #define BELLBOARD_INTPEND1_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                           */
3994   #define BELLBOARD_INTPEND1_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                             */
3995   #define BELLBOARD_INTPEND1_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending                                                    */
3996 
3997 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
3998   #define BELLBOARD_INTPEND1_TRIGGERED24_Pos (24UL)  /*!< Position of TRIGGERED24 field.                                       */
3999   #define BELLBOARD_INTPEND1_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */
4000   #define BELLBOARD_INTPEND1_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                           */
4001   #define BELLBOARD_INTPEND1_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                           */
4002   #define BELLBOARD_INTPEND1_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                             */
4003   #define BELLBOARD_INTPEND1_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending                                                    */
4004 
4005 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
4006   #define BELLBOARD_INTPEND1_TRIGGERED25_Pos (25UL)  /*!< Position of TRIGGERED25 field.                                       */
4007   #define BELLBOARD_INTPEND1_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */
4008   #define BELLBOARD_INTPEND1_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                           */
4009   #define BELLBOARD_INTPEND1_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                           */
4010   #define BELLBOARD_INTPEND1_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                             */
4011   #define BELLBOARD_INTPEND1_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending                                                    */
4012 
4013 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
4014   #define BELLBOARD_INTPEND1_TRIGGERED26_Pos (26UL)  /*!< Position of TRIGGERED26 field.                                       */
4015   #define BELLBOARD_INTPEND1_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */
4016   #define BELLBOARD_INTPEND1_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                           */
4017   #define BELLBOARD_INTPEND1_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                           */
4018   #define BELLBOARD_INTPEND1_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                             */
4019   #define BELLBOARD_INTPEND1_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending                                                    */
4020 
4021 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
4022   #define BELLBOARD_INTPEND1_TRIGGERED27_Pos (27UL)  /*!< Position of TRIGGERED27 field.                                       */
4023   #define BELLBOARD_INTPEND1_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */
4024   #define BELLBOARD_INTPEND1_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                           */
4025   #define BELLBOARD_INTPEND1_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                           */
4026   #define BELLBOARD_INTPEND1_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                             */
4027   #define BELLBOARD_INTPEND1_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending                                                    */
4028 
4029 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
4030   #define BELLBOARD_INTPEND1_TRIGGERED28_Pos (28UL)  /*!< Position of TRIGGERED28 field.                                       */
4031   #define BELLBOARD_INTPEND1_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */
4032   #define BELLBOARD_INTPEND1_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                           */
4033   #define BELLBOARD_INTPEND1_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                           */
4034   #define BELLBOARD_INTPEND1_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                             */
4035   #define BELLBOARD_INTPEND1_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending                                                    */
4036 
4037 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
4038   #define BELLBOARD_INTPEND1_TRIGGERED29_Pos (29UL)  /*!< Position of TRIGGERED29 field.                                       */
4039   #define BELLBOARD_INTPEND1_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */
4040   #define BELLBOARD_INTPEND1_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                           */
4041   #define BELLBOARD_INTPEND1_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                           */
4042   #define BELLBOARD_INTPEND1_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                             */
4043   #define BELLBOARD_INTPEND1_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending                                                    */
4044 
4045 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
4046   #define BELLBOARD_INTPEND1_TRIGGERED30_Pos (30UL)  /*!< Position of TRIGGERED30 field.                                       */
4047   #define BELLBOARD_INTPEND1_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */
4048   #define BELLBOARD_INTPEND1_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                           */
4049   #define BELLBOARD_INTPEND1_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                           */
4050   #define BELLBOARD_INTPEND1_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                             */
4051   #define BELLBOARD_INTPEND1_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending                                                    */
4052 
4053 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
4054   #define BELLBOARD_INTPEND1_TRIGGERED31_Pos (31UL)  /*!< Position of TRIGGERED31 field.                                       */
4055   #define BELLBOARD_INTPEND1_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND1_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */
4056   #define BELLBOARD_INTPEND1_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                           */
4057   #define BELLBOARD_INTPEND1_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                           */
4058   #define BELLBOARD_INTPEND1_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                             */
4059   #define BELLBOARD_INTPEND1_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending                                                    */
4060 
4061 
4062 /* BELLBOARD_INTEN2: Enable or disable interrupt */
4063   #define BELLBOARD_INTEN2_ResetValue (0x00000000UL) /*!< Reset value of INTEN2 register.                                      */
4064 
4065 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
4066   #define BELLBOARD_INTEN2_TRIGGERED0_Pos (0UL)      /*!< Position of TRIGGERED0 field.                                        */
4067   #define BELLBOARD_INTEN2_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.        */
4068   #define BELLBOARD_INTEN2_TRIGGERED0_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED0 field.                            */
4069   #define BELLBOARD_INTEN2_TRIGGERED0_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED0 field.                            */
4070   #define BELLBOARD_INTEN2_TRIGGERED0_Disabled (0x0UL) /*!< Disable                                                            */
4071   #define BELLBOARD_INTEN2_TRIGGERED0_Enabled (0x1UL) /*!< Enable                                                              */
4072 
4073 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
4074   #define BELLBOARD_INTEN2_TRIGGERED1_Pos (1UL)      /*!< Position of TRIGGERED1 field.                                        */
4075   #define BELLBOARD_INTEN2_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.        */
4076   #define BELLBOARD_INTEN2_TRIGGERED1_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED1 field.                            */
4077   #define BELLBOARD_INTEN2_TRIGGERED1_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED1 field.                            */
4078   #define BELLBOARD_INTEN2_TRIGGERED1_Disabled (0x0UL) /*!< Disable                                                            */
4079   #define BELLBOARD_INTEN2_TRIGGERED1_Enabled (0x1UL) /*!< Enable                                                              */
4080 
4081 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
4082   #define BELLBOARD_INTEN2_TRIGGERED2_Pos (2UL)      /*!< Position of TRIGGERED2 field.                                        */
4083   #define BELLBOARD_INTEN2_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.        */
4084   #define BELLBOARD_INTEN2_TRIGGERED2_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED2 field.                            */
4085   #define BELLBOARD_INTEN2_TRIGGERED2_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED2 field.                            */
4086   #define BELLBOARD_INTEN2_TRIGGERED2_Disabled (0x0UL) /*!< Disable                                                            */
4087   #define BELLBOARD_INTEN2_TRIGGERED2_Enabled (0x1UL) /*!< Enable                                                              */
4088 
4089 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
4090   #define BELLBOARD_INTEN2_TRIGGERED3_Pos (3UL)      /*!< Position of TRIGGERED3 field.                                        */
4091   #define BELLBOARD_INTEN2_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.        */
4092   #define BELLBOARD_INTEN2_TRIGGERED3_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED3 field.                            */
4093   #define BELLBOARD_INTEN2_TRIGGERED3_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED3 field.                            */
4094   #define BELLBOARD_INTEN2_TRIGGERED3_Disabled (0x0UL) /*!< Disable                                                            */
4095   #define BELLBOARD_INTEN2_TRIGGERED3_Enabled (0x1UL) /*!< Enable                                                              */
4096 
4097 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
4098   #define BELLBOARD_INTEN2_TRIGGERED4_Pos (4UL)      /*!< Position of TRIGGERED4 field.                                        */
4099   #define BELLBOARD_INTEN2_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.        */
4100   #define BELLBOARD_INTEN2_TRIGGERED4_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED4 field.                            */
4101   #define BELLBOARD_INTEN2_TRIGGERED4_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED4 field.                            */
4102   #define BELLBOARD_INTEN2_TRIGGERED4_Disabled (0x0UL) /*!< Disable                                                            */
4103   #define BELLBOARD_INTEN2_TRIGGERED4_Enabled (0x1UL) /*!< Enable                                                              */
4104 
4105 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
4106   #define BELLBOARD_INTEN2_TRIGGERED5_Pos (5UL)      /*!< Position of TRIGGERED5 field.                                        */
4107   #define BELLBOARD_INTEN2_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.        */
4108   #define BELLBOARD_INTEN2_TRIGGERED5_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED5 field.                            */
4109   #define BELLBOARD_INTEN2_TRIGGERED5_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED5 field.                            */
4110   #define BELLBOARD_INTEN2_TRIGGERED5_Disabled (0x0UL) /*!< Disable                                                            */
4111   #define BELLBOARD_INTEN2_TRIGGERED5_Enabled (0x1UL) /*!< Enable                                                              */
4112 
4113 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
4114   #define BELLBOARD_INTEN2_TRIGGERED6_Pos (6UL)      /*!< Position of TRIGGERED6 field.                                        */
4115   #define BELLBOARD_INTEN2_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.        */
4116   #define BELLBOARD_INTEN2_TRIGGERED6_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED6 field.                            */
4117   #define BELLBOARD_INTEN2_TRIGGERED6_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED6 field.                            */
4118   #define BELLBOARD_INTEN2_TRIGGERED6_Disabled (0x0UL) /*!< Disable                                                            */
4119   #define BELLBOARD_INTEN2_TRIGGERED6_Enabled (0x1UL) /*!< Enable                                                              */
4120 
4121 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
4122   #define BELLBOARD_INTEN2_TRIGGERED7_Pos (7UL)      /*!< Position of TRIGGERED7 field.                                        */
4123   #define BELLBOARD_INTEN2_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.        */
4124   #define BELLBOARD_INTEN2_TRIGGERED7_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED7 field.                            */
4125   #define BELLBOARD_INTEN2_TRIGGERED7_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED7 field.                            */
4126   #define BELLBOARD_INTEN2_TRIGGERED7_Disabled (0x0UL) /*!< Disable                                                            */
4127   #define BELLBOARD_INTEN2_TRIGGERED7_Enabled (0x1UL) /*!< Enable                                                              */
4128 
4129 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
4130   #define BELLBOARD_INTEN2_TRIGGERED8_Pos (8UL)      /*!< Position of TRIGGERED8 field.                                        */
4131   #define BELLBOARD_INTEN2_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.        */
4132   #define BELLBOARD_INTEN2_TRIGGERED8_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED8 field.                            */
4133   #define BELLBOARD_INTEN2_TRIGGERED8_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED8 field.                            */
4134   #define BELLBOARD_INTEN2_TRIGGERED8_Disabled (0x0UL) /*!< Disable                                                            */
4135   #define BELLBOARD_INTEN2_TRIGGERED8_Enabled (0x1UL) /*!< Enable                                                              */
4136 
4137 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
4138   #define BELLBOARD_INTEN2_TRIGGERED9_Pos (9UL)      /*!< Position of TRIGGERED9 field.                                        */
4139   #define BELLBOARD_INTEN2_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.        */
4140   #define BELLBOARD_INTEN2_TRIGGERED9_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED9 field.                            */
4141   #define BELLBOARD_INTEN2_TRIGGERED9_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED9 field.                            */
4142   #define BELLBOARD_INTEN2_TRIGGERED9_Disabled (0x0UL) /*!< Disable                                                            */
4143   #define BELLBOARD_INTEN2_TRIGGERED9_Enabled (0x1UL) /*!< Enable                                                              */
4144 
4145 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
4146   #define BELLBOARD_INTEN2_TRIGGERED10_Pos (10UL)    /*!< Position of TRIGGERED10 field.                                       */
4147   #define BELLBOARD_INTEN2_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.     */
4148   #define BELLBOARD_INTEN2_TRIGGERED10_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED10 field.                           */
4149   #define BELLBOARD_INTEN2_TRIGGERED10_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED10 field.                           */
4150   #define BELLBOARD_INTEN2_TRIGGERED10_Disabled (0x0UL) /*!< Disable                                                           */
4151   #define BELLBOARD_INTEN2_TRIGGERED10_Enabled (0x1UL) /*!< Enable                                                             */
4152 
4153 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
4154   #define BELLBOARD_INTEN2_TRIGGERED11_Pos (11UL)    /*!< Position of TRIGGERED11 field.                                       */
4155   #define BELLBOARD_INTEN2_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.     */
4156   #define BELLBOARD_INTEN2_TRIGGERED11_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED11 field.                           */
4157   #define BELLBOARD_INTEN2_TRIGGERED11_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED11 field.                           */
4158   #define BELLBOARD_INTEN2_TRIGGERED11_Disabled (0x0UL) /*!< Disable                                                           */
4159   #define BELLBOARD_INTEN2_TRIGGERED11_Enabled (0x1UL) /*!< Enable                                                             */
4160 
4161 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
4162   #define BELLBOARD_INTEN2_TRIGGERED12_Pos (12UL)    /*!< Position of TRIGGERED12 field.                                       */
4163   #define BELLBOARD_INTEN2_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.     */
4164   #define BELLBOARD_INTEN2_TRIGGERED12_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED12 field.                           */
4165   #define BELLBOARD_INTEN2_TRIGGERED12_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED12 field.                           */
4166   #define BELLBOARD_INTEN2_TRIGGERED12_Disabled (0x0UL) /*!< Disable                                                           */
4167   #define BELLBOARD_INTEN2_TRIGGERED12_Enabled (0x1UL) /*!< Enable                                                             */
4168 
4169 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
4170   #define BELLBOARD_INTEN2_TRIGGERED13_Pos (13UL)    /*!< Position of TRIGGERED13 field.                                       */
4171   #define BELLBOARD_INTEN2_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.     */
4172   #define BELLBOARD_INTEN2_TRIGGERED13_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED13 field.                           */
4173   #define BELLBOARD_INTEN2_TRIGGERED13_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED13 field.                           */
4174   #define BELLBOARD_INTEN2_TRIGGERED13_Disabled (0x0UL) /*!< Disable                                                           */
4175   #define BELLBOARD_INTEN2_TRIGGERED13_Enabled (0x1UL) /*!< Enable                                                             */
4176 
4177 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
4178   #define BELLBOARD_INTEN2_TRIGGERED14_Pos (14UL)    /*!< Position of TRIGGERED14 field.                                       */
4179   #define BELLBOARD_INTEN2_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.     */
4180   #define BELLBOARD_INTEN2_TRIGGERED14_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED14 field.                           */
4181   #define BELLBOARD_INTEN2_TRIGGERED14_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED14 field.                           */
4182   #define BELLBOARD_INTEN2_TRIGGERED14_Disabled (0x0UL) /*!< Disable                                                           */
4183   #define BELLBOARD_INTEN2_TRIGGERED14_Enabled (0x1UL) /*!< Enable                                                             */
4184 
4185 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
4186   #define BELLBOARD_INTEN2_TRIGGERED15_Pos (15UL)    /*!< Position of TRIGGERED15 field.                                       */
4187   #define BELLBOARD_INTEN2_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.     */
4188   #define BELLBOARD_INTEN2_TRIGGERED15_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED15 field.                           */
4189   #define BELLBOARD_INTEN2_TRIGGERED15_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED15 field.                           */
4190   #define BELLBOARD_INTEN2_TRIGGERED15_Disabled (0x0UL) /*!< Disable                                                           */
4191   #define BELLBOARD_INTEN2_TRIGGERED15_Enabled (0x1UL) /*!< Enable                                                             */
4192 
4193 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
4194   #define BELLBOARD_INTEN2_TRIGGERED16_Pos (16UL)    /*!< Position of TRIGGERED16 field.                                       */
4195   #define BELLBOARD_INTEN2_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.     */
4196   #define BELLBOARD_INTEN2_TRIGGERED16_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED16 field.                           */
4197   #define BELLBOARD_INTEN2_TRIGGERED16_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED16 field.                           */
4198   #define BELLBOARD_INTEN2_TRIGGERED16_Disabled (0x0UL) /*!< Disable                                                           */
4199   #define BELLBOARD_INTEN2_TRIGGERED16_Enabled (0x1UL) /*!< Enable                                                             */
4200 
4201 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
4202   #define BELLBOARD_INTEN2_TRIGGERED17_Pos (17UL)    /*!< Position of TRIGGERED17 field.                                       */
4203   #define BELLBOARD_INTEN2_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.     */
4204   #define BELLBOARD_INTEN2_TRIGGERED17_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED17 field.                           */
4205   #define BELLBOARD_INTEN2_TRIGGERED17_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED17 field.                           */
4206   #define BELLBOARD_INTEN2_TRIGGERED17_Disabled (0x0UL) /*!< Disable                                                           */
4207   #define BELLBOARD_INTEN2_TRIGGERED17_Enabled (0x1UL) /*!< Enable                                                             */
4208 
4209 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
4210   #define BELLBOARD_INTEN2_TRIGGERED18_Pos (18UL)    /*!< Position of TRIGGERED18 field.                                       */
4211   #define BELLBOARD_INTEN2_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.     */
4212   #define BELLBOARD_INTEN2_TRIGGERED18_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED18 field.                           */
4213   #define BELLBOARD_INTEN2_TRIGGERED18_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED18 field.                           */
4214   #define BELLBOARD_INTEN2_TRIGGERED18_Disabled (0x0UL) /*!< Disable                                                           */
4215   #define BELLBOARD_INTEN2_TRIGGERED18_Enabled (0x1UL) /*!< Enable                                                             */
4216 
4217 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
4218   #define BELLBOARD_INTEN2_TRIGGERED19_Pos (19UL)    /*!< Position of TRIGGERED19 field.                                       */
4219   #define BELLBOARD_INTEN2_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.     */
4220   #define BELLBOARD_INTEN2_TRIGGERED19_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED19 field.                           */
4221   #define BELLBOARD_INTEN2_TRIGGERED19_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED19 field.                           */
4222   #define BELLBOARD_INTEN2_TRIGGERED19_Disabled (0x0UL) /*!< Disable                                                           */
4223   #define BELLBOARD_INTEN2_TRIGGERED19_Enabled (0x1UL) /*!< Enable                                                             */
4224 
4225 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
4226   #define BELLBOARD_INTEN2_TRIGGERED20_Pos (20UL)    /*!< Position of TRIGGERED20 field.                                       */
4227   #define BELLBOARD_INTEN2_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.     */
4228   #define BELLBOARD_INTEN2_TRIGGERED20_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED20 field.                           */
4229   #define BELLBOARD_INTEN2_TRIGGERED20_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED20 field.                           */
4230   #define BELLBOARD_INTEN2_TRIGGERED20_Disabled (0x0UL) /*!< Disable                                                           */
4231   #define BELLBOARD_INTEN2_TRIGGERED20_Enabled (0x1UL) /*!< Enable                                                             */
4232 
4233 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
4234   #define BELLBOARD_INTEN2_TRIGGERED21_Pos (21UL)    /*!< Position of TRIGGERED21 field.                                       */
4235   #define BELLBOARD_INTEN2_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.     */
4236   #define BELLBOARD_INTEN2_TRIGGERED21_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED21 field.                           */
4237   #define BELLBOARD_INTEN2_TRIGGERED21_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED21 field.                           */
4238   #define BELLBOARD_INTEN2_TRIGGERED21_Disabled (0x0UL) /*!< Disable                                                           */
4239   #define BELLBOARD_INTEN2_TRIGGERED21_Enabled (0x1UL) /*!< Enable                                                             */
4240 
4241 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
4242   #define BELLBOARD_INTEN2_TRIGGERED22_Pos (22UL)    /*!< Position of TRIGGERED22 field.                                       */
4243   #define BELLBOARD_INTEN2_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.     */
4244   #define BELLBOARD_INTEN2_TRIGGERED22_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED22 field.                           */
4245   #define BELLBOARD_INTEN2_TRIGGERED22_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED22 field.                           */
4246   #define BELLBOARD_INTEN2_TRIGGERED22_Disabled (0x0UL) /*!< Disable                                                           */
4247   #define BELLBOARD_INTEN2_TRIGGERED22_Enabled (0x1UL) /*!< Enable                                                             */
4248 
4249 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
4250   #define BELLBOARD_INTEN2_TRIGGERED23_Pos (23UL)    /*!< Position of TRIGGERED23 field.                                       */
4251   #define BELLBOARD_INTEN2_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.     */
4252   #define BELLBOARD_INTEN2_TRIGGERED23_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED23 field.                           */
4253   #define BELLBOARD_INTEN2_TRIGGERED23_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED23 field.                           */
4254   #define BELLBOARD_INTEN2_TRIGGERED23_Disabled (0x0UL) /*!< Disable                                                           */
4255   #define BELLBOARD_INTEN2_TRIGGERED23_Enabled (0x1UL) /*!< Enable                                                             */
4256 
4257 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
4258   #define BELLBOARD_INTEN2_TRIGGERED24_Pos (24UL)    /*!< Position of TRIGGERED24 field.                                       */
4259   #define BELLBOARD_INTEN2_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.     */
4260   #define BELLBOARD_INTEN2_TRIGGERED24_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED24 field.                           */
4261   #define BELLBOARD_INTEN2_TRIGGERED24_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED24 field.                           */
4262   #define BELLBOARD_INTEN2_TRIGGERED24_Disabled (0x0UL) /*!< Disable                                                           */
4263   #define BELLBOARD_INTEN2_TRIGGERED24_Enabled (0x1UL) /*!< Enable                                                             */
4264 
4265 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
4266   #define BELLBOARD_INTEN2_TRIGGERED25_Pos (25UL)    /*!< Position of TRIGGERED25 field.                                       */
4267   #define BELLBOARD_INTEN2_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.     */
4268   #define BELLBOARD_INTEN2_TRIGGERED25_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED25 field.                           */
4269   #define BELLBOARD_INTEN2_TRIGGERED25_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED25 field.                           */
4270   #define BELLBOARD_INTEN2_TRIGGERED25_Disabled (0x0UL) /*!< Disable                                                           */
4271   #define BELLBOARD_INTEN2_TRIGGERED25_Enabled (0x1UL) /*!< Enable                                                             */
4272 
4273 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
4274   #define BELLBOARD_INTEN2_TRIGGERED26_Pos (26UL)    /*!< Position of TRIGGERED26 field.                                       */
4275   #define BELLBOARD_INTEN2_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.     */
4276   #define BELLBOARD_INTEN2_TRIGGERED26_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED26 field.                           */
4277   #define BELLBOARD_INTEN2_TRIGGERED26_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED26 field.                           */
4278   #define BELLBOARD_INTEN2_TRIGGERED26_Disabled (0x0UL) /*!< Disable                                                           */
4279   #define BELLBOARD_INTEN2_TRIGGERED26_Enabled (0x1UL) /*!< Enable                                                             */
4280 
4281 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
4282   #define BELLBOARD_INTEN2_TRIGGERED27_Pos (27UL)    /*!< Position of TRIGGERED27 field.                                       */
4283   #define BELLBOARD_INTEN2_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.     */
4284   #define BELLBOARD_INTEN2_TRIGGERED27_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED27 field.                           */
4285   #define BELLBOARD_INTEN2_TRIGGERED27_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED27 field.                           */
4286   #define BELLBOARD_INTEN2_TRIGGERED27_Disabled (0x0UL) /*!< Disable                                                           */
4287   #define BELLBOARD_INTEN2_TRIGGERED27_Enabled (0x1UL) /*!< Enable                                                             */
4288 
4289 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
4290   #define BELLBOARD_INTEN2_TRIGGERED28_Pos (28UL)    /*!< Position of TRIGGERED28 field.                                       */
4291   #define BELLBOARD_INTEN2_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.     */
4292   #define BELLBOARD_INTEN2_TRIGGERED28_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED28 field.                           */
4293   #define BELLBOARD_INTEN2_TRIGGERED28_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED28 field.                           */
4294   #define BELLBOARD_INTEN2_TRIGGERED28_Disabled (0x0UL) /*!< Disable                                                           */
4295   #define BELLBOARD_INTEN2_TRIGGERED28_Enabled (0x1UL) /*!< Enable                                                             */
4296 
4297 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
4298   #define BELLBOARD_INTEN2_TRIGGERED29_Pos (29UL)    /*!< Position of TRIGGERED29 field.                                       */
4299   #define BELLBOARD_INTEN2_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.     */
4300   #define BELLBOARD_INTEN2_TRIGGERED29_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED29 field.                           */
4301   #define BELLBOARD_INTEN2_TRIGGERED29_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED29 field.                           */
4302   #define BELLBOARD_INTEN2_TRIGGERED29_Disabled (0x0UL) /*!< Disable                                                           */
4303   #define BELLBOARD_INTEN2_TRIGGERED29_Enabled (0x1UL) /*!< Enable                                                             */
4304 
4305 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
4306   #define BELLBOARD_INTEN2_TRIGGERED30_Pos (30UL)    /*!< Position of TRIGGERED30 field.                                       */
4307   #define BELLBOARD_INTEN2_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.     */
4308   #define BELLBOARD_INTEN2_TRIGGERED30_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED30 field.                           */
4309   #define BELLBOARD_INTEN2_TRIGGERED30_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED30 field.                           */
4310   #define BELLBOARD_INTEN2_TRIGGERED30_Disabled (0x0UL) /*!< Disable                                                           */
4311   #define BELLBOARD_INTEN2_TRIGGERED30_Enabled (0x1UL) /*!< Enable                                                             */
4312 
4313 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
4314   #define BELLBOARD_INTEN2_TRIGGERED31_Pos (31UL)    /*!< Position of TRIGGERED31 field.                                       */
4315   #define BELLBOARD_INTEN2_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN2_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.     */
4316   #define BELLBOARD_INTEN2_TRIGGERED31_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED31 field.                           */
4317   #define BELLBOARD_INTEN2_TRIGGERED31_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED31 field.                           */
4318   #define BELLBOARD_INTEN2_TRIGGERED31_Disabled (0x0UL) /*!< Disable                                                           */
4319   #define BELLBOARD_INTEN2_TRIGGERED31_Enabled (0x1UL) /*!< Enable                                                             */
4320 
4321 
4322 /* BELLBOARD_INTENSET2: Enable interrupt */
4323   #define BELLBOARD_INTENSET2_ResetValue (0x00000000UL) /*!< Reset value of INTENSET2 register.                                */
4324 
4325 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
4326   #define BELLBOARD_INTENSET2_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
4327   #define BELLBOARD_INTENSET2_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
4328   #define BELLBOARD_INTENSET2_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
4329   #define BELLBOARD_INTENSET2_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
4330   #define BELLBOARD_INTENSET2_TRIGGERED0_Set (0x1UL) /*!< Enable                                                               */
4331   #define BELLBOARD_INTENSET2_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4332   #define BELLBOARD_INTENSET2_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4333 
4334 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
4335   #define BELLBOARD_INTENSET2_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
4336   #define BELLBOARD_INTENSET2_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
4337   #define BELLBOARD_INTENSET2_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
4338   #define BELLBOARD_INTENSET2_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
4339   #define BELLBOARD_INTENSET2_TRIGGERED1_Set (0x1UL) /*!< Enable                                                               */
4340   #define BELLBOARD_INTENSET2_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4341   #define BELLBOARD_INTENSET2_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4342 
4343 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
4344   #define BELLBOARD_INTENSET2_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
4345   #define BELLBOARD_INTENSET2_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
4346   #define BELLBOARD_INTENSET2_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
4347   #define BELLBOARD_INTENSET2_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
4348   #define BELLBOARD_INTENSET2_TRIGGERED2_Set (0x1UL) /*!< Enable                                                               */
4349   #define BELLBOARD_INTENSET2_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4350   #define BELLBOARD_INTENSET2_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4351 
4352 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
4353   #define BELLBOARD_INTENSET2_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
4354   #define BELLBOARD_INTENSET2_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
4355   #define BELLBOARD_INTENSET2_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
4356   #define BELLBOARD_INTENSET2_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
4357   #define BELLBOARD_INTENSET2_TRIGGERED3_Set (0x1UL) /*!< Enable                                                               */
4358   #define BELLBOARD_INTENSET2_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4359   #define BELLBOARD_INTENSET2_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4360 
4361 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
4362   #define BELLBOARD_INTENSET2_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
4363   #define BELLBOARD_INTENSET2_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
4364   #define BELLBOARD_INTENSET2_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
4365   #define BELLBOARD_INTENSET2_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
4366   #define BELLBOARD_INTENSET2_TRIGGERED4_Set (0x1UL) /*!< Enable                                                               */
4367   #define BELLBOARD_INTENSET2_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4368   #define BELLBOARD_INTENSET2_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4369 
4370 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
4371   #define BELLBOARD_INTENSET2_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
4372   #define BELLBOARD_INTENSET2_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
4373   #define BELLBOARD_INTENSET2_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
4374   #define BELLBOARD_INTENSET2_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
4375   #define BELLBOARD_INTENSET2_TRIGGERED5_Set (0x1UL) /*!< Enable                                                               */
4376   #define BELLBOARD_INTENSET2_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4377   #define BELLBOARD_INTENSET2_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4378 
4379 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
4380   #define BELLBOARD_INTENSET2_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
4381   #define BELLBOARD_INTENSET2_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
4382   #define BELLBOARD_INTENSET2_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
4383   #define BELLBOARD_INTENSET2_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
4384   #define BELLBOARD_INTENSET2_TRIGGERED6_Set (0x1UL) /*!< Enable                                                               */
4385   #define BELLBOARD_INTENSET2_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4386   #define BELLBOARD_INTENSET2_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4387 
4388 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
4389   #define BELLBOARD_INTENSET2_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
4390   #define BELLBOARD_INTENSET2_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
4391   #define BELLBOARD_INTENSET2_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
4392   #define BELLBOARD_INTENSET2_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
4393   #define BELLBOARD_INTENSET2_TRIGGERED7_Set (0x1UL) /*!< Enable                                                               */
4394   #define BELLBOARD_INTENSET2_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4395   #define BELLBOARD_INTENSET2_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4396 
4397 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
4398   #define BELLBOARD_INTENSET2_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
4399   #define BELLBOARD_INTENSET2_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
4400   #define BELLBOARD_INTENSET2_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
4401   #define BELLBOARD_INTENSET2_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
4402   #define BELLBOARD_INTENSET2_TRIGGERED8_Set (0x1UL) /*!< Enable                                                               */
4403   #define BELLBOARD_INTENSET2_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4404   #define BELLBOARD_INTENSET2_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4405 
4406 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
4407   #define BELLBOARD_INTENSET2_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
4408   #define BELLBOARD_INTENSET2_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
4409   #define BELLBOARD_INTENSET2_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
4410   #define BELLBOARD_INTENSET2_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
4411   #define BELLBOARD_INTENSET2_TRIGGERED9_Set (0x1UL) /*!< Enable                                                               */
4412   #define BELLBOARD_INTENSET2_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4413   #define BELLBOARD_INTENSET2_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4414 
4415 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
4416   #define BELLBOARD_INTENSET2_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
4417   #define BELLBOARD_INTENSET2_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
4418                                                                             field.*/
4419   #define BELLBOARD_INTENSET2_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
4420   #define BELLBOARD_INTENSET2_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
4421   #define BELLBOARD_INTENSET2_TRIGGERED10_Set (0x1UL) /*!< Enable                                                              */
4422   #define BELLBOARD_INTENSET2_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4423   #define BELLBOARD_INTENSET2_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4424 
4425 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
4426   #define BELLBOARD_INTENSET2_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
4427   #define BELLBOARD_INTENSET2_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
4428                                                                             field.*/
4429   #define BELLBOARD_INTENSET2_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
4430   #define BELLBOARD_INTENSET2_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
4431   #define BELLBOARD_INTENSET2_TRIGGERED11_Set (0x1UL) /*!< Enable                                                              */
4432   #define BELLBOARD_INTENSET2_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4433   #define BELLBOARD_INTENSET2_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4434 
4435 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
4436   #define BELLBOARD_INTENSET2_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
4437   #define BELLBOARD_INTENSET2_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
4438                                                                             field.*/
4439   #define BELLBOARD_INTENSET2_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
4440   #define BELLBOARD_INTENSET2_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
4441   #define BELLBOARD_INTENSET2_TRIGGERED12_Set (0x1UL) /*!< Enable                                                              */
4442   #define BELLBOARD_INTENSET2_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4443   #define BELLBOARD_INTENSET2_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4444 
4445 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
4446   #define BELLBOARD_INTENSET2_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
4447   #define BELLBOARD_INTENSET2_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
4448                                                                             field.*/
4449   #define BELLBOARD_INTENSET2_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
4450   #define BELLBOARD_INTENSET2_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
4451   #define BELLBOARD_INTENSET2_TRIGGERED13_Set (0x1UL) /*!< Enable                                                              */
4452   #define BELLBOARD_INTENSET2_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4453   #define BELLBOARD_INTENSET2_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4454 
4455 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
4456   #define BELLBOARD_INTENSET2_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
4457   #define BELLBOARD_INTENSET2_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
4458                                                                             field.*/
4459   #define BELLBOARD_INTENSET2_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
4460   #define BELLBOARD_INTENSET2_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
4461   #define BELLBOARD_INTENSET2_TRIGGERED14_Set (0x1UL) /*!< Enable                                                              */
4462   #define BELLBOARD_INTENSET2_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4463   #define BELLBOARD_INTENSET2_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4464 
4465 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
4466   #define BELLBOARD_INTENSET2_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
4467   #define BELLBOARD_INTENSET2_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
4468                                                                             field.*/
4469   #define BELLBOARD_INTENSET2_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
4470   #define BELLBOARD_INTENSET2_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
4471   #define BELLBOARD_INTENSET2_TRIGGERED15_Set (0x1UL) /*!< Enable                                                              */
4472   #define BELLBOARD_INTENSET2_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4473   #define BELLBOARD_INTENSET2_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4474 
4475 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
4476   #define BELLBOARD_INTENSET2_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
4477   #define BELLBOARD_INTENSET2_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
4478                                                                             field.*/
4479   #define BELLBOARD_INTENSET2_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
4480   #define BELLBOARD_INTENSET2_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
4481   #define BELLBOARD_INTENSET2_TRIGGERED16_Set (0x1UL) /*!< Enable                                                              */
4482   #define BELLBOARD_INTENSET2_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4483   #define BELLBOARD_INTENSET2_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4484 
4485 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
4486   #define BELLBOARD_INTENSET2_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
4487   #define BELLBOARD_INTENSET2_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
4488                                                                             field.*/
4489   #define BELLBOARD_INTENSET2_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
4490   #define BELLBOARD_INTENSET2_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
4491   #define BELLBOARD_INTENSET2_TRIGGERED17_Set (0x1UL) /*!< Enable                                                              */
4492   #define BELLBOARD_INTENSET2_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4493   #define BELLBOARD_INTENSET2_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4494 
4495 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
4496   #define BELLBOARD_INTENSET2_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
4497   #define BELLBOARD_INTENSET2_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
4498                                                                             field.*/
4499   #define BELLBOARD_INTENSET2_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
4500   #define BELLBOARD_INTENSET2_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
4501   #define BELLBOARD_INTENSET2_TRIGGERED18_Set (0x1UL) /*!< Enable                                                              */
4502   #define BELLBOARD_INTENSET2_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4503   #define BELLBOARD_INTENSET2_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4504 
4505 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
4506   #define BELLBOARD_INTENSET2_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
4507   #define BELLBOARD_INTENSET2_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
4508                                                                             field.*/
4509   #define BELLBOARD_INTENSET2_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
4510   #define BELLBOARD_INTENSET2_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
4511   #define BELLBOARD_INTENSET2_TRIGGERED19_Set (0x1UL) /*!< Enable                                                              */
4512   #define BELLBOARD_INTENSET2_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4513   #define BELLBOARD_INTENSET2_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4514 
4515 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
4516   #define BELLBOARD_INTENSET2_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
4517   #define BELLBOARD_INTENSET2_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
4518                                                                             field.*/
4519   #define BELLBOARD_INTENSET2_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
4520   #define BELLBOARD_INTENSET2_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
4521   #define BELLBOARD_INTENSET2_TRIGGERED20_Set (0x1UL) /*!< Enable                                                              */
4522   #define BELLBOARD_INTENSET2_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4523   #define BELLBOARD_INTENSET2_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4524 
4525 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
4526   #define BELLBOARD_INTENSET2_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
4527   #define BELLBOARD_INTENSET2_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
4528                                                                             field.*/
4529   #define BELLBOARD_INTENSET2_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
4530   #define BELLBOARD_INTENSET2_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
4531   #define BELLBOARD_INTENSET2_TRIGGERED21_Set (0x1UL) /*!< Enable                                                              */
4532   #define BELLBOARD_INTENSET2_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4533   #define BELLBOARD_INTENSET2_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4534 
4535 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
4536   #define BELLBOARD_INTENSET2_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
4537   #define BELLBOARD_INTENSET2_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
4538                                                                             field.*/
4539   #define BELLBOARD_INTENSET2_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
4540   #define BELLBOARD_INTENSET2_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
4541   #define BELLBOARD_INTENSET2_TRIGGERED22_Set (0x1UL) /*!< Enable                                                              */
4542   #define BELLBOARD_INTENSET2_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4543   #define BELLBOARD_INTENSET2_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4544 
4545 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
4546   #define BELLBOARD_INTENSET2_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
4547   #define BELLBOARD_INTENSET2_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
4548                                                                             field.*/
4549   #define BELLBOARD_INTENSET2_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
4550   #define BELLBOARD_INTENSET2_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
4551   #define BELLBOARD_INTENSET2_TRIGGERED23_Set (0x1UL) /*!< Enable                                                              */
4552   #define BELLBOARD_INTENSET2_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4553   #define BELLBOARD_INTENSET2_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4554 
4555 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
4556   #define BELLBOARD_INTENSET2_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
4557   #define BELLBOARD_INTENSET2_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
4558                                                                             field.*/
4559   #define BELLBOARD_INTENSET2_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
4560   #define BELLBOARD_INTENSET2_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
4561   #define BELLBOARD_INTENSET2_TRIGGERED24_Set (0x1UL) /*!< Enable                                                              */
4562   #define BELLBOARD_INTENSET2_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4563   #define BELLBOARD_INTENSET2_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4564 
4565 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
4566   #define BELLBOARD_INTENSET2_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
4567   #define BELLBOARD_INTENSET2_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
4568                                                                             field.*/
4569   #define BELLBOARD_INTENSET2_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
4570   #define BELLBOARD_INTENSET2_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
4571   #define BELLBOARD_INTENSET2_TRIGGERED25_Set (0x1UL) /*!< Enable                                                              */
4572   #define BELLBOARD_INTENSET2_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4573   #define BELLBOARD_INTENSET2_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4574 
4575 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
4576   #define BELLBOARD_INTENSET2_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
4577   #define BELLBOARD_INTENSET2_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
4578                                                                             field.*/
4579   #define BELLBOARD_INTENSET2_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
4580   #define BELLBOARD_INTENSET2_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
4581   #define BELLBOARD_INTENSET2_TRIGGERED26_Set (0x1UL) /*!< Enable                                                              */
4582   #define BELLBOARD_INTENSET2_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4583   #define BELLBOARD_INTENSET2_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4584 
4585 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
4586   #define BELLBOARD_INTENSET2_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
4587   #define BELLBOARD_INTENSET2_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
4588                                                                             field.*/
4589   #define BELLBOARD_INTENSET2_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
4590   #define BELLBOARD_INTENSET2_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
4591   #define BELLBOARD_INTENSET2_TRIGGERED27_Set (0x1UL) /*!< Enable                                                              */
4592   #define BELLBOARD_INTENSET2_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4593   #define BELLBOARD_INTENSET2_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4594 
4595 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
4596   #define BELLBOARD_INTENSET2_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
4597   #define BELLBOARD_INTENSET2_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
4598                                                                             field.*/
4599   #define BELLBOARD_INTENSET2_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
4600   #define BELLBOARD_INTENSET2_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
4601   #define BELLBOARD_INTENSET2_TRIGGERED28_Set (0x1UL) /*!< Enable                                                              */
4602   #define BELLBOARD_INTENSET2_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4603   #define BELLBOARD_INTENSET2_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4604 
4605 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
4606   #define BELLBOARD_INTENSET2_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
4607   #define BELLBOARD_INTENSET2_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
4608                                                                             field.*/
4609   #define BELLBOARD_INTENSET2_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
4610   #define BELLBOARD_INTENSET2_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
4611   #define BELLBOARD_INTENSET2_TRIGGERED29_Set (0x1UL) /*!< Enable                                                              */
4612   #define BELLBOARD_INTENSET2_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4613   #define BELLBOARD_INTENSET2_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4614 
4615 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
4616   #define BELLBOARD_INTENSET2_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
4617   #define BELLBOARD_INTENSET2_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
4618                                                                             field.*/
4619   #define BELLBOARD_INTENSET2_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
4620   #define BELLBOARD_INTENSET2_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
4621   #define BELLBOARD_INTENSET2_TRIGGERED30_Set (0x1UL) /*!< Enable                                                              */
4622   #define BELLBOARD_INTENSET2_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4623   #define BELLBOARD_INTENSET2_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4624 
4625 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
4626   #define BELLBOARD_INTENSET2_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
4627   #define BELLBOARD_INTENSET2_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET2_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
4628                                                                             field.*/
4629   #define BELLBOARD_INTENSET2_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
4630   #define BELLBOARD_INTENSET2_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
4631   #define BELLBOARD_INTENSET2_TRIGGERED31_Set (0x1UL) /*!< Enable                                                              */
4632   #define BELLBOARD_INTENSET2_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4633   #define BELLBOARD_INTENSET2_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4634 
4635 
4636 /* BELLBOARD_INTENCLR2: Disable interrupt */
4637   #define BELLBOARD_INTENCLR2_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR2 register.                                */
4638 
4639 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
4640   #define BELLBOARD_INTENCLR2_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
4641   #define BELLBOARD_INTENCLR2_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
4642   #define BELLBOARD_INTENCLR2_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
4643   #define BELLBOARD_INTENCLR2_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
4644   #define BELLBOARD_INTENCLR2_TRIGGERED0_Clear (0x1UL) /*!< Disable                                                            */
4645   #define BELLBOARD_INTENCLR2_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4646   #define BELLBOARD_INTENCLR2_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4647 
4648 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
4649   #define BELLBOARD_INTENCLR2_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
4650   #define BELLBOARD_INTENCLR2_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
4651   #define BELLBOARD_INTENCLR2_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
4652   #define BELLBOARD_INTENCLR2_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
4653   #define BELLBOARD_INTENCLR2_TRIGGERED1_Clear (0x1UL) /*!< Disable                                                            */
4654   #define BELLBOARD_INTENCLR2_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4655   #define BELLBOARD_INTENCLR2_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4656 
4657 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
4658   #define BELLBOARD_INTENCLR2_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
4659   #define BELLBOARD_INTENCLR2_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
4660   #define BELLBOARD_INTENCLR2_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
4661   #define BELLBOARD_INTENCLR2_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
4662   #define BELLBOARD_INTENCLR2_TRIGGERED2_Clear (0x1UL) /*!< Disable                                                            */
4663   #define BELLBOARD_INTENCLR2_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4664   #define BELLBOARD_INTENCLR2_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4665 
4666 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
4667   #define BELLBOARD_INTENCLR2_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
4668   #define BELLBOARD_INTENCLR2_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
4669   #define BELLBOARD_INTENCLR2_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
4670   #define BELLBOARD_INTENCLR2_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
4671   #define BELLBOARD_INTENCLR2_TRIGGERED3_Clear (0x1UL) /*!< Disable                                                            */
4672   #define BELLBOARD_INTENCLR2_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4673   #define BELLBOARD_INTENCLR2_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4674 
4675 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
4676   #define BELLBOARD_INTENCLR2_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
4677   #define BELLBOARD_INTENCLR2_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
4678   #define BELLBOARD_INTENCLR2_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
4679   #define BELLBOARD_INTENCLR2_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
4680   #define BELLBOARD_INTENCLR2_TRIGGERED4_Clear (0x1UL) /*!< Disable                                                            */
4681   #define BELLBOARD_INTENCLR2_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4682   #define BELLBOARD_INTENCLR2_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4683 
4684 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
4685   #define BELLBOARD_INTENCLR2_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
4686   #define BELLBOARD_INTENCLR2_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
4687   #define BELLBOARD_INTENCLR2_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
4688   #define BELLBOARD_INTENCLR2_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
4689   #define BELLBOARD_INTENCLR2_TRIGGERED5_Clear (0x1UL) /*!< Disable                                                            */
4690   #define BELLBOARD_INTENCLR2_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4691   #define BELLBOARD_INTENCLR2_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4692 
4693 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
4694   #define BELLBOARD_INTENCLR2_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
4695   #define BELLBOARD_INTENCLR2_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
4696   #define BELLBOARD_INTENCLR2_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
4697   #define BELLBOARD_INTENCLR2_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
4698   #define BELLBOARD_INTENCLR2_TRIGGERED6_Clear (0x1UL) /*!< Disable                                                            */
4699   #define BELLBOARD_INTENCLR2_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4700   #define BELLBOARD_INTENCLR2_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4701 
4702 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
4703   #define BELLBOARD_INTENCLR2_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
4704   #define BELLBOARD_INTENCLR2_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
4705   #define BELLBOARD_INTENCLR2_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
4706   #define BELLBOARD_INTENCLR2_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
4707   #define BELLBOARD_INTENCLR2_TRIGGERED7_Clear (0x1UL) /*!< Disable                                                            */
4708   #define BELLBOARD_INTENCLR2_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4709   #define BELLBOARD_INTENCLR2_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4710 
4711 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
4712   #define BELLBOARD_INTENCLR2_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
4713   #define BELLBOARD_INTENCLR2_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
4714   #define BELLBOARD_INTENCLR2_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
4715   #define BELLBOARD_INTENCLR2_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
4716   #define BELLBOARD_INTENCLR2_TRIGGERED8_Clear (0x1UL) /*!< Disable                                                            */
4717   #define BELLBOARD_INTENCLR2_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4718   #define BELLBOARD_INTENCLR2_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4719 
4720 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
4721   #define BELLBOARD_INTENCLR2_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
4722   #define BELLBOARD_INTENCLR2_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
4723   #define BELLBOARD_INTENCLR2_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
4724   #define BELLBOARD_INTENCLR2_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
4725   #define BELLBOARD_INTENCLR2_TRIGGERED9_Clear (0x1UL) /*!< Disable                                                            */
4726   #define BELLBOARD_INTENCLR2_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
4727   #define BELLBOARD_INTENCLR2_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
4728 
4729 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
4730   #define BELLBOARD_INTENCLR2_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
4731   #define BELLBOARD_INTENCLR2_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
4732                                                                             field.*/
4733   #define BELLBOARD_INTENCLR2_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
4734   #define BELLBOARD_INTENCLR2_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
4735   #define BELLBOARD_INTENCLR2_TRIGGERED10_Clear (0x1UL) /*!< Disable                                                           */
4736   #define BELLBOARD_INTENCLR2_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4737   #define BELLBOARD_INTENCLR2_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4738 
4739 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
4740   #define BELLBOARD_INTENCLR2_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
4741   #define BELLBOARD_INTENCLR2_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
4742                                                                             field.*/
4743   #define BELLBOARD_INTENCLR2_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
4744   #define BELLBOARD_INTENCLR2_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
4745   #define BELLBOARD_INTENCLR2_TRIGGERED11_Clear (0x1UL) /*!< Disable                                                           */
4746   #define BELLBOARD_INTENCLR2_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4747   #define BELLBOARD_INTENCLR2_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4748 
4749 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
4750   #define BELLBOARD_INTENCLR2_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
4751   #define BELLBOARD_INTENCLR2_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
4752                                                                             field.*/
4753   #define BELLBOARD_INTENCLR2_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
4754   #define BELLBOARD_INTENCLR2_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
4755   #define BELLBOARD_INTENCLR2_TRIGGERED12_Clear (0x1UL) /*!< Disable                                                           */
4756   #define BELLBOARD_INTENCLR2_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4757   #define BELLBOARD_INTENCLR2_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4758 
4759 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
4760   #define BELLBOARD_INTENCLR2_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
4761   #define BELLBOARD_INTENCLR2_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
4762                                                                             field.*/
4763   #define BELLBOARD_INTENCLR2_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
4764   #define BELLBOARD_INTENCLR2_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
4765   #define BELLBOARD_INTENCLR2_TRIGGERED13_Clear (0x1UL) /*!< Disable                                                           */
4766   #define BELLBOARD_INTENCLR2_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4767   #define BELLBOARD_INTENCLR2_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4768 
4769 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
4770   #define BELLBOARD_INTENCLR2_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
4771   #define BELLBOARD_INTENCLR2_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
4772                                                                             field.*/
4773   #define BELLBOARD_INTENCLR2_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
4774   #define BELLBOARD_INTENCLR2_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
4775   #define BELLBOARD_INTENCLR2_TRIGGERED14_Clear (0x1UL) /*!< Disable                                                           */
4776   #define BELLBOARD_INTENCLR2_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4777   #define BELLBOARD_INTENCLR2_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4778 
4779 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
4780   #define BELLBOARD_INTENCLR2_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
4781   #define BELLBOARD_INTENCLR2_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
4782                                                                             field.*/
4783   #define BELLBOARD_INTENCLR2_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
4784   #define BELLBOARD_INTENCLR2_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
4785   #define BELLBOARD_INTENCLR2_TRIGGERED15_Clear (0x1UL) /*!< Disable                                                           */
4786   #define BELLBOARD_INTENCLR2_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4787   #define BELLBOARD_INTENCLR2_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4788 
4789 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
4790   #define BELLBOARD_INTENCLR2_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
4791   #define BELLBOARD_INTENCLR2_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
4792                                                                             field.*/
4793   #define BELLBOARD_INTENCLR2_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
4794   #define BELLBOARD_INTENCLR2_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
4795   #define BELLBOARD_INTENCLR2_TRIGGERED16_Clear (0x1UL) /*!< Disable                                                           */
4796   #define BELLBOARD_INTENCLR2_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4797   #define BELLBOARD_INTENCLR2_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4798 
4799 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
4800   #define BELLBOARD_INTENCLR2_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
4801   #define BELLBOARD_INTENCLR2_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
4802                                                                             field.*/
4803   #define BELLBOARD_INTENCLR2_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
4804   #define BELLBOARD_INTENCLR2_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
4805   #define BELLBOARD_INTENCLR2_TRIGGERED17_Clear (0x1UL) /*!< Disable                                                           */
4806   #define BELLBOARD_INTENCLR2_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4807   #define BELLBOARD_INTENCLR2_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4808 
4809 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
4810   #define BELLBOARD_INTENCLR2_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
4811   #define BELLBOARD_INTENCLR2_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
4812                                                                             field.*/
4813   #define BELLBOARD_INTENCLR2_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
4814   #define BELLBOARD_INTENCLR2_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
4815   #define BELLBOARD_INTENCLR2_TRIGGERED18_Clear (0x1UL) /*!< Disable                                                           */
4816   #define BELLBOARD_INTENCLR2_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4817   #define BELLBOARD_INTENCLR2_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4818 
4819 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
4820   #define BELLBOARD_INTENCLR2_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
4821   #define BELLBOARD_INTENCLR2_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
4822                                                                             field.*/
4823   #define BELLBOARD_INTENCLR2_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
4824   #define BELLBOARD_INTENCLR2_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
4825   #define BELLBOARD_INTENCLR2_TRIGGERED19_Clear (0x1UL) /*!< Disable                                                           */
4826   #define BELLBOARD_INTENCLR2_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4827   #define BELLBOARD_INTENCLR2_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4828 
4829 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
4830   #define BELLBOARD_INTENCLR2_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
4831   #define BELLBOARD_INTENCLR2_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
4832                                                                             field.*/
4833   #define BELLBOARD_INTENCLR2_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
4834   #define BELLBOARD_INTENCLR2_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
4835   #define BELLBOARD_INTENCLR2_TRIGGERED20_Clear (0x1UL) /*!< Disable                                                           */
4836   #define BELLBOARD_INTENCLR2_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4837   #define BELLBOARD_INTENCLR2_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4838 
4839 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
4840   #define BELLBOARD_INTENCLR2_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
4841   #define BELLBOARD_INTENCLR2_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
4842                                                                             field.*/
4843   #define BELLBOARD_INTENCLR2_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
4844   #define BELLBOARD_INTENCLR2_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
4845   #define BELLBOARD_INTENCLR2_TRIGGERED21_Clear (0x1UL) /*!< Disable                                                           */
4846   #define BELLBOARD_INTENCLR2_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4847   #define BELLBOARD_INTENCLR2_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4848 
4849 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
4850   #define BELLBOARD_INTENCLR2_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
4851   #define BELLBOARD_INTENCLR2_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
4852                                                                             field.*/
4853   #define BELLBOARD_INTENCLR2_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
4854   #define BELLBOARD_INTENCLR2_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
4855   #define BELLBOARD_INTENCLR2_TRIGGERED22_Clear (0x1UL) /*!< Disable                                                           */
4856   #define BELLBOARD_INTENCLR2_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4857   #define BELLBOARD_INTENCLR2_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4858 
4859 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
4860   #define BELLBOARD_INTENCLR2_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
4861   #define BELLBOARD_INTENCLR2_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
4862                                                                             field.*/
4863   #define BELLBOARD_INTENCLR2_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
4864   #define BELLBOARD_INTENCLR2_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
4865   #define BELLBOARD_INTENCLR2_TRIGGERED23_Clear (0x1UL) /*!< Disable                                                           */
4866   #define BELLBOARD_INTENCLR2_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4867   #define BELLBOARD_INTENCLR2_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4868 
4869 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
4870   #define BELLBOARD_INTENCLR2_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
4871   #define BELLBOARD_INTENCLR2_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
4872                                                                             field.*/
4873   #define BELLBOARD_INTENCLR2_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
4874   #define BELLBOARD_INTENCLR2_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
4875   #define BELLBOARD_INTENCLR2_TRIGGERED24_Clear (0x1UL) /*!< Disable                                                           */
4876   #define BELLBOARD_INTENCLR2_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4877   #define BELLBOARD_INTENCLR2_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4878 
4879 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
4880   #define BELLBOARD_INTENCLR2_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
4881   #define BELLBOARD_INTENCLR2_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
4882                                                                             field.*/
4883   #define BELLBOARD_INTENCLR2_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
4884   #define BELLBOARD_INTENCLR2_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
4885   #define BELLBOARD_INTENCLR2_TRIGGERED25_Clear (0x1UL) /*!< Disable                                                           */
4886   #define BELLBOARD_INTENCLR2_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4887   #define BELLBOARD_INTENCLR2_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4888 
4889 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
4890   #define BELLBOARD_INTENCLR2_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
4891   #define BELLBOARD_INTENCLR2_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
4892                                                                             field.*/
4893   #define BELLBOARD_INTENCLR2_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
4894   #define BELLBOARD_INTENCLR2_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
4895   #define BELLBOARD_INTENCLR2_TRIGGERED26_Clear (0x1UL) /*!< Disable                                                           */
4896   #define BELLBOARD_INTENCLR2_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4897   #define BELLBOARD_INTENCLR2_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4898 
4899 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
4900   #define BELLBOARD_INTENCLR2_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
4901   #define BELLBOARD_INTENCLR2_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
4902                                                                             field.*/
4903   #define BELLBOARD_INTENCLR2_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
4904   #define BELLBOARD_INTENCLR2_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
4905   #define BELLBOARD_INTENCLR2_TRIGGERED27_Clear (0x1UL) /*!< Disable                                                           */
4906   #define BELLBOARD_INTENCLR2_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4907   #define BELLBOARD_INTENCLR2_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4908 
4909 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
4910   #define BELLBOARD_INTENCLR2_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
4911   #define BELLBOARD_INTENCLR2_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
4912                                                                             field.*/
4913   #define BELLBOARD_INTENCLR2_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
4914   #define BELLBOARD_INTENCLR2_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
4915   #define BELLBOARD_INTENCLR2_TRIGGERED28_Clear (0x1UL) /*!< Disable                                                           */
4916   #define BELLBOARD_INTENCLR2_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4917   #define BELLBOARD_INTENCLR2_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4918 
4919 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
4920   #define BELLBOARD_INTENCLR2_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
4921   #define BELLBOARD_INTENCLR2_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
4922                                                                             field.*/
4923   #define BELLBOARD_INTENCLR2_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
4924   #define BELLBOARD_INTENCLR2_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
4925   #define BELLBOARD_INTENCLR2_TRIGGERED29_Clear (0x1UL) /*!< Disable                                                           */
4926   #define BELLBOARD_INTENCLR2_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4927   #define BELLBOARD_INTENCLR2_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4928 
4929 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
4930   #define BELLBOARD_INTENCLR2_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
4931   #define BELLBOARD_INTENCLR2_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
4932                                                                             field.*/
4933   #define BELLBOARD_INTENCLR2_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
4934   #define BELLBOARD_INTENCLR2_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
4935   #define BELLBOARD_INTENCLR2_TRIGGERED30_Clear (0x1UL) /*!< Disable                                                           */
4936   #define BELLBOARD_INTENCLR2_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4937   #define BELLBOARD_INTENCLR2_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4938 
4939 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
4940   #define BELLBOARD_INTENCLR2_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
4941   #define BELLBOARD_INTENCLR2_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR2_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
4942                                                                             field.*/
4943   #define BELLBOARD_INTENCLR2_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
4944   #define BELLBOARD_INTENCLR2_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
4945   #define BELLBOARD_INTENCLR2_TRIGGERED31_Clear (0x1UL) /*!< Disable                                                           */
4946   #define BELLBOARD_INTENCLR2_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
4947   #define BELLBOARD_INTENCLR2_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
4948 
4949 
4950 /* BELLBOARD_INTPEND2: Pending interrupts */
4951   #define BELLBOARD_INTPEND2_ResetValue (0x00000000UL) /*!< Reset value of INTPEND2 register.                                  */
4952 
4953 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
4954   #define BELLBOARD_INTPEND2_TRIGGERED0_Pos (0UL)    /*!< Position of TRIGGERED0 field.                                        */
4955   #define BELLBOARD_INTPEND2_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.    */
4956   #define BELLBOARD_INTPEND2_TRIGGERED0_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED0 field.                            */
4957   #define BELLBOARD_INTPEND2_TRIGGERED0_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED0 field.                            */
4958   #define BELLBOARD_INTPEND2_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending                                              */
4959   #define BELLBOARD_INTPEND2_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending                                                     */
4960 
4961 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
4962   #define BELLBOARD_INTPEND2_TRIGGERED1_Pos (1UL)    /*!< Position of TRIGGERED1 field.                                        */
4963   #define BELLBOARD_INTPEND2_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.    */
4964   #define BELLBOARD_INTPEND2_TRIGGERED1_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED1 field.                            */
4965   #define BELLBOARD_INTPEND2_TRIGGERED1_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED1 field.                            */
4966   #define BELLBOARD_INTPEND2_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending                                              */
4967   #define BELLBOARD_INTPEND2_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending                                                     */
4968 
4969 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
4970   #define BELLBOARD_INTPEND2_TRIGGERED2_Pos (2UL)    /*!< Position of TRIGGERED2 field.                                        */
4971   #define BELLBOARD_INTPEND2_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.    */
4972   #define BELLBOARD_INTPEND2_TRIGGERED2_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED2 field.                            */
4973   #define BELLBOARD_INTPEND2_TRIGGERED2_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED2 field.                            */
4974   #define BELLBOARD_INTPEND2_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending                                              */
4975   #define BELLBOARD_INTPEND2_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending                                                     */
4976 
4977 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
4978   #define BELLBOARD_INTPEND2_TRIGGERED3_Pos (3UL)    /*!< Position of TRIGGERED3 field.                                        */
4979   #define BELLBOARD_INTPEND2_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.    */
4980   #define BELLBOARD_INTPEND2_TRIGGERED3_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED3 field.                            */
4981   #define BELLBOARD_INTPEND2_TRIGGERED3_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED3 field.                            */
4982   #define BELLBOARD_INTPEND2_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending                                              */
4983   #define BELLBOARD_INTPEND2_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending                                                     */
4984 
4985 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
4986   #define BELLBOARD_INTPEND2_TRIGGERED4_Pos (4UL)    /*!< Position of TRIGGERED4 field.                                        */
4987   #define BELLBOARD_INTPEND2_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.    */
4988   #define BELLBOARD_INTPEND2_TRIGGERED4_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED4 field.                            */
4989   #define BELLBOARD_INTPEND2_TRIGGERED4_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED4 field.                            */
4990   #define BELLBOARD_INTPEND2_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending                                              */
4991   #define BELLBOARD_INTPEND2_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending                                                     */
4992 
4993 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
4994   #define BELLBOARD_INTPEND2_TRIGGERED5_Pos (5UL)    /*!< Position of TRIGGERED5 field.                                        */
4995   #define BELLBOARD_INTPEND2_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.    */
4996   #define BELLBOARD_INTPEND2_TRIGGERED5_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED5 field.                            */
4997   #define BELLBOARD_INTPEND2_TRIGGERED5_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED5 field.                            */
4998   #define BELLBOARD_INTPEND2_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending                                              */
4999   #define BELLBOARD_INTPEND2_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending                                                     */
5000 
5001 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
5002   #define BELLBOARD_INTPEND2_TRIGGERED6_Pos (6UL)    /*!< Position of TRIGGERED6 field.                                        */
5003   #define BELLBOARD_INTPEND2_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.    */
5004   #define BELLBOARD_INTPEND2_TRIGGERED6_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED6 field.                            */
5005   #define BELLBOARD_INTPEND2_TRIGGERED6_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED6 field.                            */
5006   #define BELLBOARD_INTPEND2_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending                                              */
5007   #define BELLBOARD_INTPEND2_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending                                                     */
5008 
5009 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
5010   #define BELLBOARD_INTPEND2_TRIGGERED7_Pos (7UL)    /*!< Position of TRIGGERED7 field.                                        */
5011   #define BELLBOARD_INTPEND2_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.    */
5012   #define BELLBOARD_INTPEND2_TRIGGERED7_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED7 field.                            */
5013   #define BELLBOARD_INTPEND2_TRIGGERED7_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED7 field.                            */
5014   #define BELLBOARD_INTPEND2_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending                                              */
5015   #define BELLBOARD_INTPEND2_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending                                                     */
5016 
5017 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
5018   #define BELLBOARD_INTPEND2_TRIGGERED8_Pos (8UL)    /*!< Position of TRIGGERED8 field.                                        */
5019   #define BELLBOARD_INTPEND2_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.    */
5020   #define BELLBOARD_INTPEND2_TRIGGERED8_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED8 field.                            */
5021   #define BELLBOARD_INTPEND2_TRIGGERED8_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED8 field.                            */
5022   #define BELLBOARD_INTPEND2_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending                                              */
5023   #define BELLBOARD_INTPEND2_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending                                                     */
5024 
5025 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
5026   #define BELLBOARD_INTPEND2_TRIGGERED9_Pos (9UL)    /*!< Position of TRIGGERED9 field.                                        */
5027   #define BELLBOARD_INTPEND2_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.    */
5028   #define BELLBOARD_INTPEND2_TRIGGERED9_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED9 field.                            */
5029   #define BELLBOARD_INTPEND2_TRIGGERED9_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED9 field.                            */
5030   #define BELLBOARD_INTPEND2_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending                                              */
5031   #define BELLBOARD_INTPEND2_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending                                                     */
5032 
5033 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
5034   #define BELLBOARD_INTPEND2_TRIGGERED10_Pos (10UL)  /*!< Position of TRIGGERED10 field.                                       */
5035   #define BELLBOARD_INTPEND2_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
5036   #define BELLBOARD_INTPEND2_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                           */
5037   #define BELLBOARD_INTPEND2_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                           */
5038   #define BELLBOARD_INTPEND2_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                             */
5039   #define BELLBOARD_INTPEND2_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending                                                    */
5040 
5041 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
5042   #define BELLBOARD_INTPEND2_TRIGGERED11_Pos (11UL)  /*!< Position of TRIGGERED11 field.                                       */
5043   #define BELLBOARD_INTPEND2_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
5044   #define BELLBOARD_INTPEND2_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                           */
5045   #define BELLBOARD_INTPEND2_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                           */
5046   #define BELLBOARD_INTPEND2_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                             */
5047   #define BELLBOARD_INTPEND2_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending                                                    */
5048 
5049 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
5050   #define BELLBOARD_INTPEND2_TRIGGERED12_Pos (12UL)  /*!< Position of TRIGGERED12 field.                                       */
5051   #define BELLBOARD_INTPEND2_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
5052   #define BELLBOARD_INTPEND2_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                           */
5053   #define BELLBOARD_INTPEND2_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                           */
5054   #define BELLBOARD_INTPEND2_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                             */
5055   #define BELLBOARD_INTPEND2_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending                                                    */
5056 
5057 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
5058   #define BELLBOARD_INTPEND2_TRIGGERED13_Pos (13UL)  /*!< Position of TRIGGERED13 field.                                       */
5059   #define BELLBOARD_INTPEND2_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
5060   #define BELLBOARD_INTPEND2_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                           */
5061   #define BELLBOARD_INTPEND2_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                           */
5062   #define BELLBOARD_INTPEND2_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                             */
5063   #define BELLBOARD_INTPEND2_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending                                                    */
5064 
5065 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
5066   #define BELLBOARD_INTPEND2_TRIGGERED14_Pos (14UL)  /*!< Position of TRIGGERED14 field.                                       */
5067   #define BELLBOARD_INTPEND2_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
5068   #define BELLBOARD_INTPEND2_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                           */
5069   #define BELLBOARD_INTPEND2_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                           */
5070   #define BELLBOARD_INTPEND2_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                             */
5071   #define BELLBOARD_INTPEND2_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending                                                    */
5072 
5073 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
5074   #define BELLBOARD_INTPEND2_TRIGGERED15_Pos (15UL)  /*!< Position of TRIGGERED15 field.                                       */
5075   #define BELLBOARD_INTPEND2_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
5076   #define BELLBOARD_INTPEND2_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                           */
5077   #define BELLBOARD_INTPEND2_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                           */
5078   #define BELLBOARD_INTPEND2_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                             */
5079   #define BELLBOARD_INTPEND2_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending                                                    */
5080 
5081 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
5082   #define BELLBOARD_INTPEND2_TRIGGERED16_Pos (16UL)  /*!< Position of TRIGGERED16 field.                                       */
5083   #define BELLBOARD_INTPEND2_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */
5084   #define BELLBOARD_INTPEND2_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                           */
5085   #define BELLBOARD_INTPEND2_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                           */
5086   #define BELLBOARD_INTPEND2_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                             */
5087   #define BELLBOARD_INTPEND2_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending                                                    */
5088 
5089 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
5090   #define BELLBOARD_INTPEND2_TRIGGERED17_Pos (17UL)  /*!< Position of TRIGGERED17 field.                                       */
5091   #define BELLBOARD_INTPEND2_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */
5092   #define BELLBOARD_INTPEND2_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                           */
5093   #define BELLBOARD_INTPEND2_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                           */
5094   #define BELLBOARD_INTPEND2_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                             */
5095   #define BELLBOARD_INTPEND2_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending                                                    */
5096 
5097 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
5098   #define BELLBOARD_INTPEND2_TRIGGERED18_Pos (18UL)  /*!< Position of TRIGGERED18 field.                                       */
5099   #define BELLBOARD_INTPEND2_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */
5100   #define BELLBOARD_INTPEND2_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                           */
5101   #define BELLBOARD_INTPEND2_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                           */
5102   #define BELLBOARD_INTPEND2_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                             */
5103   #define BELLBOARD_INTPEND2_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending                                                    */
5104 
5105 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
5106   #define BELLBOARD_INTPEND2_TRIGGERED19_Pos (19UL)  /*!< Position of TRIGGERED19 field.                                       */
5107   #define BELLBOARD_INTPEND2_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */
5108   #define BELLBOARD_INTPEND2_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                           */
5109   #define BELLBOARD_INTPEND2_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                           */
5110   #define BELLBOARD_INTPEND2_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                             */
5111   #define BELLBOARD_INTPEND2_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending                                                    */
5112 
5113 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
5114   #define BELLBOARD_INTPEND2_TRIGGERED20_Pos (20UL)  /*!< Position of TRIGGERED20 field.                                       */
5115   #define BELLBOARD_INTPEND2_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */
5116   #define BELLBOARD_INTPEND2_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                           */
5117   #define BELLBOARD_INTPEND2_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                           */
5118   #define BELLBOARD_INTPEND2_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                             */
5119   #define BELLBOARD_INTPEND2_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending                                                    */
5120 
5121 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
5122   #define BELLBOARD_INTPEND2_TRIGGERED21_Pos (21UL)  /*!< Position of TRIGGERED21 field.                                       */
5123   #define BELLBOARD_INTPEND2_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */
5124   #define BELLBOARD_INTPEND2_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                           */
5125   #define BELLBOARD_INTPEND2_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                           */
5126   #define BELLBOARD_INTPEND2_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                             */
5127   #define BELLBOARD_INTPEND2_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending                                                    */
5128 
5129 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
5130   #define BELLBOARD_INTPEND2_TRIGGERED22_Pos (22UL)  /*!< Position of TRIGGERED22 field.                                       */
5131   #define BELLBOARD_INTPEND2_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */
5132   #define BELLBOARD_INTPEND2_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                           */
5133   #define BELLBOARD_INTPEND2_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                           */
5134   #define BELLBOARD_INTPEND2_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                             */
5135   #define BELLBOARD_INTPEND2_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending                                                    */
5136 
5137 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
5138   #define BELLBOARD_INTPEND2_TRIGGERED23_Pos (23UL)  /*!< Position of TRIGGERED23 field.                                       */
5139   #define BELLBOARD_INTPEND2_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */
5140   #define BELLBOARD_INTPEND2_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                           */
5141   #define BELLBOARD_INTPEND2_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                           */
5142   #define BELLBOARD_INTPEND2_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                             */
5143   #define BELLBOARD_INTPEND2_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending                                                    */
5144 
5145 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
5146   #define BELLBOARD_INTPEND2_TRIGGERED24_Pos (24UL)  /*!< Position of TRIGGERED24 field.                                       */
5147   #define BELLBOARD_INTPEND2_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */
5148   #define BELLBOARD_INTPEND2_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                           */
5149   #define BELLBOARD_INTPEND2_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                           */
5150   #define BELLBOARD_INTPEND2_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                             */
5151   #define BELLBOARD_INTPEND2_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending                                                    */
5152 
5153 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
5154   #define BELLBOARD_INTPEND2_TRIGGERED25_Pos (25UL)  /*!< Position of TRIGGERED25 field.                                       */
5155   #define BELLBOARD_INTPEND2_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */
5156   #define BELLBOARD_INTPEND2_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                           */
5157   #define BELLBOARD_INTPEND2_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                           */
5158   #define BELLBOARD_INTPEND2_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                             */
5159   #define BELLBOARD_INTPEND2_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending                                                    */
5160 
5161 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
5162   #define BELLBOARD_INTPEND2_TRIGGERED26_Pos (26UL)  /*!< Position of TRIGGERED26 field.                                       */
5163   #define BELLBOARD_INTPEND2_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */
5164   #define BELLBOARD_INTPEND2_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                           */
5165   #define BELLBOARD_INTPEND2_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                           */
5166   #define BELLBOARD_INTPEND2_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                             */
5167   #define BELLBOARD_INTPEND2_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending                                                    */
5168 
5169 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
5170   #define BELLBOARD_INTPEND2_TRIGGERED27_Pos (27UL)  /*!< Position of TRIGGERED27 field.                                       */
5171   #define BELLBOARD_INTPEND2_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */
5172   #define BELLBOARD_INTPEND2_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                           */
5173   #define BELLBOARD_INTPEND2_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                           */
5174   #define BELLBOARD_INTPEND2_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                             */
5175   #define BELLBOARD_INTPEND2_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending                                                    */
5176 
5177 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
5178   #define BELLBOARD_INTPEND2_TRIGGERED28_Pos (28UL)  /*!< Position of TRIGGERED28 field.                                       */
5179   #define BELLBOARD_INTPEND2_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */
5180   #define BELLBOARD_INTPEND2_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                           */
5181   #define BELLBOARD_INTPEND2_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                           */
5182   #define BELLBOARD_INTPEND2_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                             */
5183   #define BELLBOARD_INTPEND2_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending                                                    */
5184 
5185 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
5186   #define BELLBOARD_INTPEND2_TRIGGERED29_Pos (29UL)  /*!< Position of TRIGGERED29 field.                                       */
5187   #define BELLBOARD_INTPEND2_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */
5188   #define BELLBOARD_INTPEND2_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                           */
5189   #define BELLBOARD_INTPEND2_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                           */
5190   #define BELLBOARD_INTPEND2_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                             */
5191   #define BELLBOARD_INTPEND2_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending                                                    */
5192 
5193 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
5194   #define BELLBOARD_INTPEND2_TRIGGERED30_Pos (30UL)  /*!< Position of TRIGGERED30 field.                                       */
5195   #define BELLBOARD_INTPEND2_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */
5196   #define BELLBOARD_INTPEND2_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                           */
5197   #define BELLBOARD_INTPEND2_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                           */
5198   #define BELLBOARD_INTPEND2_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                             */
5199   #define BELLBOARD_INTPEND2_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending                                                    */
5200 
5201 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
5202   #define BELLBOARD_INTPEND2_TRIGGERED31_Pos (31UL)  /*!< Position of TRIGGERED31 field.                                       */
5203   #define BELLBOARD_INTPEND2_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND2_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */
5204   #define BELLBOARD_INTPEND2_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                           */
5205   #define BELLBOARD_INTPEND2_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                           */
5206   #define BELLBOARD_INTPEND2_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                             */
5207   #define BELLBOARD_INTPEND2_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending                                                    */
5208 
5209 
5210 /* BELLBOARD_INTEN3: Enable or disable interrupt */
5211   #define BELLBOARD_INTEN3_ResetValue (0x00000000UL) /*!< Reset value of INTEN3 register.                                      */
5212 
5213 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
5214   #define BELLBOARD_INTEN3_TRIGGERED0_Pos (0UL)      /*!< Position of TRIGGERED0 field.                                        */
5215   #define BELLBOARD_INTEN3_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.        */
5216   #define BELLBOARD_INTEN3_TRIGGERED0_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED0 field.                            */
5217   #define BELLBOARD_INTEN3_TRIGGERED0_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED0 field.                            */
5218   #define BELLBOARD_INTEN3_TRIGGERED0_Disabled (0x0UL) /*!< Disable                                                            */
5219   #define BELLBOARD_INTEN3_TRIGGERED0_Enabled (0x1UL) /*!< Enable                                                              */
5220 
5221 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
5222   #define BELLBOARD_INTEN3_TRIGGERED1_Pos (1UL)      /*!< Position of TRIGGERED1 field.                                        */
5223   #define BELLBOARD_INTEN3_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.        */
5224   #define BELLBOARD_INTEN3_TRIGGERED1_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED1 field.                            */
5225   #define BELLBOARD_INTEN3_TRIGGERED1_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED1 field.                            */
5226   #define BELLBOARD_INTEN3_TRIGGERED1_Disabled (0x0UL) /*!< Disable                                                            */
5227   #define BELLBOARD_INTEN3_TRIGGERED1_Enabled (0x1UL) /*!< Enable                                                              */
5228 
5229 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
5230   #define BELLBOARD_INTEN3_TRIGGERED2_Pos (2UL)      /*!< Position of TRIGGERED2 field.                                        */
5231   #define BELLBOARD_INTEN3_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.        */
5232   #define BELLBOARD_INTEN3_TRIGGERED2_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED2 field.                            */
5233   #define BELLBOARD_INTEN3_TRIGGERED2_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED2 field.                            */
5234   #define BELLBOARD_INTEN3_TRIGGERED2_Disabled (0x0UL) /*!< Disable                                                            */
5235   #define BELLBOARD_INTEN3_TRIGGERED2_Enabled (0x1UL) /*!< Enable                                                              */
5236 
5237 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
5238   #define BELLBOARD_INTEN3_TRIGGERED3_Pos (3UL)      /*!< Position of TRIGGERED3 field.                                        */
5239   #define BELLBOARD_INTEN3_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.        */
5240   #define BELLBOARD_INTEN3_TRIGGERED3_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED3 field.                            */
5241   #define BELLBOARD_INTEN3_TRIGGERED3_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED3 field.                            */
5242   #define BELLBOARD_INTEN3_TRIGGERED3_Disabled (0x0UL) /*!< Disable                                                            */
5243   #define BELLBOARD_INTEN3_TRIGGERED3_Enabled (0x1UL) /*!< Enable                                                              */
5244 
5245 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
5246   #define BELLBOARD_INTEN3_TRIGGERED4_Pos (4UL)      /*!< Position of TRIGGERED4 field.                                        */
5247   #define BELLBOARD_INTEN3_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.        */
5248   #define BELLBOARD_INTEN3_TRIGGERED4_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED4 field.                            */
5249   #define BELLBOARD_INTEN3_TRIGGERED4_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED4 field.                            */
5250   #define BELLBOARD_INTEN3_TRIGGERED4_Disabled (0x0UL) /*!< Disable                                                            */
5251   #define BELLBOARD_INTEN3_TRIGGERED4_Enabled (0x1UL) /*!< Enable                                                              */
5252 
5253 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
5254   #define BELLBOARD_INTEN3_TRIGGERED5_Pos (5UL)      /*!< Position of TRIGGERED5 field.                                        */
5255   #define BELLBOARD_INTEN3_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.        */
5256   #define BELLBOARD_INTEN3_TRIGGERED5_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED5 field.                            */
5257   #define BELLBOARD_INTEN3_TRIGGERED5_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED5 field.                            */
5258   #define BELLBOARD_INTEN3_TRIGGERED5_Disabled (0x0UL) /*!< Disable                                                            */
5259   #define BELLBOARD_INTEN3_TRIGGERED5_Enabled (0x1UL) /*!< Enable                                                              */
5260 
5261 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
5262   #define BELLBOARD_INTEN3_TRIGGERED6_Pos (6UL)      /*!< Position of TRIGGERED6 field.                                        */
5263   #define BELLBOARD_INTEN3_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.        */
5264   #define BELLBOARD_INTEN3_TRIGGERED6_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED6 field.                            */
5265   #define BELLBOARD_INTEN3_TRIGGERED6_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED6 field.                            */
5266   #define BELLBOARD_INTEN3_TRIGGERED6_Disabled (0x0UL) /*!< Disable                                                            */
5267   #define BELLBOARD_INTEN3_TRIGGERED6_Enabled (0x1UL) /*!< Enable                                                              */
5268 
5269 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
5270   #define BELLBOARD_INTEN3_TRIGGERED7_Pos (7UL)      /*!< Position of TRIGGERED7 field.                                        */
5271   #define BELLBOARD_INTEN3_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.        */
5272   #define BELLBOARD_INTEN3_TRIGGERED7_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED7 field.                            */
5273   #define BELLBOARD_INTEN3_TRIGGERED7_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED7 field.                            */
5274   #define BELLBOARD_INTEN3_TRIGGERED7_Disabled (0x0UL) /*!< Disable                                                            */
5275   #define BELLBOARD_INTEN3_TRIGGERED7_Enabled (0x1UL) /*!< Enable                                                              */
5276 
5277 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
5278   #define BELLBOARD_INTEN3_TRIGGERED8_Pos (8UL)      /*!< Position of TRIGGERED8 field.                                        */
5279   #define BELLBOARD_INTEN3_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.        */
5280   #define BELLBOARD_INTEN3_TRIGGERED8_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED8 field.                            */
5281   #define BELLBOARD_INTEN3_TRIGGERED8_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED8 field.                            */
5282   #define BELLBOARD_INTEN3_TRIGGERED8_Disabled (0x0UL) /*!< Disable                                                            */
5283   #define BELLBOARD_INTEN3_TRIGGERED8_Enabled (0x1UL) /*!< Enable                                                              */
5284 
5285 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
5286   #define BELLBOARD_INTEN3_TRIGGERED9_Pos (9UL)      /*!< Position of TRIGGERED9 field.                                        */
5287   #define BELLBOARD_INTEN3_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.        */
5288   #define BELLBOARD_INTEN3_TRIGGERED9_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED9 field.                            */
5289   #define BELLBOARD_INTEN3_TRIGGERED9_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED9 field.                            */
5290   #define BELLBOARD_INTEN3_TRIGGERED9_Disabled (0x0UL) /*!< Disable                                                            */
5291   #define BELLBOARD_INTEN3_TRIGGERED9_Enabled (0x1UL) /*!< Enable                                                              */
5292 
5293 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
5294   #define BELLBOARD_INTEN3_TRIGGERED10_Pos (10UL)    /*!< Position of TRIGGERED10 field.                                       */
5295   #define BELLBOARD_INTEN3_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.     */
5296   #define BELLBOARD_INTEN3_TRIGGERED10_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED10 field.                           */
5297   #define BELLBOARD_INTEN3_TRIGGERED10_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED10 field.                           */
5298   #define BELLBOARD_INTEN3_TRIGGERED10_Disabled (0x0UL) /*!< Disable                                                           */
5299   #define BELLBOARD_INTEN3_TRIGGERED10_Enabled (0x1UL) /*!< Enable                                                             */
5300 
5301 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
5302   #define BELLBOARD_INTEN3_TRIGGERED11_Pos (11UL)    /*!< Position of TRIGGERED11 field.                                       */
5303   #define BELLBOARD_INTEN3_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.     */
5304   #define BELLBOARD_INTEN3_TRIGGERED11_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED11 field.                           */
5305   #define BELLBOARD_INTEN3_TRIGGERED11_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED11 field.                           */
5306   #define BELLBOARD_INTEN3_TRIGGERED11_Disabled (0x0UL) /*!< Disable                                                           */
5307   #define BELLBOARD_INTEN3_TRIGGERED11_Enabled (0x1UL) /*!< Enable                                                             */
5308 
5309 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
5310   #define BELLBOARD_INTEN3_TRIGGERED12_Pos (12UL)    /*!< Position of TRIGGERED12 field.                                       */
5311   #define BELLBOARD_INTEN3_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.     */
5312   #define BELLBOARD_INTEN3_TRIGGERED12_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED12 field.                           */
5313   #define BELLBOARD_INTEN3_TRIGGERED12_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED12 field.                           */
5314   #define BELLBOARD_INTEN3_TRIGGERED12_Disabled (0x0UL) /*!< Disable                                                           */
5315   #define BELLBOARD_INTEN3_TRIGGERED12_Enabled (0x1UL) /*!< Enable                                                             */
5316 
5317 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
5318   #define BELLBOARD_INTEN3_TRIGGERED13_Pos (13UL)    /*!< Position of TRIGGERED13 field.                                       */
5319   #define BELLBOARD_INTEN3_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.     */
5320   #define BELLBOARD_INTEN3_TRIGGERED13_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED13 field.                           */
5321   #define BELLBOARD_INTEN3_TRIGGERED13_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED13 field.                           */
5322   #define BELLBOARD_INTEN3_TRIGGERED13_Disabled (0x0UL) /*!< Disable                                                           */
5323   #define BELLBOARD_INTEN3_TRIGGERED13_Enabled (0x1UL) /*!< Enable                                                             */
5324 
5325 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
5326   #define BELLBOARD_INTEN3_TRIGGERED14_Pos (14UL)    /*!< Position of TRIGGERED14 field.                                       */
5327   #define BELLBOARD_INTEN3_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.     */
5328   #define BELLBOARD_INTEN3_TRIGGERED14_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED14 field.                           */
5329   #define BELLBOARD_INTEN3_TRIGGERED14_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED14 field.                           */
5330   #define BELLBOARD_INTEN3_TRIGGERED14_Disabled (0x0UL) /*!< Disable                                                           */
5331   #define BELLBOARD_INTEN3_TRIGGERED14_Enabled (0x1UL) /*!< Enable                                                             */
5332 
5333 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
5334   #define BELLBOARD_INTEN3_TRIGGERED15_Pos (15UL)    /*!< Position of TRIGGERED15 field.                                       */
5335   #define BELLBOARD_INTEN3_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.     */
5336   #define BELLBOARD_INTEN3_TRIGGERED15_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED15 field.                           */
5337   #define BELLBOARD_INTEN3_TRIGGERED15_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED15 field.                           */
5338   #define BELLBOARD_INTEN3_TRIGGERED15_Disabled (0x0UL) /*!< Disable                                                           */
5339   #define BELLBOARD_INTEN3_TRIGGERED15_Enabled (0x1UL) /*!< Enable                                                             */
5340 
5341 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
5342   #define BELLBOARD_INTEN3_TRIGGERED16_Pos (16UL)    /*!< Position of TRIGGERED16 field.                                       */
5343   #define BELLBOARD_INTEN3_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.     */
5344   #define BELLBOARD_INTEN3_TRIGGERED16_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED16 field.                           */
5345   #define BELLBOARD_INTEN3_TRIGGERED16_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED16 field.                           */
5346   #define BELLBOARD_INTEN3_TRIGGERED16_Disabled (0x0UL) /*!< Disable                                                           */
5347   #define BELLBOARD_INTEN3_TRIGGERED16_Enabled (0x1UL) /*!< Enable                                                             */
5348 
5349 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
5350   #define BELLBOARD_INTEN3_TRIGGERED17_Pos (17UL)    /*!< Position of TRIGGERED17 field.                                       */
5351   #define BELLBOARD_INTEN3_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.     */
5352   #define BELLBOARD_INTEN3_TRIGGERED17_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED17 field.                           */
5353   #define BELLBOARD_INTEN3_TRIGGERED17_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED17 field.                           */
5354   #define BELLBOARD_INTEN3_TRIGGERED17_Disabled (0x0UL) /*!< Disable                                                           */
5355   #define BELLBOARD_INTEN3_TRIGGERED17_Enabled (0x1UL) /*!< Enable                                                             */
5356 
5357 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
5358   #define BELLBOARD_INTEN3_TRIGGERED18_Pos (18UL)    /*!< Position of TRIGGERED18 field.                                       */
5359   #define BELLBOARD_INTEN3_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.     */
5360   #define BELLBOARD_INTEN3_TRIGGERED18_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED18 field.                           */
5361   #define BELLBOARD_INTEN3_TRIGGERED18_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED18 field.                           */
5362   #define BELLBOARD_INTEN3_TRIGGERED18_Disabled (0x0UL) /*!< Disable                                                           */
5363   #define BELLBOARD_INTEN3_TRIGGERED18_Enabled (0x1UL) /*!< Enable                                                             */
5364 
5365 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
5366   #define BELLBOARD_INTEN3_TRIGGERED19_Pos (19UL)    /*!< Position of TRIGGERED19 field.                                       */
5367   #define BELLBOARD_INTEN3_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.     */
5368   #define BELLBOARD_INTEN3_TRIGGERED19_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED19 field.                           */
5369   #define BELLBOARD_INTEN3_TRIGGERED19_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED19 field.                           */
5370   #define BELLBOARD_INTEN3_TRIGGERED19_Disabled (0x0UL) /*!< Disable                                                           */
5371   #define BELLBOARD_INTEN3_TRIGGERED19_Enabled (0x1UL) /*!< Enable                                                             */
5372 
5373 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
5374   #define BELLBOARD_INTEN3_TRIGGERED20_Pos (20UL)    /*!< Position of TRIGGERED20 field.                                       */
5375   #define BELLBOARD_INTEN3_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.     */
5376   #define BELLBOARD_INTEN3_TRIGGERED20_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED20 field.                           */
5377   #define BELLBOARD_INTEN3_TRIGGERED20_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED20 field.                           */
5378   #define BELLBOARD_INTEN3_TRIGGERED20_Disabled (0x0UL) /*!< Disable                                                           */
5379   #define BELLBOARD_INTEN3_TRIGGERED20_Enabled (0x1UL) /*!< Enable                                                             */
5380 
5381 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
5382   #define BELLBOARD_INTEN3_TRIGGERED21_Pos (21UL)    /*!< Position of TRIGGERED21 field.                                       */
5383   #define BELLBOARD_INTEN3_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.     */
5384   #define BELLBOARD_INTEN3_TRIGGERED21_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED21 field.                           */
5385   #define BELLBOARD_INTEN3_TRIGGERED21_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED21 field.                           */
5386   #define BELLBOARD_INTEN3_TRIGGERED21_Disabled (0x0UL) /*!< Disable                                                           */
5387   #define BELLBOARD_INTEN3_TRIGGERED21_Enabled (0x1UL) /*!< Enable                                                             */
5388 
5389 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
5390   #define BELLBOARD_INTEN3_TRIGGERED22_Pos (22UL)    /*!< Position of TRIGGERED22 field.                                       */
5391   #define BELLBOARD_INTEN3_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.     */
5392   #define BELLBOARD_INTEN3_TRIGGERED22_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED22 field.                           */
5393   #define BELLBOARD_INTEN3_TRIGGERED22_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED22 field.                           */
5394   #define BELLBOARD_INTEN3_TRIGGERED22_Disabled (0x0UL) /*!< Disable                                                           */
5395   #define BELLBOARD_INTEN3_TRIGGERED22_Enabled (0x1UL) /*!< Enable                                                             */
5396 
5397 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
5398   #define BELLBOARD_INTEN3_TRIGGERED23_Pos (23UL)    /*!< Position of TRIGGERED23 field.                                       */
5399   #define BELLBOARD_INTEN3_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.     */
5400   #define BELLBOARD_INTEN3_TRIGGERED23_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED23 field.                           */
5401   #define BELLBOARD_INTEN3_TRIGGERED23_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED23 field.                           */
5402   #define BELLBOARD_INTEN3_TRIGGERED23_Disabled (0x0UL) /*!< Disable                                                           */
5403   #define BELLBOARD_INTEN3_TRIGGERED23_Enabled (0x1UL) /*!< Enable                                                             */
5404 
5405 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
5406   #define BELLBOARD_INTEN3_TRIGGERED24_Pos (24UL)    /*!< Position of TRIGGERED24 field.                                       */
5407   #define BELLBOARD_INTEN3_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.     */
5408   #define BELLBOARD_INTEN3_TRIGGERED24_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED24 field.                           */
5409   #define BELLBOARD_INTEN3_TRIGGERED24_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED24 field.                           */
5410   #define BELLBOARD_INTEN3_TRIGGERED24_Disabled (0x0UL) /*!< Disable                                                           */
5411   #define BELLBOARD_INTEN3_TRIGGERED24_Enabled (0x1UL) /*!< Enable                                                             */
5412 
5413 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
5414   #define BELLBOARD_INTEN3_TRIGGERED25_Pos (25UL)    /*!< Position of TRIGGERED25 field.                                       */
5415   #define BELLBOARD_INTEN3_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.     */
5416   #define BELLBOARD_INTEN3_TRIGGERED25_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED25 field.                           */
5417   #define BELLBOARD_INTEN3_TRIGGERED25_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED25 field.                           */
5418   #define BELLBOARD_INTEN3_TRIGGERED25_Disabled (0x0UL) /*!< Disable                                                           */
5419   #define BELLBOARD_INTEN3_TRIGGERED25_Enabled (0x1UL) /*!< Enable                                                             */
5420 
5421 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
5422   #define BELLBOARD_INTEN3_TRIGGERED26_Pos (26UL)    /*!< Position of TRIGGERED26 field.                                       */
5423   #define BELLBOARD_INTEN3_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.     */
5424   #define BELLBOARD_INTEN3_TRIGGERED26_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED26 field.                           */
5425   #define BELLBOARD_INTEN3_TRIGGERED26_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED26 field.                           */
5426   #define BELLBOARD_INTEN3_TRIGGERED26_Disabled (0x0UL) /*!< Disable                                                           */
5427   #define BELLBOARD_INTEN3_TRIGGERED26_Enabled (0x1UL) /*!< Enable                                                             */
5428 
5429 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
5430   #define BELLBOARD_INTEN3_TRIGGERED27_Pos (27UL)    /*!< Position of TRIGGERED27 field.                                       */
5431   #define BELLBOARD_INTEN3_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.     */
5432   #define BELLBOARD_INTEN3_TRIGGERED27_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED27 field.                           */
5433   #define BELLBOARD_INTEN3_TRIGGERED27_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED27 field.                           */
5434   #define BELLBOARD_INTEN3_TRIGGERED27_Disabled (0x0UL) /*!< Disable                                                           */
5435   #define BELLBOARD_INTEN3_TRIGGERED27_Enabled (0x1UL) /*!< Enable                                                             */
5436 
5437 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
5438   #define BELLBOARD_INTEN3_TRIGGERED28_Pos (28UL)    /*!< Position of TRIGGERED28 field.                                       */
5439   #define BELLBOARD_INTEN3_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.     */
5440   #define BELLBOARD_INTEN3_TRIGGERED28_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED28 field.                           */
5441   #define BELLBOARD_INTEN3_TRIGGERED28_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED28 field.                           */
5442   #define BELLBOARD_INTEN3_TRIGGERED28_Disabled (0x0UL) /*!< Disable                                                           */
5443   #define BELLBOARD_INTEN3_TRIGGERED28_Enabled (0x1UL) /*!< Enable                                                             */
5444 
5445 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
5446   #define BELLBOARD_INTEN3_TRIGGERED29_Pos (29UL)    /*!< Position of TRIGGERED29 field.                                       */
5447   #define BELLBOARD_INTEN3_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.     */
5448   #define BELLBOARD_INTEN3_TRIGGERED29_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED29 field.                           */
5449   #define BELLBOARD_INTEN3_TRIGGERED29_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED29 field.                           */
5450   #define BELLBOARD_INTEN3_TRIGGERED29_Disabled (0x0UL) /*!< Disable                                                           */
5451   #define BELLBOARD_INTEN3_TRIGGERED29_Enabled (0x1UL) /*!< Enable                                                             */
5452 
5453 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
5454   #define BELLBOARD_INTEN3_TRIGGERED30_Pos (30UL)    /*!< Position of TRIGGERED30 field.                                       */
5455   #define BELLBOARD_INTEN3_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.     */
5456   #define BELLBOARD_INTEN3_TRIGGERED30_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED30 field.                           */
5457   #define BELLBOARD_INTEN3_TRIGGERED30_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED30 field.                           */
5458   #define BELLBOARD_INTEN3_TRIGGERED30_Disabled (0x0UL) /*!< Disable                                                           */
5459   #define BELLBOARD_INTEN3_TRIGGERED30_Enabled (0x1UL) /*!< Enable                                                             */
5460 
5461 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
5462   #define BELLBOARD_INTEN3_TRIGGERED31_Pos (31UL)    /*!< Position of TRIGGERED31 field.                                       */
5463   #define BELLBOARD_INTEN3_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN3_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.     */
5464   #define BELLBOARD_INTEN3_TRIGGERED31_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED31 field.                           */
5465   #define BELLBOARD_INTEN3_TRIGGERED31_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED31 field.                           */
5466   #define BELLBOARD_INTEN3_TRIGGERED31_Disabled (0x0UL) /*!< Disable                                                           */
5467   #define BELLBOARD_INTEN3_TRIGGERED31_Enabled (0x1UL) /*!< Enable                                                             */
5468 
5469 
5470 /* BELLBOARD_INTENSET3: Enable interrupt */
5471   #define BELLBOARD_INTENSET3_ResetValue (0x00000000UL) /*!< Reset value of INTENSET3 register.                                */
5472 
5473 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
5474   #define BELLBOARD_INTENSET3_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
5475   #define BELLBOARD_INTENSET3_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
5476   #define BELLBOARD_INTENSET3_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
5477   #define BELLBOARD_INTENSET3_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
5478   #define BELLBOARD_INTENSET3_TRIGGERED0_Set (0x1UL) /*!< Enable                                                               */
5479   #define BELLBOARD_INTENSET3_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5480   #define BELLBOARD_INTENSET3_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5481 
5482 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
5483   #define BELLBOARD_INTENSET3_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
5484   #define BELLBOARD_INTENSET3_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
5485   #define BELLBOARD_INTENSET3_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
5486   #define BELLBOARD_INTENSET3_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
5487   #define BELLBOARD_INTENSET3_TRIGGERED1_Set (0x1UL) /*!< Enable                                                               */
5488   #define BELLBOARD_INTENSET3_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5489   #define BELLBOARD_INTENSET3_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5490 
5491 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
5492   #define BELLBOARD_INTENSET3_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
5493   #define BELLBOARD_INTENSET3_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
5494   #define BELLBOARD_INTENSET3_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
5495   #define BELLBOARD_INTENSET3_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
5496   #define BELLBOARD_INTENSET3_TRIGGERED2_Set (0x1UL) /*!< Enable                                                               */
5497   #define BELLBOARD_INTENSET3_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5498   #define BELLBOARD_INTENSET3_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5499 
5500 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
5501   #define BELLBOARD_INTENSET3_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
5502   #define BELLBOARD_INTENSET3_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
5503   #define BELLBOARD_INTENSET3_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
5504   #define BELLBOARD_INTENSET3_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
5505   #define BELLBOARD_INTENSET3_TRIGGERED3_Set (0x1UL) /*!< Enable                                                               */
5506   #define BELLBOARD_INTENSET3_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5507   #define BELLBOARD_INTENSET3_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5508 
5509 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
5510   #define BELLBOARD_INTENSET3_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
5511   #define BELLBOARD_INTENSET3_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
5512   #define BELLBOARD_INTENSET3_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
5513   #define BELLBOARD_INTENSET3_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
5514   #define BELLBOARD_INTENSET3_TRIGGERED4_Set (0x1UL) /*!< Enable                                                               */
5515   #define BELLBOARD_INTENSET3_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5516   #define BELLBOARD_INTENSET3_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5517 
5518 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
5519   #define BELLBOARD_INTENSET3_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
5520   #define BELLBOARD_INTENSET3_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
5521   #define BELLBOARD_INTENSET3_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
5522   #define BELLBOARD_INTENSET3_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
5523   #define BELLBOARD_INTENSET3_TRIGGERED5_Set (0x1UL) /*!< Enable                                                               */
5524   #define BELLBOARD_INTENSET3_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5525   #define BELLBOARD_INTENSET3_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5526 
5527 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
5528   #define BELLBOARD_INTENSET3_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
5529   #define BELLBOARD_INTENSET3_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
5530   #define BELLBOARD_INTENSET3_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
5531   #define BELLBOARD_INTENSET3_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
5532   #define BELLBOARD_INTENSET3_TRIGGERED6_Set (0x1UL) /*!< Enable                                                               */
5533   #define BELLBOARD_INTENSET3_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5534   #define BELLBOARD_INTENSET3_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5535 
5536 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
5537   #define BELLBOARD_INTENSET3_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
5538   #define BELLBOARD_INTENSET3_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
5539   #define BELLBOARD_INTENSET3_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
5540   #define BELLBOARD_INTENSET3_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
5541   #define BELLBOARD_INTENSET3_TRIGGERED7_Set (0x1UL) /*!< Enable                                                               */
5542   #define BELLBOARD_INTENSET3_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5543   #define BELLBOARD_INTENSET3_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5544 
5545 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
5546   #define BELLBOARD_INTENSET3_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
5547   #define BELLBOARD_INTENSET3_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
5548   #define BELLBOARD_INTENSET3_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
5549   #define BELLBOARD_INTENSET3_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
5550   #define BELLBOARD_INTENSET3_TRIGGERED8_Set (0x1UL) /*!< Enable                                                               */
5551   #define BELLBOARD_INTENSET3_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5552   #define BELLBOARD_INTENSET3_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5553 
5554 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
5555   #define BELLBOARD_INTENSET3_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
5556   #define BELLBOARD_INTENSET3_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
5557   #define BELLBOARD_INTENSET3_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
5558   #define BELLBOARD_INTENSET3_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
5559   #define BELLBOARD_INTENSET3_TRIGGERED9_Set (0x1UL) /*!< Enable                                                               */
5560   #define BELLBOARD_INTENSET3_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5561   #define BELLBOARD_INTENSET3_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5562 
5563 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
5564   #define BELLBOARD_INTENSET3_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
5565   #define BELLBOARD_INTENSET3_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
5566                                                                             field.*/
5567   #define BELLBOARD_INTENSET3_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
5568   #define BELLBOARD_INTENSET3_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
5569   #define BELLBOARD_INTENSET3_TRIGGERED10_Set (0x1UL) /*!< Enable                                                              */
5570   #define BELLBOARD_INTENSET3_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5571   #define BELLBOARD_INTENSET3_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5572 
5573 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
5574   #define BELLBOARD_INTENSET3_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
5575   #define BELLBOARD_INTENSET3_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
5576                                                                             field.*/
5577   #define BELLBOARD_INTENSET3_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
5578   #define BELLBOARD_INTENSET3_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
5579   #define BELLBOARD_INTENSET3_TRIGGERED11_Set (0x1UL) /*!< Enable                                                              */
5580   #define BELLBOARD_INTENSET3_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5581   #define BELLBOARD_INTENSET3_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5582 
5583 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
5584   #define BELLBOARD_INTENSET3_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
5585   #define BELLBOARD_INTENSET3_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
5586                                                                             field.*/
5587   #define BELLBOARD_INTENSET3_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
5588   #define BELLBOARD_INTENSET3_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
5589   #define BELLBOARD_INTENSET3_TRIGGERED12_Set (0x1UL) /*!< Enable                                                              */
5590   #define BELLBOARD_INTENSET3_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5591   #define BELLBOARD_INTENSET3_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5592 
5593 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
5594   #define BELLBOARD_INTENSET3_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
5595   #define BELLBOARD_INTENSET3_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
5596                                                                             field.*/
5597   #define BELLBOARD_INTENSET3_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
5598   #define BELLBOARD_INTENSET3_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
5599   #define BELLBOARD_INTENSET3_TRIGGERED13_Set (0x1UL) /*!< Enable                                                              */
5600   #define BELLBOARD_INTENSET3_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5601   #define BELLBOARD_INTENSET3_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5602 
5603 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
5604   #define BELLBOARD_INTENSET3_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
5605   #define BELLBOARD_INTENSET3_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
5606                                                                             field.*/
5607   #define BELLBOARD_INTENSET3_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
5608   #define BELLBOARD_INTENSET3_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
5609   #define BELLBOARD_INTENSET3_TRIGGERED14_Set (0x1UL) /*!< Enable                                                              */
5610   #define BELLBOARD_INTENSET3_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5611   #define BELLBOARD_INTENSET3_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5612 
5613 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
5614   #define BELLBOARD_INTENSET3_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
5615   #define BELLBOARD_INTENSET3_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
5616                                                                             field.*/
5617   #define BELLBOARD_INTENSET3_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
5618   #define BELLBOARD_INTENSET3_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
5619   #define BELLBOARD_INTENSET3_TRIGGERED15_Set (0x1UL) /*!< Enable                                                              */
5620   #define BELLBOARD_INTENSET3_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5621   #define BELLBOARD_INTENSET3_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5622 
5623 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
5624   #define BELLBOARD_INTENSET3_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
5625   #define BELLBOARD_INTENSET3_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
5626                                                                             field.*/
5627   #define BELLBOARD_INTENSET3_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
5628   #define BELLBOARD_INTENSET3_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
5629   #define BELLBOARD_INTENSET3_TRIGGERED16_Set (0x1UL) /*!< Enable                                                              */
5630   #define BELLBOARD_INTENSET3_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5631   #define BELLBOARD_INTENSET3_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5632 
5633 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
5634   #define BELLBOARD_INTENSET3_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
5635   #define BELLBOARD_INTENSET3_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
5636                                                                             field.*/
5637   #define BELLBOARD_INTENSET3_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
5638   #define BELLBOARD_INTENSET3_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
5639   #define BELLBOARD_INTENSET3_TRIGGERED17_Set (0x1UL) /*!< Enable                                                              */
5640   #define BELLBOARD_INTENSET3_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5641   #define BELLBOARD_INTENSET3_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5642 
5643 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
5644   #define BELLBOARD_INTENSET3_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
5645   #define BELLBOARD_INTENSET3_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
5646                                                                             field.*/
5647   #define BELLBOARD_INTENSET3_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
5648   #define BELLBOARD_INTENSET3_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
5649   #define BELLBOARD_INTENSET3_TRIGGERED18_Set (0x1UL) /*!< Enable                                                              */
5650   #define BELLBOARD_INTENSET3_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5651   #define BELLBOARD_INTENSET3_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5652 
5653 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
5654   #define BELLBOARD_INTENSET3_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
5655   #define BELLBOARD_INTENSET3_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
5656                                                                             field.*/
5657   #define BELLBOARD_INTENSET3_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
5658   #define BELLBOARD_INTENSET3_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
5659   #define BELLBOARD_INTENSET3_TRIGGERED19_Set (0x1UL) /*!< Enable                                                              */
5660   #define BELLBOARD_INTENSET3_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5661   #define BELLBOARD_INTENSET3_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5662 
5663 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
5664   #define BELLBOARD_INTENSET3_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
5665   #define BELLBOARD_INTENSET3_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
5666                                                                             field.*/
5667   #define BELLBOARD_INTENSET3_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
5668   #define BELLBOARD_INTENSET3_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
5669   #define BELLBOARD_INTENSET3_TRIGGERED20_Set (0x1UL) /*!< Enable                                                              */
5670   #define BELLBOARD_INTENSET3_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5671   #define BELLBOARD_INTENSET3_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5672 
5673 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
5674   #define BELLBOARD_INTENSET3_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
5675   #define BELLBOARD_INTENSET3_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
5676                                                                             field.*/
5677   #define BELLBOARD_INTENSET3_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
5678   #define BELLBOARD_INTENSET3_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
5679   #define BELLBOARD_INTENSET3_TRIGGERED21_Set (0x1UL) /*!< Enable                                                              */
5680   #define BELLBOARD_INTENSET3_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5681   #define BELLBOARD_INTENSET3_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5682 
5683 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
5684   #define BELLBOARD_INTENSET3_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
5685   #define BELLBOARD_INTENSET3_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
5686                                                                             field.*/
5687   #define BELLBOARD_INTENSET3_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
5688   #define BELLBOARD_INTENSET3_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
5689   #define BELLBOARD_INTENSET3_TRIGGERED22_Set (0x1UL) /*!< Enable                                                              */
5690   #define BELLBOARD_INTENSET3_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5691   #define BELLBOARD_INTENSET3_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5692 
5693 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
5694   #define BELLBOARD_INTENSET3_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
5695   #define BELLBOARD_INTENSET3_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
5696                                                                             field.*/
5697   #define BELLBOARD_INTENSET3_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
5698   #define BELLBOARD_INTENSET3_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
5699   #define BELLBOARD_INTENSET3_TRIGGERED23_Set (0x1UL) /*!< Enable                                                              */
5700   #define BELLBOARD_INTENSET3_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5701   #define BELLBOARD_INTENSET3_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5702 
5703 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
5704   #define BELLBOARD_INTENSET3_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
5705   #define BELLBOARD_INTENSET3_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
5706                                                                             field.*/
5707   #define BELLBOARD_INTENSET3_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
5708   #define BELLBOARD_INTENSET3_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
5709   #define BELLBOARD_INTENSET3_TRIGGERED24_Set (0x1UL) /*!< Enable                                                              */
5710   #define BELLBOARD_INTENSET3_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5711   #define BELLBOARD_INTENSET3_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5712 
5713 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
5714   #define BELLBOARD_INTENSET3_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
5715   #define BELLBOARD_INTENSET3_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
5716                                                                             field.*/
5717   #define BELLBOARD_INTENSET3_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
5718   #define BELLBOARD_INTENSET3_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
5719   #define BELLBOARD_INTENSET3_TRIGGERED25_Set (0x1UL) /*!< Enable                                                              */
5720   #define BELLBOARD_INTENSET3_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5721   #define BELLBOARD_INTENSET3_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5722 
5723 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
5724   #define BELLBOARD_INTENSET3_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
5725   #define BELLBOARD_INTENSET3_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
5726                                                                             field.*/
5727   #define BELLBOARD_INTENSET3_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
5728   #define BELLBOARD_INTENSET3_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
5729   #define BELLBOARD_INTENSET3_TRIGGERED26_Set (0x1UL) /*!< Enable                                                              */
5730   #define BELLBOARD_INTENSET3_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5731   #define BELLBOARD_INTENSET3_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5732 
5733 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
5734   #define BELLBOARD_INTENSET3_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
5735   #define BELLBOARD_INTENSET3_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
5736                                                                             field.*/
5737   #define BELLBOARD_INTENSET3_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
5738   #define BELLBOARD_INTENSET3_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
5739   #define BELLBOARD_INTENSET3_TRIGGERED27_Set (0x1UL) /*!< Enable                                                              */
5740   #define BELLBOARD_INTENSET3_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5741   #define BELLBOARD_INTENSET3_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5742 
5743 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
5744   #define BELLBOARD_INTENSET3_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
5745   #define BELLBOARD_INTENSET3_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
5746                                                                             field.*/
5747   #define BELLBOARD_INTENSET3_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
5748   #define BELLBOARD_INTENSET3_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
5749   #define BELLBOARD_INTENSET3_TRIGGERED28_Set (0x1UL) /*!< Enable                                                              */
5750   #define BELLBOARD_INTENSET3_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5751   #define BELLBOARD_INTENSET3_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5752 
5753 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
5754   #define BELLBOARD_INTENSET3_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
5755   #define BELLBOARD_INTENSET3_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
5756                                                                             field.*/
5757   #define BELLBOARD_INTENSET3_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
5758   #define BELLBOARD_INTENSET3_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
5759   #define BELLBOARD_INTENSET3_TRIGGERED29_Set (0x1UL) /*!< Enable                                                              */
5760   #define BELLBOARD_INTENSET3_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5761   #define BELLBOARD_INTENSET3_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5762 
5763 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
5764   #define BELLBOARD_INTENSET3_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
5765   #define BELLBOARD_INTENSET3_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
5766                                                                             field.*/
5767   #define BELLBOARD_INTENSET3_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
5768   #define BELLBOARD_INTENSET3_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
5769   #define BELLBOARD_INTENSET3_TRIGGERED30_Set (0x1UL) /*!< Enable                                                              */
5770   #define BELLBOARD_INTENSET3_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5771   #define BELLBOARD_INTENSET3_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5772 
5773 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
5774   #define BELLBOARD_INTENSET3_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
5775   #define BELLBOARD_INTENSET3_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET3_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
5776                                                                             field.*/
5777   #define BELLBOARD_INTENSET3_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
5778   #define BELLBOARD_INTENSET3_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
5779   #define BELLBOARD_INTENSET3_TRIGGERED31_Set (0x1UL) /*!< Enable                                                              */
5780   #define BELLBOARD_INTENSET3_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5781   #define BELLBOARD_INTENSET3_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5782 
5783 
5784 /* BELLBOARD_INTENCLR3: Disable interrupt */
5785   #define BELLBOARD_INTENCLR3_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR3 register.                                */
5786 
5787 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
5788   #define BELLBOARD_INTENCLR3_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
5789   #define BELLBOARD_INTENCLR3_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
5790   #define BELLBOARD_INTENCLR3_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
5791   #define BELLBOARD_INTENCLR3_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
5792   #define BELLBOARD_INTENCLR3_TRIGGERED0_Clear (0x1UL) /*!< Disable                                                            */
5793   #define BELLBOARD_INTENCLR3_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5794   #define BELLBOARD_INTENCLR3_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5795 
5796 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
5797   #define BELLBOARD_INTENCLR3_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
5798   #define BELLBOARD_INTENCLR3_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
5799   #define BELLBOARD_INTENCLR3_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
5800   #define BELLBOARD_INTENCLR3_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
5801   #define BELLBOARD_INTENCLR3_TRIGGERED1_Clear (0x1UL) /*!< Disable                                                            */
5802   #define BELLBOARD_INTENCLR3_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5803   #define BELLBOARD_INTENCLR3_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5804 
5805 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
5806   #define BELLBOARD_INTENCLR3_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
5807   #define BELLBOARD_INTENCLR3_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
5808   #define BELLBOARD_INTENCLR3_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
5809   #define BELLBOARD_INTENCLR3_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
5810   #define BELLBOARD_INTENCLR3_TRIGGERED2_Clear (0x1UL) /*!< Disable                                                            */
5811   #define BELLBOARD_INTENCLR3_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5812   #define BELLBOARD_INTENCLR3_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5813 
5814 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
5815   #define BELLBOARD_INTENCLR3_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
5816   #define BELLBOARD_INTENCLR3_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
5817   #define BELLBOARD_INTENCLR3_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
5818   #define BELLBOARD_INTENCLR3_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
5819   #define BELLBOARD_INTENCLR3_TRIGGERED3_Clear (0x1UL) /*!< Disable                                                            */
5820   #define BELLBOARD_INTENCLR3_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5821   #define BELLBOARD_INTENCLR3_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5822 
5823 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
5824   #define BELLBOARD_INTENCLR3_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
5825   #define BELLBOARD_INTENCLR3_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
5826   #define BELLBOARD_INTENCLR3_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
5827   #define BELLBOARD_INTENCLR3_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
5828   #define BELLBOARD_INTENCLR3_TRIGGERED4_Clear (0x1UL) /*!< Disable                                                            */
5829   #define BELLBOARD_INTENCLR3_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5830   #define BELLBOARD_INTENCLR3_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5831 
5832 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
5833   #define BELLBOARD_INTENCLR3_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
5834   #define BELLBOARD_INTENCLR3_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
5835   #define BELLBOARD_INTENCLR3_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
5836   #define BELLBOARD_INTENCLR3_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
5837   #define BELLBOARD_INTENCLR3_TRIGGERED5_Clear (0x1UL) /*!< Disable                                                            */
5838   #define BELLBOARD_INTENCLR3_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5839   #define BELLBOARD_INTENCLR3_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5840 
5841 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
5842   #define BELLBOARD_INTENCLR3_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
5843   #define BELLBOARD_INTENCLR3_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
5844   #define BELLBOARD_INTENCLR3_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
5845   #define BELLBOARD_INTENCLR3_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
5846   #define BELLBOARD_INTENCLR3_TRIGGERED6_Clear (0x1UL) /*!< Disable                                                            */
5847   #define BELLBOARD_INTENCLR3_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5848   #define BELLBOARD_INTENCLR3_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5849 
5850 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
5851   #define BELLBOARD_INTENCLR3_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
5852   #define BELLBOARD_INTENCLR3_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
5853   #define BELLBOARD_INTENCLR3_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
5854   #define BELLBOARD_INTENCLR3_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
5855   #define BELLBOARD_INTENCLR3_TRIGGERED7_Clear (0x1UL) /*!< Disable                                                            */
5856   #define BELLBOARD_INTENCLR3_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5857   #define BELLBOARD_INTENCLR3_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5858 
5859 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
5860   #define BELLBOARD_INTENCLR3_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
5861   #define BELLBOARD_INTENCLR3_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
5862   #define BELLBOARD_INTENCLR3_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
5863   #define BELLBOARD_INTENCLR3_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
5864   #define BELLBOARD_INTENCLR3_TRIGGERED8_Clear (0x1UL) /*!< Disable                                                            */
5865   #define BELLBOARD_INTENCLR3_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5866   #define BELLBOARD_INTENCLR3_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5867 
5868 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
5869   #define BELLBOARD_INTENCLR3_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
5870   #define BELLBOARD_INTENCLR3_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
5871   #define BELLBOARD_INTENCLR3_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
5872   #define BELLBOARD_INTENCLR3_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
5873   #define BELLBOARD_INTENCLR3_TRIGGERED9_Clear (0x1UL) /*!< Disable                                                            */
5874   #define BELLBOARD_INTENCLR3_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
5875   #define BELLBOARD_INTENCLR3_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
5876 
5877 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
5878   #define BELLBOARD_INTENCLR3_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
5879   #define BELLBOARD_INTENCLR3_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
5880                                                                             field.*/
5881   #define BELLBOARD_INTENCLR3_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
5882   #define BELLBOARD_INTENCLR3_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
5883   #define BELLBOARD_INTENCLR3_TRIGGERED10_Clear (0x1UL) /*!< Disable                                                           */
5884   #define BELLBOARD_INTENCLR3_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5885   #define BELLBOARD_INTENCLR3_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5886 
5887 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
5888   #define BELLBOARD_INTENCLR3_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
5889   #define BELLBOARD_INTENCLR3_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
5890                                                                             field.*/
5891   #define BELLBOARD_INTENCLR3_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
5892   #define BELLBOARD_INTENCLR3_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
5893   #define BELLBOARD_INTENCLR3_TRIGGERED11_Clear (0x1UL) /*!< Disable                                                           */
5894   #define BELLBOARD_INTENCLR3_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5895   #define BELLBOARD_INTENCLR3_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5896 
5897 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
5898   #define BELLBOARD_INTENCLR3_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
5899   #define BELLBOARD_INTENCLR3_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
5900                                                                             field.*/
5901   #define BELLBOARD_INTENCLR3_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
5902   #define BELLBOARD_INTENCLR3_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
5903   #define BELLBOARD_INTENCLR3_TRIGGERED12_Clear (0x1UL) /*!< Disable                                                           */
5904   #define BELLBOARD_INTENCLR3_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5905   #define BELLBOARD_INTENCLR3_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5906 
5907 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
5908   #define BELLBOARD_INTENCLR3_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
5909   #define BELLBOARD_INTENCLR3_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
5910                                                                             field.*/
5911   #define BELLBOARD_INTENCLR3_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
5912   #define BELLBOARD_INTENCLR3_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
5913   #define BELLBOARD_INTENCLR3_TRIGGERED13_Clear (0x1UL) /*!< Disable                                                           */
5914   #define BELLBOARD_INTENCLR3_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5915   #define BELLBOARD_INTENCLR3_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5916 
5917 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
5918   #define BELLBOARD_INTENCLR3_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
5919   #define BELLBOARD_INTENCLR3_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
5920                                                                             field.*/
5921   #define BELLBOARD_INTENCLR3_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
5922   #define BELLBOARD_INTENCLR3_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
5923   #define BELLBOARD_INTENCLR3_TRIGGERED14_Clear (0x1UL) /*!< Disable                                                           */
5924   #define BELLBOARD_INTENCLR3_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5925   #define BELLBOARD_INTENCLR3_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5926 
5927 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
5928   #define BELLBOARD_INTENCLR3_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
5929   #define BELLBOARD_INTENCLR3_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
5930                                                                             field.*/
5931   #define BELLBOARD_INTENCLR3_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
5932   #define BELLBOARD_INTENCLR3_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
5933   #define BELLBOARD_INTENCLR3_TRIGGERED15_Clear (0x1UL) /*!< Disable                                                           */
5934   #define BELLBOARD_INTENCLR3_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5935   #define BELLBOARD_INTENCLR3_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5936 
5937 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
5938   #define BELLBOARD_INTENCLR3_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
5939   #define BELLBOARD_INTENCLR3_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
5940                                                                             field.*/
5941   #define BELLBOARD_INTENCLR3_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
5942   #define BELLBOARD_INTENCLR3_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
5943   #define BELLBOARD_INTENCLR3_TRIGGERED16_Clear (0x1UL) /*!< Disable                                                           */
5944   #define BELLBOARD_INTENCLR3_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5945   #define BELLBOARD_INTENCLR3_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5946 
5947 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
5948   #define BELLBOARD_INTENCLR3_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
5949   #define BELLBOARD_INTENCLR3_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
5950                                                                             field.*/
5951   #define BELLBOARD_INTENCLR3_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
5952   #define BELLBOARD_INTENCLR3_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
5953   #define BELLBOARD_INTENCLR3_TRIGGERED17_Clear (0x1UL) /*!< Disable                                                           */
5954   #define BELLBOARD_INTENCLR3_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5955   #define BELLBOARD_INTENCLR3_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5956 
5957 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
5958   #define BELLBOARD_INTENCLR3_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
5959   #define BELLBOARD_INTENCLR3_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
5960                                                                             field.*/
5961   #define BELLBOARD_INTENCLR3_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
5962   #define BELLBOARD_INTENCLR3_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
5963   #define BELLBOARD_INTENCLR3_TRIGGERED18_Clear (0x1UL) /*!< Disable                                                           */
5964   #define BELLBOARD_INTENCLR3_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5965   #define BELLBOARD_INTENCLR3_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5966 
5967 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
5968   #define BELLBOARD_INTENCLR3_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
5969   #define BELLBOARD_INTENCLR3_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
5970                                                                             field.*/
5971   #define BELLBOARD_INTENCLR3_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
5972   #define BELLBOARD_INTENCLR3_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
5973   #define BELLBOARD_INTENCLR3_TRIGGERED19_Clear (0x1UL) /*!< Disable                                                           */
5974   #define BELLBOARD_INTENCLR3_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5975   #define BELLBOARD_INTENCLR3_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5976 
5977 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
5978   #define BELLBOARD_INTENCLR3_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
5979   #define BELLBOARD_INTENCLR3_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
5980                                                                             field.*/
5981   #define BELLBOARD_INTENCLR3_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
5982   #define BELLBOARD_INTENCLR3_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
5983   #define BELLBOARD_INTENCLR3_TRIGGERED20_Clear (0x1UL) /*!< Disable                                                           */
5984   #define BELLBOARD_INTENCLR3_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5985   #define BELLBOARD_INTENCLR3_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5986 
5987 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
5988   #define BELLBOARD_INTENCLR3_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
5989   #define BELLBOARD_INTENCLR3_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
5990                                                                             field.*/
5991   #define BELLBOARD_INTENCLR3_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
5992   #define BELLBOARD_INTENCLR3_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
5993   #define BELLBOARD_INTENCLR3_TRIGGERED21_Clear (0x1UL) /*!< Disable                                                           */
5994   #define BELLBOARD_INTENCLR3_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
5995   #define BELLBOARD_INTENCLR3_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
5996 
5997 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
5998   #define BELLBOARD_INTENCLR3_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
5999   #define BELLBOARD_INTENCLR3_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
6000                                                                             field.*/
6001   #define BELLBOARD_INTENCLR3_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
6002   #define BELLBOARD_INTENCLR3_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
6003   #define BELLBOARD_INTENCLR3_TRIGGERED22_Clear (0x1UL) /*!< Disable                                                           */
6004   #define BELLBOARD_INTENCLR3_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6005   #define BELLBOARD_INTENCLR3_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6006 
6007 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
6008   #define BELLBOARD_INTENCLR3_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
6009   #define BELLBOARD_INTENCLR3_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
6010                                                                             field.*/
6011   #define BELLBOARD_INTENCLR3_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
6012   #define BELLBOARD_INTENCLR3_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
6013   #define BELLBOARD_INTENCLR3_TRIGGERED23_Clear (0x1UL) /*!< Disable                                                           */
6014   #define BELLBOARD_INTENCLR3_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6015   #define BELLBOARD_INTENCLR3_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6016 
6017 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
6018   #define BELLBOARD_INTENCLR3_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
6019   #define BELLBOARD_INTENCLR3_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
6020                                                                             field.*/
6021   #define BELLBOARD_INTENCLR3_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
6022   #define BELLBOARD_INTENCLR3_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
6023   #define BELLBOARD_INTENCLR3_TRIGGERED24_Clear (0x1UL) /*!< Disable                                                           */
6024   #define BELLBOARD_INTENCLR3_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6025   #define BELLBOARD_INTENCLR3_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6026 
6027 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
6028   #define BELLBOARD_INTENCLR3_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
6029   #define BELLBOARD_INTENCLR3_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
6030                                                                             field.*/
6031   #define BELLBOARD_INTENCLR3_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
6032   #define BELLBOARD_INTENCLR3_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
6033   #define BELLBOARD_INTENCLR3_TRIGGERED25_Clear (0x1UL) /*!< Disable                                                           */
6034   #define BELLBOARD_INTENCLR3_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6035   #define BELLBOARD_INTENCLR3_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6036 
6037 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
6038   #define BELLBOARD_INTENCLR3_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
6039   #define BELLBOARD_INTENCLR3_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
6040                                                                             field.*/
6041   #define BELLBOARD_INTENCLR3_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
6042   #define BELLBOARD_INTENCLR3_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
6043   #define BELLBOARD_INTENCLR3_TRIGGERED26_Clear (0x1UL) /*!< Disable                                                           */
6044   #define BELLBOARD_INTENCLR3_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6045   #define BELLBOARD_INTENCLR3_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6046 
6047 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
6048   #define BELLBOARD_INTENCLR3_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
6049   #define BELLBOARD_INTENCLR3_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
6050                                                                             field.*/
6051   #define BELLBOARD_INTENCLR3_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
6052   #define BELLBOARD_INTENCLR3_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
6053   #define BELLBOARD_INTENCLR3_TRIGGERED27_Clear (0x1UL) /*!< Disable                                                           */
6054   #define BELLBOARD_INTENCLR3_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6055   #define BELLBOARD_INTENCLR3_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6056 
6057 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
6058   #define BELLBOARD_INTENCLR3_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
6059   #define BELLBOARD_INTENCLR3_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
6060                                                                             field.*/
6061   #define BELLBOARD_INTENCLR3_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
6062   #define BELLBOARD_INTENCLR3_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
6063   #define BELLBOARD_INTENCLR3_TRIGGERED28_Clear (0x1UL) /*!< Disable                                                           */
6064   #define BELLBOARD_INTENCLR3_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6065   #define BELLBOARD_INTENCLR3_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6066 
6067 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
6068   #define BELLBOARD_INTENCLR3_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
6069   #define BELLBOARD_INTENCLR3_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
6070                                                                             field.*/
6071   #define BELLBOARD_INTENCLR3_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
6072   #define BELLBOARD_INTENCLR3_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
6073   #define BELLBOARD_INTENCLR3_TRIGGERED29_Clear (0x1UL) /*!< Disable                                                           */
6074   #define BELLBOARD_INTENCLR3_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6075   #define BELLBOARD_INTENCLR3_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6076 
6077 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
6078   #define BELLBOARD_INTENCLR3_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
6079   #define BELLBOARD_INTENCLR3_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
6080                                                                             field.*/
6081   #define BELLBOARD_INTENCLR3_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
6082   #define BELLBOARD_INTENCLR3_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
6083   #define BELLBOARD_INTENCLR3_TRIGGERED30_Clear (0x1UL) /*!< Disable                                                           */
6084   #define BELLBOARD_INTENCLR3_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6085   #define BELLBOARD_INTENCLR3_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6086 
6087 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
6088   #define BELLBOARD_INTENCLR3_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
6089   #define BELLBOARD_INTENCLR3_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR3_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
6090                                                                             field.*/
6091   #define BELLBOARD_INTENCLR3_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
6092   #define BELLBOARD_INTENCLR3_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
6093   #define BELLBOARD_INTENCLR3_TRIGGERED31_Clear (0x1UL) /*!< Disable                                                           */
6094   #define BELLBOARD_INTENCLR3_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6095   #define BELLBOARD_INTENCLR3_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6096 
6097 
6098 /* BELLBOARD_INTPEND3: Pending interrupts */
6099   #define BELLBOARD_INTPEND3_ResetValue (0x00000000UL) /*!< Reset value of INTPEND3 register.                                  */
6100 
6101 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
6102   #define BELLBOARD_INTPEND3_TRIGGERED0_Pos (0UL)    /*!< Position of TRIGGERED0 field.                                        */
6103   #define BELLBOARD_INTPEND3_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.    */
6104   #define BELLBOARD_INTPEND3_TRIGGERED0_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED0 field.                            */
6105   #define BELLBOARD_INTPEND3_TRIGGERED0_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED0 field.                            */
6106   #define BELLBOARD_INTPEND3_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending                                              */
6107   #define BELLBOARD_INTPEND3_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending                                                     */
6108 
6109 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
6110   #define BELLBOARD_INTPEND3_TRIGGERED1_Pos (1UL)    /*!< Position of TRIGGERED1 field.                                        */
6111   #define BELLBOARD_INTPEND3_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.    */
6112   #define BELLBOARD_INTPEND3_TRIGGERED1_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED1 field.                            */
6113   #define BELLBOARD_INTPEND3_TRIGGERED1_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED1 field.                            */
6114   #define BELLBOARD_INTPEND3_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending                                              */
6115   #define BELLBOARD_INTPEND3_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending                                                     */
6116 
6117 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
6118   #define BELLBOARD_INTPEND3_TRIGGERED2_Pos (2UL)    /*!< Position of TRIGGERED2 field.                                        */
6119   #define BELLBOARD_INTPEND3_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.    */
6120   #define BELLBOARD_INTPEND3_TRIGGERED2_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED2 field.                            */
6121   #define BELLBOARD_INTPEND3_TRIGGERED2_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED2 field.                            */
6122   #define BELLBOARD_INTPEND3_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending                                              */
6123   #define BELLBOARD_INTPEND3_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending                                                     */
6124 
6125 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
6126   #define BELLBOARD_INTPEND3_TRIGGERED3_Pos (3UL)    /*!< Position of TRIGGERED3 field.                                        */
6127   #define BELLBOARD_INTPEND3_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.    */
6128   #define BELLBOARD_INTPEND3_TRIGGERED3_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED3 field.                            */
6129   #define BELLBOARD_INTPEND3_TRIGGERED3_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED3 field.                            */
6130   #define BELLBOARD_INTPEND3_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending                                              */
6131   #define BELLBOARD_INTPEND3_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending                                                     */
6132 
6133 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
6134   #define BELLBOARD_INTPEND3_TRIGGERED4_Pos (4UL)    /*!< Position of TRIGGERED4 field.                                        */
6135   #define BELLBOARD_INTPEND3_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.    */
6136   #define BELLBOARD_INTPEND3_TRIGGERED4_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED4 field.                            */
6137   #define BELLBOARD_INTPEND3_TRIGGERED4_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED4 field.                            */
6138   #define BELLBOARD_INTPEND3_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending                                              */
6139   #define BELLBOARD_INTPEND3_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending                                                     */
6140 
6141 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
6142   #define BELLBOARD_INTPEND3_TRIGGERED5_Pos (5UL)    /*!< Position of TRIGGERED5 field.                                        */
6143   #define BELLBOARD_INTPEND3_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.    */
6144   #define BELLBOARD_INTPEND3_TRIGGERED5_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED5 field.                            */
6145   #define BELLBOARD_INTPEND3_TRIGGERED5_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED5 field.                            */
6146   #define BELLBOARD_INTPEND3_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending                                              */
6147   #define BELLBOARD_INTPEND3_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending                                                     */
6148 
6149 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
6150   #define BELLBOARD_INTPEND3_TRIGGERED6_Pos (6UL)    /*!< Position of TRIGGERED6 field.                                        */
6151   #define BELLBOARD_INTPEND3_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.    */
6152   #define BELLBOARD_INTPEND3_TRIGGERED6_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED6 field.                            */
6153   #define BELLBOARD_INTPEND3_TRIGGERED6_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED6 field.                            */
6154   #define BELLBOARD_INTPEND3_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending                                              */
6155   #define BELLBOARD_INTPEND3_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending                                                     */
6156 
6157 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
6158   #define BELLBOARD_INTPEND3_TRIGGERED7_Pos (7UL)    /*!< Position of TRIGGERED7 field.                                        */
6159   #define BELLBOARD_INTPEND3_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.    */
6160   #define BELLBOARD_INTPEND3_TRIGGERED7_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED7 field.                            */
6161   #define BELLBOARD_INTPEND3_TRIGGERED7_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED7 field.                            */
6162   #define BELLBOARD_INTPEND3_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending                                              */
6163   #define BELLBOARD_INTPEND3_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending                                                     */
6164 
6165 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
6166   #define BELLBOARD_INTPEND3_TRIGGERED8_Pos (8UL)    /*!< Position of TRIGGERED8 field.                                        */
6167   #define BELLBOARD_INTPEND3_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.    */
6168   #define BELLBOARD_INTPEND3_TRIGGERED8_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED8 field.                            */
6169   #define BELLBOARD_INTPEND3_TRIGGERED8_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED8 field.                            */
6170   #define BELLBOARD_INTPEND3_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending                                              */
6171   #define BELLBOARD_INTPEND3_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending                                                     */
6172 
6173 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
6174   #define BELLBOARD_INTPEND3_TRIGGERED9_Pos (9UL)    /*!< Position of TRIGGERED9 field.                                        */
6175   #define BELLBOARD_INTPEND3_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.    */
6176   #define BELLBOARD_INTPEND3_TRIGGERED9_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED9 field.                            */
6177   #define BELLBOARD_INTPEND3_TRIGGERED9_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED9 field.                            */
6178   #define BELLBOARD_INTPEND3_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending                                              */
6179   #define BELLBOARD_INTPEND3_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending                                                     */
6180 
6181 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
6182   #define BELLBOARD_INTPEND3_TRIGGERED10_Pos (10UL)  /*!< Position of TRIGGERED10 field.                                       */
6183   #define BELLBOARD_INTPEND3_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
6184   #define BELLBOARD_INTPEND3_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                           */
6185   #define BELLBOARD_INTPEND3_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                           */
6186   #define BELLBOARD_INTPEND3_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                             */
6187   #define BELLBOARD_INTPEND3_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending                                                    */
6188 
6189 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
6190   #define BELLBOARD_INTPEND3_TRIGGERED11_Pos (11UL)  /*!< Position of TRIGGERED11 field.                                       */
6191   #define BELLBOARD_INTPEND3_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
6192   #define BELLBOARD_INTPEND3_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                           */
6193   #define BELLBOARD_INTPEND3_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                           */
6194   #define BELLBOARD_INTPEND3_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                             */
6195   #define BELLBOARD_INTPEND3_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending                                                    */
6196 
6197 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
6198   #define BELLBOARD_INTPEND3_TRIGGERED12_Pos (12UL)  /*!< Position of TRIGGERED12 field.                                       */
6199   #define BELLBOARD_INTPEND3_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
6200   #define BELLBOARD_INTPEND3_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                           */
6201   #define BELLBOARD_INTPEND3_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                           */
6202   #define BELLBOARD_INTPEND3_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                             */
6203   #define BELLBOARD_INTPEND3_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending                                                    */
6204 
6205 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
6206   #define BELLBOARD_INTPEND3_TRIGGERED13_Pos (13UL)  /*!< Position of TRIGGERED13 field.                                       */
6207   #define BELLBOARD_INTPEND3_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
6208   #define BELLBOARD_INTPEND3_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                           */
6209   #define BELLBOARD_INTPEND3_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                           */
6210   #define BELLBOARD_INTPEND3_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                             */
6211   #define BELLBOARD_INTPEND3_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending                                                    */
6212 
6213 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
6214   #define BELLBOARD_INTPEND3_TRIGGERED14_Pos (14UL)  /*!< Position of TRIGGERED14 field.                                       */
6215   #define BELLBOARD_INTPEND3_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
6216   #define BELLBOARD_INTPEND3_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                           */
6217   #define BELLBOARD_INTPEND3_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                           */
6218   #define BELLBOARD_INTPEND3_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                             */
6219   #define BELLBOARD_INTPEND3_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending                                                    */
6220 
6221 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
6222   #define BELLBOARD_INTPEND3_TRIGGERED15_Pos (15UL)  /*!< Position of TRIGGERED15 field.                                       */
6223   #define BELLBOARD_INTPEND3_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
6224   #define BELLBOARD_INTPEND3_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                           */
6225   #define BELLBOARD_INTPEND3_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                           */
6226   #define BELLBOARD_INTPEND3_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                             */
6227   #define BELLBOARD_INTPEND3_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending                                                    */
6228 
6229 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
6230   #define BELLBOARD_INTPEND3_TRIGGERED16_Pos (16UL)  /*!< Position of TRIGGERED16 field.                                       */
6231   #define BELLBOARD_INTPEND3_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */
6232   #define BELLBOARD_INTPEND3_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                           */
6233   #define BELLBOARD_INTPEND3_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                           */
6234   #define BELLBOARD_INTPEND3_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                             */
6235   #define BELLBOARD_INTPEND3_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending                                                    */
6236 
6237 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
6238   #define BELLBOARD_INTPEND3_TRIGGERED17_Pos (17UL)  /*!< Position of TRIGGERED17 field.                                       */
6239   #define BELLBOARD_INTPEND3_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */
6240   #define BELLBOARD_INTPEND3_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                           */
6241   #define BELLBOARD_INTPEND3_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                           */
6242   #define BELLBOARD_INTPEND3_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                             */
6243   #define BELLBOARD_INTPEND3_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending                                                    */
6244 
6245 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
6246   #define BELLBOARD_INTPEND3_TRIGGERED18_Pos (18UL)  /*!< Position of TRIGGERED18 field.                                       */
6247   #define BELLBOARD_INTPEND3_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */
6248   #define BELLBOARD_INTPEND3_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                           */
6249   #define BELLBOARD_INTPEND3_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                           */
6250   #define BELLBOARD_INTPEND3_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                             */
6251   #define BELLBOARD_INTPEND3_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending                                                    */
6252 
6253 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
6254   #define BELLBOARD_INTPEND3_TRIGGERED19_Pos (19UL)  /*!< Position of TRIGGERED19 field.                                       */
6255   #define BELLBOARD_INTPEND3_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */
6256   #define BELLBOARD_INTPEND3_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                           */
6257   #define BELLBOARD_INTPEND3_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                           */
6258   #define BELLBOARD_INTPEND3_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                             */
6259   #define BELLBOARD_INTPEND3_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending                                                    */
6260 
6261 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
6262   #define BELLBOARD_INTPEND3_TRIGGERED20_Pos (20UL)  /*!< Position of TRIGGERED20 field.                                       */
6263   #define BELLBOARD_INTPEND3_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */
6264   #define BELLBOARD_INTPEND3_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                           */
6265   #define BELLBOARD_INTPEND3_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                           */
6266   #define BELLBOARD_INTPEND3_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                             */
6267   #define BELLBOARD_INTPEND3_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending                                                    */
6268 
6269 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
6270   #define BELLBOARD_INTPEND3_TRIGGERED21_Pos (21UL)  /*!< Position of TRIGGERED21 field.                                       */
6271   #define BELLBOARD_INTPEND3_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */
6272   #define BELLBOARD_INTPEND3_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                           */
6273   #define BELLBOARD_INTPEND3_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                           */
6274   #define BELLBOARD_INTPEND3_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                             */
6275   #define BELLBOARD_INTPEND3_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending                                                    */
6276 
6277 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
6278   #define BELLBOARD_INTPEND3_TRIGGERED22_Pos (22UL)  /*!< Position of TRIGGERED22 field.                                       */
6279   #define BELLBOARD_INTPEND3_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */
6280   #define BELLBOARD_INTPEND3_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                           */
6281   #define BELLBOARD_INTPEND3_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                           */
6282   #define BELLBOARD_INTPEND3_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                             */
6283   #define BELLBOARD_INTPEND3_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending                                                    */
6284 
6285 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
6286   #define BELLBOARD_INTPEND3_TRIGGERED23_Pos (23UL)  /*!< Position of TRIGGERED23 field.                                       */
6287   #define BELLBOARD_INTPEND3_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */
6288   #define BELLBOARD_INTPEND3_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                           */
6289   #define BELLBOARD_INTPEND3_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                           */
6290   #define BELLBOARD_INTPEND3_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                             */
6291   #define BELLBOARD_INTPEND3_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending                                                    */
6292 
6293 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
6294   #define BELLBOARD_INTPEND3_TRIGGERED24_Pos (24UL)  /*!< Position of TRIGGERED24 field.                                       */
6295   #define BELLBOARD_INTPEND3_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */
6296   #define BELLBOARD_INTPEND3_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                           */
6297   #define BELLBOARD_INTPEND3_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                           */
6298   #define BELLBOARD_INTPEND3_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                             */
6299   #define BELLBOARD_INTPEND3_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending                                                    */
6300 
6301 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
6302   #define BELLBOARD_INTPEND3_TRIGGERED25_Pos (25UL)  /*!< Position of TRIGGERED25 field.                                       */
6303   #define BELLBOARD_INTPEND3_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */
6304   #define BELLBOARD_INTPEND3_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                           */
6305   #define BELLBOARD_INTPEND3_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                           */
6306   #define BELLBOARD_INTPEND3_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                             */
6307   #define BELLBOARD_INTPEND3_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending                                                    */
6308 
6309 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
6310   #define BELLBOARD_INTPEND3_TRIGGERED26_Pos (26UL)  /*!< Position of TRIGGERED26 field.                                       */
6311   #define BELLBOARD_INTPEND3_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */
6312   #define BELLBOARD_INTPEND3_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                           */
6313   #define BELLBOARD_INTPEND3_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                           */
6314   #define BELLBOARD_INTPEND3_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                             */
6315   #define BELLBOARD_INTPEND3_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending                                                    */
6316 
6317 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
6318   #define BELLBOARD_INTPEND3_TRIGGERED27_Pos (27UL)  /*!< Position of TRIGGERED27 field.                                       */
6319   #define BELLBOARD_INTPEND3_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */
6320   #define BELLBOARD_INTPEND3_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                           */
6321   #define BELLBOARD_INTPEND3_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                           */
6322   #define BELLBOARD_INTPEND3_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                             */
6323   #define BELLBOARD_INTPEND3_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending                                                    */
6324 
6325 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
6326   #define BELLBOARD_INTPEND3_TRIGGERED28_Pos (28UL)  /*!< Position of TRIGGERED28 field.                                       */
6327   #define BELLBOARD_INTPEND3_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */
6328   #define BELLBOARD_INTPEND3_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                           */
6329   #define BELLBOARD_INTPEND3_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                           */
6330   #define BELLBOARD_INTPEND3_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                             */
6331   #define BELLBOARD_INTPEND3_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending                                                    */
6332 
6333 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
6334   #define BELLBOARD_INTPEND3_TRIGGERED29_Pos (29UL)  /*!< Position of TRIGGERED29 field.                                       */
6335   #define BELLBOARD_INTPEND3_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */
6336   #define BELLBOARD_INTPEND3_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                           */
6337   #define BELLBOARD_INTPEND3_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                           */
6338   #define BELLBOARD_INTPEND3_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                             */
6339   #define BELLBOARD_INTPEND3_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending                                                    */
6340 
6341 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
6342   #define BELLBOARD_INTPEND3_TRIGGERED30_Pos (30UL)  /*!< Position of TRIGGERED30 field.                                       */
6343   #define BELLBOARD_INTPEND3_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */
6344   #define BELLBOARD_INTPEND3_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                           */
6345   #define BELLBOARD_INTPEND3_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                           */
6346   #define BELLBOARD_INTPEND3_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                             */
6347   #define BELLBOARD_INTPEND3_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending                                                    */
6348 
6349 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
6350   #define BELLBOARD_INTPEND3_TRIGGERED31_Pos (31UL)  /*!< Position of TRIGGERED31 field.                                       */
6351   #define BELLBOARD_INTPEND3_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND3_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */
6352   #define BELLBOARD_INTPEND3_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                           */
6353   #define BELLBOARD_INTPEND3_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                           */
6354   #define BELLBOARD_INTPEND3_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                             */
6355   #define BELLBOARD_INTPEND3_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending                                                    */
6356 
6357 
6358 /* BELLBOARD_INTEN4: Enable or disable interrupt */
6359   #define BELLBOARD_INTEN4_ResetValue (0x00000000UL) /*!< Reset value of INTEN4 register.                                      */
6360 
6361 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
6362   #define BELLBOARD_INTEN4_TRIGGERED0_Pos (0UL)      /*!< Position of TRIGGERED0 field.                                        */
6363   #define BELLBOARD_INTEN4_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.        */
6364   #define BELLBOARD_INTEN4_TRIGGERED0_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED0 field.                            */
6365   #define BELLBOARD_INTEN4_TRIGGERED0_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED0 field.                            */
6366   #define BELLBOARD_INTEN4_TRIGGERED0_Disabled (0x0UL) /*!< Disable                                                            */
6367   #define BELLBOARD_INTEN4_TRIGGERED0_Enabled (0x1UL) /*!< Enable                                                              */
6368 
6369 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
6370   #define BELLBOARD_INTEN4_TRIGGERED1_Pos (1UL)      /*!< Position of TRIGGERED1 field.                                        */
6371   #define BELLBOARD_INTEN4_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.        */
6372   #define BELLBOARD_INTEN4_TRIGGERED1_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED1 field.                            */
6373   #define BELLBOARD_INTEN4_TRIGGERED1_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED1 field.                            */
6374   #define BELLBOARD_INTEN4_TRIGGERED1_Disabled (0x0UL) /*!< Disable                                                            */
6375   #define BELLBOARD_INTEN4_TRIGGERED1_Enabled (0x1UL) /*!< Enable                                                              */
6376 
6377 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
6378   #define BELLBOARD_INTEN4_TRIGGERED2_Pos (2UL)      /*!< Position of TRIGGERED2 field.                                        */
6379   #define BELLBOARD_INTEN4_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.        */
6380   #define BELLBOARD_INTEN4_TRIGGERED2_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED2 field.                            */
6381   #define BELLBOARD_INTEN4_TRIGGERED2_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED2 field.                            */
6382   #define BELLBOARD_INTEN4_TRIGGERED2_Disabled (0x0UL) /*!< Disable                                                            */
6383   #define BELLBOARD_INTEN4_TRIGGERED2_Enabled (0x1UL) /*!< Enable                                                              */
6384 
6385 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
6386   #define BELLBOARD_INTEN4_TRIGGERED3_Pos (3UL)      /*!< Position of TRIGGERED3 field.                                        */
6387   #define BELLBOARD_INTEN4_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.        */
6388   #define BELLBOARD_INTEN4_TRIGGERED3_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED3 field.                            */
6389   #define BELLBOARD_INTEN4_TRIGGERED3_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED3 field.                            */
6390   #define BELLBOARD_INTEN4_TRIGGERED3_Disabled (0x0UL) /*!< Disable                                                            */
6391   #define BELLBOARD_INTEN4_TRIGGERED3_Enabled (0x1UL) /*!< Enable                                                              */
6392 
6393 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
6394   #define BELLBOARD_INTEN4_TRIGGERED4_Pos (4UL)      /*!< Position of TRIGGERED4 field.                                        */
6395   #define BELLBOARD_INTEN4_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.        */
6396   #define BELLBOARD_INTEN4_TRIGGERED4_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED4 field.                            */
6397   #define BELLBOARD_INTEN4_TRIGGERED4_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED4 field.                            */
6398   #define BELLBOARD_INTEN4_TRIGGERED4_Disabled (0x0UL) /*!< Disable                                                            */
6399   #define BELLBOARD_INTEN4_TRIGGERED4_Enabled (0x1UL) /*!< Enable                                                              */
6400 
6401 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
6402   #define BELLBOARD_INTEN4_TRIGGERED5_Pos (5UL)      /*!< Position of TRIGGERED5 field.                                        */
6403   #define BELLBOARD_INTEN4_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.        */
6404   #define BELLBOARD_INTEN4_TRIGGERED5_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED5 field.                            */
6405   #define BELLBOARD_INTEN4_TRIGGERED5_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED5 field.                            */
6406   #define BELLBOARD_INTEN4_TRIGGERED5_Disabled (0x0UL) /*!< Disable                                                            */
6407   #define BELLBOARD_INTEN4_TRIGGERED5_Enabled (0x1UL) /*!< Enable                                                              */
6408 
6409 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
6410   #define BELLBOARD_INTEN4_TRIGGERED6_Pos (6UL)      /*!< Position of TRIGGERED6 field.                                        */
6411   #define BELLBOARD_INTEN4_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.        */
6412   #define BELLBOARD_INTEN4_TRIGGERED6_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED6 field.                            */
6413   #define BELLBOARD_INTEN4_TRIGGERED6_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED6 field.                            */
6414   #define BELLBOARD_INTEN4_TRIGGERED6_Disabled (0x0UL) /*!< Disable                                                            */
6415   #define BELLBOARD_INTEN4_TRIGGERED6_Enabled (0x1UL) /*!< Enable                                                              */
6416 
6417 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
6418   #define BELLBOARD_INTEN4_TRIGGERED7_Pos (7UL)      /*!< Position of TRIGGERED7 field.                                        */
6419   #define BELLBOARD_INTEN4_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.        */
6420   #define BELLBOARD_INTEN4_TRIGGERED7_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED7 field.                            */
6421   #define BELLBOARD_INTEN4_TRIGGERED7_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED7 field.                            */
6422   #define BELLBOARD_INTEN4_TRIGGERED7_Disabled (0x0UL) /*!< Disable                                                            */
6423   #define BELLBOARD_INTEN4_TRIGGERED7_Enabled (0x1UL) /*!< Enable                                                              */
6424 
6425 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
6426   #define BELLBOARD_INTEN4_TRIGGERED8_Pos (8UL)      /*!< Position of TRIGGERED8 field.                                        */
6427   #define BELLBOARD_INTEN4_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.        */
6428   #define BELLBOARD_INTEN4_TRIGGERED8_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED8 field.                            */
6429   #define BELLBOARD_INTEN4_TRIGGERED8_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED8 field.                            */
6430   #define BELLBOARD_INTEN4_TRIGGERED8_Disabled (0x0UL) /*!< Disable                                                            */
6431   #define BELLBOARD_INTEN4_TRIGGERED8_Enabled (0x1UL) /*!< Enable                                                              */
6432 
6433 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
6434   #define BELLBOARD_INTEN4_TRIGGERED9_Pos (9UL)      /*!< Position of TRIGGERED9 field.                                        */
6435   #define BELLBOARD_INTEN4_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.        */
6436   #define BELLBOARD_INTEN4_TRIGGERED9_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED9 field.                            */
6437   #define BELLBOARD_INTEN4_TRIGGERED9_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED9 field.                            */
6438   #define BELLBOARD_INTEN4_TRIGGERED9_Disabled (0x0UL) /*!< Disable                                                            */
6439   #define BELLBOARD_INTEN4_TRIGGERED9_Enabled (0x1UL) /*!< Enable                                                              */
6440 
6441 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
6442   #define BELLBOARD_INTEN4_TRIGGERED10_Pos (10UL)    /*!< Position of TRIGGERED10 field.                                       */
6443   #define BELLBOARD_INTEN4_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.     */
6444   #define BELLBOARD_INTEN4_TRIGGERED10_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED10 field.                           */
6445   #define BELLBOARD_INTEN4_TRIGGERED10_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED10 field.                           */
6446   #define BELLBOARD_INTEN4_TRIGGERED10_Disabled (0x0UL) /*!< Disable                                                           */
6447   #define BELLBOARD_INTEN4_TRIGGERED10_Enabled (0x1UL) /*!< Enable                                                             */
6448 
6449 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
6450   #define BELLBOARD_INTEN4_TRIGGERED11_Pos (11UL)    /*!< Position of TRIGGERED11 field.                                       */
6451   #define BELLBOARD_INTEN4_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.     */
6452   #define BELLBOARD_INTEN4_TRIGGERED11_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED11 field.                           */
6453   #define BELLBOARD_INTEN4_TRIGGERED11_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED11 field.                           */
6454   #define BELLBOARD_INTEN4_TRIGGERED11_Disabled (0x0UL) /*!< Disable                                                           */
6455   #define BELLBOARD_INTEN4_TRIGGERED11_Enabled (0x1UL) /*!< Enable                                                             */
6456 
6457 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
6458   #define BELLBOARD_INTEN4_TRIGGERED12_Pos (12UL)    /*!< Position of TRIGGERED12 field.                                       */
6459   #define BELLBOARD_INTEN4_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.     */
6460   #define BELLBOARD_INTEN4_TRIGGERED12_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED12 field.                           */
6461   #define BELLBOARD_INTEN4_TRIGGERED12_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED12 field.                           */
6462   #define BELLBOARD_INTEN4_TRIGGERED12_Disabled (0x0UL) /*!< Disable                                                           */
6463   #define BELLBOARD_INTEN4_TRIGGERED12_Enabled (0x1UL) /*!< Enable                                                             */
6464 
6465 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
6466   #define BELLBOARD_INTEN4_TRIGGERED13_Pos (13UL)    /*!< Position of TRIGGERED13 field.                                       */
6467   #define BELLBOARD_INTEN4_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.     */
6468   #define BELLBOARD_INTEN4_TRIGGERED13_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED13 field.                           */
6469   #define BELLBOARD_INTEN4_TRIGGERED13_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED13 field.                           */
6470   #define BELLBOARD_INTEN4_TRIGGERED13_Disabled (0x0UL) /*!< Disable                                                           */
6471   #define BELLBOARD_INTEN4_TRIGGERED13_Enabled (0x1UL) /*!< Enable                                                             */
6472 
6473 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
6474   #define BELLBOARD_INTEN4_TRIGGERED14_Pos (14UL)    /*!< Position of TRIGGERED14 field.                                       */
6475   #define BELLBOARD_INTEN4_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.     */
6476   #define BELLBOARD_INTEN4_TRIGGERED14_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED14 field.                           */
6477   #define BELLBOARD_INTEN4_TRIGGERED14_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED14 field.                           */
6478   #define BELLBOARD_INTEN4_TRIGGERED14_Disabled (0x0UL) /*!< Disable                                                           */
6479   #define BELLBOARD_INTEN4_TRIGGERED14_Enabled (0x1UL) /*!< Enable                                                             */
6480 
6481 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
6482   #define BELLBOARD_INTEN4_TRIGGERED15_Pos (15UL)    /*!< Position of TRIGGERED15 field.                                       */
6483   #define BELLBOARD_INTEN4_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.     */
6484   #define BELLBOARD_INTEN4_TRIGGERED15_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED15 field.                           */
6485   #define BELLBOARD_INTEN4_TRIGGERED15_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED15 field.                           */
6486   #define BELLBOARD_INTEN4_TRIGGERED15_Disabled (0x0UL) /*!< Disable                                                           */
6487   #define BELLBOARD_INTEN4_TRIGGERED15_Enabled (0x1UL) /*!< Enable                                                             */
6488 
6489 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
6490   #define BELLBOARD_INTEN4_TRIGGERED16_Pos (16UL)    /*!< Position of TRIGGERED16 field.                                       */
6491   #define BELLBOARD_INTEN4_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.     */
6492   #define BELLBOARD_INTEN4_TRIGGERED16_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED16 field.                           */
6493   #define BELLBOARD_INTEN4_TRIGGERED16_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED16 field.                           */
6494   #define BELLBOARD_INTEN4_TRIGGERED16_Disabled (0x0UL) /*!< Disable                                                           */
6495   #define BELLBOARD_INTEN4_TRIGGERED16_Enabled (0x1UL) /*!< Enable                                                             */
6496 
6497 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
6498   #define BELLBOARD_INTEN4_TRIGGERED17_Pos (17UL)    /*!< Position of TRIGGERED17 field.                                       */
6499   #define BELLBOARD_INTEN4_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.     */
6500   #define BELLBOARD_INTEN4_TRIGGERED17_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED17 field.                           */
6501   #define BELLBOARD_INTEN4_TRIGGERED17_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED17 field.                           */
6502   #define BELLBOARD_INTEN4_TRIGGERED17_Disabled (0x0UL) /*!< Disable                                                           */
6503   #define BELLBOARD_INTEN4_TRIGGERED17_Enabled (0x1UL) /*!< Enable                                                             */
6504 
6505 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
6506   #define BELLBOARD_INTEN4_TRIGGERED18_Pos (18UL)    /*!< Position of TRIGGERED18 field.                                       */
6507   #define BELLBOARD_INTEN4_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.     */
6508   #define BELLBOARD_INTEN4_TRIGGERED18_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED18 field.                           */
6509   #define BELLBOARD_INTEN4_TRIGGERED18_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED18 field.                           */
6510   #define BELLBOARD_INTEN4_TRIGGERED18_Disabled (0x0UL) /*!< Disable                                                           */
6511   #define BELLBOARD_INTEN4_TRIGGERED18_Enabled (0x1UL) /*!< Enable                                                             */
6512 
6513 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
6514   #define BELLBOARD_INTEN4_TRIGGERED19_Pos (19UL)    /*!< Position of TRIGGERED19 field.                                       */
6515   #define BELLBOARD_INTEN4_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.     */
6516   #define BELLBOARD_INTEN4_TRIGGERED19_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED19 field.                           */
6517   #define BELLBOARD_INTEN4_TRIGGERED19_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED19 field.                           */
6518   #define BELLBOARD_INTEN4_TRIGGERED19_Disabled (0x0UL) /*!< Disable                                                           */
6519   #define BELLBOARD_INTEN4_TRIGGERED19_Enabled (0x1UL) /*!< Enable                                                             */
6520 
6521 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
6522   #define BELLBOARD_INTEN4_TRIGGERED20_Pos (20UL)    /*!< Position of TRIGGERED20 field.                                       */
6523   #define BELLBOARD_INTEN4_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.     */
6524   #define BELLBOARD_INTEN4_TRIGGERED20_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED20 field.                           */
6525   #define BELLBOARD_INTEN4_TRIGGERED20_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED20 field.                           */
6526   #define BELLBOARD_INTEN4_TRIGGERED20_Disabled (0x0UL) /*!< Disable                                                           */
6527   #define BELLBOARD_INTEN4_TRIGGERED20_Enabled (0x1UL) /*!< Enable                                                             */
6528 
6529 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
6530   #define BELLBOARD_INTEN4_TRIGGERED21_Pos (21UL)    /*!< Position of TRIGGERED21 field.                                       */
6531   #define BELLBOARD_INTEN4_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.     */
6532   #define BELLBOARD_INTEN4_TRIGGERED21_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED21 field.                           */
6533   #define BELLBOARD_INTEN4_TRIGGERED21_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED21 field.                           */
6534   #define BELLBOARD_INTEN4_TRIGGERED21_Disabled (0x0UL) /*!< Disable                                                           */
6535   #define BELLBOARD_INTEN4_TRIGGERED21_Enabled (0x1UL) /*!< Enable                                                             */
6536 
6537 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
6538   #define BELLBOARD_INTEN4_TRIGGERED22_Pos (22UL)    /*!< Position of TRIGGERED22 field.                                       */
6539   #define BELLBOARD_INTEN4_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.     */
6540   #define BELLBOARD_INTEN4_TRIGGERED22_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED22 field.                           */
6541   #define BELLBOARD_INTEN4_TRIGGERED22_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED22 field.                           */
6542   #define BELLBOARD_INTEN4_TRIGGERED22_Disabled (0x0UL) /*!< Disable                                                           */
6543   #define BELLBOARD_INTEN4_TRIGGERED22_Enabled (0x1UL) /*!< Enable                                                             */
6544 
6545 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
6546   #define BELLBOARD_INTEN4_TRIGGERED23_Pos (23UL)    /*!< Position of TRIGGERED23 field.                                       */
6547   #define BELLBOARD_INTEN4_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.     */
6548   #define BELLBOARD_INTEN4_TRIGGERED23_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED23 field.                           */
6549   #define BELLBOARD_INTEN4_TRIGGERED23_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED23 field.                           */
6550   #define BELLBOARD_INTEN4_TRIGGERED23_Disabled (0x0UL) /*!< Disable                                                           */
6551   #define BELLBOARD_INTEN4_TRIGGERED23_Enabled (0x1UL) /*!< Enable                                                             */
6552 
6553 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
6554   #define BELLBOARD_INTEN4_TRIGGERED24_Pos (24UL)    /*!< Position of TRIGGERED24 field.                                       */
6555   #define BELLBOARD_INTEN4_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.     */
6556   #define BELLBOARD_INTEN4_TRIGGERED24_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED24 field.                           */
6557   #define BELLBOARD_INTEN4_TRIGGERED24_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED24 field.                           */
6558   #define BELLBOARD_INTEN4_TRIGGERED24_Disabled (0x0UL) /*!< Disable                                                           */
6559   #define BELLBOARD_INTEN4_TRIGGERED24_Enabled (0x1UL) /*!< Enable                                                             */
6560 
6561 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
6562   #define BELLBOARD_INTEN4_TRIGGERED25_Pos (25UL)    /*!< Position of TRIGGERED25 field.                                       */
6563   #define BELLBOARD_INTEN4_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.     */
6564   #define BELLBOARD_INTEN4_TRIGGERED25_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED25 field.                           */
6565   #define BELLBOARD_INTEN4_TRIGGERED25_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED25 field.                           */
6566   #define BELLBOARD_INTEN4_TRIGGERED25_Disabled (0x0UL) /*!< Disable                                                           */
6567   #define BELLBOARD_INTEN4_TRIGGERED25_Enabled (0x1UL) /*!< Enable                                                             */
6568 
6569 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
6570   #define BELLBOARD_INTEN4_TRIGGERED26_Pos (26UL)    /*!< Position of TRIGGERED26 field.                                       */
6571   #define BELLBOARD_INTEN4_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.     */
6572   #define BELLBOARD_INTEN4_TRIGGERED26_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED26 field.                           */
6573   #define BELLBOARD_INTEN4_TRIGGERED26_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED26 field.                           */
6574   #define BELLBOARD_INTEN4_TRIGGERED26_Disabled (0x0UL) /*!< Disable                                                           */
6575   #define BELLBOARD_INTEN4_TRIGGERED26_Enabled (0x1UL) /*!< Enable                                                             */
6576 
6577 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
6578   #define BELLBOARD_INTEN4_TRIGGERED27_Pos (27UL)    /*!< Position of TRIGGERED27 field.                                       */
6579   #define BELLBOARD_INTEN4_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.     */
6580   #define BELLBOARD_INTEN4_TRIGGERED27_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED27 field.                           */
6581   #define BELLBOARD_INTEN4_TRIGGERED27_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED27 field.                           */
6582   #define BELLBOARD_INTEN4_TRIGGERED27_Disabled (0x0UL) /*!< Disable                                                           */
6583   #define BELLBOARD_INTEN4_TRIGGERED27_Enabled (0x1UL) /*!< Enable                                                             */
6584 
6585 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
6586   #define BELLBOARD_INTEN4_TRIGGERED28_Pos (28UL)    /*!< Position of TRIGGERED28 field.                                       */
6587   #define BELLBOARD_INTEN4_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.     */
6588   #define BELLBOARD_INTEN4_TRIGGERED28_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED28 field.                           */
6589   #define BELLBOARD_INTEN4_TRIGGERED28_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED28 field.                           */
6590   #define BELLBOARD_INTEN4_TRIGGERED28_Disabled (0x0UL) /*!< Disable                                                           */
6591   #define BELLBOARD_INTEN4_TRIGGERED28_Enabled (0x1UL) /*!< Enable                                                             */
6592 
6593 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
6594   #define BELLBOARD_INTEN4_TRIGGERED29_Pos (29UL)    /*!< Position of TRIGGERED29 field.                                       */
6595   #define BELLBOARD_INTEN4_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.     */
6596   #define BELLBOARD_INTEN4_TRIGGERED29_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED29 field.                           */
6597   #define BELLBOARD_INTEN4_TRIGGERED29_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED29 field.                           */
6598   #define BELLBOARD_INTEN4_TRIGGERED29_Disabled (0x0UL) /*!< Disable                                                           */
6599   #define BELLBOARD_INTEN4_TRIGGERED29_Enabled (0x1UL) /*!< Enable                                                             */
6600 
6601 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
6602   #define BELLBOARD_INTEN4_TRIGGERED30_Pos (30UL)    /*!< Position of TRIGGERED30 field.                                       */
6603   #define BELLBOARD_INTEN4_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.     */
6604   #define BELLBOARD_INTEN4_TRIGGERED30_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED30 field.                           */
6605   #define BELLBOARD_INTEN4_TRIGGERED30_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED30 field.                           */
6606   #define BELLBOARD_INTEN4_TRIGGERED30_Disabled (0x0UL) /*!< Disable                                                           */
6607   #define BELLBOARD_INTEN4_TRIGGERED30_Enabled (0x1UL) /*!< Enable                                                             */
6608 
6609 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
6610   #define BELLBOARD_INTEN4_TRIGGERED31_Pos (31UL)    /*!< Position of TRIGGERED31 field.                                       */
6611   #define BELLBOARD_INTEN4_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN4_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.     */
6612   #define BELLBOARD_INTEN4_TRIGGERED31_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED31 field.                           */
6613   #define BELLBOARD_INTEN4_TRIGGERED31_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED31 field.                           */
6614   #define BELLBOARD_INTEN4_TRIGGERED31_Disabled (0x0UL) /*!< Disable                                                           */
6615   #define BELLBOARD_INTEN4_TRIGGERED31_Enabled (0x1UL) /*!< Enable                                                             */
6616 
6617 
6618 /* BELLBOARD_INTENSET4: Enable interrupt */
6619   #define BELLBOARD_INTENSET4_ResetValue (0x00000000UL) /*!< Reset value of INTENSET4 register.                                */
6620 
6621 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
6622   #define BELLBOARD_INTENSET4_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
6623   #define BELLBOARD_INTENSET4_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
6624   #define BELLBOARD_INTENSET4_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
6625   #define BELLBOARD_INTENSET4_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
6626   #define BELLBOARD_INTENSET4_TRIGGERED0_Set (0x1UL) /*!< Enable                                                               */
6627   #define BELLBOARD_INTENSET4_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6628   #define BELLBOARD_INTENSET4_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6629 
6630 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
6631   #define BELLBOARD_INTENSET4_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
6632   #define BELLBOARD_INTENSET4_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
6633   #define BELLBOARD_INTENSET4_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
6634   #define BELLBOARD_INTENSET4_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
6635   #define BELLBOARD_INTENSET4_TRIGGERED1_Set (0x1UL) /*!< Enable                                                               */
6636   #define BELLBOARD_INTENSET4_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6637   #define BELLBOARD_INTENSET4_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6638 
6639 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
6640   #define BELLBOARD_INTENSET4_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
6641   #define BELLBOARD_INTENSET4_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
6642   #define BELLBOARD_INTENSET4_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
6643   #define BELLBOARD_INTENSET4_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
6644   #define BELLBOARD_INTENSET4_TRIGGERED2_Set (0x1UL) /*!< Enable                                                               */
6645   #define BELLBOARD_INTENSET4_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6646   #define BELLBOARD_INTENSET4_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6647 
6648 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
6649   #define BELLBOARD_INTENSET4_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
6650   #define BELLBOARD_INTENSET4_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
6651   #define BELLBOARD_INTENSET4_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
6652   #define BELLBOARD_INTENSET4_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
6653   #define BELLBOARD_INTENSET4_TRIGGERED3_Set (0x1UL) /*!< Enable                                                               */
6654   #define BELLBOARD_INTENSET4_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6655   #define BELLBOARD_INTENSET4_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6656 
6657 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
6658   #define BELLBOARD_INTENSET4_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
6659   #define BELLBOARD_INTENSET4_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
6660   #define BELLBOARD_INTENSET4_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
6661   #define BELLBOARD_INTENSET4_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
6662   #define BELLBOARD_INTENSET4_TRIGGERED4_Set (0x1UL) /*!< Enable                                                               */
6663   #define BELLBOARD_INTENSET4_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6664   #define BELLBOARD_INTENSET4_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6665 
6666 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
6667   #define BELLBOARD_INTENSET4_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
6668   #define BELLBOARD_INTENSET4_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
6669   #define BELLBOARD_INTENSET4_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
6670   #define BELLBOARD_INTENSET4_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
6671   #define BELLBOARD_INTENSET4_TRIGGERED5_Set (0x1UL) /*!< Enable                                                               */
6672   #define BELLBOARD_INTENSET4_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6673   #define BELLBOARD_INTENSET4_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6674 
6675 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
6676   #define BELLBOARD_INTENSET4_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
6677   #define BELLBOARD_INTENSET4_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
6678   #define BELLBOARD_INTENSET4_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
6679   #define BELLBOARD_INTENSET4_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
6680   #define BELLBOARD_INTENSET4_TRIGGERED6_Set (0x1UL) /*!< Enable                                                               */
6681   #define BELLBOARD_INTENSET4_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6682   #define BELLBOARD_INTENSET4_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6683 
6684 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
6685   #define BELLBOARD_INTENSET4_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
6686   #define BELLBOARD_INTENSET4_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
6687   #define BELLBOARD_INTENSET4_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
6688   #define BELLBOARD_INTENSET4_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
6689   #define BELLBOARD_INTENSET4_TRIGGERED7_Set (0x1UL) /*!< Enable                                                               */
6690   #define BELLBOARD_INTENSET4_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6691   #define BELLBOARD_INTENSET4_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6692 
6693 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
6694   #define BELLBOARD_INTENSET4_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
6695   #define BELLBOARD_INTENSET4_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
6696   #define BELLBOARD_INTENSET4_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
6697   #define BELLBOARD_INTENSET4_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
6698   #define BELLBOARD_INTENSET4_TRIGGERED8_Set (0x1UL) /*!< Enable                                                               */
6699   #define BELLBOARD_INTENSET4_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6700   #define BELLBOARD_INTENSET4_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6701 
6702 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
6703   #define BELLBOARD_INTENSET4_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
6704   #define BELLBOARD_INTENSET4_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
6705   #define BELLBOARD_INTENSET4_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
6706   #define BELLBOARD_INTENSET4_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
6707   #define BELLBOARD_INTENSET4_TRIGGERED9_Set (0x1UL) /*!< Enable                                                               */
6708   #define BELLBOARD_INTENSET4_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6709   #define BELLBOARD_INTENSET4_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6710 
6711 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
6712   #define BELLBOARD_INTENSET4_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
6713   #define BELLBOARD_INTENSET4_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
6714                                                                             field.*/
6715   #define BELLBOARD_INTENSET4_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
6716   #define BELLBOARD_INTENSET4_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
6717   #define BELLBOARD_INTENSET4_TRIGGERED10_Set (0x1UL) /*!< Enable                                                              */
6718   #define BELLBOARD_INTENSET4_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6719   #define BELLBOARD_INTENSET4_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6720 
6721 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
6722   #define BELLBOARD_INTENSET4_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
6723   #define BELLBOARD_INTENSET4_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
6724                                                                             field.*/
6725   #define BELLBOARD_INTENSET4_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
6726   #define BELLBOARD_INTENSET4_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
6727   #define BELLBOARD_INTENSET4_TRIGGERED11_Set (0x1UL) /*!< Enable                                                              */
6728   #define BELLBOARD_INTENSET4_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6729   #define BELLBOARD_INTENSET4_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6730 
6731 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
6732   #define BELLBOARD_INTENSET4_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
6733   #define BELLBOARD_INTENSET4_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
6734                                                                             field.*/
6735   #define BELLBOARD_INTENSET4_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
6736   #define BELLBOARD_INTENSET4_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
6737   #define BELLBOARD_INTENSET4_TRIGGERED12_Set (0x1UL) /*!< Enable                                                              */
6738   #define BELLBOARD_INTENSET4_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6739   #define BELLBOARD_INTENSET4_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6740 
6741 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
6742   #define BELLBOARD_INTENSET4_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
6743   #define BELLBOARD_INTENSET4_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
6744                                                                             field.*/
6745   #define BELLBOARD_INTENSET4_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
6746   #define BELLBOARD_INTENSET4_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
6747   #define BELLBOARD_INTENSET4_TRIGGERED13_Set (0x1UL) /*!< Enable                                                              */
6748   #define BELLBOARD_INTENSET4_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6749   #define BELLBOARD_INTENSET4_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6750 
6751 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
6752   #define BELLBOARD_INTENSET4_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
6753   #define BELLBOARD_INTENSET4_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
6754                                                                             field.*/
6755   #define BELLBOARD_INTENSET4_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
6756   #define BELLBOARD_INTENSET4_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
6757   #define BELLBOARD_INTENSET4_TRIGGERED14_Set (0x1UL) /*!< Enable                                                              */
6758   #define BELLBOARD_INTENSET4_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6759   #define BELLBOARD_INTENSET4_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6760 
6761 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
6762   #define BELLBOARD_INTENSET4_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
6763   #define BELLBOARD_INTENSET4_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
6764                                                                             field.*/
6765   #define BELLBOARD_INTENSET4_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
6766   #define BELLBOARD_INTENSET4_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
6767   #define BELLBOARD_INTENSET4_TRIGGERED15_Set (0x1UL) /*!< Enable                                                              */
6768   #define BELLBOARD_INTENSET4_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6769   #define BELLBOARD_INTENSET4_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6770 
6771 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
6772   #define BELLBOARD_INTENSET4_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
6773   #define BELLBOARD_INTENSET4_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
6774                                                                             field.*/
6775   #define BELLBOARD_INTENSET4_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
6776   #define BELLBOARD_INTENSET4_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
6777   #define BELLBOARD_INTENSET4_TRIGGERED16_Set (0x1UL) /*!< Enable                                                              */
6778   #define BELLBOARD_INTENSET4_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6779   #define BELLBOARD_INTENSET4_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6780 
6781 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
6782   #define BELLBOARD_INTENSET4_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
6783   #define BELLBOARD_INTENSET4_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
6784                                                                             field.*/
6785   #define BELLBOARD_INTENSET4_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
6786   #define BELLBOARD_INTENSET4_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
6787   #define BELLBOARD_INTENSET4_TRIGGERED17_Set (0x1UL) /*!< Enable                                                              */
6788   #define BELLBOARD_INTENSET4_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6789   #define BELLBOARD_INTENSET4_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6790 
6791 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
6792   #define BELLBOARD_INTENSET4_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
6793   #define BELLBOARD_INTENSET4_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
6794                                                                             field.*/
6795   #define BELLBOARD_INTENSET4_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
6796   #define BELLBOARD_INTENSET4_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
6797   #define BELLBOARD_INTENSET4_TRIGGERED18_Set (0x1UL) /*!< Enable                                                              */
6798   #define BELLBOARD_INTENSET4_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6799   #define BELLBOARD_INTENSET4_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6800 
6801 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
6802   #define BELLBOARD_INTENSET4_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
6803   #define BELLBOARD_INTENSET4_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
6804                                                                             field.*/
6805   #define BELLBOARD_INTENSET4_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
6806   #define BELLBOARD_INTENSET4_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
6807   #define BELLBOARD_INTENSET4_TRIGGERED19_Set (0x1UL) /*!< Enable                                                              */
6808   #define BELLBOARD_INTENSET4_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6809   #define BELLBOARD_INTENSET4_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6810 
6811 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
6812   #define BELLBOARD_INTENSET4_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
6813   #define BELLBOARD_INTENSET4_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
6814                                                                             field.*/
6815   #define BELLBOARD_INTENSET4_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
6816   #define BELLBOARD_INTENSET4_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
6817   #define BELLBOARD_INTENSET4_TRIGGERED20_Set (0x1UL) /*!< Enable                                                              */
6818   #define BELLBOARD_INTENSET4_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6819   #define BELLBOARD_INTENSET4_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6820 
6821 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
6822   #define BELLBOARD_INTENSET4_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
6823   #define BELLBOARD_INTENSET4_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
6824                                                                             field.*/
6825   #define BELLBOARD_INTENSET4_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
6826   #define BELLBOARD_INTENSET4_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
6827   #define BELLBOARD_INTENSET4_TRIGGERED21_Set (0x1UL) /*!< Enable                                                              */
6828   #define BELLBOARD_INTENSET4_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6829   #define BELLBOARD_INTENSET4_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6830 
6831 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
6832   #define BELLBOARD_INTENSET4_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
6833   #define BELLBOARD_INTENSET4_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
6834                                                                             field.*/
6835   #define BELLBOARD_INTENSET4_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
6836   #define BELLBOARD_INTENSET4_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
6837   #define BELLBOARD_INTENSET4_TRIGGERED22_Set (0x1UL) /*!< Enable                                                              */
6838   #define BELLBOARD_INTENSET4_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6839   #define BELLBOARD_INTENSET4_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6840 
6841 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
6842   #define BELLBOARD_INTENSET4_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
6843   #define BELLBOARD_INTENSET4_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
6844                                                                             field.*/
6845   #define BELLBOARD_INTENSET4_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
6846   #define BELLBOARD_INTENSET4_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
6847   #define BELLBOARD_INTENSET4_TRIGGERED23_Set (0x1UL) /*!< Enable                                                              */
6848   #define BELLBOARD_INTENSET4_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6849   #define BELLBOARD_INTENSET4_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6850 
6851 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
6852   #define BELLBOARD_INTENSET4_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
6853   #define BELLBOARD_INTENSET4_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
6854                                                                             field.*/
6855   #define BELLBOARD_INTENSET4_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
6856   #define BELLBOARD_INTENSET4_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
6857   #define BELLBOARD_INTENSET4_TRIGGERED24_Set (0x1UL) /*!< Enable                                                              */
6858   #define BELLBOARD_INTENSET4_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6859   #define BELLBOARD_INTENSET4_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6860 
6861 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
6862   #define BELLBOARD_INTENSET4_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
6863   #define BELLBOARD_INTENSET4_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
6864                                                                             field.*/
6865   #define BELLBOARD_INTENSET4_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
6866   #define BELLBOARD_INTENSET4_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
6867   #define BELLBOARD_INTENSET4_TRIGGERED25_Set (0x1UL) /*!< Enable                                                              */
6868   #define BELLBOARD_INTENSET4_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6869   #define BELLBOARD_INTENSET4_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6870 
6871 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
6872   #define BELLBOARD_INTENSET4_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
6873   #define BELLBOARD_INTENSET4_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
6874                                                                             field.*/
6875   #define BELLBOARD_INTENSET4_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
6876   #define BELLBOARD_INTENSET4_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
6877   #define BELLBOARD_INTENSET4_TRIGGERED26_Set (0x1UL) /*!< Enable                                                              */
6878   #define BELLBOARD_INTENSET4_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6879   #define BELLBOARD_INTENSET4_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6880 
6881 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
6882   #define BELLBOARD_INTENSET4_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
6883   #define BELLBOARD_INTENSET4_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
6884                                                                             field.*/
6885   #define BELLBOARD_INTENSET4_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
6886   #define BELLBOARD_INTENSET4_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
6887   #define BELLBOARD_INTENSET4_TRIGGERED27_Set (0x1UL) /*!< Enable                                                              */
6888   #define BELLBOARD_INTENSET4_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6889   #define BELLBOARD_INTENSET4_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6890 
6891 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
6892   #define BELLBOARD_INTENSET4_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
6893   #define BELLBOARD_INTENSET4_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
6894                                                                             field.*/
6895   #define BELLBOARD_INTENSET4_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
6896   #define BELLBOARD_INTENSET4_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
6897   #define BELLBOARD_INTENSET4_TRIGGERED28_Set (0x1UL) /*!< Enable                                                              */
6898   #define BELLBOARD_INTENSET4_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6899   #define BELLBOARD_INTENSET4_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6900 
6901 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
6902   #define BELLBOARD_INTENSET4_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
6903   #define BELLBOARD_INTENSET4_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
6904                                                                             field.*/
6905   #define BELLBOARD_INTENSET4_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
6906   #define BELLBOARD_INTENSET4_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
6907   #define BELLBOARD_INTENSET4_TRIGGERED29_Set (0x1UL) /*!< Enable                                                              */
6908   #define BELLBOARD_INTENSET4_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6909   #define BELLBOARD_INTENSET4_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6910 
6911 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
6912   #define BELLBOARD_INTENSET4_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
6913   #define BELLBOARD_INTENSET4_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
6914                                                                             field.*/
6915   #define BELLBOARD_INTENSET4_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
6916   #define BELLBOARD_INTENSET4_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
6917   #define BELLBOARD_INTENSET4_TRIGGERED30_Set (0x1UL) /*!< Enable                                                              */
6918   #define BELLBOARD_INTENSET4_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6919   #define BELLBOARD_INTENSET4_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6920 
6921 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
6922   #define BELLBOARD_INTENSET4_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
6923   #define BELLBOARD_INTENSET4_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET4_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
6924                                                                             field.*/
6925   #define BELLBOARD_INTENSET4_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
6926   #define BELLBOARD_INTENSET4_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
6927   #define BELLBOARD_INTENSET4_TRIGGERED31_Set (0x1UL) /*!< Enable                                                              */
6928   #define BELLBOARD_INTENSET4_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
6929   #define BELLBOARD_INTENSET4_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
6930 
6931 
6932 /* BELLBOARD_INTENCLR4: Disable interrupt */
6933   #define BELLBOARD_INTENCLR4_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR4 register.                                */
6934 
6935 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
6936   #define BELLBOARD_INTENCLR4_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
6937   #define BELLBOARD_INTENCLR4_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
6938   #define BELLBOARD_INTENCLR4_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
6939   #define BELLBOARD_INTENCLR4_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
6940   #define BELLBOARD_INTENCLR4_TRIGGERED0_Clear (0x1UL) /*!< Disable                                                            */
6941   #define BELLBOARD_INTENCLR4_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6942   #define BELLBOARD_INTENCLR4_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6943 
6944 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
6945   #define BELLBOARD_INTENCLR4_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
6946   #define BELLBOARD_INTENCLR4_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
6947   #define BELLBOARD_INTENCLR4_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
6948   #define BELLBOARD_INTENCLR4_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
6949   #define BELLBOARD_INTENCLR4_TRIGGERED1_Clear (0x1UL) /*!< Disable                                                            */
6950   #define BELLBOARD_INTENCLR4_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6951   #define BELLBOARD_INTENCLR4_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6952 
6953 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
6954   #define BELLBOARD_INTENCLR4_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
6955   #define BELLBOARD_INTENCLR4_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
6956   #define BELLBOARD_INTENCLR4_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
6957   #define BELLBOARD_INTENCLR4_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
6958   #define BELLBOARD_INTENCLR4_TRIGGERED2_Clear (0x1UL) /*!< Disable                                                            */
6959   #define BELLBOARD_INTENCLR4_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6960   #define BELLBOARD_INTENCLR4_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6961 
6962 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
6963   #define BELLBOARD_INTENCLR4_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
6964   #define BELLBOARD_INTENCLR4_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
6965   #define BELLBOARD_INTENCLR4_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
6966   #define BELLBOARD_INTENCLR4_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
6967   #define BELLBOARD_INTENCLR4_TRIGGERED3_Clear (0x1UL) /*!< Disable                                                            */
6968   #define BELLBOARD_INTENCLR4_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6969   #define BELLBOARD_INTENCLR4_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6970 
6971 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
6972   #define BELLBOARD_INTENCLR4_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
6973   #define BELLBOARD_INTENCLR4_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
6974   #define BELLBOARD_INTENCLR4_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
6975   #define BELLBOARD_INTENCLR4_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
6976   #define BELLBOARD_INTENCLR4_TRIGGERED4_Clear (0x1UL) /*!< Disable                                                            */
6977   #define BELLBOARD_INTENCLR4_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6978   #define BELLBOARD_INTENCLR4_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6979 
6980 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
6981   #define BELLBOARD_INTENCLR4_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
6982   #define BELLBOARD_INTENCLR4_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
6983   #define BELLBOARD_INTENCLR4_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
6984   #define BELLBOARD_INTENCLR4_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
6985   #define BELLBOARD_INTENCLR4_TRIGGERED5_Clear (0x1UL) /*!< Disable                                                            */
6986   #define BELLBOARD_INTENCLR4_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6987   #define BELLBOARD_INTENCLR4_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6988 
6989 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
6990   #define BELLBOARD_INTENCLR4_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
6991   #define BELLBOARD_INTENCLR4_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
6992   #define BELLBOARD_INTENCLR4_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
6993   #define BELLBOARD_INTENCLR4_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
6994   #define BELLBOARD_INTENCLR4_TRIGGERED6_Clear (0x1UL) /*!< Disable                                                            */
6995   #define BELLBOARD_INTENCLR4_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
6996   #define BELLBOARD_INTENCLR4_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
6997 
6998 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
6999   #define BELLBOARD_INTENCLR4_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
7000   #define BELLBOARD_INTENCLR4_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
7001   #define BELLBOARD_INTENCLR4_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
7002   #define BELLBOARD_INTENCLR4_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
7003   #define BELLBOARD_INTENCLR4_TRIGGERED7_Clear (0x1UL) /*!< Disable                                                            */
7004   #define BELLBOARD_INTENCLR4_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7005   #define BELLBOARD_INTENCLR4_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7006 
7007 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
7008   #define BELLBOARD_INTENCLR4_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
7009   #define BELLBOARD_INTENCLR4_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
7010   #define BELLBOARD_INTENCLR4_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
7011   #define BELLBOARD_INTENCLR4_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
7012   #define BELLBOARD_INTENCLR4_TRIGGERED8_Clear (0x1UL) /*!< Disable                                                            */
7013   #define BELLBOARD_INTENCLR4_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7014   #define BELLBOARD_INTENCLR4_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7015 
7016 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
7017   #define BELLBOARD_INTENCLR4_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
7018   #define BELLBOARD_INTENCLR4_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
7019   #define BELLBOARD_INTENCLR4_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
7020   #define BELLBOARD_INTENCLR4_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
7021   #define BELLBOARD_INTENCLR4_TRIGGERED9_Clear (0x1UL) /*!< Disable                                                            */
7022   #define BELLBOARD_INTENCLR4_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7023   #define BELLBOARD_INTENCLR4_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7024 
7025 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
7026   #define BELLBOARD_INTENCLR4_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
7027   #define BELLBOARD_INTENCLR4_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
7028                                                                             field.*/
7029   #define BELLBOARD_INTENCLR4_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
7030   #define BELLBOARD_INTENCLR4_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
7031   #define BELLBOARD_INTENCLR4_TRIGGERED10_Clear (0x1UL) /*!< Disable                                                           */
7032   #define BELLBOARD_INTENCLR4_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7033   #define BELLBOARD_INTENCLR4_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7034 
7035 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
7036   #define BELLBOARD_INTENCLR4_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
7037   #define BELLBOARD_INTENCLR4_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
7038                                                                             field.*/
7039   #define BELLBOARD_INTENCLR4_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
7040   #define BELLBOARD_INTENCLR4_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
7041   #define BELLBOARD_INTENCLR4_TRIGGERED11_Clear (0x1UL) /*!< Disable                                                           */
7042   #define BELLBOARD_INTENCLR4_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7043   #define BELLBOARD_INTENCLR4_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7044 
7045 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
7046   #define BELLBOARD_INTENCLR4_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
7047   #define BELLBOARD_INTENCLR4_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
7048                                                                             field.*/
7049   #define BELLBOARD_INTENCLR4_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
7050   #define BELLBOARD_INTENCLR4_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
7051   #define BELLBOARD_INTENCLR4_TRIGGERED12_Clear (0x1UL) /*!< Disable                                                           */
7052   #define BELLBOARD_INTENCLR4_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7053   #define BELLBOARD_INTENCLR4_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7054 
7055 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
7056   #define BELLBOARD_INTENCLR4_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
7057   #define BELLBOARD_INTENCLR4_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
7058                                                                             field.*/
7059   #define BELLBOARD_INTENCLR4_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
7060   #define BELLBOARD_INTENCLR4_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
7061   #define BELLBOARD_INTENCLR4_TRIGGERED13_Clear (0x1UL) /*!< Disable                                                           */
7062   #define BELLBOARD_INTENCLR4_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7063   #define BELLBOARD_INTENCLR4_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7064 
7065 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
7066   #define BELLBOARD_INTENCLR4_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
7067   #define BELLBOARD_INTENCLR4_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
7068                                                                             field.*/
7069   #define BELLBOARD_INTENCLR4_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
7070   #define BELLBOARD_INTENCLR4_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
7071   #define BELLBOARD_INTENCLR4_TRIGGERED14_Clear (0x1UL) /*!< Disable                                                           */
7072   #define BELLBOARD_INTENCLR4_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7073   #define BELLBOARD_INTENCLR4_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7074 
7075 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
7076   #define BELLBOARD_INTENCLR4_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
7077   #define BELLBOARD_INTENCLR4_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
7078                                                                             field.*/
7079   #define BELLBOARD_INTENCLR4_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
7080   #define BELLBOARD_INTENCLR4_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
7081   #define BELLBOARD_INTENCLR4_TRIGGERED15_Clear (0x1UL) /*!< Disable                                                           */
7082   #define BELLBOARD_INTENCLR4_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7083   #define BELLBOARD_INTENCLR4_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7084 
7085 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
7086   #define BELLBOARD_INTENCLR4_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
7087   #define BELLBOARD_INTENCLR4_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
7088                                                                             field.*/
7089   #define BELLBOARD_INTENCLR4_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
7090   #define BELLBOARD_INTENCLR4_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
7091   #define BELLBOARD_INTENCLR4_TRIGGERED16_Clear (0x1UL) /*!< Disable                                                           */
7092   #define BELLBOARD_INTENCLR4_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7093   #define BELLBOARD_INTENCLR4_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7094 
7095 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
7096   #define BELLBOARD_INTENCLR4_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
7097   #define BELLBOARD_INTENCLR4_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
7098                                                                             field.*/
7099   #define BELLBOARD_INTENCLR4_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
7100   #define BELLBOARD_INTENCLR4_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
7101   #define BELLBOARD_INTENCLR4_TRIGGERED17_Clear (0x1UL) /*!< Disable                                                           */
7102   #define BELLBOARD_INTENCLR4_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7103   #define BELLBOARD_INTENCLR4_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7104 
7105 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
7106   #define BELLBOARD_INTENCLR4_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
7107   #define BELLBOARD_INTENCLR4_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
7108                                                                             field.*/
7109   #define BELLBOARD_INTENCLR4_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
7110   #define BELLBOARD_INTENCLR4_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
7111   #define BELLBOARD_INTENCLR4_TRIGGERED18_Clear (0x1UL) /*!< Disable                                                           */
7112   #define BELLBOARD_INTENCLR4_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7113   #define BELLBOARD_INTENCLR4_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7114 
7115 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
7116   #define BELLBOARD_INTENCLR4_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
7117   #define BELLBOARD_INTENCLR4_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
7118                                                                             field.*/
7119   #define BELLBOARD_INTENCLR4_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
7120   #define BELLBOARD_INTENCLR4_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
7121   #define BELLBOARD_INTENCLR4_TRIGGERED19_Clear (0x1UL) /*!< Disable                                                           */
7122   #define BELLBOARD_INTENCLR4_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7123   #define BELLBOARD_INTENCLR4_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7124 
7125 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
7126   #define BELLBOARD_INTENCLR4_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
7127   #define BELLBOARD_INTENCLR4_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
7128                                                                             field.*/
7129   #define BELLBOARD_INTENCLR4_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
7130   #define BELLBOARD_INTENCLR4_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
7131   #define BELLBOARD_INTENCLR4_TRIGGERED20_Clear (0x1UL) /*!< Disable                                                           */
7132   #define BELLBOARD_INTENCLR4_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7133   #define BELLBOARD_INTENCLR4_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7134 
7135 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
7136   #define BELLBOARD_INTENCLR4_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
7137   #define BELLBOARD_INTENCLR4_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
7138                                                                             field.*/
7139   #define BELLBOARD_INTENCLR4_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
7140   #define BELLBOARD_INTENCLR4_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
7141   #define BELLBOARD_INTENCLR4_TRIGGERED21_Clear (0x1UL) /*!< Disable                                                           */
7142   #define BELLBOARD_INTENCLR4_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7143   #define BELLBOARD_INTENCLR4_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7144 
7145 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
7146   #define BELLBOARD_INTENCLR4_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
7147   #define BELLBOARD_INTENCLR4_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
7148                                                                             field.*/
7149   #define BELLBOARD_INTENCLR4_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
7150   #define BELLBOARD_INTENCLR4_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
7151   #define BELLBOARD_INTENCLR4_TRIGGERED22_Clear (0x1UL) /*!< Disable                                                           */
7152   #define BELLBOARD_INTENCLR4_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7153   #define BELLBOARD_INTENCLR4_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7154 
7155 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
7156   #define BELLBOARD_INTENCLR4_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
7157   #define BELLBOARD_INTENCLR4_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
7158                                                                             field.*/
7159   #define BELLBOARD_INTENCLR4_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
7160   #define BELLBOARD_INTENCLR4_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
7161   #define BELLBOARD_INTENCLR4_TRIGGERED23_Clear (0x1UL) /*!< Disable                                                           */
7162   #define BELLBOARD_INTENCLR4_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7163   #define BELLBOARD_INTENCLR4_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7164 
7165 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
7166   #define BELLBOARD_INTENCLR4_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
7167   #define BELLBOARD_INTENCLR4_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
7168                                                                             field.*/
7169   #define BELLBOARD_INTENCLR4_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
7170   #define BELLBOARD_INTENCLR4_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
7171   #define BELLBOARD_INTENCLR4_TRIGGERED24_Clear (0x1UL) /*!< Disable                                                           */
7172   #define BELLBOARD_INTENCLR4_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7173   #define BELLBOARD_INTENCLR4_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7174 
7175 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
7176   #define BELLBOARD_INTENCLR4_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
7177   #define BELLBOARD_INTENCLR4_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
7178                                                                             field.*/
7179   #define BELLBOARD_INTENCLR4_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
7180   #define BELLBOARD_INTENCLR4_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
7181   #define BELLBOARD_INTENCLR4_TRIGGERED25_Clear (0x1UL) /*!< Disable                                                           */
7182   #define BELLBOARD_INTENCLR4_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7183   #define BELLBOARD_INTENCLR4_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7184 
7185 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
7186   #define BELLBOARD_INTENCLR4_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
7187   #define BELLBOARD_INTENCLR4_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
7188                                                                             field.*/
7189   #define BELLBOARD_INTENCLR4_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
7190   #define BELLBOARD_INTENCLR4_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
7191   #define BELLBOARD_INTENCLR4_TRIGGERED26_Clear (0x1UL) /*!< Disable                                                           */
7192   #define BELLBOARD_INTENCLR4_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7193   #define BELLBOARD_INTENCLR4_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7194 
7195 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
7196   #define BELLBOARD_INTENCLR4_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
7197   #define BELLBOARD_INTENCLR4_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
7198                                                                             field.*/
7199   #define BELLBOARD_INTENCLR4_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
7200   #define BELLBOARD_INTENCLR4_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
7201   #define BELLBOARD_INTENCLR4_TRIGGERED27_Clear (0x1UL) /*!< Disable                                                           */
7202   #define BELLBOARD_INTENCLR4_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7203   #define BELLBOARD_INTENCLR4_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7204 
7205 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
7206   #define BELLBOARD_INTENCLR4_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
7207   #define BELLBOARD_INTENCLR4_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
7208                                                                             field.*/
7209   #define BELLBOARD_INTENCLR4_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
7210   #define BELLBOARD_INTENCLR4_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
7211   #define BELLBOARD_INTENCLR4_TRIGGERED28_Clear (0x1UL) /*!< Disable                                                           */
7212   #define BELLBOARD_INTENCLR4_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7213   #define BELLBOARD_INTENCLR4_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7214 
7215 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
7216   #define BELLBOARD_INTENCLR4_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
7217   #define BELLBOARD_INTENCLR4_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
7218                                                                             field.*/
7219   #define BELLBOARD_INTENCLR4_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
7220   #define BELLBOARD_INTENCLR4_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
7221   #define BELLBOARD_INTENCLR4_TRIGGERED29_Clear (0x1UL) /*!< Disable                                                           */
7222   #define BELLBOARD_INTENCLR4_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7223   #define BELLBOARD_INTENCLR4_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7224 
7225 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
7226   #define BELLBOARD_INTENCLR4_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
7227   #define BELLBOARD_INTENCLR4_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
7228                                                                             field.*/
7229   #define BELLBOARD_INTENCLR4_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
7230   #define BELLBOARD_INTENCLR4_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
7231   #define BELLBOARD_INTENCLR4_TRIGGERED30_Clear (0x1UL) /*!< Disable                                                           */
7232   #define BELLBOARD_INTENCLR4_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7233   #define BELLBOARD_INTENCLR4_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7234 
7235 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
7236   #define BELLBOARD_INTENCLR4_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
7237   #define BELLBOARD_INTENCLR4_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR4_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
7238                                                                             field.*/
7239   #define BELLBOARD_INTENCLR4_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
7240   #define BELLBOARD_INTENCLR4_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
7241   #define BELLBOARD_INTENCLR4_TRIGGERED31_Clear (0x1UL) /*!< Disable                                                           */
7242   #define BELLBOARD_INTENCLR4_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7243   #define BELLBOARD_INTENCLR4_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7244 
7245 
7246 /* BELLBOARD_INTPEND4: Pending interrupts */
7247   #define BELLBOARD_INTPEND4_ResetValue (0x00000000UL) /*!< Reset value of INTPEND4 register.                                  */
7248 
7249 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
7250   #define BELLBOARD_INTPEND4_TRIGGERED0_Pos (0UL)    /*!< Position of TRIGGERED0 field.                                        */
7251   #define BELLBOARD_INTPEND4_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.    */
7252   #define BELLBOARD_INTPEND4_TRIGGERED0_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED0 field.                            */
7253   #define BELLBOARD_INTPEND4_TRIGGERED0_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED0 field.                            */
7254   #define BELLBOARD_INTPEND4_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending                                              */
7255   #define BELLBOARD_INTPEND4_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending                                                     */
7256 
7257 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
7258   #define BELLBOARD_INTPEND4_TRIGGERED1_Pos (1UL)    /*!< Position of TRIGGERED1 field.                                        */
7259   #define BELLBOARD_INTPEND4_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.    */
7260   #define BELLBOARD_INTPEND4_TRIGGERED1_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED1 field.                            */
7261   #define BELLBOARD_INTPEND4_TRIGGERED1_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED1 field.                            */
7262   #define BELLBOARD_INTPEND4_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending                                              */
7263   #define BELLBOARD_INTPEND4_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending                                                     */
7264 
7265 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
7266   #define BELLBOARD_INTPEND4_TRIGGERED2_Pos (2UL)    /*!< Position of TRIGGERED2 field.                                        */
7267   #define BELLBOARD_INTPEND4_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.    */
7268   #define BELLBOARD_INTPEND4_TRIGGERED2_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED2 field.                            */
7269   #define BELLBOARD_INTPEND4_TRIGGERED2_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED2 field.                            */
7270   #define BELLBOARD_INTPEND4_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending                                              */
7271   #define BELLBOARD_INTPEND4_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending                                                     */
7272 
7273 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
7274   #define BELLBOARD_INTPEND4_TRIGGERED3_Pos (3UL)    /*!< Position of TRIGGERED3 field.                                        */
7275   #define BELLBOARD_INTPEND4_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.    */
7276   #define BELLBOARD_INTPEND4_TRIGGERED3_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED3 field.                            */
7277   #define BELLBOARD_INTPEND4_TRIGGERED3_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED3 field.                            */
7278   #define BELLBOARD_INTPEND4_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending                                              */
7279   #define BELLBOARD_INTPEND4_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending                                                     */
7280 
7281 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
7282   #define BELLBOARD_INTPEND4_TRIGGERED4_Pos (4UL)    /*!< Position of TRIGGERED4 field.                                        */
7283   #define BELLBOARD_INTPEND4_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.    */
7284   #define BELLBOARD_INTPEND4_TRIGGERED4_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED4 field.                            */
7285   #define BELLBOARD_INTPEND4_TRIGGERED4_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED4 field.                            */
7286   #define BELLBOARD_INTPEND4_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending                                              */
7287   #define BELLBOARD_INTPEND4_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending                                                     */
7288 
7289 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
7290   #define BELLBOARD_INTPEND4_TRIGGERED5_Pos (5UL)    /*!< Position of TRIGGERED5 field.                                        */
7291   #define BELLBOARD_INTPEND4_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.    */
7292   #define BELLBOARD_INTPEND4_TRIGGERED5_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED5 field.                            */
7293   #define BELLBOARD_INTPEND4_TRIGGERED5_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED5 field.                            */
7294   #define BELLBOARD_INTPEND4_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending                                              */
7295   #define BELLBOARD_INTPEND4_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending                                                     */
7296 
7297 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
7298   #define BELLBOARD_INTPEND4_TRIGGERED6_Pos (6UL)    /*!< Position of TRIGGERED6 field.                                        */
7299   #define BELLBOARD_INTPEND4_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.    */
7300   #define BELLBOARD_INTPEND4_TRIGGERED6_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED6 field.                            */
7301   #define BELLBOARD_INTPEND4_TRIGGERED6_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED6 field.                            */
7302   #define BELLBOARD_INTPEND4_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending                                              */
7303   #define BELLBOARD_INTPEND4_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending                                                     */
7304 
7305 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
7306   #define BELLBOARD_INTPEND4_TRIGGERED7_Pos (7UL)    /*!< Position of TRIGGERED7 field.                                        */
7307   #define BELLBOARD_INTPEND4_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.    */
7308   #define BELLBOARD_INTPEND4_TRIGGERED7_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED7 field.                            */
7309   #define BELLBOARD_INTPEND4_TRIGGERED7_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED7 field.                            */
7310   #define BELLBOARD_INTPEND4_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending                                              */
7311   #define BELLBOARD_INTPEND4_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending                                                     */
7312 
7313 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
7314   #define BELLBOARD_INTPEND4_TRIGGERED8_Pos (8UL)    /*!< Position of TRIGGERED8 field.                                        */
7315   #define BELLBOARD_INTPEND4_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.    */
7316   #define BELLBOARD_INTPEND4_TRIGGERED8_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED8 field.                            */
7317   #define BELLBOARD_INTPEND4_TRIGGERED8_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED8 field.                            */
7318   #define BELLBOARD_INTPEND4_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending                                              */
7319   #define BELLBOARD_INTPEND4_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending                                                     */
7320 
7321 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
7322   #define BELLBOARD_INTPEND4_TRIGGERED9_Pos (9UL)    /*!< Position of TRIGGERED9 field.                                        */
7323   #define BELLBOARD_INTPEND4_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.    */
7324   #define BELLBOARD_INTPEND4_TRIGGERED9_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED9 field.                            */
7325   #define BELLBOARD_INTPEND4_TRIGGERED9_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED9 field.                            */
7326   #define BELLBOARD_INTPEND4_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending                                              */
7327   #define BELLBOARD_INTPEND4_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending                                                     */
7328 
7329 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
7330   #define BELLBOARD_INTPEND4_TRIGGERED10_Pos (10UL)  /*!< Position of TRIGGERED10 field.                                       */
7331   #define BELLBOARD_INTPEND4_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
7332   #define BELLBOARD_INTPEND4_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                           */
7333   #define BELLBOARD_INTPEND4_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                           */
7334   #define BELLBOARD_INTPEND4_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                             */
7335   #define BELLBOARD_INTPEND4_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending                                                    */
7336 
7337 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
7338   #define BELLBOARD_INTPEND4_TRIGGERED11_Pos (11UL)  /*!< Position of TRIGGERED11 field.                                       */
7339   #define BELLBOARD_INTPEND4_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
7340   #define BELLBOARD_INTPEND4_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                           */
7341   #define BELLBOARD_INTPEND4_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                           */
7342   #define BELLBOARD_INTPEND4_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                             */
7343   #define BELLBOARD_INTPEND4_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending                                                    */
7344 
7345 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
7346   #define BELLBOARD_INTPEND4_TRIGGERED12_Pos (12UL)  /*!< Position of TRIGGERED12 field.                                       */
7347   #define BELLBOARD_INTPEND4_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
7348   #define BELLBOARD_INTPEND4_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                           */
7349   #define BELLBOARD_INTPEND4_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                           */
7350   #define BELLBOARD_INTPEND4_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                             */
7351   #define BELLBOARD_INTPEND4_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending                                                    */
7352 
7353 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
7354   #define BELLBOARD_INTPEND4_TRIGGERED13_Pos (13UL)  /*!< Position of TRIGGERED13 field.                                       */
7355   #define BELLBOARD_INTPEND4_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
7356   #define BELLBOARD_INTPEND4_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                           */
7357   #define BELLBOARD_INTPEND4_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                           */
7358   #define BELLBOARD_INTPEND4_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                             */
7359   #define BELLBOARD_INTPEND4_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending                                                    */
7360 
7361 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
7362   #define BELLBOARD_INTPEND4_TRIGGERED14_Pos (14UL)  /*!< Position of TRIGGERED14 field.                                       */
7363   #define BELLBOARD_INTPEND4_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
7364   #define BELLBOARD_INTPEND4_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                           */
7365   #define BELLBOARD_INTPEND4_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                           */
7366   #define BELLBOARD_INTPEND4_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                             */
7367   #define BELLBOARD_INTPEND4_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending                                                    */
7368 
7369 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
7370   #define BELLBOARD_INTPEND4_TRIGGERED15_Pos (15UL)  /*!< Position of TRIGGERED15 field.                                       */
7371   #define BELLBOARD_INTPEND4_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
7372   #define BELLBOARD_INTPEND4_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                           */
7373   #define BELLBOARD_INTPEND4_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                           */
7374   #define BELLBOARD_INTPEND4_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                             */
7375   #define BELLBOARD_INTPEND4_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending                                                    */
7376 
7377 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
7378   #define BELLBOARD_INTPEND4_TRIGGERED16_Pos (16UL)  /*!< Position of TRIGGERED16 field.                                       */
7379   #define BELLBOARD_INTPEND4_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */
7380   #define BELLBOARD_INTPEND4_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                           */
7381   #define BELLBOARD_INTPEND4_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                           */
7382   #define BELLBOARD_INTPEND4_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                             */
7383   #define BELLBOARD_INTPEND4_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending                                                    */
7384 
7385 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
7386   #define BELLBOARD_INTPEND4_TRIGGERED17_Pos (17UL)  /*!< Position of TRIGGERED17 field.                                       */
7387   #define BELLBOARD_INTPEND4_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */
7388   #define BELLBOARD_INTPEND4_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                           */
7389   #define BELLBOARD_INTPEND4_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                           */
7390   #define BELLBOARD_INTPEND4_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                             */
7391   #define BELLBOARD_INTPEND4_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending                                                    */
7392 
7393 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
7394   #define BELLBOARD_INTPEND4_TRIGGERED18_Pos (18UL)  /*!< Position of TRIGGERED18 field.                                       */
7395   #define BELLBOARD_INTPEND4_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */
7396   #define BELLBOARD_INTPEND4_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                           */
7397   #define BELLBOARD_INTPEND4_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                           */
7398   #define BELLBOARD_INTPEND4_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                             */
7399   #define BELLBOARD_INTPEND4_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending                                                    */
7400 
7401 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
7402   #define BELLBOARD_INTPEND4_TRIGGERED19_Pos (19UL)  /*!< Position of TRIGGERED19 field.                                       */
7403   #define BELLBOARD_INTPEND4_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */
7404   #define BELLBOARD_INTPEND4_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                           */
7405   #define BELLBOARD_INTPEND4_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                           */
7406   #define BELLBOARD_INTPEND4_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                             */
7407   #define BELLBOARD_INTPEND4_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending                                                    */
7408 
7409 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
7410   #define BELLBOARD_INTPEND4_TRIGGERED20_Pos (20UL)  /*!< Position of TRIGGERED20 field.                                       */
7411   #define BELLBOARD_INTPEND4_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */
7412   #define BELLBOARD_INTPEND4_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                           */
7413   #define BELLBOARD_INTPEND4_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                           */
7414   #define BELLBOARD_INTPEND4_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                             */
7415   #define BELLBOARD_INTPEND4_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending                                                    */
7416 
7417 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
7418   #define BELLBOARD_INTPEND4_TRIGGERED21_Pos (21UL)  /*!< Position of TRIGGERED21 field.                                       */
7419   #define BELLBOARD_INTPEND4_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */
7420   #define BELLBOARD_INTPEND4_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                           */
7421   #define BELLBOARD_INTPEND4_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                           */
7422   #define BELLBOARD_INTPEND4_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                             */
7423   #define BELLBOARD_INTPEND4_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending                                                    */
7424 
7425 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
7426   #define BELLBOARD_INTPEND4_TRIGGERED22_Pos (22UL)  /*!< Position of TRIGGERED22 field.                                       */
7427   #define BELLBOARD_INTPEND4_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */
7428   #define BELLBOARD_INTPEND4_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                           */
7429   #define BELLBOARD_INTPEND4_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                           */
7430   #define BELLBOARD_INTPEND4_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                             */
7431   #define BELLBOARD_INTPEND4_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending                                                    */
7432 
7433 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
7434   #define BELLBOARD_INTPEND4_TRIGGERED23_Pos (23UL)  /*!< Position of TRIGGERED23 field.                                       */
7435   #define BELLBOARD_INTPEND4_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */
7436   #define BELLBOARD_INTPEND4_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                           */
7437   #define BELLBOARD_INTPEND4_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                           */
7438   #define BELLBOARD_INTPEND4_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                             */
7439   #define BELLBOARD_INTPEND4_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending                                                    */
7440 
7441 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
7442   #define BELLBOARD_INTPEND4_TRIGGERED24_Pos (24UL)  /*!< Position of TRIGGERED24 field.                                       */
7443   #define BELLBOARD_INTPEND4_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */
7444   #define BELLBOARD_INTPEND4_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                           */
7445   #define BELLBOARD_INTPEND4_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                           */
7446   #define BELLBOARD_INTPEND4_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                             */
7447   #define BELLBOARD_INTPEND4_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending                                                    */
7448 
7449 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
7450   #define BELLBOARD_INTPEND4_TRIGGERED25_Pos (25UL)  /*!< Position of TRIGGERED25 field.                                       */
7451   #define BELLBOARD_INTPEND4_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */
7452   #define BELLBOARD_INTPEND4_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                           */
7453   #define BELLBOARD_INTPEND4_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                           */
7454   #define BELLBOARD_INTPEND4_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                             */
7455   #define BELLBOARD_INTPEND4_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending                                                    */
7456 
7457 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
7458   #define BELLBOARD_INTPEND4_TRIGGERED26_Pos (26UL)  /*!< Position of TRIGGERED26 field.                                       */
7459   #define BELLBOARD_INTPEND4_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */
7460   #define BELLBOARD_INTPEND4_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                           */
7461   #define BELLBOARD_INTPEND4_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                           */
7462   #define BELLBOARD_INTPEND4_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                             */
7463   #define BELLBOARD_INTPEND4_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending                                                    */
7464 
7465 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
7466   #define BELLBOARD_INTPEND4_TRIGGERED27_Pos (27UL)  /*!< Position of TRIGGERED27 field.                                       */
7467   #define BELLBOARD_INTPEND4_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */
7468   #define BELLBOARD_INTPEND4_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                           */
7469   #define BELLBOARD_INTPEND4_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                           */
7470   #define BELLBOARD_INTPEND4_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                             */
7471   #define BELLBOARD_INTPEND4_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending                                                    */
7472 
7473 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
7474   #define BELLBOARD_INTPEND4_TRIGGERED28_Pos (28UL)  /*!< Position of TRIGGERED28 field.                                       */
7475   #define BELLBOARD_INTPEND4_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */
7476   #define BELLBOARD_INTPEND4_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                           */
7477   #define BELLBOARD_INTPEND4_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                           */
7478   #define BELLBOARD_INTPEND4_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                             */
7479   #define BELLBOARD_INTPEND4_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending                                                    */
7480 
7481 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
7482   #define BELLBOARD_INTPEND4_TRIGGERED29_Pos (29UL)  /*!< Position of TRIGGERED29 field.                                       */
7483   #define BELLBOARD_INTPEND4_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */
7484   #define BELLBOARD_INTPEND4_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                           */
7485   #define BELLBOARD_INTPEND4_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                           */
7486   #define BELLBOARD_INTPEND4_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                             */
7487   #define BELLBOARD_INTPEND4_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending                                                    */
7488 
7489 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
7490   #define BELLBOARD_INTPEND4_TRIGGERED30_Pos (30UL)  /*!< Position of TRIGGERED30 field.                                       */
7491   #define BELLBOARD_INTPEND4_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */
7492   #define BELLBOARD_INTPEND4_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                           */
7493   #define BELLBOARD_INTPEND4_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                           */
7494   #define BELLBOARD_INTPEND4_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                             */
7495   #define BELLBOARD_INTPEND4_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending                                                    */
7496 
7497 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
7498   #define BELLBOARD_INTPEND4_TRIGGERED31_Pos (31UL)  /*!< Position of TRIGGERED31 field.                                       */
7499   #define BELLBOARD_INTPEND4_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND4_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */
7500   #define BELLBOARD_INTPEND4_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                           */
7501   #define BELLBOARD_INTPEND4_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                           */
7502   #define BELLBOARD_INTPEND4_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                             */
7503   #define BELLBOARD_INTPEND4_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending                                                    */
7504 
7505 
7506 /* BELLBOARD_INTEN5: Enable or disable interrupt */
7507   #define BELLBOARD_INTEN5_ResetValue (0x00000000UL) /*!< Reset value of INTEN5 register.                                      */
7508 
7509 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
7510   #define BELLBOARD_INTEN5_TRIGGERED0_Pos (0UL)      /*!< Position of TRIGGERED0 field.                                        */
7511   #define BELLBOARD_INTEN5_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.        */
7512   #define BELLBOARD_INTEN5_TRIGGERED0_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED0 field.                            */
7513   #define BELLBOARD_INTEN5_TRIGGERED0_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED0 field.                            */
7514   #define BELLBOARD_INTEN5_TRIGGERED0_Disabled (0x0UL) /*!< Disable                                                            */
7515   #define BELLBOARD_INTEN5_TRIGGERED0_Enabled (0x1UL) /*!< Enable                                                              */
7516 
7517 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
7518   #define BELLBOARD_INTEN5_TRIGGERED1_Pos (1UL)      /*!< Position of TRIGGERED1 field.                                        */
7519   #define BELLBOARD_INTEN5_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.        */
7520   #define BELLBOARD_INTEN5_TRIGGERED1_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED1 field.                            */
7521   #define BELLBOARD_INTEN5_TRIGGERED1_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED1 field.                            */
7522   #define BELLBOARD_INTEN5_TRIGGERED1_Disabled (0x0UL) /*!< Disable                                                            */
7523   #define BELLBOARD_INTEN5_TRIGGERED1_Enabled (0x1UL) /*!< Enable                                                              */
7524 
7525 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
7526   #define BELLBOARD_INTEN5_TRIGGERED2_Pos (2UL)      /*!< Position of TRIGGERED2 field.                                        */
7527   #define BELLBOARD_INTEN5_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.        */
7528   #define BELLBOARD_INTEN5_TRIGGERED2_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED2 field.                            */
7529   #define BELLBOARD_INTEN5_TRIGGERED2_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED2 field.                            */
7530   #define BELLBOARD_INTEN5_TRIGGERED2_Disabled (0x0UL) /*!< Disable                                                            */
7531   #define BELLBOARD_INTEN5_TRIGGERED2_Enabled (0x1UL) /*!< Enable                                                              */
7532 
7533 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
7534   #define BELLBOARD_INTEN5_TRIGGERED3_Pos (3UL)      /*!< Position of TRIGGERED3 field.                                        */
7535   #define BELLBOARD_INTEN5_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.        */
7536   #define BELLBOARD_INTEN5_TRIGGERED3_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED3 field.                            */
7537   #define BELLBOARD_INTEN5_TRIGGERED3_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED3 field.                            */
7538   #define BELLBOARD_INTEN5_TRIGGERED3_Disabled (0x0UL) /*!< Disable                                                            */
7539   #define BELLBOARD_INTEN5_TRIGGERED3_Enabled (0x1UL) /*!< Enable                                                              */
7540 
7541 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
7542   #define BELLBOARD_INTEN5_TRIGGERED4_Pos (4UL)      /*!< Position of TRIGGERED4 field.                                        */
7543   #define BELLBOARD_INTEN5_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.        */
7544   #define BELLBOARD_INTEN5_TRIGGERED4_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED4 field.                            */
7545   #define BELLBOARD_INTEN5_TRIGGERED4_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED4 field.                            */
7546   #define BELLBOARD_INTEN5_TRIGGERED4_Disabled (0x0UL) /*!< Disable                                                            */
7547   #define BELLBOARD_INTEN5_TRIGGERED4_Enabled (0x1UL) /*!< Enable                                                              */
7548 
7549 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
7550   #define BELLBOARD_INTEN5_TRIGGERED5_Pos (5UL)      /*!< Position of TRIGGERED5 field.                                        */
7551   #define BELLBOARD_INTEN5_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.        */
7552   #define BELLBOARD_INTEN5_TRIGGERED5_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED5 field.                            */
7553   #define BELLBOARD_INTEN5_TRIGGERED5_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED5 field.                            */
7554   #define BELLBOARD_INTEN5_TRIGGERED5_Disabled (0x0UL) /*!< Disable                                                            */
7555   #define BELLBOARD_INTEN5_TRIGGERED5_Enabled (0x1UL) /*!< Enable                                                              */
7556 
7557 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
7558   #define BELLBOARD_INTEN5_TRIGGERED6_Pos (6UL)      /*!< Position of TRIGGERED6 field.                                        */
7559   #define BELLBOARD_INTEN5_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.        */
7560   #define BELLBOARD_INTEN5_TRIGGERED6_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED6 field.                            */
7561   #define BELLBOARD_INTEN5_TRIGGERED6_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED6 field.                            */
7562   #define BELLBOARD_INTEN5_TRIGGERED6_Disabled (0x0UL) /*!< Disable                                                            */
7563   #define BELLBOARD_INTEN5_TRIGGERED6_Enabled (0x1UL) /*!< Enable                                                              */
7564 
7565 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
7566   #define BELLBOARD_INTEN5_TRIGGERED7_Pos (7UL)      /*!< Position of TRIGGERED7 field.                                        */
7567   #define BELLBOARD_INTEN5_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.        */
7568   #define BELLBOARD_INTEN5_TRIGGERED7_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED7 field.                            */
7569   #define BELLBOARD_INTEN5_TRIGGERED7_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED7 field.                            */
7570   #define BELLBOARD_INTEN5_TRIGGERED7_Disabled (0x0UL) /*!< Disable                                                            */
7571   #define BELLBOARD_INTEN5_TRIGGERED7_Enabled (0x1UL) /*!< Enable                                                              */
7572 
7573 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
7574   #define BELLBOARD_INTEN5_TRIGGERED8_Pos (8UL)      /*!< Position of TRIGGERED8 field.                                        */
7575   #define BELLBOARD_INTEN5_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.        */
7576   #define BELLBOARD_INTEN5_TRIGGERED8_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED8 field.                            */
7577   #define BELLBOARD_INTEN5_TRIGGERED8_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED8 field.                            */
7578   #define BELLBOARD_INTEN5_TRIGGERED8_Disabled (0x0UL) /*!< Disable                                                            */
7579   #define BELLBOARD_INTEN5_TRIGGERED8_Enabled (0x1UL) /*!< Enable                                                              */
7580 
7581 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
7582   #define BELLBOARD_INTEN5_TRIGGERED9_Pos (9UL)      /*!< Position of TRIGGERED9 field.                                        */
7583   #define BELLBOARD_INTEN5_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.        */
7584   #define BELLBOARD_INTEN5_TRIGGERED9_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED9 field.                            */
7585   #define BELLBOARD_INTEN5_TRIGGERED9_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED9 field.                            */
7586   #define BELLBOARD_INTEN5_TRIGGERED9_Disabled (0x0UL) /*!< Disable                                                            */
7587   #define BELLBOARD_INTEN5_TRIGGERED9_Enabled (0x1UL) /*!< Enable                                                              */
7588 
7589 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
7590   #define BELLBOARD_INTEN5_TRIGGERED10_Pos (10UL)    /*!< Position of TRIGGERED10 field.                                       */
7591   #define BELLBOARD_INTEN5_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.     */
7592   #define BELLBOARD_INTEN5_TRIGGERED10_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED10 field.                           */
7593   #define BELLBOARD_INTEN5_TRIGGERED10_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED10 field.                           */
7594   #define BELLBOARD_INTEN5_TRIGGERED10_Disabled (0x0UL) /*!< Disable                                                           */
7595   #define BELLBOARD_INTEN5_TRIGGERED10_Enabled (0x1UL) /*!< Enable                                                             */
7596 
7597 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
7598   #define BELLBOARD_INTEN5_TRIGGERED11_Pos (11UL)    /*!< Position of TRIGGERED11 field.                                       */
7599   #define BELLBOARD_INTEN5_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.     */
7600   #define BELLBOARD_INTEN5_TRIGGERED11_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED11 field.                           */
7601   #define BELLBOARD_INTEN5_TRIGGERED11_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED11 field.                           */
7602   #define BELLBOARD_INTEN5_TRIGGERED11_Disabled (0x0UL) /*!< Disable                                                           */
7603   #define BELLBOARD_INTEN5_TRIGGERED11_Enabled (0x1UL) /*!< Enable                                                             */
7604 
7605 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
7606   #define BELLBOARD_INTEN5_TRIGGERED12_Pos (12UL)    /*!< Position of TRIGGERED12 field.                                       */
7607   #define BELLBOARD_INTEN5_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.     */
7608   #define BELLBOARD_INTEN5_TRIGGERED12_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED12 field.                           */
7609   #define BELLBOARD_INTEN5_TRIGGERED12_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED12 field.                           */
7610   #define BELLBOARD_INTEN5_TRIGGERED12_Disabled (0x0UL) /*!< Disable                                                           */
7611   #define BELLBOARD_INTEN5_TRIGGERED12_Enabled (0x1UL) /*!< Enable                                                             */
7612 
7613 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
7614   #define BELLBOARD_INTEN5_TRIGGERED13_Pos (13UL)    /*!< Position of TRIGGERED13 field.                                       */
7615   #define BELLBOARD_INTEN5_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.     */
7616   #define BELLBOARD_INTEN5_TRIGGERED13_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED13 field.                           */
7617   #define BELLBOARD_INTEN5_TRIGGERED13_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED13 field.                           */
7618   #define BELLBOARD_INTEN5_TRIGGERED13_Disabled (0x0UL) /*!< Disable                                                           */
7619   #define BELLBOARD_INTEN5_TRIGGERED13_Enabled (0x1UL) /*!< Enable                                                             */
7620 
7621 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
7622   #define BELLBOARD_INTEN5_TRIGGERED14_Pos (14UL)    /*!< Position of TRIGGERED14 field.                                       */
7623   #define BELLBOARD_INTEN5_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.     */
7624   #define BELLBOARD_INTEN5_TRIGGERED14_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED14 field.                           */
7625   #define BELLBOARD_INTEN5_TRIGGERED14_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED14 field.                           */
7626   #define BELLBOARD_INTEN5_TRIGGERED14_Disabled (0x0UL) /*!< Disable                                                           */
7627   #define BELLBOARD_INTEN5_TRIGGERED14_Enabled (0x1UL) /*!< Enable                                                             */
7628 
7629 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
7630   #define BELLBOARD_INTEN5_TRIGGERED15_Pos (15UL)    /*!< Position of TRIGGERED15 field.                                       */
7631   #define BELLBOARD_INTEN5_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.     */
7632   #define BELLBOARD_INTEN5_TRIGGERED15_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED15 field.                           */
7633   #define BELLBOARD_INTEN5_TRIGGERED15_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED15 field.                           */
7634   #define BELLBOARD_INTEN5_TRIGGERED15_Disabled (0x0UL) /*!< Disable                                                           */
7635   #define BELLBOARD_INTEN5_TRIGGERED15_Enabled (0x1UL) /*!< Enable                                                             */
7636 
7637 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
7638   #define BELLBOARD_INTEN5_TRIGGERED16_Pos (16UL)    /*!< Position of TRIGGERED16 field.                                       */
7639   #define BELLBOARD_INTEN5_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.     */
7640   #define BELLBOARD_INTEN5_TRIGGERED16_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED16 field.                           */
7641   #define BELLBOARD_INTEN5_TRIGGERED16_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED16 field.                           */
7642   #define BELLBOARD_INTEN5_TRIGGERED16_Disabled (0x0UL) /*!< Disable                                                           */
7643   #define BELLBOARD_INTEN5_TRIGGERED16_Enabled (0x1UL) /*!< Enable                                                             */
7644 
7645 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
7646   #define BELLBOARD_INTEN5_TRIGGERED17_Pos (17UL)    /*!< Position of TRIGGERED17 field.                                       */
7647   #define BELLBOARD_INTEN5_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.     */
7648   #define BELLBOARD_INTEN5_TRIGGERED17_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED17 field.                           */
7649   #define BELLBOARD_INTEN5_TRIGGERED17_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED17 field.                           */
7650   #define BELLBOARD_INTEN5_TRIGGERED17_Disabled (0x0UL) /*!< Disable                                                           */
7651   #define BELLBOARD_INTEN5_TRIGGERED17_Enabled (0x1UL) /*!< Enable                                                             */
7652 
7653 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
7654   #define BELLBOARD_INTEN5_TRIGGERED18_Pos (18UL)    /*!< Position of TRIGGERED18 field.                                       */
7655   #define BELLBOARD_INTEN5_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.     */
7656   #define BELLBOARD_INTEN5_TRIGGERED18_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED18 field.                           */
7657   #define BELLBOARD_INTEN5_TRIGGERED18_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED18 field.                           */
7658   #define BELLBOARD_INTEN5_TRIGGERED18_Disabled (0x0UL) /*!< Disable                                                           */
7659   #define BELLBOARD_INTEN5_TRIGGERED18_Enabled (0x1UL) /*!< Enable                                                             */
7660 
7661 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
7662   #define BELLBOARD_INTEN5_TRIGGERED19_Pos (19UL)    /*!< Position of TRIGGERED19 field.                                       */
7663   #define BELLBOARD_INTEN5_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.     */
7664   #define BELLBOARD_INTEN5_TRIGGERED19_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED19 field.                           */
7665   #define BELLBOARD_INTEN5_TRIGGERED19_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED19 field.                           */
7666   #define BELLBOARD_INTEN5_TRIGGERED19_Disabled (0x0UL) /*!< Disable                                                           */
7667   #define BELLBOARD_INTEN5_TRIGGERED19_Enabled (0x1UL) /*!< Enable                                                             */
7668 
7669 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
7670   #define BELLBOARD_INTEN5_TRIGGERED20_Pos (20UL)    /*!< Position of TRIGGERED20 field.                                       */
7671   #define BELLBOARD_INTEN5_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.     */
7672   #define BELLBOARD_INTEN5_TRIGGERED20_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED20 field.                           */
7673   #define BELLBOARD_INTEN5_TRIGGERED20_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED20 field.                           */
7674   #define BELLBOARD_INTEN5_TRIGGERED20_Disabled (0x0UL) /*!< Disable                                                           */
7675   #define BELLBOARD_INTEN5_TRIGGERED20_Enabled (0x1UL) /*!< Enable                                                             */
7676 
7677 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
7678   #define BELLBOARD_INTEN5_TRIGGERED21_Pos (21UL)    /*!< Position of TRIGGERED21 field.                                       */
7679   #define BELLBOARD_INTEN5_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.     */
7680   #define BELLBOARD_INTEN5_TRIGGERED21_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED21 field.                           */
7681   #define BELLBOARD_INTEN5_TRIGGERED21_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED21 field.                           */
7682   #define BELLBOARD_INTEN5_TRIGGERED21_Disabled (0x0UL) /*!< Disable                                                           */
7683   #define BELLBOARD_INTEN5_TRIGGERED21_Enabled (0x1UL) /*!< Enable                                                             */
7684 
7685 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
7686   #define BELLBOARD_INTEN5_TRIGGERED22_Pos (22UL)    /*!< Position of TRIGGERED22 field.                                       */
7687   #define BELLBOARD_INTEN5_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.     */
7688   #define BELLBOARD_INTEN5_TRIGGERED22_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED22 field.                           */
7689   #define BELLBOARD_INTEN5_TRIGGERED22_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED22 field.                           */
7690   #define BELLBOARD_INTEN5_TRIGGERED22_Disabled (0x0UL) /*!< Disable                                                           */
7691   #define BELLBOARD_INTEN5_TRIGGERED22_Enabled (0x1UL) /*!< Enable                                                             */
7692 
7693 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
7694   #define BELLBOARD_INTEN5_TRIGGERED23_Pos (23UL)    /*!< Position of TRIGGERED23 field.                                       */
7695   #define BELLBOARD_INTEN5_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.     */
7696   #define BELLBOARD_INTEN5_TRIGGERED23_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED23 field.                           */
7697   #define BELLBOARD_INTEN5_TRIGGERED23_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED23 field.                           */
7698   #define BELLBOARD_INTEN5_TRIGGERED23_Disabled (0x0UL) /*!< Disable                                                           */
7699   #define BELLBOARD_INTEN5_TRIGGERED23_Enabled (0x1UL) /*!< Enable                                                             */
7700 
7701 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
7702   #define BELLBOARD_INTEN5_TRIGGERED24_Pos (24UL)    /*!< Position of TRIGGERED24 field.                                       */
7703   #define BELLBOARD_INTEN5_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.     */
7704   #define BELLBOARD_INTEN5_TRIGGERED24_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED24 field.                           */
7705   #define BELLBOARD_INTEN5_TRIGGERED24_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED24 field.                           */
7706   #define BELLBOARD_INTEN5_TRIGGERED24_Disabled (0x0UL) /*!< Disable                                                           */
7707   #define BELLBOARD_INTEN5_TRIGGERED24_Enabled (0x1UL) /*!< Enable                                                             */
7708 
7709 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
7710   #define BELLBOARD_INTEN5_TRIGGERED25_Pos (25UL)    /*!< Position of TRIGGERED25 field.                                       */
7711   #define BELLBOARD_INTEN5_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.     */
7712   #define BELLBOARD_INTEN5_TRIGGERED25_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED25 field.                           */
7713   #define BELLBOARD_INTEN5_TRIGGERED25_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED25 field.                           */
7714   #define BELLBOARD_INTEN5_TRIGGERED25_Disabled (0x0UL) /*!< Disable                                                           */
7715   #define BELLBOARD_INTEN5_TRIGGERED25_Enabled (0x1UL) /*!< Enable                                                             */
7716 
7717 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
7718   #define BELLBOARD_INTEN5_TRIGGERED26_Pos (26UL)    /*!< Position of TRIGGERED26 field.                                       */
7719   #define BELLBOARD_INTEN5_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.     */
7720   #define BELLBOARD_INTEN5_TRIGGERED26_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED26 field.                           */
7721   #define BELLBOARD_INTEN5_TRIGGERED26_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED26 field.                           */
7722   #define BELLBOARD_INTEN5_TRIGGERED26_Disabled (0x0UL) /*!< Disable                                                           */
7723   #define BELLBOARD_INTEN5_TRIGGERED26_Enabled (0x1UL) /*!< Enable                                                             */
7724 
7725 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
7726   #define BELLBOARD_INTEN5_TRIGGERED27_Pos (27UL)    /*!< Position of TRIGGERED27 field.                                       */
7727   #define BELLBOARD_INTEN5_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.     */
7728   #define BELLBOARD_INTEN5_TRIGGERED27_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED27 field.                           */
7729   #define BELLBOARD_INTEN5_TRIGGERED27_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED27 field.                           */
7730   #define BELLBOARD_INTEN5_TRIGGERED27_Disabled (0x0UL) /*!< Disable                                                           */
7731   #define BELLBOARD_INTEN5_TRIGGERED27_Enabled (0x1UL) /*!< Enable                                                             */
7732 
7733 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
7734   #define BELLBOARD_INTEN5_TRIGGERED28_Pos (28UL)    /*!< Position of TRIGGERED28 field.                                       */
7735   #define BELLBOARD_INTEN5_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.     */
7736   #define BELLBOARD_INTEN5_TRIGGERED28_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED28 field.                           */
7737   #define BELLBOARD_INTEN5_TRIGGERED28_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED28 field.                           */
7738   #define BELLBOARD_INTEN5_TRIGGERED28_Disabled (0x0UL) /*!< Disable                                                           */
7739   #define BELLBOARD_INTEN5_TRIGGERED28_Enabled (0x1UL) /*!< Enable                                                             */
7740 
7741 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
7742   #define BELLBOARD_INTEN5_TRIGGERED29_Pos (29UL)    /*!< Position of TRIGGERED29 field.                                       */
7743   #define BELLBOARD_INTEN5_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.     */
7744   #define BELLBOARD_INTEN5_TRIGGERED29_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED29 field.                           */
7745   #define BELLBOARD_INTEN5_TRIGGERED29_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED29 field.                           */
7746   #define BELLBOARD_INTEN5_TRIGGERED29_Disabled (0x0UL) /*!< Disable                                                           */
7747   #define BELLBOARD_INTEN5_TRIGGERED29_Enabled (0x1UL) /*!< Enable                                                             */
7748 
7749 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
7750   #define BELLBOARD_INTEN5_TRIGGERED30_Pos (30UL)    /*!< Position of TRIGGERED30 field.                                       */
7751   #define BELLBOARD_INTEN5_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.     */
7752   #define BELLBOARD_INTEN5_TRIGGERED30_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED30 field.                           */
7753   #define BELLBOARD_INTEN5_TRIGGERED30_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED30 field.                           */
7754   #define BELLBOARD_INTEN5_TRIGGERED30_Disabled (0x0UL) /*!< Disable                                                           */
7755   #define BELLBOARD_INTEN5_TRIGGERED30_Enabled (0x1UL) /*!< Enable                                                             */
7756 
7757 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
7758   #define BELLBOARD_INTEN5_TRIGGERED31_Pos (31UL)    /*!< Position of TRIGGERED31 field.                                       */
7759   #define BELLBOARD_INTEN5_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN5_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.     */
7760   #define BELLBOARD_INTEN5_TRIGGERED31_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED31 field.                           */
7761   #define BELLBOARD_INTEN5_TRIGGERED31_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED31 field.                           */
7762   #define BELLBOARD_INTEN5_TRIGGERED31_Disabled (0x0UL) /*!< Disable                                                           */
7763   #define BELLBOARD_INTEN5_TRIGGERED31_Enabled (0x1UL) /*!< Enable                                                             */
7764 
7765 
7766 /* BELLBOARD_INTENSET5: Enable interrupt */
7767   #define BELLBOARD_INTENSET5_ResetValue (0x00000000UL) /*!< Reset value of INTENSET5 register.                                */
7768 
7769 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
7770   #define BELLBOARD_INTENSET5_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
7771   #define BELLBOARD_INTENSET5_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
7772   #define BELLBOARD_INTENSET5_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
7773   #define BELLBOARD_INTENSET5_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
7774   #define BELLBOARD_INTENSET5_TRIGGERED0_Set (0x1UL) /*!< Enable                                                               */
7775   #define BELLBOARD_INTENSET5_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7776   #define BELLBOARD_INTENSET5_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7777 
7778 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
7779   #define BELLBOARD_INTENSET5_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
7780   #define BELLBOARD_INTENSET5_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
7781   #define BELLBOARD_INTENSET5_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
7782   #define BELLBOARD_INTENSET5_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
7783   #define BELLBOARD_INTENSET5_TRIGGERED1_Set (0x1UL) /*!< Enable                                                               */
7784   #define BELLBOARD_INTENSET5_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7785   #define BELLBOARD_INTENSET5_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7786 
7787 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
7788   #define BELLBOARD_INTENSET5_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
7789   #define BELLBOARD_INTENSET5_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
7790   #define BELLBOARD_INTENSET5_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
7791   #define BELLBOARD_INTENSET5_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
7792   #define BELLBOARD_INTENSET5_TRIGGERED2_Set (0x1UL) /*!< Enable                                                               */
7793   #define BELLBOARD_INTENSET5_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7794   #define BELLBOARD_INTENSET5_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7795 
7796 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
7797   #define BELLBOARD_INTENSET5_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
7798   #define BELLBOARD_INTENSET5_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
7799   #define BELLBOARD_INTENSET5_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
7800   #define BELLBOARD_INTENSET5_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
7801   #define BELLBOARD_INTENSET5_TRIGGERED3_Set (0x1UL) /*!< Enable                                                               */
7802   #define BELLBOARD_INTENSET5_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7803   #define BELLBOARD_INTENSET5_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7804 
7805 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
7806   #define BELLBOARD_INTENSET5_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
7807   #define BELLBOARD_INTENSET5_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
7808   #define BELLBOARD_INTENSET5_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
7809   #define BELLBOARD_INTENSET5_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
7810   #define BELLBOARD_INTENSET5_TRIGGERED4_Set (0x1UL) /*!< Enable                                                               */
7811   #define BELLBOARD_INTENSET5_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7812   #define BELLBOARD_INTENSET5_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7813 
7814 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
7815   #define BELLBOARD_INTENSET5_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
7816   #define BELLBOARD_INTENSET5_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
7817   #define BELLBOARD_INTENSET5_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
7818   #define BELLBOARD_INTENSET5_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
7819   #define BELLBOARD_INTENSET5_TRIGGERED5_Set (0x1UL) /*!< Enable                                                               */
7820   #define BELLBOARD_INTENSET5_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7821   #define BELLBOARD_INTENSET5_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7822 
7823 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
7824   #define BELLBOARD_INTENSET5_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
7825   #define BELLBOARD_INTENSET5_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
7826   #define BELLBOARD_INTENSET5_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
7827   #define BELLBOARD_INTENSET5_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
7828   #define BELLBOARD_INTENSET5_TRIGGERED6_Set (0x1UL) /*!< Enable                                                               */
7829   #define BELLBOARD_INTENSET5_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7830   #define BELLBOARD_INTENSET5_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7831 
7832 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
7833   #define BELLBOARD_INTENSET5_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
7834   #define BELLBOARD_INTENSET5_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
7835   #define BELLBOARD_INTENSET5_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
7836   #define BELLBOARD_INTENSET5_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
7837   #define BELLBOARD_INTENSET5_TRIGGERED7_Set (0x1UL) /*!< Enable                                                               */
7838   #define BELLBOARD_INTENSET5_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7839   #define BELLBOARD_INTENSET5_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7840 
7841 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
7842   #define BELLBOARD_INTENSET5_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
7843   #define BELLBOARD_INTENSET5_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
7844   #define BELLBOARD_INTENSET5_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
7845   #define BELLBOARD_INTENSET5_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
7846   #define BELLBOARD_INTENSET5_TRIGGERED8_Set (0x1UL) /*!< Enable                                                               */
7847   #define BELLBOARD_INTENSET5_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7848   #define BELLBOARD_INTENSET5_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7849 
7850 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
7851   #define BELLBOARD_INTENSET5_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
7852   #define BELLBOARD_INTENSET5_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
7853   #define BELLBOARD_INTENSET5_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
7854   #define BELLBOARD_INTENSET5_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
7855   #define BELLBOARD_INTENSET5_TRIGGERED9_Set (0x1UL) /*!< Enable                                                               */
7856   #define BELLBOARD_INTENSET5_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
7857   #define BELLBOARD_INTENSET5_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
7858 
7859 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
7860   #define BELLBOARD_INTENSET5_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
7861   #define BELLBOARD_INTENSET5_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
7862                                                                             field.*/
7863   #define BELLBOARD_INTENSET5_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
7864   #define BELLBOARD_INTENSET5_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
7865   #define BELLBOARD_INTENSET5_TRIGGERED10_Set (0x1UL) /*!< Enable                                                              */
7866   #define BELLBOARD_INTENSET5_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7867   #define BELLBOARD_INTENSET5_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7868 
7869 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
7870   #define BELLBOARD_INTENSET5_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
7871   #define BELLBOARD_INTENSET5_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
7872                                                                             field.*/
7873   #define BELLBOARD_INTENSET5_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
7874   #define BELLBOARD_INTENSET5_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
7875   #define BELLBOARD_INTENSET5_TRIGGERED11_Set (0x1UL) /*!< Enable                                                              */
7876   #define BELLBOARD_INTENSET5_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7877   #define BELLBOARD_INTENSET5_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7878 
7879 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
7880   #define BELLBOARD_INTENSET5_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
7881   #define BELLBOARD_INTENSET5_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
7882                                                                             field.*/
7883   #define BELLBOARD_INTENSET5_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
7884   #define BELLBOARD_INTENSET5_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
7885   #define BELLBOARD_INTENSET5_TRIGGERED12_Set (0x1UL) /*!< Enable                                                              */
7886   #define BELLBOARD_INTENSET5_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7887   #define BELLBOARD_INTENSET5_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7888 
7889 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
7890   #define BELLBOARD_INTENSET5_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
7891   #define BELLBOARD_INTENSET5_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
7892                                                                             field.*/
7893   #define BELLBOARD_INTENSET5_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
7894   #define BELLBOARD_INTENSET5_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
7895   #define BELLBOARD_INTENSET5_TRIGGERED13_Set (0x1UL) /*!< Enable                                                              */
7896   #define BELLBOARD_INTENSET5_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7897   #define BELLBOARD_INTENSET5_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7898 
7899 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
7900   #define BELLBOARD_INTENSET5_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
7901   #define BELLBOARD_INTENSET5_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
7902                                                                             field.*/
7903   #define BELLBOARD_INTENSET5_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
7904   #define BELLBOARD_INTENSET5_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
7905   #define BELLBOARD_INTENSET5_TRIGGERED14_Set (0x1UL) /*!< Enable                                                              */
7906   #define BELLBOARD_INTENSET5_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7907   #define BELLBOARD_INTENSET5_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7908 
7909 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
7910   #define BELLBOARD_INTENSET5_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
7911   #define BELLBOARD_INTENSET5_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
7912                                                                             field.*/
7913   #define BELLBOARD_INTENSET5_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
7914   #define BELLBOARD_INTENSET5_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
7915   #define BELLBOARD_INTENSET5_TRIGGERED15_Set (0x1UL) /*!< Enable                                                              */
7916   #define BELLBOARD_INTENSET5_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7917   #define BELLBOARD_INTENSET5_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7918 
7919 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
7920   #define BELLBOARD_INTENSET5_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
7921   #define BELLBOARD_INTENSET5_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
7922                                                                             field.*/
7923   #define BELLBOARD_INTENSET5_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
7924   #define BELLBOARD_INTENSET5_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
7925   #define BELLBOARD_INTENSET5_TRIGGERED16_Set (0x1UL) /*!< Enable                                                              */
7926   #define BELLBOARD_INTENSET5_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7927   #define BELLBOARD_INTENSET5_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7928 
7929 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
7930   #define BELLBOARD_INTENSET5_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
7931   #define BELLBOARD_INTENSET5_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
7932                                                                             field.*/
7933   #define BELLBOARD_INTENSET5_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
7934   #define BELLBOARD_INTENSET5_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
7935   #define BELLBOARD_INTENSET5_TRIGGERED17_Set (0x1UL) /*!< Enable                                                              */
7936   #define BELLBOARD_INTENSET5_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7937   #define BELLBOARD_INTENSET5_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7938 
7939 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
7940   #define BELLBOARD_INTENSET5_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
7941   #define BELLBOARD_INTENSET5_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
7942                                                                             field.*/
7943   #define BELLBOARD_INTENSET5_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
7944   #define BELLBOARD_INTENSET5_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
7945   #define BELLBOARD_INTENSET5_TRIGGERED18_Set (0x1UL) /*!< Enable                                                              */
7946   #define BELLBOARD_INTENSET5_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7947   #define BELLBOARD_INTENSET5_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7948 
7949 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
7950   #define BELLBOARD_INTENSET5_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
7951   #define BELLBOARD_INTENSET5_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
7952                                                                             field.*/
7953   #define BELLBOARD_INTENSET5_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
7954   #define BELLBOARD_INTENSET5_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
7955   #define BELLBOARD_INTENSET5_TRIGGERED19_Set (0x1UL) /*!< Enable                                                              */
7956   #define BELLBOARD_INTENSET5_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7957   #define BELLBOARD_INTENSET5_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7958 
7959 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
7960   #define BELLBOARD_INTENSET5_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
7961   #define BELLBOARD_INTENSET5_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
7962                                                                             field.*/
7963   #define BELLBOARD_INTENSET5_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
7964   #define BELLBOARD_INTENSET5_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
7965   #define BELLBOARD_INTENSET5_TRIGGERED20_Set (0x1UL) /*!< Enable                                                              */
7966   #define BELLBOARD_INTENSET5_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7967   #define BELLBOARD_INTENSET5_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7968 
7969 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
7970   #define BELLBOARD_INTENSET5_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
7971   #define BELLBOARD_INTENSET5_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
7972                                                                             field.*/
7973   #define BELLBOARD_INTENSET5_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
7974   #define BELLBOARD_INTENSET5_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
7975   #define BELLBOARD_INTENSET5_TRIGGERED21_Set (0x1UL) /*!< Enable                                                              */
7976   #define BELLBOARD_INTENSET5_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7977   #define BELLBOARD_INTENSET5_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7978 
7979 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
7980   #define BELLBOARD_INTENSET5_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
7981   #define BELLBOARD_INTENSET5_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
7982                                                                             field.*/
7983   #define BELLBOARD_INTENSET5_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
7984   #define BELLBOARD_INTENSET5_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
7985   #define BELLBOARD_INTENSET5_TRIGGERED22_Set (0x1UL) /*!< Enable                                                              */
7986   #define BELLBOARD_INTENSET5_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7987   #define BELLBOARD_INTENSET5_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7988 
7989 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
7990   #define BELLBOARD_INTENSET5_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
7991   #define BELLBOARD_INTENSET5_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
7992                                                                             field.*/
7993   #define BELLBOARD_INTENSET5_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
7994   #define BELLBOARD_INTENSET5_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
7995   #define BELLBOARD_INTENSET5_TRIGGERED23_Set (0x1UL) /*!< Enable                                                              */
7996   #define BELLBOARD_INTENSET5_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
7997   #define BELLBOARD_INTENSET5_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
7998 
7999 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
8000   #define BELLBOARD_INTENSET5_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
8001   #define BELLBOARD_INTENSET5_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
8002                                                                             field.*/
8003   #define BELLBOARD_INTENSET5_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
8004   #define BELLBOARD_INTENSET5_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
8005   #define BELLBOARD_INTENSET5_TRIGGERED24_Set (0x1UL) /*!< Enable                                                              */
8006   #define BELLBOARD_INTENSET5_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8007   #define BELLBOARD_INTENSET5_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8008 
8009 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
8010   #define BELLBOARD_INTENSET5_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
8011   #define BELLBOARD_INTENSET5_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
8012                                                                             field.*/
8013   #define BELLBOARD_INTENSET5_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
8014   #define BELLBOARD_INTENSET5_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
8015   #define BELLBOARD_INTENSET5_TRIGGERED25_Set (0x1UL) /*!< Enable                                                              */
8016   #define BELLBOARD_INTENSET5_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8017   #define BELLBOARD_INTENSET5_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8018 
8019 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
8020   #define BELLBOARD_INTENSET5_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
8021   #define BELLBOARD_INTENSET5_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
8022                                                                             field.*/
8023   #define BELLBOARD_INTENSET5_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
8024   #define BELLBOARD_INTENSET5_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
8025   #define BELLBOARD_INTENSET5_TRIGGERED26_Set (0x1UL) /*!< Enable                                                              */
8026   #define BELLBOARD_INTENSET5_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8027   #define BELLBOARD_INTENSET5_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8028 
8029 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
8030   #define BELLBOARD_INTENSET5_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
8031   #define BELLBOARD_INTENSET5_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
8032                                                                             field.*/
8033   #define BELLBOARD_INTENSET5_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
8034   #define BELLBOARD_INTENSET5_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
8035   #define BELLBOARD_INTENSET5_TRIGGERED27_Set (0x1UL) /*!< Enable                                                              */
8036   #define BELLBOARD_INTENSET5_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8037   #define BELLBOARD_INTENSET5_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8038 
8039 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
8040   #define BELLBOARD_INTENSET5_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
8041   #define BELLBOARD_INTENSET5_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
8042                                                                             field.*/
8043   #define BELLBOARD_INTENSET5_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
8044   #define BELLBOARD_INTENSET5_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
8045   #define BELLBOARD_INTENSET5_TRIGGERED28_Set (0x1UL) /*!< Enable                                                              */
8046   #define BELLBOARD_INTENSET5_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8047   #define BELLBOARD_INTENSET5_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8048 
8049 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
8050   #define BELLBOARD_INTENSET5_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
8051   #define BELLBOARD_INTENSET5_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
8052                                                                             field.*/
8053   #define BELLBOARD_INTENSET5_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
8054   #define BELLBOARD_INTENSET5_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
8055   #define BELLBOARD_INTENSET5_TRIGGERED29_Set (0x1UL) /*!< Enable                                                              */
8056   #define BELLBOARD_INTENSET5_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8057   #define BELLBOARD_INTENSET5_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8058 
8059 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
8060   #define BELLBOARD_INTENSET5_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
8061   #define BELLBOARD_INTENSET5_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
8062                                                                             field.*/
8063   #define BELLBOARD_INTENSET5_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
8064   #define BELLBOARD_INTENSET5_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
8065   #define BELLBOARD_INTENSET5_TRIGGERED30_Set (0x1UL) /*!< Enable                                                              */
8066   #define BELLBOARD_INTENSET5_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8067   #define BELLBOARD_INTENSET5_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8068 
8069 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
8070   #define BELLBOARD_INTENSET5_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
8071   #define BELLBOARD_INTENSET5_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET5_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
8072                                                                             field.*/
8073   #define BELLBOARD_INTENSET5_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
8074   #define BELLBOARD_INTENSET5_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
8075   #define BELLBOARD_INTENSET5_TRIGGERED31_Set (0x1UL) /*!< Enable                                                              */
8076   #define BELLBOARD_INTENSET5_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8077   #define BELLBOARD_INTENSET5_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8078 
8079 
8080 /* BELLBOARD_INTENCLR5: Disable interrupt */
8081   #define BELLBOARD_INTENCLR5_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR5 register.                                */
8082 
8083 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
8084   #define BELLBOARD_INTENCLR5_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
8085   #define BELLBOARD_INTENCLR5_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
8086   #define BELLBOARD_INTENCLR5_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
8087   #define BELLBOARD_INTENCLR5_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
8088   #define BELLBOARD_INTENCLR5_TRIGGERED0_Clear (0x1UL) /*!< Disable                                                            */
8089   #define BELLBOARD_INTENCLR5_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8090   #define BELLBOARD_INTENCLR5_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8091 
8092 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
8093   #define BELLBOARD_INTENCLR5_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
8094   #define BELLBOARD_INTENCLR5_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
8095   #define BELLBOARD_INTENCLR5_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
8096   #define BELLBOARD_INTENCLR5_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
8097   #define BELLBOARD_INTENCLR5_TRIGGERED1_Clear (0x1UL) /*!< Disable                                                            */
8098   #define BELLBOARD_INTENCLR5_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8099   #define BELLBOARD_INTENCLR5_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8100 
8101 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
8102   #define BELLBOARD_INTENCLR5_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
8103   #define BELLBOARD_INTENCLR5_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
8104   #define BELLBOARD_INTENCLR5_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
8105   #define BELLBOARD_INTENCLR5_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
8106   #define BELLBOARD_INTENCLR5_TRIGGERED2_Clear (0x1UL) /*!< Disable                                                            */
8107   #define BELLBOARD_INTENCLR5_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8108   #define BELLBOARD_INTENCLR5_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8109 
8110 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
8111   #define BELLBOARD_INTENCLR5_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
8112   #define BELLBOARD_INTENCLR5_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
8113   #define BELLBOARD_INTENCLR5_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
8114   #define BELLBOARD_INTENCLR5_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
8115   #define BELLBOARD_INTENCLR5_TRIGGERED3_Clear (0x1UL) /*!< Disable                                                            */
8116   #define BELLBOARD_INTENCLR5_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8117   #define BELLBOARD_INTENCLR5_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8118 
8119 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
8120   #define BELLBOARD_INTENCLR5_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
8121   #define BELLBOARD_INTENCLR5_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
8122   #define BELLBOARD_INTENCLR5_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
8123   #define BELLBOARD_INTENCLR5_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
8124   #define BELLBOARD_INTENCLR5_TRIGGERED4_Clear (0x1UL) /*!< Disable                                                            */
8125   #define BELLBOARD_INTENCLR5_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8126   #define BELLBOARD_INTENCLR5_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8127 
8128 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
8129   #define BELLBOARD_INTENCLR5_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
8130   #define BELLBOARD_INTENCLR5_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
8131   #define BELLBOARD_INTENCLR5_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
8132   #define BELLBOARD_INTENCLR5_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
8133   #define BELLBOARD_INTENCLR5_TRIGGERED5_Clear (0x1UL) /*!< Disable                                                            */
8134   #define BELLBOARD_INTENCLR5_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8135   #define BELLBOARD_INTENCLR5_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8136 
8137 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
8138   #define BELLBOARD_INTENCLR5_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
8139   #define BELLBOARD_INTENCLR5_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
8140   #define BELLBOARD_INTENCLR5_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
8141   #define BELLBOARD_INTENCLR5_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
8142   #define BELLBOARD_INTENCLR5_TRIGGERED6_Clear (0x1UL) /*!< Disable                                                            */
8143   #define BELLBOARD_INTENCLR5_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8144   #define BELLBOARD_INTENCLR5_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8145 
8146 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
8147   #define BELLBOARD_INTENCLR5_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
8148   #define BELLBOARD_INTENCLR5_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
8149   #define BELLBOARD_INTENCLR5_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
8150   #define BELLBOARD_INTENCLR5_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
8151   #define BELLBOARD_INTENCLR5_TRIGGERED7_Clear (0x1UL) /*!< Disable                                                            */
8152   #define BELLBOARD_INTENCLR5_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8153   #define BELLBOARD_INTENCLR5_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8154 
8155 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
8156   #define BELLBOARD_INTENCLR5_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
8157   #define BELLBOARD_INTENCLR5_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
8158   #define BELLBOARD_INTENCLR5_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
8159   #define BELLBOARD_INTENCLR5_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
8160   #define BELLBOARD_INTENCLR5_TRIGGERED8_Clear (0x1UL) /*!< Disable                                                            */
8161   #define BELLBOARD_INTENCLR5_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8162   #define BELLBOARD_INTENCLR5_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8163 
8164 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
8165   #define BELLBOARD_INTENCLR5_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
8166   #define BELLBOARD_INTENCLR5_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
8167   #define BELLBOARD_INTENCLR5_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
8168   #define BELLBOARD_INTENCLR5_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
8169   #define BELLBOARD_INTENCLR5_TRIGGERED9_Clear (0x1UL) /*!< Disable                                                            */
8170   #define BELLBOARD_INTENCLR5_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8171   #define BELLBOARD_INTENCLR5_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8172 
8173 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
8174   #define BELLBOARD_INTENCLR5_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
8175   #define BELLBOARD_INTENCLR5_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
8176                                                                             field.*/
8177   #define BELLBOARD_INTENCLR5_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
8178   #define BELLBOARD_INTENCLR5_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
8179   #define BELLBOARD_INTENCLR5_TRIGGERED10_Clear (0x1UL) /*!< Disable                                                           */
8180   #define BELLBOARD_INTENCLR5_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8181   #define BELLBOARD_INTENCLR5_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8182 
8183 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
8184   #define BELLBOARD_INTENCLR5_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
8185   #define BELLBOARD_INTENCLR5_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
8186                                                                             field.*/
8187   #define BELLBOARD_INTENCLR5_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
8188   #define BELLBOARD_INTENCLR5_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
8189   #define BELLBOARD_INTENCLR5_TRIGGERED11_Clear (0x1UL) /*!< Disable                                                           */
8190   #define BELLBOARD_INTENCLR5_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8191   #define BELLBOARD_INTENCLR5_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8192 
8193 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
8194   #define BELLBOARD_INTENCLR5_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
8195   #define BELLBOARD_INTENCLR5_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
8196                                                                             field.*/
8197   #define BELLBOARD_INTENCLR5_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
8198   #define BELLBOARD_INTENCLR5_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
8199   #define BELLBOARD_INTENCLR5_TRIGGERED12_Clear (0x1UL) /*!< Disable                                                           */
8200   #define BELLBOARD_INTENCLR5_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8201   #define BELLBOARD_INTENCLR5_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8202 
8203 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
8204   #define BELLBOARD_INTENCLR5_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
8205   #define BELLBOARD_INTENCLR5_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
8206                                                                             field.*/
8207   #define BELLBOARD_INTENCLR5_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
8208   #define BELLBOARD_INTENCLR5_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
8209   #define BELLBOARD_INTENCLR5_TRIGGERED13_Clear (0x1UL) /*!< Disable                                                           */
8210   #define BELLBOARD_INTENCLR5_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8211   #define BELLBOARD_INTENCLR5_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8212 
8213 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
8214   #define BELLBOARD_INTENCLR5_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
8215   #define BELLBOARD_INTENCLR5_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
8216                                                                             field.*/
8217   #define BELLBOARD_INTENCLR5_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
8218   #define BELLBOARD_INTENCLR5_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
8219   #define BELLBOARD_INTENCLR5_TRIGGERED14_Clear (0x1UL) /*!< Disable                                                           */
8220   #define BELLBOARD_INTENCLR5_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8221   #define BELLBOARD_INTENCLR5_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8222 
8223 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
8224   #define BELLBOARD_INTENCLR5_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
8225   #define BELLBOARD_INTENCLR5_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
8226                                                                             field.*/
8227   #define BELLBOARD_INTENCLR5_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
8228   #define BELLBOARD_INTENCLR5_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
8229   #define BELLBOARD_INTENCLR5_TRIGGERED15_Clear (0x1UL) /*!< Disable                                                           */
8230   #define BELLBOARD_INTENCLR5_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8231   #define BELLBOARD_INTENCLR5_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8232 
8233 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
8234   #define BELLBOARD_INTENCLR5_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
8235   #define BELLBOARD_INTENCLR5_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
8236                                                                             field.*/
8237   #define BELLBOARD_INTENCLR5_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
8238   #define BELLBOARD_INTENCLR5_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
8239   #define BELLBOARD_INTENCLR5_TRIGGERED16_Clear (0x1UL) /*!< Disable                                                           */
8240   #define BELLBOARD_INTENCLR5_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8241   #define BELLBOARD_INTENCLR5_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8242 
8243 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
8244   #define BELLBOARD_INTENCLR5_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
8245   #define BELLBOARD_INTENCLR5_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
8246                                                                             field.*/
8247   #define BELLBOARD_INTENCLR5_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
8248   #define BELLBOARD_INTENCLR5_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
8249   #define BELLBOARD_INTENCLR5_TRIGGERED17_Clear (0x1UL) /*!< Disable                                                           */
8250   #define BELLBOARD_INTENCLR5_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8251   #define BELLBOARD_INTENCLR5_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8252 
8253 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
8254   #define BELLBOARD_INTENCLR5_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
8255   #define BELLBOARD_INTENCLR5_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
8256                                                                             field.*/
8257   #define BELLBOARD_INTENCLR5_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
8258   #define BELLBOARD_INTENCLR5_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
8259   #define BELLBOARD_INTENCLR5_TRIGGERED18_Clear (0x1UL) /*!< Disable                                                           */
8260   #define BELLBOARD_INTENCLR5_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8261   #define BELLBOARD_INTENCLR5_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8262 
8263 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
8264   #define BELLBOARD_INTENCLR5_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
8265   #define BELLBOARD_INTENCLR5_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
8266                                                                             field.*/
8267   #define BELLBOARD_INTENCLR5_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
8268   #define BELLBOARD_INTENCLR5_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
8269   #define BELLBOARD_INTENCLR5_TRIGGERED19_Clear (0x1UL) /*!< Disable                                                           */
8270   #define BELLBOARD_INTENCLR5_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8271   #define BELLBOARD_INTENCLR5_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8272 
8273 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
8274   #define BELLBOARD_INTENCLR5_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
8275   #define BELLBOARD_INTENCLR5_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
8276                                                                             field.*/
8277   #define BELLBOARD_INTENCLR5_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
8278   #define BELLBOARD_INTENCLR5_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
8279   #define BELLBOARD_INTENCLR5_TRIGGERED20_Clear (0x1UL) /*!< Disable                                                           */
8280   #define BELLBOARD_INTENCLR5_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8281   #define BELLBOARD_INTENCLR5_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8282 
8283 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
8284   #define BELLBOARD_INTENCLR5_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
8285   #define BELLBOARD_INTENCLR5_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
8286                                                                             field.*/
8287   #define BELLBOARD_INTENCLR5_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
8288   #define BELLBOARD_INTENCLR5_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
8289   #define BELLBOARD_INTENCLR5_TRIGGERED21_Clear (0x1UL) /*!< Disable                                                           */
8290   #define BELLBOARD_INTENCLR5_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8291   #define BELLBOARD_INTENCLR5_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8292 
8293 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
8294   #define BELLBOARD_INTENCLR5_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
8295   #define BELLBOARD_INTENCLR5_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
8296                                                                             field.*/
8297   #define BELLBOARD_INTENCLR5_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
8298   #define BELLBOARD_INTENCLR5_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
8299   #define BELLBOARD_INTENCLR5_TRIGGERED22_Clear (0x1UL) /*!< Disable                                                           */
8300   #define BELLBOARD_INTENCLR5_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8301   #define BELLBOARD_INTENCLR5_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8302 
8303 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
8304   #define BELLBOARD_INTENCLR5_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
8305   #define BELLBOARD_INTENCLR5_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
8306                                                                             field.*/
8307   #define BELLBOARD_INTENCLR5_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
8308   #define BELLBOARD_INTENCLR5_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
8309   #define BELLBOARD_INTENCLR5_TRIGGERED23_Clear (0x1UL) /*!< Disable                                                           */
8310   #define BELLBOARD_INTENCLR5_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8311   #define BELLBOARD_INTENCLR5_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8312 
8313 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
8314   #define BELLBOARD_INTENCLR5_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
8315   #define BELLBOARD_INTENCLR5_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
8316                                                                             field.*/
8317   #define BELLBOARD_INTENCLR5_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
8318   #define BELLBOARD_INTENCLR5_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
8319   #define BELLBOARD_INTENCLR5_TRIGGERED24_Clear (0x1UL) /*!< Disable                                                           */
8320   #define BELLBOARD_INTENCLR5_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8321   #define BELLBOARD_INTENCLR5_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8322 
8323 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
8324   #define BELLBOARD_INTENCLR5_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
8325   #define BELLBOARD_INTENCLR5_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
8326                                                                             field.*/
8327   #define BELLBOARD_INTENCLR5_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
8328   #define BELLBOARD_INTENCLR5_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
8329   #define BELLBOARD_INTENCLR5_TRIGGERED25_Clear (0x1UL) /*!< Disable                                                           */
8330   #define BELLBOARD_INTENCLR5_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8331   #define BELLBOARD_INTENCLR5_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8332 
8333 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
8334   #define BELLBOARD_INTENCLR5_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
8335   #define BELLBOARD_INTENCLR5_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
8336                                                                             field.*/
8337   #define BELLBOARD_INTENCLR5_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
8338   #define BELLBOARD_INTENCLR5_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
8339   #define BELLBOARD_INTENCLR5_TRIGGERED26_Clear (0x1UL) /*!< Disable                                                           */
8340   #define BELLBOARD_INTENCLR5_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8341   #define BELLBOARD_INTENCLR5_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8342 
8343 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
8344   #define BELLBOARD_INTENCLR5_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
8345   #define BELLBOARD_INTENCLR5_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
8346                                                                             field.*/
8347   #define BELLBOARD_INTENCLR5_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
8348   #define BELLBOARD_INTENCLR5_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
8349   #define BELLBOARD_INTENCLR5_TRIGGERED27_Clear (0x1UL) /*!< Disable                                                           */
8350   #define BELLBOARD_INTENCLR5_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8351   #define BELLBOARD_INTENCLR5_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8352 
8353 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
8354   #define BELLBOARD_INTENCLR5_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
8355   #define BELLBOARD_INTENCLR5_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
8356                                                                             field.*/
8357   #define BELLBOARD_INTENCLR5_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
8358   #define BELLBOARD_INTENCLR5_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
8359   #define BELLBOARD_INTENCLR5_TRIGGERED28_Clear (0x1UL) /*!< Disable                                                           */
8360   #define BELLBOARD_INTENCLR5_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8361   #define BELLBOARD_INTENCLR5_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8362 
8363 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
8364   #define BELLBOARD_INTENCLR5_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
8365   #define BELLBOARD_INTENCLR5_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
8366                                                                             field.*/
8367   #define BELLBOARD_INTENCLR5_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
8368   #define BELLBOARD_INTENCLR5_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
8369   #define BELLBOARD_INTENCLR5_TRIGGERED29_Clear (0x1UL) /*!< Disable                                                           */
8370   #define BELLBOARD_INTENCLR5_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8371   #define BELLBOARD_INTENCLR5_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8372 
8373 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
8374   #define BELLBOARD_INTENCLR5_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
8375   #define BELLBOARD_INTENCLR5_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
8376                                                                             field.*/
8377   #define BELLBOARD_INTENCLR5_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
8378   #define BELLBOARD_INTENCLR5_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
8379   #define BELLBOARD_INTENCLR5_TRIGGERED30_Clear (0x1UL) /*!< Disable                                                           */
8380   #define BELLBOARD_INTENCLR5_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8381   #define BELLBOARD_INTENCLR5_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8382 
8383 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
8384   #define BELLBOARD_INTENCLR5_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
8385   #define BELLBOARD_INTENCLR5_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR5_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
8386                                                                             field.*/
8387   #define BELLBOARD_INTENCLR5_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
8388   #define BELLBOARD_INTENCLR5_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
8389   #define BELLBOARD_INTENCLR5_TRIGGERED31_Clear (0x1UL) /*!< Disable                                                           */
8390   #define BELLBOARD_INTENCLR5_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
8391   #define BELLBOARD_INTENCLR5_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
8392 
8393 
8394 /* BELLBOARD_INTPEND5: Pending interrupts */
8395   #define BELLBOARD_INTPEND5_ResetValue (0x00000000UL) /*!< Reset value of INTPEND5 register.                                  */
8396 
8397 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
8398   #define BELLBOARD_INTPEND5_TRIGGERED0_Pos (0UL)    /*!< Position of TRIGGERED0 field.                                        */
8399   #define BELLBOARD_INTPEND5_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.    */
8400   #define BELLBOARD_INTPEND5_TRIGGERED0_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED0 field.                            */
8401   #define BELLBOARD_INTPEND5_TRIGGERED0_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED0 field.                            */
8402   #define BELLBOARD_INTPEND5_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending                                              */
8403   #define BELLBOARD_INTPEND5_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending                                                     */
8404 
8405 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
8406   #define BELLBOARD_INTPEND5_TRIGGERED1_Pos (1UL)    /*!< Position of TRIGGERED1 field.                                        */
8407   #define BELLBOARD_INTPEND5_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.    */
8408   #define BELLBOARD_INTPEND5_TRIGGERED1_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED1 field.                            */
8409   #define BELLBOARD_INTPEND5_TRIGGERED1_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED1 field.                            */
8410   #define BELLBOARD_INTPEND5_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending                                              */
8411   #define BELLBOARD_INTPEND5_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending                                                     */
8412 
8413 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
8414   #define BELLBOARD_INTPEND5_TRIGGERED2_Pos (2UL)    /*!< Position of TRIGGERED2 field.                                        */
8415   #define BELLBOARD_INTPEND5_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.    */
8416   #define BELLBOARD_INTPEND5_TRIGGERED2_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED2 field.                            */
8417   #define BELLBOARD_INTPEND5_TRIGGERED2_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED2 field.                            */
8418   #define BELLBOARD_INTPEND5_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending                                              */
8419   #define BELLBOARD_INTPEND5_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending                                                     */
8420 
8421 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
8422   #define BELLBOARD_INTPEND5_TRIGGERED3_Pos (3UL)    /*!< Position of TRIGGERED3 field.                                        */
8423   #define BELLBOARD_INTPEND5_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.    */
8424   #define BELLBOARD_INTPEND5_TRIGGERED3_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED3 field.                            */
8425   #define BELLBOARD_INTPEND5_TRIGGERED3_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED3 field.                            */
8426   #define BELLBOARD_INTPEND5_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending                                              */
8427   #define BELLBOARD_INTPEND5_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending                                                     */
8428 
8429 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
8430   #define BELLBOARD_INTPEND5_TRIGGERED4_Pos (4UL)    /*!< Position of TRIGGERED4 field.                                        */
8431   #define BELLBOARD_INTPEND5_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.    */
8432   #define BELLBOARD_INTPEND5_TRIGGERED4_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED4 field.                            */
8433   #define BELLBOARD_INTPEND5_TRIGGERED4_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED4 field.                            */
8434   #define BELLBOARD_INTPEND5_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending                                              */
8435   #define BELLBOARD_INTPEND5_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending                                                     */
8436 
8437 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
8438   #define BELLBOARD_INTPEND5_TRIGGERED5_Pos (5UL)    /*!< Position of TRIGGERED5 field.                                        */
8439   #define BELLBOARD_INTPEND5_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.    */
8440   #define BELLBOARD_INTPEND5_TRIGGERED5_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED5 field.                            */
8441   #define BELLBOARD_INTPEND5_TRIGGERED5_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED5 field.                            */
8442   #define BELLBOARD_INTPEND5_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending                                              */
8443   #define BELLBOARD_INTPEND5_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending                                                     */
8444 
8445 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
8446   #define BELLBOARD_INTPEND5_TRIGGERED6_Pos (6UL)    /*!< Position of TRIGGERED6 field.                                        */
8447   #define BELLBOARD_INTPEND5_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.    */
8448   #define BELLBOARD_INTPEND5_TRIGGERED6_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED6 field.                            */
8449   #define BELLBOARD_INTPEND5_TRIGGERED6_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED6 field.                            */
8450   #define BELLBOARD_INTPEND5_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending                                              */
8451   #define BELLBOARD_INTPEND5_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending                                                     */
8452 
8453 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
8454   #define BELLBOARD_INTPEND5_TRIGGERED7_Pos (7UL)    /*!< Position of TRIGGERED7 field.                                        */
8455   #define BELLBOARD_INTPEND5_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.    */
8456   #define BELLBOARD_INTPEND5_TRIGGERED7_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED7 field.                            */
8457   #define BELLBOARD_INTPEND5_TRIGGERED7_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED7 field.                            */
8458   #define BELLBOARD_INTPEND5_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending                                              */
8459   #define BELLBOARD_INTPEND5_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending                                                     */
8460 
8461 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
8462   #define BELLBOARD_INTPEND5_TRIGGERED8_Pos (8UL)    /*!< Position of TRIGGERED8 field.                                        */
8463   #define BELLBOARD_INTPEND5_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.    */
8464   #define BELLBOARD_INTPEND5_TRIGGERED8_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED8 field.                            */
8465   #define BELLBOARD_INTPEND5_TRIGGERED8_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED8 field.                            */
8466   #define BELLBOARD_INTPEND5_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending                                              */
8467   #define BELLBOARD_INTPEND5_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending                                                     */
8468 
8469 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
8470   #define BELLBOARD_INTPEND5_TRIGGERED9_Pos (9UL)    /*!< Position of TRIGGERED9 field.                                        */
8471   #define BELLBOARD_INTPEND5_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.    */
8472   #define BELLBOARD_INTPEND5_TRIGGERED9_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED9 field.                            */
8473   #define BELLBOARD_INTPEND5_TRIGGERED9_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED9 field.                            */
8474   #define BELLBOARD_INTPEND5_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending                                              */
8475   #define BELLBOARD_INTPEND5_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending                                                     */
8476 
8477 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
8478   #define BELLBOARD_INTPEND5_TRIGGERED10_Pos (10UL)  /*!< Position of TRIGGERED10 field.                                       */
8479   #define BELLBOARD_INTPEND5_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
8480   #define BELLBOARD_INTPEND5_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                           */
8481   #define BELLBOARD_INTPEND5_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                           */
8482   #define BELLBOARD_INTPEND5_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                             */
8483   #define BELLBOARD_INTPEND5_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending                                                    */
8484 
8485 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
8486   #define BELLBOARD_INTPEND5_TRIGGERED11_Pos (11UL)  /*!< Position of TRIGGERED11 field.                                       */
8487   #define BELLBOARD_INTPEND5_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
8488   #define BELLBOARD_INTPEND5_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                           */
8489   #define BELLBOARD_INTPEND5_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                           */
8490   #define BELLBOARD_INTPEND5_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                             */
8491   #define BELLBOARD_INTPEND5_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending                                                    */
8492 
8493 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
8494   #define BELLBOARD_INTPEND5_TRIGGERED12_Pos (12UL)  /*!< Position of TRIGGERED12 field.                                       */
8495   #define BELLBOARD_INTPEND5_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
8496   #define BELLBOARD_INTPEND5_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                           */
8497   #define BELLBOARD_INTPEND5_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                           */
8498   #define BELLBOARD_INTPEND5_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                             */
8499   #define BELLBOARD_INTPEND5_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending                                                    */
8500 
8501 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
8502   #define BELLBOARD_INTPEND5_TRIGGERED13_Pos (13UL)  /*!< Position of TRIGGERED13 field.                                       */
8503   #define BELLBOARD_INTPEND5_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
8504   #define BELLBOARD_INTPEND5_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                           */
8505   #define BELLBOARD_INTPEND5_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                           */
8506   #define BELLBOARD_INTPEND5_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                             */
8507   #define BELLBOARD_INTPEND5_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending                                                    */
8508 
8509 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
8510   #define BELLBOARD_INTPEND5_TRIGGERED14_Pos (14UL)  /*!< Position of TRIGGERED14 field.                                       */
8511   #define BELLBOARD_INTPEND5_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
8512   #define BELLBOARD_INTPEND5_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                           */
8513   #define BELLBOARD_INTPEND5_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                           */
8514   #define BELLBOARD_INTPEND5_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                             */
8515   #define BELLBOARD_INTPEND5_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending                                                    */
8516 
8517 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
8518   #define BELLBOARD_INTPEND5_TRIGGERED15_Pos (15UL)  /*!< Position of TRIGGERED15 field.                                       */
8519   #define BELLBOARD_INTPEND5_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
8520   #define BELLBOARD_INTPEND5_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                           */
8521   #define BELLBOARD_INTPEND5_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                           */
8522   #define BELLBOARD_INTPEND5_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                             */
8523   #define BELLBOARD_INTPEND5_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending                                                    */
8524 
8525 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
8526   #define BELLBOARD_INTPEND5_TRIGGERED16_Pos (16UL)  /*!< Position of TRIGGERED16 field.                                       */
8527   #define BELLBOARD_INTPEND5_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */
8528   #define BELLBOARD_INTPEND5_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                           */
8529   #define BELLBOARD_INTPEND5_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                           */
8530   #define BELLBOARD_INTPEND5_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                             */
8531   #define BELLBOARD_INTPEND5_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending                                                    */
8532 
8533 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
8534   #define BELLBOARD_INTPEND5_TRIGGERED17_Pos (17UL)  /*!< Position of TRIGGERED17 field.                                       */
8535   #define BELLBOARD_INTPEND5_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */
8536   #define BELLBOARD_INTPEND5_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                           */
8537   #define BELLBOARD_INTPEND5_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                           */
8538   #define BELLBOARD_INTPEND5_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                             */
8539   #define BELLBOARD_INTPEND5_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending                                                    */
8540 
8541 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
8542   #define BELLBOARD_INTPEND5_TRIGGERED18_Pos (18UL)  /*!< Position of TRIGGERED18 field.                                       */
8543   #define BELLBOARD_INTPEND5_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */
8544   #define BELLBOARD_INTPEND5_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                           */
8545   #define BELLBOARD_INTPEND5_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                           */
8546   #define BELLBOARD_INTPEND5_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                             */
8547   #define BELLBOARD_INTPEND5_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending                                                    */
8548 
8549 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
8550   #define BELLBOARD_INTPEND5_TRIGGERED19_Pos (19UL)  /*!< Position of TRIGGERED19 field.                                       */
8551   #define BELLBOARD_INTPEND5_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */
8552   #define BELLBOARD_INTPEND5_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                           */
8553   #define BELLBOARD_INTPEND5_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                           */
8554   #define BELLBOARD_INTPEND5_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                             */
8555   #define BELLBOARD_INTPEND5_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending                                                    */
8556 
8557 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
8558   #define BELLBOARD_INTPEND5_TRIGGERED20_Pos (20UL)  /*!< Position of TRIGGERED20 field.                                       */
8559   #define BELLBOARD_INTPEND5_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */
8560   #define BELLBOARD_INTPEND5_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                           */
8561   #define BELLBOARD_INTPEND5_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                           */
8562   #define BELLBOARD_INTPEND5_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                             */
8563   #define BELLBOARD_INTPEND5_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending                                                    */
8564 
8565 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
8566   #define BELLBOARD_INTPEND5_TRIGGERED21_Pos (21UL)  /*!< Position of TRIGGERED21 field.                                       */
8567   #define BELLBOARD_INTPEND5_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */
8568   #define BELLBOARD_INTPEND5_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                           */
8569   #define BELLBOARD_INTPEND5_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                           */
8570   #define BELLBOARD_INTPEND5_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                             */
8571   #define BELLBOARD_INTPEND5_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending                                                    */
8572 
8573 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
8574   #define BELLBOARD_INTPEND5_TRIGGERED22_Pos (22UL)  /*!< Position of TRIGGERED22 field.                                       */
8575   #define BELLBOARD_INTPEND5_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */
8576   #define BELLBOARD_INTPEND5_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                           */
8577   #define BELLBOARD_INTPEND5_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                           */
8578   #define BELLBOARD_INTPEND5_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                             */
8579   #define BELLBOARD_INTPEND5_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending                                                    */
8580 
8581 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
8582   #define BELLBOARD_INTPEND5_TRIGGERED23_Pos (23UL)  /*!< Position of TRIGGERED23 field.                                       */
8583   #define BELLBOARD_INTPEND5_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */
8584   #define BELLBOARD_INTPEND5_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                           */
8585   #define BELLBOARD_INTPEND5_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                           */
8586   #define BELLBOARD_INTPEND5_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                             */
8587   #define BELLBOARD_INTPEND5_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending                                                    */
8588 
8589 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
8590   #define BELLBOARD_INTPEND5_TRIGGERED24_Pos (24UL)  /*!< Position of TRIGGERED24 field.                                       */
8591   #define BELLBOARD_INTPEND5_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */
8592   #define BELLBOARD_INTPEND5_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                           */
8593   #define BELLBOARD_INTPEND5_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                           */
8594   #define BELLBOARD_INTPEND5_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                             */
8595   #define BELLBOARD_INTPEND5_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending                                                    */
8596 
8597 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
8598   #define BELLBOARD_INTPEND5_TRIGGERED25_Pos (25UL)  /*!< Position of TRIGGERED25 field.                                       */
8599   #define BELLBOARD_INTPEND5_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */
8600   #define BELLBOARD_INTPEND5_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                           */
8601   #define BELLBOARD_INTPEND5_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                           */
8602   #define BELLBOARD_INTPEND5_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                             */
8603   #define BELLBOARD_INTPEND5_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending                                                    */
8604 
8605 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
8606   #define BELLBOARD_INTPEND5_TRIGGERED26_Pos (26UL)  /*!< Position of TRIGGERED26 field.                                       */
8607   #define BELLBOARD_INTPEND5_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */
8608   #define BELLBOARD_INTPEND5_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                           */
8609   #define BELLBOARD_INTPEND5_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                           */
8610   #define BELLBOARD_INTPEND5_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                             */
8611   #define BELLBOARD_INTPEND5_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending                                                    */
8612 
8613 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
8614   #define BELLBOARD_INTPEND5_TRIGGERED27_Pos (27UL)  /*!< Position of TRIGGERED27 field.                                       */
8615   #define BELLBOARD_INTPEND5_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */
8616   #define BELLBOARD_INTPEND5_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                           */
8617   #define BELLBOARD_INTPEND5_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                           */
8618   #define BELLBOARD_INTPEND5_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                             */
8619   #define BELLBOARD_INTPEND5_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending                                                    */
8620 
8621 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
8622   #define BELLBOARD_INTPEND5_TRIGGERED28_Pos (28UL)  /*!< Position of TRIGGERED28 field.                                       */
8623   #define BELLBOARD_INTPEND5_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */
8624   #define BELLBOARD_INTPEND5_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                           */
8625   #define BELLBOARD_INTPEND5_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                           */
8626   #define BELLBOARD_INTPEND5_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                             */
8627   #define BELLBOARD_INTPEND5_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending                                                    */
8628 
8629 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
8630   #define BELLBOARD_INTPEND5_TRIGGERED29_Pos (29UL)  /*!< Position of TRIGGERED29 field.                                       */
8631   #define BELLBOARD_INTPEND5_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */
8632   #define BELLBOARD_INTPEND5_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                           */
8633   #define BELLBOARD_INTPEND5_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                           */
8634   #define BELLBOARD_INTPEND5_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                             */
8635   #define BELLBOARD_INTPEND5_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending                                                    */
8636 
8637 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
8638   #define BELLBOARD_INTPEND5_TRIGGERED30_Pos (30UL)  /*!< Position of TRIGGERED30 field.                                       */
8639   #define BELLBOARD_INTPEND5_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */
8640   #define BELLBOARD_INTPEND5_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                           */
8641   #define BELLBOARD_INTPEND5_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                           */
8642   #define BELLBOARD_INTPEND5_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                             */
8643   #define BELLBOARD_INTPEND5_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending                                                    */
8644 
8645 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
8646   #define BELLBOARD_INTPEND5_TRIGGERED31_Pos (31UL)  /*!< Position of TRIGGERED31 field.                                       */
8647   #define BELLBOARD_INTPEND5_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND5_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */
8648   #define BELLBOARD_INTPEND5_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                           */
8649   #define BELLBOARD_INTPEND5_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                           */
8650   #define BELLBOARD_INTPEND5_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                             */
8651   #define BELLBOARD_INTPEND5_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending                                                    */
8652 
8653 
8654 /* BELLBOARD_INTEN6: Enable or disable interrupt */
8655   #define BELLBOARD_INTEN6_ResetValue (0x00000000UL) /*!< Reset value of INTEN6 register.                                      */
8656 
8657 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
8658   #define BELLBOARD_INTEN6_TRIGGERED0_Pos (0UL)      /*!< Position of TRIGGERED0 field.                                        */
8659   #define BELLBOARD_INTEN6_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.        */
8660   #define BELLBOARD_INTEN6_TRIGGERED0_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED0 field.                            */
8661   #define BELLBOARD_INTEN6_TRIGGERED0_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED0 field.                            */
8662   #define BELLBOARD_INTEN6_TRIGGERED0_Disabled (0x0UL) /*!< Disable                                                            */
8663   #define BELLBOARD_INTEN6_TRIGGERED0_Enabled (0x1UL) /*!< Enable                                                              */
8664 
8665 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
8666   #define BELLBOARD_INTEN6_TRIGGERED1_Pos (1UL)      /*!< Position of TRIGGERED1 field.                                        */
8667   #define BELLBOARD_INTEN6_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.        */
8668   #define BELLBOARD_INTEN6_TRIGGERED1_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED1 field.                            */
8669   #define BELLBOARD_INTEN6_TRIGGERED1_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED1 field.                            */
8670   #define BELLBOARD_INTEN6_TRIGGERED1_Disabled (0x0UL) /*!< Disable                                                            */
8671   #define BELLBOARD_INTEN6_TRIGGERED1_Enabled (0x1UL) /*!< Enable                                                              */
8672 
8673 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
8674   #define BELLBOARD_INTEN6_TRIGGERED2_Pos (2UL)      /*!< Position of TRIGGERED2 field.                                        */
8675   #define BELLBOARD_INTEN6_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.        */
8676   #define BELLBOARD_INTEN6_TRIGGERED2_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED2 field.                            */
8677   #define BELLBOARD_INTEN6_TRIGGERED2_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED2 field.                            */
8678   #define BELLBOARD_INTEN6_TRIGGERED2_Disabled (0x0UL) /*!< Disable                                                            */
8679   #define BELLBOARD_INTEN6_TRIGGERED2_Enabled (0x1UL) /*!< Enable                                                              */
8680 
8681 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
8682   #define BELLBOARD_INTEN6_TRIGGERED3_Pos (3UL)      /*!< Position of TRIGGERED3 field.                                        */
8683   #define BELLBOARD_INTEN6_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.        */
8684   #define BELLBOARD_INTEN6_TRIGGERED3_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED3 field.                            */
8685   #define BELLBOARD_INTEN6_TRIGGERED3_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED3 field.                            */
8686   #define BELLBOARD_INTEN6_TRIGGERED3_Disabled (0x0UL) /*!< Disable                                                            */
8687   #define BELLBOARD_INTEN6_TRIGGERED3_Enabled (0x1UL) /*!< Enable                                                              */
8688 
8689 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
8690   #define BELLBOARD_INTEN6_TRIGGERED4_Pos (4UL)      /*!< Position of TRIGGERED4 field.                                        */
8691   #define BELLBOARD_INTEN6_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.        */
8692   #define BELLBOARD_INTEN6_TRIGGERED4_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED4 field.                            */
8693   #define BELLBOARD_INTEN6_TRIGGERED4_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED4 field.                            */
8694   #define BELLBOARD_INTEN6_TRIGGERED4_Disabled (0x0UL) /*!< Disable                                                            */
8695   #define BELLBOARD_INTEN6_TRIGGERED4_Enabled (0x1UL) /*!< Enable                                                              */
8696 
8697 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
8698   #define BELLBOARD_INTEN6_TRIGGERED5_Pos (5UL)      /*!< Position of TRIGGERED5 field.                                        */
8699   #define BELLBOARD_INTEN6_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.        */
8700   #define BELLBOARD_INTEN6_TRIGGERED5_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED5 field.                            */
8701   #define BELLBOARD_INTEN6_TRIGGERED5_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED5 field.                            */
8702   #define BELLBOARD_INTEN6_TRIGGERED5_Disabled (0x0UL) /*!< Disable                                                            */
8703   #define BELLBOARD_INTEN6_TRIGGERED5_Enabled (0x1UL) /*!< Enable                                                              */
8704 
8705 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
8706   #define BELLBOARD_INTEN6_TRIGGERED6_Pos (6UL)      /*!< Position of TRIGGERED6 field.                                        */
8707   #define BELLBOARD_INTEN6_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.        */
8708   #define BELLBOARD_INTEN6_TRIGGERED6_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED6 field.                            */
8709   #define BELLBOARD_INTEN6_TRIGGERED6_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED6 field.                            */
8710   #define BELLBOARD_INTEN6_TRIGGERED6_Disabled (0x0UL) /*!< Disable                                                            */
8711   #define BELLBOARD_INTEN6_TRIGGERED6_Enabled (0x1UL) /*!< Enable                                                              */
8712 
8713 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
8714   #define BELLBOARD_INTEN6_TRIGGERED7_Pos (7UL)      /*!< Position of TRIGGERED7 field.                                        */
8715   #define BELLBOARD_INTEN6_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.        */
8716   #define BELLBOARD_INTEN6_TRIGGERED7_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED7 field.                            */
8717   #define BELLBOARD_INTEN6_TRIGGERED7_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED7 field.                            */
8718   #define BELLBOARD_INTEN6_TRIGGERED7_Disabled (0x0UL) /*!< Disable                                                            */
8719   #define BELLBOARD_INTEN6_TRIGGERED7_Enabled (0x1UL) /*!< Enable                                                              */
8720 
8721 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
8722   #define BELLBOARD_INTEN6_TRIGGERED8_Pos (8UL)      /*!< Position of TRIGGERED8 field.                                        */
8723   #define BELLBOARD_INTEN6_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.        */
8724   #define BELLBOARD_INTEN6_TRIGGERED8_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED8 field.                            */
8725   #define BELLBOARD_INTEN6_TRIGGERED8_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED8 field.                            */
8726   #define BELLBOARD_INTEN6_TRIGGERED8_Disabled (0x0UL) /*!< Disable                                                            */
8727   #define BELLBOARD_INTEN6_TRIGGERED8_Enabled (0x1UL) /*!< Enable                                                              */
8728 
8729 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
8730   #define BELLBOARD_INTEN6_TRIGGERED9_Pos (9UL)      /*!< Position of TRIGGERED9 field.                                        */
8731   #define BELLBOARD_INTEN6_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.        */
8732   #define BELLBOARD_INTEN6_TRIGGERED9_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED9 field.                            */
8733   #define BELLBOARD_INTEN6_TRIGGERED9_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED9 field.                            */
8734   #define BELLBOARD_INTEN6_TRIGGERED9_Disabled (0x0UL) /*!< Disable                                                            */
8735   #define BELLBOARD_INTEN6_TRIGGERED9_Enabled (0x1UL) /*!< Enable                                                              */
8736 
8737 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
8738   #define BELLBOARD_INTEN6_TRIGGERED10_Pos (10UL)    /*!< Position of TRIGGERED10 field.                                       */
8739   #define BELLBOARD_INTEN6_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.     */
8740   #define BELLBOARD_INTEN6_TRIGGERED10_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED10 field.                           */
8741   #define BELLBOARD_INTEN6_TRIGGERED10_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED10 field.                           */
8742   #define BELLBOARD_INTEN6_TRIGGERED10_Disabled (0x0UL) /*!< Disable                                                           */
8743   #define BELLBOARD_INTEN6_TRIGGERED10_Enabled (0x1UL) /*!< Enable                                                             */
8744 
8745 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
8746   #define BELLBOARD_INTEN6_TRIGGERED11_Pos (11UL)    /*!< Position of TRIGGERED11 field.                                       */
8747   #define BELLBOARD_INTEN6_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.     */
8748   #define BELLBOARD_INTEN6_TRIGGERED11_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED11 field.                           */
8749   #define BELLBOARD_INTEN6_TRIGGERED11_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED11 field.                           */
8750   #define BELLBOARD_INTEN6_TRIGGERED11_Disabled (0x0UL) /*!< Disable                                                           */
8751   #define BELLBOARD_INTEN6_TRIGGERED11_Enabled (0x1UL) /*!< Enable                                                             */
8752 
8753 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
8754   #define BELLBOARD_INTEN6_TRIGGERED12_Pos (12UL)    /*!< Position of TRIGGERED12 field.                                       */
8755   #define BELLBOARD_INTEN6_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.     */
8756   #define BELLBOARD_INTEN6_TRIGGERED12_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED12 field.                           */
8757   #define BELLBOARD_INTEN6_TRIGGERED12_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED12 field.                           */
8758   #define BELLBOARD_INTEN6_TRIGGERED12_Disabled (0x0UL) /*!< Disable                                                           */
8759   #define BELLBOARD_INTEN6_TRIGGERED12_Enabled (0x1UL) /*!< Enable                                                             */
8760 
8761 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
8762   #define BELLBOARD_INTEN6_TRIGGERED13_Pos (13UL)    /*!< Position of TRIGGERED13 field.                                       */
8763   #define BELLBOARD_INTEN6_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.     */
8764   #define BELLBOARD_INTEN6_TRIGGERED13_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED13 field.                           */
8765   #define BELLBOARD_INTEN6_TRIGGERED13_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED13 field.                           */
8766   #define BELLBOARD_INTEN6_TRIGGERED13_Disabled (0x0UL) /*!< Disable                                                           */
8767   #define BELLBOARD_INTEN6_TRIGGERED13_Enabled (0x1UL) /*!< Enable                                                             */
8768 
8769 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
8770   #define BELLBOARD_INTEN6_TRIGGERED14_Pos (14UL)    /*!< Position of TRIGGERED14 field.                                       */
8771   #define BELLBOARD_INTEN6_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.     */
8772   #define BELLBOARD_INTEN6_TRIGGERED14_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED14 field.                           */
8773   #define BELLBOARD_INTEN6_TRIGGERED14_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED14 field.                           */
8774   #define BELLBOARD_INTEN6_TRIGGERED14_Disabled (0x0UL) /*!< Disable                                                           */
8775   #define BELLBOARD_INTEN6_TRIGGERED14_Enabled (0x1UL) /*!< Enable                                                             */
8776 
8777 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
8778   #define BELLBOARD_INTEN6_TRIGGERED15_Pos (15UL)    /*!< Position of TRIGGERED15 field.                                       */
8779   #define BELLBOARD_INTEN6_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.     */
8780   #define BELLBOARD_INTEN6_TRIGGERED15_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED15 field.                           */
8781   #define BELLBOARD_INTEN6_TRIGGERED15_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED15 field.                           */
8782   #define BELLBOARD_INTEN6_TRIGGERED15_Disabled (0x0UL) /*!< Disable                                                           */
8783   #define BELLBOARD_INTEN6_TRIGGERED15_Enabled (0x1UL) /*!< Enable                                                             */
8784 
8785 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
8786   #define BELLBOARD_INTEN6_TRIGGERED16_Pos (16UL)    /*!< Position of TRIGGERED16 field.                                       */
8787   #define BELLBOARD_INTEN6_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.     */
8788   #define BELLBOARD_INTEN6_TRIGGERED16_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED16 field.                           */
8789   #define BELLBOARD_INTEN6_TRIGGERED16_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED16 field.                           */
8790   #define BELLBOARD_INTEN6_TRIGGERED16_Disabled (0x0UL) /*!< Disable                                                           */
8791   #define BELLBOARD_INTEN6_TRIGGERED16_Enabled (0x1UL) /*!< Enable                                                             */
8792 
8793 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
8794   #define BELLBOARD_INTEN6_TRIGGERED17_Pos (17UL)    /*!< Position of TRIGGERED17 field.                                       */
8795   #define BELLBOARD_INTEN6_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.     */
8796   #define BELLBOARD_INTEN6_TRIGGERED17_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED17 field.                           */
8797   #define BELLBOARD_INTEN6_TRIGGERED17_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED17 field.                           */
8798   #define BELLBOARD_INTEN6_TRIGGERED17_Disabled (0x0UL) /*!< Disable                                                           */
8799   #define BELLBOARD_INTEN6_TRIGGERED17_Enabled (0x1UL) /*!< Enable                                                             */
8800 
8801 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
8802   #define BELLBOARD_INTEN6_TRIGGERED18_Pos (18UL)    /*!< Position of TRIGGERED18 field.                                       */
8803   #define BELLBOARD_INTEN6_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.     */
8804   #define BELLBOARD_INTEN6_TRIGGERED18_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED18 field.                           */
8805   #define BELLBOARD_INTEN6_TRIGGERED18_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED18 field.                           */
8806   #define BELLBOARD_INTEN6_TRIGGERED18_Disabled (0x0UL) /*!< Disable                                                           */
8807   #define BELLBOARD_INTEN6_TRIGGERED18_Enabled (0x1UL) /*!< Enable                                                             */
8808 
8809 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
8810   #define BELLBOARD_INTEN6_TRIGGERED19_Pos (19UL)    /*!< Position of TRIGGERED19 field.                                       */
8811   #define BELLBOARD_INTEN6_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.     */
8812   #define BELLBOARD_INTEN6_TRIGGERED19_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED19 field.                           */
8813   #define BELLBOARD_INTEN6_TRIGGERED19_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED19 field.                           */
8814   #define BELLBOARD_INTEN6_TRIGGERED19_Disabled (0x0UL) /*!< Disable                                                           */
8815   #define BELLBOARD_INTEN6_TRIGGERED19_Enabled (0x1UL) /*!< Enable                                                             */
8816 
8817 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
8818   #define BELLBOARD_INTEN6_TRIGGERED20_Pos (20UL)    /*!< Position of TRIGGERED20 field.                                       */
8819   #define BELLBOARD_INTEN6_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.     */
8820   #define BELLBOARD_INTEN6_TRIGGERED20_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED20 field.                           */
8821   #define BELLBOARD_INTEN6_TRIGGERED20_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED20 field.                           */
8822   #define BELLBOARD_INTEN6_TRIGGERED20_Disabled (0x0UL) /*!< Disable                                                           */
8823   #define BELLBOARD_INTEN6_TRIGGERED20_Enabled (0x1UL) /*!< Enable                                                             */
8824 
8825 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
8826   #define BELLBOARD_INTEN6_TRIGGERED21_Pos (21UL)    /*!< Position of TRIGGERED21 field.                                       */
8827   #define BELLBOARD_INTEN6_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.     */
8828   #define BELLBOARD_INTEN6_TRIGGERED21_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED21 field.                           */
8829   #define BELLBOARD_INTEN6_TRIGGERED21_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED21 field.                           */
8830   #define BELLBOARD_INTEN6_TRIGGERED21_Disabled (0x0UL) /*!< Disable                                                           */
8831   #define BELLBOARD_INTEN6_TRIGGERED21_Enabled (0x1UL) /*!< Enable                                                             */
8832 
8833 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
8834   #define BELLBOARD_INTEN6_TRIGGERED22_Pos (22UL)    /*!< Position of TRIGGERED22 field.                                       */
8835   #define BELLBOARD_INTEN6_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.     */
8836   #define BELLBOARD_INTEN6_TRIGGERED22_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED22 field.                           */
8837   #define BELLBOARD_INTEN6_TRIGGERED22_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED22 field.                           */
8838   #define BELLBOARD_INTEN6_TRIGGERED22_Disabled (0x0UL) /*!< Disable                                                           */
8839   #define BELLBOARD_INTEN6_TRIGGERED22_Enabled (0x1UL) /*!< Enable                                                             */
8840 
8841 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
8842   #define BELLBOARD_INTEN6_TRIGGERED23_Pos (23UL)    /*!< Position of TRIGGERED23 field.                                       */
8843   #define BELLBOARD_INTEN6_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.     */
8844   #define BELLBOARD_INTEN6_TRIGGERED23_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED23 field.                           */
8845   #define BELLBOARD_INTEN6_TRIGGERED23_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED23 field.                           */
8846   #define BELLBOARD_INTEN6_TRIGGERED23_Disabled (0x0UL) /*!< Disable                                                           */
8847   #define BELLBOARD_INTEN6_TRIGGERED23_Enabled (0x1UL) /*!< Enable                                                             */
8848 
8849 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
8850   #define BELLBOARD_INTEN6_TRIGGERED24_Pos (24UL)    /*!< Position of TRIGGERED24 field.                                       */
8851   #define BELLBOARD_INTEN6_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.     */
8852   #define BELLBOARD_INTEN6_TRIGGERED24_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED24 field.                           */
8853   #define BELLBOARD_INTEN6_TRIGGERED24_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED24 field.                           */
8854   #define BELLBOARD_INTEN6_TRIGGERED24_Disabled (0x0UL) /*!< Disable                                                           */
8855   #define BELLBOARD_INTEN6_TRIGGERED24_Enabled (0x1UL) /*!< Enable                                                             */
8856 
8857 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
8858   #define BELLBOARD_INTEN6_TRIGGERED25_Pos (25UL)    /*!< Position of TRIGGERED25 field.                                       */
8859   #define BELLBOARD_INTEN6_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.     */
8860   #define BELLBOARD_INTEN6_TRIGGERED25_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED25 field.                           */
8861   #define BELLBOARD_INTEN6_TRIGGERED25_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED25 field.                           */
8862   #define BELLBOARD_INTEN6_TRIGGERED25_Disabled (0x0UL) /*!< Disable                                                           */
8863   #define BELLBOARD_INTEN6_TRIGGERED25_Enabled (0x1UL) /*!< Enable                                                             */
8864 
8865 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
8866   #define BELLBOARD_INTEN6_TRIGGERED26_Pos (26UL)    /*!< Position of TRIGGERED26 field.                                       */
8867   #define BELLBOARD_INTEN6_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.     */
8868   #define BELLBOARD_INTEN6_TRIGGERED26_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED26 field.                           */
8869   #define BELLBOARD_INTEN6_TRIGGERED26_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED26 field.                           */
8870   #define BELLBOARD_INTEN6_TRIGGERED26_Disabled (0x0UL) /*!< Disable                                                           */
8871   #define BELLBOARD_INTEN6_TRIGGERED26_Enabled (0x1UL) /*!< Enable                                                             */
8872 
8873 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
8874   #define BELLBOARD_INTEN6_TRIGGERED27_Pos (27UL)    /*!< Position of TRIGGERED27 field.                                       */
8875   #define BELLBOARD_INTEN6_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.     */
8876   #define BELLBOARD_INTEN6_TRIGGERED27_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED27 field.                           */
8877   #define BELLBOARD_INTEN6_TRIGGERED27_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED27 field.                           */
8878   #define BELLBOARD_INTEN6_TRIGGERED27_Disabled (0x0UL) /*!< Disable                                                           */
8879   #define BELLBOARD_INTEN6_TRIGGERED27_Enabled (0x1UL) /*!< Enable                                                             */
8880 
8881 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
8882   #define BELLBOARD_INTEN6_TRIGGERED28_Pos (28UL)    /*!< Position of TRIGGERED28 field.                                       */
8883   #define BELLBOARD_INTEN6_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.     */
8884   #define BELLBOARD_INTEN6_TRIGGERED28_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED28 field.                           */
8885   #define BELLBOARD_INTEN6_TRIGGERED28_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED28 field.                           */
8886   #define BELLBOARD_INTEN6_TRIGGERED28_Disabled (0x0UL) /*!< Disable                                                           */
8887   #define BELLBOARD_INTEN6_TRIGGERED28_Enabled (0x1UL) /*!< Enable                                                             */
8888 
8889 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
8890   #define BELLBOARD_INTEN6_TRIGGERED29_Pos (29UL)    /*!< Position of TRIGGERED29 field.                                       */
8891   #define BELLBOARD_INTEN6_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.     */
8892   #define BELLBOARD_INTEN6_TRIGGERED29_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED29 field.                           */
8893   #define BELLBOARD_INTEN6_TRIGGERED29_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED29 field.                           */
8894   #define BELLBOARD_INTEN6_TRIGGERED29_Disabled (0x0UL) /*!< Disable                                                           */
8895   #define BELLBOARD_INTEN6_TRIGGERED29_Enabled (0x1UL) /*!< Enable                                                             */
8896 
8897 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
8898   #define BELLBOARD_INTEN6_TRIGGERED30_Pos (30UL)    /*!< Position of TRIGGERED30 field.                                       */
8899   #define BELLBOARD_INTEN6_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.     */
8900   #define BELLBOARD_INTEN6_TRIGGERED30_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED30 field.                           */
8901   #define BELLBOARD_INTEN6_TRIGGERED30_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED30 field.                           */
8902   #define BELLBOARD_INTEN6_TRIGGERED30_Disabled (0x0UL) /*!< Disable                                                           */
8903   #define BELLBOARD_INTEN6_TRIGGERED30_Enabled (0x1UL) /*!< Enable                                                             */
8904 
8905 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
8906   #define BELLBOARD_INTEN6_TRIGGERED31_Pos (31UL)    /*!< Position of TRIGGERED31 field.                                       */
8907   #define BELLBOARD_INTEN6_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN6_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.     */
8908   #define BELLBOARD_INTEN6_TRIGGERED31_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED31 field.                           */
8909   #define BELLBOARD_INTEN6_TRIGGERED31_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED31 field.                           */
8910   #define BELLBOARD_INTEN6_TRIGGERED31_Disabled (0x0UL) /*!< Disable                                                           */
8911   #define BELLBOARD_INTEN6_TRIGGERED31_Enabled (0x1UL) /*!< Enable                                                             */
8912 
8913 
8914 /* BELLBOARD_INTENSET6: Enable interrupt */
8915   #define BELLBOARD_INTENSET6_ResetValue (0x00000000UL) /*!< Reset value of INTENSET6 register.                                */
8916 
8917 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
8918   #define BELLBOARD_INTENSET6_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
8919   #define BELLBOARD_INTENSET6_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
8920   #define BELLBOARD_INTENSET6_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
8921   #define BELLBOARD_INTENSET6_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
8922   #define BELLBOARD_INTENSET6_TRIGGERED0_Set (0x1UL) /*!< Enable                                                               */
8923   #define BELLBOARD_INTENSET6_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8924   #define BELLBOARD_INTENSET6_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8925 
8926 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
8927   #define BELLBOARD_INTENSET6_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
8928   #define BELLBOARD_INTENSET6_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
8929   #define BELLBOARD_INTENSET6_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
8930   #define BELLBOARD_INTENSET6_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
8931   #define BELLBOARD_INTENSET6_TRIGGERED1_Set (0x1UL) /*!< Enable                                                               */
8932   #define BELLBOARD_INTENSET6_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8933   #define BELLBOARD_INTENSET6_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8934 
8935 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
8936   #define BELLBOARD_INTENSET6_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
8937   #define BELLBOARD_INTENSET6_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
8938   #define BELLBOARD_INTENSET6_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
8939   #define BELLBOARD_INTENSET6_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
8940   #define BELLBOARD_INTENSET6_TRIGGERED2_Set (0x1UL) /*!< Enable                                                               */
8941   #define BELLBOARD_INTENSET6_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8942   #define BELLBOARD_INTENSET6_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8943 
8944 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
8945   #define BELLBOARD_INTENSET6_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
8946   #define BELLBOARD_INTENSET6_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
8947   #define BELLBOARD_INTENSET6_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
8948   #define BELLBOARD_INTENSET6_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
8949   #define BELLBOARD_INTENSET6_TRIGGERED3_Set (0x1UL) /*!< Enable                                                               */
8950   #define BELLBOARD_INTENSET6_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8951   #define BELLBOARD_INTENSET6_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8952 
8953 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
8954   #define BELLBOARD_INTENSET6_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
8955   #define BELLBOARD_INTENSET6_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
8956   #define BELLBOARD_INTENSET6_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
8957   #define BELLBOARD_INTENSET6_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
8958   #define BELLBOARD_INTENSET6_TRIGGERED4_Set (0x1UL) /*!< Enable                                                               */
8959   #define BELLBOARD_INTENSET6_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8960   #define BELLBOARD_INTENSET6_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8961 
8962 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
8963   #define BELLBOARD_INTENSET6_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
8964   #define BELLBOARD_INTENSET6_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
8965   #define BELLBOARD_INTENSET6_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
8966   #define BELLBOARD_INTENSET6_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
8967   #define BELLBOARD_INTENSET6_TRIGGERED5_Set (0x1UL) /*!< Enable                                                               */
8968   #define BELLBOARD_INTENSET6_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8969   #define BELLBOARD_INTENSET6_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8970 
8971 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
8972   #define BELLBOARD_INTENSET6_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
8973   #define BELLBOARD_INTENSET6_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
8974   #define BELLBOARD_INTENSET6_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
8975   #define BELLBOARD_INTENSET6_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
8976   #define BELLBOARD_INTENSET6_TRIGGERED6_Set (0x1UL) /*!< Enable                                                               */
8977   #define BELLBOARD_INTENSET6_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8978   #define BELLBOARD_INTENSET6_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8979 
8980 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
8981   #define BELLBOARD_INTENSET6_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
8982   #define BELLBOARD_INTENSET6_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
8983   #define BELLBOARD_INTENSET6_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
8984   #define BELLBOARD_INTENSET6_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
8985   #define BELLBOARD_INTENSET6_TRIGGERED7_Set (0x1UL) /*!< Enable                                                               */
8986   #define BELLBOARD_INTENSET6_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8987   #define BELLBOARD_INTENSET6_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8988 
8989 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
8990   #define BELLBOARD_INTENSET6_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
8991   #define BELLBOARD_INTENSET6_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
8992   #define BELLBOARD_INTENSET6_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
8993   #define BELLBOARD_INTENSET6_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
8994   #define BELLBOARD_INTENSET6_TRIGGERED8_Set (0x1UL) /*!< Enable                                                               */
8995   #define BELLBOARD_INTENSET6_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
8996   #define BELLBOARD_INTENSET6_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
8997 
8998 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
8999   #define BELLBOARD_INTENSET6_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
9000   #define BELLBOARD_INTENSET6_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
9001   #define BELLBOARD_INTENSET6_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
9002   #define BELLBOARD_INTENSET6_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
9003   #define BELLBOARD_INTENSET6_TRIGGERED9_Set (0x1UL) /*!< Enable                                                               */
9004   #define BELLBOARD_INTENSET6_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9005   #define BELLBOARD_INTENSET6_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9006 
9007 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
9008   #define BELLBOARD_INTENSET6_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
9009   #define BELLBOARD_INTENSET6_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
9010                                                                             field.*/
9011   #define BELLBOARD_INTENSET6_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
9012   #define BELLBOARD_INTENSET6_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
9013   #define BELLBOARD_INTENSET6_TRIGGERED10_Set (0x1UL) /*!< Enable                                                              */
9014   #define BELLBOARD_INTENSET6_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9015   #define BELLBOARD_INTENSET6_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9016 
9017 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
9018   #define BELLBOARD_INTENSET6_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
9019   #define BELLBOARD_INTENSET6_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
9020                                                                             field.*/
9021   #define BELLBOARD_INTENSET6_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
9022   #define BELLBOARD_INTENSET6_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
9023   #define BELLBOARD_INTENSET6_TRIGGERED11_Set (0x1UL) /*!< Enable                                                              */
9024   #define BELLBOARD_INTENSET6_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9025   #define BELLBOARD_INTENSET6_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9026 
9027 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
9028   #define BELLBOARD_INTENSET6_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
9029   #define BELLBOARD_INTENSET6_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
9030                                                                             field.*/
9031   #define BELLBOARD_INTENSET6_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
9032   #define BELLBOARD_INTENSET6_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
9033   #define BELLBOARD_INTENSET6_TRIGGERED12_Set (0x1UL) /*!< Enable                                                              */
9034   #define BELLBOARD_INTENSET6_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9035   #define BELLBOARD_INTENSET6_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9036 
9037 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
9038   #define BELLBOARD_INTENSET6_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
9039   #define BELLBOARD_INTENSET6_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
9040                                                                             field.*/
9041   #define BELLBOARD_INTENSET6_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
9042   #define BELLBOARD_INTENSET6_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
9043   #define BELLBOARD_INTENSET6_TRIGGERED13_Set (0x1UL) /*!< Enable                                                              */
9044   #define BELLBOARD_INTENSET6_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9045   #define BELLBOARD_INTENSET6_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9046 
9047 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
9048   #define BELLBOARD_INTENSET6_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
9049   #define BELLBOARD_INTENSET6_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
9050                                                                             field.*/
9051   #define BELLBOARD_INTENSET6_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
9052   #define BELLBOARD_INTENSET6_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
9053   #define BELLBOARD_INTENSET6_TRIGGERED14_Set (0x1UL) /*!< Enable                                                              */
9054   #define BELLBOARD_INTENSET6_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9055   #define BELLBOARD_INTENSET6_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9056 
9057 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
9058   #define BELLBOARD_INTENSET6_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
9059   #define BELLBOARD_INTENSET6_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
9060                                                                             field.*/
9061   #define BELLBOARD_INTENSET6_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
9062   #define BELLBOARD_INTENSET6_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
9063   #define BELLBOARD_INTENSET6_TRIGGERED15_Set (0x1UL) /*!< Enable                                                              */
9064   #define BELLBOARD_INTENSET6_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9065   #define BELLBOARD_INTENSET6_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9066 
9067 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
9068   #define BELLBOARD_INTENSET6_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
9069   #define BELLBOARD_INTENSET6_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
9070                                                                             field.*/
9071   #define BELLBOARD_INTENSET6_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
9072   #define BELLBOARD_INTENSET6_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
9073   #define BELLBOARD_INTENSET6_TRIGGERED16_Set (0x1UL) /*!< Enable                                                              */
9074   #define BELLBOARD_INTENSET6_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9075   #define BELLBOARD_INTENSET6_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9076 
9077 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
9078   #define BELLBOARD_INTENSET6_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
9079   #define BELLBOARD_INTENSET6_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
9080                                                                             field.*/
9081   #define BELLBOARD_INTENSET6_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
9082   #define BELLBOARD_INTENSET6_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
9083   #define BELLBOARD_INTENSET6_TRIGGERED17_Set (0x1UL) /*!< Enable                                                              */
9084   #define BELLBOARD_INTENSET6_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9085   #define BELLBOARD_INTENSET6_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9086 
9087 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
9088   #define BELLBOARD_INTENSET6_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
9089   #define BELLBOARD_INTENSET6_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
9090                                                                             field.*/
9091   #define BELLBOARD_INTENSET6_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
9092   #define BELLBOARD_INTENSET6_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
9093   #define BELLBOARD_INTENSET6_TRIGGERED18_Set (0x1UL) /*!< Enable                                                              */
9094   #define BELLBOARD_INTENSET6_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9095   #define BELLBOARD_INTENSET6_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9096 
9097 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
9098   #define BELLBOARD_INTENSET6_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
9099   #define BELLBOARD_INTENSET6_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
9100                                                                             field.*/
9101   #define BELLBOARD_INTENSET6_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
9102   #define BELLBOARD_INTENSET6_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
9103   #define BELLBOARD_INTENSET6_TRIGGERED19_Set (0x1UL) /*!< Enable                                                              */
9104   #define BELLBOARD_INTENSET6_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9105   #define BELLBOARD_INTENSET6_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9106 
9107 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
9108   #define BELLBOARD_INTENSET6_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
9109   #define BELLBOARD_INTENSET6_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
9110                                                                             field.*/
9111   #define BELLBOARD_INTENSET6_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
9112   #define BELLBOARD_INTENSET6_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
9113   #define BELLBOARD_INTENSET6_TRIGGERED20_Set (0x1UL) /*!< Enable                                                              */
9114   #define BELLBOARD_INTENSET6_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9115   #define BELLBOARD_INTENSET6_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9116 
9117 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
9118   #define BELLBOARD_INTENSET6_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
9119   #define BELLBOARD_INTENSET6_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
9120                                                                             field.*/
9121   #define BELLBOARD_INTENSET6_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
9122   #define BELLBOARD_INTENSET6_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
9123   #define BELLBOARD_INTENSET6_TRIGGERED21_Set (0x1UL) /*!< Enable                                                              */
9124   #define BELLBOARD_INTENSET6_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9125   #define BELLBOARD_INTENSET6_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9126 
9127 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
9128   #define BELLBOARD_INTENSET6_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
9129   #define BELLBOARD_INTENSET6_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
9130                                                                             field.*/
9131   #define BELLBOARD_INTENSET6_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
9132   #define BELLBOARD_INTENSET6_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
9133   #define BELLBOARD_INTENSET6_TRIGGERED22_Set (0x1UL) /*!< Enable                                                              */
9134   #define BELLBOARD_INTENSET6_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9135   #define BELLBOARD_INTENSET6_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9136 
9137 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
9138   #define BELLBOARD_INTENSET6_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
9139   #define BELLBOARD_INTENSET6_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
9140                                                                             field.*/
9141   #define BELLBOARD_INTENSET6_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
9142   #define BELLBOARD_INTENSET6_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
9143   #define BELLBOARD_INTENSET6_TRIGGERED23_Set (0x1UL) /*!< Enable                                                              */
9144   #define BELLBOARD_INTENSET6_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9145   #define BELLBOARD_INTENSET6_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9146 
9147 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
9148   #define BELLBOARD_INTENSET6_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
9149   #define BELLBOARD_INTENSET6_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
9150                                                                             field.*/
9151   #define BELLBOARD_INTENSET6_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
9152   #define BELLBOARD_INTENSET6_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
9153   #define BELLBOARD_INTENSET6_TRIGGERED24_Set (0x1UL) /*!< Enable                                                              */
9154   #define BELLBOARD_INTENSET6_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9155   #define BELLBOARD_INTENSET6_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9156 
9157 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
9158   #define BELLBOARD_INTENSET6_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
9159   #define BELLBOARD_INTENSET6_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
9160                                                                             field.*/
9161   #define BELLBOARD_INTENSET6_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
9162   #define BELLBOARD_INTENSET6_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
9163   #define BELLBOARD_INTENSET6_TRIGGERED25_Set (0x1UL) /*!< Enable                                                              */
9164   #define BELLBOARD_INTENSET6_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9165   #define BELLBOARD_INTENSET6_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9166 
9167 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
9168   #define BELLBOARD_INTENSET6_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
9169   #define BELLBOARD_INTENSET6_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
9170                                                                             field.*/
9171   #define BELLBOARD_INTENSET6_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
9172   #define BELLBOARD_INTENSET6_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
9173   #define BELLBOARD_INTENSET6_TRIGGERED26_Set (0x1UL) /*!< Enable                                                              */
9174   #define BELLBOARD_INTENSET6_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9175   #define BELLBOARD_INTENSET6_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9176 
9177 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
9178   #define BELLBOARD_INTENSET6_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
9179   #define BELLBOARD_INTENSET6_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
9180                                                                             field.*/
9181   #define BELLBOARD_INTENSET6_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
9182   #define BELLBOARD_INTENSET6_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
9183   #define BELLBOARD_INTENSET6_TRIGGERED27_Set (0x1UL) /*!< Enable                                                              */
9184   #define BELLBOARD_INTENSET6_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9185   #define BELLBOARD_INTENSET6_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9186 
9187 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
9188   #define BELLBOARD_INTENSET6_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
9189   #define BELLBOARD_INTENSET6_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
9190                                                                             field.*/
9191   #define BELLBOARD_INTENSET6_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
9192   #define BELLBOARD_INTENSET6_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
9193   #define BELLBOARD_INTENSET6_TRIGGERED28_Set (0x1UL) /*!< Enable                                                              */
9194   #define BELLBOARD_INTENSET6_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9195   #define BELLBOARD_INTENSET6_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9196 
9197 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
9198   #define BELLBOARD_INTENSET6_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
9199   #define BELLBOARD_INTENSET6_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
9200                                                                             field.*/
9201   #define BELLBOARD_INTENSET6_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
9202   #define BELLBOARD_INTENSET6_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
9203   #define BELLBOARD_INTENSET6_TRIGGERED29_Set (0x1UL) /*!< Enable                                                              */
9204   #define BELLBOARD_INTENSET6_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9205   #define BELLBOARD_INTENSET6_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9206 
9207 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
9208   #define BELLBOARD_INTENSET6_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
9209   #define BELLBOARD_INTENSET6_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
9210                                                                             field.*/
9211   #define BELLBOARD_INTENSET6_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
9212   #define BELLBOARD_INTENSET6_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
9213   #define BELLBOARD_INTENSET6_TRIGGERED30_Set (0x1UL) /*!< Enable                                                              */
9214   #define BELLBOARD_INTENSET6_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9215   #define BELLBOARD_INTENSET6_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9216 
9217 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
9218   #define BELLBOARD_INTENSET6_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
9219   #define BELLBOARD_INTENSET6_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET6_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
9220                                                                             field.*/
9221   #define BELLBOARD_INTENSET6_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
9222   #define BELLBOARD_INTENSET6_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
9223   #define BELLBOARD_INTENSET6_TRIGGERED31_Set (0x1UL) /*!< Enable                                                              */
9224   #define BELLBOARD_INTENSET6_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9225   #define BELLBOARD_INTENSET6_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9226 
9227 
9228 /* BELLBOARD_INTENCLR6: Disable interrupt */
9229   #define BELLBOARD_INTENCLR6_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR6 register.                                */
9230 
9231 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
9232   #define BELLBOARD_INTENCLR6_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
9233   #define BELLBOARD_INTENCLR6_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
9234   #define BELLBOARD_INTENCLR6_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
9235   #define BELLBOARD_INTENCLR6_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
9236   #define BELLBOARD_INTENCLR6_TRIGGERED0_Clear (0x1UL) /*!< Disable                                                            */
9237   #define BELLBOARD_INTENCLR6_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9238   #define BELLBOARD_INTENCLR6_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9239 
9240 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
9241   #define BELLBOARD_INTENCLR6_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
9242   #define BELLBOARD_INTENCLR6_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
9243   #define BELLBOARD_INTENCLR6_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
9244   #define BELLBOARD_INTENCLR6_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
9245   #define BELLBOARD_INTENCLR6_TRIGGERED1_Clear (0x1UL) /*!< Disable                                                            */
9246   #define BELLBOARD_INTENCLR6_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9247   #define BELLBOARD_INTENCLR6_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9248 
9249 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
9250   #define BELLBOARD_INTENCLR6_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
9251   #define BELLBOARD_INTENCLR6_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
9252   #define BELLBOARD_INTENCLR6_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
9253   #define BELLBOARD_INTENCLR6_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
9254   #define BELLBOARD_INTENCLR6_TRIGGERED2_Clear (0x1UL) /*!< Disable                                                            */
9255   #define BELLBOARD_INTENCLR6_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9256   #define BELLBOARD_INTENCLR6_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9257 
9258 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
9259   #define BELLBOARD_INTENCLR6_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
9260   #define BELLBOARD_INTENCLR6_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
9261   #define BELLBOARD_INTENCLR6_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
9262   #define BELLBOARD_INTENCLR6_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
9263   #define BELLBOARD_INTENCLR6_TRIGGERED3_Clear (0x1UL) /*!< Disable                                                            */
9264   #define BELLBOARD_INTENCLR6_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9265   #define BELLBOARD_INTENCLR6_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9266 
9267 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
9268   #define BELLBOARD_INTENCLR6_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
9269   #define BELLBOARD_INTENCLR6_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
9270   #define BELLBOARD_INTENCLR6_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
9271   #define BELLBOARD_INTENCLR6_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
9272   #define BELLBOARD_INTENCLR6_TRIGGERED4_Clear (0x1UL) /*!< Disable                                                            */
9273   #define BELLBOARD_INTENCLR6_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9274   #define BELLBOARD_INTENCLR6_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9275 
9276 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
9277   #define BELLBOARD_INTENCLR6_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
9278   #define BELLBOARD_INTENCLR6_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
9279   #define BELLBOARD_INTENCLR6_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
9280   #define BELLBOARD_INTENCLR6_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
9281   #define BELLBOARD_INTENCLR6_TRIGGERED5_Clear (0x1UL) /*!< Disable                                                            */
9282   #define BELLBOARD_INTENCLR6_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9283   #define BELLBOARD_INTENCLR6_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9284 
9285 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
9286   #define BELLBOARD_INTENCLR6_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
9287   #define BELLBOARD_INTENCLR6_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
9288   #define BELLBOARD_INTENCLR6_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
9289   #define BELLBOARD_INTENCLR6_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
9290   #define BELLBOARD_INTENCLR6_TRIGGERED6_Clear (0x1UL) /*!< Disable                                                            */
9291   #define BELLBOARD_INTENCLR6_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9292   #define BELLBOARD_INTENCLR6_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9293 
9294 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
9295   #define BELLBOARD_INTENCLR6_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
9296   #define BELLBOARD_INTENCLR6_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
9297   #define BELLBOARD_INTENCLR6_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
9298   #define BELLBOARD_INTENCLR6_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
9299   #define BELLBOARD_INTENCLR6_TRIGGERED7_Clear (0x1UL) /*!< Disable                                                            */
9300   #define BELLBOARD_INTENCLR6_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9301   #define BELLBOARD_INTENCLR6_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9302 
9303 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
9304   #define BELLBOARD_INTENCLR6_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
9305   #define BELLBOARD_INTENCLR6_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
9306   #define BELLBOARD_INTENCLR6_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
9307   #define BELLBOARD_INTENCLR6_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
9308   #define BELLBOARD_INTENCLR6_TRIGGERED8_Clear (0x1UL) /*!< Disable                                                            */
9309   #define BELLBOARD_INTENCLR6_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9310   #define BELLBOARD_INTENCLR6_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9311 
9312 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
9313   #define BELLBOARD_INTENCLR6_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
9314   #define BELLBOARD_INTENCLR6_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
9315   #define BELLBOARD_INTENCLR6_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
9316   #define BELLBOARD_INTENCLR6_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
9317   #define BELLBOARD_INTENCLR6_TRIGGERED9_Clear (0x1UL) /*!< Disable                                                            */
9318   #define BELLBOARD_INTENCLR6_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
9319   #define BELLBOARD_INTENCLR6_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
9320 
9321 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
9322   #define BELLBOARD_INTENCLR6_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
9323   #define BELLBOARD_INTENCLR6_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
9324                                                                             field.*/
9325   #define BELLBOARD_INTENCLR6_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
9326   #define BELLBOARD_INTENCLR6_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
9327   #define BELLBOARD_INTENCLR6_TRIGGERED10_Clear (0x1UL) /*!< Disable                                                           */
9328   #define BELLBOARD_INTENCLR6_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9329   #define BELLBOARD_INTENCLR6_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9330 
9331 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
9332   #define BELLBOARD_INTENCLR6_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
9333   #define BELLBOARD_INTENCLR6_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
9334                                                                             field.*/
9335   #define BELLBOARD_INTENCLR6_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
9336   #define BELLBOARD_INTENCLR6_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
9337   #define BELLBOARD_INTENCLR6_TRIGGERED11_Clear (0x1UL) /*!< Disable                                                           */
9338   #define BELLBOARD_INTENCLR6_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9339   #define BELLBOARD_INTENCLR6_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9340 
9341 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
9342   #define BELLBOARD_INTENCLR6_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
9343   #define BELLBOARD_INTENCLR6_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
9344                                                                             field.*/
9345   #define BELLBOARD_INTENCLR6_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
9346   #define BELLBOARD_INTENCLR6_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
9347   #define BELLBOARD_INTENCLR6_TRIGGERED12_Clear (0x1UL) /*!< Disable                                                           */
9348   #define BELLBOARD_INTENCLR6_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9349   #define BELLBOARD_INTENCLR6_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9350 
9351 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
9352   #define BELLBOARD_INTENCLR6_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
9353   #define BELLBOARD_INTENCLR6_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
9354                                                                             field.*/
9355   #define BELLBOARD_INTENCLR6_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
9356   #define BELLBOARD_INTENCLR6_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
9357   #define BELLBOARD_INTENCLR6_TRIGGERED13_Clear (0x1UL) /*!< Disable                                                           */
9358   #define BELLBOARD_INTENCLR6_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9359   #define BELLBOARD_INTENCLR6_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9360 
9361 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
9362   #define BELLBOARD_INTENCLR6_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
9363   #define BELLBOARD_INTENCLR6_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
9364                                                                             field.*/
9365   #define BELLBOARD_INTENCLR6_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
9366   #define BELLBOARD_INTENCLR6_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
9367   #define BELLBOARD_INTENCLR6_TRIGGERED14_Clear (0x1UL) /*!< Disable                                                           */
9368   #define BELLBOARD_INTENCLR6_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9369   #define BELLBOARD_INTENCLR6_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9370 
9371 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
9372   #define BELLBOARD_INTENCLR6_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
9373   #define BELLBOARD_INTENCLR6_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
9374                                                                             field.*/
9375   #define BELLBOARD_INTENCLR6_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
9376   #define BELLBOARD_INTENCLR6_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
9377   #define BELLBOARD_INTENCLR6_TRIGGERED15_Clear (0x1UL) /*!< Disable                                                           */
9378   #define BELLBOARD_INTENCLR6_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9379   #define BELLBOARD_INTENCLR6_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9380 
9381 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
9382   #define BELLBOARD_INTENCLR6_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
9383   #define BELLBOARD_INTENCLR6_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
9384                                                                             field.*/
9385   #define BELLBOARD_INTENCLR6_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
9386   #define BELLBOARD_INTENCLR6_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
9387   #define BELLBOARD_INTENCLR6_TRIGGERED16_Clear (0x1UL) /*!< Disable                                                           */
9388   #define BELLBOARD_INTENCLR6_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9389   #define BELLBOARD_INTENCLR6_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9390 
9391 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
9392   #define BELLBOARD_INTENCLR6_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
9393   #define BELLBOARD_INTENCLR6_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
9394                                                                             field.*/
9395   #define BELLBOARD_INTENCLR6_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
9396   #define BELLBOARD_INTENCLR6_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
9397   #define BELLBOARD_INTENCLR6_TRIGGERED17_Clear (0x1UL) /*!< Disable                                                           */
9398   #define BELLBOARD_INTENCLR6_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9399   #define BELLBOARD_INTENCLR6_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9400 
9401 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
9402   #define BELLBOARD_INTENCLR6_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
9403   #define BELLBOARD_INTENCLR6_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
9404                                                                             field.*/
9405   #define BELLBOARD_INTENCLR6_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
9406   #define BELLBOARD_INTENCLR6_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
9407   #define BELLBOARD_INTENCLR6_TRIGGERED18_Clear (0x1UL) /*!< Disable                                                           */
9408   #define BELLBOARD_INTENCLR6_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9409   #define BELLBOARD_INTENCLR6_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9410 
9411 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
9412   #define BELLBOARD_INTENCLR6_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
9413   #define BELLBOARD_INTENCLR6_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
9414                                                                             field.*/
9415   #define BELLBOARD_INTENCLR6_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
9416   #define BELLBOARD_INTENCLR6_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
9417   #define BELLBOARD_INTENCLR6_TRIGGERED19_Clear (0x1UL) /*!< Disable                                                           */
9418   #define BELLBOARD_INTENCLR6_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9419   #define BELLBOARD_INTENCLR6_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9420 
9421 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
9422   #define BELLBOARD_INTENCLR6_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
9423   #define BELLBOARD_INTENCLR6_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
9424                                                                             field.*/
9425   #define BELLBOARD_INTENCLR6_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
9426   #define BELLBOARD_INTENCLR6_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
9427   #define BELLBOARD_INTENCLR6_TRIGGERED20_Clear (0x1UL) /*!< Disable                                                           */
9428   #define BELLBOARD_INTENCLR6_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9429   #define BELLBOARD_INTENCLR6_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9430 
9431 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
9432   #define BELLBOARD_INTENCLR6_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
9433   #define BELLBOARD_INTENCLR6_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
9434                                                                             field.*/
9435   #define BELLBOARD_INTENCLR6_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
9436   #define BELLBOARD_INTENCLR6_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
9437   #define BELLBOARD_INTENCLR6_TRIGGERED21_Clear (0x1UL) /*!< Disable                                                           */
9438   #define BELLBOARD_INTENCLR6_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9439   #define BELLBOARD_INTENCLR6_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9440 
9441 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
9442   #define BELLBOARD_INTENCLR6_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
9443   #define BELLBOARD_INTENCLR6_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
9444                                                                             field.*/
9445   #define BELLBOARD_INTENCLR6_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
9446   #define BELLBOARD_INTENCLR6_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
9447   #define BELLBOARD_INTENCLR6_TRIGGERED22_Clear (0x1UL) /*!< Disable                                                           */
9448   #define BELLBOARD_INTENCLR6_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9449   #define BELLBOARD_INTENCLR6_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9450 
9451 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
9452   #define BELLBOARD_INTENCLR6_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
9453   #define BELLBOARD_INTENCLR6_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
9454                                                                             field.*/
9455   #define BELLBOARD_INTENCLR6_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
9456   #define BELLBOARD_INTENCLR6_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
9457   #define BELLBOARD_INTENCLR6_TRIGGERED23_Clear (0x1UL) /*!< Disable                                                           */
9458   #define BELLBOARD_INTENCLR6_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9459   #define BELLBOARD_INTENCLR6_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9460 
9461 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
9462   #define BELLBOARD_INTENCLR6_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
9463   #define BELLBOARD_INTENCLR6_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
9464                                                                             field.*/
9465   #define BELLBOARD_INTENCLR6_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
9466   #define BELLBOARD_INTENCLR6_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
9467   #define BELLBOARD_INTENCLR6_TRIGGERED24_Clear (0x1UL) /*!< Disable                                                           */
9468   #define BELLBOARD_INTENCLR6_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9469   #define BELLBOARD_INTENCLR6_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9470 
9471 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
9472   #define BELLBOARD_INTENCLR6_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
9473   #define BELLBOARD_INTENCLR6_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
9474                                                                             field.*/
9475   #define BELLBOARD_INTENCLR6_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
9476   #define BELLBOARD_INTENCLR6_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
9477   #define BELLBOARD_INTENCLR6_TRIGGERED25_Clear (0x1UL) /*!< Disable                                                           */
9478   #define BELLBOARD_INTENCLR6_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9479   #define BELLBOARD_INTENCLR6_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9480 
9481 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
9482   #define BELLBOARD_INTENCLR6_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
9483   #define BELLBOARD_INTENCLR6_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
9484                                                                             field.*/
9485   #define BELLBOARD_INTENCLR6_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
9486   #define BELLBOARD_INTENCLR6_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
9487   #define BELLBOARD_INTENCLR6_TRIGGERED26_Clear (0x1UL) /*!< Disable                                                           */
9488   #define BELLBOARD_INTENCLR6_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9489   #define BELLBOARD_INTENCLR6_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9490 
9491 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
9492   #define BELLBOARD_INTENCLR6_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
9493   #define BELLBOARD_INTENCLR6_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
9494                                                                             field.*/
9495   #define BELLBOARD_INTENCLR6_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
9496   #define BELLBOARD_INTENCLR6_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
9497   #define BELLBOARD_INTENCLR6_TRIGGERED27_Clear (0x1UL) /*!< Disable                                                           */
9498   #define BELLBOARD_INTENCLR6_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9499   #define BELLBOARD_INTENCLR6_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9500 
9501 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
9502   #define BELLBOARD_INTENCLR6_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
9503   #define BELLBOARD_INTENCLR6_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
9504                                                                             field.*/
9505   #define BELLBOARD_INTENCLR6_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
9506   #define BELLBOARD_INTENCLR6_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
9507   #define BELLBOARD_INTENCLR6_TRIGGERED28_Clear (0x1UL) /*!< Disable                                                           */
9508   #define BELLBOARD_INTENCLR6_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9509   #define BELLBOARD_INTENCLR6_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9510 
9511 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
9512   #define BELLBOARD_INTENCLR6_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
9513   #define BELLBOARD_INTENCLR6_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
9514                                                                             field.*/
9515   #define BELLBOARD_INTENCLR6_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
9516   #define BELLBOARD_INTENCLR6_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
9517   #define BELLBOARD_INTENCLR6_TRIGGERED29_Clear (0x1UL) /*!< Disable                                                           */
9518   #define BELLBOARD_INTENCLR6_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9519   #define BELLBOARD_INTENCLR6_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9520 
9521 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
9522   #define BELLBOARD_INTENCLR6_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
9523   #define BELLBOARD_INTENCLR6_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
9524                                                                             field.*/
9525   #define BELLBOARD_INTENCLR6_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
9526   #define BELLBOARD_INTENCLR6_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
9527   #define BELLBOARD_INTENCLR6_TRIGGERED30_Clear (0x1UL) /*!< Disable                                                           */
9528   #define BELLBOARD_INTENCLR6_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9529   #define BELLBOARD_INTENCLR6_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9530 
9531 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
9532   #define BELLBOARD_INTENCLR6_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
9533   #define BELLBOARD_INTENCLR6_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR6_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
9534                                                                             field.*/
9535   #define BELLBOARD_INTENCLR6_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
9536   #define BELLBOARD_INTENCLR6_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
9537   #define BELLBOARD_INTENCLR6_TRIGGERED31_Clear (0x1UL) /*!< Disable                                                           */
9538   #define BELLBOARD_INTENCLR6_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
9539   #define BELLBOARD_INTENCLR6_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
9540 
9541 
9542 /* BELLBOARD_INTPEND6: Pending interrupts */
9543   #define BELLBOARD_INTPEND6_ResetValue (0x00000000UL) /*!< Reset value of INTPEND6 register.                                  */
9544 
9545 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
9546   #define BELLBOARD_INTPEND6_TRIGGERED0_Pos (0UL)    /*!< Position of TRIGGERED0 field.                                        */
9547   #define BELLBOARD_INTPEND6_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.    */
9548   #define BELLBOARD_INTPEND6_TRIGGERED0_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED0 field.                            */
9549   #define BELLBOARD_INTPEND6_TRIGGERED0_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED0 field.                            */
9550   #define BELLBOARD_INTPEND6_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending                                              */
9551   #define BELLBOARD_INTPEND6_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending                                                     */
9552 
9553 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
9554   #define BELLBOARD_INTPEND6_TRIGGERED1_Pos (1UL)    /*!< Position of TRIGGERED1 field.                                        */
9555   #define BELLBOARD_INTPEND6_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.    */
9556   #define BELLBOARD_INTPEND6_TRIGGERED1_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED1 field.                            */
9557   #define BELLBOARD_INTPEND6_TRIGGERED1_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED1 field.                            */
9558   #define BELLBOARD_INTPEND6_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending                                              */
9559   #define BELLBOARD_INTPEND6_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending                                                     */
9560 
9561 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
9562   #define BELLBOARD_INTPEND6_TRIGGERED2_Pos (2UL)    /*!< Position of TRIGGERED2 field.                                        */
9563   #define BELLBOARD_INTPEND6_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.    */
9564   #define BELLBOARD_INTPEND6_TRIGGERED2_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED2 field.                            */
9565   #define BELLBOARD_INTPEND6_TRIGGERED2_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED2 field.                            */
9566   #define BELLBOARD_INTPEND6_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending                                              */
9567   #define BELLBOARD_INTPEND6_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending                                                     */
9568 
9569 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
9570   #define BELLBOARD_INTPEND6_TRIGGERED3_Pos (3UL)    /*!< Position of TRIGGERED3 field.                                        */
9571   #define BELLBOARD_INTPEND6_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.    */
9572   #define BELLBOARD_INTPEND6_TRIGGERED3_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED3 field.                            */
9573   #define BELLBOARD_INTPEND6_TRIGGERED3_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED3 field.                            */
9574   #define BELLBOARD_INTPEND6_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending                                              */
9575   #define BELLBOARD_INTPEND6_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending                                                     */
9576 
9577 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
9578   #define BELLBOARD_INTPEND6_TRIGGERED4_Pos (4UL)    /*!< Position of TRIGGERED4 field.                                        */
9579   #define BELLBOARD_INTPEND6_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.    */
9580   #define BELLBOARD_INTPEND6_TRIGGERED4_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED4 field.                            */
9581   #define BELLBOARD_INTPEND6_TRIGGERED4_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED4 field.                            */
9582   #define BELLBOARD_INTPEND6_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending                                              */
9583   #define BELLBOARD_INTPEND6_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending                                                     */
9584 
9585 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
9586   #define BELLBOARD_INTPEND6_TRIGGERED5_Pos (5UL)    /*!< Position of TRIGGERED5 field.                                        */
9587   #define BELLBOARD_INTPEND6_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.    */
9588   #define BELLBOARD_INTPEND6_TRIGGERED5_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED5 field.                            */
9589   #define BELLBOARD_INTPEND6_TRIGGERED5_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED5 field.                            */
9590   #define BELLBOARD_INTPEND6_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending                                              */
9591   #define BELLBOARD_INTPEND6_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending                                                     */
9592 
9593 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
9594   #define BELLBOARD_INTPEND6_TRIGGERED6_Pos (6UL)    /*!< Position of TRIGGERED6 field.                                        */
9595   #define BELLBOARD_INTPEND6_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.    */
9596   #define BELLBOARD_INTPEND6_TRIGGERED6_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED6 field.                            */
9597   #define BELLBOARD_INTPEND6_TRIGGERED6_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED6 field.                            */
9598   #define BELLBOARD_INTPEND6_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending                                              */
9599   #define BELLBOARD_INTPEND6_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending                                                     */
9600 
9601 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
9602   #define BELLBOARD_INTPEND6_TRIGGERED7_Pos (7UL)    /*!< Position of TRIGGERED7 field.                                        */
9603   #define BELLBOARD_INTPEND6_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.    */
9604   #define BELLBOARD_INTPEND6_TRIGGERED7_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED7 field.                            */
9605   #define BELLBOARD_INTPEND6_TRIGGERED7_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED7 field.                            */
9606   #define BELLBOARD_INTPEND6_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending                                              */
9607   #define BELLBOARD_INTPEND6_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending                                                     */
9608 
9609 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
9610   #define BELLBOARD_INTPEND6_TRIGGERED8_Pos (8UL)    /*!< Position of TRIGGERED8 field.                                        */
9611   #define BELLBOARD_INTPEND6_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.    */
9612   #define BELLBOARD_INTPEND6_TRIGGERED8_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED8 field.                            */
9613   #define BELLBOARD_INTPEND6_TRIGGERED8_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED8 field.                            */
9614   #define BELLBOARD_INTPEND6_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending                                              */
9615   #define BELLBOARD_INTPEND6_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending                                                     */
9616 
9617 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
9618   #define BELLBOARD_INTPEND6_TRIGGERED9_Pos (9UL)    /*!< Position of TRIGGERED9 field.                                        */
9619   #define BELLBOARD_INTPEND6_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.    */
9620   #define BELLBOARD_INTPEND6_TRIGGERED9_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED9 field.                            */
9621   #define BELLBOARD_INTPEND6_TRIGGERED9_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED9 field.                            */
9622   #define BELLBOARD_INTPEND6_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending                                              */
9623   #define BELLBOARD_INTPEND6_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending                                                     */
9624 
9625 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
9626   #define BELLBOARD_INTPEND6_TRIGGERED10_Pos (10UL)  /*!< Position of TRIGGERED10 field.                                       */
9627   #define BELLBOARD_INTPEND6_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
9628   #define BELLBOARD_INTPEND6_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                           */
9629   #define BELLBOARD_INTPEND6_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                           */
9630   #define BELLBOARD_INTPEND6_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                             */
9631   #define BELLBOARD_INTPEND6_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending                                                    */
9632 
9633 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
9634   #define BELLBOARD_INTPEND6_TRIGGERED11_Pos (11UL)  /*!< Position of TRIGGERED11 field.                                       */
9635   #define BELLBOARD_INTPEND6_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
9636   #define BELLBOARD_INTPEND6_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                           */
9637   #define BELLBOARD_INTPEND6_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                           */
9638   #define BELLBOARD_INTPEND6_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                             */
9639   #define BELLBOARD_INTPEND6_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending                                                    */
9640 
9641 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
9642   #define BELLBOARD_INTPEND6_TRIGGERED12_Pos (12UL)  /*!< Position of TRIGGERED12 field.                                       */
9643   #define BELLBOARD_INTPEND6_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
9644   #define BELLBOARD_INTPEND6_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                           */
9645   #define BELLBOARD_INTPEND6_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                           */
9646   #define BELLBOARD_INTPEND6_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                             */
9647   #define BELLBOARD_INTPEND6_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending                                                    */
9648 
9649 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
9650   #define BELLBOARD_INTPEND6_TRIGGERED13_Pos (13UL)  /*!< Position of TRIGGERED13 field.                                       */
9651   #define BELLBOARD_INTPEND6_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
9652   #define BELLBOARD_INTPEND6_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                           */
9653   #define BELLBOARD_INTPEND6_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                           */
9654   #define BELLBOARD_INTPEND6_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                             */
9655   #define BELLBOARD_INTPEND6_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending                                                    */
9656 
9657 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
9658   #define BELLBOARD_INTPEND6_TRIGGERED14_Pos (14UL)  /*!< Position of TRIGGERED14 field.                                       */
9659   #define BELLBOARD_INTPEND6_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
9660   #define BELLBOARD_INTPEND6_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                           */
9661   #define BELLBOARD_INTPEND6_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                           */
9662   #define BELLBOARD_INTPEND6_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                             */
9663   #define BELLBOARD_INTPEND6_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending                                                    */
9664 
9665 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
9666   #define BELLBOARD_INTPEND6_TRIGGERED15_Pos (15UL)  /*!< Position of TRIGGERED15 field.                                       */
9667   #define BELLBOARD_INTPEND6_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
9668   #define BELLBOARD_INTPEND6_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                           */
9669   #define BELLBOARD_INTPEND6_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                           */
9670   #define BELLBOARD_INTPEND6_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                             */
9671   #define BELLBOARD_INTPEND6_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending                                                    */
9672 
9673 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
9674   #define BELLBOARD_INTPEND6_TRIGGERED16_Pos (16UL)  /*!< Position of TRIGGERED16 field.                                       */
9675   #define BELLBOARD_INTPEND6_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */
9676   #define BELLBOARD_INTPEND6_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                           */
9677   #define BELLBOARD_INTPEND6_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                           */
9678   #define BELLBOARD_INTPEND6_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                             */
9679   #define BELLBOARD_INTPEND6_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending                                                    */
9680 
9681 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
9682   #define BELLBOARD_INTPEND6_TRIGGERED17_Pos (17UL)  /*!< Position of TRIGGERED17 field.                                       */
9683   #define BELLBOARD_INTPEND6_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */
9684   #define BELLBOARD_INTPEND6_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                           */
9685   #define BELLBOARD_INTPEND6_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                           */
9686   #define BELLBOARD_INTPEND6_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                             */
9687   #define BELLBOARD_INTPEND6_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending                                                    */
9688 
9689 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
9690   #define BELLBOARD_INTPEND6_TRIGGERED18_Pos (18UL)  /*!< Position of TRIGGERED18 field.                                       */
9691   #define BELLBOARD_INTPEND6_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */
9692   #define BELLBOARD_INTPEND6_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                           */
9693   #define BELLBOARD_INTPEND6_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                           */
9694   #define BELLBOARD_INTPEND6_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                             */
9695   #define BELLBOARD_INTPEND6_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending                                                    */
9696 
9697 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
9698   #define BELLBOARD_INTPEND6_TRIGGERED19_Pos (19UL)  /*!< Position of TRIGGERED19 field.                                       */
9699   #define BELLBOARD_INTPEND6_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */
9700   #define BELLBOARD_INTPEND6_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                           */
9701   #define BELLBOARD_INTPEND6_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                           */
9702   #define BELLBOARD_INTPEND6_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                             */
9703   #define BELLBOARD_INTPEND6_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending                                                    */
9704 
9705 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
9706   #define BELLBOARD_INTPEND6_TRIGGERED20_Pos (20UL)  /*!< Position of TRIGGERED20 field.                                       */
9707   #define BELLBOARD_INTPEND6_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */
9708   #define BELLBOARD_INTPEND6_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                           */
9709   #define BELLBOARD_INTPEND6_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                           */
9710   #define BELLBOARD_INTPEND6_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                             */
9711   #define BELLBOARD_INTPEND6_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending                                                    */
9712 
9713 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
9714   #define BELLBOARD_INTPEND6_TRIGGERED21_Pos (21UL)  /*!< Position of TRIGGERED21 field.                                       */
9715   #define BELLBOARD_INTPEND6_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */
9716   #define BELLBOARD_INTPEND6_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                           */
9717   #define BELLBOARD_INTPEND6_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                           */
9718   #define BELLBOARD_INTPEND6_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                             */
9719   #define BELLBOARD_INTPEND6_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending                                                    */
9720 
9721 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
9722   #define BELLBOARD_INTPEND6_TRIGGERED22_Pos (22UL)  /*!< Position of TRIGGERED22 field.                                       */
9723   #define BELLBOARD_INTPEND6_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */
9724   #define BELLBOARD_INTPEND6_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                           */
9725   #define BELLBOARD_INTPEND6_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                           */
9726   #define BELLBOARD_INTPEND6_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                             */
9727   #define BELLBOARD_INTPEND6_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending                                                    */
9728 
9729 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
9730   #define BELLBOARD_INTPEND6_TRIGGERED23_Pos (23UL)  /*!< Position of TRIGGERED23 field.                                       */
9731   #define BELLBOARD_INTPEND6_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */
9732   #define BELLBOARD_INTPEND6_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                           */
9733   #define BELLBOARD_INTPEND6_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                           */
9734   #define BELLBOARD_INTPEND6_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                             */
9735   #define BELLBOARD_INTPEND6_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending                                                    */
9736 
9737 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
9738   #define BELLBOARD_INTPEND6_TRIGGERED24_Pos (24UL)  /*!< Position of TRIGGERED24 field.                                       */
9739   #define BELLBOARD_INTPEND6_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */
9740   #define BELLBOARD_INTPEND6_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                           */
9741   #define BELLBOARD_INTPEND6_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                           */
9742   #define BELLBOARD_INTPEND6_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                             */
9743   #define BELLBOARD_INTPEND6_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending                                                    */
9744 
9745 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
9746   #define BELLBOARD_INTPEND6_TRIGGERED25_Pos (25UL)  /*!< Position of TRIGGERED25 field.                                       */
9747   #define BELLBOARD_INTPEND6_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */
9748   #define BELLBOARD_INTPEND6_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                           */
9749   #define BELLBOARD_INTPEND6_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                           */
9750   #define BELLBOARD_INTPEND6_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                             */
9751   #define BELLBOARD_INTPEND6_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending                                                    */
9752 
9753 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
9754   #define BELLBOARD_INTPEND6_TRIGGERED26_Pos (26UL)  /*!< Position of TRIGGERED26 field.                                       */
9755   #define BELLBOARD_INTPEND6_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */
9756   #define BELLBOARD_INTPEND6_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                           */
9757   #define BELLBOARD_INTPEND6_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                           */
9758   #define BELLBOARD_INTPEND6_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                             */
9759   #define BELLBOARD_INTPEND6_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending                                                    */
9760 
9761 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
9762   #define BELLBOARD_INTPEND6_TRIGGERED27_Pos (27UL)  /*!< Position of TRIGGERED27 field.                                       */
9763   #define BELLBOARD_INTPEND6_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */
9764   #define BELLBOARD_INTPEND6_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                           */
9765   #define BELLBOARD_INTPEND6_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                           */
9766   #define BELLBOARD_INTPEND6_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                             */
9767   #define BELLBOARD_INTPEND6_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending                                                    */
9768 
9769 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
9770   #define BELLBOARD_INTPEND6_TRIGGERED28_Pos (28UL)  /*!< Position of TRIGGERED28 field.                                       */
9771   #define BELLBOARD_INTPEND6_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */
9772   #define BELLBOARD_INTPEND6_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                           */
9773   #define BELLBOARD_INTPEND6_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                           */
9774   #define BELLBOARD_INTPEND6_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                             */
9775   #define BELLBOARD_INTPEND6_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending                                                    */
9776 
9777 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
9778   #define BELLBOARD_INTPEND6_TRIGGERED29_Pos (29UL)  /*!< Position of TRIGGERED29 field.                                       */
9779   #define BELLBOARD_INTPEND6_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */
9780   #define BELLBOARD_INTPEND6_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                           */
9781   #define BELLBOARD_INTPEND6_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                           */
9782   #define BELLBOARD_INTPEND6_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                             */
9783   #define BELLBOARD_INTPEND6_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending                                                    */
9784 
9785 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
9786   #define BELLBOARD_INTPEND6_TRIGGERED30_Pos (30UL)  /*!< Position of TRIGGERED30 field.                                       */
9787   #define BELLBOARD_INTPEND6_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */
9788   #define BELLBOARD_INTPEND6_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                           */
9789   #define BELLBOARD_INTPEND6_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                           */
9790   #define BELLBOARD_INTPEND6_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                             */
9791   #define BELLBOARD_INTPEND6_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending                                                    */
9792 
9793 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
9794   #define BELLBOARD_INTPEND6_TRIGGERED31_Pos (31UL)  /*!< Position of TRIGGERED31 field.                                       */
9795   #define BELLBOARD_INTPEND6_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND6_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */
9796   #define BELLBOARD_INTPEND6_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                           */
9797   #define BELLBOARD_INTPEND6_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                           */
9798   #define BELLBOARD_INTPEND6_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                             */
9799   #define BELLBOARD_INTPEND6_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending                                                    */
9800 
9801 
9802 /* BELLBOARD_INTEN7: Enable or disable interrupt */
9803   #define BELLBOARD_INTEN7_ResetValue (0x00000000UL) /*!< Reset value of INTEN7 register.                                      */
9804 
9805 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
9806   #define BELLBOARD_INTEN7_TRIGGERED0_Pos (0UL)      /*!< Position of TRIGGERED0 field.                                        */
9807   #define BELLBOARD_INTEN7_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.        */
9808   #define BELLBOARD_INTEN7_TRIGGERED0_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED0 field.                            */
9809   #define BELLBOARD_INTEN7_TRIGGERED0_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED0 field.                            */
9810   #define BELLBOARD_INTEN7_TRIGGERED0_Disabled (0x0UL) /*!< Disable                                                            */
9811   #define BELLBOARD_INTEN7_TRIGGERED0_Enabled (0x1UL) /*!< Enable                                                              */
9812 
9813 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
9814   #define BELLBOARD_INTEN7_TRIGGERED1_Pos (1UL)      /*!< Position of TRIGGERED1 field.                                        */
9815   #define BELLBOARD_INTEN7_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.        */
9816   #define BELLBOARD_INTEN7_TRIGGERED1_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED1 field.                            */
9817   #define BELLBOARD_INTEN7_TRIGGERED1_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED1 field.                            */
9818   #define BELLBOARD_INTEN7_TRIGGERED1_Disabled (0x0UL) /*!< Disable                                                            */
9819   #define BELLBOARD_INTEN7_TRIGGERED1_Enabled (0x1UL) /*!< Enable                                                              */
9820 
9821 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
9822   #define BELLBOARD_INTEN7_TRIGGERED2_Pos (2UL)      /*!< Position of TRIGGERED2 field.                                        */
9823   #define BELLBOARD_INTEN7_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.        */
9824   #define BELLBOARD_INTEN7_TRIGGERED2_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED2 field.                            */
9825   #define BELLBOARD_INTEN7_TRIGGERED2_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED2 field.                            */
9826   #define BELLBOARD_INTEN7_TRIGGERED2_Disabled (0x0UL) /*!< Disable                                                            */
9827   #define BELLBOARD_INTEN7_TRIGGERED2_Enabled (0x1UL) /*!< Enable                                                              */
9828 
9829 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
9830   #define BELLBOARD_INTEN7_TRIGGERED3_Pos (3UL)      /*!< Position of TRIGGERED3 field.                                        */
9831   #define BELLBOARD_INTEN7_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.        */
9832   #define BELLBOARD_INTEN7_TRIGGERED3_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED3 field.                            */
9833   #define BELLBOARD_INTEN7_TRIGGERED3_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED3 field.                            */
9834   #define BELLBOARD_INTEN7_TRIGGERED3_Disabled (0x0UL) /*!< Disable                                                            */
9835   #define BELLBOARD_INTEN7_TRIGGERED3_Enabled (0x1UL) /*!< Enable                                                              */
9836 
9837 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
9838   #define BELLBOARD_INTEN7_TRIGGERED4_Pos (4UL)      /*!< Position of TRIGGERED4 field.                                        */
9839   #define BELLBOARD_INTEN7_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.        */
9840   #define BELLBOARD_INTEN7_TRIGGERED4_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED4 field.                            */
9841   #define BELLBOARD_INTEN7_TRIGGERED4_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED4 field.                            */
9842   #define BELLBOARD_INTEN7_TRIGGERED4_Disabled (0x0UL) /*!< Disable                                                            */
9843   #define BELLBOARD_INTEN7_TRIGGERED4_Enabled (0x1UL) /*!< Enable                                                              */
9844 
9845 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
9846   #define BELLBOARD_INTEN7_TRIGGERED5_Pos (5UL)      /*!< Position of TRIGGERED5 field.                                        */
9847   #define BELLBOARD_INTEN7_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.        */
9848   #define BELLBOARD_INTEN7_TRIGGERED5_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED5 field.                            */
9849   #define BELLBOARD_INTEN7_TRIGGERED5_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED5 field.                            */
9850   #define BELLBOARD_INTEN7_TRIGGERED5_Disabled (0x0UL) /*!< Disable                                                            */
9851   #define BELLBOARD_INTEN7_TRIGGERED5_Enabled (0x1UL) /*!< Enable                                                              */
9852 
9853 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
9854   #define BELLBOARD_INTEN7_TRIGGERED6_Pos (6UL)      /*!< Position of TRIGGERED6 field.                                        */
9855   #define BELLBOARD_INTEN7_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.        */
9856   #define BELLBOARD_INTEN7_TRIGGERED6_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED6 field.                            */
9857   #define BELLBOARD_INTEN7_TRIGGERED6_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED6 field.                            */
9858   #define BELLBOARD_INTEN7_TRIGGERED6_Disabled (0x0UL) /*!< Disable                                                            */
9859   #define BELLBOARD_INTEN7_TRIGGERED6_Enabled (0x1UL) /*!< Enable                                                              */
9860 
9861 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
9862   #define BELLBOARD_INTEN7_TRIGGERED7_Pos (7UL)      /*!< Position of TRIGGERED7 field.                                        */
9863   #define BELLBOARD_INTEN7_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.        */
9864   #define BELLBOARD_INTEN7_TRIGGERED7_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED7 field.                            */
9865   #define BELLBOARD_INTEN7_TRIGGERED7_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED7 field.                            */
9866   #define BELLBOARD_INTEN7_TRIGGERED7_Disabled (0x0UL) /*!< Disable                                                            */
9867   #define BELLBOARD_INTEN7_TRIGGERED7_Enabled (0x1UL) /*!< Enable                                                              */
9868 
9869 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
9870   #define BELLBOARD_INTEN7_TRIGGERED8_Pos (8UL)      /*!< Position of TRIGGERED8 field.                                        */
9871   #define BELLBOARD_INTEN7_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.        */
9872   #define BELLBOARD_INTEN7_TRIGGERED8_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED8 field.                            */
9873   #define BELLBOARD_INTEN7_TRIGGERED8_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED8 field.                            */
9874   #define BELLBOARD_INTEN7_TRIGGERED8_Disabled (0x0UL) /*!< Disable                                                            */
9875   #define BELLBOARD_INTEN7_TRIGGERED8_Enabled (0x1UL) /*!< Enable                                                              */
9876 
9877 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
9878   #define BELLBOARD_INTEN7_TRIGGERED9_Pos (9UL)      /*!< Position of TRIGGERED9 field.                                        */
9879   #define BELLBOARD_INTEN7_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.        */
9880   #define BELLBOARD_INTEN7_TRIGGERED9_Min (0x0UL)    /*!< Min enumerator value of TRIGGERED9 field.                            */
9881   #define BELLBOARD_INTEN7_TRIGGERED9_Max (0x1UL)    /*!< Max enumerator value of TRIGGERED9 field.                            */
9882   #define BELLBOARD_INTEN7_TRIGGERED9_Disabled (0x0UL) /*!< Disable                                                            */
9883   #define BELLBOARD_INTEN7_TRIGGERED9_Enabled (0x1UL) /*!< Enable                                                              */
9884 
9885 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
9886   #define BELLBOARD_INTEN7_TRIGGERED10_Pos (10UL)    /*!< Position of TRIGGERED10 field.                                       */
9887   #define BELLBOARD_INTEN7_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.     */
9888   #define BELLBOARD_INTEN7_TRIGGERED10_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED10 field.                           */
9889   #define BELLBOARD_INTEN7_TRIGGERED10_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED10 field.                           */
9890   #define BELLBOARD_INTEN7_TRIGGERED10_Disabled (0x0UL) /*!< Disable                                                           */
9891   #define BELLBOARD_INTEN7_TRIGGERED10_Enabled (0x1UL) /*!< Enable                                                             */
9892 
9893 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
9894   #define BELLBOARD_INTEN7_TRIGGERED11_Pos (11UL)    /*!< Position of TRIGGERED11 field.                                       */
9895   #define BELLBOARD_INTEN7_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.     */
9896   #define BELLBOARD_INTEN7_TRIGGERED11_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED11 field.                           */
9897   #define BELLBOARD_INTEN7_TRIGGERED11_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED11 field.                           */
9898   #define BELLBOARD_INTEN7_TRIGGERED11_Disabled (0x0UL) /*!< Disable                                                           */
9899   #define BELLBOARD_INTEN7_TRIGGERED11_Enabled (0x1UL) /*!< Enable                                                             */
9900 
9901 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
9902   #define BELLBOARD_INTEN7_TRIGGERED12_Pos (12UL)    /*!< Position of TRIGGERED12 field.                                       */
9903   #define BELLBOARD_INTEN7_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.     */
9904   #define BELLBOARD_INTEN7_TRIGGERED12_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED12 field.                           */
9905   #define BELLBOARD_INTEN7_TRIGGERED12_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED12 field.                           */
9906   #define BELLBOARD_INTEN7_TRIGGERED12_Disabled (0x0UL) /*!< Disable                                                           */
9907   #define BELLBOARD_INTEN7_TRIGGERED12_Enabled (0x1UL) /*!< Enable                                                             */
9908 
9909 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
9910   #define BELLBOARD_INTEN7_TRIGGERED13_Pos (13UL)    /*!< Position of TRIGGERED13 field.                                       */
9911   #define BELLBOARD_INTEN7_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.     */
9912   #define BELLBOARD_INTEN7_TRIGGERED13_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED13 field.                           */
9913   #define BELLBOARD_INTEN7_TRIGGERED13_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED13 field.                           */
9914   #define BELLBOARD_INTEN7_TRIGGERED13_Disabled (0x0UL) /*!< Disable                                                           */
9915   #define BELLBOARD_INTEN7_TRIGGERED13_Enabled (0x1UL) /*!< Enable                                                             */
9916 
9917 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
9918   #define BELLBOARD_INTEN7_TRIGGERED14_Pos (14UL)    /*!< Position of TRIGGERED14 field.                                       */
9919   #define BELLBOARD_INTEN7_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.     */
9920   #define BELLBOARD_INTEN7_TRIGGERED14_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED14 field.                           */
9921   #define BELLBOARD_INTEN7_TRIGGERED14_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED14 field.                           */
9922   #define BELLBOARD_INTEN7_TRIGGERED14_Disabled (0x0UL) /*!< Disable                                                           */
9923   #define BELLBOARD_INTEN7_TRIGGERED14_Enabled (0x1UL) /*!< Enable                                                             */
9924 
9925 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
9926   #define BELLBOARD_INTEN7_TRIGGERED15_Pos (15UL)    /*!< Position of TRIGGERED15 field.                                       */
9927   #define BELLBOARD_INTEN7_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.     */
9928   #define BELLBOARD_INTEN7_TRIGGERED15_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED15 field.                           */
9929   #define BELLBOARD_INTEN7_TRIGGERED15_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED15 field.                           */
9930   #define BELLBOARD_INTEN7_TRIGGERED15_Disabled (0x0UL) /*!< Disable                                                           */
9931   #define BELLBOARD_INTEN7_TRIGGERED15_Enabled (0x1UL) /*!< Enable                                                             */
9932 
9933 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
9934   #define BELLBOARD_INTEN7_TRIGGERED16_Pos (16UL)    /*!< Position of TRIGGERED16 field.                                       */
9935   #define BELLBOARD_INTEN7_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.     */
9936   #define BELLBOARD_INTEN7_TRIGGERED16_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED16 field.                           */
9937   #define BELLBOARD_INTEN7_TRIGGERED16_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED16 field.                           */
9938   #define BELLBOARD_INTEN7_TRIGGERED16_Disabled (0x0UL) /*!< Disable                                                           */
9939   #define BELLBOARD_INTEN7_TRIGGERED16_Enabled (0x1UL) /*!< Enable                                                             */
9940 
9941 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
9942   #define BELLBOARD_INTEN7_TRIGGERED17_Pos (17UL)    /*!< Position of TRIGGERED17 field.                                       */
9943   #define BELLBOARD_INTEN7_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.     */
9944   #define BELLBOARD_INTEN7_TRIGGERED17_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED17 field.                           */
9945   #define BELLBOARD_INTEN7_TRIGGERED17_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED17 field.                           */
9946   #define BELLBOARD_INTEN7_TRIGGERED17_Disabled (0x0UL) /*!< Disable                                                           */
9947   #define BELLBOARD_INTEN7_TRIGGERED17_Enabled (0x1UL) /*!< Enable                                                             */
9948 
9949 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
9950   #define BELLBOARD_INTEN7_TRIGGERED18_Pos (18UL)    /*!< Position of TRIGGERED18 field.                                       */
9951   #define BELLBOARD_INTEN7_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.     */
9952   #define BELLBOARD_INTEN7_TRIGGERED18_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED18 field.                           */
9953   #define BELLBOARD_INTEN7_TRIGGERED18_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED18 field.                           */
9954   #define BELLBOARD_INTEN7_TRIGGERED18_Disabled (0x0UL) /*!< Disable                                                           */
9955   #define BELLBOARD_INTEN7_TRIGGERED18_Enabled (0x1UL) /*!< Enable                                                             */
9956 
9957 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
9958   #define BELLBOARD_INTEN7_TRIGGERED19_Pos (19UL)    /*!< Position of TRIGGERED19 field.                                       */
9959   #define BELLBOARD_INTEN7_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.     */
9960   #define BELLBOARD_INTEN7_TRIGGERED19_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED19 field.                           */
9961   #define BELLBOARD_INTEN7_TRIGGERED19_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED19 field.                           */
9962   #define BELLBOARD_INTEN7_TRIGGERED19_Disabled (0x0UL) /*!< Disable                                                           */
9963   #define BELLBOARD_INTEN7_TRIGGERED19_Enabled (0x1UL) /*!< Enable                                                             */
9964 
9965 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
9966   #define BELLBOARD_INTEN7_TRIGGERED20_Pos (20UL)    /*!< Position of TRIGGERED20 field.                                       */
9967   #define BELLBOARD_INTEN7_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.     */
9968   #define BELLBOARD_INTEN7_TRIGGERED20_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED20 field.                           */
9969   #define BELLBOARD_INTEN7_TRIGGERED20_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED20 field.                           */
9970   #define BELLBOARD_INTEN7_TRIGGERED20_Disabled (0x0UL) /*!< Disable                                                           */
9971   #define BELLBOARD_INTEN7_TRIGGERED20_Enabled (0x1UL) /*!< Enable                                                             */
9972 
9973 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
9974   #define BELLBOARD_INTEN7_TRIGGERED21_Pos (21UL)    /*!< Position of TRIGGERED21 field.                                       */
9975   #define BELLBOARD_INTEN7_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.     */
9976   #define BELLBOARD_INTEN7_TRIGGERED21_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED21 field.                           */
9977   #define BELLBOARD_INTEN7_TRIGGERED21_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED21 field.                           */
9978   #define BELLBOARD_INTEN7_TRIGGERED21_Disabled (0x0UL) /*!< Disable                                                           */
9979   #define BELLBOARD_INTEN7_TRIGGERED21_Enabled (0x1UL) /*!< Enable                                                             */
9980 
9981 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
9982   #define BELLBOARD_INTEN7_TRIGGERED22_Pos (22UL)    /*!< Position of TRIGGERED22 field.                                       */
9983   #define BELLBOARD_INTEN7_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.     */
9984   #define BELLBOARD_INTEN7_TRIGGERED22_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED22 field.                           */
9985   #define BELLBOARD_INTEN7_TRIGGERED22_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED22 field.                           */
9986   #define BELLBOARD_INTEN7_TRIGGERED22_Disabled (0x0UL) /*!< Disable                                                           */
9987   #define BELLBOARD_INTEN7_TRIGGERED22_Enabled (0x1UL) /*!< Enable                                                             */
9988 
9989 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
9990   #define BELLBOARD_INTEN7_TRIGGERED23_Pos (23UL)    /*!< Position of TRIGGERED23 field.                                       */
9991   #define BELLBOARD_INTEN7_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.     */
9992   #define BELLBOARD_INTEN7_TRIGGERED23_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED23 field.                           */
9993   #define BELLBOARD_INTEN7_TRIGGERED23_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED23 field.                           */
9994   #define BELLBOARD_INTEN7_TRIGGERED23_Disabled (0x0UL) /*!< Disable                                                           */
9995   #define BELLBOARD_INTEN7_TRIGGERED23_Enabled (0x1UL) /*!< Enable                                                             */
9996 
9997 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
9998   #define BELLBOARD_INTEN7_TRIGGERED24_Pos (24UL)    /*!< Position of TRIGGERED24 field.                                       */
9999   #define BELLBOARD_INTEN7_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.     */
10000   #define BELLBOARD_INTEN7_TRIGGERED24_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED24 field.                           */
10001   #define BELLBOARD_INTEN7_TRIGGERED24_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED24 field.                           */
10002   #define BELLBOARD_INTEN7_TRIGGERED24_Disabled (0x0UL) /*!< Disable                                                           */
10003   #define BELLBOARD_INTEN7_TRIGGERED24_Enabled (0x1UL) /*!< Enable                                                             */
10004 
10005 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
10006   #define BELLBOARD_INTEN7_TRIGGERED25_Pos (25UL)    /*!< Position of TRIGGERED25 field.                                       */
10007   #define BELLBOARD_INTEN7_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.     */
10008   #define BELLBOARD_INTEN7_TRIGGERED25_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED25 field.                           */
10009   #define BELLBOARD_INTEN7_TRIGGERED25_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED25 field.                           */
10010   #define BELLBOARD_INTEN7_TRIGGERED25_Disabled (0x0UL) /*!< Disable                                                           */
10011   #define BELLBOARD_INTEN7_TRIGGERED25_Enabled (0x1UL) /*!< Enable                                                             */
10012 
10013 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
10014   #define BELLBOARD_INTEN7_TRIGGERED26_Pos (26UL)    /*!< Position of TRIGGERED26 field.                                       */
10015   #define BELLBOARD_INTEN7_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.     */
10016   #define BELLBOARD_INTEN7_TRIGGERED26_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED26 field.                           */
10017   #define BELLBOARD_INTEN7_TRIGGERED26_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED26 field.                           */
10018   #define BELLBOARD_INTEN7_TRIGGERED26_Disabled (0x0UL) /*!< Disable                                                           */
10019   #define BELLBOARD_INTEN7_TRIGGERED26_Enabled (0x1UL) /*!< Enable                                                             */
10020 
10021 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
10022   #define BELLBOARD_INTEN7_TRIGGERED27_Pos (27UL)    /*!< Position of TRIGGERED27 field.                                       */
10023   #define BELLBOARD_INTEN7_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.     */
10024   #define BELLBOARD_INTEN7_TRIGGERED27_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED27 field.                           */
10025   #define BELLBOARD_INTEN7_TRIGGERED27_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED27 field.                           */
10026   #define BELLBOARD_INTEN7_TRIGGERED27_Disabled (0x0UL) /*!< Disable                                                           */
10027   #define BELLBOARD_INTEN7_TRIGGERED27_Enabled (0x1UL) /*!< Enable                                                             */
10028 
10029 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
10030   #define BELLBOARD_INTEN7_TRIGGERED28_Pos (28UL)    /*!< Position of TRIGGERED28 field.                                       */
10031   #define BELLBOARD_INTEN7_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.     */
10032   #define BELLBOARD_INTEN7_TRIGGERED28_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED28 field.                           */
10033   #define BELLBOARD_INTEN7_TRIGGERED28_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED28 field.                           */
10034   #define BELLBOARD_INTEN7_TRIGGERED28_Disabled (0x0UL) /*!< Disable                                                           */
10035   #define BELLBOARD_INTEN7_TRIGGERED28_Enabled (0x1UL) /*!< Enable                                                             */
10036 
10037 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
10038   #define BELLBOARD_INTEN7_TRIGGERED29_Pos (29UL)    /*!< Position of TRIGGERED29 field.                                       */
10039   #define BELLBOARD_INTEN7_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.     */
10040   #define BELLBOARD_INTEN7_TRIGGERED29_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED29 field.                           */
10041   #define BELLBOARD_INTEN7_TRIGGERED29_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED29 field.                           */
10042   #define BELLBOARD_INTEN7_TRIGGERED29_Disabled (0x0UL) /*!< Disable                                                           */
10043   #define BELLBOARD_INTEN7_TRIGGERED29_Enabled (0x1UL) /*!< Enable                                                             */
10044 
10045 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
10046   #define BELLBOARD_INTEN7_TRIGGERED30_Pos (30UL)    /*!< Position of TRIGGERED30 field.                                       */
10047   #define BELLBOARD_INTEN7_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.     */
10048   #define BELLBOARD_INTEN7_TRIGGERED30_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED30 field.                           */
10049   #define BELLBOARD_INTEN7_TRIGGERED30_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED30 field.                           */
10050   #define BELLBOARD_INTEN7_TRIGGERED30_Disabled (0x0UL) /*!< Disable                                                           */
10051   #define BELLBOARD_INTEN7_TRIGGERED30_Enabled (0x1UL) /*!< Enable                                                             */
10052 
10053 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
10054   #define BELLBOARD_INTEN7_TRIGGERED31_Pos (31UL)    /*!< Position of TRIGGERED31 field.                                       */
10055   #define BELLBOARD_INTEN7_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTEN7_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.     */
10056   #define BELLBOARD_INTEN7_TRIGGERED31_Min (0x0UL)   /*!< Min enumerator value of TRIGGERED31 field.                           */
10057   #define BELLBOARD_INTEN7_TRIGGERED31_Max (0x1UL)   /*!< Max enumerator value of TRIGGERED31 field.                           */
10058   #define BELLBOARD_INTEN7_TRIGGERED31_Disabled (0x0UL) /*!< Disable                                                           */
10059   #define BELLBOARD_INTEN7_TRIGGERED31_Enabled (0x1UL) /*!< Enable                                                             */
10060 
10061 
10062 /* BELLBOARD_INTENSET7: Enable interrupt */
10063   #define BELLBOARD_INTENSET7_ResetValue (0x00000000UL) /*!< Reset value of INTENSET7 register.                                */
10064 
10065 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
10066   #define BELLBOARD_INTENSET7_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
10067   #define BELLBOARD_INTENSET7_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
10068   #define BELLBOARD_INTENSET7_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
10069   #define BELLBOARD_INTENSET7_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
10070   #define BELLBOARD_INTENSET7_TRIGGERED0_Set (0x1UL) /*!< Enable                                                               */
10071   #define BELLBOARD_INTENSET7_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10072   #define BELLBOARD_INTENSET7_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10073 
10074 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
10075   #define BELLBOARD_INTENSET7_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
10076   #define BELLBOARD_INTENSET7_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
10077   #define BELLBOARD_INTENSET7_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
10078   #define BELLBOARD_INTENSET7_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
10079   #define BELLBOARD_INTENSET7_TRIGGERED1_Set (0x1UL) /*!< Enable                                                               */
10080   #define BELLBOARD_INTENSET7_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10081   #define BELLBOARD_INTENSET7_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10082 
10083 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
10084   #define BELLBOARD_INTENSET7_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
10085   #define BELLBOARD_INTENSET7_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
10086   #define BELLBOARD_INTENSET7_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
10087   #define BELLBOARD_INTENSET7_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
10088   #define BELLBOARD_INTENSET7_TRIGGERED2_Set (0x1UL) /*!< Enable                                                               */
10089   #define BELLBOARD_INTENSET7_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10090   #define BELLBOARD_INTENSET7_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10091 
10092 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
10093   #define BELLBOARD_INTENSET7_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
10094   #define BELLBOARD_INTENSET7_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
10095   #define BELLBOARD_INTENSET7_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
10096   #define BELLBOARD_INTENSET7_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
10097   #define BELLBOARD_INTENSET7_TRIGGERED3_Set (0x1UL) /*!< Enable                                                               */
10098   #define BELLBOARD_INTENSET7_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10099   #define BELLBOARD_INTENSET7_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10100 
10101 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
10102   #define BELLBOARD_INTENSET7_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
10103   #define BELLBOARD_INTENSET7_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
10104   #define BELLBOARD_INTENSET7_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
10105   #define BELLBOARD_INTENSET7_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
10106   #define BELLBOARD_INTENSET7_TRIGGERED4_Set (0x1UL) /*!< Enable                                                               */
10107   #define BELLBOARD_INTENSET7_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10108   #define BELLBOARD_INTENSET7_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10109 
10110 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
10111   #define BELLBOARD_INTENSET7_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
10112   #define BELLBOARD_INTENSET7_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
10113   #define BELLBOARD_INTENSET7_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
10114   #define BELLBOARD_INTENSET7_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
10115   #define BELLBOARD_INTENSET7_TRIGGERED5_Set (0x1UL) /*!< Enable                                                               */
10116   #define BELLBOARD_INTENSET7_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10117   #define BELLBOARD_INTENSET7_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10118 
10119 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
10120   #define BELLBOARD_INTENSET7_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
10121   #define BELLBOARD_INTENSET7_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
10122   #define BELLBOARD_INTENSET7_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
10123   #define BELLBOARD_INTENSET7_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
10124   #define BELLBOARD_INTENSET7_TRIGGERED6_Set (0x1UL) /*!< Enable                                                               */
10125   #define BELLBOARD_INTENSET7_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10126   #define BELLBOARD_INTENSET7_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10127 
10128 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
10129   #define BELLBOARD_INTENSET7_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
10130   #define BELLBOARD_INTENSET7_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
10131   #define BELLBOARD_INTENSET7_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
10132   #define BELLBOARD_INTENSET7_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
10133   #define BELLBOARD_INTENSET7_TRIGGERED7_Set (0x1UL) /*!< Enable                                                               */
10134   #define BELLBOARD_INTENSET7_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10135   #define BELLBOARD_INTENSET7_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10136 
10137 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
10138   #define BELLBOARD_INTENSET7_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
10139   #define BELLBOARD_INTENSET7_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
10140   #define BELLBOARD_INTENSET7_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
10141   #define BELLBOARD_INTENSET7_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
10142   #define BELLBOARD_INTENSET7_TRIGGERED8_Set (0x1UL) /*!< Enable                                                               */
10143   #define BELLBOARD_INTENSET7_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10144   #define BELLBOARD_INTENSET7_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10145 
10146 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
10147   #define BELLBOARD_INTENSET7_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
10148   #define BELLBOARD_INTENSET7_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
10149   #define BELLBOARD_INTENSET7_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
10150   #define BELLBOARD_INTENSET7_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
10151   #define BELLBOARD_INTENSET7_TRIGGERED9_Set (0x1UL) /*!< Enable                                                               */
10152   #define BELLBOARD_INTENSET7_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10153   #define BELLBOARD_INTENSET7_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10154 
10155 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
10156   #define BELLBOARD_INTENSET7_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
10157   #define BELLBOARD_INTENSET7_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
10158                                                                             field.*/
10159   #define BELLBOARD_INTENSET7_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
10160   #define BELLBOARD_INTENSET7_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
10161   #define BELLBOARD_INTENSET7_TRIGGERED10_Set (0x1UL) /*!< Enable                                                              */
10162   #define BELLBOARD_INTENSET7_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10163   #define BELLBOARD_INTENSET7_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10164 
10165 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
10166   #define BELLBOARD_INTENSET7_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
10167   #define BELLBOARD_INTENSET7_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
10168                                                                             field.*/
10169   #define BELLBOARD_INTENSET7_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
10170   #define BELLBOARD_INTENSET7_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
10171   #define BELLBOARD_INTENSET7_TRIGGERED11_Set (0x1UL) /*!< Enable                                                              */
10172   #define BELLBOARD_INTENSET7_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10173   #define BELLBOARD_INTENSET7_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10174 
10175 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
10176   #define BELLBOARD_INTENSET7_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
10177   #define BELLBOARD_INTENSET7_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
10178                                                                             field.*/
10179   #define BELLBOARD_INTENSET7_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
10180   #define BELLBOARD_INTENSET7_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
10181   #define BELLBOARD_INTENSET7_TRIGGERED12_Set (0x1UL) /*!< Enable                                                              */
10182   #define BELLBOARD_INTENSET7_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10183   #define BELLBOARD_INTENSET7_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10184 
10185 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
10186   #define BELLBOARD_INTENSET7_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
10187   #define BELLBOARD_INTENSET7_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
10188                                                                             field.*/
10189   #define BELLBOARD_INTENSET7_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
10190   #define BELLBOARD_INTENSET7_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
10191   #define BELLBOARD_INTENSET7_TRIGGERED13_Set (0x1UL) /*!< Enable                                                              */
10192   #define BELLBOARD_INTENSET7_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10193   #define BELLBOARD_INTENSET7_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10194 
10195 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
10196   #define BELLBOARD_INTENSET7_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
10197   #define BELLBOARD_INTENSET7_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
10198                                                                             field.*/
10199   #define BELLBOARD_INTENSET7_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
10200   #define BELLBOARD_INTENSET7_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
10201   #define BELLBOARD_INTENSET7_TRIGGERED14_Set (0x1UL) /*!< Enable                                                              */
10202   #define BELLBOARD_INTENSET7_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10203   #define BELLBOARD_INTENSET7_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10204 
10205 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
10206   #define BELLBOARD_INTENSET7_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
10207   #define BELLBOARD_INTENSET7_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
10208                                                                             field.*/
10209   #define BELLBOARD_INTENSET7_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
10210   #define BELLBOARD_INTENSET7_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
10211   #define BELLBOARD_INTENSET7_TRIGGERED15_Set (0x1UL) /*!< Enable                                                              */
10212   #define BELLBOARD_INTENSET7_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10213   #define BELLBOARD_INTENSET7_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10214 
10215 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
10216   #define BELLBOARD_INTENSET7_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
10217   #define BELLBOARD_INTENSET7_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
10218                                                                             field.*/
10219   #define BELLBOARD_INTENSET7_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
10220   #define BELLBOARD_INTENSET7_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
10221   #define BELLBOARD_INTENSET7_TRIGGERED16_Set (0x1UL) /*!< Enable                                                              */
10222   #define BELLBOARD_INTENSET7_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10223   #define BELLBOARD_INTENSET7_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10224 
10225 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
10226   #define BELLBOARD_INTENSET7_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
10227   #define BELLBOARD_INTENSET7_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
10228                                                                             field.*/
10229   #define BELLBOARD_INTENSET7_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
10230   #define BELLBOARD_INTENSET7_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
10231   #define BELLBOARD_INTENSET7_TRIGGERED17_Set (0x1UL) /*!< Enable                                                              */
10232   #define BELLBOARD_INTENSET7_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10233   #define BELLBOARD_INTENSET7_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10234 
10235 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
10236   #define BELLBOARD_INTENSET7_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
10237   #define BELLBOARD_INTENSET7_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
10238                                                                             field.*/
10239   #define BELLBOARD_INTENSET7_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
10240   #define BELLBOARD_INTENSET7_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
10241   #define BELLBOARD_INTENSET7_TRIGGERED18_Set (0x1UL) /*!< Enable                                                              */
10242   #define BELLBOARD_INTENSET7_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10243   #define BELLBOARD_INTENSET7_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10244 
10245 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
10246   #define BELLBOARD_INTENSET7_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
10247   #define BELLBOARD_INTENSET7_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
10248                                                                             field.*/
10249   #define BELLBOARD_INTENSET7_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
10250   #define BELLBOARD_INTENSET7_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
10251   #define BELLBOARD_INTENSET7_TRIGGERED19_Set (0x1UL) /*!< Enable                                                              */
10252   #define BELLBOARD_INTENSET7_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10253   #define BELLBOARD_INTENSET7_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10254 
10255 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
10256   #define BELLBOARD_INTENSET7_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
10257   #define BELLBOARD_INTENSET7_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
10258                                                                             field.*/
10259   #define BELLBOARD_INTENSET7_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
10260   #define BELLBOARD_INTENSET7_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
10261   #define BELLBOARD_INTENSET7_TRIGGERED20_Set (0x1UL) /*!< Enable                                                              */
10262   #define BELLBOARD_INTENSET7_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10263   #define BELLBOARD_INTENSET7_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10264 
10265 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
10266   #define BELLBOARD_INTENSET7_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
10267   #define BELLBOARD_INTENSET7_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
10268                                                                             field.*/
10269   #define BELLBOARD_INTENSET7_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
10270   #define BELLBOARD_INTENSET7_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
10271   #define BELLBOARD_INTENSET7_TRIGGERED21_Set (0x1UL) /*!< Enable                                                              */
10272   #define BELLBOARD_INTENSET7_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10273   #define BELLBOARD_INTENSET7_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10274 
10275 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
10276   #define BELLBOARD_INTENSET7_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
10277   #define BELLBOARD_INTENSET7_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
10278                                                                             field.*/
10279   #define BELLBOARD_INTENSET7_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
10280   #define BELLBOARD_INTENSET7_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
10281   #define BELLBOARD_INTENSET7_TRIGGERED22_Set (0x1UL) /*!< Enable                                                              */
10282   #define BELLBOARD_INTENSET7_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10283   #define BELLBOARD_INTENSET7_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10284 
10285 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
10286   #define BELLBOARD_INTENSET7_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
10287   #define BELLBOARD_INTENSET7_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
10288                                                                             field.*/
10289   #define BELLBOARD_INTENSET7_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
10290   #define BELLBOARD_INTENSET7_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
10291   #define BELLBOARD_INTENSET7_TRIGGERED23_Set (0x1UL) /*!< Enable                                                              */
10292   #define BELLBOARD_INTENSET7_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10293   #define BELLBOARD_INTENSET7_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10294 
10295 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
10296   #define BELLBOARD_INTENSET7_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
10297   #define BELLBOARD_INTENSET7_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
10298                                                                             field.*/
10299   #define BELLBOARD_INTENSET7_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
10300   #define BELLBOARD_INTENSET7_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
10301   #define BELLBOARD_INTENSET7_TRIGGERED24_Set (0x1UL) /*!< Enable                                                              */
10302   #define BELLBOARD_INTENSET7_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10303   #define BELLBOARD_INTENSET7_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10304 
10305 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
10306   #define BELLBOARD_INTENSET7_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
10307   #define BELLBOARD_INTENSET7_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
10308                                                                             field.*/
10309   #define BELLBOARD_INTENSET7_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
10310   #define BELLBOARD_INTENSET7_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
10311   #define BELLBOARD_INTENSET7_TRIGGERED25_Set (0x1UL) /*!< Enable                                                              */
10312   #define BELLBOARD_INTENSET7_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10313   #define BELLBOARD_INTENSET7_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10314 
10315 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
10316   #define BELLBOARD_INTENSET7_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
10317   #define BELLBOARD_INTENSET7_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
10318                                                                             field.*/
10319   #define BELLBOARD_INTENSET7_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
10320   #define BELLBOARD_INTENSET7_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
10321   #define BELLBOARD_INTENSET7_TRIGGERED26_Set (0x1UL) /*!< Enable                                                              */
10322   #define BELLBOARD_INTENSET7_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10323   #define BELLBOARD_INTENSET7_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10324 
10325 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
10326   #define BELLBOARD_INTENSET7_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
10327   #define BELLBOARD_INTENSET7_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
10328                                                                             field.*/
10329   #define BELLBOARD_INTENSET7_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
10330   #define BELLBOARD_INTENSET7_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
10331   #define BELLBOARD_INTENSET7_TRIGGERED27_Set (0x1UL) /*!< Enable                                                              */
10332   #define BELLBOARD_INTENSET7_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10333   #define BELLBOARD_INTENSET7_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10334 
10335 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
10336   #define BELLBOARD_INTENSET7_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
10337   #define BELLBOARD_INTENSET7_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
10338                                                                             field.*/
10339   #define BELLBOARD_INTENSET7_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
10340   #define BELLBOARD_INTENSET7_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
10341   #define BELLBOARD_INTENSET7_TRIGGERED28_Set (0x1UL) /*!< Enable                                                              */
10342   #define BELLBOARD_INTENSET7_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10343   #define BELLBOARD_INTENSET7_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10344 
10345 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
10346   #define BELLBOARD_INTENSET7_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
10347   #define BELLBOARD_INTENSET7_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
10348                                                                             field.*/
10349   #define BELLBOARD_INTENSET7_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
10350   #define BELLBOARD_INTENSET7_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
10351   #define BELLBOARD_INTENSET7_TRIGGERED29_Set (0x1UL) /*!< Enable                                                              */
10352   #define BELLBOARD_INTENSET7_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10353   #define BELLBOARD_INTENSET7_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10354 
10355 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
10356   #define BELLBOARD_INTENSET7_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
10357   #define BELLBOARD_INTENSET7_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
10358                                                                             field.*/
10359   #define BELLBOARD_INTENSET7_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
10360   #define BELLBOARD_INTENSET7_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
10361   #define BELLBOARD_INTENSET7_TRIGGERED30_Set (0x1UL) /*!< Enable                                                              */
10362   #define BELLBOARD_INTENSET7_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10363   #define BELLBOARD_INTENSET7_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10364 
10365 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
10366   #define BELLBOARD_INTENSET7_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
10367   #define BELLBOARD_INTENSET7_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENSET7_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
10368                                                                             field.*/
10369   #define BELLBOARD_INTENSET7_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
10370   #define BELLBOARD_INTENSET7_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
10371   #define BELLBOARD_INTENSET7_TRIGGERED31_Set (0x1UL) /*!< Enable                                                              */
10372   #define BELLBOARD_INTENSET7_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10373   #define BELLBOARD_INTENSET7_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10374 
10375 
10376 /* BELLBOARD_INTENCLR7: Disable interrupt */
10377   #define BELLBOARD_INTENCLR7_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR7 register.                                */
10378 
10379 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
10380   #define BELLBOARD_INTENCLR7_TRIGGERED0_Pos (0UL)   /*!< Position of TRIGGERED0 field.                                        */
10381   #define BELLBOARD_INTENCLR7_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.  */
10382   #define BELLBOARD_INTENCLR7_TRIGGERED0_Min (0x0UL) /*!< Min enumerator value of TRIGGERED0 field.                            */
10383   #define BELLBOARD_INTENCLR7_TRIGGERED0_Max (0x1UL) /*!< Max enumerator value of TRIGGERED0 field.                            */
10384   #define BELLBOARD_INTENCLR7_TRIGGERED0_Clear (0x1UL) /*!< Disable                                                            */
10385   #define BELLBOARD_INTENCLR7_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10386   #define BELLBOARD_INTENCLR7_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10387 
10388 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
10389   #define BELLBOARD_INTENCLR7_TRIGGERED1_Pos (1UL)   /*!< Position of TRIGGERED1 field.                                        */
10390   #define BELLBOARD_INTENCLR7_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.  */
10391   #define BELLBOARD_INTENCLR7_TRIGGERED1_Min (0x0UL) /*!< Min enumerator value of TRIGGERED1 field.                            */
10392   #define BELLBOARD_INTENCLR7_TRIGGERED1_Max (0x1UL) /*!< Max enumerator value of TRIGGERED1 field.                            */
10393   #define BELLBOARD_INTENCLR7_TRIGGERED1_Clear (0x1UL) /*!< Disable                                                            */
10394   #define BELLBOARD_INTENCLR7_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10395   #define BELLBOARD_INTENCLR7_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10396 
10397 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
10398   #define BELLBOARD_INTENCLR7_TRIGGERED2_Pos (2UL)   /*!< Position of TRIGGERED2 field.                                        */
10399   #define BELLBOARD_INTENCLR7_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.  */
10400   #define BELLBOARD_INTENCLR7_TRIGGERED2_Min (0x0UL) /*!< Min enumerator value of TRIGGERED2 field.                            */
10401   #define BELLBOARD_INTENCLR7_TRIGGERED2_Max (0x1UL) /*!< Max enumerator value of TRIGGERED2 field.                            */
10402   #define BELLBOARD_INTENCLR7_TRIGGERED2_Clear (0x1UL) /*!< Disable                                                            */
10403   #define BELLBOARD_INTENCLR7_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10404   #define BELLBOARD_INTENCLR7_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10405 
10406 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
10407   #define BELLBOARD_INTENCLR7_TRIGGERED3_Pos (3UL)   /*!< Position of TRIGGERED3 field.                                        */
10408   #define BELLBOARD_INTENCLR7_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.  */
10409   #define BELLBOARD_INTENCLR7_TRIGGERED3_Min (0x0UL) /*!< Min enumerator value of TRIGGERED3 field.                            */
10410   #define BELLBOARD_INTENCLR7_TRIGGERED3_Max (0x1UL) /*!< Max enumerator value of TRIGGERED3 field.                            */
10411   #define BELLBOARD_INTENCLR7_TRIGGERED3_Clear (0x1UL) /*!< Disable                                                            */
10412   #define BELLBOARD_INTENCLR7_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10413   #define BELLBOARD_INTENCLR7_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10414 
10415 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
10416   #define BELLBOARD_INTENCLR7_TRIGGERED4_Pos (4UL)   /*!< Position of TRIGGERED4 field.                                        */
10417   #define BELLBOARD_INTENCLR7_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.  */
10418   #define BELLBOARD_INTENCLR7_TRIGGERED4_Min (0x0UL) /*!< Min enumerator value of TRIGGERED4 field.                            */
10419   #define BELLBOARD_INTENCLR7_TRIGGERED4_Max (0x1UL) /*!< Max enumerator value of TRIGGERED4 field.                            */
10420   #define BELLBOARD_INTENCLR7_TRIGGERED4_Clear (0x1UL) /*!< Disable                                                            */
10421   #define BELLBOARD_INTENCLR7_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10422   #define BELLBOARD_INTENCLR7_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10423 
10424 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
10425   #define BELLBOARD_INTENCLR7_TRIGGERED5_Pos (5UL)   /*!< Position of TRIGGERED5 field.                                        */
10426   #define BELLBOARD_INTENCLR7_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.  */
10427   #define BELLBOARD_INTENCLR7_TRIGGERED5_Min (0x0UL) /*!< Min enumerator value of TRIGGERED5 field.                            */
10428   #define BELLBOARD_INTENCLR7_TRIGGERED5_Max (0x1UL) /*!< Max enumerator value of TRIGGERED5 field.                            */
10429   #define BELLBOARD_INTENCLR7_TRIGGERED5_Clear (0x1UL) /*!< Disable                                                            */
10430   #define BELLBOARD_INTENCLR7_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10431   #define BELLBOARD_INTENCLR7_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10432 
10433 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
10434   #define BELLBOARD_INTENCLR7_TRIGGERED6_Pos (6UL)   /*!< Position of TRIGGERED6 field.                                        */
10435   #define BELLBOARD_INTENCLR7_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.  */
10436   #define BELLBOARD_INTENCLR7_TRIGGERED6_Min (0x0UL) /*!< Min enumerator value of TRIGGERED6 field.                            */
10437   #define BELLBOARD_INTENCLR7_TRIGGERED6_Max (0x1UL) /*!< Max enumerator value of TRIGGERED6 field.                            */
10438   #define BELLBOARD_INTENCLR7_TRIGGERED6_Clear (0x1UL) /*!< Disable                                                            */
10439   #define BELLBOARD_INTENCLR7_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10440   #define BELLBOARD_INTENCLR7_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10441 
10442 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
10443   #define BELLBOARD_INTENCLR7_TRIGGERED7_Pos (7UL)   /*!< Position of TRIGGERED7 field.                                        */
10444   #define BELLBOARD_INTENCLR7_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.  */
10445   #define BELLBOARD_INTENCLR7_TRIGGERED7_Min (0x0UL) /*!< Min enumerator value of TRIGGERED7 field.                            */
10446   #define BELLBOARD_INTENCLR7_TRIGGERED7_Max (0x1UL) /*!< Max enumerator value of TRIGGERED7 field.                            */
10447   #define BELLBOARD_INTENCLR7_TRIGGERED7_Clear (0x1UL) /*!< Disable                                                            */
10448   #define BELLBOARD_INTENCLR7_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10449   #define BELLBOARD_INTENCLR7_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10450 
10451 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
10452   #define BELLBOARD_INTENCLR7_TRIGGERED8_Pos (8UL)   /*!< Position of TRIGGERED8 field.                                        */
10453   #define BELLBOARD_INTENCLR7_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.  */
10454   #define BELLBOARD_INTENCLR7_TRIGGERED8_Min (0x0UL) /*!< Min enumerator value of TRIGGERED8 field.                            */
10455   #define BELLBOARD_INTENCLR7_TRIGGERED8_Max (0x1UL) /*!< Max enumerator value of TRIGGERED8 field.                            */
10456   #define BELLBOARD_INTENCLR7_TRIGGERED8_Clear (0x1UL) /*!< Disable                                                            */
10457   #define BELLBOARD_INTENCLR7_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10458   #define BELLBOARD_INTENCLR7_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10459 
10460 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
10461   #define BELLBOARD_INTENCLR7_TRIGGERED9_Pos (9UL)   /*!< Position of TRIGGERED9 field.                                        */
10462   #define BELLBOARD_INTENCLR7_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.  */
10463   #define BELLBOARD_INTENCLR7_TRIGGERED9_Min (0x0UL) /*!< Min enumerator value of TRIGGERED9 field.                            */
10464   #define BELLBOARD_INTENCLR7_TRIGGERED9_Max (0x1UL) /*!< Max enumerator value of TRIGGERED9 field.                            */
10465   #define BELLBOARD_INTENCLR7_TRIGGERED9_Clear (0x1UL) /*!< Disable                                                            */
10466   #define BELLBOARD_INTENCLR7_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled                                                  */
10467   #define BELLBOARD_INTENCLR7_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled                                                    */
10468 
10469 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
10470   #define BELLBOARD_INTENCLR7_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field.                                       */
10471   #define BELLBOARD_INTENCLR7_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10
10472                                                                             field.*/
10473   #define BELLBOARD_INTENCLR7_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                          */
10474   #define BELLBOARD_INTENCLR7_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                          */
10475   #define BELLBOARD_INTENCLR7_TRIGGERED10_Clear (0x1UL) /*!< Disable                                                           */
10476   #define BELLBOARD_INTENCLR7_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10477   #define BELLBOARD_INTENCLR7_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10478 
10479 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
10480   #define BELLBOARD_INTENCLR7_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field.                                       */
10481   #define BELLBOARD_INTENCLR7_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11
10482                                                                             field.*/
10483   #define BELLBOARD_INTENCLR7_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                          */
10484   #define BELLBOARD_INTENCLR7_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                          */
10485   #define BELLBOARD_INTENCLR7_TRIGGERED11_Clear (0x1UL) /*!< Disable                                                           */
10486   #define BELLBOARD_INTENCLR7_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10487   #define BELLBOARD_INTENCLR7_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10488 
10489 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
10490   #define BELLBOARD_INTENCLR7_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field.                                       */
10491   #define BELLBOARD_INTENCLR7_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12
10492                                                                             field.*/
10493   #define BELLBOARD_INTENCLR7_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                          */
10494   #define BELLBOARD_INTENCLR7_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                          */
10495   #define BELLBOARD_INTENCLR7_TRIGGERED12_Clear (0x1UL) /*!< Disable                                                           */
10496   #define BELLBOARD_INTENCLR7_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10497   #define BELLBOARD_INTENCLR7_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10498 
10499 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
10500   #define BELLBOARD_INTENCLR7_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field.                                       */
10501   #define BELLBOARD_INTENCLR7_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13
10502                                                                             field.*/
10503   #define BELLBOARD_INTENCLR7_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                          */
10504   #define BELLBOARD_INTENCLR7_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                          */
10505   #define BELLBOARD_INTENCLR7_TRIGGERED13_Clear (0x1UL) /*!< Disable                                                           */
10506   #define BELLBOARD_INTENCLR7_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10507   #define BELLBOARD_INTENCLR7_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10508 
10509 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
10510   #define BELLBOARD_INTENCLR7_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field.                                       */
10511   #define BELLBOARD_INTENCLR7_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14
10512                                                                             field.*/
10513   #define BELLBOARD_INTENCLR7_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                          */
10514   #define BELLBOARD_INTENCLR7_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                          */
10515   #define BELLBOARD_INTENCLR7_TRIGGERED14_Clear (0x1UL) /*!< Disable                                                           */
10516   #define BELLBOARD_INTENCLR7_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10517   #define BELLBOARD_INTENCLR7_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10518 
10519 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
10520   #define BELLBOARD_INTENCLR7_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field.                                       */
10521   #define BELLBOARD_INTENCLR7_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15
10522                                                                             field.*/
10523   #define BELLBOARD_INTENCLR7_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                          */
10524   #define BELLBOARD_INTENCLR7_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                          */
10525   #define BELLBOARD_INTENCLR7_TRIGGERED15_Clear (0x1UL) /*!< Disable                                                           */
10526   #define BELLBOARD_INTENCLR7_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10527   #define BELLBOARD_INTENCLR7_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10528 
10529 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
10530   #define BELLBOARD_INTENCLR7_TRIGGERED16_Pos (16UL) /*!< Position of TRIGGERED16 field.                                       */
10531   #define BELLBOARD_INTENCLR7_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16
10532                                                                             field.*/
10533   #define BELLBOARD_INTENCLR7_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                          */
10534   #define BELLBOARD_INTENCLR7_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                          */
10535   #define BELLBOARD_INTENCLR7_TRIGGERED16_Clear (0x1UL) /*!< Disable                                                           */
10536   #define BELLBOARD_INTENCLR7_TRIGGERED16_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10537   #define BELLBOARD_INTENCLR7_TRIGGERED16_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10538 
10539 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
10540   #define BELLBOARD_INTENCLR7_TRIGGERED17_Pos (17UL) /*!< Position of TRIGGERED17 field.                                       */
10541   #define BELLBOARD_INTENCLR7_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17
10542                                                                             field.*/
10543   #define BELLBOARD_INTENCLR7_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                          */
10544   #define BELLBOARD_INTENCLR7_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                          */
10545   #define BELLBOARD_INTENCLR7_TRIGGERED17_Clear (0x1UL) /*!< Disable                                                           */
10546   #define BELLBOARD_INTENCLR7_TRIGGERED17_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10547   #define BELLBOARD_INTENCLR7_TRIGGERED17_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10548 
10549 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
10550   #define BELLBOARD_INTENCLR7_TRIGGERED18_Pos (18UL) /*!< Position of TRIGGERED18 field.                                       */
10551   #define BELLBOARD_INTENCLR7_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18
10552                                                                             field.*/
10553   #define BELLBOARD_INTENCLR7_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                          */
10554   #define BELLBOARD_INTENCLR7_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                          */
10555   #define BELLBOARD_INTENCLR7_TRIGGERED18_Clear (0x1UL) /*!< Disable                                                           */
10556   #define BELLBOARD_INTENCLR7_TRIGGERED18_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10557   #define BELLBOARD_INTENCLR7_TRIGGERED18_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10558 
10559 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
10560   #define BELLBOARD_INTENCLR7_TRIGGERED19_Pos (19UL) /*!< Position of TRIGGERED19 field.                                       */
10561   #define BELLBOARD_INTENCLR7_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19
10562                                                                             field.*/
10563   #define BELLBOARD_INTENCLR7_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                          */
10564   #define BELLBOARD_INTENCLR7_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                          */
10565   #define BELLBOARD_INTENCLR7_TRIGGERED19_Clear (0x1UL) /*!< Disable                                                           */
10566   #define BELLBOARD_INTENCLR7_TRIGGERED19_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10567   #define BELLBOARD_INTENCLR7_TRIGGERED19_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10568 
10569 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
10570   #define BELLBOARD_INTENCLR7_TRIGGERED20_Pos (20UL) /*!< Position of TRIGGERED20 field.                                       */
10571   #define BELLBOARD_INTENCLR7_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20
10572                                                                             field.*/
10573   #define BELLBOARD_INTENCLR7_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                          */
10574   #define BELLBOARD_INTENCLR7_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                          */
10575   #define BELLBOARD_INTENCLR7_TRIGGERED20_Clear (0x1UL) /*!< Disable                                                           */
10576   #define BELLBOARD_INTENCLR7_TRIGGERED20_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10577   #define BELLBOARD_INTENCLR7_TRIGGERED20_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10578 
10579 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
10580   #define BELLBOARD_INTENCLR7_TRIGGERED21_Pos (21UL) /*!< Position of TRIGGERED21 field.                                       */
10581   #define BELLBOARD_INTENCLR7_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21
10582                                                                             field.*/
10583   #define BELLBOARD_INTENCLR7_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                          */
10584   #define BELLBOARD_INTENCLR7_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                          */
10585   #define BELLBOARD_INTENCLR7_TRIGGERED21_Clear (0x1UL) /*!< Disable                                                           */
10586   #define BELLBOARD_INTENCLR7_TRIGGERED21_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10587   #define BELLBOARD_INTENCLR7_TRIGGERED21_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10588 
10589 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
10590   #define BELLBOARD_INTENCLR7_TRIGGERED22_Pos (22UL) /*!< Position of TRIGGERED22 field.                                       */
10591   #define BELLBOARD_INTENCLR7_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22
10592                                                                             field.*/
10593   #define BELLBOARD_INTENCLR7_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                          */
10594   #define BELLBOARD_INTENCLR7_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                          */
10595   #define BELLBOARD_INTENCLR7_TRIGGERED22_Clear (0x1UL) /*!< Disable                                                           */
10596   #define BELLBOARD_INTENCLR7_TRIGGERED22_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10597   #define BELLBOARD_INTENCLR7_TRIGGERED22_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10598 
10599 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
10600   #define BELLBOARD_INTENCLR7_TRIGGERED23_Pos (23UL) /*!< Position of TRIGGERED23 field.                                       */
10601   #define BELLBOARD_INTENCLR7_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23
10602                                                                             field.*/
10603   #define BELLBOARD_INTENCLR7_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                          */
10604   #define BELLBOARD_INTENCLR7_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                          */
10605   #define BELLBOARD_INTENCLR7_TRIGGERED23_Clear (0x1UL) /*!< Disable                                                           */
10606   #define BELLBOARD_INTENCLR7_TRIGGERED23_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10607   #define BELLBOARD_INTENCLR7_TRIGGERED23_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10608 
10609 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
10610   #define BELLBOARD_INTENCLR7_TRIGGERED24_Pos (24UL) /*!< Position of TRIGGERED24 field.                                       */
10611   #define BELLBOARD_INTENCLR7_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24
10612                                                                             field.*/
10613   #define BELLBOARD_INTENCLR7_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                          */
10614   #define BELLBOARD_INTENCLR7_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                          */
10615   #define BELLBOARD_INTENCLR7_TRIGGERED24_Clear (0x1UL) /*!< Disable                                                           */
10616   #define BELLBOARD_INTENCLR7_TRIGGERED24_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10617   #define BELLBOARD_INTENCLR7_TRIGGERED24_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10618 
10619 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
10620   #define BELLBOARD_INTENCLR7_TRIGGERED25_Pos (25UL) /*!< Position of TRIGGERED25 field.                                       */
10621   #define BELLBOARD_INTENCLR7_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25
10622                                                                             field.*/
10623   #define BELLBOARD_INTENCLR7_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                          */
10624   #define BELLBOARD_INTENCLR7_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                          */
10625   #define BELLBOARD_INTENCLR7_TRIGGERED25_Clear (0x1UL) /*!< Disable                                                           */
10626   #define BELLBOARD_INTENCLR7_TRIGGERED25_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10627   #define BELLBOARD_INTENCLR7_TRIGGERED25_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10628 
10629 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
10630   #define BELLBOARD_INTENCLR7_TRIGGERED26_Pos (26UL) /*!< Position of TRIGGERED26 field.                                       */
10631   #define BELLBOARD_INTENCLR7_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26
10632                                                                             field.*/
10633   #define BELLBOARD_INTENCLR7_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                          */
10634   #define BELLBOARD_INTENCLR7_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                          */
10635   #define BELLBOARD_INTENCLR7_TRIGGERED26_Clear (0x1UL) /*!< Disable                                                           */
10636   #define BELLBOARD_INTENCLR7_TRIGGERED26_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10637   #define BELLBOARD_INTENCLR7_TRIGGERED26_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10638 
10639 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
10640   #define BELLBOARD_INTENCLR7_TRIGGERED27_Pos (27UL) /*!< Position of TRIGGERED27 field.                                       */
10641   #define BELLBOARD_INTENCLR7_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27
10642                                                                             field.*/
10643   #define BELLBOARD_INTENCLR7_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                          */
10644   #define BELLBOARD_INTENCLR7_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                          */
10645   #define BELLBOARD_INTENCLR7_TRIGGERED27_Clear (0x1UL) /*!< Disable                                                           */
10646   #define BELLBOARD_INTENCLR7_TRIGGERED27_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10647   #define BELLBOARD_INTENCLR7_TRIGGERED27_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10648 
10649 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
10650   #define BELLBOARD_INTENCLR7_TRIGGERED28_Pos (28UL) /*!< Position of TRIGGERED28 field.                                       */
10651   #define BELLBOARD_INTENCLR7_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28
10652                                                                             field.*/
10653   #define BELLBOARD_INTENCLR7_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                          */
10654   #define BELLBOARD_INTENCLR7_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                          */
10655   #define BELLBOARD_INTENCLR7_TRIGGERED28_Clear (0x1UL) /*!< Disable                                                           */
10656   #define BELLBOARD_INTENCLR7_TRIGGERED28_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10657   #define BELLBOARD_INTENCLR7_TRIGGERED28_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10658 
10659 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
10660   #define BELLBOARD_INTENCLR7_TRIGGERED29_Pos (29UL) /*!< Position of TRIGGERED29 field.                                       */
10661   #define BELLBOARD_INTENCLR7_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29
10662                                                                             field.*/
10663   #define BELLBOARD_INTENCLR7_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                          */
10664   #define BELLBOARD_INTENCLR7_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                          */
10665   #define BELLBOARD_INTENCLR7_TRIGGERED29_Clear (0x1UL) /*!< Disable                                                           */
10666   #define BELLBOARD_INTENCLR7_TRIGGERED29_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10667   #define BELLBOARD_INTENCLR7_TRIGGERED29_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10668 
10669 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
10670   #define BELLBOARD_INTENCLR7_TRIGGERED30_Pos (30UL) /*!< Position of TRIGGERED30 field.                                       */
10671   #define BELLBOARD_INTENCLR7_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30
10672                                                                             field.*/
10673   #define BELLBOARD_INTENCLR7_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                          */
10674   #define BELLBOARD_INTENCLR7_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                          */
10675   #define BELLBOARD_INTENCLR7_TRIGGERED30_Clear (0x1UL) /*!< Disable                                                           */
10676   #define BELLBOARD_INTENCLR7_TRIGGERED30_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10677   #define BELLBOARD_INTENCLR7_TRIGGERED30_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10678 
10679 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
10680   #define BELLBOARD_INTENCLR7_TRIGGERED31_Pos (31UL) /*!< Position of TRIGGERED31 field.                                       */
10681   #define BELLBOARD_INTENCLR7_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTENCLR7_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31
10682                                                                             field.*/
10683   #define BELLBOARD_INTENCLR7_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                          */
10684   #define BELLBOARD_INTENCLR7_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                          */
10685   #define BELLBOARD_INTENCLR7_TRIGGERED31_Clear (0x1UL) /*!< Disable                                                           */
10686   #define BELLBOARD_INTENCLR7_TRIGGERED31_Disabled (0x0UL) /*!< Read: Disabled                                                 */
10687   #define BELLBOARD_INTENCLR7_TRIGGERED31_Enabled (0x1UL) /*!< Read: Enabled                                                   */
10688 
10689 
10690 /* BELLBOARD_INTPEND7: Pending interrupts */
10691   #define BELLBOARD_INTPEND7_ResetValue (0x00000000UL) /*!< Reset value of INTPEND7 register.                                  */
10692 
10693 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
10694   #define BELLBOARD_INTPEND7_TRIGGERED0_Pos (0UL)    /*!< Position of TRIGGERED0 field.                                        */
10695   #define BELLBOARD_INTPEND7_TRIGGERED0_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.    */
10696   #define BELLBOARD_INTPEND7_TRIGGERED0_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED0 field.                            */
10697   #define BELLBOARD_INTPEND7_TRIGGERED0_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED0 field.                            */
10698   #define BELLBOARD_INTPEND7_TRIGGERED0_NotPending (0x0UL) /*!< Read: Not pending                                              */
10699   #define BELLBOARD_INTPEND7_TRIGGERED0_Pending (0x1UL) /*!< Read: Pending                                                     */
10700 
10701 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
10702   #define BELLBOARD_INTPEND7_TRIGGERED1_Pos (1UL)    /*!< Position of TRIGGERED1 field.                                        */
10703   #define BELLBOARD_INTPEND7_TRIGGERED1_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.    */
10704   #define BELLBOARD_INTPEND7_TRIGGERED1_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED1 field.                            */
10705   #define BELLBOARD_INTPEND7_TRIGGERED1_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED1 field.                            */
10706   #define BELLBOARD_INTPEND7_TRIGGERED1_NotPending (0x0UL) /*!< Read: Not pending                                              */
10707   #define BELLBOARD_INTPEND7_TRIGGERED1_Pending (0x1UL) /*!< Read: Pending                                                     */
10708 
10709 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
10710   #define BELLBOARD_INTPEND7_TRIGGERED2_Pos (2UL)    /*!< Position of TRIGGERED2 field.                                        */
10711   #define BELLBOARD_INTPEND7_TRIGGERED2_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.    */
10712   #define BELLBOARD_INTPEND7_TRIGGERED2_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED2 field.                            */
10713   #define BELLBOARD_INTPEND7_TRIGGERED2_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED2 field.                            */
10714   #define BELLBOARD_INTPEND7_TRIGGERED2_NotPending (0x0UL) /*!< Read: Not pending                                              */
10715   #define BELLBOARD_INTPEND7_TRIGGERED2_Pending (0x1UL) /*!< Read: Pending                                                     */
10716 
10717 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
10718   #define BELLBOARD_INTPEND7_TRIGGERED3_Pos (3UL)    /*!< Position of TRIGGERED3 field.                                        */
10719   #define BELLBOARD_INTPEND7_TRIGGERED3_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.    */
10720   #define BELLBOARD_INTPEND7_TRIGGERED3_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED3 field.                            */
10721   #define BELLBOARD_INTPEND7_TRIGGERED3_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED3 field.                            */
10722   #define BELLBOARD_INTPEND7_TRIGGERED3_NotPending (0x0UL) /*!< Read: Not pending                                              */
10723   #define BELLBOARD_INTPEND7_TRIGGERED3_Pending (0x1UL) /*!< Read: Pending                                                     */
10724 
10725 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
10726   #define BELLBOARD_INTPEND7_TRIGGERED4_Pos (4UL)    /*!< Position of TRIGGERED4 field.                                        */
10727   #define BELLBOARD_INTPEND7_TRIGGERED4_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.    */
10728   #define BELLBOARD_INTPEND7_TRIGGERED4_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED4 field.                            */
10729   #define BELLBOARD_INTPEND7_TRIGGERED4_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED4 field.                            */
10730   #define BELLBOARD_INTPEND7_TRIGGERED4_NotPending (0x0UL) /*!< Read: Not pending                                              */
10731   #define BELLBOARD_INTPEND7_TRIGGERED4_Pending (0x1UL) /*!< Read: Pending                                                     */
10732 
10733 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
10734   #define BELLBOARD_INTPEND7_TRIGGERED5_Pos (5UL)    /*!< Position of TRIGGERED5 field.                                        */
10735   #define BELLBOARD_INTPEND7_TRIGGERED5_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.    */
10736   #define BELLBOARD_INTPEND7_TRIGGERED5_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED5 field.                            */
10737   #define BELLBOARD_INTPEND7_TRIGGERED5_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED5 field.                            */
10738   #define BELLBOARD_INTPEND7_TRIGGERED5_NotPending (0x0UL) /*!< Read: Not pending                                              */
10739   #define BELLBOARD_INTPEND7_TRIGGERED5_Pending (0x1UL) /*!< Read: Pending                                                     */
10740 
10741 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
10742   #define BELLBOARD_INTPEND7_TRIGGERED6_Pos (6UL)    /*!< Position of TRIGGERED6 field.                                        */
10743   #define BELLBOARD_INTPEND7_TRIGGERED6_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.    */
10744   #define BELLBOARD_INTPEND7_TRIGGERED6_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED6 field.                            */
10745   #define BELLBOARD_INTPEND7_TRIGGERED6_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED6 field.                            */
10746   #define BELLBOARD_INTPEND7_TRIGGERED6_NotPending (0x0UL) /*!< Read: Not pending                                              */
10747   #define BELLBOARD_INTPEND7_TRIGGERED6_Pending (0x1UL) /*!< Read: Pending                                                     */
10748 
10749 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
10750   #define BELLBOARD_INTPEND7_TRIGGERED7_Pos (7UL)    /*!< Position of TRIGGERED7 field.                                        */
10751   #define BELLBOARD_INTPEND7_TRIGGERED7_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.    */
10752   #define BELLBOARD_INTPEND7_TRIGGERED7_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED7 field.                            */
10753   #define BELLBOARD_INTPEND7_TRIGGERED7_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED7 field.                            */
10754   #define BELLBOARD_INTPEND7_TRIGGERED7_NotPending (0x0UL) /*!< Read: Not pending                                              */
10755   #define BELLBOARD_INTPEND7_TRIGGERED7_Pending (0x1UL) /*!< Read: Pending                                                     */
10756 
10757 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
10758   #define BELLBOARD_INTPEND7_TRIGGERED8_Pos (8UL)    /*!< Position of TRIGGERED8 field.                                        */
10759   #define BELLBOARD_INTPEND7_TRIGGERED8_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.    */
10760   #define BELLBOARD_INTPEND7_TRIGGERED8_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED8 field.                            */
10761   #define BELLBOARD_INTPEND7_TRIGGERED8_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED8 field.                            */
10762   #define BELLBOARD_INTPEND7_TRIGGERED8_NotPending (0x0UL) /*!< Read: Not pending                                              */
10763   #define BELLBOARD_INTPEND7_TRIGGERED8_Pending (0x1UL) /*!< Read: Pending                                                     */
10764 
10765 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
10766   #define BELLBOARD_INTPEND7_TRIGGERED9_Pos (9UL)    /*!< Position of TRIGGERED9 field.                                        */
10767   #define BELLBOARD_INTPEND7_TRIGGERED9_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.    */
10768   #define BELLBOARD_INTPEND7_TRIGGERED9_Min (0x0UL)  /*!< Min enumerator value of TRIGGERED9 field.                            */
10769   #define BELLBOARD_INTPEND7_TRIGGERED9_Max (0x1UL)  /*!< Max enumerator value of TRIGGERED9 field.                            */
10770   #define BELLBOARD_INTPEND7_TRIGGERED9_NotPending (0x0UL) /*!< Read: Not pending                                              */
10771   #define BELLBOARD_INTPEND7_TRIGGERED9_Pending (0x1UL) /*!< Read: Pending                                                     */
10772 
10773 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
10774   #define BELLBOARD_INTPEND7_TRIGGERED10_Pos (10UL)  /*!< Position of TRIGGERED10 field.                                       */
10775   #define BELLBOARD_INTPEND7_TRIGGERED10_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
10776   #define BELLBOARD_INTPEND7_TRIGGERED10_Min (0x0UL) /*!< Min enumerator value of TRIGGERED10 field.                           */
10777   #define BELLBOARD_INTPEND7_TRIGGERED10_Max (0x1UL) /*!< Max enumerator value of TRIGGERED10 field.                           */
10778   #define BELLBOARD_INTPEND7_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                             */
10779   #define BELLBOARD_INTPEND7_TRIGGERED10_Pending (0x1UL) /*!< Read: Pending                                                    */
10780 
10781 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
10782   #define BELLBOARD_INTPEND7_TRIGGERED11_Pos (11UL)  /*!< Position of TRIGGERED11 field.                                       */
10783   #define BELLBOARD_INTPEND7_TRIGGERED11_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
10784   #define BELLBOARD_INTPEND7_TRIGGERED11_Min (0x0UL) /*!< Min enumerator value of TRIGGERED11 field.                           */
10785   #define BELLBOARD_INTPEND7_TRIGGERED11_Max (0x1UL) /*!< Max enumerator value of TRIGGERED11 field.                           */
10786   #define BELLBOARD_INTPEND7_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                             */
10787   #define BELLBOARD_INTPEND7_TRIGGERED11_Pending (0x1UL) /*!< Read: Pending                                                    */
10788 
10789 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
10790   #define BELLBOARD_INTPEND7_TRIGGERED12_Pos (12UL)  /*!< Position of TRIGGERED12 field.                                       */
10791   #define BELLBOARD_INTPEND7_TRIGGERED12_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
10792   #define BELLBOARD_INTPEND7_TRIGGERED12_Min (0x0UL) /*!< Min enumerator value of TRIGGERED12 field.                           */
10793   #define BELLBOARD_INTPEND7_TRIGGERED12_Max (0x1UL) /*!< Max enumerator value of TRIGGERED12 field.                           */
10794   #define BELLBOARD_INTPEND7_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                             */
10795   #define BELLBOARD_INTPEND7_TRIGGERED12_Pending (0x1UL) /*!< Read: Pending                                                    */
10796 
10797 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
10798   #define BELLBOARD_INTPEND7_TRIGGERED13_Pos (13UL)  /*!< Position of TRIGGERED13 field.                                       */
10799   #define BELLBOARD_INTPEND7_TRIGGERED13_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
10800   #define BELLBOARD_INTPEND7_TRIGGERED13_Min (0x0UL) /*!< Min enumerator value of TRIGGERED13 field.                           */
10801   #define BELLBOARD_INTPEND7_TRIGGERED13_Max (0x1UL) /*!< Max enumerator value of TRIGGERED13 field.                           */
10802   #define BELLBOARD_INTPEND7_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                             */
10803   #define BELLBOARD_INTPEND7_TRIGGERED13_Pending (0x1UL) /*!< Read: Pending                                                    */
10804 
10805 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
10806   #define BELLBOARD_INTPEND7_TRIGGERED14_Pos (14UL)  /*!< Position of TRIGGERED14 field.                                       */
10807   #define BELLBOARD_INTPEND7_TRIGGERED14_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
10808   #define BELLBOARD_INTPEND7_TRIGGERED14_Min (0x0UL) /*!< Min enumerator value of TRIGGERED14 field.                           */
10809   #define BELLBOARD_INTPEND7_TRIGGERED14_Max (0x1UL) /*!< Max enumerator value of TRIGGERED14 field.                           */
10810   #define BELLBOARD_INTPEND7_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                             */
10811   #define BELLBOARD_INTPEND7_TRIGGERED14_Pending (0x1UL) /*!< Read: Pending                                                    */
10812 
10813 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
10814   #define BELLBOARD_INTPEND7_TRIGGERED15_Pos (15UL)  /*!< Position of TRIGGERED15 field.                                       */
10815   #define BELLBOARD_INTPEND7_TRIGGERED15_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
10816   #define BELLBOARD_INTPEND7_TRIGGERED15_Min (0x0UL) /*!< Min enumerator value of TRIGGERED15 field.                           */
10817   #define BELLBOARD_INTPEND7_TRIGGERED15_Max (0x1UL) /*!< Max enumerator value of TRIGGERED15 field.                           */
10818   #define BELLBOARD_INTPEND7_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                             */
10819   #define BELLBOARD_INTPEND7_TRIGGERED15_Pending (0x1UL) /*!< Read: Pending                                                    */
10820 
10821 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
10822   #define BELLBOARD_INTPEND7_TRIGGERED16_Pos (16UL)  /*!< Position of TRIGGERED16 field.                                       */
10823   #define BELLBOARD_INTPEND7_TRIGGERED16_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field. */
10824   #define BELLBOARD_INTPEND7_TRIGGERED16_Min (0x0UL) /*!< Min enumerator value of TRIGGERED16 field.                           */
10825   #define BELLBOARD_INTPEND7_TRIGGERED16_Max (0x1UL) /*!< Max enumerator value of TRIGGERED16 field.                           */
10826   #define BELLBOARD_INTPEND7_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                             */
10827   #define BELLBOARD_INTPEND7_TRIGGERED16_Pending (0x1UL) /*!< Read: Pending                                                    */
10828 
10829 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
10830   #define BELLBOARD_INTPEND7_TRIGGERED17_Pos (17UL)  /*!< Position of TRIGGERED17 field.                                       */
10831   #define BELLBOARD_INTPEND7_TRIGGERED17_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field. */
10832   #define BELLBOARD_INTPEND7_TRIGGERED17_Min (0x0UL) /*!< Min enumerator value of TRIGGERED17 field.                           */
10833   #define BELLBOARD_INTPEND7_TRIGGERED17_Max (0x1UL) /*!< Max enumerator value of TRIGGERED17 field.                           */
10834   #define BELLBOARD_INTPEND7_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                             */
10835   #define BELLBOARD_INTPEND7_TRIGGERED17_Pending (0x1UL) /*!< Read: Pending                                                    */
10836 
10837 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
10838   #define BELLBOARD_INTPEND7_TRIGGERED18_Pos (18UL)  /*!< Position of TRIGGERED18 field.                                       */
10839   #define BELLBOARD_INTPEND7_TRIGGERED18_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field. */
10840   #define BELLBOARD_INTPEND7_TRIGGERED18_Min (0x0UL) /*!< Min enumerator value of TRIGGERED18 field.                           */
10841   #define BELLBOARD_INTPEND7_TRIGGERED18_Max (0x1UL) /*!< Max enumerator value of TRIGGERED18 field.                           */
10842   #define BELLBOARD_INTPEND7_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                             */
10843   #define BELLBOARD_INTPEND7_TRIGGERED18_Pending (0x1UL) /*!< Read: Pending                                                    */
10844 
10845 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
10846   #define BELLBOARD_INTPEND7_TRIGGERED19_Pos (19UL)  /*!< Position of TRIGGERED19 field.                                       */
10847   #define BELLBOARD_INTPEND7_TRIGGERED19_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field. */
10848   #define BELLBOARD_INTPEND7_TRIGGERED19_Min (0x0UL) /*!< Min enumerator value of TRIGGERED19 field.                           */
10849   #define BELLBOARD_INTPEND7_TRIGGERED19_Max (0x1UL) /*!< Max enumerator value of TRIGGERED19 field.                           */
10850   #define BELLBOARD_INTPEND7_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                             */
10851   #define BELLBOARD_INTPEND7_TRIGGERED19_Pending (0x1UL) /*!< Read: Pending                                                    */
10852 
10853 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
10854   #define BELLBOARD_INTPEND7_TRIGGERED20_Pos (20UL)  /*!< Position of TRIGGERED20 field.                                       */
10855   #define BELLBOARD_INTPEND7_TRIGGERED20_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field. */
10856   #define BELLBOARD_INTPEND7_TRIGGERED20_Min (0x0UL) /*!< Min enumerator value of TRIGGERED20 field.                           */
10857   #define BELLBOARD_INTPEND7_TRIGGERED20_Max (0x1UL) /*!< Max enumerator value of TRIGGERED20 field.                           */
10858   #define BELLBOARD_INTPEND7_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                             */
10859   #define BELLBOARD_INTPEND7_TRIGGERED20_Pending (0x1UL) /*!< Read: Pending                                                    */
10860 
10861 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
10862   #define BELLBOARD_INTPEND7_TRIGGERED21_Pos (21UL)  /*!< Position of TRIGGERED21 field.                                       */
10863   #define BELLBOARD_INTPEND7_TRIGGERED21_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field. */
10864   #define BELLBOARD_INTPEND7_TRIGGERED21_Min (0x0UL) /*!< Min enumerator value of TRIGGERED21 field.                           */
10865   #define BELLBOARD_INTPEND7_TRIGGERED21_Max (0x1UL) /*!< Max enumerator value of TRIGGERED21 field.                           */
10866   #define BELLBOARD_INTPEND7_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                             */
10867   #define BELLBOARD_INTPEND7_TRIGGERED21_Pending (0x1UL) /*!< Read: Pending                                                    */
10868 
10869 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
10870   #define BELLBOARD_INTPEND7_TRIGGERED22_Pos (22UL)  /*!< Position of TRIGGERED22 field.                                       */
10871   #define BELLBOARD_INTPEND7_TRIGGERED22_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field. */
10872   #define BELLBOARD_INTPEND7_TRIGGERED22_Min (0x0UL) /*!< Min enumerator value of TRIGGERED22 field.                           */
10873   #define BELLBOARD_INTPEND7_TRIGGERED22_Max (0x1UL) /*!< Max enumerator value of TRIGGERED22 field.                           */
10874   #define BELLBOARD_INTPEND7_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                             */
10875   #define BELLBOARD_INTPEND7_TRIGGERED22_Pending (0x1UL) /*!< Read: Pending                                                    */
10876 
10877 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
10878   #define BELLBOARD_INTPEND7_TRIGGERED23_Pos (23UL)  /*!< Position of TRIGGERED23 field.                                       */
10879   #define BELLBOARD_INTPEND7_TRIGGERED23_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field. */
10880   #define BELLBOARD_INTPEND7_TRIGGERED23_Min (0x0UL) /*!< Min enumerator value of TRIGGERED23 field.                           */
10881   #define BELLBOARD_INTPEND7_TRIGGERED23_Max (0x1UL) /*!< Max enumerator value of TRIGGERED23 field.                           */
10882   #define BELLBOARD_INTPEND7_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                             */
10883   #define BELLBOARD_INTPEND7_TRIGGERED23_Pending (0x1UL) /*!< Read: Pending                                                    */
10884 
10885 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
10886   #define BELLBOARD_INTPEND7_TRIGGERED24_Pos (24UL)  /*!< Position of TRIGGERED24 field.                                       */
10887   #define BELLBOARD_INTPEND7_TRIGGERED24_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field. */
10888   #define BELLBOARD_INTPEND7_TRIGGERED24_Min (0x0UL) /*!< Min enumerator value of TRIGGERED24 field.                           */
10889   #define BELLBOARD_INTPEND7_TRIGGERED24_Max (0x1UL) /*!< Max enumerator value of TRIGGERED24 field.                           */
10890   #define BELLBOARD_INTPEND7_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                             */
10891   #define BELLBOARD_INTPEND7_TRIGGERED24_Pending (0x1UL) /*!< Read: Pending                                                    */
10892 
10893 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
10894   #define BELLBOARD_INTPEND7_TRIGGERED25_Pos (25UL)  /*!< Position of TRIGGERED25 field.                                       */
10895   #define BELLBOARD_INTPEND7_TRIGGERED25_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field. */
10896   #define BELLBOARD_INTPEND7_TRIGGERED25_Min (0x0UL) /*!< Min enumerator value of TRIGGERED25 field.                           */
10897   #define BELLBOARD_INTPEND7_TRIGGERED25_Max (0x1UL) /*!< Max enumerator value of TRIGGERED25 field.                           */
10898   #define BELLBOARD_INTPEND7_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                             */
10899   #define BELLBOARD_INTPEND7_TRIGGERED25_Pending (0x1UL) /*!< Read: Pending                                                    */
10900 
10901 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
10902   #define BELLBOARD_INTPEND7_TRIGGERED26_Pos (26UL)  /*!< Position of TRIGGERED26 field.                                       */
10903   #define BELLBOARD_INTPEND7_TRIGGERED26_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field. */
10904   #define BELLBOARD_INTPEND7_TRIGGERED26_Min (0x0UL) /*!< Min enumerator value of TRIGGERED26 field.                           */
10905   #define BELLBOARD_INTPEND7_TRIGGERED26_Max (0x1UL) /*!< Max enumerator value of TRIGGERED26 field.                           */
10906   #define BELLBOARD_INTPEND7_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                             */
10907   #define BELLBOARD_INTPEND7_TRIGGERED26_Pending (0x1UL) /*!< Read: Pending                                                    */
10908 
10909 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
10910   #define BELLBOARD_INTPEND7_TRIGGERED27_Pos (27UL)  /*!< Position of TRIGGERED27 field.                                       */
10911   #define BELLBOARD_INTPEND7_TRIGGERED27_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field. */
10912   #define BELLBOARD_INTPEND7_TRIGGERED27_Min (0x0UL) /*!< Min enumerator value of TRIGGERED27 field.                           */
10913   #define BELLBOARD_INTPEND7_TRIGGERED27_Max (0x1UL) /*!< Max enumerator value of TRIGGERED27 field.                           */
10914   #define BELLBOARD_INTPEND7_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                             */
10915   #define BELLBOARD_INTPEND7_TRIGGERED27_Pending (0x1UL) /*!< Read: Pending                                                    */
10916 
10917 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
10918   #define BELLBOARD_INTPEND7_TRIGGERED28_Pos (28UL)  /*!< Position of TRIGGERED28 field.                                       */
10919   #define BELLBOARD_INTPEND7_TRIGGERED28_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field. */
10920   #define BELLBOARD_INTPEND7_TRIGGERED28_Min (0x0UL) /*!< Min enumerator value of TRIGGERED28 field.                           */
10921   #define BELLBOARD_INTPEND7_TRIGGERED28_Max (0x1UL) /*!< Max enumerator value of TRIGGERED28 field.                           */
10922   #define BELLBOARD_INTPEND7_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                             */
10923   #define BELLBOARD_INTPEND7_TRIGGERED28_Pending (0x1UL) /*!< Read: Pending                                                    */
10924 
10925 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
10926   #define BELLBOARD_INTPEND7_TRIGGERED29_Pos (29UL)  /*!< Position of TRIGGERED29 field.                                       */
10927   #define BELLBOARD_INTPEND7_TRIGGERED29_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field. */
10928   #define BELLBOARD_INTPEND7_TRIGGERED29_Min (0x0UL) /*!< Min enumerator value of TRIGGERED29 field.                           */
10929   #define BELLBOARD_INTPEND7_TRIGGERED29_Max (0x1UL) /*!< Max enumerator value of TRIGGERED29 field.                           */
10930   #define BELLBOARD_INTPEND7_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                             */
10931   #define BELLBOARD_INTPEND7_TRIGGERED29_Pending (0x1UL) /*!< Read: Pending                                                    */
10932 
10933 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
10934   #define BELLBOARD_INTPEND7_TRIGGERED30_Pos (30UL)  /*!< Position of TRIGGERED30 field.                                       */
10935   #define BELLBOARD_INTPEND7_TRIGGERED30_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field. */
10936   #define BELLBOARD_INTPEND7_TRIGGERED30_Min (0x0UL) /*!< Min enumerator value of TRIGGERED30 field.                           */
10937   #define BELLBOARD_INTPEND7_TRIGGERED30_Max (0x1UL) /*!< Max enumerator value of TRIGGERED30 field.                           */
10938   #define BELLBOARD_INTPEND7_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                             */
10939   #define BELLBOARD_INTPEND7_TRIGGERED30_Pending (0x1UL) /*!< Read: Pending                                                    */
10940 
10941 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
10942   #define BELLBOARD_INTPEND7_TRIGGERED31_Pos (31UL)  /*!< Position of TRIGGERED31 field.                                       */
10943   #define BELLBOARD_INTPEND7_TRIGGERED31_Msk (0x1UL << BELLBOARD_INTPEND7_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field. */
10944   #define BELLBOARD_INTPEND7_TRIGGERED31_Min (0x0UL) /*!< Min enumerator value of TRIGGERED31 field.                           */
10945   #define BELLBOARD_INTPEND7_TRIGGERED31_Max (0x1UL) /*!< Max enumerator value of TRIGGERED31 field.                           */
10946   #define BELLBOARD_INTPEND7_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                             */
10947   #define BELLBOARD_INTPEND7_TRIGGERED31_Pending (0x1UL) /*!< Read: Pending                                                    */
10948 
10949 
10950 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
10951 
10952 /* =========================================================================================================================== */
10953 /* ================                                      BELLBOARDPUBLIC                                      ================ */
10954 /* =========================================================================================================================== */
10955 
10956 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
10957 /* ================================================= Struct BELLBOARDPUBLIC ================================================== */
10958 /**
10959   * @brief BELLBOARD public registers
10960   */
10961   typedef struct {                                   /*!< BELLBOARDPUBLIC Structure                                            */
10962     __OM uint32_t TASKS_TRIGGER[32];                 /*!< (@ 0x00000000) Task TRIGGER[n]                                       */
10963   } NRF_BELLBOARDPUBLIC_Type;                        /*!< Size = 128 (0x080)                                                   */
10964 
10965 /* BELLBOARDPUBLIC_TASKS_TRIGGER: Task TRIGGER[n] */
10966   #define BELLBOARDPUBLIC_TASKS_TRIGGER_MaxCount (32UL) /*!< Max size of TASKS_TRIGGER[32] array.                              */
10967   #define BELLBOARDPUBLIC_TASKS_TRIGGER_MaxIndex (31UL) /*!< Max index of TASKS_TRIGGER[32] array.                             */
10968   #define BELLBOARDPUBLIC_TASKS_TRIGGER_MinIndex (0UL) /*!< Min index of TASKS_TRIGGER[32] array.                              */
10969   #define BELLBOARDPUBLIC_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register.              */
10970 
10971 /* TASKS_TRIGGER @Bit 0 : Task TRIGGER[n] */
10972   #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field.                          */
10973   #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit
10974                                                                             mask of TASKS_TRIGGER field.*/
10975   #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field.            */
10976   #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field.            */
10977   #define BELLBOARDPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task                                        */
10978 
10979 
10980 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
10981 
10982 /* =========================================================================================================================== */
10983 /* ================                                           BICR                                           ================ */
10984 /* =========================================================================================================================== */
10985 
10986 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
10987 
10988 /* ==================================================== Struct BICR_POWER ==================================================== */
10989 /**
10990   * @brief POWER [BICR_POWER] (unspecified)
10991   */
10992 typedef struct {
10993   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Power configuration of power rails.                   */
10994 } NRF_BICR_POWER_Type;                               /*!< Size = 4 (0x004)                                                     */
10995 
10996 /* BICR_POWER_CONFIG: Power configuration of power rails. */
10997   #define BICR_POWER_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register.                                     */
10998 
10999 /* VDDAO1V8 @Bits 0..3 : VDD_AO_1V8 power configuration. */
11000   #define BICR_POWER_CONFIG_VDDAO1V8_Pos (0UL)       /*!< Position of VDDAO1V8 field.                                          */
11001   #define BICR_POWER_CONFIG_VDDAO1V8_Msk (0xFUL << BICR_POWER_CONFIG_VDDAO1V8_Pos) /*!< Bit mask of VDDAO1V8 field.            */
11002   #define BICR_POWER_CONFIG_VDDAO1V8_Min (0x0UL)     /*!< Min enumerator value of VDDAO1V8 field.                              */
11003   #define BICR_POWER_CONFIG_VDDAO1V8_Max (0xFUL)     /*!< Max enumerator value of VDDAO1V8 field.                              */
11004   #define BICR_POWER_CONFIG_VDDAO1V8_Unconfigured (0xFUL) /*!< Power rail is unconfigured.                                     */
11005   #define BICR_POWER_CONFIG_VDDAO1V8_Internal (0x0UL) /*!< Power rail is configured to use the internal regulator.             */
11006   #define BICR_POWER_CONFIG_VDDAO1V8_External (0x1UL) /*!< Power rail is configured to be externally powered.                  */
11007 
11008 /* VDD1V0 @Bits 4..7 : VDD_1V0 power configuration. */
11009   #define BICR_POWER_CONFIG_VDD1V0_Pos (4UL)         /*!< Position of VDD1V0 field.                                            */
11010   #define BICR_POWER_CONFIG_VDD1V0_Msk (0xFUL << BICR_POWER_CONFIG_VDD1V0_Pos) /*!< Bit mask of VDD1V0 field.                  */
11011   #define BICR_POWER_CONFIG_VDD1V0_Min (0x0UL)       /*!< Min enumerator value of VDD1V0 field.                                */
11012   #define BICR_POWER_CONFIG_VDD1V0_Max (0xFUL)       /*!< Max enumerator value of VDD1V0 field.                                */
11013   #define BICR_POWER_CONFIG_VDD1V0_Unconfigured (0xFUL) /*!< Power rail is unconfigured.                                       */
11014   #define BICR_POWER_CONFIG_VDD1V0_Internal (0x0UL)  /*!< Power rail is configured to use the internal regulator.              */
11015   #define BICR_POWER_CONFIG_VDD1V0_External (0x1UL)  /*!< Power rail is configured to be externally powered.                   */
11016 
11017 /* VDDRF1V0 @Bits 8..11 : VDD_RF_1V0 power configuration. */
11018   #define BICR_POWER_CONFIG_VDDRF1V0_Pos (8UL)       /*!< Position of VDDRF1V0 field.                                          */
11019   #define BICR_POWER_CONFIG_VDDRF1V0_Msk (0xFUL << BICR_POWER_CONFIG_VDDRF1V0_Pos) /*!< Bit mask of VDDRF1V0 field.            */
11020   #define BICR_POWER_CONFIG_VDDRF1V0_Min (0x1UL)     /*!< Min enumerator value of VDDRF1V0 field.                              */
11021   #define BICR_POWER_CONFIG_VDDRF1V0_Max (0xFUL)     /*!< Max enumerator value of VDDRF1V0 field.                              */
11022   #define BICR_POWER_CONFIG_VDDRF1V0_Unconfigured (0xFUL) /*!< Power rail is unconfigured.                                     */
11023   #define BICR_POWER_CONFIG_VDDRF1V0_External (0x1UL) /*!< Power rail is configured to be externally powered.                  */
11024   #define BICR_POWER_CONFIG_VDDRF1V0_Shorted (0x2UL) /*!< Power rail is shorted to VDD_1V0.                                    */
11025 
11026 /* VDDAO0V8 @Bits 12..15 : VDD_AO_0V8 power configuration. */
11027   #define BICR_POWER_CONFIG_VDDAO0V8_Pos (12UL)      /*!< Position of VDDAO0V8 field.                                          */
11028   #define BICR_POWER_CONFIG_VDDAO0V8_Msk (0xFUL << BICR_POWER_CONFIG_VDDAO0V8_Pos) /*!< Bit mask of VDDAO0V8 field.            */
11029   #define BICR_POWER_CONFIG_VDDAO0V8_Min (0x0UL)     /*!< Min enumerator value of VDDAO0V8 field.                              */
11030   #define BICR_POWER_CONFIG_VDDAO0V8_Max (0xFUL)     /*!< Max enumerator value of VDDAO0V8 field.                              */
11031   #define BICR_POWER_CONFIG_VDDAO0V8_Unconfigured (0xFUL) /*!< Power rail is unconfigured.                                     */
11032   #define BICR_POWER_CONFIG_VDDAO0V8_Internal (0x0UL) /*!< Power rail is configured to use the internal regulator.             */
11033   #define BICR_POWER_CONFIG_VDDAO0V8_External (0x1UL) /*!< Power rail is configured to be externally powered.                  */
11034 
11035 /* VDDVS0V8 @Bits 16..19 : VDD_VS_0V8 power configuration. */
11036   #define BICR_POWER_CONFIG_VDDVS0V8_Pos (16UL)      /*!< Position of VDDVS0V8 field.                                          */
11037   #define BICR_POWER_CONFIG_VDDVS0V8_Msk (0xFUL << BICR_POWER_CONFIG_VDDVS0V8_Pos) /*!< Bit mask of VDDVS0V8 field.            */
11038   #define BICR_POWER_CONFIG_VDDVS0V8_Min (0x0UL)     /*!< Min enumerator value of VDDVS0V8 field.                              */
11039   #define BICR_POWER_CONFIG_VDDVS0V8_Max (0xFUL)     /*!< Max enumerator value of VDDVS0V8 field.                              */
11040   #define BICR_POWER_CONFIG_VDDVS0V8_Unconfigured (0xFUL) /*!< Power rail is unconfigured.                                     */
11041   #define BICR_POWER_CONFIG_VDDVS0V8_Internal (0x0UL) /*!< Power rail is configured to use the internal regulator.             */
11042   #define BICR_POWER_CONFIG_VDDVS0V8_External (0x1UL) /*!< Power rail is configured to be externally powered.                  */
11043 
11044 /* INDUCTOR @Bit 31 : DC/DC inductor presence. */
11045   #define BICR_POWER_CONFIG_INDUCTOR_Pos (31UL)      /*!< Position of INDUCTOR field.                                          */
11046   #define BICR_POWER_CONFIG_INDUCTOR_Msk (0x1UL << BICR_POWER_CONFIG_INDUCTOR_Pos) /*!< Bit mask of INDUCTOR field.            */
11047   #define BICR_POWER_CONFIG_INDUCTOR_Min (0x0UL)     /*!< Min enumerator value of INDUCTOR field.                              */
11048   #define BICR_POWER_CONFIG_INDUCTOR_Max (0x1UL)     /*!< Max enumerator value of INDUCTOR field.                              */
11049   #define BICR_POWER_CONFIG_INDUCTOR_NotPresent (0x1UL) /*!< DC/DC inductor is not present.                                    */
11050   #define BICR_POWER_CONFIG_INDUCTOR_Present (0x0UL) /*!< DC/DC inductor is present.                                           */
11051 
11052 
11053 
11054 /* =================================================== Struct BICR_IOPORT ==================================================== */
11055 /**
11056   * @brief IOPORT [BICR_IOPORT] (unspecified)
11057   */
11058 typedef struct {
11059   __IOM uint32_t  POWER0;                            /*!< (@ 0x00000000) Power configuration for P0 to P7 IO ports.            */
11060   __IOM uint32_t  POWER1;                            /*!< (@ 0x00000004) Power configuration for P8 to P15 IO ports.           */
11061   __IOM uint32_t  DRIVECTRL0;                        /*!< (@ 0x00000008) Drive control configuration for P0 to P7 IO ports.    */
11062   __IOM uint32_t  DRIVECTRL1;                        /*!< (@ 0x0000000C) Drive control configuration for P8 to P15 IO ports.   */
11063 } NRF_BICR_IOPORT_Type;                              /*!< Size = 16 (0x010)                                                    */
11064 
11065 /* BICR_IOPORT_POWER0: Power configuration for P0 to P7 IO ports. */
11066   #define BICR_IOPORT_POWER0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of POWER0 register.                                    */
11067 
11068 /* P0 @Bits 0..3 : P0 power configuration. */
11069   #define BICR_IOPORT_POWER0_P0_Pos (0UL)            /*!< Position of P0 field.                                                */
11070   #define BICR_IOPORT_POWER0_P0_Msk (0xFUL << BICR_IOPORT_POWER0_P0_Pos) /*!< Bit mask of P0 field.                            */
11071   #define BICR_IOPORT_POWER0_P0_Min (0x0UL)          /*!< Min enumerator value of P0 field.                                    */
11072   #define BICR_IOPORT_POWER0_P0_Max (0xFUL)          /*!< Max enumerator value of P0 field.                                    */
11073   #define BICR_IOPORT_POWER0_P0_Unconfigured (0xFUL) /*!< Port supply is unconfigured.                                         */
11074   #define BICR_IOPORT_POWER0_P0_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used.              */
11075   #define BICR_IOPORT_POWER0_P0_Shorted (0x1UL)      /*!< Port supply is shorted to VDD_AO_1V8.                                */
11076   #define BICR_IOPORT_POWER0_P0_External1V8 (0x2UL)  /*!< Port supply is provided externally at 1.8 V.                         */
11077 
11078 /* P1 @Bits 4..7 : P1 power configuration. */
11079   #define BICR_IOPORT_POWER0_P1_Pos (4UL)            /*!< Position of P1 field.                                                */
11080   #define BICR_IOPORT_POWER0_P1_Msk (0xFUL << BICR_IOPORT_POWER0_P1_Pos) /*!< Bit mask of P1 field.                            */
11081   #define BICR_IOPORT_POWER0_P1_Min (0x0UL)          /*!< Min enumerator value of P1 field.                                    */
11082   #define BICR_IOPORT_POWER0_P1_Max (0xFUL)          /*!< Max enumerator value of P1 field.                                    */
11083   #define BICR_IOPORT_POWER0_P1_Unconfigured (0xFUL) /*!< Port supply is unconfigured.                                         */
11084   #define BICR_IOPORT_POWER0_P1_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used.              */
11085   #define BICR_IOPORT_POWER0_P1_Shorted (0x1UL)      /*!< Port supply is shorted to VDD_AO_1V8.                                */
11086   #define BICR_IOPORT_POWER0_P1_External1V8 (0x2UL)  /*!< Port supply is provided externally at 1.8 V.                         */
11087 
11088 /* P2 @Bits 8..11 : P2 power configuration. */
11089   #define BICR_IOPORT_POWER0_P2_Pos (8UL)            /*!< Position of P2 field.                                                */
11090   #define BICR_IOPORT_POWER0_P2_Msk (0xFUL << BICR_IOPORT_POWER0_P2_Pos) /*!< Bit mask of P2 field.                            */
11091   #define BICR_IOPORT_POWER0_P2_Min (0x0UL)          /*!< Min enumerator value of P2 field.                                    */
11092   #define BICR_IOPORT_POWER0_P2_Max (0xFUL)          /*!< Max enumerator value of P2 field.                                    */
11093   #define BICR_IOPORT_POWER0_P2_Unconfigured (0xFUL) /*!< Port supply is unconfigured.                                         */
11094   #define BICR_IOPORT_POWER0_P2_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used.              */
11095   #define BICR_IOPORT_POWER0_P2_Shorted (0x1UL)      /*!< Port supply is shorted to VDD_AO_1V8.                                */
11096   #define BICR_IOPORT_POWER0_P2_External1V8 (0x2UL)  /*!< Port supply is provided externally at 1.8 V.                         */
11097 
11098 /* P6 @Bits 24..27 : P6 power configuration. */
11099   #define BICR_IOPORT_POWER0_P6_Pos (24UL)           /*!< Position of P6 field.                                                */
11100   #define BICR_IOPORT_POWER0_P6_Msk (0xFUL << BICR_IOPORT_POWER0_P6_Pos) /*!< Bit mask of P6 field.                            */
11101   #define BICR_IOPORT_POWER0_P6_Min (0x0UL)          /*!< Min enumerator value of P6 field.                                    */
11102   #define BICR_IOPORT_POWER0_P6_Max (0xFUL)          /*!< Max enumerator value of P6 field.                                    */
11103   #define BICR_IOPORT_POWER0_P6_Unconfigured (0xFUL) /*!< Port supply is unconfigured.                                         */
11104   #define BICR_IOPORT_POWER0_P6_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used.              */
11105   #define BICR_IOPORT_POWER0_P6_Shorted (0x1UL)      /*!< Port supply is shorted to VDD_AO_1V8.                                */
11106   #define BICR_IOPORT_POWER0_P6_External1V8 (0x2UL)  /*!< Port supply is provided externally at 1.8 V.                         */
11107 
11108 /* P7 @Bits 28..31 : P7 power configuration. */
11109   #define BICR_IOPORT_POWER0_P7_Pos (28UL)           /*!< Position of P7 field.                                                */
11110   #define BICR_IOPORT_POWER0_P7_Msk (0xFUL << BICR_IOPORT_POWER0_P7_Pos) /*!< Bit mask of P7 field.                            */
11111   #define BICR_IOPORT_POWER0_P7_Min (0x0UL)          /*!< Min enumerator value of P7 field.                                    */
11112   #define BICR_IOPORT_POWER0_P7_Max (0xFUL)          /*!< Max enumerator value of P7 field.                                    */
11113   #define BICR_IOPORT_POWER0_P7_Unconfigured (0xFUL) /*!< Port supply is unconfigured.                                         */
11114   #define BICR_IOPORT_POWER0_P7_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used.              */
11115   #define BICR_IOPORT_POWER0_P7_Shorted (0x1UL)      /*!< Port supply is shorted to VDD_AO_1V8.                                */
11116   #define BICR_IOPORT_POWER0_P7_External1V8 (0x2UL)  /*!< Port supply is provided externally at 1.8 V.                         */
11117 
11118 
11119 /* BICR_IOPORT_POWER1: Power configuration for P8 to P15 IO ports. */
11120   #define BICR_IOPORT_POWER1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of POWER1 register.                                    */
11121 
11122 /* P9 @Bits 4..7 : P9 power configuration. */
11123   #define BICR_IOPORT_POWER1_P9_Pos (4UL)            /*!< Position of P9 field.                                                */
11124   #define BICR_IOPORT_POWER1_P9_Msk (0xFUL << BICR_IOPORT_POWER1_P9_Pos) /*!< Bit mask of P9 field.                            */
11125   #define BICR_IOPORT_POWER1_P9_Min (0x0UL)          /*!< Min enumerator value of P9 field.                                    */
11126   #define BICR_IOPORT_POWER1_P9_Max (0xFUL)          /*!< Max enumerator value of P9 field.                                    */
11127   #define BICR_IOPORT_POWER1_P9_Unconfigured (0xFUL) /*!< Port supply is unconfigured.                                         */
11128   #define BICR_IOPORT_POWER1_P9_Disconnected (0x0UL) /*!< Port supply rail is not connected. Port cannot be used.              */
11129   #define BICR_IOPORT_POWER1_P9_Shorted (0x1UL)      /*!< Port supply is shorted to VDD_AO_1V8.                                */
11130   #define BICR_IOPORT_POWER1_P9_External1V8 (0x2UL)  /*!< Port supply is provided externally at 1.8 V.                         */
11131   #define BICR_IOPORT_POWER1_P9_External3V (0x3UL)   /*!< Port supply is provided externally at 3 V.                           */
11132   #define BICR_IOPORT_POWER1_P9_ExternalFull (0x4UL) /*!< Port supply is provided externally with a full range of values, from 3
11133                                                           V to 1.8 V.*/
11134 
11135 
11136 /* BICR_IOPORT_DRIVECTRL0: Drive control configuration for P0 to P7 IO ports. */
11137   #define BICR_IOPORT_DRIVECTRL0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DRIVECTRL0 register.                            */
11138 
11139 /* P0 @Bits 0..3 : P0 drive control configuration. */
11140   #define BICR_IOPORT_DRIVECTRL0_P0_Pos (0UL)        /*!< Position of P0 field.                                                */
11141   #define BICR_IOPORT_DRIVECTRL0_P0_Msk (0xFUL << BICR_IOPORT_DRIVECTRL0_P0_Pos) /*!< Bit mask of P0 field.                    */
11142   #define BICR_IOPORT_DRIVECTRL0_P0_Min (0xFUL)      /*!< Min enumerator value of P0 field.                                    */
11143   #define BICR_IOPORT_DRIVECTRL0_P0_Max (0xFUL)      /*!< Max enumerator value of P0 field.                                    */
11144   #define BICR_IOPORT_DRIVECTRL0_P0_Unconfigured (0xFUL) /*!< Port supply is unconfigured. PORTCNF.DRIVECTRL will not be
11145                                                               adjusted.*/
11146 
11147 /* P1 @Bits 4..7 : P1 drive control configuration. */
11148   #define BICR_IOPORT_DRIVECTRL0_P1_Pos (4UL)        /*!< Position of P1 field.                                                */
11149   #define BICR_IOPORT_DRIVECTRL0_P1_Msk (0xFUL << BICR_IOPORT_DRIVECTRL0_P1_Pos) /*!< Bit mask of P1 field.                    */
11150   #define BICR_IOPORT_DRIVECTRL0_P1_Min (0xFUL)      /*!< Min enumerator value of P1 field.                                    */
11151   #define BICR_IOPORT_DRIVECTRL0_P1_Max (0xFUL)      /*!< Max enumerator value of P1 field.                                    */
11152   #define BICR_IOPORT_DRIVECTRL0_P1_Unconfigured (0xFUL) /*!< Port supply is unconfigured. PORTCNF.DRIVECTRL will not be
11153                                                               adjusted.*/
11154 
11155 /* P2 @Bits 8..11 : P2 drive control configuration. */
11156   #define BICR_IOPORT_DRIVECTRL0_P2_Pos (8UL)        /*!< Position of P2 field.                                                */
11157   #define BICR_IOPORT_DRIVECTRL0_P2_Msk (0xFUL << BICR_IOPORT_DRIVECTRL0_P2_Pos) /*!< Bit mask of P2 field.                    */
11158   #define BICR_IOPORT_DRIVECTRL0_P2_Min (0xFUL)      /*!< Min enumerator value of P2 field.                                    */
11159   #define BICR_IOPORT_DRIVECTRL0_P2_Max (0xFUL)      /*!< Max enumerator value of P2 field.                                    */
11160   #define BICR_IOPORT_DRIVECTRL0_P2_Unconfigured (0xFUL) /*!< Port supply is unconfigured. PORTCNF.DRIVECTRL will not be
11161                                                               adjusted.*/
11162 
11163 /* P6 @Bits 24..27 : P6 drive control configuration. */
11164   #define BICR_IOPORT_DRIVECTRL0_P6_Pos (24UL)       /*!< Position of P6 field.                                                */
11165   #define BICR_IOPORT_DRIVECTRL0_P6_Msk (0xFUL << BICR_IOPORT_DRIVECTRL0_P6_Pos) /*!< Bit mask of P6 field.                    */
11166   #define BICR_IOPORT_DRIVECTRL0_P6_Min (0x0UL)      /*!< Min enumerator value of P6 field.                                    */
11167   #define BICR_IOPORT_DRIVECTRL0_P6_Max (0xFUL)      /*!< Max enumerator value of P6 field.                                    */
11168   #define BICR_IOPORT_DRIVECTRL0_P6_Unconfigured (0xFUL) /*!< Port supply is unconfigured. PORTCNF.DRIVECTRL will not be
11169                                                               adjusted.*/
11170   #define BICR_IOPORT_DRIVECTRL0_P6_Ohms33 (0x0UL)   /*!< PORTCNF.DRIVECTRL will be adjusted for 33 Ohms.                      */
11171   #define BICR_IOPORT_DRIVECTRL0_P6_Ohms40 (0x1UL)   /*!< PORTCNF.DRIVECTRL will be adjusted for 40 Ohms.                      */
11172   #define BICR_IOPORT_DRIVECTRL0_P6_Ohms50 (0x2UL)   /*!< PORTCNF.DRIVECTRL will be adjusted for 50 Ohms.                      */
11173   #define BICR_IOPORT_DRIVECTRL0_P6_Ohms66 (0x3UL)   /*!< PORTCNF.DRIVECTRL will be adjusted for 66 Ohms.                      */
11174   #define BICR_IOPORT_DRIVECTRL0_P6_Ohms100 (0x4UL)  /*!< PORTCNF.DRIVECTRL will be adjusted for 100 Ohms.                     */
11175 
11176 /* P7 @Bits 28..31 : P7 drive control configuration. */
11177   #define BICR_IOPORT_DRIVECTRL0_P7_Pos (28UL)       /*!< Position of P7 field.                                                */
11178   #define BICR_IOPORT_DRIVECTRL0_P7_Msk (0xFUL << BICR_IOPORT_DRIVECTRL0_P7_Pos) /*!< Bit mask of P7 field.                    */
11179   #define BICR_IOPORT_DRIVECTRL0_P7_Min (0x0UL)      /*!< Min enumerator value of P7 field.                                    */
11180   #define BICR_IOPORT_DRIVECTRL0_P7_Max (0xFUL)      /*!< Max enumerator value of P7 field.                                    */
11181   #define BICR_IOPORT_DRIVECTRL0_P7_Unconfigured (0xFUL) /*!< Port supply is unconfigured. PORTCNF.DRIVECTRL will not be
11182                                                               adjusted.*/
11183   #define BICR_IOPORT_DRIVECTRL0_P7_Ohms33 (0x0UL)   /*!< PORTCNF.DRIVECTRL will be adjusted for 33 Ohms.                      */
11184   #define BICR_IOPORT_DRIVECTRL0_P7_Ohms40 (0x1UL)   /*!< PORTCNF.DRIVECTRL will be adjusted for 40 Ohms.                      */
11185   #define BICR_IOPORT_DRIVECTRL0_P7_Ohms50 (0x2UL)   /*!< PORTCNF.DRIVECTRL will be adjusted for 50 Ohms.                      */
11186   #define BICR_IOPORT_DRIVECTRL0_P7_Ohms66 (0x3UL)   /*!< PORTCNF.DRIVECTRL will be adjusted for 66 Ohms.                      */
11187   #define BICR_IOPORT_DRIVECTRL0_P7_Ohms100 (0x4UL)  /*!< PORTCNF.DRIVECTRL will be adjusted for 100 Ohms.                     */
11188 
11189 
11190 /* BICR_IOPORT_DRIVECTRL1: Drive control configuration for P8 to P15 IO ports. */
11191   #define BICR_IOPORT_DRIVECTRL1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DRIVECTRL1 register.                            */
11192 
11193 /* P9 @Bits 4..7 : P9 drive control configuration. */
11194   #define BICR_IOPORT_DRIVECTRL1_P9_Pos (4UL)        /*!< Position of P9 field.                                                */
11195   #define BICR_IOPORT_DRIVECTRL1_P9_Msk (0xFUL << BICR_IOPORT_DRIVECTRL1_P9_Pos) /*!< Bit mask of P9 field.                    */
11196   #define BICR_IOPORT_DRIVECTRL1_P9_Min (0xFUL)      /*!< Min enumerator value of P9 field.                                    */
11197   #define BICR_IOPORT_DRIVECTRL1_P9_Max (0xFUL)      /*!< Max enumerator value of P9 field.                                    */
11198   #define BICR_IOPORT_DRIVECTRL1_P9_Unconfigured (0xFUL) /*!< Port supply is unconfigured. PORTCNF.DRIVECTRL will not be
11199                                                               adjusted.*/
11200 
11201 
11202 
11203 /* ==================================================== Struct BICR_LFOSC ==================================================== */
11204 /**
11205   * @brief LFOSC [BICR_LFOSC] (unspecified)
11206   */
11207 typedef struct {
11208   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) LF oscillator configuration.                          */
11209   __IOM uint32_t  LFXOCONFIG;                        /*!< (@ 0x00000004) LFXO configuration.                                   */
11210   __IOM uint32_t  LFXOCAL;                           /*!< (@ 0x00000008) LFXO calibration needed. Must be written to 0xFFFFFFFF
11211                                                                          after any modification of the LFXO board circuit, load
11212                                                                          capacitance, or crystal swap.*/
11213   __IOM uint32_t  LFRCAUTOCALCONFIG;                 /*!< (@ 0x0000000C) LFRC autocalibration configuration.                   */
11214 } NRF_BICR_LFOSC_Type;                               /*!< Size = 16 (0x010)                                                    */
11215 
11216 /* BICR_LFOSC_CONFIG: LF oscillator configuration. */
11217   #define BICR_LFOSC_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register.                                     */
11218 
11219 /* SRC @Bits 0..3 : LF oscillator source. */
11220   #define BICR_LFOSC_CONFIG_SRC_Pos (0UL)            /*!< Position of SRC field.                                               */
11221   #define BICR_LFOSC_CONFIG_SRC_Msk (0xFUL << BICR_LFOSC_CONFIG_SRC_Pos) /*!< Bit mask of SRC field.                           */
11222   #define BICR_LFOSC_CONFIG_SRC_Min (0x0UL)          /*!< Min enumerator value of SRC field.                                   */
11223   #define BICR_LFOSC_CONFIG_SRC_Max (0xFUL)          /*!< Max enumerator value of SRC field.                                   */
11224   #define BICR_LFOSC_CONFIG_SRC_Unconfigured (0xFUL) /*!< LF oscillator source is unconfigured. Default will be used.          */
11225   #define BICR_LFOSC_CONFIG_SRC_LFXO (0x0UL)         /*!< Use LFXO as source for the LF oscillator.                            */
11226   #define BICR_LFOSC_CONFIG_SRC_LFRC (0x1UL)         /*!< Use LFRC as source for the LF oscillator.                            */
11227   #define BICR_LFOSC_CONFIG_SRC_Synth (0x3UL)        /*!< Use LF Synth as source for the LF oscillator.                        */
11228 
11229 
11230 /* BICR_LFOSC_LFXOCONFIG: LFXO configuration. */
11231   #define BICR_LFOSC_LFXOCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFXOCONFIG register.                             */
11232 
11233 /* ACCURACY @Bits 0..3 : LFXO crystal or external signal accuracy. */
11234   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Pos (0UL)   /*!< Position of ACCURACY field.                                          */
11235   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Msk (0xFUL << BICR_LFOSC_LFXOCONFIG_ACCURACY_Pos) /*!< Bit mask of ACCURACY field.    */
11236   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Min (0x0UL) /*!< Min enumerator value of ACCURACY field.                              */
11237   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Max (0xFUL) /*!< Max enumerator value of ACCURACY field.                              */
11238   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_Unconfigured (0xFUL) /*!< The accuracy is unconfigured.                               */
11239   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_500ppm (0x0UL) /*!< LFXO crystal or external signal has an accuracy of 500 ppm.       */
11240   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_250ppm (0x1UL) /*!< LFXO crystal or external signal has an accuracy of 250 ppm.       */
11241   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_150ppm (0x2UL) /*!< LFXO crystal or external signal has an accuracy of 150 ppm.       */
11242   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_100ppm (0x3UL) /*!< LFXO crystal or external signal has an accuracy of 100 ppm.       */
11243   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_75ppm (0x4UL) /*!< LFXO crystal or external signal has an accuracy of 75 ppm.         */
11244   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_50ppm (0x5UL) /*!< LFXO crystal or external signal has an accuracy of 50 ppm.         */
11245   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_30ppm (0x6UL) /*!< LFXO crystal or external signal has an accuracy of 30 ppm.         */
11246   #define BICR_LFOSC_LFXOCONFIG_ACCURACY_20ppm (0x7UL) /*!< LFXO crystal or external signal has an accuracy of 20 ppm.         */
11247 
11248 /* MODE @Bits 4..6 : LFXO mode. LFXO will not start unless MODE is configured. */
11249   #define BICR_LFOSC_LFXOCONFIG_MODE_Pos (4UL)       /*!< Position of MODE field.                                              */
11250   #define BICR_LFOSC_LFXOCONFIG_MODE_Msk (0x7UL << BICR_LFOSC_LFXOCONFIG_MODE_Pos) /*!< Bit mask of MODE field.                */
11251   #define BICR_LFOSC_LFXOCONFIG_MODE_Min (0x0UL)     /*!< Min enumerator value of MODE field.                                  */
11252   #define BICR_LFOSC_LFXOCONFIG_MODE_Max (0x7UL)     /*!< Max enumerator value of MODE field.                                  */
11253   #define BICR_LFOSC_LFXOCONFIG_MODE_Unconfigured (0x7UL) /*!< The mode is unconfigured.                                       */
11254   #define BICR_LFOSC_LFXOCONFIG_MODE_Pierce (0x0UL)  /*!< LFXO Pierce mode.                                                    */
11255   #define BICR_LFOSC_LFXOCONFIG_MODE_PIXO (0x1UL)    /*!< LFXO PIXO mode.                                                      */
11256   #define BICR_LFOSC_LFXOCONFIG_MODE_ExtSine (0x2UL) /*!< LFXO in external sine wave mode.                                     */
11257   #define BICR_LFOSC_LFXOCONFIG_MODE_ExtSquare (0x3UL) /*!< LFXO in external square wave mode.                                 */
11258 
11259 /* LOADCAP @Bits 8..15 : Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. */
11260   #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Pos (8UL)    /*!< Position of LOADCAP field.                                           */
11261   #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Msk (0xFFUL << BICR_LFOSC_LFXOCONFIG_LOADCAP_Pos) /*!< Bit mask of LOADCAP field.      */
11262   #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Min (0x0UL)  /*!< Min enumerator value of LOADCAP field.                               */
11263   #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Max (0xFFUL) /*!< Max enumerator value of LOADCAP field.                               */
11264   #define BICR_LFOSC_LFXOCONFIG_LOADCAP_Unconfigured (0xFFUL) /*!< The built-in load capacitors is unconfigured. LFXO will not
11265                                                                    start unless LOADCAP is configured.*/
11266   #define BICR_LFOSC_LFXOCONFIG_LOADCAP_External (0x00UL) /*!< Do not use the built-in load capacitors, only external capacitors
11267                                                                will be used.*/
11268 
11269 /* TIME @Bits 16..27 : LFXO startup time in ms. */
11270   #define BICR_LFOSC_LFXOCONFIG_TIME_Pos (16UL)      /*!< Position of TIME field.                                              */
11271   #define BICR_LFOSC_LFXOCONFIG_TIME_Msk (0xFFFUL << BICR_LFOSC_LFXOCONFIG_TIME_Pos) /*!< Bit mask of TIME field.              */
11272   #define BICR_LFOSC_LFXOCONFIG_TIME_Min (0xFFFUL)   /*!< Min enumerator value of TIME field.                                  */
11273   #define BICR_LFOSC_LFXOCONFIG_TIME_Max (0xFFFUL)   /*!< Max enumerator value of TIME field.                                  */
11274   #define BICR_LFOSC_LFXOCONFIG_TIME_Unconfigured (0xFFFUL) /*!< Startup time has not been configured.                         */
11275 
11276 
11277 /* BICR_LFOSC_LFXOCAL: LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board circuit,
11278                         load capacitance, or crystal swap. */
11279 
11280   #define BICR_LFOSC_LFXOCAL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFXOCAL register.                                   */
11281 
11282 /* LFXOCAL @Bits 0..31 : LFXO calibration needed. Must be written to 0xFFFFFFFF after any modification of the LFXO board
11283                          circuit, load capacitance, or crystal swap. */
11284 
11285   #define BICR_LFOSC_LFXOCAL_LFXOCAL_Pos (0UL)       /*!< Position of LFXOCAL field.                                           */
11286   #define BICR_LFOSC_LFXOCAL_LFXOCAL_Msk (0xFFFFFFFFUL << BICR_LFOSC_LFXOCAL_LFXOCAL_Pos) /*!< Bit mask of LFXOCAL field.      */
11287   #define BICR_LFOSC_LFXOCAL_LFXOCAL_Min (0xFFFFFFFFUL) /*!< Min enumerator value of LFXOCAL field.                            */
11288   #define BICR_LFOSC_LFXOCAL_LFXOCAL_Max (0xFFFFFFFFUL) /*!< Max enumerator value of LFXOCAL field.                            */
11289   #define BICR_LFOSC_LFXOCAL_LFXOCAL_Calibrate (0xFFFFFFFFUL) /*!< Calibrate the LFXO at startup.                              */
11290 
11291 
11292 /* BICR_LFOSC_LFRCAUTOCALCONFIG: LFRC autocalibration configuration. */
11293   #define BICR_LFOSC_LFRCAUTOCALCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LFRCAUTOCALCONFIG register.               */
11294 
11295 /* TEMPINTERVAL @Bits 0..6 : Temperature measurement interval in 0.25 s steps. */
11296   #define BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Pos (0UL) /*!< Position of TEMPINTERVAL field.                             */
11297   #define BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Msk (0x7FUL << BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPINTERVAL_Pos) /*!< Bit mask
11298                                                                             of TEMPINTERVAL field.*/
11299 
11300 /* TEMPDELTA @Bits 8..13 : Temperature delta that should trigger a calibration in 0.25 degrees steps. */
11301   #define BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Pos (8UL) /*!< Position of TEMPDELTA field.                                   */
11302   #define BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Msk (0x3FUL << BICR_LFOSC_LFRCAUTOCALCONFIG_TEMPDELTA_Pos) /*!< Bit mask of
11303                                                                             TEMPDELTA field.*/
11304 
11305 /* INTERVALMAXNO @Bits 16..20 : Maximum number of TEMPINTERVAL periods in between calibrations, independent of temperature
11306                                 changes. */
11307 
11308   #define BICR_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Pos (16UL) /*!< Position of INTERVALMAXNO field.                          */
11309   #define BICR_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Msk (0x1FUL << BICR_LFOSC_LFRCAUTOCALCONFIG_INTERVALMAXNO_Pos) /*!< Bit
11310                                                                             mask of INTERVALMAXNO field.*/
11311 
11312 /* ENABLE @Bit 31 : LFRC.AUTOCALCONFIG register enable. */
11313   #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Pos (31UL) /*!< Position of ENABLE field.                                        */
11314   #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Msk (0x1UL << BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE
11315                                                                             field.*/
11316   #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                           */
11317   #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                           */
11318   #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Enabled (0x0UL) /*!< LFRC.AUTOCALCONFIG register has been configured and can be
11319                                                                    used.*/
11320   #define BICR_LFOSC_LFRCAUTOCALCONFIG_ENABLE_Disabled (0x1UL) /*!< LFRC.AUTOCALCONFIG register has not been configured and
11321                                                                     cannot be used.*/
11322 
11323 
11324 
11325 /* ==================================================== Struct BICR_HFXO ===================================================== */
11326 /**
11327   * @brief HFXO [BICR_HFXO] (unspecified)
11328   */
11329 typedef struct {
11330   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) HFXO configuration.                                   */
11331   __IOM uint32_t  STARTUPTIME;                       /*!< (@ 0x00000004) HFXO startup time in us.                              */
11332 } NRF_BICR_HFXO_Type;                                /*!< Size = 8 (0x008)                                                     */
11333 
11334 /* BICR_HFXO_CONFIG: HFXO configuration. */
11335   #define BICR_HFXO_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register.                                      */
11336 
11337 /* MODE @Bits 8..10 : HFXO mode. */
11338   #define BICR_HFXO_CONFIG_MODE_Pos (8UL)            /*!< Position of MODE field.                                              */
11339   #define BICR_HFXO_CONFIG_MODE_Msk (0x7UL << BICR_HFXO_CONFIG_MODE_Pos) /*!< Bit mask of MODE field.                          */
11340   #define BICR_HFXO_CONFIG_MODE_Min (0x0UL)          /*!< Min enumerator value of MODE field.                                  */
11341   #define BICR_HFXO_CONFIG_MODE_Max (0x7UL)          /*!< Max enumerator value of MODE field.                                  */
11342   #define BICR_HFXO_CONFIG_MODE_Unconfigured (0x7UL) /*!< The mode is unconfigured.                                            */
11343   #define BICR_HFXO_CONFIG_MODE_Pierce (0x0UL)       /*!< HFXO Pierce mode.                                                    */
11344   #define BICR_HFXO_CONFIG_MODE_PIXO (0x1UL)         /*!< HFXO PIXO mode.                                                      */
11345   #define BICR_HFXO_CONFIG_MODE_ExtSquare (0x3UL)    /*!< HFXO in external square wave mode.                                   */
11346   #define BICR_HFXO_CONFIG_MODE_Auto (0x6UL)         /*!< Either Pierce or PIXO automatically handled by the system based on
11347                                                           system requests.*/
11348 
11349 /* LOADCAP @Bits 12..19 : Built-in load capacitors selection in 1 pF steps. Max. value 25 pF. */
11350   #define BICR_HFXO_CONFIG_LOADCAP_Pos (12UL)        /*!< Position of LOADCAP field.                                           */
11351   #define BICR_HFXO_CONFIG_LOADCAP_Msk (0xFFUL << BICR_HFXO_CONFIG_LOADCAP_Pos) /*!< Bit mask of LOADCAP field.                */
11352   #define BICR_HFXO_CONFIG_LOADCAP_Min (0x0UL)       /*!< Min enumerator value of LOADCAP field.                               */
11353   #define BICR_HFXO_CONFIG_LOADCAP_Max (0xFFUL)      /*!< Max enumerator value of LOADCAP field.                               */
11354   #define BICR_HFXO_CONFIG_LOADCAP_Unconfigured (0xFFUL) /*!< The built-in load capacitors is unconfigured. HFXO will not start
11355                                                               unless LOADCAP is configured.*/
11356   #define BICR_HFXO_CONFIG_LOADCAP_External (0x00UL) /*!< Do not use the built-in load capacitors, only external capacitors will
11357                                                           be used.*/
11358 
11359 
11360 /* BICR_HFXO_STARTUPTIME: HFXO startup time in us. */
11361   #define BICR_HFXO_STARTUPTIME_ResetValue (0xFFFFFFFFUL) /*!< Reset value of STARTUPTIME register.                            */
11362 
11363 /* TIME @Bits 0..31 : HFXO startup time in us. */
11364   #define BICR_HFXO_STARTUPTIME_TIME_Pos (0UL)       /*!< Position of TIME field.                                              */
11365   #define BICR_HFXO_STARTUPTIME_TIME_Msk (0xFFFFFFFFUL << BICR_HFXO_STARTUPTIME_TIME_Pos) /*!< Bit mask of TIME field.         */
11366   #define BICR_HFXO_STARTUPTIME_TIME_Min (0xFFFFFFFFUL) /*!< Min enumerator value of TIME field.                               */
11367   #define BICR_HFXO_STARTUPTIME_TIME_Max (0xFFFFFFFFUL) /*!< Max enumerator value of TIME field.                               */
11368   #define BICR_HFXO_STARTUPTIME_TIME_Unconfigured (0xFFFFFFFFUL) /*!< Startup time has not been configured.                    */
11369 
11370 
11371 
11372 /* ==================================================== Struct BICR_TAMPC ==================================================== */
11373 /**
11374   * @brief TAMPC [BICR_TAMPC] (unspecified)
11375   */
11376 typedef struct {
11377   __IOM uint32_t  TAMPERSWITCH;                      /*!< (@ 0x00000000) Configuration for external tamper switch detector.    */
11378   __IOM uint32_t  ACTIVESHIELD;                      /*!< (@ 0x00000004) Configuration for active shield channels.             */
11379 } NRF_BICR_TAMPC_Type;                               /*!< Size = 8 (0x008)                                                     */
11380 
11381 /* BICR_TAMPC_TAMPERSWITCH: Configuration for external tamper switch detector. */
11382   #define BICR_TAMPC_TAMPERSWITCH_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TAMPERSWITCH register.                         */
11383 
11384 /* TAMPERSWITCH @Bits 0..3 : Tamper switch enable. */
11385   #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Pos (0UL) /*!< Position of TAMPERSWITCH field.                                  */
11386   #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Msk (0xFUL << BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Pos) /*!< Bit mask of
11387                                                                             TAMPERSWITCH field.*/
11388   #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Min (0x0UL) /*!< Min enumerator value of TAMPERSWITCH field.                    */
11389   #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Max (0xFUL) /*!< Max enumerator value of TAMPERSWITCH field.                    */
11390   #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Disabled (0xFUL) /*!< Tamper switch is disabled.                                */
11391   #define BICR_TAMPC_TAMPERSWITCH_TAMPERSWITCH_Enabled (0x0UL) /*!< Tamper switch is enabled.                                  */
11392 
11393 
11394 /* BICR_TAMPC_ACTIVESHIELD: Configuration for active shield channels. */
11395   #define BICR_TAMPC_ACTIVESHIELD_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ACTIVESHIELD register.                         */
11396 
11397 /* CHEN0 @Bits 0..3 : Active shield enable for channel 0. */
11398   #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Pos (0UL)    /*!< Position of CHEN0 field.                                             */
11399   #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Msk (0xFUL << BICR_TAMPC_ACTIVESHIELD_CHEN0_Pos) /*!< Bit mask of CHEN0 field.         */
11400   #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Min (0x0UL)  /*!< Min enumerator value of CHEN0 field.                                 */
11401   #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Max (0xFUL)  /*!< Max enumerator value of CHEN0 field.                                 */
11402   #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Disabled (0xFUL) /*!< Active shield channel 0 is disabled.                             */
11403   #define BICR_TAMPC_ACTIVESHIELD_CHEN0_Enabled (0x0UL) /*!< Active shield channel 0 is enabled.                               */
11404 
11405 /* CHEN1 @Bits 4..7 : Active shield enable for channel 1. */
11406   #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Pos (4UL)    /*!< Position of CHEN1 field.                                             */
11407   #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Msk (0xFUL << BICR_TAMPC_ACTIVESHIELD_CHEN1_Pos) /*!< Bit mask of CHEN1 field.         */
11408   #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Min (0x0UL)  /*!< Min enumerator value of CHEN1 field.                                 */
11409   #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Max (0xFUL)  /*!< Max enumerator value of CHEN1 field.                                 */
11410   #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Disabled (0xFUL) /*!< Active shield channel 1 is disabled.                             */
11411   #define BICR_TAMPC_ACTIVESHIELD_CHEN1_Enabled (0x0UL) /*!< Active shield channel 1 is enabled.                               */
11412 
11413 /* CHEN2 @Bits 8..11 : Active shield enable for channel 2. */
11414   #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Pos (8UL)    /*!< Position of CHEN2 field.                                             */
11415   #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Msk (0xFUL << BICR_TAMPC_ACTIVESHIELD_CHEN2_Pos) /*!< Bit mask of CHEN2 field.         */
11416   #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Min (0x0UL)  /*!< Min enumerator value of CHEN2 field.                                 */
11417   #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Max (0xFUL)  /*!< Max enumerator value of CHEN2 field.                                 */
11418   #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Disabled (0xFUL) /*!< Active shield channel 2 is disabled.                             */
11419   #define BICR_TAMPC_ACTIVESHIELD_CHEN2_Enabled (0x0UL) /*!< Active shield channel 2 is enabled.                               */
11420 
11421 /* CHEN3 @Bits 12..15 : Active shield enable for channel 3. */
11422   #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Pos (12UL)   /*!< Position of CHEN3 field.                                             */
11423   #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Msk (0xFUL << BICR_TAMPC_ACTIVESHIELD_CHEN3_Pos) /*!< Bit mask of CHEN3 field.         */
11424   #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Min (0x0UL)  /*!< Min enumerator value of CHEN3 field.                                 */
11425   #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Max (0xFUL)  /*!< Max enumerator value of CHEN3 field.                                 */
11426   #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Disabled (0xFUL) /*!< Active shield channel 3 is disabled.                             */
11427   #define BICR_TAMPC_ACTIVESHIELD_CHEN3_Enabled (0x0UL) /*!< Active shield channel 3 is enabled.                               */
11428 
11429 
11430 /* ======================================================= Struct BICR ======================================================= */
11431 /**
11432   * @brief Board information configuration registers
11433   */
11434   typedef struct {                                   /*!< BICR Structure                                                       */
11435     __IOM NRF_BICR_POWER_Type POWER;                 /*!< (@ 0x00000000) (unspecified)                                         */
11436     __IOM NRF_BICR_IOPORT_Type IOPORT;               /*!< (@ 0x00000004) (unspecified)                                         */
11437     __IOM NRF_BICR_LFOSC_Type LFOSC;                 /*!< (@ 0x00000014) (unspecified)                                         */
11438     __IOM NRF_BICR_HFXO_Type HFXO;                   /*!< (@ 0x00000024) (unspecified)                                         */
11439     __IM uint32_t RESERVED[2];
11440     __IOM NRF_BICR_TAMPC_Type TAMPC;                 /*!< (@ 0x00000034) (unspecified)                                         */
11441   } NRF_BICR_Type;                                   /*!< Size = 60 (0x03C)                                                    */
11442 
11443 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
11444 
11445 /* =========================================================================================================================== */
11446 /* ================                                           CACHE                                           ================ */
11447 /* =========================================================================================================================== */
11448 
11449 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
11450 
11451 /* ================================================= Struct CACHE_PROFILING ================================================== */
11452 /**
11453   * @brief PROFILING [CACHE_PROFILING] (unspecified)
11454   */
11455 typedef struct {
11456   __IOM uint32_t  ENABLE;                            /*!< (@ 0x00000000) Enable the profiling counters.                        */
11457   __OM  uint32_t  CLEAR;                             /*!< (@ 0x00000004) Clear the profiling counters.                         */
11458   __IM  uint32_t  HIT;                               /*!< (@ 0x00000008) The cache hit counter for cache region.               */
11459   __IM  uint32_t  MISS;                              /*!< (@ 0x0000000C) The cache miss counter for cache region.              */
11460   __IM  uint32_t  LMISS;                             /*!< (@ 0x00000010) The cache line miss counter for cache region.         */
11461   __IM  uint32_t  READS;                             /*!< (@ 0x00000014) Number of reads for cache region.                     */
11462   __IM  uint32_t  WRITES;                            /*!< (@ 0x00000018) Number of writes for cache region.                    */
11463 } NRF_CACHE_PROFILING_Type;                          /*!< Size = 28 (0x01C)                                                    */
11464 
11465 /* CACHE_PROFILING_ENABLE: Enable the profiling counters. */
11466   #define CACHE_PROFILING_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register.                                */
11467 
11468 /* ENABLE @Bit 0 : Enable the profiling counters */
11469   #define CACHE_PROFILING_ENABLE_ENABLE_Pos (0UL)    /*!< Position of ENABLE field.                                            */
11470   #define CACHE_PROFILING_ENABLE_ENABLE_Msk (0x1UL << CACHE_PROFILING_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.        */
11471   #define CACHE_PROFILING_ENABLE_ENABLE_Min (0x0UL)  /*!< Min enumerator value of ENABLE field.                                */
11472   #define CACHE_PROFILING_ENABLE_ENABLE_Max (0x1UL)  /*!< Max enumerator value of ENABLE field.                                */
11473   #define CACHE_PROFILING_ENABLE_ENABLE_Disable (0x0UL) /*!< Disable profiling                                                 */
11474   #define CACHE_PROFILING_ENABLE_ENABLE_Enable (0x1UL) /*!< Enable profiling                                                   */
11475 
11476 
11477 /* CACHE_PROFILING_CLEAR: Clear the profiling counters. */
11478   #define CACHE_PROFILING_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of CLEAR register.                                  */
11479 
11480 /* CLEAR @Bit 0 : Clearing the profiling counters */
11481   #define CACHE_PROFILING_CLEAR_CLEAR_Pos (0UL)      /*!< Position of CLEAR field.                                             */
11482   #define CACHE_PROFILING_CLEAR_CLEAR_Msk (0x1UL << CACHE_PROFILING_CLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field.             */
11483   #define CACHE_PROFILING_CLEAR_CLEAR_Min (0x1UL)    /*!< Min enumerator value of CLEAR field.                                 */
11484   #define CACHE_PROFILING_CLEAR_CLEAR_Max (0x1UL)    /*!< Max enumerator value of CLEAR field.                                 */
11485   #define CACHE_PROFILING_CLEAR_CLEAR_Clear (0x1UL)  /*!< Clear the profiling counters                                         */
11486 
11487 
11488 /* CACHE_PROFILING_HIT: The cache hit counter for cache region. */
11489   #define CACHE_PROFILING_HIT_ResetValue (0x00000000UL) /*!< Reset value of HIT register.                                      */
11490 
11491 /* HITS @Bits 0..31 : Number of cache hits */
11492   #define CACHE_PROFILING_HIT_HITS_Pos (0UL)         /*!< Position of HITS field.                                              */
11493   #define CACHE_PROFILING_HIT_HITS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_HIT_HITS_Pos) /*!< Bit mask of HITS field.             */
11494 
11495 
11496 /* CACHE_PROFILING_MISS: The cache miss counter for cache region. */
11497   #define CACHE_PROFILING_MISS_ResetValue (0x00000000UL) /*!< Reset value of MISS register.                                    */
11498 
11499 /* MISSES @Bits 0..31 : Number of cache misses */
11500   #define CACHE_PROFILING_MISS_MISSES_Pos (0UL)      /*!< Position of MISSES field.                                            */
11501   #define CACHE_PROFILING_MISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_MISS_MISSES_Pos) /*!< Bit mask of MISSES field.     */
11502 
11503 
11504 /* CACHE_PROFILING_LMISS: The cache line miss counter for cache region. */
11505   #define CACHE_PROFILING_LMISS_ResetValue (0x00000000UL) /*!< Reset value of LMISS register.                                  */
11506 
11507 /* LMISSES @Bits 0..31 : Number of cache line misses */
11508   #define CACHE_PROFILING_LMISS_LMISSES_Pos (0UL)    /*!< Position of LMISSES field.                                           */
11509   #define CACHE_PROFILING_LMISS_LMISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_LMISS_LMISSES_Pos) /*!< Bit mask of LMISSES field.*/
11510 
11511 
11512 /* CACHE_PROFILING_READS: Number of reads for cache region. */
11513   #define CACHE_PROFILING_READS_ResetValue (0x00000000UL) /*!< Reset value of READS register.                                  */
11514 
11515 /* READS @Bits 0..31 : Number of reads for cache region. */
11516   #define CACHE_PROFILING_READS_READS_Pos (0UL)      /*!< Position of READS field.                                             */
11517   #define CACHE_PROFILING_READS_READS_Msk (0xFFFFFFFFUL << CACHE_PROFILING_READS_READS_Pos) /*!< Bit mask of READS field.      */
11518 
11519 
11520 /* CACHE_PROFILING_WRITES: Number of writes for cache region. */
11521   #define CACHE_PROFILING_WRITES_ResetValue (0x00000000UL) /*!< Reset value of WRITES register.                                */
11522 
11523 /* WRITES @Bits 0..31 : Number of writes for cache region. */
11524   #define CACHE_PROFILING_WRITES_WRITES_Pos (0UL)    /*!< Position of WRITES field.                                            */
11525   #define CACHE_PROFILING_WRITES_WRITES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_WRITES_WRITES_Pos) /*!< Bit mask of WRITES field. */
11526 
11527 
11528 /* ====================================================== Struct CACHE ======================================================= */
11529 /**
11530   * @brief Cache
11531   */
11532   typedef struct {                                   /*!< CACHE Structure                                                      */
11533     __OM uint32_t TASKS_SAVE;                        /*!< (@ 0x00000000) Save the cache state to a retained memory space.      */
11534     __OM uint32_t TASKS_RESTORE;                     /*!< (@ 0x00000004) Restore the cache state from a retained memory space. */
11535     __OM uint32_t TASKS_INVALIDATECACHE;             /*!< (@ 0x00000008) Invalidate the cache.                                 */
11536     __OM uint32_t TASKS_CLEANCACHE;                  /*!< (@ 0x0000000C) Clean the cache.                                      */
11537     __OM uint32_t TASKS_FLUSHCACHE;                  /*!< (@ 0x00000010) Flush the cache.                                      */
11538     __OM uint32_t TASKS_INVALIDATELINE;              /*!< (@ 0x00000014) Invalidate the line.                                  */
11539     __OM uint32_t TASKS_CLEANLINE;                   /*!< (@ 0x00000018) Clean the line.                                       */
11540     __OM uint32_t TASKS_FLUSHLINE;                   /*!< (@ 0x0000001C) Flush the line.                                       */
11541     __OM uint32_t TASKS_ERASE;                       /*!< (@ 0x00000020) Erase the cache.                                      */
11542     __IM uint32_t RESERVED[55];
11543     __IOM uint32_t EVENTS_DONE;                      /*!< (@ 0x00000100) Save or Restore task is done.                         */
11544     __IM uint32_t RESERVED1[127];
11545     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
11546     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
11547     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
11548     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
11549     __IM uint32_t RESERVED2[60];
11550     __IM uint32_t STATUS;                            /*!< (@ 0x00000400) Status of the cache activities.                       */
11551     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000404) Enable cache.                                         */
11552     __IOM uint32_t MODE;                             /*!< (@ 0x00000408) Cache mode.                                           */
11553     __IM uint32_t RESERVED3;
11554     __IOM uint32_t LINEADDR;                         /*!< (@ 0x00000410) Memory address covered by the line to be maintained.  */
11555     __IOM NRF_CACHE_PROFILING_Type PROFILING;        /*!< (@ 0x00000414) (unspecified)                                         */
11556     __IOM uint32_t DEBUGLOCK;                        /*!< (@ 0x00000430) Lock debug mode.                                      */
11557     __IOM uint32_t WRITELOCK;                        /*!< (@ 0x00000434) Lock cache updates.                                   */
11558   } NRF_CACHE_Type;                                  /*!< Size = 1080 (0x438)                                                  */
11559 
11560 /* CACHE_TASKS_SAVE: Save the cache state to a retained memory space. */
11561   #define CACHE_TASKS_SAVE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAVE register.                                  */
11562 
11563 /* TASKS_SAVE @Bit 0 : Save the cache state to a retained memory space. */
11564   #define CACHE_TASKS_SAVE_TASKS_SAVE_Pos (0UL)      /*!< Position of TASKS_SAVE field.                                        */
11565   #define CACHE_TASKS_SAVE_TASKS_SAVE_Msk (0x1UL << CACHE_TASKS_SAVE_TASKS_SAVE_Pos) /*!< Bit mask of TASKS_SAVE field.        */
11566   #define CACHE_TASKS_SAVE_TASKS_SAVE_Min (0x1UL)    /*!< Min enumerator value of TASKS_SAVE field.                            */
11567   #define CACHE_TASKS_SAVE_TASKS_SAVE_Max (0x1UL)    /*!< Max enumerator value of TASKS_SAVE field.                            */
11568   #define CACHE_TASKS_SAVE_TASKS_SAVE_Trigger (0x1UL) /*!< Trigger task                                                        */
11569 
11570 
11571 /* CACHE_TASKS_RESTORE: Restore the cache state from a retained memory space. */
11572   #define CACHE_TASKS_RESTORE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESTORE register.                            */
11573 
11574 /* TASKS_RESTORE @Bit 0 : Restore the cache state from a retained memory space. */
11575   #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Pos (0UL) /*!< Position of TASKS_RESTORE field.                                    */
11576   #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Msk (0x1UL << CACHE_TASKS_RESTORE_TASKS_RESTORE_Pos) /*!< Bit mask of TASKS_RESTORE
11577                                                                             field.*/
11578   #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Min (0x1UL) /*!< Min enumerator value of TASKS_RESTORE field.                      */
11579   #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Max (0x1UL) /*!< Max enumerator value of TASKS_RESTORE field.                      */
11580   #define CACHE_TASKS_RESTORE_TASKS_RESTORE_Trigger (0x1UL) /*!< Trigger task                                                  */
11581 
11582 
11583 /* CACHE_TASKS_INVALIDATECACHE: Invalidate the cache. */
11584   #define CACHE_TASKS_INVALIDATECACHE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_INVALIDATECACHE register.            */
11585 
11586 /* TASKS_INVALIDATECACHE @Bit 0 : Invalidate the cache. */
11587   #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Pos (0UL) /*!< Position of TASKS_INVALIDATECACHE field.            */
11588   #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Msk (0x1UL << CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Pos)
11589                                                                             /*!< Bit mask of TASKS_INVALIDATECACHE field.*/
11590   #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Min (0x1UL) /*!< Min enumerator value of TASKS_INVALIDATECACHE
11591                                                                             field.*/
11592   #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Max (0x1UL) /*!< Max enumerator value of TASKS_INVALIDATECACHE
11593                                                                             field.*/
11594   #define CACHE_TASKS_INVALIDATECACHE_TASKS_INVALIDATECACHE_Trigger (0x1UL) /*!< Trigger task                                  */
11595 
11596 
11597 /* CACHE_TASKS_CLEANCACHE: Clean the cache. */
11598   #define CACHE_TASKS_CLEANCACHE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEANCACHE register.                      */
11599 
11600 /* TASKS_CLEANCACHE @Bit 0 : Clean the cache. */
11601   #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Pos (0UL) /*!< Position of TASKS_CLEANCACHE field.                           */
11602   #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Msk (0x1UL << CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Pos) /*!< Bit mask of
11603                                                                             TASKS_CLEANCACHE field.*/
11604   #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Min (0x1UL) /*!< Min enumerator value of TASKS_CLEANCACHE field.             */
11605   #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Max (0x1UL) /*!< Max enumerator value of TASKS_CLEANCACHE field.             */
11606   #define CACHE_TASKS_CLEANCACHE_TASKS_CLEANCACHE_Trigger (0x1UL) /*!< Trigger task                                            */
11607 
11608 
11609 /* CACHE_TASKS_FLUSHCACHE: Flush the cache. */
11610   #define CACHE_TASKS_FLUSHCACHE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSHCACHE register.                      */
11611 
11612 /* TASKS_FLUSHCACHE @Bit 0 : Flush the cache. */
11613   #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Pos (0UL) /*!< Position of TASKS_FLUSHCACHE field.                           */
11614   #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Msk (0x1UL << CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Pos) /*!< Bit mask of
11615                                                                             TASKS_FLUSHCACHE field.*/
11616   #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSHCACHE field.             */
11617   #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSHCACHE field.             */
11618   #define CACHE_TASKS_FLUSHCACHE_TASKS_FLUSHCACHE_Trigger (0x1UL) /*!< Trigger task                                            */
11619 
11620 
11621 /* CACHE_TASKS_INVALIDATELINE: Invalidate the line. */
11622   #define CACHE_TASKS_INVALIDATELINE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_INVALIDATELINE register.              */
11623 
11624 /* TASKS_INVALIDATELINE @Bit 0 : Invalidate the line. */
11625   #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Pos (0UL) /*!< Position of TASKS_INVALIDATELINE field.               */
11626   #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Msk (0x1UL << CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Pos)
11627                                                                             /*!< Bit mask of TASKS_INVALIDATELINE field.*/
11628   #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Min (0x1UL) /*!< Min enumerator value of TASKS_INVALIDATELINE field. */
11629   #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Max (0x1UL) /*!< Max enumerator value of TASKS_INVALIDATELINE field. */
11630   #define CACHE_TASKS_INVALIDATELINE_TASKS_INVALIDATELINE_Trigger (0x1UL) /*!< Trigger task                                    */
11631 
11632 
11633 /* CACHE_TASKS_CLEANLINE: Clean the line. */
11634   #define CACHE_TASKS_CLEANLINE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEANLINE register.                        */
11635 
11636 /* TASKS_CLEANLINE @Bit 0 : Clean the line. */
11637   #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Pos (0UL) /*!< Position of TASKS_CLEANLINE field.                              */
11638   #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Msk (0x1UL << CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Pos) /*!< Bit mask of
11639                                                                             TASKS_CLEANLINE field.*/
11640   #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Min (0x1UL) /*!< Min enumerator value of TASKS_CLEANLINE field.                */
11641   #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Max (0x1UL) /*!< Max enumerator value of TASKS_CLEANLINE field.                */
11642   #define CACHE_TASKS_CLEANLINE_TASKS_CLEANLINE_Trigger (0x1UL) /*!< Trigger task                                              */
11643 
11644 
11645 /* CACHE_TASKS_FLUSHLINE: Flush the line. */
11646   #define CACHE_TASKS_FLUSHLINE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSHLINE register.                        */
11647 
11648 /* TASKS_FLUSHLINE @Bit 0 : Flush the line. */
11649   #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Pos (0UL) /*!< Position of TASKS_FLUSHLINE field.                              */
11650   #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Msk (0x1UL << CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Pos) /*!< Bit mask of
11651                                                                             TASKS_FLUSHLINE field.*/
11652   #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSHLINE field.                */
11653   #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSHLINE field.                */
11654   #define CACHE_TASKS_FLUSHLINE_TASKS_FLUSHLINE_Trigger (0x1UL) /*!< Trigger task                                              */
11655 
11656 
11657 /* CACHE_TASKS_ERASE: Erase the cache. */
11658   #define CACHE_TASKS_ERASE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ERASE register.                                */
11659 
11660 /* TASKS_ERASE @Bit 0 : Erase the cache. */
11661   #define CACHE_TASKS_ERASE_TASKS_ERASE_Pos (0UL)    /*!< Position of TASKS_ERASE field.                                       */
11662   #define CACHE_TASKS_ERASE_TASKS_ERASE_Msk (0x1UL << CACHE_TASKS_ERASE_TASKS_ERASE_Pos) /*!< Bit mask of TASKS_ERASE field.   */
11663   #define CACHE_TASKS_ERASE_TASKS_ERASE_Min (0x1UL)  /*!< Min enumerator value of TASKS_ERASE field.                           */
11664   #define CACHE_TASKS_ERASE_TASKS_ERASE_Max (0x1UL)  /*!< Max enumerator value of TASKS_ERASE field.                           */
11665   #define CACHE_TASKS_ERASE_TASKS_ERASE_Trigger (0x1UL) /*!< Trigger task                                                      */
11666 
11667 
11668 /* CACHE_EVENTS_DONE: Save or Restore task is done. */
11669   #define CACHE_EVENTS_DONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DONE register.                                */
11670 
11671 /* EVENTS_DONE @Bit 0 : Save or Restore task is done. */
11672   #define CACHE_EVENTS_DONE_EVENTS_DONE_Pos (0UL)    /*!< Position of EVENTS_DONE field.                                       */
11673   #define CACHE_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CACHE_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field.   */
11674   #define CACHE_EVENTS_DONE_EVENTS_DONE_Min (0x0UL)  /*!< Min enumerator value of EVENTS_DONE field.                           */
11675   #define CACHE_EVENTS_DONE_EVENTS_DONE_Max (0x1UL)  /*!< Max enumerator value of EVENTS_DONE field.                           */
11676   #define CACHE_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated                                          */
11677   #define CACHE_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated                                                 */
11678 
11679 
11680 /* CACHE_INTEN: Enable or disable interrupt */
11681   #define CACHE_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */
11682 
11683 /* DONE @Bit 0 : Enable or disable interrupt for event DONE */
11684   #define CACHE_INTEN_DONE_Pos (0UL)                 /*!< Position of DONE field.                                              */
11685   #define CACHE_INTEN_DONE_Msk (0x1UL << CACHE_INTEN_DONE_Pos) /*!< Bit mask of DONE field.                                    */
11686   #define CACHE_INTEN_DONE_Min (0x0UL)               /*!< Min enumerator value of DONE field.                                  */
11687   #define CACHE_INTEN_DONE_Max (0x1UL)               /*!< Max enumerator value of DONE field.                                  */
11688   #define CACHE_INTEN_DONE_Disabled (0x0UL)          /*!< Disable                                                              */
11689   #define CACHE_INTEN_DONE_Enabled (0x1UL)           /*!< Enable                                                               */
11690 
11691 
11692 /* CACHE_INTENSET: Enable interrupt */
11693   #define CACHE_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */
11694 
11695 /* DONE @Bit 0 : Write '1' to enable interrupt for event DONE */
11696   #define CACHE_INTENSET_DONE_Pos (0UL)              /*!< Position of DONE field.                                              */
11697   #define CACHE_INTENSET_DONE_Msk (0x1UL << CACHE_INTENSET_DONE_Pos) /*!< Bit mask of DONE field.                              */
11698   #define CACHE_INTENSET_DONE_Min (0x0UL)            /*!< Min enumerator value of DONE field.                                  */
11699   #define CACHE_INTENSET_DONE_Max (0x1UL)            /*!< Max enumerator value of DONE field.                                  */
11700   #define CACHE_INTENSET_DONE_Set (0x1UL)            /*!< Enable                                                               */
11701   #define CACHE_INTENSET_DONE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
11702   #define CACHE_INTENSET_DONE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
11703 
11704 
11705 /* CACHE_INTENCLR: Disable interrupt */
11706   #define CACHE_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */
11707 
11708 /* DONE @Bit 0 : Write '1' to disable interrupt for event DONE */
11709   #define CACHE_INTENCLR_DONE_Pos (0UL)              /*!< Position of DONE field.                                              */
11710   #define CACHE_INTENCLR_DONE_Msk (0x1UL << CACHE_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field.                              */
11711   #define CACHE_INTENCLR_DONE_Min (0x0UL)            /*!< Min enumerator value of DONE field.                                  */
11712   #define CACHE_INTENCLR_DONE_Max (0x1UL)            /*!< Max enumerator value of DONE field.                                  */
11713   #define CACHE_INTENCLR_DONE_Clear (0x1UL)          /*!< Disable                                                              */
11714   #define CACHE_INTENCLR_DONE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
11715   #define CACHE_INTENCLR_DONE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
11716 
11717 
11718 /* CACHE_INTPEND: Pending interrupts */
11719   #define CACHE_INTPEND_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND register.                                     */
11720 
11721 /* DONE @Bit 0 : Read pending status of interrupt for event DONE */
11722   #define CACHE_INTPEND_DONE_Pos (0UL)               /*!< Position of DONE field.                                              */
11723   #define CACHE_INTPEND_DONE_Msk (0x1UL << CACHE_INTPEND_DONE_Pos) /*!< Bit mask of DONE field.                                */
11724   #define CACHE_INTPEND_DONE_Min (0x0UL)             /*!< Min enumerator value of DONE field.                                  */
11725   #define CACHE_INTPEND_DONE_Max (0x1UL)             /*!< Max enumerator value of DONE field.                                  */
11726   #define CACHE_INTPEND_DONE_NotPending (0x0UL)      /*!< Read: Not pending                                                    */
11727   #define CACHE_INTPEND_DONE_Pending (0x1UL)         /*!< Read: Pending                                                        */
11728 
11729 
11730 /* CACHE_STATUS: Status of the cache activities. */
11731   #define CACHE_STATUS_ResetValue (0x00000000UL)     /*!< Reset value of STATUS register.                                      */
11732 
11733 /* READY @Bit 0 : Ready status. */
11734   #define CACHE_STATUS_READY_Pos (0UL)               /*!< Position of READY field.                                             */
11735   #define CACHE_STATUS_READY_Msk (0x1UL << CACHE_STATUS_READY_Pos) /*!< Bit mask of READY field.                               */
11736   #define CACHE_STATUS_READY_Min (0x0UL)             /*!< Min enumerator value of READY field.                                 */
11737   #define CACHE_STATUS_READY_Max (0x1UL)             /*!< Max enumerator value of READY field.                                 */
11738   #define CACHE_STATUS_READY_Ready (0x0UL)           /*!< Activity is done and ready for the next activity.                    */
11739   #define CACHE_STATUS_READY_Busy (0x1UL)            /*!< Activity is in progress.                                             */
11740 
11741 
11742 /* CACHE_ENABLE: Enable cache. */
11743   #define CACHE_ENABLE_ResetValue (0x00000000UL)     /*!< Reset value of ENABLE register.                                      */
11744 
11745 /* ENABLE @Bit 0 : Enable cache */
11746   #define CACHE_ENABLE_ENABLE_Pos (0UL)              /*!< Position of ENABLE field.                                            */
11747   #define CACHE_ENABLE_ENABLE_Msk (0x1UL << CACHE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                            */
11748   #define CACHE_ENABLE_ENABLE_Min (0x0UL)            /*!< Min enumerator value of ENABLE field.                                */
11749   #define CACHE_ENABLE_ENABLE_Max (0x1UL)            /*!< Max enumerator value of ENABLE field.                                */
11750   #define CACHE_ENABLE_ENABLE_Disabled (0x0UL)       /*!< Disable cache                                                        */
11751   #define CACHE_ENABLE_ENABLE_Enabled (0x1UL)        /*!< Enable cache                                                         */
11752 
11753 
11754 /* CACHE_MODE: Cache mode. */
11755   #define CACHE_MODE_ResetValue (0x00000000UL)       /*!< Reset value of MODE register.                                        */
11756 
11757 /* MODE @Bit 0 : Cache mode */
11758   #define CACHE_MODE_MODE_Pos (0UL)                  /*!< Position of MODE field.                                              */
11759   #define CACHE_MODE_MODE_Msk (0x1UL << CACHE_MODE_MODE_Pos) /*!< Bit mask of MODE field.                                      */
11760   #define CACHE_MODE_MODE_Min (0x0UL)                /*!< Min enumerator value of MODE field.                                  */
11761   #define CACHE_MODE_MODE_Max (0x1UL)                /*!< Max enumerator value of MODE field.                                  */
11762   #define CACHE_MODE_MODE_Cache (0x0UL)              /*!< Cache mode                                                           */
11763   #define CACHE_MODE_MODE_Ram (0x1UL)                /*!< RAM mode                                                             */
11764 
11765 /* RAMSIZE @Bits 4..5 : RAM size */
11766   #define CACHE_MODE_RAMSIZE_Pos (4UL)               /*!< Position of RAMSIZE field.                                           */
11767   #define CACHE_MODE_RAMSIZE_Msk (0x3UL << CACHE_MODE_RAMSIZE_Pos) /*!< Bit mask of RAMSIZE field.                             */
11768   #define CACHE_MODE_RAMSIZE_Min (0x0UL)             /*!< Min enumerator value of RAMSIZE field.                               */
11769   #define CACHE_MODE_RAMSIZE_Max (0x3UL)             /*!< Max enumerator value of RAMSIZE field.                               */
11770   #define CACHE_MODE_RAMSIZE_All (0x0UL)             /*!< All RAM is used for cache memory                                     */
11771   #define CACHE_MODE_RAMSIZE_Half (0x1UL)            /*!< Half of the RAM is used for cache memory                             */
11772   #define CACHE_MODE_RAMSIZE_Quarter (0x2UL)         /*!< Quarter of the RAM is used for cache memory                          */
11773   #define CACHE_MODE_RAMSIZE_None (0x3UL)            /*!< None of the RAM is used for cache memory                             */
11774 
11775 
11776 /* CACHE_LINEADDR: Memory address covered by the line to be maintained. */
11777   #define CACHE_LINEADDR_ResetValue (0x00000000UL)   /*!< Reset value of LINEADDR register.                                    */
11778 
11779 /* ADDR @Bits 0..31 : Address. */
11780   #define CACHE_LINEADDR_ADDR_Pos (0UL)              /*!< Position of ADDR field.                                              */
11781   #define CACHE_LINEADDR_ADDR_Msk (0xFFFFFFFFUL << CACHE_LINEADDR_ADDR_Pos) /*!< Bit mask of ADDR field.                       */
11782 
11783 
11784 /* CACHE_DEBUGLOCK: Lock debug mode. */
11785   #define CACHE_DEBUGLOCK_ResetValue (0x00000000UL)  /*!< Reset value of DEBUGLOCK register.                                   */
11786 
11787 /* DEBUGLOCK @Bit 0 : Lock debug mode */
11788   #define CACHE_DEBUGLOCK_DEBUGLOCK_Pos (0UL)        /*!< Position of DEBUGLOCK field.                                         */
11789   #define CACHE_DEBUGLOCK_DEBUGLOCK_Msk (0x1UL << CACHE_DEBUGLOCK_DEBUGLOCK_Pos) /*!< Bit mask of DEBUGLOCK field.             */
11790   #define CACHE_DEBUGLOCK_DEBUGLOCK_Min (0x0UL)      /*!< Min enumerator value of DEBUGLOCK field.                             */
11791   #define CACHE_DEBUGLOCK_DEBUGLOCK_Max (0x1UL)      /*!< Max enumerator value of DEBUGLOCK field.                             */
11792   #define CACHE_DEBUGLOCK_DEBUGLOCK_Unlocked (0x0UL) /*!< Debug mode unlocked                                                  */
11793   #define CACHE_DEBUGLOCK_DEBUGLOCK_Locked (0x1UL)   /*!< Debug mode locked. Ignores any other value written.                  */
11794 
11795 
11796 /* CACHE_WRITELOCK: Lock cache updates. */
11797   #define CACHE_WRITELOCK_ResetValue (0x00000000UL)  /*!< Reset value of WRITELOCK register.                                   */
11798 
11799 /* WRITELOCK @Bit 0 : Lock cache updates */
11800   #define CACHE_WRITELOCK_WRITELOCK_Pos (0UL)        /*!< Position of WRITELOCK field.                                         */
11801   #define CACHE_WRITELOCK_WRITELOCK_Msk (0x1UL << CACHE_WRITELOCK_WRITELOCK_Pos) /*!< Bit mask of WRITELOCK field.             */
11802   #define CACHE_WRITELOCK_WRITELOCK_Min (0x0UL)      /*!< Min enumerator value of WRITELOCK field.                             */
11803   #define CACHE_WRITELOCK_WRITELOCK_Max (0x1UL)      /*!< Max enumerator value of WRITELOCK field.                             */
11804   #define CACHE_WRITELOCK_WRITELOCK_Unlocked (0x0UL) /*!< Cache updates unlocked                                               */
11805   #define CACHE_WRITELOCK_WRITELOCK_Locked (0x1UL)   /*!< Cache updates locked                                                 */
11806 
11807 
11808 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
11809 
11810 /* =========================================================================================================================== */
11811 /* ================                                         CACHEDATA                                         ================ */
11812 /* =========================================================================================================================== */
11813 
11814 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
11815 
11816 /* =============================================== Struct CACHEDATA_SET_WAY_DU =============================================== */
11817 /**
11818   * @brief DU [CACHEDATA_SET_WAY_DU] (unspecified)
11819   */
11820 typedef struct {
11821   __IOM uint32_t  DATA[2];                           /*!< (@ 0x00000000) Cache data bits for DATA[q] in DU[p] (DataUnit) of
11822                                                                          SET[n], WAY[o].*/
11823 } NRF_CACHEDATA_SET_WAY_DU_Type;                     /*!< Size = 8 (0x008)                                                     */
11824   #define CACHEDATA_SET_WAY_DU_MaxCount (4UL)        /*!< Size of DU[4] array.                                                 */
11825   #define CACHEDATA_SET_WAY_DU_MaxIndex (3UL)        /*!< Max index of DU[4] array.                                            */
11826   #define CACHEDATA_SET_WAY_DU_MinIndex (0UL)        /*!< Min index of DU[4] array.                                            */
11827 
11828 /* CACHEDATA_SET_WAY_DU_DATA: Cache data bits for DATA[q] in DU[p] (DataUnit) of SET[n], WAY[o]. */
11829   #define CACHEDATA_SET_WAY_DU_DATA_MaxCount (2UL)   /*!< Max size of DATA[2] array.                                           */
11830   #define CACHEDATA_SET_WAY_DU_DATA_MaxIndex (1UL)   /*!< Max index of DATA[2] array.                                          */
11831   #define CACHEDATA_SET_WAY_DU_DATA_MinIndex (0UL)   /*!< Min index of DATA[2] array.                                          */
11832   #define CACHEDATA_SET_WAY_DU_DATA_ResetValue (0x00000000UL) /*!< Reset value of DATA[2] register.                            */
11833 
11834 /* Data @Bits 0..31 : Data */
11835   #define CACHEDATA_SET_WAY_DU_DATA_Data_Pos (0UL)   /*!< Position of Data field.                                              */
11836   #define CACHEDATA_SET_WAY_DU_DATA_Data_Msk (0xFFFFFFFFUL << CACHEDATA_SET_WAY_DU_DATA_Data_Pos) /*!< Bit mask of Data field. */
11837 
11838 
11839 
11840 /* ================================================ Struct CACHEDATA_SET_WAY ================================================= */
11841 /**
11842   * @brief WAY [CACHEDATA_SET_WAY] (unspecified)
11843   */
11844 typedef struct {
11845   __IOM NRF_CACHEDATA_SET_WAY_DU_Type DU[4];         /*!< (@ 0x00000000) (unspecified)                                         */
11846 } NRF_CACHEDATA_SET_WAY_Type;                        /*!< Size = 32 (0x020)                                                    */
11847   #define CACHEDATA_SET_WAY_MaxCount (2UL)           /*!< Size of WAY[2] array.                                                */
11848   #define CACHEDATA_SET_WAY_MaxIndex (1UL)           /*!< Max index of WAY[2] array.                                           */
11849   #define CACHEDATA_SET_WAY_MinIndex (0UL)           /*!< Min index of WAY[2] array.                                           */
11850 
11851 
11852 /* ================================================== Struct CACHEDATA_SET =================================================== */
11853 /**
11854   * @brief SET [CACHEDATA_SET] (unspecified)
11855   */
11856 typedef struct {
11857   __IOM NRF_CACHEDATA_SET_WAY_Type WAY[2];           /*!< (@ 0x00000000) (unspecified)                                         */
11858 } NRF_CACHEDATA_SET_Type;                            /*!< Size = 64 (0x040)                                                    */
11859   #define CACHEDATA_SET_MaxCount (256UL)             /*!< Size of SET[256] array.                                              */
11860   #define CACHEDATA_SET_MaxIndex (255UL)             /*!< Max index of SET[256] array.                                         */
11861   #define CACHEDATA_SET_MinIndex (0UL)               /*!< Min index of SET[256] array.                                         */
11862 
11863 /* ==================================================== Struct CACHEDATA ===================================================== */
11864 /**
11865   * @brief CACHEDATA
11866   */
11867   typedef struct {                                   /*!< CACHEDATA Structure                                                  */
11868     __IOM NRF_CACHEDATA_SET_Type SET[256];           /*!< (@ 0x00000000) (unspecified)                                         */
11869   } NRF_CACHEDATA_Type;                              /*!< Size = 16384 (0x4000)                                                */
11870 
11871 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
11872 
11873 /* =========================================================================================================================== */
11874 /* ================                                         CACHEINFO                                         ================ */
11875 /* =========================================================================================================================== */
11876 
11877 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
11878 
11879 /* ================================================== Struct CACHEINFO_SET =================================================== */
11880 /**
11881   * @brief SET [CACHEINFO_SET] (unspecified)
11882   */
11883 typedef struct {
11884   __IOM uint32_t  WAY[2];                            /*!< (@ 0x00000000) Cache information for SET[n], WAY[o].                 */
11885 } NRF_CACHEINFO_SET_Type;                            /*!< Size = 8 (0x008)                                                     */
11886   #define CACHEINFO_SET_MaxCount (256UL)             /*!< Size of SET[256] array.                                              */
11887   #define CACHEINFO_SET_MaxIndex (255UL)             /*!< Max index of SET[256] array.                                         */
11888   #define CACHEINFO_SET_MinIndex (0UL)               /*!< Min index of SET[256] array.                                         */
11889 
11890 /* CACHEINFO_SET_WAY: Cache information for SET[n], WAY[o]. */
11891   #define CACHEINFO_SET_WAY_MaxCount (2UL)           /*!< Max size of WAY[2] array.                                            */
11892   #define CACHEINFO_SET_WAY_MaxIndex (1UL)           /*!< Max index of WAY[2] array.                                           */
11893   #define CACHEINFO_SET_WAY_MinIndex (0UL)           /*!< Min index of WAY[2] array.                                           */
11894   #define CACHEINFO_SET_WAY_ResetValue (0x00000000UL) /*!< Reset value of WAY[2] register.                                     */
11895 
11896 /* TAG @Bits 0..23 : Cache tag. */
11897   #define CACHEINFO_SET_WAY_TAG_Pos (0UL)            /*!< Position of TAG field.                                               */
11898   #define CACHEINFO_SET_WAY_TAG_Msk (0xFFFFFFUL << CACHEINFO_SET_WAY_TAG_Pos) /*!< Bit mask of TAG field.                      */
11899 
11900 /* DUV0 @Bit 24 : Data unit valid info. */
11901   #define CACHEINFO_SET_WAY_DUV0_Pos (24UL)          /*!< Position of DUV0 field.                                              */
11902   #define CACHEINFO_SET_WAY_DUV0_Msk (0x1UL << CACHEINFO_SET_WAY_DUV0_Pos) /*!< Bit mask of DUV0 field.                        */
11903   #define CACHEINFO_SET_WAY_DUV0_Min (0x0UL)         /*!< Min enumerator value of DUV0 field.                                  */
11904   #define CACHEINFO_SET_WAY_DUV0_Max (0x1UL)         /*!< Max enumerator value of DUV0 field.                                  */
11905   #define CACHEINFO_SET_WAY_DUV0_Invalid (0x0UL)     /*!< Invalid data unit                                                    */
11906   #define CACHEINFO_SET_WAY_DUV0_Valid (0x1UL)       /*!< Valid data unit                                                      */
11907 
11908 /* DUV1 @Bit 25 : Data unit valid info. */
11909   #define CACHEINFO_SET_WAY_DUV1_Pos (25UL)          /*!< Position of DUV1 field.                                              */
11910   #define CACHEINFO_SET_WAY_DUV1_Msk (0x1UL << CACHEINFO_SET_WAY_DUV1_Pos) /*!< Bit mask of DUV1 field.                        */
11911   #define CACHEINFO_SET_WAY_DUV1_Min (0x0UL)         /*!< Min enumerator value of DUV1 field.                                  */
11912   #define CACHEINFO_SET_WAY_DUV1_Max (0x1UL)         /*!< Max enumerator value of DUV1 field.                                  */
11913   #define CACHEINFO_SET_WAY_DUV1_Invalid (0x0UL)     /*!< Invalid data unit                                                    */
11914   #define CACHEINFO_SET_WAY_DUV1_Valid (0x1UL)       /*!< Valid data unit                                                      */
11915 
11916 /* DUV2 @Bit 26 : Data unit valid info. */
11917   #define CACHEINFO_SET_WAY_DUV2_Pos (26UL)          /*!< Position of DUV2 field.                                              */
11918   #define CACHEINFO_SET_WAY_DUV2_Msk (0x1UL << CACHEINFO_SET_WAY_DUV2_Pos) /*!< Bit mask of DUV2 field.                        */
11919   #define CACHEINFO_SET_WAY_DUV2_Min (0x0UL)         /*!< Min enumerator value of DUV2 field.                                  */
11920   #define CACHEINFO_SET_WAY_DUV2_Max (0x1UL)         /*!< Max enumerator value of DUV2 field.                                  */
11921   #define CACHEINFO_SET_WAY_DUV2_Invalid (0x0UL)     /*!< Invalid data unit                                                    */
11922   #define CACHEINFO_SET_WAY_DUV2_Valid (0x1UL)       /*!< Valid data unit                                                      */
11923 
11924 /* DUV3 @Bit 27 : Data unit valid info. */
11925   #define CACHEINFO_SET_WAY_DUV3_Pos (27UL)          /*!< Position of DUV3 field.                                              */
11926   #define CACHEINFO_SET_WAY_DUV3_Msk (0x1UL << CACHEINFO_SET_WAY_DUV3_Pos) /*!< Bit mask of DUV3 field.                        */
11927   #define CACHEINFO_SET_WAY_DUV3_Min (0x0UL)         /*!< Min enumerator value of DUV3 field.                                  */
11928   #define CACHEINFO_SET_WAY_DUV3_Max (0x1UL)         /*!< Max enumerator value of DUV3 field.                                  */
11929   #define CACHEINFO_SET_WAY_DUV3_Invalid (0x0UL)     /*!< Invalid data unit                                                    */
11930   #define CACHEINFO_SET_WAY_DUV3_Valid (0x1UL)       /*!< Valid data unit                                                      */
11931 
11932 /* D0 @Bit 28 : Dirty data unit 0. */
11933   #define CACHEINFO_SET_WAY_D0_Pos (28UL)            /*!< Position of D0 field.                                                */
11934   #define CACHEINFO_SET_WAY_D0_Msk (0x1UL << CACHEINFO_SET_WAY_D0_Pos) /*!< Bit mask of D0 field.                              */
11935   #define CACHEINFO_SET_WAY_D0_Min (0x0UL)           /*!< Min enumerator value of D0 field.                                    */
11936   #define CACHEINFO_SET_WAY_D0_Max (0x1UL)           /*!< Max enumerator value of D0 field.                                    */
11937   #define CACHEINFO_SET_WAY_D0_Clean (0x0UL)         /*!< Clean data unit                                                      */
11938   #define CACHEINFO_SET_WAY_D0_Dirty (0x1UL)         /*!< Dirty data unit                                                      */
11939 
11940 /* D1 @Bit 29 : Dirty data unit 1. */
11941   #define CACHEINFO_SET_WAY_D1_Pos (29UL)            /*!< Position of D1 field.                                                */
11942   #define CACHEINFO_SET_WAY_D1_Msk (0x1UL << CACHEINFO_SET_WAY_D1_Pos) /*!< Bit mask of D1 field.                              */
11943   #define CACHEINFO_SET_WAY_D1_Min (0x0UL)           /*!< Min enumerator value of D1 field.                                    */
11944   #define CACHEINFO_SET_WAY_D1_Max (0x1UL)           /*!< Max enumerator value of D1 field.                                    */
11945   #define CACHEINFO_SET_WAY_D1_Clean (0x0UL)         /*!< Clean data unit                                                      */
11946   #define CACHEINFO_SET_WAY_D1_Dirty (0x1UL)         /*!< Dirty data unit                                                      */
11947 
11948 /* V @Bit 30 : Line valid bit. */
11949   #define CACHEINFO_SET_WAY_V_Pos (30UL)             /*!< Position of V field.                                                 */
11950   #define CACHEINFO_SET_WAY_V_Msk (0x1UL << CACHEINFO_SET_WAY_V_Pos) /*!< Bit mask of V field.                                 */
11951   #define CACHEINFO_SET_WAY_V_Min (0x0UL)            /*!< Min enumerator value of V field.                                     */
11952   #define CACHEINFO_SET_WAY_V_Max (0x1UL)            /*!< Max enumerator value of V field.                                     */
11953   #define CACHEINFO_SET_WAY_V_Invalid (0x0UL)        /*!< Invalid cache line                                                   */
11954   #define CACHEINFO_SET_WAY_V_Valid (0x1UL)          /*!< Valid cache line                                                     */
11955 
11956 /* MRU @Bit 31 : Most recently used way. */
11957   #define CACHEINFO_SET_WAY_MRU_Pos (31UL)           /*!< Position of MRU field.                                               */
11958   #define CACHEINFO_SET_WAY_MRU_Msk (0x1UL << CACHEINFO_SET_WAY_MRU_Pos) /*!< Bit mask of MRU field.                           */
11959   #define CACHEINFO_SET_WAY_MRU_Min (0x0UL)          /*!< Min enumerator value of MRU field.                                   */
11960   #define CACHEINFO_SET_WAY_MRU_Max (0x1UL)          /*!< Max enumerator value of MRU field.                                   */
11961   #define CACHEINFO_SET_WAY_MRU_Way0 (0x0UL)         /*!< Way0 was most recently used                                          */
11962   #define CACHEINFO_SET_WAY_MRU_Way1 (0x1UL)         /*!< Way1 was most recently used                                          */
11963 
11964 
11965 /* ==================================================== Struct CACHEINFO ===================================================== */
11966 /**
11967   * @brief CACHEINFO
11968   */
11969   typedef struct {                                   /*!< CACHEINFO Structure                                                  */
11970     __IOM NRF_CACHEINFO_SET_Type SET[256];           /*!< (@ 0x00000000) (unspecified)                                         */
11971   } NRF_CACHEINFO_Type;                              /*!< Size = 2048 (0x800)                                                  */
11972 
11973 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
11974 
11975 /* =========================================================================================================================== */
11976 /* ================                                            CAN                                            ================ */
11977 /* =========================================================================================================================== */
11978 
11979 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
11980 /* ======================================================= Struct CAN ======================================================== */
11981 /**
11982   * @brief Controller Area Network
11983   */
11984   typedef struct {                                   /*!< CAN Structure                                                        */
11985     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start the CAN peripheral.                             */
11986     __OM uint32_t TASKS_STOPREQ;                     /*!< (@ 0x00000004) Request to stop the CAN peripheral                    */
11987     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000008) Stop the CAN peripheral                               */
11988     __IM uint32_t RESERVED[61];
11989     __IOM uint32_t EVENTS_CORE[2];                   /*!< (@ 0x00000100) Event indicating that interrupt n triggered at CAN
11990                                                                          core*/
11991     __IOM uint32_t EVENTS_DMU;                       /*!< (@ 0x00000108) Event indicating that interrupt triggered at CAN DMU  */
11992     __IOM uint32_t EVENTS_DMA;                       /*!< (@ 0x0000010C) Event indicating that interrupt triggered at CAN DMA  */
11993     __IOM uint32_t EVENTS_READYFORSTOP;              /*!< (@ 0x00000110) Event indicating that the CAN is ready to be stopped  */
11994     __IM uint32_t RESERVED1[59];
11995     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
11996     __IM uint32_t RESERVED2[63];
11997     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
11998     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
11999     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
12000     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
12001   } NRF_CAN_Type;                                    /*!< Size = 784 (0x310)                                                   */
12002 
12003 /* CAN_TASKS_START: Start the CAN peripheral. */
12004   #define CAN_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
12005 
12006 /* TASKS_START @Bit 0 : Start the CAN peripheral. */
12007   #define CAN_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
12008   #define CAN_TASKS_START_TASKS_START_Msk (0x1UL << CAN_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
12009   #define CAN_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
12010   #define CAN_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
12011   #define CAN_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
12012 
12013 
12014 /* CAN_TASKS_STOPREQ: Request to stop the CAN peripheral */
12015   #define CAN_TASKS_STOPREQ_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPREQ register.                              */
12016 
12017 /* TASKS_STOPREQ @Bit 0 : Request to stop the CAN peripheral */
12018   #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Pos (0UL)  /*!< Position of TASKS_STOPREQ field.                                     */
12019   #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Msk (0x1UL << CAN_TASKS_STOPREQ_TASKS_STOPREQ_Pos) /*!< Bit mask of TASKS_STOPREQ
12020                                                                             field.*/
12021   #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPREQ field.                        */
12022   #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPREQ field.                        */
12023   #define CAN_TASKS_STOPREQ_TASKS_STOPREQ_Trigger (0x1UL) /*!< Trigger task                                                    */
12024 
12025 
12026 /* CAN_TASKS_STOP: Stop the CAN peripheral */
12027   #define CAN_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
12028 
12029 /* TASKS_STOP @Bit 0 : Stop the CAN peripheral */
12030   #define CAN_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
12031   #define CAN_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CAN_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
12032   #define CAN_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
12033   #define CAN_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
12034   #define CAN_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
12035 
12036 
12037 /* CAN_EVENTS_CORE: Event indicating that interrupt n triggered at CAN core */
12038   #define CAN_EVENTS_CORE_MaxCount (2UL)             /*!< Max size of EVENTS_CORE[2] array.                                    */
12039   #define CAN_EVENTS_CORE_MaxIndex (1UL)             /*!< Max index of EVENTS_CORE[2] array.                                   */
12040   #define CAN_EVENTS_CORE_MinIndex (0UL)             /*!< Min index of EVENTS_CORE[2] array.                                   */
12041   #define CAN_EVENTS_CORE_ResetValue (0x00000000UL)  /*!< Reset value of EVENTS_CORE[2] register.                              */
12042 
12043 /* EVENTS_CORE @Bit 0 : Event indicating that interrupt n triggered at CAN core */
12044   #define CAN_EVENTS_CORE_EVENTS_CORE_Pos (0UL)      /*!< Position of EVENTS_CORE field.                                       */
12045   #define CAN_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << CAN_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field.       */
12046   #define CAN_EVENTS_CORE_EVENTS_CORE_Min (0x0UL)    /*!< Min enumerator value of EVENTS_CORE field.                           */
12047   #define CAN_EVENTS_CORE_EVENTS_CORE_Max (0x1UL)    /*!< Max enumerator value of EVENTS_CORE field.                           */
12048   #define CAN_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL) /*!< Event not generated                                            */
12049   #define CAN_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL) /*!< Event generated                                                   */
12050 
12051 
12052 /* CAN_EVENTS_DMU: Event indicating that interrupt triggered at CAN DMU */
12053   #define CAN_EVENTS_DMU_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_DMU register.                                  */
12054 
12055 /* EVENTS_DMU @Bit 0 : Event indicating that interrupt triggered at CAN DMU */
12056   #define CAN_EVENTS_DMU_EVENTS_DMU_Pos (0UL)        /*!< Position of EVENTS_DMU field.                                        */
12057   #define CAN_EVENTS_DMU_EVENTS_DMU_Msk (0x1UL << CAN_EVENTS_DMU_EVENTS_DMU_Pos) /*!< Bit mask of EVENTS_DMU field.            */
12058   #define CAN_EVENTS_DMU_EVENTS_DMU_Min (0x0UL)      /*!< Min enumerator value of EVENTS_DMU field.                            */
12059   #define CAN_EVENTS_DMU_EVENTS_DMU_Max (0x1UL)      /*!< Max enumerator value of EVENTS_DMU field.                            */
12060   #define CAN_EVENTS_DMU_EVENTS_DMU_NotGenerated (0x0UL) /*!< Event not generated                                              */
12061   #define CAN_EVENTS_DMU_EVENTS_DMU_Generated (0x1UL) /*!< Event generated                                                     */
12062 
12063 
12064 /* CAN_EVENTS_DMA: Event indicating that interrupt triggered at CAN DMA */
12065   #define CAN_EVENTS_DMA_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_DMA register.                                  */
12066 
12067 /* EVENTS_DMA @Bit 0 : Event indicating that interrupt triggered at CAN DMA */
12068   #define CAN_EVENTS_DMA_EVENTS_DMA_Pos (0UL)        /*!< Position of EVENTS_DMA field.                                        */
12069   #define CAN_EVENTS_DMA_EVENTS_DMA_Msk (0x1UL << CAN_EVENTS_DMA_EVENTS_DMA_Pos) /*!< Bit mask of EVENTS_DMA field.            */
12070   #define CAN_EVENTS_DMA_EVENTS_DMA_Min (0x0UL)      /*!< Min enumerator value of EVENTS_DMA field.                            */
12071   #define CAN_EVENTS_DMA_EVENTS_DMA_Max (0x1UL)      /*!< Max enumerator value of EVENTS_DMA field.                            */
12072   #define CAN_EVENTS_DMA_EVENTS_DMA_NotGenerated (0x0UL) /*!< Event not generated                                              */
12073   #define CAN_EVENTS_DMA_EVENTS_DMA_Generated (0x1UL) /*!< Event generated                                                     */
12074 
12075 
12076 /* CAN_EVENTS_READYFORSTOP: Event indicating that the CAN is ready to be stopped */
12077   #define CAN_EVENTS_READYFORSTOP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READYFORSTOP register.                  */
12078 
12079 /* EVENTS_READYFORSTOP @Bit 0 : Event indicating that the CAN is ready to be stopped */
12080   #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Pos (0UL) /*!< Position of EVENTS_READYFORSTOP field.                    */
12081   #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Msk (0x1UL << CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Pos) /*!< Bit
12082                                                                             mask of EVENTS_READYFORSTOP field.*/
12083   #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Min (0x0UL) /*!< Min enumerator value of EVENTS_READYFORSTOP field.      */
12084   #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Max (0x1UL) /*!< Max enumerator value of EVENTS_READYFORSTOP field.      */
12085   #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_NotGenerated (0x0UL) /*!< Event not generated                            */
12086   #define CAN_EVENTS_READYFORSTOP_EVENTS_READYFORSTOP_Generated (0x1UL) /*!< Event generated                                   */
12087 
12088 
12089 /* CAN_SHORTS: Shortcuts between local events and tasks */
12090   #define CAN_SHORTS_ResetValue (0x00000000UL)       /*!< Reset value of SHORTS register.                                      */
12091 
12092 /* READYFORSTOP_STOP @Bit 0 : Shortcut between event READYFORSTOP and task STOP */
12093   #define CAN_SHORTS_READYFORSTOP_STOP_Pos (0UL)     /*!< Position of READYFORSTOP_STOP field.                                 */
12094   #define CAN_SHORTS_READYFORSTOP_STOP_Msk (0x1UL << CAN_SHORTS_READYFORSTOP_STOP_Pos) /*!< Bit mask of READYFORSTOP_STOP
12095                                                                             field.*/
12096   #define CAN_SHORTS_READYFORSTOP_STOP_Min (0x0UL)   /*!< Min enumerator value of READYFORSTOP_STOP field.                     */
12097   #define CAN_SHORTS_READYFORSTOP_STOP_Max (0x1UL)   /*!< Max enumerator value of READYFORSTOP_STOP field.                     */
12098   #define CAN_SHORTS_READYFORSTOP_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                  */
12099   #define CAN_SHORTS_READYFORSTOP_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                    */
12100 
12101 
12102 /* CAN_INTEN: Enable or disable interrupt */
12103   #define CAN_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
12104 
12105 /* CORE0 @Bit 0 : Enable or disable interrupt for event CORE[0] */
12106   #define CAN_INTEN_CORE0_Pos (0UL)                  /*!< Position of CORE0 field.                                             */
12107   #define CAN_INTEN_CORE0_Msk (0x1UL << CAN_INTEN_CORE0_Pos) /*!< Bit mask of CORE0 field.                                     */
12108   #define CAN_INTEN_CORE0_Min (0x0UL)                /*!< Min enumerator value of CORE0 field.                                 */
12109   #define CAN_INTEN_CORE0_Max (0x1UL)                /*!< Max enumerator value of CORE0 field.                                 */
12110   #define CAN_INTEN_CORE0_Disabled (0x0UL)           /*!< Disable                                                              */
12111   #define CAN_INTEN_CORE0_Enabled (0x1UL)            /*!< Enable                                                               */
12112 
12113 /* CORE1 @Bit 1 : Enable or disable interrupt for event CORE[1] */
12114   #define CAN_INTEN_CORE1_Pos (1UL)                  /*!< Position of CORE1 field.                                             */
12115   #define CAN_INTEN_CORE1_Msk (0x1UL << CAN_INTEN_CORE1_Pos) /*!< Bit mask of CORE1 field.                                     */
12116   #define CAN_INTEN_CORE1_Min (0x0UL)                /*!< Min enumerator value of CORE1 field.                                 */
12117   #define CAN_INTEN_CORE1_Max (0x1UL)                /*!< Max enumerator value of CORE1 field.                                 */
12118   #define CAN_INTEN_CORE1_Disabled (0x0UL)           /*!< Disable                                                              */
12119   #define CAN_INTEN_CORE1_Enabled (0x1UL)            /*!< Enable                                                               */
12120 
12121 /* DMU @Bit 2 : Enable or disable interrupt for event DMU */
12122   #define CAN_INTEN_DMU_Pos (2UL)                    /*!< Position of DMU field.                                               */
12123   #define CAN_INTEN_DMU_Msk (0x1UL << CAN_INTEN_DMU_Pos) /*!< Bit mask of DMU field.                                           */
12124   #define CAN_INTEN_DMU_Min (0x0UL)                  /*!< Min enumerator value of DMU field.                                   */
12125   #define CAN_INTEN_DMU_Max (0x1UL)                  /*!< Max enumerator value of DMU field.                                   */
12126   #define CAN_INTEN_DMU_Disabled (0x0UL)             /*!< Disable                                                              */
12127   #define CAN_INTEN_DMU_Enabled (0x1UL)              /*!< Enable                                                               */
12128 
12129 /* DMA @Bit 3 : Enable or disable interrupt for event DMA */
12130   #define CAN_INTEN_DMA_Pos (3UL)                    /*!< Position of DMA field.                                               */
12131   #define CAN_INTEN_DMA_Msk (0x1UL << CAN_INTEN_DMA_Pos) /*!< Bit mask of DMA field.                                           */
12132   #define CAN_INTEN_DMA_Min (0x0UL)                  /*!< Min enumerator value of DMA field.                                   */
12133   #define CAN_INTEN_DMA_Max (0x1UL)                  /*!< Max enumerator value of DMA field.                                   */
12134   #define CAN_INTEN_DMA_Disabled (0x0UL)             /*!< Disable                                                              */
12135   #define CAN_INTEN_DMA_Enabled (0x1UL)              /*!< Enable                                                               */
12136 
12137 /* READYFORSTOP @Bit 4 : Enable or disable interrupt for event READYFORSTOP */
12138   #define CAN_INTEN_READYFORSTOP_Pos (4UL)           /*!< Position of READYFORSTOP field.                                      */
12139   #define CAN_INTEN_READYFORSTOP_Msk (0x1UL << CAN_INTEN_READYFORSTOP_Pos) /*!< Bit mask of READYFORSTOP field.                */
12140   #define CAN_INTEN_READYFORSTOP_Min (0x0UL)         /*!< Min enumerator value of READYFORSTOP field.                          */
12141   #define CAN_INTEN_READYFORSTOP_Max (0x1UL)         /*!< Max enumerator value of READYFORSTOP field.                          */
12142   #define CAN_INTEN_READYFORSTOP_Disabled (0x0UL)    /*!< Disable                                                              */
12143   #define CAN_INTEN_READYFORSTOP_Enabled (0x1UL)     /*!< Enable                                                               */
12144 
12145 
12146 /* CAN_INTENSET: Enable interrupt */
12147   #define CAN_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
12148 
12149 /* CORE0 @Bit 0 : Write '1' to enable interrupt for event CORE[0] */
12150   #define CAN_INTENSET_CORE0_Pos (0UL)               /*!< Position of CORE0 field.                                             */
12151   #define CAN_INTENSET_CORE0_Msk (0x1UL << CAN_INTENSET_CORE0_Pos) /*!< Bit mask of CORE0 field.                               */
12152   #define CAN_INTENSET_CORE0_Min (0x0UL)             /*!< Min enumerator value of CORE0 field.                                 */
12153   #define CAN_INTENSET_CORE0_Max (0x1UL)             /*!< Max enumerator value of CORE0 field.                                 */
12154   #define CAN_INTENSET_CORE0_Set (0x1UL)             /*!< Enable                                                               */
12155   #define CAN_INTENSET_CORE0_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
12156   #define CAN_INTENSET_CORE0_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
12157 
12158 /* CORE1 @Bit 1 : Write '1' to enable interrupt for event CORE[1] */
12159   #define CAN_INTENSET_CORE1_Pos (1UL)               /*!< Position of CORE1 field.                                             */
12160   #define CAN_INTENSET_CORE1_Msk (0x1UL << CAN_INTENSET_CORE1_Pos) /*!< Bit mask of CORE1 field.                               */
12161   #define CAN_INTENSET_CORE1_Min (0x0UL)             /*!< Min enumerator value of CORE1 field.                                 */
12162   #define CAN_INTENSET_CORE1_Max (0x1UL)             /*!< Max enumerator value of CORE1 field.                                 */
12163   #define CAN_INTENSET_CORE1_Set (0x1UL)             /*!< Enable                                                               */
12164   #define CAN_INTENSET_CORE1_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
12165   #define CAN_INTENSET_CORE1_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
12166 
12167 /* DMU @Bit 2 : Write '1' to enable interrupt for event DMU */
12168   #define CAN_INTENSET_DMU_Pos (2UL)                 /*!< Position of DMU field.                                               */
12169   #define CAN_INTENSET_DMU_Msk (0x1UL << CAN_INTENSET_DMU_Pos) /*!< Bit mask of DMU field.                                     */
12170   #define CAN_INTENSET_DMU_Min (0x0UL)               /*!< Min enumerator value of DMU field.                                   */
12171   #define CAN_INTENSET_DMU_Max (0x1UL)               /*!< Max enumerator value of DMU field.                                   */
12172   #define CAN_INTENSET_DMU_Set (0x1UL)               /*!< Enable                                                               */
12173   #define CAN_INTENSET_DMU_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
12174   #define CAN_INTENSET_DMU_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
12175 
12176 /* DMA @Bit 3 : Write '1' to enable interrupt for event DMA */
12177   #define CAN_INTENSET_DMA_Pos (3UL)                 /*!< Position of DMA field.                                               */
12178   #define CAN_INTENSET_DMA_Msk (0x1UL << CAN_INTENSET_DMA_Pos) /*!< Bit mask of DMA field.                                     */
12179   #define CAN_INTENSET_DMA_Min (0x0UL)               /*!< Min enumerator value of DMA field.                                   */
12180   #define CAN_INTENSET_DMA_Max (0x1UL)               /*!< Max enumerator value of DMA field.                                   */
12181   #define CAN_INTENSET_DMA_Set (0x1UL)               /*!< Enable                                                               */
12182   #define CAN_INTENSET_DMA_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
12183   #define CAN_INTENSET_DMA_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
12184 
12185 /* READYFORSTOP @Bit 4 : Write '1' to enable interrupt for event READYFORSTOP */
12186   #define CAN_INTENSET_READYFORSTOP_Pos (4UL)        /*!< Position of READYFORSTOP field.                                      */
12187   #define CAN_INTENSET_READYFORSTOP_Msk (0x1UL << CAN_INTENSET_READYFORSTOP_Pos) /*!< Bit mask of READYFORSTOP field.          */
12188   #define CAN_INTENSET_READYFORSTOP_Min (0x0UL)      /*!< Min enumerator value of READYFORSTOP field.                          */
12189   #define CAN_INTENSET_READYFORSTOP_Max (0x1UL)      /*!< Max enumerator value of READYFORSTOP field.                          */
12190   #define CAN_INTENSET_READYFORSTOP_Set (0x1UL)      /*!< Enable                                                               */
12191   #define CAN_INTENSET_READYFORSTOP_Disabled (0x0UL) /*!< Read: Disabled                                                       */
12192   #define CAN_INTENSET_READYFORSTOP_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
12193 
12194 
12195 /* CAN_INTENCLR: Disable interrupt */
12196   #define CAN_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
12197 
12198 /* CORE0 @Bit 0 : Write '1' to disable interrupt for event CORE[0] */
12199   #define CAN_INTENCLR_CORE0_Pos (0UL)               /*!< Position of CORE0 field.                                             */
12200   #define CAN_INTENCLR_CORE0_Msk (0x1UL << CAN_INTENCLR_CORE0_Pos) /*!< Bit mask of CORE0 field.                               */
12201   #define CAN_INTENCLR_CORE0_Min (0x0UL)             /*!< Min enumerator value of CORE0 field.                                 */
12202   #define CAN_INTENCLR_CORE0_Max (0x1UL)             /*!< Max enumerator value of CORE0 field.                                 */
12203   #define CAN_INTENCLR_CORE0_Clear (0x1UL)           /*!< Disable                                                              */
12204   #define CAN_INTENCLR_CORE0_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
12205   #define CAN_INTENCLR_CORE0_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
12206 
12207 /* CORE1 @Bit 1 : Write '1' to disable interrupt for event CORE[1] */
12208   #define CAN_INTENCLR_CORE1_Pos (1UL)               /*!< Position of CORE1 field.                                             */
12209   #define CAN_INTENCLR_CORE1_Msk (0x1UL << CAN_INTENCLR_CORE1_Pos) /*!< Bit mask of CORE1 field.                               */
12210   #define CAN_INTENCLR_CORE1_Min (0x0UL)             /*!< Min enumerator value of CORE1 field.                                 */
12211   #define CAN_INTENCLR_CORE1_Max (0x1UL)             /*!< Max enumerator value of CORE1 field.                                 */
12212   #define CAN_INTENCLR_CORE1_Clear (0x1UL)           /*!< Disable                                                              */
12213   #define CAN_INTENCLR_CORE1_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
12214   #define CAN_INTENCLR_CORE1_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
12215 
12216 /* DMU @Bit 2 : Write '1' to disable interrupt for event DMU */
12217   #define CAN_INTENCLR_DMU_Pos (2UL)                 /*!< Position of DMU field.                                               */
12218   #define CAN_INTENCLR_DMU_Msk (0x1UL << CAN_INTENCLR_DMU_Pos) /*!< Bit mask of DMU field.                                     */
12219   #define CAN_INTENCLR_DMU_Min (0x0UL)               /*!< Min enumerator value of DMU field.                                   */
12220   #define CAN_INTENCLR_DMU_Max (0x1UL)               /*!< Max enumerator value of DMU field.                                   */
12221   #define CAN_INTENCLR_DMU_Clear (0x1UL)             /*!< Disable                                                              */
12222   #define CAN_INTENCLR_DMU_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
12223   #define CAN_INTENCLR_DMU_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
12224 
12225 /* DMA @Bit 3 : Write '1' to disable interrupt for event DMA */
12226   #define CAN_INTENCLR_DMA_Pos (3UL)                 /*!< Position of DMA field.                                               */
12227   #define CAN_INTENCLR_DMA_Msk (0x1UL << CAN_INTENCLR_DMA_Pos) /*!< Bit mask of DMA field.                                     */
12228   #define CAN_INTENCLR_DMA_Min (0x0UL)               /*!< Min enumerator value of DMA field.                                   */
12229   #define CAN_INTENCLR_DMA_Max (0x1UL)               /*!< Max enumerator value of DMA field.                                   */
12230   #define CAN_INTENCLR_DMA_Clear (0x1UL)             /*!< Disable                                                              */
12231   #define CAN_INTENCLR_DMA_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
12232   #define CAN_INTENCLR_DMA_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
12233 
12234 /* READYFORSTOP @Bit 4 : Write '1' to disable interrupt for event READYFORSTOP */
12235   #define CAN_INTENCLR_READYFORSTOP_Pos (4UL)        /*!< Position of READYFORSTOP field.                                      */
12236   #define CAN_INTENCLR_READYFORSTOP_Msk (0x1UL << CAN_INTENCLR_READYFORSTOP_Pos) /*!< Bit mask of READYFORSTOP field.          */
12237   #define CAN_INTENCLR_READYFORSTOP_Min (0x0UL)      /*!< Min enumerator value of READYFORSTOP field.                          */
12238   #define CAN_INTENCLR_READYFORSTOP_Max (0x1UL)      /*!< Max enumerator value of READYFORSTOP field.                          */
12239   #define CAN_INTENCLR_READYFORSTOP_Clear (0x1UL)    /*!< Disable                                                              */
12240   #define CAN_INTENCLR_READYFORSTOP_Disabled (0x0UL) /*!< Read: Disabled                                                       */
12241   #define CAN_INTENCLR_READYFORSTOP_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
12242 
12243 
12244 /* CAN_INTPEND: Pending interrupts */
12245   #define CAN_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */
12246 
12247 /* CORE0 @Bit 0 : Read pending status of interrupt for event CORE[0] */
12248   #define CAN_INTPEND_CORE0_Pos (0UL)                /*!< Position of CORE0 field.                                             */
12249   #define CAN_INTPEND_CORE0_Msk (0x1UL << CAN_INTPEND_CORE0_Pos) /*!< Bit mask of CORE0 field.                                 */
12250   #define CAN_INTPEND_CORE0_Min (0x0UL)              /*!< Min enumerator value of CORE0 field.                                 */
12251   #define CAN_INTPEND_CORE0_Max (0x1UL)              /*!< Max enumerator value of CORE0 field.                                 */
12252   #define CAN_INTPEND_CORE0_NotPending (0x0UL)       /*!< Read: Not pending                                                    */
12253   #define CAN_INTPEND_CORE0_Pending (0x1UL)          /*!< Read: Pending                                                        */
12254 
12255 /* CORE1 @Bit 1 : Read pending status of interrupt for event CORE[1] */
12256   #define CAN_INTPEND_CORE1_Pos (1UL)                /*!< Position of CORE1 field.                                             */
12257   #define CAN_INTPEND_CORE1_Msk (0x1UL << CAN_INTPEND_CORE1_Pos) /*!< Bit mask of CORE1 field.                                 */
12258   #define CAN_INTPEND_CORE1_Min (0x0UL)              /*!< Min enumerator value of CORE1 field.                                 */
12259   #define CAN_INTPEND_CORE1_Max (0x1UL)              /*!< Max enumerator value of CORE1 field.                                 */
12260   #define CAN_INTPEND_CORE1_NotPending (0x0UL)       /*!< Read: Not pending                                                    */
12261   #define CAN_INTPEND_CORE1_Pending (0x1UL)          /*!< Read: Pending                                                        */
12262 
12263 /* DMU @Bit 2 : Read pending status of interrupt for event DMU */
12264   #define CAN_INTPEND_DMU_Pos (2UL)                  /*!< Position of DMU field.                                               */
12265   #define CAN_INTPEND_DMU_Msk (0x1UL << CAN_INTPEND_DMU_Pos) /*!< Bit mask of DMU field.                                       */
12266   #define CAN_INTPEND_DMU_Min (0x0UL)                /*!< Min enumerator value of DMU field.                                   */
12267   #define CAN_INTPEND_DMU_Max (0x1UL)                /*!< Max enumerator value of DMU field.                                   */
12268   #define CAN_INTPEND_DMU_NotPending (0x0UL)         /*!< Read: Not pending                                                    */
12269   #define CAN_INTPEND_DMU_Pending (0x1UL)            /*!< Read: Pending                                                        */
12270 
12271 /* DMA @Bit 3 : Read pending status of interrupt for event DMA */
12272   #define CAN_INTPEND_DMA_Pos (3UL)                  /*!< Position of DMA field.                                               */
12273   #define CAN_INTPEND_DMA_Msk (0x1UL << CAN_INTPEND_DMA_Pos) /*!< Bit mask of DMA field.                                       */
12274   #define CAN_INTPEND_DMA_Min (0x0UL)                /*!< Min enumerator value of DMA field.                                   */
12275   #define CAN_INTPEND_DMA_Max (0x1UL)                /*!< Max enumerator value of DMA field.                                   */
12276   #define CAN_INTPEND_DMA_NotPending (0x0UL)         /*!< Read: Not pending                                                    */
12277   #define CAN_INTPEND_DMA_Pending (0x1UL)            /*!< Read: Pending                                                        */
12278 
12279 /* READYFORSTOP @Bit 4 : Read pending status of interrupt for event READYFORSTOP */
12280   #define CAN_INTPEND_READYFORSTOP_Pos (4UL)         /*!< Position of READYFORSTOP field.                                      */
12281   #define CAN_INTPEND_READYFORSTOP_Msk (0x1UL << CAN_INTPEND_READYFORSTOP_Pos) /*!< Bit mask of READYFORSTOP field.            */
12282   #define CAN_INTPEND_READYFORSTOP_Min (0x0UL)       /*!< Min enumerator value of READYFORSTOP field.                          */
12283   #define CAN_INTPEND_READYFORSTOP_Max (0x1UL)       /*!< Max enumerator value of READYFORSTOP field.                          */
12284   #define CAN_INTPEND_READYFORSTOP_NotPending (0x0UL) /*!< Read: Not pending                                                   */
12285   #define CAN_INTPEND_READYFORSTOP_Pending (0x1UL)   /*!< Read: Pending                                                        */
12286 
12287 
12288 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
12289 
12290 /* =========================================================================================================================== */
12291 /* ================                                            CCM                                            ================ */
12292 /* =========================================================================================================================== */
12293 
12294 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
12295 
12296 /* ===================================================== Struct CCM_KEY ====================================================== */
12297 /**
12298   * @brief KEY [CCM_KEY] (unspecified)
12299   */
12300 typedef struct {
12301   __OM  uint32_t  VALUE[4];                          /*!< (@ 0x00000000) 128-bit AES key                                       */
12302 } NRF_CCM_KEY_Type;                                  /*!< Size = 16 (0x010)                                                    */
12303 
12304 /* CCM_KEY_VALUE: 128-bit AES key */
12305   #define CCM_KEY_VALUE_MaxCount (4UL)               /*!< Max size of VALUE[4] array.                                          */
12306   #define CCM_KEY_VALUE_MaxIndex (3UL)               /*!< Max index of VALUE[4] array.                                         */
12307   #define CCM_KEY_VALUE_MinIndex (0UL)               /*!< Min index of VALUE[4] array.                                         */
12308   #define CCM_KEY_VALUE_ResetValue (0x00000000UL)    /*!< Reset value of VALUE[4] register.                                    */
12309 
12310 /* VALUE @Bits 0..31 : AES 128-bit key value, bits (32*(i+1))-1 : (32*i) */
12311   #define CCM_KEY_VALUE_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
12312   #define CCM_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << CCM_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field.                      */
12313 
12314 
12315 
12316 /* ==================================================== Struct CCM_NONCE ===================================================== */
12317 /**
12318   * @brief NONCE [CCM_NONCE] (unspecified)
12319   */
12320 typedef struct {
12321   __IOM uint32_t  VALUE[4];                          /*!< (@ 0x00000000) 13-byte NONCE vector Only the lower 13 bytes are used */
12322 } NRF_CCM_NONCE_Type;                                /*!< Size = 16 (0x010)                                                    */
12323 
12324 /* CCM_NONCE_VALUE: 13-byte NONCE vector Only the lower 13 bytes are used */
12325   #define CCM_NONCE_VALUE_MaxCount (4UL)             /*!< Max size of VALUE[4] array.                                          */
12326   #define CCM_NONCE_VALUE_MaxIndex (3UL)             /*!< Max index of VALUE[4] array.                                         */
12327   #define CCM_NONCE_VALUE_MinIndex (0UL)             /*!< Min index of VALUE[4] array.                                         */
12328   #define CCM_NONCE_VALUE_ResetValue (0x00000000UL)  /*!< Reset value of VALUE[4] register.                                    */
12329 
12330 /* VALUE @Bits 0..31 : NONCE value, bits (32*(n+1))-1 : (32*n) */
12331   #define CCM_NONCE_VALUE_VALUE_Pos (0UL)            /*!< Position of VALUE field.                                             */
12332   #define CCM_NONCE_VALUE_VALUE_Msk (0xFFFFFFFFUL << CCM_NONCE_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field.                  */
12333 
12334 
12335 
12336 /* ====================================================== Struct CCM_IN ====================================================== */
12337 /**
12338   * @brief IN [CCM_IN] IN EasyDMA channel
12339   */
12340 typedef struct {
12341   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Input pointer Points to a job list containing
12342                                                                          unencrypted CCM data structure in Encryption mode
12343                                                                          Points to a job list containing encrypted CCM data
12344                                                                          structure in Decryption mode*/
12345   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Number of bytes read from the input data, not including
12346                                                                          the job list structure*/
12347 } NRF_CCM_IN_Type;                                   /*!< Size = 8 (0x008)                                                     */
12348 
12349 /* CCM_IN_PTR: Input pointer Points to a job list containing unencrypted CCM data structure in Encryption mode Points to a job
12350                 list containing encrypted CCM data structure in Decryption mode */
12351 
12352   #define CCM_IN_PTR_ResetValue (0x00000000UL)       /*!< Reset value of PTR register.                                         */
12353 
12354 /* PTR @Bits 0..31 : Input pointer */
12355   #define CCM_IN_PTR_PTR_Pos (0UL)                   /*!< Position of PTR field.                                               */
12356   #define CCM_IN_PTR_PTR_Msk (0xFFFFFFFFUL << CCM_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                  */
12357 
12358 
12359 /* CCM_IN_AMOUNT: Number of bytes read from the input data, not including the job list structure */
12360   #define CCM_IN_AMOUNT_ResetValue (0x00000000UL)    /*!< Reset value of AMOUNT register.                                      */
12361 
12362 /* AMOUNT @Bits 0..31 : Number of bytes read from the input data */
12363   #define CCM_IN_AMOUNT_AMOUNT_Pos (0UL)             /*!< Position of AMOUNT field.                                            */
12364   #define CCM_IN_AMOUNT_AMOUNT_Msk (0xFFFFFFFFUL << CCM_IN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
12365 
12366 
12367 
12368 /* ===================================================== Struct CCM_OUT ====================================================== */
12369 /**
12370   * @brief OUT [CCM_OUT] OUT EasyDMA channel
12371   */
12372 typedef struct {
12373   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Output pointer Points to a job list containing
12374                                                                          encrypted CCM data structure in Encryption mode Points
12375                                                                          to a job list containing decrypted CCM data structure
12376                                                                          in Decryption mode*/
12377   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Number of bytes available in the output data, not
12378                                                                          including the job list structure*/
12379 } NRF_CCM_OUT_Type;                                  /*!< Size = 8 (0x008)                                                     */
12380 
12381 /* CCM_OUT_PTR: Output pointer Points to a job list containing encrypted CCM data structure in Encryption mode Points to a job
12382                  list containing decrypted CCM data structure in Decryption mode */
12383 
12384   #define CCM_OUT_PTR_ResetValue (0x00000000UL)      /*!< Reset value of PTR register.                                         */
12385 
12386 /* PTR @Bits 0..31 : Output pointer */
12387   #define CCM_OUT_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
12388   #define CCM_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << CCM_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */
12389 
12390 
12391 /* CCM_OUT_AMOUNT: Number of bytes available in the output data, not including the job list structure */
12392   #define CCM_OUT_AMOUNT_ResetValue (0x00000000UL)   /*!< Reset value of AMOUNT register.                                      */
12393 
12394 /* AMOUNT @Bits 0..31 : Number of bytes available in the output data */
12395   #define CCM_OUT_AMOUNT_AMOUNT_Pos (0UL)            /*!< Position of AMOUNT field.                                            */
12396   #define CCM_OUT_AMOUNT_AMOUNT_Msk (0xFFFFFFFFUL << CCM_OUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                 */
12397 
12398 
12399 /* ======================================================= Struct CCM ======================================================== */
12400 /**
12401   * @brief AES CCM Mode Encryption
12402   */
12403   typedef struct {                                   /*!< CCM Structure                                                        */
12404     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start encryption/decryption. This operation will stop
12405                                                                          by itself when completed.*/
12406     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop encryption/decryption                            */
12407     __OM uint32_t TASKS_RATEOVERRIDE;                /*!< (@ 0x00000008) Override DATARATE setting in MODE register with the
12408                                                                          contents of the RATEOVERRIDE register for any ongoing
12409                                                                          encryption/decryption*/
12410     __IM uint32_t RESERVED[29];
12411     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
12412     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
12413     __IOM uint32_t SUBSCRIBE_RATEOVERRIDE;           /*!< (@ 0x00000088) Subscribe configuration for task RATEOVERRIDE         */
12414     __IM uint32_t RESERVED1[30];
12415     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000104) Encrypt/decrypt complete                              */
12416     __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000108) CCM error event                                       */
12417     __IM uint32_t RESERVED2[30];
12418     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000184) Publish configuration for event END                   */
12419     __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x00000188) Publish configuration for event ERROR                 */
12420     __IM uint32_t RESERVED3[94];
12421     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
12422     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
12423     __IM uint32_t RESERVED4[61];
12424     __IM uint32_t MACSTATUS;                         /*!< (@ 0x00000400) MAC check result                                      */
12425     __IM uint32_t ERRORSTATUS;                       /*!< (@ 0x00000404) Error status                                          */
12426     __IM uint32_t RESERVED5[62];
12427     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable                                                */
12428     __IOM uint32_t MODE;                             /*!< (@ 0x00000504) Operation mode                                        */
12429     __IM uint32_t RESERVED6[2];
12430     __IOM NRF_CCM_KEY_Type KEY;                      /*!< (@ 0x00000510) (unspecified)                                         */
12431     __IOM NRF_CCM_NONCE_Type NONCE;                  /*!< (@ 0x00000520) (unspecified)                                         */
12432     __IOM NRF_CCM_IN_Type IN;                        /*!< (@ 0x00000530) IN EasyDMA channel                                    */
12433     __IOM NRF_CCM_OUT_Type OUT;                      /*!< (@ 0x00000538) OUT EasyDMA channel                                   */
12434     __IM uint32_t RESERVED7;
12435     __IOM uint32_t RATEOVERRIDE;                     /*!< (@ 0x00000544) Data rate override setting.                           */
12436     __IOM uint32_t ADATAMASK;                        /*!< (@ 0x00000548) CCM adata mask.                                       */
12437   } NRF_CCM_Type;                                    /*!< Size = 1356 (0x54C)                                                  */
12438 
12439 /* CCM_TASKS_START: Start encryption/decryption. This operation will stop by itself when completed. */
12440   #define CCM_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
12441 
12442 /* TASKS_START @Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
12443   #define CCM_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
12444   #define CCM_TASKS_START_TASKS_START_Msk (0x1UL << CCM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
12445   #define CCM_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
12446   #define CCM_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
12447   #define CCM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
12448 
12449 
12450 /* CCM_TASKS_STOP: Stop encryption/decryption */
12451   #define CCM_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
12452 
12453 /* TASKS_STOP @Bit 0 : Stop encryption/decryption */
12454   #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
12455   #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
12456   #define CCM_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
12457   #define CCM_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
12458   #define CCM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
12459 
12460 
12461 /* CCM_TASKS_RATEOVERRIDE: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any
12462                             ongoing encryption/decryption */
12463 
12464   #define CCM_TASKS_RATEOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RATEOVERRIDE register.                    */
12465 
12466 /* TASKS_RATEOVERRIDE @Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any
12467                                ongoing encryption/decryption */
12468 
12469   #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field.                       */
12470   #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask
12471                                                                             of TASKS_RATEOVERRIDE field.*/
12472   #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Min (0x1UL) /*!< Min enumerator value of TASKS_RATEOVERRIDE field.         */
12473   #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Max (0x1UL) /*!< Max enumerator value of TASKS_RATEOVERRIDE field.         */
12474   #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (0x1UL) /*!< Trigger task                                          */
12475 
12476 
12477 /* CCM_SUBSCRIBE_START: Subscribe configuration for task START */
12478   #define CCM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */
12479 
12480 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
12481   #define CCM_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
12482   #define CCM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
12483   #define CCM_SUBSCRIBE_START_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
12484   #define CCM_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
12485 
12486 /* EN @Bit 31 : (unspecified) */
12487   #define CCM_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
12488   #define CCM_SUBSCRIBE_START_EN_Msk (0x1UL << CCM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
12489   #define CCM_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
12490   #define CCM_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
12491   #define CCM_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
12492   #define CCM_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
12493 
12494 
12495 /* CCM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
12496   #define CCM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */
12497 
12498 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
12499   #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
12500   #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
12501   #define CCM_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
12502   #define CCM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
12503 
12504 /* EN @Bit 31 : (unspecified) */
12505   #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
12506   #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
12507   #define CCM_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
12508   #define CCM_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
12509   #define CCM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
12510   #define CCM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
12511 
12512 
12513 /* CCM_SUBSCRIBE_RATEOVERRIDE: Subscribe configuration for task RATEOVERRIDE */
12514   #define CCM_SUBSCRIBE_RATEOVERRIDE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RATEOVERRIDE register.            */
12515 
12516 /* CHIDX @Bits 0..7 : DPPI channel that task RATEOVERRIDE will subscribe to */
12517   #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
12518   #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
12519   #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                          */
12520   #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */
12521 
12522 /* EN @Bit 31 : (unspecified) */
12523   #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL)   /*!< Position of EN field.                                                */
12524   #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field.            */
12525   #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
12526   #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
12527   #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0x0UL) /*!< Disable subscription                                             */
12528   #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (0x1UL) /*!< Enable subscription                                               */
12529 
12530 
12531 /* CCM_EVENTS_END: Encrypt/decrypt complete */
12532   #define CCM_EVENTS_END_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_END register.                                  */
12533 
12534 /* EVENTS_END @Bit 0 : Encrypt/decrypt complete */
12535   #define CCM_EVENTS_END_EVENTS_END_Pos (0UL)        /*!< Position of EVENTS_END field.                                        */
12536   #define CCM_EVENTS_END_EVENTS_END_Msk (0x1UL << CCM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.            */
12537   #define CCM_EVENTS_END_EVENTS_END_Min (0x0UL)      /*!< Min enumerator value of EVENTS_END field.                            */
12538   #define CCM_EVENTS_END_EVENTS_END_Max (0x1UL)      /*!< Max enumerator value of EVENTS_END field.                            */
12539   #define CCM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                              */
12540   #define CCM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                     */
12541 
12542 
12543 /* CCM_EVENTS_ERROR: CCM error event */
12544   #define CCM_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                                */
12545 
12546 /* EVENTS_ERROR @Bit 0 : CCM error event */
12547   #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)    /*!< Position of EVENTS_ERROR field.                                      */
12548   #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.  */
12549   #define CCM_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL)  /*!< Min enumerator value of EVENTS_ERROR field.                          */
12550   #define CCM_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL)  /*!< Max enumerator value of EVENTS_ERROR field.                          */
12551   #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                          */
12552   #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                 */
12553 
12554 
12555 /* CCM_PUBLISH_END: Publish configuration for event END */
12556   #define CCM_PUBLISH_END_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_END register.                                 */
12557 
12558 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
12559   #define CCM_PUBLISH_END_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
12560   #define CCM_PUBLISH_END_CHIDX_Msk (0xFFUL << CCM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
12561   #define CCM_PUBLISH_END_CHIDX_Min (0x0UL)          /*!< Min value of CHIDX field.                                            */
12562   #define CCM_PUBLISH_END_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */
12563 
12564 /* EN @Bit 31 : (unspecified) */
12565   #define CCM_PUBLISH_END_EN_Pos (31UL)              /*!< Position of EN field.                                                */
12566   #define CCM_PUBLISH_END_EN_Msk (0x1UL << CCM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                  */
12567   #define CCM_PUBLISH_END_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
12568   #define CCM_PUBLISH_END_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
12569   #define CCM_PUBLISH_END_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
12570   #define CCM_PUBLISH_END_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */
12571 
12572 
12573 /* CCM_PUBLISH_ERROR: Publish configuration for event ERROR */
12574   #define CCM_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                              */
12575 
12576 /* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
12577   #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
12578   #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
12579   #define CCM_PUBLISH_ERROR_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
12580   #define CCM_PUBLISH_ERROR_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
12581 
12582 /* EN @Bit 31 : (unspecified) */
12583   #define CCM_PUBLISH_ERROR_EN_Pos (31UL)            /*!< Position of EN field.                                                */
12584   #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                              */
12585   #define CCM_PUBLISH_ERROR_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
12586   #define CCM_PUBLISH_ERROR_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
12587   #define CCM_PUBLISH_ERROR_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
12588   #define CCM_PUBLISH_ERROR_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
12589 
12590 
12591 /* CCM_INTENSET: Enable interrupt */
12592   #define CCM_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
12593 
12594 /* END @Bit 1 : Write '1' to enable interrupt for event END */
12595   #define CCM_INTENSET_END_Pos (1UL)                 /*!< Position of END field.                                               */
12596   #define CCM_INTENSET_END_Msk (0x1UL << CCM_INTENSET_END_Pos) /*!< Bit mask of END field.                                     */
12597   #define CCM_INTENSET_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
12598   #define CCM_INTENSET_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
12599   #define CCM_INTENSET_END_Set (0x1UL)               /*!< Enable                                                               */
12600   #define CCM_INTENSET_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
12601   #define CCM_INTENSET_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
12602 
12603 /* ERROR @Bit 2 : Write '1' to enable interrupt for event ERROR */
12604   #define CCM_INTENSET_ERROR_Pos (2UL)               /*!< Position of ERROR field.                                             */
12605   #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
12606   #define CCM_INTENSET_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
12607   #define CCM_INTENSET_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
12608   #define CCM_INTENSET_ERROR_Set (0x1UL)             /*!< Enable                                                               */
12609   #define CCM_INTENSET_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
12610   #define CCM_INTENSET_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
12611 
12612 
12613 /* CCM_INTENCLR: Disable interrupt */
12614   #define CCM_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
12615 
12616 /* END @Bit 1 : Write '1' to disable interrupt for event END */
12617   #define CCM_INTENCLR_END_Pos (1UL)                 /*!< Position of END field.                                               */
12618   #define CCM_INTENCLR_END_Msk (0x1UL << CCM_INTENCLR_END_Pos) /*!< Bit mask of END field.                                     */
12619   #define CCM_INTENCLR_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
12620   #define CCM_INTENCLR_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
12621   #define CCM_INTENCLR_END_Clear (0x1UL)             /*!< Disable                                                              */
12622   #define CCM_INTENCLR_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
12623   #define CCM_INTENCLR_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
12624 
12625 /* ERROR @Bit 2 : Write '1' to disable interrupt for event ERROR */
12626   #define CCM_INTENCLR_ERROR_Pos (2UL)               /*!< Position of ERROR field.                                             */
12627   #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
12628   #define CCM_INTENCLR_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
12629   #define CCM_INTENCLR_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
12630   #define CCM_INTENCLR_ERROR_Clear (0x1UL)           /*!< Disable                                                              */
12631   #define CCM_INTENCLR_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
12632   #define CCM_INTENCLR_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
12633 
12634 
12635 /* CCM_MACSTATUS: MAC check result */
12636   #define CCM_MACSTATUS_ResetValue (0x00000000UL)    /*!< Reset value of MACSTATUS register.                                   */
12637 
12638 /* MACSTATUS @Bit 0 : The result of the MAC check performed during the previous decryption operation */
12639   #define CCM_MACSTATUS_MACSTATUS_Pos (0UL)          /*!< Position of MACSTATUS field.                                         */
12640   #define CCM_MACSTATUS_MACSTATUS_Msk (0x1UL << CCM_MACSTATUS_MACSTATUS_Pos) /*!< Bit mask of MACSTATUS field.                 */
12641   #define CCM_MACSTATUS_MACSTATUS_Min (0x0UL)        /*!< Min enumerator value of MACSTATUS field.                             */
12642   #define CCM_MACSTATUS_MACSTATUS_Max (0x1UL)        /*!< Max enumerator value of MACSTATUS field.                             */
12643   #define CCM_MACSTATUS_MACSTATUS_CheckFailed (0x0UL) /*!< MAC check failed                                                    */
12644   #define CCM_MACSTATUS_MACSTATUS_CheckPassed (0x1UL) /*!< MAC check passed                                                    */
12645 
12646 
12647 /* CCM_ERRORSTATUS: Error status */
12648   #define CCM_ERRORSTATUS_ResetValue (0x00000000UL)  /*!< Reset value of ERRORSTATUS register.                                 */
12649 
12650 /* ERRORSTATUS @Bits 0..1 : Error status when the ERROR event is generated */
12651   #define CCM_ERRORSTATUS_ERRORSTATUS_Pos (0UL)      /*!< Position of ERRORSTATUS field.                                       */
12652   #define CCM_ERRORSTATUS_ERRORSTATUS_Msk (0x3UL << CCM_ERRORSTATUS_ERRORSTATUS_Pos) /*!< Bit mask of ERRORSTATUS field.       */
12653   #define CCM_ERRORSTATUS_ERRORSTATUS_Min (0x0UL)    /*!< Min enumerator value of ERRORSTATUS field.                           */
12654   #define CCM_ERRORSTATUS_ERRORSTATUS_Max (0x3UL)    /*!< Max enumerator value of ERRORSTATUS field.                           */
12655   #define CCM_ERRORSTATUS_ERRORSTATUS_NoError (0x0UL) /*!< No errors have occurred                                             */
12656   #define CCM_ERRORSTATUS_ERRORSTATUS_PrematureInptrEnd (0x1UL) /*!< End of INPTR job list before CCM data structure was read. */
12657   #define CCM_ERRORSTATUS_ERRORSTATUS_PrematureOutptrEnd (0x2UL) /*!< End of OUTPTR job list before CCM data structure was
12658                                                                       read.*/
12659   #define CCM_ERRORSTATUS_ERRORSTATUS_EncryptionTooSlow (0x3UL) /*!< Encryption of the unencrypted CCM data structure did not
12660                                                                      complete in time.*/
12661 
12662 
12663 /* CCM_ENABLE: Enable */
12664   #define CCM_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */
12665 
12666 /* ENABLE @Bits 0..1 : Enable or disable CCM */
12667   #define CCM_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
12668   #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
12669   #define CCM_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
12670   #define CCM_ENABLE_ENABLE_Max (0x2UL)              /*!< Max enumerator value of ENABLE field.                                */
12671   #define CCM_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disable                                                              */
12672   #define CCM_ENABLE_ENABLE_Enabled (0x2UL)          /*!< Enable                                                               */
12673 
12674 
12675 /* CCM_MODE: Operation mode */
12676   #define CCM_MODE_ResetValue (0x00000001UL)         /*!< Reset value of MODE register.                                        */
12677 
12678 /* MODE @Bits 0..1 : The mode of operation to be used. The settings in this register apply when the CRYPT task is triggered. */
12679   #define CCM_MODE_MODE_Pos (0UL)                    /*!< Position of MODE field.                                              */
12680   #define CCM_MODE_MODE_Msk (0x3UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field.                                          */
12681   #define CCM_MODE_MODE_Min (0x0UL)                  /*!< Min enumerator value of MODE field.                                  */
12682   #define CCM_MODE_MODE_Max (0x2UL)                  /*!< Max enumerator value of MODE field.                                  */
12683   #define CCM_MODE_MODE_Encryption (0x0UL)           /*!< AES CCM packet encryption mode                                       */
12684   #define CCM_MODE_MODE_Decryption (0x1UL)           /*!< AES CCM packet decryption mode                                       */
12685   #define CCM_MODE_MODE_FastDecryption (0x2UL)       /*!< AES fast decrypt mode. This mode will run CCM decryption as fast as
12686                                                           possible, i.e. not locked to a radio data rate. This can be used when
12687                                                           a packet has been completely received.*/
12688 
12689 /* PROTOCOL @Bits 8..9 : Protocol and packet format selection */
12690   #define CCM_MODE_PROTOCOL_Pos (8UL)                /*!< Position of PROTOCOL field.                                          */
12691   #define CCM_MODE_PROTOCOL_Msk (0x3UL << CCM_MODE_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field.                              */
12692   #define CCM_MODE_PROTOCOL_Min (0x0UL)              /*!< Min enumerator value of PROTOCOL field.                              */
12693   #define CCM_MODE_PROTOCOL_Max (0x1UL)              /*!< Max enumerator value of PROTOCOL field.                              */
12694   #define CCM_MODE_PROTOCOL_Ble (0x0UL)              /*!< Bluetooth Low Energy packet format                                   */
12695   #define CCM_MODE_PROTOCOL_Ieee802154 (0x1UL)       /*!< 802.15.4 packet format                                               */
12696 
12697 /* DATARATE @Bits 16..18 : Radio data rate that the CCM shall run synchronous with */
12698   #define CCM_MODE_DATARATE_Pos (16UL)               /*!< Position of DATARATE field.                                          */
12699   #define CCM_MODE_DATARATE_Msk (0x7UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field.                              */
12700   #define CCM_MODE_DATARATE_Min (0x0UL)              /*!< Min enumerator value of DATARATE field.                              */
12701   #define CCM_MODE_DATARATE_Max (0x5UL)              /*!< Max enumerator value of DATARATE field.                              */
12702   #define CCM_MODE_DATARATE_125Kbit (0x0UL)          /*!< 125 Kbps                                                             */
12703   #define CCM_MODE_DATARATE_250Kbit (0x1UL)          /*!< 250 Kbps                                                             */
12704   #define CCM_MODE_DATARATE_500Kbit (0x2UL)          /*!< 500 Kbps                                                             */
12705   #define CCM_MODE_DATARATE_1Mbit (0x3UL)            /*!< 1 Mbps                                                               */
12706   #define CCM_MODE_DATARATE_2Mbit (0x4UL)            /*!< 2 Mbps                                                               */
12707   #define CCM_MODE_DATARATE_4Mbit (0x5UL)            /*!< 4 Mbps                                                               */
12708 
12709 /* MACLEN @Bits 24..26 : CCM MAC length (bytes) */
12710   #define CCM_MODE_MACLEN_Pos (24UL)                 /*!< Position of MACLEN field.                                            */
12711   #define CCM_MODE_MACLEN_Msk (0x7UL << CCM_MODE_MACLEN_Pos) /*!< Bit mask of MACLEN field.                                    */
12712   #define CCM_MODE_MACLEN_Min (0x0UL)                /*!< Min enumerator value of MACLEN field.                                */
12713   #define CCM_MODE_MACLEN_Max (0x7UL)                /*!< Max enumerator value of MACLEN field.                                */
12714   #define CCM_MODE_MACLEN_M0 (0x0UL)                 /*!< M = 0 This is a special case for CCM* where encryption is required but
12715                                                           not authentication*/
12716   #define CCM_MODE_MACLEN_M4 (0x1UL)                 /*!< M = 4                                                                */
12717   #define CCM_MODE_MACLEN_M6 (0x2UL)                 /*!< M = 6                                                                */
12718   #define CCM_MODE_MACLEN_M8 (0x3UL)                 /*!< M = 8                                                                */
12719   #define CCM_MODE_MACLEN_M10 (0x4UL)                /*!< M = 10                                                               */
12720   #define CCM_MODE_MACLEN_M12 (0x5UL)                /*!< M = 12                                                               */
12721   #define CCM_MODE_MACLEN_M14 (0x6UL)                /*!< M = 14                                                               */
12722   #define CCM_MODE_MACLEN_M16 (0x7UL)                /*!< M = 16                                                               */
12723 
12724 
12725 /* CCM_RATEOVERRIDE: Data rate override setting. */
12726   #define CCM_RATEOVERRIDE_ResetValue (0x00000002UL) /*!< Reset value of RATEOVERRIDE register.                                */
12727 
12728 /* RATEOVERRIDE @Bits 0..2 : Data rate override setting. */
12729   #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL)    /*!< Position of RATEOVERRIDE field.                                      */
12730   #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x7UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field.  */
12731   #define CCM_RATEOVERRIDE_RATEOVERRIDE_Min (0x0UL)  /*!< Min enumerator value of RATEOVERRIDE field.                          */
12732   #define CCM_RATEOVERRIDE_RATEOVERRIDE_Max (0x2UL)  /*!< Max enumerator value of RATEOVERRIDE field.                          */
12733   #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbit (0x0UL) /*!< 125 Kbps                                                          */
12734   #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbit (0x2UL) /*!< 500 Kbps                                                          */
12735 
12736 
12737 /* CCM_ADATAMASK: CCM adata mask. */
12738   #define CCM_ADATAMASK_ResetValue (0x000000E3UL)    /*!< Reset value of ADATAMASK register.                                   */
12739 
12740 /* ADATAMASK @Bits 0..7 : CCM adata mask. */
12741   #define CCM_ADATAMASK_ADATAMASK_Pos (0UL)          /*!< Position of ADATAMASK field.                                         */
12742   #define CCM_ADATAMASK_ADATAMASK_Msk (0xFFUL << CCM_ADATAMASK_ADATAMASK_Pos) /*!< Bit mask of ADATAMASK field.                */
12743 
12744 
12745 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
12746 
12747 /* =========================================================================================================================== */
12748 /* ================                                           CLIC                                           ================ */
12749 /* =========================================================================================================================== */
12750 
12751 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
12752 
12753 /* ==================================================== Struct CLIC_CLIC ===================================================== */
12754 /**
12755   * @brief CLIC [CLIC_CLIC] (unspecified)
12756   */
12757 typedef struct {
12758   __IM  uint32_t  CLICCFG;                           /*!< (@ 0x00000000) CLIC configuration.                                   */
12759   __IM  uint32_t  CLICINFO;                          /*!< (@ 0x00000004) CLIC information.                                     */
12760   __IM  uint32_t  RESERVED[1022];
12761   __IOM uint32_t  CLICINT[480];                      /*!< (@ 0x00001000) Interrupt control register for IRQ number [n].        */
12762 } NRF_CLIC_CLIC_Type;                                /*!< Size = 6016 (0x1780)                                                 */
12763 
12764 /* CLIC_CLIC_CLICCFG: CLIC configuration. */
12765   #define CLIC_CLIC_CLICCFG_ResetValue (0x00000005UL) /*!< Reset value of CLICCFG register.                                    */
12766 
12767 /* NVBITS @Bit 0 : Selective interrupt hardware vectoring. */
12768   #define CLIC_CLIC_CLICCFG_NVBITS_Pos (0UL)         /*!< Position of NVBITS field.                                            */
12769   #define CLIC_CLIC_CLICCFG_NVBITS_Msk (0x1UL << CLIC_CLIC_CLICCFG_NVBITS_Pos) /*!< Bit mask of NVBITS field.                  */
12770   #define CLIC_CLIC_CLICCFG_NVBITS_Min (0x1UL)       /*!< Min enumerator value of NVBITS field.                                */
12771   #define CLIC_CLIC_CLICCFG_NVBITS_Max (0x1UL)       /*!< Max enumerator value of NVBITS field.                                */
12772   #define CLIC_CLIC_CLICCFG_NVBITS_Implemented (0x1UL) /*!< Selective interrupt hardware vectoring is implemented              */
12773 
12774 /* NLBITS @Bits 1..4 : Interrupt level encoding. */
12775   #define CLIC_CLIC_CLICCFG_NLBITS_Pos (1UL)         /*!< Position of NLBITS field.                                            */
12776   #define CLIC_CLIC_CLICCFG_NLBITS_Msk (0xFUL << CLIC_CLIC_CLICCFG_NLBITS_Pos) /*!< Bit mask of NLBITS field.                  */
12777   #define CLIC_CLIC_CLICCFG_NLBITS_Min (0x2UL)       /*!< Min enumerator value of NLBITS field.                                */
12778   #define CLIC_CLIC_CLICCFG_NLBITS_Max (0x2UL)       /*!< Max enumerator value of NLBITS field.                                */
12779   #define CLIC_CLIC_CLICCFG_NLBITS_Two (0x2UL)       /*!< 2 bits = 3 interrupt levels                                          */
12780 
12781 /* NMBITS @Bits 5..6 : Interrupt privilege mode. */
12782   #define CLIC_CLIC_CLICCFG_NMBITS_Pos (5UL)         /*!< Position of NMBITS field.                                            */
12783   #define CLIC_CLIC_CLICCFG_NMBITS_Msk (0x3UL << CLIC_CLIC_CLICCFG_NMBITS_Pos) /*!< Bit mask of NMBITS field.                  */
12784   #define CLIC_CLIC_CLICCFG_NMBITS_Min (0x0UL)       /*!< Min enumerator value of NMBITS field.                                */
12785   #define CLIC_CLIC_CLICCFG_NMBITS_Max (0x0UL)       /*!< Max enumerator value of NMBITS field.                                */
12786   #define CLIC_CLIC_CLICCFG_NMBITS_ModeM (0x0UL)     /*!< All interrupts are M-mode only                                       */
12787 
12788 
12789 /* CLIC_CLIC_CLICINFO: CLIC information. */
12790   #define CLIC_CLIC_CLICINFO_ResetValue (0x00001FFFUL) /*!< Reset value of CLICINFO register.                                  */
12791 
12792 /* NUMINTERRUPTS @Bits 0..12 : Maximum number of interrupts supported. */
12793   #define CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Pos (0UL) /*!< Position of NUMINTERRUPTS field.                                     */
12794   #define CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Msk (0x1FFFUL << CLIC_CLIC_CLICINFO_NUMINTERRUPTS_Pos) /*!< Bit mask of NUMINTERRUPTS
12795                                                                             field.*/
12796 
12797 /* VERSION @Bits 13..20 : Version */
12798   #define CLIC_CLIC_CLICINFO_VERSION_Pos (13UL)      /*!< Position of VERSION field.                                           */
12799   #define CLIC_CLIC_CLICINFO_VERSION_Msk (0xFFUL << CLIC_CLIC_CLICINFO_VERSION_Pos) /*!< Bit mask of VERSION field.            */
12800 
12801 /* NUMTRIGGER @Bits 25..30 : Number of maximum interrupt triggers supported */
12802   #define CLIC_CLIC_CLICINFO_NUMTRIGGER_Pos (25UL)   /*!< Position of NUMTRIGGER field.                                        */
12803   #define CLIC_CLIC_CLICINFO_NUMTRIGGER_Msk (0x3FUL << CLIC_CLIC_CLICINFO_NUMTRIGGER_Pos) /*!< Bit mask of NUMTRIGGER field.   */
12804 
12805 
12806 /* CLIC_CLIC_CLICINT: Interrupt control register for IRQ number [n]. */
12807   #define CLIC_CLIC_CLICINT_MaxCount (480UL)         /*!< Max size of CLICINT[480] array.                                      */
12808   #define CLIC_CLIC_CLICINT_MaxIndex (479UL)         /*!< Max index of CLICINT[480] array.                                     */
12809   #define CLIC_CLIC_CLICINT_MinIndex (0UL)           /*!< Min index of CLICINT[480] array.                                     */
12810   #define CLIC_CLIC_CLICINT_ResetValue (0x3FC3FEFEUL) /*!< Reset value of CLICINT[480] register.                               */
12811 
12812 /* IP @Bit 0 : Interrupt Pending bit. */
12813   #define CLIC_CLIC_CLICINT_IP_Pos (0UL)             /*!< Position of IP field.                                                */
12814   #define CLIC_CLIC_CLICINT_IP_Msk (0x1UL << CLIC_CLIC_CLICINT_IP_Pos) /*!< Bit mask of IP field.                              */
12815   #define CLIC_CLIC_CLICINT_IP_Min (0x0UL)           /*!< Min enumerator value of IP field.                                    */
12816   #define CLIC_CLIC_CLICINT_IP_Max (0x1UL)           /*!< Max enumerator value of IP field.                                    */
12817   #define CLIC_CLIC_CLICINT_IP_NotPending (0x0UL)    /*!< Interrupt not pending                                                */
12818   #define CLIC_CLIC_CLICINT_IP_Pending (0x1UL)       /*!< Interrupt pending                                                    */
12819 
12820 /* READ1 @Bits 1..7 : Read as 1, write ignored. */
12821   #define CLIC_CLIC_CLICINT_READ1_Pos (1UL)          /*!< Position of READ1 field.                                             */
12822   #define CLIC_CLIC_CLICINT_READ1_Msk (0x7FUL << CLIC_CLIC_CLICINT_READ1_Pos) /*!< Bit mask of READ1 field.                    */
12823 
12824 /* IE @Bit 8 : Interrupt enable bit. */
12825   #define CLIC_CLIC_CLICINT_IE_Pos (8UL)             /*!< Position of IE field.                                                */
12826   #define CLIC_CLIC_CLICINT_IE_Msk (0x1UL << CLIC_CLIC_CLICINT_IE_Pos) /*!< Bit mask of IE field.                              */
12827   #define CLIC_CLIC_CLICINT_IE_Min (0x0UL)           /*!< Min enumerator value of IE field.                                    */
12828   #define CLIC_CLIC_CLICINT_IE_Max (0x1UL)           /*!< Max enumerator value of IE field.                                    */
12829   #define CLIC_CLIC_CLICINT_IE_Disabled (0x0UL)      /*!< Interrupt disabled                                                   */
12830   #define CLIC_CLIC_CLICINT_IE_Enabled (0x1UL)       /*!< Interrupt enabled                                                    */
12831 
12832 /* READ2 @Bits 9..15 : Read as 1, write ignored. */
12833   #define CLIC_CLIC_CLICINT_READ2_Pos (9UL)          /*!< Position of READ2 field.                                             */
12834   #define CLIC_CLIC_CLICINT_READ2_Msk (0x7FUL << CLIC_CLIC_CLICINT_READ2_Pos) /*!< Bit mask of READ2 field.                    */
12835 
12836 /* SHV @Bit 16 : Selective Hardware Vectoring. */
12837   #define CLIC_CLIC_CLICINT_SHV_Pos (16UL)           /*!< Position of SHV field.                                               */
12838   #define CLIC_CLIC_CLICINT_SHV_Msk (0x1UL << CLIC_CLIC_CLICINT_SHV_Pos) /*!< Bit mask of SHV field.                           */
12839   #define CLIC_CLIC_CLICINT_SHV_Min (0x1UL)          /*!< Min enumerator value of SHV field.                                   */
12840   #define CLIC_CLIC_CLICINT_SHV_Max (0x1UL)          /*!< Max enumerator value of SHV field.                                   */
12841   #define CLIC_CLIC_CLICINT_SHV_Vectored (0x1UL)     /*!< Hardware vectored                                                    */
12842 
12843 /* TRIG @Bits 17..18 : Trigger type and polarity for each interrupt input. */
12844   #define CLIC_CLIC_CLICINT_TRIG_Pos (17UL)          /*!< Position of TRIG field.                                              */
12845   #define CLIC_CLIC_CLICINT_TRIG_Msk (0x3UL << CLIC_CLIC_CLICINT_TRIG_Pos) /*!< Bit mask of TRIG field.                        */
12846   #define CLIC_CLIC_CLICINT_TRIG_Min (0x1UL)         /*!< Min enumerator value of TRIG field.                                  */
12847   #define CLIC_CLIC_CLICINT_TRIG_Max (0x1UL)         /*!< Max enumerator value of TRIG field.                                  */
12848   #define CLIC_CLIC_CLICINT_TRIG_EdgeTriggered (0x1UL) /*!< Interrupts are edge-triggered                                      */
12849 
12850 /* MODE @Bits 22..23 : Privilege mode. */
12851   #define CLIC_CLIC_CLICINT_MODE_Pos (22UL)          /*!< Position of MODE field.                                              */
12852   #define CLIC_CLIC_CLICINT_MODE_Msk (0x3UL << CLIC_CLIC_CLICINT_MODE_Pos) /*!< Bit mask of MODE field.                        */
12853   #define CLIC_CLIC_CLICINT_MODE_Min (0x3UL)         /*!< Min enumerator value of MODE field.                                  */
12854   #define CLIC_CLIC_CLICINT_MODE_Max (0x3UL)         /*!< Max enumerator value of MODE field.                                  */
12855   #define CLIC_CLIC_CLICINT_MODE_MachineMode (0x3UL) /*!< Machine mode                                                         */
12856 
12857 /* PRIORITY @Bits 24..31 : Interrupt priority level */
12858   #define CLIC_CLIC_CLICINT_PRIORITY_Pos (24UL)      /*!< Position of PRIORITY field.                                          */
12859   #define CLIC_CLIC_CLICINT_PRIORITY_Msk (0xFFUL << CLIC_CLIC_CLICINT_PRIORITY_Pos) /*!< Bit mask of PRIORITY field.           */
12860   #define CLIC_CLIC_CLICINT_PRIORITY_Min (0x3FUL)    /*!< Min enumerator value of PRIORITY field.                              */
12861   #define CLIC_CLIC_CLICINT_PRIORITY_Max (0xFFUL)    /*!< Max enumerator value of PRIORITY field.                              */
12862   #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL0 (0x3FUL) /*!< Priority level 0                                                 */
12863   #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL1 (0x7FUL) /*!< Priority level 1                                                 */
12864   #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL2 (0xBFUL) /*!< Priority level 2                                                 */
12865   #define CLIC_CLIC_CLICINT_PRIORITY_PRIOLEVEL3 (0xFFUL) /*!< Priority level 3                                                 */
12866 
12867 
12868 /* ======================================================= Struct CLIC ======================================================= */
12869 /**
12870   * @brief VPR CLIC registers
12871   */
12872   typedef struct {                                   /*!< CLIC Structure                                                       */
12873     __IOM NRF_CLIC_CLIC_Type CLIC;                   /*!< (@ 0x00000000) (unspecified)                                         */
12874   } NRF_CLIC_Type;                                   /*!< Size = 6016 (0x1780)                                                 */
12875 
12876 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
12877 
12878 /* =========================================================================================================================== */
12879 /* ================                                          CM33SS                                          ================ */
12880 /* =========================================================================================================================== */
12881 
12882 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
12883 /* ====================================================== Struct CM33SS ====================================================== */
12884 /**
12885   * @brief CM33 SubSystem
12886   */
12887   typedef struct {                                   /*!< CM33SS Structure                                                     */
12888     __IM uint32_t RESERVED[64];
12889     __IOM uint32_t EVENTS_FPUIOC;                    /*!< (@ 0x00000100) An invalid operation exception has occurred in the
12890                                                                          FPU.*/
12891     __IOM uint32_t EVENTS_FPUDZC;                    /*!< (@ 0x00000104) A floating-point divide-by-zero exception has occurred
12892                                                                          in the FPU.*/
12893     __IOM uint32_t EVENTS_FPUOFC;                    /*!< (@ 0x00000108) A floating-point overflow exception has occurred in the
12894                                                                          FPU.*/
12895     __IOM uint32_t EVENTS_FPUUFC;                    /*!< (@ 0x0000010C) A floating-point underflow exception has occurred in
12896                                                                          the FPU.*/
12897     __IOM uint32_t EVENTS_FPUIXC;                    /*!< (@ 0x00000110) A floating-point inexact exception has occurred in the
12898                                                                          FPU.*/
12899     __IOM uint32_t EVENTS_FPUIDC;                    /*!< (@ 0x00000114) A floating-point input denormal exception has occurred
12900                                                                          in the FPU.*/
12901     __IM uint32_t RESERVED1[250];
12902     __IOM uint32_t LOCK;                             /*!< (@ 0x00000500) Register to lock the certain parts of the CPU from
12903                                                                          being modified.*/
12904     __IM uint32_t CPUID;                             /*!< (@ 0x00000504) The identifier for the CPU in this subsystem.         */
12905   } NRF_CM33SS_Type;                                 /*!< Size = 1288 (0x508)                                                  */
12906 
12907 /* CM33SS_EVENTS_FPUIOC: An invalid operation exception has occurred in the FPU. */
12908   #define CM33SS_EVENTS_FPUIOC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIOC register.                           */
12909 
12910 /* EVENTS_FPUIOC @Bit 0 : An invalid operation exception has occurred in the FPU. */
12911   #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Pos (0UL) /*!< Position of EVENTS_FPUIOC field.                                   */
12912   #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Msk (0x1UL << CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Pos) /*!< Bit mask of
12913                                                                             EVENTS_FPUIOC field.*/
12914   #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIOC field.                     */
12915   #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIOC field.                     */
12916   #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_NotGenerated (0x0UL) /*!< Event not generated                                     */
12917   #define CM33SS_EVENTS_FPUIOC_EVENTS_FPUIOC_Generated (0x1UL) /*!< Event generated                                            */
12918 
12919 
12920 /* CM33SS_EVENTS_FPUDZC: A floating-point divide-by-zero exception has occurred in the FPU. */
12921   #define CM33SS_EVENTS_FPUDZC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUDZC register.                           */
12922 
12923 /* EVENTS_FPUDZC @Bit 0 : A floating-point divide-by-zero exception has occurred in the FPU. */
12924   #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Pos (0UL) /*!< Position of EVENTS_FPUDZC field.                                   */
12925   #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Msk (0x1UL << CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Pos) /*!< Bit mask of
12926                                                                             EVENTS_FPUDZC field.*/
12927   #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUDZC field.                     */
12928   #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUDZC field.                     */
12929   #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_NotGenerated (0x0UL) /*!< Event not generated                                     */
12930   #define CM33SS_EVENTS_FPUDZC_EVENTS_FPUDZC_Generated (0x1UL) /*!< Event generated                                            */
12931 
12932 
12933 /* CM33SS_EVENTS_FPUOFC: A floating-point overflow exception has occurred in the FPU. */
12934   #define CM33SS_EVENTS_FPUOFC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUOFC register.                           */
12935 
12936 /* EVENTS_FPUOFC @Bit 0 : A floating-point overflow exception has occurred in the FPU. */
12937   #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Pos (0UL) /*!< Position of EVENTS_FPUOFC field.                                   */
12938   #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Msk (0x1UL << CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Pos) /*!< Bit mask of
12939                                                                             EVENTS_FPUOFC field.*/
12940   #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUOFC field.                     */
12941   #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUOFC field.                     */
12942   #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_NotGenerated (0x0UL) /*!< Event not generated                                     */
12943   #define CM33SS_EVENTS_FPUOFC_EVENTS_FPUOFC_Generated (0x1UL) /*!< Event generated                                            */
12944 
12945 
12946 /* CM33SS_EVENTS_FPUUFC: A floating-point underflow exception has occurred in the FPU. */
12947   #define CM33SS_EVENTS_FPUUFC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUUFC register.                           */
12948 
12949 /* EVENTS_FPUUFC @Bit 0 : A floating-point underflow exception has occurred in the FPU. */
12950   #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Pos (0UL) /*!< Position of EVENTS_FPUUFC field.                                   */
12951   #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Msk (0x1UL << CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Pos) /*!< Bit mask of
12952                                                                             EVENTS_FPUUFC field.*/
12953   #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUUFC field.                     */
12954   #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUUFC field.                     */
12955   #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_NotGenerated (0x0UL) /*!< Event not generated                                     */
12956   #define CM33SS_EVENTS_FPUUFC_EVENTS_FPUUFC_Generated (0x1UL) /*!< Event generated                                            */
12957 
12958 
12959 /* CM33SS_EVENTS_FPUIXC: A floating-point inexact exception has occurred in the FPU. */
12960   #define CM33SS_EVENTS_FPUIXC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIXC register.                           */
12961 
12962 /* EVENTS_FPUIXC @Bit 0 : A floating-point inexact exception has occurred in the FPU. */
12963   #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Pos (0UL) /*!< Position of EVENTS_FPUIXC field.                                   */
12964   #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Msk (0x1UL << CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Pos) /*!< Bit mask of
12965                                                                             EVENTS_FPUIXC field.*/
12966   #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIXC field.                     */
12967   #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIXC field.                     */
12968   #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_NotGenerated (0x0UL) /*!< Event not generated                                     */
12969   #define CM33SS_EVENTS_FPUIXC_EVENTS_FPUIXC_Generated (0x1UL) /*!< Event generated                                            */
12970 
12971 
12972 /* CM33SS_EVENTS_FPUIDC: A floating-point input denormal exception has occurred in the FPU. */
12973   #define CM33SS_EVENTS_FPUIDC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FPUIDC register.                           */
12974 
12975 /* EVENTS_FPUIDC @Bit 0 : A floating-point input denormal exception has occurred in the FPU. */
12976   #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Pos (0UL) /*!< Position of EVENTS_FPUIDC field.                                   */
12977   #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Msk (0x1UL << CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Pos) /*!< Bit mask of
12978                                                                             EVENTS_FPUIDC field.*/
12979   #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Min (0x0UL) /*!< Min enumerator value of EVENTS_FPUIDC field.                     */
12980   #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Max (0x1UL) /*!< Max enumerator value of EVENTS_FPUIDC field.                     */
12981   #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_NotGenerated (0x0UL) /*!< Event not generated                                     */
12982   #define CM33SS_EVENTS_FPUIDC_EVENTS_FPUIDC_Generated (0x1UL) /*!< Event generated                                            */
12983 
12984 
12985 /* CM33SS_LOCK: Register to lock the certain parts of the CPU from being modified. */
12986   #define CM33SS_LOCK_ResetValue (0x00000000UL)      /*!< Reset value of LOCK register.                                        */
12987 
12988 /* LOCKVTORAIRCRS @Bit 0 : Locks both the Vector table Offset Register (VTOR) and Application Interrupt and Reset Control
12989                            Register (AIRCR) for secure mode. */
12990 
12991   #define CM33SS_LOCK_LOCKVTORAIRCRS_Pos (0UL)       /*!< Position of LOCKVTORAIRCRS field.                                    */
12992   #define CM33SS_LOCK_LOCKVTORAIRCRS_Msk (0x1UL << CM33SS_LOCK_LOCKVTORAIRCRS_Pos) /*!< Bit mask of LOCKVTORAIRCRS field.      */
12993   #define CM33SS_LOCK_LOCKVTORAIRCRS_Min (0x0UL)     /*!< Min enumerator value of LOCKVTORAIRCRS field.                        */
12994   #define CM33SS_LOCK_LOCKVTORAIRCRS_Max (0x1UL)     /*!< Max enumerator value of LOCKVTORAIRCRS field.                        */
12995   #define CM33SS_LOCK_LOCKVTORAIRCRS_NotLocked (0x0UL) /*!< Both VTOR and AIRCR can be changed.                                */
12996   #define CM33SS_LOCK_LOCKVTORAIRCRS_Locked (0x1UL)  /*!< Prevents changes to both VTOR and AIRCR.                             */
12997 
12998 /* LOCKVTORNS @Bit 1 : Locks the Vector table Offset Register (VTOR) for non-secure mode. */
12999   #define CM33SS_LOCK_LOCKVTORNS_Pos (1UL)           /*!< Position of LOCKVTORNS field.                                        */
13000   #define CM33SS_LOCK_LOCKVTORNS_Msk (0x1UL << CM33SS_LOCK_LOCKVTORNS_Pos) /*!< Bit mask of LOCKVTORNS field.                  */
13001   #define CM33SS_LOCK_LOCKVTORNS_Min (0x0UL)         /*!< Min enumerator value of LOCKVTORNS field.                            */
13002   #define CM33SS_LOCK_LOCKVTORNS_Max (0x1UL)         /*!< Max enumerator value of LOCKVTORNS field.                            */
13003   #define CM33SS_LOCK_LOCKVTORNS_NotLocked (0x0UL)   /*!< VTOR can be changed.                                                 */
13004   #define CM33SS_LOCK_LOCKVTORNS_Locked (0x1UL)      /*!< Prevents changes to VTOR.                                            */
13005 
13006 /* LOCKMPUS @Bit 2 : Locks the Memory Protection Unit (MPU) for secure mode. */
13007   #define CM33SS_LOCK_LOCKMPUS_Pos (2UL)             /*!< Position of LOCKMPUS field.                                          */
13008   #define CM33SS_LOCK_LOCKMPUS_Msk (0x1UL << CM33SS_LOCK_LOCKMPUS_Pos) /*!< Bit mask of LOCKMPUS field.                        */
13009   #define CM33SS_LOCK_LOCKMPUS_Min (0x0UL)           /*!< Min enumerator value of LOCKMPUS field.                              */
13010   #define CM33SS_LOCK_LOCKMPUS_Max (0x1UL)           /*!< Max enumerator value of LOCKMPUS field.                              */
13011   #define CM33SS_LOCK_LOCKMPUS_NotLocked (0x0UL)     /*!< MPU registers can be changed.                                        */
13012   #define CM33SS_LOCK_LOCKMPUS_Locked (0x1UL)        /*!< Prevents changes to MPU registers.                                   */
13013 
13014 /* LOCKMPUNS @Bit 3 : Locks the Memory Protection Unit (MPU) for non secure mode. */
13015   #define CM33SS_LOCK_LOCKMPUNS_Pos (3UL)            /*!< Position of LOCKMPUNS field.                                         */
13016   #define CM33SS_LOCK_LOCKMPUNS_Msk (0x1UL << CM33SS_LOCK_LOCKMPUNS_Pos) /*!< Bit mask of LOCKMPUNS field.                     */
13017   #define CM33SS_LOCK_LOCKMPUNS_Min (0x0UL)          /*!< Min enumerator value of LOCKMPUNS field.                             */
13018   #define CM33SS_LOCK_LOCKMPUNS_Max (0x1UL)          /*!< Max enumerator value of LOCKMPUNS field.                             */
13019   #define CM33SS_LOCK_LOCKMPUNS_NotLocked (0x0UL)    /*!< MPU registers can be changed.                                        */
13020   #define CM33SS_LOCK_LOCKMPUNS_Locked (0x1UL)       /*!< Prevents changes to MPU registers.                                   */
13021 
13022 /* LOCKSAU @Bit 4 : Locks the Security Attribution Unit (SAU) */
13023   #define CM33SS_LOCK_LOCKSAU_Pos (4UL)              /*!< Position of LOCKSAU field.                                           */
13024   #define CM33SS_LOCK_LOCKSAU_Msk (0x1UL << CM33SS_LOCK_LOCKSAU_Pos) /*!< Bit mask of LOCKSAU field.                           */
13025   #define CM33SS_LOCK_LOCKSAU_Min (0x0UL)            /*!< Min enumerator value of LOCKSAU field.                               */
13026   #define CM33SS_LOCK_LOCKSAU_Max (0x1UL)            /*!< Max enumerator value of LOCKSAU field.                               */
13027   #define CM33SS_LOCK_LOCKSAU_NotLocked (0x0UL)      /*!< SAU registers can be changed.                                        */
13028   #define CM33SS_LOCK_LOCKSAU_Locked (0x1UL)         /*!< Prevents changes to SAU registers.                                   */
13029 
13030 
13031 /* CM33SS_CPUID: The identifier for the CPU in this subsystem. */
13032   #define CM33SS_CPUID_ResetValue (0x00000000UL)     /*!< Reset value of CPUID register.                                       */
13033 
13034 /* CPUID @Bits 0..31 : The CPU identifier. */
13035   #define CM33SS_CPUID_CPUID_Pos (0UL)               /*!< Position of CPUID field.                                             */
13036   #define CM33SS_CPUID_CPUID_Msk (0xFFFFFFFFUL << CM33SS_CPUID_CPUID_Pos) /*!< Bit mask of CPUID field.                        */
13037 
13038 
13039 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
13040 
13041 /* =========================================================================================================================== */
13042 /* ================                                           COMP                                           ================ */
13043 /* =========================================================================================================================== */
13044 
13045 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
13046 /* ======================================================= Struct COMP ======================================================= */
13047 /**
13048   * @brief Comparator
13049   */
13050   typedef struct {                                   /*!< COMP Structure                                                       */
13051     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start comparator                                      */
13052     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop comparator                                       */
13053     __OM uint32_t TASKS_SAMPLE;                      /*!< (@ 0x00000008) Sample comparator value                               */
13054     __IM uint32_t RESERVED[29];
13055     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
13056     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
13057     __IOM uint32_t SUBSCRIBE_SAMPLE;                 /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE               */
13058     __IM uint32_t RESERVED1[29];
13059     __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000100) COMP is ready and output is valid                     */
13060     __IOM uint32_t EVENTS_DOWN;                      /*!< (@ 0x00000104) Downward crossing                                     */
13061     __IOM uint32_t EVENTS_UP;                        /*!< (@ 0x00000108) Upward crossing                                       */
13062     __IOM uint32_t EVENTS_CROSS;                     /*!< (@ 0x0000010C) Downward or upward crossing                           */
13063     __IM uint32_t RESERVED2[28];
13064     __IOM uint32_t PUBLISH_READY;                    /*!< (@ 0x00000180) Publish configuration for event READY                 */
13065     __IOM uint32_t PUBLISH_DOWN;                     /*!< (@ 0x00000184) Publish configuration for event DOWN                  */
13066     __IOM uint32_t PUBLISH_UP;                       /*!< (@ 0x00000188) Publish configuration for event UP                    */
13067     __IOM uint32_t PUBLISH_CROSS;                    /*!< (@ 0x0000018C) Publish configuration for event CROSS                 */
13068     __IM uint32_t RESERVED3[28];
13069     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
13070     __IM uint32_t RESERVED4[63];
13071     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
13072     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
13073     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
13074     __IM uint32_t RESERVED5[61];
13075     __IM uint32_t RESULT;                            /*!< (@ 0x00000400) Compare result                                        */
13076     __IM uint32_t RESERVED6[63];
13077     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) COMP enable                                           */
13078     __IOM uint32_t PSEL;                             /*!< (@ 0x00000504) Pin select                                            */
13079     __IOM uint32_t REFSEL;                           /*!< (@ 0x00000508) Reference source select for single-ended mode         */
13080     __IOM uint32_t EXTREFSEL;                        /*!< (@ 0x0000050C) External reference select                             */
13081     __IM uint32_t RESERVED7[2];
13082     #if defined(_GNUC_)
13083       #pragma GCC diagnostic push
13084       #pragma GCC diagnostic ignored "-Wpedantic"
13085     #endif
13086     union {
13087       __IOM uint32_t CONFIGVOLTLVL;                  /*!< (@ 0x00000518) Configure voltage level for analog input              */
13088     };
13089     #if defined(_GNUC_)
13090       #pragma GCC diagnostic pop
13091     #endif
13092     __IM uint32_t RESERVED8[5];
13093     __IOM uint32_t TH;                               /*!< (@ 0x00000530) Threshold configuration for hysteresis unit           */
13094     __IOM uint32_t MODE;                             /*!< (@ 0x00000534) Mode configuration                                    */
13095     __IOM uint32_t HYST;                             /*!< (@ 0x00000538) Comparator hysteresis enable                          */
13096     __IOM uint32_t ISOURCE;                          /*!< (@ 0x0000053C) Current source select on analog input                 */
13097   } NRF_COMP_Type;                                   /*!< Size = 1344 (0x540)                                                  */
13098 
13099 /* COMP_TASKS_START: Start comparator */
13100   #define COMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */
13101 
13102 /* TASKS_START @Bit 0 : Start comparator */
13103   #define COMP_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
13104   #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
13105   #define COMP_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
13106   #define COMP_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
13107   #define COMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */
13108 
13109 
13110 /* COMP_TASKS_STOP: Stop comparator */
13111   #define COMP_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */
13112 
13113 /* TASKS_STOP @Bit 0 : Stop comparator */
13114   #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
13115   #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
13116   #define COMP_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
13117   #define COMP_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
13118   #define COMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */
13119 
13120 
13121 /* COMP_TASKS_SAMPLE: Sample comparator value */
13122   #define COMP_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register.                               */
13123 
13124 /* TASKS_SAMPLE @Bit 0 : Sample comparator value */
13125   #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL)   /*!< Position of TASKS_SAMPLE field.                                      */
13126   #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field.*/
13127   #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field.                          */
13128   #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field.                          */
13129   #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task                                                     */
13130 
13131 
13132 /* COMP_SUBSCRIBE_START: Subscribe configuration for task START */
13133   #define COMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                         */
13134 
13135 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
13136   #define COMP_SUBSCRIBE_START_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
13137   #define COMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
13138   #define COMP_SUBSCRIBE_START_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
13139   #define COMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
13140 
13141 /* EN @Bit 31 : (unspecified) */
13142   #define COMP_SUBSCRIBE_START_EN_Pos (31UL)         /*!< Position of EN field.                                                */
13143   #define COMP_SUBSCRIBE_START_EN_Msk (0x1UL << COMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                        */
13144   #define COMP_SUBSCRIBE_START_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
13145   #define COMP_SUBSCRIBE_START_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
13146   #define COMP_SUBSCRIBE_START_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
13147   #define COMP_SUBSCRIBE_START_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
13148 
13149 
13150 /* COMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
13151   #define COMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */
13152 
13153 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
13154   #define COMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
13155   #define COMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
13156   #define COMP_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
13157   #define COMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
13158 
13159 /* EN @Bit 31 : (unspecified) */
13160   #define COMP_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
13161   #define COMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << COMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
13162   #define COMP_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
13163   #define COMP_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
13164   #define COMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
13165   #define COMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
13166 
13167 
13168 /* COMP_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */
13169   #define COMP_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register.                       */
13170 
13171 /* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */
13172   #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
13173   #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << COMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
13174   #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
13175   #define COMP_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
13176 
13177 /* EN @Bit 31 : (unspecified) */
13178   #define COMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
13179   #define COMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << COMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field.                      */
13180   #define COMP_SUBSCRIBE_SAMPLE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
13181   #define COMP_SUBSCRIBE_SAMPLE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
13182   #define COMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
13183   #define COMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
13184 
13185 
13186 /* COMP_EVENTS_READY: COMP is ready and output is valid */
13187   #define COMP_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                               */
13188 
13189 /* EVENTS_READY @Bit 0 : COMP is ready and output is valid */
13190   #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL)   /*!< Position of EVENTS_READY field.                                      */
13191   #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field.*/
13192   #define COMP_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                          */
13193   #define COMP_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                          */
13194   #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
13195   #define COMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                                */
13196 
13197 
13198 /* COMP_EVENTS_DOWN: Downward crossing */
13199   #define COMP_EVENTS_DOWN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DOWN register.                                 */
13200 
13201 /* EVENTS_DOWN @Bit 0 : Downward crossing */
13202   #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL)     /*!< Position of EVENTS_DOWN field.                                       */
13203   #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field.     */
13204   #define COMP_EVENTS_DOWN_EVENTS_DOWN_Min (0x0UL)   /*!< Min enumerator value of EVENTS_DOWN field.                           */
13205   #define COMP_EVENTS_DOWN_EVENTS_DOWN_Max (0x1UL)   /*!< Max enumerator value of EVENTS_DOWN field.                           */
13206   #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated                                           */
13207   #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated                                                  */
13208 
13209 
13210 /* COMP_EVENTS_UP: Upward crossing */
13211   #define COMP_EVENTS_UP_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_UP register.                                   */
13212 
13213 /* EVENTS_UP @Bit 0 : Upward crossing */
13214   #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL)         /*!< Position of EVENTS_UP field.                                         */
13215   #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field.               */
13216   #define COMP_EVENTS_UP_EVENTS_UP_Min (0x0UL)       /*!< Min enumerator value of EVENTS_UP field.                             */
13217   #define COMP_EVENTS_UP_EVENTS_UP_Max (0x1UL)       /*!< Max enumerator value of EVENTS_UP field.                             */
13218   #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated                                               */
13219   #define COMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated                                                      */
13220 
13221 
13222 /* COMP_EVENTS_CROSS: Downward or upward crossing */
13223   #define COMP_EVENTS_CROSS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CROSS register.                               */
13224 
13225 /* EVENTS_CROSS @Bit 0 : Downward or upward crossing */
13226   #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL)   /*!< Position of EVENTS_CROSS field.                                      */
13227   #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field.*/
13228   #define COMP_EVENTS_CROSS_EVENTS_CROSS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CROSS field.                          */
13229   #define COMP_EVENTS_CROSS_EVENTS_CROSS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CROSS field.                          */
13230   #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated                                         */
13231   #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated                                                */
13232 
13233 
13234 /* COMP_PUBLISH_READY: Publish configuration for event READY */
13235   #define COMP_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register.                             */
13236 
13237 /* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
13238   #define COMP_PUBLISH_READY_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
13239   #define COMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << COMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
13240   #define COMP_PUBLISH_READY_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
13241   #define COMP_PUBLISH_READY_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
13242 
13243 /* EN @Bit 31 : (unspecified) */
13244   #define COMP_PUBLISH_READY_EN_Pos (31UL)           /*!< Position of EN field.                                                */
13245   #define COMP_PUBLISH_READY_EN_Msk (0x1UL << COMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field.                            */
13246   #define COMP_PUBLISH_READY_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
13247   #define COMP_PUBLISH_READY_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
13248   #define COMP_PUBLISH_READY_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
13249   #define COMP_PUBLISH_READY_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
13250 
13251 
13252 /* COMP_PUBLISH_DOWN: Publish configuration for event DOWN */
13253   #define COMP_PUBLISH_DOWN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DOWN register.                               */
13254 
13255 /* CHIDX @Bits 0..7 : DPPI channel that event DOWN will publish to */
13256   #define COMP_PUBLISH_DOWN_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
13257   #define COMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << COMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
13258   #define COMP_PUBLISH_DOWN_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
13259   #define COMP_PUBLISH_DOWN_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
13260 
13261 /* EN @Bit 31 : (unspecified) */
13262   #define COMP_PUBLISH_DOWN_EN_Pos (31UL)            /*!< Position of EN field.                                                */
13263   #define COMP_PUBLISH_DOWN_EN_Msk (0x1UL << COMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field.                              */
13264   #define COMP_PUBLISH_DOWN_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
13265   #define COMP_PUBLISH_DOWN_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
13266   #define COMP_PUBLISH_DOWN_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
13267   #define COMP_PUBLISH_DOWN_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
13268 
13269 
13270 /* COMP_PUBLISH_UP: Publish configuration for event UP */
13271   #define COMP_PUBLISH_UP_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_UP register.                                  */
13272 
13273 /* CHIDX @Bits 0..7 : DPPI channel that event UP will publish to */
13274   #define COMP_PUBLISH_UP_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
13275   #define COMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << COMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
13276   #define COMP_PUBLISH_UP_CHIDX_Min (0x0UL)          /*!< Min value of CHIDX field.                                            */
13277   #define COMP_PUBLISH_UP_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */
13278 
13279 /* EN @Bit 31 : (unspecified) */
13280   #define COMP_PUBLISH_UP_EN_Pos (31UL)              /*!< Position of EN field.                                                */
13281   #define COMP_PUBLISH_UP_EN_Msk (0x1UL << COMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field.                                  */
13282   #define COMP_PUBLISH_UP_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
13283   #define COMP_PUBLISH_UP_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
13284   #define COMP_PUBLISH_UP_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
13285   #define COMP_PUBLISH_UP_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */
13286 
13287 
13288 /* COMP_PUBLISH_CROSS: Publish configuration for event CROSS */
13289   #define COMP_PUBLISH_CROSS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CROSS register.                             */
13290 
13291 /* CHIDX @Bits 0..7 : DPPI channel that event CROSS will publish to */
13292   #define COMP_PUBLISH_CROSS_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
13293   #define COMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << COMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
13294   #define COMP_PUBLISH_CROSS_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
13295   #define COMP_PUBLISH_CROSS_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
13296 
13297 /* EN @Bit 31 : (unspecified) */
13298   #define COMP_PUBLISH_CROSS_EN_Pos (31UL)           /*!< Position of EN field.                                                */
13299   #define COMP_PUBLISH_CROSS_EN_Msk (0x1UL << COMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field.                            */
13300   #define COMP_PUBLISH_CROSS_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
13301   #define COMP_PUBLISH_CROSS_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
13302   #define COMP_PUBLISH_CROSS_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
13303   #define COMP_PUBLISH_CROSS_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
13304 
13305 
13306 /* COMP_SHORTS: Shortcuts between local events and tasks */
13307   #define COMP_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */
13308 
13309 /* READY_SAMPLE @Bit 0 : Shortcut between event READY and task SAMPLE */
13310   #define COMP_SHORTS_READY_SAMPLE_Pos (0UL)         /*!< Position of READY_SAMPLE field.                                      */
13311   #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field.            */
13312   #define COMP_SHORTS_READY_SAMPLE_Min (0x0UL)       /*!< Min enumerator value of READY_SAMPLE field.                          */
13313   #define COMP_SHORTS_READY_SAMPLE_Max (0x1UL)       /*!< Max enumerator value of READY_SAMPLE field.                          */
13314   #define COMP_SHORTS_READY_SAMPLE_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
13315   #define COMP_SHORTS_READY_SAMPLE_Enabled (0x1UL)   /*!< Enable shortcut                                                      */
13316 
13317 /* READY_STOP @Bit 1 : Shortcut between event READY and task STOP */
13318   #define COMP_SHORTS_READY_STOP_Pos (1UL)           /*!< Position of READY_STOP field.                                        */
13319   #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field.                  */
13320   #define COMP_SHORTS_READY_STOP_Min (0x0UL)         /*!< Min enumerator value of READY_STOP field.                            */
13321   #define COMP_SHORTS_READY_STOP_Max (0x1UL)         /*!< Max enumerator value of READY_STOP field.                            */
13322   #define COMP_SHORTS_READY_STOP_Disabled (0x0UL)    /*!< Disable shortcut                                                     */
13323   #define COMP_SHORTS_READY_STOP_Enabled (0x1UL)     /*!< Enable shortcut                                                      */
13324 
13325 /* DOWN_STOP @Bit 2 : Shortcut between event DOWN and task STOP */
13326   #define COMP_SHORTS_DOWN_STOP_Pos (2UL)            /*!< Position of DOWN_STOP field.                                         */
13327   #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field.                     */
13328   #define COMP_SHORTS_DOWN_STOP_Min (0x0UL)          /*!< Min enumerator value of DOWN_STOP field.                             */
13329   #define COMP_SHORTS_DOWN_STOP_Max (0x1UL)          /*!< Max enumerator value of DOWN_STOP field.                             */
13330   #define COMP_SHORTS_DOWN_STOP_Disabled (0x0UL)     /*!< Disable shortcut                                                     */
13331   #define COMP_SHORTS_DOWN_STOP_Enabled (0x1UL)      /*!< Enable shortcut                                                      */
13332 
13333 /* UP_STOP @Bit 3 : Shortcut between event UP and task STOP */
13334   #define COMP_SHORTS_UP_STOP_Pos (3UL)              /*!< Position of UP_STOP field.                                           */
13335   #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field.                           */
13336   #define COMP_SHORTS_UP_STOP_Min (0x0UL)            /*!< Min enumerator value of UP_STOP field.                               */
13337   #define COMP_SHORTS_UP_STOP_Max (0x1UL)            /*!< Max enumerator value of UP_STOP field.                               */
13338   #define COMP_SHORTS_UP_STOP_Disabled (0x0UL)       /*!< Disable shortcut                                                     */
13339   #define COMP_SHORTS_UP_STOP_Enabled (0x1UL)        /*!< Enable shortcut                                                      */
13340 
13341 /* CROSS_STOP @Bit 4 : Shortcut between event CROSS and task STOP */
13342   #define COMP_SHORTS_CROSS_STOP_Pos (4UL)           /*!< Position of CROSS_STOP field.                                        */
13343   #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field.                  */
13344   #define COMP_SHORTS_CROSS_STOP_Min (0x0UL)         /*!< Min enumerator value of CROSS_STOP field.                            */
13345   #define COMP_SHORTS_CROSS_STOP_Max (0x1UL)         /*!< Max enumerator value of CROSS_STOP field.                            */
13346   #define COMP_SHORTS_CROSS_STOP_Disabled (0x0UL)    /*!< Disable shortcut                                                     */
13347   #define COMP_SHORTS_CROSS_STOP_Enabled (0x1UL)     /*!< Enable shortcut                                                      */
13348 
13349 
13350 /* COMP_INTEN: Enable or disable interrupt */
13351   #define COMP_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */
13352 
13353 /* READY @Bit 0 : Enable or disable interrupt for event READY */
13354   #define COMP_INTEN_READY_Pos (0UL)                 /*!< Position of READY field.                                             */
13355   #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field.                                   */
13356   #define COMP_INTEN_READY_Min (0x0UL)               /*!< Min enumerator value of READY field.                                 */
13357   #define COMP_INTEN_READY_Max (0x1UL)               /*!< Max enumerator value of READY field.                                 */
13358   #define COMP_INTEN_READY_Disabled (0x0UL)          /*!< Disable                                                              */
13359   #define COMP_INTEN_READY_Enabled (0x1UL)           /*!< Enable                                                               */
13360 
13361 /* DOWN @Bit 1 : Enable or disable interrupt for event DOWN */
13362   #define COMP_INTEN_DOWN_Pos (1UL)                  /*!< Position of DOWN field.                                              */
13363   #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field.                                      */
13364   #define COMP_INTEN_DOWN_Min (0x0UL)                /*!< Min enumerator value of DOWN field.                                  */
13365   #define COMP_INTEN_DOWN_Max (0x1UL)                /*!< Max enumerator value of DOWN field.                                  */
13366   #define COMP_INTEN_DOWN_Disabled (0x0UL)           /*!< Disable                                                              */
13367   #define COMP_INTEN_DOWN_Enabled (0x1UL)            /*!< Enable                                                               */
13368 
13369 /* UP @Bit 2 : Enable or disable interrupt for event UP */
13370   #define COMP_INTEN_UP_Pos (2UL)                    /*!< Position of UP field.                                                */
13371   #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field.                                            */
13372   #define COMP_INTEN_UP_Min (0x0UL)                  /*!< Min enumerator value of UP field.                                    */
13373   #define COMP_INTEN_UP_Max (0x1UL)                  /*!< Max enumerator value of UP field.                                    */
13374   #define COMP_INTEN_UP_Disabled (0x0UL)             /*!< Disable                                                              */
13375   #define COMP_INTEN_UP_Enabled (0x1UL)              /*!< Enable                                                               */
13376 
13377 /* CROSS @Bit 3 : Enable or disable interrupt for event CROSS */
13378   #define COMP_INTEN_CROSS_Pos (3UL)                 /*!< Position of CROSS field.                                             */
13379   #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field.                                   */
13380   #define COMP_INTEN_CROSS_Min (0x0UL)               /*!< Min enumerator value of CROSS field.                                 */
13381   #define COMP_INTEN_CROSS_Max (0x1UL)               /*!< Max enumerator value of CROSS field.                                 */
13382   #define COMP_INTEN_CROSS_Disabled (0x0UL)          /*!< Disable                                                              */
13383   #define COMP_INTEN_CROSS_Enabled (0x1UL)           /*!< Enable                                                               */
13384 
13385 
13386 /* COMP_INTENSET: Enable interrupt */
13387   #define COMP_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */
13388 
13389 /* READY @Bit 0 : Write '1' to enable interrupt for event READY */
13390   #define COMP_INTENSET_READY_Pos (0UL)              /*!< Position of READY field.                                             */
13391   #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field.                             */
13392   #define COMP_INTENSET_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
13393   #define COMP_INTENSET_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
13394   #define COMP_INTENSET_READY_Set (0x1UL)            /*!< Enable                                                               */
13395   #define COMP_INTENSET_READY_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
13396   #define COMP_INTENSET_READY_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
13397 
13398 /* DOWN @Bit 1 : Write '1' to enable interrupt for event DOWN */
13399   #define COMP_INTENSET_DOWN_Pos (1UL)               /*!< Position of DOWN field.                                              */
13400   #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field.                                */
13401   #define COMP_INTENSET_DOWN_Min (0x0UL)             /*!< Min enumerator value of DOWN field.                                  */
13402   #define COMP_INTENSET_DOWN_Max (0x1UL)             /*!< Max enumerator value of DOWN field.                                  */
13403   #define COMP_INTENSET_DOWN_Set (0x1UL)             /*!< Enable                                                               */
13404   #define COMP_INTENSET_DOWN_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
13405   #define COMP_INTENSET_DOWN_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
13406 
13407 /* UP @Bit 2 : Write '1' to enable interrupt for event UP */
13408   #define COMP_INTENSET_UP_Pos (2UL)                 /*!< Position of UP field.                                                */
13409   #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field.                                      */
13410   #define COMP_INTENSET_UP_Min (0x0UL)               /*!< Min enumerator value of UP field.                                    */
13411   #define COMP_INTENSET_UP_Max (0x1UL)               /*!< Max enumerator value of UP field.                                    */
13412   #define COMP_INTENSET_UP_Set (0x1UL)               /*!< Enable                                                               */
13413   #define COMP_INTENSET_UP_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
13414   #define COMP_INTENSET_UP_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
13415 
13416 /* CROSS @Bit 3 : Write '1' to enable interrupt for event CROSS */
13417   #define COMP_INTENSET_CROSS_Pos (3UL)              /*!< Position of CROSS field.                                             */
13418   #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field.                             */
13419   #define COMP_INTENSET_CROSS_Min (0x0UL)            /*!< Min enumerator value of CROSS field.                                 */
13420   #define COMP_INTENSET_CROSS_Max (0x1UL)            /*!< Max enumerator value of CROSS field.                                 */
13421   #define COMP_INTENSET_CROSS_Set (0x1UL)            /*!< Enable                                                               */
13422   #define COMP_INTENSET_CROSS_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
13423   #define COMP_INTENSET_CROSS_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
13424 
13425 
13426 /* COMP_INTENCLR: Disable interrupt */
13427   #define COMP_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */
13428 
13429 /* READY @Bit 0 : Write '1' to disable interrupt for event READY */
13430   #define COMP_INTENCLR_READY_Pos (0UL)              /*!< Position of READY field.                                             */
13431   #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field.                             */
13432   #define COMP_INTENCLR_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
13433   #define COMP_INTENCLR_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
13434   #define COMP_INTENCLR_READY_Clear (0x1UL)          /*!< Disable                                                              */
13435   #define COMP_INTENCLR_READY_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
13436   #define COMP_INTENCLR_READY_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
13437 
13438 /* DOWN @Bit 1 : Write '1' to disable interrupt for event DOWN */
13439   #define COMP_INTENCLR_DOWN_Pos (1UL)               /*!< Position of DOWN field.                                              */
13440   #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field.                                */
13441   #define COMP_INTENCLR_DOWN_Min (0x0UL)             /*!< Min enumerator value of DOWN field.                                  */
13442   #define COMP_INTENCLR_DOWN_Max (0x1UL)             /*!< Max enumerator value of DOWN field.                                  */
13443   #define COMP_INTENCLR_DOWN_Clear (0x1UL)           /*!< Disable                                                              */
13444   #define COMP_INTENCLR_DOWN_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
13445   #define COMP_INTENCLR_DOWN_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
13446 
13447 /* UP @Bit 2 : Write '1' to disable interrupt for event UP */
13448   #define COMP_INTENCLR_UP_Pos (2UL)                 /*!< Position of UP field.                                                */
13449   #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field.                                      */
13450   #define COMP_INTENCLR_UP_Min (0x0UL)               /*!< Min enumerator value of UP field.                                    */
13451   #define COMP_INTENCLR_UP_Max (0x1UL)               /*!< Max enumerator value of UP field.                                    */
13452   #define COMP_INTENCLR_UP_Clear (0x1UL)             /*!< Disable                                                              */
13453   #define COMP_INTENCLR_UP_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
13454   #define COMP_INTENCLR_UP_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
13455 
13456 /* CROSS @Bit 3 : Write '1' to disable interrupt for event CROSS */
13457   #define COMP_INTENCLR_CROSS_Pos (3UL)              /*!< Position of CROSS field.                                             */
13458   #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field.                             */
13459   #define COMP_INTENCLR_CROSS_Min (0x0UL)            /*!< Min enumerator value of CROSS field.                                 */
13460   #define COMP_INTENCLR_CROSS_Max (0x1UL)            /*!< Max enumerator value of CROSS field.                                 */
13461   #define COMP_INTENCLR_CROSS_Clear (0x1UL)          /*!< Disable                                                              */
13462   #define COMP_INTENCLR_CROSS_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
13463   #define COMP_INTENCLR_CROSS_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
13464 
13465 
13466 /* COMP_RESULT: Compare result */
13467   #define COMP_RESULT_ResetValue (0x00000000UL)      /*!< Reset value of RESULT register.                                      */
13468 
13469 /* RESULT @Bit 0 : Result of last compare. Decision point SAMPLE task. */
13470   #define COMP_RESULT_RESULT_Pos (0UL)               /*!< Position of RESULT field.                                            */
13471   #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field.                              */
13472   #define COMP_RESULT_RESULT_Min (0x0UL)             /*!< Min enumerator value of RESULT field.                                */
13473   #define COMP_RESULT_RESULT_Max (0x1UL)             /*!< Max enumerator value of RESULT field.                                */
13474   #define COMP_RESULT_RESULT_Below (0x0UL)           /*!< Input voltage is below the threshold (VIN+ < VIN-)                   */
13475   #define COMP_RESULT_RESULT_Above (0x1UL)           /*!< Input voltage is above the threshold (VIN+ > VIN-)                   */
13476 
13477 
13478 /* COMP_ENABLE: COMP enable */
13479   #define COMP_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */
13480 
13481 /* ENABLE @Bits 0..1 : Enable or disable COMP */
13482   #define COMP_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
13483   #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
13484   #define COMP_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
13485   #define COMP_ENABLE_ENABLE_Max (0x2UL)             /*!< Max enumerator value of ENABLE field.                                */
13486   #define COMP_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable                                                              */
13487   #define COMP_ENABLE_ENABLE_Enabled (0x2UL)         /*!< Enable                                                               */
13488 
13489 
13490 /* COMP_PSEL: Pin select */
13491   #define COMP_PSEL_ResetValue (0x00000000UL)        /*!< Reset value of PSEL register.                                        */
13492 
13493 /* PSEL @Bits 0..3 : Analog pin select */
13494   #define COMP_PSEL_PSEL_Pos (0UL)                   /*!< Position of PSEL field.                                              */
13495   #define COMP_PSEL_PSEL_Msk (0xFUL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field.                                        */
13496   #define COMP_PSEL_PSEL_Min (0x0UL)                 /*!< Min enumerator value of PSEL field.                                  */
13497   #define COMP_PSEL_PSEL_Max (0x9UL)                 /*!< Max enumerator value of PSEL field.                                  */
13498   #define COMP_PSEL_PSEL_AnalogInput0 (0x0UL)        /*!< AIN0 selected as analog input                                        */
13499   #define COMP_PSEL_PSEL_AnalogInput1 (0x1UL)        /*!< AIN1 selected as analog input                                        */
13500   #define COMP_PSEL_PSEL_AnalogInput2 (0x2UL)        /*!< AIN2 selected as analog input                                        */
13501   #define COMP_PSEL_PSEL_AnalogInput3 (0x3UL)        /*!< AIN3 selected as analog input                                        */
13502   #define COMP_PSEL_PSEL_AnalogInput4 (0x4UL)        /*!< AIN4 selected as analog input                                        */
13503   #define COMP_PSEL_PSEL_AnalogInput5 (0x5UL)        /*!< AIN5 selected as analog input                                        */
13504   #define COMP_PSEL_PSEL_AnalogInput6 (0x6UL)        /*!< AIN6 selected as analog input                                        */
13505   #define COMP_PSEL_PSEL_AnalogInput7 (0x7UL)        /*!< AIN7 selected as analog input                                        */
13506   #define COMP_PSEL_PSEL_AnalogInput8 (0x8UL)        /*!< AIN8 selected as analog input                                        */
13507   #define COMP_PSEL_PSEL_AnalogInput9 (0x9UL)        /*!< AIN9 selected as analog input                                        */
13508 
13509 
13510 /* COMP_REFSEL: Reference source select for single-ended mode */
13511   #define COMP_REFSEL_ResetValue (0x00000004UL)      /*!< Reset value of REFSEL register.                                      */
13512 
13513 /* REFSEL @Bits 0..2 : Reference select */
13514   #define COMP_REFSEL_REFSEL_Pos (0UL)               /*!< Position of REFSEL field.                                            */
13515   #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field.                              */
13516   #define COMP_REFSEL_REFSEL_Min (0x0UL)             /*!< Min enumerator value of REFSEL field.                                */
13517   #define COMP_REFSEL_REFSEL_Max (0x5UL)             /*!< Max enumerator value of REFSEL field.                                */
13518   #define COMP_REFSEL_REFSEL_Int1V2 (0x0UL)          /*!< VREF = internal 1.2 V reference (AVDD_AO_1V8 >= 1.7 V)               */
13519   #define COMP_REFSEL_REFSEL_AVDDAO1V8 (0x4UL)       /*!< VREF = AVDD_AO_1V8                                                   */
13520   #define COMP_REFSEL_REFSEL_ARef (0x5UL)            /*!< VREF = AREF                                                          */
13521 
13522 
13523 /* COMP_EXTREFSEL: External reference select */
13524   #define COMP_EXTREFSEL_ResetValue (0x00000000UL)   /*!< Reset value of EXTREFSEL register.                                   */
13525 
13526 /* EXTREFSEL @Bits 0..3 : External analog reference select */
13527   #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL)         /*!< Position of EXTREFSEL field.                                         */
13528   #define COMP_EXTREFSEL_EXTREFSEL_Msk (0xFUL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field.               */
13529   #define COMP_EXTREFSEL_EXTREFSEL_Min (0x0UL)       /*!< Min enumerator value of EXTREFSEL field.                             */
13530   #define COMP_EXTREFSEL_EXTREFSEL_Max (0x9UL)       /*!< Max enumerator value of EXTREFSEL field.                             */
13531   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0x0UL) /*!< Use AIN0 as external analog reference                         */
13532   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (0x1UL) /*!< Use AIN1 as external analog reference                         */
13533   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (0x2UL) /*!< Use AIN2 as external analog reference                         */
13534   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (0x3UL) /*!< Use AIN3 as external analog reference                         */
13535   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (0x4UL) /*!< Use AIN4 as external analog reference                         */
13536   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (0x5UL) /*!< Use AIN5 as external analog reference                         */
13537   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (0x6UL) /*!< Use AIN6 as external analog reference                         */
13538   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (0x7UL) /*!< Use AIN7 as external analog reference                         */
13539   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference8 (0x8UL) /*!< Use AIN8 as external analog reference                         */
13540   #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference9 (0x9UL) /*!< Use AIN9 as external analog reference                         */
13541 
13542 
13543 /* COMP_CONFIGVOLTLVL: Configure voltage level for analog input */
13544   #define COMP_CONFIGVOLTLVL_ResetValue (0x00000000UL) /*!< Reset value of CONFIGVOLTLVL register.                             */
13545 
13546 /* EN @Bit 0 : Enable 3.3V on analog input */
13547   #define COMP_CONFIGVOLTLVL_EN_Pos (0UL)            /*!< Position of EN field.                                                */
13548   #define COMP_CONFIGVOLTLVL_EN_Msk (0x1UL << COMP_CONFIGVOLTLVL_EN_Pos) /*!< Bit mask of EN field.                            */
13549   #define COMP_CONFIGVOLTLVL_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
13550   #define COMP_CONFIGVOLTLVL_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
13551   #define COMP_CONFIGVOLTLVL_EN_Disable (0x0UL)      /*!< Disable                                                              */
13552   #define COMP_CONFIGVOLTLVL_EN_Enable (0x1UL)       /*!< Enable                                                               */
13553 
13554 
13555 /* COMP_TH: Threshold configuration for hysteresis unit */
13556   #define COMP_TH_ResetValue (0x00002020UL)          /*!< Reset value of TH register.                                          */
13557 
13558 /* THDOWN @Bits 0..5 : VDOWN = (THDOWN+1)/64*VREF */
13559   #define COMP_TH_THDOWN_Pos (0UL)                   /*!< Position of THDOWN field.                                            */
13560   #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field.                                     */
13561   #define COMP_TH_THDOWN_Min (0x0UL)                 /*!< Min value of THDOWN field.                                           */
13562   #define COMP_TH_THDOWN_Max (0x3FUL)                /*!< Max size of THDOWN field.                                            */
13563 
13564 /* THUP @Bits 8..13 : VUP = (THUP+1)/64*VREF */
13565   #define COMP_TH_THUP_Pos (8UL)                     /*!< Position of THUP field.                                              */
13566   #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field.                                           */
13567   #define COMP_TH_THUP_Min (0x0UL)                   /*!< Min value of THUP field.                                             */
13568   #define COMP_TH_THUP_Max (0x3FUL)                  /*!< Max size of THUP field.                                              */
13569 
13570 
13571 /* COMP_MODE: Mode configuration */
13572   #define COMP_MODE_ResetValue (0x00000000UL)        /*!< Reset value of MODE register.                                        */
13573 
13574 /* SP @Bit 0 : Speed and power modes */
13575   #define COMP_MODE_SP_Pos (0UL)                     /*!< Position of SP field.                                                */
13576   #define COMP_MODE_SP_Msk (0x1UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field.                                              */
13577   #define COMP_MODE_SP_Min (0x0UL)                   /*!< Min enumerator value of SP field.                                    */
13578   #define COMP_MODE_SP_Max (0x1UL)                   /*!< Max enumerator value of SP field.                                    */
13579   #define COMP_MODE_SP_Low (0x0UL)                   /*!< Low-power mode                                                       */
13580   #define COMP_MODE_SP_High (0x1UL)                  /*!< High-speed mode                                                      */
13581 
13582 /* MAIN @Bit 8 : Main operation modes */
13583   #define COMP_MODE_MAIN_Pos (8UL)                   /*!< Position of MAIN field.                                              */
13584   #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field.                                        */
13585   #define COMP_MODE_MAIN_Min (0x0UL)                 /*!< Min enumerator value of MAIN field.                                  */
13586   #define COMP_MODE_MAIN_Max (0x1UL)                 /*!< Max enumerator value of MAIN field.                                  */
13587   #define COMP_MODE_MAIN_SE (0x0UL)                  /*!< Single-ended mode                                                    */
13588   #define COMP_MODE_MAIN_Diff (0x1UL)                /*!< Differential mode                                                    */
13589 
13590 
13591 /* COMP_HYST: Comparator hysteresis enable */
13592   #define COMP_HYST_ResetValue (0x00000000UL)        /*!< Reset value of HYST register.                                        */
13593 
13594 /* HYST @Bit 0 : Comparator hysteresis */
13595   #define COMP_HYST_HYST_Pos (0UL)                   /*!< Position of HYST field.                                              */
13596   #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field.                                        */
13597   #define COMP_HYST_HYST_Min (0x0UL)                 /*!< Min enumerator value of HYST field.                                  */
13598   #define COMP_HYST_HYST_Max (0x1UL)                 /*!< Max enumerator value of HYST field.                                  */
13599   #define COMP_HYST_HYST_NoHyst (0x0UL)              /*!< Comparator hysteresis disabled                                       */
13600   #define COMP_HYST_HYST_Hyst40mV (0x1UL)            /*!< Comparator hysteresis enabled                                        */
13601 
13602 
13603 /* COMP_ISOURCE: Current source select on analog input */
13604   #define COMP_ISOURCE_ResetValue (0x00000000UL)     /*!< Reset value of ISOURCE register.                                     */
13605 
13606 /* ISOURCE @Bits 0..1 : Current source select on analog input */
13607   #define COMP_ISOURCE_ISOURCE_Pos (0UL)             /*!< Position of ISOURCE field.                                           */
13608   #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field.                         */
13609   #define COMP_ISOURCE_ISOURCE_Min (0x0UL)           /*!< Min enumerator value of ISOURCE field.                               */
13610   #define COMP_ISOURCE_ISOURCE_Max (0x3UL)           /*!< Max enumerator value of ISOURCE field.                               */
13611   #define COMP_ISOURCE_ISOURCE_Off (0x0UL)           /*!< Current source disabled                                              */
13612   #define COMP_ISOURCE_ISOURCE_Ien2uA5 (0x1UL)       /*!< Current source enabled (+/- 2.5 uA)                                  */
13613   #define COMP_ISOURCE_ISOURCE_Ien5uA (0x2UL)        /*!< Current source enabled (+/- 5 uA)                                    */
13614   #define COMP_ISOURCE_ISOURCE_Ien10uA (0x3UL)       /*!< Current source enabled (+/- 10 uA)                                   */
13615 
13616 
13617 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
13618 
13619 /* =========================================================================================================================== */
13620 /* ================                                            CTI                                            ================ */
13621 /* =========================================================================================================================== */
13622 
13623 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
13624 /* ======================================================= Struct CTI ======================================================== */
13625 /**
13626   * @brief Cross-Trigger Interface control
13627   */
13628   typedef struct {                                   /*!< CTI Structure                                                        */
13629     __IOM uint32_t CTICONTROL;                       /*!< (@ 0x00000000) CTI Control register                                  */
13630     __IM uint32_t RESERVED[3];
13631     __OM uint32_t CTIINTACK;                         /*!< (@ 0x00000010) CTI Interrupt Acknowledge register                    */
13632     __IOM uint32_t CTIAPPSET;                        /*!< (@ 0x00000014) CTI Application Trigger Set register                  */
13633     __OM uint32_t CTIAPPCLEAR;                       /*!< (@ 0x00000018) CTI Application Trigger Clear register                */
13634     __OM uint32_t CTIAPPPULSE;                       /*!< (@ 0x0000001C) CTI Application Pulse register                        */
13635     __IOM uint32_t CTIINEN[8];                       /*!< (@ 0x00000020) CTI Trigger to Channel Enable register                */
13636     __IM uint32_t RESERVED1[24];
13637     __IOM uint32_t CTIOUTEN[8];                      /*!< (@ 0x000000A0) CTI Channel to Trigger Enable register                */
13638     __IM uint32_t RESERVED2[28];
13639     __IM uint32_t CTITRIGINSTATUS;                   /*!< (@ 0x00000130) CTI Trigger In Status register                        */
13640     __IM uint32_t CTITRIGOUTSTATUS;                  /*!< (@ 0x00000134) CTI Trigger Out Status register                       */
13641     __IM uint32_t CTICHINSTATUS;                     /*!< (@ 0x00000138) CTI Channel In Status register                        */
13642     __IM uint32_t RESERVED3;
13643     __IOM uint32_t CTIGATE;                          /*!< (@ 0x00000140) Enable CTI Channel Gate register                      */
13644     __IM uint32_t RESERVED4[926];
13645     __IM uint32_t DEVARCH;                           /*!< (@ 0x00000FBC) Device Architecture register                          */
13646     __IM uint32_t RESERVED5[2];
13647     __IM uint32_t DEVID;                             /*!< (@ 0x00000FC8) Device Configuration register                         */
13648     __IM uint32_t DEVTYPE;                           /*!< (@ 0x00000FCC) Device Type Identifier register                       */
13649     __IM uint32_t PIDR4;                             /*!< (@ 0x00000FD0) Peripheral ID4 Register                               */
13650     __IM uint32_t PIDR5;                             /*!< (@ 0x00000FD4) Peripheral ID5 register                               */
13651     __IM uint32_t PIDR6;                             /*!< (@ 0x00000FD8) Peripheral ID6 register                               */
13652     __IM uint32_t PIDR7;                             /*!< (@ 0x00000FDC) Peripheral ID7 register                               */
13653     __IM uint32_t PIDR0;                             /*!< (@ 0x00000FE0) Peripheral ID0 Register                               */
13654     __IM uint32_t PIDR1;                             /*!< (@ 0x00000FE4) Peripheral ID1 Register                               */
13655     __IM uint32_t PIDR2;                             /*!< (@ 0x00000FE8) Peripheral ID2 Register                               */
13656     __IM uint32_t PIDR3;                             /*!< (@ 0x00000FEC) Peripheral ID3 Register                               */
13657     __IM uint32_t CIDR0;                             /*!< (@ 0x00000FF0) Component ID0 Register                                */
13658     __IM uint32_t CIDR1;                             /*!< (@ 0x00000FF4) Component ID1 Register                                */
13659     __IM uint32_t CIDR2;                             /*!< (@ 0x00000FF8) Component ID2 Register                                */
13660     __IM uint32_t CIDR3;                             /*!< (@ 0x00000FFC) Component ID3 Register                                */
13661   } NRF_CTI_Type;                                    /*!< Size = 4096 (0x1000)                                                 */
13662 
13663 /* CTI_CTICONTROL: CTI Control register */
13664   #define CTI_CTICONTROL_ResetValue (0x00000000UL)   /*!< Reset value of CTICONTROL register.                                  */
13665 
13666 /* GLBEN @Bit 0 : Enables or disables the CTI. */
13667   #define CTI_CTICONTROL_GLBEN_Pos (0UL)             /*!< Position of GLBEN field.                                             */
13668   #define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos) /*!< Bit mask of GLBEN field.                           */
13669   #define CTI_CTICONTROL_GLBEN_Min (0x0UL)           /*!< Min enumerator value of GLBEN field.                                 */
13670   #define CTI_CTICONTROL_GLBEN_Max (0x1UL)           /*!< Max enumerator value of GLBEN field.                                 */
13671   #define CTI_CTICONTROL_GLBEN_Disabled (0x0UL)      /*!< All cross-triggering mapping logic functionality is disabled.        */
13672   #define CTI_CTICONTROL_GLBEN_Enabled (0x1UL)       /*!< Cross-triggering mapping logic functionality is enabled.             */
13673 
13674 
13675 /* CTI_CTIINTACK: CTI Interrupt Acknowledge register */
13676   #define CTI_CTIINTACK_ResetValue (0x00000000UL)    /*!< Reset value of CTIINTACK register.                                   */
13677 
13678 /* INTACK0 @Bit 0 : Acknowledges the ctitrigout 0 output. */
13679   #define CTI_CTIINTACK_INTACK0_Pos (0UL)            /*!< Position of INTACK0 field.                                           */
13680   #define CTI_CTIINTACK_INTACK0_Msk (0x1UL << CTI_CTIINTACK_INTACK0_Pos) /*!< Bit mask of INTACK0 field.                       */
13681   #define CTI_CTIINTACK_INTACK0_Min (0x1UL)          /*!< Min enumerator value of INTACK0 field.                               */
13682   #define CTI_CTIINTACK_INTACK0_Max (0x1UL)          /*!< Max enumerator value of INTACK0 field.                               */
13683   #define CTI_CTIINTACK_INTACK0_Acknowledge (0x1UL)  /*!< Clears the ctitrigout.                                               */
13684 
13685 /* INTACK1 @Bit 1 : Acknowledges the ctitrigout 1 output. */
13686   #define CTI_CTIINTACK_INTACK1_Pos (1UL)            /*!< Position of INTACK1 field.                                           */
13687   #define CTI_CTIINTACK_INTACK1_Msk (0x1UL << CTI_CTIINTACK_INTACK1_Pos) /*!< Bit mask of INTACK1 field.                       */
13688   #define CTI_CTIINTACK_INTACK1_Min (0x1UL)          /*!< Min enumerator value of INTACK1 field.                               */
13689   #define CTI_CTIINTACK_INTACK1_Max (0x1UL)          /*!< Max enumerator value of INTACK1 field.                               */
13690   #define CTI_CTIINTACK_INTACK1_Acknowledge (0x1UL)  /*!< Clears the ctitrigout.                                               */
13691 
13692 /* INTACK2 @Bit 2 : Acknowledges the ctitrigout 2 output. */
13693   #define CTI_CTIINTACK_INTACK2_Pos (2UL)            /*!< Position of INTACK2 field.                                           */
13694   #define CTI_CTIINTACK_INTACK2_Msk (0x1UL << CTI_CTIINTACK_INTACK2_Pos) /*!< Bit mask of INTACK2 field.                       */
13695   #define CTI_CTIINTACK_INTACK2_Min (0x1UL)          /*!< Min enumerator value of INTACK2 field.                               */
13696   #define CTI_CTIINTACK_INTACK2_Max (0x1UL)          /*!< Max enumerator value of INTACK2 field.                               */
13697   #define CTI_CTIINTACK_INTACK2_Acknowledge (0x1UL)  /*!< Clears the ctitrigout.                                               */
13698 
13699 /* INTACK3 @Bit 3 : Acknowledges the ctitrigout 3 output. */
13700   #define CTI_CTIINTACK_INTACK3_Pos (3UL)            /*!< Position of INTACK3 field.                                           */
13701   #define CTI_CTIINTACK_INTACK3_Msk (0x1UL << CTI_CTIINTACK_INTACK3_Pos) /*!< Bit mask of INTACK3 field.                       */
13702   #define CTI_CTIINTACK_INTACK3_Min (0x1UL)          /*!< Min enumerator value of INTACK3 field.                               */
13703   #define CTI_CTIINTACK_INTACK3_Max (0x1UL)          /*!< Max enumerator value of INTACK3 field.                               */
13704   #define CTI_CTIINTACK_INTACK3_Acknowledge (0x1UL)  /*!< Clears the ctitrigout.                                               */
13705 
13706 /* INTACK4 @Bit 4 : Acknowledges the ctitrigout 4 output. */
13707   #define CTI_CTIINTACK_INTACK4_Pos (4UL)            /*!< Position of INTACK4 field.                                           */
13708   #define CTI_CTIINTACK_INTACK4_Msk (0x1UL << CTI_CTIINTACK_INTACK4_Pos) /*!< Bit mask of INTACK4 field.                       */
13709   #define CTI_CTIINTACK_INTACK4_Min (0x1UL)          /*!< Min enumerator value of INTACK4 field.                               */
13710   #define CTI_CTIINTACK_INTACK4_Max (0x1UL)          /*!< Max enumerator value of INTACK4 field.                               */
13711   #define CTI_CTIINTACK_INTACK4_Acknowledge (0x1UL)  /*!< Clears the ctitrigout.                                               */
13712 
13713 /* INTACK5 @Bit 5 : Acknowledges the ctitrigout 5 output. */
13714   #define CTI_CTIINTACK_INTACK5_Pos (5UL)            /*!< Position of INTACK5 field.                                           */
13715   #define CTI_CTIINTACK_INTACK5_Msk (0x1UL << CTI_CTIINTACK_INTACK5_Pos) /*!< Bit mask of INTACK5 field.                       */
13716   #define CTI_CTIINTACK_INTACK5_Min (0x1UL)          /*!< Min enumerator value of INTACK5 field.                               */
13717   #define CTI_CTIINTACK_INTACK5_Max (0x1UL)          /*!< Max enumerator value of INTACK5 field.                               */
13718   #define CTI_CTIINTACK_INTACK5_Acknowledge (0x1UL)  /*!< Clears the ctitrigout.                                               */
13719 
13720 /* INTACK6 @Bit 6 : Acknowledges the ctitrigout 6 output. */
13721   #define CTI_CTIINTACK_INTACK6_Pos (6UL)            /*!< Position of INTACK6 field.                                           */
13722   #define CTI_CTIINTACK_INTACK6_Msk (0x1UL << CTI_CTIINTACK_INTACK6_Pos) /*!< Bit mask of INTACK6 field.                       */
13723   #define CTI_CTIINTACK_INTACK6_Min (0x1UL)          /*!< Min enumerator value of INTACK6 field.                               */
13724   #define CTI_CTIINTACK_INTACK6_Max (0x1UL)          /*!< Max enumerator value of INTACK6 field.                               */
13725   #define CTI_CTIINTACK_INTACK6_Acknowledge (0x1UL)  /*!< Clears the ctitrigout.                                               */
13726 
13727 /* INTACK7 @Bit 7 : Acknowledges the ctitrigout 7 output. */
13728   #define CTI_CTIINTACK_INTACK7_Pos (7UL)            /*!< Position of INTACK7 field.                                           */
13729   #define CTI_CTIINTACK_INTACK7_Msk (0x1UL << CTI_CTIINTACK_INTACK7_Pos) /*!< Bit mask of INTACK7 field.                       */
13730   #define CTI_CTIINTACK_INTACK7_Min (0x1UL)          /*!< Min enumerator value of INTACK7 field.                               */
13731   #define CTI_CTIINTACK_INTACK7_Max (0x1UL)          /*!< Max enumerator value of INTACK7 field.                               */
13732   #define CTI_CTIINTACK_INTACK7_Acknowledge (0x1UL)  /*!< Clears the ctitrigout.                                               */
13733 
13734 
13735 /* CTI_CTIAPPSET: CTI Application Trigger Set register */
13736   #define CTI_CTIAPPSET_ResetValue (0x00000000UL)    /*!< Reset value of CTIAPPSET register.                                   */
13737 
13738 /* APPSET0 @Bit 0 : Application trigger event for channel 0. */
13739   #define CTI_CTIAPPSET_APPSET0_Pos (0UL)            /*!< Position of APPSET0 field.                                           */
13740   #define CTI_CTIAPPSET_APPSET0_Msk (0x1UL << CTI_CTIAPPSET_APPSET0_Pos) /*!< Bit mask of APPSET0 field.                       */
13741   #define CTI_CTIAPPSET_APPSET0_Min (0x0UL)          /*!< Min enumerator value of APPSET0 field.                               */
13742   #define CTI_CTIAPPSET_APPSET0_Max (0x1UL)          /*!< Max enumerator value of APPSET0 field.                               */
13743   #define CTI_CTIAPPSET_APPSET0_Inactive (0x0UL)     /*!< Application trigger 0 is inactive.                                   */
13744   #define CTI_CTIAPPSET_APPSET0_Active (0x1UL)       /*!< Application trigger 0 is active.                                     */
13745   #define CTI_CTIAPPSET_APPSET0_Activate (0x1UL)     /*!< Generate channel event for channel 0.                                */
13746 
13747 /* APPSET1 @Bit 1 : Application trigger event for channel 1. */
13748   #define CTI_CTIAPPSET_APPSET1_Pos (1UL)            /*!< Position of APPSET1 field.                                           */
13749   #define CTI_CTIAPPSET_APPSET1_Msk (0x1UL << CTI_CTIAPPSET_APPSET1_Pos) /*!< Bit mask of APPSET1 field.                       */
13750   #define CTI_CTIAPPSET_APPSET1_Min (0x0UL)          /*!< Min enumerator value of APPSET1 field.                               */
13751   #define CTI_CTIAPPSET_APPSET1_Max (0x1UL)          /*!< Max enumerator value of APPSET1 field.                               */
13752   #define CTI_CTIAPPSET_APPSET1_Inactive (0x0UL)     /*!< Application trigger 1 is inactive.                                   */
13753   #define CTI_CTIAPPSET_APPSET1_Active (0x1UL)       /*!< Application trigger 1 is active.                                     */
13754   #define CTI_CTIAPPSET_APPSET1_Activate (0x1UL)     /*!< Generate channel event for channel 1.                                */
13755 
13756 /* APPSET2 @Bit 2 : Application trigger event for channel 2. */
13757   #define CTI_CTIAPPSET_APPSET2_Pos (2UL)            /*!< Position of APPSET2 field.                                           */
13758   #define CTI_CTIAPPSET_APPSET2_Msk (0x1UL << CTI_CTIAPPSET_APPSET2_Pos) /*!< Bit mask of APPSET2 field.                       */
13759   #define CTI_CTIAPPSET_APPSET2_Min (0x0UL)          /*!< Min enumerator value of APPSET2 field.                               */
13760   #define CTI_CTIAPPSET_APPSET2_Max (0x1UL)          /*!< Max enumerator value of APPSET2 field.                               */
13761   #define CTI_CTIAPPSET_APPSET2_Inactive (0x0UL)     /*!< Application trigger 2 is inactive.                                   */
13762   #define CTI_CTIAPPSET_APPSET2_Active (0x1UL)       /*!< Application trigger 2 is active.                                     */
13763   #define CTI_CTIAPPSET_APPSET2_Activate (0x1UL)     /*!< Generate channel event for channel 2.                                */
13764 
13765 /* APPSET3 @Bit 3 : Application trigger event for channel 3. */
13766   #define CTI_CTIAPPSET_APPSET3_Pos (3UL)            /*!< Position of APPSET3 field.                                           */
13767   #define CTI_CTIAPPSET_APPSET3_Msk (0x1UL << CTI_CTIAPPSET_APPSET3_Pos) /*!< Bit mask of APPSET3 field.                       */
13768   #define CTI_CTIAPPSET_APPSET3_Min (0x0UL)          /*!< Min enumerator value of APPSET3 field.                               */
13769   #define CTI_CTIAPPSET_APPSET3_Max (0x1UL)          /*!< Max enumerator value of APPSET3 field.                               */
13770   #define CTI_CTIAPPSET_APPSET3_Inactive (0x0UL)     /*!< Application trigger 3 is inactive.                                   */
13771   #define CTI_CTIAPPSET_APPSET3_Active (0x1UL)       /*!< Application trigger 3 is active.                                     */
13772   #define CTI_CTIAPPSET_APPSET3_Activate (0x1UL)     /*!< Generate channel event for channel 3.                                */
13773 
13774 
13775 /* CTI_CTIAPPCLEAR: CTI Application Trigger Clear register */
13776   #define CTI_CTIAPPCLEAR_ResetValue (0x00000000UL)  /*!< Reset value of CTIAPPCLEAR register.                                 */
13777 
13778 /* APPCLEAR0 @Bit 0 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
13779   #define CTI_CTIAPPCLEAR_APPCLEAR0_Pos (0UL)        /*!< Position of APPCLEAR0 field.                                         */
13780   #define CTI_CTIAPPCLEAR_APPCLEAR0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR0_Pos) /*!< Bit mask of APPCLEAR0 field.             */
13781   #define CTI_CTIAPPCLEAR_APPCLEAR0_Min (0x1UL)      /*!< Min enumerator value of APPCLEAR0 field.                             */
13782   #define CTI_CTIAPPCLEAR_APPCLEAR0_Max (0x1UL)      /*!< Max enumerator value of APPCLEAR0 field.                             */
13783   #define CTI_CTIAPPCLEAR_APPCLEAR0_Clear (0x1UL)    /*!< Clears the event for channel 0.                                      */
13784 
13785 /* APPCLEAR1 @Bit 1 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
13786   #define CTI_CTIAPPCLEAR_APPCLEAR1_Pos (1UL)        /*!< Position of APPCLEAR1 field.                                         */
13787   #define CTI_CTIAPPCLEAR_APPCLEAR1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR1_Pos) /*!< Bit mask of APPCLEAR1 field.             */
13788   #define CTI_CTIAPPCLEAR_APPCLEAR1_Min (0x1UL)      /*!< Min enumerator value of APPCLEAR1 field.                             */
13789   #define CTI_CTIAPPCLEAR_APPCLEAR1_Max (0x1UL)      /*!< Max enumerator value of APPCLEAR1 field.                             */
13790   #define CTI_CTIAPPCLEAR_APPCLEAR1_Clear (0x1UL)    /*!< Clears the event for channel 1.                                      */
13791 
13792 /* APPCLEAR2 @Bit 2 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
13793   #define CTI_CTIAPPCLEAR_APPCLEAR2_Pos (2UL)        /*!< Position of APPCLEAR2 field.                                         */
13794   #define CTI_CTIAPPCLEAR_APPCLEAR2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR2_Pos) /*!< Bit mask of APPCLEAR2 field.             */
13795   #define CTI_CTIAPPCLEAR_APPCLEAR2_Min (0x1UL)      /*!< Min enumerator value of APPCLEAR2 field.                             */
13796   #define CTI_CTIAPPCLEAR_APPCLEAR2_Max (0x1UL)      /*!< Max enumerator value of APPCLEAR2 field.                             */
13797   #define CTI_CTIAPPCLEAR_APPCLEAR2_Clear (0x1UL)    /*!< Clears the event for channel 2.                                      */
13798 
13799 /* APPCLEAR3 @Bit 3 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */
13800   #define CTI_CTIAPPCLEAR_APPCLEAR3_Pos (3UL)        /*!< Position of APPCLEAR3 field.                                         */
13801   #define CTI_CTIAPPCLEAR_APPCLEAR3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR3_Pos) /*!< Bit mask of APPCLEAR3 field.             */
13802   #define CTI_CTIAPPCLEAR_APPCLEAR3_Min (0x1UL)      /*!< Min enumerator value of APPCLEAR3 field.                             */
13803   #define CTI_CTIAPPCLEAR_APPCLEAR3_Max (0x1UL)      /*!< Max enumerator value of APPCLEAR3 field.                             */
13804   #define CTI_CTIAPPCLEAR_APPCLEAR3_Clear (0x1UL)    /*!< Clears the event for channel 3.                                      */
13805 
13806 
13807 /* CTI_CTIAPPPULSE: CTI Application Pulse register */
13808   #define CTI_CTIAPPPULSE_ResetValue (0x00000000UL)  /*!< Reset value of CTIAPPPULSE register.                                 */
13809 
13810 /* APPULSE0 @Bit 0 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the
13811                      register for each channel. */
13812 
13813   #define CTI_CTIAPPPULSE_APPULSE0_Pos (0UL)         /*!< Position of APPULSE0 field.                                          */
13814   #define CTI_CTIAPPPULSE_APPULSE0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE0_Pos) /*!< Bit mask of APPULSE0 field.                */
13815   #define CTI_CTIAPPPULSE_APPULSE0_Min (0x1UL)       /*!< Min enumerator value of APPULSE0 field.                              */
13816   #define CTI_CTIAPPPULSE_APPULSE0_Max (0x1UL)       /*!< Max enumerator value of APPULSE0 field.                              */
13817   #define CTI_CTIAPPPULSE_APPULSE0_Generate (0x1UL)  /*!< Generates an event pulse on channel 0.                               */
13818 
13819 /* APPULSE1 @Bit 1 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the
13820                      register for each channel. */
13821 
13822   #define CTI_CTIAPPPULSE_APPULSE1_Pos (1UL)         /*!< Position of APPULSE1 field.                                          */
13823   #define CTI_CTIAPPPULSE_APPULSE1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE1_Pos) /*!< Bit mask of APPULSE1 field.                */
13824   #define CTI_CTIAPPPULSE_APPULSE1_Min (0x1UL)       /*!< Min enumerator value of APPULSE1 field.                              */
13825   #define CTI_CTIAPPPULSE_APPULSE1_Max (0x1UL)       /*!< Max enumerator value of APPULSE1 field.                              */
13826   #define CTI_CTIAPPPULSE_APPULSE1_Generate (0x1UL)  /*!< Generates an event pulse on channel 1.                               */
13827 
13828 /* APPULSE2 @Bit 2 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the
13829                      register for each channel. */
13830 
13831   #define CTI_CTIAPPPULSE_APPULSE2_Pos (2UL)         /*!< Position of APPULSE2 field.                                          */
13832   #define CTI_CTIAPPPULSE_APPULSE2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE2_Pos) /*!< Bit mask of APPULSE2 field.                */
13833   #define CTI_CTIAPPPULSE_APPULSE2_Min (0x1UL)       /*!< Min enumerator value of APPULSE2 field.                              */
13834   #define CTI_CTIAPPPULSE_APPULSE2_Max (0x1UL)       /*!< Max enumerator value of APPULSE2 field.                              */
13835   #define CTI_CTIAPPPULSE_APPULSE2_Generate (0x1UL)  /*!< Generates an event pulse on channel 2.                               */
13836 
13837 /* APPULSE3 @Bit 3 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the
13838                      register for each channel. */
13839 
13840   #define CTI_CTIAPPPULSE_APPULSE3_Pos (3UL)         /*!< Position of APPULSE3 field.                                          */
13841   #define CTI_CTIAPPPULSE_APPULSE3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE3_Pos) /*!< Bit mask of APPULSE3 field.                */
13842   #define CTI_CTIAPPPULSE_APPULSE3_Min (0x1UL)       /*!< Min enumerator value of APPULSE3 field.                              */
13843   #define CTI_CTIAPPPULSE_APPULSE3_Max (0x1UL)       /*!< Max enumerator value of APPULSE3 field.                              */
13844   #define CTI_CTIAPPPULSE_APPULSE3_Generate (0x1UL)  /*!< Generates an event pulse on channel 3.                               */
13845 
13846 
13847 /* CTI_CTIINEN: CTI Trigger to Channel Enable register */
13848   #define CTI_CTIINEN_MaxCount (8UL)                 /*!< Max size of CTIINEN[8] array.                                        */
13849   #define CTI_CTIINEN_MaxIndex (7UL)                 /*!< Max index of CTIINEN[8] array.                                       */
13850   #define CTI_CTIINEN_MinIndex (0UL)                 /*!< Min index of CTIINEN[8] array.                                       */
13851   #define CTI_CTIINEN_ResetValue (0x00000000UL)      /*!< Reset value of CTIINEN[8] register.                                  */
13852 
13853 /* TRIGINEN0 @Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated. */
13854   #define CTI_CTIINEN_TRIGINEN0_Pos (0UL)            /*!< Position of TRIGINEN0 field.                                         */
13855   #define CTI_CTIINEN_TRIGINEN0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN0_Pos) /*!< Bit mask of TRIGINEN0 field.                     */
13856   #define CTI_CTIINEN_TRIGINEN0_Min (0x0UL)          /*!< Min enumerator value of TRIGINEN0 field.                             */
13857   #define CTI_CTIINEN_TRIGINEN0_Max (0x1UL)          /*!< Max enumerator value of TRIGINEN0 field.                             */
13858   #define CTI_CTIINEN_TRIGINEN0_Disabled (0x0UL)     /*!< Input trigger n events are ignored by channel 0.                     */
13859   #define CTI_CTIINEN_TRIGINEN0_Enabled (0x1UL)      /*!< When an event is received on input trigger n (ctitrigin[n]), generate
13860                                                           an event on channel 0.*/
13861 
13862 /* TRIGINEN1 @Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated. */
13863   #define CTI_CTIINEN_TRIGINEN1_Pos (1UL)            /*!< Position of TRIGINEN1 field.                                         */
13864   #define CTI_CTIINEN_TRIGINEN1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN1_Pos) /*!< Bit mask of TRIGINEN1 field.                     */
13865   #define CTI_CTIINEN_TRIGINEN1_Min (0x0UL)          /*!< Min enumerator value of TRIGINEN1 field.                             */
13866   #define CTI_CTIINEN_TRIGINEN1_Max (0x1UL)          /*!< Max enumerator value of TRIGINEN1 field.                             */
13867   #define CTI_CTIINEN_TRIGINEN1_Disabled (0x0UL)     /*!< Input trigger n events are ignored by channel 1.                     */
13868   #define CTI_CTIINEN_TRIGINEN1_Enabled (0x1UL)      /*!< When an event is received on input trigger n (ctitrigin[n]), generate
13869                                                           an event on channel 1.*/
13870 
13871 /* TRIGINEN2 @Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated. */
13872   #define CTI_CTIINEN_TRIGINEN2_Pos (2UL)            /*!< Position of TRIGINEN2 field.                                         */
13873   #define CTI_CTIINEN_TRIGINEN2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN2_Pos) /*!< Bit mask of TRIGINEN2 field.                     */
13874   #define CTI_CTIINEN_TRIGINEN2_Min (0x0UL)          /*!< Min enumerator value of TRIGINEN2 field.                             */
13875   #define CTI_CTIINEN_TRIGINEN2_Max (0x1UL)          /*!< Max enumerator value of TRIGINEN2 field.                             */
13876   #define CTI_CTIINEN_TRIGINEN2_Disabled (0x0UL)     /*!< Input trigger n events are ignored by channel 2.                     */
13877   #define CTI_CTIINEN_TRIGINEN2_Enabled (0x1UL)      /*!< When an event is received on input trigger n (ctitrigin[n]), generate
13878                                                           an event on channel 2.*/
13879 
13880 /* TRIGINEN3 @Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated. */
13881   #define CTI_CTIINEN_TRIGINEN3_Pos (3UL)            /*!< Position of TRIGINEN3 field.                                         */
13882   #define CTI_CTIINEN_TRIGINEN3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN3_Pos) /*!< Bit mask of TRIGINEN3 field.                     */
13883   #define CTI_CTIINEN_TRIGINEN3_Min (0x0UL)          /*!< Min enumerator value of TRIGINEN3 field.                             */
13884   #define CTI_CTIINEN_TRIGINEN3_Max (0x1UL)          /*!< Max enumerator value of TRIGINEN3 field.                             */
13885   #define CTI_CTIINEN_TRIGINEN3_Disabled (0x0UL)     /*!< Input trigger n events are ignored by channel 3.                     */
13886   #define CTI_CTIINEN_TRIGINEN3_Enabled (0x1UL)      /*!< When an event is received on input trigger n (ctitrigin[n]), generate
13887                                                           an event on channel 3.*/
13888 
13889 
13890 /* CTI_CTIOUTEN: CTI Channel to Trigger Enable register */
13891   #define CTI_CTIOUTEN_MaxCount (8UL)                /*!< Max size of CTIOUTEN[8] array.                                       */
13892   #define CTI_CTIOUTEN_MaxIndex (7UL)                /*!< Max index of CTIOUTEN[8] array.                                      */
13893   #define CTI_CTIOUTEN_MinIndex (0UL)                /*!< Min index of CTIOUTEN[8] array.                                      */
13894   #define CTI_CTIOUTEN_ResetValue (0x00000000UL)     /*!< Reset value of CTIOUTEN[8] register.                                 */
13895 
13896 /* TRIGOUTEN0 @Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 is activated. */
13897   #define CTI_CTIOUTEN_TRIGOUTEN0_Pos (0UL)          /*!< Position of TRIGOUTEN0 field.                                        */
13898   #define CTI_CTIOUTEN_TRIGOUTEN0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN0_Pos) /*!< Bit mask of TRIGOUTEN0 field.                */
13899   #define CTI_CTIOUTEN_TRIGOUTEN0_Min (0x0UL)        /*!< Min enumerator value of TRIGOUTEN0 field.                            */
13900   #define CTI_CTIOUTEN_TRIGOUTEN0_Max (0x1UL)        /*!< Max enumerator value of TRIGOUTEN0 field.                            */
13901   #define CTI_CTIOUTEN_TRIGOUTEN0_Disabled (0x0UL)   /*!< Channel 0 is ignored by output trigger n.                            */
13902   #define CTI_CTIOUTEN_TRIGOUTEN0_Enabled (0x1UL)    /*!< When an event occurs on channel 0, generate an event on output event n
13903                                                           (ctitrigout[n]).*/
13904 
13905 /* TRIGOUTEN1 @Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 is activated. */
13906   #define CTI_CTIOUTEN_TRIGOUTEN1_Pos (1UL)          /*!< Position of TRIGOUTEN1 field.                                        */
13907   #define CTI_CTIOUTEN_TRIGOUTEN1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN1_Pos) /*!< Bit mask of TRIGOUTEN1 field.                */
13908   #define CTI_CTIOUTEN_TRIGOUTEN1_Min (0x0UL)        /*!< Min enumerator value of TRIGOUTEN1 field.                            */
13909   #define CTI_CTIOUTEN_TRIGOUTEN1_Max (0x1UL)        /*!< Max enumerator value of TRIGOUTEN1 field.                            */
13910   #define CTI_CTIOUTEN_TRIGOUTEN1_Disabled (0x0UL)   /*!< Channel 1 is ignored by output trigger n.                            */
13911   #define CTI_CTIOUTEN_TRIGOUTEN1_Enabled (0x1UL)    /*!< When an event occurs on channel 1, generate an event on output event n
13912                                                           (ctitrigout[n]).*/
13913 
13914 /* TRIGOUTEN2 @Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 is activated. */
13915   #define CTI_CTIOUTEN_TRIGOUTEN2_Pos (2UL)          /*!< Position of TRIGOUTEN2 field.                                        */
13916   #define CTI_CTIOUTEN_TRIGOUTEN2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN2_Pos) /*!< Bit mask of TRIGOUTEN2 field.                */
13917   #define CTI_CTIOUTEN_TRIGOUTEN2_Min (0x0UL)        /*!< Min enumerator value of TRIGOUTEN2 field.                            */
13918   #define CTI_CTIOUTEN_TRIGOUTEN2_Max (0x1UL)        /*!< Max enumerator value of TRIGOUTEN2 field.                            */
13919   #define CTI_CTIOUTEN_TRIGOUTEN2_Disabled (0x0UL)   /*!< Channel 2 is ignored by output trigger n.                            */
13920   #define CTI_CTIOUTEN_TRIGOUTEN2_Enabled (0x1UL)    /*!< When an event occurs on channel 2, generate an event on output event n
13921                                                           (ctitrigout[n]).*/
13922 
13923 /* TRIGOUTEN3 @Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 is activated. */
13924   #define CTI_CTIOUTEN_TRIGOUTEN3_Pos (3UL)          /*!< Position of TRIGOUTEN3 field.                                        */
13925   #define CTI_CTIOUTEN_TRIGOUTEN3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN3_Pos) /*!< Bit mask of TRIGOUTEN3 field.                */
13926   #define CTI_CTIOUTEN_TRIGOUTEN3_Min (0x0UL)        /*!< Min enumerator value of TRIGOUTEN3 field.                            */
13927   #define CTI_CTIOUTEN_TRIGOUTEN3_Max (0x1UL)        /*!< Max enumerator value of TRIGOUTEN3 field.                            */
13928   #define CTI_CTIOUTEN_TRIGOUTEN3_Disabled (0x0UL)   /*!< Channel 3 is ignored by output trigger n.                            */
13929   #define CTI_CTIOUTEN_TRIGOUTEN3_Enabled (0x1UL)    /*!< When an event occurs on channel 3, generate an event on output event n
13930                                                           (ctitrigout[n]).*/
13931 
13932 
13933 /* CTI_CTITRIGINSTATUS: CTI Trigger In Status register */
13934   #define CTI_CTITRIGINSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CTITRIGINSTATUS register.                          */
13935 
13936 /* TRIGINSTATUS0 @Bit 0 : Shows the status of ctitrigin0 input. */
13937   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Pos (0UL) /*!< Position of TRIGINSTATUS0 field.                                    */
13938   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Pos) /*!< Bit mask of TRIGINSTATUS0
13939                                                                             field.*/
13940   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS0 field.                      */
13941   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS0 field.                      */
13942   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Active (0x1UL) /*!< Ctitrigin 0 is active.                                         */
13943   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS0_Inactive (0x0UL) /*!< Ctitrigin 0 is inactive.                                     */
13944 
13945 /* TRIGINSTATUS1 @Bit 1 : Shows the status of ctitrigin1 input. */
13946   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Pos (1UL) /*!< Position of TRIGINSTATUS1 field.                                    */
13947   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Pos) /*!< Bit mask of TRIGINSTATUS1
13948                                                                             field.*/
13949   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS1 field.                      */
13950   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS1 field.                      */
13951   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Active (0x1UL) /*!< Ctitrigin 1 is active.                                         */
13952   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS1_Inactive (0x0UL) /*!< Ctitrigin 1 is inactive.                                     */
13953 
13954 /* TRIGINSTATUS2 @Bit 2 : Shows the status of ctitrigin2 input. */
13955   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Pos (2UL) /*!< Position of TRIGINSTATUS2 field.                                    */
13956   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Pos) /*!< Bit mask of TRIGINSTATUS2
13957                                                                             field.*/
13958   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS2 field.                      */
13959   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS2 field.                      */
13960   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Active (0x1UL) /*!< Ctitrigin 2 is active.                                         */
13961   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS2_Inactive (0x0UL) /*!< Ctitrigin 2 is inactive.                                     */
13962 
13963 /* TRIGINSTATUS3 @Bit 3 : Shows the status of ctitrigin3 input. */
13964   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Pos (3UL) /*!< Position of TRIGINSTATUS3 field.                                    */
13965   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Pos) /*!< Bit mask of TRIGINSTATUS3
13966                                                                             field.*/
13967   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS3 field.                      */
13968   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS3 field.                      */
13969   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Active (0x1UL) /*!< Ctitrigin 3 is active.                                         */
13970   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS3_Inactive (0x0UL) /*!< Ctitrigin 3 is inactive.                                     */
13971 
13972 /* TRIGINSTATUS4 @Bit 4 : Shows the status of ctitrigin4 input. */
13973   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Pos (4UL) /*!< Position of TRIGINSTATUS4 field.                                    */
13974   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Pos) /*!< Bit mask of TRIGINSTATUS4
13975                                                                             field.*/
13976   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS4 field.                      */
13977   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS4 field.                      */
13978   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Active (0x1UL) /*!< Ctitrigin 4 is active.                                         */
13979   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS4_Inactive (0x0UL) /*!< Ctitrigin 4 is inactive.                                     */
13980 
13981 /* TRIGINSTATUS5 @Bit 5 : Shows the status of ctitrigin5 input. */
13982   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Pos (5UL) /*!< Position of TRIGINSTATUS5 field.                                    */
13983   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Pos) /*!< Bit mask of TRIGINSTATUS5
13984                                                                             field.*/
13985   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS5 field.                      */
13986   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS5 field.                      */
13987   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Active (0x1UL) /*!< Ctitrigin 5 is active.                                         */
13988   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS5_Inactive (0x0UL) /*!< Ctitrigin 5 is inactive.                                     */
13989 
13990 /* TRIGINSTATUS6 @Bit 6 : Shows the status of ctitrigin6 input. */
13991   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Pos (6UL) /*!< Position of TRIGINSTATUS6 field.                                    */
13992   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Pos) /*!< Bit mask of TRIGINSTATUS6
13993                                                                             field.*/
13994   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS6 field.                      */
13995   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS6 field.                      */
13996   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Active (0x1UL) /*!< Ctitrigin 6 is active.                                         */
13997   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS6_Inactive (0x0UL) /*!< Ctitrigin 6 is inactive.                                     */
13998 
13999 /* TRIGINSTATUS7 @Bit 7 : Shows the status of ctitrigin7 input. */
14000   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Pos (7UL) /*!< Position of TRIGINSTATUS7 field.                                    */
14001   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Msk (0x1UL << CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Pos) /*!< Bit mask of TRIGINSTATUS7
14002                                                                             field.*/
14003   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Min (0x0UL) /*!< Min enumerator value of TRIGINSTATUS7 field.                      */
14004   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Max (0x1UL) /*!< Max enumerator value of TRIGINSTATUS7 field.                      */
14005   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Active (0x1UL) /*!< Ctitrigin 7 is active.                                         */
14006   #define CTI_CTITRIGINSTATUS_TRIGINSTATUS7_Inactive (0x0UL) /*!< Ctitrigin 7 is inactive.                                     */
14007 
14008 
14009 /* CTI_CTITRIGOUTSTATUS: CTI Trigger Out Status register */
14010   #define CTI_CTITRIGOUTSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CTITRIGOUTSTATUS register.                        */
14011 
14012 /* TRIGOUTSTATUS0 @Bit 0 : Shows the status of ctitrigout0 output. */
14013   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Pos (0UL) /*!< Position of TRIGOUTSTATUS0 field.                                 */
14014   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Pos) /*!< Bit mask of
14015                                                                             TRIGOUTSTATUS0 field.*/
14016   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS0 field.                   */
14017   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS0 field.                   */
14018   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Active (0x1UL) /*!< Ctitrigout 0 is active.                                      */
14019   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS0_Inactive (0x0UL) /*!< Ctitrigout 0 is inactive.                                  */
14020 
14021 /* TRIGOUTSTATUS1 @Bit 1 : Shows the status of ctitrigout1 output. */
14022   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Pos (1UL) /*!< Position of TRIGOUTSTATUS1 field.                                 */
14023   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Pos) /*!< Bit mask of
14024                                                                             TRIGOUTSTATUS1 field.*/
14025   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS1 field.                   */
14026   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS1 field.                   */
14027   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Active (0x1UL) /*!< Ctitrigout 1 is active.                                      */
14028   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS1_Inactive (0x0UL) /*!< Ctitrigout 1 is inactive.                                  */
14029 
14030 /* TRIGOUTSTATUS2 @Bit 2 : Shows the status of ctitrigout2 output. */
14031   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Pos (2UL) /*!< Position of TRIGOUTSTATUS2 field.                                 */
14032   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Pos) /*!< Bit mask of
14033                                                                             TRIGOUTSTATUS2 field.*/
14034   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS2 field.                   */
14035   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS2 field.                   */
14036   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Active (0x1UL) /*!< Ctitrigout 2 is active.                                      */
14037   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS2_Inactive (0x0UL) /*!< Ctitrigout 2 is inactive.                                  */
14038 
14039 /* TRIGOUTSTATUS3 @Bit 3 : Shows the status of ctitrigout3 output. */
14040   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Pos (3UL) /*!< Position of TRIGOUTSTATUS3 field.                                 */
14041   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Pos) /*!< Bit mask of
14042                                                                             TRIGOUTSTATUS3 field.*/
14043   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS3 field.                   */
14044   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS3 field.                   */
14045   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Active (0x1UL) /*!< Ctitrigout 3 is active.                                      */
14046   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS3_Inactive (0x0UL) /*!< Ctitrigout 3 is inactive.                                  */
14047 
14048 /* TRIGOUTSTATUS4 @Bit 4 : Shows the status of ctitrigout4 output. */
14049   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Pos (4UL) /*!< Position of TRIGOUTSTATUS4 field.                                 */
14050   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Pos) /*!< Bit mask of
14051                                                                             TRIGOUTSTATUS4 field.*/
14052   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS4 field.                   */
14053   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS4 field.                   */
14054   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Active (0x1UL) /*!< Ctitrigout 4 is active.                                      */
14055   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS4_Inactive (0x0UL) /*!< Ctitrigout 4 is inactive.                                  */
14056 
14057 /* TRIGOUTSTATUS5 @Bit 5 : Shows the status of ctitrigout5 output. */
14058   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Pos (5UL) /*!< Position of TRIGOUTSTATUS5 field.                                 */
14059   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Pos) /*!< Bit mask of
14060                                                                             TRIGOUTSTATUS5 field.*/
14061   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS5 field.                   */
14062   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS5 field.                   */
14063   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Active (0x1UL) /*!< Ctitrigout 5 is active.                                      */
14064   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS5_Inactive (0x0UL) /*!< Ctitrigout 5 is inactive.                                  */
14065 
14066 /* TRIGOUTSTATUS6 @Bit 6 : Shows the status of ctitrigout6 output. */
14067   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Pos (6UL) /*!< Position of TRIGOUTSTATUS6 field.                                 */
14068   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Pos) /*!< Bit mask of
14069                                                                             TRIGOUTSTATUS6 field.*/
14070   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS6 field.                   */
14071   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS6 field.                   */
14072   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Active (0x1UL) /*!< Ctitrigout 6 is active.                                      */
14073   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS6_Inactive (0x0UL) /*!< Ctitrigout 6 is inactive.                                  */
14074 
14075 /* TRIGOUTSTATUS7 @Bit 7 : Shows the status of ctitrigout7 output. */
14076   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Pos (7UL) /*!< Position of TRIGOUTSTATUS7 field.                                 */
14077   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Pos) /*!< Bit mask of
14078                                                                             TRIGOUTSTATUS7 field.*/
14079   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Min (0x0UL) /*!< Min enumerator value of TRIGOUTSTATUS7 field.                   */
14080   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Max (0x1UL) /*!< Max enumerator value of TRIGOUTSTATUS7 field.                   */
14081   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Active (0x1UL) /*!< Ctitrigout 7 is active.                                      */
14082   #define CTI_CTITRIGOUTSTATUS_TRIGOUTSTATUS7_Inactive (0x0UL) /*!< Ctitrigout 7 is inactive.                                  */
14083 
14084 
14085 /* CTI_CTICHINSTATUS: CTI Channel In Status register */
14086   #define CTI_CTICHINSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CTICHINSTATUS register.                              */
14087 
14088 /* CTICHINSTATUS0 @Bit 0 : Shows the status of the ctitrigin 0 input. */
14089   #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Pos (0UL) /*!< Position of CTICHINSTATUS0 field.                                    */
14090   #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS0_Pos) /*!< Bit mask of CTICHINSTATUS0
14091                                                                             field.*/
14092   #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Min (0x0UL) /*!< Min enumerator value of CTICHINSTATUS0 field.                      */
14093   #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Max (0x1UL) /*!< Max enumerator value of CTICHINSTATUS0 field.                      */
14094   #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Active (0x1UL) /*!< Ctichin 0 is active.                                            */
14095   #define CTI_CTICHINSTATUS_CTICHINSTATUS0_Inactive (0x0UL) /*!< Ctichin 0 is inactive.                                        */
14096 
14097 /* CTICHINSTATUS1 @Bit 1 : Shows the status of the ctitrigin 1 input. */
14098   #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Pos (1UL) /*!< Position of CTICHINSTATUS1 field.                                    */
14099   #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS1_Pos) /*!< Bit mask of CTICHINSTATUS1
14100                                                                             field.*/
14101   #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Min (0x0UL) /*!< Min enumerator value of CTICHINSTATUS1 field.                      */
14102   #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Max (0x1UL) /*!< Max enumerator value of CTICHINSTATUS1 field.                      */
14103   #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Active (0x1UL) /*!< Ctichin 1 is active.                                            */
14104   #define CTI_CTICHINSTATUS_CTICHINSTATUS1_Inactive (0x0UL) /*!< Ctichin 1 is inactive.                                        */
14105 
14106 /* CTICHINSTATUS2 @Bit 2 : Shows the status of the ctitrigin 2 input. */
14107   #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Pos (2UL) /*!< Position of CTICHINSTATUS2 field.                                    */
14108   #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS2_Pos) /*!< Bit mask of CTICHINSTATUS2
14109                                                                             field.*/
14110   #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Min (0x0UL) /*!< Min enumerator value of CTICHINSTATUS2 field.                      */
14111   #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Max (0x1UL) /*!< Max enumerator value of CTICHINSTATUS2 field.                      */
14112   #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Active (0x1UL) /*!< Ctichin 2 is active.                                            */
14113   #define CTI_CTICHINSTATUS_CTICHINSTATUS2_Inactive (0x0UL) /*!< Ctichin 2 is inactive.                                        */
14114 
14115 /* CTICHINSTATUS3 @Bit 3 : Shows the status of the ctitrigin 3 input. */
14116   #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Pos (3UL) /*!< Position of CTICHINSTATUS3 field.                                    */
14117   #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS3_Pos) /*!< Bit mask of CTICHINSTATUS3
14118                                                                             field.*/
14119   #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Min (0x0UL) /*!< Min enumerator value of CTICHINSTATUS3 field.                      */
14120   #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Max (0x1UL) /*!< Max enumerator value of CTICHINSTATUS3 field.                      */
14121   #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Active (0x1UL) /*!< Ctichin 3 is active.                                            */
14122   #define CTI_CTICHINSTATUS_CTICHINSTATUS3_Inactive (0x0UL) /*!< Ctichin 3 is inactive.                                        */
14123 
14124 
14125 /* CTI_CTIGATE: Enable CTI Channel Gate register */
14126   #define CTI_CTIGATE_ResetValue (0x0000000FUL)      /*!< Reset value of CTIGATE register.                                     */
14127 
14128 /* CTIGATEEN0 @Bit 0 : Enable ctichout0. */
14129   #define CTI_CTIGATE_CTIGATEEN0_Pos (0UL)           /*!< Position of CTIGATEEN0 field.                                        */
14130   #define CTI_CTIGATE_CTIGATEEN0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN0_Pos) /*!< Bit mask of CTIGATEEN0 field.                  */
14131   #define CTI_CTIGATE_CTIGATEEN0_Min (0x0UL)         /*!< Min enumerator value of CTIGATEEN0 field.                            */
14132   #define CTI_CTIGATE_CTIGATEEN0_Max (0x1UL)         /*!< Max enumerator value of CTIGATEEN0 field.                            */
14133   #define CTI_CTIGATE_CTIGATEEN0_Enabled (0x1UL)     /*!< Enable ctichout channel 0 propagation.                               */
14134   #define CTI_CTIGATE_CTIGATEEN0_Disabled (0x0UL)    /*!< Disable ctichout channel 0 propagation.                              */
14135 
14136 /* CTIGATEEN1 @Bit 1 : Enable ctichout1. */
14137   #define CTI_CTIGATE_CTIGATEEN1_Pos (1UL)           /*!< Position of CTIGATEEN1 field.                                        */
14138   #define CTI_CTIGATE_CTIGATEEN1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN1_Pos) /*!< Bit mask of CTIGATEEN1 field.                  */
14139   #define CTI_CTIGATE_CTIGATEEN1_Min (0x0UL)         /*!< Min enumerator value of CTIGATEEN1 field.                            */
14140   #define CTI_CTIGATE_CTIGATEEN1_Max (0x1UL)         /*!< Max enumerator value of CTIGATEEN1 field.                            */
14141   #define CTI_CTIGATE_CTIGATEEN1_Enabled (0x1UL)     /*!< Enable ctichout channel 1 propagation.                               */
14142   #define CTI_CTIGATE_CTIGATEEN1_Disabled (0x0UL)    /*!< Disable ctichout channel 1 propagation.                              */
14143 
14144 /* CTIGATEEN2 @Bit 2 : Enable ctichout2. */
14145   #define CTI_CTIGATE_CTIGATEEN2_Pos (2UL)           /*!< Position of CTIGATEEN2 field.                                        */
14146   #define CTI_CTIGATE_CTIGATEEN2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN2_Pos) /*!< Bit mask of CTIGATEEN2 field.                  */
14147   #define CTI_CTIGATE_CTIGATEEN2_Min (0x0UL)         /*!< Min enumerator value of CTIGATEEN2 field.                            */
14148   #define CTI_CTIGATE_CTIGATEEN2_Max (0x1UL)         /*!< Max enumerator value of CTIGATEEN2 field.                            */
14149   #define CTI_CTIGATE_CTIGATEEN2_Enabled (0x1UL)     /*!< Enable ctichout channel 2 propagation.                               */
14150   #define CTI_CTIGATE_CTIGATEEN2_Disabled (0x0UL)    /*!< Disable ctichout channel 2 propagation.                              */
14151 
14152 /* CTIGATEEN3 @Bit 3 : Enable ctichout3. */
14153   #define CTI_CTIGATE_CTIGATEEN3_Pos (3UL)           /*!< Position of CTIGATEEN3 field.                                        */
14154   #define CTI_CTIGATE_CTIGATEEN3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN3_Pos) /*!< Bit mask of CTIGATEEN3 field.                  */
14155   #define CTI_CTIGATE_CTIGATEEN3_Min (0x0UL)         /*!< Min enumerator value of CTIGATEEN3 field.                            */
14156   #define CTI_CTIGATE_CTIGATEEN3_Max (0x1UL)         /*!< Max enumerator value of CTIGATEEN3 field.                            */
14157   #define CTI_CTIGATE_CTIGATEEN3_Enabled (0x1UL)     /*!< Enable ctichout channel 3 propagation.                               */
14158   #define CTI_CTIGATE_CTIGATEEN3_Disabled (0x0UL)    /*!< Disable ctichout channel 3 propagation.                              */
14159 
14160 
14161 /* CTI_DEVARCH: Device Architecture register */
14162   #define CTI_DEVARCH_ResetValue (0x47701A14UL)      /*!< Reset value of DEVARCH register.                                     */
14163 
14164 /* Architecture @Bit 0 : Contains the CTI device architecture. */
14165   #define CTI_DEVARCH_Architecture_Pos (0UL)         /*!< Position of Architecture field.                                      */
14166   #define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos) /*!< Bit mask of Architecture field.            */
14167 
14168 
14169 /* CTI_DEVID: Device Configuration register */
14170   #define CTI_DEVID_ResetValue (0x00040800UL)        /*!< Reset value of DEVID register.                                       */
14171 
14172 /* EXTMUXNUM @Bits 0..4 : Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using
14173                           asicctl. The default value of 0b00000 indicates that no multiplexing is present. */
14174 
14175   #define CTI_DEVID_EXTMUXNUM_Pos (0UL)              /*!< Position of EXTMUXNUM field.                                         */
14176   #define CTI_DEVID_EXTMUXNUM_Msk (0x1FUL << CTI_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field.                        */
14177 
14178 /* NUMTRIG @Bits 8..15 : Number of ECT triggers available. */
14179   #define CTI_DEVID_NUMTRIG_Pos (8UL)                /*!< Position of NUMTRIG field.                                           */
14180   #define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos) /*!< Bit mask of NUMTRIG field.                              */
14181 
14182 /* NUMCH @Bits 16..19 : Number of ECT channels available. */
14183   #define CTI_DEVID_NUMCH_Pos (16UL)                 /*!< Position of NUMCH field.                                             */
14184   #define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos) /*!< Bit mask of NUMCH field.                                     */
14185 
14186 
14187 /* CTI_DEVTYPE: Device Type Identifier register */
14188   #define CTI_DEVTYPE_ResetValue (0x00000014UL)      /*!< Reset value of DEVTYPE register.                                     */
14189 
14190 /* MAJOR @Bits 0..3 : Major classification of the type of the debug component as specified in the Arm Architecture Specification
14191                       for this debug and trace component. */
14192 
14193   #define CTI_DEVTYPE_MAJOR_Pos (0UL)                /*!< Position of MAJOR field.                                             */
14194   #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field.                                 */
14195   #define CTI_DEVTYPE_MAJOR_Min (0x4UL)              /*!< Min enumerator value of MAJOR field.                                 */
14196   #define CTI_DEVTYPE_MAJOR_Max (0x4UL)              /*!< Max enumerator value of MAJOR field.                                 */
14197   #define CTI_DEVTYPE_MAJOR_Controller (0x4UL)       /*!< Indicates that this component allows a debugger to control other
14198                                                           components in an Arm CoreSight SoC-400 system.*/
14199 
14200 /* SUB @Bits 4..7 : Sub-classification of the type of the debug component as specified in the Arm Architecture Specification
14201                     within the major classification as specified in the MAJOR field. */
14202 
14203   #define CTI_DEVTYPE_SUB_Pos (4UL)                  /*!< Position of SUB field.                                               */
14204   #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field.                                       */
14205   #define CTI_DEVTYPE_SUB_Min (0x1UL)                /*!< Min enumerator value of SUB field.                                   */
14206   #define CTI_DEVTYPE_SUB_Max (0x1UL)                /*!< Max enumerator value of SUB field.                                   */
14207   #define CTI_DEVTYPE_SUB_Crosstrigger (0x1UL)       /*!< Indicates that this component is a sub-triggering component.         */
14208 
14209 
14210 /* CTI_PIDR4: Peripheral ID4 Register */
14211   #define CTI_PIDR4_ResetValue (0x00000004UL)        /*!< Reset value of PIDR4 register.                                       */
14212 
14213 /* DES_2 @Bits 0..3 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
14214   #define CTI_PIDR4_DES_2_Pos (0UL)                  /*!< Position of DES_2 field.                                             */
14215   #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field.                                     */
14216   #define CTI_PIDR4_DES_2_Min (0x4UL)                /*!< Min enumerator value of DES_2 field.                                 */
14217   #define CTI_PIDR4_DES_2_Max (0x4UL)                /*!< Max enumerator value of DES_2 field.                                 */
14218   #define CTI_PIDR4_DES_2_Code (0x4UL)               /*!< JEDEC continuation code.                                             */
14219 
14220 /* SIZE @Bits 4..7 : Always 0b0000. Indicates that the device only occupies 4KB of memory. */
14221   #define CTI_PIDR4_SIZE_Pos (4UL)                   /*!< Position of SIZE field.                                              */
14222   #define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field.                                        */
14223 
14224 
14225 /* CTI_PIDR0: Peripheral ID0 Register */
14226   #define CTI_PIDR0_ResetValue (0x00000021UL)        /*!< Reset value of PIDR0 register.                                       */
14227 
14228 /* PART_0 @Bits 0..7 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part
14229                        number. */
14230 
14231   #define CTI_PIDR0_PART_0_Pos (0UL)                 /*!< Position of PART_0 field.                                            */
14232   #define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field.                                 */
14233   #define CTI_PIDR0_PART_0_Min (0x21UL)              /*!< Min enumerator value of PART_0 field.                                */
14234   #define CTI_PIDR0_PART_0_Max (0x21UL)              /*!< Max enumerator value of PART_0 field.                                */
14235   #define CTI_PIDR0_PART_0_PartnumberL (0x21UL)      /*!< Indicates bits[7:0] of the part number of the component.             */
14236 
14237 
14238 /* CTI_PIDR1: Peripheral ID1 Register */
14239   #define CTI_PIDR1_ResetValue (0x000000BDUL)        /*!< Reset value of PIDR1 register.                                       */
14240 
14241 /* PART_1 @Bits 0..3 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part
14242                        number. */
14243 
14244   #define CTI_PIDR1_PART_1_Pos (0UL)                 /*!< Position of PART_1 field.                                            */
14245   #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field.                                  */
14246   #define CTI_PIDR1_PART_1_Min (0xDUL)               /*!< Min enumerator value of PART_1 field.                                */
14247   #define CTI_PIDR1_PART_1_Max (0xDUL)               /*!< Max enumerator value of PART_1 field.                                */
14248   #define CTI_PIDR1_PART_1_PartnumberH (0xDUL)       /*!< Indicates bits[11:8] of the part number of the component.            */
14249 
14250 /* DES_0 @Bits 4..7 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
14251   #define CTI_PIDR1_DES_0_Pos (4UL)                  /*!< Position of DES_0 field.                                             */
14252   #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field.                                     */
14253   #define CTI_PIDR1_DES_0_Min (0xBUL)                /*!< Min enumerator value of DES_0 field.                                 */
14254   #define CTI_PIDR1_DES_0_Max (0xBUL)                /*!< Max enumerator value of DES_0 field.                                 */
14255   #define CTI_PIDR1_DES_0_Arm (0xBUL)                /*!< Arm. Bits[3:0] of the JEDEC JEP106 Identity Code                     */
14256 
14257 
14258 /* CTI_PIDR2: Peripheral ID2 Register */
14259   #define CTI_PIDR2_ResetValue (0x0000000BUL)        /*!< Reset value of PIDR2 register.                                       */
14260 
14261 /* DES_1 @Bits 0..2 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */
14262   #define CTI_PIDR2_DES_1_Pos (0UL)                  /*!< Position of DES_1 field.                                             */
14263   #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field.                                     */
14264   #define CTI_PIDR2_DES_1_Min (0x3UL)                /*!< Min enumerator value of DES_1 field.                                 */
14265   #define CTI_PIDR2_DES_1_Max (0x3UL)                /*!< Max enumerator value of DES_1 field.                                 */
14266   #define CTI_PIDR2_DES_1_Arm (0x3UL)                /*!< Arm. Bits[6:4] of the JEDEC JEP106 Identity Code                     */
14267 
14268 /* JEDEC @Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */
14269   #define CTI_PIDR2_JEDEC_Pos (3UL)                  /*!< Position of JEDEC field.                                             */
14270   #define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field.                                     */
14271 
14272 /* REVISION @Bits 4..7 : Peripheral revision */
14273   #define CTI_PIDR2_REVISION_Pos (4UL)               /*!< Position of REVISION field.                                          */
14274   #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field.                            */
14275   #define CTI_PIDR2_REVISION_Min (0x0UL)             /*!< Min enumerator value of REVISION field.                              */
14276   #define CTI_PIDR2_REVISION_Max (0x0UL)             /*!< Max enumerator value of REVISION field.                              */
14277   #define CTI_PIDR2_REVISION_Rev0p0 (0x0UL)          /*!< This device is at r0p0                                               */
14278 
14279 
14280 /* CTI_PIDR3: Peripheral ID3 Register */
14281   #define CTI_PIDR3_ResetValue (0x00000000UL)        /*!< Reset value of PIDR3 register.                                       */
14282 
14283 /* CMOD @Bits 0..3 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most
14284                      cases, this field is 0b0000. Customers change this value when they make authorized modifications to this
14285                      component. */
14286 
14287   #define CTI_PIDR3_CMOD_Pos (0UL)                   /*!< Position of CMOD field.                                              */
14288   #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field.                                        */
14289   #define CTI_PIDR3_CMOD_Min (0x0UL)                 /*!< Min enumerator value of CMOD field.                                  */
14290   #define CTI_PIDR3_CMOD_Max (0x0UL)                 /*!< Max enumerator value of CMOD field.                                  */
14291   #define CTI_PIDR3_CMOD_Unmodified (0x0UL)          /*!< Indicates that the customer has not modified this component.         */
14292 
14293 /* REVAND @Bits 4..7 : Indicates minor errata fixes specific to the revision of the component being used, for example metal
14294                        fixes after implementation. In most cases, this field is 0b0000. Arm recommends that the component
14295                        designers ensure that a metal fix can change this field if required, for example, by driving it from
14296                        registers that reset to 0b0000. */
14297 
14298   #define CTI_PIDR3_REVAND_Pos (4UL)                 /*!< Position of REVAND field.                                            */
14299   #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field.                                  */
14300   #define CTI_PIDR3_REVAND_Min (0x0UL)               /*!< Min enumerator value of REVAND field.                                */
14301   #define CTI_PIDR3_REVAND_Max (0x0UL)               /*!< Max enumerator value of REVAND field.                                */
14302   #define CTI_PIDR3_REVAND_NoErrata (0x0UL)          /*!< Indicates that there are no errata fixes to this component.          */
14303 
14304 
14305 /* CTI_CIDR0: Component ID0 Register */
14306   #define CTI_CIDR0_ResetValue (0x0000000DUL)        /*!< Reset value of CIDR0 register.                                       */
14307 
14308 /* PRMBL_0 @Bits 0..7 : Preamble[0]. Contains bits[7:0] of the component identification code. */
14309   #define CTI_CIDR0_PRMBL_0_Pos (0UL)                /*!< Position of PRMBL_0 field.                                           */
14310   #define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field.                              */
14311   #define CTI_CIDR0_PRMBL_0_Min (0xDUL)              /*!< Min enumerator value of PRMBL_0 field.                               */
14312   #define CTI_CIDR0_PRMBL_0_Max (0xDUL)              /*!< Max enumerator value of PRMBL_0 field.                               */
14313   #define CTI_CIDR0_PRMBL_0_Value (0x0DUL)           /*!< Bits[7:0] of the identification code.                                */
14314 
14315 
14316 /* CTI_CIDR1: Component ID1 Register */
14317   #define CTI_CIDR1_ResetValue (0x00000090UL)        /*!< Reset value of CIDR1 register.                                       */
14318 
14319 /* PRMBL_1 @Bits 0..3 : Preamble[1]. Contains bits[11:8] of the component identification code. */
14320   #define CTI_CIDR1_PRMBL_1_Pos (0UL)                /*!< Position of PRMBL_1 field.                                           */
14321   #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field.                               */
14322   #define CTI_CIDR1_PRMBL_1_Min (0x0UL)              /*!< Min enumerator value of PRMBL_1 field.                               */
14323   #define CTI_CIDR1_PRMBL_1_Max (0x0UL)              /*!< Max enumerator value of PRMBL_1 field.                               */
14324   #define CTI_CIDR1_PRMBL_1_Value (0x0UL)            /*!< Bits[11:8] of the identification code.                               */
14325 
14326 /* CLASS @Bits 4..7 : Class of the component, for example, whether the component is a ROM table or a generic CoreSight
14327                       component. Contains bits[15:12] of the component identification code */
14328 
14329   #define CTI_CIDR1_CLASS_Pos (4UL)                  /*!< Position of CLASS field.                                             */
14330   #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field.                                     */
14331   #define CTI_CIDR1_CLASS_Min (0x9UL)                /*!< Min enumerator value of CLASS field.                                 */
14332   #define CTI_CIDR1_CLASS_Max (0x9UL)                /*!< Max enumerator value of CLASS field.                                 */
14333   #define CTI_CIDR1_CLASS_Coresight (0x9UL)          /*!< Indicates that the component is a CoreSight component.               */
14334 
14335 
14336 /* CTI_CIDR2: Component ID2 Register */
14337   #define CTI_CIDR2_ResetValue (0x00000005UL)        /*!< Reset value of CIDR2 register.                                       */
14338 
14339 /* PRMBL_2 @Bits 0..7 : Preamble[2]. Contains bits[23:16] of the component identification code. */
14340   #define CTI_CIDR2_PRMBL_2_Pos (0UL)                /*!< Position of PRMBL_2 field.                                           */
14341   #define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field.                              */
14342   #define CTI_CIDR2_PRMBL_2_Min (0x5UL)              /*!< Min enumerator value of PRMBL_2 field.                               */
14343   #define CTI_CIDR2_PRMBL_2_Max (0x5UL)              /*!< Max enumerator value of PRMBL_2 field.                               */
14344   #define CTI_CIDR2_PRMBL_2_Value (0x05UL)           /*!< Bits[23:16] of the identification code.                              */
14345 
14346 
14347 /* CTI_CIDR3: Component ID3 Register */
14348   #define CTI_CIDR3_ResetValue (0x000000B1UL)        /*!< Reset value of CIDR3 register.                                       */
14349 
14350 /* PRMBL_3 @Bits 0..7 : Preamble[3]. Contains bits[31:24] of the component identification code. */
14351   #define CTI_CIDR3_PRMBL_3_Pos (0UL)                /*!< Position of PRMBL_3 field.                                           */
14352   #define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field.                              */
14353   #define CTI_CIDR3_PRMBL_3_Min (0xB1UL)             /*!< Min enumerator value of PRMBL_3 field.                               */
14354   #define CTI_CIDR3_PRMBL_3_Max (0xB1UL)             /*!< Max enumerator value of PRMBL_3 field.                               */
14355   #define CTI_CIDR3_PRMBL_3_Value (0xB1UL)           /*!< Bits[31:24] of the identification code.                              */
14356 
14357 
14358 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
14359 
14360 /* =========================================================================================================================== */
14361 /* ================                                        CTRLAPPERI                                        ================ */
14362 /* =========================================================================================================================== */
14363 
14364 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
14365 
14366 /* ================================================ Struct CTRLAPPERI_MAILBOX ================================================ */
14367 /**
14368   * @brief MAILBOX [CTRLAPPERI_MAILBOX] (unspecified)
14369   */
14370 typedef struct {
14371   __IM  uint32_t  RXDATA;                            /*!< (@ 0x00000000) Data sent from the debugger to the CPU                */
14372   __IM  uint32_t  RXSTATUS;                          /*!< (@ 0x00000004) Status to indicate if data sent from the debugger to
14373                                                                          the CPU has been read*/
14374   __IM  uint32_t  RESERVED[30];
14375   __IOM uint32_t  TXDATA;                            /*!< (@ 0x00000080) Data sent from the CPU to the debugger                */
14376   __IM  uint32_t  TXSTATUS;                          /*!< (@ 0x00000084) Status to indicate if data sent from the CPU to the
14377                                                                          debugger has been read*/
14378   __IM  uint32_t  BOOTMODE;                          /*!< (@ 0x00000088) Secure domain boot mode.                              */
14379 } NRF_CTRLAPPERI_MAILBOX_Type;                       /*!< Size = 140 (0x08C)                                                   */
14380 
14381 /* CTRLAPPERI_MAILBOX_RXDATA: Data sent from the debugger to the CPU */
14382   #define CTRLAPPERI_MAILBOX_RXDATA_ResetValue (0x00000000UL) /*!< Reset value of RXDATA register.                             */
14383 
14384 /* RXDATA @Bits 0..31 : Data received from debugger */
14385   #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field.                                            */
14386   #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA
14387                                                                             field.*/
14388 
14389 
14390 /* CTRLAPPERI_MAILBOX_RXSTATUS: Status to indicate if data sent from the debugger to the CPU has been read */
14391   #define CTRLAPPERI_MAILBOX_RXSTATUS_ResetValue (0x00000000UL) /*!< Reset value of RXSTATUS register.                         */
14392 
14393 /* RXSTATUS @Bit 0 : Status of data in register RXDATA */
14394   #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field.                                      */
14395   #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS
14396                                                                             field.*/
14397   #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Min (0x0UL) /*!< Min enumerator value of RXSTATUS field.                        */
14398   #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Max (0x1UL) /*!< Max enumerator value of RXSTATUS field.                        */
14399   #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register RXDATA                   */
14400   #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (0x1UL) /*!< Data pending in register RXDATA                        */
14401 
14402 
14403 /* CTRLAPPERI_MAILBOX_TXDATA: Data sent from the CPU to the debugger */
14404   #define CTRLAPPERI_MAILBOX_TXDATA_ResetValue (0x00000000UL) /*!< Reset value of TXDATA register.                             */
14405 
14406 /* TXDATA @Bits 0..31 : Data sent to debugger */
14407   #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field.                                            */
14408   #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA
14409                                                                             field.*/
14410 
14411 
14412 /* CTRLAPPERI_MAILBOX_TXSTATUS: Status to indicate if data sent from the CPU to the debugger has been read */
14413   #define CTRLAPPERI_MAILBOX_TXSTATUS_ResetValue (0x00000000UL) /*!< Reset value of TXSTATUS register.                         */
14414 
14415 /* TXSTATUS @Bit 0 : Status of data in register TXDATA */
14416   #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field.                                      */
14417   #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS
14418                                                                             field.*/
14419   #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Min (0x0UL) /*!< Min enumerator value of TXSTATUS field.                        */
14420   #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Max (0x1UL) /*!< Max enumerator value of TXSTATUS field.                        */
14421   #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register TXDATA                   */
14422   #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (0x1UL) /*!< Data pending in register TXDATA                        */
14423 
14424 
14425 /* CTRLAPPERI_MAILBOX_BOOTMODE: Secure domain boot mode. */
14426   #define CTRLAPPERI_MAILBOX_BOOTMODE_ResetValue (0x00000000UL) /*!< Reset value of BOOTMODE register.                         */
14427 
14428 /* MODE @Bit 0 : Mode */
14429   #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Pos (0UL) /*!< Position of MODE field.                                              */
14430   #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Msk (0x1UL << CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Pos) /*!< Bit mask of MODE field.    */
14431   #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field.                                */
14432   #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Max (0x1UL) /*!< Max enumerator value of MODE field.                                */
14433   #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_Normal (0x0UL) /*!< Normal mode of operation                                        */
14434   #define CTRLAPPERI_MAILBOX_BOOTMODE_MODE_ROMOperation (0x1UL) /*!< ROM operation mode                                        */
14435 
14436 
14437 /* ==================================================== Struct CTRLAPPERI ==================================================== */
14438 /**
14439   * @brief Control access port
14440   */
14441   typedef struct {                                   /*!< CTRLAPPERI Structure                                                 */
14442     __IM uint32_t RESERVED[64];
14443     __IOM uint32_t EVENTS_RXREADY;                   /*!< (@ 0x00000100) The RXSTATUS is changed to DataPending                */
14444     __IOM uint32_t EVENTS_TXDONE;                    /*!< (@ 0x00000104) The TXSTATUS is changed to NoDataPending              */
14445     __IM uint32_t RESERVED1[126];
14446     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
14447     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
14448     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
14449     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
14450     __IM uint32_t RESERVED2[60];
14451     __IOM NRF_CTRLAPPERI_MAILBOX_Type MAILBOX;       /*!< (@ 0x00000400) (unspecified)                                         */
14452   } NRF_CTRLAPPERI_Type;                             /*!< Size = 1164 (0x48C)                                                  */
14453 
14454 /* CTRLAPPERI_EVENTS_RXREADY: The RXSTATUS is changed to DataPending */
14455   #define CTRLAPPERI_EVENTS_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXREADY register.                     */
14456 
14457 /* EVENTS_RXREADY @Bit 0 : The RXSTATUS is changed to DataPending */
14458   #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field.                            */
14459   #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of
14460                                                                             EVENTS_RXREADY field.*/
14461   #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXREADY field.              */
14462   #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXREADY field.              */
14463   #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated                               */
14464   #define CTRLAPPERI_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated                                      */
14465 
14466 
14467 /* CTRLAPPERI_EVENTS_TXDONE: The TXSTATUS is changed to NoDataPending */
14468   #define CTRLAPPERI_EVENTS_TXDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXDONE register.                       */
14469 
14470 /* EVENTS_TXDONE @Bit 0 : The TXSTATUS is changed to NoDataPending */
14471   #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Pos (0UL) /*!< Position of EVENTS_TXDONE field.                               */
14472   #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Msk (0x1UL << CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Pos) /*!< Bit mask of
14473                                                                             EVENTS_TXDONE field.*/
14474   #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXDONE field.                 */
14475   #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXDONE field.                 */
14476   #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_NotGenerated (0x0UL) /*!< Event not generated                                 */
14477   #define CTRLAPPERI_EVENTS_TXDONE_EVENTS_TXDONE_Generated (0x1UL) /*!< Event generated                                        */
14478 
14479 
14480 /* CTRLAPPERI_INTEN: Enable or disable interrupt */
14481   #define CTRLAPPERI_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register.                                       */
14482 
14483 /* RXREADY @Bit 0 : Enable or disable interrupt for event RXREADY */
14484   #define CTRLAPPERI_INTEN_RXREADY_Pos (0UL)         /*!< Position of RXREADY field.                                           */
14485   #define CTRLAPPERI_INTEN_RXREADY_Msk (0x1UL << CTRLAPPERI_INTEN_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
14486   #define CTRLAPPERI_INTEN_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
14487   #define CTRLAPPERI_INTEN_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
14488   #define CTRLAPPERI_INTEN_RXREADY_Disabled (0x0UL)  /*!< Disable                                                              */
14489   #define CTRLAPPERI_INTEN_RXREADY_Enabled (0x1UL)   /*!< Enable                                                               */
14490 
14491 /* TXDONE @Bit 1 : Enable or disable interrupt for event TXDONE */
14492   #define CTRLAPPERI_INTEN_TXDONE_Pos (1UL)          /*!< Position of TXDONE field.                                            */
14493   #define CTRLAPPERI_INTEN_TXDONE_Msk (0x1UL << CTRLAPPERI_INTEN_TXDONE_Pos) /*!< Bit mask of TXDONE field.                    */
14494   #define CTRLAPPERI_INTEN_TXDONE_Min (0x0UL)        /*!< Min enumerator value of TXDONE field.                                */
14495   #define CTRLAPPERI_INTEN_TXDONE_Max (0x1UL)        /*!< Max enumerator value of TXDONE field.                                */
14496   #define CTRLAPPERI_INTEN_TXDONE_Disabled (0x0UL)   /*!< Disable                                                              */
14497   #define CTRLAPPERI_INTEN_TXDONE_Enabled (0x1UL)    /*!< Enable                                                               */
14498 
14499 
14500 /* CTRLAPPERI_INTENSET: Enable interrupt */
14501   #define CTRLAPPERI_INTENSET_ResetValue (0x00000000UL) /*!< Reset value of INTENSET register.                                 */
14502 
14503 /* RXREADY @Bit 0 : Write '1' to enable interrupt for event RXREADY */
14504   #define CTRLAPPERI_INTENSET_RXREADY_Pos (0UL)      /*!< Position of RXREADY field.                                           */
14505   #define CTRLAPPERI_INTENSET_RXREADY_Msk (0x1UL << CTRLAPPERI_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field.           */
14506   #define CTRLAPPERI_INTENSET_RXREADY_Min (0x0UL)    /*!< Min enumerator value of RXREADY field.                               */
14507   #define CTRLAPPERI_INTENSET_RXREADY_Max (0x1UL)    /*!< Max enumerator value of RXREADY field.                               */
14508   #define CTRLAPPERI_INTENSET_RXREADY_Set (0x1UL)    /*!< Enable                                                               */
14509   #define CTRLAPPERI_INTENSET_RXREADY_Disabled (0x0UL) /*!< Read: Disabled                                                     */
14510   #define CTRLAPPERI_INTENSET_RXREADY_Enabled (0x1UL) /*!< Read: Enabled                                                       */
14511 
14512 /* TXDONE @Bit 1 : Write '1' to enable interrupt for event TXDONE */
14513   #define CTRLAPPERI_INTENSET_TXDONE_Pos (1UL)       /*!< Position of TXDONE field.                                            */
14514   #define CTRLAPPERI_INTENSET_TXDONE_Msk (0x1UL << CTRLAPPERI_INTENSET_TXDONE_Pos) /*!< Bit mask of TXDONE field.              */
14515   #define CTRLAPPERI_INTENSET_TXDONE_Min (0x0UL)     /*!< Min enumerator value of TXDONE field.                                */
14516   #define CTRLAPPERI_INTENSET_TXDONE_Max (0x1UL)     /*!< Max enumerator value of TXDONE field.                                */
14517   #define CTRLAPPERI_INTENSET_TXDONE_Set (0x1UL)     /*!< Enable                                                               */
14518   #define CTRLAPPERI_INTENSET_TXDONE_Disabled (0x0UL) /*!< Read: Disabled                                                      */
14519   #define CTRLAPPERI_INTENSET_TXDONE_Enabled (0x1UL) /*!< Read: Enabled                                                        */
14520 
14521 
14522 /* CTRLAPPERI_INTENCLR: Disable interrupt */
14523   #define CTRLAPPERI_INTENCLR_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR register.                                 */
14524 
14525 /* RXREADY @Bit 0 : Write '1' to disable interrupt for event RXREADY */
14526   #define CTRLAPPERI_INTENCLR_RXREADY_Pos (0UL)      /*!< Position of RXREADY field.                                           */
14527   #define CTRLAPPERI_INTENCLR_RXREADY_Msk (0x1UL << CTRLAPPERI_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field.           */
14528   #define CTRLAPPERI_INTENCLR_RXREADY_Min (0x0UL)    /*!< Min enumerator value of RXREADY field.                               */
14529   #define CTRLAPPERI_INTENCLR_RXREADY_Max (0x1UL)    /*!< Max enumerator value of RXREADY field.                               */
14530   #define CTRLAPPERI_INTENCLR_RXREADY_Clear (0x1UL)  /*!< Disable                                                              */
14531   #define CTRLAPPERI_INTENCLR_RXREADY_Disabled (0x0UL) /*!< Read: Disabled                                                     */
14532   #define CTRLAPPERI_INTENCLR_RXREADY_Enabled (0x1UL) /*!< Read: Enabled                                                       */
14533 
14534 /* TXDONE @Bit 1 : Write '1' to disable interrupt for event TXDONE */
14535   #define CTRLAPPERI_INTENCLR_TXDONE_Pos (1UL)       /*!< Position of TXDONE field.                                            */
14536   #define CTRLAPPERI_INTENCLR_TXDONE_Msk (0x1UL << CTRLAPPERI_INTENCLR_TXDONE_Pos) /*!< Bit mask of TXDONE field.              */
14537   #define CTRLAPPERI_INTENCLR_TXDONE_Min (0x0UL)     /*!< Min enumerator value of TXDONE field.                                */
14538   #define CTRLAPPERI_INTENCLR_TXDONE_Max (0x1UL)     /*!< Max enumerator value of TXDONE field.                                */
14539   #define CTRLAPPERI_INTENCLR_TXDONE_Clear (0x1UL)   /*!< Disable                                                              */
14540   #define CTRLAPPERI_INTENCLR_TXDONE_Disabled (0x0UL) /*!< Read: Disabled                                                      */
14541   #define CTRLAPPERI_INTENCLR_TXDONE_Enabled (0x1UL) /*!< Read: Enabled                                                        */
14542 
14543 
14544 /* CTRLAPPERI_INTPEND: Pending interrupts */
14545   #define CTRLAPPERI_INTPEND_ResetValue (0x00000000UL) /*!< Reset value of INTPEND register.                                   */
14546 
14547 /* RXREADY @Bit 0 : Read pending status of interrupt for event RXREADY */
14548   #define CTRLAPPERI_INTPEND_RXREADY_Pos (0UL)       /*!< Position of RXREADY field.                                           */
14549   #define CTRLAPPERI_INTPEND_RXREADY_Msk (0x1UL << CTRLAPPERI_INTPEND_RXREADY_Pos) /*!< Bit mask of RXREADY field.             */
14550   #define CTRLAPPERI_INTPEND_RXREADY_Min (0x0UL)     /*!< Min enumerator value of RXREADY field.                               */
14551   #define CTRLAPPERI_INTPEND_RXREADY_Max (0x1UL)     /*!< Max enumerator value of RXREADY field.                               */
14552   #define CTRLAPPERI_INTPEND_RXREADY_NotPending (0x0UL) /*!< Read: Not pending                                                 */
14553   #define CTRLAPPERI_INTPEND_RXREADY_Pending (0x1UL) /*!< Read: Pending                                                        */
14554 
14555 /* TXDONE @Bit 1 : Read pending status of interrupt for event TXDONE */
14556   #define CTRLAPPERI_INTPEND_TXDONE_Pos (1UL)        /*!< Position of TXDONE field.                                            */
14557   #define CTRLAPPERI_INTPEND_TXDONE_Msk (0x1UL << CTRLAPPERI_INTPEND_TXDONE_Pos) /*!< Bit mask of TXDONE field.                */
14558   #define CTRLAPPERI_INTPEND_TXDONE_Min (0x0UL)      /*!< Min enumerator value of TXDONE field.                                */
14559   #define CTRLAPPERI_INTPEND_TXDONE_Max (0x1UL)      /*!< Max enumerator value of TXDONE field.                                */
14560   #define CTRLAPPERI_INTPEND_TXDONE_NotPending (0x0UL) /*!< Read: Not pending                                                  */
14561   #define CTRLAPPERI_INTPEND_TXDONE_Pending (0x1UL)  /*!< Read: Pending                                                        */
14562 
14563 
14564 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
14565 
14566 /* =========================================================================================================================== */
14567 /* ================                                            DMU                                            ================ */
14568 /* =========================================================================================================================== */
14569 
14570 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
14571 /* ======================================================= Struct DMU ======================================================== */
14572 /**
14573   * @brief DMU
14574   */
14575   typedef struct {                                   /*!< DMU Structure                                                        */
14576     __IM uint32_t RESERVED[240];
14577     __IM uint32_t DMUCR;                             /*!< (@ 0x000003C0) DMU Core Release                                      */
14578     __IOM uint32_t DMUI;                             /*!< (@ 0x000003C4) DMU Internals                                         */
14579     __IOM uint32_t DMUQC;                            /*!< (@ 0x000003C8) DMU Queueing Counter                                  */
14580     __IOM uint32_t DMUIR;                            /*!< (@ 0x000003CC) DMU Interrupt Register                                */
14581     __IOM uint32_t DMUIE;                            /*!< (@ 0x000003D0) DMU Interrupt Enable                                  */
14582     __IOM uint32_t DMUC;                             /*!< (@ 0x000003D4) DMU Configuration                                     */
14583   } NRF_DMU_Type;                                    /*!< Size = 984 (0x3D8)                                                   */
14584 
14585 /* DMU_DMUCR: DMU Core Release */
14586   #define DMU_DMUCR_ResetValue (0x00000000UL)        /*!< Reset value of DMUCR register.                                       */
14587 
14588 /* REL @Bit 1 : Core Release */
14589   #define DMU_DMUCR_REL_Pos (1UL)                    /*!< Position of REL field.                                               */
14590   #define DMU_DMUCR_REL_Msk (0x1UL << DMU_DMUCR_REL_Pos) /*!< Bit mask of REL field.                                           */
14591 
14592 /* STEP @Bit 2 : Step of Core Release */
14593   #define DMU_DMUCR_STEP_Pos (2UL)                   /*!< Position of STEP field.                                              */
14594   #define DMU_DMUCR_STEP_Msk (0x1UL << DMU_DMUCR_STEP_Pos) /*!< Bit mask of STEP field.                                        */
14595 
14596 /* SUBSTEP @Bit 3 : Sub-step of Core Release */
14597   #define DMU_DMUCR_SUBSTEP_Pos (3UL)                /*!< Position of SUBSTEP field.                                           */
14598   #define DMU_DMUCR_SUBSTEP_Msk (0x1UL << DMU_DMUCR_SUBSTEP_Pos) /*!< Bit mask of SUBSTEP field.                               */
14599 
14600 /* YEAR @Bit 4 : Time Stamp Year */
14601   #define DMU_DMUCR_YEAR_Pos (4UL)                   /*!< Position of YEAR field.                                              */
14602   #define DMU_DMUCR_YEAR_Msk (0x1UL << DMU_DMUCR_YEAR_Pos) /*!< Bit mask of YEAR field.                                        */
14603 
14604 /* MON @Bit 6 : Time Stamp Month */
14605   #define DMU_DMUCR_MON_Pos (6UL)                    /*!< Position of MON field.                                               */
14606   #define DMU_DMUCR_MON_Msk (0x1UL << DMU_DMUCR_MON_Pos) /*!< Bit mask of MON field.                                           */
14607 
14608 /* DAY @Bit 8 : Time Stamp Day */
14609   #define DMU_DMUCR_DAY_Pos (8UL)                    /*!< Position of DAY field.                                               */
14610   #define DMU_DMUCR_DAY_Msk (0x1UL << DMU_DMUCR_DAY_Pos) /*!< Bit mask of DAY field.                                           */
14611 
14612 
14613 /* DMU_DMUI: DMU Internals */
14614   #define DMU_DMUI_ResetValue (0x00070000UL)         /*!< Reset value of DMUI register.                                        */
14615 
14616 /* TXR @Bit 0 : TX Service Request line of DMU */
14617   #define DMU_DMUI_TXR_Pos (0UL)                     /*!< Position of TXR field.                                               */
14618   #define DMU_DMUI_TXR_Msk (0x1UL << DMU_DMUI_TXR_Pos) /*!< Bit mask of TXR field.                                             */
14619   #define DMU_DMUI_TXR_Min (0x0UL)                   /*!< Min enumerator value of TXR field.                                   */
14620   #define DMU_DMUI_TXR_Max (0x1UL)                   /*!< Max enumerator value of TXR field.                                   */
14621   #define DMU_DMUI_TXR_NotRequested (0x0UL)          /*!< No TX DMA service requested                                          */
14622   #define DMU_DMUI_TXR_Requested (0x1UL)             /*!< TX DMA Service requested                                             */
14623 
14624 /* RX0R @Bit 1 : RX0 Service Request line of DMU */
14625   #define DMU_DMUI_RX0R_Pos (1UL)                    /*!< Position of RX0R field.                                              */
14626   #define DMU_DMUI_RX0R_Msk (0x1UL << DMU_DMUI_RX0R_Pos) /*!< Bit mask of RX0R field.                                          */
14627   #define DMU_DMUI_RX0R_Min (0x0UL)                  /*!< Min enumerator value of RX0R field.                                  */
14628   #define DMU_DMUI_RX0R_Max (0x1UL)                  /*!< Max enumerator value of RX0R field.                                  */
14629   #define DMU_DMUI_RX0R_NotRequested (0x0UL)         /*!< No RX0 DMA service requested                                         */
14630   #define DMU_DMUI_RX0R_Requested (0x1UL)            /*!< RX0 DMA Service requested                                            */
14631 
14632 /* RX1R @Bit 2 : RX1 Service Request line of DMU */
14633   #define DMU_DMUI_RX1R_Pos (2UL)                    /*!< Position of RX1R field.                                              */
14634   #define DMU_DMUI_RX1R_Msk (0x1UL << DMU_DMUI_RX1R_Pos) /*!< Bit mask of RX1R field.                                          */
14635   #define DMU_DMUI_RX1R_Min (0x0UL)                  /*!< Min enumerator value of RX1R field.                                  */
14636   #define DMU_DMUI_RX1R_Max (0x1UL)                  /*!< Max enumerator value of RX1R field.                                  */
14637   #define DMU_DMUI_RX1R_NotRequested (0x0UL)         /*!< No RX1 DMA service requested                                         */
14638   #define DMU_DMUI_RX1R_Requested (0x1UL)            /*!< RX1 DMA Service requested                                            */
14639 
14640 /* TXER @Bit 3 : TX Event Service Request line of DMU */
14641   #define DMU_DMUI_TXER_Pos (3UL)                    /*!< Position of TXER field.                                              */
14642   #define DMU_DMUI_TXER_Msk (0x1UL << DMU_DMUI_TXER_Pos) /*!< Bit mask of TXER field.                                          */
14643   #define DMU_DMUI_TXER_Min (0x0UL)                  /*!< Min enumerator value of TXER field.                                  */
14644   #define DMU_DMUI_TXER_Max (0x1UL)                  /*!< Max enumerator value of TXER field.                                  */
14645   #define DMU_DMUI_TXER_NotRequested (0x0UL)         /*!< No TX Event DMA service requested                                    */
14646   #define DMU_DMUI_TXER_Requested (0x1UL)            /*!< TX Event DMA Service requested                                       */
14647 
14648 /* TFQPIP @Bits 8..12 : TX FIFO/Queue Put Index Previous */
14649   #define DMU_DMUI_TFQPIP_Pos (8UL)                  /*!< Position of TFQPIP field.                                            */
14650   #define DMU_DMUI_TFQPIP_Msk (0x1FUL << DMU_DMUI_TFQPIP_Pos) /*!< Bit mask of TFQPIP field.                                   */
14651 
14652 /* ENA @Bit 15 : DMU is enabled */
14653   #define DMU_DMUI_ENA_Pos (15UL)                    /*!< Position of ENA field.                                               */
14654   #define DMU_DMUI_ENA_Msk (0x1UL << DMU_DMUI_ENA_Pos) /*!< Bit mask of ENA field.                                             */
14655   #define DMU_DMUI_ENA_Min (0x0UL)                   /*!< Min enumerator value of ENA field.                                   */
14656   #define DMU_DMUI_ENA_Max (0x1UL)                   /*!< Max enumerator value of ENA field.                                   */
14657   #define DMU_DMUI_ENA_Disabled (0x0UL)              /*!< DMU is disabled                                                      */
14658   #define DMU_DMUI_ENA_Enabled (0x1UL)               /*!< DMU is enabled and can process DMA data                              */
14659 
14660 /* DEHS @Bits 16..18 : Detect Element Handler State */
14661   #define DMU_DMUI_DEHS_Pos (16UL)                   /*!< Position of DEHS field.                                              */
14662   #define DMU_DMUI_DEHS_Msk (0x7UL << DMU_DMUI_DEHS_Pos) /*!< Bit mask of DEHS field.                                          */
14663 
14664 /* DTX @Bit 20 : Detect DMU Element Service */
14665   #define DMU_DMUI_DTX_Pos (20UL)                    /*!< Position of DTX field.                                               */
14666   #define DMU_DMUI_DTX_Msk (0x1UL << DMU_DMUI_DTX_Pos) /*!< Bit mask of DTX field.                                             */
14667   #define DMU_DMUI_DTX_Min (0x0UL)                   /*!< Min enumerator value of DTX field.                                   */
14668   #define DMU_DMUI_DTX_Max (0x1UL)                   /*!< Max enumerator value of DTX field.                                   */
14669   #define DMU_DMUI_DTX_Disabled (0x0UL)              /*!< Queueing of DMU Element does not activate interrupt flag             */
14670   #define DMU_DMUI_DTX_Enabled (0x1UL)               /*!< Queueing of DMU Element will activate interrupt flag when DMUI.EHS =
14671                                                           DMUI.DEHS*/
14672 
14673 /* DRX0 @Bit 21 : Detect DMU Element Service */
14674   #define DMU_DMUI_DRX0_Pos (21UL)                   /*!< Position of DRX0 field.                                              */
14675   #define DMU_DMUI_DRX0_Msk (0x1UL << DMU_DMUI_DRX0_Pos) /*!< Bit mask of DRX0 field.                                          */
14676   #define DMU_DMUI_DRX0_Min (0x0UL)                  /*!< Min enumerator value of DRX0 field.                                  */
14677   #define DMU_DMUI_DRX0_Max (0x1UL)                  /*!< Max enumerator value of DRX0 field.                                  */
14678   #define DMU_DMUI_DRX0_Disabled (0x0UL)             /*!< Queueing of DMU Element does not activate interrupt flag             */
14679   #define DMU_DMUI_DRX0_Enabled (0x1UL)              /*!< Queueing of DMU Element will activate interrupt flag when DMUI.EHS =
14680                                                           DMUI.DEHS*/
14681 
14682 /* DRX1 @Bit 22 : Detect DMU Element Service */
14683   #define DMU_DMUI_DRX1_Pos (22UL)                   /*!< Position of DRX1 field.                                              */
14684   #define DMU_DMUI_DRX1_Msk (0x1UL << DMU_DMUI_DRX1_Pos) /*!< Bit mask of DRX1 field.                                          */
14685   #define DMU_DMUI_DRX1_Min (0x0UL)                  /*!< Min enumerator value of DRX1 field.                                  */
14686   #define DMU_DMUI_DRX1_Max (0x1UL)                  /*!< Max enumerator value of DRX1 field.                                  */
14687   #define DMU_DMUI_DRX1_Disabled (0x0UL)             /*!< Queueing of DMU Element does not activate interrupt flag             */
14688   #define DMU_DMUI_DRX1_Enabled (0x1UL)              /*!< Queueing of DMU Element will activate interrupt flag when DMUI.EHS =
14689                                                           DMUI.DEHS*/
14690 
14691 /* DTXE @Bit 23 : Detect DMU Element Service */
14692   #define DMU_DMUI_DTXE_Pos (23UL)                   /*!< Position of DTXE field.                                              */
14693   #define DMU_DMUI_DTXE_Msk (0x1UL << DMU_DMUI_DTXE_Pos) /*!< Bit mask of DTXE field.                                          */
14694   #define DMU_DMUI_DTXE_Min (0x0UL)                  /*!< Min enumerator value of DTXE field.                                  */
14695   #define DMU_DMUI_DTXE_Max (0x1UL)                  /*!< Max enumerator value of DTXE field.                                  */
14696   #define DMU_DMUI_DTXE_Disabled (0x0UL)             /*!< Queueing of DMU Element does not activate interrupt flag             */
14697   #define DMU_DMUI_DTXE_Enabled (0x1UL)              /*!< Queueing of DMU Element will activate interrupt flag when DMUI.EHS =
14698                                                           DMUI.DEHS*/
14699 
14700 /* EHS @Bits 24..26 : Element Handler State */
14701   #define DMU_DMUI_EHS_Pos (24UL)                    /*!< Position of EHS field.                                               */
14702   #define DMU_DMUI_EHS_Msk (0x7UL << DMU_DMUI_EHS_Pos) /*!< Bit mask of EHS field.                                             */
14703   #define DMU_DMUI_EHS_Min (0x0UL)                   /*!< Min enumerator value of EHS field.                                   */
14704   #define DMU_DMUI_EHS_Max (0x5UL)                   /*!< Max enumerator value of EHS field.                                   */
14705   #define DMU_DMUI_EHS_wait4cce (0x0UL)              /*!< wait for bit MCAN:CCCR.CCE getting zero                              */
14706   #define DMU_DMUI_EHS_wait4sa (0x1UL)               /*!< wait for Start Address                                               */
14707   #define DMU_DMUI_EHS_wait4ta (0x2UL)               /*!< wait for Trigger Address                                             */
14708   #define DMU_DMUI_EHS_transfer (0x3UL)              /*!< wait for transfer of Element word                                    */
14709   #define DMU_DMUI_EHS_ack2mcan (0x4UL)              /*!< acknowledge to MCAN                                                  */
14710   #define DMU_DMUI_EHS_recovery (0x5UL)              /*!< exception recovery                                                   */
14711 
14712 /* TX @Bit 28 : Actual DMU Element Service */
14713   #define DMU_DMUI_TX_Pos (28UL)                     /*!< Position of TX field.                                                */
14714   #define DMU_DMUI_TX_Msk (0x1UL << DMU_DMUI_TX_Pos) /*!< Bit mask of TX field.                                                */
14715   #define DMU_DMUI_TX_Min (0x0UL)                    /*!< Min enumerator value of TX field.                                    */
14716   #define DMU_DMUI_TX_Max (0x1UL)                    /*!< Max enumerator value of TX field.                                    */
14717   #define DMU_DMUI_TX_NotServed (0x0UL)              /*!< DMU Virtual Buffer is currently not served                           */
14718   #define DMU_DMUI_TX_Served (0x1UL)                 /*!< DMU Virtual Buffer is currently served                               */
14719 
14720 /* RX0 @Bit 29 : Actual DMU Element Service */
14721   #define DMU_DMUI_RX0_Pos (29UL)                    /*!< Position of RX0 field.                                               */
14722   #define DMU_DMUI_RX0_Msk (0x1UL << DMU_DMUI_RX0_Pos) /*!< Bit mask of RX0 field.                                             */
14723   #define DMU_DMUI_RX0_Min (0x0UL)                   /*!< Min enumerator value of RX0 field.                                   */
14724   #define DMU_DMUI_RX0_Max (0x1UL)                   /*!< Max enumerator value of RX0 field.                                   */
14725   #define DMU_DMUI_RX0_NotServed (0x0UL)             /*!< DMU Virtual Buffer is currently not served                           */
14726   #define DMU_DMUI_RX0_Served (0x1UL)                /*!< DMU Virtual Buffer is currently served                               */
14727 
14728 /* RX1 @Bit 30 : Actual DMU Element Service */
14729   #define DMU_DMUI_RX1_Pos (30UL)                    /*!< Position of RX1 field.                                               */
14730   #define DMU_DMUI_RX1_Msk (0x1UL << DMU_DMUI_RX1_Pos) /*!< Bit mask of RX1 field.                                             */
14731   #define DMU_DMUI_RX1_Min (0x0UL)                   /*!< Min enumerator value of RX1 field.                                   */
14732   #define DMU_DMUI_RX1_Max (0x1UL)                   /*!< Max enumerator value of RX1 field.                                   */
14733   #define DMU_DMUI_RX1_NotServed (0x0UL)             /*!< DMU Virtual Buffer is currently not served                           */
14734   #define DMU_DMUI_RX1_Served (0x1UL)                /*!< DMU Virtual Buffer is currently served                               */
14735 
14736 /* TXE @Bit 31 : Actual DMU Element Service */
14737   #define DMU_DMUI_TXE_Pos (31UL)                    /*!< Position of TXE field.                                               */
14738   #define DMU_DMUI_TXE_Msk (0x1UL << DMU_DMUI_TXE_Pos) /*!< Bit mask of TXE field.                                             */
14739   #define DMU_DMUI_TXE_Min (0x0UL)                   /*!< Min enumerator value of TXE field.                                   */
14740   #define DMU_DMUI_TXE_Max (0x1UL)                   /*!< Max enumerator value of TXE field.                                   */
14741   #define DMU_DMUI_TXE_NotServed (0x0UL)             /*!< DMU Virtual Buffer is currently not served                           */
14742   #define DMU_DMUI_TXE_Served (0x1UL)                /*!< DMU Virtual Buffer is currently served                               */
14743 
14744 
14745 /* DMU_DMUQC: DMU Queueing Counter */
14746   #define DMU_DMUQC_ResetValue (0x00000000UL)        /*!< Reset value of DMUQC register.                                       */
14747 
14748 /* TXEEC @Bits 0..7 : TX Element Enqueueing Counter */
14749   #define DMU_DMUQC_TXEEC_Pos (0UL)                  /*!< Position of TXEEC field.                                             */
14750   #define DMU_DMUQC_TXEEC_Msk (0xFFUL << DMU_DMUQC_TXEEC_Pos) /*!< Bit mask of TXEEC field.                                    */
14751 
14752 /* RX0EDC @Bits 8..15 : RX0 Element Dequeueing Counter */
14753   #define DMU_DMUQC_RX0EDC_Pos (8UL)                 /*!< Position of RX0EDC field.                                            */
14754   #define DMU_DMUQC_RX0EDC_Msk (0xFFUL << DMU_DMUQC_RX0EDC_Pos) /*!< Bit mask of RX0EDC field.                                 */
14755 
14756 /* RX1EDC @Bits 16..23 : RX1 Element Dequeueing Counter */
14757   #define DMU_DMUQC_RX1EDC_Pos (16UL)                /*!< Position of RX1EDC field.                                            */
14758   #define DMU_DMUQC_RX1EDC_Msk (0xFFUL << DMU_DMUQC_RX1EDC_Pos) /*!< Bit mask of RX1EDC field.                                 */
14759 
14760 /* TXEEDC @Bits 24..31 : TX Event Element Dequeueing Counter */
14761   #define DMU_DMUQC_TXEEDC_Pos (24UL)                /*!< Position of TXEEDC field.                                            */
14762   #define DMU_DMUQC_TXEEDC_Msk (0xFFUL << DMU_DMUQC_TXEEDC_Pos) /*!< Bit mask of TXEEDC field.                                 */
14763 
14764 
14765 /* DMU_DMUIR: DMU Interrupt Register */
14766   #define DMU_DMUIR_ResetValue (0x00000000UL)        /*!< Reset value of DMUIR register.                                       */
14767 
14768 /* TXENSA @Bit 0 : TX Element Not Start Address */
14769   #define DMU_DMUIR_TXENSA_Pos (0UL)                 /*!< Position of TXENSA field.                                            */
14770   #define DMU_DMUIR_TXENSA_Msk (0x1UL << DMU_DMUIR_TXENSA_Pos) /*!< Bit mask of TXENSA field.                                  */
14771   #define DMU_DMUIR_TXENSA_Min (0x0UL)               /*!< Min enumerator value of TXENSA field.                                */
14772   #define DMU_DMUIR_TXENSA_Max (0x1UL)               /*!< Max enumerator value of TXENSA field.                                */
14773   #define DMU_DMUIR_TXENSA_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14774   #define DMU_DMUIR_TXENSA_NotGenerated (0x0UL)      /*!< No illegal write access                                              */
14775   #define DMU_DMUIR_TXENSA_Generated (0x1UL)         /*!< Write to TX Element begins without using start address, exception
14776                                                           recovery started.*/
14777 
14778 /* TXEIE @Bit 1 : TX Element Illegal Enqueueing */
14779   #define DMU_DMUIR_TXEIE_Pos (1UL)                  /*!< Position of TXEIE field.                                             */
14780   #define DMU_DMUIR_TXEIE_Msk (0x1UL << DMU_DMUIR_TXEIE_Pos) /*!< Bit mask of TXEIE field.                                     */
14781   #define DMU_DMUIR_TXEIE_Min (0x0UL)                /*!< Min enumerator value of TXEIE field.                                 */
14782   #define DMU_DMUIR_TXEIE_Max (0x1UL)                /*!< Max enumerator value of TXEIE field.                                 */
14783   #define DMU_DMUIR_TXEIE_Clear (0x1UL)              /*!< Write '1' to clear interrupt flag                                    */
14784   #define DMU_DMUIR_TXEIE_NotGenerated (0x0UL)       /*!< No illegal enqueueing                                                */
14785   #define DMU_DMUIR_TXEIE_Generated (0x1UL)          /*!< Start of enqueueing without request detected, exception recovery
14786                                                           started.*/
14787 
14788 /* TXEIAS @Bit 2 : TX Element Illegal Access Sequence */
14789   #define DMU_DMUIR_TXEIAS_Pos (2UL)                 /*!< Position of TXEIAS field.                                            */
14790   #define DMU_DMUIR_TXEIAS_Msk (0x1UL << DMU_DMUIR_TXEIAS_Pos) /*!< Bit mask of TXEIAS field.                                  */
14791   #define DMU_DMUIR_TXEIAS_Min (0x0UL)               /*!< Min enumerator value of TXEIAS field.                                */
14792   #define DMU_DMUIR_TXEIAS_Max (0x1UL)               /*!< Max enumerator value of TXEIAS field.                                */
14793   #define DMU_DMUIR_TXEIAS_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14794   #define DMU_DMUIR_TXEIAS_NotGenerated (0x0UL)      /*!< No illegal addressing sequence detected                              */
14795   #define DMU_DMUIR_TXEIAS_Generated (0x1UL)         /*!< Accesses are not strictly linear to ascending and consecutive
14796                                                           addresses, exception recovery started.*/
14797 
14798 /* TXEIDLC @Bit 3 : TX Element Illegal DLC */
14799   #define DMU_DMUIR_TXEIDLC_Pos (3UL)                /*!< Position of TXEIDLC field.                                           */
14800   #define DMU_DMUIR_TXEIDLC_Msk (0x1UL << DMU_DMUIR_TXEIDLC_Pos) /*!< Bit mask of TXEIDLC field.                               */
14801   #define DMU_DMUIR_TXEIDLC_Min (0x0UL)              /*!< Min enumerator value of TXEIDLC field.                               */
14802   #define DMU_DMUIR_TXEIDLC_Max (0x1UL)              /*!< Max enumerator value of TXEIDLC field.                               */
14803   #define DMU_DMUIR_TXEIDLC_Clear (0x1UL)            /*!< Write '1' to clear interrupt flag                                    */
14804   #define DMU_DMUIR_TXEIDLC_NotGenerated (0x0UL)     /*!< No illegal DLC detected                                              */
14805   #define DMU_DMUIR_TXEIDLC_Generated (0x1UL)        /*!< DLC exceeds Tx Buffer element size of MCAN, exception recovery
14806                                                           started.*/
14807 
14808 /* TXEWATA @Bit 4 : TX Element Write After Trigger Address */
14809   #define DMU_DMUIR_TXEWATA_Pos (4UL)                /*!< Position of TXEWATA field.                                           */
14810   #define DMU_DMUIR_TXEWATA_Msk (0x1UL << DMU_DMUIR_TXEWATA_Pos) /*!< Bit mask of TXEWATA field.                               */
14811   #define DMU_DMUIR_TXEWATA_Min (0x0UL)              /*!< Min enumerator value of TXEWATA field.                               */
14812   #define DMU_DMUIR_TXEWATA_Max (0x1UL)              /*!< Max enumerator value of TXEWATA field.                               */
14813   #define DMU_DMUIR_TXEWATA_Clear (0x1UL)            /*!< Write '1' to clear interrupt flag                                    */
14814   #define DMU_DMUIR_TXEWATA_NotGenerated (0x0UL)     /*!< No write after Trigger Address                                       */
14815   #define DMU_DMUIR_TXEWATA_Generated (0x1UL)        /*!< Write after Trigger address detected                                 */
14816 
14817 /* TXEIR @Bit 5 : TX Element Illegal Read */
14818   #define DMU_DMUIR_TXEIR_Pos (5UL)                  /*!< Position of TXEIR field.                                             */
14819   #define DMU_DMUIR_TXEIR_Msk (0x1UL << DMU_DMUIR_TXEIR_Pos) /*!< Bit mask of TXEIR field.                                     */
14820   #define DMU_DMUIR_TXEIR_Min (0x0UL)                /*!< Min enumerator value of TXEIR field.                                 */
14821   #define DMU_DMUIR_TXEIR_Max (0x1UL)                /*!< Max enumerator value of TXEIR field.                                 */
14822   #define DMU_DMUIR_TXEIR_Clear (0x1UL)              /*!< Write '1' to clear interrupt flag                                    */
14823   #define DMU_DMUIR_TXEIR_NotGenerated (0x0UL)       /*!< No read access                                                       */
14824   #define DMU_DMUIR_TXEIR_Generated (0x1UL)          /*!< Illegal read access to DMU TX Element section detected, exception
14825                                                           recovery started.*/
14826 
14827 /* TXEE @Bit 6 : A successful enqueueing of a Tx message with the DMU TX Element section sets this flag. */
14828   #define DMU_DMUIR_TXEE_Pos (6UL)                   /*!< Position of TXEE field.                                              */
14829   #define DMU_DMUIR_TXEE_Msk (0x1UL << DMU_DMUIR_TXEE_Pos) /*!< Bit mask of TXEE field.                                        */
14830   #define DMU_DMUIR_TXEE_Min (0x0UL)                 /*!< Min enumerator value of TXEE field.                                  */
14831   #define DMU_DMUIR_TXEE_Max (0x1UL)                 /*!< Max enumerator value of TXEE field.                                  */
14832   #define DMU_DMUIR_TXEE_Clear (0x1UL)               /*!< Write '1' to clear interrupt flag                                    */
14833   #define DMU_DMUIR_TXEE_NotGenerated (0x0UL)        /*!< No Tx message enqueued                                               */
14834   #define DMU_DMUIR_TXEE_Generated (0x1UL)           /*!< Tx message successfully enqueued                                     */
14835 
14836 /* RX0ENSA @Bit 7 : RX0 Element Not Start Address */
14837   #define DMU_DMUIR_RX0ENSA_Pos (7UL)                /*!< Position of RX0ENSA field.                                           */
14838   #define DMU_DMUIR_RX0ENSA_Msk (0x1UL << DMU_DMUIR_RX0ENSA_Pos) /*!< Bit mask of RX0ENSA field.                               */
14839   #define DMU_DMUIR_RX0ENSA_Min (0x0UL)              /*!< Min enumerator value of RX0ENSA field.                               */
14840   #define DMU_DMUIR_RX0ENSA_Max (0x1UL)              /*!< Max enumerator value of RX0ENSA field.                               */
14841   #define DMU_DMUIR_RX0ENSA_Clear (0x1UL)            /*!< Write '1' to clear interrupt flag                                    */
14842   #define DMU_DMUIR_RX0ENSA_NotGenerated (0x0UL)     /*!< No illegal read access                                               */
14843   #define DMU_DMUIR_RX0ENSA_Generated (0x1UL)        /*!< Read from RX0 Element begins without using start address, exception
14844                                                           recovery started.*/
14845 
14846 /* RX0EID @Bit 8 : RX0 Element Illegal Dequeueing */
14847   #define DMU_DMUIR_RX0EID_Pos (8UL)                 /*!< Position of RX0EID field.                                            */
14848   #define DMU_DMUIR_RX0EID_Msk (0x1UL << DMU_DMUIR_RX0EID_Pos) /*!< Bit mask of RX0EID field.                                  */
14849   #define DMU_DMUIR_RX0EID_Min (0x0UL)               /*!< Min enumerator value of RX0EID field.                                */
14850   #define DMU_DMUIR_RX0EID_Max (0x1UL)               /*!< Max enumerator value of RX0EID field.                                */
14851   #define DMU_DMUIR_RX0EID_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14852   #define DMU_DMUIR_RX0EID_NotGenerated (0x0UL)      /*!< No illegal dequeueing                                                */
14853   #define DMU_DMUIR_RX0EID_Generated (0x1UL)         /*!< Start of dequeueing without request detected, exception recovery
14854                                                           started,*/
14855 
14856 /* RX0EIAS @Bit 9 : RX0 Element Illegal Access Sequence */
14857   #define DMU_DMUIR_RX0EIAS_Pos (9UL)                /*!< Position of RX0EIAS field.                                           */
14858   #define DMU_DMUIR_RX0EIAS_Msk (0x1UL << DMU_DMUIR_RX0EIAS_Pos) /*!< Bit mask of RX0EIAS field.                               */
14859   #define DMU_DMUIR_RX0EIAS_Min (0x0UL)              /*!< Min enumerator value of RX0EIAS field.                               */
14860   #define DMU_DMUIR_RX0EIAS_Max (0x1UL)              /*!< Max enumerator value of RX0EIAS field.                               */
14861   #define DMU_DMUIR_RX0EIAS_Clear (0x1UL)            /*!< Write '1' to clear interrupt flag                                    */
14862   #define DMU_DMUIR_RX0EIAS_NotGenerated (0x0UL)     /*!< No illegal addressing sequence detected                              */
14863   #define DMU_DMUIR_RX0EIAS_Generated (0x1UL)        /*!< Accesses are not strictly linear to ascending and consecutive
14864                                                           addresses, exception recovery started.*/
14865 
14866 /* RX0EIW @Bit 10 : RX0 Element Illegal Write */
14867   #define DMU_DMUIR_RX0EIW_Pos (10UL)                /*!< Position of RX0EIW field.                                            */
14868   #define DMU_DMUIR_RX0EIW_Msk (0x1UL << DMU_DMUIR_RX0EIW_Pos) /*!< Bit mask of RX0EIW field.                                  */
14869   #define DMU_DMUIR_RX0EIW_Min (0x0UL)               /*!< Min enumerator value of RX0EIW field.                                */
14870   #define DMU_DMUIR_RX0EIW_Max (0x1UL)               /*!< Max enumerator value of RX0EIW field.                                */
14871   #define DMU_DMUIR_RX0EIW_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14872   #define DMU_DMUIR_RX0EIW_NotGenerated (0x0UL)      /*!< No write access detected                                             */
14873   #define DMU_DMUIR_RX0EIW_Generated (0x1UL)         /*!< Illegal write access to DMU RX0 Element detected, exception recovery
14874                                                           started.*/
14875 
14876 /* RX0ED @Bit 11 : RX0 Element Dequeued */
14877   #define DMU_DMUIR_RX0ED_Pos (11UL)                 /*!< Position of RX0ED field.                                             */
14878   #define DMU_DMUIR_RX0ED_Msk (0x1UL << DMU_DMUIR_RX0ED_Pos) /*!< Bit mask of RX0ED field.                                     */
14879   #define DMU_DMUIR_RX0ED_Min (0x0UL)                /*!< Min enumerator value of RX0ED field.                                 */
14880   #define DMU_DMUIR_RX0ED_Max (0x1UL)                /*!< Max enumerator value of RX0ED field.                                 */
14881   #define DMU_DMUIR_RX0ED_Clear (0x1UL)              /*!< Write '1' to clear interrupt flag                                    */
14882   #define DMU_DMUIR_RX0ED_NotGenerated (0x0UL)       /*!< No Rx message dequeued                                               */
14883   #define DMU_DMUIR_RX0ED_Generated (0x1UL)          /*!< Rx message successfully dequeued                                     */
14884 
14885 /* RX0EIO @Bit 12 : RX0 Element Illegal Overwrite by timestamp */
14886   #define DMU_DMUIR_RX0EIO_Pos (12UL)                /*!< Position of RX0EIO field.                                            */
14887   #define DMU_DMUIR_RX0EIO_Msk (0x1UL << DMU_DMUIR_RX0EIO_Pos) /*!< Bit mask of RX0EIO field.                                  */
14888   #define DMU_DMUIR_RX0EIO_Min (0x0UL)               /*!< Min enumerator value of RX0EIO field.                                */
14889   #define DMU_DMUIR_RX0EIO_Max (0x1UL)               /*!< Max enumerator value of RX0EIO field.                                */
14890   #define DMU_DMUIR_RX0EIO_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14891   #define DMU_DMUIR_RX0EIO_NotGenerated (0x0UL)      /*!< No illegal overwrite detected                                        */
14892   #define DMU_DMUIR_RX0EIO_Generated (0x1UL)         /*!< DMU has internally overwritten the last element word of a SYNC
14893                                                           message*/
14894 
14895 /* BEU @Bit 15 : Bus Error Uncorrected */
14896   #define DMU_DMUIR_BEU_Pos (15UL)                   /*!< Position of BEU field.                                               */
14897   #define DMU_DMUIR_BEU_Msk (0x1UL << DMU_DMUIR_BEU_Pos) /*!< Bit mask of BEU field.                                           */
14898   #define DMU_DMUIR_BEU_Min (0x0UL)                  /*!< Min enumerator value of BEU field.                                   */
14899   #define DMU_DMUIR_BEU_Max (0x1UL)                  /*!< Max enumerator value of BEU field.                                   */
14900   #define DMU_DMUIR_BEU_Clear (0x1UL)                /*!< Write '1' to clear interrupt flag                                    */
14901   #define DMU_DMUIR_BEU_NotGenerated (0x0UL)         /*!< No read slave error detected when reading from Message RAM           */
14902   #define DMU_DMUIR_BEU_Generated (0x1UL)            /*!< Read slave error detected                                            */
14903 
14904 /* RX1ENSA @Bit 16 : RX1 Element Not Start Address */
14905   #define DMU_DMUIR_RX1ENSA_Pos (16UL)               /*!< Position of RX1ENSA field.                                           */
14906   #define DMU_DMUIR_RX1ENSA_Msk (0x1UL << DMU_DMUIR_RX1ENSA_Pos) /*!< Bit mask of RX1ENSA field.                               */
14907   #define DMU_DMUIR_RX1ENSA_Min (0x0UL)              /*!< Min enumerator value of RX1ENSA field.                               */
14908   #define DMU_DMUIR_RX1ENSA_Max (0x1UL)              /*!< Max enumerator value of RX1ENSA field.                               */
14909   #define DMU_DMUIR_RX1ENSA_Clear (0x1UL)            /*!< Write '1' to clear interrupt flag                                    */
14910   #define DMU_DMUIR_RX1ENSA_NotGenerated (0x0UL)     /*!< No illegal read access                                               */
14911   #define DMU_DMUIR_RX1ENSA_Generated (0x1UL)        /*!< Read from RX1 Element begins without using start address, exception
14912                                                           recovery started.*/
14913 
14914 /* RX1EID @Bit 17 : RX1 Element Illegal Dequeueing */
14915   #define DMU_DMUIR_RX1EID_Pos (17UL)                /*!< Position of RX1EID field.                                            */
14916   #define DMU_DMUIR_RX1EID_Msk (0x1UL << DMU_DMUIR_RX1EID_Pos) /*!< Bit mask of RX1EID field.                                  */
14917   #define DMU_DMUIR_RX1EID_Min (0x0UL)               /*!< Min enumerator value of RX1EID field.                                */
14918   #define DMU_DMUIR_RX1EID_Max (0x1UL)               /*!< Max enumerator value of RX1EID field.                                */
14919   #define DMU_DMUIR_RX1EID_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14920   #define DMU_DMUIR_RX1EID_NotGenerated (0x0UL)      /*!< No illegal dequeueing                                                */
14921   #define DMU_DMUIR_RX1EID_Generated (0x1UL)         /*!< Start of dequeueing without request detected, exception recovery
14922                                                           started,*/
14923 
14924 /* RX1EIAS @Bit 18 : RX0 Element Illegal Access Sequence */
14925   #define DMU_DMUIR_RX1EIAS_Pos (18UL)               /*!< Position of RX1EIAS field.                                           */
14926   #define DMU_DMUIR_RX1EIAS_Msk (0x1UL << DMU_DMUIR_RX1EIAS_Pos) /*!< Bit mask of RX1EIAS field.                               */
14927   #define DMU_DMUIR_RX1EIAS_Min (0x0UL)              /*!< Min enumerator value of RX1EIAS field.                               */
14928   #define DMU_DMUIR_RX1EIAS_Max (0x1UL)              /*!< Max enumerator value of RX1EIAS field.                               */
14929   #define DMU_DMUIR_RX1EIAS_Clear (0x1UL)            /*!< Write '1' to clear interrupt flag                                    */
14930   #define DMU_DMUIR_RX1EIAS_NotGenerated (0x0UL)     /*!< No illegal addressing sequence detected                              */
14931   #define DMU_DMUIR_RX1EIAS_Generated (0x1UL)        /*!< Accesses are not strictly linear to ascending and consecutive
14932                                                           addresses, exception recovery started.*/
14933 
14934 /* RX1EIW @Bit 19 : RX1 Element Illegal Write */
14935   #define DMU_DMUIR_RX1EIW_Pos (19UL)                /*!< Position of RX1EIW field.                                            */
14936   #define DMU_DMUIR_RX1EIW_Msk (0x1UL << DMU_DMUIR_RX1EIW_Pos) /*!< Bit mask of RX1EIW field.                                  */
14937   #define DMU_DMUIR_RX1EIW_Min (0x0UL)               /*!< Min enumerator value of RX1EIW field.                                */
14938   #define DMU_DMUIR_RX1EIW_Max (0x1UL)               /*!< Max enumerator value of RX1EIW field.                                */
14939   #define DMU_DMUIR_RX1EIW_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14940   #define DMU_DMUIR_RX1EIW_NotGenerated (0x0UL)      /*!< No write access detected                                             */
14941   #define DMU_DMUIR_RX1EIW_Generated (0x1UL)         /*!< Illegal write access to DMU RX1 Element detected, exception recovery
14942                                                           started.*/
14943 
14944 /* RX1ED @Bit 20 : RX0 Element Dequeued */
14945   #define DMU_DMUIR_RX1ED_Pos (20UL)                 /*!< Position of RX1ED field.                                             */
14946   #define DMU_DMUIR_RX1ED_Msk (0x1UL << DMU_DMUIR_RX1ED_Pos) /*!< Bit mask of RX1ED field.                                     */
14947   #define DMU_DMUIR_RX1ED_Min (0x0UL)                /*!< Min enumerator value of RX1ED field.                                 */
14948   #define DMU_DMUIR_RX1ED_Max (0x1UL)                /*!< Max enumerator value of RX1ED field.                                 */
14949   #define DMU_DMUIR_RX1ED_Clear (0x1UL)              /*!< Write '1' to clear interrupt flag                                    */
14950   #define DMU_DMUIR_RX1ED_NotGenerated (0x0UL)       /*!< No Rx message dequeued                                               */
14951   #define DMU_DMUIR_RX1ED_Generated (0x1UL)          /*!< Rx message successfully dequeued                                     */
14952 
14953 /* RX1EIO @Bit 21 : RX1 Element Illegal Overwrite by timestamp */
14954   #define DMU_DMUIR_RX1EIO_Pos (21UL)                /*!< Position of RX1EIO field.                                            */
14955   #define DMU_DMUIR_RX1EIO_Msk (0x1UL << DMU_DMUIR_RX1EIO_Pos) /*!< Bit mask of RX1EIO field.                                  */
14956   #define DMU_DMUIR_RX1EIO_Min (0x0UL)               /*!< Min enumerator value of RX1EIO field.                                */
14957   #define DMU_DMUIR_RX1EIO_Max (0x1UL)               /*!< Max enumerator value of RX1EIO field.                                */
14958   #define DMU_DMUIR_RX1EIO_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14959   #define DMU_DMUIR_RX1EIO_NotGenerated (0x0UL)      /*!< No illegal overwrite detected                                        */
14960   #define DMU_DMUIR_RX1EIO_Generated (0x1UL)         /*!< DMU has internally overwritten the last element word of a SYNC
14961                                                           message*/
14962 
14963 /* TXEENSA @Bit 24 : TX Event Element Not Start Address */
14964   #define DMU_DMUIR_TXEENSA_Pos (24UL)               /*!< Position of TXEENSA field.                                           */
14965   #define DMU_DMUIR_TXEENSA_Msk (0x1UL << DMU_DMUIR_TXEENSA_Pos) /*!< Bit mask of TXEENSA field.                               */
14966   #define DMU_DMUIR_TXEENSA_Min (0x0UL)              /*!< Min enumerator value of TXEENSA field.                               */
14967   #define DMU_DMUIR_TXEENSA_Max (0x1UL)              /*!< Max enumerator value of TXEENSA field.                               */
14968   #define DMU_DMUIR_TXEENSA_Clear (0x1UL)            /*!< Write '1' to clear interrupt flag                                    */
14969   #define DMU_DMUIR_TXEENSA_NotGenerated (0x0UL)     /*!< No illegal read access                                               */
14970   #define DMU_DMUIR_TXEENSA_Generated (0x1UL)        /*!< Read from TX Event Element begins without using start address,
14971                                                           exception recovery started.*/
14972 
14973 /* TXEEID @Bit 25 : TX Event Element Illegal Dequeueing */
14974   #define DMU_DMUIR_TXEEID_Pos (25UL)                /*!< Position of TXEEID field.                                            */
14975   #define DMU_DMUIR_TXEEID_Msk (0x1UL << DMU_DMUIR_TXEEID_Pos) /*!< Bit mask of TXEEID field.                                  */
14976   #define DMU_DMUIR_TXEEID_Min (0x0UL)               /*!< Min enumerator value of TXEEID field.                                */
14977   #define DMU_DMUIR_TXEEID_Max (0x1UL)               /*!< Max enumerator value of TXEEID field.                                */
14978   #define DMU_DMUIR_TXEEID_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14979   #define DMU_DMUIR_TXEEID_NotGenerated (0x0UL)      /*!< No illegal dequeueing                                                */
14980   #define DMU_DMUIR_TXEEID_Generated (0x1UL)         /*!< Start of dequeueing without request detected, exception recovery
14981                                                           started.*/
14982 
14983 /* TXEEIAS @Bit 26 : TX Event Element Illegal Access Sequence */
14984   #define DMU_DMUIR_TXEEIAS_Pos (26UL)               /*!< Position of TXEEIAS field.                                           */
14985   #define DMU_DMUIR_TXEEIAS_Msk (0x1UL << DMU_DMUIR_TXEEIAS_Pos) /*!< Bit mask of TXEEIAS field.                               */
14986   #define DMU_DMUIR_TXEEIAS_Min (0x0UL)              /*!< Min enumerator value of TXEEIAS field.                               */
14987   #define DMU_DMUIR_TXEEIAS_Max (0x1UL)              /*!< Max enumerator value of TXEEIAS field.                               */
14988   #define DMU_DMUIR_TXEEIAS_Clear (0x1UL)            /*!< Write '1' to clear interrupt flag                                    */
14989   #define DMU_DMUIR_TXEEIAS_NotGenerated (0x0UL)     /*!< No illegal addressing sequence detected                              */
14990   #define DMU_DMUIR_TXEEIAS_Generated (0x1UL)        /*!< Accesses are not strictly linear to ascending and consecutive
14991                                                           addresses, exception recovery started.*/
14992 
14993 /* TXEEIW @Bit 27 : TX Event Element Illegal Write */
14994   #define DMU_DMUIR_TXEEIW_Pos (27UL)                /*!< Position of TXEEIW field.                                            */
14995   #define DMU_DMUIR_TXEEIW_Msk (0x1UL << DMU_DMUIR_TXEEIW_Pos) /*!< Bit mask of TXEEIW field.                                  */
14996   #define DMU_DMUIR_TXEEIW_Min (0x0UL)               /*!< Min enumerator value of TXEEIW field.                                */
14997   #define DMU_DMUIR_TXEEIW_Max (0x1UL)               /*!< Max enumerator value of TXEEIW field.                                */
14998   #define DMU_DMUIR_TXEEIW_Clear (0x1UL)             /*!< Write '1' to clear interrupt flag                                    */
14999   #define DMU_DMUIR_TXEEIW_NotGenerated (0x0UL)      /*!< No write access detected                                             */
15000   #define DMU_DMUIR_TXEEIW_Generated (0x1UL)         /*!< Illegal write access to DMU TX Event Element detected, exception
15001                                                           recovery started.*/
15002 
15003 /* TXEED @Bit 28 : TX Event Element Dequeued */
15004   #define DMU_DMUIR_TXEED_Pos (28UL)                 /*!< Position of TXEED field.                                             */
15005   #define DMU_DMUIR_TXEED_Msk (0x1UL << DMU_DMUIR_TXEED_Pos) /*!< Bit mask of TXEED field.                                     */
15006   #define DMU_DMUIR_TXEED_Min (0x0UL)                /*!< Min enumerator value of TXEED field.                                 */
15007   #define DMU_DMUIR_TXEED_Max (0x1UL)                /*!< Max enumerator value of TXEED field.                                 */
15008   #define DMU_DMUIR_TXEED_Clear (0x1UL)              /*!< Write '1' to clear interrupt flag                                    */
15009   #define DMU_DMUIR_TXEED_NotGenerated (0x0UL)       /*!< No TX Event Element dequeued                                         */
15010   #define DMU_DMUIR_TXEED_Generated (0x1UL)          /*!< TX Event Element successfully dequeued                               */
15011 
15012 /* DT @Bit 29 : Debug Trigger */
15013   #define DMU_DMUIR_DT_Pos (29UL)                    /*!< Position of DT field.                                                */
15014   #define DMU_DMUIR_DT_Msk (0x1UL << DMU_DMUIR_DT_Pos) /*!< Bit mask of DT field.                                              */
15015   #define DMU_DMUIR_DT_Min (0x0UL)                   /*!< Min enumerator value of DT field.                                    */
15016   #define DMU_DMUIR_DT_Max (0x1UL)                   /*!< Max enumerator value of DT field.                                    */
15017   #define DMU_DMUIR_DT_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
15018   #define DMU_DMUIR_DT_NotGenerated (0x0UL)          /*!< Debug point not reached                                              */
15019   #define DMU_DMUIR_DT_Generated (0x1UL)             /*!< Debug point reached                                                  */
15020 
15021 /* IAC @Bit 30 : Illegal Access while in Configuration mode */
15022   #define DMU_DMUIR_IAC_Pos (30UL)                   /*!< Position of IAC field.                                               */
15023   #define DMU_DMUIR_IAC_Msk (0x1UL << DMU_DMUIR_IAC_Pos) /*!< Bit mask of IAC field.                                           */
15024   #define DMU_DMUIR_IAC_Min (0x0UL)                  /*!< Min enumerator value of IAC field.                                   */
15025   #define DMU_DMUIR_IAC_Max (0x1UL)                  /*!< Max enumerator value of IAC field.                                   */
15026   #define DMU_DMUIR_IAC_Clear (0x1UL)                /*!< Write '1' to clear interrupt flag                                    */
15027   #define DMU_DMUIR_IAC_NotGenerated (0x0UL)         /*!< No Illegal Access while CCE mode                                     */
15028   #define DMU_DMUIR_IAC_Generated (0x1UL)            /*!< Illegal Access while CCE mode                                        */
15029 
15030 
15031 /* DMU_DMUIE: DMU Interrupt Enable */
15032   #define DMU_DMUIE_ResetValue (0x00000000UL)        /*!< Reset value of DMUIE register.                                       */
15033 
15034 /* TXENSAE @Bit 0 : TX Element Not Start Address Enable */
15035   #define DMU_DMUIE_TXENSAE_Pos (0UL)                /*!< Position of TXENSAE field.                                           */
15036   #define DMU_DMUIE_TXENSAE_Msk (0x1UL << DMU_DMUIE_TXENSAE_Pos) /*!< Bit mask of TXENSAE field.                               */
15037   #define DMU_DMUIE_TXENSAE_Min (0x0UL)              /*!< Min enumerator value of TXENSAE field.                               */
15038   #define DMU_DMUIE_TXENSAE_Max (0x1UL)              /*!< Max enumerator value of TXENSAE field.                               */
15039   #define DMU_DMUIE_TXENSAE_Disabled (0x0UL)         /*!< Flag does not activate the interrupt line DMU                        */
15040   #define DMU_DMUIE_TXENSAE_Enabled (0x1UL)          /*!< the interrupt line DMU will be activated                             */
15041 
15042 
15043 /* DMU_DMUC: DMU Configuration */
15044   #define DMU_DMUC_ResetValue (0x00000000UL)         /*!< Reset value of DMUC register.                                        */
15045 
15046 /* TTS @Bit 0 : Transfer Timestamp */
15047   #define DMU_DMUC_TTS_Pos (0UL)                     /*!< Position of TTS field.                                               */
15048   #define DMU_DMUC_TTS_Msk (0x1UL << DMU_DMUC_TTS_Pos) /*!< Bit mask of TTS field.                                             */
15049   #define DMU_DMUC_TTS_Min (0x0UL)                   /*!< Min enumerator value of TTS field.                                   */
15050   #define DMU_DMUC_TTS_Max (0x1UL)                   /*!< Max enumerator value of TTS field.                                   */
15051   #define DMU_DMUC_TTS_Disabled (0x0UL)              /*!< No timestamp will be transferred via DMU Virtual Buffer              */
15052   #define DMU_DMUC_TTS_Enabled (0x1UL)               /*!< Timestamp of message will be transferred from TSU via DMU Virtual
15053                                                           Buffer*/
15054 
15055 
15056 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
15057 
15058 /* =========================================================================================================================== */
15059 /* ================                                           DPPIC                                           ================ */
15060 /* =========================================================================================================================== */
15061 
15062 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
15063 
15064 /* ================================================= Struct DPPIC_TASKS_CHG ================================================== */
15065 /**
15066   * @brief TASKS_CHG [DPPIC_TASKS_CHG] Channel group tasks
15067   */
15068 typedef struct {
15069   __OM  uint32_t  EN;                                /*!< (@ 0x00000000) Enable channel group n                                */
15070   __OM  uint32_t  DIS;                               /*!< (@ 0x00000004) Disable channel group n                               */
15071 } NRF_DPPIC_TASKS_CHG_Type;                          /*!< Size = 8 (0x008)                                                     */
15072   #define DPPIC_TASKS_CHG_MaxCount (2UL)             /*!< Size of TASKS_CHG[2] array.                                          */
15073   #define DPPIC_TASKS_CHG_MaxIndex (1UL)             /*!< Max index of TASKS_CHG[2] array.                                     */
15074   #define DPPIC_TASKS_CHG_MinIndex (0UL)             /*!< Min index of TASKS_CHG[2] array.                                     */
15075 
15076 /* DPPIC_TASKS_CHG_EN: Enable channel group n */
15077   #define DPPIC_TASKS_CHG_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register.                                        */
15078 
15079 /* EN @Bit 0 : Enable channel group n */
15080   #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL)            /*!< Position of EN field.                                                */
15081   #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field.                            */
15082   #define DPPIC_TASKS_CHG_EN_EN_Min (0x1UL)          /*!< Min enumerator value of EN field.                                    */
15083   #define DPPIC_TASKS_CHG_EN_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
15084   #define DPPIC_TASKS_CHG_EN_EN_Trigger (0x1UL)      /*!< Trigger task                                                         */
15085 
15086 
15087 /* DPPIC_TASKS_CHG_DIS: Disable channel group n */
15088   #define DPPIC_TASKS_CHG_DIS_ResetValue (0x00000000UL) /*!< Reset value of DIS register.                                      */
15089 
15090 /* DIS @Bit 0 : Disable channel group n */
15091   #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL)          /*!< Position of DIS field.                                               */
15092   #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field.                       */
15093   #define DPPIC_TASKS_CHG_DIS_DIS_Min (0x1UL)        /*!< Min enumerator value of DIS field.                                   */
15094   #define DPPIC_TASKS_CHG_DIS_DIS_Max (0x1UL)        /*!< Max enumerator value of DIS field.                                   */
15095   #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (0x1UL)    /*!< Trigger task                                                         */
15096 
15097 
15098 
15099 /* =============================================== Struct DPPIC_SUBSCRIBE_CHG ================================================ */
15100 /**
15101   * @brief SUBSCRIBE_CHG [DPPIC_SUBSCRIBE_CHG] Subscribe configuration for tasks
15102   */
15103 typedef struct {
15104   __IOM uint32_t  EN;                                /*!< (@ 0x00000000) Subscribe configuration for task CHG[n].EN            */
15105   __IOM uint32_t  DIS;                               /*!< (@ 0x00000004) Subscribe configuration for task CHG[n].DIS           */
15106 } NRF_DPPIC_SUBSCRIBE_CHG_Type;                      /*!< Size = 8 (0x008)                                                     */
15107   #define DPPIC_SUBSCRIBE_CHG_MaxCount (2UL)         /*!< Size of SUBSCRIBE_CHG[2] array.                                      */
15108   #define DPPIC_SUBSCRIBE_CHG_MaxIndex (1UL)         /*!< Max index of SUBSCRIBE_CHG[2] array.                                 */
15109   #define DPPIC_SUBSCRIBE_CHG_MinIndex (0UL)         /*!< Min index of SUBSCRIBE_CHG[2] array.                                 */
15110 
15111 /* DPPIC_SUBSCRIBE_CHG_EN: Subscribe configuration for task CHG[n].EN */
15112   #define DPPIC_SUBSCRIBE_CHG_EN_ResetValue (0x00000000UL) /*!< Reset value of EN register.                                    */
15113 
15114 /* CHIDX @Bits 0..7 : DPPI channel that task CHG[n].EN will subscribe to */
15115   #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
15116   #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
15117   #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
15118   #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
15119 
15120 /* EN @Bit 31 : (unspecified) */
15121   #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL)       /*!< Position of EN field.                                                */
15122   #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field.                    */
15123   #define DPPIC_SUBSCRIBE_CHG_EN_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
15124   #define DPPIC_SUBSCRIBE_CHG_EN_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
15125   #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
15126   #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
15127 
15128 
15129 /* DPPIC_SUBSCRIBE_CHG_DIS: Subscribe configuration for task CHG[n].DIS */
15130   #define DPPIC_SUBSCRIBE_CHG_DIS_ResetValue (0x00000000UL) /*!< Reset value of DIS register.                                  */
15131 
15132 /* CHIDX @Bits 0..7 : DPPI channel that task CHG[n].DIS will subscribe to */
15133   #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
15134   #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
15135   #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
15136   #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
15137 
15138 /* EN @Bit 31 : (unspecified) */
15139   #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL)      /*!< Position of EN field.                                                */
15140   #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field.                  */
15141   #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
15142   #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
15143   #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
15144   #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
15145 
15146 
15147 /* ====================================================== Struct DPPIC ======================================================= */
15148 /**
15149   * @brief Distributed programmable peripheral interconnect controller
15150   */
15151   typedef struct {                                   /*!< DPPIC Structure                                                      */
15152     __OM NRF_DPPIC_TASKS_CHG_Type TASKS_CHG[2];      /*!< (@ 0x00000000) Channel group tasks                                   */
15153     __IM uint32_t RESERVED[28];
15154     __IOM NRF_DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[2]; /*!< (@ 0x00000080) Subscribe configuration for tasks                 */
15155     __IM uint32_t RESERVED1[284];
15156     __IOM uint32_t CHEN;                             /*!< (@ 0x00000500) Channel enable register                               */
15157     __IOM uint32_t CHENSET;                          /*!< (@ 0x00000504) Channel enable set register                           */
15158     __IOM uint32_t CHENCLR;                          /*!< (@ 0x00000508) Channel enable clear register                         */
15159     __IM uint32_t RESERVED2[189];
15160     __IOM uint32_t CHG[2];                           /*!< (@ 0x00000800) Channel group n Note: Writes to this register are
15161                                                                          ignored if either SUBSCRIBE_CHG[n].EN or
15162                                                                          SUBSCRIBE_CHG[n].DIS is enabled*/
15163   } NRF_DPPIC_Type;                                  /*!< Size = 2056 (0x808)                                                  */
15164 
15165 /* DPPIC_CHEN: Channel enable register */
15166   #define DPPIC_CHEN_ResetValue (0x00000000UL)       /*!< Reset value of CHEN register.                                        */
15167 
15168 /* CH0 @Bit 0 : Enable or disable channel 0 */
15169   #define DPPIC_CHEN_CH0_Pos (0UL)                   /*!< Position of CH0 field.                                               */
15170   #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field.                                         */
15171   #define DPPIC_CHEN_CH0_Min (0x0UL)                 /*!< Min enumerator value of CH0 field.                                   */
15172   #define DPPIC_CHEN_CH0_Max (0x1UL)                 /*!< Max enumerator value of CH0 field.                                   */
15173   #define DPPIC_CHEN_CH0_Disabled (0x0UL)            /*!< Disable channel                                                      */
15174   #define DPPIC_CHEN_CH0_Enabled (0x1UL)             /*!< Enable channel                                                       */
15175 
15176 /* CH1 @Bit 1 : Enable or disable channel 1 */
15177   #define DPPIC_CHEN_CH1_Pos (1UL)                   /*!< Position of CH1 field.                                               */
15178   #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field.                                         */
15179   #define DPPIC_CHEN_CH1_Min (0x0UL)                 /*!< Min enumerator value of CH1 field.                                   */
15180   #define DPPIC_CHEN_CH1_Max (0x1UL)                 /*!< Max enumerator value of CH1 field.                                   */
15181   #define DPPIC_CHEN_CH1_Disabled (0x0UL)            /*!< Disable channel                                                      */
15182   #define DPPIC_CHEN_CH1_Enabled (0x1UL)             /*!< Enable channel                                                       */
15183 
15184 /* CH2 @Bit 2 : Enable or disable channel 2 */
15185   #define DPPIC_CHEN_CH2_Pos (2UL)                   /*!< Position of CH2 field.                                               */
15186   #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field.                                         */
15187   #define DPPIC_CHEN_CH2_Min (0x0UL)                 /*!< Min enumerator value of CH2 field.                                   */
15188   #define DPPIC_CHEN_CH2_Max (0x1UL)                 /*!< Max enumerator value of CH2 field.                                   */
15189   #define DPPIC_CHEN_CH2_Disabled (0x0UL)            /*!< Disable channel                                                      */
15190   #define DPPIC_CHEN_CH2_Enabled (0x1UL)             /*!< Enable channel                                                       */
15191 
15192 /* CH3 @Bit 3 : Enable or disable channel 3 */
15193   #define DPPIC_CHEN_CH3_Pos (3UL)                   /*!< Position of CH3 field.                                               */
15194   #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field.                                         */
15195   #define DPPIC_CHEN_CH3_Min (0x0UL)                 /*!< Min enumerator value of CH3 field.                                   */
15196   #define DPPIC_CHEN_CH3_Max (0x1UL)                 /*!< Max enumerator value of CH3 field.                                   */
15197   #define DPPIC_CHEN_CH3_Disabled (0x0UL)            /*!< Disable channel                                                      */
15198   #define DPPIC_CHEN_CH3_Enabled (0x1UL)             /*!< Enable channel                                                       */
15199 
15200 /* CH4 @Bit 4 : Enable or disable channel 4 */
15201   #define DPPIC_CHEN_CH4_Pos (4UL)                   /*!< Position of CH4 field.                                               */
15202   #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field.                                         */
15203   #define DPPIC_CHEN_CH4_Min (0x0UL)                 /*!< Min enumerator value of CH4 field.                                   */
15204   #define DPPIC_CHEN_CH4_Max (0x1UL)                 /*!< Max enumerator value of CH4 field.                                   */
15205   #define DPPIC_CHEN_CH4_Disabled (0x0UL)            /*!< Disable channel                                                      */
15206   #define DPPIC_CHEN_CH4_Enabled (0x1UL)             /*!< Enable channel                                                       */
15207 
15208 /* CH5 @Bit 5 : Enable or disable channel 5 */
15209   #define DPPIC_CHEN_CH5_Pos (5UL)                   /*!< Position of CH5 field.                                               */
15210   #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field.                                         */
15211   #define DPPIC_CHEN_CH5_Min (0x0UL)                 /*!< Min enumerator value of CH5 field.                                   */
15212   #define DPPIC_CHEN_CH5_Max (0x1UL)                 /*!< Max enumerator value of CH5 field.                                   */
15213   #define DPPIC_CHEN_CH5_Disabled (0x0UL)            /*!< Disable channel                                                      */
15214   #define DPPIC_CHEN_CH5_Enabled (0x1UL)             /*!< Enable channel                                                       */
15215 
15216 /* CH6 @Bit 6 : Enable or disable channel 6 */
15217   #define DPPIC_CHEN_CH6_Pos (6UL)                   /*!< Position of CH6 field.                                               */
15218   #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field.                                         */
15219   #define DPPIC_CHEN_CH6_Min (0x0UL)                 /*!< Min enumerator value of CH6 field.                                   */
15220   #define DPPIC_CHEN_CH6_Max (0x1UL)                 /*!< Max enumerator value of CH6 field.                                   */
15221   #define DPPIC_CHEN_CH6_Disabled (0x0UL)            /*!< Disable channel                                                      */
15222   #define DPPIC_CHEN_CH6_Enabled (0x1UL)             /*!< Enable channel                                                       */
15223 
15224 /* CH7 @Bit 7 : Enable or disable channel 7 */
15225   #define DPPIC_CHEN_CH7_Pos (7UL)                   /*!< Position of CH7 field.                                               */
15226   #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field.                                         */
15227   #define DPPIC_CHEN_CH7_Min (0x0UL)                 /*!< Min enumerator value of CH7 field.                                   */
15228   #define DPPIC_CHEN_CH7_Max (0x1UL)                 /*!< Max enumerator value of CH7 field.                                   */
15229   #define DPPIC_CHEN_CH7_Disabled (0x0UL)            /*!< Disable channel                                                      */
15230   #define DPPIC_CHEN_CH7_Enabled (0x1UL)             /*!< Enable channel                                                       */
15231 
15232 /* CH8 @Bit 8 : Enable or disable channel 8 */
15233   #define DPPIC_CHEN_CH8_Pos (8UL)                   /*!< Position of CH8 field.                                               */
15234   #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field.                                         */
15235   #define DPPIC_CHEN_CH8_Min (0x0UL)                 /*!< Min enumerator value of CH8 field.                                   */
15236   #define DPPIC_CHEN_CH8_Max (0x1UL)                 /*!< Max enumerator value of CH8 field.                                   */
15237   #define DPPIC_CHEN_CH8_Disabled (0x0UL)            /*!< Disable channel                                                      */
15238   #define DPPIC_CHEN_CH8_Enabled (0x1UL)             /*!< Enable channel                                                       */
15239 
15240 /* CH9 @Bit 9 : Enable or disable channel 9 */
15241   #define DPPIC_CHEN_CH9_Pos (9UL)                   /*!< Position of CH9 field.                                               */
15242   #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field.                                         */
15243   #define DPPIC_CHEN_CH9_Min (0x0UL)                 /*!< Min enumerator value of CH9 field.                                   */
15244   #define DPPIC_CHEN_CH9_Max (0x1UL)                 /*!< Max enumerator value of CH9 field.                                   */
15245   #define DPPIC_CHEN_CH9_Disabled (0x0UL)            /*!< Disable channel                                                      */
15246   #define DPPIC_CHEN_CH9_Enabled (0x1UL)             /*!< Enable channel                                                       */
15247 
15248 /* CH10 @Bit 10 : Enable or disable channel 10 */
15249   #define DPPIC_CHEN_CH10_Pos (10UL)                 /*!< Position of CH10 field.                                              */
15250   #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field.                                      */
15251   #define DPPIC_CHEN_CH10_Min (0x0UL)                /*!< Min enumerator value of CH10 field.                                  */
15252   #define DPPIC_CHEN_CH10_Max (0x1UL)                /*!< Max enumerator value of CH10 field.                                  */
15253   #define DPPIC_CHEN_CH10_Disabled (0x0UL)           /*!< Disable channel                                                      */
15254   #define DPPIC_CHEN_CH10_Enabled (0x1UL)            /*!< Enable channel                                                       */
15255 
15256 /* CH11 @Bit 11 : Enable or disable channel 11 */
15257   #define DPPIC_CHEN_CH11_Pos (11UL)                 /*!< Position of CH11 field.                                              */
15258   #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field.                                      */
15259   #define DPPIC_CHEN_CH11_Min (0x0UL)                /*!< Min enumerator value of CH11 field.                                  */
15260   #define DPPIC_CHEN_CH11_Max (0x1UL)                /*!< Max enumerator value of CH11 field.                                  */
15261   #define DPPIC_CHEN_CH11_Disabled (0x0UL)           /*!< Disable channel                                                      */
15262   #define DPPIC_CHEN_CH11_Enabled (0x1UL)            /*!< Enable channel                                                       */
15263 
15264 /* CH12 @Bit 12 : Enable or disable channel 12 */
15265   #define DPPIC_CHEN_CH12_Pos (12UL)                 /*!< Position of CH12 field.                                              */
15266   #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field.                                      */
15267   #define DPPIC_CHEN_CH12_Min (0x0UL)                /*!< Min enumerator value of CH12 field.                                  */
15268   #define DPPIC_CHEN_CH12_Max (0x1UL)                /*!< Max enumerator value of CH12 field.                                  */
15269   #define DPPIC_CHEN_CH12_Disabled (0x0UL)           /*!< Disable channel                                                      */
15270   #define DPPIC_CHEN_CH12_Enabled (0x1UL)            /*!< Enable channel                                                       */
15271 
15272 /* CH13 @Bit 13 : Enable or disable channel 13 */
15273   #define DPPIC_CHEN_CH13_Pos (13UL)                 /*!< Position of CH13 field.                                              */
15274   #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field.                                      */
15275   #define DPPIC_CHEN_CH13_Min (0x0UL)                /*!< Min enumerator value of CH13 field.                                  */
15276   #define DPPIC_CHEN_CH13_Max (0x1UL)                /*!< Max enumerator value of CH13 field.                                  */
15277   #define DPPIC_CHEN_CH13_Disabled (0x0UL)           /*!< Disable channel                                                      */
15278   #define DPPIC_CHEN_CH13_Enabled (0x1UL)            /*!< Enable channel                                                       */
15279 
15280 /* CH14 @Bit 14 : Enable or disable channel 14 */
15281   #define DPPIC_CHEN_CH14_Pos (14UL)                 /*!< Position of CH14 field.                                              */
15282   #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field.                                      */
15283   #define DPPIC_CHEN_CH14_Min (0x0UL)                /*!< Min enumerator value of CH14 field.                                  */
15284   #define DPPIC_CHEN_CH14_Max (0x1UL)                /*!< Max enumerator value of CH14 field.                                  */
15285   #define DPPIC_CHEN_CH14_Disabled (0x0UL)           /*!< Disable channel                                                      */
15286   #define DPPIC_CHEN_CH14_Enabled (0x1UL)            /*!< Enable channel                                                       */
15287 
15288 /* CH15 @Bit 15 : Enable or disable channel 15 */
15289   #define DPPIC_CHEN_CH15_Pos (15UL)                 /*!< Position of CH15 field.                                              */
15290   #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field.                                      */
15291   #define DPPIC_CHEN_CH15_Min (0x0UL)                /*!< Min enumerator value of CH15 field.                                  */
15292   #define DPPIC_CHEN_CH15_Max (0x1UL)                /*!< Max enumerator value of CH15 field.                                  */
15293   #define DPPIC_CHEN_CH15_Disabled (0x0UL)           /*!< Disable channel                                                      */
15294   #define DPPIC_CHEN_CH15_Enabled (0x1UL)            /*!< Enable channel                                                       */
15295 
15296 
15297 /* DPPIC_CHENSET: Channel enable set register */
15298   #define DPPIC_CHENSET_ResetValue (0x00000000UL)    /*!< Reset value of CHENSET register.                                     */
15299 
15300 /* CH0 @Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
15301   #define DPPIC_CHENSET_CH0_Pos (0UL)                /*!< Position of CH0 field.                                               */
15302   #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field.                                   */
15303   #define DPPIC_CHENSET_CH0_Min (0x0UL)              /*!< Min enumerator value of CH0 field.                                   */
15304   #define DPPIC_CHENSET_CH0_Max (0x1UL)              /*!< Max enumerator value of CH0 field.                                   */
15305   #define DPPIC_CHENSET_CH0_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15306   #define DPPIC_CHENSET_CH0_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15307   #define DPPIC_CHENSET_CH0_Set (0x1UL)              /*!< Write: Enable channel                                                */
15308 
15309 /* CH1 @Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */
15310   #define DPPIC_CHENSET_CH1_Pos (1UL)                /*!< Position of CH1 field.                                               */
15311   #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field.                                   */
15312   #define DPPIC_CHENSET_CH1_Min (0x0UL)              /*!< Min enumerator value of CH1 field.                                   */
15313   #define DPPIC_CHENSET_CH1_Max (0x1UL)              /*!< Max enumerator value of CH1 field.                                   */
15314   #define DPPIC_CHENSET_CH1_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15315   #define DPPIC_CHENSET_CH1_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15316   #define DPPIC_CHENSET_CH1_Set (0x1UL)              /*!< Write: Enable channel                                                */
15317 
15318 /* CH2 @Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */
15319   #define DPPIC_CHENSET_CH2_Pos (2UL)                /*!< Position of CH2 field.                                               */
15320   #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field.                                   */
15321   #define DPPIC_CHENSET_CH2_Min (0x0UL)              /*!< Min enumerator value of CH2 field.                                   */
15322   #define DPPIC_CHENSET_CH2_Max (0x1UL)              /*!< Max enumerator value of CH2 field.                                   */
15323   #define DPPIC_CHENSET_CH2_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15324   #define DPPIC_CHENSET_CH2_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15325   #define DPPIC_CHENSET_CH2_Set (0x1UL)              /*!< Write: Enable channel                                                */
15326 
15327 /* CH3 @Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */
15328   #define DPPIC_CHENSET_CH3_Pos (3UL)                /*!< Position of CH3 field.                                               */
15329   #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field.                                   */
15330   #define DPPIC_CHENSET_CH3_Min (0x0UL)              /*!< Min enumerator value of CH3 field.                                   */
15331   #define DPPIC_CHENSET_CH3_Max (0x1UL)              /*!< Max enumerator value of CH3 field.                                   */
15332   #define DPPIC_CHENSET_CH3_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15333   #define DPPIC_CHENSET_CH3_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15334   #define DPPIC_CHENSET_CH3_Set (0x1UL)              /*!< Write: Enable channel                                                */
15335 
15336 /* CH4 @Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */
15337   #define DPPIC_CHENSET_CH4_Pos (4UL)                /*!< Position of CH4 field.                                               */
15338   #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field.                                   */
15339   #define DPPIC_CHENSET_CH4_Min (0x0UL)              /*!< Min enumerator value of CH4 field.                                   */
15340   #define DPPIC_CHENSET_CH4_Max (0x1UL)              /*!< Max enumerator value of CH4 field.                                   */
15341   #define DPPIC_CHENSET_CH4_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15342   #define DPPIC_CHENSET_CH4_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15343   #define DPPIC_CHENSET_CH4_Set (0x1UL)              /*!< Write: Enable channel                                                */
15344 
15345 /* CH5 @Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */
15346   #define DPPIC_CHENSET_CH5_Pos (5UL)                /*!< Position of CH5 field.                                               */
15347   #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field.                                   */
15348   #define DPPIC_CHENSET_CH5_Min (0x0UL)              /*!< Min enumerator value of CH5 field.                                   */
15349   #define DPPIC_CHENSET_CH5_Max (0x1UL)              /*!< Max enumerator value of CH5 field.                                   */
15350   #define DPPIC_CHENSET_CH5_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15351   #define DPPIC_CHENSET_CH5_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15352   #define DPPIC_CHENSET_CH5_Set (0x1UL)              /*!< Write: Enable channel                                                */
15353 
15354 /* CH6 @Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */
15355   #define DPPIC_CHENSET_CH6_Pos (6UL)                /*!< Position of CH6 field.                                               */
15356   #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field.                                   */
15357   #define DPPIC_CHENSET_CH6_Min (0x0UL)              /*!< Min enumerator value of CH6 field.                                   */
15358   #define DPPIC_CHENSET_CH6_Max (0x1UL)              /*!< Max enumerator value of CH6 field.                                   */
15359   #define DPPIC_CHENSET_CH6_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15360   #define DPPIC_CHENSET_CH6_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15361   #define DPPIC_CHENSET_CH6_Set (0x1UL)              /*!< Write: Enable channel                                                */
15362 
15363 /* CH7 @Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */
15364   #define DPPIC_CHENSET_CH7_Pos (7UL)                /*!< Position of CH7 field.                                               */
15365   #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field.                                   */
15366   #define DPPIC_CHENSET_CH7_Min (0x0UL)              /*!< Min enumerator value of CH7 field.                                   */
15367   #define DPPIC_CHENSET_CH7_Max (0x1UL)              /*!< Max enumerator value of CH7 field.                                   */
15368   #define DPPIC_CHENSET_CH7_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15369   #define DPPIC_CHENSET_CH7_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15370   #define DPPIC_CHENSET_CH7_Set (0x1UL)              /*!< Write: Enable channel                                                */
15371 
15372 /* CH8 @Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */
15373   #define DPPIC_CHENSET_CH8_Pos (8UL)                /*!< Position of CH8 field.                                               */
15374   #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field.                                   */
15375   #define DPPIC_CHENSET_CH8_Min (0x0UL)              /*!< Min enumerator value of CH8 field.                                   */
15376   #define DPPIC_CHENSET_CH8_Max (0x1UL)              /*!< Max enumerator value of CH8 field.                                   */
15377   #define DPPIC_CHENSET_CH8_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15378   #define DPPIC_CHENSET_CH8_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15379   #define DPPIC_CHENSET_CH8_Set (0x1UL)              /*!< Write: Enable channel                                                */
15380 
15381 /* CH9 @Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */
15382   #define DPPIC_CHENSET_CH9_Pos (9UL)                /*!< Position of CH9 field.                                               */
15383   #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field.                                   */
15384   #define DPPIC_CHENSET_CH9_Min (0x0UL)              /*!< Min enumerator value of CH9 field.                                   */
15385   #define DPPIC_CHENSET_CH9_Max (0x1UL)              /*!< Max enumerator value of CH9 field.                                   */
15386   #define DPPIC_CHENSET_CH9_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15387   #define DPPIC_CHENSET_CH9_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15388   #define DPPIC_CHENSET_CH9_Set (0x1UL)              /*!< Write: Enable channel                                                */
15389 
15390 /* CH10 @Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */
15391   #define DPPIC_CHENSET_CH10_Pos (10UL)              /*!< Position of CH10 field.                                              */
15392   #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field.                                */
15393   #define DPPIC_CHENSET_CH10_Min (0x0UL)             /*!< Min enumerator value of CH10 field.                                  */
15394   #define DPPIC_CHENSET_CH10_Max (0x1UL)             /*!< Max enumerator value of CH10 field.                                  */
15395   #define DPPIC_CHENSET_CH10_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15396   #define DPPIC_CHENSET_CH10_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15397   #define DPPIC_CHENSET_CH10_Set (0x1UL)             /*!< Write: Enable channel                                                */
15398 
15399 /* CH11 @Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */
15400   #define DPPIC_CHENSET_CH11_Pos (11UL)              /*!< Position of CH11 field.                                              */
15401   #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field.                                */
15402   #define DPPIC_CHENSET_CH11_Min (0x0UL)             /*!< Min enumerator value of CH11 field.                                  */
15403   #define DPPIC_CHENSET_CH11_Max (0x1UL)             /*!< Max enumerator value of CH11 field.                                  */
15404   #define DPPIC_CHENSET_CH11_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15405   #define DPPIC_CHENSET_CH11_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15406   #define DPPIC_CHENSET_CH11_Set (0x1UL)             /*!< Write: Enable channel                                                */
15407 
15408 /* CH12 @Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */
15409   #define DPPIC_CHENSET_CH12_Pos (12UL)              /*!< Position of CH12 field.                                              */
15410   #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field.                                */
15411   #define DPPIC_CHENSET_CH12_Min (0x0UL)             /*!< Min enumerator value of CH12 field.                                  */
15412   #define DPPIC_CHENSET_CH12_Max (0x1UL)             /*!< Max enumerator value of CH12 field.                                  */
15413   #define DPPIC_CHENSET_CH12_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15414   #define DPPIC_CHENSET_CH12_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15415   #define DPPIC_CHENSET_CH12_Set (0x1UL)             /*!< Write: Enable channel                                                */
15416 
15417 /* CH13 @Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */
15418   #define DPPIC_CHENSET_CH13_Pos (13UL)              /*!< Position of CH13 field.                                              */
15419   #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field.                                */
15420   #define DPPIC_CHENSET_CH13_Min (0x0UL)             /*!< Min enumerator value of CH13 field.                                  */
15421   #define DPPIC_CHENSET_CH13_Max (0x1UL)             /*!< Max enumerator value of CH13 field.                                  */
15422   #define DPPIC_CHENSET_CH13_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15423   #define DPPIC_CHENSET_CH13_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15424   #define DPPIC_CHENSET_CH13_Set (0x1UL)             /*!< Write: Enable channel                                                */
15425 
15426 /* CH14 @Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */
15427   #define DPPIC_CHENSET_CH14_Pos (14UL)              /*!< Position of CH14 field.                                              */
15428   #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field.                                */
15429   #define DPPIC_CHENSET_CH14_Min (0x0UL)             /*!< Min enumerator value of CH14 field.                                  */
15430   #define DPPIC_CHENSET_CH14_Max (0x1UL)             /*!< Max enumerator value of CH14 field.                                  */
15431   #define DPPIC_CHENSET_CH14_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15432   #define DPPIC_CHENSET_CH14_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15433   #define DPPIC_CHENSET_CH14_Set (0x1UL)             /*!< Write: Enable channel                                                */
15434 
15435 /* CH15 @Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */
15436   #define DPPIC_CHENSET_CH15_Pos (15UL)              /*!< Position of CH15 field.                                              */
15437   #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field.                                */
15438   #define DPPIC_CHENSET_CH15_Min (0x0UL)             /*!< Min enumerator value of CH15 field.                                  */
15439   #define DPPIC_CHENSET_CH15_Max (0x1UL)             /*!< Max enumerator value of CH15 field.                                  */
15440   #define DPPIC_CHENSET_CH15_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15441   #define DPPIC_CHENSET_CH15_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15442   #define DPPIC_CHENSET_CH15_Set (0x1UL)             /*!< Write: Enable channel                                                */
15443 
15444 
15445 /* DPPIC_CHENCLR: Channel enable clear register */
15446   #define DPPIC_CHENCLR_ResetValue (0x00000000UL)    /*!< Reset value of CHENCLR register.                                     */
15447 
15448 /* CH0 @Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */
15449   #define DPPIC_CHENCLR_CH0_Pos (0UL)                /*!< Position of CH0 field.                                               */
15450   #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field.                                   */
15451   #define DPPIC_CHENCLR_CH0_Min (0x0UL)              /*!< Min enumerator value of CH0 field.                                   */
15452   #define DPPIC_CHENCLR_CH0_Max (0x1UL)              /*!< Max enumerator value of CH0 field.                                   */
15453   #define DPPIC_CHENCLR_CH0_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15454   #define DPPIC_CHENCLR_CH0_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15455   #define DPPIC_CHENCLR_CH0_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15456 
15457 /* CH1 @Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */
15458   #define DPPIC_CHENCLR_CH1_Pos (1UL)                /*!< Position of CH1 field.                                               */
15459   #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field.                                   */
15460   #define DPPIC_CHENCLR_CH1_Min (0x0UL)              /*!< Min enumerator value of CH1 field.                                   */
15461   #define DPPIC_CHENCLR_CH1_Max (0x1UL)              /*!< Max enumerator value of CH1 field.                                   */
15462   #define DPPIC_CHENCLR_CH1_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15463   #define DPPIC_CHENCLR_CH1_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15464   #define DPPIC_CHENCLR_CH1_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15465 
15466 /* CH2 @Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */
15467   #define DPPIC_CHENCLR_CH2_Pos (2UL)                /*!< Position of CH2 field.                                               */
15468   #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field.                                   */
15469   #define DPPIC_CHENCLR_CH2_Min (0x0UL)              /*!< Min enumerator value of CH2 field.                                   */
15470   #define DPPIC_CHENCLR_CH2_Max (0x1UL)              /*!< Max enumerator value of CH2 field.                                   */
15471   #define DPPIC_CHENCLR_CH2_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15472   #define DPPIC_CHENCLR_CH2_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15473   #define DPPIC_CHENCLR_CH2_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15474 
15475 /* CH3 @Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */
15476   #define DPPIC_CHENCLR_CH3_Pos (3UL)                /*!< Position of CH3 field.                                               */
15477   #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field.                                   */
15478   #define DPPIC_CHENCLR_CH3_Min (0x0UL)              /*!< Min enumerator value of CH3 field.                                   */
15479   #define DPPIC_CHENCLR_CH3_Max (0x1UL)              /*!< Max enumerator value of CH3 field.                                   */
15480   #define DPPIC_CHENCLR_CH3_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15481   #define DPPIC_CHENCLR_CH3_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15482   #define DPPIC_CHENCLR_CH3_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15483 
15484 /* CH4 @Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */
15485   #define DPPIC_CHENCLR_CH4_Pos (4UL)                /*!< Position of CH4 field.                                               */
15486   #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field.                                   */
15487   #define DPPIC_CHENCLR_CH4_Min (0x0UL)              /*!< Min enumerator value of CH4 field.                                   */
15488   #define DPPIC_CHENCLR_CH4_Max (0x1UL)              /*!< Max enumerator value of CH4 field.                                   */
15489   #define DPPIC_CHENCLR_CH4_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15490   #define DPPIC_CHENCLR_CH4_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15491   #define DPPIC_CHENCLR_CH4_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15492 
15493 /* CH5 @Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */
15494   #define DPPIC_CHENCLR_CH5_Pos (5UL)                /*!< Position of CH5 field.                                               */
15495   #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field.                                   */
15496   #define DPPIC_CHENCLR_CH5_Min (0x0UL)              /*!< Min enumerator value of CH5 field.                                   */
15497   #define DPPIC_CHENCLR_CH5_Max (0x1UL)              /*!< Max enumerator value of CH5 field.                                   */
15498   #define DPPIC_CHENCLR_CH5_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15499   #define DPPIC_CHENCLR_CH5_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15500   #define DPPIC_CHENCLR_CH5_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15501 
15502 /* CH6 @Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */
15503   #define DPPIC_CHENCLR_CH6_Pos (6UL)                /*!< Position of CH6 field.                                               */
15504   #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field.                                   */
15505   #define DPPIC_CHENCLR_CH6_Min (0x0UL)              /*!< Min enumerator value of CH6 field.                                   */
15506   #define DPPIC_CHENCLR_CH6_Max (0x1UL)              /*!< Max enumerator value of CH6 field.                                   */
15507   #define DPPIC_CHENCLR_CH6_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15508   #define DPPIC_CHENCLR_CH6_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15509   #define DPPIC_CHENCLR_CH6_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15510 
15511 /* CH7 @Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */
15512   #define DPPIC_CHENCLR_CH7_Pos (7UL)                /*!< Position of CH7 field.                                               */
15513   #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field.                                   */
15514   #define DPPIC_CHENCLR_CH7_Min (0x0UL)              /*!< Min enumerator value of CH7 field.                                   */
15515   #define DPPIC_CHENCLR_CH7_Max (0x1UL)              /*!< Max enumerator value of CH7 field.                                   */
15516   #define DPPIC_CHENCLR_CH7_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15517   #define DPPIC_CHENCLR_CH7_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15518   #define DPPIC_CHENCLR_CH7_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15519 
15520 /* CH8 @Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */
15521   #define DPPIC_CHENCLR_CH8_Pos (8UL)                /*!< Position of CH8 field.                                               */
15522   #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field.                                   */
15523   #define DPPIC_CHENCLR_CH8_Min (0x0UL)              /*!< Min enumerator value of CH8 field.                                   */
15524   #define DPPIC_CHENCLR_CH8_Max (0x1UL)              /*!< Max enumerator value of CH8 field.                                   */
15525   #define DPPIC_CHENCLR_CH8_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15526   #define DPPIC_CHENCLR_CH8_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15527   #define DPPIC_CHENCLR_CH8_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15528 
15529 /* CH9 @Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */
15530   #define DPPIC_CHENCLR_CH9_Pos (9UL)                /*!< Position of CH9 field.                                               */
15531   #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field.                                   */
15532   #define DPPIC_CHENCLR_CH9_Min (0x0UL)              /*!< Min enumerator value of CH9 field.                                   */
15533   #define DPPIC_CHENCLR_CH9_Max (0x1UL)              /*!< Max enumerator value of CH9 field.                                   */
15534   #define DPPIC_CHENCLR_CH9_Disabled (0x0UL)         /*!< Read: Channel disabled                                               */
15535   #define DPPIC_CHENCLR_CH9_Enabled (0x1UL)          /*!< Read: Channel enabled                                                */
15536   #define DPPIC_CHENCLR_CH9_Clear (0x1UL)            /*!< Write: Disable channel                                               */
15537 
15538 /* CH10 @Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */
15539   #define DPPIC_CHENCLR_CH10_Pos (10UL)              /*!< Position of CH10 field.                                              */
15540   #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field.                                */
15541   #define DPPIC_CHENCLR_CH10_Min (0x0UL)             /*!< Min enumerator value of CH10 field.                                  */
15542   #define DPPIC_CHENCLR_CH10_Max (0x1UL)             /*!< Max enumerator value of CH10 field.                                  */
15543   #define DPPIC_CHENCLR_CH10_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15544   #define DPPIC_CHENCLR_CH10_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15545   #define DPPIC_CHENCLR_CH10_Clear (0x1UL)           /*!< Write: Disable channel                                               */
15546 
15547 /* CH11 @Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */
15548   #define DPPIC_CHENCLR_CH11_Pos (11UL)              /*!< Position of CH11 field.                                              */
15549   #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field.                                */
15550   #define DPPIC_CHENCLR_CH11_Min (0x0UL)             /*!< Min enumerator value of CH11 field.                                  */
15551   #define DPPIC_CHENCLR_CH11_Max (0x1UL)             /*!< Max enumerator value of CH11 field.                                  */
15552   #define DPPIC_CHENCLR_CH11_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15553   #define DPPIC_CHENCLR_CH11_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15554   #define DPPIC_CHENCLR_CH11_Clear (0x1UL)           /*!< Write: Disable channel                                               */
15555 
15556 /* CH12 @Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */
15557   #define DPPIC_CHENCLR_CH12_Pos (12UL)              /*!< Position of CH12 field.                                              */
15558   #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field.                                */
15559   #define DPPIC_CHENCLR_CH12_Min (0x0UL)             /*!< Min enumerator value of CH12 field.                                  */
15560   #define DPPIC_CHENCLR_CH12_Max (0x1UL)             /*!< Max enumerator value of CH12 field.                                  */
15561   #define DPPIC_CHENCLR_CH12_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15562   #define DPPIC_CHENCLR_CH12_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15563   #define DPPIC_CHENCLR_CH12_Clear (0x1UL)           /*!< Write: Disable channel                                               */
15564 
15565 /* CH13 @Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */
15566   #define DPPIC_CHENCLR_CH13_Pos (13UL)              /*!< Position of CH13 field.                                              */
15567   #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field.                                */
15568   #define DPPIC_CHENCLR_CH13_Min (0x0UL)             /*!< Min enumerator value of CH13 field.                                  */
15569   #define DPPIC_CHENCLR_CH13_Max (0x1UL)             /*!< Max enumerator value of CH13 field.                                  */
15570   #define DPPIC_CHENCLR_CH13_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15571   #define DPPIC_CHENCLR_CH13_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15572   #define DPPIC_CHENCLR_CH13_Clear (0x1UL)           /*!< Write: Disable channel                                               */
15573 
15574 /* CH14 @Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */
15575   #define DPPIC_CHENCLR_CH14_Pos (14UL)              /*!< Position of CH14 field.                                              */
15576   #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field.                                */
15577   #define DPPIC_CHENCLR_CH14_Min (0x0UL)             /*!< Min enumerator value of CH14 field.                                  */
15578   #define DPPIC_CHENCLR_CH14_Max (0x1UL)             /*!< Max enumerator value of CH14 field.                                  */
15579   #define DPPIC_CHENCLR_CH14_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15580   #define DPPIC_CHENCLR_CH14_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15581   #define DPPIC_CHENCLR_CH14_Clear (0x1UL)           /*!< Write: Disable channel                                               */
15582 
15583 /* CH15 @Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */
15584   #define DPPIC_CHENCLR_CH15_Pos (15UL)              /*!< Position of CH15 field.                                              */
15585   #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field.                                */
15586   #define DPPIC_CHENCLR_CH15_Min (0x0UL)             /*!< Min enumerator value of CH15 field.                                  */
15587   #define DPPIC_CHENCLR_CH15_Max (0x1UL)             /*!< Max enumerator value of CH15 field.                                  */
15588   #define DPPIC_CHENCLR_CH15_Disabled (0x0UL)        /*!< Read: Channel disabled                                               */
15589   #define DPPIC_CHENCLR_CH15_Enabled (0x1UL)         /*!< Read: Channel enabled                                                */
15590   #define DPPIC_CHENCLR_CH15_Clear (0x1UL)           /*!< Write: Disable channel                                               */
15591 
15592 
15593 /* DPPIC_CHG: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is
15594                enabled */
15595 
15596   #define DPPIC_CHG_MaxCount (2UL)                   /*!< Max size of CHG[2] array.                                            */
15597   #define DPPIC_CHG_MaxIndex (1UL)                   /*!< Max index of CHG[2] array.                                           */
15598   #define DPPIC_CHG_MinIndex (0UL)                   /*!< Min index of CHG[2] array.                                           */
15599   #define DPPIC_CHG_ResetValue (0x00000000UL)        /*!< Reset value of CHG[2] register.                                      */
15600 
15601 /* CH0 @Bit 0 : Include or exclude channel 0 */
15602   #define DPPIC_CHG_CH0_Pos (0UL)                    /*!< Position of CH0 field.                                               */
15603   #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field.                                           */
15604   #define DPPIC_CHG_CH0_Min (0x0UL)                  /*!< Min enumerator value of CH0 field.                                   */
15605   #define DPPIC_CHG_CH0_Max (0x1UL)                  /*!< Max enumerator value of CH0 field.                                   */
15606   #define DPPIC_CHG_CH0_Excluded (0x0UL)             /*!< Exclude                                                              */
15607   #define DPPIC_CHG_CH0_Included (0x1UL)             /*!< Include                                                              */
15608 
15609 /* CH1 @Bit 1 : Include or exclude channel 1 */
15610   #define DPPIC_CHG_CH1_Pos (1UL)                    /*!< Position of CH1 field.                                               */
15611   #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field.                                           */
15612   #define DPPIC_CHG_CH1_Min (0x0UL)                  /*!< Min enumerator value of CH1 field.                                   */
15613   #define DPPIC_CHG_CH1_Max (0x1UL)                  /*!< Max enumerator value of CH1 field.                                   */
15614   #define DPPIC_CHG_CH1_Excluded (0x0UL)             /*!< Exclude                                                              */
15615   #define DPPIC_CHG_CH1_Included (0x1UL)             /*!< Include                                                              */
15616 
15617 /* CH2 @Bit 2 : Include or exclude channel 2 */
15618   #define DPPIC_CHG_CH2_Pos (2UL)                    /*!< Position of CH2 field.                                               */
15619   #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field.                                           */
15620   #define DPPIC_CHG_CH2_Min (0x0UL)                  /*!< Min enumerator value of CH2 field.                                   */
15621   #define DPPIC_CHG_CH2_Max (0x1UL)                  /*!< Max enumerator value of CH2 field.                                   */
15622   #define DPPIC_CHG_CH2_Excluded (0x0UL)             /*!< Exclude                                                              */
15623   #define DPPIC_CHG_CH2_Included (0x1UL)             /*!< Include                                                              */
15624 
15625 /* CH3 @Bit 3 : Include or exclude channel 3 */
15626   #define DPPIC_CHG_CH3_Pos (3UL)                    /*!< Position of CH3 field.                                               */
15627   #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field.                                           */
15628   #define DPPIC_CHG_CH3_Min (0x0UL)                  /*!< Min enumerator value of CH3 field.                                   */
15629   #define DPPIC_CHG_CH3_Max (0x1UL)                  /*!< Max enumerator value of CH3 field.                                   */
15630   #define DPPIC_CHG_CH3_Excluded (0x0UL)             /*!< Exclude                                                              */
15631   #define DPPIC_CHG_CH3_Included (0x1UL)             /*!< Include                                                              */
15632 
15633 /* CH4 @Bit 4 : Include or exclude channel 4 */
15634   #define DPPIC_CHG_CH4_Pos (4UL)                    /*!< Position of CH4 field.                                               */
15635   #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field.                                           */
15636   #define DPPIC_CHG_CH4_Min (0x0UL)                  /*!< Min enumerator value of CH4 field.                                   */
15637   #define DPPIC_CHG_CH4_Max (0x1UL)                  /*!< Max enumerator value of CH4 field.                                   */
15638   #define DPPIC_CHG_CH4_Excluded (0x0UL)             /*!< Exclude                                                              */
15639   #define DPPIC_CHG_CH4_Included (0x1UL)             /*!< Include                                                              */
15640 
15641 /* CH5 @Bit 5 : Include or exclude channel 5 */
15642   #define DPPIC_CHG_CH5_Pos (5UL)                    /*!< Position of CH5 field.                                               */
15643   #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field.                                           */
15644   #define DPPIC_CHG_CH5_Min (0x0UL)                  /*!< Min enumerator value of CH5 field.                                   */
15645   #define DPPIC_CHG_CH5_Max (0x1UL)                  /*!< Max enumerator value of CH5 field.                                   */
15646   #define DPPIC_CHG_CH5_Excluded (0x0UL)             /*!< Exclude                                                              */
15647   #define DPPIC_CHG_CH5_Included (0x1UL)             /*!< Include                                                              */
15648 
15649 /* CH6 @Bit 6 : Include or exclude channel 6 */
15650   #define DPPIC_CHG_CH6_Pos (6UL)                    /*!< Position of CH6 field.                                               */
15651   #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field.                                           */
15652   #define DPPIC_CHG_CH6_Min (0x0UL)                  /*!< Min enumerator value of CH6 field.                                   */
15653   #define DPPIC_CHG_CH6_Max (0x1UL)                  /*!< Max enumerator value of CH6 field.                                   */
15654   #define DPPIC_CHG_CH6_Excluded (0x0UL)             /*!< Exclude                                                              */
15655   #define DPPIC_CHG_CH6_Included (0x1UL)             /*!< Include                                                              */
15656 
15657 /* CH7 @Bit 7 : Include or exclude channel 7 */
15658   #define DPPIC_CHG_CH7_Pos (7UL)                    /*!< Position of CH7 field.                                               */
15659   #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field.                                           */
15660   #define DPPIC_CHG_CH7_Min (0x0UL)                  /*!< Min enumerator value of CH7 field.                                   */
15661   #define DPPIC_CHG_CH7_Max (0x1UL)                  /*!< Max enumerator value of CH7 field.                                   */
15662   #define DPPIC_CHG_CH7_Excluded (0x0UL)             /*!< Exclude                                                              */
15663   #define DPPIC_CHG_CH7_Included (0x1UL)             /*!< Include                                                              */
15664 
15665 /* CH8 @Bit 8 : Include or exclude channel 8 */
15666   #define DPPIC_CHG_CH8_Pos (8UL)                    /*!< Position of CH8 field.                                               */
15667   #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field.                                           */
15668   #define DPPIC_CHG_CH8_Min (0x0UL)                  /*!< Min enumerator value of CH8 field.                                   */
15669   #define DPPIC_CHG_CH8_Max (0x1UL)                  /*!< Max enumerator value of CH8 field.                                   */
15670   #define DPPIC_CHG_CH8_Excluded (0x0UL)             /*!< Exclude                                                              */
15671   #define DPPIC_CHG_CH8_Included (0x1UL)             /*!< Include                                                              */
15672 
15673 /* CH9 @Bit 9 : Include or exclude channel 9 */
15674   #define DPPIC_CHG_CH9_Pos (9UL)                    /*!< Position of CH9 field.                                               */
15675   #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field.                                           */
15676   #define DPPIC_CHG_CH9_Min (0x0UL)                  /*!< Min enumerator value of CH9 field.                                   */
15677   #define DPPIC_CHG_CH9_Max (0x1UL)                  /*!< Max enumerator value of CH9 field.                                   */
15678   #define DPPIC_CHG_CH9_Excluded (0x0UL)             /*!< Exclude                                                              */
15679   #define DPPIC_CHG_CH9_Included (0x1UL)             /*!< Include                                                              */
15680 
15681 /* CH10 @Bit 10 : Include or exclude channel 10 */
15682   #define DPPIC_CHG_CH10_Pos (10UL)                  /*!< Position of CH10 field.                                              */
15683   #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field.                                        */
15684   #define DPPIC_CHG_CH10_Min (0x0UL)                 /*!< Min enumerator value of CH10 field.                                  */
15685   #define DPPIC_CHG_CH10_Max (0x1UL)                 /*!< Max enumerator value of CH10 field.                                  */
15686   #define DPPIC_CHG_CH10_Excluded (0x0UL)            /*!< Exclude                                                              */
15687   #define DPPIC_CHG_CH10_Included (0x1UL)            /*!< Include                                                              */
15688 
15689 /* CH11 @Bit 11 : Include or exclude channel 11 */
15690   #define DPPIC_CHG_CH11_Pos (11UL)                  /*!< Position of CH11 field.                                              */
15691   #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field.                                        */
15692   #define DPPIC_CHG_CH11_Min (0x0UL)                 /*!< Min enumerator value of CH11 field.                                  */
15693   #define DPPIC_CHG_CH11_Max (0x1UL)                 /*!< Max enumerator value of CH11 field.                                  */
15694   #define DPPIC_CHG_CH11_Excluded (0x0UL)            /*!< Exclude                                                              */
15695   #define DPPIC_CHG_CH11_Included (0x1UL)            /*!< Include                                                              */
15696 
15697 /* CH12 @Bit 12 : Include or exclude channel 12 */
15698   #define DPPIC_CHG_CH12_Pos (12UL)                  /*!< Position of CH12 field.                                              */
15699   #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field.                                        */
15700   #define DPPIC_CHG_CH12_Min (0x0UL)                 /*!< Min enumerator value of CH12 field.                                  */
15701   #define DPPIC_CHG_CH12_Max (0x1UL)                 /*!< Max enumerator value of CH12 field.                                  */
15702   #define DPPIC_CHG_CH12_Excluded (0x0UL)            /*!< Exclude                                                              */
15703   #define DPPIC_CHG_CH12_Included (0x1UL)            /*!< Include                                                              */
15704 
15705 /* CH13 @Bit 13 : Include or exclude channel 13 */
15706   #define DPPIC_CHG_CH13_Pos (13UL)                  /*!< Position of CH13 field.                                              */
15707   #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field.                                        */
15708   #define DPPIC_CHG_CH13_Min (0x0UL)                 /*!< Min enumerator value of CH13 field.                                  */
15709   #define DPPIC_CHG_CH13_Max (0x1UL)                 /*!< Max enumerator value of CH13 field.                                  */
15710   #define DPPIC_CHG_CH13_Excluded (0x0UL)            /*!< Exclude                                                              */
15711   #define DPPIC_CHG_CH13_Included (0x1UL)            /*!< Include                                                              */
15712 
15713 /* CH14 @Bit 14 : Include or exclude channel 14 */
15714   #define DPPIC_CHG_CH14_Pos (14UL)                  /*!< Position of CH14 field.                                              */
15715   #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field.                                        */
15716   #define DPPIC_CHG_CH14_Min (0x0UL)                 /*!< Min enumerator value of CH14 field.                                  */
15717   #define DPPIC_CHG_CH14_Max (0x1UL)                 /*!< Max enumerator value of CH14 field.                                  */
15718   #define DPPIC_CHG_CH14_Excluded (0x0UL)            /*!< Exclude                                                              */
15719   #define DPPIC_CHG_CH14_Included (0x1UL)            /*!< Include                                                              */
15720 
15721 /* CH15 @Bit 15 : Include or exclude channel 15 */
15722   #define DPPIC_CHG_CH15_Pos (15UL)                  /*!< Position of CH15 field.                                              */
15723   #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field.                                        */
15724   #define DPPIC_CHG_CH15_Min (0x0UL)                 /*!< Min enumerator value of CH15 field.                                  */
15725   #define DPPIC_CHG_CH15_Max (0x1UL)                 /*!< Max enumerator value of CH15 field.                                  */
15726   #define DPPIC_CHG_CH15_Excluded (0x0UL)            /*!< Exclude                                                              */
15727   #define DPPIC_CHG_CH15_Included (0x1UL)            /*!< Include                                                              */
15728 
15729 
15730 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
15731 
15732 /* =========================================================================================================================== */
15733 /* ================                                            ECB                                            ================ */
15734 /* =========================================================================================================================== */
15735 
15736 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
15737 
15738 /* ===================================================== Struct ECB_KEY ====================================================== */
15739 /**
15740   * @brief KEY [ECB_KEY] (unspecified)
15741   */
15742 typedef struct {
15743   __OM  uint32_t  VALUE[4];                          /*!< (@ 0x00000000) 128-bit AES key                                       */
15744 } NRF_ECB_KEY_Type;                                  /*!< Size = 16 (0x010)                                                    */
15745 
15746 /* ECB_KEY_VALUE: 128-bit AES key */
15747   #define ECB_KEY_VALUE_MaxCount (4UL)               /*!< Max size of VALUE[4] array.                                          */
15748   #define ECB_KEY_VALUE_MaxIndex (3UL)               /*!< Max index of VALUE[4] array.                                         */
15749   #define ECB_KEY_VALUE_MinIndex (0UL)               /*!< Min index of VALUE[4] array.                                         */
15750   #define ECB_KEY_VALUE_ResetValue (0x00000000UL)    /*!< Reset value of VALUE[4] register.                                    */
15751 
15752 /* VALUE @Bits 0..31 : AES 128-bit key value, bits (32*(n+1))-1 : (32*n) */
15753   #define ECB_KEY_VALUE_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
15754   #define ECB_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << ECB_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field.                      */
15755 
15756 
15757 
15758 /* ====================================================== Struct ECB_IN ====================================================== */
15759 /**
15760   * @brief IN [ECB_IN] IN EasyDMA channel
15761   */
15762 typedef struct {
15763   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Input pointer                                         */
15764   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Number of bytes read from the input data, not including
15765                                                                          the job list structure*/
15766 } NRF_ECB_IN_Type;                                   /*!< Size = 8 (0x008)                                                     */
15767 
15768 /* ECB_IN_PTR: Input pointer */
15769   #define ECB_IN_PTR_ResetValue (0x00000000UL)       /*!< Reset value of PTR register.                                         */
15770 
15771 /* PTR @Bits 0..31 : Points to a job list containing unencrypted ECB data structure */
15772   #define ECB_IN_PTR_PTR_Pos (0UL)                   /*!< Position of PTR field.                                               */
15773   #define ECB_IN_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_IN_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                  */
15774 
15775 
15776 /* ECB_IN_AMOUNT: Number of bytes read from the input data, not including the job list structure */
15777   #define ECB_IN_AMOUNT_ResetValue (0x00000000UL)    /*!< Reset value of AMOUNT register.                                      */
15778 
15779 /* AMOUNT @Bits 0..31 : Number of bytes read from the input data */
15780   #define ECB_IN_AMOUNT_AMOUNT_Pos (0UL)             /*!< Position of AMOUNT field.                                            */
15781   #define ECB_IN_AMOUNT_AMOUNT_Msk (0xFFFFFFFFUL << ECB_IN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
15782 
15783 
15784 
15785 /* ===================================================== Struct ECB_OUT ====================================================== */
15786 /**
15787   * @brief OUT [ECB_OUT] OUT EasyDMA channel
15788   */
15789 typedef struct {
15790   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Output pointer Points to a job list containing
15791                                                                          encrypted ECB data structure*/
15792   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Number of bytes available in the output data, not
15793                                                                          including the job list structure*/
15794 } NRF_ECB_OUT_Type;                                  /*!< Size = 8 (0x008)                                                     */
15795 
15796 /* ECB_OUT_PTR: Output pointer Points to a job list containing encrypted ECB data structure */
15797   #define ECB_OUT_PTR_ResetValue (0x00000000UL)      /*!< Reset value of PTR register.                                         */
15798 
15799 /* PTR @Bits 0..31 : Output pointer */
15800   #define ECB_OUT_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
15801   #define ECB_OUT_PTR_PTR_Msk (0xFFFFFFFFUL << ECB_OUT_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */
15802 
15803 
15804 /* ECB_OUT_AMOUNT: Number of bytes available in the output data, not including the job list structure */
15805   #define ECB_OUT_AMOUNT_ResetValue (0x00000000UL)   /*!< Reset value of AMOUNT register.                                      */
15806 
15807 /* AMOUNT @Bits 0..31 : Number of bytes available in the output data */
15808   #define ECB_OUT_AMOUNT_AMOUNT_Pos (0UL)            /*!< Position of AMOUNT field.                                            */
15809   #define ECB_OUT_AMOUNT_AMOUNT_Msk (0xFFFFFFFFUL << ECB_OUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                 */
15810 
15811 
15812 /* ======================================================= Struct ECB ======================================================== */
15813 /**
15814   * @brief AES ECB Mode Encryption
15815   */
15816   typedef struct {                                   /*!< ECB Structure                                                        */
15817     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start ECB block encrypt                               */
15818     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Abort a possible executing ECB operation              */
15819     __IM uint32_t RESERVED[30];
15820     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
15821     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
15822     __IM uint32_t RESERVED1[30];
15823     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000100) ECB block encrypt complete                            */
15824     __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOP task or due
15825                                                                          to an error*/
15826     __IM uint32_t RESERVED2[30];
15827     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000180) Publish configuration for event END                   */
15828     __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x00000184) Publish configuration for event ERROR                 */
15829     __IM uint32_t RESERVED3[95];
15830     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
15831     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
15832     __IM uint32_t RESERVED4[129];
15833     __IOM NRF_ECB_KEY_Type KEY;                      /*!< (@ 0x00000510) (unspecified)                                         */
15834     __IM uint32_t RESERVED5[4];
15835     __IOM NRF_ECB_IN_Type IN;                        /*!< (@ 0x00000530) IN EasyDMA channel                                    */
15836     __IOM NRF_ECB_OUT_Type OUT;                      /*!< (@ 0x00000538) OUT EasyDMA channel                                   */
15837   } NRF_ECB_Type;                                    /*!< Size = 1344 (0x540)                                                  */
15838 
15839 /* ECB_TASKS_START: Start ECB block encrypt */
15840   #define ECB_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
15841 
15842 /* TASKS_START @Bit 0 : Start ECB block encrypt */
15843   #define ECB_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
15844   #define ECB_TASKS_START_TASKS_START_Msk (0x1UL << ECB_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
15845   #define ECB_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
15846   #define ECB_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
15847   #define ECB_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
15848 
15849 
15850 /* ECB_TASKS_STOP: Abort a possible executing ECB operation */
15851   #define ECB_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
15852 
15853 /* TASKS_STOP @Bit 0 : Abort a possible executing ECB operation */
15854   #define ECB_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
15855   #define ECB_TASKS_STOP_TASKS_STOP_Msk (0x1UL << ECB_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
15856   #define ECB_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
15857   #define ECB_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
15858   #define ECB_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
15859 
15860 
15861 /* ECB_SUBSCRIBE_START: Subscribe configuration for task START */
15862   #define ECB_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */
15863 
15864 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
15865   #define ECB_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
15866   #define ECB_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
15867   #define ECB_SUBSCRIBE_START_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
15868   #define ECB_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
15869 
15870 /* EN @Bit 31 : (unspecified) */
15871   #define ECB_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
15872   #define ECB_SUBSCRIBE_START_EN_Msk (0x1UL << ECB_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
15873   #define ECB_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
15874   #define ECB_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
15875   #define ECB_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
15876   #define ECB_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
15877 
15878 
15879 /* ECB_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
15880   #define ECB_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */
15881 
15882 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
15883   #define ECB_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
15884   #define ECB_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
15885   #define ECB_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
15886   #define ECB_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
15887 
15888 /* EN @Bit 31 : (unspecified) */
15889   #define ECB_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
15890   #define ECB_SUBSCRIBE_STOP_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
15891   #define ECB_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
15892   #define ECB_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
15893   #define ECB_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
15894   #define ECB_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
15895 
15896 
15897 /* ECB_EVENTS_END: ECB block encrypt complete */
15898   #define ECB_EVENTS_END_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_END register.                                  */
15899 
15900 /* EVENTS_END @Bit 0 : ECB block encrypt complete */
15901   #define ECB_EVENTS_END_EVENTS_END_Pos (0UL)        /*!< Position of EVENTS_END field.                                        */
15902   #define ECB_EVENTS_END_EVENTS_END_Msk (0x1UL << ECB_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.            */
15903   #define ECB_EVENTS_END_EVENTS_END_Min (0x0UL)      /*!< Min enumerator value of EVENTS_END field.                            */
15904   #define ECB_EVENTS_END_EVENTS_END_Max (0x1UL)      /*!< Max enumerator value of EVENTS_END field.                            */
15905   #define ECB_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                              */
15906   #define ECB_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                     */
15907 
15908 
15909 /* ECB_EVENTS_ERROR: ECB block encrypt aborted because of a STOP task or due to an error */
15910   #define ECB_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                                */
15911 
15912 /* EVENTS_ERROR @Bit 0 : ECB block encrypt aborted because of a STOP task or due to an error */
15913   #define ECB_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)    /*!< Position of EVENTS_ERROR field.                                      */
15914   #define ECB_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << ECB_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.  */
15915   #define ECB_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL)  /*!< Min enumerator value of EVENTS_ERROR field.                          */
15916   #define ECB_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL)  /*!< Max enumerator value of EVENTS_ERROR field.                          */
15917   #define ECB_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                          */
15918   #define ECB_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                 */
15919 
15920 
15921 /* ECB_PUBLISH_END: Publish configuration for event END */
15922   #define ECB_PUBLISH_END_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_END register.                                 */
15923 
15924 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
15925   #define ECB_PUBLISH_END_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
15926   #define ECB_PUBLISH_END_CHIDX_Msk (0xFFUL << ECB_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
15927   #define ECB_PUBLISH_END_CHIDX_Min (0x0UL)          /*!< Min value of CHIDX field.                                            */
15928   #define ECB_PUBLISH_END_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */
15929 
15930 /* EN @Bit 31 : (unspecified) */
15931   #define ECB_PUBLISH_END_EN_Pos (31UL)              /*!< Position of EN field.                                                */
15932   #define ECB_PUBLISH_END_EN_Msk (0x1UL << ECB_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                  */
15933   #define ECB_PUBLISH_END_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
15934   #define ECB_PUBLISH_END_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
15935   #define ECB_PUBLISH_END_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
15936   #define ECB_PUBLISH_END_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */
15937 
15938 
15939 /* ECB_PUBLISH_ERROR: Publish configuration for event ERROR */
15940   #define ECB_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                              */
15941 
15942 /* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
15943   #define ECB_PUBLISH_ERROR_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
15944   #define ECB_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
15945   #define ECB_PUBLISH_ERROR_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
15946   #define ECB_PUBLISH_ERROR_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
15947 
15948 /* EN @Bit 31 : (unspecified) */
15949   #define ECB_PUBLISH_ERROR_EN_Pos (31UL)            /*!< Position of EN field.                                                */
15950   #define ECB_PUBLISH_ERROR_EN_Msk (0x1UL << ECB_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                              */
15951   #define ECB_PUBLISH_ERROR_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
15952   #define ECB_PUBLISH_ERROR_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
15953   #define ECB_PUBLISH_ERROR_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
15954   #define ECB_PUBLISH_ERROR_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
15955 
15956 
15957 /* ECB_INTENSET: Enable interrupt */
15958   #define ECB_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
15959 
15960 /* END @Bit 0 : Write '1' to enable interrupt for event END */
15961   #define ECB_INTENSET_END_Pos (0UL)                 /*!< Position of END field.                                               */
15962   #define ECB_INTENSET_END_Msk (0x1UL << ECB_INTENSET_END_Pos) /*!< Bit mask of END field.                                     */
15963   #define ECB_INTENSET_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
15964   #define ECB_INTENSET_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
15965   #define ECB_INTENSET_END_Set (0x1UL)               /*!< Enable                                                               */
15966   #define ECB_INTENSET_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
15967   #define ECB_INTENSET_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
15968 
15969 /* ERROR @Bit 1 : Write '1' to enable interrupt for event ERROR */
15970   #define ECB_INTENSET_ERROR_Pos (1UL)               /*!< Position of ERROR field.                                             */
15971   #define ECB_INTENSET_ERROR_Msk (0x1UL << ECB_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
15972   #define ECB_INTENSET_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
15973   #define ECB_INTENSET_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
15974   #define ECB_INTENSET_ERROR_Set (0x1UL)             /*!< Enable                                                               */
15975   #define ECB_INTENSET_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
15976   #define ECB_INTENSET_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
15977 
15978 
15979 /* ECB_INTENCLR: Disable interrupt */
15980   #define ECB_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
15981 
15982 /* END @Bit 0 : Write '1' to disable interrupt for event END */
15983   #define ECB_INTENCLR_END_Pos (0UL)                 /*!< Position of END field.                                               */
15984   #define ECB_INTENCLR_END_Msk (0x1UL << ECB_INTENCLR_END_Pos) /*!< Bit mask of END field.                                     */
15985   #define ECB_INTENCLR_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
15986   #define ECB_INTENCLR_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
15987   #define ECB_INTENCLR_END_Clear (0x1UL)             /*!< Disable                                                              */
15988   #define ECB_INTENCLR_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
15989   #define ECB_INTENCLR_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
15990 
15991 /* ERROR @Bit 1 : Write '1' to disable interrupt for event ERROR */
15992   #define ECB_INTENCLR_ERROR_Pos (1UL)               /*!< Position of ERROR field.                                             */
15993   #define ECB_INTENCLR_ERROR_Msk (0x1UL << ECB_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                               */
15994   #define ECB_INTENCLR_ERROR_Min (0x0UL)             /*!< Min enumerator value of ERROR field.                                 */
15995   #define ECB_INTENCLR_ERROR_Max (0x1UL)             /*!< Max enumerator value of ERROR field.                                 */
15996   #define ECB_INTENCLR_ERROR_Clear (0x1UL)           /*!< Disable                                                              */
15997   #define ECB_INTENCLR_ERROR_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
15998   #define ECB_INTENCLR_ERROR_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
15999 
16000 
16001 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
16002 
16003 /* =========================================================================================================================== */
16004 /* ================                                            EGU                                            ================ */
16005 /* =========================================================================================================================== */
16006 
16007 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
16008 /* ======================================================= Struct EGU ======================================================== */
16009 /**
16010   * @brief Event generator unit
16011   */
16012   typedef struct {                                   /*!< EGU Structure                                                        */
16013     __OM uint32_t TASKS_TRIGGER[16];                 /*!< (@ 0x00000000) Trigger n for triggering the corresponding TRIGGERED[n]
16014                                                                          event*/
16015     __IM uint32_t RESERVED[16];
16016     __IOM uint32_t SUBSCRIBE_TRIGGER[16];            /*!< (@ 0x00000080) Subscribe configuration for task TRIGGER[n]           */
16017     __IM uint32_t RESERVED1[16];
16018     __IOM uint32_t EVENTS_TRIGGERED[16];             /*!< (@ 0x00000100) Event number n generated by triggering the
16019                                                                          corresponding TRIGGER[n] task*/
16020     __IM uint32_t RESERVED2[16];
16021     __IOM uint32_t PUBLISH_TRIGGERED[16];            /*!< (@ 0x00000180) Publish configuration for event TRIGGERED[n]          */
16022     __IM uint32_t RESERVED3[80];
16023     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
16024     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
16025     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
16026     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
16027   } NRF_EGU_Type;                                    /*!< Size = 784 (0x310)                                                   */
16028 
16029 /* EGU_TASKS_TRIGGER: Trigger n for triggering the corresponding TRIGGERED[n] event */
16030   #define EGU_TASKS_TRIGGER_MaxCount (16UL)          /*!< Max size of TASKS_TRIGGER[16] array.                                 */
16031   #define EGU_TASKS_TRIGGER_MaxIndex (15UL)          /*!< Max index of TASKS_TRIGGER[16] array.                                */
16032   #define EGU_TASKS_TRIGGER_MinIndex (0UL)           /*!< Min index of TASKS_TRIGGER[16] array.                                */
16033   #define EGU_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[16] register.                          */
16034 
16035 /* TASKS_TRIGGER @Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
16036   #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL)  /*!< Position of TASKS_TRIGGER field.                                     */
16037   #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER
16038                                                                             field.*/
16039   #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field.                        */
16040   #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field.                        */
16041   #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task                                                    */
16042 
16043 
16044 /* EGU_SUBSCRIBE_TRIGGER: Subscribe configuration for task TRIGGER[n] */
16045   #define EGU_SUBSCRIBE_TRIGGER_MaxCount (16UL)      /*!< Max size of SUBSCRIBE_TRIGGER[16] array.                             */
16046   #define EGU_SUBSCRIBE_TRIGGER_MaxIndex (15UL)      /*!< Max index of SUBSCRIBE_TRIGGER[16] array.                            */
16047   #define EGU_SUBSCRIBE_TRIGGER_MinIndex (0UL)       /*!< Min index of SUBSCRIBE_TRIGGER[16] array.                            */
16048   #define EGU_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[16] register.                  */
16049 
16050 /* CHIDX @Bits 0..7 : DPPI channel that task TRIGGER[n] will subscribe to */
16051   #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
16052   #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
16053   #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
16054   #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
16055 
16056 /* EN @Bit 31 : (unspecified) */
16057   #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL)        /*!< Position of EN field.                                                */
16058   #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field.                      */
16059   #define EGU_SUBSCRIBE_TRIGGER_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
16060   #define EGU_SUBSCRIBE_TRIGGER_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
16061   #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
16062   #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
16063 
16064 
16065 /* EGU_EVENTS_TRIGGERED: Event number n generated by triggering the corresponding TRIGGER[n] task */
16066   #define EGU_EVENTS_TRIGGERED_MaxCount (16UL)       /*!< Max size of EVENTS_TRIGGERED[16] array.                              */
16067   #define EGU_EVENTS_TRIGGERED_MaxIndex (15UL)       /*!< Max index of EVENTS_TRIGGERED[16] array.                             */
16068   #define EGU_EVENTS_TRIGGERED_MinIndex (0UL)        /*!< Min index of EVENTS_TRIGGERED[16] array.                             */
16069   #define EGU_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[16] register.                    */
16070 
16071 /* EVENTS_TRIGGERED @Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
16072   #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field.                             */
16073   #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of
16074                                                                             EVENTS_TRIGGERED field.*/
16075   #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field.               */
16076   #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field.               */
16077   #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated                                  */
16078   #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated                                         */
16079 
16080 
16081 /* EGU_PUBLISH_TRIGGERED: Publish configuration for event TRIGGERED[n] */
16082   #define EGU_PUBLISH_TRIGGERED_MaxCount (16UL)      /*!< Max size of PUBLISH_TRIGGERED[16] array.                             */
16083   #define EGU_PUBLISH_TRIGGERED_MaxIndex (15UL)      /*!< Max index of PUBLISH_TRIGGERED[16] array.                            */
16084   #define EGU_PUBLISH_TRIGGERED_MinIndex (0UL)       /*!< Min index of PUBLISH_TRIGGERED[16] array.                            */
16085   #define EGU_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[16] register.                  */
16086 
16087 /* CHIDX @Bits 0..7 : DPPI channel that event TRIGGERED[n] will publish to */
16088   #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
16089   #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
16090   #define EGU_PUBLISH_TRIGGERED_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
16091   #define EGU_PUBLISH_TRIGGERED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
16092 
16093 /* EN @Bit 31 : (unspecified) */
16094   #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
16095   #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field.                      */
16096   #define EGU_PUBLISH_TRIGGERED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
16097   #define EGU_PUBLISH_TRIGGERED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
16098   #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
16099   #define EGU_PUBLISH_TRIGGERED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
16100 
16101 
16102 /* EGU_INTEN: Enable or disable interrupt */
16103   #define EGU_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
16104 
16105 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
16106   #define EGU_INTEN_TRIGGERED0_Pos (0UL)             /*!< Position of TRIGGERED0 field.                                        */
16107   #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                      */
16108   #define EGU_INTEN_TRIGGERED0_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED0 field.                            */
16109   #define EGU_INTEN_TRIGGERED0_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED0 field.                            */
16110   #define EGU_INTEN_TRIGGERED0_Disabled (0x0UL)      /*!< Disable                                                              */
16111   #define EGU_INTEN_TRIGGERED0_Enabled (0x1UL)       /*!< Enable                                                               */
16112 
16113 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
16114   #define EGU_INTEN_TRIGGERED1_Pos (1UL)             /*!< Position of TRIGGERED1 field.                                        */
16115   #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                      */
16116   #define EGU_INTEN_TRIGGERED1_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED1 field.                            */
16117   #define EGU_INTEN_TRIGGERED1_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED1 field.                            */
16118   #define EGU_INTEN_TRIGGERED1_Disabled (0x0UL)      /*!< Disable                                                              */
16119   #define EGU_INTEN_TRIGGERED1_Enabled (0x1UL)       /*!< Enable                                                               */
16120 
16121 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
16122   #define EGU_INTEN_TRIGGERED2_Pos (2UL)             /*!< Position of TRIGGERED2 field.                                        */
16123   #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                      */
16124   #define EGU_INTEN_TRIGGERED2_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED2 field.                            */
16125   #define EGU_INTEN_TRIGGERED2_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED2 field.                            */
16126   #define EGU_INTEN_TRIGGERED2_Disabled (0x0UL)      /*!< Disable                                                              */
16127   #define EGU_INTEN_TRIGGERED2_Enabled (0x1UL)       /*!< Enable                                                               */
16128 
16129 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
16130   #define EGU_INTEN_TRIGGERED3_Pos (3UL)             /*!< Position of TRIGGERED3 field.                                        */
16131   #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                      */
16132   #define EGU_INTEN_TRIGGERED3_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED3 field.                            */
16133   #define EGU_INTEN_TRIGGERED3_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED3 field.                            */
16134   #define EGU_INTEN_TRIGGERED3_Disabled (0x0UL)      /*!< Disable                                                              */
16135   #define EGU_INTEN_TRIGGERED3_Enabled (0x1UL)       /*!< Enable                                                               */
16136 
16137 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
16138   #define EGU_INTEN_TRIGGERED4_Pos (4UL)             /*!< Position of TRIGGERED4 field.                                        */
16139   #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                      */
16140   #define EGU_INTEN_TRIGGERED4_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED4 field.                            */
16141   #define EGU_INTEN_TRIGGERED4_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED4 field.                            */
16142   #define EGU_INTEN_TRIGGERED4_Disabled (0x0UL)      /*!< Disable                                                              */
16143   #define EGU_INTEN_TRIGGERED4_Enabled (0x1UL)       /*!< Enable                                                               */
16144 
16145 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
16146   #define EGU_INTEN_TRIGGERED5_Pos (5UL)             /*!< Position of TRIGGERED5 field.                                        */
16147   #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                      */
16148   #define EGU_INTEN_TRIGGERED5_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED5 field.                            */
16149   #define EGU_INTEN_TRIGGERED5_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED5 field.                            */
16150   #define EGU_INTEN_TRIGGERED5_Disabled (0x0UL)      /*!< Disable                                                              */
16151   #define EGU_INTEN_TRIGGERED5_Enabled (0x1UL)       /*!< Enable                                                               */
16152 
16153 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
16154   #define EGU_INTEN_TRIGGERED6_Pos (6UL)             /*!< Position of TRIGGERED6 field.                                        */
16155   #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                      */
16156   #define EGU_INTEN_TRIGGERED6_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED6 field.                            */
16157   #define EGU_INTEN_TRIGGERED6_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED6 field.                            */
16158   #define EGU_INTEN_TRIGGERED6_Disabled (0x0UL)      /*!< Disable                                                              */
16159   #define EGU_INTEN_TRIGGERED6_Enabled (0x1UL)       /*!< Enable                                                               */
16160 
16161 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
16162   #define EGU_INTEN_TRIGGERED7_Pos (7UL)             /*!< Position of TRIGGERED7 field.                                        */
16163   #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                      */
16164   #define EGU_INTEN_TRIGGERED7_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED7 field.                            */
16165   #define EGU_INTEN_TRIGGERED7_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED7 field.                            */
16166   #define EGU_INTEN_TRIGGERED7_Disabled (0x0UL)      /*!< Disable                                                              */
16167   #define EGU_INTEN_TRIGGERED7_Enabled (0x1UL)       /*!< Enable                                                               */
16168 
16169 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
16170   #define EGU_INTEN_TRIGGERED8_Pos (8UL)             /*!< Position of TRIGGERED8 field.                                        */
16171   #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                      */
16172   #define EGU_INTEN_TRIGGERED8_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED8 field.                            */
16173   #define EGU_INTEN_TRIGGERED8_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED8 field.                            */
16174   #define EGU_INTEN_TRIGGERED8_Disabled (0x0UL)      /*!< Disable                                                              */
16175   #define EGU_INTEN_TRIGGERED8_Enabled (0x1UL)       /*!< Enable                                                               */
16176 
16177 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
16178   #define EGU_INTEN_TRIGGERED9_Pos (9UL)             /*!< Position of TRIGGERED9 field.                                        */
16179   #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                      */
16180   #define EGU_INTEN_TRIGGERED9_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED9 field.                            */
16181   #define EGU_INTEN_TRIGGERED9_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED9 field.                            */
16182   #define EGU_INTEN_TRIGGERED9_Disabled (0x0UL)      /*!< Disable                                                              */
16183   #define EGU_INTEN_TRIGGERED9_Enabled (0x1UL)       /*!< Enable                                                               */
16184 
16185 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
16186   #define EGU_INTEN_TRIGGERED10_Pos (10UL)           /*!< Position of TRIGGERED10 field.                                       */
16187   #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.                   */
16188   #define EGU_INTEN_TRIGGERED10_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED10 field.                           */
16189   #define EGU_INTEN_TRIGGERED10_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED10 field.                           */
16190   #define EGU_INTEN_TRIGGERED10_Disabled (0x0UL)     /*!< Disable                                                              */
16191   #define EGU_INTEN_TRIGGERED10_Enabled (0x1UL)      /*!< Enable                                                               */
16192 
16193 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
16194   #define EGU_INTEN_TRIGGERED11_Pos (11UL)           /*!< Position of TRIGGERED11 field.                                       */
16195   #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.                   */
16196   #define EGU_INTEN_TRIGGERED11_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED11 field.                           */
16197   #define EGU_INTEN_TRIGGERED11_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED11 field.                           */
16198   #define EGU_INTEN_TRIGGERED11_Disabled (0x0UL)     /*!< Disable                                                              */
16199   #define EGU_INTEN_TRIGGERED11_Enabled (0x1UL)      /*!< Enable                                                               */
16200 
16201 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
16202   #define EGU_INTEN_TRIGGERED12_Pos (12UL)           /*!< Position of TRIGGERED12 field.                                       */
16203   #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.                   */
16204   #define EGU_INTEN_TRIGGERED12_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED12 field.                           */
16205   #define EGU_INTEN_TRIGGERED12_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED12 field.                           */
16206   #define EGU_INTEN_TRIGGERED12_Disabled (0x0UL)     /*!< Disable                                                              */
16207   #define EGU_INTEN_TRIGGERED12_Enabled (0x1UL)      /*!< Enable                                                               */
16208 
16209 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
16210   #define EGU_INTEN_TRIGGERED13_Pos (13UL)           /*!< Position of TRIGGERED13 field.                                       */
16211   #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.                   */
16212   #define EGU_INTEN_TRIGGERED13_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED13 field.                           */
16213   #define EGU_INTEN_TRIGGERED13_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED13 field.                           */
16214   #define EGU_INTEN_TRIGGERED13_Disabled (0x0UL)     /*!< Disable                                                              */
16215   #define EGU_INTEN_TRIGGERED13_Enabled (0x1UL)      /*!< Enable                                                               */
16216 
16217 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
16218   #define EGU_INTEN_TRIGGERED14_Pos (14UL)           /*!< Position of TRIGGERED14 field.                                       */
16219   #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.                   */
16220   #define EGU_INTEN_TRIGGERED14_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED14 field.                           */
16221   #define EGU_INTEN_TRIGGERED14_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED14 field.                           */
16222   #define EGU_INTEN_TRIGGERED14_Disabled (0x0UL)     /*!< Disable                                                              */
16223   #define EGU_INTEN_TRIGGERED14_Enabled (0x1UL)      /*!< Enable                                                               */
16224 
16225 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
16226   #define EGU_INTEN_TRIGGERED15_Pos (15UL)           /*!< Position of TRIGGERED15 field.                                       */
16227   #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.                   */
16228   #define EGU_INTEN_TRIGGERED15_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED15 field.                           */
16229   #define EGU_INTEN_TRIGGERED15_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED15 field.                           */
16230   #define EGU_INTEN_TRIGGERED15_Disabled (0x0UL)     /*!< Disable                                                              */
16231   #define EGU_INTEN_TRIGGERED15_Enabled (0x1UL)      /*!< Enable                                                               */
16232 
16233 
16234 /* EGU_INTENSET: Enable interrupt */
16235   #define EGU_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
16236 
16237 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
16238   #define EGU_INTENSET_TRIGGERED0_Pos (0UL)          /*!< Position of TRIGGERED0 field.                                        */
16239   #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                */
16240   #define EGU_INTENSET_TRIGGERED0_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED0 field.                            */
16241   #define EGU_INTENSET_TRIGGERED0_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED0 field.                            */
16242   #define EGU_INTENSET_TRIGGERED0_Set (0x1UL)        /*!< Enable                                                               */
16243   #define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16244   #define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16245 
16246 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
16247   #define EGU_INTENSET_TRIGGERED1_Pos (1UL)          /*!< Position of TRIGGERED1 field.                                        */
16248   #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                */
16249   #define EGU_INTENSET_TRIGGERED1_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED1 field.                            */
16250   #define EGU_INTENSET_TRIGGERED1_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED1 field.                            */
16251   #define EGU_INTENSET_TRIGGERED1_Set (0x1UL)        /*!< Enable                                                               */
16252   #define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16253   #define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16254 
16255 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
16256   #define EGU_INTENSET_TRIGGERED2_Pos (2UL)          /*!< Position of TRIGGERED2 field.                                        */
16257   #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                */
16258   #define EGU_INTENSET_TRIGGERED2_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED2 field.                            */
16259   #define EGU_INTENSET_TRIGGERED2_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED2 field.                            */
16260   #define EGU_INTENSET_TRIGGERED2_Set (0x1UL)        /*!< Enable                                                               */
16261   #define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16262   #define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16263 
16264 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
16265   #define EGU_INTENSET_TRIGGERED3_Pos (3UL)          /*!< Position of TRIGGERED3 field.                                        */
16266   #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                */
16267   #define EGU_INTENSET_TRIGGERED3_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED3 field.                            */
16268   #define EGU_INTENSET_TRIGGERED3_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED3 field.                            */
16269   #define EGU_INTENSET_TRIGGERED3_Set (0x1UL)        /*!< Enable                                                               */
16270   #define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16271   #define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16272 
16273 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
16274   #define EGU_INTENSET_TRIGGERED4_Pos (4UL)          /*!< Position of TRIGGERED4 field.                                        */
16275   #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                */
16276   #define EGU_INTENSET_TRIGGERED4_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED4 field.                            */
16277   #define EGU_INTENSET_TRIGGERED4_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED4 field.                            */
16278   #define EGU_INTENSET_TRIGGERED4_Set (0x1UL)        /*!< Enable                                                               */
16279   #define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16280   #define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16281 
16282 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
16283   #define EGU_INTENSET_TRIGGERED5_Pos (5UL)          /*!< Position of TRIGGERED5 field.                                        */
16284   #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                */
16285   #define EGU_INTENSET_TRIGGERED5_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED5 field.                            */
16286   #define EGU_INTENSET_TRIGGERED5_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED5 field.                            */
16287   #define EGU_INTENSET_TRIGGERED5_Set (0x1UL)        /*!< Enable                                                               */
16288   #define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16289   #define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16290 
16291 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
16292   #define EGU_INTENSET_TRIGGERED6_Pos (6UL)          /*!< Position of TRIGGERED6 field.                                        */
16293   #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                */
16294   #define EGU_INTENSET_TRIGGERED6_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED6 field.                            */
16295   #define EGU_INTENSET_TRIGGERED6_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED6 field.                            */
16296   #define EGU_INTENSET_TRIGGERED6_Set (0x1UL)        /*!< Enable                                                               */
16297   #define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16298   #define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16299 
16300 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
16301   #define EGU_INTENSET_TRIGGERED7_Pos (7UL)          /*!< Position of TRIGGERED7 field.                                        */
16302   #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                */
16303   #define EGU_INTENSET_TRIGGERED7_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED7 field.                            */
16304   #define EGU_INTENSET_TRIGGERED7_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED7 field.                            */
16305   #define EGU_INTENSET_TRIGGERED7_Set (0x1UL)        /*!< Enable                                                               */
16306   #define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16307   #define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16308 
16309 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
16310   #define EGU_INTENSET_TRIGGERED8_Pos (8UL)          /*!< Position of TRIGGERED8 field.                                        */
16311   #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                */
16312   #define EGU_INTENSET_TRIGGERED8_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED8 field.                            */
16313   #define EGU_INTENSET_TRIGGERED8_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED8 field.                            */
16314   #define EGU_INTENSET_TRIGGERED8_Set (0x1UL)        /*!< Enable                                                               */
16315   #define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16316   #define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16317 
16318 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
16319   #define EGU_INTENSET_TRIGGERED9_Pos (9UL)          /*!< Position of TRIGGERED9 field.                                        */
16320   #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                */
16321   #define EGU_INTENSET_TRIGGERED9_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED9 field.                            */
16322   #define EGU_INTENSET_TRIGGERED9_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED9 field.                            */
16323   #define EGU_INTENSET_TRIGGERED9_Set (0x1UL)        /*!< Enable                                                               */
16324   #define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16325   #define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16326 
16327 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
16328   #define EGU_INTENSET_TRIGGERED10_Pos (10UL)        /*!< Position of TRIGGERED10 field.                                       */
16329   #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.             */
16330   #define EGU_INTENSET_TRIGGERED10_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED10 field.                           */
16331   #define EGU_INTENSET_TRIGGERED10_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED10 field.                           */
16332   #define EGU_INTENSET_TRIGGERED10_Set (0x1UL)       /*!< Enable                                                               */
16333   #define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16334   #define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16335 
16336 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
16337   #define EGU_INTENSET_TRIGGERED11_Pos (11UL)        /*!< Position of TRIGGERED11 field.                                       */
16338   #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.             */
16339   #define EGU_INTENSET_TRIGGERED11_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED11 field.                           */
16340   #define EGU_INTENSET_TRIGGERED11_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED11 field.                           */
16341   #define EGU_INTENSET_TRIGGERED11_Set (0x1UL)       /*!< Enable                                                               */
16342   #define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16343   #define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16344 
16345 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
16346   #define EGU_INTENSET_TRIGGERED12_Pos (12UL)        /*!< Position of TRIGGERED12 field.                                       */
16347   #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.             */
16348   #define EGU_INTENSET_TRIGGERED12_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED12 field.                           */
16349   #define EGU_INTENSET_TRIGGERED12_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED12 field.                           */
16350   #define EGU_INTENSET_TRIGGERED12_Set (0x1UL)       /*!< Enable                                                               */
16351   #define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16352   #define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16353 
16354 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
16355   #define EGU_INTENSET_TRIGGERED13_Pos (13UL)        /*!< Position of TRIGGERED13 field.                                       */
16356   #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.             */
16357   #define EGU_INTENSET_TRIGGERED13_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED13 field.                           */
16358   #define EGU_INTENSET_TRIGGERED13_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED13 field.                           */
16359   #define EGU_INTENSET_TRIGGERED13_Set (0x1UL)       /*!< Enable                                                               */
16360   #define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16361   #define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16362 
16363 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
16364   #define EGU_INTENSET_TRIGGERED14_Pos (14UL)        /*!< Position of TRIGGERED14 field.                                       */
16365   #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.             */
16366   #define EGU_INTENSET_TRIGGERED14_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED14 field.                           */
16367   #define EGU_INTENSET_TRIGGERED14_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED14 field.                           */
16368   #define EGU_INTENSET_TRIGGERED14_Set (0x1UL)       /*!< Enable                                                               */
16369   #define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16370   #define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16371 
16372 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
16373   #define EGU_INTENSET_TRIGGERED15_Pos (15UL)        /*!< Position of TRIGGERED15 field.                                       */
16374   #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.             */
16375   #define EGU_INTENSET_TRIGGERED15_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED15 field.                           */
16376   #define EGU_INTENSET_TRIGGERED15_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED15 field.                           */
16377   #define EGU_INTENSET_TRIGGERED15_Set (0x1UL)       /*!< Enable                                                               */
16378   #define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16379   #define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16380 
16381 
16382 /* EGU_INTENCLR: Disable interrupt */
16383   #define EGU_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
16384 
16385 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
16386   #define EGU_INTENCLR_TRIGGERED0_Pos (0UL)          /*!< Position of TRIGGERED0 field.                                        */
16387   #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                */
16388   #define EGU_INTENCLR_TRIGGERED0_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED0 field.                            */
16389   #define EGU_INTENCLR_TRIGGERED0_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED0 field.                            */
16390   #define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL)      /*!< Disable                                                              */
16391   #define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16392   #define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16393 
16394 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
16395   #define EGU_INTENCLR_TRIGGERED1_Pos (1UL)          /*!< Position of TRIGGERED1 field.                                        */
16396   #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                */
16397   #define EGU_INTENCLR_TRIGGERED1_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED1 field.                            */
16398   #define EGU_INTENCLR_TRIGGERED1_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED1 field.                            */
16399   #define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL)      /*!< Disable                                                              */
16400   #define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16401   #define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16402 
16403 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
16404   #define EGU_INTENCLR_TRIGGERED2_Pos (2UL)          /*!< Position of TRIGGERED2 field.                                        */
16405   #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                */
16406   #define EGU_INTENCLR_TRIGGERED2_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED2 field.                            */
16407   #define EGU_INTENCLR_TRIGGERED2_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED2 field.                            */
16408   #define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL)      /*!< Disable                                                              */
16409   #define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16410   #define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16411 
16412 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
16413   #define EGU_INTENCLR_TRIGGERED3_Pos (3UL)          /*!< Position of TRIGGERED3 field.                                        */
16414   #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                */
16415   #define EGU_INTENCLR_TRIGGERED3_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED3 field.                            */
16416   #define EGU_INTENCLR_TRIGGERED3_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED3 field.                            */
16417   #define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL)      /*!< Disable                                                              */
16418   #define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16419   #define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16420 
16421 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
16422   #define EGU_INTENCLR_TRIGGERED4_Pos (4UL)          /*!< Position of TRIGGERED4 field.                                        */
16423   #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                */
16424   #define EGU_INTENCLR_TRIGGERED4_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED4 field.                            */
16425   #define EGU_INTENCLR_TRIGGERED4_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED4 field.                            */
16426   #define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL)      /*!< Disable                                                              */
16427   #define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16428   #define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16429 
16430 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
16431   #define EGU_INTENCLR_TRIGGERED5_Pos (5UL)          /*!< Position of TRIGGERED5 field.                                        */
16432   #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                */
16433   #define EGU_INTENCLR_TRIGGERED5_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED5 field.                            */
16434   #define EGU_INTENCLR_TRIGGERED5_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED5 field.                            */
16435   #define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL)      /*!< Disable                                                              */
16436   #define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16437   #define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16438 
16439 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
16440   #define EGU_INTENCLR_TRIGGERED6_Pos (6UL)          /*!< Position of TRIGGERED6 field.                                        */
16441   #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                */
16442   #define EGU_INTENCLR_TRIGGERED6_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED6 field.                            */
16443   #define EGU_INTENCLR_TRIGGERED6_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED6 field.                            */
16444   #define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL)      /*!< Disable                                                              */
16445   #define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16446   #define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16447 
16448 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
16449   #define EGU_INTENCLR_TRIGGERED7_Pos (7UL)          /*!< Position of TRIGGERED7 field.                                        */
16450   #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                */
16451   #define EGU_INTENCLR_TRIGGERED7_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED7 field.                            */
16452   #define EGU_INTENCLR_TRIGGERED7_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED7 field.                            */
16453   #define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL)      /*!< Disable                                                              */
16454   #define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16455   #define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16456 
16457 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
16458   #define EGU_INTENCLR_TRIGGERED8_Pos (8UL)          /*!< Position of TRIGGERED8 field.                                        */
16459   #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                */
16460   #define EGU_INTENCLR_TRIGGERED8_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED8 field.                            */
16461   #define EGU_INTENCLR_TRIGGERED8_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED8 field.                            */
16462   #define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL)      /*!< Disable                                                              */
16463   #define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16464   #define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16465 
16466 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
16467   #define EGU_INTENCLR_TRIGGERED9_Pos (9UL)          /*!< Position of TRIGGERED9 field.                                        */
16468   #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                */
16469   #define EGU_INTENCLR_TRIGGERED9_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED9 field.                            */
16470   #define EGU_INTENCLR_TRIGGERED9_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED9 field.                            */
16471   #define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL)      /*!< Disable                                                              */
16472   #define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
16473   #define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
16474 
16475 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
16476   #define EGU_INTENCLR_TRIGGERED10_Pos (10UL)        /*!< Position of TRIGGERED10 field.                                       */
16477   #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.             */
16478   #define EGU_INTENCLR_TRIGGERED10_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED10 field.                           */
16479   #define EGU_INTENCLR_TRIGGERED10_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED10 field.                           */
16480   #define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL)     /*!< Disable                                                              */
16481   #define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16482   #define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16483 
16484 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
16485   #define EGU_INTENCLR_TRIGGERED11_Pos (11UL)        /*!< Position of TRIGGERED11 field.                                       */
16486   #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.             */
16487   #define EGU_INTENCLR_TRIGGERED11_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED11 field.                           */
16488   #define EGU_INTENCLR_TRIGGERED11_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED11 field.                           */
16489   #define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL)     /*!< Disable                                                              */
16490   #define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16491   #define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16492 
16493 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
16494   #define EGU_INTENCLR_TRIGGERED12_Pos (12UL)        /*!< Position of TRIGGERED12 field.                                       */
16495   #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.             */
16496   #define EGU_INTENCLR_TRIGGERED12_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED12 field.                           */
16497   #define EGU_INTENCLR_TRIGGERED12_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED12 field.                           */
16498   #define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL)     /*!< Disable                                                              */
16499   #define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16500   #define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16501 
16502 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
16503   #define EGU_INTENCLR_TRIGGERED13_Pos (13UL)        /*!< Position of TRIGGERED13 field.                                       */
16504   #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.             */
16505   #define EGU_INTENCLR_TRIGGERED13_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED13 field.                           */
16506   #define EGU_INTENCLR_TRIGGERED13_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED13 field.                           */
16507   #define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL)     /*!< Disable                                                              */
16508   #define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16509   #define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16510 
16511 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
16512   #define EGU_INTENCLR_TRIGGERED14_Pos (14UL)        /*!< Position of TRIGGERED14 field.                                       */
16513   #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.             */
16514   #define EGU_INTENCLR_TRIGGERED14_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED14 field.                           */
16515   #define EGU_INTENCLR_TRIGGERED14_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED14 field.                           */
16516   #define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL)     /*!< Disable                                                              */
16517   #define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16518   #define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16519 
16520 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
16521   #define EGU_INTENCLR_TRIGGERED15_Pos (15UL)        /*!< Position of TRIGGERED15 field.                                       */
16522   #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.             */
16523   #define EGU_INTENCLR_TRIGGERED15_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED15 field.                           */
16524   #define EGU_INTENCLR_TRIGGERED15_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED15 field.                           */
16525   #define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL)     /*!< Disable                                                              */
16526   #define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
16527   #define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
16528 
16529 
16530 /* EGU_INTPEND: Pending interrupts */
16531   #define EGU_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */
16532 
16533 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
16534   #define EGU_INTPEND_TRIGGERED0_Pos (0UL)           /*!< Position of TRIGGERED0 field.                                        */
16535   #define EGU_INTPEND_TRIGGERED0_Msk (0x1UL << EGU_INTPEND_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                  */
16536   #define EGU_INTPEND_TRIGGERED0_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED0 field.                            */
16537   #define EGU_INTPEND_TRIGGERED0_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED0 field.                            */
16538   #define EGU_INTPEND_TRIGGERED0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16539   #define EGU_INTPEND_TRIGGERED0_Pending (0x1UL)     /*!< Read: Pending                                                        */
16540 
16541 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
16542   #define EGU_INTPEND_TRIGGERED1_Pos (1UL)           /*!< Position of TRIGGERED1 field.                                        */
16543   #define EGU_INTPEND_TRIGGERED1_Msk (0x1UL << EGU_INTPEND_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                  */
16544   #define EGU_INTPEND_TRIGGERED1_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED1 field.                            */
16545   #define EGU_INTPEND_TRIGGERED1_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED1 field.                            */
16546   #define EGU_INTPEND_TRIGGERED1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16547   #define EGU_INTPEND_TRIGGERED1_Pending (0x1UL)     /*!< Read: Pending                                                        */
16548 
16549 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
16550   #define EGU_INTPEND_TRIGGERED2_Pos (2UL)           /*!< Position of TRIGGERED2 field.                                        */
16551   #define EGU_INTPEND_TRIGGERED2_Msk (0x1UL << EGU_INTPEND_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                  */
16552   #define EGU_INTPEND_TRIGGERED2_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED2 field.                            */
16553   #define EGU_INTPEND_TRIGGERED2_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED2 field.                            */
16554   #define EGU_INTPEND_TRIGGERED2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16555   #define EGU_INTPEND_TRIGGERED2_Pending (0x1UL)     /*!< Read: Pending                                                        */
16556 
16557 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
16558   #define EGU_INTPEND_TRIGGERED3_Pos (3UL)           /*!< Position of TRIGGERED3 field.                                        */
16559   #define EGU_INTPEND_TRIGGERED3_Msk (0x1UL << EGU_INTPEND_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                  */
16560   #define EGU_INTPEND_TRIGGERED3_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED3 field.                            */
16561   #define EGU_INTPEND_TRIGGERED3_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED3 field.                            */
16562   #define EGU_INTPEND_TRIGGERED3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16563   #define EGU_INTPEND_TRIGGERED3_Pending (0x1UL)     /*!< Read: Pending                                                        */
16564 
16565 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
16566   #define EGU_INTPEND_TRIGGERED4_Pos (4UL)           /*!< Position of TRIGGERED4 field.                                        */
16567   #define EGU_INTPEND_TRIGGERED4_Msk (0x1UL << EGU_INTPEND_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                  */
16568   #define EGU_INTPEND_TRIGGERED4_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED4 field.                            */
16569   #define EGU_INTPEND_TRIGGERED4_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED4 field.                            */
16570   #define EGU_INTPEND_TRIGGERED4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16571   #define EGU_INTPEND_TRIGGERED4_Pending (0x1UL)     /*!< Read: Pending                                                        */
16572 
16573 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
16574   #define EGU_INTPEND_TRIGGERED5_Pos (5UL)           /*!< Position of TRIGGERED5 field.                                        */
16575   #define EGU_INTPEND_TRIGGERED5_Msk (0x1UL << EGU_INTPEND_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                  */
16576   #define EGU_INTPEND_TRIGGERED5_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED5 field.                            */
16577   #define EGU_INTPEND_TRIGGERED5_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED5 field.                            */
16578   #define EGU_INTPEND_TRIGGERED5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16579   #define EGU_INTPEND_TRIGGERED5_Pending (0x1UL)     /*!< Read: Pending                                                        */
16580 
16581 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
16582   #define EGU_INTPEND_TRIGGERED6_Pos (6UL)           /*!< Position of TRIGGERED6 field.                                        */
16583   #define EGU_INTPEND_TRIGGERED6_Msk (0x1UL << EGU_INTPEND_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                  */
16584   #define EGU_INTPEND_TRIGGERED6_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED6 field.                            */
16585   #define EGU_INTPEND_TRIGGERED6_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED6 field.                            */
16586   #define EGU_INTPEND_TRIGGERED6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16587   #define EGU_INTPEND_TRIGGERED6_Pending (0x1UL)     /*!< Read: Pending                                                        */
16588 
16589 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
16590   #define EGU_INTPEND_TRIGGERED7_Pos (7UL)           /*!< Position of TRIGGERED7 field.                                        */
16591   #define EGU_INTPEND_TRIGGERED7_Msk (0x1UL << EGU_INTPEND_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                  */
16592   #define EGU_INTPEND_TRIGGERED7_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED7 field.                            */
16593   #define EGU_INTPEND_TRIGGERED7_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED7 field.                            */
16594   #define EGU_INTPEND_TRIGGERED7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16595   #define EGU_INTPEND_TRIGGERED7_Pending (0x1UL)     /*!< Read: Pending                                                        */
16596 
16597 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
16598   #define EGU_INTPEND_TRIGGERED8_Pos (8UL)           /*!< Position of TRIGGERED8 field.                                        */
16599   #define EGU_INTPEND_TRIGGERED8_Msk (0x1UL << EGU_INTPEND_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                  */
16600   #define EGU_INTPEND_TRIGGERED8_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED8 field.                            */
16601   #define EGU_INTPEND_TRIGGERED8_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED8 field.                            */
16602   #define EGU_INTPEND_TRIGGERED8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16603   #define EGU_INTPEND_TRIGGERED8_Pending (0x1UL)     /*!< Read: Pending                                                        */
16604 
16605 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
16606   #define EGU_INTPEND_TRIGGERED9_Pos (9UL)           /*!< Position of TRIGGERED9 field.                                        */
16607   #define EGU_INTPEND_TRIGGERED9_Msk (0x1UL << EGU_INTPEND_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                  */
16608   #define EGU_INTPEND_TRIGGERED9_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED9 field.                            */
16609   #define EGU_INTPEND_TRIGGERED9_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED9 field.                            */
16610   #define EGU_INTPEND_TRIGGERED9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
16611   #define EGU_INTPEND_TRIGGERED9_Pending (0x1UL)     /*!< Read: Pending                                                        */
16612 
16613 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
16614   #define EGU_INTPEND_TRIGGERED10_Pos (10UL)         /*!< Position of TRIGGERED10 field.                                       */
16615   #define EGU_INTPEND_TRIGGERED10_Msk (0x1UL << EGU_INTPEND_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.               */
16616   #define EGU_INTPEND_TRIGGERED10_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED10 field.                           */
16617   #define EGU_INTPEND_TRIGGERED10_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED10 field.                           */
16618   #define EGU_INTPEND_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
16619   #define EGU_INTPEND_TRIGGERED10_Pending (0x1UL)    /*!< Read: Pending                                                        */
16620 
16621 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
16622   #define EGU_INTPEND_TRIGGERED11_Pos (11UL)         /*!< Position of TRIGGERED11 field.                                       */
16623   #define EGU_INTPEND_TRIGGERED11_Msk (0x1UL << EGU_INTPEND_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.               */
16624   #define EGU_INTPEND_TRIGGERED11_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED11 field.                           */
16625   #define EGU_INTPEND_TRIGGERED11_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED11 field.                           */
16626   #define EGU_INTPEND_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
16627   #define EGU_INTPEND_TRIGGERED11_Pending (0x1UL)    /*!< Read: Pending                                                        */
16628 
16629 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
16630   #define EGU_INTPEND_TRIGGERED12_Pos (12UL)         /*!< Position of TRIGGERED12 field.                                       */
16631   #define EGU_INTPEND_TRIGGERED12_Msk (0x1UL << EGU_INTPEND_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.               */
16632   #define EGU_INTPEND_TRIGGERED12_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED12 field.                           */
16633   #define EGU_INTPEND_TRIGGERED12_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED12 field.                           */
16634   #define EGU_INTPEND_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
16635   #define EGU_INTPEND_TRIGGERED12_Pending (0x1UL)    /*!< Read: Pending                                                        */
16636 
16637 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
16638   #define EGU_INTPEND_TRIGGERED13_Pos (13UL)         /*!< Position of TRIGGERED13 field.                                       */
16639   #define EGU_INTPEND_TRIGGERED13_Msk (0x1UL << EGU_INTPEND_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.               */
16640   #define EGU_INTPEND_TRIGGERED13_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED13 field.                           */
16641   #define EGU_INTPEND_TRIGGERED13_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED13 field.                           */
16642   #define EGU_INTPEND_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
16643   #define EGU_INTPEND_TRIGGERED13_Pending (0x1UL)    /*!< Read: Pending                                                        */
16644 
16645 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
16646   #define EGU_INTPEND_TRIGGERED14_Pos (14UL)         /*!< Position of TRIGGERED14 field.                                       */
16647   #define EGU_INTPEND_TRIGGERED14_Msk (0x1UL << EGU_INTPEND_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.               */
16648   #define EGU_INTPEND_TRIGGERED14_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED14 field.                           */
16649   #define EGU_INTPEND_TRIGGERED14_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED14 field.                           */
16650   #define EGU_INTPEND_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
16651   #define EGU_INTPEND_TRIGGERED14_Pending (0x1UL)    /*!< Read: Pending                                                        */
16652 
16653 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
16654   #define EGU_INTPEND_TRIGGERED15_Pos (15UL)         /*!< Position of TRIGGERED15 field.                                       */
16655   #define EGU_INTPEND_TRIGGERED15_Msk (0x1UL << EGU_INTPEND_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.               */
16656   #define EGU_INTPEND_TRIGGERED15_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED15 field.                           */
16657   #define EGU_INTPEND_TRIGGERED15_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED15 field.                           */
16658   #define EGU_INTPEND_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
16659   #define EGU_INTPEND_TRIGGERED15_Pending (0x1UL)    /*!< Read: Pending                                                        */
16660 
16661 
16662 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
16663 
16664 /* =========================================================================================================================== */
16665 /* ================                                            ETB                                            ================ */
16666 /* =========================================================================================================================== */
16667 
16668 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
16669 /* ======================================================= Struct ETB ======================================================== */
16670 /**
16671   * @brief Embedded Trace Buffer
16672   */
16673   typedef struct {                                   /*!< ETB Structure                                                        */
16674     __IM uint32_t RESERVED;
16675     __IM uint32_t RDP;                               /*!< (@ 0x00000004) ETB RAM Depth Register                                */
16676     __IM uint32_t RESERVED1;
16677     __IM uint32_t STS;                               /*!< (@ 0x0000000C) ETB Status Register                                   */
16678     __IM uint32_t RRD;                               /*!< (@ 0x00000010) ETB RAM Read Data Register                            */
16679     __IOM uint32_t RRP;                              /*!< (@ 0x00000014) ETB RAM Read Pointer Register                         */
16680     __IOM uint32_t RWP;                              /*!< (@ 0x00000018) ETB RAM Write Pointer Register                        */
16681     __IOM uint32_t TRG;                              /*!< (@ 0x0000001C) ETB Trigger Counter Register                          */
16682     __IOM uint32_t CTL;                              /*!< (@ 0x00000020) ETB Control Register                                  */
16683     __IOM uint32_t RWD;                              /*!< (@ 0x00000024) ETB RAM Write Data Register                           */
16684     __IM uint32_t RESERVED2[182];
16685     __IM uint32_t FFSR;                              /*!< (@ 0x00000300) ETB Formatter and Flush Status Register               */
16686     __IOM uint32_t FFCR;                             /*!< (@ 0x00000304) ETB Formatter and Flush Control Register              */
16687     __IM uint32_t RESERVED3[758];
16688     __OM uint32_t ITMISCOP0;                         /*!< (@ 0x00000EE0) Integration Test Miscellaneous Output Register 0      */
16689     __OM uint32_t ITTRFLINACK;                       /*!< (@ 0x00000EE4) Integration Test Trigger In and Flush In Acknowledge
16690                                                                          Register*/
16691     __IM uint32_t ITTRFLIN;                          /*!< (@ 0x00000EE8) Integration Test Trigger In and Flush In Register     */
16692     __IM uint32_t ITATBDATA0;                        /*!< (@ 0x00000EEC) Integration Test ATB Data Register 0                  */
16693     __OM uint32_t ITATBCTR2;                         /*!< (@ 0x00000EF0) Integration Test ATB Control Register 2               */
16694     __IM uint32_t ITATBCTR1;                         /*!< (@ 0x00000EF4) Integration Test ATB Control Register 1               */
16695     __IM uint32_t ITATBCTR0;                         /*!< (@ 0x00000EF8) Integration Test ATB Control Register 0               */
16696     __IM uint32_t RESERVED4;
16697     __IOM uint32_t ITCTRL;                           /*!< (@ 0x00000F00) Integration Mode Control Register                     */
16698     __IM uint32_t RESERVED5[39];
16699     __IOM uint32_t CLAIMSET;                         /*!< (@ 0x00000FA0) Claim Tag Set Register                                */
16700     __IOM uint32_t CLAIMCLR;                         /*!< (@ 0x00000FA4) Claim Tag Clear Register                              */
16701     __IM uint32_t RESERVED6[2];
16702     __OM uint32_t LAR;                               /*!< (@ 0x00000FB0) Lock Access Register                                  */
16703     __IM uint32_t LSR;                               /*!< (@ 0x00000FB4) Lock Status Register                                  */
16704     __IM uint32_t AUTHSTATUS;                        /*!< (@ 0x00000FB8) Authentication Status Register                        */
16705     __IM uint32_t RESERVED7[3];
16706     __IM uint32_t DEVID;                             /*!< (@ 0x00000FC8) Device Configuration Register                         */
16707     __IM uint32_t DEVTYPE;                           /*!< (@ 0x00000FCC) Device Type Identifier Register                       */
16708     __IM uint32_t PERIPHID4;                         /*!< (@ 0x00000FD0) Peripheral ID4 Register                               */
16709     __IM uint32_t RESERVED8[3];
16710     __IM uint32_t PERIPHID0;                         /*!< (@ 0x00000FE0) Peripheral ID0 Register                               */
16711     __IM uint32_t PERIPHID1;                         /*!< (@ 0x00000FE4) Peripheral ID1 Register                               */
16712     __IM uint32_t PERIPHID2;                         /*!< (@ 0x00000FE8) Peripheral ID2 Register                               */
16713     __IM uint32_t PERIPHID3;                         /*!< (@ 0x00000FEC) Peripheral ID3 Register                               */
16714     __IM uint32_t COMPID0;                           /*!< (@ 0x00000FF0) Component ID0 Register                                */
16715     __IM uint32_t COMPID1;                           /*!< (@ 0x00000FF4) Component ID1 Register                                */
16716     __IM uint32_t COMPID2;                           /*!< (@ 0x00000FF8) Component ID2 Register                                */
16717     __IM uint32_t COMPID3;                           /*!< (@ 0x00000FFC) Component ID3 Register                                */
16718   } NRF_ETB_Type;                                    /*!< Size = 4096 (0x1000)                                                 */
16719 
16720 /* ETB_RDP: ETB RAM Depth Register */
16721   #define ETB_RDP_ResetValue (0x00000000UL)          /*!< Reset value of RDP register.                                         */
16722 
16723 /* ETB_RAM_DEPTH @Bits 0..31 : Defines the depth, in words, of the trace RAM. */
16724   #define ETB_RDP_ETB_RAM_DEPTH_Pos (0UL)            /*!< Position of ETB_RAM_DEPTH field.                                     */
16725   #define ETB_RDP_ETB_RAM_DEPTH_Msk (0xFFFFFFFFUL << ETB_RDP_ETB_RAM_DEPTH_Pos) /*!< Bit mask of ETB_RAM_DEPTH field.          */
16726 
16727 
16728 /* ETB_STS: ETB Status Register */
16729   #define ETB_STS_ResetValue (0x00000008UL)          /*!< Reset value of STS register.                                         */
16730 
16731 /* FULL @Bit 0 : RAM Full. The flag indicates when the RAM write pointer has wrapped around. */
16732   #define ETB_STS_FULL_Pos (0UL)                     /*!< Position of FULL field.                                              */
16733   #define ETB_STS_FULL_Msk (0x1UL << ETB_STS_FULL_Pos) /*!< Bit mask of FULL field.                                            */
16734 
16735 /* TRIGGERED @Bit 1 : The Triggered bit is set when a trigger has been observed. This does not indicate that a trigger has been
16736                       embedded in the trace data by the formatter, but is determined by the programming of the Formatter and
16737                       Flush Control Register. */
16738 
16739   #define ETB_STS_TRIGGERED_Pos (1UL)                /*!< Position of TRIGGERED field.                                         */
16740   #define ETB_STS_TRIGGERED_Msk (0x1UL << ETB_STS_TRIGGERED_Pos) /*!< Bit mask of TRIGGERED field.                             */
16741 
16742 /* ACQCOMP @Bit 2 : The acquisition complete flag indicates that capture has been completed when the formatter stops because of
16743                     any of the methods defined in the Formatter and Flush Control Register, or TraceCaptEn = 0. This also
16744                     results in FtStopped in the Formatter and Flush Status Register going HIGH. */
16745 
16746   #define ETB_STS_ACQCOMP_Pos (2UL)                  /*!< Position of ACQCOMP field.                                           */
16747   #define ETB_STS_ACQCOMP_Msk (0x1UL << ETB_STS_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field.                                   */
16748 
16749 /* FTEMPTY @Bit 3 : Formatter pipeline empty. All data stored to RAM. */
16750   #define ETB_STS_FTEMPTY_Pos (3UL)                  /*!< Position of FTEMPTY field.                                           */
16751   #define ETB_STS_FTEMPTY_Msk (0x1UL << ETB_STS_FTEMPTY_Pos) /*!< Bit mask of FTEMPTY field.                                   */
16752 
16753 
16754 /* ETB_RRD: ETB RAM Read Data Register */
16755   #define ETB_RRD_ResetValue (0x00000000UL)          /*!< Reset value of RRD register.                                         */
16756 
16757 /* RAM_READ_DATA @Bits 0..31 : Data read from the ETB Trace RAM. */
16758   #define ETB_RRD_RAM_READ_DATA_Pos (0UL)            /*!< Position of RAM_READ_DATA field.                                     */
16759   #define ETB_RRD_RAM_READ_DATA_Msk (0xFFFFFFFFUL << ETB_RRD_RAM_READ_DATA_Pos) /*!< Bit mask of RAM_READ_DATA field.          */
16760 
16761 
16762 /* ETB_RRP: ETB RAM Read Pointer Register */
16763   #define ETB_RRP_ResetValue (0x00000000UL)          /*!< Reset value of RRP register.                                         */
16764 
16765 /* RAM_READ_POINTER @Bits 0..9 : Sets the read pointer used to read entries from the Trace RAM over the APB interface. */
16766   #define ETB_RRP_RAM_READ_POINTER_Pos (0UL)         /*!< Position of RAM_READ_POINTER field.                                  */
16767   #define ETB_RRP_RAM_READ_POINTER_Msk (0x3FFUL << ETB_RRP_RAM_READ_POINTER_Pos) /*!< Bit mask of RAM_READ_POINTER field.      */
16768 
16769 
16770 /* ETB_RWP: ETB RAM Write Pointer Register */
16771   #define ETB_RWP_ResetValue (0x00000000UL)          /*!< Reset value of RWP register.                                         */
16772 
16773 /* RAM_WRITE_POINTER @Bits 0..9 : Sets the write pointer used to write entries from the CoreSight bus into the Trace RAM. */
16774   #define ETB_RWP_RAM_WRITE_POINTER_Pos (0UL)        /*!< Position of RAM_WRITE_POINTER field.                                 */
16775   #define ETB_RWP_RAM_WRITE_POINTER_Msk (0x3FFUL << ETB_RWP_RAM_WRITE_POINTER_Pos) /*!< Bit mask of RAM_WRITE_POINTER field.   */
16776 
16777 
16778 /* ETB_TRG: ETB Trigger Counter Register */
16779   #define ETB_TRG_ResetValue (0x00000000UL)          /*!< Reset value of TRG register.                                         */
16780 
16781 /* TRIGGER_COUNTER @Bits 0..9 : The counter is used as follows:Trace after - The counter is set to a large value, slightly less
16782                                 than the number of entries in the RAM. Trace before - The counter is set to a small value. Trace
16783                                 about - The counter is set to half the depth of the Trace RAM. This register must not be written
16784                                 to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If a write is attempted, the
16785                                 register is not updated. A read access is permitted with trace capture enabled. */
16786 
16787   #define ETB_TRG_TRIGGER_COUNTER_Pos (0UL)          /*!< Position of TRIGGER_COUNTER field.                                   */
16788   #define ETB_TRG_TRIGGER_COUNTER_Msk (0x3FFUL << ETB_TRG_TRIGGER_COUNTER_Pos) /*!< Bit mask of TRIGGER_COUNTER field.         */
16789 
16790 
16791 /* ETB_CTL: ETB Control Register */
16792   #define ETB_CTL_ResetValue (0x00000000UL)          /*!< Reset value of CTL register.                                         */
16793 
16794 /* TRACECAPTEN @Bit 0 : ETB Trace Capture Enable. This is the master enable bit forcing FtStopped HIGH when TraceCaptEn is LOW.
16795                         When capture is disabled, any remaining data in the ATB formatter is stored to RAM. When all data is
16796                         stored the formatter outputs FtStopped. Capture is fully disabled, or complete, when FtStopped goes
16797                         HIGH. See ETB Formatter and Flush Status Register, FFSR, 0x300. */
16798 
16799   #define ETB_CTL_TRACECAPTEN_Pos (0UL)              /*!< Position of TRACECAPTEN field.                                       */
16800   #define ETB_CTL_TRACECAPTEN_Msk (0x1UL << ETB_CTL_TRACECAPTEN_Pos) /*!< Bit mask of TRACECAPTEN field.                       */
16801 
16802 
16803 /* ETB_RWD: ETB RAM Write Data Register */
16804   #define ETB_RWD_ResetValue (0x00000000UL)          /*!< Reset value of RWD register.                                         */
16805 
16806 /* RAM_WRITE_DATA @Bits 0..31 : Data written to the ETB Trace RAM. When trace capture is disabled, the contents of this register
16807                                 are placed into the ETB Trace RAM when this register is written to. Writing to this register
16808                                 increments the RAM Write Pointer Register. If trace capture is enabled, and this register is
16809                                 accessed, then a read from this register outputs 0xFFFFFFFF. Reads of this register never
16810                                 increment the RAM Write Pointer Register. A constant stream of 1s being output corresponds to a
16811                                 synchronization output from the ETB. If a write access is attempted, the data is not written
16812                                 into Trace RAM. */
16813 
16814   #define ETB_RWD_RAM_WRITE_DATA_Pos (0UL)           /*!< Position of RAM_WRITE_DATA field.                                    */
16815   #define ETB_RWD_RAM_WRITE_DATA_Msk (0xFFFFFFFFUL << ETB_RWD_RAM_WRITE_DATA_Pos) /*!< Bit mask of RAM_WRITE_DATA field.       */
16816 
16817 
16818 /* ETB_FFSR: ETB Formatter and Flush Status Register */
16819   #define ETB_FFSR_ResetValue (0x00000002UL)         /*!< Reset value of FFSR register.                                        */
16820 
16821 /* FLINPROG @Bit 0 : Flush In Progress. This is an indication of the current state of afvalids. */
16822   #define ETB_FFSR_FLINPROG_Pos (0UL)                /*!< Position of FLINPROG field.                                          */
16823   #define ETB_FFSR_FLINPROG_Msk (0x1UL << ETB_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field.                              */
16824 
16825 /* FTSTOPPED @Bit 1 : Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has
16826                       been output. Any more trace data on the ATB interface is ignored and atreadys goes HIGH. */
16827 
16828   #define ETB_FFSR_FTSTOPPED_Pos (1UL)               /*!< Position of FTSTOPPED field.                                         */
16829   #define ETB_FFSR_FTSTOPPED_Msk (0x1UL << ETB_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field.                           */
16830 
16831 
16832 /* ETB_FFCR: ETB Formatter and Flush Control Register */
16833   #define ETB_FFCR_ResetValue (0x00000000UL)         /*!< Reset value of FFCR register.                                        */
16834 
16835 /* ENFTC @Bit 0 : Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL,
16836                   where fitted. Can only be changed when FtStopped is HIGH. This bit is clear on reset. */
16837 
16838   #define ETB_FFCR_ENFTC_Pos (0UL)                   /*!< Position of ENFTC field.                                             */
16839   #define ETB_FFCR_ENFTC_Msk (0x1UL << ETB_FFCR_ENFTC_Pos) /*!< Bit mask of ENFTC field.                                       */
16840 
16841 /* ENFCONT @Bit 1 : Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. Can only be changed
16842                     when FtStopped is HIGH. This bit is clear on reset. */
16843 
16844   #define ETB_FFCR_ENFCONT_Pos (1UL)                 /*!< Position of ENFCONT field.                                           */
16845   #define ETB_FFCR_ENFCONT_Msk (0x1UL << ETB_FFCR_ENFCONT_Pos) /*!< Bit mask of ENFCONT field.                                 */
16846 
16847 /* FONFLIN @Bit 4 : Set this bit to enable use of the flushin connection. This is clear on reset. */
16848   #define ETB_FFCR_FONFLIN_Pos (4UL)                 /*!< Position of FONFLIN field.                                           */
16849   #define ETB_FFCR_FONFLIN_Msk (0x1UL << ETB_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field.                                 */
16850 
16851 /* FONTRIG @Bit 5 : Generate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event
16852                     occurs. This bit is clear on reset. A Trigger Event is defined as when the Trigger counter reaches zero
16853                     (where fitted) or, in the case of the trigger counter being zero (or not fitted), when trigin is HIGH. */
16854 
16855   #define ETB_FFCR_FONTRIG_Pos (5UL)                 /*!< Position of FONTRIG field.                                           */
16856   #define ETB_FFCR_FONTRIG_Msk (0x1UL << ETB_FFCR_FONTRIG_Pos) /*!< Bit mask of FONTRIG field.                                 */
16857 
16858 /* FONMAN @Bit 6 : Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. This bit
16859                    is clear on reset. */
16860 
16861   #define ETB_FFCR_FONMAN_Pos (6UL)                  /*!< Position of FONMAN field.                                            */
16862   #define ETB_FFCR_FONMAN_Msk (0x1UL << ETB_FFCR_FONMAN_Pos) /*!< Bit mask of FONMAN field.                                    */
16863 
16864 /* TRIGIN @Bit 8 : Indicate a trigger on trigin being asserted. */
16865   #define ETB_FFCR_TRIGIN_Pos (8UL)                  /*!< Position of TRIGIN field.                                            */
16866   #define ETB_FFCR_TRIGIN_Msk (0x1UL << ETB_FFCR_TRIGIN_Pos) /*!< Bit mask of TRIGIN field.                                    */
16867 
16868 /* TRIGEVT @Bit 9 : Indicate a trigger on a Trigger Event. */
16869   #define ETB_FFCR_TRIGEVT_Pos (9UL)                 /*!< Position of TRIGEVT field.                                           */
16870   #define ETB_FFCR_TRIGEVT_Msk (0x1UL << ETB_FFCR_TRIGEVT_Pos) /*!< Bit mask of TRIGEVT field.                                 */
16871 
16872 /* TRIGFL @Bit 10 : Indicates a trigger on Flush completion (afreadys being returned). */
16873   #define ETB_FFCR_TRIGFL_Pos (10UL)                 /*!< Position of TRIGFL field.                                            */
16874   #define ETB_FFCR_TRIGFL_Msk (0x1UL << ETB_FFCR_TRIGFL_Pos) /*!< Bit mask of TRIGFL field.                                    */
16875 
16876 /* STOPFL @Bit 12 : This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but
16877                     this is clear on reset (disabled). */
16878 
16879   #define ETB_FFCR_STOPFL_Pos (12UL)                 /*!< Position of STOPFL field.                                            */
16880   #define ETB_FFCR_STOPFL_Msk (0x1UL << ETB_FFCR_STOPFL_Pos) /*!< Bit mask of STOPFL field.                                    */
16881 
16882 /* STOPTRIG @Bit 13 : Stop the formatter after a Trigger Event is observed. Reset to disabled (zero). */
16883   #define ETB_FFCR_STOPTRIG_Pos (13UL)               /*!< Position of STOPTRIG field.                                          */
16884   #define ETB_FFCR_STOPTRIG_Msk (0x1UL << ETB_FFCR_STOPTRIG_Pos) /*!< Bit mask of STOPTRIG field.                              */
16885 
16886 
16887 /* ETB_ITMISCOP0: Integration Test Miscellaneous Output Register 0 */
16888   #define ETB_ITMISCOP0_ResetValue (0x00000000UL)    /*!< Reset value of ITMISCOP0 register.                                   */
16889 
16890 /* ACQCOMP @Bit 0 : Set the value of acqcomp. */
16891   #define ETB_ITMISCOP0_ACQCOMP_Pos (0UL)            /*!< Position of ACQCOMP field.                                           */
16892   #define ETB_ITMISCOP0_ACQCOMP_Msk (0x1UL << ETB_ITMISCOP0_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field.                       */
16893 
16894 /* FULL @Bit 1 : Set the value of full output port. */
16895   #define ETB_ITMISCOP0_FULL_Pos (1UL)               /*!< Position of FULL field.                                              */
16896   #define ETB_ITMISCOP0_FULL_Msk (0x1UL << ETB_ITMISCOP0_FULL_Pos) /*!< Bit mask of FULL field.                                */
16897 
16898 
16899 /* ETB_ITTRFLINACK: Integration Test Trigger In and Flush In Acknowledge Register */
16900   #define ETB_ITTRFLINACK_ResetValue (0x00000000UL)  /*!< Reset value of ITTRFLINACK register.                                 */
16901 
16902 /* TRIGINACK @Bit 0 : Set the value of triginack. */
16903   #define ETB_ITTRFLINACK_TRIGINACK_Pos (0UL)        /*!< Position of TRIGINACK field.                                         */
16904   #define ETB_ITTRFLINACK_TRIGINACK_Msk (0x1UL << ETB_ITTRFLINACK_TRIGINACK_Pos) /*!< Bit mask of TRIGINACK field.             */
16905 
16906 /* FLUSHINACK @Bit 1 : Set the value of flushinack. */
16907   #define ETB_ITTRFLINACK_FLUSHINACK_Pos (1UL)       /*!< Position of FLUSHINACK field.                                        */
16908   #define ETB_ITTRFLINACK_FLUSHINACK_Msk (0x1UL << ETB_ITTRFLINACK_FLUSHINACK_Pos) /*!< Bit mask of FLUSHINACK field.          */
16909 
16910 
16911 /* ETB_ITTRFLIN: Integration Test Trigger In and Flush In Register */
16912   #define ETB_ITTRFLIN_ResetValue (0x00000000UL)     /*!< Reset value of ITTRFLIN register.                                    */
16913 
16914 /* TRIGIN @Bit 0 : Read the value of trigin. */
16915   #define ETB_ITTRFLIN_TRIGIN_Pos (0UL)              /*!< Position of TRIGIN field.                                            */
16916   #define ETB_ITTRFLIN_TRIGIN_Msk (0x1UL << ETB_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field.                            */
16917 
16918 /* FLUSHIN @Bit 1 : Read the value of flushin. */
16919   #define ETB_ITTRFLIN_FLUSHIN_Pos (1UL)             /*!< Position of FLUSHIN field.                                           */
16920   #define ETB_ITTRFLIN_FLUSHIN_Msk (0x1UL << ETB_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field.                         */
16921 
16922 
16923 /* ETB_ITATBDATA0: Integration Test ATB Data Register 0 */
16924   #define ETB_ITATBDATA0_ResetValue (0x00000000UL)   /*!< Reset value of ITATBDATA0 register.                                  */
16925 
16926 /* ATDATA_0 @Bit 0 : Read the value of atdatas[0]. */
16927   #define ETB_ITATBDATA0_ATDATA_0_Pos (0UL)          /*!< Position of ATDATA_0 field.                                          */
16928   #define ETB_ITATBDATA0_ATDATA_0_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_0_Pos) /*!< Bit mask of ATDATA_0 field.                  */
16929 
16930 /* ATDATA_7 @Bit 1 : Read the value of atdatas[7]. */
16931   #define ETB_ITATBDATA0_ATDATA_7_Pos (1UL)          /*!< Position of ATDATA_7 field.                                          */
16932   #define ETB_ITATBDATA0_ATDATA_7_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_7_Pos) /*!< Bit mask of ATDATA_7 field.                  */
16933 
16934 /* ATDATA_15 @Bit 2 : Read the value of atdatas[15]. */
16935   #define ETB_ITATBDATA0_ATDATA_15_Pos (2UL)         /*!< Position of ATDATA_15 field.                                         */
16936   #define ETB_ITATBDATA0_ATDATA_15_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_15_Pos) /*!< Bit mask of ATDATA_15 field.               */
16937 
16938 /* ATDATA_23 @Bit 3 : Read the value of atdatas[23]. */
16939   #define ETB_ITATBDATA0_ATDATA_23_Pos (3UL)         /*!< Position of ATDATA_23 field.                                         */
16940   #define ETB_ITATBDATA0_ATDATA_23_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_23_Pos) /*!< Bit mask of ATDATA_23 field.               */
16941 
16942 /* ATDATA_31 @Bit 4 : Read the value of atdatas[31]. */
16943   #define ETB_ITATBDATA0_ATDATA_31_Pos (4UL)         /*!< Position of ATDATA_31 field.                                         */
16944   #define ETB_ITATBDATA0_ATDATA_31_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_31_Pos) /*!< Bit mask of ATDATA_31 field.               */
16945 
16946 
16947 /* ETB_ITATBCTR2: Integration Test ATB Control Register 2 */
16948   #define ETB_ITATBCTR2_ResetValue (0x00000000UL)    /*!< Reset value of ITATBCTR2 register.                                   */
16949 
16950 /* ATREADYS @Bit 0 : Set the value of atreadys. */
16951   #define ETB_ITATBCTR2_ATREADYS_Pos (0UL)           /*!< Position of ATREADYS field.                                          */
16952   #define ETB_ITATBCTR2_ATREADYS_Msk (0x1UL << ETB_ITATBCTR2_ATREADYS_Pos) /*!< Bit mask of ATREADYS field.                    */
16953 
16954 /* AFVALIDS @Bit 1 : Set the value of afvalids. */
16955   #define ETB_ITATBCTR2_AFVALIDS_Pos (1UL)           /*!< Position of AFVALIDS field.                                          */
16956   #define ETB_ITATBCTR2_AFVALIDS_Msk (0x1UL << ETB_ITATBCTR2_AFVALIDS_Pos) /*!< Bit mask of AFVALIDS field.                    */
16957 
16958 
16959 /* ETB_ITATBCTR1: Integration Test ATB Control Register 1 */
16960   #define ETB_ITATBCTR1_ResetValue (0x00000000UL)    /*!< Reset value of ITATBCTR1 register.                                   */
16961 
16962 /* ATID @Bits 0..6 : Read the value of atids. */
16963   #define ETB_ITATBCTR1_ATID_Pos (0UL)               /*!< Position of ATID field.                                              */
16964   #define ETB_ITATBCTR1_ATID_Msk (0x7FUL << ETB_ITATBCTR1_ATID_Pos) /*!< Bit mask of ATID field.                               */
16965 
16966 
16967 /* ETB_ITATBCTR0: Integration Test ATB Control Register 0 */
16968   #define ETB_ITATBCTR0_ResetValue (0x00000000UL)    /*!< Reset value of ITATBCTR0 register.                                   */
16969 
16970 /* ATVALID @Bit 0 : Read the value of atvalids. */
16971   #define ETB_ITATBCTR0_ATVALID_Pos (0UL)            /*!< Position of ATVALID field.                                           */
16972   #define ETB_ITATBCTR0_ATVALID_Msk (0x1UL << ETB_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field.                       */
16973 
16974 /* AFREADY @Bit 1 : Read the value of afreadys. */
16975   #define ETB_ITATBCTR0_AFREADY_Pos (1UL)            /*!< Position of AFREADY field.                                           */
16976   #define ETB_ITATBCTR0_AFREADY_Msk (0x1UL << ETB_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field.                       */
16977 
16978 /* ATBYTES @Bits 8..9 : Read the value of atbytess. */
16979   #define ETB_ITATBCTR0_ATBYTES_Pos (8UL)            /*!< Position of ATBYTES field.                                           */
16980   #define ETB_ITATBCTR0_ATBYTES_Msk (0x3UL << ETB_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field.                       */
16981 
16982 
16983 /* ETB_ITCTRL: Integration Mode Control Register */
16984   #define ETB_ITCTRL_ResetValue (0x00000000UL)       /*!< Reset value of ITCTRL register.                                      */
16985 
16986 /* INTEGRATION_MODE @Bit 0 : Allows the component to switch from functional mode to integration mode or back. */
16987   #define ETB_ITCTRL_INTEGRATION_MODE_Pos (0UL)      /*!< Position of INTEGRATION_MODE field.                                  */
16988   #define ETB_ITCTRL_INTEGRATION_MODE_Msk (0x1UL << ETB_ITCTRL_INTEGRATION_MODE_Pos) /*!< Bit mask of INTEGRATION_MODE field.  */
16989 
16990 
16991 /* ETB_CLAIMSET: Claim Tag Set Register */
16992   #define ETB_CLAIMSET_ResetValue (0x0000000FUL)     /*!< Reset value of CLAIMSET register.                                    */
16993 
16994 /* CLAIMSET @Bits 0..3 : This claim tag bit is implemented */
16995   #define ETB_CLAIMSET_CLAIMSET_Pos (0UL)            /*!< Position of CLAIMSET field.                                          */
16996   #define ETB_CLAIMSET_CLAIMSET_Msk (0xFUL << ETB_CLAIMSET_CLAIMSET_Pos) /*!< Bit mask of CLAIMSET field.                      */
16997 
16998 
16999 /* ETB_CLAIMCLR: Claim Tag Clear Register */
17000   #define ETB_CLAIMCLR_ResetValue (0x00000000UL)     /*!< Reset value of CLAIMCLR register.                                    */
17001 
17002 /* CLAIMCLR @Bits 0..3 : The value present reflects the current setting of the Claim Tag. */
17003   #define ETB_CLAIMCLR_CLAIMCLR_Pos (0UL)            /*!< Position of CLAIMCLR field.                                          */
17004   #define ETB_CLAIMCLR_CLAIMCLR_Msk (0xFUL << ETB_CLAIMCLR_CLAIMCLR_Pos) /*!< Bit mask of CLAIMCLR field.                      */
17005 
17006 
17007 /* ETB_LAR: Lock Access Register */
17008   #define ETB_LAR_ResetValue (0x00000000UL)          /*!< Reset value of LAR register.                                         */
17009 
17010 /* ACCESS_W @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than
17011                           0xC5ACCE55 will have the affect of removing write access. */
17012 
17013   #define ETB_LAR_ACCESS_W_Pos (0UL)                 /*!< Position of ACCESS_W field.                                          */
17014   #define ETB_LAR_ACCESS_W_Msk (0xFFFFFFFFUL << ETB_LAR_ACCESS_W_Pos) /*!< Bit mask of ACCESS_W field.                         */
17015 
17016 
17017 /* ETB_LSR: Lock Status Register */
17018   #define ETB_LSR_ResetValue (0x00000003UL)          /*!< Reset value of LSR register.                                         */
17019 
17020 /* LOCKEXIST @Bit 0 : Indicates that a lock control mechanism exists for this device. This bit reads as 0 when read from an
17021                       external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers. */
17022 
17023   #define ETB_LSR_LOCKEXIST_Pos (0UL)                /*!< Position of LOCKEXIST field.                                         */
17024   #define ETB_LSR_LOCKEXIST_Msk (0x1UL << ETB_LSR_LOCKEXIST_Pos) /*!< Bit mask of LOCKEXIST field.                             */
17025 
17026 /* LOCKGRANT @Bit 1 : Returns the current status of the Lock. This bit reads as 0 when read from an external debugger
17027                       (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers. */
17028 
17029   #define ETB_LSR_LOCKGRANT_Pos (1UL)                /*!< Position of LOCKGRANT field.                                         */
17030   #define ETB_LSR_LOCKGRANT_Msk (0x1UL << ETB_LSR_LOCKGRANT_Pos) /*!< Bit mask of LOCKGRANT field.                             */
17031 
17032 /* LOCKTYPE @Bit 2 : Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit */
17033   #define ETB_LSR_LOCKTYPE_Pos (2UL)                 /*!< Position of LOCKTYPE field.                                          */
17034   #define ETB_LSR_LOCKTYPE_Msk (0x1UL << ETB_LSR_LOCKTYPE_Pos) /*!< Bit mask of LOCKTYPE field.                                */
17035 
17036 
17037 /* ETB_AUTHSTATUS: Authentication Status Register */
17038   #define ETB_AUTHSTATUS_ResetValue (0x00000000UL)   /*!< Reset value of AUTHSTATUS register.                                  */
17039 
17040 /* NSID @Bits 0..1 : Indicates the security level for non-secure invasive debug */
17041   #define ETB_AUTHSTATUS_NSID_Pos (0UL)              /*!< Position of NSID field.                                              */
17042   #define ETB_AUTHSTATUS_NSID_Msk (0x3UL << ETB_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field.                              */
17043 
17044 /* NSNID @Bits 2..3 : Indicates the security level for non-secure non-invasive debug */
17045   #define ETB_AUTHSTATUS_NSNID_Pos (2UL)             /*!< Position of NSNID field.                                             */
17046   #define ETB_AUTHSTATUS_NSNID_Msk (0x3UL << ETB_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field.                           */
17047 
17048 /* SID @Bits 4..5 : Indicates the security level for secure invasive debug */
17049   #define ETB_AUTHSTATUS_SID_Pos (4UL)               /*!< Position of SID field.                                               */
17050   #define ETB_AUTHSTATUS_SID_Msk (0x3UL << ETB_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field.                                 */
17051 
17052 /* SNID @Bits 6..7 : Indicates the security level for secure non-invasive debug */
17053   #define ETB_AUTHSTATUS_SNID_Pos (6UL)              /*!< Position of SNID field.                                              */
17054   #define ETB_AUTHSTATUS_SNID_Msk (0x3UL << ETB_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field.                              */
17055 
17056 
17057 /* ETB_DEVID: Device Configuration Register */
17058   #define ETB_DEVID_ResetValue (0x00000000UL)        /*!< Reset value of DEVID register.                                       */
17059 
17060 /* EXTMUXNUM @Bits 0..4 : When non-zero this value indicates the type/number of ATB multiplexing present on the input to the
17061                           ATB. */
17062 
17063   #define ETB_DEVID_EXTMUXNUM_Pos (0UL)              /*!< Position of EXTMUXNUM field.                                         */
17064   #define ETB_DEVID_EXTMUXNUM_Msk (0x1FUL << ETB_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field.                        */
17065 
17066 /* RAMCLK @Bit 5 : This bit returns 0 on reads indicating that the ETB RAM operates synchronously to atclk. */
17067   #define ETB_DEVID_RAMCLK_Pos (5UL)                 /*!< Position of RAMCLK field.                                            */
17068   #define ETB_DEVID_RAMCLK_Msk (0x1UL << ETB_DEVID_RAMCLK_Pos) /*!< Bit mask of RAMCLK field.                                  */
17069 
17070 
17071 /* ETB_DEVTYPE: Device Type Identifier Register */
17072   #define ETB_DEVTYPE_ResetValue (0x00000021UL)      /*!< Reset value of DEVTYPE register.                                     */
17073 
17074 /* MAJOR_TYPE @Bits 0..3 : Major classification grouping for this debug/trace component */
17075   #define ETB_DEVTYPE_MAJOR_TYPE_Pos (0UL)           /*!< Position of MAJOR_TYPE field.                                        */
17076   #define ETB_DEVTYPE_MAJOR_TYPE_Msk (0xFUL << ETB_DEVTYPE_MAJOR_TYPE_Pos) /*!< Bit mask of MAJOR_TYPE field.                  */
17077 
17078 /* SUB_TYPE @Bits 4..7 : Sub-classification within the major category */
17079   #define ETB_DEVTYPE_SUB_TYPE_Pos (4UL)             /*!< Position of SUB_TYPE field.                                          */
17080   #define ETB_DEVTYPE_SUB_TYPE_Msk (0xFUL << ETB_DEVTYPE_SUB_TYPE_Pos) /*!< Bit mask of SUB_TYPE field.                        */
17081 
17082 
17083 /* ETB_PERIPHID4: Peripheral ID4 Register */
17084   #define ETB_PERIPHID4_ResetValue (0x00000004UL)    /*!< Reset value of PERIPHID4 register.                                   */
17085 
17086 /* DES_2 @Bits 0..3 : JEDEC continuation code indicating the designer of the component (along with the identity code) */
17087   #define ETB_PERIPHID4_DES_2_Pos (0UL)              /*!< Position of DES_2 field.                                             */
17088   #define ETB_PERIPHID4_DES_2_Msk (0xFUL << ETB_PERIPHID4_DES_2_Pos) /*!< Bit mask of DES_2 field.                             */
17089 
17090 /* SIZE @Bits 4..7 : This is a 4-bit value that indicates the total contiguous size of the memory window used by this component
17091                      in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read
17092                      as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. */
17093 
17094   #define ETB_PERIPHID4_SIZE_Pos (4UL)               /*!< Position of SIZE field.                                              */
17095   #define ETB_PERIPHID4_SIZE_Msk (0xFUL << ETB_PERIPHID4_SIZE_Pos) /*!< Bit mask of SIZE field.                                */
17096 
17097 
17098 /* ETB_PERIPHID0: Peripheral ID0 Register */
17099   #define ETB_PERIPHID0_ResetValue (0x00000007UL)    /*!< Reset value of PERIPHID0 register.                                   */
17100 
17101 /* PART_0 @Bits 0..7 : Bits [7:0] of the component's part number. This is selected by the designer of the component. */
17102   #define ETB_PERIPHID0_PART_0_Pos (0UL)             /*!< Position of PART_0 field.                                            */
17103   #define ETB_PERIPHID0_PART_0_Msk (0xFFUL << ETB_PERIPHID0_PART_0_Pos) /*!< Bit mask of PART_0 field.                         */
17104 
17105 
17106 /* ETB_PERIPHID1: Peripheral ID1 Register */
17107   #define ETB_PERIPHID1_ResetValue (0x000000B9UL)    /*!< Reset value of PERIPHID1 register.                                   */
17108 
17109 /* PART_1 @Bits 0..3 : Bits [11:8] of the component's part number. This is selected by the designer of the component. */
17110   #define ETB_PERIPHID1_PART_1_Pos (0UL)             /*!< Position of PART_1 field.                                            */
17111   #define ETB_PERIPHID1_PART_1_Msk (0xFUL << ETB_PERIPHID1_PART_1_Pos) /*!< Bit mask of PART_1 field.                          */
17112 
17113 /* DES_0 @Bits 4..7 : Bits 3:0 of the JEDEC identity code indicating the designer of the component (along with the continuation
17114                       code) */
17115 
17116   #define ETB_PERIPHID1_DES_0_Pos (4UL)              /*!< Position of DES_0 field.                                             */
17117   #define ETB_PERIPHID1_DES_0_Msk (0xFUL << ETB_PERIPHID1_DES_0_Pos) /*!< Bit mask of DES_0 field.                             */
17118 
17119 
17120 /* ETB_PERIPHID2: Peripheral ID2 Register */
17121   #define ETB_PERIPHID2_ResetValue (0x0000004BUL)    /*!< Reset value of PERIPHID2 register.                                   */
17122 
17123 /* DES_1 @Bits 0..2 : Bits 6:4 of the JEDEC identity code indicating the designer of the component (along with the continuation
17124                       code) */
17125 
17126   #define ETB_PERIPHID2_DES_1_Pos (0UL)              /*!< Position of DES_1 field.                                             */
17127   #define ETB_PERIPHID2_DES_1_Msk (0x7UL << ETB_PERIPHID2_DES_1_Pos) /*!< Bit mask of DES_1 field.                             */
17128 
17129 /* JEDEC @Bit 3 : Always set. Indicates that a JEDEC assigned value is used */
17130   #define ETB_PERIPHID2_JEDEC_Pos (3UL)              /*!< Position of JEDEC field.                                             */
17131   #define ETB_PERIPHID2_JEDEC_Msk (0x1UL << ETB_PERIPHID2_JEDEC_Pos) /*!< Bit mask of JEDEC field.                             */
17132 
17133 /* REVISION @Bits 4..7 : The Revision field is an incremental value starting at 0x0 for the first design of this component. This
17134                          only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the
17135                          exact major/minor revision. */
17136 
17137   #define ETB_PERIPHID2_REVISION_Pos (4UL)           /*!< Position of REVISION field.                                          */
17138   #define ETB_PERIPHID2_REVISION_Msk (0xFUL << ETB_PERIPHID2_REVISION_Pos) /*!< Bit mask of REVISION field.                    */
17139 
17140 
17141 /* ETB_PERIPHID3: Peripheral ID3 Register */
17142   #define ETB_PERIPHID3_ResetValue (0x00000000UL)    /*!< Reset value of PERIPHID3 register.                                   */
17143 
17144 /* CMOD @Bits 0..3 : Where the component is reusable IP, this value indicates if the customer has modified the behavior of the
17145                      component. In most cases this field is zero. */
17146 
17147   #define ETB_PERIPHID3_CMOD_Pos (0UL)               /*!< Position of CMOD field.                                              */
17148   #define ETB_PERIPHID3_CMOD_Msk (0xFUL << ETB_PERIPHID3_CMOD_Pos) /*!< Bit mask of CMOD field.                                */
17149 
17150 /* REVAND @Bits 4..7 : This field indicates minor errata fixes specific to this design, for example metal fixes after
17151                        implementation. In most cases this field is zero. It is recommended that component designers ensure this
17152                        field can be changed by a metal fix if required, for example by driving it from registers that reset to
17153                        zero. */
17154 
17155   #define ETB_PERIPHID3_REVAND_Pos (4UL)             /*!< Position of REVAND field.                                            */
17156   #define ETB_PERIPHID3_REVAND_Msk (0xFUL << ETB_PERIPHID3_REVAND_Pos) /*!< Bit mask of REVAND field.                          */
17157 
17158 
17159 /* ETB_COMPID0: Component ID0 Register */
17160   #define ETB_COMPID0_ResetValue (0x0000000DUL)      /*!< Reset value of COMPID0 register.                                     */
17161 
17162 /* PRMBL_0 @Bits 0..7 : Contains bits [7:0] of the component identification */
17163   #define ETB_COMPID0_PRMBL_0_Pos (0UL)              /*!< Position of PRMBL_0 field.                                           */
17164   #define ETB_COMPID0_PRMBL_0_Msk (0xFFUL << ETB_COMPID0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field.                          */
17165 
17166 
17167 /* ETB_COMPID1: Component ID1 Register */
17168   #define ETB_COMPID1_ResetValue (0x00000090UL)      /*!< Reset value of COMPID1 register.                                     */
17169 
17170 /* PRMBL_1 @Bits 0..3 : Contains bits [11:8] of the component identification */
17171   #define ETB_COMPID1_PRMBL_1_Pos (0UL)              /*!< Position of PRMBL_1 field.                                           */
17172   #define ETB_COMPID1_PRMBL_1_Msk (0xFUL << ETB_COMPID1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field.                           */
17173 
17174 /* CLASS @Bits 4..7 : Class of the component. E. g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the
17175                       component identification. */
17176 
17177   #define ETB_COMPID1_CLASS_Pos (4UL)                /*!< Position of CLASS field.                                             */
17178   #define ETB_COMPID1_CLASS_Msk (0xFUL << ETB_COMPID1_CLASS_Pos) /*!< Bit mask of CLASS field.                                 */
17179 
17180 
17181 /* ETB_COMPID2: Component ID2 Register */
17182   #define ETB_COMPID2_ResetValue (0x00000005UL)      /*!< Reset value of COMPID2 register.                                     */
17183 
17184 /* PRMBL_2 @Bits 0..7 : Contains bits [23:16] of the component identification */
17185   #define ETB_COMPID2_PRMBL_2_Pos (0UL)              /*!< Position of PRMBL_2 field.                                           */
17186   #define ETB_COMPID2_PRMBL_2_Msk (0xFFUL << ETB_COMPID2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field.                          */
17187 
17188 
17189 /* ETB_COMPID3: Component ID3 Register */
17190   #define ETB_COMPID3_ResetValue (0x000000B1UL)      /*!< Reset value of COMPID3 register.                                     */
17191 
17192 /* PRMBL_3 @Bits 0..7 : Contains bits [31:24] of the component identification */
17193   #define ETB_COMPID3_PRMBL_3_Pos (0UL)              /*!< Position of PRMBL_3 field.                                           */
17194   #define ETB_COMPID3_PRMBL_3_Msk (0xFFUL << ETB_COMPID3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field.                          */
17195 
17196 
17197 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
17198 
17199 /* =========================================================================================================================== */
17200 /* ================                                            ETM                                            ================ */
17201 /* =========================================================================================================================== */
17202 
17203 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
17204 /* ======================================================= Struct ETM ======================================================== */
17205 /**
17206   * @brief Embedded Trace Macrocell
17207   */
17208   typedef struct {                                   /*!< ETM Structure                                                        */
17209     __IM uint32_t RESERVED;
17210     __IOM uint32_t TRCPRGCTLR;                       /*!< (@ 0x00000004) Enables the trace unit.                               */
17211     __IOM uint32_t TRCPROCSELR;                      /*!< (@ 0x00000008) Controls which PE to trace. Might ignore writes when
17212                                                                          the trace unit is enabled or not idle. Before writing
17213                                                                          to this register, ensure that TRCSTATR.IDLE == 1 so
17214                                                                          that the trace unit can synchronize with the chosen PE.
17215                                                                          Implemented if TRCIDR3.NUMPROC is greater than zero.*/
17216     __IOM uint32_t TRCSTATR;                         /*!< (@ 0x0000000C) Idle status bit                                       */
17217     __IOM uint32_t TRCCONFIGR;                       /*!< (@ 0x00000010) Controls the tracing options This register must always
17218                                                                          be programmed as part of trace unit initialization.
17219                                                                          Might ignore writes when the trace unit is enabled or
17220                                                                          not idle.*/
17221     __IM uint32_t RESERVED1[3];
17222     __IOM uint32_t TRCEVENTCTL0R;                    /*!< (@ 0x00000020) Controls the tracing of arbitrary events. If the
17223                                                                          selected event occurs a trace element is generated in
17224                                                                          the trace stream according to the settings in
17225                                                                          TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN.*/
17226     __IOM uint32_t TRCEVENTCTL1R;                    /*!< (@ 0x00000024) Controls the behavior of the events that TRCEVENTCTL0R
17227                                                                          selects. This register must always be programmed as
17228                                                                          part of trace unit initialization. Might ignore writes
17229                                                                          when the trace unit is enabled or not idle.*/
17230     __IM uint32_t RESERVED2;
17231     __IOM uint32_t TRCSTALLCTLR;                     /*!< (@ 0x0000002C) Enables trace unit functionality that prevents trace
17232                                                                          unit buffer overflows. Might ignore writes when the
17233                                                                          trace unit is enabled or not idle. Must be programmed
17234                                                                          if TRCIDR3.STALLCTL == 1.*/
17235     __IOM uint32_t TRCTSCTLR;                        /*!< (@ 0x00000030) Controls the insertion of global timestamps in the
17236                                                                          trace streams. When the selected event is triggered,
17237                                                                          the trace unit inserts a global timestamp into the
17238                                                                          trace streams. Might ignore writes when the trace unit
17239                                                                          is enabled or not idle. Must be programmed if
17240                                                                          TRCCONFIGR.TS == 1.*/
17241     __IOM uint32_t TRCSYNCPR;                        /*!< (@ 0x00000034) Controls how often trace synchronization requests
17242                                                                          occur. Might ignore writes when the trace unit is
17243                                                                          enabled or not idle. If writes are permitted then the
17244                                                                          register must be programmed.*/
17245     __IOM uint32_t TRCCCCTLR;                        /*!< (@ 0x00000038) Sets the threshold value for cycle counting. Might
17246                                                                          ignore writes when the trace unit is enabled or not
17247                                                                          idle. Must be programmed if TRCCONFIGR.CCI==1.*/
17248     __IOM uint32_t TRCBBCTLR;                        /*!< (@ 0x0000003C) Controls which regions in the memory map are enabled to
17249                                                                          use branch broadcasting. Might ignore writes when the
17250                                                                          trace unit is enabled or not idle. Must be programmed
17251                                                                          if TRCCONFIGR.BB == 1.*/
17252     __IOM uint32_t TRCTRACEIDR;                      /*!< (@ 0x00000040) Sets the trace ID for instruction trace. If data trace
17253                                                                          is enabled then it also sets the trace ID for data
17254                                                                          trace, to (trace ID for instruction trace) + 1. This
17255                                                                          register must always be programmed as part of trace
17256                                                                          unit initialization. Might ignore writes when the trace
17257                                                                          unit is enabled or not idle.*/
17258     __IOM uint32_t TRCQCTLR;                         /*!< (@ 0x00000044) Controls when Q elements are enabled. Might ignore
17259                                                                          writes when the trace unit is enabled or not idle. This
17260                                                                          register must be programmed if it is implemented and
17261                                                                          TRCCONFIGR.QE is set to any value other than 0b00.*/
17262     __IM uint32_t RESERVED3[14];
17263     __IOM uint32_t TRCVICTLR;                        /*!< (@ 0x00000080) Controls instruction trace filtering. Might ignore
17264                                                                          writes when the trace unit is enabled or not idle. Only
17265                                                                          returns stable data when TRCSTATR.PMSTABLE == 1. Must
17266                                                                          be programmed, particularly to set the value of the
17267                                                                          SSSTATUS bit, which sets the state of the start/stop
17268                                                                          logic.*/
17269     __IOM uint32_t TRCVIIECTLR;                      /*!< (@ 0x00000084) ViewInst exclude control. Might ignore writes when the
17270                                                                          trace unit is enabled or not idle. This register must
17271                                                                          be programmed when one or more address comparators are
17272                                                                          implemented.*/
17273     __IOM uint32_t TRCVISSCTLR;                      /*!< (@ 0x00000088) Use this to set, or read, the single address
17274                                                                          comparators that control the ViewInst start/stop logic.
17275                                                                          The start/stop logic is active for an instruction which
17276                                                                          causes a start and remains active up to and including
17277                                                                          an instruction which causes a stop, and then the
17278                                                                          start/stop logic becomes inactive. Might ignore writes
17279                                                                          when the trace unit is enabled or not idle. If
17280                                                                          implemented then this register must be programmed.*/
17281     __IOM uint32_t TRCVIPCSSCTLR;                    /*!< (@ 0x0000008C) Use this to set, or read, which PE comparator inputs
17282                                                                          can control the ViewInst start/stop logic. Might ignore
17283                                                                          writes when the trace unit is enabled or not idle. If
17284                                                                          implemented then this register must be programmed.*/
17285     __IM uint32_t RESERVED4[4];
17286     __IOM uint32_t TRCVDCTLR;                        /*!< (@ 0x000000A0) Controls data trace filtering. Might ignore writes when
17287                                                                          the trace unit is enabled or not idle. This register
17288                                                                          must be programmed when data tracing is enabled, that
17289                                                                          is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV ==
17290                                                                          1.*/
17291     __IOM uint32_t TRCVDSACCTLR;                     /*!< (@ 0x000000A4) ViewData include / exclude control. Might ignore writes
17292                                                                          when the trace unit is enabled or not idle. This
17293                                                                          register must be programmed when one or more address
17294                                                                          comparators are implemented.*/
17295     __IOM uint32_t TRCVDARCCTLR;                     /*!< (@ 0x000000A8) ViewData include / exclude control. Might ignore writes
17296                                                                          when the trace unit is enabled or not idle. This
17297                                                                          register must be programmed when one or more address
17298                                                                          comparators are implemented.*/
17299     __IM uint32_t RESERVED5[21];
17300     __IOM uint32_t TRCSEQEVR[3];                     /*!< (@ 0x00000100) Moves the sequencer state according to programmed
17301                                                                          events. Might ignore writes when the trace unit is
17302                                                                          enabled or not idle. When the sequencer is used, all
17303                                                                          sequencer state transitions must be programmed with a
17304                                                                          valid event.*/
17305     __IM uint32_t RESERVED6[3];
17306     __IOM uint32_t TRCSEQRSTEVR;                     /*!< (@ 0x00000118) Moves the sequencer to state 0 when a programmed event
17307                                                                          occurs. Might ignore writes when the trace unit is
17308                                                                          enabled or not idle. When the sequencer is used, all
17309                                                                          sequencer state transitions must be programmed with a
17310                                                                          valid event.*/
17311     __IOM uint32_t TRCSEQSTR;                        /*!< (@ 0x0000011C) Use this to set, or read, the sequencer state. Might
17312                                                                          ignore writes when the trace unit is enabled or not
17313                                                                          idle. Only returns stable data when TRCSTATR.PMSTABLE
17314                                                                          == 1. When the sequencer is used, all sequencer state
17315                                                                          transitions must be programmed with a valid event.*/
17316     __IOM uint32_t TRCEXTINSELR;                     /*!< (@ 0x00000120) Use this to set, or read, which external inputs are
17317                                                                          resources to the trace unit. Might ignore writes when
17318                                                                          the trace unit is enabled or not idle. Only returns
17319                                                                          stable data when TRCSTATR.PMSTABLE == 1. When the
17320                                                                          sequencer is used, all sequencer state transitions must
17321                                                                          be programmed with a valid event.*/
17322     __IM uint32_t RESERVED7[7];
17323     __IOM uint32_t TRCCNTRLDVR[4];                   /*!< (@ 0x00000140) This sets or returns the reload count value for counter
17324                                                                          n. Might ignore writes when the trace unit is enabled
17325                                                                          or not idle.*/
17326     __IOM uint32_t TRCCNTCTLR[4];                    /*!< (@ 0x00000150) Controls the operation of counter n. Might ignore
17327                                                                          writes when the trace unit is enabled or not idle.*/
17328     __IOM uint32_t TRCCNTVR[4];                      /*!< (@ 0x00000160) This sets or returns the value of counter n. The count
17329                                                                          value is only stable when TRCSTATR.PMSTABLE == 1. If
17330                                                                          software uses counter n then it must write to this
17331                                                                          register to set the initial counter value. Might ignore
17332                                                                          writes when the trace unit is enabled or not idle.*/
17333     __IM uint32_t RESERVED8[36];
17334     __IOM uint32_t TRCRSCTLR[32];                    /*!< (@ 0x00000200) Controls the selection of the resources in the trace
17335                                                                          unit. Might ignore writes when the trace unit is
17336                                                                          enabled or not idle. If software selects a
17337                                                                          non-implemented resource then CONSTRAINED UNPREDICTABLE
17338                                                                          behavior of the resource selector occurs, so the
17339                                                                          resource selector might fire unexpectedly or might not
17340                                                                          fire. Reads of the TRCRSCTLRn might return UNKNOWN.*/
17341     __IOM uint32_t TRCSSCCR0;                        /*!< (@ 0x00000280) Controls the single-shot comparator.                  */
17342     __IM uint32_t RESERVED9[7];
17343     __IOM uint32_t TRCSSCSR0;                        /*!< (@ 0x000002A0) Indicates the status of the single-shot comparators.
17344                                                                          TRCSSCSR0 is sensitive toinstruction addresses.*/
17345     __IM uint32_t RESERVED10[7];
17346     __IOM uint32_t TRCSSPCICR0;                      /*!< (@ 0x000002C0) Selects the processor comparator inputs for Single-shot
17347                                                                          control.*/
17348     __IM uint32_t RESERVED11[19];
17349     __IOM uint32_t TRCPDCR;                          /*!< (@ 0x00000310) Controls the single-shot comparator.                  */
17350     __IOM uint32_t TRCPDSR;                          /*!< (@ 0x00000314) Indicates the power down status of the ETM.           */
17351     __IM uint32_t RESERVED12[755];
17352     __IOM uint32_t TRCITATBIDR;                      /*!< (@ 0x00000EE4) Sets the state of output pins.                        */
17353     __IM uint32_t RESERVED13[3];
17354     __IOM uint32_t TRCITIATBINR;                     /*!< (@ 0x00000EF4) Reads the state of the input pins.                    */
17355     __IM uint32_t RESERVED14;
17356     __IOM uint32_t TRCITIATBOUTR;                    /*!< (@ 0x00000EFC) Sets the state of the output pins.                    */
17357     __IOM uint32_t TRCITCTRL;                        /*!< (@ 0x00000F00) Enables topology detection or integration testing, by
17358                                                                          putting ETM-M33 into integration mode.*/
17359     __IM uint32_t RESERVED15[39];
17360     __IOM uint32_t TRCCLAIMSET;                      /*!< (@ 0x00000FA0) Sets bits in the claim tag and determines the number of
17361                                                                          claim tag bits implemented.*/
17362     __IOM uint32_t TRCCLAIMCLR;                      /*!< (@ 0x00000FA4) Clears bits in the claim tag and determines the current
17363                                                                          value of the claim tag.*/
17364     __IM uint32_t RESERVED16[4];
17365     __IOM uint32_t TRCAUTHSTATUS;                    /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the
17366                                                                          system*/
17367     __IM uint32_t TRCDEVARCH;                        /*!< (@ 0x00000FBC) The TRCDEVARCH identifies ETM-M33 as an ETMv4.2
17368                                                                          component*/
17369     __IM uint32_t RESERVED17[3];
17370     __IM uint32_t TRCDEVTYPE;                        /*!< (@ 0x00000FCC) Controls the single-shot comparator.                  */
17371     __IOM uint32_t TRCPIDR[8];                       /*!< (@ 0x00000FD0) Coresight peripheral identification registers.        */
17372     __IOM uint32_t TRCCIDR[4];                       /*!< (@ 0x00000FF0) Coresight component identification registers.         */
17373   } NRF_ETM_Type;                                    /*!< Size = 4096 (0x1000)                                                 */
17374 
17375 /* ETM_TRCPRGCTLR: Enables the trace unit. */
17376   #define ETM_TRCPRGCTLR_ResetValue (0x00000000UL)   /*!< Reset value of TRCPRGCTLR register.                                  */
17377 
17378 /* EN @Bit 0 : Trace unit enable bit */
17379   #define ETM_TRCPRGCTLR_EN_Pos (0UL)                /*!< Position of EN field.                                                */
17380   #define ETM_TRCPRGCTLR_EN_Msk (0x1UL << ETM_TRCPRGCTLR_EN_Pos) /*!< Bit mask of EN field.                                    */
17381   #define ETM_TRCPRGCTLR_EN_Min (0x0UL)              /*!< Min enumerator value of EN field.                                    */
17382   #define ETM_TRCPRGCTLR_EN_Max (0x1UL)              /*!< Max enumerator value of EN field.                                    */
17383   #define ETM_TRCPRGCTLR_EN_Disabled (0x0UL)         /*!< The trace unit is disabled. All trace resources are inactive and no
17384                                                           trace is generated.*/
17385   #define ETM_TRCPRGCTLR_EN_Enabled (0x1UL)          /*!< The trace unit is enabled.                                           */
17386 
17387 
17388 /* ETM_TRCPROCSELR: Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing
17389                      to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE.
17390                      Implemented if TRCIDR3.NUMPROC is greater than zero. */
17391 
17392   #define ETM_TRCPROCSELR_ResetValue (0x00000000UL)  /*!< Reset value of TRCPROCSELR register.                                 */
17393 
17394 /* PROCSEL @Bits 0..4 : PE select bits that select the PE to trace. */
17395   #define ETM_TRCPROCSELR_PROCSEL_Pos (0UL)          /*!< Position of PROCSEL field.                                           */
17396   #define ETM_TRCPROCSELR_PROCSEL_Msk (0x1FUL << ETM_TRCPROCSELR_PROCSEL_Pos) /*!< Bit mask of PROCSEL field.                  */
17397 
17398 
17399 /* ETM_TRCSTATR: Idle status bit */
17400   #define ETM_TRCSTATR_ResetValue (0x00000000UL)     /*!< Reset value of TRCSTATR register.                                    */
17401 
17402 /* IDLE @Bit 0 : Trace unit enable bit */
17403   #define ETM_TRCSTATR_IDLE_Pos (0UL)                /*!< Position of IDLE field.                                              */
17404   #define ETM_TRCSTATR_IDLE_Msk (0x1UL << ETM_TRCSTATR_IDLE_Pos) /*!< Bit mask of IDLE field.                                  */
17405   #define ETM_TRCSTATR_IDLE_Min (0x0UL)              /*!< Min enumerator value of IDLE field.                                  */
17406   #define ETM_TRCSTATR_IDLE_Max (0x1UL)              /*!< Max enumerator value of IDLE field.                                  */
17407   #define ETM_TRCSTATR_IDLE_NotIdle (0x0UL)          /*!< The trace unit is not idle.                                          */
17408   #define ETM_TRCSTATR_IDLE_Idle (0x1UL)             /*!< The trace unit is idle.                                              */
17409 
17410 /* PMSTABLE @Bit 1 : Programmers' model stable bit */
17411   #define ETM_TRCSTATR_PMSTABLE_Pos (1UL)            /*!< Position of PMSTABLE field.                                          */
17412   #define ETM_TRCSTATR_PMSTABLE_Msk (0x1UL << ETM_TRCSTATR_PMSTABLE_Pos) /*!< Bit mask of PMSTABLE field.                      */
17413   #define ETM_TRCSTATR_PMSTABLE_Min (0x0UL)          /*!< Min enumerator value of PMSTABLE field.                              */
17414   #define ETM_TRCSTATR_PMSTABLE_Max (0x1UL)          /*!< Max enumerator value of PMSTABLE field.                              */
17415   #define ETM_TRCSTATR_PMSTABLE_NotStable (0x0UL)    /*!< The programmers' model is not stable.                                */
17416   #define ETM_TRCSTATR_PMSTABLE_Stable (0x1UL)       /*!< The programmers' model is stable.                                    */
17417 
17418 
17419 /* ETM_TRCCONFIGR: Controls the tracing options This register must always be programmed as part of trace unit initialization.
17420                     Might ignore writes when the trace unit is enabled or not idle. */
17421 
17422   #define ETM_TRCCONFIGR_ResetValue (0x00000000UL)   /*!< Reset value of TRCCONFIGR register.                                  */
17423 
17424 /* LOADASP0INST @Bit 1 : Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions.
17425                          */
17426 
17427   #define ETM_TRCCONFIGR_LOADASP0INST_Pos (1UL)      /*!< Position of LOADASP0INST field.                                      */
17428   #define ETM_TRCCONFIGR_LOADASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_LOADASP0INST_Pos) /*!< Bit mask of LOADASP0INST field.      */
17429   #define ETM_TRCCONFIGR_LOADASP0INST_Min (0x0UL)    /*!< Min enumerator value of LOADASP0INST field.                          */
17430   #define ETM_TRCCONFIGR_LOADASP0INST_Max (0x1UL)    /*!< Max enumerator value of LOADASP0INST field.                          */
17431   #define ETM_TRCCONFIGR_LOADASP0INST_No (0x0UL)     /*!< Do not trace load instructions as P0 instructions.                   */
17432   #define ETM_TRCCONFIGR_LOADASP0INST_Yes (0x1UL)    /*!< Trace load instructions as P0 instructions.                          */
17433 
17434 /* STOREASP0INST @Bit 2 : Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. */
17435   #define ETM_TRCCONFIGR_STOREASP0INST_Pos (2UL)     /*!< Position of STOREASP0INST field.                                     */
17436   #define ETM_TRCCONFIGR_STOREASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_STOREASP0INST_Pos) /*!< Bit mask of STOREASP0INST field.   */
17437   #define ETM_TRCCONFIGR_STOREASP0INST_Min (0x0UL)   /*!< Min enumerator value of STOREASP0INST field.                         */
17438   #define ETM_TRCCONFIGR_STOREASP0INST_Max (0x1UL)   /*!< Max enumerator value of STOREASP0INST field.                         */
17439   #define ETM_TRCCONFIGR_STOREASP0INST_No (0x0UL)    /*!< Do not trace store instructions as P0 instructions.                  */
17440   #define ETM_TRCCONFIGR_STOREASP0INST_Yes (0x1UL)   /*!< Trace store instructions as P0 instructions.                         */
17441 
17442 /* BB @Bit 3 : Branch broadcast mode bit. */
17443   #define ETM_TRCCONFIGR_BB_Pos (3UL)                /*!< Position of BB field.                                                */
17444   #define ETM_TRCCONFIGR_BB_Msk (0x1UL << ETM_TRCCONFIGR_BB_Pos) /*!< Bit mask of BB field.                                    */
17445   #define ETM_TRCCONFIGR_BB_Min (0x0UL)              /*!< Min enumerator value of BB field.                                    */
17446   #define ETM_TRCCONFIGR_BB_Max (0x1UL)              /*!< Max enumerator value of BB field.                                    */
17447   #define ETM_TRCCONFIGR_BB_Disabled (0x0UL)         /*!< Branch broadcast mode is disabled.                                   */
17448   #define ETM_TRCCONFIGR_BB_Enabled (0x1UL)          /*!< Branch broadcast mode is enabled.                                    */
17449 
17450 /* CCI @Bit 4 : Cycle counting instruction trace bit. */
17451   #define ETM_TRCCONFIGR_CCI_Pos (4UL)               /*!< Position of CCI field.                                               */
17452   #define ETM_TRCCONFIGR_CCI_Msk (0x1UL << ETM_TRCCONFIGR_CCI_Pos) /*!< Bit mask of CCI field.                                 */
17453   #define ETM_TRCCONFIGR_CCI_Min (0x0UL)             /*!< Min enumerator value of CCI field.                                   */
17454   #define ETM_TRCCONFIGR_CCI_Max (0x1UL)             /*!< Max enumerator value of CCI field.                                   */
17455   #define ETM_TRCCONFIGR_CCI_Disabled (0x0UL)        /*!< Cycle counting in the instruction trace is disabled.                 */
17456   #define ETM_TRCCONFIGR_CCI_Enabled (0x1UL)         /*!< Cycle counting in the instruction trace is enabled.                  */
17457 
17458 /* CID @Bit 6 : Context ID tracing bit. */
17459   #define ETM_TRCCONFIGR_CID_Pos (6UL)               /*!< Position of CID field.                                               */
17460   #define ETM_TRCCONFIGR_CID_Msk (0x1UL << ETM_TRCCONFIGR_CID_Pos) /*!< Bit mask of CID field.                                 */
17461   #define ETM_TRCCONFIGR_CID_Min (0x0UL)             /*!< Min enumerator value of CID field.                                   */
17462   #define ETM_TRCCONFIGR_CID_Max (0x1UL)             /*!< Max enumerator value of CID field.                                   */
17463   #define ETM_TRCCONFIGR_CID_Disabled (0x0UL)        /*!< Context ID tracing is disabled.                                      */
17464   #define ETM_TRCCONFIGR_CID_Enabled (0x1UL)         /*!< Context ID tracing is enabled.                                       */
17465 
17466 /* VMID @Bit 7 : Virtual context identifier tracing bit. */
17467   #define ETM_TRCCONFIGR_VMID_Pos (7UL)              /*!< Position of VMID field.                                              */
17468   #define ETM_TRCCONFIGR_VMID_Msk (0x1UL << ETM_TRCCONFIGR_VMID_Pos) /*!< Bit mask of VMID field.                              */
17469   #define ETM_TRCCONFIGR_VMID_Min (0x0UL)            /*!< Min enumerator value of VMID field.                                  */
17470   #define ETM_TRCCONFIGR_VMID_Max (0x1UL)            /*!< Max enumerator value of VMID field.                                  */
17471   #define ETM_TRCCONFIGR_VMID_Disabled (0x0UL)       /*!< Virtual context identifier tracing is disabled.                      */
17472   #define ETM_TRCCONFIGR_VMID_Enabled (0x1UL)        /*!< Virtual context identifier tracing is enabled.                       */
17473 
17474 /* COND @Bits 8..10 : Conditional instruction tracing bit. */
17475   #define ETM_TRCCONFIGR_COND_Pos (8UL)              /*!< Position of COND field.                                              */
17476   #define ETM_TRCCONFIGR_COND_Msk (0x7UL << ETM_TRCCONFIGR_COND_Pos) /*!< Bit mask of COND field.                              */
17477   #define ETM_TRCCONFIGR_COND_Min (0x0UL)            /*!< Min enumerator value of COND field.                                  */
17478   #define ETM_TRCCONFIGR_COND_Max (0x7UL)            /*!< Max enumerator value of COND field.                                  */
17479   #define ETM_TRCCONFIGR_COND_Disabled (0x0UL)       /*!< Conditional instruction tracing is disabled.                         */
17480   #define ETM_TRCCONFIGR_COND_LoadOnly (0x1UL)       /*!< Conditional load instructions are traced.                            */
17481   #define ETM_TRCCONFIGR_COND_StoreOnly (0x2UL)      /*!< Conditional store instructions are traced.                           */
17482   #define ETM_TRCCONFIGR_COND_LoadAndStore (0x3UL)   /*!< Conditional load and store instructions are traced.                  */
17483   #define ETM_TRCCONFIGR_COND_All (0x7UL)            /*!< All conditional instructions are traced.                             */
17484 
17485 /* TS @Bit 11 : Global timestamp tracing bit. */
17486   #define ETM_TRCCONFIGR_TS_Pos (11UL)               /*!< Position of TS field.                                                */
17487   #define ETM_TRCCONFIGR_TS_Msk (0x1UL << ETM_TRCCONFIGR_TS_Pos) /*!< Bit mask of TS field.                                    */
17488   #define ETM_TRCCONFIGR_TS_Min (0x0UL)              /*!< Min enumerator value of TS field.                                    */
17489   #define ETM_TRCCONFIGR_TS_Max (0x1UL)              /*!< Max enumerator value of TS field.                                    */
17490   #define ETM_TRCCONFIGR_TS_Disabled (0x0UL)         /*!< Global timestamp tracing is disabled.                                */
17491   #define ETM_TRCCONFIGR_TS_Enabled (0x1UL)          /*!< Global timestamp tracing is enabled.                                 */
17492 
17493 /* RS @Bit 12 : Return stack enable bit. */
17494   #define ETM_TRCCONFIGR_RS_Pos (12UL)               /*!< Position of RS field.                                                */
17495   #define ETM_TRCCONFIGR_RS_Msk (0x1UL << ETM_TRCCONFIGR_RS_Pos) /*!< Bit mask of RS field.                                    */
17496   #define ETM_TRCCONFIGR_RS_Min (0x0UL)              /*!< Min enumerator value of RS field.                                    */
17497   #define ETM_TRCCONFIGR_RS_Max (0x1UL)              /*!< Max enumerator value of RS field.                                    */
17498   #define ETM_TRCCONFIGR_RS_Disabled (0x0UL)         /*!< Return stack is disabled.                                            */
17499   #define ETM_TRCCONFIGR_RS_Enabled (0x1UL)          /*!< Return stack is enabled.                                             */
17500 
17501 /* QE @Bits 13..14 : Q element enable field. */
17502   #define ETM_TRCCONFIGR_QE_Pos (13UL)               /*!< Position of QE field.                                                */
17503   #define ETM_TRCCONFIGR_QE_Msk (0x3UL << ETM_TRCCONFIGR_QE_Pos) /*!< Bit mask of QE field.                                    */
17504   #define ETM_TRCCONFIGR_QE_Min (0x0UL)              /*!< Min enumerator value of QE field.                                    */
17505   #define ETM_TRCCONFIGR_QE_Max (0x3UL)              /*!< Max enumerator value of QE field.                                    */
17506   #define ETM_TRCCONFIGR_QE_Disabled (0x0UL)         /*!< Q elements are disabled.                                             */
17507   #define ETM_TRCCONFIGR_QE_OnlyWithoutInstCounts (0x1UL) /*!< Q elements with instruction counts are enabled. Q elements
17508                                                                without instruction counts are disabled.*/
17509   #define ETM_TRCCONFIGR_QE_Enabled (0x3UL)          /*!< Q elements with and without instruction counts are enabled.          */
17510 
17511 /* VMIDOPT @Bit 15 : Control bit to select the Virtual context identifier value used by the trace unit, both for trace
17512                      generation and in the Virtual context identifier comparators. */
17513 
17514   #define ETM_TRCCONFIGR_VMIDOPT_Pos (15UL)          /*!< Position of VMIDOPT field.                                           */
17515   #define ETM_TRCCONFIGR_VMIDOPT_Msk (0x1UL << ETM_TRCCONFIGR_VMIDOPT_Pos) /*!< Bit mask of VMIDOPT field.                     */
17516   #define ETM_TRCCONFIGR_VMIDOPT_Min (0x0UL)         /*!< Min enumerator value of VMIDOPT field.                               */
17517   #define ETM_TRCCONFIGR_VMIDOPT_Max (0x1UL)         /*!< Max enumerator value of VMIDOPT field.                               */
17518   #define ETM_TRCCONFIGR_VMIDOPT_VTTBR_EL2 (0x0UL)   /*!< VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context
17519                                                           identifier larger than the VTTBR_EL2.VMID, the upper unused bits are
17520                                                           always zero. If the trace unit supports a Virtual context identifier
17521                                                           larger than 8 bits and if the VTCR_EL2.VS bit forces use of an 8-bit
17522                                                           Virtual context identifier, bits [15:8] of the trace unit Virtual
17523                                                           context identifier are always zero.*/
17524   #define ETM_TRCCONFIGR_VMIDOPT_CONTEXTIDR_EL2 (0x1UL) /*!< CONTEXTIDR_EL2 is used.                                           */
17525 
17526 /* DA @Bit 16 : Data address tracing bit. */
17527   #define ETM_TRCCONFIGR_DA_Pos (16UL)               /*!< Position of DA field.                                                */
17528   #define ETM_TRCCONFIGR_DA_Msk (0x1UL << ETM_TRCCONFIGR_DA_Pos) /*!< Bit mask of DA field.                                    */
17529   #define ETM_TRCCONFIGR_DA_Min (0x0UL)              /*!< Min enumerator value of DA field.                                    */
17530   #define ETM_TRCCONFIGR_DA_Max (0x1UL)              /*!< Max enumerator value of DA field.                                    */
17531   #define ETM_TRCCONFIGR_DA_Disabled (0x0UL)         /*!< Data address tracing is disabled.                                    */
17532   #define ETM_TRCCONFIGR_DA_Enabled (0x1UL)          /*!< Data address tracing is enabled.                                     */
17533 
17534 /* DV @Bit 17 : Data value tracing bit. */
17535   #define ETM_TRCCONFIGR_DV_Pos (17UL)               /*!< Position of DV field.                                                */
17536   #define ETM_TRCCONFIGR_DV_Msk (0x1UL << ETM_TRCCONFIGR_DV_Pos) /*!< Bit mask of DV field.                                    */
17537   #define ETM_TRCCONFIGR_DV_Min (0x0UL)              /*!< Min enumerator value of DV field.                                    */
17538   #define ETM_TRCCONFIGR_DV_Max (0x1UL)              /*!< Max enumerator value of DV field.                                    */
17539   #define ETM_TRCCONFIGR_DV_Disabled (0x0UL)         /*!< Data value tracing is disabled.                                      */
17540   #define ETM_TRCCONFIGR_DV_Enabled (0x1UL)          /*!< Data value tracing is enabled.                                       */
17541 
17542 
17543 /* ETM_TRCEVENTCTL0R: Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the
17544                        trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. */
17545 
17546   #define ETM_TRCEVENTCTL0R_ResetValue (0x00000000UL) /*!< Reset value of TRCEVENTCTL0R register.                              */
17547 
17548 /* EVENT @Bits 0..7 : Select which event should generate trace elements. */
17549   #define ETM_TRCEVENTCTL0R_EVENT_Pos (0UL)          /*!< Position of EVENT field.                                             */
17550   #define ETM_TRCEVENTCTL0R_EVENT_Msk (0xFFUL << ETM_TRCEVENTCTL0R_EVENT_Pos) /*!< Bit mask of EVENT field.                    */
17551   #define ETM_TRCEVENTCTL0R_EVENT_Min (0x0UL)        /*!< Min value of EVENT field.                                            */
17552   #define ETM_TRCEVENTCTL0R_EVENT_Max (0xFFUL)       /*!< Max size of EVENT field.                                             */
17553 
17554 
17555 /* ETM_TRCEVENTCTL1R: Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as
17556                        part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */
17557 
17558   #define ETM_TRCEVENTCTL1R_ResetValue (0x00000000UL) /*!< Reset value of TRCEVENTCTL1R register.                              */
17559 
17560 /* INSTEN0 @Bit 0 : Instruction event enable field. */
17561   #define ETM_TRCEVENTCTL1R_INSTEN0_Pos (0UL)        /*!< Position of INSTEN0 field.                                           */
17562   #define ETM_TRCEVENTCTL1R_INSTEN0_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN0_Pos) /*!< Bit mask of INSTEN0 field.               */
17563   #define ETM_TRCEVENTCTL1R_INSTEN0_Min (0x0UL)      /*!< Min enumerator value of INSTEN0 field.                               */
17564   #define ETM_TRCEVENTCTL1R_INSTEN0_Max (0x1UL)      /*!< Max enumerator value of INSTEN0 field.                               */
17565   #define ETM_TRCEVENTCTL1R_INSTEN0_Disabled (0x0UL) /*!< The trace unit does not generate an Event element.                   */
17566   #define ETM_TRCEVENTCTL1R_INSTEN0_Enabled (0x1UL)  /*!< The trace unit generates an Event element for event 0, in the
17567                                                           instruction trace stream.*/
17568 
17569 /* INSTEN1 @Bit 1 : Instruction event enable field. */
17570   #define ETM_TRCEVENTCTL1R_INSTEN1_Pos (1UL)        /*!< Position of INSTEN1 field.                                           */
17571   #define ETM_TRCEVENTCTL1R_INSTEN1_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN1_Pos) /*!< Bit mask of INSTEN1 field.               */
17572   #define ETM_TRCEVENTCTL1R_INSTEN1_Min (0x0UL)      /*!< Min enumerator value of INSTEN1 field.                               */
17573   #define ETM_TRCEVENTCTL1R_INSTEN1_Max (0x1UL)      /*!< Max enumerator value of INSTEN1 field.                               */
17574   #define ETM_TRCEVENTCTL1R_INSTEN1_Disabled (0x0UL) /*!< The trace unit does not generate an Event element.                   */
17575   #define ETM_TRCEVENTCTL1R_INSTEN1_Enabled (0x1UL)  /*!< The trace unit generates an Event element for event 1, in the
17576                                                           instruction trace stream.*/
17577 
17578 /* INSTEN2 @Bit 2 : Instruction event enable field. */
17579   #define ETM_TRCEVENTCTL1R_INSTEN2_Pos (2UL)        /*!< Position of INSTEN2 field.                                           */
17580   #define ETM_TRCEVENTCTL1R_INSTEN2_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN2_Pos) /*!< Bit mask of INSTEN2 field.               */
17581   #define ETM_TRCEVENTCTL1R_INSTEN2_Min (0x0UL)      /*!< Min enumerator value of INSTEN2 field.                               */
17582   #define ETM_TRCEVENTCTL1R_INSTEN2_Max (0x1UL)      /*!< Max enumerator value of INSTEN2 field.                               */
17583   #define ETM_TRCEVENTCTL1R_INSTEN2_Disabled (0x0UL) /*!< The trace unit does not generate an Event element.                   */
17584   #define ETM_TRCEVENTCTL1R_INSTEN2_Enabled (0x1UL)  /*!< The trace unit generates an Event element for event 2, in the
17585                                                           instruction trace stream.*/
17586 
17587 /* INSTEN3 @Bit 3 : Instruction event enable field. */
17588   #define ETM_TRCEVENTCTL1R_INSTEN3_Pos (3UL)        /*!< Position of INSTEN3 field.                                           */
17589   #define ETM_TRCEVENTCTL1R_INSTEN3_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN3_Pos) /*!< Bit mask of INSTEN3 field.               */
17590   #define ETM_TRCEVENTCTL1R_INSTEN3_Min (0x0UL)      /*!< Min enumerator value of INSTEN3 field.                               */
17591   #define ETM_TRCEVENTCTL1R_INSTEN3_Max (0x1UL)      /*!< Max enumerator value of INSTEN3 field.                               */
17592   #define ETM_TRCEVENTCTL1R_INSTEN3_Disabled (0x0UL) /*!< The trace unit does not generate an Event element.                   */
17593   #define ETM_TRCEVENTCTL1R_INSTEN3_Enabled (0x1UL)  /*!< The trace unit generates an Event element for event 3, in the
17594                                                           instruction trace stream.*/
17595 
17596 /* DATAEN @Bit 4 : Data event enable bit. */
17597   #define ETM_TRCEVENTCTL1R_DATAEN_Pos (4UL)         /*!< Position of DATAEN field.                                            */
17598   #define ETM_TRCEVENTCTL1R_DATAEN_Msk (0x1UL << ETM_TRCEVENTCTL1R_DATAEN_Pos) /*!< Bit mask of DATAEN field.                  */
17599   #define ETM_TRCEVENTCTL1R_DATAEN_Min (0x0UL)       /*!< Min enumerator value of DATAEN field.                                */
17600   #define ETM_TRCEVENTCTL1R_DATAEN_Max (0x1UL)       /*!< Max enumerator value of DATAEN field.                                */
17601   #define ETM_TRCEVENTCTL1R_DATAEN_Disabled (0x0UL)  /*!< The trace unit does not generate an Event element if event 0 occurs. */
17602   #define ETM_TRCEVENTCTL1R_DATAEN_Enabled (0x1UL)   /*!< The trace unit generates an Event element in the data trace stream if
17603                                                           event 0 occurs.*/
17604 
17605 /* ATB @Bit 11 : AMBA Trace Bus (ATB) trigger enable bit. */
17606   #define ETM_TRCEVENTCTL1R_ATB_Pos (11UL)           /*!< Position of ATB field.                                               */
17607   #define ETM_TRCEVENTCTL1R_ATB_Msk (0x1UL << ETM_TRCEVENTCTL1R_ATB_Pos) /*!< Bit mask of ATB field.                           */
17608   #define ETM_TRCEVENTCTL1R_ATB_Min (0x0UL)          /*!< Min enumerator value of ATB field.                                   */
17609   #define ETM_TRCEVENTCTL1R_ATB_Max (0x1UL)          /*!< Max enumerator value of ATB field.                                   */
17610   #define ETM_TRCEVENTCTL1R_ATB_Disabled (0x0UL)     /*!< ATB trigger is disabled.                                             */
17611   #define ETM_TRCEVENTCTL1R_ATB_Enabled (0x1UL)      /*!< ATB trigger is enabled. If a CoreSight ATB interface is implemented
17612                                                           then when event 0 occurs the trace unit generates an ATB event.*/
17613 
17614 /* LPOVERRIDE @Bit 12 : Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. */
17615   #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos (12UL)    /*!< Position of LPOVERRIDE field.                                        */
17616   #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Msk (0x1UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos) /*!< Bit mask of LPOVERRIDE field.      */
17617   #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Min (0x0UL)   /*!< Min enumerator value of LPOVERRIDE field.                            */
17618   #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Max (0x1UL)   /*!< Max enumerator value of LPOVERRIDE field.                            */
17619   #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Disabled (0x0UL) /*!< Trace unit low-power state behavior is not affected. That is, the
17620                                                              trace unit is enabled to enter low-power state.*/
17621   #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Enabled (0x1UL) /*!< Trace unit low-power state behavior is overridden. That is, entry to
17622                                                             a low-power state does not affect the trace unit resources or trace
17623                                                             generation.*/
17624 
17625 
17626 /* ETM_TRCSTALLCTLR: Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the
17627                       trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. */
17628 
17629   #define ETM_TRCSTALLCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCSTALLCTLR register.                                */
17630 
17631 /* LEVEL @Bits 0..3 : Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global
17632                       timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction
17633                       trace stream, although the cumulative cycle count remains correct. */
17634 
17635   #define ETM_TRCSTALLCTLR_LEVEL_Pos (0UL)           /*!< Position of LEVEL field.                                             */
17636   #define ETM_TRCSTALLCTLR_LEVEL_Msk (0xFUL << ETM_TRCSTALLCTLR_LEVEL_Pos) /*!< Bit mask of LEVEL field.                       */
17637   #define ETM_TRCSTALLCTLR_LEVEL_Min (0x0UL)         /*!< Zero invasion. This setting has a greater risk of a FIFO overflow    */
17638   #define ETM_TRCSTALLCTLR_LEVEL_Max (0xFUL)         /*!< Maximum invasion occurs but there is less risk of a FIFO overflow.   */
17639 
17640 /* ISTALL @Bit 8 : Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is
17641                    less than LEVEL. */
17642 
17643   #define ETM_TRCSTALLCTLR_ISTALL_Pos (8UL)          /*!< Position of ISTALL field.                                            */
17644   #define ETM_TRCSTALLCTLR_ISTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_ISTALL_Pos) /*!< Bit mask of ISTALL field.                    */
17645   #define ETM_TRCSTALLCTLR_ISTALL_Min (0x0UL)        /*!< Min enumerator value of ISTALL field.                                */
17646   #define ETM_TRCSTALLCTLR_ISTALL_Max (0x1UL)        /*!< Max enumerator value of ISTALL field.                                */
17647   #define ETM_TRCSTALLCTLR_ISTALL_Disabled (0x0UL)   /*!< The trace unit must not stall the PE.                                */
17648   #define ETM_TRCSTALLCTLR_ISTALL_Enabled (0x1UL)    /*!< The trace unit can stall the PE.                                     */
17649 
17650 /* DSTALL @Bit 9 : Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than
17651                    LEVEL. */
17652 
17653   #define ETM_TRCSTALLCTLR_DSTALL_Pos (9UL)          /*!< Position of DSTALL field.                                            */
17654   #define ETM_TRCSTALLCTLR_DSTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_DSTALL_Pos) /*!< Bit mask of DSTALL field.                    */
17655   #define ETM_TRCSTALLCTLR_DSTALL_Min (0x0UL)        /*!< Min enumerator value of DSTALL field.                                */
17656   #define ETM_TRCSTALLCTLR_DSTALL_Max (0x1UL)        /*!< Max enumerator value of DSTALL field.                                */
17657   #define ETM_TRCSTALLCTLR_DSTALL_Disabled (0x0UL)   /*!< The trace unit must not stall the PE.                                */
17658   #define ETM_TRCSTALLCTLR_DSTALL_Enabled (0x1UL)    /*!< The trace unit can stall the PE.                                     */
17659 
17660 /* INSTPRIORITY @Bit 10 : Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the
17661                           instruction trace buffer space is less than LEVEL. */
17662 
17663   #define ETM_TRCSTALLCTLR_INSTPRIORITY_Pos (10UL)   /*!< Position of INSTPRIORITY field.                                      */
17664   #define ETM_TRCSTALLCTLR_INSTPRIORITY_Msk (0x1UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos) /*!< Bit mask of INSTPRIORITY field.  */
17665   #define ETM_TRCSTALLCTLR_INSTPRIORITY_Min (0x0UL)  /*!< Min enumerator value of INSTPRIORITY field.                          */
17666   #define ETM_TRCSTALLCTLR_INSTPRIORITY_Max (0x1UL)  /*!< Max enumerator value of INSTPRIORITY field.                          */
17667   #define ETM_TRCSTALLCTLR_INSTPRIORITY_Disabled (0x0UL) /*!< The trace unit must not prioritize instruction trace.            */
17668   #define ETM_TRCSTALLCTLR_INSTPRIORITY_Enabled (0x1UL) /*!< The trace unit can prioritize instruction trace. A trace unit might
17669                                                              prioritize instruction trace by preventing output of data trace, or
17670                                                              other means which ensure that the instruction trace has a higher
17671                                                              priority than the data trace.*/
17672 
17673 /* DATADISCARDLOAD @Bit 11 : Data discard field. Controls if a trace unit can discard data trace elements on a load when the
17674                              data trace buffer space is less than LEVEL. */
17675 
17676   #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos (11UL) /*!< Position of DATADISCARDLOAD field.                                  */
17677   #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos) /*!< Bit mask of DATADISCARDLOAD
17678                                                                             field.*/
17679   #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Min (0x0UL) /*!< Min enumerator value of DATADISCARDLOAD field.                     */
17680   #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Max (0x1UL) /*!< Max enumerator value of DATADISCARDLOAD field.                     */
17681   #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements.      */
17682   #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with
17683                                                                 data loads.*/
17684 
17685 /* DATADISCARDSTORE @Bit 12 : Data discard field. Controls if a trace unit can discard data trace elements on a store when the
17686                               data trace buffer space is less than LEVEL. */
17687 
17688   #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos (12UL) /*!< Position of DATADISCARDSTORE field.                                */
17689   #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos) /*!< Bit mask of
17690                                                                             DATADISCARDSTORE field.*/
17691   #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Min (0x0UL) /*!< Min enumerator value of DATADISCARDSTORE field.                   */
17692   #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Max (0x1UL) /*!< Max enumerator value of DATADISCARDSTORE field.                   */
17693   #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements.     */
17694   #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with
17695                                                                  data stores.*/
17696 
17697 /* NOOVERFLOW @Bit 13 : Trace overflow prevention bit. */
17698   #define ETM_TRCSTALLCTLR_NOOVERFLOW_Pos (13UL)     /*!< Position of NOOVERFLOW field.                                        */
17699   #define ETM_TRCSTALLCTLR_NOOVERFLOW_Msk (0x1UL << ETM_TRCSTALLCTLR_NOOVERFLOW_Pos) /*!< Bit mask of NOOVERFLOW field.        */
17700   #define ETM_TRCSTALLCTLR_NOOVERFLOW_Min (0x0UL)    /*!< Min enumerator value of NOOVERFLOW field.                            */
17701   #define ETM_TRCSTALLCTLR_NOOVERFLOW_Max (0x1UL)    /*!< Max enumerator value of NOOVERFLOW field.                            */
17702   #define ETM_TRCSTALLCTLR_NOOVERFLOW_Disabled (0x0UL) /*!< Trace overflow prevention is disabled.                             */
17703   #define ETM_TRCSTALLCTLR_NOOVERFLOW_Enabled (0x1UL) /*!< Trace overflow prevention is enabled. This might cause a significant
17704                                                            performance impact.*/
17705 
17706 
17707 /* ETM_TRCTSCTLR: Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the
17708                    trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is
17709                    enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. */
17710 
17711   #define ETM_TRCTSCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCTSCTLR register.                                   */
17712 
17713 /* EVENT @Bits 0..7 : Select which event should generate time stamps. */
17714   #define ETM_TRCTSCTLR_EVENT_Pos (0UL)              /*!< Position of EVENT field.                                             */
17715   #define ETM_TRCTSCTLR_EVENT_Msk (0xFFUL << ETM_TRCTSCTLR_EVENT_Pos) /*!< Bit mask of EVENT field.                            */
17716   #define ETM_TRCTSCTLR_EVENT_Min (0x0UL)            /*!< Min value of EVENT field.                                            */
17717   #define ETM_TRCTSCTLR_EVENT_Max (0xFFUL)           /*!< Max size of EVENT field.                                             */
17718 
17719 
17720 /* ETM_TRCSYNCPR: Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or
17721                    not idle. If writes are permitted then the register must be programmed. */
17722 
17723   #define ETM_TRCSYNCPR_ResetValue (0x00000000UL)    /*!< Reset value of TRCSYNCPR register.                                   */
17724 
17725 /* PERIOD @Bits 0..4 : Controls how many bytes of trace, the sum of instruction and data, that a trace unit can generate before
17726                        a trace synchronization request occurs. The number of bytes is always a power of two, calculated by
17727                        2^PERIOD */
17728 
17729   #define ETM_TRCSYNCPR_PERIOD_Pos (0UL)             /*!< Position of PERIOD field.                                            */
17730   #define ETM_TRCSYNCPR_PERIOD_Msk (0x1FUL << ETM_TRCSYNCPR_PERIOD_Pos) /*!< Bit mask of PERIOD field.                         */
17731   #define ETM_TRCSYNCPR_PERIOD_Min (0x0UL)           /*!< Min value of PERIOD field.                                           */
17732   #define ETM_TRCSYNCPR_PERIOD_Max (0x1FUL)          /*!< Max size of PERIOD field.                                            */
17733   #define ETM_TRCSYNCPR_PERIOD_Disabled (0x00UL)     /*!< Trace synchronization requests are disabled. This setting does not
17734                                                           disable other types of trace synchronization request.*/
17735 
17736 
17737 /* ETM_TRCCCCTLR: Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle.
17738                    Must be programmed if TRCCONFIGR.CCI==1. */
17739 
17740   #define ETM_TRCCCCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCCCCTLR register.                                   */
17741 
17742 /* THRESHOLD @Bits 0..11 : Sets the threshold value for instruction trace cycle counting. */
17743   #define ETM_TRCCCCTLR_THRESHOLD_Pos (0UL)          /*!< Position of THRESHOLD field.                                         */
17744   #define ETM_TRCCCCTLR_THRESHOLD_Msk (0xFFFUL << ETM_TRCCCCTLR_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field.               */
17745   #define ETM_TRCCCCTLR_THRESHOLD_Min (0x0UL)        /*!< Min value of THRESHOLD field.                                        */
17746   #define ETM_TRCCCCTLR_THRESHOLD_Max (0x7FFUL)      /*!< Max size of THRESHOLD field.                                         */
17747 
17748 
17749 /* ETM_TRCBBCTLR: Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the
17750                    trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. */
17751 
17752   #define ETM_TRCBBCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCBBCTLR register.                                   */
17753 
17754 /* RANGE0 @Bit 0 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
17755                    field represents an address range comparator pair, so field[0] controls the selection of address range
17756                    comparator pair 0. */
17757 
17758   #define ETM_TRCBBCTLR_RANGE0_Pos (0UL)             /*!< Position of RANGE0 field.                                            */
17759   #define ETM_TRCBBCTLR_RANGE0_Msk (0x1UL << ETM_TRCBBCTLR_RANGE0_Pos) /*!< Bit mask of RANGE0 field.                          */
17760   #define ETM_TRCBBCTLR_RANGE0_Min (0x0UL)           /*!< Min enumerator value of RANGE0 field.                                */
17761   #define ETM_TRCBBCTLR_RANGE0_Max (0x1UL)           /*!< Max enumerator value of RANGE0 field.                                */
17762   #define ETM_TRCBBCTLR_RANGE0_Disabled (0x0UL)      /*!< The address range that address range comparator pair 0 defines, is not
17763                                                           selected.*/
17764   #define ETM_TRCBBCTLR_RANGE0_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
17765                                                           selected.*/
17766 
17767 /* RANGE1 @Bit 1 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
17768                    field represents an address range comparator pair, so field[1] controls the selection of address range
17769                    comparator pair 1. */
17770 
17771   #define ETM_TRCBBCTLR_RANGE1_Pos (1UL)             /*!< Position of RANGE1 field.                                            */
17772   #define ETM_TRCBBCTLR_RANGE1_Msk (0x1UL << ETM_TRCBBCTLR_RANGE1_Pos) /*!< Bit mask of RANGE1 field.                          */
17773   #define ETM_TRCBBCTLR_RANGE1_Min (0x0UL)           /*!< Min enumerator value of RANGE1 field.                                */
17774   #define ETM_TRCBBCTLR_RANGE1_Max (0x1UL)           /*!< Max enumerator value of RANGE1 field.                                */
17775   #define ETM_TRCBBCTLR_RANGE1_Disabled (0x0UL)      /*!< The address range that address range comparator pair 1 defines, is not
17776                                                           selected.*/
17777   #define ETM_TRCBBCTLR_RANGE1_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
17778                                                           selected.*/
17779 
17780 /* RANGE2 @Bit 2 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
17781                    field represents an address range comparator pair, so field[2] controls the selection of address range
17782                    comparator pair 2. */
17783 
17784   #define ETM_TRCBBCTLR_RANGE2_Pos (2UL)             /*!< Position of RANGE2 field.                                            */
17785   #define ETM_TRCBBCTLR_RANGE2_Msk (0x1UL << ETM_TRCBBCTLR_RANGE2_Pos) /*!< Bit mask of RANGE2 field.                          */
17786   #define ETM_TRCBBCTLR_RANGE2_Min (0x0UL)           /*!< Min enumerator value of RANGE2 field.                                */
17787   #define ETM_TRCBBCTLR_RANGE2_Max (0x1UL)           /*!< Max enumerator value of RANGE2 field.                                */
17788   #define ETM_TRCBBCTLR_RANGE2_Disabled (0x0UL)      /*!< The address range that address range comparator pair 2 defines, is not
17789                                                           selected.*/
17790   #define ETM_TRCBBCTLR_RANGE2_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
17791                                                           selected.*/
17792 
17793 /* RANGE3 @Bit 3 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
17794                    field represents an address range comparator pair, so field[3] controls the selection of address range
17795                    comparator pair 3. */
17796 
17797   #define ETM_TRCBBCTLR_RANGE3_Pos (3UL)             /*!< Position of RANGE3 field.                                            */
17798   #define ETM_TRCBBCTLR_RANGE3_Msk (0x1UL << ETM_TRCBBCTLR_RANGE3_Pos) /*!< Bit mask of RANGE3 field.                          */
17799   #define ETM_TRCBBCTLR_RANGE3_Min (0x0UL)           /*!< Min enumerator value of RANGE3 field.                                */
17800   #define ETM_TRCBBCTLR_RANGE3_Max (0x1UL)           /*!< Max enumerator value of RANGE3 field.                                */
17801   #define ETM_TRCBBCTLR_RANGE3_Disabled (0x0UL)      /*!< The address range that address range comparator pair 3 defines, is not
17802                                                           selected.*/
17803   #define ETM_TRCBBCTLR_RANGE3_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
17804                                                           selected.*/
17805 
17806 /* RANGE4 @Bit 4 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
17807                    field represents an address range comparator pair, so field[4] controls the selection of address range
17808                    comparator pair 4. */
17809 
17810   #define ETM_TRCBBCTLR_RANGE4_Pos (4UL)             /*!< Position of RANGE4 field.                                            */
17811   #define ETM_TRCBBCTLR_RANGE4_Msk (0x1UL << ETM_TRCBBCTLR_RANGE4_Pos) /*!< Bit mask of RANGE4 field.                          */
17812   #define ETM_TRCBBCTLR_RANGE4_Min (0x0UL)           /*!< Min enumerator value of RANGE4 field.                                */
17813   #define ETM_TRCBBCTLR_RANGE4_Max (0x1UL)           /*!< Max enumerator value of RANGE4 field.                                */
17814   #define ETM_TRCBBCTLR_RANGE4_Disabled (0x0UL)      /*!< The address range that address range comparator pair 4 defines, is not
17815                                                           selected.*/
17816   #define ETM_TRCBBCTLR_RANGE4_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
17817                                                           selected.*/
17818 
17819 /* RANGE5 @Bit 5 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
17820                    field represents an address range comparator pair, so field[5] controls the selection of address range
17821                    comparator pair 5. */
17822 
17823   #define ETM_TRCBBCTLR_RANGE5_Pos (5UL)             /*!< Position of RANGE5 field.                                            */
17824   #define ETM_TRCBBCTLR_RANGE5_Msk (0x1UL << ETM_TRCBBCTLR_RANGE5_Pos) /*!< Bit mask of RANGE5 field.                          */
17825   #define ETM_TRCBBCTLR_RANGE5_Min (0x0UL)           /*!< Min enumerator value of RANGE5 field.                                */
17826   #define ETM_TRCBBCTLR_RANGE5_Max (0x1UL)           /*!< Max enumerator value of RANGE5 field.                                */
17827   #define ETM_TRCBBCTLR_RANGE5_Disabled (0x0UL)      /*!< The address range that address range comparator pair 5 defines, is not
17828                                                           selected.*/
17829   #define ETM_TRCBBCTLR_RANGE5_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
17830                                                           selected.*/
17831 
17832 /* RANGE6 @Bit 6 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
17833                    field represents an address range comparator pair, so field[6] controls the selection of address range
17834                    comparator pair 6. */
17835 
17836   #define ETM_TRCBBCTLR_RANGE6_Pos (6UL)             /*!< Position of RANGE6 field.                                            */
17837   #define ETM_TRCBBCTLR_RANGE6_Msk (0x1UL << ETM_TRCBBCTLR_RANGE6_Pos) /*!< Bit mask of RANGE6 field.                          */
17838   #define ETM_TRCBBCTLR_RANGE6_Min (0x0UL)           /*!< Min enumerator value of RANGE6 field.                                */
17839   #define ETM_TRCBBCTLR_RANGE6_Max (0x1UL)           /*!< Max enumerator value of RANGE6 field.                                */
17840   #define ETM_TRCBBCTLR_RANGE6_Disabled (0x0UL)      /*!< The address range that address range comparator pair 6 defines, is not
17841                                                           selected.*/
17842   #define ETM_TRCBBCTLR_RANGE6_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
17843                                                           selected.*/
17844 
17845 /* RANGE7 @Bit 7 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. Each
17846                    field represents an address range comparator pair, so field[7] controls the selection of address range
17847                    comparator pair 7. */
17848 
17849   #define ETM_TRCBBCTLR_RANGE7_Pos (7UL)             /*!< Position of RANGE7 field.                                            */
17850   #define ETM_TRCBBCTLR_RANGE7_Msk (0x1UL << ETM_TRCBBCTLR_RANGE7_Pos) /*!< Bit mask of RANGE7 field.                          */
17851   #define ETM_TRCBBCTLR_RANGE7_Min (0x0UL)           /*!< Min enumerator value of RANGE7 field.                                */
17852   #define ETM_TRCBBCTLR_RANGE7_Max (0x1UL)           /*!< Max enumerator value of RANGE7 field.                                */
17853   #define ETM_TRCBBCTLR_RANGE7_Disabled (0x0UL)      /*!< The address range that address range comparator pair 7 defines, is not
17854                                                           selected.*/
17855   #define ETM_TRCBBCTLR_RANGE7_Enabled (0x1UL)       /*!< The address range that address range comparator pair n defines, is
17856                                                           selected.*/
17857 
17858 
17859 /* ETM_TRCTRACEIDR: Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data
17860                      trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace
17861                      unit initialization. Might ignore writes when the trace unit is enabled or not idle. */
17862 
17863   #define ETM_TRCTRACEIDR_ResetValue (0x00000000UL)  /*!< Reset value of TRCTRACEIDR register.                                 */
17864 
17865 /* TRACEID @Bits 0..6 : Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is
17866                         enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. */
17867 
17868   #define ETM_TRCTRACEIDR_TRACEID_Pos (0UL)          /*!< Position of TRACEID field.                                           */
17869   #define ETM_TRCTRACEIDR_TRACEID_Msk (0x7FUL << ETM_TRCTRACEIDR_TRACEID_Pos) /*!< Bit mask of TRACEID field.                  */
17870 
17871 
17872 /* ETM_TRCQCTLR: Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This
17873                   register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. */
17874 
17875   #define ETM_TRCQCTLR_ResetValue (0x00000000UL)     /*!< Reset value of TRCQCTLR register.                                    */
17876 
17877 /* RANGE0 @Bit 0 : Specifies the address range comparators to be used for controlling Q elements. */
17878   #define ETM_TRCQCTLR_RANGE0_Pos (0UL)              /*!< Position of RANGE0 field.                                            */
17879   #define ETM_TRCQCTLR_RANGE0_Msk (0x1UL << ETM_TRCQCTLR_RANGE0_Pos) /*!< Bit mask of RANGE0 field.                            */
17880   #define ETM_TRCQCTLR_RANGE0_Min (0x0UL)            /*!< Min enumerator value of RANGE0 field.                                */
17881   #define ETM_TRCQCTLR_RANGE0_Max (0x1UL)            /*!< Max enumerator value of RANGE0 field.                                */
17882   #define ETM_TRCQCTLR_RANGE0_Disabled (0x0UL)       /*!< Address range comparator 0 is disabled.                              */
17883   #define ETM_TRCQCTLR_RANGE0_Enabled (0x1UL)        /*!< Address range comparator 0 is selected for use.                      */
17884 
17885 /* RANGE1 @Bit 1 : Specifies the address range comparators to be used for controlling Q elements. */
17886   #define ETM_TRCQCTLR_RANGE1_Pos (1UL)              /*!< Position of RANGE1 field.                                            */
17887   #define ETM_TRCQCTLR_RANGE1_Msk (0x1UL << ETM_TRCQCTLR_RANGE1_Pos) /*!< Bit mask of RANGE1 field.                            */
17888   #define ETM_TRCQCTLR_RANGE1_Min (0x0UL)            /*!< Min enumerator value of RANGE1 field.                                */
17889   #define ETM_TRCQCTLR_RANGE1_Max (0x1UL)            /*!< Max enumerator value of RANGE1 field.                                */
17890   #define ETM_TRCQCTLR_RANGE1_Disabled (0x0UL)       /*!< Address range comparator 1 is disabled.                              */
17891   #define ETM_TRCQCTLR_RANGE1_Enabled (0x1UL)        /*!< Address range comparator 1 is selected for use.                      */
17892 
17893 /* RANGE2 @Bit 2 : Specifies the address range comparators to be used for controlling Q elements. */
17894   #define ETM_TRCQCTLR_RANGE2_Pos (2UL)              /*!< Position of RANGE2 field.                                            */
17895   #define ETM_TRCQCTLR_RANGE2_Msk (0x1UL << ETM_TRCQCTLR_RANGE2_Pos) /*!< Bit mask of RANGE2 field.                            */
17896   #define ETM_TRCQCTLR_RANGE2_Min (0x0UL)            /*!< Min enumerator value of RANGE2 field.                                */
17897   #define ETM_TRCQCTLR_RANGE2_Max (0x1UL)            /*!< Max enumerator value of RANGE2 field.                                */
17898   #define ETM_TRCQCTLR_RANGE2_Disabled (0x0UL)       /*!< Address range comparator 2 is disabled.                              */
17899   #define ETM_TRCQCTLR_RANGE2_Enabled (0x1UL)        /*!< Address range comparator 2 is selected for use.                      */
17900 
17901 /* RANGE3 @Bit 3 : Specifies the address range comparators to be used for controlling Q elements. */
17902   #define ETM_TRCQCTLR_RANGE3_Pos (3UL)              /*!< Position of RANGE3 field.                                            */
17903   #define ETM_TRCQCTLR_RANGE3_Msk (0x1UL << ETM_TRCQCTLR_RANGE3_Pos) /*!< Bit mask of RANGE3 field.                            */
17904   #define ETM_TRCQCTLR_RANGE3_Min (0x0UL)            /*!< Min enumerator value of RANGE3 field.                                */
17905   #define ETM_TRCQCTLR_RANGE3_Max (0x1UL)            /*!< Max enumerator value of RANGE3 field.                                */
17906   #define ETM_TRCQCTLR_RANGE3_Disabled (0x0UL)       /*!< Address range comparator 3 is disabled.                              */
17907   #define ETM_TRCQCTLR_RANGE3_Enabled (0x1UL)        /*!< Address range comparator 3 is selected for use.                      */
17908 
17909 /* RANGE4 @Bit 4 : Specifies the address range comparators to be used for controlling Q elements. */
17910   #define ETM_TRCQCTLR_RANGE4_Pos (4UL)              /*!< Position of RANGE4 field.                                            */
17911   #define ETM_TRCQCTLR_RANGE4_Msk (0x1UL << ETM_TRCQCTLR_RANGE4_Pos) /*!< Bit mask of RANGE4 field.                            */
17912   #define ETM_TRCQCTLR_RANGE4_Min (0x0UL)            /*!< Min enumerator value of RANGE4 field.                                */
17913   #define ETM_TRCQCTLR_RANGE4_Max (0x1UL)            /*!< Max enumerator value of RANGE4 field.                                */
17914   #define ETM_TRCQCTLR_RANGE4_Disabled (0x0UL)       /*!< Address range comparator 4 is disabled.                              */
17915   #define ETM_TRCQCTLR_RANGE4_Enabled (0x1UL)        /*!< Address range comparator 4 is selected for use.                      */
17916 
17917 /* RANGE5 @Bit 5 : Specifies the address range comparators to be used for controlling Q elements. */
17918   #define ETM_TRCQCTLR_RANGE5_Pos (5UL)              /*!< Position of RANGE5 field.                                            */
17919   #define ETM_TRCQCTLR_RANGE5_Msk (0x1UL << ETM_TRCQCTLR_RANGE5_Pos) /*!< Bit mask of RANGE5 field.                            */
17920   #define ETM_TRCQCTLR_RANGE5_Min (0x0UL)            /*!< Min enumerator value of RANGE5 field.                                */
17921   #define ETM_TRCQCTLR_RANGE5_Max (0x1UL)            /*!< Max enumerator value of RANGE5 field.                                */
17922   #define ETM_TRCQCTLR_RANGE5_Disabled (0x0UL)       /*!< Address range comparator 5 is disabled.                              */
17923   #define ETM_TRCQCTLR_RANGE5_Enabled (0x1UL)        /*!< Address range comparator 5 is selected for use.                      */
17924 
17925 /* RANGE6 @Bit 6 : Specifies the address range comparators to be used for controlling Q elements. */
17926   #define ETM_TRCQCTLR_RANGE6_Pos (6UL)              /*!< Position of RANGE6 field.                                            */
17927   #define ETM_TRCQCTLR_RANGE6_Msk (0x1UL << ETM_TRCQCTLR_RANGE6_Pos) /*!< Bit mask of RANGE6 field.                            */
17928   #define ETM_TRCQCTLR_RANGE6_Min (0x0UL)            /*!< Min enumerator value of RANGE6 field.                                */
17929   #define ETM_TRCQCTLR_RANGE6_Max (0x1UL)            /*!< Max enumerator value of RANGE6 field.                                */
17930   #define ETM_TRCQCTLR_RANGE6_Disabled (0x0UL)       /*!< Address range comparator 6 is disabled.                              */
17931   #define ETM_TRCQCTLR_RANGE6_Enabled (0x1UL)        /*!< Address range comparator 6 is selected for use.                      */
17932 
17933 /* RANGE7 @Bit 7 : Specifies the address range comparators to be used for controlling Q elements. */
17934   #define ETM_TRCQCTLR_RANGE7_Pos (7UL)              /*!< Position of RANGE7 field.                                            */
17935   #define ETM_TRCQCTLR_RANGE7_Msk (0x1UL << ETM_TRCQCTLR_RANGE7_Pos) /*!< Bit mask of RANGE7 field.                            */
17936   #define ETM_TRCQCTLR_RANGE7_Min (0x0UL)            /*!< Min enumerator value of RANGE7 field.                                */
17937   #define ETM_TRCQCTLR_RANGE7_Max (0x1UL)            /*!< Max enumerator value of RANGE7 field.                                */
17938   #define ETM_TRCQCTLR_RANGE7_Disabled (0x0UL)       /*!< Address range comparator 7 is disabled.                              */
17939   #define ETM_TRCQCTLR_RANGE7_Enabled (0x1UL)        /*!< Address range comparator 7 is selected for use.                      */
17940 
17941 /* MODE @Bit 8 : Selects whether the address range comparators selected by the RANGE field indicate address ranges where the
17942                  trace unit is permitted to generate Q elements or address ranges where the trace unit is not permitted to
17943                  generate Q elements: */
17944 
17945   #define ETM_TRCQCTLR_MODE_Pos (8UL)                /*!< Position of MODE field.                                              */
17946   #define ETM_TRCQCTLR_MODE_Msk (0x1UL << ETM_TRCQCTLR_MODE_Pos) /*!< Bit mask of MODE field.                                  */
17947   #define ETM_TRCQCTLR_MODE_Min (0x0UL)              /*!< Min enumerator value of MODE field.                                  */
17948   #define ETM_TRCQCTLR_MODE_Max (0x1UL)              /*!< Max enumerator value of MODE field.                                  */
17949   #define ETM_TRCQCTLR_MODE_Exclude (0x0UL)          /*!< Exclude mode. The address range comparators selected by the RANGE
17950                                                           field indicate address ranges where the trace unit cannot generate Q
17951                                                           elements. If no ranges are selected, Q elements are permitted across
17952                                                           the entire memory map.*/
17953   #define ETM_TRCQCTLR_MODE_Include (0x1UL)          /*!< Include mode. The address range comparators selected by the RANGE
17954                                                           field indicate address ranges where the trace unit can generate Q
17955                                                           elements. If all the implemented bits in RANGE are set to 0 then Q
17956                                                           elements are disabled.*/
17957 
17958 
17959 /* ETM_TRCVICTLR: Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only
17960                    returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the
17961                    SSSTATUS bit, which sets the state of the start/stop logic. */
17962 
17963   #define ETM_TRCVICTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCVICTLR register.                                   */
17964 
17965 /* EVENT_SEL @Bits 0..4 : Select which resource number should be filtered. */
17966   #define ETM_TRCVICTLR_EVENT_SEL_Pos (0UL)          /*!< Position of EVENT_SEL field.                                         */
17967   #define ETM_TRCVICTLR_EVENT_SEL_Msk (0x1FUL << ETM_TRCVICTLR_EVENT_SEL_Pos) /*!< Bit mask of EVENT_SEL field.                */
17968   #define ETM_TRCVICTLR_EVENT_SEL_Min (0x0UL)        /*!< Min enumerator value of EVENT_SEL field.                             */
17969   #define ETM_TRCVICTLR_EVENT_SEL_Max (0x1UL)        /*!< Max enumerator value of EVENT_SEL field.                             */
17970   #define ETM_TRCVICTLR_EVENT_SEL_Disabled (0x00UL)  /*!< This event is not filtered.                                          */
17971   #define ETM_TRCVICTLR_EVENT_SEL_Enabled (0x01UL)   /*!< This event is filtered.                                              */
17972 
17973 /* SSSTATUS @Bit 9 : When TRCIDR4.NUMACPAIRS > 0 or TRCIDR4.NUMPC > 0, this bit returns the status of the start/stop logic. */
17974   #define ETM_TRCVICTLR_SSSTATUS_Pos (9UL)           /*!< Position of SSSTATUS field.                                          */
17975   #define ETM_TRCVICTLR_SSSTATUS_Msk (0x1UL << ETM_TRCVICTLR_SSSTATUS_Pos) /*!< Bit mask of SSSTATUS field.                    */
17976   #define ETM_TRCVICTLR_SSSTATUS_Min (0x0UL)         /*!< Min enumerator value of SSSTATUS field.                              */
17977   #define ETM_TRCVICTLR_SSSTATUS_Max (0x1UL)         /*!< Max enumerator value of SSSTATUS field.                              */
17978   #define ETM_TRCVICTLR_SSSTATUS_Stopped (0x0UL)     /*!< The start/stop logic is in the stopped state.                        */
17979   #define ETM_TRCVICTLR_SSSTATUS_Started (0x1UL)     /*!< The start/stop logic is in the started state.                        */
17980 
17981 /* TRCRESET @Bit 10 : Controls whether a trace unit must trace a Reset exception. */
17982   #define ETM_TRCVICTLR_TRCRESET_Pos (10UL)          /*!< Position of TRCRESET field.                                          */
17983   #define ETM_TRCVICTLR_TRCRESET_Msk (0x1UL << ETM_TRCVICTLR_TRCRESET_Pos) /*!< Bit mask of TRCRESET field.                    */
17984   #define ETM_TRCVICTLR_TRCRESET_Min (0x0UL)         /*!< Min enumerator value of TRCRESET field.                              */
17985   #define ETM_TRCVICTLR_TRCRESET_Max (0x1UL)         /*!< Max enumerator value of TRCRESET field.                              */
17986   #define ETM_TRCVICTLR_TRCRESET_Disabled (0x0UL)    /*!< The trace unit does not trace a Reset exception unless it traces the
17987                                                           exception or instruction immediately prior to the Reset exception.*/
17988   #define ETM_TRCVICTLR_TRCRESET_Enabled (0x1UL)     /*!< The trace unit always traces a Reset exception.                      */
17989 
17990 /* TRCERR @Bit 11 : When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. */
17991   #define ETM_TRCVICTLR_TRCERR_Pos (11UL)            /*!< Position of TRCERR field.                                            */
17992   #define ETM_TRCVICTLR_TRCERR_Msk (0x1UL << ETM_TRCVICTLR_TRCERR_Pos) /*!< Bit mask of TRCERR field.                          */
17993   #define ETM_TRCVICTLR_TRCERR_Min (0x0UL)           /*!< Min enumerator value of TRCERR field.                                */
17994   #define ETM_TRCVICTLR_TRCERR_Max (0x1UL)           /*!< Max enumerator value of TRCERR field.                                */
17995   #define ETM_TRCVICTLR_TRCERR_Disabled (0x0UL)      /*!< The trace unit does not trace a System error exception unless it
17996                                                           traces the exception or instruction immediately prior to the System
17997                                                           error exception.*/
17998   #define ETM_TRCVICTLR_TRCERR_Enabled (0x1UL)       /*!< The trace unit always traces a System error exception, regardless of
17999                                                           the value of ViewInst.*/
18000 
18001 /* EXLEVEL0_S @Bit 16 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
18002                         Exception level 0. */
18003 
18004   #define ETM_TRCVICTLR_EXLEVEL0_S_Pos (16UL)        /*!< Position of EXLEVEL0_S field.                                        */
18005   #define ETM_TRCVICTLR_EXLEVEL0_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_S_Pos) /*!< Bit mask of EXLEVEL0_S field.              */
18006   #define ETM_TRCVICTLR_EXLEVEL0_S_Min (0x0UL)       /*!< Min enumerator value of EXLEVEL0_S field.                            */
18007   #define ETM_TRCVICTLR_EXLEVEL0_S_Max (0x1UL)       /*!< Max enumerator value of EXLEVEL0_S field.                            */
18008   #define ETM_TRCVICTLR_EXLEVEL0_S_Disabled (0x1UL)  /*!< The trace unit does not generate instruction trace, in Secure state,
18009                                                           for Exception level 0.*/
18010   #define ETM_TRCVICTLR_EXLEVEL0_S_Enabled (0x0UL)   /*!< The trace unit generates instruction trace, in Secure state, for
18011                                                           Exception level 0.*/
18012 
18013 /* EXLEVEL1_S @Bit 17 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
18014                         Exception level 1. */
18015 
18016   #define ETM_TRCVICTLR_EXLEVEL1_S_Pos (17UL)        /*!< Position of EXLEVEL1_S field.                                        */
18017   #define ETM_TRCVICTLR_EXLEVEL1_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_S_Pos) /*!< Bit mask of EXLEVEL1_S field.              */
18018   #define ETM_TRCVICTLR_EXLEVEL1_S_Min (0x0UL)       /*!< Min enumerator value of EXLEVEL1_S field.                            */
18019   #define ETM_TRCVICTLR_EXLEVEL1_S_Max (0x1UL)       /*!< Max enumerator value of EXLEVEL1_S field.                            */
18020   #define ETM_TRCVICTLR_EXLEVEL1_S_Disabled (0x1UL)  /*!< The trace unit does not generate instruction trace, in Secure state,
18021                                                           for Exception level 1.*/
18022   #define ETM_TRCVICTLR_EXLEVEL1_S_Enabled (0x0UL)   /*!< The trace unit generates instruction trace, in Secure state, for
18023                                                           Exception level 1.*/
18024 
18025 /* EXLEVEL2_S @Bit 18 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
18026                         Exception level 2. */
18027 
18028   #define ETM_TRCVICTLR_EXLEVEL2_S_Pos (18UL)        /*!< Position of EXLEVEL2_S field.                                        */
18029   #define ETM_TRCVICTLR_EXLEVEL2_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_S_Pos) /*!< Bit mask of EXLEVEL2_S field.              */
18030   #define ETM_TRCVICTLR_EXLEVEL2_S_Min (0x0UL)       /*!< Min enumerator value of EXLEVEL2_S field.                            */
18031   #define ETM_TRCVICTLR_EXLEVEL2_S_Max (0x1UL)       /*!< Max enumerator value of EXLEVEL2_S field.                            */
18032   #define ETM_TRCVICTLR_EXLEVEL2_S_Disabled (0x1UL)  /*!< The trace unit does not generate instruction trace, in Secure state,
18033                                                           for Exception level 2.*/
18034   #define ETM_TRCVICTLR_EXLEVEL2_S_Enabled (0x0UL)   /*!< The trace unit generates instruction trace, in Secure state, for
18035                                                           Exception level 2.*/
18036 
18037 /* EXLEVEL3_S @Bit 19 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding
18038                         Exception level 3. */
18039 
18040   #define ETM_TRCVICTLR_EXLEVEL3_S_Pos (19UL)        /*!< Position of EXLEVEL3_S field.                                        */
18041   #define ETM_TRCVICTLR_EXLEVEL3_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_S_Pos) /*!< Bit mask of EXLEVEL3_S field.              */
18042   #define ETM_TRCVICTLR_EXLEVEL3_S_Min (0x0UL)       /*!< Min enumerator value of EXLEVEL3_S field.                            */
18043   #define ETM_TRCVICTLR_EXLEVEL3_S_Max (0x1UL)       /*!< Max enumerator value of EXLEVEL3_S field.                            */
18044   #define ETM_TRCVICTLR_EXLEVEL3_S_Disabled (0x1UL)  /*!< The trace unit does not generate instruction trace, in Secure state,
18045                                                           for Exception level 3.*/
18046   #define ETM_TRCVICTLR_EXLEVEL3_S_Enabled (0x0UL)   /*!< The trace unit generates instruction trace, in Secure state, for
18047                                                           Exception level 3.*/
18048 
18049 /* EXLEVEL0_NS @Bit 20 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
18050                          Exception level 0. */
18051 
18052   #define ETM_TRCVICTLR_EXLEVEL0_NS_Pos (20UL)       /*!< Position of EXLEVEL0_NS field.                                       */
18053   #define ETM_TRCVICTLR_EXLEVEL0_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_NS_Pos) /*!< Bit mask of EXLEVEL0_NS field.           */
18054   #define ETM_TRCVICTLR_EXLEVEL0_NS_Min (0x0UL)      /*!< Min enumerator value of EXLEVEL0_NS field.                           */
18055   #define ETM_TRCVICTLR_EXLEVEL0_NS_Max (0x1UL)      /*!< Max enumerator value of EXLEVEL0_NS field.                           */
18056   #define ETM_TRCVICTLR_EXLEVEL0_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure
18057                                                           state, for Exception level 0.*/
18058   #define ETM_TRCVICTLR_EXLEVEL0_NS_Enabled (0x0UL)  /*!< The trace unit generates instruction trace, in Non-secure state, for
18059                                                           Exception level 0.*/
18060 
18061 /* EXLEVEL1_NS @Bit 21 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
18062                          Exception level 1. */
18063 
18064   #define ETM_TRCVICTLR_EXLEVEL1_NS_Pos (21UL)       /*!< Position of EXLEVEL1_NS field.                                       */
18065   #define ETM_TRCVICTLR_EXLEVEL1_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_NS_Pos) /*!< Bit mask of EXLEVEL1_NS field.           */
18066   #define ETM_TRCVICTLR_EXLEVEL1_NS_Min (0x0UL)      /*!< Min enumerator value of EXLEVEL1_NS field.                           */
18067   #define ETM_TRCVICTLR_EXLEVEL1_NS_Max (0x1UL)      /*!< Max enumerator value of EXLEVEL1_NS field.                           */
18068   #define ETM_TRCVICTLR_EXLEVEL1_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure
18069                                                           state, for Exception level 1.*/
18070   #define ETM_TRCVICTLR_EXLEVEL1_NS_Enabled (0x0UL)  /*!< The trace unit generates instruction trace, in Non-secure state, for
18071                                                           Exception level 1.*/
18072 
18073 /* EXLEVEL2_NS @Bit 22 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
18074                          Exception level 2. */
18075 
18076   #define ETM_TRCVICTLR_EXLEVEL2_NS_Pos (22UL)       /*!< Position of EXLEVEL2_NS field.                                       */
18077   #define ETM_TRCVICTLR_EXLEVEL2_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_NS_Pos) /*!< Bit mask of EXLEVEL2_NS field.           */
18078   #define ETM_TRCVICTLR_EXLEVEL2_NS_Min (0x0UL)      /*!< Min enumerator value of EXLEVEL2_NS field.                           */
18079   #define ETM_TRCVICTLR_EXLEVEL2_NS_Max (0x1UL)      /*!< Max enumerator value of EXLEVEL2_NS field.                           */
18080   #define ETM_TRCVICTLR_EXLEVEL2_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure
18081                                                           state, for Exception level 2.*/
18082   #define ETM_TRCVICTLR_EXLEVEL2_NS_Enabled (0x0UL)  /*!< The trace unit generates instruction trace, in Non-secure state, for
18083                                                           Exception level 2.*/
18084 
18085 /* EXLEVEL3_NS @Bit 23 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding
18086                          Exception level 3. */
18087 
18088   #define ETM_TRCVICTLR_EXLEVEL3_NS_Pos (23UL)       /*!< Position of EXLEVEL3_NS field.                                       */
18089   #define ETM_TRCVICTLR_EXLEVEL3_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_NS_Pos) /*!< Bit mask of EXLEVEL3_NS field.           */
18090   #define ETM_TRCVICTLR_EXLEVEL3_NS_Min (0x0UL)      /*!< Min enumerator value of EXLEVEL3_NS field.                           */
18091   #define ETM_TRCVICTLR_EXLEVEL3_NS_Max (0x1UL)      /*!< Max enumerator value of EXLEVEL3_NS field.                           */
18092   #define ETM_TRCVICTLR_EXLEVEL3_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure
18093                                                           state, for Exception level 3.*/
18094   #define ETM_TRCVICTLR_EXLEVEL3_NS_Enabled (0x0UL)  /*!< The trace unit generates instruction trace, in Non-secure state, for
18095                                                           Exception level 3.*/
18096 
18097 
18098 /* ETM_TRCVIIECTLR: ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must
18099                      be programmed when one or more address comparators are implemented. */
18100 
18101   #define ETM_TRCVIIECTLR_ResetValue (0x00000000UL)  /*!< Reset value of TRCVIIECTLR register.                                 */
18102 
18103 /* INCLUDE0 @Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
18104                      */
18105 
18106   #define ETM_TRCVIIECTLR_INCLUDE0_Pos (0UL)         /*!< Position of INCLUDE0 field.                                          */
18107   #define ETM_TRCVIIECTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field.                */
18108   #define ETM_TRCVIIECTLR_INCLUDE0_Min (0x0UL)       /*!< Min enumerator value of INCLUDE0 field.                              */
18109   #define ETM_TRCVIIECTLR_INCLUDE0_Max (0x1UL)       /*!< Max enumerator value of INCLUDE0 field.                              */
18110   #define ETM_TRCVIIECTLR_INCLUDE0_Disabled (0x0UL)  /*!< The address range that address range comparator pair 0 defines, is not
18111                                                           selected for ViewInst include control.*/
18112   #define ETM_TRCVIIECTLR_INCLUDE0_Enabled (0x1UL)   /*!< The address range that address range comparator pair 0 defines, is
18113                                                           selected for ViewInst include control.*/
18114 
18115 /* INCLUDE1 @Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
18116                      */
18117 
18118   #define ETM_TRCVIIECTLR_INCLUDE1_Pos (1UL)         /*!< Position of INCLUDE1 field.                                          */
18119   #define ETM_TRCVIIECTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field.                */
18120   #define ETM_TRCVIIECTLR_INCLUDE1_Min (0x0UL)       /*!< Min enumerator value of INCLUDE1 field.                              */
18121   #define ETM_TRCVIIECTLR_INCLUDE1_Max (0x1UL)       /*!< Max enumerator value of INCLUDE1 field.                              */
18122   #define ETM_TRCVIIECTLR_INCLUDE1_Disabled (0x0UL)  /*!< The address range that address range comparator pair 1 defines, is not
18123                                                           selected for ViewInst include control.*/
18124   #define ETM_TRCVIIECTLR_INCLUDE1_Enabled (0x1UL)   /*!< The address range that address range comparator pair 1 defines, is
18125                                                           selected for ViewInst include control.*/
18126 
18127 /* INCLUDE2 @Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
18128                      */
18129 
18130   #define ETM_TRCVIIECTLR_INCLUDE2_Pos (2UL)         /*!< Position of INCLUDE2 field.                                          */
18131   #define ETM_TRCVIIECTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field.                */
18132   #define ETM_TRCVIIECTLR_INCLUDE2_Min (0x0UL)       /*!< Min enumerator value of INCLUDE2 field.                              */
18133   #define ETM_TRCVIIECTLR_INCLUDE2_Max (0x1UL)       /*!< Max enumerator value of INCLUDE2 field.                              */
18134   #define ETM_TRCVIIECTLR_INCLUDE2_Disabled (0x0UL)  /*!< The address range that address range comparator pair 2 defines, is not
18135                                                           selected for ViewInst include control.*/
18136   #define ETM_TRCVIIECTLR_INCLUDE2_Enabled (0x1UL)   /*!< The address range that address range comparator pair 2 defines, is
18137                                                           selected for ViewInst include control.*/
18138 
18139 /* INCLUDE3 @Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
18140                      */
18141 
18142   #define ETM_TRCVIIECTLR_INCLUDE3_Pos (3UL)         /*!< Position of INCLUDE3 field.                                          */
18143   #define ETM_TRCVIIECTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field.                */
18144   #define ETM_TRCVIIECTLR_INCLUDE3_Min (0x0UL)       /*!< Min enumerator value of INCLUDE3 field.                              */
18145   #define ETM_TRCVIIECTLR_INCLUDE3_Max (0x1UL)       /*!< Max enumerator value of INCLUDE3 field.                              */
18146   #define ETM_TRCVIIECTLR_INCLUDE3_Disabled (0x0UL)  /*!< The address range that address range comparator pair 3 defines, is not
18147                                                           selected for ViewInst include control.*/
18148   #define ETM_TRCVIIECTLR_INCLUDE3_Enabled (0x1UL)   /*!< The address range that address range comparator pair 3 defines, is
18149                                                           selected for ViewInst include control.*/
18150 
18151 /* INCLUDE4 @Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
18152                      */
18153 
18154   #define ETM_TRCVIIECTLR_INCLUDE4_Pos (4UL)         /*!< Position of INCLUDE4 field.                                          */
18155   #define ETM_TRCVIIECTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field.                */
18156   #define ETM_TRCVIIECTLR_INCLUDE4_Min (0x0UL)       /*!< Min enumerator value of INCLUDE4 field.                              */
18157   #define ETM_TRCVIIECTLR_INCLUDE4_Max (0x1UL)       /*!< Max enumerator value of INCLUDE4 field.                              */
18158   #define ETM_TRCVIIECTLR_INCLUDE4_Disabled (0x0UL)  /*!< The address range that address range comparator pair 4 defines, is not
18159                                                           selected for ViewInst include control.*/
18160   #define ETM_TRCVIIECTLR_INCLUDE4_Enabled (0x1UL)   /*!< The address range that address range comparator pair 4 defines, is
18161                                                           selected for ViewInst include control.*/
18162 
18163 /* INCLUDE5 @Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
18164                      */
18165 
18166   #define ETM_TRCVIIECTLR_INCLUDE5_Pos (5UL)         /*!< Position of INCLUDE5 field.                                          */
18167   #define ETM_TRCVIIECTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field.                */
18168   #define ETM_TRCVIIECTLR_INCLUDE5_Min (0x0UL)       /*!< Min enumerator value of INCLUDE5 field.                              */
18169   #define ETM_TRCVIIECTLR_INCLUDE5_Max (0x1UL)       /*!< Max enumerator value of INCLUDE5 field.                              */
18170   #define ETM_TRCVIIECTLR_INCLUDE5_Disabled (0x0UL)  /*!< The address range that address range comparator pair 5 defines, is not
18171                                                           selected for ViewInst include control.*/
18172   #define ETM_TRCVIIECTLR_INCLUDE5_Enabled (0x1UL)   /*!< The address range that address range comparator pair 5 defines, is
18173                                                           selected for ViewInst include control.*/
18174 
18175 /* INCLUDE6 @Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
18176                      */
18177 
18178   #define ETM_TRCVIIECTLR_INCLUDE6_Pos (6UL)         /*!< Position of INCLUDE6 field.                                          */
18179   #define ETM_TRCVIIECTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field.                */
18180   #define ETM_TRCVIIECTLR_INCLUDE6_Min (0x0UL)       /*!< Min enumerator value of INCLUDE6 field.                              */
18181   #define ETM_TRCVIIECTLR_INCLUDE6_Max (0x1UL)       /*!< Max enumerator value of INCLUDE6 field.                              */
18182   #define ETM_TRCVIIECTLR_INCLUDE6_Disabled (0x0UL)  /*!< The address range that address range comparator pair 6 defines, is not
18183                                                           selected for ViewInst include control.*/
18184   #define ETM_TRCVIIECTLR_INCLUDE6_Enabled (0x1UL)   /*!< The address range that address range comparator pair 6 defines, is
18185                                                           selected for ViewInst include control.*/
18186 
18187 /* INCLUDE7 @Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control.
18188                      */
18189 
18190   #define ETM_TRCVIIECTLR_INCLUDE7_Pos (7UL)         /*!< Position of INCLUDE7 field.                                          */
18191   #define ETM_TRCVIIECTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field.                */
18192   #define ETM_TRCVIIECTLR_INCLUDE7_Min (0x0UL)       /*!< Min enumerator value of INCLUDE7 field.                              */
18193   #define ETM_TRCVIIECTLR_INCLUDE7_Max (0x1UL)       /*!< Max enumerator value of INCLUDE7 field.                              */
18194   #define ETM_TRCVIIECTLR_INCLUDE7_Disabled (0x0UL)  /*!< The address range that address range comparator pair 7 defines, is not
18195                                                           selected for ViewInst include control.*/
18196   #define ETM_TRCVIIECTLR_INCLUDE7_Enabled (0x1UL)   /*!< The address range that address range comparator pair 7 defines, is
18197                                                           selected for ViewInst include control.*/
18198 
18199 /* EXCLUDE0 @Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
18200                       control. */
18201 
18202   #define ETM_TRCVIIECTLR_EXCLUDE0_Pos (16UL)        /*!< Position of EXCLUDE0 field.                                          */
18203   #define ETM_TRCVIIECTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field.                */
18204   #define ETM_TRCVIIECTLR_EXCLUDE0_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE0 field.                              */
18205   #define ETM_TRCVIIECTLR_EXCLUDE0_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE0 field.                              */
18206   #define ETM_TRCVIIECTLR_EXCLUDE0_Disabled (0x0UL)  /*!< The address range that address range comparator pair 0 defines, is not
18207                                                           selected for ViewInst exclude control.*/
18208   #define ETM_TRCVIIECTLR_EXCLUDE0_Enabled (0x1UL)   /*!< The address range that address range comparator pair 0 defines, is
18209                                                           selected for ViewInst exclude control.*/
18210 
18211 /* EXCLUDE1 @Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
18212                       control. */
18213 
18214   #define ETM_TRCVIIECTLR_EXCLUDE1_Pos (17UL)        /*!< Position of EXCLUDE1 field.                                          */
18215   #define ETM_TRCVIIECTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field.                */
18216   #define ETM_TRCVIIECTLR_EXCLUDE1_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE1 field.                              */
18217   #define ETM_TRCVIIECTLR_EXCLUDE1_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE1 field.                              */
18218   #define ETM_TRCVIIECTLR_EXCLUDE1_Disabled (0x0UL)  /*!< The address range that address range comparator pair 1 defines, is not
18219                                                           selected for ViewInst exclude control.*/
18220   #define ETM_TRCVIIECTLR_EXCLUDE1_Enabled (0x1UL)   /*!< The address range that address range comparator pair 1 defines, is
18221                                                           selected for ViewInst exclude control.*/
18222 
18223 /* EXCLUDE2 @Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
18224                       control. */
18225 
18226   #define ETM_TRCVIIECTLR_EXCLUDE2_Pos (18UL)        /*!< Position of EXCLUDE2 field.                                          */
18227   #define ETM_TRCVIIECTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field.                */
18228   #define ETM_TRCVIIECTLR_EXCLUDE2_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE2 field.                              */
18229   #define ETM_TRCVIIECTLR_EXCLUDE2_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE2 field.                              */
18230   #define ETM_TRCVIIECTLR_EXCLUDE2_Disabled (0x0UL)  /*!< The address range that address range comparator pair 2 defines, is not
18231                                                           selected for ViewInst exclude control.*/
18232   #define ETM_TRCVIIECTLR_EXCLUDE2_Enabled (0x1UL)   /*!< The address range that address range comparator pair 2 defines, is
18233                                                           selected for ViewInst exclude control.*/
18234 
18235 /* EXCLUDE3 @Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
18236                       control. */
18237 
18238   #define ETM_TRCVIIECTLR_EXCLUDE3_Pos (19UL)        /*!< Position of EXCLUDE3 field.                                          */
18239   #define ETM_TRCVIIECTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field.                */
18240   #define ETM_TRCVIIECTLR_EXCLUDE3_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE3 field.                              */
18241   #define ETM_TRCVIIECTLR_EXCLUDE3_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE3 field.                              */
18242   #define ETM_TRCVIIECTLR_EXCLUDE3_Disabled (0x0UL)  /*!< The address range that address range comparator pair 3 defines, is not
18243                                                           selected for ViewInst exclude control.*/
18244   #define ETM_TRCVIIECTLR_EXCLUDE3_Enabled (0x1UL)   /*!< The address range that address range comparator pair 3 defines, is
18245                                                           selected for ViewInst exclude control.*/
18246 
18247 /* EXCLUDE4 @Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
18248                       control. */
18249 
18250   #define ETM_TRCVIIECTLR_EXCLUDE4_Pos (20UL)        /*!< Position of EXCLUDE4 field.                                          */
18251   #define ETM_TRCVIIECTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field.                */
18252   #define ETM_TRCVIIECTLR_EXCLUDE4_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE4 field.                              */
18253   #define ETM_TRCVIIECTLR_EXCLUDE4_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE4 field.                              */
18254   #define ETM_TRCVIIECTLR_EXCLUDE4_Disabled (0x0UL)  /*!< The address range that address range comparator pair 4 defines, is not
18255                                                           selected for ViewInst exclude control.*/
18256   #define ETM_TRCVIIECTLR_EXCLUDE4_Enabled (0x1UL)   /*!< The address range that address range comparator pair 4 defines, is
18257                                                           selected for ViewInst exclude control.*/
18258 
18259 /* EXCLUDE5 @Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
18260                       control. */
18261 
18262   #define ETM_TRCVIIECTLR_EXCLUDE5_Pos (21UL)        /*!< Position of EXCLUDE5 field.                                          */
18263   #define ETM_TRCVIIECTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field.                */
18264   #define ETM_TRCVIIECTLR_EXCLUDE5_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE5 field.                              */
18265   #define ETM_TRCVIIECTLR_EXCLUDE5_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE5 field.                              */
18266   #define ETM_TRCVIIECTLR_EXCLUDE5_Disabled (0x0UL)  /*!< The address range that address range comparator pair 5 defines, is not
18267                                                           selected for ViewInst exclude control.*/
18268   #define ETM_TRCVIIECTLR_EXCLUDE5_Enabled (0x1UL)   /*!< The address range that address range comparator pair 5 defines, is
18269                                                           selected for ViewInst exclude control.*/
18270 
18271 /* EXCLUDE6 @Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
18272                       control. */
18273 
18274   #define ETM_TRCVIIECTLR_EXCLUDE6_Pos (22UL)        /*!< Position of EXCLUDE6 field.                                          */
18275   #define ETM_TRCVIIECTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field.                */
18276   #define ETM_TRCVIIECTLR_EXCLUDE6_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE6 field.                              */
18277   #define ETM_TRCVIIECTLR_EXCLUDE6_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE6 field.                              */
18278   #define ETM_TRCVIIECTLR_EXCLUDE6_Disabled (0x0UL)  /*!< The address range that address range comparator pair 6 defines, is not
18279                                                           selected for ViewInst exclude control.*/
18280   #define ETM_TRCVIIECTLR_EXCLUDE6_Enabled (0x1UL)   /*!< The address range that address range comparator pair 6 defines, is
18281                                                           selected for ViewInst exclude control.*/
18282 
18283 /* EXCLUDE7 @Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude
18284                       control. */
18285 
18286   #define ETM_TRCVIIECTLR_EXCLUDE7_Pos (23UL)        /*!< Position of EXCLUDE7 field.                                          */
18287   #define ETM_TRCVIIECTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field.                */
18288   #define ETM_TRCVIIECTLR_EXCLUDE7_Min (0x0UL)       /*!< Min enumerator value of EXCLUDE7 field.                              */
18289   #define ETM_TRCVIIECTLR_EXCLUDE7_Max (0x1UL)       /*!< Max enumerator value of EXCLUDE7 field.                              */
18290   #define ETM_TRCVIIECTLR_EXCLUDE7_Disabled (0x0UL)  /*!< The address range that address range comparator pair 7 defines, is not
18291                                                           selected for ViewInst exclude control.*/
18292   #define ETM_TRCVIIECTLR_EXCLUDE7_Enabled (0x1UL)   /*!< The address range that address range comparator pair 7 defines, is
18293                                                           selected for ViewInst exclude control.*/
18294 
18295 
18296 /* ETM_TRCVISSCTLR: Use this to set, or read, the single address comparators that control the ViewInst start/stop logic. The
18297                      start/stop logic is active for an instruction which causes a start and remains active up to and including
18298                      an instruction which causes a stop, and then the start/stop logic becomes inactive. Might ignore writes
18299                      when the trace unit is enabled or not idle. If implemented then this register must be programmed. */
18300 
18301   #define ETM_TRCVISSCTLR_ResetValue (0x00000000UL)  /*!< Reset value of TRCVISSCTLR register.                                 */
18302 
18303 /* START0 @Bit 0 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18304                    starting trace. */
18305 
18306   #define ETM_TRCVISSCTLR_START0_Pos (0UL)           /*!< Position of START0 field.                                            */
18307   #define ETM_TRCVISSCTLR_START0_Msk (0x1UL << ETM_TRCVISSCTLR_START0_Pos) /*!< Bit mask of START0 field.                      */
18308   #define ETM_TRCVISSCTLR_START0_Min (0x0UL)         /*!< Min enumerator value of START0 field.                                */
18309   #define ETM_TRCVISSCTLR_START0_Max (0x1UL)         /*!< Max enumerator value of START0 field.                                */
18310   #define ETM_TRCVISSCTLR_START0_Disabled (0x0UL)    /*!< The single address comparator 0, is not selected as a start resource.*/
18311   #define ETM_TRCVISSCTLR_START0_Enabled (0x1UL)     /*!< The single address comparator 0, is selected as a start resource.    */
18312 
18313 /* START1 @Bit 1 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18314                    starting trace. */
18315 
18316   #define ETM_TRCVISSCTLR_START1_Pos (1UL)           /*!< Position of START1 field.                                            */
18317   #define ETM_TRCVISSCTLR_START1_Msk (0x1UL << ETM_TRCVISSCTLR_START1_Pos) /*!< Bit mask of START1 field.                      */
18318   #define ETM_TRCVISSCTLR_START1_Min (0x0UL)         /*!< Min enumerator value of START1 field.                                */
18319   #define ETM_TRCVISSCTLR_START1_Max (0x1UL)         /*!< Max enumerator value of START1 field.                                */
18320   #define ETM_TRCVISSCTLR_START1_Disabled (0x0UL)    /*!< The single address comparator 1, is not selected as a start resource.*/
18321   #define ETM_TRCVISSCTLR_START1_Enabled (0x1UL)     /*!< The single address comparator 1, is selected as a start resource.    */
18322 
18323 /* START2 @Bit 2 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18324                    starting trace. */
18325 
18326   #define ETM_TRCVISSCTLR_START2_Pos (2UL)           /*!< Position of START2 field.                                            */
18327   #define ETM_TRCVISSCTLR_START2_Msk (0x1UL << ETM_TRCVISSCTLR_START2_Pos) /*!< Bit mask of START2 field.                      */
18328   #define ETM_TRCVISSCTLR_START2_Min (0x0UL)         /*!< Min enumerator value of START2 field.                                */
18329   #define ETM_TRCVISSCTLR_START2_Max (0x1UL)         /*!< Max enumerator value of START2 field.                                */
18330   #define ETM_TRCVISSCTLR_START2_Disabled (0x0UL)    /*!< The single address comparator 2, is not selected as a start resource.*/
18331   #define ETM_TRCVISSCTLR_START2_Enabled (0x1UL)     /*!< The single address comparator 2, is selected as a start resource.    */
18332 
18333 /* START3 @Bit 3 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18334                    starting trace. */
18335 
18336   #define ETM_TRCVISSCTLR_START3_Pos (3UL)           /*!< Position of START3 field.                                            */
18337   #define ETM_TRCVISSCTLR_START3_Msk (0x1UL << ETM_TRCVISSCTLR_START3_Pos) /*!< Bit mask of START3 field.                      */
18338   #define ETM_TRCVISSCTLR_START3_Min (0x0UL)         /*!< Min enumerator value of START3 field.                                */
18339   #define ETM_TRCVISSCTLR_START3_Max (0x1UL)         /*!< Max enumerator value of START3 field.                                */
18340   #define ETM_TRCVISSCTLR_START3_Disabled (0x0UL)    /*!< The single address comparator 3, is not selected as a start resource.*/
18341   #define ETM_TRCVISSCTLR_START3_Enabled (0x1UL)     /*!< The single address comparator 3, is selected as a start resource.    */
18342 
18343 /* START4 @Bit 4 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18344                    starting trace. */
18345 
18346   #define ETM_TRCVISSCTLR_START4_Pos (4UL)           /*!< Position of START4 field.                                            */
18347   #define ETM_TRCVISSCTLR_START4_Msk (0x1UL << ETM_TRCVISSCTLR_START4_Pos) /*!< Bit mask of START4 field.                      */
18348   #define ETM_TRCVISSCTLR_START4_Min (0x0UL)         /*!< Min enumerator value of START4 field.                                */
18349   #define ETM_TRCVISSCTLR_START4_Max (0x1UL)         /*!< Max enumerator value of START4 field.                                */
18350   #define ETM_TRCVISSCTLR_START4_Disabled (0x0UL)    /*!< The single address comparator 4, is not selected as a start resource.*/
18351   #define ETM_TRCVISSCTLR_START4_Enabled (0x1UL)     /*!< The single address comparator 4, is selected as a start resource.    */
18352 
18353 /* START5 @Bit 5 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18354                    starting trace. */
18355 
18356   #define ETM_TRCVISSCTLR_START5_Pos (5UL)           /*!< Position of START5 field.                                            */
18357   #define ETM_TRCVISSCTLR_START5_Msk (0x1UL << ETM_TRCVISSCTLR_START5_Pos) /*!< Bit mask of START5 field.                      */
18358   #define ETM_TRCVISSCTLR_START5_Min (0x0UL)         /*!< Min enumerator value of START5 field.                                */
18359   #define ETM_TRCVISSCTLR_START5_Max (0x1UL)         /*!< Max enumerator value of START5 field.                                */
18360   #define ETM_TRCVISSCTLR_START5_Disabled (0x0UL)    /*!< The single address comparator 5, is not selected as a start resource.*/
18361   #define ETM_TRCVISSCTLR_START5_Enabled (0x1UL)     /*!< The single address comparator 5, is selected as a start resource.    */
18362 
18363 /* START6 @Bit 6 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18364                    starting trace. */
18365 
18366   #define ETM_TRCVISSCTLR_START6_Pos (6UL)           /*!< Position of START6 field.                                            */
18367   #define ETM_TRCVISSCTLR_START6_Msk (0x1UL << ETM_TRCVISSCTLR_START6_Pos) /*!< Bit mask of START6 field.                      */
18368   #define ETM_TRCVISSCTLR_START6_Min (0x0UL)         /*!< Min enumerator value of START6 field.                                */
18369   #define ETM_TRCVISSCTLR_START6_Max (0x1UL)         /*!< Max enumerator value of START6 field.                                */
18370   #define ETM_TRCVISSCTLR_START6_Disabled (0x0UL)    /*!< The single address comparator 6, is not selected as a start resource.*/
18371   #define ETM_TRCVISSCTLR_START6_Enabled (0x1UL)     /*!< The single address comparator 6, is selected as a start resource.    */
18372 
18373 /* START7 @Bit 7 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18374                    starting trace. */
18375 
18376   #define ETM_TRCVISSCTLR_START7_Pos (7UL)           /*!< Position of START7 field.                                            */
18377   #define ETM_TRCVISSCTLR_START7_Msk (0x1UL << ETM_TRCVISSCTLR_START7_Pos) /*!< Bit mask of START7 field.                      */
18378   #define ETM_TRCVISSCTLR_START7_Min (0x0UL)         /*!< Min enumerator value of START7 field.                                */
18379   #define ETM_TRCVISSCTLR_START7_Max (0x1UL)         /*!< Max enumerator value of START7 field.                                */
18380   #define ETM_TRCVISSCTLR_START7_Disabled (0x0UL)    /*!< The single address comparator 7, is not selected as a start resource.*/
18381   #define ETM_TRCVISSCTLR_START7_Enabled (0x1UL)     /*!< The single address comparator 7, is selected as a start resource.    */
18382 
18383 /* STOP0 @Bit 16 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18384                    stopping trace */
18385 
18386   #define ETM_TRCVISSCTLR_STOP0_Pos (16UL)           /*!< Position of STOP0 field.                                             */
18387   #define ETM_TRCVISSCTLR_STOP0_Msk (0x1UL << ETM_TRCVISSCTLR_STOP0_Pos) /*!< Bit mask of STOP0 field.                         */
18388   #define ETM_TRCVISSCTLR_STOP0_Min (0x0UL)          /*!< Min enumerator value of STOP0 field.                                 */
18389   #define ETM_TRCVISSCTLR_STOP0_Max (0x1UL)          /*!< Max enumerator value of STOP0 field.                                 */
18390   #define ETM_TRCVISSCTLR_STOP0_Disabled (0x0UL)     /*!< The single address comparator 0, is not selected as a stop resource. */
18391   #define ETM_TRCVISSCTLR_STOP0_Enabled (0x1UL)      /*!< The single address comparator 0, is selected as a stop resource.     */
18392 
18393 /* STOP1 @Bit 17 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18394                    stopping trace */
18395 
18396   #define ETM_TRCVISSCTLR_STOP1_Pos (17UL)           /*!< Position of STOP1 field.                                             */
18397   #define ETM_TRCVISSCTLR_STOP1_Msk (0x1UL << ETM_TRCVISSCTLR_STOP1_Pos) /*!< Bit mask of STOP1 field.                         */
18398   #define ETM_TRCVISSCTLR_STOP1_Min (0x0UL)          /*!< Min enumerator value of STOP1 field.                                 */
18399   #define ETM_TRCVISSCTLR_STOP1_Max (0x1UL)          /*!< Max enumerator value of STOP1 field.                                 */
18400   #define ETM_TRCVISSCTLR_STOP1_Disabled (0x0UL)     /*!< The single address comparator 1, is not selected as a stop resource. */
18401   #define ETM_TRCVISSCTLR_STOP1_Enabled (0x1UL)      /*!< The single address comparator 1, is selected as a stop resource.     */
18402 
18403 /* STOP2 @Bit 18 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18404                    stopping trace */
18405 
18406   #define ETM_TRCVISSCTLR_STOP2_Pos (18UL)           /*!< Position of STOP2 field.                                             */
18407   #define ETM_TRCVISSCTLR_STOP2_Msk (0x1UL << ETM_TRCVISSCTLR_STOP2_Pos) /*!< Bit mask of STOP2 field.                         */
18408   #define ETM_TRCVISSCTLR_STOP2_Min (0x0UL)          /*!< Min enumerator value of STOP2 field.                                 */
18409   #define ETM_TRCVISSCTLR_STOP2_Max (0x1UL)          /*!< Max enumerator value of STOP2 field.                                 */
18410   #define ETM_TRCVISSCTLR_STOP2_Disabled (0x0UL)     /*!< The single address comparator 2, is not selected as a stop resource. */
18411   #define ETM_TRCVISSCTLR_STOP2_Enabled (0x1UL)      /*!< The single address comparator 2, is selected as a stop resource.     */
18412 
18413 /* STOP3 @Bit 19 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18414                    stopping trace */
18415 
18416   #define ETM_TRCVISSCTLR_STOP3_Pos (19UL)           /*!< Position of STOP3 field.                                             */
18417   #define ETM_TRCVISSCTLR_STOP3_Msk (0x1UL << ETM_TRCVISSCTLR_STOP3_Pos) /*!< Bit mask of STOP3 field.                         */
18418   #define ETM_TRCVISSCTLR_STOP3_Min (0x0UL)          /*!< Min enumerator value of STOP3 field.                                 */
18419   #define ETM_TRCVISSCTLR_STOP3_Max (0x1UL)          /*!< Max enumerator value of STOP3 field.                                 */
18420   #define ETM_TRCVISSCTLR_STOP3_Disabled (0x0UL)     /*!< The single address comparator 3, is not selected as a stop resource. */
18421   #define ETM_TRCVISSCTLR_STOP3_Enabled (0x1UL)      /*!< The single address comparator 3, is selected as a stop resource.     */
18422 
18423 /* STOP4 @Bit 20 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18424                    stopping trace */
18425 
18426   #define ETM_TRCVISSCTLR_STOP4_Pos (20UL)           /*!< Position of STOP4 field.                                             */
18427   #define ETM_TRCVISSCTLR_STOP4_Msk (0x1UL << ETM_TRCVISSCTLR_STOP4_Pos) /*!< Bit mask of STOP4 field.                         */
18428   #define ETM_TRCVISSCTLR_STOP4_Min (0x0UL)          /*!< Min enumerator value of STOP4 field.                                 */
18429   #define ETM_TRCVISSCTLR_STOP4_Max (0x1UL)          /*!< Max enumerator value of STOP4 field.                                 */
18430   #define ETM_TRCVISSCTLR_STOP4_Disabled (0x0UL)     /*!< The single address comparator 4, is not selected as a stop resource. */
18431   #define ETM_TRCVISSCTLR_STOP4_Enabled (0x1UL)      /*!< The single address comparator 4, is selected as a stop resource.     */
18432 
18433 /* STOP5 @Bit 21 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18434                    stopping trace */
18435 
18436   #define ETM_TRCVISSCTLR_STOP5_Pos (21UL)           /*!< Position of STOP5 field.                                             */
18437   #define ETM_TRCVISSCTLR_STOP5_Msk (0x1UL << ETM_TRCVISSCTLR_STOP5_Pos) /*!< Bit mask of STOP5 field.                         */
18438   #define ETM_TRCVISSCTLR_STOP5_Min (0x0UL)          /*!< Min enumerator value of STOP5 field.                                 */
18439   #define ETM_TRCVISSCTLR_STOP5_Max (0x1UL)          /*!< Max enumerator value of STOP5 field.                                 */
18440   #define ETM_TRCVISSCTLR_STOP5_Disabled (0x0UL)     /*!< The single address comparator 5, is not selected as a stop resource. */
18441   #define ETM_TRCVISSCTLR_STOP5_Enabled (0x1UL)      /*!< The single address comparator 5, is selected as a stop resource.     */
18442 
18443 /* STOP6 @Bit 22 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18444                    stopping trace */
18445 
18446   #define ETM_TRCVISSCTLR_STOP6_Pos (22UL)           /*!< Position of STOP6 field.                                             */
18447   #define ETM_TRCVISSCTLR_STOP6_Msk (0x1UL << ETM_TRCVISSCTLR_STOP6_Pos) /*!< Bit mask of STOP6 field.                         */
18448   #define ETM_TRCVISSCTLR_STOP6_Min (0x0UL)          /*!< Min enumerator value of STOP6 field.                                 */
18449   #define ETM_TRCVISSCTLR_STOP6_Max (0x1UL)          /*!< Max enumerator value of STOP6 field.                                 */
18450   #define ETM_TRCVISSCTLR_STOP6_Disabled (0x0UL)     /*!< The single address comparator 6, is not selected as a stop resource. */
18451   #define ETM_TRCVISSCTLR_STOP6_Enabled (0x1UL)      /*!< The single address comparator 6, is selected as a stop resource.     */
18452 
18453 /* STOP7 @Bit 23 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of
18454                    stopping trace */
18455 
18456   #define ETM_TRCVISSCTLR_STOP7_Pos (23UL)           /*!< Position of STOP7 field.                                             */
18457   #define ETM_TRCVISSCTLR_STOP7_Msk (0x1UL << ETM_TRCVISSCTLR_STOP7_Pos) /*!< Bit mask of STOP7 field.                         */
18458   #define ETM_TRCVISSCTLR_STOP7_Min (0x0UL)          /*!< Min enumerator value of STOP7 field.                                 */
18459   #define ETM_TRCVISSCTLR_STOP7_Max (0x1UL)          /*!< Max enumerator value of STOP7 field.                                 */
18460   #define ETM_TRCVISSCTLR_STOP7_Disabled (0x0UL)     /*!< The single address comparator 7, is not selected as a stop resource. */
18461   #define ETM_TRCVISSCTLR_STOP7_Enabled (0x1UL)      /*!< The single address comparator 7, is selected as a stop resource.     */
18462 
18463 
18464 /* ETM_TRCVIPCSSCTLR: Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might
18465                        ignore writes when the trace unit is enabled or not idle. If implemented then this register must be
18466                        programmed. */
18467 
18468   #define ETM_TRCVIPCSSCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVIPCSSCTLR register.                              */
18469 
18470 /* START0 @Bit 0 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
18471                    trace */
18472 
18473   #define ETM_TRCVIPCSSCTLR_START0_Pos (0UL)         /*!< Position of START0 field.                                            */
18474   #define ETM_TRCVIPCSSCTLR_START0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START0_Pos) /*!< Bit mask of START0 field.                  */
18475   #define ETM_TRCVIPCSSCTLR_START0_Min (0x0UL)       /*!< Min enumerator value of START0 field.                                */
18476   #define ETM_TRCVIPCSSCTLR_START0_Max (0x1UL)       /*!< Max enumerator value of START0 field.                                */
18477   #define ETM_TRCVIPCSSCTLR_START0_Disabled (0x0UL)  /*!< The single PE comparator input 0, is not selected as a start
18478                                                           resource.*/
18479   #define ETM_TRCVIPCSSCTLR_START0_Enabled (0x1UL)   /*!< The single PE comparator input 0, is selected as a start resource.   */
18480 
18481 /* START1 @Bit 1 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
18482                    trace */
18483 
18484   #define ETM_TRCVIPCSSCTLR_START1_Pos (1UL)         /*!< Position of START1 field.                                            */
18485   #define ETM_TRCVIPCSSCTLR_START1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START1_Pos) /*!< Bit mask of START1 field.                  */
18486   #define ETM_TRCVIPCSSCTLR_START1_Min (0x0UL)       /*!< Min enumerator value of START1 field.                                */
18487   #define ETM_TRCVIPCSSCTLR_START1_Max (0x1UL)       /*!< Max enumerator value of START1 field.                                */
18488   #define ETM_TRCVIPCSSCTLR_START1_Disabled (0x0UL)  /*!< The single PE comparator input 1, is not selected as a start
18489                                                           resource.*/
18490   #define ETM_TRCVIPCSSCTLR_START1_Enabled (0x1UL)   /*!< The single PE comparator input 1, is selected as a start resource.   */
18491 
18492 /* START2 @Bit 2 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
18493                    trace */
18494 
18495   #define ETM_TRCVIPCSSCTLR_START2_Pos (2UL)         /*!< Position of START2 field.                                            */
18496   #define ETM_TRCVIPCSSCTLR_START2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START2_Pos) /*!< Bit mask of START2 field.                  */
18497   #define ETM_TRCVIPCSSCTLR_START2_Min (0x0UL)       /*!< Min enumerator value of START2 field.                                */
18498   #define ETM_TRCVIPCSSCTLR_START2_Max (0x1UL)       /*!< Max enumerator value of START2 field.                                */
18499   #define ETM_TRCVIPCSSCTLR_START2_Disabled (0x0UL)  /*!< The single PE comparator input 2, is not selected as a start
18500                                                           resource.*/
18501   #define ETM_TRCVIPCSSCTLR_START2_Enabled (0x1UL)   /*!< The single PE comparator input 2, is selected as a start resource.   */
18502 
18503 /* START3 @Bit 3 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
18504                    trace */
18505 
18506   #define ETM_TRCVIPCSSCTLR_START3_Pos (3UL)         /*!< Position of START3 field.                                            */
18507   #define ETM_TRCVIPCSSCTLR_START3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START3_Pos) /*!< Bit mask of START3 field.                  */
18508   #define ETM_TRCVIPCSSCTLR_START3_Min (0x0UL)       /*!< Min enumerator value of START3 field.                                */
18509   #define ETM_TRCVIPCSSCTLR_START3_Max (0x1UL)       /*!< Max enumerator value of START3 field.                                */
18510   #define ETM_TRCVIPCSSCTLR_START3_Disabled (0x0UL)  /*!< The single PE comparator input 3, is not selected as a start
18511                                                           resource.*/
18512   #define ETM_TRCVIPCSSCTLR_START3_Enabled (0x1UL)   /*!< The single PE comparator input 3, is selected as a start resource.   */
18513 
18514 /* START4 @Bit 4 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
18515                    trace */
18516 
18517   #define ETM_TRCVIPCSSCTLR_START4_Pos (4UL)         /*!< Position of START4 field.                                            */
18518   #define ETM_TRCVIPCSSCTLR_START4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START4_Pos) /*!< Bit mask of START4 field.                  */
18519   #define ETM_TRCVIPCSSCTLR_START4_Min (0x0UL)       /*!< Min enumerator value of START4 field.                                */
18520   #define ETM_TRCVIPCSSCTLR_START4_Max (0x1UL)       /*!< Max enumerator value of START4 field.                                */
18521   #define ETM_TRCVIPCSSCTLR_START4_Disabled (0x0UL)  /*!< The single PE comparator input 4, is not selected as a start
18522                                                           resource.*/
18523   #define ETM_TRCVIPCSSCTLR_START4_Enabled (0x1UL)   /*!< The single PE comparator input 4, is selected as a start resource.   */
18524 
18525 /* START5 @Bit 5 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
18526                    trace */
18527 
18528   #define ETM_TRCVIPCSSCTLR_START5_Pos (5UL)         /*!< Position of START5 field.                                            */
18529   #define ETM_TRCVIPCSSCTLR_START5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START5_Pos) /*!< Bit mask of START5 field.                  */
18530   #define ETM_TRCVIPCSSCTLR_START5_Min (0x0UL)       /*!< Min enumerator value of START5 field.                                */
18531   #define ETM_TRCVIPCSSCTLR_START5_Max (0x1UL)       /*!< Max enumerator value of START5 field.                                */
18532   #define ETM_TRCVIPCSSCTLR_START5_Disabled (0x0UL)  /*!< The single PE comparator input 5, is not selected as a start
18533                                                           resource.*/
18534   #define ETM_TRCVIPCSSCTLR_START5_Enabled (0x1UL)   /*!< The single PE comparator input 5, is selected as a start resource.   */
18535 
18536 /* START6 @Bit 6 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
18537                    trace */
18538 
18539   #define ETM_TRCVIPCSSCTLR_START6_Pos (6UL)         /*!< Position of START6 field.                                            */
18540   #define ETM_TRCVIPCSSCTLR_START6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START6_Pos) /*!< Bit mask of START6 field.                  */
18541   #define ETM_TRCVIPCSSCTLR_START6_Min (0x0UL)       /*!< Min enumerator value of START6 field.                                */
18542   #define ETM_TRCVIPCSSCTLR_START6_Max (0x1UL)       /*!< Max enumerator value of START6 field.                                */
18543   #define ETM_TRCVIPCSSCTLR_START6_Disabled (0x0UL)  /*!< The single PE comparator input 6, is not selected as a start
18544                                                           resource.*/
18545   #define ETM_TRCVIPCSSCTLR_START6_Enabled (0x1UL)   /*!< The single PE comparator input 6, is selected as a start resource.   */
18546 
18547 /* START7 @Bit 7 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting
18548                    trace */
18549 
18550   #define ETM_TRCVIPCSSCTLR_START7_Pos (7UL)         /*!< Position of START7 field.                                            */
18551   #define ETM_TRCVIPCSSCTLR_START7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START7_Pos) /*!< Bit mask of START7 field.                  */
18552   #define ETM_TRCVIPCSSCTLR_START7_Min (0x0UL)       /*!< Min enumerator value of START7 field.                                */
18553   #define ETM_TRCVIPCSSCTLR_START7_Max (0x1UL)       /*!< Max enumerator value of START7 field.                                */
18554   #define ETM_TRCVIPCSSCTLR_START7_Disabled (0x0UL)  /*!< The single PE comparator input 7, is not selected as a start
18555                                                           resource.*/
18556   #define ETM_TRCVIPCSSCTLR_START7_Enabled (0x1UL)   /*!< The single PE comparator input 7, is selected as a start resource.   */
18557 
18558 /* STOP0 @Bit 16 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
18559                    trace. */
18560 
18561   #define ETM_TRCVIPCSSCTLR_STOP0_Pos (16UL)         /*!< Position of STOP0 field.                                             */
18562   #define ETM_TRCVIPCSSCTLR_STOP0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP0_Pos) /*!< Bit mask of STOP0 field.                     */
18563   #define ETM_TRCVIPCSSCTLR_STOP0_Min (0x0UL)        /*!< Min enumerator value of STOP0 field.                                 */
18564   #define ETM_TRCVIPCSSCTLR_STOP0_Max (0x1UL)        /*!< Max enumerator value of STOP0 field.                                 */
18565   #define ETM_TRCVIPCSSCTLR_STOP0_Disabled (0x0UL)   /*!< The single PE comparator input 0, is not selected as a stop resource.*/
18566   #define ETM_TRCVIPCSSCTLR_STOP0_Enabled (0x1UL)    /*!< The single PE comparator input 0, is selected as a stop resource.    */
18567 
18568 /* STOP1 @Bit 17 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
18569                    trace. */
18570 
18571   #define ETM_TRCVIPCSSCTLR_STOP1_Pos (17UL)         /*!< Position of STOP1 field.                                             */
18572   #define ETM_TRCVIPCSSCTLR_STOP1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP1_Pos) /*!< Bit mask of STOP1 field.                     */
18573   #define ETM_TRCVIPCSSCTLR_STOP1_Min (0x0UL)        /*!< Min enumerator value of STOP1 field.                                 */
18574   #define ETM_TRCVIPCSSCTLR_STOP1_Max (0x1UL)        /*!< Max enumerator value of STOP1 field.                                 */
18575   #define ETM_TRCVIPCSSCTLR_STOP1_Disabled (0x0UL)   /*!< The single PE comparator input 1, is not selected as a stop resource.*/
18576   #define ETM_TRCVIPCSSCTLR_STOP1_Enabled (0x1UL)    /*!< The single PE comparator input 1, is selected as a stop resource.    */
18577 
18578 /* STOP2 @Bit 18 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
18579                    trace. */
18580 
18581   #define ETM_TRCVIPCSSCTLR_STOP2_Pos (18UL)         /*!< Position of STOP2 field.                                             */
18582   #define ETM_TRCVIPCSSCTLR_STOP2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP2_Pos) /*!< Bit mask of STOP2 field.                     */
18583   #define ETM_TRCVIPCSSCTLR_STOP2_Min (0x0UL)        /*!< Min enumerator value of STOP2 field.                                 */
18584   #define ETM_TRCVIPCSSCTLR_STOP2_Max (0x1UL)        /*!< Max enumerator value of STOP2 field.                                 */
18585   #define ETM_TRCVIPCSSCTLR_STOP2_Disabled (0x0UL)   /*!< The single PE comparator input 2, is not selected as a stop resource.*/
18586   #define ETM_TRCVIPCSSCTLR_STOP2_Enabled (0x1UL)    /*!< The single PE comparator input 2, is selected as a stop resource.    */
18587 
18588 /* STOP3 @Bit 19 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
18589                    trace. */
18590 
18591   #define ETM_TRCVIPCSSCTLR_STOP3_Pos (19UL)         /*!< Position of STOP3 field.                                             */
18592   #define ETM_TRCVIPCSSCTLR_STOP3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP3_Pos) /*!< Bit mask of STOP3 field.                     */
18593   #define ETM_TRCVIPCSSCTLR_STOP3_Min (0x0UL)        /*!< Min enumerator value of STOP3 field.                                 */
18594   #define ETM_TRCVIPCSSCTLR_STOP3_Max (0x1UL)        /*!< Max enumerator value of STOP3 field.                                 */
18595   #define ETM_TRCVIPCSSCTLR_STOP3_Disabled (0x0UL)   /*!< The single PE comparator input 3, is not selected as a stop resource.*/
18596   #define ETM_TRCVIPCSSCTLR_STOP3_Enabled (0x1UL)    /*!< The single PE comparator input 3, is selected as a stop resource.    */
18597 
18598 /* STOP4 @Bit 20 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
18599                    trace. */
18600 
18601   #define ETM_TRCVIPCSSCTLR_STOP4_Pos (20UL)         /*!< Position of STOP4 field.                                             */
18602   #define ETM_TRCVIPCSSCTLR_STOP4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP4_Pos) /*!< Bit mask of STOP4 field.                     */
18603   #define ETM_TRCVIPCSSCTLR_STOP4_Min (0x0UL)        /*!< Min enumerator value of STOP4 field.                                 */
18604   #define ETM_TRCVIPCSSCTLR_STOP4_Max (0x1UL)        /*!< Max enumerator value of STOP4 field.                                 */
18605   #define ETM_TRCVIPCSSCTLR_STOP4_Disabled (0x0UL)   /*!< The single PE comparator input 4, is not selected as a stop resource.*/
18606   #define ETM_TRCVIPCSSCTLR_STOP4_Enabled (0x1UL)    /*!< The single PE comparator input 4, is selected as a stop resource.    */
18607 
18608 /* STOP5 @Bit 21 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
18609                    trace. */
18610 
18611   #define ETM_TRCVIPCSSCTLR_STOP5_Pos (21UL)         /*!< Position of STOP5 field.                                             */
18612   #define ETM_TRCVIPCSSCTLR_STOP5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP5_Pos) /*!< Bit mask of STOP5 field.                     */
18613   #define ETM_TRCVIPCSSCTLR_STOP5_Min (0x0UL)        /*!< Min enumerator value of STOP5 field.                                 */
18614   #define ETM_TRCVIPCSSCTLR_STOP5_Max (0x1UL)        /*!< Max enumerator value of STOP5 field.                                 */
18615   #define ETM_TRCVIPCSSCTLR_STOP5_Disabled (0x0UL)   /*!< The single PE comparator input 5, is not selected as a stop resource.*/
18616   #define ETM_TRCVIPCSSCTLR_STOP5_Enabled (0x1UL)    /*!< The single PE comparator input 5, is selected as a stop resource.    */
18617 
18618 /* STOP6 @Bit 22 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
18619                    trace. */
18620 
18621   #define ETM_TRCVIPCSSCTLR_STOP6_Pos (22UL)         /*!< Position of STOP6 field.                                             */
18622   #define ETM_TRCVIPCSSCTLR_STOP6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP6_Pos) /*!< Bit mask of STOP6 field.                     */
18623   #define ETM_TRCVIPCSSCTLR_STOP6_Min (0x0UL)        /*!< Min enumerator value of STOP6 field.                                 */
18624   #define ETM_TRCVIPCSSCTLR_STOP6_Max (0x1UL)        /*!< Max enumerator value of STOP6 field.                                 */
18625   #define ETM_TRCVIPCSSCTLR_STOP6_Disabled (0x0UL)   /*!< The single PE comparator input 6, is not selected as a stop resource.*/
18626   #define ETM_TRCVIPCSSCTLR_STOP6_Enabled (0x1UL)    /*!< The single PE comparator input 6, is selected as a stop resource.    */
18627 
18628 /* STOP7 @Bit 23 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping
18629                    trace. */
18630 
18631   #define ETM_TRCVIPCSSCTLR_STOP7_Pos (23UL)         /*!< Position of STOP7 field.                                             */
18632   #define ETM_TRCVIPCSSCTLR_STOP7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP7_Pos) /*!< Bit mask of STOP7 field.                     */
18633   #define ETM_TRCVIPCSSCTLR_STOP7_Min (0x0UL)        /*!< Min enumerator value of STOP7 field.                                 */
18634   #define ETM_TRCVIPCSSCTLR_STOP7_Max (0x1UL)        /*!< Max enumerator value of STOP7 field.                                 */
18635   #define ETM_TRCVIPCSSCTLR_STOP7_Disabled (0x0UL)   /*!< The single PE comparator input 7, is not selected as a stop resource.*/
18636   #define ETM_TRCVIPCSSCTLR_STOP7_Enabled (0x1UL)    /*!< The single PE comparator input 7, is selected as a stop resource.    */
18637 
18638 
18639 /* ETM_TRCVDCTLR: Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register
18640                    must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV ==
18641                    1. */
18642 
18643   #define ETM_TRCVDCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCVDCTLR register.                                   */
18644 
18645 /* EVENT0 @Bit 0 : Event unit enable bit. */
18646   #define ETM_TRCVDCTLR_EVENT0_Pos (0UL)             /*!< Position of EVENT0 field.                                            */
18647   #define ETM_TRCVDCTLR_EVENT0_Msk (0x1UL << ETM_TRCVDCTLR_EVENT0_Pos) /*!< Bit mask of EVENT0 field.                          */
18648   #define ETM_TRCVDCTLR_EVENT0_Min (0x0UL)           /*!< Min enumerator value of EVENT0 field.                                */
18649   #define ETM_TRCVDCTLR_EVENT0_Max (0x1UL)           /*!< Max enumerator value of EVENT0 field.                                */
18650   #define ETM_TRCVDCTLR_EVENT0_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
18651   #define ETM_TRCVDCTLR_EVENT0_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */
18652 
18653 /* EVENT1 @Bit 1 : Event unit enable bit. */
18654   #define ETM_TRCVDCTLR_EVENT1_Pos (1UL)             /*!< Position of EVENT1 field.                                            */
18655   #define ETM_TRCVDCTLR_EVENT1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT1_Pos) /*!< Bit mask of EVENT1 field.                          */
18656   #define ETM_TRCVDCTLR_EVENT1_Min (0x0UL)           /*!< Min enumerator value of EVENT1 field.                                */
18657   #define ETM_TRCVDCTLR_EVENT1_Max (0x1UL)           /*!< Max enumerator value of EVENT1 field.                                */
18658   #define ETM_TRCVDCTLR_EVENT1_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
18659   #define ETM_TRCVDCTLR_EVENT1_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */
18660 
18661 /* EVENT2 @Bit 2 : Event unit enable bit. */
18662   #define ETM_TRCVDCTLR_EVENT2_Pos (2UL)             /*!< Position of EVENT2 field.                                            */
18663   #define ETM_TRCVDCTLR_EVENT2_Msk (0x1UL << ETM_TRCVDCTLR_EVENT2_Pos) /*!< Bit mask of EVENT2 field.                          */
18664   #define ETM_TRCVDCTLR_EVENT2_Min (0x0UL)           /*!< Min enumerator value of EVENT2 field.                                */
18665   #define ETM_TRCVDCTLR_EVENT2_Max (0x1UL)           /*!< Max enumerator value of EVENT2 field.                                */
18666   #define ETM_TRCVDCTLR_EVENT2_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
18667   #define ETM_TRCVDCTLR_EVENT2_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */
18668 
18669 /* EVENT3 @Bit 3 : Event unit enable bit. */
18670   #define ETM_TRCVDCTLR_EVENT3_Pos (3UL)             /*!< Position of EVENT3 field.                                            */
18671   #define ETM_TRCVDCTLR_EVENT3_Msk (0x1UL << ETM_TRCVDCTLR_EVENT3_Pos) /*!< Bit mask of EVENT3 field.                          */
18672   #define ETM_TRCVDCTLR_EVENT3_Min (0x0UL)           /*!< Min enumerator value of EVENT3 field.                                */
18673   #define ETM_TRCVDCTLR_EVENT3_Max (0x1UL)           /*!< Max enumerator value of EVENT3 field.                                */
18674   #define ETM_TRCVDCTLR_EVENT3_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
18675   #define ETM_TRCVDCTLR_EVENT3_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */
18676 
18677 /* EVENT4 @Bit 4 : Event unit enable bit. */
18678   #define ETM_TRCVDCTLR_EVENT4_Pos (4UL)             /*!< Position of EVENT4 field.                                            */
18679   #define ETM_TRCVDCTLR_EVENT4_Msk (0x1UL << ETM_TRCVDCTLR_EVENT4_Pos) /*!< Bit mask of EVENT4 field.                          */
18680   #define ETM_TRCVDCTLR_EVENT4_Min (0x0UL)           /*!< Min enumerator value of EVENT4 field.                                */
18681   #define ETM_TRCVDCTLR_EVENT4_Max (0x1UL)           /*!< Max enumerator value of EVENT4 field.                                */
18682   #define ETM_TRCVDCTLR_EVENT4_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
18683   #define ETM_TRCVDCTLR_EVENT4_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */
18684 
18685 /* EVENT5 @Bit 5 : Event unit enable bit. */
18686   #define ETM_TRCVDCTLR_EVENT5_Pos (5UL)             /*!< Position of EVENT5 field.                                            */
18687   #define ETM_TRCVDCTLR_EVENT5_Msk (0x1UL << ETM_TRCVDCTLR_EVENT5_Pos) /*!< Bit mask of EVENT5 field.                          */
18688   #define ETM_TRCVDCTLR_EVENT5_Min (0x0UL)           /*!< Min enumerator value of EVENT5 field.                                */
18689   #define ETM_TRCVDCTLR_EVENT5_Max (0x1UL)           /*!< Max enumerator value of EVENT5 field.                                */
18690   #define ETM_TRCVDCTLR_EVENT5_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
18691   #define ETM_TRCVDCTLR_EVENT5_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */
18692 
18693 /* EVENT6 @Bit 6 : Event unit enable bit. */
18694   #define ETM_TRCVDCTLR_EVENT6_Pos (6UL)             /*!< Position of EVENT6 field.                                            */
18695   #define ETM_TRCVDCTLR_EVENT6_Msk (0x1UL << ETM_TRCVDCTLR_EVENT6_Pos) /*!< Bit mask of EVENT6 field.                          */
18696   #define ETM_TRCVDCTLR_EVENT6_Min (0x0UL)           /*!< Min enumerator value of EVENT6 field.                                */
18697   #define ETM_TRCVDCTLR_EVENT6_Max (0x1UL)           /*!< Max enumerator value of EVENT6 field.                                */
18698   #define ETM_TRCVDCTLR_EVENT6_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
18699   #define ETM_TRCVDCTLR_EVENT6_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */
18700 
18701 /* EVENT7 @Bit 7 : Event unit enable bit. */
18702   #define ETM_TRCVDCTLR_EVENT7_Pos (7UL)             /*!< Position of EVENT7 field.                                            */
18703   #define ETM_TRCVDCTLR_EVENT7_Msk (0x1UL << ETM_TRCVDCTLR_EVENT7_Pos) /*!< Bit mask of EVENT7 field.                          */
18704   #define ETM_TRCVDCTLR_EVENT7_Min (0x0UL)           /*!< Min enumerator value of EVENT7 field.                                */
18705   #define ETM_TRCVDCTLR_EVENT7_Max (0x1UL)           /*!< Max enumerator value of EVENT7 field.                                */
18706   #define ETM_TRCVDCTLR_EVENT7_Disabled (0x0UL)      /*!< The trace event is not selected for trace filtering.                 */
18707   #define ETM_TRCVDCTLR_EVENT7_Enabled (0x1UL)       /*!< The trace event is selected for trace filtering.                     */
18708 
18709 /* SPREL @Bits 8..9 : Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). */
18710   #define ETM_TRCVDCTLR_SPREL_Pos (8UL)              /*!< Position of SPREL field.                                             */
18711   #define ETM_TRCVDCTLR_SPREL_Msk (0x3UL << ETM_TRCVDCTLR_SPREL_Pos) /*!< Bit mask of SPREL field.                             */
18712   #define ETM_TRCVDCTLR_SPREL_Min (0x0UL)            /*!< Min enumerator value of SPREL field.                                 */
18713   #define ETM_TRCVDCTLR_SPREL_Max (0x3UL)            /*!< Max enumerator value of SPREL field.                                 */
18714   #define ETM_TRCVDCTLR_SPREL_Enabled (0x0UL)        /*!< The trace unit does not affect the tracing of SP-relative transfers. */
18715   #define ETM_TRCVDCTLR_SPREL_DataOnly (0x2UL)       /*!< The trace unit does not trace the address portion of SP-relative
18716                                                           transfers. If data value tracing is enabled then the trace unit
18717                                                           generates a P1 data address element.*/
18718   #define ETM_TRCVDCTLR_SPREL_Disabled (0x3UL)       /*!< The trace unit does not trace the address or value portions of
18719                                                           SP-relative transfers.*/
18720 
18721 /* PCREL @Bit 10 : Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). */
18722   #define ETM_TRCVDCTLR_PCREL_Pos (10UL)             /*!< Position of PCREL field.                                             */
18723   #define ETM_TRCVDCTLR_PCREL_Msk (0x1UL << ETM_TRCVDCTLR_PCREL_Pos) /*!< Bit mask of PCREL field.                             */
18724   #define ETM_TRCVDCTLR_PCREL_Min (0x0UL)            /*!< Min enumerator value of PCREL field.                                 */
18725   #define ETM_TRCVDCTLR_PCREL_Max (0x1UL)            /*!< Max enumerator value of PCREL field.                                 */
18726   #define ETM_TRCVDCTLR_PCREL_Enabled (0x0UL)        /*!< The trace unit does not affect the tracing of PC-relative transfers. */
18727   #define ETM_TRCVDCTLR_PCREL_Disabled (0x1UL)       /*!< The trace unit does not trace the address or value portions of
18728                                                           PC-relative transfers.*/
18729 
18730 /* TBI @Bit 11 : Controls which information a trace unit populates in bits[63:56] of the data address. */
18731   #define ETM_TRCVDCTLR_TBI_Pos (11UL)               /*!< Position of TBI field.                                               */
18732   #define ETM_TRCVDCTLR_TBI_Msk (0x1UL << ETM_TRCVDCTLR_TBI_Pos) /*!< Bit mask of TBI field.                                   */
18733   #define ETM_TRCVDCTLR_TBI_Min (0x0UL)              /*!< Min enumerator value of TBI field.                                   */
18734   #define ETM_TRCVDCTLR_TBI_Max (0x1UL)              /*!< Max enumerator value of TBI field.                                   */
18735   #define ETM_TRCVDCTLR_TBI_SignExtend (0x0UL)       /*!< The trace unit assigns bits[63:56] to have the same value as bit[55]
18736                                                           of the data address, that is, it sign-extends the value.*/
18737   #define ETM_TRCVDCTLR_TBI_Copy (0x1UL)             /*!< The trace unit assigns bits[63:56] to have the same value as
18738                                                           bits[63:56] of the data address.*/
18739 
18740 /* TRCEXDATA @Bit 12 : Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and
18741                        Armv8-M PEs. */
18742 
18743   #define ETM_TRCVDCTLR_TRCEXDATA_Pos (12UL)         /*!< Position of TRCEXDATA field.                                         */
18744   #define ETM_TRCVDCTLR_TRCEXDATA_Msk (0x1UL << ETM_TRCVDCTLR_TRCEXDATA_Pos) /*!< Bit mask of TRCEXDATA field.                 */
18745   #define ETM_TRCVDCTLR_TRCEXDATA_Min (0x0UL)        /*!< Min enumerator value of TRCEXDATA field.                             */
18746   #define ETM_TRCVDCTLR_TRCEXDATA_Max (0x1UL)        /*!< Max enumerator value of TRCEXDATA field.                             */
18747   #define ETM_TRCVDCTLR_TRCEXDATA_Disabled (0x0UL)   /*!< Exception and exception return data transfers are not traced.        */
18748   #define ETM_TRCVDCTLR_TRCEXDATA_Enabled (0x1UL)    /*!< Exception and exception return data transfers are traced if the other
18749                                                           aspects of ViewData indicate that the data transfers must be traced.*/
18750 
18751 
18752 /* ETM_TRCVDSACCTLR: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This
18753                       register must be programmed when one or more address comparators are implemented. */
18754 
18755   #define ETM_TRCVDSACCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDSACCTLR register.                                */
18756 
18757 /* INCLUDE0 @Bit 0 : Selects which single address comparators are in use with ViewData include control. */
18758   #define ETM_TRCVDSACCTLR_INCLUDE0_Pos (0UL)        /*!< Position of INCLUDE0 field.                                          */
18759   #define ETM_TRCVDSACCTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field.              */
18760   #define ETM_TRCVDSACCTLR_INCLUDE0_Min (0x0UL)      /*!< Min enumerator value of INCLUDE0 field.                              */
18761   #define ETM_TRCVDSACCTLR_INCLUDE0_Max (0x1UL)      /*!< Max enumerator value of INCLUDE0 field.                              */
18762   #define ETM_TRCVDSACCTLR_INCLUDE0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData include
18763                                                           control.*/
18764   #define ETM_TRCVDSACCTLR_INCLUDE0_Enabled (0x1UL)  /*!< The single address comparator 0, is selected for ViewData include
18765                                                           control.*/
18766 
18767 /* INCLUDE1 @Bit 1 : Selects which single address comparators are in use with ViewData include control. */
18768   #define ETM_TRCVDSACCTLR_INCLUDE1_Pos (1UL)        /*!< Position of INCLUDE1 field.                                          */
18769   #define ETM_TRCVDSACCTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field.              */
18770   #define ETM_TRCVDSACCTLR_INCLUDE1_Min (0x0UL)      /*!< Min enumerator value of INCLUDE1 field.                              */
18771   #define ETM_TRCVDSACCTLR_INCLUDE1_Max (0x1UL)      /*!< Max enumerator value of INCLUDE1 field.                              */
18772   #define ETM_TRCVDSACCTLR_INCLUDE1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData include
18773                                                           control.*/
18774   #define ETM_TRCVDSACCTLR_INCLUDE1_Enabled (0x1UL)  /*!< The single address comparator 1, is selected for ViewData include
18775                                                           control.*/
18776 
18777 /* INCLUDE2 @Bit 2 : Selects which single address comparators are in use with ViewData include control. */
18778   #define ETM_TRCVDSACCTLR_INCLUDE2_Pos (2UL)        /*!< Position of INCLUDE2 field.                                          */
18779   #define ETM_TRCVDSACCTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field.              */
18780   #define ETM_TRCVDSACCTLR_INCLUDE2_Min (0x0UL)      /*!< Min enumerator value of INCLUDE2 field.                              */
18781   #define ETM_TRCVDSACCTLR_INCLUDE2_Max (0x1UL)      /*!< Max enumerator value of INCLUDE2 field.                              */
18782   #define ETM_TRCVDSACCTLR_INCLUDE2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData include
18783                                                           control.*/
18784   #define ETM_TRCVDSACCTLR_INCLUDE2_Enabled (0x1UL)  /*!< The single address comparator 2, is selected for ViewData include
18785                                                           control.*/
18786 
18787 /* INCLUDE3 @Bit 3 : Selects which single address comparators are in use with ViewData include control. */
18788   #define ETM_TRCVDSACCTLR_INCLUDE3_Pos (3UL)        /*!< Position of INCLUDE3 field.                                          */
18789   #define ETM_TRCVDSACCTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field.              */
18790   #define ETM_TRCVDSACCTLR_INCLUDE3_Min (0x0UL)      /*!< Min enumerator value of INCLUDE3 field.                              */
18791   #define ETM_TRCVDSACCTLR_INCLUDE3_Max (0x1UL)      /*!< Max enumerator value of INCLUDE3 field.                              */
18792   #define ETM_TRCVDSACCTLR_INCLUDE3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData include
18793                                                           control.*/
18794   #define ETM_TRCVDSACCTLR_INCLUDE3_Enabled (0x1UL)  /*!< The single address comparator 3, is selected for ViewData include
18795                                                           control.*/
18796 
18797 /* INCLUDE4 @Bit 4 : Selects which single address comparators are in use with ViewData include control. */
18798   #define ETM_TRCVDSACCTLR_INCLUDE4_Pos (4UL)        /*!< Position of INCLUDE4 field.                                          */
18799   #define ETM_TRCVDSACCTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field.              */
18800   #define ETM_TRCVDSACCTLR_INCLUDE4_Min (0x0UL)      /*!< Min enumerator value of INCLUDE4 field.                              */
18801   #define ETM_TRCVDSACCTLR_INCLUDE4_Max (0x1UL)      /*!< Max enumerator value of INCLUDE4 field.                              */
18802   #define ETM_TRCVDSACCTLR_INCLUDE4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData include
18803                                                           control.*/
18804   #define ETM_TRCVDSACCTLR_INCLUDE4_Enabled (0x1UL)  /*!< The single address comparator 4, is selected for ViewData include
18805                                                           control.*/
18806 
18807 /* INCLUDE5 @Bit 5 : Selects which single address comparators are in use with ViewData include control. */
18808   #define ETM_TRCVDSACCTLR_INCLUDE5_Pos (5UL)        /*!< Position of INCLUDE5 field.                                          */
18809   #define ETM_TRCVDSACCTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field.              */
18810   #define ETM_TRCVDSACCTLR_INCLUDE5_Min (0x0UL)      /*!< Min enumerator value of INCLUDE5 field.                              */
18811   #define ETM_TRCVDSACCTLR_INCLUDE5_Max (0x1UL)      /*!< Max enumerator value of INCLUDE5 field.                              */
18812   #define ETM_TRCVDSACCTLR_INCLUDE5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData include
18813                                                           control.*/
18814   #define ETM_TRCVDSACCTLR_INCLUDE5_Enabled (0x1UL)  /*!< The single address comparator 5, is selected for ViewData include
18815                                                           control.*/
18816 
18817 /* INCLUDE6 @Bit 6 : Selects which single address comparators are in use with ViewData include control. */
18818   #define ETM_TRCVDSACCTLR_INCLUDE6_Pos (6UL)        /*!< Position of INCLUDE6 field.                                          */
18819   #define ETM_TRCVDSACCTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field.              */
18820   #define ETM_TRCVDSACCTLR_INCLUDE6_Min (0x0UL)      /*!< Min enumerator value of INCLUDE6 field.                              */
18821   #define ETM_TRCVDSACCTLR_INCLUDE6_Max (0x1UL)      /*!< Max enumerator value of INCLUDE6 field.                              */
18822   #define ETM_TRCVDSACCTLR_INCLUDE6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData include
18823                                                           control.*/
18824   #define ETM_TRCVDSACCTLR_INCLUDE6_Enabled (0x1UL)  /*!< The single address comparator 6, is selected for ViewData include
18825                                                           control.*/
18826 
18827 /* INCLUDE7 @Bit 7 : Selects which single address comparators are in use with ViewData include control. */
18828   #define ETM_TRCVDSACCTLR_INCLUDE7_Pos (7UL)        /*!< Position of INCLUDE7 field.                                          */
18829   #define ETM_TRCVDSACCTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field.              */
18830   #define ETM_TRCVDSACCTLR_INCLUDE7_Min (0x0UL)      /*!< Min enumerator value of INCLUDE7 field.                              */
18831   #define ETM_TRCVDSACCTLR_INCLUDE7_Max (0x1UL)      /*!< Max enumerator value of INCLUDE7 field.                              */
18832   #define ETM_TRCVDSACCTLR_INCLUDE7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData include
18833                                                           control.*/
18834   #define ETM_TRCVDSACCTLR_INCLUDE7_Enabled (0x1UL)  /*!< The single address comparator 7, is selected for ViewData include
18835                                                           control.*/
18836 
18837 /* EXCLUDE0 @Bit 16 : Selects which single address comparators are in use with ViewData exclude control. */
18838   #define ETM_TRCVDSACCTLR_EXCLUDE0_Pos (16UL)       /*!< Position of EXCLUDE0 field.                                          */
18839   #define ETM_TRCVDSACCTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field.              */
18840   #define ETM_TRCVDSACCTLR_EXCLUDE0_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE0 field.                              */
18841   #define ETM_TRCVDSACCTLR_EXCLUDE0_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE0 field.                              */
18842   #define ETM_TRCVDSACCTLR_EXCLUDE0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData exclude
18843                                                           control.*/
18844   #define ETM_TRCVDSACCTLR_EXCLUDE0_Enabled (0x1UL)  /*!< The single address comparator 0, s selected for ViewData exclude
18845                                                           control.*/
18846 
18847 /* EXCLUDE1 @Bit 17 : Selects which single address comparators are in use with ViewData exclude control. */
18848   #define ETM_TRCVDSACCTLR_EXCLUDE1_Pos (17UL)       /*!< Position of EXCLUDE1 field.                                          */
18849   #define ETM_TRCVDSACCTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field.              */
18850   #define ETM_TRCVDSACCTLR_EXCLUDE1_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE1 field.                              */
18851   #define ETM_TRCVDSACCTLR_EXCLUDE1_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE1 field.                              */
18852   #define ETM_TRCVDSACCTLR_EXCLUDE1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData exclude
18853                                                           control.*/
18854   #define ETM_TRCVDSACCTLR_EXCLUDE1_Enabled (0x1UL)  /*!< The single address comparator 1, s selected for ViewData exclude
18855                                                           control.*/
18856 
18857 /* EXCLUDE2 @Bit 18 : Selects which single address comparators are in use with ViewData exclude control. */
18858   #define ETM_TRCVDSACCTLR_EXCLUDE2_Pos (18UL)       /*!< Position of EXCLUDE2 field.                                          */
18859   #define ETM_TRCVDSACCTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field.              */
18860   #define ETM_TRCVDSACCTLR_EXCLUDE2_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE2 field.                              */
18861   #define ETM_TRCVDSACCTLR_EXCLUDE2_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE2 field.                              */
18862   #define ETM_TRCVDSACCTLR_EXCLUDE2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData exclude
18863                                                           control.*/
18864   #define ETM_TRCVDSACCTLR_EXCLUDE2_Enabled (0x1UL)  /*!< The single address comparator 2, s selected for ViewData exclude
18865                                                           control.*/
18866 
18867 /* EXCLUDE3 @Bit 19 : Selects which single address comparators are in use with ViewData exclude control. */
18868   #define ETM_TRCVDSACCTLR_EXCLUDE3_Pos (19UL)       /*!< Position of EXCLUDE3 field.                                          */
18869   #define ETM_TRCVDSACCTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field.              */
18870   #define ETM_TRCVDSACCTLR_EXCLUDE3_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE3 field.                              */
18871   #define ETM_TRCVDSACCTLR_EXCLUDE3_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE3 field.                              */
18872   #define ETM_TRCVDSACCTLR_EXCLUDE3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData exclude
18873                                                           control.*/
18874   #define ETM_TRCVDSACCTLR_EXCLUDE3_Enabled (0x1UL)  /*!< The single address comparator 3, s selected for ViewData exclude
18875                                                           control.*/
18876 
18877 /* EXCLUDE4 @Bit 20 : Selects which single address comparators are in use with ViewData exclude control. */
18878   #define ETM_TRCVDSACCTLR_EXCLUDE4_Pos (20UL)       /*!< Position of EXCLUDE4 field.                                          */
18879   #define ETM_TRCVDSACCTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field.              */
18880   #define ETM_TRCVDSACCTLR_EXCLUDE4_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE4 field.                              */
18881   #define ETM_TRCVDSACCTLR_EXCLUDE4_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE4 field.                              */
18882   #define ETM_TRCVDSACCTLR_EXCLUDE4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData exclude
18883                                                           control.*/
18884   #define ETM_TRCVDSACCTLR_EXCLUDE4_Enabled (0x1UL)  /*!< The single address comparator 4, s selected for ViewData exclude
18885                                                           control.*/
18886 
18887 /* EXCLUDE5 @Bit 21 : Selects which single address comparators are in use with ViewData exclude control. */
18888   #define ETM_TRCVDSACCTLR_EXCLUDE5_Pos (21UL)       /*!< Position of EXCLUDE5 field.                                          */
18889   #define ETM_TRCVDSACCTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field.              */
18890   #define ETM_TRCVDSACCTLR_EXCLUDE5_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE5 field.                              */
18891   #define ETM_TRCVDSACCTLR_EXCLUDE5_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE5 field.                              */
18892   #define ETM_TRCVDSACCTLR_EXCLUDE5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData exclude
18893                                                           control.*/
18894   #define ETM_TRCVDSACCTLR_EXCLUDE5_Enabled (0x1UL)  /*!< The single address comparator 5, s selected for ViewData exclude
18895                                                           control.*/
18896 
18897 /* EXCLUDE6 @Bit 22 : Selects which single address comparators are in use with ViewData exclude control. */
18898   #define ETM_TRCVDSACCTLR_EXCLUDE6_Pos (22UL)       /*!< Position of EXCLUDE6 field.                                          */
18899   #define ETM_TRCVDSACCTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field.              */
18900   #define ETM_TRCVDSACCTLR_EXCLUDE6_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE6 field.                              */
18901   #define ETM_TRCVDSACCTLR_EXCLUDE6_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE6 field.                              */
18902   #define ETM_TRCVDSACCTLR_EXCLUDE6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData exclude
18903                                                           control.*/
18904   #define ETM_TRCVDSACCTLR_EXCLUDE6_Enabled (0x1UL)  /*!< The single address comparator 6, s selected for ViewData exclude
18905                                                           control.*/
18906 
18907 /* EXCLUDE7 @Bit 23 : Selects which single address comparators are in use with ViewData exclude control. */
18908   #define ETM_TRCVDSACCTLR_EXCLUDE7_Pos (23UL)       /*!< Position of EXCLUDE7 field.                                          */
18909   #define ETM_TRCVDSACCTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field.              */
18910   #define ETM_TRCVDSACCTLR_EXCLUDE7_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE7 field.                              */
18911   #define ETM_TRCVDSACCTLR_EXCLUDE7_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE7 field.                              */
18912   #define ETM_TRCVDSACCTLR_EXCLUDE7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData exclude
18913                                                           control.*/
18914   #define ETM_TRCVDSACCTLR_EXCLUDE7_Enabled (0x1UL)  /*!< The single address comparator 7, s selected for ViewData exclude
18915                                                           control.*/
18916 
18917 
18918 /* ETM_TRCVDARCCTLR: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This
18919                       register must be programmed when one or more address comparators are implemented. */
18920 
18921   #define ETM_TRCVDARCCTLR_ResetValue (0x00000000UL) /*!< Reset value of TRCVDARCCTLR register.                                */
18922 
18923 /* INCLUDE0 @Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
18924                      */
18925 
18926   #define ETM_TRCVDARCCTLR_INCLUDE0_Pos (0UL)        /*!< Position of INCLUDE0 field.                                          */
18927   #define ETM_TRCVDARCCTLR_INCLUDE0_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE0_Pos) /*!< Bit mask of INCLUDE0 field.              */
18928   #define ETM_TRCVDARCCTLR_INCLUDE0_Min (0x0UL)      /*!< Min enumerator value of INCLUDE0 field.                              */
18929   #define ETM_TRCVDARCCTLR_INCLUDE0_Max (0x1UL)      /*!< Max enumerator value of INCLUDE0 field.                              */
18930   #define ETM_TRCVDARCCTLR_INCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not
18931                                                           selected for ViewData include control.*/
18932   #define ETM_TRCVDARCCTLR_INCLUDE0_Enabled (0x1UL)  /*!< The address range that address range comparator 0 defines, is selected
18933                                                           for ViewData include control.*/
18934 
18935 /* INCLUDE1 @Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
18936                      */
18937 
18938   #define ETM_TRCVDARCCTLR_INCLUDE1_Pos (1UL)        /*!< Position of INCLUDE1 field.                                          */
18939   #define ETM_TRCVDARCCTLR_INCLUDE1_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE1_Pos) /*!< Bit mask of INCLUDE1 field.              */
18940   #define ETM_TRCVDARCCTLR_INCLUDE1_Min (0x0UL)      /*!< Min enumerator value of INCLUDE1 field.                              */
18941   #define ETM_TRCVDARCCTLR_INCLUDE1_Max (0x1UL)      /*!< Max enumerator value of INCLUDE1 field.                              */
18942   #define ETM_TRCVDARCCTLR_INCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not
18943                                                           selected for ViewData include control.*/
18944   #define ETM_TRCVDARCCTLR_INCLUDE1_Enabled (0x1UL)  /*!< The address range that address range comparator 1 defines, is selected
18945                                                           for ViewData include control.*/
18946 
18947 /* INCLUDE2 @Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
18948                      */
18949 
18950   #define ETM_TRCVDARCCTLR_INCLUDE2_Pos (2UL)        /*!< Position of INCLUDE2 field.                                          */
18951   #define ETM_TRCVDARCCTLR_INCLUDE2_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE2_Pos) /*!< Bit mask of INCLUDE2 field.              */
18952   #define ETM_TRCVDARCCTLR_INCLUDE2_Min (0x0UL)      /*!< Min enumerator value of INCLUDE2 field.                              */
18953   #define ETM_TRCVDARCCTLR_INCLUDE2_Max (0x1UL)      /*!< Max enumerator value of INCLUDE2 field.                              */
18954   #define ETM_TRCVDARCCTLR_INCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not
18955                                                           selected for ViewData include control.*/
18956   #define ETM_TRCVDARCCTLR_INCLUDE2_Enabled (0x1UL)  /*!< The address range that address range comparator 2 defines, is selected
18957                                                           for ViewData include control.*/
18958 
18959 /* INCLUDE3 @Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
18960                      */
18961 
18962   #define ETM_TRCVDARCCTLR_INCLUDE3_Pos (3UL)        /*!< Position of INCLUDE3 field.                                          */
18963   #define ETM_TRCVDARCCTLR_INCLUDE3_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE3_Pos) /*!< Bit mask of INCLUDE3 field.              */
18964   #define ETM_TRCVDARCCTLR_INCLUDE3_Min (0x0UL)      /*!< Min enumerator value of INCLUDE3 field.                              */
18965   #define ETM_TRCVDARCCTLR_INCLUDE3_Max (0x1UL)      /*!< Max enumerator value of INCLUDE3 field.                              */
18966   #define ETM_TRCVDARCCTLR_INCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not
18967                                                           selected for ViewData include control.*/
18968   #define ETM_TRCVDARCCTLR_INCLUDE3_Enabled (0x1UL)  /*!< The address range that address range comparator 3 defines, is selected
18969                                                           for ViewData include control.*/
18970 
18971 /* INCLUDE4 @Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
18972                      */
18973 
18974   #define ETM_TRCVDARCCTLR_INCLUDE4_Pos (4UL)        /*!< Position of INCLUDE4 field.                                          */
18975   #define ETM_TRCVDARCCTLR_INCLUDE4_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE4_Pos) /*!< Bit mask of INCLUDE4 field.              */
18976   #define ETM_TRCVDARCCTLR_INCLUDE4_Min (0x0UL)      /*!< Min enumerator value of INCLUDE4 field.                              */
18977   #define ETM_TRCVDARCCTLR_INCLUDE4_Max (0x1UL)      /*!< Max enumerator value of INCLUDE4 field.                              */
18978   #define ETM_TRCVDARCCTLR_INCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not
18979                                                           selected for ViewData include control.*/
18980   #define ETM_TRCVDARCCTLR_INCLUDE4_Enabled (0x1UL)  /*!< The address range that address range comparator 4 defines, is selected
18981                                                           for ViewData include control.*/
18982 
18983 /* INCLUDE5 @Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
18984                      */
18985 
18986   #define ETM_TRCVDARCCTLR_INCLUDE5_Pos (5UL)        /*!< Position of INCLUDE5 field.                                          */
18987   #define ETM_TRCVDARCCTLR_INCLUDE5_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE5_Pos) /*!< Bit mask of INCLUDE5 field.              */
18988   #define ETM_TRCVDARCCTLR_INCLUDE5_Min (0x0UL)      /*!< Min enumerator value of INCLUDE5 field.                              */
18989   #define ETM_TRCVDARCCTLR_INCLUDE5_Max (0x1UL)      /*!< Max enumerator value of INCLUDE5 field.                              */
18990   #define ETM_TRCVDARCCTLR_INCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not
18991                                                           selected for ViewData include control.*/
18992   #define ETM_TRCVDARCCTLR_INCLUDE5_Enabled (0x1UL)  /*!< The address range that address range comparator 5 defines, is selected
18993                                                           for ViewData include control.*/
18994 
18995 /* INCLUDE6 @Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
18996                      */
18997 
18998   #define ETM_TRCVDARCCTLR_INCLUDE6_Pos (6UL)        /*!< Position of INCLUDE6 field.                                          */
18999   #define ETM_TRCVDARCCTLR_INCLUDE6_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE6_Pos) /*!< Bit mask of INCLUDE6 field.              */
19000   #define ETM_TRCVDARCCTLR_INCLUDE6_Min (0x0UL)      /*!< Min enumerator value of INCLUDE6 field.                              */
19001   #define ETM_TRCVDARCCTLR_INCLUDE6_Max (0x1UL)      /*!< Max enumerator value of INCLUDE6 field.                              */
19002   #define ETM_TRCVDARCCTLR_INCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not
19003                                                           selected for ViewData include control.*/
19004   #define ETM_TRCVDARCCTLR_INCLUDE6_Enabled (0x1UL)  /*!< The address range that address range comparator 6 defines, is selected
19005                                                           for ViewData include control.*/
19006 
19007 /* INCLUDE7 @Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewData include control.
19008                      */
19009 
19010   #define ETM_TRCVDARCCTLR_INCLUDE7_Pos (7UL)        /*!< Position of INCLUDE7 field.                                          */
19011   #define ETM_TRCVDARCCTLR_INCLUDE7_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE7_Pos) /*!< Bit mask of INCLUDE7 field.              */
19012   #define ETM_TRCVDARCCTLR_INCLUDE7_Min (0x0UL)      /*!< Min enumerator value of INCLUDE7 field.                              */
19013   #define ETM_TRCVDARCCTLR_INCLUDE7_Max (0x1UL)      /*!< Max enumerator value of INCLUDE7 field.                              */
19014   #define ETM_TRCVDARCCTLR_INCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not
19015                                                           selected for ViewData include control.*/
19016   #define ETM_TRCVDARCCTLR_INCLUDE7_Enabled (0x1UL)  /*!< The address range that address range comparator 7 defines, is selected
19017                                                           for ViewData include control.*/
19018 
19019 /* EXCLUDE0 @Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
19020                       control. */
19021 
19022   #define ETM_TRCVDARCCTLR_EXCLUDE0_Pos (16UL)       /*!< Position of EXCLUDE0 field.                                          */
19023   #define ETM_TRCVDARCCTLR_EXCLUDE0_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE0_Pos) /*!< Bit mask of EXCLUDE0 field.              */
19024   #define ETM_TRCVDARCCTLR_EXCLUDE0_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE0 field.                              */
19025   #define ETM_TRCVDARCCTLR_EXCLUDE0_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE0 field.                              */
19026   #define ETM_TRCVDARCCTLR_EXCLUDE0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not
19027                                                           selected for ViewData exclude control.*/
19028   #define ETM_TRCVDARCCTLR_EXCLUDE0_Enabled (0x1UL)  /*!< The address range that address range comparator 0 defines, s selected
19029                                                           for ViewData exclude control.*/
19030 
19031 /* EXCLUDE1 @Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
19032                       control. */
19033 
19034   #define ETM_TRCVDARCCTLR_EXCLUDE1_Pos (17UL)       /*!< Position of EXCLUDE1 field.                                          */
19035   #define ETM_TRCVDARCCTLR_EXCLUDE1_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE1_Pos) /*!< Bit mask of EXCLUDE1 field.              */
19036   #define ETM_TRCVDARCCTLR_EXCLUDE1_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE1 field.                              */
19037   #define ETM_TRCVDARCCTLR_EXCLUDE1_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE1 field.                              */
19038   #define ETM_TRCVDARCCTLR_EXCLUDE1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not
19039                                                           selected for ViewData exclude control.*/
19040   #define ETM_TRCVDARCCTLR_EXCLUDE1_Enabled (0x1UL)  /*!< The address range that address range comparator 1 defines, s selected
19041                                                           for ViewData exclude control.*/
19042 
19043 /* EXCLUDE2 @Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
19044                       control. */
19045 
19046   #define ETM_TRCVDARCCTLR_EXCLUDE2_Pos (18UL)       /*!< Position of EXCLUDE2 field.                                          */
19047   #define ETM_TRCVDARCCTLR_EXCLUDE2_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE2_Pos) /*!< Bit mask of EXCLUDE2 field.              */
19048   #define ETM_TRCVDARCCTLR_EXCLUDE2_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE2 field.                              */
19049   #define ETM_TRCVDARCCTLR_EXCLUDE2_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE2 field.                              */
19050   #define ETM_TRCVDARCCTLR_EXCLUDE2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not
19051                                                           selected for ViewData exclude control.*/
19052   #define ETM_TRCVDARCCTLR_EXCLUDE2_Enabled (0x1UL)  /*!< The address range that address range comparator 2 defines, s selected
19053                                                           for ViewData exclude control.*/
19054 
19055 /* EXCLUDE3 @Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
19056                       control. */
19057 
19058   #define ETM_TRCVDARCCTLR_EXCLUDE3_Pos (19UL)       /*!< Position of EXCLUDE3 field.                                          */
19059   #define ETM_TRCVDARCCTLR_EXCLUDE3_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE3_Pos) /*!< Bit mask of EXCLUDE3 field.              */
19060   #define ETM_TRCVDARCCTLR_EXCLUDE3_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE3 field.                              */
19061   #define ETM_TRCVDARCCTLR_EXCLUDE3_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE3 field.                              */
19062   #define ETM_TRCVDARCCTLR_EXCLUDE3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not
19063                                                           selected for ViewData exclude control.*/
19064   #define ETM_TRCVDARCCTLR_EXCLUDE3_Enabled (0x1UL)  /*!< The address range that address range comparator 3 defines, s selected
19065                                                           for ViewData exclude control.*/
19066 
19067 /* EXCLUDE4 @Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
19068                       control. */
19069 
19070   #define ETM_TRCVDARCCTLR_EXCLUDE4_Pos (20UL)       /*!< Position of EXCLUDE4 field.                                          */
19071   #define ETM_TRCVDARCCTLR_EXCLUDE4_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE4_Pos) /*!< Bit mask of EXCLUDE4 field.              */
19072   #define ETM_TRCVDARCCTLR_EXCLUDE4_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE4 field.                              */
19073   #define ETM_TRCVDARCCTLR_EXCLUDE4_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE4 field.                              */
19074   #define ETM_TRCVDARCCTLR_EXCLUDE4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not
19075                                                           selected for ViewData exclude control.*/
19076   #define ETM_TRCVDARCCTLR_EXCLUDE4_Enabled (0x1UL)  /*!< The address range that address range comparator 4 defines, s selected
19077                                                           for ViewData exclude control.*/
19078 
19079 /* EXCLUDE5 @Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
19080                       control. */
19081 
19082   #define ETM_TRCVDARCCTLR_EXCLUDE5_Pos (21UL)       /*!< Position of EXCLUDE5 field.                                          */
19083   #define ETM_TRCVDARCCTLR_EXCLUDE5_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE5_Pos) /*!< Bit mask of EXCLUDE5 field.              */
19084   #define ETM_TRCVDARCCTLR_EXCLUDE5_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE5 field.                              */
19085   #define ETM_TRCVDARCCTLR_EXCLUDE5_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE5 field.                              */
19086   #define ETM_TRCVDARCCTLR_EXCLUDE5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not
19087                                                           selected for ViewData exclude control.*/
19088   #define ETM_TRCVDARCCTLR_EXCLUDE5_Enabled (0x1UL)  /*!< The address range that address range comparator 5 defines, s selected
19089                                                           for ViewData exclude control.*/
19090 
19091 /* EXCLUDE6 @Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
19092                       control. */
19093 
19094   #define ETM_TRCVDARCCTLR_EXCLUDE6_Pos (22UL)       /*!< Position of EXCLUDE6 field.                                          */
19095   #define ETM_TRCVDARCCTLR_EXCLUDE6_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE6_Pos) /*!< Bit mask of EXCLUDE6 field.              */
19096   #define ETM_TRCVDARCCTLR_EXCLUDE6_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE6 field.                              */
19097   #define ETM_TRCVDARCCTLR_EXCLUDE6_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE6 field.                              */
19098   #define ETM_TRCVDARCCTLR_EXCLUDE6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not
19099                                                           selected for ViewData exclude control.*/
19100   #define ETM_TRCVDARCCTLR_EXCLUDE6_Enabled (0x1UL)  /*!< The address range that address range comparator 6 defines, s selected
19101                                                           for ViewData exclude control.*/
19102 
19103 /* EXCLUDE7 @Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude
19104                       control. */
19105 
19106   #define ETM_TRCVDARCCTLR_EXCLUDE7_Pos (23UL)       /*!< Position of EXCLUDE7 field.                                          */
19107   #define ETM_TRCVDARCCTLR_EXCLUDE7_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE7_Pos) /*!< Bit mask of EXCLUDE7 field.              */
19108   #define ETM_TRCVDARCCTLR_EXCLUDE7_Min (0x0UL)      /*!< Min enumerator value of EXCLUDE7 field.                              */
19109   #define ETM_TRCVDARCCTLR_EXCLUDE7_Max (0x1UL)      /*!< Max enumerator value of EXCLUDE7 field.                              */
19110   #define ETM_TRCVDARCCTLR_EXCLUDE7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not
19111                                                           selected for ViewData exclude control.*/
19112   #define ETM_TRCVDARCCTLR_EXCLUDE7_Enabled (0x1UL)  /*!< The address range that address range comparator 7 defines, s selected
19113                                                           for ViewData exclude control.*/
19114 
19115 
19116 /* ETM_TRCSEQEVR: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled
19117                    or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid
19118                    event. */
19119 
19120   #define ETM_TRCSEQEVR_MaxCount (3UL)               /*!< Max size of TRCSEQEVR[3] array.                                      */
19121   #define ETM_TRCSEQEVR_MaxIndex (2UL)               /*!< Max index of TRCSEQEVR[3] array.                                     */
19122   #define ETM_TRCSEQEVR_MinIndex (0UL)               /*!< Min index of TRCSEQEVR[3] array.                                     */
19123   #define ETM_TRCSEQEVR_ResetValue (0x00000000UL)    /*!< Reset value of TRCSEQEVR[3] register.                                */
19124 
19125 /* F0 @Bit 0 : Forward field. */
19126   #define ETM_TRCSEQEVR_F0_Pos (0UL)                 /*!< Position of F0 field.                                                */
19127   #define ETM_TRCSEQEVR_F0_Msk (0x1UL << ETM_TRCSEQEVR_F0_Pos) /*!< Bit mask of F0 field.                                      */
19128   #define ETM_TRCSEQEVR_F0_Min (0x0UL)               /*!< Min enumerator value of F0 field.                                    */
19129   #define ETM_TRCSEQEVR_F0_Max (0x1UL)               /*!< Max enumerator value of F0 field.                                    */
19130   #define ETM_TRCSEQEVR_F0_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19131   #define ETM_TRCSEQEVR_F0_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
19132                                                           state n+1.*/
19133 
19134 /* F1 @Bit 1 : Forward field. */
19135   #define ETM_TRCSEQEVR_F1_Pos (1UL)                 /*!< Position of F1 field.                                                */
19136   #define ETM_TRCSEQEVR_F1_Msk (0x1UL << ETM_TRCSEQEVR_F1_Pos) /*!< Bit mask of F1 field.                                      */
19137   #define ETM_TRCSEQEVR_F1_Min (0x0UL)               /*!< Min enumerator value of F1 field.                                    */
19138   #define ETM_TRCSEQEVR_F1_Max (0x1UL)               /*!< Max enumerator value of F1 field.                                    */
19139   #define ETM_TRCSEQEVR_F1_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19140   #define ETM_TRCSEQEVR_F1_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
19141                                                           state n+1.*/
19142 
19143 /* F2 @Bit 2 : Forward field. */
19144   #define ETM_TRCSEQEVR_F2_Pos (2UL)                 /*!< Position of F2 field.                                                */
19145   #define ETM_TRCSEQEVR_F2_Msk (0x1UL << ETM_TRCSEQEVR_F2_Pos) /*!< Bit mask of F2 field.                                      */
19146   #define ETM_TRCSEQEVR_F2_Min (0x0UL)               /*!< Min enumerator value of F2 field.                                    */
19147   #define ETM_TRCSEQEVR_F2_Max (0x1UL)               /*!< Max enumerator value of F2 field.                                    */
19148   #define ETM_TRCSEQEVR_F2_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19149   #define ETM_TRCSEQEVR_F2_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
19150                                                           state n+1.*/
19151 
19152 /* F3 @Bit 3 : Forward field. */
19153   #define ETM_TRCSEQEVR_F3_Pos (3UL)                 /*!< Position of F3 field.                                                */
19154   #define ETM_TRCSEQEVR_F3_Msk (0x1UL << ETM_TRCSEQEVR_F3_Pos) /*!< Bit mask of F3 field.                                      */
19155   #define ETM_TRCSEQEVR_F3_Min (0x0UL)               /*!< Min enumerator value of F3 field.                                    */
19156   #define ETM_TRCSEQEVR_F3_Max (0x1UL)               /*!< Max enumerator value of F3 field.                                    */
19157   #define ETM_TRCSEQEVR_F3_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19158   #define ETM_TRCSEQEVR_F3_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
19159                                                           state n+1.*/
19160 
19161 /* F4 @Bit 4 : Forward field. */
19162   #define ETM_TRCSEQEVR_F4_Pos (4UL)                 /*!< Position of F4 field.                                                */
19163   #define ETM_TRCSEQEVR_F4_Msk (0x1UL << ETM_TRCSEQEVR_F4_Pos) /*!< Bit mask of F4 field.                                      */
19164   #define ETM_TRCSEQEVR_F4_Min (0x0UL)               /*!< Min enumerator value of F4 field.                                    */
19165   #define ETM_TRCSEQEVR_F4_Max (0x1UL)               /*!< Max enumerator value of F4 field.                                    */
19166   #define ETM_TRCSEQEVR_F4_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19167   #define ETM_TRCSEQEVR_F4_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
19168                                                           state n+1.*/
19169 
19170 /* F5 @Bit 5 : Forward field. */
19171   #define ETM_TRCSEQEVR_F5_Pos (5UL)                 /*!< Position of F5 field.                                                */
19172   #define ETM_TRCSEQEVR_F5_Msk (0x1UL << ETM_TRCSEQEVR_F5_Pos) /*!< Bit mask of F5 field.                                      */
19173   #define ETM_TRCSEQEVR_F5_Min (0x0UL)               /*!< Min enumerator value of F5 field.                                    */
19174   #define ETM_TRCSEQEVR_F5_Max (0x1UL)               /*!< Max enumerator value of F5 field.                                    */
19175   #define ETM_TRCSEQEVR_F5_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19176   #define ETM_TRCSEQEVR_F5_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
19177                                                           state n+1.*/
19178 
19179 /* F6 @Bit 6 : Forward field. */
19180   #define ETM_TRCSEQEVR_F6_Pos (6UL)                 /*!< Position of F6 field.                                                */
19181   #define ETM_TRCSEQEVR_F6_Msk (0x1UL << ETM_TRCSEQEVR_F6_Pos) /*!< Bit mask of F6 field.                                      */
19182   #define ETM_TRCSEQEVR_F6_Min (0x0UL)               /*!< Min enumerator value of F6 field.                                    */
19183   #define ETM_TRCSEQEVR_F6_Max (0x1UL)               /*!< Max enumerator value of F6 field.                                    */
19184   #define ETM_TRCSEQEVR_F6_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19185   #define ETM_TRCSEQEVR_F6_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
19186                                                           state n+1.*/
19187 
19188 /* F7 @Bit 7 : Forward field. */
19189   #define ETM_TRCSEQEVR_F7_Pos (7UL)                 /*!< Position of F7 field.                                                */
19190   #define ETM_TRCSEQEVR_F7_Msk (0x1UL << ETM_TRCSEQEVR_F7_Pos) /*!< Bit mask of F7 field.                                      */
19191   #define ETM_TRCSEQEVR_F7_Min (0x0UL)               /*!< Min enumerator value of F7 field.                                    */
19192   #define ETM_TRCSEQEVR_F7_Max (0x1UL)               /*!< Max enumerator value of F7 field.                                    */
19193   #define ETM_TRCSEQEVR_F7_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19194   #define ETM_TRCSEQEVR_F7_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n to
19195                                                           state n+1.*/
19196 
19197 /* B0 @Bit 8 : Backward field. */
19198   #define ETM_TRCSEQEVR_B0_Pos (8UL)                 /*!< Position of B0 field.                                                */
19199   #define ETM_TRCSEQEVR_B0_Msk (0x1UL << ETM_TRCSEQEVR_B0_Pos) /*!< Bit mask of B0 field.                                      */
19200   #define ETM_TRCSEQEVR_B0_Min (0x0UL)               /*!< Min enumerator value of B0 field.                                    */
19201   #define ETM_TRCSEQEVR_B0_Max (0x1UL)               /*!< Max enumerator value of B0 field.                                    */
19202   #define ETM_TRCSEQEVR_B0_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19203   #define ETM_TRCSEQEVR_B0_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
19204                                                           state n.*/
19205 
19206 /* B1 @Bit 9 : Backward field. */
19207   #define ETM_TRCSEQEVR_B1_Pos (9UL)                 /*!< Position of B1 field.                                                */
19208   #define ETM_TRCSEQEVR_B1_Msk (0x1UL << ETM_TRCSEQEVR_B1_Pos) /*!< Bit mask of B1 field.                                      */
19209   #define ETM_TRCSEQEVR_B1_Min (0x0UL)               /*!< Min enumerator value of B1 field.                                    */
19210   #define ETM_TRCSEQEVR_B1_Max (0x1UL)               /*!< Max enumerator value of B1 field.                                    */
19211   #define ETM_TRCSEQEVR_B1_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19212   #define ETM_TRCSEQEVR_B1_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
19213                                                           state n.*/
19214 
19215 /* B2 @Bit 10 : Backward field. */
19216   #define ETM_TRCSEQEVR_B2_Pos (10UL)                /*!< Position of B2 field.                                                */
19217   #define ETM_TRCSEQEVR_B2_Msk (0x1UL << ETM_TRCSEQEVR_B2_Pos) /*!< Bit mask of B2 field.                                      */
19218   #define ETM_TRCSEQEVR_B2_Min (0x0UL)               /*!< Min enumerator value of B2 field.                                    */
19219   #define ETM_TRCSEQEVR_B2_Max (0x1UL)               /*!< Max enumerator value of B2 field.                                    */
19220   #define ETM_TRCSEQEVR_B2_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19221   #define ETM_TRCSEQEVR_B2_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
19222                                                           state n.*/
19223 
19224 /* B3 @Bit 11 : Backward field. */
19225   #define ETM_TRCSEQEVR_B3_Pos (11UL)                /*!< Position of B3 field.                                                */
19226   #define ETM_TRCSEQEVR_B3_Msk (0x1UL << ETM_TRCSEQEVR_B3_Pos) /*!< Bit mask of B3 field.                                      */
19227   #define ETM_TRCSEQEVR_B3_Min (0x0UL)               /*!< Min enumerator value of B3 field.                                    */
19228   #define ETM_TRCSEQEVR_B3_Max (0x1UL)               /*!< Max enumerator value of B3 field.                                    */
19229   #define ETM_TRCSEQEVR_B3_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19230   #define ETM_TRCSEQEVR_B3_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
19231                                                           state n.*/
19232 
19233 /* B4 @Bit 12 : Backward field. */
19234   #define ETM_TRCSEQEVR_B4_Pos (12UL)                /*!< Position of B4 field.                                                */
19235   #define ETM_TRCSEQEVR_B4_Msk (0x1UL << ETM_TRCSEQEVR_B4_Pos) /*!< Bit mask of B4 field.                                      */
19236   #define ETM_TRCSEQEVR_B4_Min (0x0UL)               /*!< Min enumerator value of B4 field.                                    */
19237   #define ETM_TRCSEQEVR_B4_Max (0x1UL)               /*!< Max enumerator value of B4 field.                                    */
19238   #define ETM_TRCSEQEVR_B4_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19239   #define ETM_TRCSEQEVR_B4_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
19240                                                           state n.*/
19241 
19242 /* B5 @Bit 13 : Backward field. */
19243   #define ETM_TRCSEQEVR_B5_Pos (13UL)                /*!< Position of B5 field.                                                */
19244   #define ETM_TRCSEQEVR_B5_Msk (0x1UL << ETM_TRCSEQEVR_B5_Pos) /*!< Bit mask of B5 field.                                      */
19245   #define ETM_TRCSEQEVR_B5_Min (0x0UL)               /*!< Min enumerator value of B5 field.                                    */
19246   #define ETM_TRCSEQEVR_B5_Max (0x1UL)               /*!< Max enumerator value of B5 field.                                    */
19247   #define ETM_TRCSEQEVR_B5_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19248   #define ETM_TRCSEQEVR_B5_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
19249                                                           state n.*/
19250 
19251 /* B6 @Bit 14 : Backward field. */
19252   #define ETM_TRCSEQEVR_B6_Pos (14UL)                /*!< Position of B6 field.                                                */
19253   #define ETM_TRCSEQEVR_B6_Msk (0x1UL << ETM_TRCSEQEVR_B6_Pos) /*!< Bit mask of B6 field.                                      */
19254   #define ETM_TRCSEQEVR_B6_Min (0x0UL)               /*!< Min enumerator value of B6 field.                                    */
19255   #define ETM_TRCSEQEVR_B6_Max (0x1UL)               /*!< Max enumerator value of B6 field.                                    */
19256   #define ETM_TRCSEQEVR_B6_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19257   #define ETM_TRCSEQEVR_B6_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
19258                                                           state n.*/
19259 
19260 /* B7 @Bit 15 : Backward field. */
19261   #define ETM_TRCSEQEVR_B7_Pos (15UL)                /*!< Position of B7 field.                                                */
19262   #define ETM_TRCSEQEVR_B7_Msk (0x1UL << ETM_TRCSEQEVR_B7_Pos) /*!< Bit mask of B7 field.                                      */
19263   #define ETM_TRCSEQEVR_B7_Min (0x0UL)               /*!< Min enumerator value of B7 field.                                    */
19264   #define ETM_TRCSEQEVR_B7_Max (0x1UL)               /*!< Max enumerator value of B7 field.                                    */
19265   #define ETM_TRCSEQEVR_B7_Disabled (0x0UL)          /*!< The trace event does not affect the sequencer.                       */
19266   #define ETM_TRCSEQEVR_B7_Enabled (0x1UL)           /*!< When the event occurs then the sequencer state moves from state n+1 to
19267                                                           state n.*/
19268 
19269 
19270 /* ETM_TRCSEQRSTEVR: Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is
19271                       enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a
19272                       valid event. */
19273 
19274   #define ETM_TRCSEQRSTEVR_ResetValue (0x00000000UL) /*!< Reset value of TRCSEQRSTEVR register.                                */
19275 
19276 /* EVENT @Bits 0..7 : Select which event should reset the sequencer. */
19277   #define ETM_TRCSEQRSTEVR_EVENT_Pos (0UL)           /*!< Position of EVENT field.                                             */
19278   #define ETM_TRCSEQRSTEVR_EVENT_Msk (0xFFUL << ETM_TRCSEQRSTEVR_EVENT_Pos) /*!< Bit mask of EVENT field.                      */
19279   #define ETM_TRCSEQRSTEVR_EVENT_Min (0x0UL)         /*!< Min value of EVENT field.                                            */
19280   #define ETM_TRCSEQRSTEVR_EVENT_Max (0xFFUL)        /*!< Max size of EVENT field.                                             */
19281 
19282 
19283 /* ETM_TRCSEQSTR: Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle.
19284                    Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state
19285                    transitions must be programmed with a valid event. */
19286 
19287   #define ETM_TRCSEQSTR_ResetValue (0x00000000UL)    /*!< Reset value of TRCSEQSTR register.                                   */
19288 
19289 /* STATE @Bits 0..1 : Sets or returns the state of the sequencer. */
19290   #define ETM_TRCSEQSTR_STATE_Pos (0UL)              /*!< Position of STATE field.                                             */
19291   #define ETM_TRCSEQSTR_STATE_Msk (0x3UL << ETM_TRCSEQSTR_STATE_Pos) /*!< Bit mask of STATE field.                             */
19292   #define ETM_TRCSEQSTR_STATE_Min (0x0UL)            /*!< Min enumerator value of STATE field.                                 */
19293   #define ETM_TRCSEQSTR_STATE_Max (0x3UL)            /*!< Max enumerator value of STATE field.                                 */
19294   #define ETM_TRCSEQSTR_STATE_State0 (0x0UL)         /*!< The sequencer is in state 0.                                         */
19295   #define ETM_TRCSEQSTR_STATE_State1 (0x1UL)         /*!< The sequencer is in state 1.                                         */
19296   #define ETM_TRCSEQSTR_STATE_State2 (0x2UL)         /*!< The sequencer is in state 2.                                         */
19297   #define ETM_TRCSEQSTR_STATE_State3 (0x3UL)         /*!< The sequencer is in state 3.                                         */
19298 
19299 
19300 /* ETM_TRCEXTINSELR: Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when
19301                       the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the
19302                       sequencer is used, all sequencer state transitions must be programmed with a valid event. */
19303 
19304   #define ETM_TRCEXTINSELR_ResetValue (0x00000000UL) /*!< Reset value of TRCEXTINSELR register.                                */
19305 
19306 /* SEL0 @Bits 0..7 : Each field in this collection selects an external input as a resource for the trace unit. */
19307   #define ETM_TRCEXTINSELR_SEL0_Pos (0UL)            /*!< Position of SEL0 field.                                              */
19308   #define ETM_TRCEXTINSELR_SEL0_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL0_Pos) /*!< Bit mask of SEL0 field.                         */
19309   #define ETM_TRCEXTINSELR_SEL0_Min (0x0UL)          /*!< Min value of SEL0 field.                                             */
19310   #define ETM_TRCEXTINSELR_SEL0_Max (0xFFUL)         /*!< Max size of SEL0 field.                                              */
19311 
19312 /* SEL1 @Bits 8..15 : Each field in this collection selects an external input as a resource for the trace unit. */
19313   #define ETM_TRCEXTINSELR_SEL1_Pos (8UL)            /*!< Position of SEL1 field.                                              */
19314   #define ETM_TRCEXTINSELR_SEL1_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL1_Pos) /*!< Bit mask of SEL1 field.                         */
19315   #define ETM_TRCEXTINSELR_SEL1_Min (0x0UL)          /*!< Min value of SEL1 field.                                             */
19316   #define ETM_TRCEXTINSELR_SEL1_Max (0xFFUL)         /*!< Max size of SEL1 field.                                              */
19317 
19318 /* SEL2 @Bits 16..23 : Each field in this collection selects an external input as a resource for the trace unit. */
19319   #define ETM_TRCEXTINSELR_SEL2_Pos (16UL)           /*!< Position of SEL2 field.                                              */
19320   #define ETM_TRCEXTINSELR_SEL2_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL2_Pos) /*!< Bit mask of SEL2 field.                         */
19321   #define ETM_TRCEXTINSELR_SEL2_Min (0x0UL)          /*!< Min value of SEL2 field.                                             */
19322   #define ETM_TRCEXTINSELR_SEL2_Max (0xFFUL)         /*!< Max size of SEL2 field.                                              */
19323 
19324 /* SEL3 @Bits 24..31 : Each field in this collection selects an external input as a resource for the trace unit. */
19325   #define ETM_TRCEXTINSELR_SEL3_Pos (24UL)           /*!< Position of SEL3 field.                                              */
19326   #define ETM_TRCEXTINSELR_SEL3_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL3_Pos) /*!< Bit mask of SEL3 field.                         */
19327   #define ETM_TRCEXTINSELR_SEL3_Min (0x0UL)          /*!< Min value of SEL3 field.                                             */
19328   #define ETM_TRCEXTINSELR_SEL3_Max (0xFFUL)         /*!< Max size of SEL3 field.                                              */
19329 
19330 
19331 /* ETM_TRCCNTRLDVR: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is
19332                      enabled or not idle. */
19333 
19334   #define ETM_TRCCNTRLDVR_MaxCount (4UL)             /*!< Max size of TRCCNTRLDVR[4] array.                                    */
19335   #define ETM_TRCCNTRLDVR_MaxIndex (3UL)             /*!< Max index of TRCCNTRLDVR[4] array.                                   */
19336   #define ETM_TRCCNTRLDVR_MinIndex (0UL)             /*!< Min index of TRCCNTRLDVR[4] array.                                   */
19337   #define ETM_TRCCNTRLDVR_ResetValue (0x00000000UL)  /*!< Reset value of TRCCNTRLDVR[4] register.                              */
19338 
19339 /* VALUE @Bits 0..15 : Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit
19340                        copies the VALUEn field into counter n. */
19341 
19342   #define ETM_TRCCNTRLDVR_VALUE_Pos (0UL)            /*!< Position of VALUE field.                                             */
19343   #define ETM_TRCCNTRLDVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTRLDVR_VALUE_Pos) /*!< Bit mask of VALUE field.                      */
19344   #define ETM_TRCCNTRLDVR_VALUE_Min (0x0UL)          /*!< Min value of VALUE field.                                            */
19345   #define ETM_TRCCNTRLDVR_VALUE_Max (0xFFFFUL)       /*!< Max size of VALUE field.                                             */
19346 
19347 
19348 /* ETM_TRCCNTCTLR: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. */
19349   #define ETM_TRCCNTCTLR_MaxCount (4UL)              /*!< Max size of TRCCNTCTLR[4] array.                                     */
19350   #define ETM_TRCCNTCTLR_MaxIndex (3UL)              /*!< Max index of TRCCNTCTLR[4] array.                                    */
19351   #define ETM_TRCCNTCTLR_MinIndex (0UL)              /*!< Min index of TRCCNTCTLR[4] array.                                    */
19352   #define ETM_TRCCNTCTLR_ResetValue (0x00000000UL)   /*!< Reset value of TRCCNTCTLR[4] register.                               */
19353 
19354 /* CNTEVENT @Bits 0..7 : Selects an event, that when it occurs causes counter n to decrement. */
19355   #define ETM_TRCCNTCTLR_CNTEVENT_Pos (0UL)          /*!< Position of CNTEVENT field.                                          */
19356   #define ETM_TRCCNTCTLR_CNTEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_CNTEVENT_Pos) /*!< Bit mask of CNTEVENT field.                 */
19357   #define ETM_TRCCNTCTLR_CNTEVENT_Min (0x0UL)        /*!< Min value of CNTEVENT field.                                         */
19358   #define ETM_TRCCNTCTLR_CNTEVENT_Max (0xFFUL)       /*!< Max size of CNTEVENT field.                                          */
19359 
19360 /* RLDEVENT @Bits 8..15 : Selects an event, that when it occurs causes a reload event for counter n. */
19361   #define ETM_TRCCNTCTLR_RLDEVENT_Pos (8UL)          /*!< Position of RLDEVENT field.                                          */
19362   #define ETM_TRCCNTCTLR_RLDEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_RLDEVENT_Pos) /*!< Bit mask of RLDEVENT field.                 */
19363   #define ETM_TRCCNTCTLR_RLDEVENT_Min (0x0UL)        /*!< Min value of RLDEVENT field.                                         */
19364   #define ETM_TRCCNTCTLR_RLDEVENT_Max (0xFFUL)       /*!< Max size of RLDEVENT field.                                          */
19365 
19366 /* RLDSELF @Bit 16 : Controls whether a reload event occurs for counter n, when counter n reaches zero. */
19367   #define ETM_TRCCNTCTLR_RLDSELF_Pos (16UL)          /*!< Position of RLDSELF field.                                           */
19368   #define ETM_TRCCNTCTLR_RLDSELF_Msk (0x1UL << ETM_TRCCNTCTLR_RLDSELF_Pos) /*!< Bit mask of RLDSELF field.                     */
19369   #define ETM_TRCCNTCTLR_RLDSELF_Min (0x0UL)         /*!< Min enumerator value of RLDSELF field.                               */
19370   #define ETM_TRCCNTCTLR_RLDSELF_Max (0x1UL)         /*!< Max enumerator value of RLDSELF field.                               */
19371   #define ETM_TRCCNTCTLR_RLDSELF_Disabled (0x0UL)    /*!< The counter is in Normal mode.                                       */
19372   #define ETM_TRCCNTCTLR_RLDSELF_Enabled (0x1UL)     /*!< The counter is in Self-reload mode.                                  */
19373 
19374 /* CNTCHAIN @Bit 17 : For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs
19375                       for counter n-1. */
19376 
19377   #define ETM_TRCCNTCTLR_CNTCHAIN_Pos (17UL)         /*!< Position of CNTCHAIN field.                                          */
19378   #define ETM_TRCCNTCTLR_CNTCHAIN_Msk (0x1UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos) /*!< Bit mask of CNTCHAIN field.                  */
19379   #define ETM_TRCCNTCTLR_CNTCHAIN_Min (0x0UL)        /*!< Min enumerator value of CNTCHAIN field.                              */
19380   #define ETM_TRCCNTCTLR_CNTCHAIN_Max (0x1UL)        /*!< Max enumerator value of CNTCHAIN field.                              */
19381   #define ETM_TRCCNTCTLR_CNTCHAIN_Disabled (0x0UL)   /*!< Counter n does not decrement when a reload event for counter n-1
19382                                                           occurs.*/
19383   #define ETM_TRCCNTCTLR_CNTCHAIN_Enabled (0x1UL)    /*!< Counter n decrements when a reload event for counter n-1 occurs. This
19384                                                           concatenates counter n and counter n-1, to provide a larger count
19385                                                           value.*/
19386 
19387 
19388 /* ETM_TRCCNTVR: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If
19389                   software uses counter n then it must write to this register to set the initial counter value. Might ignore
19390                   writes when the trace unit is enabled or not idle. */
19391 
19392   #define ETM_TRCCNTVR_MaxCount (4UL)                /*!< Max size of TRCCNTVR[4] array.                                       */
19393   #define ETM_TRCCNTVR_MaxIndex (3UL)                /*!< Max index of TRCCNTVR[4] array.                                      */
19394   #define ETM_TRCCNTVR_MinIndex (0UL)                /*!< Min index of TRCCNTVR[4] array.                                      */
19395   #define ETM_TRCCNTVR_ResetValue (0x00000000UL)     /*!< Reset value of TRCCNTVR[4] register.                                 */
19396 
19397 /* VALUE @Bits 0..15 : Contains the count value of counter n. */
19398   #define ETM_TRCCNTVR_VALUE_Pos (0UL)               /*!< Position of VALUE field.                                             */
19399   #define ETM_TRCCNTVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTVR_VALUE_Pos) /*!< Bit mask of VALUE field.                            */
19400   #define ETM_TRCCNTVR_VALUE_Min (0x0UL)             /*!< Min value of VALUE field.                                            */
19401   #define ETM_TRCCNTVR_VALUE_Max (0xFFFFUL)          /*!< Max size of VALUE field.                                             */
19402 
19403 
19404 /* ETM_TRCRSCTLR: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled
19405                    or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE behavior of the
19406                    resource selector occurs, so the resource selector might fire unexpectedly or might not fire. Reads of the
19407                    TRCRSCTLRn might return UNKNOWN. */
19408 
19409   #define ETM_TRCRSCTLR_MaxCount (30UL)              /*!< Max size of TRCRSCTLR[32] array.                                     */
19410   #define ETM_TRCRSCTLR_MaxIndex (31UL)              /*!< Max index of TRCRSCTLR[32] array.                                    */
19411   #define ETM_TRCRSCTLR_MinIndex (2UL)               /*!< Min index of TRCRSCTLR[32] array.                                    */
19412   #define ETM_TRCRSCTLR_ResetValue (0x00000000UL)    /*!< Reset value of TRCRSCTLR[32] register.                               */
19413 
19414 /* EN @Bit 0 : Trace unit enable bit */
19415   #define ETM_TRCRSCTLR_EN_Pos (0UL)                 /*!< Position of EN field.                                                */
19416   #define ETM_TRCRSCTLR_EN_Msk (0x1UL << ETM_TRCRSCTLR_EN_Pos) /*!< Bit mask of EN field.                                      */
19417   #define ETM_TRCRSCTLR_EN_Min (0x0UL)               /*!< Min enumerator value of EN field.                                    */
19418   #define ETM_TRCRSCTLR_EN_Max (0x1UL)               /*!< Max enumerator value of EN field.                                    */
19419   #define ETM_TRCRSCTLR_EN_Disabled (0x0UL)          /*!< The trace unit is disabled. All trace resources are inactive and no
19420                                                           trace is generated.*/
19421   #define ETM_TRCRSCTLR_EN_Enabled (0x1UL)           /*!< The trace unit is enabled.                                           */
19422 
19423 
19424 /* ETM_TRCSSCCR0: Controls the single-shot comparator. */
19425   #define ETM_TRCSSCCR0_ResetValue (0x00000000UL)    /*!< Reset value of TRCSSCCR0 register.                                   */
19426 
19427 /* RST @Bit 24 : Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to
19428                  be detected */
19429 
19430   #define ETM_TRCSSCCR0_RST_Pos (24UL)               /*!< Position of RST field.                                               */
19431   #define ETM_TRCSSCCR0_RST_Msk (0x1UL << ETM_TRCSSCCR0_RST_Pos) /*!< Bit mask of RST field.                                   */
19432   #define ETM_TRCSSCCR0_RST_Min (0x0UL)              /*!< Min enumerator value of RST field.                                   */
19433   #define ETM_TRCSSCCR0_RST_Max (0x1UL)              /*!< Max enumerator value of RST field.                                   */
19434   #define ETM_TRCSSCCR0_RST_Disabled (0x0UL)         /*!< Multiple matches can not be detected.                                */
19435   #define ETM_TRCSSCCR0_RST_Enabled (0x1UL)          /*!< Multiple matches can occur.                                          */
19436 
19437 
19438 /* ETM_TRCSSCSR0: Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. */
19439   #define ETM_TRCSSCSR0_ResetValue (0x00000000UL)    /*!< Reset value of TRCSSCSR0 register.                                   */
19440 
19441 /* INST @Bit 0 : Instruction address comparator support */
19442   #define ETM_TRCSSCSR0_INST_Pos (0UL)               /*!< Position of INST field.                                              */
19443   #define ETM_TRCSSCSR0_INST_Msk (0x1UL << ETM_TRCSSCSR0_INST_Pos) /*!< Bit mask of INST field.                                */
19444   #define ETM_TRCSSCSR0_INST_Min (0x0UL)             /*!< Min enumerator value of INST field.                                  */
19445   #define ETM_TRCSSCSR0_INST_Max (0x1UL)             /*!< Max enumerator value of INST field.                                  */
19446   #define ETM_TRCSSCSR0_INST_False (0x0UL)           /*!< Single-shot instruction address comparisons not supported.           */
19447   #define ETM_TRCSSCSR0_INST_True (0x1UL)            /*!< Single-shot instruction address comparisons supported.               */
19448 
19449 /* DA @Bit 1 : Data address comparator support */
19450   #define ETM_TRCSSCSR0_DA_Pos (1UL)                 /*!< Position of DA field.                                                */
19451   #define ETM_TRCSSCSR0_DA_Msk (0x1UL << ETM_TRCSSCSR0_DA_Pos) /*!< Bit mask of DA field.                                      */
19452   #define ETM_TRCSSCSR0_DA_Min (0x0UL)               /*!< Min enumerator value of DA field.                                    */
19453   #define ETM_TRCSSCSR0_DA_Max (0x1UL)               /*!< Max enumerator value of DA field.                                    */
19454   #define ETM_TRCSSCSR0_DA_False (0x0UL)             /*!< Data address comparisons not supported.                              */
19455   #define ETM_TRCSSCSR0_DA_True (0x1UL)              /*!< Data address comparisons supported.                                  */
19456 
19457 /* DV @Bit 2 : Data value comparator support */
19458   #define ETM_TRCSSCSR0_DV_Pos (2UL)                 /*!< Position of DV field.                                                */
19459   #define ETM_TRCSSCSR0_DV_Msk (0x1UL << ETM_TRCSSCSR0_DV_Pos) /*!< Bit mask of DV field.                                      */
19460   #define ETM_TRCSSCSR0_DV_Min (0x0UL)               /*!< Min enumerator value of DV field.                                    */
19461   #define ETM_TRCSSCSR0_DV_Max (0x1UL)               /*!< Max enumerator value of DV field.                                    */
19462   #define ETM_TRCSSCSR0_DV_False (0x0UL)             /*!< Data value comparisons not supported.                                */
19463   #define ETM_TRCSSCSR0_DV_True (0x1UL)              /*!< Data value comparisons supported.                                    */
19464 
19465 /* PC @Bit 3 : Process counter value comparator support */
19466   #define ETM_TRCSSCSR0_PC_Pos (3UL)                 /*!< Position of PC field.                                                */
19467   #define ETM_TRCSSCSR0_PC_Msk (0x1UL << ETM_TRCSSCSR0_PC_Pos) /*!< Bit mask of PC field.                                      */
19468   #define ETM_TRCSSCSR0_PC_Min (0x0UL)               /*!< Min enumerator value of PC field.                                    */
19469   #define ETM_TRCSSCSR0_PC_Max (0x1UL)               /*!< Max enumerator value of PC field.                                    */
19470   #define ETM_TRCSSCSR0_PC_False (0x0UL)             /*!< Process counter value comparisons not supported.                     */
19471   #define ETM_TRCSSCSR0_PC_True (0x1UL)              /*!< Process counter value comparisons supported.                         */
19472 
19473 /* STATUS @Bit 31 : Single-shot status. This indicates whether any of the selected comparators have matched. */
19474   #define ETM_TRCSSCSR0_STATUS_Pos (31UL)            /*!< Position of STATUS field.                                            */
19475   #define ETM_TRCSSCSR0_STATUS_Msk (0x1UL << ETM_TRCSSCSR0_STATUS_Pos) /*!< Bit mask of STATUS field.                          */
19476   #define ETM_TRCSSCSR0_STATUS_Min (0x0UL)           /*!< Min enumerator value of STATUS field.                                */
19477   #define ETM_TRCSSCSR0_STATUS_Max (0x1UL)           /*!< Max enumerator value of STATUS field.                                */
19478   #define ETM_TRCSSCSR0_STATUS_NoMatch (0x0UL)       /*!< Match has not occurred.                                              */
19479   #define ETM_TRCSSCSR0_STATUS_Match (0x1UL)         /*!< Match has occurred at least once.                                    */
19480 
19481 
19482 /* ETM_TRCSSPCICR0: Selects the processor comparator inputs for Single-shot control. */
19483   #define ETM_TRCSSPCICR0_ResetValue (0x00000000UL)  /*!< Reset value of TRCSSPCICR0 register.                                 */
19484 
19485 /* PC0 @Bit 0 : Selects processor comparator 0 inputs for Single-shot control */
19486   #define ETM_TRCSSPCICR0_PC0_Pos (0UL)              /*!< Position of PC0 field.                                               */
19487   #define ETM_TRCSSPCICR0_PC0_Msk (0x1UL << ETM_TRCSSPCICR0_PC0_Pos) /*!< Bit mask of PC0 field.                               */
19488   #define ETM_TRCSSPCICR0_PC0_Min (0x0UL)            /*!< Min enumerator value of PC0 field.                                   */
19489   #define ETM_TRCSSPCICR0_PC0_Max (0x1UL)            /*!< Max enumerator value of PC0 field.                                   */
19490   #define ETM_TRCSSPCICR0_PC0_Disabled (0x0UL)       /*!< Processor comparator 0 is not selected for Single-shot control.      */
19491   #define ETM_TRCSSPCICR0_PC0_Enabled (0x1UL)        /*!< Processor comparator 0 is selected for Single-shot control.          */
19492 
19493 /* PC1 @Bit 1 : Selects processor comparator 1 inputs for Single-shot control */
19494   #define ETM_TRCSSPCICR0_PC1_Pos (1UL)              /*!< Position of PC1 field.                                               */
19495   #define ETM_TRCSSPCICR0_PC1_Msk (0x1UL << ETM_TRCSSPCICR0_PC1_Pos) /*!< Bit mask of PC1 field.                               */
19496   #define ETM_TRCSSPCICR0_PC1_Min (0x0UL)            /*!< Min enumerator value of PC1 field.                                   */
19497   #define ETM_TRCSSPCICR0_PC1_Max (0x1UL)            /*!< Max enumerator value of PC1 field.                                   */
19498   #define ETM_TRCSSPCICR0_PC1_Disabled (0x0UL)       /*!< Processor comparator 1 is not selected for Single-shot control.      */
19499   #define ETM_TRCSSPCICR0_PC1_Enabled (0x1UL)        /*!< Processor comparator 1 is selected for Single-shot control.          */
19500 
19501 /* PC2 @Bit 2 : Selects processor comparator 2 inputs for Single-shot control */
19502   #define ETM_TRCSSPCICR0_PC2_Pos (2UL)              /*!< Position of PC2 field.                                               */
19503   #define ETM_TRCSSPCICR0_PC2_Msk (0x1UL << ETM_TRCSSPCICR0_PC2_Pos) /*!< Bit mask of PC2 field.                               */
19504   #define ETM_TRCSSPCICR0_PC2_Min (0x0UL)            /*!< Min enumerator value of PC2 field.                                   */
19505   #define ETM_TRCSSPCICR0_PC2_Max (0x1UL)            /*!< Max enumerator value of PC2 field.                                   */
19506   #define ETM_TRCSSPCICR0_PC2_Disabled (0x0UL)       /*!< Processor comparator 2 is not selected for Single-shot control.      */
19507   #define ETM_TRCSSPCICR0_PC2_Enabled (0x1UL)        /*!< Processor comparator 2 is selected for Single-shot control.          */
19508 
19509 /* PC3 @Bit 3 : Selects processor comparator 3 inputs for Single-shot control */
19510   #define ETM_TRCSSPCICR0_PC3_Pos (3UL)              /*!< Position of PC3 field.                                               */
19511   #define ETM_TRCSSPCICR0_PC3_Msk (0x1UL << ETM_TRCSSPCICR0_PC3_Pos) /*!< Bit mask of PC3 field.                               */
19512   #define ETM_TRCSSPCICR0_PC3_Min (0x0UL)            /*!< Min enumerator value of PC3 field.                                   */
19513   #define ETM_TRCSSPCICR0_PC3_Max (0x1UL)            /*!< Max enumerator value of PC3 field.                                   */
19514   #define ETM_TRCSSPCICR0_PC3_Disabled (0x0UL)       /*!< Processor comparator 3 is not selected for Single-shot control.      */
19515   #define ETM_TRCSSPCICR0_PC3_Enabled (0x1UL)        /*!< Processor comparator 3 is selected for Single-shot control.          */
19516 
19517 
19518 /* ETM_TRCPDCR: Controls the single-shot comparator. */
19519   #define ETM_TRCPDCR_ResetValue (0x00000000UL)      /*!< Reset value of TRCPDCR register.                                     */
19520 
19521 /* PU @Bit 24 : Power up request, to request that power to ETM and access to the trace registers is maintained. */
19522   #define ETM_TRCPDCR_PU_Pos (24UL)                  /*!< Position of PU field.                                                */
19523   #define ETM_TRCPDCR_PU_Msk (0x1UL << ETM_TRCPDCR_PU_Pos) /*!< Bit mask of PU field.                                          */
19524   #define ETM_TRCPDCR_PU_Min (0x0UL)                 /*!< Min enumerator value of PU field.                                    */
19525   #define ETM_TRCPDCR_PU_Max (0x1UL)                 /*!< Max enumerator value of PU field.                                    */
19526   #define ETM_TRCPDCR_PU_Disabled (0x0UL)            /*!< Power not requested.                                                 */
19527   #define ETM_TRCPDCR_PU_Enabled (0x1UL)             /*!< Power requested.                                                     */
19528 
19529 
19530 /* ETM_TRCPDSR: Indicates the power down status of the ETM. */
19531   #define ETM_TRCPDSR_ResetValue (0x00000000UL)      /*!< Reset value of TRCPDSR register.                                     */
19532 
19533 /* POWER @Bit 0 : Indicates ETM is powered up */
19534   #define ETM_TRCPDSR_POWER_Pos (0UL)                /*!< Position of POWER field.                                             */
19535   #define ETM_TRCPDSR_POWER_Msk (0x1UL << ETM_TRCPDSR_POWER_Pos) /*!< Bit mask of POWER field.                                 */
19536   #define ETM_TRCPDSR_POWER_Min (0x0UL)              /*!< Min enumerator value of POWER field.                                 */
19537   #define ETM_TRCPDSR_POWER_Max (0x1UL)              /*!< Max enumerator value of POWER field.                                 */
19538   #define ETM_TRCPDSR_POWER_NotPoweredUp (0x0UL)     /*!< ETM is not powered up. All registers are not accessible.             */
19539   #define ETM_TRCPDSR_POWER_PoweredUp (0x1UL)        /*!< ETM is powered up. All registers are accessible.                     */
19540 
19541 /* STICKYPD @Bit 1 : Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that
19542                      programming state has been lost. It is cleared after a read of the TRCPDSR */
19543 
19544   #define ETM_TRCPDSR_STICKYPD_Pos (1UL)             /*!< Position of STICKYPD field.                                          */
19545   #define ETM_TRCPDSR_STICKYPD_Msk (0x1UL << ETM_TRCPDSR_STICKYPD_Pos) /*!< Bit mask of STICKYPD field.                        */
19546   #define ETM_TRCPDSR_STICKYPD_Min (0x0UL)           /*!< Min enumerator value of STICKYPD field.                              */
19547   #define ETM_TRCPDSR_STICKYPD_Max (0x1UL)           /*!< Max enumerator value of STICKYPD field.                              */
19548   #define ETM_TRCPDSR_STICKYPD_NotPoweredDown (0x0UL) /*!< Trace register power has not been removed since the TRCPDSR was last
19549                                                            read.*/
19550   #define ETM_TRCPDSR_STICKYPD_PoweredDown (0x1UL)   /*!< Trace register power has been removed since the TRCPDSR was last
19551                                                           read.*/
19552 
19553 
19554 /* ETM_TRCITATBIDR: Sets the state of output pins. */
19555   #define ETM_TRCITATBIDR_ResetValue (0x00000000UL)  /*!< Reset value of TRCITATBIDR register.                                 */
19556 
19557 /* ID0 @Bit 0 : Drives the ATIDMI[0] output pin. */
19558   #define ETM_TRCITATBIDR_ID0_Pos (0UL)              /*!< Position of ID0 field.                                               */
19559   #define ETM_TRCITATBIDR_ID0_Msk (0x1UL << ETM_TRCITATBIDR_ID0_Pos) /*!< Bit mask of ID0 field.                               */
19560 
19561 /* ID1 @Bit 1 : Drives the ATIDMI[1] output pin. */
19562   #define ETM_TRCITATBIDR_ID1_Pos (1UL)              /*!< Position of ID1 field.                                               */
19563   #define ETM_TRCITATBIDR_ID1_Msk (0x1UL << ETM_TRCITATBIDR_ID1_Pos) /*!< Bit mask of ID1 field.                               */
19564 
19565 /* ID2 @Bit 2 : Drives the ATIDMI[2] output pin. */
19566   #define ETM_TRCITATBIDR_ID2_Pos (2UL)              /*!< Position of ID2 field.                                               */
19567   #define ETM_TRCITATBIDR_ID2_Msk (0x1UL << ETM_TRCITATBIDR_ID2_Pos) /*!< Bit mask of ID2 field.                               */
19568 
19569 /* ID3 @Bit 3 : Drives the ATIDMI[3] output pin. */
19570   #define ETM_TRCITATBIDR_ID3_Pos (3UL)              /*!< Position of ID3 field.                                               */
19571   #define ETM_TRCITATBIDR_ID3_Msk (0x1UL << ETM_TRCITATBIDR_ID3_Pos) /*!< Bit mask of ID3 field.                               */
19572 
19573 /* ID4 @Bit 4 : Drives the ATIDMI[4] output pin. */
19574   #define ETM_TRCITATBIDR_ID4_Pos (4UL)              /*!< Position of ID4 field.                                               */
19575   #define ETM_TRCITATBIDR_ID4_Msk (0x1UL << ETM_TRCITATBIDR_ID4_Pos) /*!< Bit mask of ID4 field.                               */
19576 
19577 /* ID5 @Bit 5 : Drives the ATIDMI[5] output pin. */
19578   #define ETM_TRCITATBIDR_ID5_Pos (5UL)              /*!< Position of ID5 field.                                               */
19579   #define ETM_TRCITATBIDR_ID5_Msk (0x1UL << ETM_TRCITATBIDR_ID5_Pos) /*!< Bit mask of ID5 field.                               */
19580 
19581 /* ID6 @Bit 6 : Drives the ATIDMI[6] output pin. */
19582   #define ETM_TRCITATBIDR_ID6_Pos (6UL)              /*!< Position of ID6 field.                                               */
19583   #define ETM_TRCITATBIDR_ID6_Msk (0x1UL << ETM_TRCITATBIDR_ID6_Pos) /*!< Bit mask of ID6 field.                               */
19584 
19585 
19586 /* ETM_TRCITIATBINR: Reads the state of the input pins. */
19587   #define ETM_TRCITIATBINR_ResetValue (0x00000000UL) /*!< Reset value of TRCITIATBINR register.                                */
19588 
19589 /* ATVALID @Bit 0 : Returns the value of the ATVALIDMI input pin. */
19590   #define ETM_TRCITIATBINR_ATVALID_Pos (0UL)         /*!< Position of ATVALID field.                                           */
19591   #define ETM_TRCITIATBINR_ATVALID_Msk (0x1UL << ETM_TRCITIATBINR_ATVALID_Pos) /*!< Bit mask of ATVALID field.                 */
19592 
19593 /* AFREADY @Bit 1 : Returns the value of the AFREADYMI input pin. */
19594   #define ETM_TRCITIATBINR_AFREADY_Pos (1UL)         /*!< Position of AFREADY field.                                           */
19595   #define ETM_TRCITIATBINR_AFREADY_Msk (0x1UL << ETM_TRCITIATBINR_AFREADY_Pos) /*!< Bit mask of AFREADY field.                 */
19596 
19597 
19598 /* ETM_TRCITIATBOUTR: Sets the state of the output pins. */
19599   #define ETM_TRCITIATBOUTR_ResetValue (0x00000000UL) /*!< Reset value of TRCITIATBOUTR register.                              */
19600 
19601 /* ATVALID @Bit 0 : Drives the ATVALIDMI output pin. */
19602   #define ETM_TRCITIATBOUTR_ATVALID_Pos (0UL)        /*!< Position of ATVALID field.                                           */
19603   #define ETM_TRCITIATBOUTR_ATVALID_Msk (0x1UL << ETM_TRCITIATBOUTR_ATVALID_Pos) /*!< Bit mask of ATVALID field.               */
19604 
19605 /* AFREADY @Bit 1 : Drives the AFREADYMI output pin. */
19606   #define ETM_TRCITIATBOUTR_AFREADY_Pos (1UL)        /*!< Position of AFREADY field.                                           */
19607   #define ETM_TRCITIATBOUTR_AFREADY_Msk (0x1UL << ETM_TRCITIATBOUTR_AFREADY_Pos) /*!< Bit mask of AFREADY field.               */
19608 
19609 
19610 /* ETM_TRCITCTRL: Enables topology detection or integration testing, by putting ETM-M33 into integration mode. */
19611   #define ETM_TRCITCTRL_ResetValue (0x00000000UL)    /*!< Reset value of TRCITCTRL register.                                   */
19612 
19613 /* IME @Bit 0 : Integration mode enable */
19614   #define ETM_TRCITCTRL_IME_Pos (0UL)                /*!< Position of IME field.                                               */
19615   #define ETM_TRCITCTRL_IME_Msk (0x1UL << ETM_TRCITCTRL_IME_Pos) /*!< Bit mask of IME field.                                   */
19616   #define ETM_TRCITCTRL_IME_Min (0x0UL)              /*!< Min enumerator value of IME field.                                   */
19617   #define ETM_TRCITCTRL_IME_Max (0x1UL)              /*!< Max enumerator value of IME field.                                   */
19618   #define ETM_TRCITCTRL_IME_Disabled (0x0UL)         /*!< ETM is not in integration mode.                                      */
19619   #define ETM_TRCITCTRL_IME_Enabled (0x1UL)          /*!< ETM is in integration mode.                                          */
19620 
19621 
19622 /* ETM_TRCCLAIMSET: Sets bits in the claim tag and determines the number of claim tag bits implemented. */
19623   #define ETM_TRCCLAIMSET_ResetValue (0x00000000UL)  /*!< Reset value of TRCCLAIMSET register.                                 */
19624 
19625 /* SET0 @Bit 0 : Claim tag set register */
19626   #define ETM_TRCCLAIMSET_SET0_Pos (0UL)             /*!< Position of SET0 field.                                              */
19627   #define ETM_TRCCLAIMSET_SET0_Msk (0x1UL << ETM_TRCCLAIMSET_SET0_Pos) /*!< Bit mask of SET0 field.                            */
19628   #define ETM_TRCCLAIMSET_SET0_Min (0x0UL)           /*!< Min enumerator value of SET0 field.                                  */
19629   #define ETM_TRCCLAIMSET_SET0_Max (0x1UL)           /*!< Max enumerator value of SET0 field.                                  */
19630   #define ETM_TRCCLAIMSET_SET0_NotSet (0x0UL)        /*!< Claim tag 0 is not set.                                              */
19631   #define ETM_TRCCLAIMSET_SET0_Set (0x1UL)           /*!< Claim tag 0 is set.                                                  */
19632   #define ETM_TRCCLAIMSET_SET0_Claim (0x1UL)         /*!< Set claim tag 0.                                                     */
19633 
19634 /* SET1 @Bit 1 : Claim tag set register */
19635   #define ETM_TRCCLAIMSET_SET1_Pos (1UL)             /*!< Position of SET1 field.                                              */
19636   #define ETM_TRCCLAIMSET_SET1_Msk (0x1UL << ETM_TRCCLAIMSET_SET1_Pos) /*!< Bit mask of SET1 field.                            */
19637   #define ETM_TRCCLAIMSET_SET1_Min (0x0UL)           /*!< Min enumerator value of SET1 field.                                  */
19638   #define ETM_TRCCLAIMSET_SET1_Max (0x1UL)           /*!< Max enumerator value of SET1 field.                                  */
19639   #define ETM_TRCCLAIMSET_SET1_NotSet (0x0UL)        /*!< Claim tag 1 is not set.                                              */
19640   #define ETM_TRCCLAIMSET_SET1_Set (0x1UL)           /*!< Claim tag 1 is set.                                                  */
19641   #define ETM_TRCCLAIMSET_SET1_Claim (0x1UL)         /*!< Set claim tag 1.                                                     */
19642 
19643 /* SET2 @Bit 2 : Claim tag set register */
19644   #define ETM_TRCCLAIMSET_SET2_Pos (2UL)             /*!< Position of SET2 field.                                              */
19645   #define ETM_TRCCLAIMSET_SET2_Msk (0x1UL << ETM_TRCCLAIMSET_SET2_Pos) /*!< Bit mask of SET2 field.                            */
19646   #define ETM_TRCCLAIMSET_SET2_Min (0x0UL)           /*!< Min enumerator value of SET2 field.                                  */
19647   #define ETM_TRCCLAIMSET_SET2_Max (0x1UL)           /*!< Max enumerator value of SET2 field.                                  */
19648   #define ETM_TRCCLAIMSET_SET2_NotSet (0x0UL)        /*!< Claim tag 2 is not set.                                              */
19649   #define ETM_TRCCLAIMSET_SET2_Set (0x1UL)           /*!< Claim tag 2 is set.                                                  */
19650   #define ETM_TRCCLAIMSET_SET2_Claim (0x1UL)         /*!< Set claim tag 2.                                                     */
19651 
19652 /* SET3 @Bit 3 : Claim tag set register */
19653   #define ETM_TRCCLAIMSET_SET3_Pos (3UL)             /*!< Position of SET3 field.                                              */
19654   #define ETM_TRCCLAIMSET_SET3_Msk (0x1UL << ETM_TRCCLAIMSET_SET3_Pos) /*!< Bit mask of SET3 field.                            */
19655   #define ETM_TRCCLAIMSET_SET3_Min (0x0UL)           /*!< Min enumerator value of SET3 field.                                  */
19656   #define ETM_TRCCLAIMSET_SET3_Max (0x1UL)           /*!< Max enumerator value of SET3 field.                                  */
19657   #define ETM_TRCCLAIMSET_SET3_NotSet (0x0UL)        /*!< Claim tag 3 is not set.                                              */
19658   #define ETM_TRCCLAIMSET_SET3_Set (0x1UL)           /*!< Claim tag 3 is set.                                                  */
19659   #define ETM_TRCCLAIMSET_SET3_Claim (0x1UL)         /*!< Set claim tag 3.                                                     */
19660 
19661 
19662 /* ETM_TRCCLAIMCLR: Clears bits in the claim tag and determines the current value of the claim tag. */
19663   #define ETM_TRCCLAIMCLR_ResetValue (0x00000000UL)  /*!< Reset value of TRCCLAIMCLR register.                                 */
19664 
19665 /* CLR0 @Bit 0 : Claim tag clear register */
19666   #define ETM_TRCCLAIMCLR_CLR0_Pos (0UL)             /*!< Position of CLR0 field.                                              */
19667   #define ETM_TRCCLAIMCLR_CLR0_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR0_Pos) /*!< Bit mask of CLR0 field.                            */
19668   #define ETM_TRCCLAIMCLR_CLR0_Min (0x0UL)           /*!< Min enumerator value of CLR0 field.                                  */
19669   #define ETM_TRCCLAIMCLR_CLR0_Max (0x1UL)           /*!< Max enumerator value of CLR0 field.                                  */
19670   #define ETM_TRCCLAIMCLR_CLR0_NotSet (0x0UL)        /*!< Claim tag 0 is not set.                                              */
19671   #define ETM_TRCCLAIMCLR_CLR0_Set (0x1UL)           /*!< Claim tag 0 is set.                                                  */
19672   #define ETM_TRCCLAIMCLR_CLR0_Clear (0x1UL)         /*!< Clear claim tag 0.                                                   */
19673 
19674 /* CLR1 @Bit 1 : Claim tag clear register */
19675   #define ETM_TRCCLAIMCLR_CLR1_Pos (1UL)             /*!< Position of CLR1 field.                                              */
19676   #define ETM_TRCCLAIMCLR_CLR1_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR1_Pos) /*!< Bit mask of CLR1 field.                            */
19677   #define ETM_TRCCLAIMCLR_CLR1_Min (0x0UL)           /*!< Min enumerator value of CLR1 field.                                  */
19678   #define ETM_TRCCLAIMCLR_CLR1_Max (0x1UL)           /*!< Max enumerator value of CLR1 field.                                  */
19679   #define ETM_TRCCLAIMCLR_CLR1_NotSet (0x0UL)        /*!< Claim tag 1 is not set.                                              */
19680   #define ETM_TRCCLAIMCLR_CLR1_Set (0x1UL)           /*!< Claim tag 1 is set.                                                  */
19681   #define ETM_TRCCLAIMCLR_CLR1_Clear (0x1UL)         /*!< Clear claim tag 1.                                                   */
19682 
19683 /* CLR2 @Bit 2 : Claim tag clear register */
19684   #define ETM_TRCCLAIMCLR_CLR2_Pos (2UL)             /*!< Position of CLR2 field.                                              */
19685   #define ETM_TRCCLAIMCLR_CLR2_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR2_Pos) /*!< Bit mask of CLR2 field.                            */
19686   #define ETM_TRCCLAIMCLR_CLR2_Min (0x0UL)           /*!< Min enumerator value of CLR2 field.                                  */
19687   #define ETM_TRCCLAIMCLR_CLR2_Max (0x1UL)           /*!< Max enumerator value of CLR2 field.                                  */
19688   #define ETM_TRCCLAIMCLR_CLR2_NotSet (0x0UL)        /*!< Claim tag 2 is not set.                                              */
19689   #define ETM_TRCCLAIMCLR_CLR2_Set (0x1UL)           /*!< Claim tag 2 is set.                                                  */
19690   #define ETM_TRCCLAIMCLR_CLR2_Clear (0x1UL)         /*!< Clear claim tag 2.                                                   */
19691 
19692 /* CLR3 @Bit 3 : Claim tag clear register */
19693   #define ETM_TRCCLAIMCLR_CLR3_Pos (3UL)             /*!< Position of CLR3 field.                                              */
19694   #define ETM_TRCCLAIMCLR_CLR3_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR3_Pos) /*!< Bit mask of CLR3 field.                            */
19695   #define ETM_TRCCLAIMCLR_CLR3_Min (0x0UL)           /*!< Min enumerator value of CLR3 field.                                  */
19696   #define ETM_TRCCLAIMCLR_CLR3_Max (0x1UL)           /*!< Max enumerator value of CLR3 field.                                  */
19697   #define ETM_TRCCLAIMCLR_CLR3_NotSet (0x0UL)        /*!< Claim tag 3 is not set.                                              */
19698   #define ETM_TRCCLAIMCLR_CLR3_Set (0x1UL)           /*!< Claim tag 3 is set.                                                  */
19699   #define ETM_TRCCLAIMCLR_CLR3_Clear (0x1UL)         /*!< Clear claim tag 3.                                                   */
19700 
19701 
19702 /* ETM_TRCAUTHSTATUS: Indicates the current level of tracing permitted by the system */
19703   #define ETM_TRCAUTHSTATUS_ResetValue (0x00000000UL) /*!< Reset value of TRCAUTHSTATUS register.                              */
19704 
19705 /* NSID @Bits 0..1 : Non-secure Invasive Debug */
19706   #define ETM_TRCAUTHSTATUS_NSID_Pos (0UL)           /*!< Position of NSID field.                                              */
19707   #define ETM_TRCAUTHSTATUS_NSID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field.                        */
19708   #define ETM_TRCAUTHSTATUS_NSID_Min (0x0UL)         /*!< Min enumerator value of NSID field.                                  */
19709   #define ETM_TRCAUTHSTATUS_NSID_Max (0x1UL)         /*!< Max enumerator value of NSID field.                                  */
19710   #define ETM_TRCAUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                   */
19711   #define ETM_TRCAUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented.                                          */
19712 
19713 /* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */
19714   #define ETM_TRCAUTHSTATUS_NSNID_Pos (2UL)          /*!< Position of NSNID field.                                             */
19715   #define ETM_TRCAUTHSTATUS_NSNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field.                     */
19716   #define ETM_TRCAUTHSTATUS_NSNID_Min (0x0UL)        /*!< Min enumerator value of NSNID field.                                 */
19717   #define ETM_TRCAUTHSTATUS_NSNID_Max (0x1UL)        /*!< Max enumerator value of NSNID field.                                 */
19718   #define ETM_TRCAUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                  */
19719   #define ETM_TRCAUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented.                                         */
19720 
19721 /* SID @Bits 4..5 : Secure Invasive Debug */
19722   #define ETM_TRCAUTHSTATUS_SID_Pos (4UL)            /*!< Position of SID field.                                               */
19723   #define ETM_TRCAUTHSTATUS_SID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SID_Pos) /*!< Bit mask of SID field.                           */
19724   #define ETM_TRCAUTHSTATUS_SID_Min (0x0UL)          /*!< Min enumerator value of SID field.                                   */
19725   #define ETM_TRCAUTHSTATUS_SID_Max (0x1UL)          /*!< Max enumerator value of SID field.                                   */
19726   #define ETM_TRCAUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                    */
19727   #define ETM_TRCAUTHSTATUS_SID_Implemented (0x1UL)  /*!< The feature is implemented.                                          */
19728 
19729 /* SNID @Bits 6..7 : Secure Non-Invasive Debug */
19730   #define ETM_TRCAUTHSTATUS_SNID_Pos (6UL)           /*!< Position of SNID field.                                              */
19731   #define ETM_TRCAUTHSTATUS_SNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field.                        */
19732   #define ETM_TRCAUTHSTATUS_SNID_Min (0x0UL)         /*!< Min enumerator value of SNID field.                                  */
19733   #define ETM_TRCAUTHSTATUS_SNID_Max (0x1UL)         /*!< Max enumerator value of SNID field.                                  */
19734   #define ETM_TRCAUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                   */
19735   #define ETM_TRCAUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented.                                          */
19736 
19737 
19738 /* ETM_TRCDEVARCH: The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component */
19739   #define ETM_TRCDEVARCH_ResetValue (0x00000000UL)   /*!< Reset value of TRCDEVARCH register.                                  */
19740 
19741 /* ARCHID @Bits 0..15 : Architecture ID */
19742   #define ETM_TRCDEVARCH_ARCHID_Pos (0UL)            /*!< Position of ARCHID field.                                            */
19743   #define ETM_TRCDEVARCH_ARCHID_Msk (0xFFFFUL << ETM_TRCDEVARCH_ARCHID_Pos) /*!< Bit mask of ARCHID field.                     */
19744   #define ETM_TRCDEVARCH_ARCHID_Min (0x4A13UL)       /*!< Min enumerator value of ARCHID field.                                */
19745   #define ETM_TRCDEVARCH_ARCHID_Max (0x4A13UL)       /*!< Max enumerator value of ARCHID field.                                */
19746   #define ETM_TRCDEVARCH_ARCHID_ETMv42 (0x4A13UL)    /*!< Component is an ETMv4 component                                      */
19747 
19748 /* REVISION @Bits 16..19 : Architecture revision */
19749   #define ETM_TRCDEVARCH_REVISION_Pos (16UL)         /*!< Position of REVISION field.                                          */
19750   #define ETM_TRCDEVARCH_REVISION_Msk (0xFUL << ETM_TRCDEVARCH_REVISION_Pos) /*!< Bit mask of REVISION field.                  */
19751   #define ETM_TRCDEVARCH_REVISION_Min (0x2UL)        /*!< Min enumerator value of REVISION field.                              */
19752   #define ETM_TRCDEVARCH_REVISION_Max (0x2UL)        /*!< Max enumerator value of REVISION field.                              */
19753   #define ETM_TRCDEVARCH_REVISION_v2 (0x2UL)         /*!< Component is part of architecture 4.2                                */
19754 
19755 /* PRESENT @Bit 20 : This register is implemented */
19756   #define ETM_TRCDEVARCH_PRESENT_Pos (20UL)          /*!< Position of PRESENT field.                                           */
19757   #define ETM_TRCDEVARCH_PRESENT_Msk (0x1UL << ETM_TRCDEVARCH_PRESENT_Pos) /*!< Bit mask of PRESENT field.                     */
19758   #define ETM_TRCDEVARCH_PRESENT_Min (0x0UL)         /*!< Min enumerator value of PRESENT field.                               */
19759   #define ETM_TRCDEVARCH_PRESENT_Max (0x1UL)         /*!< Max enumerator value of PRESENT field.                               */
19760   #define ETM_TRCDEVARCH_PRESENT_Absent (0x0UL)      /*!< The register is not implemented.                                     */
19761   #define ETM_TRCDEVARCH_PRESENT_Present (0x1UL)     /*!< The register is implemented.                                         */
19762 
19763 /* ARCHITECT @Bits 21..31 : Defines the architect of the component */
19764   #define ETM_TRCDEVARCH_ARCHITECT_Pos (21UL)        /*!< Position of ARCHITECT field.                                         */
19765   #define ETM_TRCDEVARCH_ARCHITECT_Msk (0x7FFUL << ETM_TRCDEVARCH_ARCHITECT_Pos) /*!< Bit mask of ARCHITECT field.             */
19766   #define ETM_TRCDEVARCH_ARCHITECT_Min (0x23BUL)     /*!< Min enumerator value of ARCHITECT field.                             */
19767   #define ETM_TRCDEVARCH_ARCHITECT_Max (0x23BUL)     /*!< Max enumerator value of ARCHITECT field.                             */
19768   #define ETM_TRCDEVARCH_ARCHITECT_Arm (0x23BUL)     /*!< This peripheral was architected by Arm.                              */
19769 
19770 
19771 /* ETM_TRCDEVTYPE: Controls the single-shot comparator. */
19772   #define ETM_TRCDEVTYPE_ResetValue (0x00000000UL)   /*!< Reset value of TRCDEVTYPE register.                                  */
19773 
19774 /* MAJOR @Bits 0..3 : The main type of the component */
19775   #define ETM_TRCDEVTYPE_MAJOR_Pos (0UL)             /*!< Position of MAJOR field.                                             */
19776   #define ETM_TRCDEVTYPE_MAJOR_Msk (0xFUL << ETM_TRCDEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field.                           */
19777   #define ETM_TRCDEVTYPE_MAJOR_Min (0x3UL)           /*!< Min enumerator value of MAJOR field.                                 */
19778   #define ETM_TRCDEVTYPE_MAJOR_Max (0x3UL)           /*!< Max enumerator value of MAJOR field.                                 */
19779   #define ETM_TRCDEVTYPE_MAJOR_TraceSource (0x3UL)   /*!< Peripheral is a trace source.                                        */
19780 
19781 /* SUB @Bits 4..7 : The sub-type of the component */
19782   #define ETM_TRCDEVTYPE_SUB_Pos (4UL)               /*!< Position of SUB field.                                               */
19783   #define ETM_TRCDEVTYPE_SUB_Msk (0xFUL << ETM_TRCDEVTYPE_SUB_Pos) /*!< Bit mask of SUB field.                                 */
19784   #define ETM_TRCDEVTYPE_SUB_Min (0x1UL)             /*!< Min enumerator value of SUB field.                                   */
19785   #define ETM_TRCDEVTYPE_SUB_Max (0x1UL)             /*!< Max enumerator value of SUB field.                                   */
19786   #define ETM_TRCDEVTYPE_SUB_ProcessorTrace (0x1UL)  /*!< Peripheral is a processor trace source.                              */
19787 
19788 
19789 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
19790 
19791 /* =========================================================================================================================== */
19792 /* ================                                            ETR                                            ================ */
19793 /* =========================================================================================================================== */
19794 
19795 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
19796 /* ======================================================= Struct ETR ======================================================== */
19797 /**
19798   * @brief Embedded Trace Router
19799   */
19800   typedef struct {                                   /*!< ETR Structure                                                        */
19801     __IM uint32_t RESERVED;
19802     __IOM uint32_t RSZ;                              /*!< (@ 0x00000004) RAM Size register                                     */
19803     __IM uint32_t RESERVED1;
19804     __IM uint32_t STS;                               /*!< (@ 0x0000000C) Status Register                                       */
19805     __IM uint32_t RRD;                               /*!< (@ 0x00000010) RAM Read Data Register                                */
19806     __IOM uint32_t RRP;                              /*!< (@ 0x00000014) RAM Read Pointer Register                             */
19807     __IOM uint32_t RWP;                              /*!< (@ 0x00000018) RAM Write Pointer Register                            */
19808     __IOM uint32_t TRG;                              /*!< (@ 0x0000001C) Trigger Counter Register                              */
19809     __IOM uint32_t CTL;                              /*!< (@ 0x00000020) Control Register                                      */
19810     __OM uint32_t RWD;                               /*!< (@ 0x00000024) RAM Write Data Register                               */
19811     __IOM uint32_t MODE;                             /*!< (@ 0x00000028) Mode Register                                         */
19812     __IM uint32_t LBUFLEVEL;                         /*!< (@ 0x0000002C) Latched Buffer Fill Level                             */
19813     __IM uint32_t CBUFLEVEL;                         /*!< (@ 0x00000030) Current Buffer Fill Level                             */
19814     __IOM uint32_t BUFWM;                            /*!< (@ 0x00000034) Buffer Level Water Mark                               */
19815     __IOM uint32_t RRPHI;                            /*!< (@ 0x00000038) RAM Read Pointer High Register                        */
19816     __IOM uint32_t RWPHI;                            /*!< (@ 0x0000003C) RAM Write Pointer High Register                       */
19817     __IM uint32_t RESERVED2[52];
19818     __IOM uint32_t AXICTL;                           /*!< (@ 0x00000110) AXI Control Register                                  */
19819     __IM uint32_t RESERVED3;
19820     __IOM uint32_t DBALO;                            /*!< (@ 0x00000118) Data Buffer Address Low Register                      */
19821     __IOM uint32_t DBAHI;                            /*!< (@ 0x0000011C) Data Buffer Address High Register                     */
19822     __IM uint32_t RESERVED4[120];
19823     __IM uint32_t FFSR;                              /*!< (@ 0x00000300) Formatter and Flush Status Register                   */
19824     __IOM uint32_t FFCR;                             /*!< (@ 0x00000304) Formatter and Flush Control Register                  */
19825     __IOM uint32_t PSCR;                             /*!< (@ 0x00000308) Periodic Synchronization Counter Register             */
19826     __IM uint32_t RESERVED5[756];
19827     __OM uint32_t ITATBMCTR0;                        /*!< (@ 0x00000EDC) Integration Test ATB Master Interface Control 0
19828                                                                          Register*/
19829     __OM uint32_t ITMISCOP0;                         /*!< (@ 0x00000EE0) Integration Test Miscellaneous Output Register 0      */
19830     __IM uint32_t RESERVED6;
19831     __IM uint32_t ITTRFLIN;                          /*!< (@ 0x00000EE8) Integration Test Trigger In and Flush In Register     */
19832     __IM uint32_t ITATBDATA0;                        /*!< (@ 0x00000EEC) Integration Test ATB Data Register 0                  */
19833     __OM uint32_t ITATBCTR2;                         /*!< (@ 0x00000EF0) Integration Test ATB Control 2 Register               */
19834     __IM uint32_t ITATBCTR1;                         /*!< (@ 0x00000EF4) Integration Test ATB Control 1 Register               */
19835     __IM uint32_t ITATBCTR0;                         /*!< (@ 0x00000EF8) Integration Test ATB Control 0 Register               */
19836     __IM uint32_t RESERVED7;
19837     __IOM uint32_t ITCTRL;                           /*!< (@ 0x00000F00) Integration Mode Control Register                     */
19838     __IM uint32_t RESERVED8[39];
19839     __IOM uint32_t CLAIMSET;                         /*!< (@ 0x00000FA0) Claim Tag Set Register                                */
19840     __IOM uint32_t CLAIMCLR;                         /*!< (@ 0x00000FA4) Claim Tag Clear Register                              */
19841     __IM uint32_t RESERVED9[2];
19842     __OM uint32_t LAR;                               /*!< (@ 0x00000FB0) Lock Access Register                                  */
19843     __IM uint32_t LSR;                               /*!< (@ 0x00000FB4) Lock Status Register                                  */
19844     __IM uint32_t AUTHSTATUS;                        /*!< (@ 0x00000FB8) Authentication Status Register                        */
19845     __IM uint32_t RESERVED10[3];
19846     __IM uint32_t DEVID;                             /*!< (@ 0x00000FC8) Device Configuration Register                         */
19847     __IM uint32_t DEVTYPE;                           /*!< (@ 0x00000FCC) Device Type Identifier Register                       */
19848     __IM uint32_t PERIPHID4;                         /*!< (@ 0x00000FD0) Peripheral ID4 Register                               */
19849     __IM uint32_t RESERVED11[3];
19850     __IM uint32_t PERIPHID0;                         /*!< (@ 0x00000FE0) Peripheral ID0 Register                               */
19851     __IM uint32_t PERIPHID1;                         /*!< (@ 0x00000FE4) Peripheral ID1 Register                               */
19852     __IM uint32_t PERIPHID2;                         /*!< (@ 0x00000FE8) Peripheral ID2 Register                               */
19853     __IM uint32_t PERIPHID3;                         /*!< (@ 0x00000FEC) Peripheral ID3 Register                               */
19854     __IM uint32_t COMPID0;                           /*!< (@ 0x00000FF0) Component ID0 Register                                */
19855     __IM uint32_t COMPID1;                           /*!< (@ 0x00000FF4) Component ID1 Register                                */
19856     __IM uint32_t COMPID2;                           /*!< (@ 0x00000FF8) Component ID2 Register                                */
19857     __IM uint32_t COMPID3;                           /*!< (@ 0x00000FFC) Component ID3 Register                                */
19858   } NRF_ETR_Type;                                    /*!< Size = 4096 (0x1000)                                                 */
19859 
19860 /* ETR_RSZ: RAM Size register */
19861   #define ETR_RSZ_ResetValue (0x00000000UL)          /*!< Reset value of RSZ register.                                         */
19862 
19863 /* RSZ @Bits 0..30 : Size of the RAM in 32-bit words. */
19864   #define ETR_RSZ_RSZ_Pos (0UL)                      /*!< Position of RSZ field.                                               */
19865   #define ETR_RSZ_RSZ_Msk (0x7FFFFFFFUL << ETR_RSZ_RSZ_Pos) /*!< Bit mask of RSZ field.                                        */
19866 
19867 
19868 /* ETR_STS: Status Register */
19869   #define ETR_STS_ResetValue (0x0000000CUL)          /*!< Reset value of STS register.                                         */
19870 
19871 /* FULL @Bit 0 : This bit can be used to help determine how much of the trace buffer contains valid data. */
19872   #define ETR_STS_FULL_Pos (0UL)                     /*!< Position of FULL field.                                              */
19873   #define ETR_STS_FULL_Msk (0x1UL << ETR_STS_FULL_Pos) /*!< Bit mask of FULL field.                                            */
19874 
19875 /* TRIGGERED @Bit 1 : The Triggered bit is set when trace capture is in progress and the TMC has detected a trigger event. */
19876   #define ETR_STS_TRIGGERED_Pos (1UL)                /*!< Position of TRIGGERED field.                                         */
19877   #define ETR_STS_TRIGGERED_Msk (0x1UL << ETR_STS_TRIGGERED_Pos) /*!< Bit mask of TRIGGERED field.                             */
19878 
19879 /* TMCREADY @Bit 2 : TMC ready */
19880   #define ETR_STS_TMCREADY_Pos (2UL)                 /*!< Position of TMCREADY field.                                          */
19881   #define ETR_STS_TMCREADY_Msk (0x1UL << ETR_STS_TMCREADY_Pos) /*!< Bit mask of TMCREADY field.                                */
19882 
19883 /* FTEMPTY @Bit 3 : This bit is set when trace capture has stopped, and all internal pipelines and buffers have drained. */
19884   #define ETR_STS_FTEMPTY_Pos (3UL)                  /*!< Position of FTEMPTY field.                                           */
19885   #define ETR_STS_FTEMPTY_Msk (0x1UL << ETR_STS_FTEMPTY_Pos) /*!< Bit mask of FTEMPTY field.                                   */
19886 
19887 /* EMPTY @Bit 4 : If set, this bit indicates that the TMC does not contain any valid trace data in the trace memory. */
19888   #define ETR_STS_EMPTY_Pos (4UL)                    /*!< Position of EMPTY field.                                             */
19889   #define ETR_STS_EMPTY_Msk (0x1UL << ETR_STS_EMPTY_Pos) /*!< Bit mask of EMPTY field.                                         */
19890 
19891 /* MEMERR @Bit 5 : This bit indicates that an error has occurred on the AXI master interface. */
19892   #define ETR_STS_MEMERR_Pos (5UL)                   /*!< Position of MEMERR field.                                            */
19893   #define ETR_STS_MEMERR_Msk (0x1UL << ETR_STS_MEMERR_Pos) /*!< Bit mask of MEMERR field.                                      */
19894 
19895 
19896 /* ETR_RRD: RAM Read Data Register */
19897   #define ETR_RRD_ResetValue (0x00000000UL)          /*!< Reset value of RRD register.                                         */
19898 
19899 /* RRD @Bits 0..31 : Reads return data from Trace RAM */
19900   #define ETR_RRD_RRD_Pos (0UL)                      /*!< Position of RRD field.                                               */
19901   #define ETR_RRD_RRD_Msk (0xFFFFFFFFUL << ETR_RRD_RRD_Pos) /*!< Bit mask of RRD field.                                        */
19902 
19903 
19904 /* ETR_RRP: RAM Read Pointer Register */
19905   #define ETR_RRP_ResetValue (0x00000000UL)          /*!< Reset value of RRP register.                                         */
19906 
19907 /* RRP @Bits 0..8 : This value represents the location in trace memory that will be accessed on a subsequent RRD read. */
19908   #define ETR_RRP_RRP_Pos (0UL)                      /*!< Position of RRP field.                                               */
19909   #define ETR_RRP_RRP_Msk (0x1FFUL << ETR_RRP_RRP_Pos) /*!< Bit mask of RRP field.                                             */
19910 
19911 
19912 /* ETR_RWP: RAM Write Pointer Register */
19913   #define ETR_RWP_ResetValue (0x00000000UL)          /*!< Reset value of RWP register.                                         */
19914 
19915 /* RWP @Bits 0..31 : This value represents the location in trace memory that will be accessed on a subsequent write to the trace
19916                      memory. */
19917 
19918   #define ETR_RWP_RWP_Pos (0UL)                      /*!< Position of RWP field.                                               */
19919   #define ETR_RWP_RWP_Msk (0xFFFFFFFFUL << ETR_RWP_RWP_Pos) /*!< Bit mask of RWP field.                                        */
19920 
19921 
19922 /* ETR_TRG: Trigger Counter Register */
19923   #define ETR_TRG_ResetValue (0x00000000UL)          /*!< Reset value of TRG register.                                         */
19924 
19925 /* TRG @Bits 0..31 : This count represents the number of 32-bit words between a TRIGIN/trigger packet and a trigger event. */
19926   #define ETR_TRG_TRG_Pos (0UL)                      /*!< Position of TRG field.                                               */
19927   #define ETR_TRG_TRG_Msk (0xFFFFFFFFUL << ETR_TRG_TRG_Pos) /*!< Bit mask of TRG field.                                        */
19928 
19929 
19930 /* ETR_CTL: Control Register */
19931   #define ETR_CTL_ResetValue (0x00000000UL)          /*!< Reset value of CTL register.                                         */
19932 
19933 /* TRACECAPTEN @Bit 0 : Setting this bit to 1 enables the TMC to capture trace data. */
19934   #define ETR_CTL_TRACECAPTEN_Pos (0UL)              /*!< Position of TRACECAPTEN field.                                       */
19935   #define ETR_CTL_TRACECAPTEN_Msk (0x1UL << ETR_CTL_TRACECAPTEN_Pos) /*!< Bit mask of TRACECAPTEN field.                       */
19936 
19937 
19938 /* ETR_RWD: RAM Write Data Register */
19939   #define ETR_RWD_ResetValue (0x00000000UL)          /*!< Reset value of RWD register.                                         */
19940 
19941 /* RWD @Bits 0..31 : Data written to this register is placed in the Trace RAM. */
19942   #define ETR_RWD_RWD_Pos (0UL)                      /*!< Position of RWD field.                                               */
19943   #define ETR_RWD_RWD_Msk (0xFFFFFFFFUL << ETR_RWD_RWD_Pos) /*!< Bit mask of RWD field.                                        */
19944 
19945 
19946 /* ETR_MODE: Mode Register */
19947   #define ETR_MODE_ResetValue (0x00000000UL)         /*!< Reset value of MODE register.                                        */
19948 
19949 /* MODE @Bits 0..1 : Selects the operating mode. */
19950   #define ETR_MODE_MODE_Pos (0UL)                    /*!< Position of MODE field.                                              */
19951   #define ETR_MODE_MODE_Msk (0x3UL << ETR_MODE_MODE_Pos) /*!< Bit mask of MODE field.                                          */
19952   #define ETR_MODE_MODE_Min (0x0UL)                  /*!< Min enumerator value of MODE field.                                  */
19953   #define ETR_MODE_MODE_Max (0x1UL)                  /*!< Max enumerator value of MODE field.                                  */
19954   #define ETR_MODE_MODE_CIRCULARBUF (0x0UL)          /*!< Circular Buffer mode                                                 */
19955   #define ETR_MODE_MODE_FIFO (0x1UL)                 /*!< Software FIFO mode                                                   */
19956 
19957 
19958 /* ETR_LBUFLEVEL: Latched Buffer Fill Level */
19959   #define ETR_LBUFLEVEL_ResetValue (0x00000000UL)    /*!< Reset value of LBUFLEVEL register.                                   */
19960 
19961 /* LBUFLEVEL @Bits 0..30 : Indicates the maximum fill level of the trace memory in 32-bit words since this register was last
19962                            read. */
19963 
19964   #define ETR_LBUFLEVEL_LBUFLEVEL_Pos (0UL)          /*!< Position of LBUFLEVEL field.                                         */
19965   #define ETR_LBUFLEVEL_LBUFLEVEL_Msk (0x7FFFFFFFUL << ETR_LBUFLEVEL_LBUFLEVEL_Pos) /*!< Bit mask of LBUFLEVEL field.          */
19966 
19967 
19968 /* ETR_CBUFLEVEL: Current Buffer Fill Level */
19969   #define ETR_CBUFLEVEL_ResetValue (0x00000000UL)    /*!< Reset value of CBUFLEVEL register.                                   */
19970 
19971 /* CBUFLEVEL @Bits 0..7 : Indicates the current fill level of the trace memory in 32-bit words. */
19972   #define ETR_CBUFLEVEL_CBUFLEVEL_Pos (0UL)          /*!< Position of CBUFLEVEL field.                                         */
19973   #define ETR_CBUFLEVEL_CBUFLEVEL_Msk (0xFFUL << ETR_CBUFLEVEL_CBUFLEVEL_Pos) /*!< Bit mask of CBUFLEVEL field.                */
19974 
19975 
19976 /* ETR_BUFWM: Buffer Level Water Mark */
19977   #define ETR_BUFWM_ResetValue (0x00000000UL)        /*!< Reset value of BUFWM register.                                       */
19978 
19979 /* BUFWM @Bits 0..6 : Indicates the desired threshold vacancy level in 32-bit words in the trace memory. */
19980   #define ETR_BUFWM_BUFWM_Pos (0UL)                  /*!< Position of BUFWM field.                                             */
19981   #define ETR_BUFWM_BUFWM_Msk (0x7FUL << ETR_BUFWM_BUFWM_Pos) /*!< Bit mask of BUFWM field.                                    */
19982 
19983 
19984 /* ETR_RRPHI: RAM Read Pointer High Register */
19985   #define ETR_RRPHI_ResetValue (0x00000000UL)        /*!< Reset value of RRPHI register.                                       */
19986 
19987 /* RRPHI @Bits 0..7 : Bits[39:32] of the read pointer */
19988   #define ETR_RRPHI_RRPHI_Pos (0UL)                  /*!< Position of RRPHI field.                                             */
19989   #define ETR_RRPHI_RRPHI_Msk (0xFFUL << ETR_RRPHI_RRPHI_Pos) /*!< Bit mask of RRPHI field.                                    */
19990 
19991 
19992 /* ETR_RWPHI: RAM Write Pointer High Register */
19993   #define ETR_RWPHI_ResetValue (0x00000000UL)        /*!< Reset value of RWPHI register.                                       */
19994 
19995 /* RWPHI @Bits 0..7 : Bits[39:32] of the write pointer */
19996   #define ETR_RWPHI_RWPHI_Pos (0UL)                  /*!< Position of RWPHI field.                                             */
19997   #define ETR_RWPHI_RWPHI_Msk (0xFFUL << ETR_RWPHI_RWPHI_Pos) /*!< Bit mask of RWPHI field.                                    */
19998 
19999 
20000 /* ETR_AXICTL: AXI Control Register */
20001   #define ETR_AXICTL_ResetValue (0x00000000UL)       /*!< Reset value of AXICTL register.                                      */
20002 
20003 /* PROTCTRLBIT0 @Bit 0 : This bit controls the value driven on ARPROTM[0]/AWPROTM[0] on the AXI interface when performing AXI
20004                          transfers. */
20005 
20006   #define ETR_AXICTL_PROTCTRLBIT0_Pos (0UL)          /*!< Position of PROTCTRLBIT0 field.                                      */
20007   #define ETR_AXICTL_PROTCTRLBIT0_Msk (0x1UL << ETR_AXICTL_PROTCTRLBIT0_Pos) /*!< Bit mask of PROTCTRLBIT0 field.              */
20008 
20009 /* PROTCTRLBIT1 @Bit 1 : This bit controls the value driven on ARPROTM[1]/AWPROTM[1] on the AXI interface when performing AXI
20010                          transfers. */
20011 
20012   #define ETR_AXICTL_PROTCTRLBIT1_Pos (1UL)          /*!< Position of PROTCTRLBIT1 field.                                      */
20013   #define ETR_AXICTL_PROTCTRLBIT1_Msk (0x1UL << ETR_AXICTL_PROTCTRLBIT1_Pos) /*!< Bit mask of PROTCTRLBIT1 field.              */
20014 
20015 /* CACHECTRLBIT0 @Bit 2 : This bit controls the value driven on the ARCACHEM[0]/AWCACHEM[0] signal on the AXI interface when
20016                           performing AXI transfers. */
20017 
20018   #define ETR_AXICTL_CACHECTRLBIT0_Pos (2UL)         /*!< Position of CACHECTRLBIT0 field.                                     */
20019   #define ETR_AXICTL_CACHECTRLBIT0_Msk (0x1UL << ETR_AXICTL_CACHECTRLBIT0_Pos) /*!< Bit mask of CACHECTRLBIT0 field.           */
20020 
20021 /* CACHECTRLBIT1 @Bit 3 : This bit controls the value driven on the ARCACHEM[1]/AWCACHEM[1] signal on the AXI interface when
20022                           performing AXI transfers. */
20023 
20024   #define ETR_AXICTL_CACHECTRLBIT1_Pos (3UL)         /*!< Position of CACHECTRLBIT1 field.                                     */
20025   #define ETR_AXICTL_CACHECTRLBIT1_Msk (0x1UL << ETR_AXICTL_CACHECTRLBIT1_Pos) /*!< Bit mask of CACHECTRLBIT1 field.           */
20026 
20027 /* CACHECTRLBIT2 @Bit 4 : This bit controls the value driven on the ARCACHEM[2]/AWCACHEM[2] signal on the AXI interface when
20028                           performing AXI transfers. */
20029 
20030   #define ETR_AXICTL_CACHECTRLBIT2_Pos (4UL)         /*!< Position of CACHECTRLBIT2 field.                                     */
20031   #define ETR_AXICTL_CACHECTRLBIT2_Msk (0x1UL << ETR_AXICTL_CACHECTRLBIT2_Pos) /*!< Bit mask of CACHECTRLBIT2 field.           */
20032 
20033 /* CACHECTRLBIT3 @Bit 5 : This bit controls the value driven on the ARCACHEM[3]/AWCACHEM[3] signal on the AXI interface when
20034                           performing AXI transfers. */
20035 
20036   #define ETR_AXICTL_CACHECTRLBIT3_Pos (5UL)         /*!< Position of CACHECTRLBIT3 field.                                     */
20037   #define ETR_AXICTL_CACHECTRLBIT3_Msk (0x1UL << ETR_AXICTL_CACHECTRLBIT3_Pos) /*!< Bit mask of CACHECTRLBIT3 field.           */
20038 
20039 /* SCATTERGATHERMODE @Bit 7 : This bit indicates whether trace memory is accessed as a single buffer in system memory or as a
20040                               linked-list based scatter-gather memory. */
20041 
20042   #define ETR_AXICTL_SCATTERGATHERMODE_Pos (7UL)     /*!< Position of SCATTERGATHERMODE field.                                 */
20043   #define ETR_AXICTL_SCATTERGATHERMODE_Msk (0x1UL << ETR_AXICTL_SCATTERGATHERMODE_Pos) /*!< Bit mask of SCATTERGATHERMODE
20044                                                                             field.*/
20045 
20046 /* WRBURSTLEN @Bits 8..11 : This field indicates the maximum number of data transfers that can occur within each burst initiated
20047                             by the TMC on the AXI interface. */
20048 
20049   #define ETR_AXICTL_WRBURSTLEN_Pos (8UL)            /*!< Position of WRBURSTLEN field.                                        */
20050   #define ETR_AXICTL_WRBURSTLEN_Msk (0xFUL << ETR_AXICTL_WRBURSTLEN_Pos) /*!< Bit mask of WRBURSTLEN field.                    */
20051 
20052 
20053 /* ETR_DBALO: Data Buffer Address Low Register */
20054   #define ETR_DBALO_ResetValue (0x00000000UL)        /*!< Reset value of DBALO register.                                       */
20055 
20056 /* BUFADDRLO @Bits 0..31 : Holds the lower 32 bits of the 40-bit address used to locate the trace buffer in system memory */
20057   #define ETR_DBALO_BUFADDRLO_Pos (0UL)              /*!< Position of BUFADDRLO field.                                         */
20058   #define ETR_DBALO_BUFADDRLO_Msk (0xFFFFFFFFUL << ETR_DBALO_BUFADDRLO_Pos) /*!< Bit mask of BUFADDRLO field.                  */
20059 
20060 
20061 /* ETR_DBAHI: Data Buffer Address High Register */
20062   #define ETR_DBAHI_ResetValue (0x00000000UL)        /*!< Reset value of DBAHI register.                                       */
20063 
20064 /* BUFADDRHI @Bits 0..7 : Holds the upper 8 bits of the 40-bit address used to locate the trace buffer in system memory */
20065   #define ETR_DBAHI_BUFADDRHI_Pos (0UL)              /*!< Position of BUFADDRHI field.                                         */
20066   #define ETR_DBAHI_BUFADDRHI_Msk (0xFFUL << ETR_DBAHI_BUFADDRHI_Pos) /*!< Bit mask of BUFADDRHI field.                        */
20067 
20068 
20069 /* ETR_FFSR: Formatter and Flush Status Register */
20070   #define ETR_FFSR_ResetValue (0x00000002UL)         /*!< Reset value of FFSR register.                                        */
20071 
20072 /* FLINPROG @Bit 0 : This bit indicates whether the TMC is currently processing a flush on the ATB slave port. This bit reflects
20073                      the status of the AFVALIDS output. The flush initiation is controlled by the flush-control bits in the FFCR
20074                      register. */
20075 
20076   #define ETR_FFSR_FLINPROG_Pos (0UL)                /*!< Position of FLINPROG field.                                          */
20077   #define ETR_FFSR_FLINPROG_Msk (0x1UL << ETR_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field.                              */
20078 
20079 /* FTSTOPPED @Bit 1 : This bit behaves the same way as the FtEmpty bit in the STS register, 0x00C. */
20080   #define ETR_FFSR_FTSTOPPED_Pos (1UL)               /*!< Position of FTSTOPPED field.                                         */
20081   #define ETR_FFSR_FTSTOPPED_Msk (0x1UL << ETR_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field.                           */
20082 
20083 
20084 /* ETR_FFCR: Formatter and Flush Control Register */
20085   #define ETR_FFCR_ResetValue (0x00000000UL)         /*!< Reset value of FFCR register.                                        */
20086 
20087 /* ENFT @Bit 0 : If this bit is set, formatting is enabled. */
20088   #define ETR_FFCR_ENFT_Pos (0UL)                    /*!< Position of ENFT field.                                              */
20089   #define ETR_FFCR_ENFT_Msk (0x1UL << ETR_FFCR_ENFT_Pos) /*!< Bit mask of ENFT field.                                          */
20090 
20091 /* ENTI @Bit 1 : Setting this bit enables the insertion of triggers in the formatted trace stream. */
20092   #define ETR_FFCR_ENTI_Pos (1UL)                    /*!< Position of ENTI field.                                              */
20093   #define ETR_FFCR_ENTI_Msk (0x1UL << ETR_FFCR_ENTI_Pos) /*!< Bit mask of ENTI field.                                          */
20094 
20095 /* FONFLIN @Bit 4 : Setting this bit enables the detection of transitions on the FLUSHIN input by the TMC. */
20096   #define ETR_FFCR_FONFLIN_Pos (4UL)                 /*!< Position of FONFLIN field.                                           */
20097   #define ETR_FFCR_FONFLIN_Msk (0x1UL << ETR_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field.                                 */
20098 
20099 /* FONTRIGEVT @Bit 5 : Setting this bit generates a flush when a Trigger event occurs. */
20100   #define ETR_FFCR_FONTRIGEVT_Pos (5UL)              /*!< Position of FONTRIGEVT field.                                        */
20101   #define ETR_FFCR_FONTRIGEVT_Msk (0x1UL << ETR_FFCR_FONTRIGEVT_Pos) /*!< Bit mask of FONTRIGEVT field.                        */
20102 
20103 /* FLUSHMAN @Bit 6 : Manually generate a flush of the system. */
20104   #define ETR_FFCR_FLUSHMAN_Pos (6UL)                /*!< Position of FLUSHMAN field.                                          */
20105   #define ETR_FFCR_FLUSHMAN_Msk (0x1UL << ETR_FFCR_FLUSHMAN_Pos) /*!< Bit mask of FLUSHMAN field.                              */
20106 
20107 /* TRIGONTRIGIN @Bit 8 : If this bit is set, a trigger is indicated on the trace stream when a rising edge is detected on the
20108                          TRIGIN input. */
20109 
20110   #define ETR_FFCR_TRIGONTRIGIN_Pos (8UL)            /*!< Position of TRIGONTRIGIN field.                                      */
20111   #define ETR_FFCR_TRIGONTRIGIN_Msk (0x1UL << ETR_FFCR_TRIGONTRIGIN_Pos) /*!< Bit mask of TRIGONTRIGIN field.                  */
20112 
20113 /* TRIGONTRIGEVT @Bit 9 : If this bit is set, a trigger is indicated on the output trace stream when a Trigger Event occurs. */
20114   #define ETR_FFCR_TRIGONTRIGEVT_Pos (9UL)           /*!< Position of TRIGONTRIGEVT field.                                     */
20115   #define ETR_FFCR_TRIGONTRIGEVT_Msk (0x1UL << ETR_FFCR_TRIGONTRIGEVT_Pos) /*!< Bit mask of TRIGONTRIGEVT field.               */
20116 
20117 /* TRIGONFL @Bit 10 : If this bit is set, a trigger is indicated on the trace stream on AFREADYS being returned. */
20118   #define ETR_FFCR_TRIGONFL_Pos (10UL)               /*!< Position of TRIGONFL field.                                          */
20119   #define ETR_FFCR_TRIGONFL_Msk (0x1UL << ETR_FFCR_TRIGONFL_Pos) /*!< Bit mask of TRIGONFL field.                              */
20120 
20121 /* STOPONFL @Bit 12 : If this bit is set, the formatter is stopped on completion of a flush operation. */
20122   #define ETR_FFCR_STOPONFL_Pos (12UL)               /*!< Position of STOPONFL field.                                          */
20123   #define ETR_FFCR_STOPONFL_Msk (0x1UL << ETR_FFCR_STOPONFL_Pos) /*!< Bit mask of STOPONFL field.                              */
20124 
20125 /* STOPONTRIGEVT @Bit 13 : If this bit is set, the formatter is stopped when a Trigger Event has been observed. */
20126   #define ETR_FFCR_STOPONTRIGEVT_Pos (13UL)          /*!< Position of STOPONTRIGEVT field.                                     */
20127   #define ETR_FFCR_STOPONTRIGEVT_Msk (0x1UL << ETR_FFCR_STOPONTRIGEVT_Pos) /*!< Bit mask of STOPONTRIGEVT field.               */
20128 
20129 /* DRAINBUFFER @Bit 14 : This bit is used to enable draining of the trace data through the ATB Master interface after the
20130                          formatter has stopped. */
20131 
20132   #define ETR_FFCR_DRAINBUFFER_Pos (14UL)            /*!< Position of DRAINBUFFER field.                                       */
20133   #define ETR_FFCR_DRAINBUFFER_Msk (0x1UL << ETR_FFCR_DRAINBUFFER_Pos) /*!< Bit mask of DRAINBUFFER field.                     */
20134 
20135 
20136 /* ETR_PSCR: Periodic Synchronization Counter Register */
20137   #define ETR_PSCR_ResetValue (0x00000000UL)         /*!< Reset value of PSCR register.                                        */
20138 
20139 /* PSCOUNT @Bits 0..4 : The reload value of the Synchronization Counter */
20140   #define ETR_PSCR_PSCOUNT_Pos (0UL)                 /*!< Position of PSCOUNT field.                                           */
20141   #define ETR_PSCR_PSCOUNT_Msk (0x1FUL << ETR_PSCR_PSCOUNT_Pos) /*!< Bit mask of PSCOUNT field.                                */
20142 
20143 
20144 /* ETR_ITATBMCTR0: Integration Test ATB Master Interface Control 0 Register */
20145   #define ETR_ITATBMCTR0_ResetValue (0x00000000UL)   /*!< Reset value of ITATBMCTR0 register.                                  */
20146 
20147 /* ATVALIDM @Bit 0 : Set the value of ATVALIDM output */
20148   #define ETR_ITATBMCTR0_ATVALIDM_Pos (0UL)          /*!< Position of ATVALIDM field.                                          */
20149   #define ETR_ITATBMCTR0_ATVALIDM_Msk (0x1UL << ETR_ITATBMCTR0_ATVALIDM_Pos) /*!< Bit mask of ATVALIDM field.                  */
20150 
20151 /* AFREADYM @Bit 1 : Set the value of AFREADYM output */
20152   #define ETR_ITATBMCTR0_AFREADYM_Pos (1UL)          /*!< Position of AFREADYM field.                                          */
20153   #define ETR_ITATBMCTR0_AFREADYM_Msk (0x1UL << ETR_ITATBMCTR0_AFREADYM_Pos) /*!< Bit mask of AFREADYM field.                  */
20154 
20155 /* ATBYTESM @Bits 8..9 : Control the value of ATBYTESM output from TMC. The value written to this field is driven on the
20156                          ATBYTESM output of the TMC. */
20157 
20158   #define ETR_ITATBMCTR0_ATBYTESM_Pos (8UL)          /*!< Position of ATBYTESM field.                                          */
20159   #define ETR_ITATBMCTR0_ATBYTESM_Msk (0x3UL << ETR_ITATBMCTR0_ATBYTESM_Pos) /*!< Bit mask of ATBYTESM field.                  */
20160 
20161 
20162 /* ETR_ITMISCOP0: Integration Test Miscellaneous Output Register 0 */
20163   #define ETR_ITMISCOP0_ResetValue (0x00000000UL)    /*!< Reset value of ITMISCOP0 register.                                   */
20164 
20165 /* ACQCOMP @Bit 0 : Set the value of the ACQCOMP output. */
20166   #define ETR_ITMISCOP0_ACQCOMP_Pos (0UL)            /*!< Position of ACQCOMP field.                                           */
20167   #define ETR_ITMISCOP0_ACQCOMP_Msk (0x1UL << ETR_ITMISCOP0_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field.                       */
20168 
20169 /* FULL @Bit 1 : Set the value of the FULL output. */
20170   #define ETR_ITMISCOP0_FULL_Pos (1UL)               /*!< Position of FULL field.                                              */
20171   #define ETR_ITMISCOP0_FULL_Msk (0x1UL << ETR_ITMISCOP0_FULL_Pos) /*!< Bit mask of FULL field.                                */
20172 
20173 
20174 /* ETR_ITTRFLIN: Integration Test Trigger In and Flush In Register */
20175   #define ETR_ITTRFLIN_ResetValue (0x00000000UL)     /*!< Reset value of ITTRFLIN register.                                    */
20176 
20177 /* TRIGIN @Bit 0 : Read the value of the TRIGIN input. */
20178   #define ETR_ITTRFLIN_TRIGIN_Pos (0UL)              /*!< Position of TRIGIN field.                                            */
20179   #define ETR_ITTRFLIN_TRIGIN_Msk (0x1UL << ETR_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field.                            */
20180 
20181 /* FLUSHIN @Bit 1 : Read the value of the FLUSHIN input. */
20182   #define ETR_ITTRFLIN_FLUSHIN_Pos (1UL)             /*!< Position of FLUSHIN field.                                           */
20183   #define ETR_ITTRFLIN_FLUSHIN_Msk (0x1UL << ETR_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field.                         */
20184 
20185 
20186 /* ETR_ITATBDATA0: Integration Test ATB Data Register 0 */
20187   #define ETR_ITATBDATA0_ResetValue (0x00000000UL)   /*!< Reset value of ITATBDATA0 register.                                  */
20188 
20189 /* ATDATASBIT0 @Bit 0 : Read the value of ATDATAS[0] input to TMC */
20190   #define ETR_ITATBDATA0_ATDATASBIT0_Pos (0UL)       /*!< Position of ATDATASBIT0 field.                                       */
20191   #define ETR_ITATBDATA0_ATDATASBIT0_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT0_Pos) /*!< Bit mask of ATDATASBIT0 field.         */
20192 
20193 /* ATDATASBIT7 @Bit 1 : Read the value of ATDATAS[7] input to TMC */
20194   #define ETR_ITATBDATA0_ATDATASBIT7_Pos (1UL)       /*!< Position of ATDATASBIT7 field.                                       */
20195   #define ETR_ITATBDATA0_ATDATASBIT7_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT7_Pos) /*!< Bit mask of ATDATASBIT7 field.         */
20196 
20197 /* ATDATASBIT15 @Bit 2 : Read the value of ATDATAS[15] input to TMC */
20198   #define ETR_ITATBDATA0_ATDATASBIT15_Pos (2UL)      /*!< Position of ATDATASBIT15 field.                                      */
20199   #define ETR_ITATBDATA0_ATDATASBIT15_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT15_Pos) /*!< Bit mask of ATDATASBIT15 field.      */
20200 
20201 /* ATDATASBIT23 @Bit 3 : Read the value of ATDATAS[23] input to TMC */
20202   #define ETR_ITATBDATA0_ATDATASBIT23_Pos (3UL)      /*!< Position of ATDATASBIT23 field.                                      */
20203   #define ETR_ITATBDATA0_ATDATASBIT23_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT23_Pos) /*!< Bit mask of ATDATASBIT23 field.      */
20204 
20205 /* ATDATASBIT31 @Bit 4 : Read the value of ATDATAS[31] input to TMC */
20206   #define ETR_ITATBDATA0_ATDATASBIT31_Pos (4UL)      /*!< Position of ATDATASBIT31 field.                                      */
20207   #define ETR_ITATBDATA0_ATDATASBIT31_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT31_Pos) /*!< Bit mask of ATDATASBIT31 field.      */
20208 
20209 /* ATDATASBIT39 @Bit 5 : Read the value of ATDATAS[39] input to TMC */
20210   #define ETR_ITATBDATA0_ATDATASBIT39_Pos (5UL)      /*!< Position of ATDATASBIT39 field.                                      */
20211   #define ETR_ITATBDATA0_ATDATASBIT39_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT39_Pos) /*!< Bit mask of ATDATASBIT39 field.      */
20212 
20213 /* ATDATASBIT47 @Bit 6 : Read the value of ATDATAS[47] input to TMC */
20214   #define ETR_ITATBDATA0_ATDATASBIT47_Pos (6UL)      /*!< Position of ATDATASBIT47 field.                                      */
20215   #define ETR_ITATBDATA0_ATDATASBIT47_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT47_Pos) /*!< Bit mask of ATDATASBIT47 field.      */
20216 
20217 /* ATDATASBIT55 @Bit 7 : Read the value of ATDATAS[55] input to TMC */
20218   #define ETR_ITATBDATA0_ATDATASBIT55_Pos (7UL)      /*!< Position of ATDATASBIT55 field.                                      */
20219   #define ETR_ITATBDATA0_ATDATASBIT55_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT55_Pos) /*!< Bit mask of ATDATASBIT55 field.      */
20220 
20221 /* ATDATASBIT63 @Bit 8 : Read the value of ATDATAS[63] input to TMC */
20222   #define ETR_ITATBDATA0_ATDATASBIT63_Pos (8UL)      /*!< Position of ATDATASBIT63 field.                                      */
20223   #define ETR_ITATBDATA0_ATDATASBIT63_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT63_Pos) /*!< Bit mask of ATDATASBIT63 field.      */
20224 
20225 /* ATDATASBIT71 @Bit 9 : Read the value of ATDATAS[71] input to TMC */
20226   #define ETR_ITATBDATA0_ATDATASBIT71_Pos (9UL)      /*!< Position of ATDATASBIT71 field.                                      */
20227   #define ETR_ITATBDATA0_ATDATASBIT71_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT71_Pos) /*!< Bit mask of ATDATASBIT71 field.      */
20228 
20229 /* ATDATASBIT79 @Bit 10 : Read the value of ATDATAS[79] input to TMC */
20230   #define ETR_ITATBDATA0_ATDATASBIT79_Pos (10UL)     /*!< Position of ATDATASBIT79 field.                                      */
20231   #define ETR_ITATBDATA0_ATDATASBIT79_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT79_Pos) /*!< Bit mask of ATDATASBIT79 field.      */
20232 
20233 /* ATDATASBIT87 @Bit 11 : Read the value of ATDATAS[87] input to TMC */
20234   #define ETR_ITATBDATA0_ATDATASBIT87_Pos (11UL)     /*!< Position of ATDATASBIT87 field.                                      */
20235   #define ETR_ITATBDATA0_ATDATASBIT87_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT87_Pos) /*!< Bit mask of ATDATASBIT87 field.      */
20236 
20237 /* ATDATASBIT95 @Bit 12 : Read the value of ATDATAS[95] input to TMC */
20238   #define ETR_ITATBDATA0_ATDATASBIT95_Pos (12UL)     /*!< Position of ATDATASBIT95 field.                                      */
20239   #define ETR_ITATBDATA0_ATDATASBIT95_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT95_Pos) /*!< Bit mask of ATDATASBIT95 field.      */
20240 
20241 /* ATDATASBIT103 @Bit 13 : Read the value of ATDATAS[103] input to TMC */
20242   #define ETR_ITATBDATA0_ATDATASBIT103_Pos (13UL)    /*!< Position of ATDATASBIT103 field.                                     */
20243   #define ETR_ITATBDATA0_ATDATASBIT103_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT103_Pos) /*!< Bit mask of ATDATASBIT103 field.   */
20244 
20245 /* ATDATASBIT111 @Bit 14 : Read the value of ATDATAS[111] input to TMC */
20246   #define ETR_ITATBDATA0_ATDATASBIT111_Pos (14UL)    /*!< Position of ATDATASBIT111 field.                                     */
20247   #define ETR_ITATBDATA0_ATDATASBIT111_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT111_Pos) /*!< Bit mask of ATDATASBIT111 field.   */
20248 
20249 /* ATDATASBIT119 @Bit 15 : Read the value of ATDATAS[119] input to TMC */
20250   #define ETR_ITATBDATA0_ATDATASBIT119_Pos (15UL)    /*!< Position of ATDATASBIT119 field.                                     */
20251   #define ETR_ITATBDATA0_ATDATASBIT119_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT119_Pos) /*!< Bit mask of ATDATASBIT119 field.   */
20252 
20253 /* ATDATASBIT127 @Bit 16 : Read the value of ATDATAS[127] input to TMC */
20254   #define ETR_ITATBDATA0_ATDATASBIT127_Pos (16UL)    /*!< Position of ATDATASBIT127 field.                                     */
20255   #define ETR_ITATBDATA0_ATDATASBIT127_Msk (0x1UL << ETR_ITATBDATA0_ATDATASBIT127_Pos) /*!< Bit mask of ATDATASBIT127 field.   */
20256 
20257 
20258 /* ETR_ITATBCTR2: Integration Test ATB Control 2 Register */
20259   #define ETR_ITATBCTR2_ResetValue (0x00000000UL)    /*!< Reset value of ITATBCTR2 register.                                   */
20260 
20261 /* ATREADYS @Bit 0 : Set the value of ATREADYS output */
20262   #define ETR_ITATBCTR2_ATREADYS_Pos (0UL)           /*!< Position of ATREADYS field.                                          */
20263   #define ETR_ITATBCTR2_ATREADYS_Msk (0x1UL << ETR_ITATBCTR2_ATREADYS_Pos) /*!< Bit mask of ATREADYS field.                    */
20264 
20265 /* AFVALIDS @Bit 1 : Set the value of AFVALIDS output */
20266   #define ETR_ITATBCTR2_AFVALIDS_Pos (1UL)           /*!< Position of AFVALIDS field.                                          */
20267   #define ETR_ITATBCTR2_AFVALIDS_Msk (0x1UL << ETR_ITATBCTR2_AFVALIDS_Pos) /*!< Bit mask of AFVALIDS field.                    */
20268 
20269 /* SYNCREQS @Bit 2 : Set the value of SYNCREQS output */
20270   #define ETR_ITATBCTR2_SYNCREQS_Pos (2UL)           /*!< Position of SYNCREQS field.                                          */
20271   #define ETR_ITATBCTR2_SYNCREQS_Msk (0x1UL << ETR_ITATBCTR2_SYNCREQS_Pos) /*!< Bit mask of SYNCREQS field.                    */
20272 
20273 
20274 /* ETR_ITATBCTR1: Integration Test ATB Control 1 Register */
20275   #define ETR_ITATBCTR1_ResetValue (0x00000000UL)    /*!< Reset value of ITATBCTR1 register.                                   */
20276 
20277 /* ATIDS @Bits 0..6 : Read the value of ATIDS input to TMC */
20278   #define ETR_ITATBCTR1_ATIDS_Pos (0UL)              /*!< Position of ATIDS field.                                             */
20279   #define ETR_ITATBCTR1_ATIDS_Msk (0x7FUL << ETR_ITATBCTR1_ATIDS_Pos) /*!< Bit mask of ATIDS field.                            */
20280 
20281 
20282 /* ETR_ITATBCTR0: Integration Test ATB Control 0 Register */
20283   #define ETR_ITATBCTR0_ResetValue (0x00000000UL)    /*!< Reset value of ITATBCTR0 register.                                   */
20284 
20285 /* ATVALIDS @Bit 0 : Read the value of ATVALIDS input to TMC */
20286   #define ETR_ITATBCTR0_ATVALIDS_Pos (0UL)           /*!< Position of ATVALIDS field.                                          */
20287   #define ETR_ITATBCTR0_ATVALIDS_Msk (0x1UL << ETR_ITATBCTR0_ATVALIDS_Pos) /*!< Bit mask of ATVALIDS field.                    */
20288 
20289 /* AFREADYS @Bit 1 : Read the value of AFREADYS input to TMC */
20290   #define ETR_ITATBCTR0_AFREADYS_Pos (1UL)           /*!< Position of AFREADYS field.                                          */
20291   #define ETR_ITATBCTR0_AFREADYS_Msk (0x1UL << ETR_ITATBCTR0_AFREADYS_Pos) /*!< Bit mask of AFREADYS field.                    */
20292 
20293 /* ATBYTESS @Bits 8..9 : Read the value of ATBYTESS input to TMC */
20294   #define ETR_ITATBCTR0_ATBYTESS_Pos (8UL)           /*!< Position of ATBYTESS field.                                          */
20295   #define ETR_ITATBCTR0_ATBYTESS_Msk (0x3UL << ETR_ITATBCTR0_ATBYTESS_Pos) /*!< Bit mask of ATBYTESS field.                    */
20296 
20297 
20298 /* ETR_ITCTRL: Integration Mode Control Register */
20299   #define ETR_ITCTRL_ResetValue (0x00000000UL)       /*!< Reset value of ITCTRL register.                                      */
20300 
20301 /* INTEGRATION_MODE @Bit 0 : Allows the component to switch from functional mode to integration mode or back. */
20302   #define ETR_ITCTRL_INTEGRATION_MODE_Pos (0UL)      /*!< Position of INTEGRATION_MODE field.                                  */
20303   #define ETR_ITCTRL_INTEGRATION_MODE_Msk (0x1UL << ETR_ITCTRL_INTEGRATION_MODE_Pos) /*!< Bit mask of INTEGRATION_MODE field.  */
20304 
20305 
20306 /* ETR_CLAIMSET: Claim Tag Set Register */
20307   #define ETR_CLAIMSET_ResetValue (0x0000000FUL)     /*!< Reset value of CLAIMSET register.                                    */
20308 
20309 /* CLAIMSET @Bits 0..3 : This claim tag bit is implemented */
20310   #define ETR_CLAIMSET_CLAIMSET_Pos (0UL)            /*!< Position of CLAIMSET field.                                          */
20311   #define ETR_CLAIMSET_CLAIMSET_Msk (0xFUL << ETR_CLAIMSET_CLAIMSET_Pos) /*!< Bit mask of CLAIMSET field.                      */
20312 
20313 
20314 /* ETR_CLAIMCLR: Claim Tag Clear Register */
20315   #define ETR_CLAIMCLR_ResetValue (0x00000000UL)     /*!< Reset value of CLAIMCLR register.                                    */
20316 
20317 /* CLAIMCLR @Bits 0..3 : The value present reflects the current setting of the Claim Tag. */
20318   #define ETR_CLAIMCLR_CLAIMCLR_Pos (0UL)            /*!< Position of CLAIMCLR field.                                          */
20319   #define ETR_CLAIMCLR_CLAIMCLR_Msk (0xFUL << ETR_CLAIMCLR_CLAIMCLR_Pos) /*!< Bit mask of CLAIMCLR field.                      */
20320 
20321 
20322 /* ETR_LAR: Lock Access Register */
20323   #define ETR_LAR_ResetValue (0x00000000UL)          /*!< Reset value of LAR register.                                         */
20324 
20325 /* ACCESS_W @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than
20326                           0xC5ACCE55 will have the affect of removing write access. */
20327 
20328   #define ETR_LAR_ACCESS_W_Pos (0UL)                 /*!< Position of ACCESS_W field.                                          */
20329   #define ETR_LAR_ACCESS_W_Msk (0xFFFFFFFFUL << ETR_LAR_ACCESS_W_Pos) /*!< Bit mask of ACCESS_W field.                         */
20330 
20331 
20332 /* ETR_LSR: Lock Status Register */
20333   #define ETR_LSR_ResetValue (0x00000003UL)          /*!< Reset value of LSR register.                                         */
20334 
20335 /* LOCKEXIST @Bit 0 : Indicates that a lock control mechanism exists for this device. */
20336   #define ETR_LSR_LOCKEXIST_Pos (0UL)                /*!< Position of LOCKEXIST field.                                         */
20337   #define ETR_LSR_LOCKEXIST_Msk (0x1UL << ETR_LSR_LOCKEXIST_Pos) /*!< Bit mask of LOCKEXIST field.                             */
20338 
20339 /* LOCKGRANT @Bit 1 : Returns the current status of the Lock. */
20340   #define ETR_LSR_LOCKGRANT_Pos (1UL)                /*!< Position of LOCKGRANT field.                                         */
20341   #define ETR_LSR_LOCKGRANT_Msk (0x1UL << ETR_LSR_LOCKGRANT_Pos) /*!< Bit mask of LOCKGRANT field.                             */
20342 
20343 /* LOCKTYPE @Bit 2 : Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit */
20344   #define ETR_LSR_LOCKTYPE_Pos (2UL)                 /*!< Position of LOCKTYPE field.                                          */
20345   #define ETR_LSR_LOCKTYPE_Msk (0x1UL << ETR_LSR_LOCKTYPE_Pos) /*!< Bit mask of LOCKTYPE field.                                */
20346   #define ETR_LSR_LOCKTYPE_Min (0x0UL)               /*!< Min enumerator value of LOCKTYPE field.                              */
20347   #define ETR_LSR_LOCKTYPE_Max (0x0UL)               /*!< Max enumerator value of LOCKTYPE field.                              */
20348   #define ETR_LSR_LOCKTYPE_32BIT (0x0UL)             /*!< This component implements a 32-bit Lock Access Register              */
20349 
20350 
20351 /* ETR_AUTHSTATUS: Authentication Status Register */
20352   #define ETR_AUTHSTATUS_ResetValue (0x00000000UL)   /*!< Reset value of AUTHSTATUS register.                                  */
20353 
20354 /* NSID @Bits 0..1 : Indicates the security level for non-secure invasive debug */
20355   #define ETR_AUTHSTATUS_NSID_Pos (0UL)              /*!< Position of NSID field.                                              */
20356   #define ETR_AUTHSTATUS_NSID_Msk (0x3UL << ETR_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field.                              */
20357   #define ETR_AUTHSTATUS_NSID_Min (0x2UL)            /*!< Min enumerator value of NSID field.                                  */
20358   #define ETR_AUTHSTATUS_NSID_Max (0x3UL)            /*!< Max enumerator value of NSID field.                                  */
20359   #define ETR_AUTHSTATUS_NSID_DISABLED (0x2UL)       /*!< Functionality disabled. This return value occurs when DBGEN is LOW.  */
20360   #define ETR_AUTHSTATUS_NSID_ENABLED (0x3UL)        /*!< Functionality enabled. This return value occurs when DBGEN is HIGH.  */
20361 
20362 /* NSNID @Bits 2..3 : Indicates the security level for non-secure non-invasive debug */
20363   #define ETR_AUTHSTATUS_NSNID_Pos (2UL)             /*!< Position of NSNID field.                                             */
20364   #define ETR_AUTHSTATUS_NSNID_Msk (0x3UL << ETR_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field.                           */
20365   #define ETR_AUTHSTATUS_NSNID_Min (0x0UL)           /*!< Min enumerator value of NSNID field.                                 */
20366   #define ETR_AUTHSTATUS_NSNID_Max (0x0UL)           /*!< Max enumerator value of NSNID field.                                 */
20367   #define ETR_AUTHSTATUS_NSNID_NONE (0x0UL)          /*!< Functionality not implemented or controlled elsewhere.               */
20368 
20369 /* SID @Bits 4..5 : Indicates the security level for secure invasive debug */
20370   #define ETR_AUTHSTATUS_SID_Pos (4UL)               /*!< Position of SID field.                                               */
20371   #define ETR_AUTHSTATUS_SID_Msk (0x3UL << ETR_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field.                                 */
20372   #define ETR_AUTHSTATUS_SID_Min (0x2UL)             /*!< Min enumerator value of SID field.                                   */
20373   #define ETR_AUTHSTATUS_SID_Max (0x3UL)             /*!< Max enumerator value of SID field.                                   */
20374   #define ETR_AUTHSTATUS_SID_DISABLED (0x2UL)        /*!< Functionality disabled. This return value occurs when DBGEN is LOW or
20375                                                           SPIDEN is LOW.*/
20376   #define ETR_AUTHSTATUS_SID_ENABLED (0x3UL)         /*!< Functionality enabled. This return value occurs when DBGEN and SPIDEN
20377                                                           are HIGH.*/
20378 
20379 /* SNID @Bits 6..7 : Indicates the security level for secure non-invasive debug */
20380   #define ETR_AUTHSTATUS_SNID_Pos (6UL)              /*!< Position of SNID field.                                              */
20381   #define ETR_AUTHSTATUS_SNID_Msk (0x3UL << ETR_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field.                              */
20382   #define ETR_AUTHSTATUS_SNID_Min (0x0UL)            /*!< Min enumerator value of SNID field.                                  */
20383   #define ETR_AUTHSTATUS_SNID_Max (0x0UL)            /*!< Max enumerator value of SNID field.                                  */
20384   #define ETR_AUTHSTATUS_SNID_NONE (0x0UL)           /*!< Functionality not implemented or controlled elsewhere.               */
20385 
20386 
20387 /* ETR_DEVID: Device Configuration Register */
20388   #define ETR_DEVID_ResetValue (0x00000300UL)        /*!< Reset value of DEVID register.                                       */
20389 
20390 /* ATBINPORTCOUNT @Bits 0..4 : This value indicates the type/number of ATB multiplexing present on the input ATB. */
20391   #define ETR_DEVID_ATBINPORTCOUNT_Pos (0UL)         /*!< Position of ATBINPORTCOUNT field.                                    */
20392   #define ETR_DEVID_ATBINPORTCOUNT_Msk (0x1FUL << ETR_DEVID_ATBINPORTCOUNT_Pos) /*!< Bit mask of ATBINPORTCOUNT field.         */
20393 
20394 /* CLKSCHEME @Bit 5 : This value indicates the TMC RAM clocking scheme used, ie. whether the TMC RAM operates synchronously or
20395                       asynchronously to CLK. */
20396 
20397   #define ETR_DEVID_CLKSCHEME_Pos (5UL)              /*!< Position of CLKSCHEME field.                                         */
20398   #define ETR_DEVID_CLKSCHEME_Msk (0x1UL << ETR_DEVID_CLKSCHEME_Pos) /*!< Bit mask of CLKSCHEME field.                         */
20399   #define ETR_DEVID_CLKSCHEME_Min (0x0UL)            /*!< Min enumerator value of CLKSCHEME field.                             */
20400   #define ETR_DEVID_CLKSCHEME_Max (0x0UL)            /*!< Max enumerator value of CLKSCHEME field.                             */
20401   #define ETR_DEVID_CLKSCHEME_SYNC (0x0UL)           /*!< The TMC RAM operates synchronously to CLK.                           */
20402 
20403 /* CONFIGTYPE @Bits 6..7 : This value indicates TMC configuration type. */
20404   #define ETR_DEVID_CONFIGTYPE_Pos (6UL)             /*!< Position of CONFIGTYPE field.                                        */
20405   #define ETR_DEVID_CONFIGTYPE_Msk (0x3UL << ETR_DEVID_CONFIGTYPE_Pos) /*!< Bit mask of CONFIGTYPE field.                      */
20406   #define ETR_DEVID_CONFIGTYPE_Min (0x0UL)           /*!< Min enumerator value of CONFIGTYPE field.                            */
20407   #define ETR_DEVID_CONFIGTYPE_Max (0x2UL)           /*!< Max enumerator value of CONFIGTYPE field.                            */
20408   #define ETR_DEVID_CONFIGTYPE_ETB (0x0UL)           /*!< (unspecified)                                                        */
20409   #define ETR_DEVID_CONFIGTYPE_ETR (0x1UL)           /*!< (unspecified)                                                        */
20410   #define ETR_DEVID_CONFIGTYPE_ETF (0x2UL)           /*!< (unspecified)                                                        */
20411 
20412 /* MEMWIDTH @Bits 8..10 : This value indicates the width of the Memory interface databus. */
20413   #define ETR_DEVID_MEMWIDTH_Pos (8UL)               /*!< Position of MEMWIDTH field.                                          */
20414   #define ETR_DEVID_MEMWIDTH_Msk (0x7UL << ETR_DEVID_MEMWIDTH_Pos) /*!< Bit mask of MEMWIDTH field.                            */
20415   #define ETR_DEVID_MEMWIDTH_Min (0x2UL)             /*!< Min enumerator value of MEMWIDTH field.                              */
20416   #define ETR_DEVID_MEMWIDTH_Max (0x5UL)             /*!< Max enumerator value of MEMWIDTH field.                              */
20417   #define ETR_DEVID_MEMWIDTH_32BIT (0x2UL)           /*!< Memory interface databus is 32 bits wide.                            */
20418   #define ETR_DEVID_MEMWIDTH_64BIT (0x3UL)           /*!< Memory interface databus is 64 bits wide.                            */
20419   #define ETR_DEVID_MEMWIDTH_128BIT (0x4UL)          /*!< Memory interface databus is 128 bits wide.                           */
20420   #define ETR_DEVID_MEMWIDTH_256BIT (0x5UL)          /*!< Memory interface databus is 256 bits wide.                           */
20421 
20422 /* WBUF_DEPTH @Bits 11..13 : This value indicates, in powers of two, the number of entries in the Write buffer. Each entry is of
20423                              size ATB_DATA_WIDTH. */
20424 
20425   #define ETR_DEVID_WBUF_DEPTH_Pos (11UL)            /*!< Position of WBUF_DEPTH field.                                        */
20426   #define ETR_DEVID_WBUF_DEPTH_Msk (0x7UL << ETR_DEVID_WBUF_DEPTH_Pos) /*!< Bit mask of WBUF_DEPTH field.                      */
20427   #define ETR_DEVID_WBUF_DEPTH_Min (0x2UL)           /*!< Min enumerator value of WBUF_DEPTH field.                            */
20428   #define ETR_DEVID_WBUF_DEPTH_Max (0x5UL)           /*!< Max enumerator value of WBUF_DEPTH field.                            */
20429   #define ETR_DEVID_WBUF_DEPTH_4ENTRIES (0x2UL)      /*!< Depth of the Write buffer is 4 entries.                              */
20430   #define ETR_DEVID_WBUF_DEPTH_8ENTRIES (0x3UL)      /*!< Depth of the Write buffer is 8 entries.                              */
20431   #define ETR_DEVID_WBUF_DEPTH_16ENTRIES (0x4UL)     /*!< Depth of the Write buffer is 16 entries.                             */
20432   #define ETR_DEVID_WBUF_DEPTH_32ENTRIES (0x5UL)     /*!< Depth of the Write buffer is 32 entries.                             */
20433 
20434 
20435 /* ETR_DEVTYPE: Device Type Identifier Register */
20436   #define ETR_DEVTYPE_ResetValue (0x00000021UL)      /*!< Reset value of DEVTYPE register.                                     */
20437 
20438 /* MAJOR_TYPE @Bits 0..3 : Major classification grouping for this debug/trace component */
20439   #define ETR_DEVTYPE_MAJOR_TYPE_Pos (0UL)           /*!< Position of MAJOR_TYPE field.                                        */
20440   #define ETR_DEVTYPE_MAJOR_TYPE_Msk (0xFUL << ETR_DEVTYPE_MAJOR_TYPE_Pos) /*!< Bit mask of MAJOR_TYPE field.                  */
20441   #define ETR_DEVTYPE_MAJOR_TYPE_Min (0x1UL)         /*!< Min enumerator value of MAJOR_TYPE field.                            */
20442   #define ETR_DEVTYPE_MAJOR_TYPE_Max (0x1UL)         /*!< Max enumerator value of MAJOR_TYPE field.                            */
20443   #define ETR_DEVTYPE_MAJOR_TYPE_SINK (0x1UL)        /*!< This component is a trace sink.                                      */
20444 
20445 /* SUB_TYPE @Bits 4..7 : Sub-classification within the major category */
20446   #define ETR_DEVTYPE_SUB_TYPE_Pos (4UL)             /*!< Position of SUB_TYPE field.                                          */
20447   #define ETR_DEVTYPE_SUB_TYPE_Msk (0xFUL << ETR_DEVTYPE_SUB_TYPE_Pos) /*!< Bit mask of SUB_TYPE field.                        */
20448   #define ETR_DEVTYPE_SUB_TYPE_Min (0x2UL)           /*!< Min enumerator value of SUB_TYPE field.                              */
20449   #define ETR_DEVTYPE_SUB_TYPE_Max (0x2UL)           /*!< Max enumerator value of SUB_TYPE field.                              */
20450   #define ETR_DEVTYPE_SUB_TYPE (0x2UL)               /*!< This component captures the trace data into RAM that can be drained
20451                                                           through APB.*/
20452 
20453 
20454 /* ETR_PERIPHID4: Peripheral ID4 Register */
20455   #define ETR_PERIPHID4_ResetValue (0x00000004UL)    /*!< Reset value of PERIPHID4 register.                                   */
20456 
20457 /* JEP106_CONT @Bits 0..3 : JEDEC continuation code indicating the designer of the component (along with the identity code) */
20458   #define ETR_PERIPHID4_JEP106_CONT_Pos (0UL)        /*!< Position of JEP106_CONT field.                                       */
20459   #define ETR_PERIPHID4_JEP106_CONT_Msk (0xFUL << ETR_PERIPHID4_JEP106_CONT_Pos) /*!< Bit mask of JEP106_CONT field.           */
20460 
20461 /* FOURKB_COUNT @Bits 4..7 : This is a 4-bit value that indicates the total contiguous size of the memory window used by this
20462                              component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then
20463                              this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. */
20464 
20465   #define ETR_PERIPHID4_FOURKB_COUNT_Pos (4UL)       /*!< Position of FOURKB_COUNT field.                                      */
20466   #define ETR_PERIPHID4_FOURKB_COUNT_Msk (0xFUL << ETR_PERIPHID4_FOURKB_COUNT_Pos) /*!< Bit mask of FOURKB_COUNT field.        */
20467 
20468 
20469 /* ETR_PERIPHID0: Peripheral ID0 Register */
20470   #define ETR_PERIPHID0_ResetValue (0x00000061UL)    /*!< Reset value of PERIPHID0 register.                                   */
20471 
20472 /* PART_NUMBER_BITS7TO0 @Bits 0..7 : Bits [7:0] of the component's part number. This is selected by the designer of the
20473                                      component. */
20474 
20475   #define ETR_PERIPHID0_PART_NUMBER_BITS7TO0_Pos (0UL) /*!< Position of PART_NUMBER_BITS7TO0 field.                            */
20476   #define ETR_PERIPHID0_PART_NUMBER_BITS7TO0_Msk (0xFFUL << ETR_PERIPHID0_PART_NUMBER_BITS7TO0_Pos) /*!< Bit mask of
20477                                                                             PART_NUMBER_BITS7TO0 field.*/
20478 
20479 
20480 /* ETR_PERIPHID1: Peripheral ID1 Register */
20481   #define ETR_PERIPHID1_ResetValue (0x000000B9UL)    /*!< Reset value of PERIPHID1 register.                                   */
20482 
20483 /* PART_NUMBER_BITS11TO8 @Bits 0..3 : Bits [11:8] of the component's part number. This is selected by the designer of the
20484                                       component. */
20485 
20486   #define ETR_PERIPHID1_PART_NUMBER_BITS11TO8_Pos (0UL) /*!< Position of PART_NUMBER_BITS11TO8 field.                          */
20487   #define ETR_PERIPHID1_PART_NUMBER_BITS11TO8_Msk (0xFUL << ETR_PERIPHID1_PART_NUMBER_BITS11TO8_Pos) /*!< Bit mask of
20488                                                                             PART_NUMBER_BITS11TO8 field.*/
20489 
20490 /* JEP106_BITS3TO0 @Bits 4..7 : Bits 3:0 of the JEDEC identity code indicating the designer of the component (along with the
20491                                 continuation code) */
20492 
20493   #define ETR_PERIPHID1_JEP106_BITS3TO0_Pos (4UL)    /*!< Position of JEP106_BITS3TO0 field.                                   */
20494   #define ETR_PERIPHID1_JEP106_BITS3TO0_Msk (0xFUL << ETR_PERIPHID1_JEP106_BITS3TO0_Pos) /*!< Bit mask of JEP106_BITS3TO0
20495                                                                             field.*/
20496 
20497 
20498 /* ETR_PERIPHID2: Peripheral ID2 Register */
20499   #define ETR_PERIPHID2_ResetValue (0x0000001BUL)    /*!< Reset value of PERIPHID2 register.                                   */
20500 
20501 /* JEP106_BITS6TO4 @Bits 0..2 : Bits 6:4 of the JEDEC identity code indicating the designer of the component (along with the
20502                                 continuation code) */
20503 
20504   #define ETR_PERIPHID2_JEP106_BITS6TO4_Pos (0UL)    /*!< Position of JEP106_BITS6TO4 field.                                   */
20505   #define ETR_PERIPHID2_JEP106_BITS6TO4_Msk (0x7UL << ETR_PERIPHID2_JEP106_BITS6TO4_Pos) /*!< Bit mask of JEP106_BITS6TO4
20506                                                                             field.*/
20507 
20508 /* JEDEC @Bit 3 : Always set. Indicates that a JEDEC assigned value is used */
20509   #define ETR_PERIPHID2_JEDEC_Pos (3UL)              /*!< Position of JEDEC field.                                             */
20510   #define ETR_PERIPHID2_JEDEC_Msk (0x1UL << ETR_PERIPHID2_JEDEC_Pos) /*!< Bit mask of JEDEC field.                             */
20511 
20512 /* REVISION @Bits 4..7 : The Revision field is an incremental value starting at 0x0 for the first design of this component. This
20513                          only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the
20514                          exact major/minor revision. */
20515 
20516   #define ETR_PERIPHID2_REVISION_Pos (4UL)           /*!< Position of REVISION field.                                          */
20517   #define ETR_PERIPHID2_REVISION_Msk (0xFUL << ETR_PERIPHID2_REVISION_Pos) /*!< Bit mask of REVISION field.                    */
20518 
20519 
20520 /* ETR_PERIPHID3: Peripheral ID3 Register */
20521   #define ETR_PERIPHID3_ResetValue (0x00000000UL)    /*!< Reset value of PERIPHID3 register.                                   */
20522 
20523 /* CUSTOMER_MODIFIED @Bits 0..3 : Where the component is reusable IP, this value indicates if the customer has modified the
20524                                   behavior of the component. In most cases this field is zero. */
20525 
20526   #define ETR_PERIPHID3_CUSTOMER_MODIFIED_Pos (0UL)  /*!< Position of CUSTOMER_MODIFIED field.                                 */
20527   #define ETR_PERIPHID3_CUSTOMER_MODIFIED_Msk (0xFUL << ETR_PERIPHID3_CUSTOMER_MODIFIED_Pos) /*!< Bit mask of CUSTOMER_MODIFIED
20528                                                                             field.*/
20529 
20530 /* REVAND @Bits 4..7 : This field indicates minor errata fixes specific to this design, for example metal fixes after
20531                        implementation. In most cases this field is zero. It is recommended that component designers ensure this
20532                        field can be changed by a metal fix if required, for example by driving it from registers that reset to
20533                        zero. */
20534 
20535   #define ETR_PERIPHID3_REVAND_Pos (4UL)             /*!< Position of REVAND field.                                            */
20536   #define ETR_PERIPHID3_REVAND_Msk (0xFUL << ETR_PERIPHID3_REVAND_Pos) /*!< Bit mask of REVAND field.                          */
20537 
20538 
20539 /* ETR_COMPID0: Component ID0 Register */
20540   #define ETR_COMPID0_ResetValue (0x0000000DUL)      /*!< Reset value of COMPID0 register.                                     */
20541 
20542 /* PREAMBLE @Bits 0..7 : Contains bits [7:0] of the component identification */
20543   #define ETR_COMPID0_PREAMBLE_Pos (0UL)             /*!< Position of PREAMBLE field.                                          */
20544   #define ETR_COMPID0_PREAMBLE_Msk (0xFFUL << ETR_COMPID0_PREAMBLE_Pos) /*!< Bit mask of PREAMBLE field.                       */
20545 
20546 
20547 /* ETR_COMPID1: Component ID1 Register */
20548   #define ETR_COMPID1_ResetValue (0x00000090UL)      /*!< Reset value of COMPID1 register.                                     */
20549 
20550 /* PREAMBLE @Bits 0..3 : Contains bits [11:8] of the component identification */
20551   #define ETR_COMPID1_PREAMBLE_Pos (0UL)             /*!< Position of PREAMBLE field.                                          */
20552   #define ETR_COMPID1_PREAMBLE_Msk (0xFUL << ETR_COMPID1_PREAMBLE_Pos) /*!< Bit mask of PREAMBLE field.                        */
20553 
20554 /* CLASS @Bits 4..7 : Class of the component. E.g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the component
20555                       identification. */
20556 
20557   #define ETR_COMPID1_CLASS_Pos (4UL)                /*!< Position of CLASS field.                                             */
20558   #define ETR_COMPID1_CLASS_Msk (0xFUL << ETR_COMPID1_CLASS_Pos) /*!< Bit mask of CLASS field.                                 */
20559 
20560 
20561 /* ETR_COMPID2: Component ID2 Register */
20562   #define ETR_COMPID2_ResetValue (0x00000005UL)      /*!< Reset value of COMPID2 register.                                     */
20563 
20564 /* PREAMBLE @Bits 0..7 : Contains bits [23:16] of the component identification */
20565   #define ETR_COMPID2_PREAMBLE_Pos (0UL)             /*!< Position of PREAMBLE field.                                          */
20566   #define ETR_COMPID2_PREAMBLE_Msk (0xFFUL << ETR_COMPID2_PREAMBLE_Pos) /*!< Bit mask of PREAMBLE field.                       */
20567 
20568 
20569 /* ETR_COMPID3: Component ID3 Register */
20570   #define ETR_COMPID3_ResetValue (0x000000B1UL)      /*!< Reset value of COMPID3 register.                                     */
20571 
20572 /* PREAMBLE @Bits 0..7 : Contains bits [31:24] of the component identification */
20573   #define ETR_COMPID3_PREAMBLE_Pos (0UL)             /*!< Position of PREAMBLE field.                                          */
20574   #define ETR_COMPID3_PREAMBLE_Msk (0xFFUL << ETR_COMPID3_PREAMBLE_Pos) /*!< Bit mask of PREAMBLE field.                       */
20575 
20576 
20577 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
20578 
20579 /* =========================================================================================================================== */
20580 /* ================                                           EXMIF                                           ================ */
20581 /* =========================================================================================================================== */
20582 
20583 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
20584 
20585 /* ================================================== Struct EXMIF_EXTCONF1 ================================================== */
20586 /**
20587   * @brief EXTCONF1 [EXMIF_EXTCONF1] Configuration for external memory device 1.
20588   */
20589 typedef struct {
20590   __IOM uint32_t  OFFSET;                            /*!< (@ 0x00000000) Address offset for external memory device 1.          */
20591   __IOM uint32_t  SIZE;                              /*!< (@ 0x00000004) Upper address range for external memory device 1.     */
20592   __IM  uint32_t  RESERVED[2];
20593   __IOM uint32_t  ENABLE;                            /*!< (@ 0x00000010) Enable or disable external memory access.             */
20594 } NRF_EXMIF_EXTCONF1_Type;                           /*!< Size = 20 (0x014)                                                    */
20595 
20596 /* EXMIF_EXTCONF1_OFFSET: Address offset for external memory device 1. */
20597   #define EXMIF_EXTCONF1_OFFSET_ResetValue (0x00000000UL) /*!< Reset value of OFFSET register.                                 */
20598 
20599 /* OFFSET @Bits 0..31 : External memory Offset. */
20600   #define EXMIF_EXTCONF1_OFFSET_OFFSET_Pos (0UL)     /*!< Position of OFFSET field.                                            */
20601   #define EXMIF_EXTCONF1_OFFSET_OFFSET_Msk (0xFFFFFFFFUL << EXMIF_EXTCONF1_OFFSET_OFFSET_Pos) /*!< Bit mask of OFFSET field.   */
20602   #define EXMIF_EXTCONF1_OFFSET_OFFSET_Min (0x0UL)   /*!< Min value of OFFSET field.                                           */
20603   #define EXMIF_EXTCONF1_OFFSET_OFFSET_Max (0xFFFFFFFFUL) /*!< Max size of OFFSET field.                                       */
20604 
20605 
20606 /* EXMIF_EXTCONF1_SIZE: Upper address range for external memory device 1. */
20607   #define EXMIF_EXTCONF1_SIZE_ResetValue (0x0FFFFFFFUL) /*!< Reset value of SIZE register.                                     */
20608 
20609 /* SIZE @Bits 0..31 : Upper limit address. */
20610   #define EXMIF_EXTCONF1_SIZE_SIZE_Pos (0UL)         /*!< Position of SIZE field.                                              */
20611   #define EXMIF_EXTCONF1_SIZE_SIZE_Msk (0xFFFFFFFFUL << EXMIF_EXTCONF1_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field.             */
20612   #define EXMIF_EXTCONF1_SIZE_SIZE_Min (0x0UL)       /*!< Min value of SIZE field.                                             */
20613   #define EXMIF_EXTCONF1_SIZE_SIZE_Max (0xFFFFFFFFUL) /*!< Max size of SIZE field.                                             */
20614 
20615 
20616 /* EXMIF_EXTCONF1_ENABLE: Enable or disable external memory access. */
20617   #define EXMIF_EXTCONF1_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register.                                 */
20618 
20619 /* ENABLE @Bit 0 : Enable or disable external memory access from AXI interface. */
20620   #define EXMIF_EXTCONF1_ENABLE_ENABLE_Pos (0UL)     /*!< Position of ENABLE field.                                            */
20621   #define EXMIF_EXTCONF1_ENABLE_ENABLE_Msk (0x1UL << EXMIF_EXTCONF1_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.          */
20622   #define EXMIF_EXTCONF1_ENABLE_ENABLE_Min (0x0UL)   /*!< Min enumerator value of ENABLE field.                                */
20623   #define EXMIF_EXTCONF1_ENABLE_ENABLE_Max (0x1UL)   /*!< Max enumerator value of ENABLE field.                                */
20624   #define EXMIF_EXTCONF1_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable external memory.                                          */
20625   #define EXMIF_EXTCONF1_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable external memory.                                            */
20626 
20627 
20628 
20629 /* ================================================== Struct EXMIF_EXTCONF2 ================================================== */
20630 /**
20631   * @brief EXTCONF2 [EXMIF_EXTCONF2] Configuration for external memory device 2.
20632   */
20633 typedef struct {
20634   __IOM uint32_t  OFFSET;                            /*!< (@ 0x00000000) Address offset for external memory device 2.          */
20635   __IOM uint32_t  SIZE;                              /*!< (@ 0x00000004) Upper address range for external memory device 2.     */
20636   __IM  uint32_t  RESERVED[4];
20637   __IOM uint32_t  ENABLE;                            /*!< (@ 0x00000018) Enable or disable external memory access.             */
20638 } NRF_EXMIF_EXTCONF2_Type;                           /*!< Size = 28 (0x01C)                                                    */
20639 
20640 /* EXMIF_EXTCONF2_OFFSET: Address offset for external memory device 2. */
20641   #define EXMIF_EXTCONF2_OFFSET_ResetValue (0x00000000UL) /*!< Reset value of OFFSET register.                                 */
20642 
20643 /* OFFSET @Bits 0..31 : External memory Offset. */
20644   #define EXMIF_EXTCONF2_OFFSET_OFFSET_Pos (0UL)     /*!< Position of OFFSET field.                                            */
20645   #define EXMIF_EXTCONF2_OFFSET_OFFSET_Msk (0xFFFFFFFFUL << EXMIF_EXTCONF2_OFFSET_OFFSET_Pos) /*!< Bit mask of OFFSET field.   */
20646   #define EXMIF_EXTCONF2_OFFSET_OFFSET_Min (0x0UL)   /*!< Min value of OFFSET field.                                           */
20647   #define EXMIF_EXTCONF2_OFFSET_OFFSET_Max (0xFFFFFFFFUL) /*!< Max size of OFFSET field.                                       */
20648 
20649 
20650 /* EXMIF_EXTCONF2_SIZE: Upper address range for external memory device 2. */
20651   #define EXMIF_EXTCONF2_SIZE_ResetValue (0x0FFFFFFFUL) /*!< Reset value of SIZE register.                                     */
20652 
20653 /* SIZE @Bits 0..31 : Upper limit address. */
20654   #define EXMIF_EXTCONF2_SIZE_SIZE_Pos (0UL)         /*!< Position of SIZE field.                                              */
20655   #define EXMIF_EXTCONF2_SIZE_SIZE_Msk (0xFFFFFFFFUL << EXMIF_EXTCONF2_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field.             */
20656   #define EXMIF_EXTCONF2_SIZE_SIZE_Min (0x0UL)       /*!< Min value of SIZE field.                                             */
20657   #define EXMIF_EXTCONF2_SIZE_SIZE_Max (0xFFFFFFFFUL) /*!< Max size of SIZE field.                                             */
20658 
20659 
20660 /* EXMIF_EXTCONF2_ENABLE: Enable or disable external memory access. */
20661   #define EXMIF_EXTCONF2_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register.                                 */
20662 
20663 /* ENABLE @Bit 0 : Enable or disable external memory access from AXI interface. */
20664   #define EXMIF_EXTCONF2_ENABLE_ENABLE_Pos (0UL)     /*!< Position of ENABLE field.                                            */
20665   #define EXMIF_EXTCONF2_ENABLE_ENABLE_Msk (0x1UL << EXMIF_EXTCONF2_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.          */
20666   #define EXMIF_EXTCONF2_ENABLE_ENABLE_Min (0x0UL)   /*!< Min enumerator value of ENABLE field.                                */
20667   #define EXMIF_EXTCONF2_ENABLE_ENABLE_Max (0x1UL)   /*!< Max enumerator value of ENABLE field.                                */
20668   #define EXMIF_EXTCONF2_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable external memory.                                          */
20669   #define EXMIF_EXTCONF2_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable external memory.                                            */
20670 
20671 
20672 
20673 /* ============================================== Struct EXMIF_CORE_SSICADDRESS ============================================== */
20674 /**
20675   * @brief SSICADDRESS [EXMIF_CORE_SSICADDRESS] (unspecified)
20676   */
20677 typedef struct {
20678   __IOM uint32_t  CTRLR0;                            /*!< (@ 0x00000000) This register controls the serial data transfer.      */
20679   __IOM uint32_t  CTRLR1;                            /*!< (@ 0x00000004) This register exists only when the DWC_ssi is
20680                                                                          configured as a master device.*/
20681   __IOM uint32_t  SSIENR;                            /*!< (@ 0x00000008) This register enables and disables the DWC_ssi.       */
20682   __IOM uint32_t  MWCR;                              /*!< (@ 0x0000000C) This register controls the direction of the data word
20683                                                                          for the half-duplex Microwire serial protocol.*/
20684   __IOM uint32_t  SER;                               /*!< (@ 0x00000010) This register is valid only when the DWC_ssi is
20685                                                                          configured as a master device.*/
20686   __IOM uint32_t  BAUDR;                             /*!< (@ 0x00000014) This register is valid only when the DWC_ssi is
20687                                                                          configured as a master device.*/
20688   __IOM uint32_t  TXFTLR;                            /*!< (@ 0x00000018) This register controls the threshold value for the
20689                                                                          transmit FIFO memory..*/
20690   __IOM uint32_t  RXFTLR;                            /*!< (@ 0x0000001C) This register controls the threshold value for the
20691                                                                          receive FIFO memory..*/
20692   __IOM uint32_t  TXFLR;                             /*!< (@ 0x00000020) This register contains the number of valid data entries
20693                                                                          in the transmit FIFO memory.*/
20694   __IOM uint32_t  RXFLR;                             /*!< (@ 0x00000024) This register contains the number of valid data entries
20695                                                                          in the receive FIFO memory.*/
20696   __IOM uint32_t  SR;                                /*!< (@ 0x00000028) This is a read-only register used to indicate the
20697                                                                          current transfer status, FIFO status, and any
20698                                                                          transmission/reception errors that may have occurred.*/
20699   __IOM uint32_t  IMR;                               /*!< (@ 0x0000002C) This read/write register masks or enables all
20700                                                                          interrupts generated by the DWC_ssi.*/
20701   __IOM uint32_t  ISR;                               /*!< (@ 0x00000030) This register reports the status of the DWC_ssi
20702                                                                          interrupts after they have been masked.*/
20703   __IOM uint32_t  RISR;                              /*!< (@ 0x00000034) Raw Interrupt Status Register                         */
20704   __IOM uint32_t  TXEICR;                            /*!< (@ 0x00000038) Transmit FIFO Error Interrupt Clear Register          */
20705   __IOM uint32_t  RXOICR;                            /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register        */
20706   __IOM uint32_t  RXUICR;                            /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt Clear Register       */
20707   __IOM uint32_t  MSTICR;                            /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register                 */
20708   __IOM uint32_t  ICR;                               /*!< (@ 0x00000048) Interrupt Clear Register                              */
20709   __IM  uint32_t  RESERVED[3];
20710   __IOM uint32_t  IDR;                               /*!< (@ 0x00000058) This register contains the peripherals identification
20711                                                                          code, which is written into the register at
20712                                                                          configuration time using coreConsultant.*/
20713   __IOM uint32_t  SSICVERSIONID;                     /*!< (@ 0x0000005C) This read-only register stores the specific DWC_ssi
20714                                                                          component version.*/
20715   __IOM uint32_t  DR[36];                            /*!< (@ 0x00000060) The DWC_ssi data register is a 32-bit read/write buffer
20716                                                                          for the transmit/receive FIFOs.*/
20717   __IOM uint32_t  RXSAMPLEDELAY;                     /*!< (@ 0x000000F0) This register is only valid when the DWC_ssi is
20718                                                                          configured with rxd sample delay logic
20719                                                                          (SSIC_HAS_RX_SAMPLE_DELAY==1).*/
20720   __IOM uint32_t  SPICTRLR0;                         /*!< (@ 0x000000F4) This register is used to control the serial data
20721                                                                          transfer in enhanced SPI mode of operation.*/
20722   __IOM uint32_t  DDRDRIVEEDGE;                      /*!< (@ 0x000000F8) This Register is valid only when SSIC_HAS_DDR is equal
20723                                                                          to 1.*/
20724   __IOM uint32_t  XIPMODEBITS;                       /*!< (@ 0x000000FC) This register carries the mode bits which are sent in
20725                                                                          the XIP mode of operation after address phase.*/
20726 } NRF_EXMIF_CORE_SSICADDRESS_Type;                   /*!< Size = 256 (0x100)                                                   */
20727 
20728 /* EXMIF_CORE_SSICADDRESS_CTRLR0: This register controls the serial data transfer. */
20729   #define EXMIF_CORE_SSICADDRESS_CTRLR0_ResetValue (0x00004007UL) /*!< Reset value of CTRLR0 register.                         */
20730 
20731 /* DFS @Bits 0..4 : Data Frame Size. */
20732   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Pos (0UL) /*!< Position of DFS field.                                              */
20733   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Pos) /*!< Bit mask of DFS field.  */
20734   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Min (0x0UL) /*!< Min enumerator value of DFS field.                                */
20735   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_Max (0x1FUL) /*!< Max enumerator value of DFS field.                               */
20736   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_01_BIT (0x00UL) /*!< (unspecified)                                             */
20737   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_02_BIT (0x01UL) /*!< (unspecified)                                             */
20738   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_03_BIT (0x02UL) /*!< (unspecified)                                             */
20739   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_04_BIT (0x03UL) /*!< (unspecified)                                             */
20740   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_05_BIT (0x04UL) /*!< (unspecified)                                             */
20741   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_06_BIT (0x05UL) /*!< (unspecified)                                             */
20742   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_07_BIT (0x06UL) /*!< (unspecified)                                             */
20743   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_08_BIT (0x07UL) /*!< (unspecified)                                             */
20744   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_09_BIT (0x08UL) /*!< (unspecified)                                             */
20745   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_10_BIT (0x09UL) /*!< (unspecified)                                             */
20746   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_11_BIT (0x0AUL) /*!< (unspecified)                                             */
20747   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_12_BIT (0x0BUL) /*!< (unspecified)                                             */
20748   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_13_BIT (0x0CUL) /*!< (unspecified)                                             */
20749   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_14_BIT (0x0DUL) /*!< (unspecified)                                             */
20750   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_15_BIT (0x0EUL) /*!< (unspecified)                                             */
20751   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_16_BIT (0x0FUL) /*!< (unspecified)                                             */
20752   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_17_BIT (0x10UL) /*!< (unspecified)                                             */
20753   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_18_BIT (0x11UL) /*!< (unspecified)                                             */
20754   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_19_BIT (0x12UL) /*!< (unspecified)                                             */
20755   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_20_BIT (0x13UL) /*!< (unspecified)                                             */
20756   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_21_BIT (0x14UL) /*!< (unspecified)                                             */
20757   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_22_BIT (0x15UL) /*!< (unspecified)                                             */
20758   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_23_BIT (0x16UL) /*!< (unspecified)                                             */
20759   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_24_BIT (0x17UL) /*!< (unspecified)                                             */
20760   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_25_BIT (0x18UL) /*!< (unspecified)                                             */
20761   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_26_BIT (0x19UL) /*!< (unspecified)                                             */
20762   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_27_BIT (0x1AUL) /*!< (unspecified)                                             */
20763   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_28_BIT (0x1BUL) /*!< (unspecified)                                             */
20764   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_29_BIT (0x1CUL) /*!< (unspecified)                                             */
20765   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_30_BIT (0x1DUL) /*!< (unspecified)                                             */
20766   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_31_BIT (0x1EUL) /*!< (unspecified)                                             */
20767   #define EXMIF_CORE_SSICADDRESS_CTRLR0_DFS_DFS_32_BIT (0x1FUL) /*!< (unspecified)                                             */
20768 
20769 /* RSVDCTRLR05 @Bit 5 : Reserved bits - read as zero */
20770   #define EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR05_Pos (5UL) /*!< Position of RSVDCTRLR05 field.                              */
20771   #define EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR05_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR05_Pos) /*!< Bit mask
20772                                                                             of RSVDCTRLR05 field.*/
20773 
20774 /* FRF @Bits 6..7 : Frame Format. */
20775   #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Pos (6UL) /*!< Position of FRF field.                                              */
20776   #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Pos) /*!< Bit mask of FRF field.   */
20777   #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Min (0x0UL) /*!< Min enumerator value of FRF field.                                */
20778   #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_Max (0x2UL) /*!< Max enumerator value of FRF field.                                */
20779   #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_SPI (0x0UL) /*!< (unspecified)                                                     */
20780   #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_SSP (0x1UL) /*!< (unspecified)                                                     */
20781   #define EXMIF_CORE_SSICADDRESS_CTRLR0_FRF_MICROWIRE (0x2UL) /*!< (unspecified)                                               */
20782 
20783 /* SCPH @Bit 8 : Serial Clock Phase. */
20784   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Pos (8UL) /*!< Position of SCPH field.                                            */
20785   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Pos) /*!< Bit mask of SCPH field.*/
20786   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Min (0x0UL) /*!< Min enumerator value of SCPH field.                              */
20787   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_Max (0x1UL) /*!< Max enumerator value of SCPH field.                              */
20788   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_MIDDLE_BIT (0x0UL) /*!< (unspecified)                                             */
20789   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPH_START_BIT (0x1UL) /*!< (unspecified)                                              */
20790 
20791 /* SCPOL @Bit 9 : Serial Clock Polarity. */
20792   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Pos (9UL) /*!< Position of SCPOL field.                                          */
20793   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Pos) /*!< Bit mask of SCPOL
20794                                                                             field.*/
20795   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Min (0x0UL) /*!< Min enumerator value of SCPOL field.                            */
20796   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_Max (0x1UL) /*!< Max enumerator value of SCPOL field.                            */
20797   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_INACTIVE_HIGH (0x0UL) /*!< (unspecified)                                         */
20798   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SCPOL_INACTIVE_LOW (0x1UL) /*!< (unspecified)                                          */
20799 
20800 /* TMOD @Bits 10..11 : Transfer Mode. */
20801   #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Pos (10UL) /*!< Position of TMOD field.                                           */
20802   #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Pos) /*!< Bit mask of TMOD field.*/
20803   #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Min (0x0UL) /*!< Min enumerator value of TMOD field.                              */
20804   #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_Max (0x3UL) /*!< Max enumerator value of TMOD field.                              */
20805   #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_TX_AND_RX (0x0UL) /*!< (unspecified)                                              */
20806   #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_TX_ONLY (0x1UL) /*!< (unspecified)                                                */
20807   #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_RX_ONLY (0x2UL) /*!< (unspecified)                                                */
20808   #define EXMIF_CORE_SSICADDRESS_CTRLR0_TMOD_EEPROM_READ (0x3UL) /*!< (unspecified)                                            */
20809 
20810 /* SLVOE @Bit 12 : Slave Output Enable. */
20811   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Pos (12UL) /*!< Position of SLVOE field.                                         */
20812   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Pos) /*!< Bit mask of SLVOE
20813                                                                             field.*/
20814   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Min (0x0UL) /*!< Min enumerator value of SLVOE field.                            */
20815   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_Max (0x1UL) /*!< Max enumerator value of SLVOE field.                            */
20816   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_ENABLED (0x0UL) /*!< (unspecified)                                               */
20817   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SLVOE_DISABLED (0x1UL) /*!< (unspecified)                                              */
20818 
20819 /* SRL @Bit 13 : Shift Register Loop. */
20820   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Pos (13UL) /*!< Position of SRL field.                                             */
20821   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Pos) /*!< Bit mask of SRL field.   */
20822   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Min (0x0UL) /*!< Min enumerator value of SRL field.                                */
20823   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_Max (0x1UL) /*!< Max enumerator value of SRL field.                                */
20824   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_NORMAL_MODE (0x0UL) /*!< (unspecified)                                             */
20825   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SRL_TESTING_MODE (0x1UL) /*!< (unspecified)                                            */
20826 
20827 /* SSTE @Bit 14 : Slave Select Toggle Enable. */
20828   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Pos (14UL) /*!< Position of SSTE field.                                           */
20829   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Pos) /*!< Bit mask of SSTE field.*/
20830   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Min (0x0UL) /*!< Min enumerator value of SSTE field.                              */
20831   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_Max (0x1UL) /*!< Max enumerator value of SSTE field.                              */
20832   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_TOGGLE_DISABLE (0x0UL) /*!< (unspecified)                                         */
20833   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSTE_TOGGLE_EN (0x1UL) /*!< (unspecified)                                              */
20834 
20835 /* RSVDCTRLR015 @Bit 15 : Reserved bits - read as zero */
20836   #define EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR015_Pos (15UL) /*!< Position of RSVDCTRLR015 field.                           */
20837   #define EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR015_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR015_Pos) /*!< Bit mask
20838                                                                             of RSVDCTRLR015 field.*/
20839 
20840 /* CFS @Bits 16..19 : Control Frame Size. */
20841   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Pos (16UL) /*!< Position of CFS field.                                             */
20842   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Msk (0xFUL << EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Pos) /*!< Bit mask of CFS field.   */
20843   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Min (0x0UL) /*!< Min enumerator value of CFS field.                                */
20844   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_Max (0xFUL) /*!< Max enumerator value of CFS field.                                */
20845   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_01_BIT (0x0UL) /*!< (unspecified)                                             */
20846   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_02_BIT (0x1UL) /*!< (unspecified)                                             */
20847   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_03_BIT (0x2UL) /*!< (unspecified)                                             */
20848   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_04_BIT (0x3UL) /*!< (unspecified)                                             */
20849   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_05_BIT (0x4UL) /*!< (unspecified)                                             */
20850   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_06_BIT (0x5UL) /*!< (unspecified)                                             */
20851   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_07_BIT (0x6UL) /*!< (unspecified)                                             */
20852   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_08_BIT (0x7UL) /*!< (unspecified)                                             */
20853   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_09_BIT (0x8UL) /*!< (unspecified)                                             */
20854   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_10_BIT (0x9UL) /*!< (unspecified)                                             */
20855   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_11_BIT (0xAUL) /*!< (unspecified)                                             */
20856   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_12_BIT (0xBUL) /*!< (unspecified)                                             */
20857   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_13_BIT (0xCUL) /*!< (unspecified)                                             */
20858   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_14_BIT (0xDUL) /*!< (unspecified)                                             */
20859   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_15_BIT (0xEUL) /*!< (unspecified)                                             */
20860   #define EXMIF_CORE_SSICADDRESS_CTRLR0_CFS_SIZE_16_BIT (0xFUL) /*!< (unspecified)                                             */
20861 
20862 /* RSVDCTRLR02021 @Bits 20..21 : Reserved bits - read as zero */
20863   #define EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR02021_Pos (20UL) /*!< Position of RSVDCTRLR02021 field.                       */
20864   #define EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR02021_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR02021_Pos) /*!< Bit
20865                                                                             mask of RSVDCTRLR02021 field.*/
20866 
20867 /* SPIFRF @Bits 22..23 : SPI Frame Format */
20868   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Pos (22UL) /*!< Position of SPIFRF field.                                       */
20869   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Pos) /*!< Bit mask of SPIFRF
20870                                                                             field.*/
20871   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Min (0x0UL) /*!< Min enumerator value of SPIFRF field.                          */
20872   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_Max (0x3UL) /*!< Max enumerator value of SPIFRF field.                          */
20873   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_SPI_STANDARD (0x0UL) /*!< (unspecified)                                         */
20874   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_SPI_DUAL (0x1UL) /*!< (unspecified)                                             */
20875   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_SPI_QUAD (0x2UL) /*!< (unspecified)                                             */
20876   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIFRF_SPI_OCTAL (0x3UL) /*!< (unspecified)                                            */
20877 
20878 /* SPIHYPERBUSEN @Bit 24 : SPI Hyperbus Frame format enable. */
20879   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Pos (24UL) /*!< Position of SPIHYPERBUSEN field.                         */
20880   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Pos) /*!< Bit
20881                                                                             mask of SPIHYPERBUSEN field.*/
20882   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Min (0x0UL) /*!< Min enumerator value of SPIHYPERBUSEN field.            */
20883   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_Max (0x1UL) /*!< Max enumerator value of SPIHYPERBUSEN field.            */
20884   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_DISABLE (0x0UL) /*!< (unspecified)                                       */
20885   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIHYPERBUSEN_ENABLE (0x1UL) /*!< (unspecified)                                        */
20886 
20887 /* SPIDWSEN @Bit 25 : Enable Dynamic wait states in SPI mode of operation. */
20888   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Pos (25UL) /*!< Position of SPIDWSEN field.                                   */
20889   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Pos) /*!< Bit mask of
20890                                                                             SPIDWSEN field.*/
20891   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Min (0x0UL) /*!< Min enumerator value of SPIDWSEN field.                      */
20892   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_Max (0x1UL) /*!< Max enumerator value of SPIDWSEN field.                      */
20893   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_DISABLE (0x0UL) /*!< (unspecified)                                            */
20894   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SPIDWSEN_ENABLE (0x1UL) /*!< (unspecified)                                             */
20895 
20896 /* RSVDCTRLR02631 @Bits 26..30 : Reserved bits - read as zero */
20897   #define EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR02631_Pos (26UL) /*!< Position of RSVDCTRLR02631 field.                       */
20898   #define EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR02631_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_CTRLR0_RSVDCTRLR02631_Pos) /*!< Bit
20899                                                                             mask of RSVDCTRLR02631 field.*/
20900 
20901 /* SSIISMST @Bit 31 : This field selects if DWC_ssi is working in Master or Slave mode */
20902   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Pos (31UL) /*!< Position of SSIISMST field.                                   */
20903   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Pos) /*!< Bit mask of
20904                                                                             SSIISMST field.*/
20905   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Min (0x0UL) /*!< Min enumerator value of SSIISMST field.                      */
20906   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_Max (0x1UL) /*!< Max enumerator value of SSIISMST field.                      */
20907   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_SLAVE (0x0UL) /*!< (unspecified)                                              */
20908   #define EXMIF_CORE_SSICADDRESS_CTRLR0_SSIISMST_MASTER (0x1UL) /*!< (unspecified)                                             */
20909 
20910 
20911 /* EXMIF_CORE_SSICADDRESS_CTRLR1: This register exists only when the DWC_ssi is configured as a master device. */
20912   #define EXMIF_CORE_SSICADDRESS_CTRLR1_ResetValue (0x00000000UL) /*!< Reset value of CTRLR1 register.                         */
20913 
20914 /* NDF @Bits 0..15 : Number of Data Frames. */
20915   #define EXMIF_CORE_SSICADDRESS_CTRLR1_NDF_Pos (0UL) /*!< Position of NDF field.                                              */
20916   #define EXMIF_CORE_SSICADDRESS_CTRLR1_NDF_Msk (0xFFFFUL << EXMIF_CORE_SSICADDRESS_CTRLR1_NDF_Pos) /*!< Bit mask of NDF field.*/
20917 
20918 /* RSVDCTRLR1 @Bits 16..31 : Reserved bits - read as zero */
20919   #define EXMIF_CORE_SSICADDRESS_CTRLR1_RSVDCTRLR1_Pos (16UL) /*!< Position of RSVDCTRLR1 field.                               */
20920   #define EXMIF_CORE_SSICADDRESS_CTRLR1_RSVDCTRLR1_Msk (0xFFFFUL << EXMIF_CORE_SSICADDRESS_CTRLR1_RSVDCTRLR1_Pos) /*!< Bit mask
20921                                                                             of RSVDCTRLR1 field.*/
20922 
20923 
20924 /* EXMIF_CORE_SSICADDRESS_SSIENR: This register enables and disables the DWC_ssi. */
20925   #define EXMIF_CORE_SSICADDRESS_SSIENR_ResetValue (0x00000000UL) /*!< Reset value of SSIENR register.                         */
20926 
20927 /* SSICEN @Bit 0 : SSI Enable. */
20928   #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Pos (0UL) /*!< Position of SSICEN field.                                        */
20929   #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Pos) /*!< Bit mask of SSICEN
20930                                                                             field.*/
20931   #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Min (0x0UL) /*!< Min enumerator value of SSICEN field.                          */
20932   #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_Max (0x1UL) /*!< Max enumerator value of SSICEN field.                          */
20933   #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_DISABLE (0x0UL) /*!< (unspecified)                                              */
20934   #define EXMIF_CORE_SSICADDRESS_SSIENR_SSICEN_ENABLED (0x1UL) /*!< (unspecified)                                              */
20935 
20936 /* RSVDSSIENR @Bits 1..31 : Reserved bits - read as zero */
20937   #define EXMIF_CORE_SSICADDRESS_SSIENR_RSVDSSIENR_Pos (1UL) /*!< Position of RSVDSSIENR field.                                */
20938   #define EXMIF_CORE_SSICADDRESS_SSIENR_RSVDSSIENR_Msk (0x7FFFFFFFUL << EXMIF_CORE_SSICADDRESS_SSIENR_RSVDSSIENR_Pos) /*!< Bit
20939                                                                             mask of RSVDSSIENR field.*/
20940 
20941 
20942 /* EXMIF_CORE_SSICADDRESS_MWCR: This register controls the direction of the data word for the half-duplex Microwire serial
20943                                  protocol. */
20944 
20945   #define EXMIF_CORE_SSICADDRESS_MWCR_ResetValue (0x00000000UL) /*!< Reset value of MWCR register.                             */
20946 
20947 /* MWMOD @Bit 0 : Microwire Transfer Mode. */
20948   #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Pos (0UL) /*!< Position of MWMOD field.                                            */
20949   #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Pos) /*!< Bit mask of MWMOD field. */
20950   #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Min (0x0UL) /*!< Min enumerator value of MWMOD field.                              */
20951   #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_Max (0x1UL) /*!< Max enumerator value of MWMOD field.                              */
20952   #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_NON_SEQUENTIAL (0x0UL) /*!< (unspecified)                                          */
20953   #define EXMIF_CORE_SSICADDRESS_MWCR_MWMOD_SEQUENTIAL (0x1UL) /*!< (unspecified)                                              */
20954 
20955 /* MDD @Bit 1 : Microwire Control. */
20956   #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_Pos (1UL)  /*!< Position of MDD field.                                               */
20957   #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_MWCR_MDD_Pos) /*!< Bit mask of MDD field.       */
20958   #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_Min (0x0UL) /*!< Min enumerator value of MDD field.                                  */
20959   #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_Max (0x1UL) /*!< Max enumerator value of MDD field.                                  */
20960   #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_RECEIVE (0x0UL) /*!< (unspecified)                                                   */
20961   #define EXMIF_CORE_SSICADDRESS_MWCR_MDD_TRANSMIT (0x1UL) /*!< (unspecified)                                                  */
20962 
20963 /* MHS @Bit 2 : Microwire Handshaking. */
20964   #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_Pos (2UL)  /*!< Position of MHS field.                                               */
20965   #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_MWCR_MHS_Pos) /*!< Bit mask of MHS field.       */
20966   #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_Min (0x0UL) /*!< Min enumerator value of MHS field.                                  */
20967   #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_Max (0x1UL) /*!< Max enumerator value of MHS field.                                  */
20968   #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_DISABLE (0x0UL) /*!< (unspecified)                                                   */
20969   #define EXMIF_CORE_SSICADDRESS_MWCR_MHS_ENABLED (0x1UL) /*!< (unspecified)                                                   */
20970 
20971 /* RSVDMWCR @Bits 3..31 : Reserved bits - read as zero */
20972   #define EXMIF_CORE_SSICADDRESS_MWCR_RSVDMWCR_Pos (3UL) /*!< Position of RSVDMWCR field.                                      */
20973   #define EXMIF_CORE_SSICADDRESS_MWCR_RSVDMWCR_Msk (0x1FFFFFFFUL << EXMIF_CORE_SSICADDRESS_MWCR_RSVDMWCR_Pos) /*!< Bit mask of
20974                                                                             RSVDMWCR field.*/
20975 
20976 
20977 /* EXMIF_CORE_SSICADDRESS_SER: This register is valid only when the DWC_ssi is configured as a master device. */
20978   #define EXMIF_CORE_SSICADDRESS_SER_ResetValue (0x00000000UL) /*!< Reset value of SER register.                               */
20979 
20980 /* SER @Bits 0..1 : Slave Select Enable Flag. */
20981   #define EXMIF_CORE_SSICADDRESS_SER_SER_Pos (0UL)   /*!< Position of SER field.                                               */
20982   #define EXMIF_CORE_SSICADDRESS_SER_SER_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SER_SER_Pos) /*!< Bit mask of SER field.         */
20983   #define EXMIF_CORE_SSICADDRESS_SER_SER_Min (0x0UL) /*!< Min enumerator value of SER field.                                   */
20984   #define EXMIF_CORE_SSICADDRESS_SER_SER_Max (0x1UL) /*!< Max enumerator value of SER field.                                   */
20985   #define EXMIF_CORE_SSICADDRESS_SER_SER_NOTSELECTED (0x0UL) /*!< (unspecified)                                                */
20986   #define EXMIF_CORE_SSICADDRESS_SER_SER_SELECTED (0x1UL) /*!< (unspecified)                                                   */
20987 
20988 /* RSVDSER @Bits 2..31 : Reserved bits - read as zero */
20989   #define EXMIF_CORE_SSICADDRESS_SER_RSVDSER_Pos (2UL) /*!< Position of RSVDSER field.                                         */
20990   #define EXMIF_CORE_SSICADDRESS_SER_RSVDSER_Msk (0x3FFFFFFFUL << EXMIF_CORE_SSICADDRESS_SER_RSVDSER_Pos) /*!< Bit mask of
20991                                                                             RSVDSER field.*/
20992 
20993 
20994 /* EXMIF_CORE_SSICADDRESS_BAUDR: This register is valid only when the DWC_ssi is configured as a master device. */
20995   #define EXMIF_CORE_SSICADDRESS_BAUDR_ResetValue (0x00000000UL) /*!< Reset value of BAUDR register.                           */
20996 
20997 /* RSVDBAUDR0 @Bit 0 : Reserved bits - read as zero */
20998   #define EXMIF_CORE_SSICADDRESS_BAUDR_RSVDBAUDR0_Pos (0UL) /*!< Position of RSVDBAUDR0 field.                                 */
20999   #define EXMIF_CORE_SSICADDRESS_BAUDR_RSVDBAUDR0_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_BAUDR_RSVDBAUDR0_Pos) /*!< Bit mask of
21000                                                                             RSVDBAUDR0 field.*/
21001 
21002 /* SCKDV @Bits 1..15 : SSI Clock Divider. */
21003   #define EXMIF_CORE_SSICADDRESS_BAUDR_SCKDV_Pos (1UL) /*!< Position of SCKDV field.                                           */
21004   #define EXMIF_CORE_SSICADDRESS_BAUDR_SCKDV_Msk (0x7FFFUL << EXMIF_CORE_SSICADDRESS_BAUDR_SCKDV_Pos) /*!< Bit mask of SCKDV
21005                                                                             field.*/
21006 
21007 /* RSVDBAUDR1631 @Bits 16..31 : Reserved bits - read as zero */
21008   #define EXMIF_CORE_SSICADDRESS_BAUDR_RSVDBAUDR1631_Pos (16UL) /*!< Position of RSVDBAUDR1631 field.                          */
21009   #define EXMIF_CORE_SSICADDRESS_BAUDR_RSVDBAUDR1631_Msk (0xFFFFUL << EXMIF_CORE_SSICADDRESS_BAUDR_RSVDBAUDR1631_Pos) /*!< Bit
21010                                                                             mask of RSVDBAUDR1631 field.*/
21011 
21012 
21013 /* EXMIF_CORE_SSICADDRESS_TXFTLR: This register controls the threshold value for the transmit FIFO memory.. */
21014   #define EXMIF_CORE_SSICADDRESS_TXFTLR_ResetValue (0x00000000UL) /*!< Reset value of TXFTLR register.                         */
21015 
21016 /* TFT @Bits 0..4 : Transmit FIFO Threshold. */
21017   #define EXMIF_CORE_SSICADDRESS_TXFTLR_TFT_Pos (0UL) /*!< Position of TFT field.                                              */
21018   #define EXMIF_CORE_SSICADDRESS_TXFTLR_TFT_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_TXFTLR_TFT_Pos) /*!< Bit mask of TFT field.  */
21019 
21020 /* RSVDTXFTLR @Bits 5..15 : Reserved bits - read as zero */
21021   #define EXMIF_CORE_SSICADDRESS_TXFTLR_RSVDTXFTLR_Pos (5UL) /*!< Position of RSVDTXFTLR field.                                */
21022   #define EXMIF_CORE_SSICADDRESS_TXFTLR_RSVDTXFTLR_Msk (0x7FFUL << EXMIF_CORE_SSICADDRESS_TXFTLR_RSVDTXFTLR_Pos) /*!< Bit mask
21023                                                                             of RSVDTXFTLR field.*/
21024 
21025 /* TXFTHR @Bits 16..20 : Transfer start FIFO level. */
21026   #define EXMIF_CORE_SSICADDRESS_TXFTLR_TXFTHR_Pos (16UL) /*!< Position of TXFTHR field.                                       */
21027   #define EXMIF_CORE_SSICADDRESS_TXFTLR_TXFTHR_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_TXFTLR_TXFTHR_Pos) /*!< Bit mask of TXFTHR
21028                                                                             field.*/
21029 
21030 /* RSVDTXFTHR @Bits 21..31 : Reserved bits - read as zero */
21031   #define EXMIF_CORE_SSICADDRESS_TXFTLR_RSVDTXFTHR_Pos (21UL) /*!< Position of RSVDTXFTHR field.                               */
21032   #define EXMIF_CORE_SSICADDRESS_TXFTLR_RSVDTXFTHR_Msk (0x7FFUL << EXMIF_CORE_SSICADDRESS_TXFTLR_RSVDTXFTHR_Pos) /*!< Bit mask
21033                                                                             of RSVDTXFTHR field.*/
21034 
21035 
21036 /* EXMIF_CORE_SSICADDRESS_RXFTLR: This register controls the threshold value for the receive FIFO memory.. */
21037   #define EXMIF_CORE_SSICADDRESS_RXFTLR_ResetValue (0x00000000UL) /*!< Reset value of RXFTLR register.                         */
21038 
21039 /* RFT @Bits 0..4 : Receive FIFO Threshold. */
21040   #define EXMIF_CORE_SSICADDRESS_RXFTLR_RFT_Pos (0UL) /*!< Position of RFT field.                                              */
21041   #define EXMIF_CORE_SSICADDRESS_RXFTLR_RFT_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_RXFTLR_RFT_Pos) /*!< Bit mask of RFT field.  */
21042 
21043 /* RSVDRXFTLR @Bits 5..31 : Reserved bits - read as zero */
21044   #define EXMIF_CORE_SSICADDRESS_RXFTLR_RSVDRXFTLR_Pos (5UL) /*!< Position of RSVDRXFTLR field.                                */
21045   #define EXMIF_CORE_SSICADDRESS_RXFTLR_RSVDRXFTLR_Msk (0x7FFFFFFUL << EXMIF_CORE_SSICADDRESS_RXFTLR_RSVDRXFTLR_Pos) /*!< Bit
21046                                                                             mask of RSVDRXFTLR field.*/
21047 
21048 
21049 /* EXMIF_CORE_SSICADDRESS_TXFLR: This register contains the number of valid data entries in the transmit FIFO memory. */
21050   #define EXMIF_CORE_SSICADDRESS_TXFLR_ResetValue (0x00000000UL) /*!< Reset value of TXFLR register.                           */
21051 
21052 /* TXTFL @Bits 0..5 : Transmit FIFO Level. */
21053   #define EXMIF_CORE_SSICADDRESS_TXFLR_TXTFL_Pos (0UL) /*!< Position of TXTFL field.                                           */
21054   #define EXMIF_CORE_SSICADDRESS_TXFLR_TXTFL_Msk (0x3FUL << EXMIF_CORE_SSICADDRESS_TXFLR_TXTFL_Pos) /*!< Bit mask of TXTFL
21055                                                                             field.*/
21056 
21057 /* RSVDTXFLR @Bits 6..31 : Reserved bits - read as zero */
21058   #define EXMIF_CORE_SSICADDRESS_TXFLR_RSVDTXFLR_Pos (6UL) /*!< Position of RSVDTXFLR field.                                   */
21059   #define EXMIF_CORE_SSICADDRESS_TXFLR_RSVDTXFLR_Msk (0x3FFFFFFUL << EXMIF_CORE_SSICADDRESS_TXFLR_RSVDTXFLR_Pos) /*!< Bit mask
21060                                                                             of RSVDTXFLR field.*/
21061 
21062 
21063 /* EXMIF_CORE_SSICADDRESS_RXFLR: This register contains the number of valid data entries in the receive FIFO memory. */
21064   #define EXMIF_CORE_SSICADDRESS_RXFLR_ResetValue (0x00000000UL) /*!< Reset value of RXFLR register.                           */
21065 
21066 /* RXTFL @Bits 0..5 : Receive FIFO Level. */
21067   #define EXMIF_CORE_SSICADDRESS_RXFLR_RXTFL_Pos (0UL) /*!< Position of RXTFL field.                                           */
21068   #define EXMIF_CORE_SSICADDRESS_RXFLR_RXTFL_Msk (0x3FUL << EXMIF_CORE_SSICADDRESS_RXFLR_RXTFL_Pos) /*!< Bit mask of RXTFL
21069                                                                             field.*/
21070 
21071 /* RSVDRXFLR @Bits 6..31 : Reserved bits - read as zero */
21072   #define EXMIF_CORE_SSICADDRESS_RXFLR_RSVDRXFLR_Pos (6UL) /*!< Position of RSVDRXFLR field.                                   */
21073   #define EXMIF_CORE_SSICADDRESS_RXFLR_RSVDRXFLR_Msk (0x3FFFFFFUL << EXMIF_CORE_SSICADDRESS_RXFLR_RSVDRXFLR_Pos) /*!< Bit mask
21074                                                                             of RSVDRXFLR field.*/
21075 
21076 
21077 /* EXMIF_CORE_SSICADDRESS_SR: This is a read-only register used to indicate the current transfer status, FIFO status, and any
21078                                transmission/reception errors that may have occurred. */
21079 
21080   #define EXMIF_CORE_SSICADDRESS_SR_ResetValue (0x00000006UL) /*!< Reset value of SR register.                                 */
21081 
21082 /* BUSY @Bit 0 : SSI Busy Flag. */
21083   #define EXMIF_CORE_SSICADDRESS_SR_BUSY_Pos (0UL)   /*!< Position of BUSY field.                                              */
21084   #define EXMIF_CORE_SSICADDRESS_SR_BUSY_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_BUSY_Pos) /*!< Bit mask of BUSY field.        */
21085   #define EXMIF_CORE_SSICADDRESS_SR_BUSY_Min (0x0UL) /*!< Min enumerator value of BUSY field.                                  */
21086   #define EXMIF_CORE_SSICADDRESS_SR_BUSY_Max (0x1UL) /*!< Max enumerator value of BUSY field.                                  */
21087   #define EXMIF_CORE_SSICADDRESS_SR_BUSY_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
21088   #define EXMIF_CORE_SSICADDRESS_SR_BUSY_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
21089 
21090 /* TFNF @Bit 1 : Transmit FIFO Not Full. */
21091   #define EXMIF_CORE_SSICADDRESS_SR_TFNF_Pos (1UL)   /*!< Position of TFNF field.                                              */
21092   #define EXMIF_CORE_SSICADDRESS_SR_TFNF_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_TFNF_Pos) /*!< Bit mask of TFNF field.        */
21093   #define EXMIF_CORE_SSICADDRESS_SR_TFNF_Min (0x0UL) /*!< Min enumerator value of TFNF field.                                  */
21094   #define EXMIF_CORE_SSICADDRESS_SR_TFNF_Max (0x1UL) /*!< Max enumerator value of TFNF field.                                  */
21095   #define EXMIF_CORE_SSICADDRESS_SR_TFNF_FULL (0x0UL) /*!< (unspecified)                                                       */
21096   #define EXMIF_CORE_SSICADDRESS_SR_TFNF_NOT_FULL (0x1UL) /*!< (unspecified)                                                   */
21097 
21098 /* TFE @Bit 2 : Transmit FIFO Empty. */
21099   #define EXMIF_CORE_SSICADDRESS_SR_TFE_Pos (2UL)    /*!< Position of TFE field.                                               */
21100   #define EXMIF_CORE_SSICADDRESS_SR_TFE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_TFE_Pos) /*!< Bit mask of TFE field.           */
21101   #define EXMIF_CORE_SSICADDRESS_SR_TFE_Min (0x0UL)  /*!< Min enumerator value of TFE field.                                   */
21102   #define EXMIF_CORE_SSICADDRESS_SR_TFE_Max (0x1UL)  /*!< Max enumerator value of TFE field.                                   */
21103   #define EXMIF_CORE_SSICADDRESS_SR_TFE_NOT_EMPTY (0x0UL) /*!< (unspecified)                                                   */
21104   #define EXMIF_CORE_SSICADDRESS_SR_TFE_EMPTY (0x1UL) /*!< (unspecified)                                                       */
21105 
21106 /* RFNE @Bit 3 : Receive FIFO Not Empty. */
21107   #define EXMIF_CORE_SSICADDRESS_SR_RFNE_Pos (3UL)   /*!< Position of RFNE field.                                              */
21108   #define EXMIF_CORE_SSICADDRESS_SR_RFNE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_RFNE_Pos) /*!< Bit mask of RFNE field.        */
21109   #define EXMIF_CORE_SSICADDRESS_SR_RFNE_Min (0x0UL) /*!< Min enumerator value of RFNE field.                                  */
21110   #define EXMIF_CORE_SSICADDRESS_SR_RFNE_Max (0x1UL) /*!< Max enumerator value of RFNE field.                                  */
21111   #define EXMIF_CORE_SSICADDRESS_SR_RFNE_EMPTY (0x0UL) /*!< (unspecified)                                                      */
21112   #define EXMIF_CORE_SSICADDRESS_SR_RFNE_NOT_EMPTY (0x1UL) /*!< (unspecified)                                                  */
21113 
21114 /* RFF @Bit 4 : Receive FIFO Full. */
21115   #define EXMIF_CORE_SSICADDRESS_SR_RFF_Pos (4UL)    /*!< Position of RFF field.                                               */
21116   #define EXMIF_CORE_SSICADDRESS_SR_RFF_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_RFF_Pos) /*!< Bit mask of RFF field.           */
21117   #define EXMIF_CORE_SSICADDRESS_SR_RFF_Min (0x0UL)  /*!< Min enumerator value of RFF field.                                   */
21118   #define EXMIF_CORE_SSICADDRESS_SR_RFF_Max (0x1UL)  /*!< Max enumerator value of RFF field.                                   */
21119   #define EXMIF_CORE_SSICADDRESS_SR_RFF_NOT_FULL (0x0UL) /*!< (unspecified)                                                    */
21120   #define EXMIF_CORE_SSICADDRESS_SR_RFF_FULL (0x1UL) /*!< (unspecified)                                                        */
21121 
21122 /* TXE @Bit 5 : Transmission Error. */
21123   #define EXMIF_CORE_SSICADDRESS_SR_TXE_Pos (5UL)    /*!< Position of TXE field.                                               */
21124   #define EXMIF_CORE_SSICADDRESS_SR_TXE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_TXE_Pos) /*!< Bit mask of TXE field.           */
21125   #define EXMIF_CORE_SSICADDRESS_SR_TXE_Min (0x0UL)  /*!< Min enumerator value of TXE field.                                   */
21126   #define EXMIF_CORE_SSICADDRESS_SR_TXE_Max (0x1UL)  /*!< Max enumerator value of TXE field.                                   */
21127   #define EXMIF_CORE_SSICADDRESS_SR_TXE_NO_ERROR (0x0UL) /*!< (unspecified)                                                    */
21128   #define EXMIF_CORE_SSICADDRESS_SR_TXE_TX_ERROR (0x1UL) /*!< (unspecified)                                                    */
21129 
21130 /* DCOL @Bit 6 : Data Collision Error. */
21131   #define EXMIF_CORE_SSICADDRESS_SR_DCOL_Pos (6UL)   /*!< Position of DCOL field.                                              */
21132   #define EXMIF_CORE_SSICADDRESS_SR_DCOL_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SR_DCOL_Pos) /*!< Bit mask of DCOL field.        */
21133   #define EXMIF_CORE_SSICADDRESS_SR_DCOL_Min (0x0UL) /*!< Min enumerator value of DCOL field.                                  */
21134   #define EXMIF_CORE_SSICADDRESS_SR_DCOL_Max (0x1UL) /*!< Max enumerator value of DCOL field.                                  */
21135   #define EXMIF_CORE_SSICADDRESS_SR_DCOL_NO_ERROR_CONDITION (0x0UL) /*!< (unspecified)                                         */
21136   #define EXMIF_CORE_SSICADDRESS_SR_DCOL_TX_COLLISION_ERROR (0x1UL) /*!< (unspecified)                                         */
21137 
21138 /* RSVDSR @Bits 7..14 : Reserved bits - read as zero */
21139   #define EXMIF_CORE_SSICADDRESS_SR_RSVDSR_Pos (7UL) /*!< Position of RSVDSR field.                                            */
21140   #define EXMIF_CORE_SSICADDRESS_SR_RSVDSR_Msk (0xFFUL << EXMIF_CORE_SSICADDRESS_SR_RSVDSR_Pos) /*!< Bit mask of RSVDSR field. */
21141 
21142 /* CMPLTDDF @Bits 15..31 : Completed Data frames */
21143   #define EXMIF_CORE_SSICADDRESS_SR_CMPLTDDF_Pos (15UL) /*!< Position of CMPLTDDF field.                                       */
21144   #define EXMIF_CORE_SSICADDRESS_SR_CMPLTDDF_Msk (0x1FFFFUL << EXMIF_CORE_SSICADDRESS_SR_CMPLTDDF_Pos) /*!< Bit mask of CMPLTDDF
21145                                                                             field.*/
21146 
21147 
21148 /* EXMIF_CORE_SSICADDRESS_IMR: This read/write register masks or enables all interrupts generated by the DWC_ssi. */
21149   #define EXMIF_CORE_SSICADDRESS_IMR_ResetValue (0x000000FFUL) /*!< Reset value of IMR register.                               */
21150 
21151 /* TXEIM @Bit 0 : Transmit FIFO Empty Interrupt Mask */
21152   #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Pos (0UL) /*!< Position of TXEIM field.                                             */
21153   #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Pos) /*!< Bit mask of TXEIM field.   */
21154   #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Min (0x0UL) /*!< Min enumerator value of TXEIM field.                               */
21155   #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_Max (0x1UL) /*!< Max enumerator value of TXEIM field.                               */
21156   #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_MASKED (0x0UL) /*!< (unspecified)                                                   */
21157   #define EXMIF_CORE_SSICADDRESS_IMR_TXEIM_UNMASKED (0x1UL) /*!< (unspecified)                                                 */
21158 
21159 /* TXOIM @Bit 1 : Transmit FIFO Overflow Interrupt Mask */
21160   #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Pos (1UL) /*!< Position of TXOIM field.                                             */
21161   #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Pos) /*!< Bit mask of TXOIM field.   */
21162   #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Min (0x0UL) /*!< Min enumerator value of TXOIM field.                               */
21163   #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_Max (0x1UL) /*!< Max enumerator value of TXOIM field.                               */
21164   #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_MASKED (0x0UL) /*!< (unspecified)                                                   */
21165   #define EXMIF_CORE_SSICADDRESS_IMR_TXOIM_UNMASKED (0x1UL) /*!< (unspecified)                                                 */
21166 
21167 /* RXUIM @Bit 2 : Receive FIFO Underflow Interrupt Mask */
21168   #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Pos (2UL) /*!< Position of RXUIM field.                                             */
21169   #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Pos) /*!< Bit mask of RXUIM field.   */
21170   #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Min (0x0UL) /*!< Min enumerator value of RXUIM field.                               */
21171   #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_Max (0x1UL) /*!< Max enumerator value of RXUIM field.                               */
21172   #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_MASKED (0x0UL) /*!< (unspecified)                                                   */
21173   #define EXMIF_CORE_SSICADDRESS_IMR_RXUIM_UNMASKED (0x1UL) /*!< (unspecified)                                                 */
21174 
21175 /* RXOIM @Bit 3 : Receive FIFO Overflow Interrupt Mask */
21176   #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Pos (3UL) /*!< Position of RXOIM field.                                             */
21177   #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Pos) /*!< Bit mask of RXOIM field.   */
21178   #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Min (0x0UL) /*!< Min enumerator value of RXOIM field.                               */
21179   #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_Max (0x1UL) /*!< Max enumerator value of RXOIM field.                               */
21180   #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_MASKED (0x0UL) /*!< (unspecified)                                                   */
21181   #define EXMIF_CORE_SSICADDRESS_IMR_RXOIM_UNMASKED (0x1UL) /*!< (unspecified)                                                 */
21182 
21183 /* RXFIM @Bit 4 : Receive FIFO Full Interrupt Mask */
21184   #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Pos (4UL) /*!< Position of RXFIM field.                                             */
21185   #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Pos) /*!< Bit mask of RXFIM field.   */
21186   #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Min (0x0UL) /*!< Min enumerator value of RXFIM field.                               */
21187   #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_Max (0x1UL) /*!< Max enumerator value of RXFIM field.                               */
21188   #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_MASKED (0x0UL) /*!< ssi_rxf_intr interrupt is masked                                */
21189   #define EXMIF_CORE_SSICADDRESS_IMR_RXFIM_UNMASKED (0x1UL) /*!< ssi_rxf_intr interrupt is not masked                          */
21190 
21191 /* MSTIM @Bit 5 : Multi-Master Contention Interrupt Mask. */
21192   #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Pos (5UL) /*!< Position of MSTIM field.                                             */
21193   #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Pos) /*!< Bit mask of MSTIM field.   */
21194   #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Min (0x0UL) /*!< Min enumerator value of MSTIM field.                               */
21195   #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_Max (0x1UL) /*!< Max enumerator value of MSTIM field.                               */
21196   #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_MASKED (0x0UL) /*!< (unspecified)                                                   */
21197   #define EXMIF_CORE_SSICADDRESS_IMR_MSTIM_UNMASKED (0x1UL) /*!< (unspecified)                                                 */
21198 
21199 /* XRXOIM @Bit 6 : XIP Receive FIFO Overflow Interrupt Mask */
21200   #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Pos (6UL) /*!< Position of XRXOIM field.                                           */
21201   #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Pos) /*!< Bit mask of XRXOIM field.*/
21202   #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Min (0x0UL) /*!< Min enumerator value of XRXOIM field.                             */
21203   #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_Max (0x1UL) /*!< Max enumerator value of XRXOIM field.                             */
21204   #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_MASKED (0x0UL) /*!< (unspecified)                                                  */
21205   #define EXMIF_CORE_SSICADDRESS_IMR_XRXOIM_UNMASKED (0x1UL) /*!< (unspecified)                                                */
21206 
21207 /* TXUIM @Bit 7 : Transmit FIFO Underflow Interrupt Mask */
21208   #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Pos (7UL) /*!< Position of TXUIM field.                                             */
21209   #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Pos) /*!< Bit mask of TXUIM field.   */
21210   #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Min (0x0UL) /*!< Min enumerator value of TXUIM field.                               */
21211   #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_Max (0x1UL) /*!< Max enumerator value of TXUIM field.                               */
21212   #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_MASKED (0x0UL) /*!< (unspecified)                                                   */
21213   #define EXMIF_CORE_SSICADDRESS_IMR_TXUIM_UNMASKED (0x1UL) /*!< (unspecified)                                                 */
21214 
21215 /* AXIEM @Bit 8 : AXI Error Interrupt Mask */
21216   #define EXMIF_CORE_SSICADDRESS_IMR_AXIEM_Pos (8UL) /*!< Position of AXIEM field.                                             */
21217   #define EXMIF_CORE_SSICADDRESS_IMR_AXIEM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_AXIEM_Pos) /*!< Bit mask of AXIEM field.   */
21218   #define EXMIF_CORE_SSICADDRESS_IMR_AXIEM_Min (0x0UL) /*!< Min enumerator value of AXIEM field.                               */
21219   #define EXMIF_CORE_SSICADDRESS_IMR_AXIEM_Max (0x1UL) /*!< Max enumerator value of AXIEM field.                               */
21220   #define EXMIF_CORE_SSICADDRESS_IMR_AXIEM_MASKED (0x0UL) /*!< (unspecified)                                                   */
21221   #define EXMIF_CORE_SSICADDRESS_IMR_AXIEM_UNMASKED (0x1UL) /*!< (unspecified)                                                 */
21222 
21223 /* RSVD9IMR @Bit 9 : Reserved bits - read as zero */
21224   #define EXMIF_CORE_SSICADDRESS_IMR_RSVD9IMR_Pos (9UL) /*!< Position of RSVD9IMR field.                                       */
21225   #define EXMIF_CORE_SSICADDRESS_IMR_RSVD9IMR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_RSVD9IMR_Pos) /*!< Bit mask of RSVD9IMR
21226                                                                             field.*/
21227 
21228 /* SPITEM @Bit 10 : SPI Transmit Error Interrupt Mask */
21229   #define EXMIF_CORE_SSICADDRESS_IMR_SPITEM_Pos (10UL) /*!< Position of SPITEM field.                                          */
21230   #define EXMIF_CORE_SSICADDRESS_IMR_SPITEM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_SPITEM_Pos) /*!< Bit mask of SPITEM field.*/
21231   #define EXMIF_CORE_SSICADDRESS_IMR_SPITEM_Min (0x0UL) /*!< Min enumerator value of SPITEM field.                             */
21232   #define EXMIF_CORE_SSICADDRESS_IMR_SPITEM_Max (0x1UL) /*!< Max enumerator value of SPITEM field.                             */
21233   #define EXMIF_CORE_SSICADDRESS_IMR_SPITEM_MASKED (0x0UL) /*!< (unspecified)                                                  */
21234   #define EXMIF_CORE_SSICADDRESS_IMR_SPITEM_UNMASKED (0x1UL) /*!< (unspecified)                                                */
21235 
21236 /* DONEM @Bit 11 : SSI Done Interrupt Mask */
21237   #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_Pos (11UL) /*!< Position of DONEM field.                                            */
21238   #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_IMR_DONEM_Pos) /*!< Bit mask of DONEM field.   */
21239   #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_Min (0x0UL) /*!< Min enumerator value of DONEM field.                               */
21240   #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_Max (0x1UL) /*!< Max enumerator value of DONEM field.                               */
21241   #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_MASKED (0x0UL) /*!< (unspecified)                                                   */
21242   #define EXMIF_CORE_SSICADDRESS_IMR_DONEM_UNMASKED (0x1UL) /*!< (unspecified)                                                 */
21243 
21244 /* RSVD1232IMR @Bits 12..31 : Reserved bits - read as zero */
21245   #define EXMIF_CORE_SSICADDRESS_IMR_RSVD1232IMR_Pos (12UL) /*!< Position of RSVD1232IMR field.                                */
21246   #define EXMIF_CORE_SSICADDRESS_IMR_RSVD1232IMR_Msk (0xFFFFFUL << EXMIF_CORE_SSICADDRESS_IMR_RSVD1232IMR_Pos) /*!< Bit mask of
21247                                                                             RSVD1232IMR field.*/
21248 
21249 
21250 /* EXMIF_CORE_SSICADDRESS_ISR: This register reports the status of the DWC_ssi interrupts after they have been masked. */
21251   #define EXMIF_CORE_SSICADDRESS_ISR_ResetValue (0x00000000UL) /*!< Reset value of ISR register.                               */
21252 
21253 /* TXEIS @Bit 0 : Transmit FIFO Empty Interrupt Status */
21254   #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Pos (0UL) /*!< Position of TXEIS field.                                             */
21255   #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Pos) /*!< Bit mask of TXEIS field.   */
21256   #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Min (0x0UL) /*!< Min enumerator value of TXEIS field.                               */
21257   #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_Max (0x1UL) /*!< Max enumerator value of TXEIS field.                               */
21258   #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21259   #define EXMIF_CORE_SSICADDRESS_ISR_TXEIS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21260 
21261 /* TXOIS @Bit 1 : Transmit FIFO Overflow Interrupt Status */
21262   #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Pos (1UL) /*!< Position of TXOIS field.                                             */
21263   #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Pos) /*!< Bit mask of TXOIS field.   */
21264   #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Min (0x0UL) /*!< Min enumerator value of TXOIS field.                               */
21265   #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_Max (0x1UL) /*!< Max enumerator value of TXOIS field.                               */
21266   #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21267   #define EXMIF_CORE_SSICADDRESS_ISR_TXOIS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21268 
21269 /* RXUIS @Bit 2 : Receive FIFO Underflow Interrupt Status */
21270   #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Pos (2UL) /*!< Position of RXUIS field.                                             */
21271   #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Pos) /*!< Bit mask of RXUIS field.   */
21272   #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Min (0x0UL) /*!< Min enumerator value of RXUIS field.                               */
21273   #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_Max (0x1UL) /*!< Max enumerator value of RXUIS field.                               */
21274   #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21275   #define EXMIF_CORE_SSICADDRESS_ISR_RXUIS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21276 
21277 /* RXOIS @Bit 3 : Receive FIFO Overflow Interrupt Status */
21278   #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Pos (3UL) /*!< Position of RXOIS field.                                             */
21279   #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Pos) /*!< Bit mask of RXOIS field.   */
21280   #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Min (0x0UL) /*!< Min enumerator value of RXOIS field.                               */
21281   #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_Max (0x1UL) /*!< Max enumerator value of RXOIS field.                               */
21282   #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21283   #define EXMIF_CORE_SSICADDRESS_ISR_RXOIS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21284 
21285 /* RXFIS @Bit 4 : Receive FIFO Full Interrupt Status */
21286   #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Pos (4UL) /*!< Position of RXFIS field.                                             */
21287   #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Pos) /*!< Bit mask of RXFIS field.   */
21288   #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Min (0x0UL) /*!< Min enumerator value of RXFIS field.                               */
21289   #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_Max (0x1UL) /*!< Max enumerator value of RXFIS field.                               */
21290   #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21291   #define EXMIF_CORE_SSICADDRESS_ISR_RXFIS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21292 
21293 /* MSTIS @Bit 5 : Multi-Master Contention Interrupt Status. */
21294   #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Pos (5UL) /*!< Position of MSTIS field.                                             */
21295   #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Pos) /*!< Bit mask of MSTIS field.   */
21296   #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Min (0x0UL) /*!< Min enumerator value of MSTIS field.                               */
21297   #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_Max (0x1UL) /*!< Max enumerator value of MSTIS field.                               */
21298   #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21299   #define EXMIF_CORE_SSICADDRESS_ISR_MSTIS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21300 
21301 /* XRXOIS @Bit 6 : XIP Receive FIFO Overflow Interrupt Status */
21302   #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Pos (6UL) /*!< Position of XRXOIS field.                                           */
21303   #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Pos) /*!< Bit mask of XRXOIS field.*/
21304   #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Min (0x0UL) /*!< Min enumerator value of XRXOIS field.                             */
21305   #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_Max (0x1UL) /*!< Max enumerator value of XRXOIS field.                             */
21306   #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21307   #define EXMIF_CORE_SSICADDRESS_ISR_XRXOIS_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21308 
21309 /* TXUIS @Bit 7 : Transmit FIFO Underflow Interrupt Status */
21310   #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Pos (7UL) /*!< Position of TXUIS field.                                             */
21311   #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Pos) /*!< Bit mask of TXUIS field.   */
21312   #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Min (0x0UL) /*!< Min enumerator value of TXUIS field.                               */
21313   #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_Max (0x1UL) /*!< Max enumerator value of TXUIS field.                               */
21314   #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21315   #define EXMIF_CORE_SSICADDRESS_ISR_TXUIS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21316 
21317 /* AXIES @Bit 8 : AXI Error Interrupt Status */
21318   #define EXMIF_CORE_SSICADDRESS_ISR_AXIES_Pos (8UL) /*!< Position of AXIES field.                                             */
21319   #define EXMIF_CORE_SSICADDRESS_ISR_AXIES_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_AXIES_Pos) /*!< Bit mask of AXIES field.   */
21320   #define EXMIF_CORE_SSICADDRESS_ISR_AXIES_Min (0x0UL) /*!< Min enumerator value of AXIES field.                               */
21321   #define EXMIF_CORE_SSICADDRESS_ISR_AXIES_Max (0x1UL) /*!< Max enumerator value of AXIES field.                               */
21322   #define EXMIF_CORE_SSICADDRESS_ISR_AXIES_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21323   #define EXMIF_CORE_SSICADDRESS_ISR_AXIES_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21324 
21325 /* RSVD9RISR @Bit 9 : Reserved bits - read as zero */
21326   #define EXMIF_CORE_SSICADDRESS_ISR_RSVD9RISR_Pos (9UL) /*!< Position of RSVD9RISR field.                                     */
21327   #define EXMIF_CORE_SSICADDRESS_ISR_RSVD9RISR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_RSVD9RISR_Pos) /*!< Bit mask of
21328                                                                             RSVD9RISR field.*/
21329 
21330 /* SPITES @Bit 10 : SPI Transmit Error Interrupt */
21331   #define EXMIF_CORE_SSICADDRESS_ISR_SPITES_Pos (10UL) /*!< Position of SPITES field.                                          */
21332   #define EXMIF_CORE_SSICADDRESS_ISR_SPITES_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_SPITES_Pos) /*!< Bit mask of SPITES field.*/
21333   #define EXMIF_CORE_SSICADDRESS_ISR_SPITES_Min (0x0UL) /*!< Min enumerator value of SPITES field.                             */
21334   #define EXMIF_CORE_SSICADDRESS_ISR_SPITES_Max (0x1UL) /*!< Max enumerator value of SPITES field.                             */
21335   #define EXMIF_CORE_SSICADDRESS_ISR_SPITES_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21336   #define EXMIF_CORE_SSICADDRESS_ISR_SPITES_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21337 
21338 /* DONES @Bit 11 : SSI Done Interrupt Status */
21339   #define EXMIF_CORE_SSICADDRESS_ISR_DONES_Pos (11UL) /*!< Position of DONES field.                                            */
21340   #define EXMIF_CORE_SSICADDRESS_ISR_DONES_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ISR_DONES_Pos) /*!< Bit mask of DONES field.   */
21341   #define EXMIF_CORE_SSICADDRESS_ISR_DONES_Min (0x0UL) /*!< Min enumerator value of DONES field.                               */
21342   #define EXMIF_CORE_SSICADDRESS_ISR_DONES_Max (0x1UL) /*!< Max enumerator value of DONES field.                               */
21343   #define EXMIF_CORE_SSICADDRESS_ISR_DONES_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
21344   #define EXMIF_CORE_SSICADDRESS_ISR_DONES_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
21345 
21346 /* RSVD1232RISR @Bits 12..31 : Reserved bits - read as zero */
21347   #define EXMIF_CORE_SSICADDRESS_ISR_RSVD1232RISR_Pos (12UL) /*!< Position of RSVD1232RISR field.                              */
21348   #define EXMIF_CORE_SSICADDRESS_ISR_RSVD1232RISR_Msk (0xFFFFFUL << EXMIF_CORE_SSICADDRESS_ISR_RSVD1232RISR_Pos) /*!< Bit mask
21349                                                                             of RSVD1232RISR field.*/
21350 
21351 
21352 /* EXMIF_CORE_SSICADDRESS_RISR: Raw Interrupt Status Register */
21353   #define EXMIF_CORE_SSICADDRESS_RISR_ResetValue (0x00000000UL) /*!< Reset value of RISR register.                             */
21354 
21355 /* TXEIR @Bit 0 : Transmit FIFO Empty Raw Interrupt Status */
21356   #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Pos (0UL) /*!< Position of TXEIR field.                                            */
21357   #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Pos) /*!< Bit mask of TXEIR field. */
21358   #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Min (0x0UL) /*!< Min enumerator value of TXEIR field.                              */
21359   #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_Max (0x1UL) /*!< Max enumerator value of TXEIR field.                              */
21360   #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21361   #define EXMIF_CORE_SSICADDRESS_RISR_TXEIR_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21362 
21363 /* TXOIR @Bit 1 : Transmit FIFO Overflow Raw Interrupt Status */
21364   #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Pos (1UL) /*!< Position of TXOIR field.                                            */
21365   #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Pos) /*!< Bit mask of TXOIR field. */
21366   #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Min (0x0UL) /*!< Min enumerator value of TXOIR field.                              */
21367   #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_Max (0x1UL) /*!< Max enumerator value of TXOIR field.                              */
21368   #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21369   #define EXMIF_CORE_SSICADDRESS_RISR_TXOIR_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21370 
21371 /* RXUIR @Bit 2 : Receive FIFO Underflow Raw Interrupt Status */
21372   #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Pos (2UL) /*!< Position of RXUIR field.                                            */
21373   #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Pos) /*!< Bit mask of RXUIR field. */
21374   #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Min (0x0UL) /*!< Min enumerator value of RXUIR field.                              */
21375   #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_Max (0x1UL) /*!< Max enumerator value of RXUIR field.                              */
21376   #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21377   #define EXMIF_CORE_SSICADDRESS_RISR_RXUIR_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21378 
21379 /* RXOIR @Bit 3 : Receive FIFO Overflow Raw Interrupt Status */
21380   #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Pos (3UL) /*!< Position of RXOIR field.                                            */
21381   #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Pos) /*!< Bit mask of RXOIR field. */
21382   #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Min (0x0UL) /*!< Min enumerator value of RXOIR field.                              */
21383   #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_Max (0x1UL) /*!< Max enumerator value of RXOIR field.                              */
21384   #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21385   #define EXMIF_CORE_SSICADDRESS_RISR_RXOIR_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21386 
21387 /* RXFIR @Bit 4 : Receive FIFO Full Raw Interrupt Status */
21388   #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Pos (4UL) /*!< Position of RXFIR field.                                            */
21389   #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Pos) /*!< Bit mask of RXFIR field. */
21390   #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Min (0x0UL) /*!< Min enumerator value of RXFIR field.                              */
21391   #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_Max (0x1UL) /*!< Max enumerator value of RXFIR field.                              */
21392   #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21393   #define EXMIF_CORE_SSICADDRESS_RISR_RXFIR_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21394 
21395 /* MSTIR @Bit 5 : Multi-Master Contention Raw Interrupt Status. */
21396   #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Pos (5UL) /*!< Position of MSTIR field.                                            */
21397   #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Pos) /*!< Bit mask of MSTIR field. */
21398   #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Min (0x0UL) /*!< Min enumerator value of MSTIR field.                              */
21399   #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_Max (0x1UL) /*!< Max enumerator value of MSTIR field.                              */
21400   #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21401   #define EXMIF_CORE_SSICADDRESS_RISR_MSTIR_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21402 
21403 /* XRXOIR @Bit 6 : XIP Receive FIFO Overflow Raw Interrupt Status */
21404   #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Pos (6UL) /*!< Position of XRXOIR field.                                          */
21405   #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Pos) /*!< Bit mask of XRXOIR
21406                                                                             field.*/
21407   #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Min (0x0UL) /*!< Min enumerator value of XRXOIR field.                            */
21408   #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_Max (0x1UL) /*!< Max enumerator value of XRXOIR field.                            */
21409   #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_INACTIVE (0x0UL) /*!< (unspecified)                                               */
21410   #define EXMIF_CORE_SSICADDRESS_RISR_XRXOIR_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
21411 
21412 /* TXUIR @Bit 7 : Transmit FIFO Underflow Interrupt Raw Status */
21413   #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Pos (7UL) /*!< Position of TXUIR field.                                            */
21414   #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Pos) /*!< Bit mask of TXUIR field. */
21415   #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Min (0x0UL) /*!< Min enumerator value of TXUIR field.                              */
21416   #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_Max (0x1UL) /*!< Max enumerator value of TXUIR field.                              */
21417   #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21418   #define EXMIF_CORE_SSICADDRESS_RISR_TXUIR_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21419 
21420 /* AXIER @Bit 8 : AXI Error Interrupt Raw Status */
21421   #define EXMIF_CORE_SSICADDRESS_RISR_AXIER_Pos (8UL) /*!< Position of AXIER field.                                            */
21422   #define EXMIF_CORE_SSICADDRESS_RISR_AXIER_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_AXIER_Pos) /*!< Bit mask of AXIER field. */
21423   #define EXMIF_CORE_SSICADDRESS_RISR_AXIER_Min (0x0UL) /*!< Min enumerator value of AXIER field.                              */
21424   #define EXMIF_CORE_SSICADDRESS_RISR_AXIER_Max (0x1UL) /*!< Max enumerator value of AXIER field.                              */
21425   #define EXMIF_CORE_SSICADDRESS_RISR_AXIER_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21426   #define EXMIF_CORE_SSICADDRESS_RISR_AXIER_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21427 
21428 /* RSVD9RISR @Bit 9 : Reserved bits - read as zero */
21429   #define EXMIF_CORE_SSICADDRESS_RISR_RSVD9RISR_Pos (9UL) /*!< Position of RSVD9RISR field.                                    */
21430   #define EXMIF_CORE_SSICADDRESS_RISR_RSVD9RISR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_RSVD9RISR_Pos) /*!< Bit mask of
21431                                                                             RSVD9RISR field.*/
21432 
21433 /* SPITER @Bit 10 : SPI Transmit Error Interrupt status. */
21434   #define EXMIF_CORE_SSICADDRESS_RISR_SPITER_Pos (10UL) /*!< Position of SPITER field.                                         */
21435   #define EXMIF_CORE_SSICADDRESS_RISR_SPITER_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_SPITER_Pos) /*!< Bit mask of SPITER
21436                                                                             field.*/
21437   #define EXMIF_CORE_SSICADDRESS_RISR_SPITER_Min (0x0UL) /*!< Min enumerator value of SPITER field.                            */
21438   #define EXMIF_CORE_SSICADDRESS_RISR_SPITER_Max (0x1UL) /*!< Max enumerator value of SPITER field.                            */
21439   #define EXMIF_CORE_SSICADDRESS_RISR_SPITER_INACTIVE (0x0UL) /*!< (unspecified)                                               */
21440   #define EXMIF_CORE_SSICADDRESS_RISR_SPITER_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
21441 
21442 /* DONER @Bit 11 : SSI Done Interrupt Raw Status */
21443   #define EXMIF_CORE_SSICADDRESS_RISR_DONER_Pos (11UL) /*!< Position of DONER field.                                           */
21444   #define EXMIF_CORE_SSICADDRESS_RISR_DONER_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RISR_DONER_Pos) /*!< Bit mask of DONER field. */
21445   #define EXMIF_CORE_SSICADDRESS_RISR_DONER_Min (0x0UL) /*!< Min enumerator value of DONER field.                              */
21446   #define EXMIF_CORE_SSICADDRESS_RISR_DONER_Max (0x1UL) /*!< Max enumerator value of DONER field.                              */
21447   #define EXMIF_CORE_SSICADDRESS_RISR_DONER_INACTIVE (0x0UL) /*!< (unspecified)                                                */
21448   #define EXMIF_CORE_SSICADDRESS_RISR_DONER_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
21449 
21450 /* RSVD1232RISR @Bits 12..31 : Reserved bits - read as zero */
21451   #define EXMIF_CORE_SSICADDRESS_RISR_RSVD1232RISR_Pos (12UL) /*!< Position of RSVD1232RISR field.                             */
21452   #define EXMIF_CORE_SSICADDRESS_RISR_RSVD1232RISR_Msk (0xFFFFFUL << EXMIF_CORE_SSICADDRESS_RISR_RSVD1232RISR_Pos) /*!< Bit mask
21453                                                                             of RSVD1232RISR field.*/
21454 
21455 
21456 /* EXMIF_CORE_SSICADDRESS_TXEICR: Transmit FIFO Error Interrupt Clear Register */
21457   #define EXMIF_CORE_SSICADDRESS_TXEICR_ResetValue (0x00000000UL) /*!< Reset value of TXEICR register.                         */
21458 
21459 /* TXEICR @Bit 0 : Clear Transmit FIFO Overflow/Underflow Interrupt. */
21460   #define EXMIF_CORE_SSICADDRESS_TXEICR_TXEICR_Pos (0UL) /*!< Position of TXEICR field.                                        */
21461   #define EXMIF_CORE_SSICADDRESS_TXEICR_TXEICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_TXEICR_TXEICR_Pos) /*!< Bit mask of TXEICR
21462                                                                             field.*/
21463 
21464 /* RSVDTXEICR @Bits 1..31 : Reserved bits - read as zero */
21465   #define EXMIF_CORE_SSICADDRESS_TXEICR_RSVDTXEICR_Pos (1UL) /*!< Position of RSVDTXEICR field.                                */
21466   #define EXMIF_CORE_SSICADDRESS_TXEICR_RSVDTXEICR_Msk (0x7FFFFFFFUL << EXMIF_CORE_SSICADDRESS_TXEICR_RSVDTXEICR_Pos) /*!< Bit
21467                                                                             mask of RSVDTXEICR field.*/
21468 
21469 
21470 /* EXMIF_CORE_SSICADDRESS_RXOICR: Receive FIFO Overflow Interrupt Clear Register */
21471   #define EXMIF_CORE_SSICADDRESS_RXOICR_ResetValue (0x00000000UL) /*!< Reset value of RXOICR register.                         */
21472 
21473 /* RXOICR @Bit 0 : Clear Receive FIFO Overflow Interrupt. */
21474   #define EXMIF_CORE_SSICADDRESS_RXOICR_RXOICR_Pos (0UL) /*!< Position of RXOICR field.                                        */
21475   #define EXMIF_CORE_SSICADDRESS_RXOICR_RXOICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RXOICR_RXOICR_Pos) /*!< Bit mask of RXOICR
21476                                                                             field.*/
21477 
21478 /* RSVDRXOICR @Bits 1..31 : Reserved bits - read as zero */
21479   #define EXMIF_CORE_SSICADDRESS_RXOICR_RSVDRXOICR_Pos (1UL) /*!< Position of RSVDRXOICR field.                                */
21480   #define EXMIF_CORE_SSICADDRESS_RXOICR_RSVDRXOICR_Msk (0x7FFFFFFFUL << EXMIF_CORE_SSICADDRESS_RXOICR_RSVDRXOICR_Pos) /*!< Bit
21481                                                                             mask of RSVDRXOICR field.*/
21482 
21483 
21484 /* EXMIF_CORE_SSICADDRESS_RXUICR: Receive FIFO Underflow Interrupt Clear Register */
21485   #define EXMIF_CORE_SSICADDRESS_RXUICR_ResetValue (0x00000000UL) /*!< Reset value of RXUICR register.                         */
21486 
21487 /* RXUICR @Bit 0 : Clear Receive FIFO Underflow Interrupt. */
21488   #define EXMIF_CORE_SSICADDRESS_RXUICR_RXUICR_Pos (0UL) /*!< Position of RXUICR field.                                        */
21489   #define EXMIF_CORE_SSICADDRESS_RXUICR_RXUICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RXUICR_RXUICR_Pos) /*!< Bit mask of RXUICR
21490                                                                             field.*/
21491 
21492 /* RSVDRXUICR @Bits 1..31 : Reserved bits - read as zero */
21493   #define EXMIF_CORE_SSICADDRESS_RXUICR_RSVDRXUICR_Pos (1UL) /*!< Position of RSVDRXUICR field.                                */
21494   #define EXMIF_CORE_SSICADDRESS_RXUICR_RSVDRXUICR_Msk (0x7FFFFFFFUL << EXMIF_CORE_SSICADDRESS_RXUICR_RSVDRXUICR_Pos) /*!< Bit
21495                                                                             mask of RSVDRXUICR field.*/
21496 
21497 
21498 /* EXMIF_CORE_SSICADDRESS_MSTICR: Multi-Master Interrupt Clear Register */
21499   #define EXMIF_CORE_SSICADDRESS_MSTICR_ResetValue (0x00000000UL) /*!< Reset value of MSTICR register.                         */
21500 
21501 /* MSTICR @Bit 0 : Clear Multi-Master Contention Interrupt. */
21502   #define EXMIF_CORE_SSICADDRESS_MSTICR_MSTICR_Pos (0UL) /*!< Position of MSTICR field.                                        */
21503   #define EXMIF_CORE_SSICADDRESS_MSTICR_MSTICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_MSTICR_MSTICR_Pos) /*!< Bit mask of MSTICR
21504                                                                             field.*/
21505 
21506 /* RSVDMSTICR @Bits 1..31 : Reserved bits - read as zero */
21507   #define EXMIF_CORE_SSICADDRESS_MSTICR_RSVDMSTICR_Pos (1UL) /*!< Position of RSVDMSTICR field.                                */
21508   #define EXMIF_CORE_SSICADDRESS_MSTICR_RSVDMSTICR_Msk (0x7FFFFFFFUL << EXMIF_CORE_SSICADDRESS_MSTICR_RSVDMSTICR_Pos) /*!< Bit
21509                                                                             mask of RSVDMSTICR field.*/
21510 
21511 
21512 /* EXMIF_CORE_SSICADDRESS_ICR: Interrupt Clear Register */
21513   #define EXMIF_CORE_SSICADDRESS_ICR_ResetValue (0x00000000UL) /*!< Reset value of ICR register.                               */
21514 
21515 /* ICR @Bit 0 : Clear Interrupts. */
21516   #define EXMIF_CORE_SSICADDRESS_ICR_ICR_Pos (0UL)   /*!< Position of ICR field.                                               */
21517   #define EXMIF_CORE_SSICADDRESS_ICR_ICR_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_ICR_ICR_Pos) /*!< Bit mask of ICR field.         */
21518 
21519 /* RSVDICR @Bits 1..31 : Reserved bits - read as zero */
21520   #define EXMIF_CORE_SSICADDRESS_ICR_RSVDICR_Pos (1UL) /*!< Position of RSVDICR field.                                         */
21521   #define EXMIF_CORE_SSICADDRESS_ICR_RSVDICR_Msk (0x7FFFFFFFUL << EXMIF_CORE_SSICADDRESS_ICR_RSVDICR_Pos) /*!< Bit mask of
21522                                                                             RSVDICR field.*/
21523 
21524 
21525 /* EXMIF_CORE_SSICADDRESS_IDR: This register contains the peripherals identification code, which is written into the register at
21526                                 configuration time using coreConsultant. */
21527 
21528   #define EXMIF_CORE_SSICADDRESS_IDR_ResetValue (0x00010003UL) /*!< Reset value of IDR register.                               */
21529 
21530 /* IDCODE @Bits 0..31 : Identification code. */
21531   #define EXMIF_CORE_SSICADDRESS_IDR_IDCODE_Pos (0UL) /*!< Position of IDCODE field.                                           */
21532   #define EXMIF_CORE_SSICADDRESS_IDR_IDCODE_Msk (0xFFFFFFFFUL << EXMIF_CORE_SSICADDRESS_IDR_IDCODE_Pos) /*!< Bit mask of IDCODE
21533                                                                             field.*/
21534 
21535 
21536 /* EXMIF_CORE_SSICADDRESS_SSICVERSIONID: This read-only register stores the specific DWC_ssi component version. */
21537   #define EXMIF_CORE_SSICADDRESS_SSICVERSIONID_ResetValue (0x3130332AUL) /*!< Reset value of SSICVERSIONID register.           */
21538 
21539 /* SSICCOMPVERSION @Bits 0..31 : Contains the hex representation of the Synopsys component version. */
21540   #define EXMIF_CORE_SSICADDRESS_SSICVERSIONID_SSICCOMPVERSION_Pos (0UL) /*!< Position of SSICCOMPVERSION field.               */
21541   #define EXMIF_CORE_SSICADDRESS_SSICVERSIONID_SSICCOMPVERSION_Msk (0xFFFFFFFFUL << EXMIF_CORE_SSICADDRESS_SSICVERSIONID_SSICCOMPVERSION_Pos)
21542                                                                             /*!< Bit mask of SSICCOMPVERSION field.*/
21543 
21544 
21545 /* EXMIF_CORE_SSICADDRESS_DR: The DWC_ssi data register is a 32-bit read/write buffer for the transmit/receive FIFOs. */
21546   #define EXMIF_CORE_SSICADDRESS_DR_MaxCount (36UL)  /*!< Max size of DR[36] array.                                            */
21547   #define EXMIF_CORE_SSICADDRESS_DR_MaxIndex (35UL)  /*!< Max index of DR[36] array.                                           */
21548   #define EXMIF_CORE_SSICADDRESS_DR_MinIndex (0UL)   /*!< Min index of DR[36] array.                                           */
21549   #define EXMIF_CORE_SSICADDRESS_DR_ResetValue (0x00000000UL) /*!< Reset value of DR[36] register.                             */
21550 
21551 /* DR @Bits 0..31 : Data Register. */
21552   #define EXMIF_CORE_SSICADDRESS_DR_DR_Pos (0UL)     /*!< Position of DR field.                                                */
21553   #define EXMIF_CORE_SSICADDRESS_DR_DR_Msk (0xFFFFFFFFUL << EXMIF_CORE_SSICADDRESS_DR_DR_Pos) /*!< Bit mask of DR field.       */
21554 
21555 
21556 /* EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY: This register is only valid when the DWC_ssi is configured with rxd sample delay logic
21557                                           (SSIC_HAS_RX_SAMPLE_DELAY==1). */
21558 
21559   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_ResetValue (0x00000000UL) /*!< Reset value of RXSAMPLEDELAY register.           */
21560 
21561 /* RSD @Bits 0..7 : Receive Data (rxd) Sample Delay. */
21562   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSD_Pos (0UL) /*!< Position of RSD field.                                       */
21563   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSD_Msk (0xFFUL << EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSD_Pos) /*!< Bit mask of
21564                                                                             RSD field.*/
21565 
21566 /* RSVD0RXSAMPLEDLY @Bits 8..15 : Reserved bits - read as zero */
21567   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSVD0RXSAMPLEDLY_Pos (8UL) /*!< Position of RSVD0RXSAMPLEDLY field.             */
21568   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSVD0RXSAMPLEDLY_Msk (0xFFUL << EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSVD0RXSAMPLEDLY_Pos)
21569                                                                             /*!< Bit mask of RSVD0RXSAMPLEDLY field.*/
21570 
21571 /* SE @Bit 16 : Receive Data (rxd) Sampling Edge. */
21572   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_SE_Pos (16UL) /*!< Position of SE field.                                        */
21573   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_SE_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_SE_Pos) /*!< Bit mask of SE
21574                                                                             field.*/
21575 
21576 /* RSVD1RXSAMPLEDLY @Bits 17..31 : Reserved bits - read as zero */
21577   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSVD1RXSAMPLEDLY_Pos (17UL) /*!< Position of RSVD1RXSAMPLEDLY field.            */
21578   #define EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSVD1RXSAMPLEDLY_Msk (0x7FFFUL << EXMIF_CORE_SSICADDRESS_RXSAMPLEDELAY_RSVD1RXSAMPLEDLY_Pos)
21579                                                                             /*!< Bit mask of RSVD1RXSAMPLEDLY field.*/
21580 
21581 
21582 /* EXMIF_CORE_SSICADDRESS_SPICTRLR0: This register is used to control the serial data transfer in enhanced SPI mode of
21583                                       operation. */
21584 
21585   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ResetValue (0x00000A00UL) /*!< Reset value of SPICTRLR0 register.                   */
21586 
21587 /* TRANSTYPE @Bits 0..1 : Address and instruction transfer format. */
21588   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Pos (0UL) /*!< Position of TRANSTYPE field.                               */
21589   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Pos) /*!< Bit mask
21590                                                                             of TRANSTYPE field.*/
21591   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Min (0x0UL) /*!< Min enumerator value of TRANSTYPE field.                 */
21592   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_Max (0x3UL) /*!< Max enumerator value of TRANSTYPE field.                 */
21593   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_TT0 (0x0UL) /*!< (unspecified)                                            */
21594   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_TT1 (0x1UL) /*!< (unspecified)                                            */
21595   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_TT2 (0x2UL) /*!< (unspecified)                                            */
21596   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_TRANSTYPE_TT3 (0x3UL) /*!< (unspecified)                                            */
21597 
21598 /* ADDRL @Bits 2..5 : This bit defines Length of Address to be transmitted. */
21599   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Pos (2UL) /*!< Position of ADDRL field.                                       */
21600   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Msk (0xFUL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Pos) /*!< Bit mask of
21601                                                                             ADDRL field.*/
21602   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Min (0x0UL) /*!< Min enumerator value of ADDRL field.                         */
21603   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_Max (0xFUL) /*!< Max enumerator value of ADDRL field.                         */
21604   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L0 (0x0UL) /*!< (unspecified)                                            */
21605   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L4 (0x1UL) /*!< (unspecified)                                            */
21606   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L8 (0x2UL) /*!< (unspecified)                                            */
21607   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L12 (0x3UL) /*!< (unspecified)                                           */
21608   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L16 (0x4UL) /*!< (unspecified)                                           */
21609   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L20 (0x5UL) /*!< (unspecified)                                           */
21610   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L24 (0x6UL) /*!< (unspecified)                                           */
21611   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L28 (0x7UL) /*!< (unspecified)                                           */
21612   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L32 (0x8UL) /*!< (unspecified)                                           */
21613   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L36 (0x9UL) /*!< (unspecified)                                           */
21614   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L40 (0xAUL) /*!< (unspecified)                                           */
21615   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L44 (0xBUL) /*!< (unspecified)                                           */
21616   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L48 (0xCUL) /*!< (unspecified)                                           */
21617   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L52 (0xDUL) /*!< (unspecified)                                           */
21618   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L56 (0xEUL) /*!< (unspecified)                                           */
21619   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_ADDRL_ADDR_L60 (0xFUL) /*!< (unspecified)                                           */
21620 
21621 /* RSVDSPICTRLR06 @Bit 6 : Reserved bits - read as zero */
21622   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR06_Pos (6UL) /*!< Position of RSVDSPICTRLR06 field.                     */
21623   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR06_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR06_Pos)
21624                                                                             /*!< Bit mask of RSVDSPICTRLR06 field.*/
21625 
21626 /* XIPMDBITEN @Bit 7 : Mode bits enable in XIP mode. */
21627   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMDBITEN_Pos (7UL) /*!< Position of XIPMDBITEN field.                             */
21628   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMDBITEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMDBITEN_Pos) /*!< Bit
21629                                                                             mask of XIPMDBITEN field.*/
21630 
21631 /* INSTL @Bits 8..9 : Dual/Quad/Octal mode instruction length in bits. */
21632   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Pos (8UL) /*!< Position of INSTL field.                                       */
21633   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Pos) /*!< Bit mask of
21634                                                                             INSTL field.*/
21635   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Min (0x0UL) /*!< Min enumerator value of INSTL field.                         */
21636   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_Max (0x3UL) /*!< Max enumerator value of INSTL field.                         */
21637   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_INST_L0 (0x0UL) /*!< (unspecified)                                            */
21638   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_INST_L4 (0x1UL) /*!< (unspecified)                                            */
21639   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_INST_L8 (0x2UL) /*!< (unspecified)                                            */
21640   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTL_INST_L16 (0x3UL) /*!< (unspecified)                                           */
21641 
21642 /* RSVDSPICTRLR010 @Bit 10 : Reserved bits - read as zero */
21643   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR010_Pos (10UL) /*!< Position of RSVDSPICTRLR010 field.                  */
21644   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR010_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR010_Pos)
21645                                                                             /*!< Bit mask of RSVDSPICTRLR010 field.*/
21646 
21647 /* WAITCYCLES @Bits 11..15 : Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. */
21648   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_WAITCYCLES_Pos (11UL) /*!< Position of WAITCYCLES field.                            */
21649   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_WAITCYCLES_Msk (0x1FUL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_WAITCYCLES_Pos) /*!< Bit
21650                                                                             mask of WAITCYCLES field.*/
21651 
21652 /* SPIDDREN @Bit 16 : SPI DDR Enable bit. */
21653   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDDREN_Pos (16UL) /*!< Position of SPIDDREN field.                                */
21654   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDDREN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDDREN_Pos) /*!< Bit mask
21655                                                                             of SPIDDREN field.*/
21656 
21657 /* INSTDDREN @Bit 17 : Instruction DDR Enable bit. */
21658   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTDDREN_Pos (17UL) /*!< Position of INSTDDREN field.                              */
21659   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTDDREN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_INSTDDREN_Pos) /*!< Bit mask
21660                                                                             of INSTDDREN field.*/
21661 
21662 /* SPIRXDSEN @Bit 18 : Read data strobe enable bit. */
21663   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSEN_Pos (18UL) /*!< Position of SPIRXDSEN field.                              */
21664   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSEN_Pos) /*!< Bit mask
21665                                                                             of SPIRXDSEN field.*/
21666 
21667 /* XIPDFSHC @Bit 19 : Fix DFS for XIP transfers. */
21668   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPDFSHC_Pos (19UL) /*!< Position of XIPDFSHC field.                                */
21669   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPDFSHC_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPDFSHC_Pos) /*!< Bit mask
21670                                                                             of XIPDFSHC field.*/
21671 
21672 /* XIPINSTEN @Bit 20 : XIP instruction enable bit. */
21673   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPINSTEN_Pos (20UL) /*!< Position of XIPINSTEN field.                              */
21674   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPINSTEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPINSTEN_Pos) /*!< Bit mask
21675                                                                             of XIPINSTEN field.*/
21676 
21677 /* SSICXIPCONTXFEREN @Bit 21 : Enable continuous transfer in XIP mode. */
21678   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SSICXIPCONTXFEREN_Pos (21UL) /*!< Position of SSICXIPCONTXFEREN field.              */
21679   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SSICXIPCONTXFEREN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SSICXIPCONTXFEREN_Pos)
21680                                                                             /*!< Bit mask of SSICXIPCONTXFEREN field.*/
21681 
21682 /* RSVDSPICTRLR02223 @Bits 22..23 : Reserved bits - read as zero */
21683   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR02223_Pos (22UL) /*!< Position of RSVDSPICTRLR02223 field.              */
21684   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR02223_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR02223_Pos)
21685                                                                             /*!< Bit mask of RSVDSPICTRLR02223 field.*/
21686 
21687 /* SPIDMEN @Bit 24 : SPI data mask enable bit. */
21688   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDMEN_Pos (24UL) /*!< Position of SPIDMEN field.                                  */
21689   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDMEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIDMEN_Pos) /*!< Bit mask of
21690                                                                             SPIDMEN field.*/
21691 
21692 /* SPIRXDSSIGEN @Bit 25 : Enable rxds signaling during address and command phase of Hyperbus transfer. */
21693   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSSIGEN_Pos (25UL) /*!< Position of SPIRXDSSIGEN field.                        */
21694   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSSIGEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_SPIRXDSSIGEN_Pos) /*!<
21695                                                                             Bit mask of SPIRXDSSIGEN field.*/
21696 
21697 /* XIPMBL @Bits 26..27 : XIP Mode bits length. */
21698   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Pos (26UL) /*!< Position of XIPMBL field.                                    */
21699   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Msk (0x3UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Pos) /*!< Bit mask of
21700                                                                             XIPMBL field.*/
21701   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Min (0x0UL) /*!< Min enumerator value of XIPMBL field.                       */
21702   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_Max (0x3UL) /*!< Max enumerator value of XIPMBL field.                       */
21703   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_MBL_2 (0x0UL) /*!< (unspecified)                                             */
21704   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_MBL_4 (0x1UL) /*!< (unspecified)                                             */
21705   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_MBL_8 (0x2UL) /*!< (unspecified)                                             */
21706   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPMBL_MBL_16 (0x3UL) /*!< (unspecified)                                            */
21707 
21708 /* RSVDSPICTRLR028 @Bit 28 : Reserved bits - read as zero */
21709   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR028_Pos (28UL) /*!< Position of RSVDSPICTRLR028 field.                  */
21710   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR028_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR028_Pos)
21711                                                                             /*!< Bit mask of RSVDSPICTRLR028 field.*/
21712 
21713 /* XIPPREFETCHEN @Bit 29 : Enables XIP pre-fetch functionality in DWC_ssi. */
21714   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPPREFETCHEN_Pos (29UL) /*!< Position of XIPPREFETCHEN field.                      */
21715   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPPREFETCHEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_XIPPREFETCHEN_Pos) /*!<
21716                                                                             Bit mask of XIPPREFETCHEN field.*/
21717 
21718 /* CLKSTRETCHEN @Bit 30 : Enables clock stretching capability in SPI transfers. */
21719   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_CLKSTRETCHEN_Pos (30UL) /*!< Position of CLKSTRETCHEN field.                        */
21720   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_CLKSTRETCHEN_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_CLKSTRETCHEN_Pos) /*!<
21721                                                                             Bit mask of CLKSTRETCHEN field.*/
21722 
21723 /* RSVDSPICTRLR0 @Bit 31 : Reserved bits - read as zero */
21724   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR0_Pos (31UL) /*!< Position of RSVDSPICTRLR0 field.                      */
21725   #define EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR0_Msk (0x1UL << EXMIF_CORE_SSICADDRESS_SPICTRLR0_RSVDSPICTRLR0_Pos) /*!<
21726                                                                             Bit mask of RSVDSPICTRLR0 field.*/
21727 
21728 
21729 /* EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE: This Register is valid only when SSIC_HAS_DDR is equal to 1. */
21730   #define EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_ResetValue (0x00000000UL) /*!< Reset value of DDRDRIVEEDGE register.             */
21731 
21732 /* TDE @Bits 0..7 : TXD Drive edge register which decided the driving edge of transmit data. */
21733   #define EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_TDE_Pos (0UL) /*!< Position of TDE field.                                        */
21734   #define EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_TDE_Msk (0xFFUL << EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_TDE_Pos) /*!< Bit mask of
21735                                                                             TDE field.*/
21736 
21737 /* RSVDDDRDRIVEEDGE @Bits 8..31 : Reserved bits - read as zero */
21738   #define EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_RSVDDDRDRIVEEDGE_Pos (8UL) /*!< Position of RSVDDDRDRIVEEDGE field.              */
21739   #define EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_RSVDDDRDRIVEEDGE_Msk (0xFFFFFFUL << EXMIF_CORE_SSICADDRESS_DDRDRIVEEDGE_RSVDDDRDRIVEEDGE_Pos)
21740                                                                             /*!< Bit mask of RSVDDDRDRIVEEDGE field.*/
21741 
21742 
21743 /* EXMIF_CORE_SSICADDRESS_XIPMODEBITS: This register carries the mode bits which are sent in the XIP mode of operation after
21744                                         address phase. */
21745 
21746   #define EXMIF_CORE_SSICADDRESS_XIPMODEBITS_ResetValue (0x00000000UL) /*!< Reset value of XIPMODEBITS register.               */
21747 
21748 /* XIPMDBITS @Bits 0..15 : XIP mode bits to be sent after address phase of XIP transfer. */
21749   #define EXMIF_CORE_SSICADDRESS_XIPMODEBITS_XIPMDBITS_Pos (0UL) /*!< Position of XIPMDBITS field.                             */
21750   #define EXMIF_CORE_SSICADDRESS_XIPMODEBITS_XIPMDBITS_Msk (0xFFFFUL << EXMIF_CORE_SSICADDRESS_XIPMODEBITS_XIPMDBITS_Pos) /*!<
21751                                                                             Bit mask of XIPMDBITS field.*/
21752 
21753 /* RSVDXIPMDBITS @Bits 16..31 : Reserved bits - read as zero */
21754   #define EXMIF_CORE_SSICADDRESS_XIPMODEBITS_RSVDXIPMDBITS_Pos (16UL) /*!< Position of RSVDXIPMDBITS field.                    */
21755   #define EXMIF_CORE_SSICADDRESS_XIPMODEBITS_RSVDXIPMDBITS_Msk (0xFFFFUL << EXMIF_CORE_SSICADDRESS_XIPMODEBITS_RSVDXIPMDBITS_Pos)
21756                                                                             /*!< Bit mask of RSVDXIPMDBITS field.*/
21757 
21758 
21759 
21760 /* ============================================ Struct EXMIF_CORE_SSICXIPADDRESS ============================================= */
21761 /**
21762   * @brief SSICXIPADDRESS [EXMIF_CORE_SSICXIPADDRESS] (unspecified)
21763   */
21764 typedef struct {
21765   __IOM uint32_t  XIPINCRINST;                       /*!< (@ 0x00000000) This Register is valid only when SSIC_XIP_EN is equal
21766                                                                          to 1.*/
21767   __IOM uint32_t  XIPWRAPINST;                       /*!< (@ 0x00000004) This Register is valid only when SSIC_XIP_EN is equal
21768                                                                          to 1.*/
21769   __IOM uint32_t  XIPCTRL;                           /*!< (@ 0x00000008) This Register is valid only when SSIC_CONCURRENT_XIP_EN
21770                                                                          is equal to 1.*/
21771   __IM  uint32_t  RESERVED;
21772   __IOM uint32_t  XRXOICR;                           /*!< (@ 0x00000010) XIP Receive FIFO Overflow Interrupt Clear Register    */
21773   __IM  uint32_t  RESERVED1[11];
21774   __IOM uint32_t  XIPWRITEINCRINST;                  /*!< (@ 0x00000040) This Register is valid only when both
21775                                                                          SSIC_XIP_WRITE_REG_EN is set to 1.*/
21776   __IOM uint32_t  XIPWRITEWRAPINST;                  /*!< (@ 0x00000044) This Register is valid only when both
21777                                                                          SSIC_XIP_WRITE_REG_EN is set to 1.*/
21778   __IOM uint32_t  XIPWRITECTRL;                      /*!< (@ 0x00000048) This Register is valid only when SSIC_XIP_WRITE_REG_EN
21779                                                                          is equal to 1.*/
21780 } NRF_EXMIF_CORE_SSICXIPADDRESS_Type;                /*!< Size = 76 (0x04C)                                                    */
21781 
21782 /* EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST: This Register is valid only when SSIC_XIP_EN is equal to 1. */
21783   #define EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_ResetValue (0x00000000UL) /*!< Reset value of XIPINCRINST register.            */
21784 
21785 /* INCRINST @Bits 0..15 : XIP INCR transfer opcode. */
21786   #define EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_INCRINST_Pos (0UL) /*!< Position of INCRINST field.                            */
21787   #define EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_INCRINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_INCRINST_Pos)
21788                                                                             /*!< Bit mask of INCRINST field.*/
21789 
21790 /* RSVDINCRINST @Bits 16..31 : Reserved bits - read as zero */
21791   #define EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_RSVDINCRINST_Pos (16UL) /*!< Position of RSVDINCRINST field.                   */
21792   #define EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_RSVDINCRINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPINCRINST_RSVDINCRINST_Pos)
21793                                                                             /*!< Bit mask of RSVDINCRINST field.*/
21794 
21795 
21796 /* EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST: This Register is valid only when SSIC_XIP_EN is equal to 1. */
21797   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_ResetValue (0x00000000UL) /*!< Reset value of XIPWRAPINST register.            */
21798 
21799 /* WRAPINST @Bits 0..15 : XIP WRAP transfer opcode. */
21800   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_WRAPINST_Pos (0UL) /*!< Position of WRAPINST field.                            */
21801   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_WRAPINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_WRAPINST_Pos)
21802                                                                             /*!< Bit mask of WRAPINST field.*/
21803 
21804 /* RSVDWRAPINST @Bits 16..31 : Reserved bits - read as zero */
21805   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_RSVDWRAPINST_Pos (16UL) /*!< Position of RSVDWRAPINST field.                   */
21806   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_RSVDWRAPINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRAPINST_RSVDWRAPINST_Pos)
21807                                                                             /*!< Bit mask of RSVDWRAPINST field.*/
21808 
21809 
21810 /* EXMIF_CORE_SSICXIPADDRESS_XIPCTRL: This Register is valid only when SSIC_CONCURRENT_XIP_EN is equal to 1. */
21811   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ResetValue (0x08000401UL) /*!< Reset value of XIPCTRL register.                    */
21812 
21813 /* FRF @Bits 0..1 : SPI Frame Format */
21814   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Pos (0UL) /*!< Position of FRF field.                                          */
21815   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Pos) /*!< Bit mask of FRF
21816                                                                             field.*/
21817   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Min (0x0UL) /*!< Min enumerator value of FRF field.                            */
21818   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_Max (0x3UL) /*!< Max enumerator value of FRF field.                            */
21819   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_RSVD (0x0UL) /*!< (unspecified)                                                */
21820   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_SPI_DUAL (0x1UL) /*!< (unspecified)                                            */
21821   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_SPI_QUAD (0x2UL) /*!< (unspecified)                                            */
21822   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_FRF_SPI_OCTAL (0x3UL) /*!< (unspecified)                                           */
21823 
21824 /* TRANSTYPE @Bits 2..3 : Address and instruction transfer format. */
21825   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Pos (2UL) /*!< Position of TRANSTYPE field.                              */
21826   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Pos) /*!< Bit
21827                                                                             mask of TRANSTYPE field.*/
21828   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Min (0x0UL) /*!< Min enumerator value of TRANSTYPE field.                */
21829   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_Max (0x3UL) /*!< Max enumerator value of TRANSTYPE field.                */
21830   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_TT0 (0x0UL) /*!< (unspecified)                                           */
21831   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_TT1 (0x1UL) /*!< (unspecified)                                           */
21832   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_TT2 (0x2UL) /*!< (unspecified)                                           */
21833   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_TRANSTYPE_TT3 (0x3UL) /*!< (unspecified)                                           */
21834 
21835 /* ADDRL @Bits 4..7 : This bit defines Length of Address to be transmitted. */
21836   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Pos (4UL) /*!< Position of ADDRL field.                                      */
21837   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Msk (0xFUL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Pos) /*!< Bit mask of
21838                                                                             ADDRL field.*/
21839   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Min (0x0UL) /*!< Min enumerator value of ADDRL field.                        */
21840   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_Max (0xFUL) /*!< Max enumerator value of ADDRL field.                        */
21841   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L0 (0x0UL) /*!< (unspecified)                                           */
21842   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L4 (0x1UL) /*!< (unspecified)                                           */
21843   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L8 (0x2UL) /*!< (unspecified)                                           */
21844   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L12 (0x3UL) /*!< (unspecified)                                          */
21845   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L16 (0x4UL) /*!< (unspecified)                                          */
21846   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L20 (0x5UL) /*!< (unspecified)                                          */
21847   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L24 (0x6UL) /*!< (unspecified)                                          */
21848   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L28 (0x7UL) /*!< (unspecified)                                          */
21849   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L32 (0x8UL) /*!< (unspecified)                                          */
21850   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L36 (0x9UL) /*!< (unspecified)                                          */
21851   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L40 (0xAUL) /*!< (unspecified)                                          */
21852   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L44 (0xBUL) /*!< (unspecified)                                          */
21853   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L48 (0xCUL) /*!< (unspecified)                                          */
21854   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L52 (0xDUL) /*!< (unspecified)                                          */
21855   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L56 (0xEUL) /*!< (unspecified)                                          */
21856   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_ADDRL_ADDR_L60 (0xFUL) /*!< (unspecified)                                          */
21857 
21858 /* RSVDXIPCTRL8 @Bit 8 : Reserved bits - read as zero */
21859   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL8_Pos (8UL) /*!< Position of RSVDXIPCTRL8 field.                        */
21860   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL8_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL8_Pos) /*!<
21861                                                                             Bit mask of RSVDXIPCTRL8 field.*/
21862 
21863 /* INSTL @Bits 9..10 : Dual/Quad/Octal mode instruction length in bits. */
21864   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Pos (9UL) /*!< Position of INSTL field.                                      */
21865   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Pos) /*!< Bit mask of
21866                                                                             INSTL field.*/
21867   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Min (0x0UL) /*!< Min enumerator value of INSTL field.                        */
21868   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_Max (0x3UL) /*!< Max enumerator value of INSTL field.                        */
21869   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_INST_L0 (0x0UL) /*!< (unspecified)                                           */
21870   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_INST_L4 (0x1UL) /*!< (unspecified)                                           */
21871   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_INST_L8 (0x2UL) /*!< (unspecified)                                           */
21872   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTL_INST_L16 (0x3UL) /*!< (unspecified)                                          */
21873 
21874 /* RSVDSPICTRLR011 @Bit 11 : Reserved bits - read as zero */
21875   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDSPICTRLR011_Pos (11UL) /*!< Position of RSVDSPICTRLR011 field.                 */
21876   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDSPICTRLR011_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDSPICTRLR011_Pos)
21877                                                                             /*!< Bit mask of RSVDSPICTRLR011 field.*/
21878 
21879 /* MDBITSEN @Bit 12 : Mode bits enable in XIP mode. */
21880   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_MDBITSEN_Pos (12UL) /*!< Position of MDBITSEN field.                               */
21881   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_MDBITSEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_MDBITSEN_Pos) /*!< Bit mask
21882                                                                             of MDBITSEN field.*/
21883 
21884 /* WAITCYCLES @Bits 13..17 : Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. */
21885   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_WAITCYCLES_Pos (13UL) /*!< Position of WAITCYCLES field.                           */
21886   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_WAITCYCLES_Msk (0x1FUL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_WAITCYCLES_Pos) /*!< Bit
21887                                                                             mask of WAITCYCLES field.*/
21888 
21889 /* DFSHC @Bit 18 : Fix DFS for XIP transfers. */
21890   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DFSHC_Pos (18UL) /*!< Position of DFSHC field.                                     */
21891   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DFSHC_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DFSHC_Pos) /*!< Bit mask of
21892                                                                             DFSHC field.*/
21893 
21894 /* DDREN @Bit 19 : SPI DDR Enable bit. */
21895   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DDREN_Pos (19UL) /*!< Position of DDREN field.                                     */
21896   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DDREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_DDREN_Pos) /*!< Bit mask of
21897                                                                             DDREN field.*/
21898 
21899 /* INSTDDREN @Bit 20 : Instruction DDR Enable bit. */
21900   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTDDREN_Pos (20UL) /*!< Position of INSTDDREN field.                             */
21901   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTDDREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTDDREN_Pos) /*!< Bit
21902                                                                             mask of INSTDDREN field.*/
21903 
21904 /* RXDSEN @Bit 21 : Read data strobe enable bit. */
21905   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSEN_Pos (21UL) /*!< Position of RXDSEN field.                                   */
21906   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSEN_Pos) /*!< Bit mask of
21907                                                                             RXDSEN field.*/
21908 
21909 /* INSTEN @Bit 22 : XIP instruction enable bit. */
21910   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTEN_Pos (22UL) /*!< Position of INSTEN field.                                   */
21911   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_INSTEN_Pos) /*!< Bit mask of
21912                                                                             INSTEN field.*/
21913 
21914 /* CONTXFEREN @Bit 23 : Enable continuous transfer in XIP mode. */
21915   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_CONTXFEREN_Pos (23UL) /*!< Position of CONTXFEREN field.                           */
21916   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_CONTXFEREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_CONTXFEREN_Pos) /*!< Bit
21917                                                                             mask of CONTXFEREN field.*/
21918 
21919 /* XIPHYPERBUSEN @Bit 24 : SPI Hyperbus Frame format enable for XIP transfers. */
21920   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPHYPERBUSEN_Pos (24UL) /*!< Position of XIPHYPERBUSEN field.                     */
21921   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPHYPERBUSEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPHYPERBUSEN_Pos)
21922                                                                             /*!< Bit mask of XIPHYPERBUSEN field.*/
21923 
21924 /* RXDSSIGEN @Bit 25 : Enable rxds signaling during address and command phase of Hyperbus transfer. */
21925   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSSIGEN_Pos (25UL) /*!< Position of RXDSSIGEN field.                             */
21926   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSSIGEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RXDSSIGEN_Pos) /*!< Bit
21927                                                                             mask of RXDSSIGEN field.*/
21928 
21929 /* XIPMBL @Bits 26..27 : XIP Mode bits length. */
21930   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Pos (26UL) /*!< Position of XIPMBL field.                                   */
21931   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Pos) /*!< Bit mask of
21932                                                                             XIPMBL field.*/
21933   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Min (0x0UL) /*!< Min enumerator value of XIPMBL field.                      */
21934   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_Max (0x3UL) /*!< Max enumerator value of XIPMBL field.                      */
21935   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_MBL_2 (0x0UL) /*!< (unspecified)                                            */
21936   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_MBL_4 (0x1UL) /*!< (unspecified)                                            */
21937   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_MBL_8 (0x2UL) /*!< (unspecified)                                            */
21938   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPMBL_MBL_16 (0x3UL) /*!< (unspecified)                                           */
21939 
21940 /* RSVDXIPCTRL28 @Bit 28 : Reserved bits - read as zero */
21941   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL28_Pos (28UL) /*!< Position of RSVDXIPCTRL28 field.                     */
21942   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL28_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL28_Pos)
21943                                                                             /*!< Bit mask of RSVDXIPCTRL28 field.*/
21944 
21945 /* XIPPREFETCHEN @Bit 29 : Enables XIP pre-fetch functionality in DWC_ssi. */
21946   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPPREFETCHEN_Pos (29UL) /*!< Position of XIPPREFETCHEN field.                     */
21947   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPPREFETCHEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_XIPPREFETCHEN_Pos)
21948                                                                             /*!< Bit mask of XIPPREFETCHEN field.*/
21949 
21950 /* RSVDXIPCTRL @Bits 30..31 : Reserved bits - read as zero */
21951   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL_Pos (30UL) /*!< Position of RSVDXIPCTRL field.                         */
21952   #define EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPCTRL_RSVDXIPCTRL_Pos) /*!<
21953                                                                             Bit mask of RSVDXIPCTRL field.*/
21954 
21955 
21956 /* EXMIF_CORE_SSICXIPADDRESS_XRXOICR: XIP Receive FIFO Overflow Interrupt Clear Register */
21957   #define EXMIF_CORE_SSICXIPADDRESS_XRXOICR_ResetValue (0x00000000UL) /*!< Reset value of XRXOICR register.                    */
21958 
21959 /* XRXOICR @Bit 0 : Clear XIP Receive FIFO Overflow Interrupt. */
21960   #define EXMIF_CORE_SSICXIPADDRESS_XRXOICR_XRXOICR_Pos (0UL) /*!< Position of XRXOICR field.                                  */
21961   #define EXMIF_CORE_SSICXIPADDRESS_XRXOICR_XRXOICR_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XRXOICR_XRXOICR_Pos) /*!< Bit mask
21962                                                                             of XRXOICR field.*/
21963 
21964 /* RSVDXRXOICR @Bits 1..31 : Reserved bits - read as zero */
21965   #define EXMIF_CORE_SSICXIPADDRESS_XRXOICR_RSVDXRXOICR_Pos (1UL) /*!< Position of RSVDXRXOICR field.                          */
21966   #define EXMIF_CORE_SSICXIPADDRESS_XRXOICR_RSVDXRXOICR_Msk (0x7FFFFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XRXOICR_RSVDXRXOICR_Pos)
21967                                                                             /*!< Bit mask of RSVDXRXOICR field.*/
21968 
21969 
21970 /* EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST: This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. */
21971   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_ResetValue (0x00000000UL) /*!< Reset value of XIPWRITEINCRINST register.  */
21972 
21973 /* INCRWRITEINST @Bits 0..15 : XIP Write INCR transfer opcode. */
21974   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_INCRWRITEINST_Pos (0UL) /*!< Position of INCRWRITEINST field.             */
21975   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_INCRWRITEINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_INCRWRITEINST_Pos)
21976                                                                             /*!< Bit mask of INCRWRITEINST field.*/
21977 
21978 /* RSVDINCRINST16TO31 @Bits 16..31 : Reserved bits - Read Only */
21979   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_RSVDINCRINST16TO31_Pos (16UL) /*!< Position of RSVDINCRINST16TO31 field.  */
21980   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_RSVDINCRINST16TO31_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITEINCRINST_RSVDINCRINST16TO31_Pos)
21981                                                                             /*!< Bit mask of RSVDINCRINST16TO31 field.*/
21982 
21983 
21984 /* EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST: This Register is valid only when both SSIC_XIP_WRITE_REG_EN is set to 1. */
21985   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_ResetValue (0x00000000UL) /*!< Reset value of XIPWRITEWRAPINST register.  */
21986 
21987 /* WRAPWRITEINST @Bits 0..15 : XIP Write WRAP transfer opcode. */
21988   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_WRAPWRITEINST_Pos (0UL) /*!< Position of WRAPWRITEINST field.             */
21989   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_WRAPWRITEINST_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_WRAPWRITEINST_Pos)
21990                                                                             /*!< Bit mask of WRAPWRITEINST field.*/
21991 
21992 /* RSVDWRAPINST16TO31 @Bits 16..31 : Reserved bits - Read Only */
21993   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_RSVDWRAPINST16TO31_Pos (16UL) /*!< Position of RSVDWRAPINST16TO31 field.  */
21994   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_RSVDWRAPINST16TO31_Msk (0xFFFFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITEWRAPINST_RSVDWRAPINST16TO31_Pos)
21995                                                                             /*!< Bit mask of RSVDWRAPINST16TO31 field.*/
21996 
21997 
21998 /* EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL: This Register is valid only when SSIC_XIP_WRITE_REG_EN is equal to 1. */
21999   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_ResetValue (0x00000002UL) /*!< Reset value of XIPWRITECTRL register.          */
22000 
22001 /* WRFRF @Bits 0..1 : SPI Frame Format */
22002   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Pos (0UL) /*!< Position of WRFRF field.                                 */
22003   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Pos) /*!< Bit
22004                                                                             mask of WRFRF field.*/
22005   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Min (0x0UL) /*!< Min enumerator value of WRFRF field.                   */
22006   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_Max (0x3UL) /*!< Max enumerator value of WRFRF field.                   */
22007   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_RSVD (0x0UL) /*!< (unspecified)                                         */
22008   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_SPI_DUAL (0x1UL) /*!< (unspecified)                                     */
22009   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_SPI_QUAD (0x2UL) /*!< (unspecified)                                     */
22010   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRFRF_SPI_OCTAL (0x3UL) /*!< (unspecified)                                    */
22011 
22012 /* WRTRANSTYPE @Bits 2..3 : Address and instruction transfer format. */
22013   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Pos (2UL) /*!< Position of WRTRANSTYPE field.                     */
22014   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Pos)
22015                                                                             /*!< Bit mask of WRTRANSTYPE field.*/
22016   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Min (0x0UL) /*!< Min enumerator value of WRTRANSTYPE field.       */
22017   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_Max (0x3UL) /*!< Max enumerator value of WRTRANSTYPE field.       */
22018   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_TT0 (0x0UL) /*!< (unspecified)                                    */
22019   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_TT1 (0x1UL) /*!< (unspecified)                                    */
22020   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_TT2 (0x2UL) /*!< (unspecified)                                    */
22021   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRTRANSTYPE_TT3 (0x3UL) /*!< (unspecified)                                    */
22022 
22023 /* WRADDRL @Bits 4..7 : This bit defines Length of Address to be transmitted. */
22024   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Pos (4UL) /*!< Position of WRADDRL field.                             */
22025   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Msk (0xFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Pos) /*!<
22026                                                                             Bit mask of WRADDRL field.*/
22027   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Min (0x0UL) /*!< Min enumerator value of WRADDRL field.               */
22028   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_Max (0x8UL) /*!< Max enumerator value of WRADDRL field.               */
22029   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L0 (0x0UL) /*!< (unspecified)                                    */
22030   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L4 (0x1UL) /*!< (unspecified)                                    */
22031   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L8 (0x2UL) /*!< (unspecified)                                    */
22032   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L12 (0x3UL) /*!< (unspecified)                                   */
22033   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L16 (0x4UL) /*!< (unspecified)                                   */
22034   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L20 (0x5UL) /*!< (unspecified)                                   */
22035   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L24 (0x6UL) /*!< (unspecified)                                   */
22036   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L28 (0x7UL) /*!< (unspecified)                                   */
22037   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRADDRL_ADDR_L32 (0x8UL) /*!< (unspecified)                                   */
22038 
22039 /* WRINSTL @Bits 8..9 : Dual/Quad/Octal mode instruction length in bits. */
22040   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Pos (8UL) /*!< Position of WRINSTL field.                             */
22041   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Pos) /*!<
22042                                                                             Bit mask of WRINSTL field.*/
22043   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Min (0x0UL) /*!< Min enumerator value of WRINSTL field.               */
22044   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_Max (0x3UL) /*!< Max enumerator value of WRINSTL field.               */
22045   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_INST_L0 (0x0UL) /*!< (unspecified)                                    */
22046   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_INST_L4 (0x1UL) /*!< (unspecified)                                    */
22047   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_INST_L8 (0x2UL) /*!< (unspecified)                                    */
22048   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTL_INST_L16 (0x3UL) /*!< (unspecified)                                   */
22049 
22050 /* WRSPIDDREN @Bit 10 : SPI DDR Enable bit. */
22051   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRSPIDDREN_Pos (10UL) /*!< Position of WRSPIDDREN field.                      */
22052   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRSPIDDREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRSPIDDREN_Pos)
22053                                                                             /*!< Bit mask of WRSPIDDREN field.*/
22054 
22055 /* WRINSTDDREN @Bit 11 : Instruction DDR Enable bit. */
22056   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTDDREN_Pos (11UL) /*!< Position of WRINSTDDREN field.                    */
22057   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTDDREN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_WRINSTDDREN_Pos)
22058                                                                             /*!< Bit mask of WRINSTDDREN field.*/
22059 
22060 /* XIPWRHYPERBUSEN @Bit 12 : SPI Hyperbus Frame format enable for XIP Write transfers. */
22061   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRHYPERBUSEN_Pos (12UL) /*!< Position of XIPWRHYPERBUSEN field.            */
22062   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRHYPERBUSEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRHYPERBUSEN_Pos)
22063                                                                             /*!< Bit mask of XIPWRHYPERBUSEN field.*/
22064 
22065 /* XIPWRRXDSSIGEN @Bit 13 : Enable rxds signaling during address and command phase of Hyperbus transfer. */
22066   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRRXDSSIGEN_Pos (13UL) /*!< Position of XIPWRRXDSSIGEN field.              */
22067   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRRXDSSIGEN_Msk (0x1UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRRXDSSIGEN_Pos)
22068                                                                             /*!< Bit mask of XIPWRRXDSSIGEN field.*/
22069 
22070 /* RSVDXIPWRITECTRL14TO15 @Bits 14..15 : Reserved bits - Read Only */
22071   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL14TO15_Pos (14UL) /*!< Position of RSVDXIPWRITECTRL14TO15
22072                                                                             field.*/
22073   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL14TO15_Msk (0x3UL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL14TO15_Pos)
22074                                                                             /*!< Bit mask of RSVDXIPWRITECTRL14TO15 field.*/
22075 
22076 /* XIPWRWAITCYCLES @Bits 16..20 : Wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. */
22077   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRWAITCYCLES_Pos (16UL) /*!< Position of XIPWRWAITCYCLES field.            */
22078   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRWAITCYCLES_Msk (0x1FUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_XIPWRWAITCYCLES_Pos)
22079                                                                             /*!< Bit mask of XIPWRWAITCYCLES field.*/
22080 
22081 /* RSVDXIPWRITECTRL21TO31 @Bits 21..31 : Reserved bits - Read Only */
22082   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL21TO31_Pos (21UL) /*!< Position of RSVDXIPWRITECTRL21TO31
22083                                                                             field.*/
22084   #define EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL21TO31_Msk (0x7FFUL << EXMIF_CORE_SSICXIPADDRESS_XIPWRITECTRL_RSVDXIPWRITECTRL21TO31_Pos)
22085                                                                             /*!< Bit mask of RSVDXIPWRITECTRL21TO31 field.*/
22086 
22087 
22088 
22089 /* ==================================================== Struct EXMIF_CORE ==================================================== */
22090 /**
22091   * @brief CORE [EXMIF_CORE] (unspecified)
22092   */
22093 typedef struct {
22094   __IOM NRF_EXMIF_CORE_SSICADDRESS_Type SSICADDRESS; /*!< (@ 0x00000000) (unspecified)                                         */
22095   __IOM NRF_EXMIF_CORE_SSICXIPADDRESS_Type SSICXIPADDRESS; /*!< (@ 0x00000100) (unspecified)                                   */
22096 } NRF_EXMIF_CORE_Type;                               /*!< Size = 332 (0x14C)                                                   */
22097 
22098 /* ====================================================== Struct EXMIF ======================================================= */
22099 /**
22100   * @brief External Memory Interface
22101   */
22102   typedef struct {                                   /*!< EXMIF Structure                                                      */
22103     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start operation.                                      */
22104     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop operation.                                       */
22105     __IM uint32_t RESERVED[62];
22106     __IOM uint32_t EVENTS_CORE;                      /*!< (@ 0x00000100) Event indicating that interrupt triggered at EXMIF
22107                                                                          core*/
22108     __IM uint32_t RESERVED1[127];
22109     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
22110     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
22111     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
22112     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
22113     __IM uint32_t RESERVED2[60];
22114     #if defined(_GNUC_)
22115       #pragma GCC diagnostic push
22116       #pragma GCC diagnostic ignored "-Wpedantic"
22117     #endif
22118     union {
22119       __IOM NRF_EXMIF_EXTCONF1_Type EXTCONF1;        /*!< (@ 0x00000400) Configuration for external memory device 1.           */
22120       struct {
22121         __IM uint32_t RESERVED3[2];
22122         __IOM NRF_EXMIF_EXTCONF2_Type EXTCONF2;      /*!< (@ 0x00000408) Configuration for external memory device 2.           */
22123       };
22124       struct {
22125       __IM uint32_t RESERVED4[5];
22126         __IOM uint32_t LOCKEDACCESS;                 /*!< (@ 0x00000414) Enable or disable locked APB access to serial memory
22127                                                                          controller.*/
22128         __IM uint32_t RESERVED5;
22129         __IOM uint32_t RESET;                        /*!< (@ 0x0000041C) Reset the external memory.                            */
22130       };
22131       __IM uint32_t RESERVED6[9];
22132     };
22133     #if defined(_GNUC_)
22134       #pragma GCC diagnostic pop
22135     #endif
22136     __IM uint32_t RESERVED7[55];
22137     __IOM NRF_EXMIF_CORE_Type CORE;                  /*!< (@ 0x00000500) (unspecified)                                         */
22138   } NRF_EXMIF_Type;                                  /*!< Size = 1612 (0x64C)                                                  */
22139 
22140 /* EXMIF_TASKS_START: Start operation. */
22141   #define EXMIF_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */
22142 
22143 /* TASKS_START @Bit 0 : Start operation. */
22144   #define EXMIF_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
22145   #define EXMIF_TASKS_START_TASKS_START_Msk (0x1UL << EXMIF_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
22146   #define EXMIF_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
22147   #define EXMIF_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
22148   #define EXMIF_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */
22149 
22150 
22151 /* EXMIF_TASKS_STOP: Stop operation. */
22152   #define EXMIF_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */
22153 
22154 /* TASKS_STOP @Bit 0 : Stop operation. */
22155   #define EXMIF_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
22156   #define EXMIF_TASKS_STOP_TASKS_STOP_Msk (0x1UL << EXMIF_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
22157   #define EXMIF_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
22158   #define EXMIF_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
22159   #define EXMIF_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */
22160 
22161 
22162 /* EXMIF_EVENTS_CORE: Event indicating that interrupt triggered at EXMIF core */
22163   #define EXMIF_EVENTS_CORE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CORE register.                                */
22164 
22165 /* EVENTS_CORE @Bit 0 : Event indicating that interrupt triggered at EXMIF core */
22166   #define EXMIF_EVENTS_CORE_EVENTS_CORE_Pos (0UL)    /*!< Position of EVENTS_CORE field.                                       */
22167   #define EXMIF_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << EXMIF_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field.   */
22168   #define EXMIF_EVENTS_CORE_EVENTS_CORE_Min (0x0UL)  /*!< Min enumerator value of EVENTS_CORE field.                           */
22169   #define EXMIF_EVENTS_CORE_EVENTS_CORE_Max (0x1UL)  /*!< Max enumerator value of EVENTS_CORE field.                           */
22170   #define EXMIF_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL) /*!< Event not generated                                          */
22171   #define EXMIF_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL) /*!< Event generated                                                 */
22172 
22173 
22174 /* EXMIF_INTEN: Enable or disable interrupt */
22175   #define EXMIF_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */
22176 
22177 /* CORE @Bit 0 : Enable or disable interrupt for event CORE */
22178   #define EXMIF_INTEN_CORE_Pos (0UL)                 /*!< Position of CORE field.                                              */
22179   #define EXMIF_INTEN_CORE_Msk (0x1UL << EXMIF_INTEN_CORE_Pos) /*!< Bit mask of CORE field.                                    */
22180   #define EXMIF_INTEN_CORE_Min (0x0UL)               /*!< Min enumerator value of CORE field.                                  */
22181   #define EXMIF_INTEN_CORE_Max (0x1UL)               /*!< Max enumerator value of CORE field.                                  */
22182   #define EXMIF_INTEN_CORE_Disabled (0x0UL)          /*!< Disable                                                              */
22183   #define EXMIF_INTEN_CORE_Enabled (0x1UL)           /*!< Enable                                                               */
22184 
22185 
22186 /* EXMIF_INTENSET: Enable interrupt */
22187   #define EXMIF_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */
22188 
22189 /* CORE @Bit 0 : Write '1' to enable interrupt for event CORE */
22190   #define EXMIF_INTENSET_CORE_Pos (0UL)              /*!< Position of CORE field.                                              */
22191   #define EXMIF_INTENSET_CORE_Msk (0x1UL << EXMIF_INTENSET_CORE_Pos) /*!< Bit mask of CORE field.                              */
22192   #define EXMIF_INTENSET_CORE_Min (0x0UL)            /*!< Min enumerator value of CORE field.                                  */
22193   #define EXMIF_INTENSET_CORE_Max (0x1UL)            /*!< Max enumerator value of CORE field.                                  */
22194   #define EXMIF_INTENSET_CORE_Set (0x1UL)            /*!< Enable                                                               */
22195   #define EXMIF_INTENSET_CORE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
22196   #define EXMIF_INTENSET_CORE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
22197 
22198 
22199 /* EXMIF_INTENCLR: Disable interrupt */
22200   #define EXMIF_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */
22201 
22202 /* CORE @Bit 0 : Write '1' to disable interrupt for event CORE */
22203   #define EXMIF_INTENCLR_CORE_Pos (0UL)              /*!< Position of CORE field.                                              */
22204   #define EXMIF_INTENCLR_CORE_Msk (0x1UL << EXMIF_INTENCLR_CORE_Pos) /*!< Bit mask of CORE field.                              */
22205   #define EXMIF_INTENCLR_CORE_Min (0x0UL)            /*!< Min enumerator value of CORE field.                                  */
22206   #define EXMIF_INTENCLR_CORE_Max (0x1UL)            /*!< Max enumerator value of CORE field.                                  */
22207   #define EXMIF_INTENCLR_CORE_Clear (0x1UL)          /*!< Disable                                                              */
22208   #define EXMIF_INTENCLR_CORE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
22209   #define EXMIF_INTENCLR_CORE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
22210 
22211 
22212 /* EXMIF_INTPEND: Pending interrupts */
22213   #define EXMIF_INTPEND_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND register.                                     */
22214 
22215 /* CORE @Bit 0 : Read pending status of interrupt for event CORE */
22216   #define EXMIF_INTPEND_CORE_Pos (0UL)               /*!< Position of CORE field.                                              */
22217   #define EXMIF_INTPEND_CORE_Msk (0x1UL << EXMIF_INTPEND_CORE_Pos) /*!< Bit mask of CORE field.                                */
22218   #define EXMIF_INTPEND_CORE_Min (0x0UL)             /*!< Min enumerator value of CORE field.                                  */
22219   #define EXMIF_INTPEND_CORE_Max (0x1UL)             /*!< Max enumerator value of CORE field.                                  */
22220   #define EXMIF_INTPEND_CORE_NotPending (0x0UL)      /*!< Read: Not pending                                                    */
22221   #define EXMIF_INTPEND_CORE_Pending (0x1UL)         /*!< Read: Pending                                                        */
22222 
22223 
22224 /* EXMIF_LOCKEDACCESS: Enable or disable locked APB access to serial memory controller. */
22225   #define EXMIF_LOCKEDACCESS_ResetValue (0x00000000UL) /*!< Reset value of LOCKEDACCESS register.                              */
22226 
22227 /* ENABLE @Bit 0 : Enable or disable locked APB access to SSI. */
22228   #define EXMIF_LOCKEDACCESS_ENABLE_Pos (0UL)        /*!< Position of ENABLE field.                                            */
22229   #define EXMIF_LOCKEDACCESS_ENABLE_Msk (0x1UL << EXMIF_LOCKEDACCESS_ENABLE_Pos) /*!< Bit mask of ENABLE field.                */
22230   #define EXMIF_LOCKEDACCESS_ENABLE_Min (0x0UL)      /*!< Min enumerator value of ENABLE field.                                */
22231   #define EXMIF_LOCKEDACCESS_ENABLE_Max (0x1UL)      /*!< Max enumerator value of ENABLE field.                                */
22232   #define EXMIF_LOCKEDACCESS_ENABLE_Disabled (0x0UL) /*!< Disable locked APB access.                                           */
22233   #define EXMIF_LOCKEDACCESS_ENABLE_Enabled (0x1UL)  /*!< Enable locked APB access.                                            */
22234 
22235 
22236 /* EXMIF_RESET: Reset the external memory. */
22237   #define EXMIF_RESET_ResetValue (0x00000000UL)      /*!< Reset value of RESET register.                                       */
22238 
22239 /* RESET @Bit 0 : (unspecified) */
22240   #define EXMIF_RESET_RESET_Pos (0UL)                /*!< Position of RESET field.                                             */
22241   #define EXMIF_RESET_RESET_Msk (0x1UL << EXMIF_RESET_RESET_Pos) /*!< Bit mask of RESET field.                                 */
22242   #define EXMIF_RESET_RESET_Min (0x0UL)              /*!< Min enumerator value of RESET field.                                 */
22243   #define EXMIF_RESET_RESET_Max (0x1UL)              /*!< Max enumerator value of RESET field.                                 */
22244   #define EXMIF_RESET_RESET_Clear (0x0UL)            /*!< Reset is cleared.                                                    */
22245   #define EXMIF_RESET_RESET_Set (0x1UL)              /*!< Reset is set.                                                        */
22246 
22247 
22248 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
22249 
22250 /* =========================================================================================================================== */
22251 /* ================                                           FICR                                           ================ */
22252 /* =========================================================================================================================== */
22253 
22254 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
22255 
22256 /* ===================================================== Struct FICR_BLE ===================================================== */
22257 /**
22258   * @brief BLE [FICR_BLE] (unspecified)
22259   */
22260 typedef struct {
22261   __IM  uint32_t  ADDRTYPE;                          /*!< (@ 0x00000000) Device address type.                                  */
22262   __IM  uint32_t  ADDR[2];                           /*!< (@ 0x00000004) 48 bit device address.                                */
22263   __IM  uint32_t  ER[4];                             /*!< (@ 0x0000000C) Encryption Root.                                      */
22264   __IM  uint32_t  IR[4];                             /*!< (@ 0x0000001C) Identity Root.                                        */
22265 } NRF_FICR_BLE_Type;                                 /*!< Size = 44 (0x02C)                                                    */
22266 
22267 /* FICR_BLE_ADDRTYPE: Device address type. */
22268   #define FICR_BLE_ADDRTYPE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ADDRTYPE register.                                   */
22269 
22270 /* TYPE @Bit 0 : Device address type. */
22271   #define FICR_BLE_ADDRTYPE_TYPE_Pos (0UL)           /*!< Position of TYPE field.                                              */
22272   #define FICR_BLE_ADDRTYPE_TYPE_Msk (0x1UL << FICR_BLE_ADDRTYPE_TYPE_Pos) /*!< Bit mask of TYPE field.                        */
22273   #define FICR_BLE_ADDRTYPE_TYPE_Min (0x0UL)         /*!< Min enumerator value of TYPE field.                                  */
22274   #define FICR_BLE_ADDRTYPE_TYPE_Max (0x1UL)         /*!< Max enumerator value of TYPE field.                                  */
22275   #define FICR_BLE_ADDRTYPE_TYPE_Public (0x0UL)      /*!< Public address.                                                      */
22276   #define FICR_BLE_ADDRTYPE_TYPE_Random (0x1UL)      /*!< Random address.                                                      */
22277 
22278 
22279 /* FICR_BLE_ADDR: 48 bit device address. */
22280   #define FICR_BLE_ADDR_MaxCount (2UL)               /*!< Max size of ADDR[2] array.                                           */
22281   #define FICR_BLE_ADDR_MaxIndex (1UL)               /*!< Max index of ADDR[2] array.                                          */
22282   #define FICR_BLE_ADDR_MinIndex (0UL)               /*!< Min index of ADDR[2] array.                                          */
22283   #define FICR_BLE_ADDR_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of ADDR[2] register.                                     */
22284 
22285 /* ADDR @Bits 0..31 : Device address [n]. */
22286   #define FICR_BLE_ADDR_ADDR_Pos (0UL)               /*!< Position of ADDR field.                                              */
22287   #define FICR_BLE_ADDR_ADDR_Msk (0xFFFFFFFFUL << FICR_BLE_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field.                         */
22288 
22289 
22290 /* FICR_BLE_ER: Encryption Root. */
22291   #define FICR_BLE_ER_MaxCount (4UL)                 /*!< Max size of ER[4] array.                                             */
22292   #define FICR_BLE_ER_MaxIndex (3UL)                 /*!< Max index of ER[4] array.                                            */
22293   #define FICR_BLE_ER_MinIndex (0UL)                 /*!< Min index of ER[4] array.                                            */
22294   #define FICR_BLE_ER_ResetValue (0xFFFFFFFFUL)      /*!< Reset value of ER[4] register.                                       */
22295 
22296 /* ER @Bits 0..31 : Encryption root word [n]. */
22297   #define FICR_BLE_ER_ER_Pos (0UL)                   /*!< Position of ER field.                                                */
22298   #define FICR_BLE_ER_ER_Msk (0xFFFFFFFFUL << FICR_BLE_ER_ER_Pos) /*!< Bit mask of ER field.                                   */
22299 
22300 
22301 /* FICR_BLE_IR: Identity Root. */
22302   #define FICR_BLE_IR_MaxCount (4UL)                 /*!< Max size of IR[4] array.                                             */
22303   #define FICR_BLE_IR_MaxIndex (3UL)                 /*!< Max index of IR[4] array.                                            */
22304   #define FICR_BLE_IR_MinIndex (0UL)                 /*!< Min index of IR[4] array.                                            */
22305   #define FICR_BLE_IR_ResetValue (0xFFFFFFFFUL)      /*!< Reset value of IR[4] register.                                       */
22306 
22307 /* IR @Bits 0..31 : Identity root word [n]. */
22308   #define FICR_BLE_IR_IR_Pos (0UL)                   /*!< Position of IR field.                                                */
22309   #define FICR_BLE_IR_IR_Msk (0xFFFFFFFFUL << FICR_BLE_IR_IR_Pos) /*!< Bit mask of IR field.                                   */
22310 
22311 
22312 
22313 /* ===================================================== Struct FICR_NFC ===================================================== */
22314 /**
22315   * @brief NFC [FICR_NFC] (unspecified)
22316   */
22317 typedef struct {
22318   __IM  uint32_t  TAGHEADER[4];                      /*!< (@ 0x00000000) Default header for NFC Tag.                           */
22319 } NRF_FICR_NFC_Type;                                 /*!< Size = 16 (0x010)                                                    */
22320 
22321 /* FICR_NFC_TAGHEADER: Default header for NFC Tag. */
22322   #define FICR_NFC_TAGHEADER_MaxCount (4UL)          /*!< Max size of TAGHEADER[4] array.                                      */
22323   #define FICR_NFC_TAGHEADER_MaxIndex (3UL)          /*!< Max index of TAGHEADER[4] array.                                     */
22324   #define FICR_NFC_TAGHEADER_MinIndex (0UL)          /*!< Min index of TAGHEADER[4] array.                                     */
22325   #define FICR_NFC_TAGHEADER_ResetValue (0xFFFFFF5FUL) /*!< Reset value of TAGHEADER[4] register.                              */
22326 
22327 /* UD0 @Bits 0..7 : Unique identifier byte 0 */
22328   #define FICR_NFC_TAGHEADER_UD0_Pos (0UL)           /*!< Position of UD0 field.                                               */
22329   #define FICR_NFC_TAGHEADER_UD0_Msk (0xFFUL << FICR_NFC_TAGHEADER_UD0_Pos) /*!< Bit mask of UD0 field.                        */
22330 
22331 /* UD1 @Bits 8..15 : Unique identifier byte 1 */
22332   #define FICR_NFC_TAGHEADER_UD1_Pos (8UL)           /*!< Position of UD1 field.                                               */
22333   #define FICR_NFC_TAGHEADER_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER_UD1_Pos) /*!< Bit mask of UD1 field.                        */
22334 
22335 /* UD2 @Bits 16..23 : Unique identifier byte 2 */
22336   #define FICR_NFC_TAGHEADER_UD2_Pos (16UL)          /*!< Position of UD2 field.                                               */
22337   #define FICR_NFC_TAGHEADER_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER_UD2_Pos) /*!< Bit mask of UD2 field.                        */
22338 
22339 /* UD3 @Bits 24..31 : Unique identifier byte 3 */
22340   #define FICR_NFC_TAGHEADER_UD3_Pos (24UL)          /*!< Position of UD3 field.                                               */
22341   #define FICR_NFC_TAGHEADER_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER_UD3_Pos) /*!< Bit mask of UD3 field.                        */
22342 
22343 
22344 
22345 /* ==================================================== Struct FICR_INFO ===================================================== */
22346 /**
22347   * @brief INFO [FICR_INFO] Device info
22348   */
22349 typedef struct {
22350   __IM  uint32_t  CONFIGID;                          /*!< (@ 0x00000000) Configuration identifier                              */
22351   __IM  uint32_t  PART;                              /*!< (@ 0x00000004) Part code                                             */
22352   __IM  uint32_t  VARIANT;                           /*!< (@ 0x00000008) Part Variant, Hardware version and Production
22353                                                                          configuration*/
22354   __IM  uint32_t  PACKAGE;                           /*!< (@ 0x0000000C) Package option                                        */
22355   __IM  uint32_t  RAM;                               /*!< (@ 0x00000010) RAM variant                                           */
22356   __IM  uint32_t  MRAM;                              /*!< (@ 0x00000014) MRAM variant                                          */
22357   __IM  uint32_t  CODEPAGESIZE;                      /*!< (@ 0x00000018) Code memory page size in bytes                        */
22358   __IM  uint32_t  CODESIZE;                          /*!< (@ 0x0000001C) Code memory size                                      */
22359   __IM  uint32_t  DEVICETYPE;                        /*!< (@ 0x00000020) Device type                                           */
22360 } NRF_FICR_INFO_Type;                                /*!< Size = 36 (0x024)                                                    */
22361 
22362 /* FICR_INFO_CONFIGID: Configuration identifier */
22363   #define FICR_INFO_CONFIGID_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIGID register.                                  */
22364 
22365 /* HWID @Bits 0..15 : Identification number for the HW */
22366   #define FICR_INFO_CONFIGID_HWID_Pos (0UL)          /*!< Position of HWID field.                                              */
22367   #define FICR_INFO_CONFIGID_HWID_Msk (0xFFFFUL << FICR_INFO_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field.                   */
22368 
22369 
22370 /* FICR_INFO_PART: Part code */
22371   #define FICR_INFO_PART_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of PART register.                                        */
22372 
22373 /* PART @Bits 0..31 : Part code */
22374   #define FICR_INFO_PART_PART_Pos (0UL)              /*!< Position of PART field.                                              */
22375   #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field.                       */
22376   #define FICR_INFO_PART_PART_Min (0xFFFFFFFFUL)     /*!< Min enumerator value of PART field.                                  */
22377   #define FICR_INFO_PART_PART_Max (0xFFFFFFFFUL)     /*!< Max enumerator value of PART field.                                  */
22378   #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                      */
22379 
22380 
22381 /* FICR_INFO_VARIANT: Part Variant, Hardware version and Production configuration */
22382   #define FICR_INFO_VARIANT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of VARIANT register.                                    */
22383 
22384 /* VARIANT @Bits 0..31 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
22385   #define FICR_INFO_VARIANT_VARIANT_Pos (0UL)        /*!< Position of VARIANT field.                                           */
22386   #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field.        */
22387   #define FICR_INFO_VARIANT_VARIANT_Min (0xFFFFFFFFUL) /*!< Min enumerator value of VARIANT field.                             */
22388   #define FICR_INFO_VARIANT_VARIANT_Max (0xFFFFFFFFUL) /*!< Max enumerator value of VARIANT field.                             */
22389   #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                */
22390 
22391 
22392 /* FICR_INFO_PACKAGE: Package option */
22393   #define FICR_INFO_PACKAGE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PACKAGE register.                                    */
22394 
22395 /* PACKAGE @Bits 0..31 : Package option */
22396   #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL)        /*!< Position of PACKAGE field.                                           */
22397   #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field.        */
22398   #define FICR_INFO_PACKAGE_PACKAGE_Min (0xFFFFFFFFUL) /*!< Min enumerator value of PACKAGE field.                             */
22399   #define FICR_INFO_PACKAGE_PACKAGE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of PACKAGE field.                             */
22400   #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                */
22401 
22402 
22403 /* FICR_INFO_RAM: RAM variant */
22404   #define FICR_INFO_RAM_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of RAM register.                                         */
22405 
22406 /* RAM @Bits 0..31 : RAM variant */
22407   #define FICR_INFO_RAM_RAM_Pos (0UL)                /*!< Position of RAM field.                                               */
22408   #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field.                            */
22409   #define FICR_INFO_RAM_RAM_Min (0xFFFFFFFFUL)       /*!< Min enumerator value of RAM field.                                   */
22410   #define FICR_INFO_RAM_RAM_Max (0xFFFFFFFFUL)       /*!< Max enumerator value of RAM field.                                   */
22411   #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                        */
22412 
22413 
22414 /* FICR_INFO_MRAM: MRAM variant */
22415   #define FICR_INFO_MRAM_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MRAM register.                                        */
22416 
22417 /* MRAM @Bits 0..31 : MRAM variant */
22418   #define FICR_INFO_MRAM_MRAM_Pos (0UL)              /*!< Position of MRAM field.                                              */
22419   #define FICR_INFO_MRAM_MRAM_Msk (0xFFFFFFFFUL << FICR_INFO_MRAM_MRAM_Pos) /*!< Bit mask of MRAM field.                       */
22420   #define FICR_INFO_MRAM_MRAM_Min (0xFFFFFFFFUL)     /*!< Min enumerator value of MRAM field.                                  */
22421   #define FICR_INFO_MRAM_MRAM_Max (0xFFFFFFFFUL)     /*!< Max enumerator value of MRAM field.                                  */
22422   #define FICR_INFO_MRAM_MRAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                                      */
22423 
22424 
22425 /* FICR_INFO_CODEPAGESIZE: Code memory page size in bytes */
22426   #define FICR_INFO_CODEPAGESIZE_ResetValue (0x00001000UL) /*!< Reset value of CODEPAGESIZE register.                          */
22427 
22428 /* CODEPAGESIZE @Bits 0..31 : Code memory page size in bytes */
22429   #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field.                                   */
22430   #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of
22431                                                                             CODEPAGESIZE field.*/
22432   #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Min (0xFFFFFFFFUL) /*!< Min enumerator value of CODEPAGESIZE field.              */
22433   #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of CODEPAGESIZE field.              */
22434   #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                      */
22435 
22436 
22437 /* FICR_INFO_CODESIZE: Code memory size */
22438   #define FICR_INFO_CODESIZE_ResetValue (0x00000100UL) /*!< Reset value of CODESIZE register.                                  */
22439 
22440 /* CODESIZE @Bits 0..31 : Code memory size in number of pages */
22441   #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL)      /*!< Position of CODESIZE field.                                          */
22442   #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field.   */
22443   #define FICR_INFO_CODESIZE_CODESIZE_Min (0xFFFFFFFFUL) /*!< Min enumerator value of CODESIZE field.                          */
22444   #define FICR_INFO_CODESIZE_CODESIZE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of CODESIZE field.                          */
22445   #define FICR_INFO_CODESIZE_CODESIZE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified                                              */
22446 
22447 
22448 /* FICR_INFO_DEVICETYPE: Device type */
22449   #define FICR_INFO_DEVICETYPE_ResetValue (0x00000000UL) /*!< Reset value of DEVICETYPE register.                              */
22450 
22451 /* DEVICETYPE @Bits 0..31 : Device type */
22452   #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL)  /*!< Position of DEVICETYPE field.                                        */
22453   #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE
22454                                                                             field.*/
22455   #define FICR_INFO_DEVICETYPE_DEVICETYPE_Min (0x0UL) /*!< Min enumerator value of DEVICETYPE field.                           */
22456   #define FICR_INFO_DEVICETYPE_DEVICETYPE_Max (0xFFFFFFFFUL) /*!< Max enumerator value of DEVICETYPE field.                    */
22457   #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x00000000UL) /*!< Device is an physical DIE                                    */
22458   #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA                                           */
22459 
22460 
22461 
22462 /* ============================================== Struct FICR_TRIM_GLOBAL_SAADC ============================================== */
22463 /**
22464   * @brief SAADC [FICR_TRIM_GLOBAL_SAADC] (unspecified)
22465   */
22466 typedef struct {
22467   __IM  uint32_t  CALVREF;                           /*!< (@ 0x00000000) Trim value for GLOBAL.SAADC.CALVREF                   */
22468   __IM  uint32_t  CALGAIN[3];                        /*!< (@ 0x00000004) Trim value for GLOBAL.SAADC.CALGAIN                   */
22469   __IM  uint32_t  CALOFFSET;                         /*!< (@ 0x00000010) Trim value for GLOBAL.SAADC.CALOFFSET                 */
22470   __IM  uint32_t  LINCALCOEFF[6];                    /*!< (@ 0x00000014) Trim value for GLOBAL.SAADC.LINCALCOEFF               */
22471   __IM  uint32_t  CALIREF;                           /*!< (@ 0x0000002C) Trim value for GLOBAL.SAADC.CALIREF                   */
22472   __IM  uint32_t  CALVREFTC;                         /*!< (@ 0x00000030) Trim value for GLOBAL.SAADC.CALVREFTC                 */
22473 } NRF_FICR_TRIM_GLOBAL_SAADC_Type;                   /*!< Size = 52 (0x034)                                                    */
22474 
22475 /* FICR_TRIM_GLOBAL_SAADC_CALVREF: Trim value for GLOBAL.SAADC.CALVREF */
22476   #define FICR_TRIM_GLOBAL_SAADC_CALVREF_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALVREF register.                       */
22477 
22478 /* VALUE @Bits 0..31 : Trim value */
22479   #define FICR_TRIM_GLOBAL_SAADC_CALVREF_VALUE_Pos (0UL) /*!< Position of VALUE field.                                         */
22480   #define FICR_TRIM_GLOBAL_SAADC_CALVREF_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALVREF_VALUE_Pos) /*!< Bit mask of
22481                                                                             VALUE field.*/
22482 
22483 
22484 /* FICR_TRIM_GLOBAL_SAADC_CALGAIN: Trim value for GLOBAL.SAADC.CALGAIN */
22485   #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_MaxCount (3UL) /*!< Max size of CALGAIN[3] array.                                     */
22486   #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_MaxIndex (2UL) /*!< Max index of CALGAIN[3] array.                                    */
22487   #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_MinIndex (0UL) /*!< Min index of CALGAIN[3] array.                                    */
22488   #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALGAIN[3] register.                    */
22489 
22490 /* VALUE @Bits 0..31 : Trim value */
22491   #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_VALUE_Pos (0UL) /*!< Position of VALUE field.                                         */
22492   #define FICR_TRIM_GLOBAL_SAADC_CALGAIN_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALGAIN_VALUE_Pos) /*!< Bit mask of
22493                                                                             VALUE field.*/
22494 
22495 
22496 /* FICR_TRIM_GLOBAL_SAADC_CALOFFSET: Trim value for GLOBAL.SAADC.CALOFFSET */
22497   #define FICR_TRIM_GLOBAL_SAADC_CALOFFSET_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALOFFSET register.                   */
22498 
22499 /* VALUE @Bits 0..31 : Trim value */
22500   #define FICR_TRIM_GLOBAL_SAADC_CALOFFSET_VALUE_Pos (0UL) /*!< Position of VALUE field.                                       */
22501   #define FICR_TRIM_GLOBAL_SAADC_CALOFFSET_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALOFFSET_VALUE_Pos) /*!< Bit mask
22502                                                                             of VALUE field.*/
22503 
22504 
22505 /* FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF: Trim value for GLOBAL.SAADC.LINCALCOEFF */
22506   #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_MaxCount (6UL) /*!< Max size of LINCALCOEFF[6] array.                             */
22507   #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_MaxIndex (5UL) /*!< Max index of LINCALCOEFF[6] array.                            */
22508   #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_MinIndex (0UL) /*!< Min index of LINCALCOEFF[6] array.                            */
22509   #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LINCALCOEFF[6] register.            */
22510 
22511 /* VALUE @Bits 0..31 : Trim value */
22512   #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_VALUE_Pos (0UL) /*!< Position of VALUE field.                                     */
22513   #define FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_VALUE_Pos) /*!< Bit
22514                                                                             mask of VALUE field.*/
22515 
22516 
22517 /* FICR_TRIM_GLOBAL_SAADC_CALIREF: Trim value for GLOBAL.SAADC.CALIREF */
22518   #define FICR_TRIM_GLOBAL_SAADC_CALIREF_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALIREF register.                       */
22519 
22520 /* VALUE @Bits 0..31 : Trim value */
22521   #define FICR_TRIM_GLOBAL_SAADC_CALIREF_VALUE_Pos (0UL) /*!< Position of VALUE field.                                         */
22522   #define FICR_TRIM_GLOBAL_SAADC_CALIREF_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALIREF_VALUE_Pos) /*!< Bit mask of
22523                                                                             VALUE field.*/
22524 
22525 
22526 /* FICR_TRIM_GLOBAL_SAADC_CALVREFTC: Trim value for GLOBAL.SAADC.CALVREFTC */
22527   #define FICR_TRIM_GLOBAL_SAADC_CALVREFTC_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALVREFTC register.                   */
22528 
22529 /* VALUE @Bits 0..31 : Trim value */
22530   #define FICR_TRIM_GLOBAL_SAADC_CALVREFTC_VALUE_Pos (0UL) /*!< Position of VALUE field.                                       */
22531   #define FICR_TRIM_GLOBAL_SAADC_CALVREFTC_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_SAADC_CALVREFTC_VALUE_Pos) /*!< Bit mask
22532                                                                             of VALUE field.*/
22533 
22534 
22535 
22536 /* ============================================== Struct FICR_TRIM_GLOBAL_NFCT =============================================== */
22537 /**
22538   * @brief NFCT [FICR_TRIM_GLOBAL_NFCT] (unspecified)
22539   */
22540 typedef struct {
22541   __IM  uint32_t  BIASCFG;                           /*!< (@ 0x00000000) Trim value for NFCT.BIASCFG                           */
22542 } NRF_FICR_TRIM_GLOBAL_NFCT_Type;                    /*!< Size = 4 (0x004)                                                     */
22543 
22544 /* FICR_TRIM_GLOBAL_NFCT_BIASCFG: Trim value for NFCT.BIASCFG */
22545   #define FICR_TRIM_GLOBAL_NFCT_BIASCFG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of BIASCFG register.                        */
22546 
22547 /* VALUE @Bits 0..31 : Trim value */
22548   #define FICR_TRIM_GLOBAL_NFCT_BIASCFG_VALUE_Pos (0UL) /*!< Position of VALUE field.                                          */
22549   #define FICR_TRIM_GLOBAL_NFCT_BIASCFG_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_NFCT_BIASCFG_VALUE_Pos) /*!< Bit mask of
22550                                                                             VALUE field.*/
22551 
22552 
22553 
22554 /* =========================================== Struct FICR_TRIM_GLOBAL_CANPLL_TRIM =========================================== */
22555 /**
22556   * @brief TRIM [FICR_TRIM_GLOBAL_CANPLL_TRIM] (unspecified)
22557   */
22558 typedef struct {
22559   __IM  uint32_t  CTUNE;                             /*!< (@ 0x00000000) Trim value for GLOBAL.CANPLL.CTUNE                    */
22560 } NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_Type;             /*!< Size = 4 (0x004)                                                     */
22561 
22562 /* FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE: Trim value for GLOBAL.CANPLL.CTUNE */
22563   #define FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CTUNE register.                     */
22564 
22565 /* VALUE @Bits 0..31 : Trim value */
22566   #define FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE_VALUE_Pos (0UL) /*!< Position of VALUE field.                                     */
22567   #define FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE_VALUE_Pos) /*!< Bit
22568                                                                             mask of VALUE field.*/
22569 
22570 
22571 
22572 /* ============================================= Struct FICR_TRIM_GLOBAL_CANPLL ============================================== */
22573 /**
22574   * @brief CANPLL [FICR_TRIM_GLOBAL_CANPLL] (unspecified)
22575   */
22576 typedef struct {
22577   __IOM NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_Type TRIM;  /*!< (@ 0x00000000) (unspecified)                                         */
22578 } NRF_FICR_TRIM_GLOBAL_CANPLL_Type;                  /*!< Size = 4 (0x004)                                                     */
22579 
22580 
22581 /* ============================================== Struct FICR_TRIM_GLOBAL_COMP =============================================== */
22582 /**
22583   * @brief COMP [FICR_TRIM_GLOBAL_COMP] (unspecified)
22584   */
22585 typedef struct {
22586   __IM  uint32_t  REFTRIM;                           /*!< (@ 0x00000000) Trim value for GLOBAL.COMP.REFTRIM                    */
22587   __IM  uint32_t  RCALTRIM;                          /*!< (@ 0x00000004) Trim value used during production test                */
22588 } NRF_FICR_TRIM_GLOBAL_COMP_Type;                    /*!< Size = 8 (0x008)                                                     */
22589 
22590 /* FICR_TRIM_GLOBAL_COMP_REFTRIM: Trim value for GLOBAL.COMP.REFTRIM */
22591   #define FICR_TRIM_GLOBAL_COMP_REFTRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of REFTRIM register.                        */
22592 
22593 /* VALUE @Bits 0..31 : Trim value */
22594   #define FICR_TRIM_GLOBAL_COMP_REFTRIM_VALUE_Pos (0UL) /*!< Position of VALUE field.                                          */
22595   #define FICR_TRIM_GLOBAL_COMP_REFTRIM_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_COMP_REFTRIM_VALUE_Pos) /*!< Bit mask of
22596                                                                             VALUE field.*/
22597 
22598 
22599 /* FICR_TRIM_GLOBAL_COMP_RCALTRIM: Trim value used during production test */
22600   #define FICR_TRIM_GLOBAL_COMP_RCALTRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RCALTRIM register.                      */
22601 
22602 /* VALUE @Bits 0..31 : Trim value */
22603   #define FICR_TRIM_GLOBAL_COMP_RCALTRIM_VALUE_Pos (0UL) /*!< Position of VALUE field.                                         */
22604   #define FICR_TRIM_GLOBAL_COMP_RCALTRIM_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_GLOBAL_COMP_RCALTRIM_VALUE_Pos) /*!< Bit mask of
22605                                                                             VALUE field.*/
22606 
22607 
22608 
22609 /* ================================================= Struct FICR_TRIM_GLOBAL ================================================= */
22610 /**
22611   * @brief GLOBAL [FICR_TRIM_GLOBAL] (unspecified)
22612   */
22613 typedef struct {
22614   __IOM NRF_FICR_TRIM_GLOBAL_SAADC_Type SAADC;       /*!< (@ 0x00000000) (unspecified)                                         */
22615   __IM  uint32_t  RESERVED;
22616   __IOM NRF_FICR_TRIM_GLOBAL_NFCT_Type NFCT;         /*!< (@ 0x00000038) (unspecified)                                         */
22617   __IOM NRF_FICR_TRIM_GLOBAL_CANPLL_Type CANPLL;     /*!< (@ 0x0000003C) (unspecified)                                         */
22618   __IM  uint32_t  RESERVED1[3];
22619   __IOM NRF_FICR_TRIM_GLOBAL_COMP_Type COMP;         /*!< (@ 0x0000004C) (unspecified)                                         */
22620 } NRF_FICR_TRIM_GLOBAL_Type;                         /*!< Size = 84 (0x054)                                                    */
22621 
22622 
22623 /* ========================================= Struct FICR_TRIM_APPLICATION_HSFLL_TRIM ========================================= */
22624 /**
22625   * @brief TRIM [FICR_TRIM_APPLICATION_HSFLL_TRIM] (unspecified)
22626   */
22627 typedef struct {
22628   __IM  uint32_t  VSUP;                              /*!< (@ 0x00000000) Trim value for APPLICATION.HSFLL.VSUP                 */
22629   __IM  uint32_t  COARSE[6];                         /*!< (@ 0x00000004) Trim value for APPLICATION.HSFLL.COARSE               */
22630   __IM  uint32_t  FINE[6];                           /*!< (@ 0x0000001C) Trim value for APPLICATION.HSFLL.FINE                 */
22631 } NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_Type;         /*!< Size = 52 (0x034)                                                    */
22632 
22633 /* FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP: Trim value for APPLICATION.HSFLL.VSUP */
22634   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP_ResetValue (0xFFFFFFFFUL) /*!< Reset value of VSUP register.                   */
22635 
22636 /* VALUE @Bits 0..31 : Trim value */
22637   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP_VALUE_Pos (0UL) /*!< Position of VALUE field.                                  */
22638   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP_VALUE_Pos) /*!<
22639                                                                             Bit mask of VALUE field.*/
22640 
22641 
22642 /* FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE: Trim value for APPLICATION.HSFLL.COARSE */
22643   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_MaxCount (6UL) /*!< Max size of COARSE[6] array.                             */
22644   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_MaxIndex (5UL) /*!< Max index of COARSE[6] array.                            */
22645   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_MinIndex (0UL) /*!< Min index of COARSE[6] array.                            */
22646   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of COARSE[6] register.            */
22647 
22648 /* VALUE @Bits 0..31 : Trim value */
22649   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_VALUE_Pos (0UL) /*!< Position of VALUE field.                                */
22650   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_VALUE_Pos)
22651                                                                             /*!< Bit mask of VALUE field.*/
22652 
22653 
22654 /* FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE: Trim value for APPLICATION.HSFLL.FINE */
22655   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_MaxCount (6UL) /*!< Max size of FINE[6] array.                                 */
22656   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_MaxIndex (5UL) /*!< Max index of FINE[6] array.                                */
22657   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_MinIndex (0UL) /*!< Min index of FINE[6] array.                                */
22658   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of FINE[6] register.                */
22659 
22660 /* VALUE @Bits 0..31 : Trim value */
22661   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_VALUE_Pos (0UL) /*!< Position of VALUE field.                                  */
22662   #define FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_VALUE_Pos) /*!<
22663                                                                             Bit mask of VALUE field.*/
22664 
22665 
22666 
22667 /* =========================================== Struct FICR_TRIM_APPLICATION_HSFLL ============================================ */
22668 /**
22669   * @brief HSFLL [FICR_TRIM_APPLICATION_HSFLL] (unspecified)
22670   */
22671 typedef struct {
22672   __IOM NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_Type TRIM; /*!< (@ 0x00000000) (unspecified)                                      */
22673 } NRF_FICR_TRIM_APPLICATION_HSFLL_Type;              /*!< Size = 52 (0x034)                                                    */
22674 
22675 
22676 /* ===================================== Struct FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE ====================================== */
22677 /**
22678   * @brief BLOCKTYPE [FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE] (unspecified)
22679   */
22680 typedef struct {
22681   __IM  uint32_t  TRIM;                              /*!< (@ 0x00000000) Trim value for APPLICATION.MEMCONF.TRIM               */
22682 } NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_Type;  /*!< Size = 4 (0x004)                                                     */
22683   #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_MaxCount (3UL) /*!< Size of BLOCKTYPE[3] array.                              */
22684   #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_MaxIndex (2UL) /*!< Max index of BLOCKTYPE[3] array.                         */
22685   #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_MinIndex (0UL) /*!< Min index of BLOCKTYPE[3] array.                         */
22686 
22687 /* FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM: Trim value for APPLICATION.MEMCONF.TRIM */
22688   #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TRIM register.            */
22689 
22690 /* VALUE @Bits 0..31 : Trim value */
22691   #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM_VALUE_Pos (0UL) /*!< Position of VALUE field.                           */
22692   #define FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_TRIM_VALUE_Pos)
22693                                                                             /*!< Bit mask of VALUE field.*/
22694 
22695 
22696 
22697 /* ========================================== Struct FICR_TRIM_APPLICATION_MEMCONF =========================================== */
22698 /**
22699   * @brief MEMCONF [FICR_TRIM_APPLICATION_MEMCONF] (unspecified)
22700   */
22701 typedef struct {
22702   __IOM NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_Type BLOCKTYPE[3]; /*!< (@ 0x00000000) (unspecified)                       */
22703 } NRF_FICR_TRIM_APPLICATION_MEMCONF_Type;            /*!< Size = 12 (0x00C)                                                    */
22704 
22705 
22706 /* ============================================== Struct FICR_TRIM_APPLICATION =============================================== */
22707 /**
22708   * @brief APPLICATION [FICR_TRIM_APPLICATION] (unspecified)
22709   */
22710 typedef struct {
22711   __IOM NRF_FICR_TRIM_APPLICATION_HSFLL_Type HSFLL;  /*!< (@ 0x00000000) (unspecified)                                         */
22712   __IOM NRF_FICR_TRIM_APPLICATION_MEMCONF_Type MEMCONF; /*!< (@ 0x00000034) (unspecified)                                      */
22713 } NRF_FICR_TRIM_APPLICATION_Type;                    /*!< Size = 64 (0x040)                                                    */
22714 
22715 
22716 /* ========================================== Struct FICR_TRIM_RADIOCORE_HSFLL_TRIM ========================================== */
22717 /**
22718   * @brief TRIM [FICR_TRIM_RADIOCORE_HSFLL_TRIM] (unspecified)
22719   */
22720 typedef struct {
22721   __IM  uint32_t  VSUP;                              /*!< (@ 0x00000000) Trim value for RADIOCORE.HSFLL.VSUP                   */
22722   __IM  uint32_t  COARSE[6];                         /*!< (@ 0x00000004) Trim value for RADIOCORE.HSFLL.COARSE                 */
22723   __IM  uint32_t  FINE[6];                           /*!< (@ 0x0000001C) Trim value for RADIOCORE.HSFLL.FINE                   */
22724 } NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_Type;           /*!< Size = 52 (0x034)                                                    */
22725 
22726 /* FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP: Trim value for RADIOCORE.HSFLL.VSUP */
22727   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP_ResetValue (0xFFFFFFFFUL) /*!< Reset value of VSUP register.                     */
22728 
22729 /* VALUE @Bits 0..31 : Trim value */
22730   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP_VALUE_Pos (0UL) /*!< Position of VALUE field.                                    */
22731   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP_VALUE_Pos) /*!< Bit
22732                                                                             mask of VALUE field.*/
22733 
22734 
22735 /* FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE: Trim value for RADIOCORE.HSFLL.COARSE */
22736   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_MaxCount (6UL) /*!< Max size of COARSE[6] array.                               */
22737   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_MaxIndex (5UL) /*!< Max index of COARSE[6] array.                              */
22738   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_MinIndex (0UL) /*!< Min index of COARSE[6] array.                              */
22739   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of COARSE[6] register.              */
22740 
22741 /* VALUE @Bits 0..31 : Trim value */
22742   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_VALUE_Pos (0UL) /*!< Position of VALUE field.                                  */
22743   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_VALUE_Pos) /*!<
22744                                                                             Bit mask of VALUE field.*/
22745 
22746 
22747 /* FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE: Trim value for RADIOCORE.HSFLL.FINE */
22748   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_MaxCount (6UL) /*!< Max size of FINE[6] array.                                   */
22749   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_MaxIndex (5UL) /*!< Max index of FINE[6] array.                                  */
22750   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_MinIndex (0UL) /*!< Min index of FINE[6] array.                                  */
22751   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of FINE[6] register.                  */
22752 
22753 /* VALUE @Bits 0..31 : Trim value */
22754   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_VALUE_Pos (0UL) /*!< Position of VALUE field.                                    */
22755   #define FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_VALUE_Pos) /*!< Bit
22756                                                                             mask of VALUE field.*/
22757 
22758 
22759 
22760 /* ============================================ Struct FICR_TRIM_RADIOCORE_HSFLL ============================================= */
22761 /**
22762   * @brief HSFLL [FICR_TRIM_RADIOCORE_HSFLL] (unspecified)
22763   */
22764 typedef struct {
22765   __IOM NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_Type TRIM; /*!< (@ 0x00000000) (unspecified)                                        */
22766 } NRF_FICR_TRIM_RADIOCORE_HSFLL_Type;                /*!< Size = 52 (0x034)                                                    */
22767 
22768 
22769 /* ====================================== Struct FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE ======================================= */
22770 /**
22771   * @brief BLOCKTYPE [FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE] (unspecified)
22772   */
22773 typedef struct {
22774   __IM  uint32_t  TRIM;                              /*!< (@ 0x00000000) Trim value for RADIOCORE.MEMCONF.TRIM                 */
22775 } NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_Type;    /*!< Size = 4 (0x004)                                                     */
22776   #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_MaxCount (3UL) /*!< Size of BLOCKTYPE[3] array.                                */
22777   #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_MaxIndex (2UL) /*!< Max index of BLOCKTYPE[3] array.                           */
22778   #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_MinIndex (0UL) /*!< Min index of BLOCKTYPE[3] array.                           */
22779 
22780 /* FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM: Trim value for RADIOCORE.MEMCONF.TRIM */
22781   #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TRIM register.              */
22782 
22783 /* VALUE @Bits 0..31 : Trim value */
22784   #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM_VALUE_Pos (0UL) /*!< Position of VALUE field.                             */
22785   #define FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_TRIM_VALUE_Pos)
22786                                                                             /*!< Bit mask of VALUE field.*/
22787 
22788 
22789 
22790 /* =========================================== Struct FICR_TRIM_RADIOCORE_MEMCONF ============================================ */
22791 /**
22792   * @brief MEMCONF [FICR_TRIM_RADIOCORE_MEMCONF] (unspecified)
22793   */
22794 typedef struct {
22795   __IOM NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_Type BLOCKTYPE[3]; /*!< (@ 0x00000000) (unspecified)                         */
22796 } NRF_FICR_TRIM_RADIOCORE_MEMCONF_Type;              /*!< Size = 12 (0x00C)                                                    */
22797 
22798 
22799 /* ======================================= Struct FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA ======================================== */
22800 /**
22801   * @brief SPHYNXANA [FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA] (unspecified)
22802   */
22803 typedef struct {
22804   __IM  uint32_t  FSCTRL0;                           /*!< (@ 0x00000000) Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL0      */
22805   __IM  uint32_t  FSCTRL1;                           /*!< (@ 0x00000004) Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL1      */
22806   __IM  uint32_t  FSCTRL2;                           /*!< (@ 0x00000008) Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL2      */
22807   __IM  uint32_t  RXCTRL;                            /*!< (@ 0x0000000C) Trim value for RADIOCORE.RADIO.SPHYNXANA.RXCTRL       */
22808   __IM  uint32_t  OVRRXTRIMCODE;                     /*!< (@ 0x00000010) Trim value for RADIOCORE.RADIO.SPHYNXANA.OVRRXTRIMCODE*/
22809 } NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_Type;      /*!< Size = 20 (0x014)                                                    */
22810 
22811 /* FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL0: Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL0 */
22812   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL0_ResetValue (0xFFFFFFFFUL) /*!< Reset value of FSCTRL0 register.          */
22813 
22814 /* VALUE @Bits 0..31 : Trim value */
22815   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL0_VALUE_Pos (0UL) /*!< Position of VALUE field.                            */
22816   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL0_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL0_VALUE_Pos)
22817                                                                             /*!< Bit mask of VALUE field.*/
22818 
22819 
22820 /* FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL1: Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL1 */
22821   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL1_ResetValue (0xFFFFFFFFUL) /*!< Reset value of FSCTRL1 register.          */
22822 
22823 /* VALUE @Bits 0..31 : Trim value */
22824   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL1_VALUE_Pos (0UL) /*!< Position of VALUE field.                            */
22825   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL1_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL1_VALUE_Pos)
22826                                                                             /*!< Bit mask of VALUE field.*/
22827 
22828 
22829 /* FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL2: Trim value for RADIOCORE.RADIO.SPHYNXANA.FSCTRL2 */
22830   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL2_ResetValue (0xFFFFFFFFUL) /*!< Reset value of FSCTRL2 register.          */
22831 
22832 /* VALUE @Bits 0..31 : Trim value */
22833   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL2_VALUE_Pos (0UL) /*!< Position of VALUE field.                            */
22834   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL2_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_FSCTRL2_VALUE_Pos)
22835                                                                             /*!< Bit mask of VALUE field.*/
22836 
22837 
22838 /* FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_RXCTRL: Trim value for RADIOCORE.RADIO.SPHYNXANA.RXCTRL */
22839   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_RXCTRL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of RXCTRL register.            */
22840 
22841 /* VALUE @Bits 0..31 : Trim value */
22842   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_RXCTRL_VALUE_Pos (0UL) /*!< Position of VALUE field.                             */
22843   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_RXCTRL_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_RXCTRL_VALUE_Pos)
22844                                                                             /*!< Bit mask of VALUE field.*/
22845 
22846 
22847 /* FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_OVRRXTRIMCODE: Trim value for RADIOCORE.RADIO.SPHYNXANA.OVRRXTRIMCODE */
22848   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_OVRRXTRIMCODE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OVRRXTRIMCODE
22849                                                                             register.*/
22850 
22851 /* VALUE @Bits 0..31 : Trim value */
22852   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_OVRRXTRIMCODE_VALUE_Pos (0UL) /*!< Position of VALUE field.                      */
22853   #define FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_OVRRXTRIMCODE_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_OVRRXTRIMCODE_VALUE_Pos)
22854                                                                             /*!< Bit mask of VALUE field.*/
22855 
22856 
22857 
22858 /* ========================================= Struct FICR_TRIM_RADIOCORE_RADIO_RXAGC ========================================== */
22859 /**
22860   * @brief RXAGC [FICR_TRIM_RADIOCORE_RADIO_RXAGC] (unspecified)
22861   */
22862 typedef struct {
22863   __IM  uint32_t  CALIBRATION;                       /*!< (@ 0x00000000) Trim value for RSSICAL and ED154CAL in
22864                                                                          RADIOCORE.RADIO.RXAGC.CALIBRATION*/
22865 } NRF_FICR_TRIM_RADIOCORE_RADIO_RXAGC_Type;          /*!< Size = 4 (0x004)                                                     */
22866 
22867 /* FICR_TRIM_RADIOCORE_RADIO_RXAGC_CALIBRATION: Trim value for RSSICAL and ED154CAL in RADIOCORE.RADIO.RXAGC.CALIBRATION */
22868   #define FICR_TRIM_RADIOCORE_RADIO_RXAGC_CALIBRATION_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CALIBRATION register.      */
22869 
22870 /* VALUE @Bits 0..31 : Trim value */
22871   #define FICR_TRIM_RADIOCORE_RADIO_RXAGC_CALIBRATION_VALUE_Pos (0UL) /*!< Position of VALUE field.                            */
22872   #define FICR_TRIM_RADIOCORE_RADIO_RXAGC_CALIBRATION_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_RXAGC_CALIBRATION_VALUE_Pos)
22873                                                                             /*!< Bit mask of VALUE field.*/
22874 
22875 
22876 
22877 /* ============================================ Struct FICR_TRIM_RADIOCORE_RADIO ============================================= */
22878 /**
22879   * @brief RADIO [FICR_TRIM_RADIOCORE_RADIO] (unspecified)
22880   */
22881 typedef struct {
22882   __IOM NRF_FICR_TRIM_RADIOCORE_RADIO_SPHYNXANA_Type SPHYNXANA; /*!< (@ 0x00000000) (unspecified)                              */
22883   __IOM NRF_FICR_TRIM_RADIOCORE_RADIO_RXAGC_Type RXAGC; /*!< (@ 0x00000014) (unspecified)                                      */
22884   __IM  uint32_t  PVTTOT;                            /*!< (@ 0x00000018) Trim value for RADIOCORE.RADIO.EXPECTEDPVTTOTRATIO    */
22885   __IM  uint32_t  KDTC;                              /*!< (@ 0x0000001C) Trim value for RADIOCORE.RADIO.ESTKDTCVAL             */
22886   __IM  uint32_t  TXHFGAIN;                          /*!< (@ 0x00000020) Trim value for RADIOCORE.RADIO.TXINTERFACEHFGAIN      */
22887   __IM  uint32_t  PVTTOFIX;                          /*!< (@ 0x00000024) Trim value for RADIOCORE.RADIO.ADPLLSTARTUPCOMMAND6   */
22888   __IM  uint32_t  LOOPGAIN;                          /*!< (@ 0x00000028) Trim value for RADIOCORE.RADIO.ADPLLSTARTUPCOMMAND5   */
22889 } NRF_FICR_TRIM_RADIOCORE_RADIO_Type;                /*!< Size = 44 (0x02C)                                                    */
22890 
22891 /* FICR_TRIM_RADIOCORE_RADIO_PVTTOT: Trim value for RADIOCORE.RADIO.EXPECTEDPVTTOTRATIO */
22892   #define FICR_TRIM_RADIOCORE_RADIO_PVTTOT_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PVTTOT register.                      */
22893 
22894 /* VALUE @Bits 0..31 : Trim value */
22895   #define FICR_TRIM_RADIOCORE_RADIO_PVTTOT_VALUE_Pos (0UL) /*!< Position of VALUE field.                                       */
22896   #define FICR_TRIM_RADIOCORE_RADIO_PVTTOT_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_PVTTOT_VALUE_Pos) /*!< Bit mask
22897                                                                             of VALUE field.*/
22898 
22899 
22900 /* FICR_TRIM_RADIOCORE_RADIO_KDTC: Trim value for RADIOCORE.RADIO.ESTKDTCVAL */
22901   #define FICR_TRIM_RADIOCORE_RADIO_KDTC_ResetValue (0xFFFFFFFFUL) /*!< Reset value of KDTC register.                          */
22902 
22903 /* VALUE @Bits 0..31 : Trim value */
22904   #define FICR_TRIM_RADIOCORE_RADIO_KDTC_VALUE_Pos (0UL) /*!< Position of VALUE field.                                         */
22905   #define FICR_TRIM_RADIOCORE_RADIO_KDTC_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_KDTC_VALUE_Pos) /*!< Bit mask of
22906                                                                             VALUE field.*/
22907 
22908 
22909 /* FICR_TRIM_RADIOCORE_RADIO_TXHFGAIN: Trim value for RADIOCORE.RADIO.TXINTERFACEHFGAIN */
22910   #define FICR_TRIM_RADIOCORE_RADIO_TXHFGAIN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of TXHFGAIN register.                  */
22911 
22912 /* VALUE @Bits 0..31 : Trim value */
22913   #define FICR_TRIM_RADIOCORE_RADIO_TXHFGAIN_VALUE_Pos (0UL) /*!< Position of VALUE field.                                     */
22914   #define FICR_TRIM_RADIOCORE_RADIO_TXHFGAIN_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_TXHFGAIN_VALUE_Pos) /*!< Bit
22915                                                                             mask of VALUE field.*/
22916 
22917 
22918 /* FICR_TRIM_RADIOCORE_RADIO_PVTTOFIX: Trim value for RADIOCORE.RADIO.ADPLLSTARTUPCOMMAND6 */
22919   #define FICR_TRIM_RADIOCORE_RADIO_PVTTOFIX_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PVTTOFIX register.                  */
22920 
22921 /* VALUE @Bits 0..31 : Trim value */
22922   #define FICR_TRIM_RADIOCORE_RADIO_PVTTOFIX_VALUE_Pos (0UL) /*!< Position of VALUE field.                                     */
22923   #define FICR_TRIM_RADIOCORE_RADIO_PVTTOFIX_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_PVTTOFIX_VALUE_Pos) /*!< Bit
22924                                                                             mask of VALUE field.*/
22925 
22926 
22927 /* FICR_TRIM_RADIOCORE_RADIO_LOOPGAIN: Trim value for RADIOCORE.RADIO.ADPLLSTARTUPCOMMAND5 */
22928   #define FICR_TRIM_RADIOCORE_RADIO_LOOPGAIN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of LOOPGAIN register.                  */
22929 
22930 /* VALUE @Bits 0..31 : Trim value */
22931   #define FICR_TRIM_RADIOCORE_RADIO_LOOPGAIN_VALUE_Pos (0UL) /*!< Position of VALUE field.                                     */
22932   #define FICR_TRIM_RADIOCORE_RADIO_LOOPGAIN_VALUE_Msk (0xFFFFFFFFUL << FICR_TRIM_RADIOCORE_RADIO_LOOPGAIN_VALUE_Pos) /*!< Bit
22933                                                                             mask of VALUE field.*/
22934 
22935 
22936 
22937 /* =============================================== Struct FICR_TRIM_RADIOCORE ================================================ */
22938 /**
22939   * @brief RADIOCORE [FICR_TRIM_RADIOCORE] (unspecified)
22940   */
22941 typedef struct {
22942   __IOM NRF_FICR_TRIM_RADIOCORE_HSFLL_Type HSFLL;    /*!< (@ 0x00000000) (unspecified)                                         */
22943   __IOM NRF_FICR_TRIM_RADIOCORE_MEMCONF_Type MEMCONF; /*!< (@ 0x00000034) (unspecified)                                        */
22944   __IOM NRF_FICR_TRIM_RADIOCORE_RADIO_Type RADIO;    /*!< (@ 0x00000040) (unspecified)                                         */
22945 } NRF_FICR_TRIM_RADIOCORE_Type;                      /*!< Size = 108 (0x06C)                                                   */
22946 
22947 
22948 /* ==================================================== Struct FICR_TRIM ===================================================== */
22949 /**
22950   * @brief TRIM [FICR_TRIM] (unspecified)
22951   */
22952 typedef struct {
22953   __IM  uint32_t  RESERVED[161];
22954   __IOM NRF_FICR_TRIM_GLOBAL_Type GLOBAL;            /*!< (@ 0x00000284) (unspecified)                                         */
22955   __IOM NRF_FICR_TRIM_APPLICATION_Type APPLICATION;  /*!< (@ 0x000002D8) (unspecified)                                         */
22956   __IOM NRF_FICR_TRIM_RADIOCORE_Type RADIOCORE;      /*!< (@ 0x00000318) (unspecified)                                         */
22957   __IM  uint32_t  RESERVED1[61];
22958 } NRF_FICR_TRIM_Type;                                /*!< Size = 1144 (0x478)                                                  */
22959 
22960 /* ======================================================= Struct FICR ======================================================= */
22961 /**
22962   * @brief Factory Information Configuration Registers
22963   */
22964   typedef struct {                                   /*!< FICR Structure                                                       */
22965     __IM uint32_t RESERVED[3];
22966     __IOM NRF_FICR_BLE_Type BLE;                     /*!< (@ 0x0000000C) (unspecified)                                         */
22967     __IM uint32_t RESERVED1[2];
22968     __IOM NRF_FICR_NFC_Type NFC;                     /*!< (@ 0x00000040) (unspecified)                                         */
22969     __IOM NRF_FICR_INFO_Type INFO;                   /*!< (@ 0x00000050) Device info                                           */
22970     __IM uint32_t RESERVED2[35];
22971     __IOM NRF_FICR_TRIM_Type TRIM;                   /*!< (@ 0x00000100) (unspecified)                                         */
22972   } NRF_FICR_Type;                                   /*!< Size = 1400 (0x578)                                                  */
22973 
22974 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
22975 
22976 /* =========================================================================================================================== */
22977 /* ================                                           GPIO                                           ================ */
22978 /* =========================================================================================================================== */
22979 
22980 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
22981 
22982 /* =================================================== Struct GPIO_PORTCNF =================================================== */
22983 /**
22984   * @brief PORTCNF [GPIO_PORTCNF] (unspecified)
22985   */
22986 typedef struct {
22987   #if defined(_GNUC_)
22988     #pragma GCC diagnostic push
22989     #pragma GCC diagnostic ignored "-Wpedantic"
22990   #endif
22991   union {
22992     struct {
22993       __IOM uint32_t DRIVECTRL;                      /*!< (@ 0x00000000) Drive control for impedance matching of the pins in
22994                                                                          this port*/
22995     };
22996     struct {
22997     };
22998   };
22999   #if defined(_GNUC_)
23000     #pragma GCC diagnostic pop
23001   #endif
23002 } NRF_GPIO_PORTCNF_Type;                             /*!< Size = 4 (0x004)                                                     */
23003 
23004 /* GPIO_PORTCNF_DRIVECTRL: Drive control for impedance matching of the pins in this port */
23005   #define GPIO_PORTCNF_DRIVECTRL_ResetValue (0x00000000UL) /*!< Reset value of DRIVECTRL register.                             */
23006 
23007 /* IMPEDANCE50 @Bit 0 : Enable 50 ohms impedance to the pins in this port */
23008   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Pos (0UL) /*!< Position of IMPEDANCE50 field.                                     */
23009   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Pos) /*!< Bit mask of IMPEDANCE50
23010                                                                             field.*/
23011   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE50 field.                       */
23012   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE50 field.                       */
23013   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Disable (0x0UL) /*!< Disabled                                                     */
23014   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE50_Enable (0x1UL) /*!< Enable                                                        */
23015 
23016 /* IMPEDANCE100 @Bit 1 : Enable 100 ohms impedance to the pins in this port */
23017   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Pos (1UL) /*!< Position of IMPEDANCE100 field.                                   */
23018   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Pos) /*!< Bit mask of
23019                                                                             IMPEDANCE100 field.*/
23020   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE100 field.                     */
23021   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE100 field.                     */
23022   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Disable (0x0UL) /*!< Disabled                                                    */
23023   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE100_Enable (0x1UL) /*!< Enable                                                       */
23024 
23025 /* IMPEDANCE200 @Bit 2 : Enable 200 ohms impedance to the pins in this port */
23026   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Pos (2UL) /*!< Position of IMPEDANCE200 field.                                   */
23027   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Pos) /*!< Bit mask of
23028                                                                             IMPEDANCE200 field.*/
23029   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE200 field.                     */
23030   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE200 field.                     */
23031   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Disable (0x0UL) /*!< Disabled                                                    */
23032   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE200_Enable (0x1UL) /*!< Enable                                                       */
23033 
23034 /* IMPEDANCE400 @Bit 3 : Enable 400 ohms impedance to the pins in this port */
23035   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Pos (3UL) /*!< Position of IMPEDANCE400 field.                                   */
23036   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Pos) /*!< Bit mask of
23037                                                                             IMPEDANCE400 field.*/
23038   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE400 field.                     */
23039   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE400 field.                     */
23040   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Disable (0x0UL) /*!< Disabled                                                    */
23041   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE400_Enable (0x1UL) /*!< Enable                                                       */
23042 
23043 /* IMPEDANCE800 @Bit 4 : Enable 800 ohms impedance to the pins in this port */
23044   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Pos (4UL) /*!< Position of IMPEDANCE800 field.                                   */
23045   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Pos) /*!< Bit mask of
23046                                                                             IMPEDANCE800 field.*/
23047   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE800 field.                     */
23048   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE800 field.                     */
23049   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Disable (0x0UL) /*!< Disabled                                                    */
23050   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE800_Enable (0x1UL) /*!< Enable                                                       */
23051 
23052 /* IMPEDANCE1600 @Bit 5 : Enable 1600 ohms impedance to the pins in this port */
23053   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Pos (5UL) /*!< Position of IMPEDANCE1600 field.                                 */
23054   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Msk (0x1UL << GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Pos) /*!< Bit mask of
23055                                                                             IMPEDANCE1600 field.*/
23056   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Min (0x0UL) /*!< Min enumerator value of IMPEDANCE1600 field.                   */
23057   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Max (0x1UL) /*!< Max enumerator value of IMPEDANCE1600 field.                   */
23058   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Disable (0x0UL) /*!< Disabled                                                   */
23059   #define GPIO_PORTCNF_DRIVECTRL_IMPEDANCE1600_Enable (0x1UL) /*!< Enable                                                      */
23060 
23061 
23062 /* ======================================================= Struct GPIO ======================================================= */
23063 /**
23064   * @brief GPIO Port
23065   */
23066   typedef struct {                                   /*!< GPIO Structure                                                       */
23067     __IOM uint32_t OUT;                              /*!< (@ 0x00000000) Write GPIO port                                       */
23068     __IOM uint32_t OUTSET;                           /*!< (@ 0x00000004) Set individual bits in GPIO port                      */
23069     __IOM uint32_t OUTCLR;                           /*!< (@ 0x00000008) Clear individual bits in GPIO port                    */
23070     __IM uint32_t IN;                                /*!< (@ 0x0000000C) Read GPIO port                                        */
23071     __IOM uint32_t DIR;                              /*!< (@ 0x00000010) Direction of GPIO pins                                */
23072     __IOM uint32_t DIRSET;                           /*!< (@ 0x00000014) DIR set register                                      */
23073     __IOM uint32_t DIRCLR;                           /*!< (@ 0x00000018) DIR clear register                                    */
23074     __IM uint32_t RESERVED;
23075     __IOM uint32_t LATCH;                            /*!< (@ 0x00000020) Latch register indicating what GPIO pins that have met
23076                                                                          the criteria set in the PIN_CNF[n].SENSE registers*/
23077     __IOM uint32_t DETECTMODE;                       /*!< (@ 0x00000024) Select between default DETECT signal behavior and
23078                                                                          LDETECT mode*/
23079     __IOM uint32_t RETAIN;                           /*!< (@ 0x00000028) Enable retention for those GPIO registers marked as
23080                                                                          retained*/
23081     __IM uint32_t RESERVED1;
23082     __IOM NRF_GPIO_PORTCNF_Type PORTCNF;             /*!< (@ 0x00000030) (unspecified)                                         */
23083     __IM uint32_t RESERVED2[19];
23084     __IOM uint32_t PIN_CNF[32];                      /*!< (@ 0x00000080) Pin n configuration of GPIO pin                       */
23085   } NRF_GPIO_Type;                                   /*!< Size = 256 (0x100)                                                   */
23086 
23087 /* GPIO_OUT: Write GPIO port */
23088   #define GPIO_OUT_ResetValue (0x00000000UL)         /*!< Reset value of OUT register.                                         */
23089 
23090 /* PIN0 @Bit 0 : Pin 0 */
23091   #define GPIO_OUT_PIN0_Pos (0UL)                    /*!< Position of PIN0 field.                                              */
23092   #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field.                                          */
23093   #define GPIO_OUT_PIN0_Min (0x0UL)                  /*!< Min enumerator value of PIN0 field.                                  */
23094   #define GPIO_OUT_PIN0_Max (0x1UL)                  /*!< Max enumerator value of PIN0 field.                                  */
23095   #define GPIO_OUT_PIN0_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23096   #define GPIO_OUT_PIN0_High (0x1UL)                 /*!< Pin driver is high                                                   */
23097 
23098 /* PIN1 @Bit 1 : Pin 1 */
23099   #define GPIO_OUT_PIN1_Pos (1UL)                    /*!< Position of PIN1 field.                                              */
23100   #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field.                                          */
23101   #define GPIO_OUT_PIN1_Min (0x0UL)                  /*!< Min enumerator value of PIN1 field.                                  */
23102   #define GPIO_OUT_PIN1_Max (0x1UL)                  /*!< Max enumerator value of PIN1 field.                                  */
23103   #define GPIO_OUT_PIN1_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23104   #define GPIO_OUT_PIN1_High (0x1UL)                 /*!< Pin driver is high                                                   */
23105 
23106 /* PIN2 @Bit 2 : Pin 2 */
23107   #define GPIO_OUT_PIN2_Pos (2UL)                    /*!< Position of PIN2 field.                                              */
23108   #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field.                                          */
23109   #define GPIO_OUT_PIN2_Min (0x0UL)                  /*!< Min enumerator value of PIN2 field.                                  */
23110   #define GPIO_OUT_PIN2_Max (0x1UL)                  /*!< Max enumerator value of PIN2 field.                                  */
23111   #define GPIO_OUT_PIN2_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23112   #define GPIO_OUT_PIN2_High (0x1UL)                 /*!< Pin driver is high                                                   */
23113 
23114 /* PIN3 @Bit 3 : Pin 3 */
23115   #define GPIO_OUT_PIN3_Pos (3UL)                    /*!< Position of PIN3 field.                                              */
23116   #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field.                                          */
23117   #define GPIO_OUT_PIN3_Min (0x0UL)                  /*!< Min enumerator value of PIN3 field.                                  */
23118   #define GPIO_OUT_PIN3_Max (0x1UL)                  /*!< Max enumerator value of PIN3 field.                                  */
23119   #define GPIO_OUT_PIN3_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23120   #define GPIO_OUT_PIN3_High (0x1UL)                 /*!< Pin driver is high                                                   */
23121 
23122 /* PIN4 @Bit 4 : Pin 4 */
23123   #define GPIO_OUT_PIN4_Pos (4UL)                    /*!< Position of PIN4 field.                                              */
23124   #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field.                                          */
23125   #define GPIO_OUT_PIN4_Min (0x0UL)                  /*!< Min enumerator value of PIN4 field.                                  */
23126   #define GPIO_OUT_PIN4_Max (0x1UL)                  /*!< Max enumerator value of PIN4 field.                                  */
23127   #define GPIO_OUT_PIN4_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23128   #define GPIO_OUT_PIN4_High (0x1UL)                 /*!< Pin driver is high                                                   */
23129 
23130 /* PIN5 @Bit 5 : Pin 5 */
23131   #define GPIO_OUT_PIN5_Pos (5UL)                    /*!< Position of PIN5 field.                                              */
23132   #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field.                                          */
23133   #define GPIO_OUT_PIN5_Min (0x0UL)                  /*!< Min enumerator value of PIN5 field.                                  */
23134   #define GPIO_OUT_PIN5_Max (0x1UL)                  /*!< Max enumerator value of PIN5 field.                                  */
23135   #define GPIO_OUT_PIN5_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23136   #define GPIO_OUT_PIN5_High (0x1UL)                 /*!< Pin driver is high                                                   */
23137 
23138 /* PIN6 @Bit 6 : Pin 6 */
23139   #define GPIO_OUT_PIN6_Pos (6UL)                    /*!< Position of PIN6 field.                                              */
23140   #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field.                                          */
23141   #define GPIO_OUT_PIN6_Min (0x0UL)                  /*!< Min enumerator value of PIN6 field.                                  */
23142   #define GPIO_OUT_PIN6_Max (0x1UL)                  /*!< Max enumerator value of PIN6 field.                                  */
23143   #define GPIO_OUT_PIN6_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23144   #define GPIO_OUT_PIN6_High (0x1UL)                 /*!< Pin driver is high                                                   */
23145 
23146 /* PIN7 @Bit 7 : Pin 7 */
23147   #define GPIO_OUT_PIN7_Pos (7UL)                    /*!< Position of PIN7 field.                                              */
23148   #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field.                                          */
23149   #define GPIO_OUT_PIN7_Min (0x0UL)                  /*!< Min enumerator value of PIN7 field.                                  */
23150   #define GPIO_OUT_PIN7_Max (0x1UL)                  /*!< Max enumerator value of PIN7 field.                                  */
23151   #define GPIO_OUT_PIN7_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23152   #define GPIO_OUT_PIN7_High (0x1UL)                 /*!< Pin driver is high                                                   */
23153 
23154 /* PIN8 @Bit 8 : Pin 8 */
23155   #define GPIO_OUT_PIN8_Pos (8UL)                    /*!< Position of PIN8 field.                                              */
23156   #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field.                                          */
23157   #define GPIO_OUT_PIN8_Min (0x0UL)                  /*!< Min enumerator value of PIN8 field.                                  */
23158   #define GPIO_OUT_PIN8_Max (0x1UL)                  /*!< Max enumerator value of PIN8 field.                                  */
23159   #define GPIO_OUT_PIN8_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23160   #define GPIO_OUT_PIN8_High (0x1UL)                 /*!< Pin driver is high                                                   */
23161 
23162 /* PIN9 @Bit 9 : Pin 9 */
23163   #define GPIO_OUT_PIN9_Pos (9UL)                    /*!< Position of PIN9 field.                                              */
23164   #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field.                                          */
23165   #define GPIO_OUT_PIN9_Min (0x0UL)                  /*!< Min enumerator value of PIN9 field.                                  */
23166   #define GPIO_OUT_PIN9_Max (0x1UL)                  /*!< Max enumerator value of PIN9 field.                                  */
23167   #define GPIO_OUT_PIN9_Low (0x0UL)                  /*!< Pin driver is low                                                    */
23168   #define GPIO_OUT_PIN9_High (0x1UL)                 /*!< Pin driver is high                                                   */
23169 
23170 /* PIN10 @Bit 10 : Pin 10 */
23171   #define GPIO_OUT_PIN10_Pos (10UL)                  /*!< Position of PIN10 field.                                             */
23172   #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field.                                       */
23173   #define GPIO_OUT_PIN10_Min (0x0UL)                 /*!< Min enumerator value of PIN10 field.                                 */
23174   #define GPIO_OUT_PIN10_Max (0x1UL)                 /*!< Max enumerator value of PIN10 field.                                 */
23175   #define GPIO_OUT_PIN10_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23176   #define GPIO_OUT_PIN10_High (0x1UL)                /*!< Pin driver is high                                                   */
23177 
23178 /* PIN11 @Bit 11 : Pin 11 */
23179   #define GPIO_OUT_PIN11_Pos (11UL)                  /*!< Position of PIN11 field.                                             */
23180   #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field.                                       */
23181   #define GPIO_OUT_PIN11_Min (0x0UL)                 /*!< Min enumerator value of PIN11 field.                                 */
23182   #define GPIO_OUT_PIN11_Max (0x1UL)                 /*!< Max enumerator value of PIN11 field.                                 */
23183   #define GPIO_OUT_PIN11_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23184   #define GPIO_OUT_PIN11_High (0x1UL)                /*!< Pin driver is high                                                   */
23185 
23186 /* PIN12 @Bit 12 : Pin 12 */
23187   #define GPIO_OUT_PIN12_Pos (12UL)                  /*!< Position of PIN12 field.                                             */
23188   #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field.                                       */
23189   #define GPIO_OUT_PIN12_Min (0x0UL)                 /*!< Min enumerator value of PIN12 field.                                 */
23190   #define GPIO_OUT_PIN12_Max (0x1UL)                 /*!< Max enumerator value of PIN12 field.                                 */
23191   #define GPIO_OUT_PIN12_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23192   #define GPIO_OUT_PIN12_High (0x1UL)                /*!< Pin driver is high                                                   */
23193 
23194 /* PIN13 @Bit 13 : Pin 13 */
23195   #define GPIO_OUT_PIN13_Pos (13UL)                  /*!< Position of PIN13 field.                                             */
23196   #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field.                                       */
23197   #define GPIO_OUT_PIN13_Min (0x0UL)                 /*!< Min enumerator value of PIN13 field.                                 */
23198   #define GPIO_OUT_PIN13_Max (0x1UL)                 /*!< Max enumerator value of PIN13 field.                                 */
23199   #define GPIO_OUT_PIN13_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23200   #define GPIO_OUT_PIN13_High (0x1UL)                /*!< Pin driver is high                                                   */
23201 
23202 /* PIN14 @Bit 14 : Pin 14 */
23203   #define GPIO_OUT_PIN14_Pos (14UL)                  /*!< Position of PIN14 field.                                             */
23204   #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field.                                       */
23205   #define GPIO_OUT_PIN14_Min (0x0UL)                 /*!< Min enumerator value of PIN14 field.                                 */
23206   #define GPIO_OUT_PIN14_Max (0x1UL)                 /*!< Max enumerator value of PIN14 field.                                 */
23207   #define GPIO_OUT_PIN14_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23208   #define GPIO_OUT_PIN14_High (0x1UL)                /*!< Pin driver is high                                                   */
23209 
23210 /* PIN15 @Bit 15 : Pin 15 */
23211   #define GPIO_OUT_PIN15_Pos (15UL)                  /*!< Position of PIN15 field.                                             */
23212   #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field.                                       */
23213   #define GPIO_OUT_PIN15_Min (0x0UL)                 /*!< Min enumerator value of PIN15 field.                                 */
23214   #define GPIO_OUT_PIN15_Max (0x1UL)                 /*!< Max enumerator value of PIN15 field.                                 */
23215   #define GPIO_OUT_PIN15_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23216   #define GPIO_OUT_PIN15_High (0x1UL)                /*!< Pin driver is high                                                   */
23217 
23218 /* PIN16 @Bit 16 : Pin 16 */
23219   #define GPIO_OUT_PIN16_Pos (16UL)                  /*!< Position of PIN16 field.                                             */
23220   #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field.                                       */
23221   #define GPIO_OUT_PIN16_Min (0x0UL)                 /*!< Min enumerator value of PIN16 field.                                 */
23222   #define GPIO_OUT_PIN16_Max (0x1UL)                 /*!< Max enumerator value of PIN16 field.                                 */
23223   #define GPIO_OUT_PIN16_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23224   #define GPIO_OUT_PIN16_High (0x1UL)                /*!< Pin driver is high                                                   */
23225 
23226 /* PIN17 @Bit 17 : Pin 17 */
23227   #define GPIO_OUT_PIN17_Pos (17UL)                  /*!< Position of PIN17 field.                                             */
23228   #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field.                                       */
23229   #define GPIO_OUT_PIN17_Min (0x0UL)                 /*!< Min enumerator value of PIN17 field.                                 */
23230   #define GPIO_OUT_PIN17_Max (0x1UL)                 /*!< Max enumerator value of PIN17 field.                                 */
23231   #define GPIO_OUT_PIN17_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23232   #define GPIO_OUT_PIN17_High (0x1UL)                /*!< Pin driver is high                                                   */
23233 
23234 /* PIN18 @Bit 18 : Pin 18 */
23235   #define GPIO_OUT_PIN18_Pos (18UL)                  /*!< Position of PIN18 field.                                             */
23236   #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field.                                       */
23237   #define GPIO_OUT_PIN18_Min (0x0UL)                 /*!< Min enumerator value of PIN18 field.                                 */
23238   #define GPIO_OUT_PIN18_Max (0x1UL)                 /*!< Max enumerator value of PIN18 field.                                 */
23239   #define GPIO_OUT_PIN18_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23240   #define GPIO_OUT_PIN18_High (0x1UL)                /*!< Pin driver is high                                                   */
23241 
23242 /* PIN19 @Bit 19 : Pin 19 */
23243   #define GPIO_OUT_PIN19_Pos (19UL)                  /*!< Position of PIN19 field.                                             */
23244   #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field.                                       */
23245   #define GPIO_OUT_PIN19_Min (0x0UL)                 /*!< Min enumerator value of PIN19 field.                                 */
23246   #define GPIO_OUT_PIN19_Max (0x1UL)                 /*!< Max enumerator value of PIN19 field.                                 */
23247   #define GPIO_OUT_PIN19_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23248   #define GPIO_OUT_PIN19_High (0x1UL)                /*!< Pin driver is high                                                   */
23249 
23250 /* PIN20 @Bit 20 : Pin 20 */
23251   #define GPIO_OUT_PIN20_Pos (20UL)                  /*!< Position of PIN20 field.                                             */
23252   #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field.                                       */
23253   #define GPIO_OUT_PIN20_Min (0x0UL)                 /*!< Min enumerator value of PIN20 field.                                 */
23254   #define GPIO_OUT_PIN20_Max (0x1UL)                 /*!< Max enumerator value of PIN20 field.                                 */
23255   #define GPIO_OUT_PIN20_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23256   #define GPIO_OUT_PIN20_High (0x1UL)                /*!< Pin driver is high                                                   */
23257 
23258 /* PIN21 @Bit 21 : Pin 21 */
23259   #define GPIO_OUT_PIN21_Pos (21UL)                  /*!< Position of PIN21 field.                                             */
23260   #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field.                                       */
23261   #define GPIO_OUT_PIN21_Min (0x0UL)                 /*!< Min enumerator value of PIN21 field.                                 */
23262   #define GPIO_OUT_PIN21_Max (0x1UL)                 /*!< Max enumerator value of PIN21 field.                                 */
23263   #define GPIO_OUT_PIN21_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23264   #define GPIO_OUT_PIN21_High (0x1UL)                /*!< Pin driver is high                                                   */
23265 
23266 /* PIN22 @Bit 22 : Pin 22 */
23267   #define GPIO_OUT_PIN22_Pos (22UL)                  /*!< Position of PIN22 field.                                             */
23268   #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field.                                       */
23269   #define GPIO_OUT_PIN22_Min (0x0UL)                 /*!< Min enumerator value of PIN22 field.                                 */
23270   #define GPIO_OUT_PIN22_Max (0x1UL)                 /*!< Max enumerator value of PIN22 field.                                 */
23271   #define GPIO_OUT_PIN22_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23272   #define GPIO_OUT_PIN22_High (0x1UL)                /*!< Pin driver is high                                                   */
23273 
23274 /* PIN23 @Bit 23 : Pin 23 */
23275   #define GPIO_OUT_PIN23_Pos (23UL)                  /*!< Position of PIN23 field.                                             */
23276   #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field.                                       */
23277   #define GPIO_OUT_PIN23_Min (0x0UL)                 /*!< Min enumerator value of PIN23 field.                                 */
23278   #define GPIO_OUT_PIN23_Max (0x1UL)                 /*!< Max enumerator value of PIN23 field.                                 */
23279   #define GPIO_OUT_PIN23_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23280   #define GPIO_OUT_PIN23_High (0x1UL)                /*!< Pin driver is high                                                   */
23281 
23282 /* PIN24 @Bit 24 : Pin 24 */
23283   #define GPIO_OUT_PIN24_Pos (24UL)                  /*!< Position of PIN24 field.                                             */
23284   #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field.                                       */
23285   #define GPIO_OUT_PIN24_Min (0x0UL)                 /*!< Min enumerator value of PIN24 field.                                 */
23286   #define GPIO_OUT_PIN24_Max (0x1UL)                 /*!< Max enumerator value of PIN24 field.                                 */
23287   #define GPIO_OUT_PIN24_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23288   #define GPIO_OUT_PIN24_High (0x1UL)                /*!< Pin driver is high                                                   */
23289 
23290 /* PIN25 @Bit 25 : Pin 25 */
23291   #define GPIO_OUT_PIN25_Pos (25UL)                  /*!< Position of PIN25 field.                                             */
23292   #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field.                                       */
23293   #define GPIO_OUT_PIN25_Min (0x0UL)                 /*!< Min enumerator value of PIN25 field.                                 */
23294   #define GPIO_OUT_PIN25_Max (0x1UL)                 /*!< Max enumerator value of PIN25 field.                                 */
23295   #define GPIO_OUT_PIN25_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23296   #define GPIO_OUT_PIN25_High (0x1UL)                /*!< Pin driver is high                                                   */
23297 
23298 /* PIN26 @Bit 26 : Pin 26 */
23299   #define GPIO_OUT_PIN26_Pos (26UL)                  /*!< Position of PIN26 field.                                             */
23300   #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field.                                       */
23301   #define GPIO_OUT_PIN26_Min (0x0UL)                 /*!< Min enumerator value of PIN26 field.                                 */
23302   #define GPIO_OUT_PIN26_Max (0x1UL)                 /*!< Max enumerator value of PIN26 field.                                 */
23303   #define GPIO_OUT_PIN26_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23304   #define GPIO_OUT_PIN26_High (0x1UL)                /*!< Pin driver is high                                                   */
23305 
23306 /* PIN27 @Bit 27 : Pin 27 */
23307   #define GPIO_OUT_PIN27_Pos (27UL)                  /*!< Position of PIN27 field.                                             */
23308   #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field.                                       */
23309   #define GPIO_OUT_PIN27_Min (0x0UL)                 /*!< Min enumerator value of PIN27 field.                                 */
23310   #define GPIO_OUT_PIN27_Max (0x1UL)                 /*!< Max enumerator value of PIN27 field.                                 */
23311   #define GPIO_OUT_PIN27_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23312   #define GPIO_OUT_PIN27_High (0x1UL)                /*!< Pin driver is high                                                   */
23313 
23314 /* PIN28 @Bit 28 : Pin 28 */
23315   #define GPIO_OUT_PIN28_Pos (28UL)                  /*!< Position of PIN28 field.                                             */
23316   #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field.                                       */
23317   #define GPIO_OUT_PIN28_Min (0x0UL)                 /*!< Min enumerator value of PIN28 field.                                 */
23318   #define GPIO_OUT_PIN28_Max (0x1UL)                 /*!< Max enumerator value of PIN28 field.                                 */
23319   #define GPIO_OUT_PIN28_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23320   #define GPIO_OUT_PIN28_High (0x1UL)                /*!< Pin driver is high                                                   */
23321 
23322 /* PIN29 @Bit 29 : Pin 29 */
23323   #define GPIO_OUT_PIN29_Pos (29UL)                  /*!< Position of PIN29 field.                                             */
23324   #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field.                                       */
23325   #define GPIO_OUT_PIN29_Min (0x0UL)                 /*!< Min enumerator value of PIN29 field.                                 */
23326   #define GPIO_OUT_PIN29_Max (0x1UL)                 /*!< Max enumerator value of PIN29 field.                                 */
23327   #define GPIO_OUT_PIN29_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23328   #define GPIO_OUT_PIN29_High (0x1UL)                /*!< Pin driver is high                                                   */
23329 
23330 /* PIN30 @Bit 30 : Pin 30 */
23331   #define GPIO_OUT_PIN30_Pos (30UL)                  /*!< Position of PIN30 field.                                             */
23332   #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field.                                       */
23333   #define GPIO_OUT_PIN30_Min (0x0UL)                 /*!< Min enumerator value of PIN30 field.                                 */
23334   #define GPIO_OUT_PIN30_Max (0x1UL)                 /*!< Max enumerator value of PIN30 field.                                 */
23335   #define GPIO_OUT_PIN30_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23336   #define GPIO_OUT_PIN30_High (0x1UL)                /*!< Pin driver is high                                                   */
23337 
23338 /* PIN31 @Bit 31 : Pin 31 */
23339   #define GPIO_OUT_PIN31_Pos (31UL)                  /*!< Position of PIN31 field.                                             */
23340   #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field.                                       */
23341   #define GPIO_OUT_PIN31_Min (0x0UL)                 /*!< Min enumerator value of PIN31 field.                                 */
23342   #define GPIO_OUT_PIN31_Max (0x1UL)                 /*!< Max enumerator value of PIN31 field.                                 */
23343   #define GPIO_OUT_PIN31_Low (0x0UL)                 /*!< Pin driver is low                                                    */
23344   #define GPIO_OUT_PIN31_High (0x1UL)                /*!< Pin driver is high                                                   */
23345 
23346 
23347 /* GPIO_OUTSET: Set individual bits in GPIO port */
23348   #define GPIO_OUTSET_ResetValue (0x00000000UL)      /*!< Reset value of OUTSET register.                                      */
23349 
23350 /* PIN0 @Bit 0 : Pin 0 */
23351   #define GPIO_OUTSET_PIN0_Pos (0UL)                 /*!< Position of PIN0 field.                                              */
23352   #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field.                                    */
23353   #define GPIO_OUTSET_PIN0_Min (0x0UL)               /*!< Min enumerator value of PIN0 field.                                  */
23354   #define GPIO_OUTSET_PIN0_Max (0x1UL)               /*!< Max enumerator value of PIN0 field.                                  */
23355   #define GPIO_OUTSET_PIN0_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23356   #define GPIO_OUTSET_PIN0_High (0x1UL)              /*!< Read: pin driver is high                                             */
23357   #define GPIO_OUTSET_PIN0_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23358 
23359 /* PIN1 @Bit 1 : Pin 1 */
23360   #define GPIO_OUTSET_PIN1_Pos (1UL)                 /*!< Position of PIN1 field.                                              */
23361   #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field.                                    */
23362   #define GPIO_OUTSET_PIN1_Min (0x0UL)               /*!< Min enumerator value of PIN1 field.                                  */
23363   #define GPIO_OUTSET_PIN1_Max (0x1UL)               /*!< Max enumerator value of PIN1 field.                                  */
23364   #define GPIO_OUTSET_PIN1_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23365   #define GPIO_OUTSET_PIN1_High (0x1UL)              /*!< Read: pin driver is high                                             */
23366   #define GPIO_OUTSET_PIN1_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23367 
23368 /* PIN2 @Bit 2 : Pin 2 */
23369   #define GPIO_OUTSET_PIN2_Pos (2UL)                 /*!< Position of PIN2 field.                                              */
23370   #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field.                                    */
23371   #define GPIO_OUTSET_PIN2_Min (0x0UL)               /*!< Min enumerator value of PIN2 field.                                  */
23372   #define GPIO_OUTSET_PIN2_Max (0x1UL)               /*!< Max enumerator value of PIN2 field.                                  */
23373   #define GPIO_OUTSET_PIN2_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23374   #define GPIO_OUTSET_PIN2_High (0x1UL)              /*!< Read: pin driver is high                                             */
23375   #define GPIO_OUTSET_PIN2_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23376 
23377 /* PIN3 @Bit 3 : Pin 3 */
23378   #define GPIO_OUTSET_PIN3_Pos (3UL)                 /*!< Position of PIN3 field.                                              */
23379   #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field.                                    */
23380   #define GPIO_OUTSET_PIN3_Min (0x0UL)               /*!< Min enumerator value of PIN3 field.                                  */
23381   #define GPIO_OUTSET_PIN3_Max (0x1UL)               /*!< Max enumerator value of PIN3 field.                                  */
23382   #define GPIO_OUTSET_PIN3_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23383   #define GPIO_OUTSET_PIN3_High (0x1UL)              /*!< Read: pin driver is high                                             */
23384   #define GPIO_OUTSET_PIN3_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23385 
23386 /* PIN4 @Bit 4 : Pin 4 */
23387   #define GPIO_OUTSET_PIN4_Pos (4UL)                 /*!< Position of PIN4 field.                                              */
23388   #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field.                                    */
23389   #define GPIO_OUTSET_PIN4_Min (0x0UL)               /*!< Min enumerator value of PIN4 field.                                  */
23390   #define GPIO_OUTSET_PIN4_Max (0x1UL)               /*!< Max enumerator value of PIN4 field.                                  */
23391   #define GPIO_OUTSET_PIN4_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23392   #define GPIO_OUTSET_PIN4_High (0x1UL)              /*!< Read: pin driver is high                                             */
23393   #define GPIO_OUTSET_PIN4_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23394 
23395 /* PIN5 @Bit 5 : Pin 5 */
23396   #define GPIO_OUTSET_PIN5_Pos (5UL)                 /*!< Position of PIN5 field.                                              */
23397   #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field.                                    */
23398   #define GPIO_OUTSET_PIN5_Min (0x0UL)               /*!< Min enumerator value of PIN5 field.                                  */
23399   #define GPIO_OUTSET_PIN5_Max (0x1UL)               /*!< Max enumerator value of PIN5 field.                                  */
23400   #define GPIO_OUTSET_PIN5_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23401   #define GPIO_OUTSET_PIN5_High (0x1UL)              /*!< Read: pin driver is high                                             */
23402   #define GPIO_OUTSET_PIN5_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23403 
23404 /* PIN6 @Bit 6 : Pin 6 */
23405   #define GPIO_OUTSET_PIN6_Pos (6UL)                 /*!< Position of PIN6 field.                                              */
23406   #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field.                                    */
23407   #define GPIO_OUTSET_PIN6_Min (0x0UL)               /*!< Min enumerator value of PIN6 field.                                  */
23408   #define GPIO_OUTSET_PIN6_Max (0x1UL)               /*!< Max enumerator value of PIN6 field.                                  */
23409   #define GPIO_OUTSET_PIN6_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23410   #define GPIO_OUTSET_PIN6_High (0x1UL)              /*!< Read: pin driver is high                                             */
23411   #define GPIO_OUTSET_PIN6_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23412 
23413 /* PIN7 @Bit 7 : Pin 7 */
23414   #define GPIO_OUTSET_PIN7_Pos (7UL)                 /*!< Position of PIN7 field.                                              */
23415   #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field.                                    */
23416   #define GPIO_OUTSET_PIN7_Min (0x0UL)               /*!< Min enumerator value of PIN7 field.                                  */
23417   #define GPIO_OUTSET_PIN7_Max (0x1UL)               /*!< Max enumerator value of PIN7 field.                                  */
23418   #define GPIO_OUTSET_PIN7_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23419   #define GPIO_OUTSET_PIN7_High (0x1UL)              /*!< Read: pin driver is high                                             */
23420   #define GPIO_OUTSET_PIN7_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23421 
23422 /* PIN8 @Bit 8 : Pin 8 */
23423   #define GPIO_OUTSET_PIN8_Pos (8UL)                 /*!< Position of PIN8 field.                                              */
23424   #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field.                                    */
23425   #define GPIO_OUTSET_PIN8_Min (0x0UL)               /*!< Min enumerator value of PIN8 field.                                  */
23426   #define GPIO_OUTSET_PIN8_Max (0x1UL)               /*!< Max enumerator value of PIN8 field.                                  */
23427   #define GPIO_OUTSET_PIN8_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23428   #define GPIO_OUTSET_PIN8_High (0x1UL)              /*!< Read: pin driver is high                                             */
23429   #define GPIO_OUTSET_PIN8_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23430 
23431 /* PIN9 @Bit 9 : Pin 9 */
23432   #define GPIO_OUTSET_PIN9_Pos (9UL)                 /*!< Position of PIN9 field.                                              */
23433   #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field.                                    */
23434   #define GPIO_OUTSET_PIN9_Min (0x0UL)               /*!< Min enumerator value of PIN9 field.                                  */
23435   #define GPIO_OUTSET_PIN9_Max (0x1UL)               /*!< Max enumerator value of PIN9 field.                                  */
23436   #define GPIO_OUTSET_PIN9_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23437   #define GPIO_OUTSET_PIN9_High (0x1UL)              /*!< Read: pin driver is high                                             */
23438   #define GPIO_OUTSET_PIN9_Set (0x1UL)               /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23439 
23440 /* PIN10 @Bit 10 : Pin 10 */
23441   #define GPIO_OUTSET_PIN10_Pos (10UL)               /*!< Position of PIN10 field.                                             */
23442   #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field.                                 */
23443   #define GPIO_OUTSET_PIN10_Min (0x0UL)              /*!< Min enumerator value of PIN10 field.                                 */
23444   #define GPIO_OUTSET_PIN10_Max (0x1UL)              /*!< Max enumerator value of PIN10 field.                                 */
23445   #define GPIO_OUTSET_PIN10_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23446   #define GPIO_OUTSET_PIN10_High (0x1UL)             /*!< Read: pin driver is high                                             */
23447   #define GPIO_OUTSET_PIN10_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23448 
23449 /* PIN11 @Bit 11 : Pin 11 */
23450   #define GPIO_OUTSET_PIN11_Pos (11UL)               /*!< Position of PIN11 field.                                             */
23451   #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field.                                 */
23452   #define GPIO_OUTSET_PIN11_Min (0x0UL)              /*!< Min enumerator value of PIN11 field.                                 */
23453   #define GPIO_OUTSET_PIN11_Max (0x1UL)              /*!< Max enumerator value of PIN11 field.                                 */
23454   #define GPIO_OUTSET_PIN11_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23455   #define GPIO_OUTSET_PIN11_High (0x1UL)             /*!< Read: pin driver is high                                             */
23456   #define GPIO_OUTSET_PIN11_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23457 
23458 /* PIN12 @Bit 12 : Pin 12 */
23459   #define GPIO_OUTSET_PIN12_Pos (12UL)               /*!< Position of PIN12 field.                                             */
23460   #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field.                                 */
23461   #define GPIO_OUTSET_PIN12_Min (0x0UL)              /*!< Min enumerator value of PIN12 field.                                 */
23462   #define GPIO_OUTSET_PIN12_Max (0x1UL)              /*!< Max enumerator value of PIN12 field.                                 */
23463   #define GPIO_OUTSET_PIN12_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23464   #define GPIO_OUTSET_PIN12_High (0x1UL)             /*!< Read: pin driver is high                                             */
23465   #define GPIO_OUTSET_PIN12_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23466 
23467 /* PIN13 @Bit 13 : Pin 13 */
23468   #define GPIO_OUTSET_PIN13_Pos (13UL)               /*!< Position of PIN13 field.                                             */
23469   #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field.                                 */
23470   #define GPIO_OUTSET_PIN13_Min (0x0UL)              /*!< Min enumerator value of PIN13 field.                                 */
23471   #define GPIO_OUTSET_PIN13_Max (0x1UL)              /*!< Max enumerator value of PIN13 field.                                 */
23472   #define GPIO_OUTSET_PIN13_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23473   #define GPIO_OUTSET_PIN13_High (0x1UL)             /*!< Read: pin driver is high                                             */
23474   #define GPIO_OUTSET_PIN13_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23475 
23476 /* PIN14 @Bit 14 : Pin 14 */
23477   #define GPIO_OUTSET_PIN14_Pos (14UL)               /*!< Position of PIN14 field.                                             */
23478   #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field.                                 */
23479   #define GPIO_OUTSET_PIN14_Min (0x0UL)              /*!< Min enumerator value of PIN14 field.                                 */
23480   #define GPIO_OUTSET_PIN14_Max (0x1UL)              /*!< Max enumerator value of PIN14 field.                                 */
23481   #define GPIO_OUTSET_PIN14_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23482   #define GPIO_OUTSET_PIN14_High (0x1UL)             /*!< Read: pin driver is high                                             */
23483   #define GPIO_OUTSET_PIN14_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23484 
23485 /* PIN15 @Bit 15 : Pin 15 */
23486   #define GPIO_OUTSET_PIN15_Pos (15UL)               /*!< Position of PIN15 field.                                             */
23487   #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field.                                 */
23488   #define GPIO_OUTSET_PIN15_Min (0x0UL)              /*!< Min enumerator value of PIN15 field.                                 */
23489   #define GPIO_OUTSET_PIN15_Max (0x1UL)              /*!< Max enumerator value of PIN15 field.                                 */
23490   #define GPIO_OUTSET_PIN15_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23491   #define GPIO_OUTSET_PIN15_High (0x1UL)             /*!< Read: pin driver is high                                             */
23492   #define GPIO_OUTSET_PIN15_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23493 
23494 /* PIN16 @Bit 16 : Pin 16 */
23495   #define GPIO_OUTSET_PIN16_Pos (16UL)               /*!< Position of PIN16 field.                                             */
23496   #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field.                                 */
23497   #define GPIO_OUTSET_PIN16_Min (0x0UL)              /*!< Min enumerator value of PIN16 field.                                 */
23498   #define GPIO_OUTSET_PIN16_Max (0x1UL)              /*!< Max enumerator value of PIN16 field.                                 */
23499   #define GPIO_OUTSET_PIN16_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23500   #define GPIO_OUTSET_PIN16_High (0x1UL)             /*!< Read: pin driver is high                                             */
23501   #define GPIO_OUTSET_PIN16_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23502 
23503 /* PIN17 @Bit 17 : Pin 17 */
23504   #define GPIO_OUTSET_PIN17_Pos (17UL)               /*!< Position of PIN17 field.                                             */
23505   #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field.                                 */
23506   #define GPIO_OUTSET_PIN17_Min (0x0UL)              /*!< Min enumerator value of PIN17 field.                                 */
23507   #define GPIO_OUTSET_PIN17_Max (0x1UL)              /*!< Max enumerator value of PIN17 field.                                 */
23508   #define GPIO_OUTSET_PIN17_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23509   #define GPIO_OUTSET_PIN17_High (0x1UL)             /*!< Read: pin driver is high                                             */
23510   #define GPIO_OUTSET_PIN17_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23511 
23512 /* PIN18 @Bit 18 : Pin 18 */
23513   #define GPIO_OUTSET_PIN18_Pos (18UL)               /*!< Position of PIN18 field.                                             */
23514   #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field.                                 */
23515   #define GPIO_OUTSET_PIN18_Min (0x0UL)              /*!< Min enumerator value of PIN18 field.                                 */
23516   #define GPIO_OUTSET_PIN18_Max (0x1UL)              /*!< Max enumerator value of PIN18 field.                                 */
23517   #define GPIO_OUTSET_PIN18_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23518   #define GPIO_OUTSET_PIN18_High (0x1UL)             /*!< Read: pin driver is high                                             */
23519   #define GPIO_OUTSET_PIN18_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23520 
23521 /* PIN19 @Bit 19 : Pin 19 */
23522   #define GPIO_OUTSET_PIN19_Pos (19UL)               /*!< Position of PIN19 field.                                             */
23523   #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field.                                 */
23524   #define GPIO_OUTSET_PIN19_Min (0x0UL)              /*!< Min enumerator value of PIN19 field.                                 */
23525   #define GPIO_OUTSET_PIN19_Max (0x1UL)              /*!< Max enumerator value of PIN19 field.                                 */
23526   #define GPIO_OUTSET_PIN19_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23527   #define GPIO_OUTSET_PIN19_High (0x1UL)             /*!< Read: pin driver is high                                             */
23528   #define GPIO_OUTSET_PIN19_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23529 
23530 /* PIN20 @Bit 20 : Pin 20 */
23531   #define GPIO_OUTSET_PIN20_Pos (20UL)               /*!< Position of PIN20 field.                                             */
23532   #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field.                                 */
23533   #define GPIO_OUTSET_PIN20_Min (0x0UL)              /*!< Min enumerator value of PIN20 field.                                 */
23534   #define GPIO_OUTSET_PIN20_Max (0x1UL)              /*!< Max enumerator value of PIN20 field.                                 */
23535   #define GPIO_OUTSET_PIN20_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23536   #define GPIO_OUTSET_PIN20_High (0x1UL)             /*!< Read: pin driver is high                                             */
23537   #define GPIO_OUTSET_PIN20_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23538 
23539 /* PIN21 @Bit 21 : Pin 21 */
23540   #define GPIO_OUTSET_PIN21_Pos (21UL)               /*!< Position of PIN21 field.                                             */
23541   #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field.                                 */
23542   #define GPIO_OUTSET_PIN21_Min (0x0UL)              /*!< Min enumerator value of PIN21 field.                                 */
23543   #define GPIO_OUTSET_PIN21_Max (0x1UL)              /*!< Max enumerator value of PIN21 field.                                 */
23544   #define GPIO_OUTSET_PIN21_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23545   #define GPIO_OUTSET_PIN21_High (0x1UL)             /*!< Read: pin driver is high                                             */
23546   #define GPIO_OUTSET_PIN21_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23547 
23548 /* PIN22 @Bit 22 : Pin 22 */
23549   #define GPIO_OUTSET_PIN22_Pos (22UL)               /*!< Position of PIN22 field.                                             */
23550   #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field.                                 */
23551   #define GPIO_OUTSET_PIN22_Min (0x0UL)              /*!< Min enumerator value of PIN22 field.                                 */
23552   #define GPIO_OUTSET_PIN22_Max (0x1UL)              /*!< Max enumerator value of PIN22 field.                                 */
23553   #define GPIO_OUTSET_PIN22_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23554   #define GPIO_OUTSET_PIN22_High (0x1UL)             /*!< Read: pin driver is high                                             */
23555   #define GPIO_OUTSET_PIN22_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23556 
23557 /* PIN23 @Bit 23 : Pin 23 */
23558   #define GPIO_OUTSET_PIN23_Pos (23UL)               /*!< Position of PIN23 field.                                             */
23559   #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field.                                 */
23560   #define GPIO_OUTSET_PIN23_Min (0x0UL)              /*!< Min enumerator value of PIN23 field.                                 */
23561   #define GPIO_OUTSET_PIN23_Max (0x1UL)              /*!< Max enumerator value of PIN23 field.                                 */
23562   #define GPIO_OUTSET_PIN23_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23563   #define GPIO_OUTSET_PIN23_High (0x1UL)             /*!< Read: pin driver is high                                             */
23564   #define GPIO_OUTSET_PIN23_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23565 
23566 /* PIN24 @Bit 24 : Pin 24 */
23567   #define GPIO_OUTSET_PIN24_Pos (24UL)               /*!< Position of PIN24 field.                                             */
23568   #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field.                                 */
23569   #define GPIO_OUTSET_PIN24_Min (0x0UL)              /*!< Min enumerator value of PIN24 field.                                 */
23570   #define GPIO_OUTSET_PIN24_Max (0x1UL)              /*!< Max enumerator value of PIN24 field.                                 */
23571   #define GPIO_OUTSET_PIN24_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23572   #define GPIO_OUTSET_PIN24_High (0x1UL)             /*!< Read: pin driver is high                                             */
23573   #define GPIO_OUTSET_PIN24_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23574 
23575 /* PIN25 @Bit 25 : Pin 25 */
23576   #define GPIO_OUTSET_PIN25_Pos (25UL)               /*!< Position of PIN25 field.                                             */
23577   #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field.                                 */
23578   #define GPIO_OUTSET_PIN25_Min (0x0UL)              /*!< Min enumerator value of PIN25 field.                                 */
23579   #define GPIO_OUTSET_PIN25_Max (0x1UL)              /*!< Max enumerator value of PIN25 field.                                 */
23580   #define GPIO_OUTSET_PIN25_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23581   #define GPIO_OUTSET_PIN25_High (0x1UL)             /*!< Read: pin driver is high                                             */
23582   #define GPIO_OUTSET_PIN25_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23583 
23584 /* PIN26 @Bit 26 : Pin 26 */
23585   #define GPIO_OUTSET_PIN26_Pos (26UL)               /*!< Position of PIN26 field.                                             */
23586   #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field.                                 */
23587   #define GPIO_OUTSET_PIN26_Min (0x0UL)              /*!< Min enumerator value of PIN26 field.                                 */
23588   #define GPIO_OUTSET_PIN26_Max (0x1UL)              /*!< Max enumerator value of PIN26 field.                                 */
23589   #define GPIO_OUTSET_PIN26_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23590   #define GPIO_OUTSET_PIN26_High (0x1UL)             /*!< Read: pin driver is high                                             */
23591   #define GPIO_OUTSET_PIN26_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23592 
23593 /* PIN27 @Bit 27 : Pin 27 */
23594   #define GPIO_OUTSET_PIN27_Pos (27UL)               /*!< Position of PIN27 field.                                             */
23595   #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field.                                 */
23596   #define GPIO_OUTSET_PIN27_Min (0x0UL)              /*!< Min enumerator value of PIN27 field.                                 */
23597   #define GPIO_OUTSET_PIN27_Max (0x1UL)              /*!< Max enumerator value of PIN27 field.                                 */
23598   #define GPIO_OUTSET_PIN27_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23599   #define GPIO_OUTSET_PIN27_High (0x1UL)             /*!< Read: pin driver is high                                             */
23600   #define GPIO_OUTSET_PIN27_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23601 
23602 /* PIN28 @Bit 28 : Pin 28 */
23603   #define GPIO_OUTSET_PIN28_Pos (28UL)               /*!< Position of PIN28 field.                                             */
23604   #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field.                                 */
23605   #define GPIO_OUTSET_PIN28_Min (0x0UL)              /*!< Min enumerator value of PIN28 field.                                 */
23606   #define GPIO_OUTSET_PIN28_Max (0x1UL)              /*!< Max enumerator value of PIN28 field.                                 */
23607   #define GPIO_OUTSET_PIN28_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23608   #define GPIO_OUTSET_PIN28_High (0x1UL)             /*!< Read: pin driver is high                                             */
23609   #define GPIO_OUTSET_PIN28_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23610 
23611 /* PIN29 @Bit 29 : Pin 29 */
23612   #define GPIO_OUTSET_PIN29_Pos (29UL)               /*!< Position of PIN29 field.                                             */
23613   #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field.                                 */
23614   #define GPIO_OUTSET_PIN29_Min (0x0UL)              /*!< Min enumerator value of PIN29 field.                                 */
23615   #define GPIO_OUTSET_PIN29_Max (0x1UL)              /*!< Max enumerator value of PIN29 field.                                 */
23616   #define GPIO_OUTSET_PIN29_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23617   #define GPIO_OUTSET_PIN29_High (0x1UL)             /*!< Read: pin driver is high                                             */
23618   #define GPIO_OUTSET_PIN29_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23619 
23620 /* PIN30 @Bit 30 : Pin 30 */
23621   #define GPIO_OUTSET_PIN30_Pos (30UL)               /*!< Position of PIN30 field.                                             */
23622   #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field.                                 */
23623   #define GPIO_OUTSET_PIN30_Min (0x0UL)              /*!< Min enumerator value of PIN30 field.                                 */
23624   #define GPIO_OUTSET_PIN30_Max (0x1UL)              /*!< Max enumerator value of PIN30 field.                                 */
23625   #define GPIO_OUTSET_PIN30_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23626   #define GPIO_OUTSET_PIN30_High (0x1UL)             /*!< Read: pin driver is high                                             */
23627   #define GPIO_OUTSET_PIN30_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23628 
23629 /* PIN31 @Bit 31 : Pin 31 */
23630   #define GPIO_OUTSET_PIN31_Pos (31UL)               /*!< Position of PIN31 field.                                             */
23631   #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field.                                 */
23632   #define GPIO_OUTSET_PIN31_Min (0x0UL)              /*!< Min enumerator value of PIN31 field.                                 */
23633   #define GPIO_OUTSET_PIN31_Max (0x1UL)              /*!< Max enumerator value of PIN31 field.                                 */
23634   #define GPIO_OUTSET_PIN31_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23635   #define GPIO_OUTSET_PIN31_High (0x1UL)             /*!< Read: pin driver is high                                             */
23636   #define GPIO_OUTSET_PIN31_Set (0x1UL)              /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect  */
23637 
23638 
23639 /* GPIO_OUTCLR: Clear individual bits in GPIO port */
23640   #define GPIO_OUTCLR_ResetValue (0x00000000UL)      /*!< Reset value of OUTCLR register.                                      */
23641 
23642 /* PIN0 @Bit 0 : Pin 0 */
23643   #define GPIO_OUTCLR_PIN0_Pos (0UL)                 /*!< Position of PIN0 field.                                              */
23644   #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field.                                    */
23645   #define GPIO_OUTCLR_PIN0_Min (0x0UL)               /*!< Min enumerator value of PIN0 field.                                  */
23646   #define GPIO_OUTCLR_PIN0_Max (0x1UL)               /*!< Max enumerator value of PIN0 field.                                  */
23647   #define GPIO_OUTCLR_PIN0_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23648   #define GPIO_OUTCLR_PIN0_High (0x1UL)              /*!< Read: pin driver is high                                             */
23649   #define GPIO_OUTCLR_PIN0_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23650 
23651 /* PIN1 @Bit 1 : Pin 1 */
23652   #define GPIO_OUTCLR_PIN1_Pos (1UL)                 /*!< Position of PIN1 field.                                              */
23653   #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field.                                    */
23654   #define GPIO_OUTCLR_PIN1_Min (0x0UL)               /*!< Min enumerator value of PIN1 field.                                  */
23655   #define GPIO_OUTCLR_PIN1_Max (0x1UL)               /*!< Max enumerator value of PIN1 field.                                  */
23656   #define GPIO_OUTCLR_PIN1_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23657   #define GPIO_OUTCLR_PIN1_High (0x1UL)              /*!< Read: pin driver is high                                             */
23658   #define GPIO_OUTCLR_PIN1_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23659 
23660 /* PIN2 @Bit 2 : Pin 2 */
23661   #define GPIO_OUTCLR_PIN2_Pos (2UL)                 /*!< Position of PIN2 field.                                              */
23662   #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field.                                    */
23663   #define GPIO_OUTCLR_PIN2_Min (0x0UL)               /*!< Min enumerator value of PIN2 field.                                  */
23664   #define GPIO_OUTCLR_PIN2_Max (0x1UL)               /*!< Max enumerator value of PIN2 field.                                  */
23665   #define GPIO_OUTCLR_PIN2_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23666   #define GPIO_OUTCLR_PIN2_High (0x1UL)              /*!< Read: pin driver is high                                             */
23667   #define GPIO_OUTCLR_PIN2_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23668 
23669 /* PIN3 @Bit 3 : Pin 3 */
23670   #define GPIO_OUTCLR_PIN3_Pos (3UL)                 /*!< Position of PIN3 field.                                              */
23671   #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field.                                    */
23672   #define GPIO_OUTCLR_PIN3_Min (0x0UL)               /*!< Min enumerator value of PIN3 field.                                  */
23673   #define GPIO_OUTCLR_PIN3_Max (0x1UL)               /*!< Max enumerator value of PIN3 field.                                  */
23674   #define GPIO_OUTCLR_PIN3_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23675   #define GPIO_OUTCLR_PIN3_High (0x1UL)              /*!< Read: pin driver is high                                             */
23676   #define GPIO_OUTCLR_PIN3_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23677 
23678 /* PIN4 @Bit 4 : Pin 4 */
23679   #define GPIO_OUTCLR_PIN4_Pos (4UL)                 /*!< Position of PIN4 field.                                              */
23680   #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field.                                    */
23681   #define GPIO_OUTCLR_PIN4_Min (0x0UL)               /*!< Min enumerator value of PIN4 field.                                  */
23682   #define GPIO_OUTCLR_PIN4_Max (0x1UL)               /*!< Max enumerator value of PIN4 field.                                  */
23683   #define GPIO_OUTCLR_PIN4_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23684   #define GPIO_OUTCLR_PIN4_High (0x1UL)              /*!< Read: pin driver is high                                             */
23685   #define GPIO_OUTCLR_PIN4_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23686 
23687 /* PIN5 @Bit 5 : Pin 5 */
23688   #define GPIO_OUTCLR_PIN5_Pos (5UL)                 /*!< Position of PIN5 field.                                              */
23689   #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field.                                    */
23690   #define GPIO_OUTCLR_PIN5_Min (0x0UL)               /*!< Min enumerator value of PIN5 field.                                  */
23691   #define GPIO_OUTCLR_PIN5_Max (0x1UL)               /*!< Max enumerator value of PIN5 field.                                  */
23692   #define GPIO_OUTCLR_PIN5_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23693   #define GPIO_OUTCLR_PIN5_High (0x1UL)              /*!< Read: pin driver is high                                             */
23694   #define GPIO_OUTCLR_PIN5_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23695 
23696 /* PIN6 @Bit 6 : Pin 6 */
23697   #define GPIO_OUTCLR_PIN6_Pos (6UL)                 /*!< Position of PIN6 field.                                              */
23698   #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field.                                    */
23699   #define GPIO_OUTCLR_PIN6_Min (0x0UL)               /*!< Min enumerator value of PIN6 field.                                  */
23700   #define GPIO_OUTCLR_PIN6_Max (0x1UL)               /*!< Max enumerator value of PIN6 field.                                  */
23701   #define GPIO_OUTCLR_PIN6_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23702   #define GPIO_OUTCLR_PIN6_High (0x1UL)              /*!< Read: pin driver is high                                             */
23703   #define GPIO_OUTCLR_PIN6_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23704 
23705 /* PIN7 @Bit 7 : Pin 7 */
23706   #define GPIO_OUTCLR_PIN7_Pos (7UL)                 /*!< Position of PIN7 field.                                              */
23707   #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field.                                    */
23708   #define GPIO_OUTCLR_PIN7_Min (0x0UL)               /*!< Min enumerator value of PIN7 field.                                  */
23709   #define GPIO_OUTCLR_PIN7_Max (0x1UL)               /*!< Max enumerator value of PIN7 field.                                  */
23710   #define GPIO_OUTCLR_PIN7_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23711   #define GPIO_OUTCLR_PIN7_High (0x1UL)              /*!< Read: pin driver is high                                             */
23712   #define GPIO_OUTCLR_PIN7_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23713 
23714 /* PIN8 @Bit 8 : Pin 8 */
23715   #define GPIO_OUTCLR_PIN8_Pos (8UL)                 /*!< Position of PIN8 field.                                              */
23716   #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field.                                    */
23717   #define GPIO_OUTCLR_PIN8_Min (0x0UL)               /*!< Min enumerator value of PIN8 field.                                  */
23718   #define GPIO_OUTCLR_PIN8_Max (0x1UL)               /*!< Max enumerator value of PIN8 field.                                  */
23719   #define GPIO_OUTCLR_PIN8_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23720   #define GPIO_OUTCLR_PIN8_High (0x1UL)              /*!< Read: pin driver is high                                             */
23721   #define GPIO_OUTCLR_PIN8_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23722 
23723 /* PIN9 @Bit 9 : Pin 9 */
23724   #define GPIO_OUTCLR_PIN9_Pos (9UL)                 /*!< Position of PIN9 field.                                              */
23725   #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field.                                    */
23726   #define GPIO_OUTCLR_PIN9_Min (0x0UL)               /*!< Min enumerator value of PIN9 field.                                  */
23727   #define GPIO_OUTCLR_PIN9_Max (0x1UL)               /*!< Max enumerator value of PIN9 field.                                  */
23728   #define GPIO_OUTCLR_PIN9_Low (0x0UL)               /*!< Read: pin driver is low                                              */
23729   #define GPIO_OUTCLR_PIN9_High (0x1UL)              /*!< Read: pin driver is high                                             */
23730   #define GPIO_OUTCLR_PIN9_Clear (0x1UL)             /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23731 
23732 /* PIN10 @Bit 10 : Pin 10 */
23733   #define GPIO_OUTCLR_PIN10_Pos (10UL)               /*!< Position of PIN10 field.                                             */
23734   #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field.                                 */
23735   #define GPIO_OUTCLR_PIN10_Min (0x0UL)              /*!< Min enumerator value of PIN10 field.                                 */
23736   #define GPIO_OUTCLR_PIN10_Max (0x1UL)              /*!< Max enumerator value of PIN10 field.                                 */
23737   #define GPIO_OUTCLR_PIN10_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23738   #define GPIO_OUTCLR_PIN10_High (0x1UL)             /*!< Read: pin driver is high                                             */
23739   #define GPIO_OUTCLR_PIN10_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23740 
23741 /* PIN11 @Bit 11 : Pin 11 */
23742   #define GPIO_OUTCLR_PIN11_Pos (11UL)               /*!< Position of PIN11 field.                                             */
23743   #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field.                                 */
23744   #define GPIO_OUTCLR_PIN11_Min (0x0UL)              /*!< Min enumerator value of PIN11 field.                                 */
23745   #define GPIO_OUTCLR_PIN11_Max (0x1UL)              /*!< Max enumerator value of PIN11 field.                                 */
23746   #define GPIO_OUTCLR_PIN11_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23747   #define GPIO_OUTCLR_PIN11_High (0x1UL)             /*!< Read: pin driver is high                                             */
23748   #define GPIO_OUTCLR_PIN11_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23749 
23750 /* PIN12 @Bit 12 : Pin 12 */
23751   #define GPIO_OUTCLR_PIN12_Pos (12UL)               /*!< Position of PIN12 field.                                             */
23752   #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field.                                 */
23753   #define GPIO_OUTCLR_PIN12_Min (0x0UL)              /*!< Min enumerator value of PIN12 field.                                 */
23754   #define GPIO_OUTCLR_PIN12_Max (0x1UL)              /*!< Max enumerator value of PIN12 field.                                 */
23755   #define GPIO_OUTCLR_PIN12_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23756   #define GPIO_OUTCLR_PIN12_High (0x1UL)             /*!< Read: pin driver is high                                             */
23757   #define GPIO_OUTCLR_PIN12_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23758 
23759 /* PIN13 @Bit 13 : Pin 13 */
23760   #define GPIO_OUTCLR_PIN13_Pos (13UL)               /*!< Position of PIN13 field.                                             */
23761   #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field.                                 */
23762   #define GPIO_OUTCLR_PIN13_Min (0x0UL)              /*!< Min enumerator value of PIN13 field.                                 */
23763   #define GPIO_OUTCLR_PIN13_Max (0x1UL)              /*!< Max enumerator value of PIN13 field.                                 */
23764   #define GPIO_OUTCLR_PIN13_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23765   #define GPIO_OUTCLR_PIN13_High (0x1UL)             /*!< Read: pin driver is high                                             */
23766   #define GPIO_OUTCLR_PIN13_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23767 
23768 /* PIN14 @Bit 14 : Pin 14 */
23769   #define GPIO_OUTCLR_PIN14_Pos (14UL)               /*!< Position of PIN14 field.                                             */
23770   #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field.                                 */
23771   #define GPIO_OUTCLR_PIN14_Min (0x0UL)              /*!< Min enumerator value of PIN14 field.                                 */
23772   #define GPIO_OUTCLR_PIN14_Max (0x1UL)              /*!< Max enumerator value of PIN14 field.                                 */
23773   #define GPIO_OUTCLR_PIN14_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23774   #define GPIO_OUTCLR_PIN14_High (0x1UL)             /*!< Read: pin driver is high                                             */
23775   #define GPIO_OUTCLR_PIN14_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23776 
23777 /* PIN15 @Bit 15 : Pin 15 */
23778   #define GPIO_OUTCLR_PIN15_Pos (15UL)               /*!< Position of PIN15 field.                                             */
23779   #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field.                                 */
23780   #define GPIO_OUTCLR_PIN15_Min (0x0UL)              /*!< Min enumerator value of PIN15 field.                                 */
23781   #define GPIO_OUTCLR_PIN15_Max (0x1UL)              /*!< Max enumerator value of PIN15 field.                                 */
23782   #define GPIO_OUTCLR_PIN15_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23783   #define GPIO_OUTCLR_PIN15_High (0x1UL)             /*!< Read: pin driver is high                                             */
23784   #define GPIO_OUTCLR_PIN15_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23785 
23786 /* PIN16 @Bit 16 : Pin 16 */
23787   #define GPIO_OUTCLR_PIN16_Pos (16UL)               /*!< Position of PIN16 field.                                             */
23788   #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field.                                 */
23789   #define GPIO_OUTCLR_PIN16_Min (0x0UL)              /*!< Min enumerator value of PIN16 field.                                 */
23790   #define GPIO_OUTCLR_PIN16_Max (0x1UL)              /*!< Max enumerator value of PIN16 field.                                 */
23791   #define GPIO_OUTCLR_PIN16_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23792   #define GPIO_OUTCLR_PIN16_High (0x1UL)             /*!< Read: pin driver is high                                             */
23793   #define GPIO_OUTCLR_PIN16_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23794 
23795 /* PIN17 @Bit 17 : Pin 17 */
23796   #define GPIO_OUTCLR_PIN17_Pos (17UL)               /*!< Position of PIN17 field.                                             */
23797   #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field.                                 */
23798   #define GPIO_OUTCLR_PIN17_Min (0x0UL)              /*!< Min enumerator value of PIN17 field.                                 */
23799   #define GPIO_OUTCLR_PIN17_Max (0x1UL)              /*!< Max enumerator value of PIN17 field.                                 */
23800   #define GPIO_OUTCLR_PIN17_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23801   #define GPIO_OUTCLR_PIN17_High (0x1UL)             /*!< Read: pin driver is high                                             */
23802   #define GPIO_OUTCLR_PIN17_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23803 
23804 /* PIN18 @Bit 18 : Pin 18 */
23805   #define GPIO_OUTCLR_PIN18_Pos (18UL)               /*!< Position of PIN18 field.                                             */
23806   #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field.                                 */
23807   #define GPIO_OUTCLR_PIN18_Min (0x0UL)              /*!< Min enumerator value of PIN18 field.                                 */
23808   #define GPIO_OUTCLR_PIN18_Max (0x1UL)              /*!< Max enumerator value of PIN18 field.                                 */
23809   #define GPIO_OUTCLR_PIN18_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23810   #define GPIO_OUTCLR_PIN18_High (0x1UL)             /*!< Read: pin driver is high                                             */
23811   #define GPIO_OUTCLR_PIN18_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23812 
23813 /* PIN19 @Bit 19 : Pin 19 */
23814   #define GPIO_OUTCLR_PIN19_Pos (19UL)               /*!< Position of PIN19 field.                                             */
23815   #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field.                                 */
23816   #define GPIO_OUTCLR_PIN19_Min (0x0UL)              /*!< Min enumerator value of PIN19 field.                                 */
23817   #define GPIO_OUTCLR_PIN19_Max (0x1UL)              /*!< Max enumerator value of PIN19 field.                                 */
23818   #define GPIO_OUTCLR_PIN19_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23819   #define GPIO_OUTCLR_PIN19_High (0x1UL)             /*!< Read: pin driver is high                                             */
23820   #define GPIO_OUTCLR_PIN19_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23821 
23822 /* PIN20 @Bit 20 : Pin 20 */
23823   #define GPIO_OUTCLR_PIN20_Pos (20UL)               /*!< Position of PIN20 field.                                             */
23824   #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field.                                 */
23825   #define GPIO_OUTCLR_PIN20_Min (0x0UL)              /*!< Min enumerator value of PIN20 field.                                 */
23826   #define GPIO_OUTCLR_PIN20_Max (0x1UL)              /*!< Max enumerator value of PIN20 field.                                 */
23827   #define GPIO_OUTCLR_PIN20_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23828   #define GPIO_OUTCLR_PIN20_High (0x1UL)             /*!< Read: pin driver is high                                             */
23829   #define GPIO_OUTCLR_PIN20_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23830 
23831 /* PIN21 @Bit 21 : Pin 21 */
23832   #define GPIO_OUTCLR_PIN21_Pos (21UL)               /*!< Position of PIN21 field.                                             */
23833   #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field.                                 */
23834   #define GPIO_OUTCLR_PIN21_Min (0x0UL)              /*!< Min enumerator value of PIN21 field.                                 */
23835   #define GPIO_OUTCLR_PIN21_Max (0x1UL)              /*!< Max enumerator value of PIN21 field.                                 */
23836   #define GPIO_OUTCLR_PIN21_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23837   #define GPIO_OUTCLR_PIN21_High (0x1UL)             /*!< Read: pin driver is high                                             */
23838   #define GPIO_OUTCLR_PIN21_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23839 
23840 /* PIN22 @Bit 22 : Pin 22 */
23841   #define GPIO_OUTCLR_PIN22_Pos (22UL)               /*!< Position of PIN22 field.                                             */
23842   #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field.                                 */
23843   #define GPIO_OUTCLR_PIN22_Min (0x0UL)              /*!< Min enumerator value of PIN22 field.                                 */
23844   #define GPIO_OUTCLR_PIN22_Max (0x1UL)              /*!< Max enumerator value of PIN22 field.                                 */
23845   #define GPIO_OUTCLR_PIN22_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23846   #define GPIO_OUTCLR_PIN22_High (0x1UL)             /*!< Read: pin driver is high                                             */
23847   #define GPIO_OUTCLR_PIN22_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23848 
23849 /* PIN23 @Bit 23 : Pin 23 */
23850   #define GPIO_OUTCLR_PIN23_Pos (23UL)               /*!< Position of PIN23 field.                                             */
23851   #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field.                                 */
23852   #define GPIO_OUTCLR_PIN23_Min (0x0UL)              /*!< Min enumerator value of PIN23 field.                                 */
23853   #define GPIO_OUTCLR_PIN23_Max (0x1UL)              /*!< Max enumerator value of PIN23 field.                                 */
23854   #define GPIO_OUTCLR_PIN23_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23855   #define GPIO_OUTCLR_PIN23_High (0x1UL)             /*!< Read: pin driver is high                                             */
23856   #define GPIO_OUTCLR_PIN23_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23857 
23858 /* PIN24 @Bit 24 : Pin 24 */
23859   #define GPIO_OUTCLR_PIN24_Pos (24UL)               /*!< Position of PIN24 field.                                             */
23860   #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field.                                 */
23861   #define GPIO_OUTCLR_PIN24_Min (0x0UL)              /*!< Min enumerator value of PIN24 field.                                 */
23862   #define GPIO_OUTCLR_PIN24_Max (0x1UL)              /*!< Max enumerator value of PIN24 field.                                 */
23863   #define GPIO_OUTCLR_PIN24_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23864   #define GPIO_OUTCLR_PIN24_High (0x1UL)             /*!< Read: pin driver is high                                             */
23865   #define GPIO_OUTCLR_PIN24_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23866 
23867 /* PIN25 @Bit 25 : Pin 25 */
23868   #define GPIO_OUTCLR_PIN25_Pos (25UL)               /*!< Position of PIN25 field.                                             */
23869   #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field.                                 */
23870   #define GPIO_OUTCLR_PIN25_Min (0x0UL)              /*!< Min enumerator value of PIN25 field.                                 */
23871   #define GPIO_OUTCLR_PIN25_Max (0x1UL)              /*!< Max enumerator value of PIN25 field.                                 */
23872   #define GPIO_OUTCLR_PIN25_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23873   #define GPIO_OUTCLR_PIN25_High (0x1UL)             /*!< Read: pin driver is high                                             */
23874   #define GPIO_OUTCLR_PIN25_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23875 
23876 /* PIN26 @Bit 26 : Pin 26 */
23877   #define GPIO_OUTCLR_PIN26_Pos (26UL)               /*!< Position of PIN26 field.                                             */
23878   #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field.                                 */
23879   #define GPIO_OUTCLR_PIN26_Min (0x0UL)              /*!< Min enumerator value of PIN26 field.                                 */
23880   #define GPIO_OUTCLR_PIN26_Max (0x1UL)              /*!< Max enumerator value of PIN26 field.                                 */
23881   #define GPIO_OUTCLR_PIN26_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23882   #define GPIO_OUTCLR_PIN26_High (0x1UL)             /*!< Read: pin driver is high                                             */
23883   #define GPIO_OUTCLR_PIN26_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23884 
23885 /* PIN27 @Bit 27 : Pin 27 */
23886   #define GPIO_OUTCLR_PIN27_Pos (27UL)               /*!< Position of PIN27 field.                                             */
23887   #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field.                                 */
23888   #define GPIO_OUTCLR_PIN27_Min (0x0UL)              /*!< Min enumerator value of PIN27 field.                                 */
23889   #define GPIO_OUTCLR_PIN27_Max (0x1UL)              /*!< Max enumerator value of PIN27 field.                                 */
23890   #define GPIO_OUTCLR_PIN27_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23891   #define GPIO_OUTCLR_PIN27_High (0x1UL)             /*!< Read: pin driver is high                                             */
23892   #define GPIO_OUTCLR_PIN27_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23893 
23894 /* PIN28 @Bit 28 : Pin 28 */
23895   #define GPIO_OUTCLR_PIN28_Pos (28UL)               /*!< Position of PIN28 field.                                             */
23896   #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field.                                 */
23897   #define GPIO_OUTCLR_PIN28_Min (0x0UL)              /*!< Min enumerator value of PIN28 field.                                 */
23898   #define GPIO_OUTCLR_PIN28_Max (0x1UL)              /*!< Max enumerator value of PIN28 field.                                 */
23899   #define GPIO_OUTCLR_PIN28_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23900   #define GPIO_OUTCLR_PIN28_High (0x1UL)             /*!< Read: pin driver is high                                             */
23901   #define GPIO_OUTCLR_PIN28_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23902 
23903 /* PIN29 @Bit 29 : Pin 29 */
23904   #define GPIO_OUTCLR_PIN29_Pos (29UL)               /*!< Position of PIN29 field.                                             */
23905   #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field.                                 */
23906   #define GPIO_OUTCLR_PIN29_Min (0x0UL)              /*!< Min enumerator value of PIN29 field.                                 */
23907   #define GPIO_OUTCLR_PIN29_Max (0x1UL)              /*!< Max enumerator value of PIN29 field.                                 */
23908   #define GPIO_OUTCLR_PIN29_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23909   #define GPIO_OUTCLR_PIN29_High (0x1UL)             /*!< Read: pin driver is high                                             */
23910   #define GPIO_OUTCLR_PIN29_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23911 
23912 /* PIN30 @Bit 30 : Pin 30 */
23913   #define GPIO_OUTCLR_PIN30_Pos (30UL)               /*!< Position of PIN30 field.                                             */
23914   #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field.                                 */
23915   #define GPIO_OUTCLR_PIN30_Min (0x0UL)              /*!< Min enumerator value of PIN30 field.                                 */
23916   #define GPIO_OUTCLR_PIN30_Max (0x1UL)              /*!< Max enumerator value of PIN30 field.                                 */
23917   #define GPIO_OUTCLR_PIN30_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23918   #define GPIO_OUTCLR_PIN30_High (0x1UL)             /*!< Read: pin driver is high                                             */
23919   #define GPIO_OUTCLR_PIN30_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23920 
23921 /* PIN31 @Bit 31 : Pin 31 */
23922   #define GPIO_OUTCLR_PIN31_Pos (31UL)               /*!< Position of PIN31 field.                                             */
23923   #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field.                                 */
23924   #define GPIO_OUTCLR_PIN31_Min (0x0UL)              /*!< Min enumerator value of PIN31 field.                                 */
23925   #define GPIO_OUTCLR_PIN31_Max (0x1UL)              /*!< Max enumerator value of PIN31 field.                                 */
23926   #define GPIO_OUTCLR_PIN31_Low (0x0UL)              /*!< Read: pin driver is low                                              */
23927   #define GPIO_OUTCLR_PIN31_High (0x1UL)             /*!< Read: pin driver is high                                             */
23928   #define GPIO_OUTCLR_PIN31_Clear (0x1UL)            /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect   */
23929 
23930 
23931 /* GPIO_IN: Read GPIO port */
23932   #define GPIO_IN_ResetValue (0x00000000UL)          /*!< Reset value of IN register.                                          */
23933 
23934 /* PIN0 @Bit 0 : Pin 0 */
23935   #define GPIO_IN_PIN0_Pos (0UL)                     /*!< Position of PIN0 field.                                              */
23936   #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field.                                            */
23937   #define GPIO_IN_PIN0_Min (0x0UL)                   /*!< Min enumerator value of PIN0 field.                                  */
23938   #define GPIO_IN_PIN0_Max (0x1UL)                   /*!< Max enumerator value of PIN0 field.                                  */
23939   #define GPIO_IN_PIN0_Low (0x0UL)                   /*!< Pin input is low                                                     */
23940   #define GPIO_IN_PIN0_High (0x1UL)                  /*!< Pin input is high                                                    */
23941 
23942 /* PIN1 @Bit 1 : Pin 1 */
23943   #define GPIO_IN_PIN1_Pos (1UL)                     /*!< Position of PIN1 field.                                              */
23944   #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field.                                            */
23945   #define GPIO_IN_PIN1_Min (0x0UL)                   /*!< Min enumerator value of PIN1 field.                                  */
23946   #define GPIO_IN_PIN1_Max (0x1UL)                   /*!< Max enumerator value of PIN1 field.                                  */
23947   #define GPIO_IN_PIN1_Low (0x0UL)                   /*!< Pin input is low                                                     */
23948   #define GPIO_IN_PIN1_High (0x1UL)                  /*!< Pin input is high                                                    */
23949 
23950 /* PIN2 @Bit 2 : Pin 2 */
23951   #define GPIO_IN_PIN2_Pos (2UL)                     /*!< Position of PIN2 field.                                              */
23952   #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field.                                            */
23953   #define GPIO_IN_PIN2_Min (0x0UL)                   /*!< Min enumerator value of PIN2 field.                                  */
23954   #define GPIO_IN_PIN2_Max (0x1UL)                   /*!< Max enumerator value of PIN2 field.                                  */
23955   #define GPIO_IN_PIN2_Low (0x0UL)                   /*!< Pin input is low                                                     */
23956   #define GPIO_IN_PIN2_High (0x1UL)                  /*!< Pin input is high                                                    */
23957 
23958 /* PIN3 @Bit 3 : Pin 3 */
23959   #define GPIO_IN_PIN3_Pos (3UL)                     /*!< Position of PIN3 field.                                              */
23960   #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field.                                            */
23961   #define GPIO_IN_PIN3_Min (0x0UL)                   /*!< Min enumerator value of PIN3 field.                                  */
23962   #define GPIO_IN_PIN3_Max (0x1UL)                   /*!< Max enumerator value of PIN3 field.                                  */
23963   #define GPIO_IN_PIN3_Low (0x0UL)                   /*!< Pin input is low                                                     */
23964   #define GPIO_IN_PIN3_High (0x1UL)                  /*!< Pin input is high                                                    */
23965 
23966 /* PIN4 @Bit 4 : Pin 4 */
23967   #define GPIO_IN_PIN4_Pos (4UL)                     /*!< Position of PIN4 field.                                              */
23968   #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field.                                            */
23969   #define GPIO_IN_PIN4_Min (0x0UL)                   /*!< Min enumerator value of PIN4 field.                                  */
23970   #define GPIO_IN_PIN4_Max (0x1UL)                   /*!< Max enumerator value of PIN4 field.                                  */
23971   #define GPIO_IN_PIN4_Low (0x0UL)                   /*!< Pin input is low                                                     */
23972   #define GPIO_IN_PIN4_High (0x1UL)                  /*!< Pin input is high                                                    */
23973 
23974 /* PIN5 @Bit 5 : Pin 5 */
23975   #define GPIO_IN_PIN5_Pos (5UL)                     /*!< Position of PIN5 field.                                              */
23976   #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field.                                            */
23977   #define GPIO_IN_PIN5_Min (0x0UL)                   /*!< Min enumerator value of PIN5 field.                                  */
23978   #define GPIO_IN_PIN5_Max (0x1UL)                   /*!< Max enumerator value of PIN5 field.                                  */
23979   #define GPIO_IN_PIN5_Low (0x0UL)                   /*!< Pin input is low                                                     */
23980   #define GPIO_IN_PIN5_High (0x1UL)                  /*!< Pin input is high                                                    */
23981 
23982 /* PIN6 @Bit 6 : Pin 6 */
23983   #define GPIO_IN_PIN6_Pos (6UL)                     /*!< Position of PIN6 field.                                              */
23984   #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field.                                            */
23985   #define GPIO_IN_PIN6_Min (0x0UL)                   /*!< Min enumerator value of PIN6 field.                                  */
23986   #define GPIO_IN_PIN6_Max (0x1UL)                   /*!< Max enumerator value of PIN6 field.                                  */
23987   #define GPIO_IN_PIN6_Low (0x0UL)                   /*!< Pin input is low                                                     */
23988   #define GPIO_IN_PIN6_High (0x1UL)                  /*!< Pin input is high                                                    */
23989 
23990 /* PIN7 @Bit 7 : Pin 7 */
23991   #define GPIO_IN_PIN7_Pos (7UL)                     /*!< Position of PIN7 field.                                              */
23992   #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field.                                            */
23993   #define GPIO_IN_PIN7_Min (0x0UL)                   /*!< Min enumerator value of PIN7 field.                                  */
23994   #define GPIO_IN_PIN7_Max (0x1UL)                   /*!< Max enumerator value of PIN7 field.                                  */
23995   #define GPIO_IN_PIN7_Low (0x0UL)                   /*!< Pin input is low                                                     */
23996   #define GPIO_IN_PIN7_High (0x1UL)                  /*!< Pin input is high                                                    */
23997 
23998 /* PIN8 @Bit 8 : Pin 8 */
23999   #define GPIO_IN_PIN8_Pos (8UL)                     /*!< Position of PIN8 field.                                              */
24000   #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field.                                            */
24001   #define GPIO_IN_PIN8_Min (0x0UL)                   /*!< Min enumerator value of PIN8 field.                                  */
24002   #define GPIO_IN_PIN8_Max (0x1UL)                   /*!< Max enumerator value of PIN8 field.                                  */
24003   #define GPIO_IN_PIN8_Low (0x0UL)                   /*!< Pin input is low                                                     */
24004   #define GPIO_IN_PIN8_High (0x1UL)                  /*!< Pin input is high                                                    */
24005 
24006 /* PIN9 @Bit 9 : Pin 9 */
24007   #define GPIO_IN_PIN9_Pos (9UL)                     /*!< Position of PIN9 field.                                              */
24008   #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field.                                            */
24009   #define GPIO_IN_PIN9_Min (0x0UL)                   /*!< Min enumerator value of PIN9 field.                                  */
24010   #define GPIO_IN_PIN9_Max (0x1UL)                   /*!< Max enumerator value of PIN9 field.                                  */
24011   #define GPIO_IN_PIN9_Low (0x0UL)                   /*!< Pin input is low                                                     */
24012   #define GPIO_IN_PIN9_High (0x1UL)                  /*!< Pin input is high                                                    */
24013 
24014 /* PIN10 @Bit 10 : Pin 10 */
24015   #define GPIO_IN_PIN10_Pos (10UL)                   /*!< Position of PIN10 field.                                             */
24016   #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field.                                         */
24017   #define GPIO_IN_PIN10_Min (0x0UL)                  /*!< Min enumerator value of PIN10 field.                                 */
24018   #define GPIO_IN_PIN10_Max (0x1UL)                  /*!< Max enumerator value of PIN10 field.                                 */
24019   #define GPIO_IN_PIN10_Low (0x0UL)                  /*!< Pin input is low                                                     */
24020   #define GPIO_IN_PIN10_High (0x1UL)                 /*!< Pin input is high                                                    */
24021 
24022 /* PIN11 @Bit 11 : Pin 11 */
24023   #define GPIO_IN_PIN11_Pos (11UL)                   /*!< Position of PIN11 field.                                             */
24024   #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field.                                         */
24025   #define GPIO_IN_PIN11_Min (0x0UL)                  /*!< Min enumerator value of PIN11 field.                                 */
24026   #define GPIO_IN_PIN11_Max (0x1UL)                  /*!< Max enumerator value of PIN11 field.                                 */
24027   #define GPIO_IN_PIN11_Low (0x0UL)                  /*!< Pin input is low                                                     */
24028   #define GPIO_IN_PIN11_High (0x1UL)                 /*!< Pin input is high                                                    */
24029 
24030 /* PIN12 @Bit 12 : Pin 12 */
24031   #define GPIO_IN_PIN12_Pos (12UL)                   /*!< Position of PIN12 field.                                             */
24032   #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field.                                         */
24033   #define GPIO_IN_PIN12_Min (0x0UL)                  /*!< Min enumerator value of PIN12 field.                                 */
24034   #define GPIO_IN_PIN12_Max (0x1UL)                  /*!< Max enumerator value of PIN12 field.                                 */
24035   #define GPIO_IN_PIN12_Low (0x0UL)                  /*!< Pin input is low                                                     */
24036   #define GPIO_IN_PIN12_High (0x1UL)                 /*!< Pin input is high                                                    */
24037 
24038 /* PIN13 @Bit 13 : Pin 13 */
24039   #define GPIO_IN_PIN13_Pos (13UL)                   /*!< Position of PIN13 field.                                             */
24040   #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field.                                         */
24041   #define GPIO_IN_PIN13_Min (0x0UL)                  /*!< Min enumerator value of PIN13 field.                                 */
24042   #define GPIO_IN_PIN13_Max (0x1UL)                  /*!< Max enumerator value of PIN13 field.                                 */
24043   #define GPIO_IN_PIN13_Low (0x0UL)                  /*!< Pin input is low                                                     */
24044   #define GPIO_IN_PIN13_High (0x1UL)                 /*!< Pin input is high                                                    */
24045 
24046 /* PIN14 @Bit 14 : Pin 14 */
24047   #define GPIO_IN_PIN14_Pos (14UL)                   /*!< Position of PIN14 field.                                             */
24048   #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field.                                         */
24049   #define GPIO_IN_PIN14_Min (0x0UL)                  /*!< Min enumerator value of PIN14 field.                                 */
24050   #define GPIO_IN_PIN14_Max (0x1UL)                  /*!< Max enumerator value of PIN14 field.                                 */
24051   #define GPIO_IN_PIN14_Low (0x0UL)                  /*!< Pin input is low                                                     */
24052   #define GPIO_IN_PIN14_High (0x1UL)                 /*!< Pin input is high                                                    */
24053 
24054 /* PIN15 @Bit 15 : Pin 15 */
24055   #define GPIO_IN_PIN15_Pos (15UL)                   /*!< Position of PIN15 field.                                             */
24056   #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field.                                         */
24057   #define GPIO_IN_PIN15_Min (0x0UL)                  /*!< Min enumerator value of PIN15 field.                                 */
24058   #define GPIO_IN_PIN15_Max (0x1UL)                  /*!< Max enumerator value of PIN15 field.                                 */
24059   #define GPIO_IN_PIN15_Low (0x0UL)                  /*!< Pin input is low                                                     */
24060   #define GPIO_IN_PIN15_High (0x1UL)                 /*!< Pin input is high                                                    */
24061 
24062 /* PIN16 @Bit 16 : Pin 16 */
24063   #define GPIO_IN_PIN16_Pos (16UL)                   /*!< Position of PIN16 field.                                             */
24064   #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field.                                         */
24065   #define GPIO_IN_PIN16_Min (0x0UL)                  /*!< Min enumerator value of PIN16 field.                                 */
24066   #define GPIO_IN_PIN16_Max (0x1UL)                  /*!< Max enumerator value of PIN16 field.                                 */
24067   #define GPIO_IN_PIN16_Low (0x0UL)                  /*!< Pin input is low                                                     */
24068   #define GPIO_IN_PIN16_High (0x1UL)                 /*!< Pin input is high                                                    */
24069 
24070 /* PIN17 @Bit 17 : Pin 17 */
24071   #define GPIO_IN_PIN17_Pos (17UL)                   /*!< Position of PIN17 field.                                             */
24072   #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field.                                         */
24073   #define GPIO_IN_PIN17_Min (0x0UL)                  /*!< Min enumerator value of PIN17 field.                                 */
24074   #define GPIO_IN_PIN17_Max (0x1UL)                  /*!< Max enumerator value of PIN17 field.                                 */
24075   #define GPIO_IN_PIN17_Low (0x0UL)                  /*!< Pin input is low                                                     */
24076   #define GPIO_IN_PIN17_High (0x1UL)                 /*!< Pin input is high                                                    */
24077 
24078 /* PIN18 @Bit 18 : Pin 18 */
24079   #define GPIO_IN_PIN18_Pos (18UL)                   /*!< Position of PIN18 field.                                             */
24080   #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field.                                         */
24081   #define GPIO_IN_PIN18_Min (0x0UL)                  /*!< Min enumerator value of PIN18 field.                                 */
24082   #define GPIO_IN_PIN18_Max (0x1UL)                  /*!< Max enumerator value of PIN18 field.                                 */
24083   #define GPIO_IN_PIN18_Low (0x0UL)                  /*!< Pin input is low                                                     */
24084   #define GPIO_IN_PIN18_High (0x1UL)                 /*!< Pin input is high                                                    */
24085 
24086 /* PIN19 @Bit 19 : Pin 19 */
24087   #define GPIO_IN_PIN19_Pos (19UL)                   /*!< Position of PIN19 field.                                             */
24088   #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field.                                         */
24089   #define GPIO_IN_PIN19_Min (0x0UL)                  /*!< Min enumerator value of PIN19 field.                                 */
24090   #define GPIO_IN_PIN19_Max (0x1UL)                  /*!< Max enumerator value of PIN19 field.                                 */
24091   #define GPIO_IN_PIN19_Low (0x0UL)                  /*!< Pin input is low                                                     */
24092   #define GPIO_IN_PIN19_High (0x1UL)                 /*!< Pin input is high                                                    */
24093 
24094 /* PIN20 @Bit 20 : Pin 20 */
24095   #define GPIO_IN_PIN20_Pos (20UL)                   /*!< Position of PIN20 field.                                             */
24096   #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field.                                         */
24097   #define GPIO_IN_PIN20_Min (0x0UL)                  /*!< Min enumerator value of PIN20 field.                                 */
24098   #define GPIO_IN_PIN20_Max (0x1UL)                  /*!< Max enumerator value of PIN20 field.                                 */
24099   #define GPIO_IN_PIN20_Low (0x0UL)                  /*!< Pin input is low                                                     */
24100   #define GPIO_IN_PIN20_High (0x1UL)                 /*!< Pin input is high                                                    */
24101 
24102 /* PIN21 @Bit 21 : Pin 21 */
24103   #define GPIO_IN_PIN21_Pos (21UL)                   /*!< Position of PIN21 field.                                             */
24104   #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field.                                         */
24105   #define GPIO_IN_PIN21_Min (0x0UL)                  /*!< Min enumerator value of PIN21 field.                                 */
24106   #define GPIO_IN_PIN21_Max (0x1UL)                  /*!< Max enumerator value of PIN21 field.                                 */
24107   #define GPIO_IN_PIN21_Low (0x0UL)                  /*!< Pin input is low                                                     */
24108   #define GPIO_IN_PIN21_High (0x1UL)                 /*!< Pin input is high                                                    */
24109 
24110 /* PIN22 @Bit 22 : Pin 22 */
24111   #define GPIO_IN_PIN22_Pos (22UL)                   /*!< Position of PIN22 field.                                             */
24112   #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field.                                         */
24113   #define GPIO_IN_PIN22_Min (0x0UL)                  /*!< Min enumerator value of PIN22 field.                                 */
24114   #define GPIO_IN_PIN22_Max (0x1UL)                  /*!< Max enumerator value of PIN22 field.                                 */
24115   #define GPIO_IN_PIN22_Low (0x0UL)                  /*!< Pin input is low                                                     */
24116   #define GPIO_IN_PIN22_High (0x1UL)                 /*!< Pin input is high                                                    */
24117 
24118 /* PIN23 @Bit 23 : Pin 23 */
24119   #define GPIO_IN_PIN23_Pos (23UL)                   /*!< Position of PIN23 field.                                             */
24120   #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field.                                         */
24121   #define GPIO_IN_PIN23_Min (0x0UL)                  /*!< Min enumerator value of PIN23 field.                                 */
24122   #define GPIO_IN_PIN23_Max (0x1UL)                  /*!< Max enumerator value of PIN23 field.                                 */
24123   #define GPIO_IN_PIN23_Low (0x0UL)                  /*!< Pin input is low                                                     */
24124   #define GPIO_IN_PIN23_High (0x1UL)                 /*!< Pin input is high                                                    */
24125 
24126 /* PIN24 @Bit 24 : Pin 24 */
24127   #define GPIO_IN_PIN24_Pos (24UL)                   /*!< Position of PIN24 field.                                             */
24128   #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field.                                         */
24129   #define GPIO_IN_PIN24_Min (0x0UL)                  /*!< Min enumerator value of PIN24 field.                                 */
24130   #define GPIO_IN_PIN24_Max (0x1UL)                  /*!< Max enumerator value of PIN24 field.                                 */
24131   #define GPIO_IN_PIN24_Low (0x0UL)                  /*!< Pin input is low                                                     */
24132   #define GPIO_IN_PIN24_High (0x1UL)                 /*!< Pin input is high                                                    */
24133 
24134 /* PIN25 @Bit 25 : Pin 25 */
24135   #define GPIO_IN_PIN25_Pos (25UL)                   /*!< Position of PIN25 field.                                             */
24136   #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field.                                         */
24137   #define GPIO_IN_PIN25_Min (0x0UL)                  /*!< Min enumerator value of PIN25 field.                                 */
24138   #define GPIO_IN_PIN25_Max (0x1UL)                  /*!< Max enumerator value of PIN25 field.                                 */
24139   #define GPIO_IN_PIN25_Low (0x0UL)                  /*!< Pin input is low                                                     */
24140   #define GPIO_IN_PIN25_High (0x1UL)                 /*!< Pin input is high                                                    */
24141 
24142 /* PIN26 @Bit 26 : Pin 26 */
24143   #define GPIO_IN_PIN26_Pos (26UL)                   /*!< Position of PIN26 field.                                             */
24144   #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field.                                         */
24145   #define GPIO_IN_PIN26_Min (0x0UL)                  /*!< Min enumerator value of PIN26 field.                                 */
24146   #define GPIO_IN_PIN26_Max (0x1UL)                  /*!< Max enumerator value of PIN26 field.                                 */
24147   #define GPIO_IN_PIN26_Low (0x0UL)                  /*!< Pin input is low                                                     */
24148   #define GPIO_IN_PIN26_High (0x1UL)                 /*!< Pin input is high                                                    */
24149 
24150 /* PIN27 @Bit 27 : Pin 27 */
24151   #define GPIO_IN_PIN27_Pos (27UL)                   /*!< Position of PIN27 field.                                             */
24152   #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field.                                         */
24153   #define GPIO_IN_PIN27_Min (0x0UL)                  /*!< Min enumerator value of PIN27 field.                                 */
24154   #define GPIO_IN_PIN27_Max (0x1UL)                  /*!< Max enumerator value of PIN27 field.                                 */
24155   #define GPIO_IN_PIN27_Low (0x0UL)                  /*!< Pin input is low                                                     */
24156   #define GPIO_IN_PIN27_High (0x1UL)                 /*!< Pin input is high                                                    */
24157 
24158 /* PIN28 @Bit 28 : Pin 28 */
24159   #define GPIO_IN_PIN28_Pos (28UL)                   /*!< Position of PIN28 field.                                             */
24160   #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field.                                         */
24161   #define GPIO_IN_PIN28_Min (0x0UL)                  /*!< Min enumerator value of PIN28 field.                                 */
24162   #define GPIO_IN_PIN28_Max (0x1UL)                  /*!< Max enumerator value of PIN28 field.                                 */
24163   #define GPIO_IN_PIN28_Low (0x0UL)                  /*!< Pin input is low                                                     */
24164   #define GPIO_IN_PIN28_High (0x1UL)                 /*!< Pin input is high                                                    */
24165 
24166 /* PIN29 @Bit 29 : Pin 29 */
24167   #define GPIO_IN_PIN29_Pos (29UL)                   /*!< Position of PIN29 field.                                             */
24168   #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field.                                         */
24169   #define GPIO_IN_PIN29_Min (0x0UL)                  /*!< Min enumerator value of PIN29 field.                                 */
24170   #define GPIO_IN_PIN29_Max (0x1UL)                  /*!< Max enumerator value of PIN29 field.                                 */
24171   #define GPIO_IN_PIN29_Low (0x0UL)                  /*!< Pin input is low                                                     */
24172   #define GPIO_IN_PIN29_High (0x1UL)                 /*!< Pin input is high                                                    */
24173 
24174 /* PIN30 @Bit 30 : Pin 30 */
24175   #define GPIO_IN_PIN30_Pos (30UL)                   /*!< Position of PIN30 field.                                             */
24176   #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field.                                         */
24177   #define GPIO_IN_PIN30_Min (0x0UL)                  /*!< Min enumerator value of PIN30 field.                                 */
24178   #define GPIO_IN_PIN30_Max (0x1UL)                  /*!< Max enumerator value of PIN30 field.                                 */
24179   #define GPIO_IN_PIN30_Low (0x0UL)                  /*!< Pin input is low                                                     */
24180   #define GPIO_IN_PIN30_High (0x1UL)                 /*!< Pin input is high                                                    */
24181 
24182 /* PIN31 @Bit 31 : Pin 31 */
24183   #define GPIO_IN_PIN31_Pos (31UL)                   /*!< Position of PIN31 field.                                             */
24184   #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field.                                         */
24185   #define GPIO_IN_PIN31_Min (0x0UL)                  /*!< Min enumerator value of PIN31 field.                                 */
24186   #define GPIO_IN_PIN31_Max (0x1UL)                  /*!< Max enumerator value of PIN31 field.                                 */
24187   #define GPIO_IN_PIN31_Low (0x0UL)                  /*!< Pin input is low                                                     */
24188   #define GPIO_IN_PIN31_High (0x1UL)                 /*!< Pin input is high                                                    */
24189 
24190 
24191 /* GPIO_DIR: Direction of GPIO pins */
24192   #define GPIO_DIR_ResetValue (0x00000000UL)         /*!< Reset value of DIR register.                                         */
24193 
24194 /* PIN0 @Bit 0 : Pin 0 */
24195   #define GPIO_DIR_PIN0_Pos (0UL)                    /*!< Position of PIN0 field.                                              */
24196   #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field.                                          */
24197   #define GPIO_DIR_PIN0_Min (0x0UL)                  /*!< Min enumerator value of PIN0 field.                                  */
24198   #define GPIO_DIR_PIN0_Max (0x1UL)                  /*!< Max enumerator value of PIN0 field.                                  */
24199   #define GPIO_DIR_PIN0_Input (0x0UL)                /*!< Pin set as input                                                     */
24200   #define GPIO_DIR_PIN0_Output (0x1UL)               /*!< Pin set as output                                                    */
24201 
24202 /* PIN1 @Bit 1 : Pin 1 */
24203   #define GPIO_DIR_PIN1_Pos (1UL)                    /*!< Position of PIN1 field.                                              */
24204   #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field.                                          */
24205   #define GPIO_DIR_PIN1_Min (0x0UL)                  /*!< Min enumerator value of PIN1 field.                                  */
24206   #define GPIO_DIR_PIN1_Max (0x1UL)                  /*!< Max enumerator value of PIN1 field.                                  */
24207   #define GPIO_DIR_PIN1_Input (0x0UL)                /*!< Pin set as input                                                     */
24208   #define GPIO_DIR_PIN1_Output (0x1UL)               /*!< Pin set as output                                                    */
24209 
24210 /* PIN2 @Bit 2 : Pin 2 */
24211   #define GPIO_DIR_PIN2_Pos (2UL)                    /*!< Position of PIN2 field.                                              */
24212   #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field.                                          */
24213   #define GPIO_DIR_PIN2_Min (0x0UL)                  /*!< Min enumerator value of PIN2 field.                                  */
24214   #define GPIO_DIR_PIN2_Max (0x1UL)                  /*!< Max enumerator value of PIN2 field.                                  */
24215   #define GPIO_DIR_PIN2_Input (0x0UL)                /*!< Pin set as input                                                     */
24216   #define GPIO_DIR_PIN2_Output (0x1UL)               /*!< Pin set as output                                                    */
24217 
24218 /* PIN3 @Bit 3 : Pin 3 */
24219   #define GPIO_DIR_PIN3_Pos (3UL)                    /*!< Position of PIN3 field.                                              */
24220   #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field.                                          */
24221   #define GPIO_DIR_PIN3_Min (0x0UL)                  /*!< Min enumerator value of PIN3 field.                                  */
24222   #define GPIO_DIR_PIN3_Max (0x1UL)                  /*!< Max enumerator value of PIN3 field.                                  */
24223   #define GPIO_DIR_PIN3_Input (0x0UL)                /*!< Pin set as input                                                     */
24224   #define GPIO_DIR_PIN3_Output (0x1UL)               /*!< Pin set as output                                                    */
24225 
24226 /* PIN4 @Bit 4 : Pin 4 */
24227   #define GPIO_DIR_PIN4_Pos (4UL)                    /*!< Position of PIN4 field.                                              */
24228   #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field.                                          */
24229   #define GPIO_DIR_PIN4_Min (0x0UL)                  /*!< Min enumerator value of PIN4 field.                                  */
24230   #define GPIO_DIR_PIN4_Max (0x1UL)                  /*!< Max enumerator value of PIN4 field.                                  */
24231   #define GPIO_DIR_PIN4_Input (0x0UL)                /*!< Pin set as input                                                     */
24232   #define GPIO_DIR_PIN4_Output (0x1UL)               /*!< Pin set as output                                                    */
24233 
24234 /* PIN5 @Bit 5 : Pin 5 */
24235   #define GPIO_DIR_PIN5_Pos (5UL)                    /*!< Position of PIN5 field.                                              */
24236   #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field.                                          */
24237   #define GPIO_DIR_PIN5_Min (0x0UL)                  /*!< Min enumerator value of PIN5 field.                                  */
24238   #define GPIO_DIR_PIN5_Max (0x1UL)                  /*!< Max enumerator value of PIN5 field.                                  */
24239   #define GPIO_DIR_PIN5_Input (0x0UL)                /*!< Pin set as input                                                     */
24240   #define GPIO_DIR_PIN5_Output (0x1UL)               /*!< Pin set as output                                                    */
24241 
24242 /* PIN6 @Bit 6 : Pin 6 */
24243   #define GPIO_DIR_PIN6_Pos (6UL)                    /*!< Position of PIN6 field.                                              */
24244   #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field.                                          */
24245   #define GPIO_DIR_PIN6_Min (0x0UL)                  /*!< Min enumerator value of PIN6 field.                                  */
24246   #define GPIO_DIR_PIN6_Max (0x1UL)                  /*!< Max enumerator value of PIN6 field.                                  */
24247   #define GPIO_DIR_PIN6_Input (0x0UL)                /*!< Pin set as input                                                     */
24248   #define GPIO_DIR_PIN6_Output (0x1UL)               /*!< Pin set as output                                                    */
24249 
24250 /* PIN7 @Bit 7 : Pin 7 */
24251   #define GPIO_DIR_PIN7_Pos (7UL)                    /*!< Position of PIN7 field.                                              */
24252   #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field.                                          */
24253   #define GPIO_DIR_PIN7_Min (0x0UL)                  /*!< Min enumerator value of PIN7 field.                                  */
24254   #define GPIO_DIR_PIN7_Max (0x1UL)                  /*!< Max enumerator value of PIN7 field.                                  */
24255   #define GPIO_DIR_PIN7_Input (0x0UL)                /*!< Pin set as input                                                     */
24256   #define GPIO_DIR_PIN7_Output (0x1UL)               /*!< Pin set as output                                                    */
24257 
24258 /* PIN8 @Bit 8 : Pin 8 */
24259   #define GPIO_DIR_PIN8_Pos (8UL)                    /*!< Position of PIN8 field.                                              */
24260   #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field.                                          */
24261   #define GPIO_DIR_PIN8_Min (0x0UL)                  /*!< Min enumerator value of PIN8 field.                                  */
24262   #define GPIO_DIR_PIN8_Max (0x1UL)                  /*!< Max enumerator value of PIN8 field.                                  */
24263   #define GPIO_DIR_PIN8_Input (0x0UL)                /*!< Pin set as input                                                     */
24264   #define GPIO_DIR_PIN8_Output (0x1UL)               /*!< Pin set as output                                                    */
24265 
24266 /* PIN9 @Bit 9 : Pin 9 */
24267   #define GPIO_DIR_PIN9_Pos (9UL)                    /*!< Position of PIN9 field.                                              */
24268   #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field.                                          */
24269   #define GPIO_DIR_PIN9_Min (0x0UL)                  /*!< Min enumerator value of PIN9 field.                                  */
24270   #define GPIO_DIR_PIN9_Max (0x1UL)                  /*!< Max enumerator value of PIN9 field.                                  */
24271   #define GPIO_DIR_PIN9_Input (0x0UL)                /*!< Pin set as input                                                     */
24272   #define GPIO_DIR_PIN9_Output (0x1UL)               /*!< Pin set as output                                                    */
24273 
24274 /* PIN10 @Bit 10 : Pin 10 */
24275   #define GPIO_DIR_PIN10_Pos (10UL)                  /*!< Position of PIN10 field.                                             */
24276   #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field.                                       */
24277   #define GPIO_DIR_PIN10_Min (0x0UL)                 /*!< Min enumerator value of PIN10 field.                                 */
24278   #define GPIO_DIR_PIN10_Max (0x1UL)                 /*!< Max enumerator value of PIN10 field.                                 */
24279   #define GPIO_DIR_PIN10_Input (0x0UL)               /*!< Pin set as input                                                     */
24280   #define GPIO_DIR_PIN10_Output (0x1UL)              /*!< Pin set as output                                                    */
24281 
24282 /* PIN11 @Bit 11 : Pin 11 */
24283   #define GPIO_DIR_PIN11_Pos (11UL)                  /*!< Position of PIN11 field.                                             */
24284   #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field.                                       */
24285   #define GPIO_DIR_PIN11_Min (0x0UL)                 /*!< Min enumerator value of PIN11 field.                                 */
24286   #define GPIO_DIR_PIN11_Max (0x1UL)                 /*!< Max enumerator value of PIN11 field.                                 */
24287   #define GPIO_DIR_PIN11_Input (0x0UL)               /*!< Pin set as input                                                     */
24288   #define GPIO_DIR_PIN11_Output (0x1UL)              /*!< Pin set as output                                                    */
24289 
24290 /* PIN12 @Bit 12 : Pin 12 */
24291   #define GPIO_DIR_PIN12_Pos (12UL)                  /*!< Position of PIN12 field.                                             */
24292   #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field.                                       */
24293   #define GPIO_DIR_PIN12_Min (0x0UL)                 /*!< Min enumerator value of PIN12 field.                                 */
24294   #define GPIO_DIR_PIN12_Max (0x1UL)                 /*!< Max enumerator value of PIN12 field.                                 */
24295   #define GPIO_DIR_PIN12_Input (0x0UL)               /*!< Pin set as input                                                     */
24296   #define GPIO_DIR_PIN12_Output (0x1UL)              /*!< Pin set as output                                                    */
24297 
24298 /* PIN13 @Bit 13 : Pin 13 */
24299   #define GPIO_DIR_PIN13_Pos (13UL)                  /*!< Position of PIN13 field.                                             */
24300   #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field.                                       */
24301   #define GPIO_DIR_PIN13_Min (0x0UL)                 /*!< Min enumerator value of PIN13 field.                                 */
24302   #define GPIO_DIR_PIN13_Max (0x1UL)                 /*!< Max enumerator value of PIN13 field.                                 */
24303   #define GPIO_DIR_PIN13_Input (0x0UL)               /*!< Pin set as input                                                     */
24304   #define GPIO_DIR_PIN13_Output (0x1UL)              /*!< Pin set as output                                                    */
24305 
24306 /* PIN14 @Bit 14 : Pin 14 */
24307   #define GPIO_DIR_PIN14_Pos (14UL)                  /*!< Position of PIN14 field.                                             */
24308   #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field.                                       */
24309   #define GPIO_DIR_PIN14_Min (0x0UL)                 /*!< Min enumerator value of PIN14 field.                                 */
24310   #define GPIO_DIR_PIN14_Max (0x1UL)                 /*!< Max enumerator value of PIN14 field.                                 */
24311   #define GPIO_DIR_PIN14_Input (0x0UL)               /*!< Pin set as input                                                     */
24312   #define GPIO_DIR_PIN14_Output (0x1UL)              /*!< Pin set as output                                                    */
24313 
24314 /* PIN15 @Bit 15 : Pin 15 */
24315   #define GPIO_DIR_PIN15_Pos (15UL)                  /*!< Position of PIN15 field.                                             */
24316   #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field.                                       */
24317   #define GPIO_DIR_PIN15_Min (0x0UL)                 /*!< Min enumerator value of PIN15 field.                                 */
24318   #define GPIO_DIR_PIN15_Max (0x1UL)                 /*!< Max enumerator value of PIN15 field.                                 */
24319   #define GPIO_DIR_PIN15_Input (0x0UL)               /*!< Pin set as input                                                     */
24320   #define GPIO_DIR_PIN15_Output (0x1UL)              /*!< Pin set as output                                                    */
24321 
24322 /* PIN16 @Bit 16 : Pin 16 */
24323   #define GPIO_DIR_PIN16_Pos (16UL)                  /*!< Position of PIN16 field.                                             */
24324   #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field.                                       */
24325   #define GPIO_DIR_PIN16_Min (0x0UL)                 /*!< Min enumerator value of PIN16 field.                                 */
24326   #define GPIO_DIR_PIN16_Max (0x1UL)                 /*!< Max enumerator value of PIN16 field.                                 */
24327   #define GPIO_DIR_PIN16_Input (0x0UL)               /*!< Pin set as input                                                     */
24328   #define GPIO_DIR_PIN16_Output (0x1UL)              /*!< Pin set as output                                                    */
24329 
24330 /* PIN17 @Bit 17 : Pin 17 */
24331   #define GPIO_DIR_PIN17_Pos (17UL)                  /*!< Position of PIN17 field.                                             */
24332   #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field.                                       */
24333   #define GPIO_DIR_PIN17_Min (0x0UL)                 /*!< Min enumerator value of PIN17 field.                                 */
24334   #define GPIO_DIR_PIN17_Max (0x1UL)                 /*!< Max enumerator value of PIN17 field.                                 */
24335   #define GPIO_DIR_PIN17_Input (0x0UL)               /*!< Pin set as input                                                     */
24336   #define GPIO_DIR_PIN17_Output (0x1UL)              /*!< Pin set as output                                                    */
24337 
24338 /* PIN18 @Bit 18 : Pin 18 */
24339   #define GPIO_DIR_PIN18_Pos (18UL)                  /*!< Position of PIN18 field.                                             */
24340   #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field.                                       */
24341   #define GPIO_DIR_PIN18_Min (0x0UL)                 /*!< Min enumerator value of PIN18 field.                                 */
24342   #define GPIO_DIR_PIN18_Max (0x1UL)                 /*!< Max enumerator value of PIN18 field.                                 */
24343   #define GPIO_DIR_PIN18_Input (0x0UL)               /*!< Pin set as input                                                     */
24344   #define GPIO_DIR_PIN18_Output (0x1UL)              /*!< Pin set as output                                                    */
24345 
24346 /* PIN19 @Bit 19 : Pin 19 */
24347   #define GPIO_DIR_PIN19_Pos (19UL)                  /*!< Position of PIN19 field.                                             */
24348   #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field.                                       */
24349   #define GPIO_DIR_PIN19_Min (0x0UL)                 /*!< Min enumerator value of PIN19 field.                                 */
24350   #define GPIO_DIR_PIN19_Max (0x1UL)                 /*!< Max enumerator value of PIN19 field.                                 */
24351   #define GPIO_DIR_PIN19_Input (0x0UL)               /*!< Pin set as input                                                     */
24352   #define GPIO_DIR_PIN19_Output (0x1UL)              /*!< Pin set as output                                                    */
24353 
24354 /* PIN20 @Bit 20 : Pin 20 */
24355   #define GPIO_DIR_PIN20_Pos (20UL)                  /*!< Position of PIN20 field.                                             */
24356   #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field.                                       */
24357   #define GPIO_DIR_PIN20_Min (0x0UL)                 /*!< Min enumerator value of PIN20 field.                                 */
24358   #define GPIO_DIR_PIN20_Max (0x1UL)                 /*!< Max enumerator value of PIN20 field.                                 */
24359   #define GPIO_DIR_PIN20_Input (0x0UL)               /*!< Pin set as input                                                     */
24360   #define GPIO_DIR_PIN20_Output (0x1UL)              /*!< Pin set as output                                                    */
24361 
24362 /* PIN21 @Bit 21 : Pin 21 */
24363   #define GPIO_DIR_PIN21_Pos (21UL)                  /*!< Position of PIN21 field.                                             */
24364   #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field.                                       */
24365   #define GPIO_DIR_PIN21_Min (0x0UL)                 /*!< Min enumerator value of PIN21 field.                                 */
24366   #define GPIO_DIR_PIN21_Max (0x1UL)                 /*!< Max enumerator value of PIN21 field.                                 */
24367   #define GPIO_DIR_PIN21_Input (0x0UL)               /*!< Pin set as input                                                     */
24368   #define GPIO_DIR_PIN21_Output (0x1UL)              /*!< Pin set as output                                                    */
24369 
24370 /* PIN22 @Bit 22 : Pin 22 */
24371   #define GPIO_DIR_PIN22_Pos (22UL)                  /*!< Position of PIN22 field.                                             */
24372   #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field.                                       */
24373   #define GPIO_DIR_PIN22_Min (0x0UL)                 /*!< Min enumerator value of PIN22 field.                                 */
24374   #define GPIO_DIR_PIN22_Max (0x1UL)                 /*!< Max enumerator value of PIN22 field.                                 */
24375   #define GPIO_DIR_PIN22_Input (0x0UL)               /*!< Pin set as input                                                     */
24376   #define GPIO_DIR_PIN22_Output (0x1UL)              /*!< Pin set as output                                                    */
24377 
24378 /* PIN23 @Bit 23 : Pin 23 */
24379   #define GPIO_DIR_PIN23_Pos (23UL)                  /*!< Position of PIN23 field.                                             */
24380   #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field.                                       */
24381   #define GPIO_DIR_PIN23_Min (0x0UL)                 /*!< Min enumerator value of PIN23 field.                                 */
24382   #define GPIO_DIR_PIN23_Max (0x1UL)                 /*!< Max enumerator value of PIN23 field.                                 */
24383   #define GPIO_DIR_PIN23_Input (0x0UL)               /*!< Pin set as input                                                     */
24384   #define GPIO_DIR_PIN23_Output (0x1UL)              /*!< Pin set as output                                                    */
24385 
24386 /* PIN24 @Bit 24 : Pin 24 */
24387   #define GPIO_DIR_PIN24_Pos (24UL)                  /*!< Position of PIN24 field.                                             */
24388   #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field.                                       */
24389   #define GPIO_DIR_PIN24_Min (0x0UL)                 /*!< Min enumerator value of PIN24 field.                                 */
24390   #define GPIO_DIR_PIN24_Max (0x1UL)                 /*!< Max enumerator value of PIN24 field.                                 */
24391   #define GPIO_DIR_PIN24_Input (0x0UL)               /*!< Pin set as input                                                     */
24392   #define GPIO_DIR_PIN24_Output (0x1UL)              /*!< Pin set as output                                                    */
24393 
24394 /* PIN25 @Bit 25 : Pin 25 */
24395   #define GPIO_DIR_PIN25_Pos (25UL)                  /*!< Position of PIN25 field.                                             */
24396   #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field.                                       */
24397   #define GPIO_DIR_PIN25_Min (0x0UL)                 /*!< Min enumerator value of PIN25 field.                                 */
24398   #define GPIO_DIR_PIN25_Max (0x1UL)                 /*!< Max enumerator value of PIN25 field.                                 */
24399   #define GPIO_DIR_PIN25_Input (0x0UL)               /*!< Pin set as input                                                     */
24400   #define GPIO_DIR_PIN25_Output (0x1UL)              /*!< Pin set as output                                                    */
24401 
24402 /* PIN26 @Bit 26 : Pin 26 */
24403   #define GPIO_DIR_PIN26_Pos (26UL)                  /*!< Position of PIN26 field.                                             */
24404   #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field.                                       */
24405   #define GPIO_DIR_PIN26_Min (0x0UL)                 /*!< Min enumerator value of PIN26 field.                                 */
24406   #define GPIO_DIR_PIN26_Max (0x1UL)                 /*!< Max enumerator value of PIN26 field.                                 */
24407   #define GPIO_DIR_PIN26_Input (0x0UL)               /*!< Pin set as input                                                     */
24408   #define GPIO_DIR_PIN26_Output (0x1UL)              /*!< Pin set as output                                                    */
24409 
24410 /* PIN27 @Bit 27 : Pin 27 */
24411   #define GPIO_DIR_PIN27_Pos (27UL)                  /*!< Position of PIN27 field.                                             */
24412   #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field.                                       */
24413   #define GPIO_DIR_PIN27_Min (0x0UL)                 /*!< Min enumerator value of PIN27 field.                                 */
24414   #define GPIO_DIR_PIN27_Max (0x1UL)                 /*!< Max enumerator value of PIN27 field.                                 */
24415   #define GPIO_DIR_PIN27_Input (0x0UL)               /*!< Pin set as input                                                     */
24416   #define GPIO_DIR_PIN27_Output (0x1UL)              /*!< Pin set as output                                                    */
24417 
24418 /* PIN28 @Bit 28 : Pin 28 */
24419   #define GPIO_DIR_PIN28_Pos (28UL)                  /*!< Position of PIN28 field.                                             */
24420   #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field.                                       */
24421   #define GPIO_DIR_PIN28_Min (0x0UL)                 /*!< Min enumerator value of PIN28 field.                                 */
24422   #define GPIO_DIR_PIN28_Max (0x1UL)                 /*!< Max enumerator value of PIN28 field.                                 */
24423   #define GPIO_DIR_PIN28_Input (0x0UL)               /*!< Pin set as input                                                     */
24424   #define GPIO_DIR_PIN28_Output (0x1UL)              /*!< Pin set as output                                                    */
24425 
24426 /* PIN29 @Bit 29 : Pin 29 */
24427   #define GPIO_DIR_PIN29_Pos (29UL)                  /*!< Position of PIN29 field.                                             */
24428   #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field.                                       */
24429   #define GPIO_DIR_PIN29_Min (0x0UL)                 /*!< Min enumerator value of PIN29 field.                                 */
24430   #define GPIO_DIR_PIN29_Max (0x1UL)                 /*!< Max enumerator value of PIN29 field.                                 */
24431   #define GPIO_DIR_PIN29_Input (0x0UL)               /*!< Pin set as input                                                     */
24432   #define GPIO_DIR_PIN29_Output (0x1UL)              /*!< Pin set as output                                                    */
24433 
24434 /* PIN30 @Bit 30 : Pin 30 */
24435   #define GPIO_DIR_PIN30_Pos (30UL)                  /*!< Position of PIN30 field.                                             */
24436   #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field.                                       */
24437   #define GPIO_DIR_PIN30_Min (0x0UL)                 /*!< Min enumerator value of PIN30 field.                                 */
24438   #define GPIO_DIR_PIN30_Max (0x1UL)                 /*!< Max enumerator value of PIN30 field.                                 */
24439   #define GPIO_DIR_PIN30_Input (0x0UL)               /*!< Pin set as input                                                     */
24440   #define GPIO_DIR_PIN30_Output (0x1UL)              /*!< Pin set as output                                                    */
24441 
24442 /* PIN31 @Bit 31 : Pin 31 */
24443   #define GPIO_DIR_PIN31_Pos (31UL)                  /*!< Position of PIN31 field.                                             */
24444   #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field.                                       */
24445   #define GPIO_DIR_PIN31_Min (0x0UL)                 /*!< Min enumerator value of PIN31 field.                                 */
24446   #define GPIO_DIR_PIN31_Max (0x1UL)                 /*!< Max enumerator value of PIN31 field.                                 */
24447   #define GPIO_DIR_PIN31_Input (0x0UL)               /*!< Pin set as input                                                     */
24448   #define GPIO_DIR_PIN31_Output (0x1UL)              /*!< Pin set as output                                                    */
24449 
24450 
24451 /* GPIO_DIRSET: DIR set register */
24452   #define GPIO_DIRSET_ResetValue (0x00000000UL)      /*!< Reset value of DIRSET register.                                      */
24453 
24454 /* PIN0 @Bit 0 : Set as output pin 0 */
24455   #define GPIO_DIRSET_PIN0_Pos (0UL)                 /*!< Position of PIN0 field.                                              */
24456   #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field.                                    */
24457   #define GPIO_DIRSET_PIN0_Min (0x0UL)               /*!< Min enumerator value of PIN0 field.                                  */
24458   #define GPIO_DIRSET_PIN0_Max (0x1UL)               /*!< Max enumerator value of PIN0 field.                                  */
24459   #define GPIO_DIRSET_PIN0_Input (0x0UL)             /*!< Read: pin set as input                                               */
24460   #define GPIO_DIRSET_PIN0_Output (0x1UL)            /*!< Read: pin set as output                                              */
24461   #define GPIO_DIRSET_PIN0_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24462 
24463 /* PIN1 @Bit 1 : Set as output pin 1 */
24464   #define GPIO_DIRSET_PIN1_Pos (1UL)                 /*!< Position of PIN1 field.                                              */
24465   #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field.                                    */
24466   #define GPIO_DIRSET_PIN1_Min (0x0UL)               /*!< Min enumerator value of PIN1 field.                                  */
24467   #define GPIO_DIRSET_PIN1_Max (0x1UL)               /*!< Max enumerator value of PIN1 field.                                  */
24468   #define GPIO_DIRSET_PIN1_Input (0x0UL)             /*!< Read: pin set as input                                               */
24469   #define GPIO_DIRSET_PIN1_Output (0x1UL)            /*!< Read: pin set as output                                              */
24470   #define GPIO_DIRSET_PIN1_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24471 
24472 /* PIN2 @Bit 2 : Set as output pin 2 */
24473   #define GPIO_DIRSET_PIN2_Pos (2UL)                 /*!< Position of PIN2 field.                                              */
24474   #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field.                                    */
24475   #define GPIO_DIRSET_PIN2_Min (0x0UL)               /*!< Min enumerator value of PIN2 field.                                  */
24476   #define GPIO_DIRSET_PIN2_Max (0x1UL)               /*!< Max enumerator value of PIN2 field.                                  */
24477   #define GPIO_DIRSET_PIN2_Input (0x0UL)             /*!< Read: pin set as input                                               */
24478   #define GPIO_DIRSET_PIN2_Output (0x1UL)            /*!< Read: pin set as output                                              */
24479   #define GPIO_DIRSET_PIN2_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24480 
24481 /* PIN3 @Bit 3 : Set as output pin 3 */
24482   #define GPIO_DIRSET_PIN3_Pos (3UL)                 /*!< Position of PIN3 field.                                              */
24483   #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field.                                    */
24484   #define GPIO_DIRSET_PIN3_Min (0x0UL)               /*!< Min enumerator value of PIN3 field.                                  */
24485   #define GPIO_DIRSET_PIN3_Max (0x1UL)               /*!< Max enumerator value of PIN3 field.                                  */
24486   #define GPIO_DIRSET_PIN3_Input (0x0UL)             /*!< Read: pin set as input                                               */
24487   #define GPIO_DIRSET_PIN3_Output (0x1UL)            /*!< Read: pin set as output                                              */
24488   #define GPIO_DIRSET_PIN3_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24489 
24490 /* PIN4 @Bit 4 : Set as output pin 4 */
24491   #define GPIO_DIRSET_PIN4_Pos (4UL)                 /*!< Position of PIN4 field.                                              */
24492   #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field.                                    */
24493   #define GPIO_DIRSET_PIN4_Min (0x0UL)               /*!< Min enumerator value of PIN4 field.                                  */
24494   #define GPIO_DIRSET_PIN4_Max (0x1UL)               /*!< Max enumerator value of PIN4 field.                                  */
24495   #define GPIO_DIRSET_PIN4_Input (0x0UL)             /*!< Read: pin set as input                                               */
24496   #define GPIO_DIRSET_PIN4_Output (0x1UL)            /*!< Read: pin set as output                                              */
24497   #define GPIO_DIRSET_PIN4_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24498 
24499 /* PIN5 @Bit 5 : Set as output pin 5 */
24500   #define GPIO_DIRSET_PIN5_Pos (5UL)                 /*!< Position of PIN5 field.                                              */
24501   #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field.                                    */
24502   #define GPIO_DIRSET_PIN5_Min (0x0UL)               /*!< Min enumerator value of PIN5 field.                                  */
24503   #define GPIO_DIRSET_PIN5_Max (0x1UL)               /*!< Max enumerator value of PIN5 field.                                  */
24504   #define GPIO_DIRSET_PIN5_Input (0x0UL)             /*!< Read: pin set as input                                               */
24505   #define GPIO_DIRSET_PIN5_Output (0x1UL)            /*!< Read: pin set as output                                              */
24506   #define GPIO_DIRSET_PIN5_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24507 
24508 /* PIN6 @Bit 6 : Set as output pin 6 */
24509   #define GPIO_DIRSET_PIN6_Pos (6UL)                 /*!< Position of PIN6 field.                                              */
24510   #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field.                                    */
24511   #define GPIO_DIRSET_PIN6_Min (0x0UL)               /*!< Min enumerator value of PIN6 field.                                  */
24512   #define GPIO_DIRSET_PIN6_Max (0x1UL)               /*!< Max enumerator value of PIN6 field.                                  */
24513   #define GPIO_DIRSET_PIN6_Input (0x0UL)             /*!< Read: pin set as input                                               */
24514   #define GPIO_DIRSET_PIN6_Output (0x1UL)            /*!< Read: pin set as output                                              */
24515   #define GPIO_DIRSET_PIN6_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24516 
24517 /* PIN7 @Bit 7 : Set as output pin 7 */
24518   #define GPIO_DIRSET_PIN7_Pos (7UL)                 /*!< Position of PIN7 field.                                              */
24519   #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field.                                    */
24520   #define GPIO_DIRSET_PIN7_Min (0x0UL)               /*!< Min enumerator value of PIN7 field.                                  */
24521   #define GPIO_DIRSET_PIN7_Max (0x1UL)               /*!< Max enumerator value of PIN7 field.                                  */
24522   #define GPIO_DIRSET_PIN7_Input (0x0UL)             /*!< Read: pin set as input                                               */
24523   #define GPIO_DIRSET_PIN7_Output (0x1UL)            /*!< Read: pin set as output                                              */
24524   #define GPIO_DIRSET_PIN7_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24525 
24526 /* PIN8 @Bit 8 : Set as output pin 8 */
24527   #define GPIO_DIRSET_PIN8_Pos (8UL)                 /*!< Position of PIN8 field.                                              */
24528   #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field.                                    */
24529   #define GPIO_DIRSET_PIN8_Min (0x0UL)               /*!< Min enumerator value of PIN8 field.                                  */
24530   #define GPIO_DIRSET_PIN8_Max (0x1UL)               /*!< Max enumerator value of PIN8 field.                                  */
24531   #define GPIO_DIRSET_PIN8_Input (0x0UL)             /*!< Read: pin set as input                                               */
24532   #define GPIO_DIRSET_PIN8_Output (0x1UL)            /*!< Read: pin set as output                                              */
24533   #define GPIO_DIRSET_PIN8_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24534 
24535 /* PIN9 @Bit 9 : Set as output pin 9 */
24536   #define GPIO_DIRSET_PIN9_Pos (9UL)                 /*!< Position of PIN9 field.                                              */
24537   #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field.                                    */
24538   #define GPIO_DIRSET_PIN9_Min (0x0UL)               /*!< Min enumerator value of PIN9 field.                                  */
24539   #define GPIO_DIRSET_PIN9_Max (0x1UL)               /*!< Max enumerator value of PIN9 field.                                  */
24540   #define GPIO_DIRSET_PIN9_Input (0x0UL)             /*!< Read: pin set as input                                               */
24541   #define GPIO_DIRSET_PIN9_Output (0x1UL)            /*!< Read: pin set as output                                              */
24542   #define GPIO_DIRSET_PIN9_Set (0x1UL)               /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24543 
24544 /* PIN10 @Bit 10 : Set as output pin 10 */
24545   #define GPIO_DIRSET_PIN10_Pos (10UL)               /*!< Position of PIN10 field.                                             */
24546   #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field.                                 */
24547   #define GPIO_DIRSET_PIN10_Min (0x0UL)              /*!< Min enumerator value of PIN10 field.                                 */
24548   #define GPIO_DIRSET_PIN10_Max (0x1UL)              /*!< Max enumerator value of PIN10 field.                                 */
24549   #define GPIO_DIRSET_PIN10_Input (0x0UL)            /*!< Read: pin set as input                                               */
24550   #define GPIO_DIRSET_PIN10_Output (0x1UL)           /*!< Read: pin set as output                                              */
24551   #define GPIO_DIRSET_PIN10_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24552 
24553 /* PIN11 @Bit 11 : Set as output pin 11 */
24554   #define GPIO_DIRSET_PIN11_Pos (11UL)               /*!< Position of PIN11 field.                                             */
24555   #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field.                                 */
24556   #define GPIO_DIRSET_PIN11_Min (0x0UL)              /*!< Min enumerator value of PIN11 field.                                 */
24557   #define GPIO_DIRSET_PIN11_Max (0x1UL)              /*!< Max enumerator value of PIN11 field.                                 */
24558   #define GPIO_DIRSET_PIN11_Input (0x0UL)            /*!< Read: pin set as input                                               */
24559   #define GPIO_DIRSET_PIN11_Output (0x1UL)           /*!< Read: pin set as output                                              */
24560   #define GPIO_DIRSET_PIN11_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24561 
24562 /* PIN12 @Bit 12 : Set as output pin 12 */
24563   #define GPIO_DIRSET_PIN12_Pos (12UL)               /*!< Position of PIN12 field.                                             */
24564   #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field.                                 */
24565   #define GPIO_DIRSET_PIN12_Min (0x0UL)              /*!< Min enumerator value of PIN12 field.                                 */
24566   #define GPIO_DIRSET_PIN12_Max (0x1UL)              /*!< Max enumerator value of PIN12 field.                                 */
24567   #define GPIO_DIRSET_PIN12_Input (0x0UL)            /*!< Read: pin set as input                                               */
24568   #define GPIO_DIRSET_PIN12_Output (0x1UL)           /*!< Read: pin set as output                                              */
24569   #define GPIO_DIRSET_PIN12_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24570 
24571 /* PIN13 @Bit 13 : Set as output pin 13 */
24572   #define GPIO_DIRSET_PIN13_Pos (13UL)               /*!< Position of PIN13 field.                                             */
24573   #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field.                                 */
24574   #define GPIO_DIRSET_PIN13_Min (0x0UL)              /*!< Min enumerator value of PIN13 field.                                 */
24575   #define GPIO_DIRSET_PIN13_Max (0x1UL)              /*!< Max enumerator value of PIN13 field.                                 */
24576   #define GPIO_DIRSET_PIN13_Input (0x0UL)            /*!< Read: pin set as input                                               */
24577   #define GPIO_DIRSET_PIN13_Output (0x1UL)           /*!< Read: pin set as output                                              */
24578   #define GPIO_DIRSET_PIN13_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24579 
24580 /* PIN14 @Bit 14 : Set as output pin 14 */
24581   #define GPIO_DIRSET_PIN14_Pos (14UL)               /*!< Position of PIN14 field.                                             */
24582   #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field.                                 */
24583   #define GPIO_DIRSET_PIN14_Min (0x0UL)              /*!< Min enumerator value of PIN14 field.                                 */
24584   #define GPIO_DIRSET_PIN14_Max (0x1UL)              /*!< Max enumerator value of PIN14 field.                                 */
24585   #define GPIO_DIRSET_PIN14_Input (0x0UL)            /*!< Read: pin set as input                                               */
24586   #define GPIO_DIRSET_PIN14_Output (0x1UL)           /*!< Read: pin set as output                                              */
24587   #define GPIO_DIRSET_PIN14_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24588 
24589 /* PIN15 @Bit 15 : Set as output pin 15 */
24590   #define GPIO_DIRSET_PIN15_Pos (15UL)               /*!< Position of PIN15 field.                                             */
24591   #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field.                                 */
24592   #define GPIO_DIRSET_PIN15_Min (0x0UL)              /*!< Min enumerator value of PIN15 field.                                 */
24593   #define GPIO_DIRSET_PIN15_Max (0x1UL)              /*!< Max enumerator value of PIN15 field.                                 */
24594   #define GPIO_DIRSET_PIN15_Input (0x0UL)            /*!< Read: pin set as input                                               */
24595   #define GPIO_DIRSET_PIN15_Output (0x1UL)           /*!< Read: pin set as output                                              */
24596   #define GPIO_DIRSET_PIN15_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24597 
24598 /* PIN16 @Bit 16 : Set as output pin 16 */
24599   #define GPIO_DIRSET_PIN16_Pos (16UL)               /*!< Position of PIN16 field.                                             */
24600   #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field.                                 */
24601   #define GPIO_DIRSET_PIN16_Min (0x0UL)              /*!< Min enumerator value of PIN16 field.                                 */
24602   #define GPIO_DIRSET_PIN16_Max (0x1UL)              /*!< Max enumerator value of PIN16 field.                                 */
24603   #define GPIO_DIRSET_PIN16_Input (0x0UL)            /*!< Read: pin set as input                                               */
24604   #define GPIO_DIRSET_PIN16_Output (0x1UL)           /*!< Read: pin set as output                                              */
24605   #define GPIO_DIRSET_PIN16_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24606 
24607 /* PIN17 @Bit 17 : Set as output pin 17 */
24608   #define GPIO_DIRSET_PIN17_Pos (17UL)               /*!< Position of PIN17 field.                                             */
24609   #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field.                                 */
24610   #define GPIO_DIRSET_PIN17_Min (0x0UL)              /*!< Min enumerator value of PIN17 field.                                 */
24611   #define GPIO_DIRSET_PIN17_Max (0x1UL)              /*!< Max enumerator value of PIN17 field.                                 */
24612   #define GPIO_DIRSET_PIN17_Input (0x0UL)            /*!< Read: pin set as input                                               */
24613   #define GPIO_DIRSET_PIN17_Output (0x1UL)           /*!< Read: pin set as output                                              */
24614   #define GPIO_DIRSET_PIN17_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24615 
24616 /* PIN18 @Bit 18 : Set as output pin 18 */
24617   #define GPIO_DIRSET_PIN18_Pos (18UL)               /*!< Position of PIN18 field.                                             */
24618   #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field.                                 */
24619   #define GPIO_DIRSET_PIN18_Min (0x0UL)              /*!< Min enumerator value of PIN18 field.                                 */
24620   #define GPIO_DIRSET_PIN18_Max (0x1UL)              /*!< Max enumerator value of PIN18 field.                                 */
24621   #define GPIO_DIRSET_PIN18_Input (0x0UL)            /*!< Read: pin set as input                                               */
24622   #define GPIO_DIRSET_PIN18_Output (0x1UL)           /*!< Read: pin set as output                                              */
24623   #define GPIO_DIRSET_PIN18_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24624 
24625 /* PIN19 @Bit 19 : Set as output pin 19 */
24626   #define GPIO_DIRSET_PIN19_Pos (19UL)               /*!< Position of PIN19 field.                                             */
24627   #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field.                                 */
24628   #define GPIO_DIRSET_PIN19_Min (0x0UL)              /*!< Min enumerator value of PIN19 field.                                 */
24629   #define GPIO_DIRSET_PIN19_Max (0x1UL)              /*!< Max enumerator value of PIN19 field.                                 */
24630   #define GPIO_DIRSET_PIN19_Input (0x0UL)            /*!< Read: pin set as input                                               */
24631   #define GPIO_DIRSET_PIN19_Output (0x1UL)           /*!< Read: pin set as output                                              */
24632   #define GPIO_DIRSET_PIN19_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24633 
24634 /* PIN20 @Bit 20 : Set as output pin 20 */
24635   #define GPIO_DIRSET_PIN20_Pos (20UL)               /*!< Position of PIN20 field.                                             */
24636   #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field.                                 */
24637   #define GPIO_DIRSET_PIN20_Min (0x0UL)              /*!< Min enumerator value of PIN20 field.                                 */
24638   #define GPIO_DIRSET_PIN20_Max (0x1UL)              /*!< Max enumerator value of PIN20 field.                                 */
24639   #define GPIO_DIRSET_PIN20_Input (0x0UL)            /*!< Read: pin set as input                                               */
24640   #define GPIO_DIRSET_PIN20_Output (0x1UL)           /*!< Read: pin set as output                                              */
24641   #define GPIO_DIRSET_PIN20_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24642 
24643 /* PIN21 @Bit 21 : Set as output pin 21 */
24644   #define GPIO_DIRSET_PIN21_Pos (21UL)               /*!< Position of PIN21 field.                                             */
24645   #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field.                                 */
24646   #define GPIO_DIRSET_PIN21_Min (0x0UL)              /*!< Min enumerator value of PIN21 field.                                 */
24647   #define GPIO_DIRSET_PIN21_Max (0x1UL)              /*!< Max enumerator value of PIN21 field.                                 */
24648   #define GPIO_DIRSET_PIN21_Input (0x0UL)            /*!< Read: pin set as input                                               */
24649   #define GPIO_DIRSET_PIN21_Output (0x1UL)           /*!< Read: pin set as output                                              */
24650   #define GPIO_DIRSET_PIN21_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24651 
24652 /* PIN22 @Bit 22 : Set as output pin 22 */
24653   #define GPIO_DIRSET_PIN22_Pos (22UL)               /*!< Position of PIN22 field.                                             */
24654   #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field.                                 */
24655   #define GPIO_DIRSET_PIN22_Min (0x0UL)              /*!< Min enumerator value of PIN22 field.                                 */
24656   #define GPIO_DIRSET_PIN22_Max (0x1UL)              /*!< Max enumerator value of PIN22 field.                                 */
24657   #define GPIO_DIRSET_PIN22_Input (0x0UL)            /*!< Read: pin set as input                                               */
24658   #define GPIO_DIRSET_PIN22_Output (0x1UL)           /*!< Read: pin set as output                                              */
24659   #define GPIO_DIRSET_PIN22_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24660 
24661 /* PIN23 @Bit 23 : Set as output pin 23 */
24662   #define GPIO_DIRSET_PIN23_Pos (23UL)               /*!< Position of PIN23 field.                                             */
24663   #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field.                                 */
24664   #define GPIO_DIRSET_PIN23_Min (0x0UL)              /*!< Min enumerator value of PIN23 field.                                 */
24665   #define GPIO_DIRSET_PIN23_Max (0x1UL)              /*!< Max enumerator value of PIN23 field.                                 */
24666   #define GPIO_DIRSET_PIN23_Input (0x0UL)            /*!< Read: pin set as input                                               */
24667   #define GPIO_DIRSET_PIN23_Output (0x1UL)           /*!< Read: pin set as output                                              */
24668   #define GPIO_DIRSET_PIN23_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24669 
24670 /* PIN24 @Bit 24 : Set as output pin 24 */
24671   #define GPIO_DIRSET_PIN24_Pos (24UL)               /*!< Position of PIN24 field.                                             */
24672   #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field.                                 */
24673   #define GPIO_DIRSET_PIN24_Min (0x0UL)              /*!< Min enumerator value of PIN24 field.                                 */
24674   #define GPIO_DIRSET_PIN24_Max (0x1UL)              /*!< Max enumerator value of PIN24 field.                                 */
24675   #define GPIO_DIRSET_PIN24_Input (0x0UL)            /*!< Read: pin set as input                                               */
24676   #define GPIO_DIRSET_PIN24_Output (0x1UL)           /*!< Read: pin set as output                                              */
24677   #define GPIO_DIRSET_PIN24_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24678 
24679 /* PIN25 @Bit 25 : Set as output pin 25 */
24680   #define GPIO_DIRSET_PIN25_Pos (25UL)               /*!< Position of PIN25 field.                                             */
24681   #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field.                                 */
24682   #define GPIO_DIRSET_PIN25_Min (0x0UL)              /*!< Min enumerator value of PIN25 field.                                 */
24683   #define GPIO_DIRSET_PIN25_Max (0x1UL)              /*!< Max enumerator value of PIN25 field.                                 */
24684   #define GPIO_DIRSET_PIN25_Input (0x0UL)            /*!< Read: pin set as input                                               */
24685   #define GPIO_DIRSET_PIN25_Output (0x1UL)           /*!< Read: pin set as output                                              */
24686   #define GPIO_DIRSET_PIN25_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24687 
24688 /* PIN26 @Bit 26 : Set as output pin 26 */
24689   #define GPIO_DIRSET_PIN26_Pos (26UL)               /*!< Position of PIN26 field.                                             */
24690   #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field.                                 */
24691   #define GPIO_DIRSET_PIN26_Min (0x0UL)              /*!< Min enumerator value of PIN26 field.                                 */
24692   #define GPIO_DIRSET_PIN26_Max (0x1UL)              /*!< Max enumerator value of PIN26 field.                                 */
24693   #define GPIO_DIRSET_PIN26_Input (0x0UL)            /*!< Read: pin set as input                                               */
24694   #define GPIO_DIRSET_PIN26_Output (0x1UL)           /*!< Read: pin set as output                                              */
24695   #define GPIO_DIRSET_PIN26_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24696 
24697 /* PIN27 @Bit 27 : Set as output pin 27 */
24698   #define GPIO_DIRSET_PIN27_Pos (27UL)               /*!< Position of PIN27 field.                                             */
24699   #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field.                                 */
24700   #define GPIO_DIRSET_PIN27_Min (0x0UL)              /*!< Min enumerator value of PIN27 field.                                 */
24701   #define GPIO_DIRSET_PIN27_Max (0x1UL)              /*!< Max enumerator value of PIN27 field.                                 */
24702   #define GPIO_DIRSET_PIN27_Input (0x0UL)            /*!< Read: pin set as input                                               */
24703   #define GPIO_DIRSET_PIN27_Output (0x1UL)           /*!< Read: pin set as output                                              */
24704   #define GPIO_DIRSET_PIN27_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24705 
24706 /* PIN28 @Bit 28 : Set as output pin 28 */
24707   #define GPIO_DIRSET_PIN28_Pos (28UL)               /*!< Position of PIN28 field.                                             */
24708   #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field.                                 */
24709   #define GPIO_DIRSET_PIN28_Min (0x0UL)              /*!< Min enumerator value of PIN28 field.                                 */
24710   #define GPIO_DIRSET_PIN28_Max (0x1UL)              /*!< Max enumerator value of PIN28 field.                                 */
24711   #define GPIO_DIRSET_PIN28_Input (0x0UL)            /*!< Read: pin set as input                                               */
24712   #define GPIO_DIRSET_PIN28_Output (0x1UL)           /*!< Read: pin set as output                                              */
24713   #define GPIO_DIRSET_PIN28_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24714 
24715 /* PIN29 @Bit 29 : Set as output pin 29 */
24716   #define GPIO_DIRSET_PIN29_Pos (29UL)               /*!< Position of PIN29 field.                                             */
24717   #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field.                                 */
24718   #define GPIO_DIRSET_PIN29_Min (0x0UL)              /*!< Min enumerator value of PIN29 field.                                 */
24719   #define GPIO_DIRSET_PIN29_Max (0x1UL)              /*!< Max enumerator value of PIN29 field.                                 */
24720   #define GPIO_DIRSET_PIN29_Input (0x0UL)            /*!< Read: pin set as input                                               */
24721   #define GPIO_DIRSET_PIN29_Output (0x1UL)           /*!< Read: pin set as output                                              */
24722   #define GPIO_DIRSET_PIN29_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24723 
24724 /* PIN30 @Bit 30 : Set as output pin 30 */
24725   #define GPIO_DIRSET_PIN30_Pos (30UL)               /*!< Position of PIN30 field.                                             */
24726   #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field.                                 */
24727   #define GPIO_DIRSET_PIN30_Min (0x0UL)              /*!< Min enumerator value of PIN30 field.                                 */
24728   #define GPIO_DIRSET_PIN30_Max (0x1UL)              /*!< Max enumerator value of PIN30 field.                                 */
24729   #define GPIO_DIRSET_PIN30_Input (0x0UL)            /*!< Read: pin set as input                                               */
24730   #define GPIO_DIRSET_PIN30_Output (0x1UL)           /*!< Read: pin set as output                                              */
24731   #define GPIO_DIRSET_PIN30_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24732 
24733 /* PIN31 @Bit 31 : Set as output pin 31 */
24734   #define GPIO_DIRSET_PIN31_Pos (31UL)               /*!< Position of PIN31 field.                                             */
24735   #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field.                                 */
24736   #define GPIO_DIRSET_PIN31_Min (0x0UL)              /*!< Min enumerator value of PIN31 field.                                 */
24737   #define GPIO_DIRSET_PIN31_Max (0x1UL)              /*!< Max enumerator value of PIN31 field.                                 */
24738   #define GPIO_DIRSET_PIN31_Input (0x0UL)            /*!< Read: pin set as input                                               */
24739   #define GPIO_DIRSET_PIN31_Output (0x1UL)           /*!< Read: pin set as output                                              */
24740   #define GPIO_DIRSET_PIN31_Set (0x1UL)              /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
24741 
24742 
24743 /* GPIO_DIRCLR: DIR clear register */
24744   #define GPIO_DIRCLR_ResetValue (0x00000000UL)      /*!< Reset value of DIRCLR register.                                      */
24745 
24746 /* PIN0 @Bit 0 : Set as input pin 0 */
24747   #define GPIO_DIRCLR_PIN0_Pos (0UL)                 /*!< Position of PIN0 field.                                              */
24748   #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field.                                    */
24749   #define GPIO_DIRCLR_PIN0_Min (0x0UL)               /*!< Min enumerator value of PIN0 field.                                  */
24750   #define GPIO_DIRCLR_PIN0_Max (0x1UL)               /*!< Max enumerator value of PIN0 field.                                  */
24751   #define GPIO_DIRCLR_PIN0_Input (0x0UL)             /*!< Read: pin set as input                                               */
24752   #define GPIO_DIRCLR_PIN0_Output (0x1UL)            /*!< Read: pin set as output                                              */
24753   #define GPIO_DIRCLR_PIN0_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24754 
24755 /* PIN1 @Bit 1 : Set as input pin 1 */
24756   #define GPIO_DIRCLR_PIN1_Pos (1UL)                 /*!< Position of PIN1 field.                                              */
24757   #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field.                                    */
24758   #define GPIO_DIRCLR_PIN1_Min (0x0UL)               /*!< Min enumerator value of PIN1 field.                                  */
24759   #define GPIO_DIRCLR_PIN1_Max (0x1UL)               /*!< Max enumerator value of PIN1 field.                                  */
24760   #define GPIO_DIRCLR_PIN1_Input (0x0UL)             /*!< Read: pin set as input                                               */
24761   #define GPIO_DIRCLR_PIN1_Output (0x1UL)            /*!< Read: pin set as output                                              */
24762   #define GPIO_DIRCLR_PIN1_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24763 
24764 /* PIN2 @Bit 2 : Set as input pin 2 */
24765   #define GPIO_DIRCLR_PIN2_Pos (2UL)                 /*!< Position of PIN2 field.                                              */
24766   #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field.                                    */
24767   #define GPIO_DIRCLR_PIN2_Min (0x0UL)               /*!< Min enumerator value of PIN2 field.                                  */
24768   #define GPIO_DIRCLR_PIN2_Max (0x1UL)               /*!< Max enumerator value of PIN2 field.                                  */
24769   #define GPIO_DIRCLR_PIN2_Input (0x0UL)             /*!< Read: pin set as input                                               */
24770   #define GPIO_DIRCLR_PIN2_Output (0x1UL)            /*!< Read: pin set as output                                              */
24771   #define GPIO_DIRCLR_PIN2_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24772 
24773 /* PIN3 @Bit 3 : Set as input pin 3 */
24774   #define GPIO_DIRCLR_PIN3_Pos (3UL)                 /*!< Position of PIN3 field.                                              */
24775   #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field.                                    */
24776   #define GPIO_DIRCLR_PIN3_Min (0x0UL)               /*!< Min enumerator value of PIN3 field.                                  */
24777   #define GPIO_DIRCLR_PIN3_Max (0x1UL)               /*!< Max enumerator value of PIN3 field.                                  */
24778   #define GPIO_DIRCLR_PIN3_Input (0x0UL)             /*!< Read: pin set as input                                               */
24779   #define GPIO_DIRCLR_PIN3_Output (0x1UL)            /*!< Read: pin set as output                                              */
24780   #define GPIO_DIRCLR_PIN3_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24781 
24782 /* PIN4 @Bit 4 : Set as input pin 4 */
24783   #define GPIO_DIRCLR_PIN4_Pos (4UL)                 /*!< Position of PIN4 field.                                              */
24784   #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field.                                    */
24785   #define GPIO_DIRCLR_PIN4_Min (0x0UL)               /*!< Min enumerator value of PIN4 field.                                  */
24786   #define GPIO_DIRCLR_PIN4_Max (0x1UL)               /*!< Max enumerator value of PIN4 field.                                  */
24787   #define GPIO_DIRCLR_PIN4_Input (0x0UL)             /*!< Read: pin set as input                                               */
24788   #define GPIO_DIRCLR_PIN4_Output (0x1UL)            /*!< Read: pin set as output                                              */
24789   #define GPIO_DIRCLR_PIN4_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24790 
24791 /* PIN5 @Bit 5 : Set as input pin 5 */
24792   #define GPIO_DIRCLR_PIN5_Pos (5UL)                 /*!< Position of PIN5 field.                                              */
24793   #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field.                                    */
24794   #define GPIO_DIRCLR_PIN5_Min (0x0UL)               /*!< Min enumerator value of PIN5 field.                                  */
24795   #define GPIO_DIRCLR_PIN5_Max (0x1UL)               /*!< Max enumerator value of PIN5 field.                                  */
24796   #define GPIO_DIRCLR_PIN5_Input (0x0UL)             /*!< Read: pin set as input                                               */
24797   #define GPIO_DIRCLR_PIN5_Output (0x1UL)            /*!< Read: pin set as output                                              */
24798   #define GPIO_DIRCLR_PIN5_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24799 
24800 /* PIN6 @Bit 6 : Set as input pin 6 */
24801   #define GPIO_DIRCLR_PIN6_Pos (6UL)                 /*!< Position of PIN6 field.                                              */
24802   #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field.                                    */
24803   #define GPIO_DIRCLR_PIN6_Min (0x0UL)               /*!< Min enumerator value of PIN6 field.                                  */
24804   #define GPIO_DIRCLR_PIN6_Max (0x1UL)               /*!< Max enumerator value of PIN6 field.                                  */
24805   #define GPIO_DIRCLR_PIN6_Input (0x0UL)             /*!< Read: pin set as input                                               */
24806   #define GPIO_DIRCLR_PIN6_Output (0x1UL)            /*!< Read: pin set as output                                              */
24807   #define GPIO_DIRCLR_PIN6_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24808 
24809 /* PIN7 @Bit 7 : Set as input pin 7 */
24810   #define GPIO_DIRCLR_PIN7_Pos (7UL)                 /*!< Position of PIN7 field.                                              */
24811   #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field.                                    */
24812   #define GPIO_DIRCLR_PIN7_Min (0x0UL)               /*!< Min enumerator value of PIN7 field.                                  */
24813   #define GPIO_DIRCLR_PIN7_Max (0x1UL)               /*!< Max enumerator value of PIN7 field.                                  */
24814   #define GPIO_DIRCLR_PIN7_Input (0x0UL)             /*!< Read: pin set as input                                               */
24815   #define GPIO_DIRCLR_PIN7_Output (0x1UL)            /*!< Read: pin set as output                                              */
24816   #define GPIO_DIRCLR_PIN7_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24817 
24818 /* PIN8 @Bit 8 : Set as input pin 8 */
24819   #define GPIO_DIRCLR_PIN8_Pos (8UL)                 /*!< Position of PIN8 field.                                              */
24820   #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field.                                    */
24821   #define GPIO_DIRCLR_PIN8_Min (0x0UL)               /*!< Min enumerator value of PIN8 field.                                  */
24822   #define GPIO_DIRCLR_PIN8_Max (0x1UL)               /*!< Max enumerator value of PIN8 field.                                  */
24823   #define GPIO_DIRCLR_PIN8_Input (0x0UL)             /*!< Read: pin set as input                                               */
24824   #define GPIO_DIRCLR_PIN8_Output (0x1UL)            /*!< Read: pin set as output                                              */
24825   #define GPIO_DIRCLR_PIN8_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24826 
24827 /* PIN9 @Bit 9 : Set as input pin 9 */
24828   #define GPIO_DIRCLR_PIN9_Pos (9UL)                 /*!< Position of PIN9 field.                                              */
24829   #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field.                                    */
24830   #define GPIO_DIRCLR_PIN9_Min (0x0UL)               /*!< Min enumerator value of PIN9 field.                                  */
24831   #define GPIO_DIRCLR_PIN9_Max (0x1UL)               /*!< Max enumerator value of PIN9 field.                                  */
24832   #define GPIO_DIRCLR_PIN9_Input (0x0UL)             /*!< Read: pin set as input                                               */
24833   #define GPIO_DIRCLR_PIN9_Output (0x1UL)            /*!< Read: pin set as output                                              */
24834   #define GPIO_DIRCLR_PIN9_Clear (0x1UL)             /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24835 
24836 /* PIN10 @Bit 10 : Set as input pin 10 */
24837   #define GPIO_DIRCLR_PIN10_Pos (10UL)               /*!< Position of PIN10 field.                                             */
24838   #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field.                                 */
24839   #define GPIO_DIRCLR_PIN10_Min (0x0UL)              /*!< Min enumerator value of PIN10 field.                                 */
24840   #define GPIO_DIRCLR_PIN10_Max (0x1UL)              /*!< Max enumerator value of PIN10 field.                                 */
24841   #define GPIO_DIRCLR_PIN10_Input (0x0UL)            /*!< Read: pin set as input                                               */
24842   #define GPIO_DIRCLR_PIN10_Output (0x1UL)           /*!< Read: pin set as output                                              */
24843   #define GPIO_DIRCLR_PIN10_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24844 
24845 /* PIN11 @Bit 11 : Set as input pin 11 */
24846   #define GPIO_DIRCLR_PIN11_Pos (11UL)               /*!< Position of PIN11 field.                                             */
24847   #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field.                                 */
24848   #define GPIO_DIRCLR_PIN11_Min (0x0UL)              /*!< Min enumerator value of PIN11 field.                                 */
24849   #define GPIO_DIRCLR_PIN11_Max (0x1UL)              /*!< Max enumerator value of PIN11 field.                                 */
24850   #define GPIO_DIRCLR_PIN11_Input (0x0UL)            /*!< Read: pin set as input                                               */
24851   #define GPIO_DIRCLR_PIN11_Output (0x1UL)           /*!< Read: pin set as output                                              */
24852   #define GPIO_DIRCLR_PIN11_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24853 
24854 /* PIN12 @Bit 12 : Set as input pin 12 */
24855   #define GPIO_DIRCLR_PIN12_Pos (12UL)               /*!< Position of PIN12 field.                                             */
24856   #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field.                                 */
24857   #define GPIO_DIRCLR_PIN12_Min (0x0UL)              /*!< Min enumerator value of PIN12 field.                                 */
24858   #define GPIO_DIRCLR_PIN12_Max (0x1UL)              /*!< Max enumerator value of PIN12 field.                                 */
24859   #define GPIO_DIRCLR_PIN12_Input (0x0UL)            /*!< Read: pin set as input                                               */
24860   #define GPIO_DIRCLR_PIN12_Output (0x1UL)           /*!< Read: pin set as output                                              */
24861   #define GPIO_DIRCLR_PIN12_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24862 
24863 /* PIN13 @Bit 13 : Set as input pin 13 */
24864   #define GPIO_DIRCLR_PIN13_Pos (13UL)               /*!< Position of PIN13 field.                                             */
24865   #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field.                                 */
24866   #define GPIO_DIRCLR_PIN13_Min (0x0UL)              /*!< Min enumerator value of PIN13 field.                                 */
24867   #define GPIO_DIRCLR_PIN13_Max (0x1UL)              /*!< Max enumerator value of PIN13 field.                                 */
24868   #define GPIO_DIRCLR_PIN13_Input (0x0UL)            /*!< Read: pin set as input                                               */
24869   #define GPIO_DIRCLR_PIN13_Output (0x1UL)           /*!< Read: pin set as output                                              */
24870   #define GPIO_DIRCLR_PIN13_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24871 
24872 /* PIN14 @Bit 14 : Set as input pin 14 */
24873   #define GPIO_DIRCLR_PIN14_Pos (14UL)               /*!< Position of PIN14 field.                                             */
24874   #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field.                                 */
24875   #define GPIO_DIRCLR_PIN14_Min (0x0UL)              /*!< Min enumerator value of PIN14 field.                                 */
24876   #define GPIO_DIRCLR_PIN14_Max (0x1UL)              /*!< Max enumerator value of PIN14 field.                                 */
24877   #define GPIO_DIRCLR_PIN14_Input (0x0UL)            /*!< Read: pin set as input                                               */
24878   #define GPIO_DIRCLR_PIN14_Output (0x1UL)           /*!< Read: pin set as output                                              */
24879   #define GPIO_DIRCLR_PIN14_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24880 
24881 /* PIN15 @Bit 15 : Set as input pin 15 */
24882   #define GPIO_DIRCLR_PIN15_Pos (15UL)               /*!< Position of PIN15 field.                                             */
24883   #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field.                                 */
24884   #define GPIO_DIRCLR_PIN15_Min (0x0UL)              /*!< Min enumerator value of PIN15 field.                                 */
24885   #define GPIO_DIRCLR_PIN15_Max (0x1UL)              /*!< Max enumerator value of PIN15 field.                                 */
24886   #define GPIO_DIRCLR_PIN15_Input (0x0UL)            /*!< Read: pin set as input                                               */
24887   #define GPIO_DIRCLR_PIN15_Output (0x1UL)           /*!< Read: pin set as output                                              */
24888   #define GPIO_DIRCLR_PIN15_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24889 
24890 /* PIN16 @Bit 16 : Set as input pin 16 */
24891   #define GPIO_DIRCLR_PIN16_Pos (16UL)               /*!< Position of PIN16 field.                                             */
24892   #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field.                                 */
24893   #define GPIO_DIRCLR_PIN16_Min (0x0UL)              /*!< Min enumerator value of PIN16 field.                                 */
24894   #define GPIO_DIRCLR_PIN16_Max (0x1UL)              /*!< Max enumerator value of PIN16 field.                                 */
24895   #define GPIO_DIRCLR_PIN16_Input (0x0UL)            /*!< Read: pin set as input                                               */
24896   #define GPIO_DIRCLR_PIN16_Output (0x1UL)           /*!< Read: pin set as output                                              */
24897   #define GPIO_DIRCLR_PIN16_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24898 
24899 /* PIN17 @Bit 17 : Set as input pin 17 */
24900   #define GPIO_DIRCLR_PIN17_Pos (17UL)               /*!< Position of PIN17 field.                                             */
24901   #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field.                                 */
24902   #define GPIO_DIRCLR_PIN17_Min (0x0UL)              /*!< Min enumerator value of PIN17 field.                                 */
24903   #define GPIO_DIRCLR_PIN17_Max (0x1UL)              /*!< Max enumerator value of PIN17 field.                                 */
24904   #define GPIO_DIRCLR_PIN17_Input (0x0UL)            /*!< Read: pin set as input                                               */
24905   #define GPIO_DIRCLR_PIN17_Output (0x1UL)           /*!< Read: pin set as output                                              */
24906   #define GPIO_DIRCLR_PIN17_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24907 
24908 /* PIN18 @Bit 18 : Set as input pin 18 */
24909   #define GPIO_DIRCLR_PIN18_Pos (18UL)               /*!< Position of PIN18 field.                                             */
24910   #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field.                                 */
24911   #define GPIO_DIRCLR_PIN18_Min (0x0UL)              /*!< Min enumerator value of PIN18 field.                                 */
24912   #define GPIO_DIRCLR_PIN18_Max (0x1UL)              /*!< Max enumerator value of PIN18 field.                                 */
24913   #define GPIO_DIRCLR_PIN18_Input (0x0UL)            /*!< Read: pin set as input                                               */
24914   #define GPIO_DIRCLR_PIN18_Output (0x1UL)           /*!< Read: pin set as output                                              */
24915   #define GPIO_DIRCLR_PIN18_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24916 
24917 /* PIN19 @Bit 19 : Set as input pin 19 */
24918   #define GPIO_DIRCLR_PIN19_Pos (19UL)               /*!< Position of PIN19 field.                                             */
24919   #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field.                                 */
24920   #define GPIO_DIRCLR_PIN19_Min (0x0UL)              /*!< Min enumerator value of PIN19 field.                                 */
24921   #define GPIO_DIRCLR_PIN19_Max (0x1UL)              /*!< Max enumerator value of PIN19 field.                                 */
24922   #define GPIO_DIRCLR_PIN19_Input (0x0UL)            /*!< Read: pin set as input                                               */
24923   #define GPIO_DIRCLR_PIN19_Output (0x1UL)           /*!< Read: pin set as output                                              */
24924   #define GPIO_DIRCLR_PIN19_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24925 
24926 /* PIN20 @Bit 20 : Set as input pin 20 */
24927   #define GPIO_DIRCLR_PIN20_Pos (20UL)               /*!< Position of PIN20 field.                                             */
24928   #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field.                                 */
24929   #define GPIO_DIRCLR_PIN20_Min (0x0UL)              /*!< Min enumerator value of PIN20 field.                                 */
24930   #define GPIO_DIRCLR_PIN20_Max (0x1UL)              /*!< Max enumerator value of PIN20 field.                                 */
24931   #define GPIO_DIRCLR_PIN20_Input (0x0UL)            /*!< Read: pin set as input                                               */
24932   #define GPIO_DIRCLR_PIN20_Output (0x1UL)           /*!< Read: pin set as output                                              */
24933   #define GPIO_DIRCLR_PIN20_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24934 
24935 /* PIN21 @Bit 21 : Set as input pin 21 */
24936   #define GPIO_DIRCLR_PIN21_Pos (21UL)               /*!< Position of PIN21 field.                                             */
24937   #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field.                                 */
24938   #define GPIO_DIRCLR_PIN21_Min (0x0UL)              /*!< Min enumerator value of PIN21 field.                                 */
24939   #define GPIO_DIRCLR_PIN21_Max (0x1UL)              /*!< Max enumerator value of PIN21 field.                                 */
24940   #define GPIO_DIRCLR_PIN21_Input (0x0UL)            /*!< Read: pin set as input                                               */
24941   #define GPIO_DIRCLR_PIN21_Output (0x1UL)           /*!< Read: pin set as output                                              */
24942   #define GPIO_DIRCLR_PIN21_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24943 
24944 /* PIN22 @Bit 22 : Set as input pin 22 */
24945   #define GPIO_DIRCLR_PIN22_Pos (22UL)               /*!< Position of PIN22 field.                                             */
24946   #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field.                                 */
24947   #define GPIO_DIRCLR_PIN22_Min (0x0UL)              /*!< Min enumerator value of PIN22 field.                                 */
24948   #define GPIO_DIRCLR_PIN22_Max (0x1UL)              /*!< Max enumerator value of PIN22 field.                                 */
24949   #define GPIO_DIRCLR_PIN22_Input (0x0UL)            /*!< Read: pin set as input                                               */
24950   #define GPIO_DIRCLR_PIN22_Output (0x1UL)           /*!< Read: pin set as output                                              */
24951   #define GPIO_DIRCLR_PIN22_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24952 
24953 /* PIN23 @Bit 23 : Set as input pin 23 */
24954   #define GPIO_DIRCLR_PIN23_Pos (23UL)               /*!< Position of PIN23 field.                                             */
24955   #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field.                                 */
24956   #define GPIO_DIRCLR_PIN23_Min (0x0UL)              /*!< Min enumerator value of PIN23 field.                                 */
24957   #define GPIO_DIRCLR_PIN23_Max (0x1UL)              /*!< Max enumerator value of PIN23 field.                                 */
24958   #define GPIO_DIRCLR_PIN23_Input (0x0UL)            /*!< Read: pin set as input                                               */
24959   #define GPIO_DIRCLR_PIN23_Output (0x1UL)           /*!< Read: pin set as output                                              */
24960   #define GPIO_DIRCLR_PIN23_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24961 
24962 /* PIN24 @Bit 24 : Set as input pin 24 */
24963   #define GPIO_DIRCLR_PIN24_Pos (24UL)               /*!< Position of PIN24 field.                                             */
24964   #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field.                                 */
24965   #define GPIO_DIRCLR_PIN24_Min (0x0UL)              /*!< Min enumerator value of PIN24 field.                                 */
24966   #define GPIO_DIRCLR_PIN24_Max (0x1UL)              /*!< Max enumerator value of PIN24 field.                                 */
24967   #define GPIO_DIRCLR_PIN24_Input (0x0UL)            /*!< Read: pin set as input                                               */
24968   #define GPIO_DIRCLR_PIN24_Output (0x1UL)           /*!< Read: pin set as output                                              */
24969   #define GPIO_DIRCLR_PIN24_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24970 
24971 /* PIN25 @Bit 25 : Set as input pin 25 */
24972   #define GPIO_DIRCLR_PIN25_Pos (25UL)               /*!< Position of PIN25 field.                                             */
24973   #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field.                                 */
24974   #define GPIO_DIRCLR_PIN25_Min (0x0UL)              /*!< Min enumerator value of PIN25 field.                                 */
24975   #define GPIO_DIRCLR_PIN25_Max (0x1UL)              /*!< Max enumerator value of PIN25 field.                                 */
24976   #define GPIO_DIRCLR_PIN25_Input (0x0UL)            /*!< Read: pin set as input                                               */
24977   #define GPIO_DIRCLR_PIN25_Output (0x1UL)           /*!< Read: pin set as output                                              */
24978   #define GPIO_DIRCLR_PIN25_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24979 
24980 /* PIN26 @Bit 26 : Set as input pin 26 */
24981   #define GPIO_DIRCLR_PIN26_Pos (26UL)               /*!< Position of PIN26 field.                                             */
24982   #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field.                                 */
24983   #define GPIO_DIRCLR_PIN26_Min (0x0UL)              /*!< Min enumerator value of PIN26 field.                                 */
24984   #define GPIO_DIRCLR_PIN26_Max (0x1UL)              /*!< Max enumerator value of PIN26 field.                                 */
24985   #define GPIO_DIRCLR_PIN26_Input (0x0UL)            /*!< Read: pin set as input                                               */
24986   #define GPIO_DIRCLR_PIN26_Output (0x1UL)           /*!< Read: pin set as output                                              */
24987   #define GPIO_DIRCLR_PIN26_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24988 
24989 /* PIN27 @Bit 27 : Set as input pin 27 */
24990   #define GPIO_DIRCLR_PIN27_Pos (27UL)               /*!< Position of PIN27 field.                                             */
24991   #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field.                                 */
24992   #define GPIO_DIRCLR_PIN27_Min (0x0UL)              /*!< Min enumerator value of PIN27 field.                                 */
24993   #define GPIO_DIRCLR_PIN27_Max (0x1UL)              /*!< Max enumerator value of PIN27 field.                                 */
24994   #define GPIO_DIRCLR_PIN27_Input (0x0UL)            /*!< Read: pin set as input                                               */
24995   #define GPIO_DIRCLR_PIN27_Output (0x1UL)           /*!< Read: pin set as output                                              */
24996   #define GPIO_DIRCLR_PIN27_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
24997 
24998 /* PIN28 @Bit 28 : Set as input pin 28 */
24999   #define GPIO_DIRCLR_PIN28_Pos (28UL)               /*!< Position of PIN28 field.                                             */
25000   #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field.                                 */
25001   #define GPIO_DIRCLR_PIN28_Min (0x0UL)              /*!< Min enumerator value of PIN28 field.                                 */
25002   #define GPIO_DIRCLR_PIN28_Max (0x1UL)              /*!< Max enumerator value of PIN28 field.                                 */
25003   #define GPIO_DIRCLR_PIN28_Input (0x0UL)            /*!< Read: pin set as input                                               */
25004   #define GPIO_DIRCLR_PIN28_Output (0x1UL)           /*!< Read: pin set as output                                              */
25005   #define GPIO_DIRCLR_PIN28_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
25006 
25007 /* PIN29 @Bit 29 : Set as input pin 29 */
25008   #define GPIO_DIRCLR_PIN29_Pos (29UL)               /*!< Position of PIN29 field.                                             */
25009   #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field.                                 */
25010   #define GPIO_DIRCLR_PIN29_Min (0x0UL)              /*!< Min enumerator value of PIN29 field.                                 */
25011   #define GPIO_DIRCLR_PIN29_Max (0x1UL)              /*!< Max enumerator value of PIN29 field.                                 */
25012   #define GPIO_DIRCLR_PIN29_Input (0x0UL)            /*!< Read: pin set as input                                               */
25013   #define GPIO_DIRCLR_PIN29_Output (0x1UL)           /*!< Read: pin set as output                                              */
25014   #define GPIO_DIRCLR_PIN29_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
25015 
25016 /* PIN30 @Bit 30 : Set as input pin 30 */
25017   #define GPIO_DIRCLR_PIN30_Pos (30UL)               /*!< Position of PIN30 field.                                             */
25018   #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field.                                 */
25019   #define GPIO_DIRCLR_PIN30_Min (0x0UL)              /*!< Min enumerator value of PIN30 field.                                 */
25020   #define GPIO_DIRCLR_PIN30_Max (0x1UL)              /*!< Max enumerator value of PIN30 field.                                 */
25021   #define GPIO_DIRCLR_PIN30_Input (0x0UL)            /*!< Read: pin set as input                                               */
25022   #define GPIO_DIRCLR_PIN30_Output (0x1UL)           /*!< Read: pin set as output                                              */
25023   #define GPIO_DIRCLR_PIN30_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
25024 
25025 /* PIN31 @Bit 31 : Set as input pin 31 */
25026   #define GPIO_DIRCLR_PIN31_Pos (31UL)               /*!< Position of PIN31 field.                                             */
25027   #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field.                                 */
25028   #define GPIO_DIRCLR_PIN31_Min (0x0UL)              /*!< Min enumerator value of PIN31 field.                                 */
25029   #define GPIO_DIRCLR_PIN31_Max (0x1UL)              /*!< Max enumerator value of PIN31 field.                                 */
25030   #define GPIO_DIRCLR_PIN31_Input (0x0UL)            /*!< Read: pin set as input                                               */
25031   #define GPIO_DIRCLR_PIN31_Output (0x1UL)           /*!< Read: pin set as output                                              */
25032   #define GPIO_DIRCLR_PIN31_Clear (0x1UL)            /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect  */
25033 
25034 
25035 /* GPIO_LATCH: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
25036   #define GPIO_LATCH_ResetValue (0x00000000UL)       /*!< Reset value of LATCH register.                                       */
25037 
25038 /* PIN0 @Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */
25039   #define GPIO_LATCH_PIN0_Pos (0UL)                  /*!< Position of PIN0 field.                                              */
25040   #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field.                                      */
25041   #define GPIO_LATCH_PIN0_Min (0x0UL)                /*!< Min enumerator value of PIN0 field.                                  */
25042   #define GPIO_LATCH_PIN0_Max (0x1UL)                /*!< Max enumerator value of PIN0 field.                                  */
25043   #define GPIO_LATCH_PIN0_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25044   #define GPIO_LATCH_PIN0_Latched (0x1UL)            /*!< Criteria has been met                                                */
25045 
25046 /* PIN1 @Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */
25047   #define GPIO_LATCH_PIN1_Pos (1UL)                  /*!< Position of PIN1 field.                                              */
25048   #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field.                                      */
25049   #define GPIO_LATCH_PIN1_Min (0x0UL)                /*!< Min enumerator value of PIN1 field.                                  */
25050   #define GPIO_LATCH_PIN1_Max (0x1UL)                /*!< Max enumerator value of PIN1 field.                                  */
25051   #define GPIO_LATCH_PIN1_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25052   #define GPIO_LATCH_PIN1_Latched (0x1UL)            /*!< Criteria has been met                                                */
25053 
25054 /* PIN2 @Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */
25055   #define GPIO_LATCH_PIN2_Pos (2UL)                  /*!< Position of PIN2 field.                                              */
25056   #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field.                                      */
25057   #define GPIO_LATCH_PIN2_Min (0x0UL)                /*!< Min enumerator value of PIN2 field.                                  */
25058   #define GPIO_LATCH_PIN2_Max (0x1UL)                /*!< Max enumerator value of PIN2 field.                                  */
25059   #define GPIO_LATCH_PIN2_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25060   #define GPIO_LATCH_PIN2_Latched (0x1UL)            /*!< Criteria has been met                                                */
25061 
25062 /* PIN3 @Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */
25063   #define GPIO_LATCH_PIN3_Pos (3UL)                  /*!< Position of PIN3 field.                                              */
25064   #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field.                                      */
25065   #define GPIO_LATCH_PIN3_Min (0x0UL)                /*!< Min enumerator value of PIN3 field.                                  */
25066   #define GPIO_LATCH_PIN3_Max (0x1UL)                /*!< Max enumerator value of PIN3 field.                                  */
25067   #define GPIO_LATCH_PIN3_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25068   #define GPIO_LATCH_PIN3_Latched (0x1UL)            /*!< Criteria has been met                                                */
25069 
25070 /* PIN4 @Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */
25071   #define GPIO_LATCH_PIN4_Pos (4UL)                  /*!< Position of PIN4 field.                                              */
25072   #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field.                                      */
25073   #define GPIO_LATCH_PIN4_Min (0x0UL)                /*!< Min enumerator value of PIN4 field.                                  */
25074   #define GPIO_LATCH_PIN4_Max (0x1UL)                /*!< Max enumerator value of PIN4 field.                                  */
25075   #define GPIO_LATCH_PIN4_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25076   #define GPIO_LATCH_PIN4_Latched (0x1UL)            /*!< Criteria has been met                                                */
25077 
25078 /* PIN5 @Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */
25079   #define GPIO_LATCH_PIN5_Pos (5UL)                  /*!< Position of PIN5 field.                                              */
25080   #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field.                                      */
25081   #define GPIO_LATCH_PIN5_Min (0x0UL)                /*!< Min enumerator value of PIN5 field.                                  */
25082   #define GPIO_LATCH_PIN5_Max (0x1UL)                /*!< Max enumerator value of PIN5 field.                                  */
25083   #define GPIO_LATCH_PIN5_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25084   #define GPIO_LATCH_PIN5_Latched (0x1UL)            /*!< Criteria has been met                                                */
25085 
25086 /* PIN6 @Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */
25087   #define GPIO_LATCH_PIN6_Pos (6UL)                  /*!< Position of PIN6 field.                                              */
25088   #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field.                                      */
25089   #define GPIO_LATCH_PIN6_Min (0x0UL)                /*!< Min enumerator value of PIN6 field.                                  */
25090   #define GPIO_LATCH_PIN6_Max (0x1UL)                /*!< Max enumerator value of PIN6 field.                                  */
25091   #define GPIO_LATCH_PIN6_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25092   #define GPIO_LATCH_PIN6_Latched (0x1UL)            /*!< Criteria has been met                                                */
25093 
25094 /* PIN7 @Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */
25095   #define GPIO_LATCH_PIN7_Pos (7UL)                  /*!< Position of PIN7 field.                                              */
25096   #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field.                                      */
25097   #define GPIO_LATCH_PIN7_Min (0x0UL)                /*!< Min enumerator value of PIN7 field.                                  */
25098   #define GPIO_LATCH_PIN7_Max (0x1UL)                /*!< Max enumerator value of PIN7 field.                                  */
25099   #define GPIO_LATCH_PIN7_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25100   #define GPIO_LATCH_PIN7_Latched (0x1UL)            /*!< Criteria has been met                                                */
25101 
25102 /* PIN8 @Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */
25103   #define GPIO_LATCH_PIN8_Pos (8UL)                  /*!< Position of PIN8 field.                                              */
25104   #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field.                                      */
25105   #define GPIO_LATCH_PIN8_Min (0x0UL)                /*!< Min enumerator value of PIN8 field.                                  */
25106   #define GPIO_LATCH_PIN8_Max (0x1UL)                /*!< Max enumerator value of PIN8 field.                                  */
25107   #define GPIO_LATCH_PIN8_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25108   #define GPIO_LATCH_PIN8_Latched (0x1UL)            /*!< Criteria has been met                                                */
25109 
25110 /* PIN9 @Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */
25111   #define GPIO_LATCH_PIN9_Pos (9UL)                  /*!< Position of PIN9 field.                                              */
25112   #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field.                                      */
25113   #define GPIO_LATCH_PIN9_Min (0x0UL)                /*!< Min enumerator value of PIN9 field.                                  */
25114   #define GPIO_LATCH_PIN9_Max (0x1UL)                /*!< Max enumerator value of PIN9 field.                                  */
25115   #define GPIO_LATCH_PIN9_NotLatched (0x0UL)         /*!< Criteria has not been met                                            */
25116   #define GPIO_LATCH_PIN9_Latched (0x1UL)            /*!< Criteria has been met                                                */
25117 
25118 /* PIN10 @Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */
25119   #define GPIO_LATCH_PIN10_Pos (10UL)                /*!< Position of PIN10 field.                                             */
25120   #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field.                                   */
25121   #define GPIO_LATCH_PIN10_Min (0x0UL)               /*!< Min enumerator value of PIN10 field.                                 */
25122   #define GPIO_LATCH_PIN10_Max (0x1UL)               /*!< Max enumerator value of PIN10 field.                                 */
25123   #define GPIO_LATCH_PIN10_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25124   #define GPIO_LATCH_PIN10_Latched (0x1UL)           /*!< Criteria has been met                                                */
25125 
25126 /* PIN11 @Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */
25127   #define GPIO_LATCH_PIN11_Pos (11UL)                /*!< Position of PIN11 field.                                             */
25128   #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field.                                   */
25129   #define GPIO_LATCH_PIN11_Min (0x0UL)               /*!< Min enumerator value of PIN11 field.                                 */
25130   #define GPIO_LATCH_PIN11_Max (0x1UL)               /*!< Max enumerator value of PIN11 field.                                 */
25131   #define GPIO_LATCH_PIN11_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25132   #define GPIO_LATCH_PIN11_Latched (0x1UL)           /*!< Criteria has been met                                                */
25133 
25134 /* PIN12 @Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */
25135   #define GPIO_LATCH_PIN12_Pos (12UL)                /*!< Position of PIN12 field.                                             */
25136   #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field.                                   */
25137   #define GPIO_LATCH_PIN12_Min (0x0UL)               /*!< Min enumerator value of PIN12 field.                                 */
25138   #define GPIO_LATCH_PIN12_Max (0x1UL)               /*!< Max enumerator value of PIN12 field.                                 */
25139   #define GPIO_LATCH_PIN12_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25140   #define GPIO_LATCH_PIN12_Latched (0x1UL)           /*!< Criteria has been met                                                */
25141 
25142 /* PIN13 @Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */
25143   #define GPIO_LATCH_PIN13_Pos (13UL)                /*!< Position of PIN13 field.                                             */
25144   #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field.                                   */
25145   #define GPIO_LATCH_PIN13_Min (0x0UL)               /*!< Min enumerator value of PIN13 field.                                 */
25146   #define GPIO_LATCH_PIN13_Max (0x1UL)               /*!< Max enumerator value of PIN13 field.                                 */
25147   #define GPIO_LATCH_PIN13_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25148   #define GPIO_LATCH_PIN13_Latched (0x1UL)           /*!< Criteria has been met                                                */
25149 
25150 /* PIN14 @Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */
25151   #define GPIO_LATCH_PIN14_Pos (14UL)                /*!< Position of PIN14 field.                                             */
25152   #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field.                                   */
25153   #define GPIO_LATCH_PIN14_Min (0x0UL)               /*!< Min enumerator value of PIN14 field.                                 */
25154   #define GPIO_LATCH_PIN14_Max (0x1UL)               /*!< Max enumerator value of PIN14 field.                                 */
25155   #define GPIO_LATCH_PIN14_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25156   #define GPIO_LATCH_PIN14_Latched (0x1UL)           /*!< Criteria has been met                                                */
25157 
25158 /* PIN15 @Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */
25159   #define GPIO_LATCH_PIN15_Pos (15UL)                /*!< Position of PIN15 field.                                             */
25160   #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field.                                   */
25161   #define GPIO_LATCH_PIN15_Min (0x0UL)               /*!< Min enumerator value of PIN15 field.                                 */
25162   #define GPIO_LATCH_PIN15_Max (0x1UL)               /*!< Max enumerator value of PIN15 field.                                 */
25163   #define GPIO_LATCH_PIN15_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25164   #define GPIO_LATCH_PIN15_Latched (0x1UL)           /*!< Criteria has been met                                                */
25165 
25166 /* PIN16 @Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */
25167   #define GPIO_LATCH_PIN16_Pos (16UL)                /*!< Position of PIN16 field.                                             */
25168   #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field.                                   */
25169   #define GPIO_LATCH_PIN16_Min (0x0UL)               /*!< Min enumerator value of PIN16 field.                                 */
25170   #define GPIO_LATCH_PIN16_Max (0x1UL)               /*!< Max enumerator value of PIN16 field.                                 */
25171   #define GPIO_LATCH_PIN16_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25172   #define GPIO_LATCH_PIN16_Latched (0x1UL)           /*!< Criteria has been met                                                */
25173 
25174 /* PIN17 @Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */
25175   #define GPIO_LATCH_PIN17_Pos (17UL)                /*!< Position of PIN17 field.                                             */
25176   #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field.                                   */
25177   #define GPIO_LATCH_PIN17_Min (0x0UL)               /*!< Min enumerator value of PIN17 field.                                 */
25178   #define GPIO_LATCH_PIN17_Max (0x1UL)               /*!< Max enumerator value of PIN17 field.                                 */
25179   #define GPIO_LATCH_PIN17_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25180   #define GPIO_LATCH_PIN17_Latched (0x1UL)           /*!< Criteria has been met                                                */
25181 
25182 /* PIN18 @Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */
25183   #define GPIO_LATCH_PIN18_Pos (18UL)                /*!< Position of PIN18 field.                                             */
25184   #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field.                                   */
25185   #define GPIO_LATCH_PIN18_Min (0x0UL)               /*!< Min enumerator value of PIN18 field.                                 */
25186   #define GPIO_LATCH_PIN18_Max (0x1UL)               /*!< Max enumerator value of PIN18 field.                                 */
25187   #define GPIO_LATCH_PIN18_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25188   #define GPIO_LATCH_PIN18_Latched (0x1UL)           /*!< Criteria has been met                                                */
25189 
25190 /* PIN19 @Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */
25191   #define GPIO_LATCH_PIN19_Pos (19UL)                /*!< Position of PIN19 field.                                             */
25192   #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field.                                   */
25193   #define GPIO_LATCH_PIN19_Min (0x0UL)               /*!< Min enumerator value of PIN19 field.                                 */
25194   #define GPIO_LATCH_PIN19_Max (0x1UL)               /*!< Max enumerator value of PIN19 field.                                 */
25195   #define GPIO_LATCH_PIN19_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25196   #define GPIO_LATCH_PIN19_Latched (0x1UL)           /*!< Criteria has been met                                                */
25197 
25198 /* PIN20 @Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */
25199   #define GPIO_LATCH_PIN20_Pos (20UL)                /*!< Position of PIN20 field.                                             */
25200   #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field.                                   */
25201   #define GPIO_LATCH_PIN20_Min (0x0UL)               /*!< Min enumerator value of PIN20 field.                                 */
25202   #define GPIO_LATCH_PIN20_Max (0x1UL)               /*!< Max enumerator value of PIN20 field.                                 */
25203   #define GPIO_LATCH_PIN20_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25204   #define GPIO_LATCH_PIN20_Latched (0x1UL)           /*!< Criteria has been met                                                */
25205 
25206 /* PIN21 @Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */
25207   #define GPIO_LATCH_PIN21_Pos (21UL)                /*!< Position of PIN21 field.                                             */
25208   #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field.                                   */
25209   #define GPIO_LATCH_PIN21_Min (0x0UL)               /*!< Min enumerator value of PIN21 field.                                 */
25210   #define GPIO_LATCH_PIN21_Max (0x1UL)               /*!< Max enumerator value of PIN21 field.                                 */
25211   #define GPIO_LATCH_PIN21_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25212   #define GPIO_LATCH_PIN21_Latched (0x1UL)           /*!< Criteria has been met                                                */
25213 
25214 /* PIN22 @Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */
25215   #define GPIO_LATCH_PIN22_Pos (22UL)                /*!< Position of PIN22 field.                                             */
25216   #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field.                                   */
25217   #define GPIO_LATCH_PIN22_Min (0x0UL)               /*!< Min enumerator value of PIN22 field.                                 */
25218   #define GPIO_LATCH_PIN22_Max (0x1UL)               /*!< Max enumerator value of PIN22 field.                                 */
25219   #define GPIO_LATCH_PIN22_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25220   #define GPIO_LATCH_PIN22_Latched (0x1UL)           /*!< Criteria has been met                                                */
25221 
25222 /* PIN23 @Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */
25223   #define GPIO_LATCH_PIN23_Pos (23UL)                /*!< Position of PIN23 field.                                             */
25224   #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field.                                   */
25225   #define GPIO_LATCH_PIN23_Min (0x0UL)               /*!< Min enumerator value of PIN23 field.                                 */
25226   #define GPIO_LATCH_PIN23_Max (0x1UL)               /*!< Max enumerator value of PIN23 field.                                 */
25227   #define GPIO_LATCH_PIN23_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25228   #define GPIO_LATCH_PIN23_Latched (0x1UL)           /*!< Criteria has been met                                                */
25229 
25230 /* PIN24 @Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */
25231   #define GPIO_LATCH_PIN24_Pos (24UL)                /*!< Position of PIN24 field.                                             */
25232   #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field.                                   */
25233   #define GPIO_LATCH_PIN24_Min (0x0UL)               /*!< Min enumerator value of PIN24 field.                                 */
25234   #define GPIO_LATCH_PIN24_Max (0x1UL)               /*!< Max enumerator value of PIN24 field.                                 */
25235   #define GPIO_LATCH_PIN24_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25236   #define GPIO_LATCH_PIN24_Latched (0x1UL)           /*!< Criteria has been met                                                */
25237 
25238 /* PIN25 @Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */
25239   #define GPIO_LATCH_PIN25_Pos (25UL)                /*!< Position of PIN25 field.                                             */
25240   #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field.                                   */
25241   #define GPIO_LATCH_PIN25_Min (0x0UL)               /*!< Min enumerator value of PIN25 field.                                 */
25242   #define GPIO_LATCH_PIN25_Max (0x1UL)               /*!< Max enumerator value of PIN25 field.                                 */
25243   #define GPIO_LATCH_PIN25_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25244   #define GPIO_LATCH_PIN25_Latched (0x1UL)           /*!< Criteria has been met                                                */
25245 
25246 /* PIN26 @Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */
25247   #define GPIO_LATCH_PIN26_Pos (26UL)                /*!< Position of PIN26 field.                                             */
25248   #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field.                                   */
25249   #define GPIO_LATCH_PIN26_Min (0x0UL)               /*!< Min enumerator value of PIN26 field.                                 */
25250   #define GPIO_LATCH_PIN26_Max (0x1UL)               /*!< Max enumerator value of PIN26 field.                                 */
25251   #define GPIO_LATCH_PIN26_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25252   #define GPIO_LATCH_PIN26_Latched (0x1UL)           /*!< Criteria has been met                                                */
25253 
25254 /* PIN27 @Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */
25255   #define GPIO_LATCH_PIN27_Pos (27UL)                /*!< Position of PIN27 field.                                             */
25256   #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field.                                   */
25257   #define GPIO_LATCH_PIN27_Min (0x0UL)               /*!< Min enumerator value of PIN27 field.                                 */
25258   #define GPIO_LATCH_PIN27_Max (0x1UL)               /*!< Max enumerator value of PIN27 field.                                 */
25259   #define GPIO_LATCH_PIN27_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25260   #define GPIO_LATCH_PIN27_Latched (0x1UL)           /*!< Criteria has been met                                                */
25261 
25262 /* PIN28 @Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */
25263   #define GPIO_LATCH_PIN28_Pos (28UL)                /*!< Position of PIN28 field.                                             */
25264   #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field.                                   */
25265   #define GPIO_LATCH_PIN28_Min (0x0UL)               /*!< Min enumerator value of PIN28 field.                                 */
25266   #define GPIO_LATCH_PIN28_Max (0x1UL)               /*!< Max enumerator value of PIN28 field.                                 */
25267   #define GPIO_LATCH_PIN28_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25268   #define GPIO_LATCH_PIN28_Latched (0x1UL)           /*!< Criteria has been met                                                */
25269 
25270 /* PIN29 @Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */
25271   #define GPIO_LATCH_PIN29_Pos (29UL)                /*!< Position of PIN29 field.                                             */
25272   #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field.                                   */
25273   #define GPIO_LATCH_PIN29_Min (0x0UL)               /*!< Min enumerator value of PIN29 field.                                 */
25274   #define GPIO_LATCH_PIN29_Max (0x1UL)               /*!< Max enumerator value of PIN29 field.                                 */
25275   #define GPIO_LATCH_PIN29_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25276   #define GPIO_LATCH_PIN29_Latched (0x1UL)           /*!< Criteria has been met                                                */
25277 
25278 /* PIN30 @Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */
25279   #define GPIO_LATCH_PIN30_Pos (30UL)                /*!< Position of PIN30 field.                                             */
25280   #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field.                                   */
25281   #define GPIO_LATCH_PIN30_Min (0x0UL)               /*!< Min enumerator value of PIN30 field.                                 */
25282   #define GPIO_LATCH_PIN30_Max (0x1UL)               /*!< Max enumerator value of PIN30 field.                                 */
25283   #define GPIO_LATCH_PIN30_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25284   #define GPIO_LATCH_PIN30_Latched (0x1UL)           /*!< Criteria has been met                                                */
25285 
25286 /* PIN31 @Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */
25287   #define GPIO_LATCH_PIN31_Pos (31UL)                /*!< Position of PIN31 field.                                             */
25288   #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field.                                   */
25289   #define GPIO_LATCH_PIN31_Min (0x0UL)               /*!< Min enumerator value of PIN31 field.                                 */
25290   #define GPIO_LATCH_PIN31_Max (0x1UL)               /*!< Max enumerator value of PIN31 field.                                 */
25291   #define GPIO_LATCH_PIN31_NotLatched (0x0UL)        /*!< Criteria has not been met                                            */
25292   #define GPIO_LATCH_PIN31_Latched (0x1UL)           /*!< Criteria has been met                                                */
25293 
25294 
25295 /* GPIO_DETECTMODE: Select between default DETECT signal behavior and LDETECT mode */
25296   #define GPIO_DETECTMODE_ResetValue (0x00000000UL)  /*!< Reset value of DETECTMODE register.                                  */
25297 
25298 /* DETECTMODE @Bit 0 : Select between default DETECT signal behavior and LDETECT mode */
25299   #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL)       /*!< Position of DETECTMODE field.                                        */
25300   #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field.          */
25301   #define GPIO_DETECTMODE_DETECTMODE_Min (0x0UL)     /*!< Min enumerator value of DETECTMODE field.                            */
25302   #define GPIO_DETECTMODE_DETECTMODE_Max (0x1UL)     /*!< Max enumerator value of DETECTMODE field.                            */
25303   #define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals                      */
25304   #define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior                                     */
25305 
25306 
25307 /* GPIO_RETAIN: Enable retention for those GPIO registers marked as retained */
25308   #define GPIO_RETAIN_ResetValue (0x0000000CUL)      /*!< Reset value of RETAIN register.                                      */
25309 
25310 /* APPLICAION @Bit 2 : Enable retention for GPIO registers for Application domain */
25311   #define GPIO_RETAIN_APPLICAION_Pos (2UL)           /*!< Position of APPLICAION field.                                        */
25312   #define GPIO_RETAIN_APPLICAION_Msk (0x1UL << GPIO_RETAIN_APPLICAION_Pos) /*!< Bit mask of APPLICAION field.                  */
25313   #define GPIO_RETAIN_APPLICAION_Min (0x0UL)         /*!< Min enumerator value of APPLICAION field.                            */
25314   #define GPIO_RETAIN_APPLICAION_Max (0x1UL)         /*!< Max enumerator value of APPLICAION field.                            */
25315   #define GPIO_RETAIN_APPLICAION_Disabled (0x0UL)    /*!< Retention disabled                                                   */
25316   #define GPIO_RETAIN_APPLICAION_Enabled (0x1UL)     /*!< Retention enabled                                                    */
25317 
25318 /* RADIOCORE @Bit 3 : Enable retention for GPIO registers for Radio core */
25319   #define GPIO_RETAIN_RADIOCORE_Pos (3UL)            /*!< Position of RADIOCORE field.                                         */
25320   #define GPIO_RETAIN_RADIOCORE_Msk (0x1UL << GPIO_RETAIN_RADIOCORE_Pos) /*!< Bit mask of RADIOCORE field.                     */
25321   #define GPIO_RETAIN_RADIOCORE_Min (0x0UL)          /*!< Min enumerator value of RADIOCORE field.                             */
25322   #define GPIO_RETAIN_RADIOCORE_Max (0x1UL)          /*!< Max enumerator value of RADIOCORE field.                             */
25323   #define GPIO_RETAIN_RADIOCORE_Disabled (0x0UL)     /*!< Retention disabled                                                   */
25324   #define GPIO_RETAIN_RADIOCORE_Enabled (0x1UL)      /*!< Retention enabled                                                    */
25325 
25326 
25327 /* GPIO_PIN_CNF: Pin n configuration of GPIO pin */
25328   #define GPIO_PIN_CNF_MaxCount (32UL)               /*!< Max size of PIN_CNF[32] array.                                       */
25329   #define GPIO_PIN_CNF_MaxIndex (31UL)               /*!< Max index of PIN_CNF[32] array.                                      */
25330   #define GPIO_PIN_CNF_MinIndex (0UL)                /*!< Min index of PIN_CNF[32] array.                                      */
25331   #define GPIO_PIN_CNF_ResetValue (0x00000002UL)     /*!< Reset value of PIN_CNF[32] register.                                 */
25332 
25333 /* DIR @Bit 0 : Pin direction. Same physical register as DIR register */
25334   #define GPIO_PIN_CNF_DIR_Pos (0UL)                 /*!< Position of DIR field.                                               */
25335   #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field.                                     */
25336   #define GPIO_PIN_CNF_DIR_Min (0x0UL)               /*!< Min enumerator value of DIR field.                                   */
25337   #define GPIO_PIN_CNF_DIR_Max (0x1UL)               /*!< Max enumerator value of DIR field.                                   */
25338   #define GPIO_PIN_CNF_DIR_Input (0x0UL)             /*!< Configure pin as an input pin                                        */
25339   #define GPIO_PIN_CNF_DIR_Output (0x1UL)            /*!< Configure pin as an output pin                                       */
25340 
25341 /* INPUT @Bit 1 : Connect or disconnect input buffer */
25342   #define GPIO_PIN_CNF_INPUT_Pos (1UL)               /*!< Position of INPUT field.                                             */
25343   #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field.                               */
25344   #define GPIO_PIN_CNF_INPUT_Min (0x0UL)             /*!< Min enumerator value of INPUT field.                                 */
25345   #define GPIO_PIN_CNF_INPUT_Max (0x1UL)             /*!< Max enumerator value of INPUT field.                                 */
25346   #define GPIO_PIN_CNF_INPUT_Connect (0x0UL)         /*!< Connect input buffer                                                 */
25347   #define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL)      /*!< Disconnect input buffer                                              */
25348 
25349 /* PULL @Bits 2..3 : Pull configuration */
25350   #define GPIO_PIN_CNF_PULL_Pos (2UL)                /*!< Position of PULL field.                                              */
25351   #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field.                                  */
25352   #define GPIO_PIN_CNF_PULL_Min (0x0UL)              /*!< Min enumerator value of PULL field.                                  */
25353   #define GPIO_PIN_CNF_PULL_Max (0x3UL)              /*!< Max enumerator value of PULL field.                                  */
25354   #define GPIO_PIN_CNF_PULL_Disabled (0x0UL)         /*!< No pull                                                              */
25355   #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL)         /*!< Pull down on pin                                                     */
25356   #define GPIO_PIN_CNF_PULL_Pullup (0x3UL)           /*!< Pull up on pin                                                       */
25357 
25358 /* DRIVE0 @Bits 8..9 : Drive configuration for '0' */
25359   #define GPIO_PIN_CNF_DRIVE0_Pos (8UL)              /*!< Position of DRIVE0 field.                                            */
25360   #define GPIO_PIN_CNF_DRIVE0_Msk (0x3UL << GPIO_PIN_CNF_DRIVE0_Pos) /*!< Bit mask of DRIVE0 field.                            */
25361   #define GPIO_PIN_CNF_DRIVE0_Min (0x0UL)            /*!< Min enumerator value of DRIVE0 field.                                */
25362   #define GPIO_PIN_CNF_DRIVE0_Max (0x3UL)            /*!< Max enumerator value of DRIVE0 field.                                */
25363   #define GPIO_PIN_CNF_DRIVE0_S0 (0x0UL)             /*!< Standard '0'                                                         */
25364   #define GPIO_PIN_CNF_DRIVE0_H0 (0x1UL)             /*!< High drive '0'                                                       */
25365   #define GPIO_PIN_CNF_DRIVE0_D0 (0x2UL)             /*!< Disconnect '0'(normally used for wired-or connections)               */
25366   #define GPIO_PIN_CNF_DRIVE0_E0 (0x3UL)             /*!< Extra high drive '0'                                                 */
25367 
25368 /* DRIVE1 @Bits 10..11 : Drive configuration for '1' */
25369   #define GPIO_PIN_CNF_DRIVE1_Pos (10UL)             /*!< Position of DRIVE1 field.                                            */
25370   #define GPIO_PIN_CNF_DRIVE1_Msk (0x3UL << GPIO_PIN_CNF_DRIVE1_Pos) /*!< Bit mask of DRIVE1 field.                            */
25371   #define GPIO_PIN_CNF_DRIVE1_Min (0x0UL)            /*!< Min enumerator value of DRIVE1 field.                                */
25372   #define GPIO_PIN_CNF_DRIVE1_Max (0x3UL)            /*!< Max enumerator value of DRIVE1 field.                                */
25373   #define GPIO_PIN_CNF_DRIVE1_S1 (0x0UL)             /*!< Standard '1'                                                         */
25374   #define GPIO_PIN_CNF_DRIVE1_H1 (0x1UL)             /*!< High drive '1'                                                       */
25375   #define GPIO_PIN_CNF_DRIVE1_D1 (0x2UL)             /*!< Disconnect '1'(normally used for wired-or connections)               */
25376   #define GPIO_PIN_CNF_DRIVE1_E1 (0x3UL)             /*!< Extra high drive '1'                                                 */
25377 
25378 /* SENSE @Bits 16..17 : Pin sensing mechanism */
25379   #define GPIO_PIN_CNF_SENSE_Pos (16UL)              /*!< Position of SENSE field.                                             */
25380   #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field.                               */
25381   #define GPIO_PIN_CNF_SENSE_Min (0x0UL)             /*!< Min enumerator value of SENSE field.                                 */
25382   #define GPIO_PIN_CNF_SENSE_Max (0x3UL)             /*!< Max enumerator value of SENSE field.                                 */
25383   #define GPIO_PIN_CNF_SENSE_Disabled (0x0UL)        /*!< Disabled                                                             */
25384   #define GPIO_PIN_CNF_SENSE_High (0x2UL)            /*!< Sense for high level                                                 */
25385   #define GPIO_PIN_CNF_SENSE_Low (0x3UL)             /*!< Sense for low level                                                  */
25386 
25387 /* CLOCKPIN @Bit 31 : Enable clock on the pin. */
25388   #define GPIO_PIN_CNF_CLOCKPIN_Pos (31UL)           /*!< Position of CLOCKPIN field.                                          */
25389   #define GPIO_PIN_CNF_CLOCKPIN_Msk (0x1UL << GPIO_PIN_CNF_CLOCKPIN_Pos) /*!< Bit mask of CLOCKPIN field.                      */
25390   #define GPIO_PIN_CNF_CLOCKPIN_Min (0x0UL)          /*!< Min enumerator value of CLOCKPIN field.                              */
25391   #define GPIO_PIN_CNF_CLOCKPIN_Max (0x1UL)          /*!< Max enumerator value of CLOCKPIN field.                              */
25392   #define GPIO_PIN_CNF_CLOCKPIN_Disabled (0x0UL)     /*!< Clock disabled                                                       */
25393   #define GPIO_PIN_CNF_CLOCKPIN_Enabled (0x1UL)      /*!< Clock enabled                                                        */
25394 
25395 
25396 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
25397 
25398 /* =========================================================================================================================== */
25399 /* ================                                          GPIOTE                                          ================ */
25400 /* =========================================================================================================================== */
25401 
25402 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
25403 
25404 /* ================================================ Struct GPIOTE_EVENTS_PORT ================================================ */
25405 /**
25406   * @brief EVENTS_PORT [GPIOTE_EVENTS_PORT] Peripheral events.
25407   */
25408 typedef struct {
25409   __IOM uint32_t  NONSECURE;                         /*!< (@ 0x00000000) Non-secure port event from owner n                    */
25410   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Secure port event from owner n                        */
25411 } NRF_GPIOTE_EVENTS_PORT_Type;                       /*!< Size = 8 (0x008)                                                     */
25412   #define GPIOTE_EVENTS_PORT_MaxCount (4UL)          /*!< Size of EVENTS_PORT[4] array.                                        */
25413   #define GPIOTE_EVENTS_PORT_MaxIndex (3UL)          /*!< Max index of EVENTS_PORT[4] array.                                   */
25414   #define GPIOTE_EVENTS_PORT_MinIndex (0UL)          /*!< Min index of EVENTS_PORT[4] array.                                   */
25415 
25416 /* GPIOTE_EVENTS_PORT_NONSECURE: Non-secure port event from owner n */
25417   #define GPIOTE_EVENTS_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register.                       */
25418 
25419 /* NONSECURE @Bit 0 : Non-secure port event from owner n */
25420   #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos (0UL) /*!< Position of NONSECURE field.                                   */
25421   #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Pos) /*!< Bit mask of
25422                                                                             NONSECURE field.*/
25423   #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Min (0x0UL) /*!< Min enumerator value of NONSECURE field.                     */
25424   #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Max (0x1UL) /*!< Max enumerator value of NONSECURE field.                     */
25425   #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_NotGenerated (0x0UL) /*!< Event not generated                                 */
25426   #define GPIOTE_EVENTS_PORT_NONSECURE_NONSECURE_Generated (0x1UL) /*!< Event generated                                        */
25427 
25428 
25429 /* GPIOTE_EVENTS_PORT_SECURE: Secure port event from owner n */
25430   #define GPIOTE_EVENTS_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register.                             */
25431 
25432 /* SECURE @Bit 0 : Secure port event from owner n */
25433   #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos (0UL) /*!< Position of SECURE field.                                            */
25434   #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Msk (0x1UL << GPIOTE_EVENTS_PORT_SECURE_SECURE_Pos) /*!< Bit mask of SECURE field.  */
25435   #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Min (0x0UL) /*!< Min enumerator value of SECURE field.                              */
25436   #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Max (0x1UL) /*!< Max enumerator value of SECURE field.                              */
25437   #define GPIOTE_EVENTS_PORT_SECURE_SECURE_NotGenerated (0x0UL) /*!< Event not generated                                       */
25438   #define GPIOTE_EVENTS_PORT_SECURE_SECURE_Generated (0x1UL) /*!< Event generated                                              */
25439 
25440 
25441 
25442 /* =============================================== Struct GPIOTE_PUBLISH_PORT ================================================ */
25443 /**
25444   * @brief PUBLISH_PORT [GPIOTE_PUBLISH_PORT] Publish configuration for events
25445   */
25446 typedef struct {
25447   __IOM uint32_t  NONSECURE;                         /*!< (@ 0x00000000) Publish configuration for event PORT[n].NONSECURE     */
25448   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Publish configuration for event PORT[n].SECURE        */
25449 } NRF_GPIOTE_PUBLISH_PORT_Type;                      /*!< Size = 8 (0x008)                                                     */
25450   #define GPIOTE_PUBLISH_PORT_MaxCount (4UL)         /*!< Size of PUBLISH_PORT[4] array.                                       */
25451   #define GPIOTE_PUBLISH_PORT_MaxIndex (3UL)         /*!< Max index of PUBLISH_PORT[4] array.                                  */
25452   #define GPIOTE_PUBLISH_PORT_MinIndex (0UL)         /*!< Min index of PUBLISH_PORT[4] array.                                  */
25453 
25454 /* GPIOTE_PUBLISH_PORT_NONSECURE: Publish configuration for event PORT[n].NONSECURE */
25455   #define GPIOTE_PUBLISH_PORT_NONSECURE_ResetValue (0x00000000UL) /*!< Reset value of NONSECURE register.                      */
25456 
25457 /* CHIDX @Bits 0..7 : DPPI channel that event PORT[n].NONSECURE will publish to */
25458   #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                          */
25459   #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Pos) /*!< Bit mask of CHIDX
25460                                                                             field.*/
25461   #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                       */
25462   #define GPIOTE_PUBLISH_PORT_NONSECURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                       */
25463 
25464 /* EN @Bit 31 : (unspecified) */
25465   #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Pos (31UL) /*!< Position of EN field.                                               */
25466   #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_NONSECURE_EN_Pos) /*!< Bit mask of EN field.      */
25467   #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                  */
25468   #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                  */
25469   #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Disabled (0x0UL) /*!< Disable publishing                                            */
25470   #define GPIOTE_PUBLISH_PORT_NONSECURE_EN_Enabled (0x1UL) /*!< Enable publishing                                              */
25471 
25472 
25473 /* GPIOTE_PUBLISH_PORT_SECURE: Publish configuration for event PORT[n].SECURE */
25474   #define GPIOTE_PUBLISH_PORT_SECURE_ResetValue (0x00000000UL) /*!< Reset value of SECURE register.                            */
25475 
25476 /* CHIDX @Bits 0..7 : DPPI channel that event PORT[n].SECURE will publish to */
25477   #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
25478   #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
25479   #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                          */
25480   #define GPIOTE_PUBLISH_PORT_SECURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */
25481 
25482 /* EN @Bit 31 : (unspecified) */
25483   #define GPIOTE_PUBLISH_PORT_SECURE_EN_Pos (31UL)   /*!< Position of EN field.                                                */
25484   #define GPIOTE_PUBLISH_PORT_SECURE_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_SECURE_EN_Pos) /*!< Bit mask of EN field.            */
25485   #define GPIOTE_PUBLISH_PORT_SECURE_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
25486   #define GPIOTE_PUBLISH_PORT_SECURE_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
25487   #define GPIOTE_PUBLISH_PORT_SECURE_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
25488   #define GPIOTE_PUBLISH_PORT_SECURE_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */
25489 
25490 
25491 /* ====================================================== Struct GPIOTE ====================================================== */
25492 /**
25493   * @brief GPIO Tasks and Events
25494   */
25495   typedef struct {                                   /*!< GPIOTE Structure                                                     */
25496     __OM uint32_t TASKS_OUT[8];                      /*!< (@ 0x00000000) Task for writing to pin specified in CONFIG[n].PSEL.
25497                                                                          Action on pin is configured in CONFIG[n].POLARITY.*/
25498     __IM uint32_t RESERVED[4];
25499     __OM uint32_t TASKS_SET[8];                      /*!< (@ 0x00000030) Task for writing to pin specified in CONFIG[n].PSEL.
25500                                                                          Action on pin is to set it high.*/
25501     __IM uint32_t RESERVED1[4];
25502     __OM uint32_t TASKS_CLR[8];                      /*!< (@ 0x00000060) Task for writing to pin specified in CONFIG[n].PSEL.
25503                                                                          Action on pin is to set it low.*/
25504     __IOM uint32_t SUBSCRIBE_OUT[8];                 /*!< (@ 0x00000080) Subscribe configuration for task OUT[n]               */
25505     __IM uint32_t RESERVED2[4];
25506     __IOM uint32_t SUBSCRIBE_SET[8];                 /*!< (@ 0x000000B0) Subscribe configuration for task SET[n]               */
25507     __IM uint32_t RESERVED3[4];
25508     __IOM uint32_t SUBSCRIBE_CLR[8];                 /*!< (@ 0x000000E0) Subscribe configuration for task CLR[n]               */
25509     __IOM uint32_t EVENTS_IN[8];                     /*!< (@ 0x00000100) Event from pin specified in CONFIG[n].PSEL            */
25510     __IM uint32_t RESERVED4[8];
25511     __IOM NRF_GPIOTE_EVENTS_PORT_Type EVENTS_PORT[4]; /*!< (@ 0x00000140) Peripheral events.                                   */
25512     __IM uint32_t RESERVED5[8];
25513     __IOM uint32_t PUBLISH_IN[8];                    /*!< (@ 0x00000180) Publish configuration for event IN[n]                 */
25514     __IM uint32_t RESERVED6[8];
25515     __IOM NRF_GPIOTE_PUBLISH_PORT_Type PUBLISH_PORT[4]; /*!< (@ 0x000001C0) Publish configuration for events                   */
25516     __IM uint32_t RESERVED7[73];
25517     __IOM uint32_t INTENSET0;                        /*!< (@ 0x00000304) Enable interrupt                                      */
25518     __IOM uint32_t INTENCLR0;                        /*!< (@ 0x00000308) Disable interrupt                                     */
25519     __IM uint32_t RESERVED8[2];
25520     __IOM uint32_t INTENSET1;                        /*!< (@ 0x00000314) Enable interrupt                                      */
25521     __IOM uint32_t INTENCLR1;                        /*!< (@ 0x00000318) Disable interrupt                                     */
25522     __IM uint32_t RESERVED9[2];
25523     __IOM uint32_t INTENSET2;                        /*!< (@ 0x00000324) Enable interrupt                                      */
25524     __IOM uint32_t INTENCLR2;                        /*!< (@ 0x00000328) Disable interrupt                                     */
25525     __IM uint32_t RESERVED10[2];
25526     __IOM uint32_t INTENSET3;                        /*!< (@ 0x00000334) Enable interrupt                                      */
25527     __IOM uint32_t INTENCLR3;                        /*!< (@ 0x00000338) Disable interrupt                                     */
25528     __IM uint32_t RESERVED11[2];
25529     __IOM uint32_t INTENSET4;                        /*!< (@ 0x00000344) Enable interrupt                                      */
25530     __IOM uint32_t INTENCLR4;                        /*!< (@ 0x00000348) Disable interrupt                                     */
25531     __IM uint32_t RESERVED12[2];
25532     __IOM uint32_t INTENSET5;                        /*!< (@ 0x00000354) Enable interrupt                                      */
25533     __IOM uint32_t INTENCLR5;                        /*!< (@ 0x00000358) Disable interrupt                                     */
25534     __IM uint32_t RESERVED13[2];
25535     __IOM uint32_t INTENSET6;                        /*!< (@ 0x00000364) Enable interrupt                                      */
25536     __IOM uint32_t INTENCLR6;                        /*!< (@ 0x00000368) Disable interrupt                                     */
25537     __IM uint32_t RESERVED14[102];
25538     __IOM uint32_t LATENCY;                          /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event) with
25539                                                                          rising or falling edge detection on the pin.*/
25540     __IM uint32_t RESERVED15[2];
25541     __IOM uint32_t CONFIG[8];                        /*!< (@ 0x00000510) Configuration for OUT[n], SET[n], and CLR[n] tasks and
25542                                                                          IN[n] event*/
25543   } NRF_GPIOTE_Type;                                 /*!< Size = 1328 (0x530)                                                  */
25544 
25545 /* GPIOTE_TASKS_OUT: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
25546   #define GPIOTE_TASKS_OUT_MaxCount (8UL)            /*!< Max size of TASKS_OUT[8] array.                                      */
25547   #define GPIOTE_TASKS_OUT_MaxIndex (7UL)            /*!< Max index of TASKS_OUT[8] array.                                     */
25548   #define GPIOTE_TASKS_OUT_MinIndex (0UL)            /*!< Min index of TASKS_OUT[8] array.                                     */
25549   #define GPIOTE_TASKS_OUT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_OUT[8] register.                                */
25550 
25551 /* TASKS_OUT @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
25552   #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL)       /*!< Position of TASKS_OUT field.                                         */
25553   #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field.           */
25554   #define GPIOTE_TASKS_OUT_TASKS_OUT_Min (0x1UL)     /*!< Min enumerator value of TASKS_OUT field.                             */
25555   #define GPIOTE_TASKS_OUT_TASKS_OUT_Max (0x1UL)     /*!< Max enumerator value of TASKS_OUT field.                             */
25556   #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task                                                         */
25557 
25558 
25559 /* GPIOTE_TASKS_SET: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
25560   #define GPIOTE_TASKS_SET_MaxCount (8UL)            /*!< Max size of TASKS_SET[8] array.                                      */
25561   #define GPIOTE_TASKS_SET_MaxIndex (7UL)            /*!< Max index of TASKS_SET[8] array.                                     */
25562   #define GPIOTE_TASKS_SET_MinIndex (0UL)            /*!< Min index of TASKS_SET[8] array.                                     */
25563   #define GPIOTE_TASKS_SET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SET[8] register.                                */
25564 
25565 /* TASKS_SET @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
25566   #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL)       /*!< Position of TASKS_SET field.                                         */
25567   #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field.           */
25568   #define GPIOTE_TASKS_SET_TASKS_SET_Min (0x1UL)     /*!< Min enumerator value of TASKS_SET field.                             */
25569   #define GPIOTE_TASKS_SET_TASKS_SET_Max (0x1UL)     /*!< Max enumerator value of TASKS_SET field.                             */
25570   #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task                                                         */
25571 
25572 
25573 /* GPIOTE_TASKS_CLR: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
25574   #define GPIOTE_TASKS_CLR_MaxCount (8UL)            /*!< Max size of TASKS_CLR[8] array.                                      */
25575   #define GPIOTE_TASKS_CLR_MaxIndex (7UL)            /*!< Max index of TASKS_CLR[8] array.                                     */
25576   #define GPIOTE_TASKS_CLR_MinIndex (0UL)            /*!< Min index of TASKS_CLR[8] array.                                     */
25577   #define GPIOTE_TASKS_CLR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLR[8] register.                                */
25578 
25579 /* TASKS_CLR @Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
25580   #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL)       /*!< Position of TASKS_CLR field.                                         */
25581   #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field.           */
25582   #define GPIOTE_TASKS_CLR_TASKS_CLR_Min (0x1UL)     /*!< Min enumerator value of TASKS_CLR field.                             */
25583   #define GPIOTE_TASKS_CLR_TASKS_CLR_Max (0x1UL)     /*!< Max enumerator value of TASKS_CLR field.                             */
25584   #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task                                                         */
25585 
25586 
25587 /* GPIOTE_SUBSCRIBE_OUT: Subscribe configuration for task OUT[n] */
25588   #define GPIOTE_SUBSCRIBE_OUT_MaxCount (8UL)        /*!< Max size of SUBSCRIBE_OUT[8] array.                                  */
25589   #define GPIOTE_SUBSCRIBE_OUT_MaxIndex (7UL)        /*!< Max index of SUBSCRIBE_OUT[8] array.                                 */
25590   #define GPIOTE_SUBSCRIBE_OUT_MinIndex (0UL)        /*!< Min index of SUBSCRIBE_OUT[8] array.                                 */
25591   #define GPIOTE_SUBSCRIBE_OUT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_OUT[8] register.                        */
25592 
25593 /* CHIDX @Bits 0..7 : DPPI channel that task OUT[n] will subscribe to */
25594   #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
25595   #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
25596   #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
25597   #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
25598 
25599 /* EN @Bit 31 : (unspecified) */
25600   #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL)         /*!< Position of EN field.                                                */
25601   #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field.                        */
25602   #define GPIOTE_SUBSCRIBE_OUT_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
25603   #define GPIOTE_SUBSCRIBE_OUT_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
25604   #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
25605   #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
25606 
25607 
25608 /* GPIOTE_SUBSCRIBE_SET: Subscribe configuration for task SET[n] */
25609   #define GPIOTE_SUBSCRIBE_SET_MaxCount (8UL)        /*!< Max size of SUBSCRIBE_SET[8] array.                                  */
25610   #define GPIOTE_SUBSCRIBE_SET_MaxIndex (7UL)        /*!< Max index of SUBSCRIBE_SET[8] array.                                 */
25611   #define GPIOTE_SUBSCRIBE_SET_MinIndex (0UL)        /*!< Min index of SUBSCRIBE_SET[8] array.                                 */
25612   #define GPIOTE_SUBSCRIBE_SET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SET[8] register.                        */
25613 
25614 /* CHIDX @Bits 0..7 : DPPI channel that task SET[n] will subscribe to */
25615   #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
25616   #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
25617   #define GPIOTE_SUBSCRIBE_SET_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
25618   #define GPIOTE_SUBSCRIBE_SET_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
25619 
25620 /* EN @Bit 31 : (unspecified) */
25621   #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL)         /*!< Position of EN field.                                                */
25622   #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field.                        */
25623   #define GPIOTE_SUBSCRIBE_SET_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
25624   #define GPIOTE_SUBSCRIBE_SET_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
25625   #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
25626   #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
25627 
25628 
25629 /* GPIOTE_SUBSCRIBE_CLR: Subscribe configuration for task CLR[n] */
25630   #define GPIOTE_SUBSCRIBE_CLR_MaxCount (8UL)        /*!< Max size of SUBSCRIBE_CLR[8] array.                                  */
25631   #define GPIOTE_SUBSCRIBE_CLR_MaxIndex (7UL)        /*!< Max index of SUBSCRIBE_CLR[8] array.                                 */
25632   #define GPIOTE_SUBSCRIBE_CLR_MinIndex (0UL)        /*!< Min index of SUBSCRIBE_CLR[8] array.                                 */
25633   #define GPIOTE_SUBSCRIBE_CLR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLR[8] register.                        */
25634 
25635 /* CHIDX @Bits 0..7 : DPPI channel that task CLR[n] will subscribe to */
25636   #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
25637   #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
25638   #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
25639   #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
25640 
25641 /* EN @Bit 31 : (unspecified) */
25642   #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL)         /*!< Position of EN field.                                                */
25643   #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field.                        */
25644   #define GPIOTE_SUBSCRIBE_CLR_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
25645   #define GPIOTE_SUBSCRIBE_CLR_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
25646   #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
25647   #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
25648 
25649 
25650 /* GPIOTE_EVENTS_IN: Event from pin specified in CONFIG[n].PSEL */
25651   #define GPIOTE_EVENTS_IN_MaxCount (8UL)            /*!< Max size of EVENTS_IN[8] array.                                      */
25652   #define GPIOTE_EVENTS_IN_MaxIndex (7UL)            /*!< Max index of EVENTS_IN[8] array.                                     */
25653   #define GPIOTE_EVENTS_IN_MinIndex (0UL)            /*!< Min index of EVENTS_IN[8] array.                                     */
25654   #define GPIOTE_EVENTS_IN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_IN[8] register.                                */
25655 
25656 /* EVENTS_IN @Bit 0 : Event from pin specified in CONFIG[n].PSEL */
25657   #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL)       /*!< Position of EVENTS_IN field.                                         */
25658   #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field.           */
25659   #define GPIOTE_EVENTS_IN_EVENTS_IN_Min (0x0UL)     /*!< Min enumerator value of EVENTS_IN field.                             */
25660   #define GPIOTE_EVENTS_IN_EVENTS_IN_Max (0x1UL)     /*!< Max enumerator value of EVENTS_IN field.                             */
25661   #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated                                             */
25662   #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated                                                    */
25663 
25664 
25665 /* GPIOTE_PUBLISH_IN: Publish configuration for event IN[n] */
25666   #define GPIOTE_PUBLISH_IN_MaxCount (8UL)           /*!< Max size of PUBLISH_IN[8] array.                                     */
25667   #define GPIOTE_PUBLISH_IN_MaxIndex (7UL)           /*!< Max index of PUBLISH_IN[8] array.                                    */
25668   #define GPIOTE_PUBLISH_IN_MinIndex (0UL)           /*!< Min index of PUBLISH_IN[8] array.                                    */
25669   #define GPIOTE_PUBLISH_IN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_IN[8] register.                              */
25670 
25671 /* CHIDX @Bits 0..7 : DPPI channel that event IN[n] will publish to */
25672   #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
25673   #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
25674   #define GPIOTE_PUBLISH_IN_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
25675   #define GPIOTE_PUBLISH_IN_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
25676 
25677 /* EN @Bit 31 : (unspecified) */
25678   #define GPIOTE_PUBLISH_IN_EN_Pos (31UL)            /*!< Position of EN field.                                                */
25679   #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field.                              */
25680   #define GPIOTE_PUBLISH_IN_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
25681   #define GPIOTE_PUBLISH_IN_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
25682   #define GPIOTE_PUBLISH_IN_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
25683   #define GPIOTE_PUBLISH_IN_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
25684 
25685 
25686 /* GPIOTE_INTENSET0: Enable interrupt */
25687   #define GPIOTE_INTENSET0_ResetValue (0x00000000UL) /*!< Reset value of INTENSET0 register.                                   */
25688 
25689 /* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
25690   #define GPIOTE_INTENSET0_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
25691   #define GPIOTE_INTENSET0_IN0_Msk (0x1UL << GPIOTE_INTENSET0_IN0_Pos) /*!< Bit mask of IN0 field.                             */
25692   #define GPIOTE_INTENSET0_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
25693   #define GPIOTE_INTENSET0_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
25694   #define GPIOTE_INTENSET0_IN0_Set (0x1UL)           /*!< Enable                                                               */
25695   #define GPIOTE_INTENSET0_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25696   #define GPIOTE_INTENSET0_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25697 
25698 /* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
25699   #define GPIOTE_INTENSET0_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
25700   #define GPIOTE_INTENSET0_IN1_Msk (0x1UL << GPIOTE_INTENSET0_IN1_Pos) /*!< Bit mask of IN1 field.                             */
25701   #define GPIOTE_INTENSET0_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
25702   #define GPIOTE_INTENSET0_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
25703   #define GPIOTE_INTENSET0_IN1_Set (0x1UL)           /*!< Enable                                                               */
25704   #define GPIOTE_INTENSET0_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25705   #define GPIOTE_INTENSET0_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25706 
25707 /* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
25708   #define GPIOTE_INTENSET0_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
25709   #define GPIOTE_INTENSET0_IN2_Msk (0x1UL << GPIOTE_INTENSET0_IN2_Pos) /*!< Bit mask of IN2 field.                             */
25710   #define GPIOTE_INTENSET0_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
25711   #define GPIOTE_INTENSET0_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
25712   #define GPIOTE_INTENSET0_IN2_Set (0x1UL)           /*!< Enable                                                               */
25713   #define GPIOTE_INTENSET0_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25714   #define GPIOTE_INTENSET0_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25715 
25716 /* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
25717   #define GPIOTE_INTENSET0_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
25718   #define GPIOTE_INTENSET0_IN3_Msk (0x1UL << GPIOTE_INTENSET0_IN3_Pos) /*!< Bit mask of IN3 field.                             */
25719   #define GPIOTE_INTENSET0_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
25720   #define GPIOTE_INTENSET0_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
25721   #define GPIOTE_INTENSET0_IN3_Set (0x1UL)           /*!< Enable                                                               */
25722   #define GPIOTE_INTENSET0_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25723   #define GPIOTE_INTENSET0_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25724 
25725 /* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
25726   #define GPIOTE_INTENSET0_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
25727   #define GPIOTE_INTENSET0_IN4_Msk (0x1UL << GPIOTE_INTENSET0_IN4_Pos) /*!< Bit mask of IN4 field.                             */
25728   #define GPIOTE_INTENSET0_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
25729   #define GPIOTE_INTENSET0_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
25730   #define GPIOTE_INTENSET0_IN4_Set (0x1UL)           /*!< Enable                                                               */
25731   #define GPIOTE_INTENSET0_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25732   #define GPIOTE_INTENSET0_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25733 
25734 /* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
25735   #define GPIOTE_INTENSET0_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
25736   #define GPIOTE_INTENSET0_IN5_Msk (0x1UL << GPIOTE_INTENSET0_IN5_Pos) /*!< Bit mask of IN5 field.                             */
25737   #define GPIOTE_INTENSET0_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
25738   #define GPIOTE_INTENSET0_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
25739   #define GPIOTE_INTENSET0_IN5_Set (0x1UL)           /*!< Enable                                                               */
25740   #define GPIOTE_INTENSET0_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25741   #define GPIOTE_INTENSET0_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25742 
25743 /* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
25744   #define GPIOTE_INTENSET0_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
25745   #define GPIOTE_INTENSET0_IN6_Msk (0x1UL << GPIOTE_INTENSET0_IN6_Pos) /*!< Bit mask of IN6 field.                             */
25746   #define GPIOTE_INTENSET0_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
25747   #define GPIOTE_INTENSET0_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
25748   #define GPIOTE_INTENSET0_IN6_Set (0x1UL)           /*!< Enable                                                               */
25749   #define GPIOTE_INTENSET0_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25750   #define GPIOTE_INTENSET0_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25751 
25752 /* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
25753   #define GPIOTE_INTENSET0_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
25754   #define GPIOTE_INTENSET0_IN7_Msk (0x1UL << GPIOTE_INTENSET0_IN7_Pos) /*!< Bit mask of IN7 field.                             */
25755   #define GPIOTE_INTENSET0_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
25756   #define GPIOTE_INTENSET0_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
25757   #define GPIOTE_INTENSET0_IN7_Set (0x1UL)           /*!< Enable                                                               */
25758   #define GPIOTE_INTENSET0_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25759   #define GPIOTE_INTENSET0_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25760 
25761 /* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
25762   #define GPIOTE_INTENSET0_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
25763   #define GPIOTE_INTENSET0_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
25764                                                                             field.*/
25765   #define GPIOTE_INTENSET0_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
25766   #define GPIOTE_INTENSET0_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
25767   #define GPIOTE_INTENSET0_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
25768   #define GPIOTE_INTENSET0_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
25769   #define GPIOTE_INTENSET0_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
25770 
25771 /* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
25772   #define GPIOTE_INTENSET0_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
25773   #define GPIOTE_INTENSET0_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
25774   #define GPIOTE_INTENSET0_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
25775   #define GPIOTE_INTENSET0_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
25776   #define GPIOTE_INTENSET0_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
25777   #define GPIOTE_INTENSET0_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
25778   #define GPIOTE_INTENSET0_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
25779 
25780 /* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */
25781   #define GPIOTE_INTENSET0_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
25782   #define GPIOTE_INTENSET0_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
25783                                                                             field.*/
25784   #define GPIOTE_INTENSET0_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
25785   #define GPIOTE_INTENSET0_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
25786   #define GPIOTE_INTENSET0_PORT1NONSECURE_Set (0x1UL) /*!< Enable                                                              */
25787   #define GPIOTE_INTENSET0_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
25788   #define GPIOTE_INTENSET0_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
25789 
25790 /* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */
25791   #define GPIOTE_INTENSET0_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
25792   #define GPIOTE_INTENSET0_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
25793   #define GPIOTE_INTENSET0_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
25794   #define GPIOTE_INTENSET0_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
25795   #define GPIOTE_INTENSET0_PORT1SECURE_Set (0x1UL)   /*!< Enable                                                               */
25796   #define GPIOTE_INTENSET0_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
25797   #define GPIOTE_INTENSET0_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
25798 
25799 /* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */
25800   #define GPIOTE_INTENSET0_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
25801   #define GPIOTE_INTENSET0_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
25802                                                                             field.*/
25803   #define GPIOTE_INTENSET0_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
25804   #define GPIOTE_INTENSET0_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
25805   #define GPIOTE_INTENSET0_PORT2NONSECURE_Set (0x1UL) /*!< Enable                                                              */
25806   #define GPIOTE_INTENSET0_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
25807   #define GPIOTE_INTENSET0_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
25808 
25809 /* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */
25810   #define GPIOTE_INTENSET0_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
25811   #define GPIOTE_INTENSET0_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
25812   #define GPIOTE_INTENSET0_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
25813   #define GPIOTE_INTENSET0_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
25814   #define GPIOTE_INTENSET0_PORT2SECURE_Set (0x1UL)   /*!< Enable                                                               */
25815   #define GPIOTE_INTENSET0_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
25816   #define GPIOTE_INTENSET0_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
25817 
25818 /* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */
25819   #define GPIOTE_INTENSET0_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
25820   #define GPIOTE_INTENSET0_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
25821                                                                             field.*/
25822   #define GPIOTE_INTENSET0_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
25823   #define GPIOTE_INTENSET0_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
25824   #define GPIOTE_INTENSET0_PORT3NONSECURE_Set (0x1UL) /*!< Enable                                                              */
25825   #define GPIOTE_INTENSET0_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
25826   #define GPIOTE_INTENSET0_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
25827 
25828 /* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */
25829   #define GPIOTE_INTENSET0_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
25830   #define GPIOTE_INTENSET0_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET0_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
25831   #define GPIOTE_INTENSET0_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
25832   #define GPIOTE_INTENSET0_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
25833   #define GPIOTE_INTENSET0_PORT3SECURE_Set (0x1UL)   /*!< Enable                                                               */
25834   #define GPIOTE_INTENSET0_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
25835   #define GPIOTE_INTENSET0_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
25836 
25837 
25838 /* GPIOTE_INTENCLR0: Disable interrupt */
25839   #define GPIOTE_INTENCLR0_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR0 register.                                   */
25840 
25841 /* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
25842   #define GPIOTE_INTENCLR0_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
25843   #define GPIOTE_INTENCLR0_IN0_Msk (0x1UL << GPIOTE_INTENCLR0_IN0_Pos) /*!< Bit mask of IN0 field.                             */
25844   #define GPIOTE_INTENCLR0_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
25845   #define GPIOTE_INTENCLR0_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
25846   #define GPIOTE_INTENCLR0_IN0_Clear (0x1UL)         /*!< Disable                                                              */
25847   #define GPIOTE_INTENCLR0_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25848   #define GPIOTE_INTENCLR0_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25849 
25850 /* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
25851   #define GPIOTE_INTENCLR0_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
25852   #define GPIOTE_INTENCLR0_IN1_Msk (0x1UL << GPIOTE_INTENCLR0_IN1_Pos) /*!< Bit mask of IN1 field.                             */
25853   #define GPIOTE_INTENCLR0_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
25854   #define GPIOTE_INTENCLR0_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
25855   #define GPIOTE_INTENCLR0_IN1_Clear (0x1UL)         /*!< Disable                                                              */
25856   #define GPIOTE_INTENCLR0_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25857   #define GPIOTE_INTENCLR0_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25858 
25859 /* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
25860   #define GPIOTE_INTENCLR0_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
25861   #define GPIOTE_INTENCLR0_IN2_Msk (0x1UL << GPIOTE_INTENCLR0_IN2_Pos) /*!< Bit mask of IN2 field.                             */
25862   #define GPIOTE_INTENCLR0_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
25863   #define GPIOTE_INTENCLR0_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
25864   #define GPIOTE_INTENCLR0_IN2_Clear (0x1UL)         /*!< Disable                                                              */
25865   #define GPIOTE_INTENCLR0_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25866   #define GPIOTE_INTENCLR0_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25867 
25868 /* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
25869   #define GPIOTE_INTENCLR0_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
25870   #define GPIOTE_INTENCLR0_IN3_Msk (0x1UL << GPIOTE_INTENCLR0_IN3_Pos) /*!< Bit mask of IN3 field.                             */
25871   #define GPIOTE_INTENCLR0_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
25872   #define GPIOTE_INTENCLR0_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
25873   #define GPIOTE_INTENCLR0_IN3_Clear (0x1UL)         /*!< Disable                                                              */
25874   #define GPIOTE_INTENCLR0_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25875   #define GPIOTE_INTENCLR0_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25876 
25877 /* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
25878   #define GPIOTE_INTENCLR0_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
25879   #define GPIOTE_INTENCLR0_IN4_Msk (0x1UL << GPIOTE_INTENCLR0_IN4_Pos) /*!< Bit mask of IN4 field.                             */
25880   #define GPIOTE_INTENCLR0_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
25881   #define GPIOTE_INTENCLR0_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
25882   #define GPIOTE_INTENCLR0_IN4_Clear (0x1UL)         /*!< Disable                                                              */
25883   #define GPIOTE_INTENCLR0_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25884   #define GPIOTE_INTENCLR0_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25885 
25886 /* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
25887   #define GPIOTE_INTENCLR0_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
25888   #define GPIOTE_INTENCLR0_IN5_Msk (0x1UL << GPIOTE_INTENCLR0_IN5_Pos) /*!< Bit mask of IN5 field.                             */
25889   #define GPIOTE_INTENCLR0_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
25890   #define GPIOTE_INTENCLR0_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
25891   #define GPIOTE_INTENCLR0_IN5_Clear (0x1UL)         /*!< Disable                                                              */
25892   #define GPIOTE_INTENCLR0_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25893   #define GPIOTE_INTENCLR0_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25894 
25895 /* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
25896   #define GPIOTE_INTENCLR0_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
25897   #define GPIOTE_INTENCLR0_IN6_Msk (0x1UL << GPIOTE_INTENCLR0_IN6_Pos) /*!< Bit mask of IN6 field.                             */
25898   #define GPIOTE_INTENCLR0_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
25899   #define GPIOTE_INTENCLR0_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
25900   #define GPIOTE_INTENCLR0_IN6_Clear (0x1UL)         /*!< Disable                                                              */
25901   #define GPIOTE_INTENCLR0_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25902   #define GPIOTE_INTENCLR0_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25903 
25904 /* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
25905   #define GPIOTE_INTENCLR0_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
25906   #define GPIOTE_INTENCLR0_IN7_Msk (0x1UL << GPIOTE_INTENCLR0_IN7_Pos) /*!< Bit mask of IN7 field.                             */
25907   #define GPIOTE_INTENCLR0_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
25908   #define GPIOTE_INTENCLR0_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
25909   #define GPIOTE_INTENCLR0_IN7_Clear (0x1UL)         /*!< Disable                                                              */
25910   #define GPIOTE_INTENCLR0_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
25911   #define GPIOTE_INTENCLR0_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
25912 
25913 /* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
25914   #define GPIOTE_INTENCLR0_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
25915   #define GPIOTE_INTENCLR0_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
25916                                                                             field.*/
25917   #define GPIOTE_INTENCLR0_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
25918   #define GPIOTE_INTENCLR0_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
25919   #define GPIOTE_INTENCLR0_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
25920   #define GPIOTE_INTENCLR0_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
25921   #define GPIOTE_INTENCLR0_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
25922 
25923 /* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
25924   #define GPIOTE_INTENCLR0_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
25925   #define GPIOTE_INTENCLR0_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
25926   #define GPIOTE_INTENCLR0_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
25927   #define GPIOTE_INTENCLR0_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
25928   #define GPIOTE_INTENCLR0_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
25929   #define GPIOTE_INTENCLR0_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
25930   #define GPIOTE_INTENCLR0_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
25931 
25932 /* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */
25933   #define GPIOTE_INTENCLR0_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
25934   #define GPIOTE_INTENCLR0_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
25935                                                                             field.*/
25936   #define GPIOTE_INTENCLR0_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
25937   #define GPIOTE_INTENCLR0_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
25938   #define GPIOTE_INTENCLR0_PORT1NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
25939   #define GPIOTE_INTENCLR0_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
25940   #define GPIOTE_INTENCLR0_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
25941 
25942 /* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */
25943   #define GPIOTE_INTENCLR0_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
25944   #define GPIOTE_INTENCLR0_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
25945   #define GPIOTE_INTENCLR0_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
25946   #define GPIOTE_INTENCLR0_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
25947   #define GPIOTE_INTENCLR0_PORT1SECURE_Clear (0x1UL) /*!< Disable                                                              */
25948   #define GPIOTE_INTENCLR0_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
25949   #define GPIOTE_INTENCLR0_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
25950 
25951 /* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */
25952   #define GPIOTE_INTENCLR0_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
25953   #define GPIOTE_INTENCLR0_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
25954                                                                             field.*/
25955   #define GPIOTE_INTENCLR0_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
25956   #define GPIOTE_INTENCLR0_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
25957   #define GPIOTE_INTENCLR0_PORT2NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
25958   #define GPIOTE_INTENCLR0_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
25959   #define GPIOTE_INTENCLR0_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
25960 
25961 /* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */
25962   #define GPIOTE_INTENCLR0_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
25963   #define GPIOTE_INTENCLR0_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
25964   #define GPIOTE_INTENCLR0_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
25965   #define GPIOTE_INTENCLR0_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
25966   #define GPIOTE_INTENCLR0_PORT2SECURE_Clear (0x1UL) /*!< Disable                                                              */
25967   #define GPIOTE_INTENCLR0_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
25968   #define GPIOTE_INTENCLR0_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
25969 
25970 /* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */
25971   #define GPIOTE_INTENCLR0_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
25972   #define GPIOTE_INTENCLR0_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
25973                                                                             field.*/
25974   #define GPIOTE_INTENCLR0_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
25975   #define GPIOTE_INTENCLR0_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
25976   #define GPIOTE_INTENCLR0_PORT3NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
25977   #define GPIOTE_INTENCLR0_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
25978   #define GPIOTE_INTENCLR0_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
25979 
25980 /* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */
25981   #define GPIOTE_INTENCLR0_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
25982   #define GPIOTE_INTENCLR0_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR0_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
25983   #define GPIOTE_INTENCLR0_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
25984   #define GPIOTE_INTENCLR0_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
25985   #define GPIOTE_INTENCLR0_PORT3SECURE_Clear (0x1UL) /*!< Disable                                                              */
25986   #define GPIOTE_INTENCLR0_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
25987   #define GPIOTE_INTENCLR0_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
25988 
25989 
25990 /* GPIOTE_INTENSET1: Enable interrupt */
25991   #define GPIOTE_INTENSET1_ResetValue (0x00000000UL) /*!< Reset value of INTENSET1 register.                                   */
25992 
25993 /* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
25994   #define GPIOTE_INTENSET1_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
25995   #define GPIOTE_INTENSET1_IN0_Msk (0x1UL << GPIOTE_INTENSET1_IN0_Pos) /*!< Bit mask of IN0 field.                             */
25996   #define GPIOTE_INTENSET1_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
25997   #define GPIOTE_INTENSET1_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
25998   #define GPIOTE_INTENSET1_IN0_Set (0x1UL)           /*!< Enable                                                               */
25999   #define GPIOTE_INTENSET1_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26000   #define GPIOTE_INTENSET1_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26001 
26002 /* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
26003   #define GPIOTE_INTENSET1_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
26004   #define GPIOTE_INTENSET1_IN1_Msk (0x1UL << GPIOTE_INTENSET1_IN1_Pos) /*!< Bit mask of IN1 field.                             */
26005   #define GPIOTE_INTENSET1_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
26006   #define GPIOTE_INTENSET1_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
26007   #define GPIOTE_INTENSET1_IN1_Set (0x1UL)           /*!< Enable                                                               */
26008   #define GPIOTE_INTENSET1_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26009   #define GPIOTE_INTENSET1_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26010 
26011 /* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
26012   #define GPIOTE_INTENSET1_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
26013   #define GPIOTE_INTENSET1_IN2_Msk (0x1UL << GPIOTE_INTENSET1_IN2_Pos) /*!< Bit mask of IN2 field.                             */
26014   #define GPIOTE_INTENSET1_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
26015   #define GPIOTE_INTENSET1_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
26016   #define GPIOTE_INTENSET1_IN2_Set (0x1UL)           /*!< Enable                                                               */
26017   #define GPIOTE_INTENSET1_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26018   #define GPIOTE_INTENSET1_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26019 
26020 /* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
26021   #define GPIOTE_INTENSET1_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
26022   #define GPIOTE_INTENSET1_IN3_Msk (0x1UL << GPIOTE_INTENSET1_IN3_Pos) /*!< Bit mask of IN3 field.                             */
26023   #define GPIOTE_INTENSET1_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
26024   #define GPIOTE_INTENSET1_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
26025   #define GPIOTE_INTENSET1_IN3_Set (0x1UL)           /*!< Enable                                                               */
26026   #define GPIOTE_INTENSET1_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26027   #define GPIOTE_INTENSET1_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26028 
26029 /* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
26030   #define GPIOTE_INTENSET1_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
26031   #define GPIOTE_INTENSET1_IN4_Msk (0x1UL << GPIOTE_INTENSET1_IN4_Pos) /*!< Bit mask of IN4 field.                             */
26032   #define GPIOTE_INTENSET1_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
26033   #define GPIOTE_INTENSET1_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
26034   #define GPIOTE_INTENSET1_IN4_Set (0x1UL)           /*!< Enable                                                               */
26035   #define GPIOTE_INTENSET1_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26036   #define GPIOTE_INTENSET1_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26037 
26038 /* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
26039   #define GPIOTE_INTENSET1_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
26040   #define GPIOTE_INTENSET1_IN5_Msk (0x1UL << GPIOTE_INTENSET1_IN5_Pos) /*!< Bit mask of IN5 field.                             */
26041   #define GPIOTE_INTENSET1_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
26042   #define GPIOTE_INTENSET1_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
26043   #define GPIOTE_INTENSET1_IN5_Set (0x1UL)           /*!< Enable                                                               */
26044   #define GPIOTE_INTENSET1_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26045   #define GPIOTE_INTENSET1_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26046 
26047 /* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
26048   #define GPIOTE_INTENSET1_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
26049   #define GPIOTE_INTENSET1_IN6_Msk (0x1UL << GPIOTE_INTENSET1_IN6_Pos) /*!< Bit mask of IN6 field.                             */
26050   #define GPIOTE_INTENSET1_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
26051   #define GPIOTE_INTENSET1_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
26052   #define GPIOTE_INTENSET1_IN6_Set (0x1UL)           /*!< Enable                                                               */
26053   #define GPIOTE_INTENSET1_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26054   #define GPIOTE_INTENSET1_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26055 
26056 /* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
26057   #define GPIOTE_INTENSET1_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
26058   #define GPIOTE_INTENSET1_IN7_Msk (0x1UL << GPIOTE_INTENSET1_IN7_Pos) /*!< Bit mask of IN7 field.                             */
26059   #define GPIOTE_INTENSET1_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
26060   #define GPIOTE_INTENSET1_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
26061   #define GPIOTE_INTENSET1_IN7_Set (0x1UL)           /*!< Enable                                                               */
26062   #define GPIOTE_INTENSET1_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26063   #define GPIOTE_INTENSET1_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26064 
26065 /* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
26066   #define GPIOTE_INTENSET1_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
26067   #define GPIOTE_INTENSET1_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
26068                                                                             field.*/
26069   #define GPIOTE_INTENSET1_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
26070   #define GPIOTE_INTENSET1_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
26071   #define GPIOTE_INTENSET1_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26072   #define GPIOTE_INTENSET1_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26073   #define GPIOTE_INTENSET1_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26074 
26075 /* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
26076   #define GPIOTE_INTENSET1_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
26077   #define GPIOTE_INTENSET1_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
26078   #define GPIOTE_INTENSET1_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
26079   #define GPIOTE_INTENSET1_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
26080   #define GPIOTE_INTENSET1_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
26081   #define GPIOTE_INTENSET1_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26082   #define GPIOTE_INTENSET1_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26083 
26084 /* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */
26085   #define GPIOTE_INTENSET1_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
26086   #define GPIOTE_INTENSET1_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
26087                                                                             field.*/
26088   #define GPIOTE_INTENSET1_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
26089   #define GPIOTE_INTENSET1_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
26090   #define GPIOTE_INTENSET1_PORT1NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26091   #define GPIOTE_INTENSET1_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26092   #define GPIOTE_INTENSET1_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26093 
26094 /* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */
26095   #define GPIOTE_INTENSET1_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
26096   #define GPIOTE_INTENSET1_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
26097   #define GPIOTE_INTENSET1_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
26098   #define GPIOTE_INTENSET1_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
26099   #define GPIOTE_INTENSET1_PORT1SECURE_Set (0x1UL)   /*!< Enable                                                               */
26100   #define GPIOTE_INTENSET1_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26101   #define GPIOTE_INTENSET1_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26102 
26103 /* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */
26104   #define GPIOTE_INTENSET1_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
26105   #define GPIOTE_INTENSET1_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
26106                                                                             field.*/
26107   #define GPIOTE_INTENSET1_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
26108   #define GPIOTE_INTENSET1_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
26109   #define GPIOTE_INTENSET1_PORT2NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26110   #define GPIOTE_INTENSET1_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26111   #define GPIOTE_INTENSET1_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26112 
26113 /* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */
26114   #define GPIOTE_INTENSET1_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
26115   #define GPIOTE_INTENSET1_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
26116   #define GPIOTE_INTENSET1_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
26117   #define GPIOTE_INTENSET1_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
26118   #define GPIOTE_INTENSET1_PORT2SECURE_Set (0x1UL)   /*!< Enable                                                               */
26119   #define GPIOTE_INTENSET1_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26120   #define GPIOTE_INTENSET1_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26121 
26122 /* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */
26123   #define GPIOTE_INTENSET1_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
26124   #define GPIOTE_INTENSET1_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
26125                                                                             field.*/
26126   #define GPIOTE_INTENSET1_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
26127   #define GPIOTE_INTENSET1_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
26128   #define GPIOTE_INTENSET1_PORT3NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26129   #define GPIOTE_INTENSET1_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26130   #define GPIOTE_INTENSET1_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26131 
26132 /* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */
26133   #define GPIOTE_INTENSET1_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
26134   #define GPIOTE_INTENSET1_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET1_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
26135   #define GPIOTE_INTENSET1_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
26136   #define GPIOTE_INTENSET1_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
26137   #define GPIOTE_INTENSET1_PORT3SECURE_Set (0x1UL)   /*!< Enable                                                               */
26138   #define GPIOTE_INTENSET1_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26139   #define GPIOTE_INTENSET1_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26140 
26141 
26142 /* GPIOTE_INTENCLR1: Disable interrupt */
26143   #define GPIOTE_INTENCLR1_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR1 register.                                   */
26144 
26145 /* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
26146   #define GPIOTE_INTENCLR1_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
26147   #define GPIOTE_INTENCLR1_IN0_Msk (0x1UL << GPIOTE_INTENCLR1_IN0_Pos) /*!< Bit mask of IN0 field.                             */
26148   #define GPIOTE_INTENCLR1_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
26149   #define GPIOTE_INTENCLR1_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
26150   #define GPIOTE_INTENCLR1_IN0_Clear (0x1UL)         /*!< Disable                                                              */
26151   #define GPIOTE_INTENCLR1_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26152   #define GPIOTE_INTENCLR1_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26153 
26154 /* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
26155   #define GPIOTE_INTENCLR1_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
26156   #define GPIOTE_INTENCLR1_IN1_Msk (0x1UL << GPIOTE_INTENCLR1_IN1_Pos) /*!< Bit mask of IN1 field.                             */
26157   #define GPIOTE_INTENCLR1_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
26158   #define GPIOTE_INTENCLR1_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
26159   #define GPIOTE_INTENCLR1_IN1_Clear (0x1UL)         /*!< Disable                                                              */
26160   #define GPIOTE_INTENCLR1_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26161   #define GPIOTE_INTENCLR1_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26162 
26163 /* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
26164   #define GPIOTE_INTENCLR1_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
26165   #define GPIOTE_INTENCLR1_IN2_Msk (0x1UL << GPIOTE_INTENCLR1_IN2_Pos) /*!< Bit mask of IN2 field.                             */
26166   #define GPIOTE_INTENCLR1_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
26167   #define GPIOTE_INTENCLR1_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
26168   #define GPIOTE_INTENCLR1_IN2_Clear (0x1UL)         /*!< Disable                                                              */
26169   #define GPIOTE_INTENCLR1_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26170   #define GPIOTE_INTENCLR1_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26171 
26172 /* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
26173   #define GPIOTE_INTENCLR1_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
26174   #define GPIOTE_INTENCLR1_IN3_Msk (0x1UL << GPIOTE_INTENCLR1_IN3_Pos) /*!< Bit mask of IN3 field.                             */
26175   #define GPIOTE_INTENCLR1_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
26176   #define GPIOTE_INTENCLR1_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
26177   #define GPIOTE_INTENCLR1_IN3_Clear (0x1UL)         /*!< Disable                                                              */
26178   #define GPIOTE_INTENCLR1_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26179   #define GPIOTE_INTENCLR1_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26180 
26181 /* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
26182   #define GPIOTE_INTENCLR1_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
26183   #define GPIOTE_INTENCLR1_IN4_Msk (0x1UL << GPIOTE_INTENCLR1_IN4_Pos) /*!< Bit mask of IN4 field.                             */
26184   #define GPIOTE_INTENCLR1_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
26185   #define GPIOTE_INTENCLR1_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
26186   #define GPIOTE_INTENCLR1_IN4_Clear (0x1UL)         /*!< Disable                                                              */
26187   #define GPIOTE_INTENCLR1_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26188   #define GPIOTE_INTENCLR1_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26189 
26190 /* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
26191   #define GPIOTE_INTENCLR1_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
26192   #define GPIOTE_INTENCLR1_IN5_Msk (0x1UL << GPIOTE_INTENCLR1_IN5_Pos) /*!< Bit mask of IN5 field.                             */
26193   #define GPIOTE_INTENCLR1_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
26194   #define GPIOTE_INTENCLR1_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
26195   #define GPIOTE_INTENCLR1_IN5_Clear (0x1UL)         /*!< Disable                                                              */
26196   #define GPIOTE_INTENCLR1_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26197   #define GPIOTE_INTENCLR1_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26198 
26199 /* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
26200   #define GPIOTE_INTENCLR1_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
26201   #define GPIOTE_INTENCLR1_IN6_Msk (0x1UL << GPIOTE_INTENCLR1_IN6_Pos) /*!< Bit mask of IN6 field.                             */
26202   #define GPIOTE_INTENCLR1_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
26203   #define GPIOTE_INTENCLR1_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
26204   #define GPIOTE_INTENCLR1_IN6_Clear (0x1UL)         /*!< Disable                                                              */
26205   #define GPIOTE_INTENCLR1_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26206   #define GPIOTE_INTENCLR1_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26207 
26208 /* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
26209   #define GPIOTE_INTENCLR1_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
26210   #define GPIOTE_INTENCLR1_IN7_Msk (0x1UL << GPIOTE_INTENCLR1_IN7_Pos) /*!< Bit mask of IN7 field.                             */
26211   #define GPIOTE_INTENCLR1_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
26212   #define GPIOTE_INTENCLR1_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
26213   #define GPIOTE_INTENCLR1_IN7_Clear (0x1UL)         /*!< Disable                                                              */
26214   #define GPIOTE_INTENCLR1_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26215   #define GPIOTE_INTENCLR1_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26216 
26217 /* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
26218   #define GPIOTE_INTENCLR1_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
26219   #define GPIOTE_INTENCLR1_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
26220                                                                             field.*/
26221   #define GPIOTE_INTENCLR1_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
26222   #define GPIOTE_INTENCLR1_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
26223   #define GPIOTE_INTENCLR1_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26224   #define GPIOTE_INTENCLR1_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26225   #define GPIOTE_INTENCLR1_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26226 
26227 /* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
26228   #define GPIOTE_INTENCLR1_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
26229   #define GPIOTE_INTENCLR1_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
26230   #define GPIOTE_INTENCLR1_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
26231   #define GPIOTE_INTENCLR1_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
26232   #define GPIOTE_INTENCLR1_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
26233   #define GPIOTE_INTENCLR1_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26234   #define GPIOTE_INTENCLR1_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26235 
26236 /* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */
26237   #define GPIOTE_INTENCLR1_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
26238   #define GPIOTE_INTENCLR1_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
26239                                                                             field.*/
26240   #define GPIOTE_INTENCLR1_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
26241   #define GPIOTE_INTENCLR1_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
26242   #define GPIOTE_INTENCLR1_PORT1NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26243   #define GPIOTE_INTENCLR1_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26244   #define GPIOTE_INTENCLR1_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26245 
26246 /* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */
26247   #define GPIOTE_INTENCLR1_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
26248   #define GPIOTE_INTENCLR1_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
26249   #define GPIOTE_INTENCLR1_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
26250   #define GPIOTE_INTENCLR1_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
26251   #define GPIOTE_INTENCLR1_PORT1SECURE_Clear (0x1UL) /*!< Disable                                                              */
26252   #define GPIOTE_INTENCLR1_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26253   #define GPIOTE_INTENCLR1_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26254 
26255 /* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */
26256   #define GPIOTE_INTENCLR1_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
26257   #define GPIOTE_INTENCLR1_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
26258                                                                             field.*/
26259   #define GPIOTE_INTENCLR1_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
26260   #define GPIOTE_INTENCLR1_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
26261   #define GPIOTE_INTENCLR1_PORT2NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26262   #define GPIOTE_INTENCLR1_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26263   #define GPIOTE_INTENCLR1_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26264 
26265 /* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */
26266   #define GPIOTE_INTENCLR1_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
26267   #define GPIOTE_INTENCLR1_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
26268   #define GPIOTE_INTENCLR1_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
26269   #define GPIOTE_INTENCLR1_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
26270   #define GPIOTE_INTENCLR1_PORT2SECURE_Clear (0x1UL) /*!< Disable                                                              */
26271   #define GPIOTE_INTENCLR1_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26272   #define GPIOTE_INTENCLR1_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26273 
26274 /* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */
26275   #define GPIOTE_INTENCLR1_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
26276   #define GPIOTE_INTENCLR1_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
26277                                                                             field.*/
26278   #define GPIOTE_INTENCLR1_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
26279   #define GPIOTE_INTENCLR1_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
26280   #define GPIOTE_INTENCLR1_PORT3NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26281   #define GPIOTE_INTENCLR1_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26282   #define GPIOTE_INTENCLR1_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26283 
26284 /* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */
26285   #define GPIOTE_INTENCLR1_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
26286   #define GPIOTE_INTENCLR1_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR1_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
26287   #define GPIOTE_INTENCLR1_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
26288   #define GPIOTE_INTENCLR1_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
26289   #define GPIOTE_INTENCLR1_PORT3SECURE_Clear (0x1UL) /*!< Disable                                                              */
26290   #define GPIOTE_INTENCLR1_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26291   #define GPIOTE_INTENCLR1_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26292 
26293 
26294 /* GPIOTE_INTENSET2: Enable interrupt */
26295   #define GPIOTE_INTENSET2_ResetValue (0x00000000UL) /*!< Reset value of INTENSET2 register.                                   */
26296 
26297 /* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
26298   #define GPIOTE_INTENSET2_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
26299   #define GPIOTE_INTENSET2_IN0_Msk (0x1UL << GPIOTE_INTENSET2_IN0_Pos) /*!< Bit mask of IN0 field.                             */
26300   #define GPIOTE_INTENSET2_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
26301   #define GPIOTE_INTENSET2_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
26302   #define GPIOTE_INTENSET2_IN0_Set (0x1UL)           /*!< Enable                                                               */
26303   #define GPIOTE_INTENSET2_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26304   #define GPIOTE_INTENSET2_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26305 
26306 /* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
26307   #define GPIOTE_INTENSET2_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
26308   #define GPIOTE_INTENSET2_IN1_Msk (0x1UL << GPIOTE_INTENSET2_IN1_Pos) /*!< Bit mask of IN1 field.                             */
26309   #define GPIOTE_INTENSET2_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
26310   #define GPIOTE_INTENSET2_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
26311   #define GPIOTE_INTENSET2_IN1_Set (0x1UL)           /*!< Enable                                                               */
26312   #define GPIOTE_INTENSET2_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26313   #define GPIOTE_INTENSET2_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26314 
26315 /* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
26316   #define GPIOTE_INTENSET2_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
26317   #define GPIOTE_INTENSET2_IN2_Msk (0x1UL << GPIOTE_INTENSET2_IN2_Pos) /*!< Bit mask of IN2 field.                             */
26318   #define GPIOTE_INTENSET2_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
26319   #define GPIOTE_INTENSET2_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
26320   #define GPIOTE_INTENSET2_IN2_Set (0x1UL)           /*!< Enable                                                               */
26321   #define GPIOTE_INTENSET2_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26322   #define GPIOTE_INTENSET2_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26323 
26324 /* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
26325   #define GPIOTE_INTENSET2_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
26326   #define GPIOTE_INTENSET2_IN3_Msk (0x1UL << GPIOTE_INTENSET2_IN3_Pos) /*!< Bit mask of IN3 field.                             */
26327   #define GPIOTE_INTENSET2_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
26328   #define GPIOTE_INTENSET2_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
26329   #define GPIOTE_INTENSET2_IN3_Set (0x1UL)           /*!< Enable                                                               */
26330   #define GPIOTE_INTENSET2_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26331   #define GPIOTE_INTENSET2_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26332 
26333 /* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
26334   #define GPIOTE_INTENSET2_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
26335   #define GPIOTE_INTENSET2_IN4_Msk (0x1UL << GPIOTE_INTENSET2_IN4_Pos) /*!< Bit mask of IN4 field.                             */
26336   #define GPIOTE_INTENSET2_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
26337   #define GPIOTE_INTENSET2_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
26338   #define GPIOTE_INTENSET2_IN4_Set (0x1UL)           /*!< Enable                                                               */
26339   #define GPIOTE_INTENSET2_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26340   #define GPIOTE_INTENSET2_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26341 
26342 /* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
26343   #define GPIOTE_INTENSET2_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
26344   #define GPIOTE_INTENSET2_IN5_Msk (0x1UL << GPIOTE_INTENSET2_IN5_Pos) /*!< Bit mask of IN5 field.                             */
26345   #define GPIOTE_INTENSET2_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
26346   #define GPIOTE_INTENSET2_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
26347   #define GPIOTE_INTENSET2_IN5_Set (0x1UL)           /*!< Enable                                                               */
26348   #define GPIOTE_INTENSET2_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26349   #define GPIOTE_INTENSET2_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26350 
26351 /* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
26352   #define GPIOTE_INTENSET2_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
26353   #define GPIOTE_INTENSET2_IN6_Msk (0x1UL << GPIOTE_INTENSET2_IN6_Pos) /*!< Bit mask of IN6 field.                             */
26354   #define GPIOTE_INTENSET2_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
26355   #define GPIOTE_INTENSET2_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
26356   #define GPIOTE_INTENSET2_IN6_Set (0x1UL)           /*!< Enable                                                               */
26357   #define GPIOTE_INTENSET2_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26358   #define GPIOTE_INTENSET2_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26359 
26360 /* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
26361   #define GPIOTE_INTENSET2_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
26362   #define GPIOTE_INTENSET2_IN7_Msk (0x1UL << GPIOTE_INTENSET2_IN7_Pos) /*!< Bit mask of IN7 field.                             */
26363   #define GPIOTE_INTENSET2_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
26364   #define GPIOTE_INTENSET2_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
26365   #define GPIOTE_INTENSET2_IN7_Set (0x1UL)           /*!< Enable                                                               */
26366   #define GPIOTE_INTENSET2_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26367   #define GPIOTE_INTENSET2_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26368 
26369 /* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
26370   #define GPIOTE_INTENSET2_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
26371   #define GPIOTE_INTENSET2_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
26372                                                                             field.*/
26373   #define GPIOTE_INTENSET2_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
26374   #define GPIOTE_INTENSET2_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
26375   #define GPIOTE_INTENSET2_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26376   #define GPIOTE_INTENSET2_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26377   #define GPIOTE_INTENSET2_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26378 
26379 /* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
26380   #define GPIOTE_INTENSET2_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
26381   #define GPIOTE_INTENSET2_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
26382   #define GPIOTE_INTENSET2_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
26383   #define GPIOTE_INTENSET2_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
26384   #define GPIOTE_INTENSET2_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
26385   #define GPIOTE_INTENSET2_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26386   #define GPIOTE_INTENSET2_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26387 
26388 /* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */
26389   #define GPIOTE_INTENSET2_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
26390   #define GPIOTE_INTENSET2_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
26391                                                                             field.*/
26392   #define GPIOTE_INTENSET2_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
26393   #define GPIOTE_INTENSET2_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
26394   #define GPIOTE_INTENSET2_PORT1NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26395   #define GPIOTE_INTENSET2_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26396   #define GPIOTE_INTENSET2_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26397 
26398 /* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */
26399   #define GPIOTE_INTENSET2_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
26400   #define GPIOTE_INTENSET2_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
26401   #define GPIOTE_INTENSET2_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
26402   #define GPIOTE_INTENSET2_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
26403   #define GPIOTE_INTENSET2_PORT1SECURE_Set (0x1UL)   /*!< Enable                                                               */
26404   #define GPIOTE_INTENSET2_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26405   #define GPIOTE_INTENSET2_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26406 
26407 /* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */
26408   #define GPIOTE_INTENSET2_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
26409   #define GPIOTE_INTENSET2_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
26410                                                                             field.*/
26411   #define GPIOTE_INTENSET2_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
26412   #define GPIOTE_INTENSET2_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
26413   #define GPIOTE_INTENSET2_PORT2NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26414   #define GPIOTE_INTENSET2_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26415   #define GPIOTE_INTENSET2_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26416 
26417 /* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */
26418   #define GPIOTE_INTENSET2_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
26419   #define GPIOTE_INTENSET2_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
26420   #define GPIOTE_INTENSET2_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
26421   #define GPIOTE_INTENSET2_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
26422   #define GPIOTE_INTENSET2_PORT2SECURE_Set (0x1UL)   /*!< Enable                                                               */
26423   #define GPIOTE_INTENSET2_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26424   #define GPIOTE_INTENSET2_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26425 
26426 /* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */
26427   #define GPIOTE_INTENSET2_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
26428   #define GPIOTE_INTENSET2_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
26429                                                                             field.*/
26430   #define GPIOTE_INTENSET2_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
26431   #define GPIOTE_INTENSET2_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
26432   #define GPIOTE_INTENSET2_PORT3NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26433   #define GPIOTE_INTENSET2_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26434   #define GPIOTE_INTENSET2_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26435 
26436 /* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */
26437   #define GPIOTE_INTENSET2_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
26438   #define GPIOTE_INTENSET2_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET2_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
26439   #define GPIOTE_INTENSET2_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
26440   #define GPIOTE_INTENSET2_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
26441   #define GPIOTE_INTENSET2_PORT3SECURE_Set (0x1UL)   /*!< Enable                                                               */
26442   #define GPIOTE_INTENSET2_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26443   #define GPIOTE_INTENSET2_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26444 
26445 
26446 /* GPIOTE_INTENCLR2: Disable interrupt */
26447   #define GPIOTE_INTENCLR2_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR2 register.                                   */
26448 
26449 /* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
26450   #define GPIOTE_INTENCLR2_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
26451   #define GPIOTE_INTENCLR2_IN0_Msk (0x1UL << GPIOTE_INTENCLR2_IN0_Pos) /*!< Bit mask of IN0 field.                             */
26452   #define GPIOTE_INTENCLR2_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
26453   #define GPIOTE_INTENCLR2_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
26454   #define GPIOTE_INTENCLR2_IN0_Clear (0x1UL)         /*!< Disable                                                              */
26455   #define GPIOTE_INTENCLR2_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26456   #define GPIOTE_INTENCLR2_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26457 
26458 /* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
26459   #define GPIOTE_INTENCLR2_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
26460   #define GPIOTE_INTENCLR2_IN1_Msk (0x1UL << GPIOTE_INTENCLR2_IN1_Pos) /*!< Bit mask of IN1 field.                             */
26461   #define GPIOTE_INTENCLR2_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
26462   #define GPIOTE_INTENCLR2_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
26463   #define GPIOTE_INTENCLR2_IN1_Clear (0x1UL)         /*!< Disable                                                              */
26464   #define GPIOTE_INTENCLR2_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26465   #define GPIOTE_INTENCLR2_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26466 
26467 /* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
26468   #define GPIOTE_INTENCLR2_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
26469   #define GPIOTE_INTENCLR2_IN2_Msk (0x1UL << GPIOTE_INTENCLR2_IN2_Pos) /*!< Bit mask of IN2 field.                             */
26470   #define GPIOTE_INTENCLR2_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
26471   #define GPIOTE_INTENCLR2_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
26472   #define GPIOTE_INTENCLR2_IN2_Clear (0x1UL)         /*!< Disable                                                              */
26473   #define GPIOTE_INTENCLR2_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26474   #define GPIOTE_INTENCLR2_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26475 
26476 /* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
26477   #define GPIOTE_INTENCLR2_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
26478   #define GPIOTE_INTENCLR2_IN3_Msk (0x1UL << GPIOTE_INTENCLR2_IN3_Pos) /*!< Bit mask of IN3 field.                             */
26479   #define GPIOTE_INTENCLR2_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
26480   #define GPIOTE_INTENCLR2_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
26481   #define GPIOTE_INTENCLR2_IN3_Clear (0x1UL)         /*!< Disable                                                              */
26482   #define GPIOTE_INTENCLR2_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26483   #define GPIOTE_INTENCLR2_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26484 
26485 /* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
26486   #define GPIOTE_INTENCLR2_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
26487   #define GPIOTE_INTENCLR2_IN4_Msk (0x1UL << GPIOTE_INTENCLR2_IN4_Pos) /*!< Bit mask of IN4 field.                             */
26488   #define GPIOTE_INTENCLR2_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
26489   #define GPIOTE_INTENCLR2_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
26490   #define GPIOTE_INTENCLR2_IN4_Clear (0x1UL)         /*!< Disable                                                              */
26491   #define GPIOTE_INTENCLR2_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26492   #define GPIOTE_INTENCLR2_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26493 
26494 /* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
26495   #define GPIOTE_INTENCLR2_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
26496   #define GPIOTE_INTENCLR2_IN5_Msk (0x1UL << GPIOTE_INTENCLR2_IN5_Pos) /*!< Bit mask of IN5 field.                             */
26497   #define GPIOTE_INTENCLR2_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
26498   #define GPIOTE_INTENCLR2_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
26499   #define GPIOTE_INTENCLR2_IN5_Clear (0x1UL)         /*!< Disable                                                              */
26500   #define GPIOTE_INTENCLR2_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26501   #define GPIOTE_INTENCLR2_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26502 
26503 /* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
26504   #define GPIOTE_INTENCLR2_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
26505   #define GPIOTE_INTENCLR2_IN6_Msk (0x1UL << GPIOTE_INTENCLR2_IN6_Pos) /*!< Bit mask of IN6 field.                             */
26506   #define GPIOTE_INTENCLR2_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
26507   #define GPIOTE_INTENCLR2_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
26508   #define GPIOTE_INTENCLR2_IN6_Clear (0x1UL)         /*!< Disable                                                              */
26509   #define GPIOTE_INTENCLR2_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26510   #define GPIOTE_INTENCLR2_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26511 
26512 /* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
26513   #define GPIOTE_INTENCLR2_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
26514   #define GPIOTE_INTENCLR2_IN7_Msk (0x1UL << GPIOTE_INTENCLR2_IN7_Pos) /*!< Bit mask of IN7 field.                             */
26515   #define GPIOTE_INTENCLR2_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
26516   #define GPIOTE_INTENCLR2_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
26517   #define GPIOTE_INTENCLR2_IN7_Clear (0x1UL)         /*!< Disable                                                              */
26518   #define GPIOTE_INTENCLR2_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26519   #define GPIOTE_INTENCLR2_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26520 
26521 /* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
26522   #define GPIOTE_INTENCLR2_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
26523   #define GPIOTE_INTENCLR2_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
26524                                                                             field.*/
26525   #define GPIOTE_INTENCLR2_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
26526   #define GPIOTE_INTENCLR2_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
26527   #define GPIOTE_INTENCLR2_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26528   #define GPIOTE_INTENCLR2_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26529   #define GPIOTE_INTENCLR2_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26530 
26531 /* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
26532   #define GPIOTE_INTENCLR2_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
26533   #define GPIOTE_INTENCLR2_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
26534   #define GPIOTE_INTENCLR2_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
26535   #define GPIOTE_INTENCLR2_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
26536   #define GPIOTE_INTENCLR2_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
26537   #define GPIOTE_INTENCLR2_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26538   #define GPIOTE_INTENCLR2_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26539 
26540 /* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */
26541   #define GPIOTE_INTENCLR2_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
26542   #define GPIOTE_INTENCLR2_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
26543                                                                             field.*/
26544   #define GPIOTE_INTENCLR2_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
26545   #define GPIOTE_INTENCLR2_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
26546   #define GPIOTE_INTENCLR2_PORT1NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26547   #define GPIOTE_INTENCLR2_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26548   #define GPIOTE_INTENCLR2_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26549 
26550 /* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */
26551   #define GPIOTE_INTENCLR2_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
26552   #define GPIOTE_INTENCLR2_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
26553   #define GPIOTE_INTENCLR2_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
26554   #define GPIOTE_INTENCLR2_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
26555   #define GPIOTE_INTENCLR2_PORT1SECURE_Clear (0x1UL) /*!< Disable                                                              */
26556   #define GPIOTE_INTENCLR2_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26557   #define GPIOTE_INTENCLR2_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26558 
26559 /* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */
26560   #define GPIOTE_INTENCLR2_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
26561   #define GPIOTE_INTENCLR2_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
26562                                                                             field.*/
26563   #define GPIOTE_INTENCLR2_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
26564   #define GPIOTE_INTENCLR2_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
26565   #define GPIOTE_INTENCLR2_PORT2NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26566   #define GPIOTE_INTENCLR2_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26567   #define GPIOTE_INTENCLR2_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26568 
26569 /* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */
26570   #define GPIOTE_INTENCLR2_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
26571   #define GPIOTE_INTENCLR2_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
26572   #define GPIOTE_INTENCLR2_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
26573   #define GPIOTE_INTENCLR2_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
26574   #define GPIOTE_INTENCLR2_PORT2SECURE_Clear (0x1UL) /*!< Disable                                                              */
26575   #define GPIOTE_INTENCLR2_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26576   #define GPIOTE_INTENCLR2_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26577 
26578 /* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */
26579   #define GPIOTE_INTENCLR2_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
26580   #define GPIOTE_INTENCLR2_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
26581                                                                             field.*/
26582   #define GPIOTE_INTENCLR2_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
26583   #define GPIOTE_INTENCLR2_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
26584   #define GPIOTE_INTENCLR2_PORT3NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26585   #define GPIOTE_INTENCLR2_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26586   #define GPIOTE_INTENCLR2_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26587 
26588 /* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */
26589   #define GPIOTE_INTENCLR2_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
26590   #define GPIOTE_INTENCLR2_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR2_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
26591   #define GPIOTE_INTENCLR2_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
26592   #define GPIOTE_INTENCLR2_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
26593   #define GPIOTE_INTENCLR2_PORT3SECURE_Clear (0x1UL) /*!< Disable                                                              */
26594   #define GPIOTE_INTENCLR2_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26595   #define GPIOTE_INTENCLR2_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26596 
26597 
26598 /* GPIOTE_INTENSET3: Enable interrupt */
26599   #define GPIOTE_INTENSET3_ResetValue (0x00000000UL) /*!< Reset value of INTENSET3 register.                                   */
26600 
26601 /* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
26602   #define GPIOTE_INTENSET3_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
26603   #define GPIOTE_INTENSET3_IN0_Msk (0x1UL << GPIOTE_INTENSET3_IN0_Pos) /*!< Bit mask of IN0 field.                             */
26604   #define GPIOTE_INTENSET3_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
26605   #define GPIOTE_INTENSET3_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
26606   #define GPIOTE_INTENSET3_IN0_Set (0x1UL)           /*!< Enable                                                               */
26607   #define GPIOTE_INTENSET3_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26608   #define GPIOTE_INTENSET3_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26609 
26610 /* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
26611   #define GPIOTE_INTENSET3_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
26612   #define GPIOTE_INTENSET3_IN1_Msk (0x1UL << GPIOTE_INTENSET3_IN1_Pos) /*!< Bit mask of IN1 field.                             */
26613   #define GPIOTE_INTENSET3_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
26614   #define GPIOTE_INTENSET3_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
26615   #define GPIOTE_INTENSET3_IN1_Set (0x1UL)           /*!< Enable                                                               */
26616   #define GPIOTE_INTENSET3_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26617   #define GPIOTE_INTENSET3_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26618 
26619 /* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
26620   #define GPIOTE_INTENSET3_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
26621   #define GPIOTE_INTENSET3_IN2_Msk (0x1UL << GPIOTE_INTENSET3_IN2_Pos) /*!< Bit mask of IN2 field.                             */
26622   #define GPIOTE_INTENSET3_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
26623   #define GPIOTE_INTENSET3_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
26624   #define GPIOTE_INTENSET3_IN2_Set (0x1UL)           /*!< Enable                                                               */
26625   #define GPIOTE_INTENSET3_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26626   #define GPIOTE_INTENSET3_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26627 
26628 /* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
26629   #define GPIOTE_INTENSET3_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
26630   #define GPIOTE_INTENSET3_IN3_Msk (0x1UL << GPIOTE_INTENSET3_IN3_Pos) /*!< Bit mask of IN3 field.                             */
26631   #define GPIOTE_INTENSET3_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
26632   #define GPIOTE_INTENSET3_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
26633   #define GPIOTE_INTENSET3_IN3_Set (0x1UL)           /*!< Enable                                                               */
26634   #define GPIOTE_INTENSET3_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26635   #define GPIOTE_INTENSET3_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26636 
26637 /* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
26638   #define GPIOTE_INTENSET3_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
26639   #define GPIOTE_INTENSET3_IN4_Msk (0x1UL << GPIOTE_INTENSET3_IN4_Pos) /*!< Bit mask of IN4 field.                             */
26640   #define GPIOTE_INTENSET3_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
26641   #define GPIOTE_INTENSET3_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
26642   #define GPIOTE_INTENSET3_IN4_Set (0x1UL)           /*!< Enable                                                               */
26643   #define GPIOTE_INTENSET3_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26644   #define GPIOTE_INTENSET3_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26645 
26646 /* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
26647   #define GPIOTE_INTENSET3_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
26648   #define GPIOTE_INTENSET3_IN5_Msk (0x1UL << GPIOTE_INTENSET3_IN5_Pos) /*!< Bit mask of IN5 field.                             */
26649   #define GPIOTE_INTENSET3_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
26650   #define GPIOTE_INTENSET3_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
26651   #define GPIOTE_INTENSET3_IN5_Set (0x1UL)           /*!< Enable                                                               */
26652   #define GPIOTE_INTENSET3_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26653   #define GPIOTE_INTENSET3_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26654 
26655 /* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
26656   #define GPIOTE_INTENSET3_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
26657   #define GPIOTE_INTENSET3_IN6_Msk (0x1UL << GPIOTE_INTENSET3_IN6_Pos) /*!< Bit mask of IN6 field.                             */
26658   #define GPIOTE_INTENSET3_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
26659   #define GPIOTE_INTENSET3_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
26660   #define GPIOTE_INTENSET3_IN6_Set (0x1UL)           /*!< Enable                                                               */
26661   #define GPIOTE_INTENSET3_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26662   #define GPIOTE_INTENSET3_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26663 
26664 /* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
26665   #define GPIOTE_INTENSET3_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
26666   #define GPIOTE_INTENSET3_IN7_Msk (0x1UL << GPIOTE_INTENSET3_IN7_Pos) /*!< Bit mask of IN7 field.                             */
26667   #define GPIOTE_INTENSET3_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
26668   #define GPIOTE_INTENSET3_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
26669   #define GPIOTE_INTENSET3_IN7_Set (0x1UL)           /*!< Enable                                                               */
26670   #define GPIOTE_INTENSET3_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26671   #define GPIOTE_INTENSET3_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26672 
26673 /* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
26674   #define GPIOTE_INTENSET3_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
26675   #define GPIOTE_INTENSET3_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
26676                                                                             field.*/
26677   #define GPIOTE_INTENSET3_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
26678   #define GPIOTE_INTENSET3_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
26679   #define GPIOTE_INTENSET3_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26680   #define GPIOTE_INTENSET3_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26681   #define GPIOTE_INTENSET3_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26682 
26683 /* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
26684   #define GPIOTE_INTENSET3_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
26685   #define GPIOTE_INTENSET3_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
26686   #define GPIOTE_INTENSET3_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
26687   #define GPIOTE_INTENSET3_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
26688   #define GPIOTE_INTENSET3_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
26689   #define GPIOTE_INTENSET3_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26690   #define GPIOTE_INTENSET3_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26691 
26692 /* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */
26693   #define GPIOTE_INTENSET3_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
26694   #define GPIOTE_INTENSET3_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
26695                                                                             field.*/
26696   #define GPIOTE_INTENSET3_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
26697   #define GPIOTE_INTENSET3_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
26698   #define GPIOTE_INTENSET3_PORT1NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26699   #define GPIOTE_INTENSET3_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26700   #define GPIOTE_INTENSET3_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26701 
26702 /* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */
26703   #define GPIOTE_INTENSET3_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
26704   #define GPIOTE_INTENSET3_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
26705   #define GPIOTE_INTENSET3_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
26706   #define GPIOTE_INTENSET3_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
26707   #define GPIOTE_INTENSET3_PORT1SECURE_Set (0x1UL)   /*!< Enable                                                               */
26708   #define GPIOTE_INTENSET3_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26709   #define GPIOTE_INTENSET3_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26710 
26711 /* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */
26712   #define GPIOTE_INTENSET3_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
26713   #define GPIOTE_INTENSET3_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
26714                                                                             field.*/
26715   #define GPIOTE_INTENSET3_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
26716   #define GPIOTE_INTENSET3_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
26717   #define GPIOTE_INTENSET3_PORT2NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26718   #define GPIOTE_INTENSET3_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26719   #define GPIOTE_INTENSET3_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26720 
26721 /* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */
26722   #define GPIOTE_INTENSET3_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
26723   #define GPIOTE_INTENSET3_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
26724   #define GPIOTE_INTENSET3_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
26725   #define GPIOTE_INTENSET3_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
26726   #define GPIOTE_INTENSET3_PORT2SECURE_Set (0x1UL)   /*!< Enable                                                               */
26727   #define GPIOTE_INTENSET3_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26728   #define GPIOTE_INTENSET3_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26729 
26730 /* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */
26731   #define GPIOTE_INTENSET3_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
26732   #define GPIOTE_INTENSET3_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
26733                                                                             field.*/
26734   #define GPIOTE_INTENSET3_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
26735   #define GPIOTE_INTENSET3_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
26736   #define GPIOTE_INTENSET3_PORT3NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26737   #define GPIOTE_INTENSET3_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26738   #define GPIOTE_INTENSET3_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26739 
26740 /* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */
26741   #define GPIOTE_INTENSET3_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
26742   #define GPIOTE_INTENSET3_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET3_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
26743   #define GPIOTE_INTENSET3_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
26744   #define GPIOTE_INTENSET3_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
26745   #define GPIOTE_INTENSET3_PORT3SECURE_Set (0x1UL)   /*!< Enable                                                               */
26746   #define GPIOTE_INTENSET3_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26747   #define GPIOTE_INTENSET3_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26748 
26749 
26750 /* GPIOTE_INTENCLR3: Disable interrupt */
26751   #define GPIOTE_INTENCLR3_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR3 register.                                   */
26752 
26753 /* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
26754   #define GPIOTE_INTENCLR3_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
26755   #define GPIOTE_INTENCLR3_IN0_Msk (0x1UL << GPIOTE_INTENCLR3_IN0_Pos) /*!< Bit mask of IN0 field.                             */
26756   #define GPIOTE_INTENCLR3_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
26757   #define GPIOTE_INTENCLR3_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
26758   #define GPIOTE_INTENCLR3_IN0_Clear (0x1UL)         /*!< Disable                                                              */
26759   #define GPIOTE_INTENCLR3_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26760   #define GPIOTE_INTENCLR3_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26761 
26762 /* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
26763   #define GPIOTE_INTENCLR3_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
26764   #define GPIOTE_INTENCLR3_IN1_Msk (0x1UL << GPIOTE_INTENCLR3_IN1_Pos) /*!< Bit mask of IN1 field.                             */
26765   #define GPIOTE_INTENCLR3_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
26766   #define GPIOTE_INTENCLR3_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
26767   #define GPIOTE_INTENCLR3_IN1_Clear (0x1UL)         /*!< Disable                                                              */
26768   #define GPIOTE_INTENCLR3_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26769   #define GPIOTE_INTENCLR3_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26770 
26771 /* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
26772   #define GPIOTE_INTENCLR3_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
26773   #define GPIOTE_INTENCLR3_IN2_Msk (0x1UL << GPIOTE_INTENCLR3_IN2_Pos) /*!< Bit mask of IN2 field.                             */
26774   #define GPIOTE_INTENCLR3_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
26775   #define GPIOTE_INTENCLR3_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
26776   #define GPIOTE_INTENCLR3_IN2_Clear (0x1UL)         /*!< Disable                                                              */
26777   #define GPIOTE_INTENCLR3_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26778   #define GPIOTE_INTENCLR3_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26779 
26780 /* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
26781   #define GPIOTE_INTENCLR3_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
26782   #define GPIOTE_INTENCLR3_IN3_Msk (0x1UL << GPIOTE_INTENCLR3_IN3_Pos) /*!< Bit mask of IN3 field.                             */
26783   #define GPIOTE_INTENCLR3_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
26784   #define GPIOTE_INTENCLR3_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
26785   #define GPIOTE_INTENCLR3_IN3_Clear (0x1UL)         /*!< Disable                                                              */
26786   #define GPIOTE_INTENCLR3_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26787   #define GPIOTE_INTENCLR3_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26788 
26789 /* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
26790   #define GPIOTE_INTENCLR3_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
26791   #define GPIOTE_INTENCLR3_IN4_Msk (0x1UL << GPIOTE_INTENCLR3_IN4_Pos) /*!< Bit mask of IN4 field.                             */
26792   #define GPIOTE_INTENCLR3_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
26793   #define GPIOTE_INTENCLR3_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
26794   #define GPIOTE_INTENCLR3_IN4_Clear (0x1UL)         /*!< Disable                                                              */
26795   #define GPIOTE_INTENCLR3_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26796   #define GPIOTE_INTENCLR3_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26797 
26798 /* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
26799   #define GPIOTE_INTENCLR3_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
26800   #define GPIOTE_INTENCLR3_IN5_Msk (0x1UL << GPIOTE_INTENCLR3_IN5_Pos) /*!< Bit mask of IN5 field.                             */
26801   #define GPIOTE_INTENCLR3_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
26802   #define GPIOTE_INTENCLR3_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
26803   #define GPIOTE_INTENCLR3_IN5_Clear (0x1UL)         /*!< Disable                                                              */
26804   #define GPIOTE_INTENCLR3_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26805   #define GPIOTE_INTENCLR3_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26806 
26807 /* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
26808   #define GPIOTE_INTENCLR3_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
26809   #define GPIOTE_INTENCLR3_IN6_Msk (0x1UL << GPIOTE_INTENCLR3_IN6_Pos) /*!< Bit mask of IN6 field.                             */
26810   #define GPIOTE_INTENCLR3_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
26811   #define GPIOTE_INTENCLR3_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
26812   #define GPIOTE_INTENCLR3_IN6_Clear (0x1UL)         /*!< Disable                                                              */
26813   #define GPIOTE_INTENCLR3_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26814   #define GPIOTE_INTENCLR3_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26815 
26816 /* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
26817   #define GPIOTE_INTENCLR3_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
26818   #define GPIOTE_INTENCLR3_IN7_Msk (0x1UL << GPIOTE_INTENCLR3_IN7_Pos) /*!< Bit mask of IN7 field.                             */
26819   #define GPIOTE_INTENCLR3_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
26820   #define GPIOTE_INTENCLR3_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
26821   #define GPIOTE_INTENCLR3_IN7_Clear (0x1UL)         /*!< Disable                                                              */
26822   #define GPIOTE_INTENCLR3_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26823   #define GPIOTE_INTENCLR3_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26824 
26825 /* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
26826   #define GPIOTE_INTENCLR3_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
26827   #define GPIOTE_INTENCLR3_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
26828                                                                             field.*/
26829   #define GPIOTE_INTENCLR3_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
26830   #define GPIOTE_INTENCLR3_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
26831   #define GPIOTE_INTENCLR3_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26832   #define GPIOTE_INTENCLR3_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26833   #define GPIOTE_INTENCLR3_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26834 
26835 /* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
26836   #define GPIOTE_INTENCLR3_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
26837   #define GPIOTE_INTENCLR3_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
26838   #define GPIOTE_INTENCLR3_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
26839   #define GPIOTE_INTENCLR3_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
26840   #define GPIOTE_INTENCLR3_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
26841   #define GPIOTE_INTENCLR3_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26842   #define GPIOTE_INTENCLR3_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26843 
26844 /* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */
26845   #define GPIOTE_INTENCLR3_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
26846   #define GPIOTE_INTENCLR3_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
26847                                                                             field.*/
26848   #define GPIOTE_INTENCLR3_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
26849   #define GPIOTE_INTENCLR3_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
26850   #define GPIOTE_INTENCLR3_PORT1NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26851   #define GPIOTE_INTENCLR3_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26852   #define GPIOTE_INTENCLR3_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26853 
26854 /* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */
26855   #define GPIOTE_INTENCLR3_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
26856   #define GPIOTE_INTENCLR3_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
26857   #define GPIOTE_INTENCLR3_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
26858   #define GPIOTE_INTENCLR3_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
26859   #define GPIOTE_INTENCLR3_PORT1SECURE_Clear (0x1UL) /*!< Disable                                                              */
26860   #define GPIOTE_INTENCLR3_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26861   #define GPIOTE_INTENCLR3_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26862 
26863 /* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */
26864   #define GPIOTE_INTENCLR3_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
26865   #define GPIOTE_INTENCLR3_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
26866                                                                             field.*/
26867   #define GPIOTE_INTENCLR3_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
26868   #define GPIOTE_INTENCLR3_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
26869   #define GPIOTE_INTENCLR3_PORT2NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26870   #define GPIOTE_INTENCLR3_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26871   #define GPIOTE_INTENCLR3_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26872 
26873 /* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */
26874   #define GPIOTE_INTENCLR3_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
26875   #define GPIOTE_INTENCLR3_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
26876   #define GPIOTE_INTENCLR3_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
26877   #define GPIOTE_INTENCLR3_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
26878   #define GPIOTE_INTENCLR3_PORT2SECURE_Clear (0x1UL) /*!< Disable                                                              */
26879   #define GPIOTE_INTENCLR3_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26880   #define GPIOTE_INTENCLR3_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26881 
26882 /* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */
26883   #define GPIOTE_INTENCLR3_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
26884   #define GPIOTE_INTENCLR3_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
26885                                                                             field.*/
26886   #define GPIOTE_INTENCLR3_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
26887   #define GPIOTE_INTENCLR3_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
26888   #define GPIOTE_INTENCLR3_PORT3NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
26889   #define GPIOTE_INTENCLR3_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26890   #define GPIOTE_INTENCLR3_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26891 
26892 /* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */
26893   #define GPIOTE_INTENCLR3_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
26894   #define GPIOTE_INTENCLR3_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR3_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
26895   #define GPIOTE_INTENCLR3_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
26896   #define GPIOTE_INTENCLR3_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
26897   #define GPIOTE_INTENCLR3_PORT3SECURE_Clear (0x1UL) /*!< Disable                                                              */
26898   #define GPIOTE_INTENCLR3_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26899   #define GPIOTE_INTENCLR3_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26900 
26901 
26902 /* GPIOTE_INTENSET4: Enable interrupt */
26903   #define GPIOTE_INTENSET4_ResetValue (0x00000000UL) /*!< Reset value of INTENSET4 register.                                   */
26904 
26905 /* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
26906   #define GPIOTE_INTENSET4_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
26907   #define GPIOTE_INTENSET4_IN0_Msk (0x1UL << GPIOTE_INTENSET4_IN0_Pos) /*!< Bit mask of IN0 field.                             */
26908   #define GPIOTE_INTENSET4_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
26909   #define GPIOTE_INTENSET4_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
26910   #define GPIOTE_INTENSET4_IN0_Set (0x1UL)           /*!< Enable                                                               */
26911   #define GPIOTE_INTENSET4_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26912   #define GPIOTE_INTENSET4_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26913 
26914 /* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
26915   #define GPIOTE_INTENSET4_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
26916   #define GPIOTE_INTENSET4_IN1_Msk (0x1UL << GPIOTE_INTENSET4_IN1_Pos) /*!< Bit mask of IN1 field.                             */
26917   #define GPIOTE_INTENSET4_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
26918   #define GPIOTE_INTENSET4_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
26919   #define GPIOTE_INTENSET4_IN1_Set (0x1UL)           /*!< Enable                                                               */
26920   #define GPIOTE_INTENSET4_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26921   #define GPIOTE_INTENSET4_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26922 
26923 /* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
26924   #define GPIOTE_INTENSET4_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
26925   #define GPIOTE_INTENSET4_IN2_Msk (0x1UL << GPIOTE_INTENSET4_IN2_Pos) /*!< Bit mask of IN2 field.                             */
26926   #define GPIOTE_INTENSET4_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
26927   #define GPIOTE_INTENSET4_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
26928   #define GPIOTE_INTENSET4_IN2_Set (0x1UL)           /*!< Enable                                                               */
26929   #define GPIOTE_INTENSET4_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26930   #define GPIOTE_INTENSET4_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26931 
26932 /* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
26933   #define GPIOTE_INTENSET4_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
26934   #define GPIOTE_INTENSET4_IN3_Msk (0x1UL << GPIOTE_INTENSET4_IN3_Pos) /*!< Bit mask of IN3 field.                             */
26935   #define GPIOTE_INTENSET4_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
26936   #define GPIOTE_INTENSET4_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
26937   #define GPIOTE_INTENSET4_IN3_Set (0x1UL)           /*!< Enable                                                               */
26938   #define GPIOTE_INTENSET4_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26939   #define GPIOTE_INTENSET4_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26940 
26941 /* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
26942   #define GPIOTE_INTENSET4_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
26943   #define GPIOTE_INTENSET4_IN4_Msk (0x1UL << GPIOTE_INTENSET4_IN4_Pos) /*!< Bit mask of IN4 field.                             */
26944   #define GPIOTE_INTENSET4_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
26945   #define GPIOTE_INTENSET4_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
26946   #define GPIOTE_INTENSET4_IN4_Set (0x1UL)           /*!< Enable                                                               */
26947   #define GPIOTE_INTENSET4_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26948   #define GPIOTE_INTENSET4_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26949 
26950 /* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
26951   #define GPIOTE_INTENSET4_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
26952   #define GPIOTE_INTENSET4_IN5_Msk (0x1UL << GPIOTE_INTENSET4_IN5_Pos) /*!< Bit mask of IN5 field.                             */
26953   #define GPIOTE_INTENSET4_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
26954   #define GPIOTE_INTENSET4_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
26955   #define GPIOTE_INTENSET4_IN5_Set (0x1UL)           /*!< Enable                                                               */
26956   #define GPIOTE_INTENSET4_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26957   #define GPIOTE_INTENSET4_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26958 
26959 /* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
26960   #define GPIOTE_INTENSET4_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
26961   #define GPIOTE_INTENSET4_IN6_Msk (0x1UL << GPIOTE_INTENSET4_IN6_Pos) /*!< Bit mask of IN6 field.                             */
26962   #define GPIOTE_INTENSET4_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
26963   #define GPIOTE_INTENSET4_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
26964   #define GPIOTE_INTENSET4_IN6_Set (0x1UL)           /*!< Enable                                                               */
26965   #define GPIOTE_INTENSET4_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26966   #define GPIOTE_INTENSET4_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26967 
26968 /* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
26969   #define GPIOTE_INTENSET4_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
26970   #define GPIOTE_INTENSET4_IN7_Msk (0x1UL << GPIOTE_INTENSET4_IN7_Pos) /*!< Bit mask of IN7 field.                             */
26971   #define GPIOTE_INTENSET4_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
26972   #define GPIOTE_INTENSET4_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
26973   #define GPIOTE_INTENSET4_IN7_Set (0x1UL)           /*!< Enable                                                               */
26974   #define GPIOTE_INTENSET4_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
26975   #define GPIOTE_INTENSET4_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
26976 
26977 /* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
26978   #define GPIOTE_INTENSET4_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
26979   #define GPIOTE_INTENSET4_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
26980                                                                             field.*/
26981   #define GPIOTE_INTENSET4_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
26982   #define GPIOTE_INTENSET4_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
26983   #define GPIOTE_INTENSET4_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
26984   #define GPIOTE_INTENSET4_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
26985   #define GPIOTE_INTENSET4_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
26986 
26987 /* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
26988   #define GPIOTE_INTENSET4_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
26989   #define GPIOTE_INTENSET4_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
26990   #define GPIOTE_INTENSET4_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
26991   #define GPIOTE_INTENSET4_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
26992   #define GPIOTE_INTENSET4_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
26993   #define GPIOTE_INTENSET4_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
26994   #define GPIOTE_INTENSET4_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
26995 
26996 /* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */
26997   #define GPIOTE_INTENSET4_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
26998   #define GPIOTE_INTENSET4_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
26999                                                                             field.*/
27000   #define GPIOTE_INTENSET4_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
27001   #define GPIOTE_INTENSET4_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
27002   #define GPIOTE_INTENSET4_PORT1NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27003   #define GPIOTE_INTENSET4_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27004   #define GPIOTE_INTENSET4_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27005 
27006 /* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */
27007   #define GPIOTE_INTENSET4_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
27008   #define GPIOTE_INTENSET4_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
27009   #define GPIOTE_INTENSET4_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
27010   #define GPIOTE_INTENSET4_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
27011   #define GPIOTE_INTENSET4_PORT1SECURE_Set (0x1UL)   /*!< Enable                                                               */
27012   #define GPIOTE_INTENSET4_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27013   #define GPIOTE_INTENSET4_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27014 
27015 /* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */
27016   #define GPIOTE_INTENSET4_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
27017   #define GPIOTE_INTENSET4_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
27018                                                                             field.*/
27019   #define GPIOTE_INTENSET4_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
27020   #define GPIOTE_INTENSET4_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
27021   #define GPIOTE_INTENSET4_PORT2NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27022   #define GPIOTE_INTENSET4_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27023   #define GPIOTE_INTENSET4_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27024 
27025 /* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */
27026   #define GPIOTE_INTENSET4_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
27027   #define GPIOTE_INTENSET4_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
27028   #define GPIOTE_INTENSET4_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
27029   #define GPIOTE_INTENSET4_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
27030   #define GPIOTE_INTENSET4_PORT2SECURE_Set (0x1UL)   /*!< Enable                                                               */
27031   #define GPIOTE_INTENSET4_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27032   #define GPIOTE_INTENSET4_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27033 
27034 /* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */
27035   #define GPIOTE_INTENSET4_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
27036   #define GPIOTE_INTENSET4_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
27037                                                                             field.*/
27038   #define GPIOTE_INTENSET4_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
27039   #define GPIOTE_INTENSET4_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
27040   #define GPIOTE_INTENSET4_PORT3NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27041   #define GPIOTE_INTENSET4_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27042   #define GPIOTE_INTENSET4_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27043 
27044 /* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */
27045   #define GPIOTE_INTENSET4_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
27046   #define GPIOTE_INTENSET4_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET4_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
27047   #define GPIOTE_INTENSET4_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
27048   #define GPIOTE_INTENSET4_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
27049   #define GPIOTE_INTENSET4_PORT3SECURE_Set (0x1UL)   /*!< Enable                                                               */
27050   #define GPIOTE_INTENSET4_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27051   #define GPIOTE_INTENSET4_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27052 
27053 
27054 /* GPIOTE_INTENCLR4: Disable interrupt */
27055   #define GPIOTE_INTENCLR4_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR4 register.                                   */
27056 
27057 /* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
27058   #define GPIOTE_INTENCLR4_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
27059   #define GPIOTE_INTENCLR4_IN0_Msk (0x1UL << GPIOTE_INTENCLR4_IN0_Pos) /*!< Bit mask of IN0 field.                             */
27060   #define GPIOTE_INTENCLR4_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
27061   #define GPIOTE_INTENCLR4_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
27062   #define GPIOTE_INTENCLR4_IN0_Clear (0x1UL)         /*!< Disable                                                              */
27063   #define GPIOTE_INTENCLR4_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27064   #define GPIOTE_INTENCLR4_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27065 
27066 /* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
27067   #define GPIOTE_INTENCLR4_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
27068   #define GPIOTE_INTENCLR4_IN1_Msk (0x1UL << GPIOTE_INTENCLR4_IN1_Pos) /*!< Bit mask of IN1 field.                             */
27069   #define GPIOTE_INTENCLR4_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
27070   #define GPIOTE_INTENCLR4_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
27071   #define GPIOTE_INTENCLR4_IN1_Clear (0x1UL)         /*!< Disable                                                              */
27072   #define GPIOTE_INTENCLR4_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27073   #define GPIOTE_INTENCLR4_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27074 
27075 /* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
27076   #define GPIOTE_INTENCLR4_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
27077   #define GPIOTE_INTENCLR4_IN2_Msk (0x1UL << GPIOTE_INTENCLR4_IN2_Pos) /*!< Bit mask of IN2 field.                             */
27078   #define GPIOTE_INTENCLR4_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
27079   #define GPIOTE_INTENCLR4_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
27080   #define GPIOTE_INTENCLR4_IN2_Clear (0x1UL)         /*!< Disable                                                              */
27081   #define GPIOTE_INTENCLR4_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27082   #define GPIOTE_INTENCLR4_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27083 
27084 /* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
27085   #define GPIOTE_INTENCLR4_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
27086   #define GPIOTE_INTENCLR4_IN3_Msk (0x1UL << GPIOTE_INTENCLR4_IN3_Pos) /*!< Bit mask of IN3 field.                             */
27087   #define GPIOTE_INTENCLR4_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
27088   #define GPIOTE_INTENCLR4_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
27089   #define GPIOTE_INTENCLR4_IN3_Clear (0x1UL)         /*!< Disable                                                              */
27090   #define GPIOTE_INTENCLR4_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27091   #define GPIOTE_INTENCLR4_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27092 
27093 /* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
27094   #define GPIOTE_INTENCLR4_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
27095   #define GPIOTE_INTENCLR4_IN4_Msk (0x1UL << GPIOTE_INTENCLR4_IN4_Pos) /*!< Bit mask of IN4 field.                             */
27096   #define GPIOTE_INTENCLR4_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
27097   #define GPIOTE_INTENCLR4_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
27098   #define GPIOTE_INTENCLR4_IN4_Clear (0x1UL)         /*!< Disable                                                              */
27099   #define GPIOTE_INTENCLR4_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27100   #define GPIOTE_INTENCLR4_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27101 
27102 /* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
27103   #define GPIOTE_INTENCLR4_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
27104   #define GPIOTE_INTENCLR4_IN5_Msk (0x1UL << GPIOTE_INTENCLR4_IN5_Pos) /*!< Bit mask of IN5 field.                             */
27105   #define GPIOTE_INTENCLR4_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
27106   #define GPIOTE_INTENCLR4_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
27107   #define GPIOTE_INTENCLR4_IN5_Clear (0x1UL)         /*!< Disable                                                              */
27108   #define GPIOTE_INTENCLR4_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27109   #define GPIOTE_INTENCLR4_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27110 
27111 /* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
27112   #define GPIOTE_INTENCLR4_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
27113   #define GPIOTE_INTENCLR4_IN6_Msk (0x1UL << GPIOTE_INTENCLR4_IN6_Pos) /*!< Bit mask of IN6 field.                             */
27114   #define GPIOTE_INTENCLR4_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
27115   #define GPIOTE_INTENCLR4_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
27116   #define GPIOTE_INTENCLR4_IN6_Clear (0x1UL)         /*!< Disable                                                              */
27117   #define GPIOTE_INTENCLR4_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27118   #define GPIOTE_INTENCLR4_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27119 
27120 /* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
27121   #define GPIOTE_INTENCLR4_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
27122   #define GPIOTE_INTENCLR4_IN7_Msk (0x1UL << GPIOTE_INTENCLR4_IN7_Pos) /*!< Bit mask of IN7 field.                             */
27123   #define GPIOTE_INTENCLR4_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
27124   #define GPIOTE_INTENCLR4_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
27125   #define GPIOTE_INTENCLR4_IN7_Clear (0x1UL)         /*!< Disable                                                              */
27126   #define GPIOTE_INTENCLR4_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27127   #define GPIOTE_INTENCLR4_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27128 
27129 /* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
27130   #define GPIOTE_INTENCLR4_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
27131   #define GPIOTE_INTENCLR4_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
27132                                                                             field.*/
27133   #define GPIOTE_INTENCLR4_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
27134   #define GPIOTE_INTENCLR4_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
27135   #define GPIOTE_INTENCLR4_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27136   #define GPIOTE_INTENCLR4_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27137   #define GPIOTE_INTENCLR4_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27138 
27139 /* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
27140   #define GPIOTE_INTENCLR4_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
27141   #define GPIOTE_INTENCLR4_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
27142   #define GPIOTE_INTENCLR4_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
27143   #define GPIOTE_INTENCLR4_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
27144   #define GPIOTE_INTENCLR4_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
27145   #define GPIOTE_INTENCLR4_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27146   #define GPIOTE_INTENCLR4_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27147 
27148 /* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */
27149   #define GPIOTE_INTENCLR4_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
27150   #define GPIOTE_INTENCLR4_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
27151                                                                             field.*/
27152   #define GPIOTE_INTENCLR4_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
27153   #define GPIOTE_INTENCLR4_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
27154   #define GPIOTE_INTENCLR4_PORT1NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27155   #define GPIOTE_INTENCLR4_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27156   #define GPIOTE_INTENCLR4_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27157 
27158 /* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */
27159   #define GPIOTE_INTENCLR4_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
27160   #define GPIOTE_INTENCLR4_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
27161   #define GPIOTE_INTENCLR4_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
27162   #define GPIOTE_INTENCLR4_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
27163   #define GPIOTE_INTENCLR4_PORT1SECURE_Clear (0x1UL) /*!< Disable                                                              */
27164   #define GPIOTE_INTENCLR4_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27165   #define GPIOTE_INTENCLR4_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27166 
27167 /* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */
27168   #define GPIOTE_INTENCLR4_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
27169   #define GPIOTE_INTENCLR4_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
27170                                                                             field.*/
27171   #define GPIOTE_INTENCLR4_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
27172   #define GPIOTE_INTENCLR4_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
27173   #define GPIOTE_INTENCLR4_PORT2NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27174   #define GPIOTE_INTENCLR4_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27175   #define GPIOTE_INTENCLR4_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27176 
27177 /* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */
27178   #define GPIOTE_INTENCLR4_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
27179   #define GPIOTE_INTENCLR4_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
27180   #define GPIOTE_INTENCLR4_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
27181   #define GPIOTE_INTENCLR4_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
27182   #define GPIOTE_INTENCLR4_PORT2SECURE_Clear (0x1UL) /*!< Disable                                                              */
27183   #define GPIOTE_INTENCLR4_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27184   #define GPIOTE_INTENCLR4_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27185 
27186 /* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */
27187   #define GPIOTE_INTENCLR4_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
27188   #define GPIOTE_INTENCLR4_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
27189                                                                             field.*/
27190   #define GPIOTE_INTENCLR4_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
27191   #define GPIOTE_INTENCLR4_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
27192   #define GPIOTE_INTENCLR4_PORT3NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27193   #define GPIOTE_INTENCLR4_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27194   #define GPIOTE_INTENCLR4_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27195 
27196 /* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */
27197   #define GPIOTE_INTENCLR4_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
27198   #define GPIOTE_INTENCLR4_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR4_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
27199   #define GPIOTE_INTENCLR4_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
27200   #define GPIOTE_INTENCLR4_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
27201   #define GPIOTE_INTENCLR4_PORT3SECURE_Clear (0x1UL) /*!< Disable                                                              */
27202   #define GPIOTE_INTENCLR4_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27203   #define GPIOTE_INTENCLR4_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27204 
27205 
27206 /* GPIOTE_INTENSET5: Enable interrupt */
27207   #define GPIOTE_INTENSET5_ResetValue (0x00000000UL) /*!< Reset value of INTENSET5 register.                                   */
27208 
27209 /* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
27210   #define GPIOTE_INTENSET5_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
27211   #define GPIOTE_INTENSET5_IN0_Msk (0x1UL << GPIOTE_INTENSET5_IN0_Pos) /*!< Bit mask of IN0 field.                             */
27212   #define GPIOTE_INTENSET5_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
27213   #define GPIOTE_INTENSET5_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
27214   #define GPIOTE_INTENSET5_IN0_Set (0x1UL)           /*!< Enable                                                               */
27215   #define GPIOTE_INTENSET5_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27216   #define GPIOTE_INTENSET5_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27217 
27218 /* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
27219   #define GPIOTE_INTENSET5_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
27220   #define GPIOTE_INTENSET5_IN1_Msk (0x1UL << GPIOTE_INTENSET5_IN1_Pos) /*!< Bit mask of IN1 field.                             */
27221   #define GPIOTE_INTENSET5_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
27222   #define GPIOTE_INTENSET5_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
27223   #define GPIOTE_INTENSET5_IN1_Set (0x1UL)           /*!< Enable                                                               */
27224   #define GPIOTE_INTENSET5_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27225   #define GPIOTE_INTENSET5_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27226 
27227 /* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
27228   #define GPIOTE_INTENSET5_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
27229   #define GPIOTE_INTENSET5_IN2_Msk (0x1UL << GPIOTE_INTENSET5_IN2_Pos) /*!< Bit mask of IN2 field.                             */
27230   #define GPIOTE_INTENSET5_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
27231   #define GPIOTE_INTENSET5_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
27232   #define GPIOTE_INTENSET5_IN2_Set (0x1UL)           /*!< Enable                                                               */
27233   #define GPIOTE_INTENSET5_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27234   #define GPIOTE_INTENSET5_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27235 
27236 /* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
27237   #define GPIOTE_INTENSET5_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
27238   #define GPIOTE_INTENSET5_IN3_Msk (0x1UL << GPIOTE_INTENSET5_IN3_Pos) /*!< Bit mask of IN3 field.                             */
27239   #define GPIOTE_INTENSET5_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
27240   #define GPIOTE_INTENSET5_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
27241   #define GPIOTE_INTENSET5_IN3_Set (0x1UL)           /*!< Enable                                                               */
27242   #define GPIOTE_INTENSET5_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27243   #define GPIOTE_INTENSET5_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27244 
27245 /* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
27246   #define GPIOTE_INTENSET5_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
27247   #define GPIOTE_INTENSET5_IN4_Msk (0x1UL << GPIOTE_INTENSET5_IN4_Pos) /*!< Bit mask of IN4 field.                             */
27248   #define GPIOTE_INTENSET5_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
27249   #define GPIOTE_INTENSET5_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
27250   #define GPIOTE_INTENSET5_IN4_Set (0x1UL)           /*!< Enable                                                               */
27251   #define GPIOTE_INTENSET5_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27252   #define GPIOTE_INTENSET5_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27253 
27254 /* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
27255   #define GPIOTE_INTENSET5_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
27256   #define GPIOTE_INTENSET5_IN5_Msk (0x1UL << GPIOTE_INTENSET5_IN5_Pos) /*!< Bit mask of IN5 field.                             */
27257   #define GPIOTE_INTENSET5_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
27258   #define GPIOTE_INTENSET5_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
27259   #define GPIOTE_INTENSET5_IN5_Set (0x1UL)           /*!< Enable                                                               */
27260   #define GPIOTE_INTENSET5_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27261   #define GPIOTE_INTENSET5_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27262 
27263 /* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
27264   #define GPIOTE_INTENSET5_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
27265   #define GPIOTE_INTENSET5_IN6_Msk (0x1UL << GPIOTE_INTENSET5_IN6_Pos) /*!< Bit mask of IN6 field.                             */
27266   #define GPIOTE_INTENSET5_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
27267   #define GPIOTE_INTENSET5_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
27268   #define GPIOTE_INTENSET5_IN6_Set (0x1UL)           /*!< Enable                                                               */
27269   #define GPIOTE_INTENSET5_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27270   #define GPIOTE_INTENSET5_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27271 
27272 /* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
27273   #define GPIOTE_INTENSET5_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
27274   #define GPIOTE_INTENSET5_IN7_Msk (0x1UL << GPIOTE_INTENSET5_IN7_Pos) /*!< Bit mask of IN7 field.                             */
27275   #define GPIOTE_INTENSET5_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
27276   #define GPIOTE_INTENSET5_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
27277   #define GPIOTE_INTENSET5_IN7_Set (0x1UL)           /*!< Enable                                                               */
27278   #define GPIOTE_INTENSET5_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27279   #define GPIOTE_INTENSET5_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27280 
27281 /* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
27282   #define GPIOTE_INTENSET5_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
27283   #define GPIOTE_INTENSET5_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
27284                                                                             field.*/
27285   #define GPIOTE_INTENSET5_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
27286   #define GPIOTE_INTENSET5_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
27287   #define GPIOTE_INTENSET5_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27288   #define GPIOTE_INTENSET5_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27289   #define GPIOTE_INTENSET5_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27290 
27291 /* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
27292   #define GPIOTE_INTENSET5_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
27293   #define GPIOTE_INTENSET5_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
27294   #define GPIOTE_INTENSET5_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
27295   #define GPIOTE_INTENSET5_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
27296   #define GPIOTE_INTENSET5_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
27297   #define GPIOTE_INTENSET5_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27298   #define GPIOTE_INTENSET5_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27299 
27300 /* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */
27301   #define GPIOTE_INTENSET5_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
27302   #define GPIOTE_INTENSET5_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
27303                                                                             field.*/
27304   #define GPIOTE_INTENSET5_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
27305   #define GPIOTE_INTENSET5_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
27306   #define GPIOTE_INTENSET5_PORT1NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27307   #define GPIOTE_INTENSET5_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27308   #define GPIOTE_INTENSET5_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27309 
27310 /* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */
27311   #define GPIOTE_INTENSET5_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
27312   #define GPIOTE_INTENSET5_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
27313   #define GPIOTE_INTENSET5_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
27314   #define GPIOTE_INTENSET5_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
27315   #define GPIOTE_INTENSET5_PORT1SECURE_Set (0x1UL)   /*!< Enable                                                               */
27316   #define GPIOTE_INTENSET5_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27317   #define GPIOTE_INTENSET5_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27318 
27319 /* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */
27320   #define GPIOTE_INTENSET5_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
27321   #define GPIOTE_INTENSET5_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
27322                                                                             field.*/
27323   #define GPIOTE_INTENSET5_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
27324   #define GPIOTE_INTENSET5_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
27325   #define GPIOTE_INTENSET5_PORT2NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27326   #define GPIOTE_INTENSET5_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27327   #define GPIOTE_INTENSET5_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27328 
27329 /* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */
27330   #define GPIOTE_INTENSET5_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
27331   #define GPIOTE_INTENSET5_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
27332   #define GPIOTE_INTENSET5_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
27333   #define GPIOTE_INTENSET5_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
27334   #define GPIOTE_INTENSET5_PORT2SECURE_Set (0x1UL)   /*!< Enable                                                               */
27335   #define GPIOTE_INTENSET5_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27336   #define GPIOTE_INTENSET5_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27337 
27338 /* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */
27339   #define GPIOTE_INTENSET5_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
27340   #define GPIOTE_INTENSET5_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
27341                                                                             field.*/
27342   #define GPIOTE_INTENSET5_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
27343   #define GPIOTE_INTENSET5_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
27344   #define GPIOTE_INTENSET5_PORT3NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27345   #define GPIOTE_INTENSET5_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27346   #define GPIOTE_INTENSET5_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27347 
27348 /* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */
27349   #define GPIOTE_INTENSET5_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
27350   #define GPIOTE_INTENSET5_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET5_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
27351   #define GPIOTE_INTENSET5_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
27352   #define GPIOTE_INTENSET5_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
27353   #define GPIOTE_INTENSET5_PORT3SECURE_Set (0x1UL)   /*!< Enable                                                               */
27354   #define GPIOTE_INTENSET5_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27355   #define GPIOTE_INTENSET5_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27356 
27357 
27358 /* GPIOTE_INTENCLR5: Disable interrupt */
27359   #define GPIOTE_INTENCLR5_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR5 register.                                   */
27360 
27361 /* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
27362   #define GPIOTE_INTENCLR5_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
27363   #define GPIOTE_INTENCLR5_IN0_Msk (0x1UL << GPIOTE_INTENCLR5_IN0_Pos) /*!< Bit mask of IN0 field.                             */
27364   #define GPIOTE_INTENCLR5_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
27365   #define GPIOTE_INTENCLR5_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
27366   #define GPIOTE_INTENCLR5_IN0_Clear (0x1UL)         /*!< Disable                                                              */
27367   #define GPIOTE_INTENCLR5_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27368   #define GPIOTE_INTENCLR5_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27369 
27370 /* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
27371   #define GPIOTE_INTENCLR5_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
27372   #define GPIOTE_INTENCLR5_IN1_Msk (0x1UL << GPIOTE_INTENCLR5_IN1_Pos) /*!< Bit mask of IN1 field.                             */
27373   #define GPIOTE_INTENCLR5_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
27374   #define GPIOTE_INTENCLR5_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
27375   #define GPIOTE_INTENCLR5_IN1_Clear (0x1UL)         /*!< Disable                                                              */
27376   #define GPIOTE_INTENCLR5_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27377   #define GPIOTE_INTENCLR5_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27378 
27379 /* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
27380   #define GPIOTE_INTENCLR5_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
27381   #define GPIOTE_INTENCLR5_IN2_Msk (0x1UL << GPIOTE_INTENCLR5_IN2_Pos) /*!< Bit mask of IN2 field.                             */
27382   #define GPIOTE_INTENCLR5_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
27383   #define GPIOTE_INTENCLR5_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
27384   #define GPIOTE_INTENCLR5_IN2_Clear (0x1UL)         /*!< Disable                                                              */
27385   #define GPIOTE_INTENCLR5_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27386   #define GPIOTE_INTENCLR5_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27387 
27388 /* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
27389   #define GPIOTE_INTENCLR5_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
27390   #define GPIOTE_INTENCLR5_IN3_Msk (0x1UL << GPIOTE_INTENCLR5_IN3_Pos) /*!< Bit mask of IN3 field.                             */
27391   #define GPIOTE_INTENCLR5_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
27392   #define GPIOTE_INTENCLR5_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
27393   #define GPIOTE_INTENCLR5_IN3_Clear (0x1UL)         /*!< Disable                                                              */
27394   #define GPIOTE_INTENCLR5_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27395   #define GPIOTE_INTENCLR5_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27396 
27397 /* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
27398   #define GPIOTE_INTENCLR5_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
27399   #define GPIOTE_INTENCLR5_IN4_Msk (0x1UL << GPIOTE_INTENCLR5_IN4_Pos) /*!< Bit mask of IN4 field.                             */
27400   #define GPIOTE_INTENCLR5_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
27401   #define GPIOTE_INTENCLR5_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
27402   #define GPIOTE_INTENCLR5_IN4_Clear (0x1UL)         /*!< Disable                                                              */
27403   #define GPIOTE_INTENCLR5_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27404   #define GPIOTE_INTENCLR5_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27405 
27406 /* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
27407   #define GPIOTE_INTENCLR5_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
27408   #define GPIOTE_INTENCLR5_IN5_Msk (0x1UL << GPIOTE_INTENCLR5_IN5_Pos) /*!< Bit mask of IN5 field.                             */
27409   #define GPIOTE_INTENCLR5_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
27410   #define GPIOTE_INTENCLR5_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
27411   #define GPIOTE_INTENCLR5_IN5_Clear (0x1UL)         /*!< Disable                                                              */
27412   #define GPIOTE_INTENCLR5_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27413   #define GPIOTE_INTENCLR5_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27414 
27415 /* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
27416   #define GPIOTE_INTENCLR5_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
27417   #define GPIOTE_INTENCLR5_IN6_Msk (0x1UL << GPIOTE_INTENCLR5_IN6_Pos) /*!< Bit mask of IN6 field.                             */
27418   #define GPIOTE_INTENCLR5_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
27419   #define GPIOTE_INTENCLR5_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
27420   #define GPIOTE_INTENCLR5_IN6_Clear (0x1UL)         /*!< Disable                                                              */
27421   #define GPIOTE_INTENCLR5_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27422   #define GPIOTE_INTENCLR5_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27423 
27424 /* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
27425   #define GPIOTE_INTENCLR5_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
27426   #define GPIOTE_INTENCLR5_IN7_Msk (0x1UL << GPIOTE_INTENCLR5_IN7_Pos) /*!< Bit mask of IN7 field.                             */
27427   #define GPIOTE_INTENCLR5_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
27428   #define GPIOTE_INTENCLR5_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
27429   #define GPIOTE_INTENCLR5_IN7_Clear (0x1UL)         /*!< Disable                                                              */
27430   #define GPIOTE_INTENCLR5_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27431   #define GPIOTE_INTENCLR5_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27432 
27433 /* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
27434   #define GPIOTE_INTENCLR5_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
27435   #define GPIOTE_INTENCLR5_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
27436                                                                             field.*/
27437   #define GPIOTE_INTENCLR5_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
27438   #define GPIOTE_INTENCLR5_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
27439   #define GPIOTE_INTENCLR5_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27440   #define GPIOTE_INTENCLR5_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27441   #define GPIOTE_INTENCLR5_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27442 
27443 /* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
27444   #define GPIOTE_INTENCLR5_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
27445   #define GPIOTE_INTENCLR5_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
27446   #define GPIOTE_INTENCLR5_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
27447   #define GPIOTE_INTENCLR5_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
27448   #define GPIOTE_INTENCLR5_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
27449   #define GPIOTE_INTENCLR5_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27450   #define GPIOTE_INTENCLR5_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27451 
27452 /* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */
27453   #define GPIOTE_INTENCLR5_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
27454   #define GPIOTE_INTENCLR5_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
27455                                                                             field.*/
27456   #define GPIOTE_INTENCLR5_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
27457   #define GPIOTE_INTENCLR5_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
27458   #define GPIOTE_INTENCLR5_PORT1NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27459   #define GPIOTE_INTENCLR5_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27460   #define GPIOTE_INTENCLR5_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27461 
27462 /* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */
27463   #define GPIOTE_INTENCLR5_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
27464   #define GPIOTE_INTENCLR5_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
27465   #define GPIOTE_INTENCLR5_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
27466   #define GPIOTE_INTENCLR5_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
27467   #define GPIOTE_INTENCLR5_PORT1SECURE_Clear (0x1UL) /*!< Disable                                                              */
27468   #define GPIOTE_INTENCLR5_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27469   #define GPIOTE_INTENCLR5_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27470 
27471 /* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */
27472   #define GPIOTE_INTENCLR5_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
27473   #define GPIOTE_INTENCLR5_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
27474                                                                             field.*/
27475   #define GPIOTE_INTENCLR5_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
27476   #define GPIOTE_INTENCLR5_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
27477   #define GPIOTE_INTENCLR5_PORT2NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27478   #define GPIOTE_INTENCLR5_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27479   #define GPIOTE_INTENCLR5_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27480 
27481 /* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */
27482   #define GPIOTE_INTENCLR5_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
27483   #define GPIOTE_INTENCLR5_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
27484   #define GPIOTE_INTENCLR5_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
27485   #define GPIOTE_INTENCLR5_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
27486   #define GPIOTE_INTENCLR5_PORT2SECURE_Clear (0x1UL) /*!< Disable                                                              */
27487   #define GPIOTE_INTENCLR5_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27488   #define GPIOTE_INTENCLR5_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27489 
27490 /* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */
27491   #define GPIOTE_INTENCLR5_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
27492   #define GPIOTE_INTENCLR5_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
27493                                                                             field.*/
27494   #define GPIOTE_INTENCLR5_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
27495   #define GPIOTE_INTENCLR5_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
27496   #define GPIOTE_INTENCLR5_PORT3NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27497   #define GPIOTE_INTENCLR5_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27498   #define GPIOTE_INTENCLR5_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27499 
27500 /* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */
27501   #define GPIOTE_INTENCLR5_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
27502   #define GPIOTE_INTENCLR5_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR5_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
27503   #define GPIOTE_INTENCLR5_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
27504   #define GPIOTE_INTENCLR5_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
27505   #define GPIOTE_INTENCLR5_PORT3SECURE_Clear (0x1UL) /*!< Disable                                                              */
27506   #define GPIOTE_INTENCLR5_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27507   #define GPIOTE_INTENCLR5_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27508 
27509 
27510 /* GPIOTE_INTENSET6: Enable interrupt */
27511   #define GPIOTE_INTENSET6_ResetValue (0x00000000UL) /*!< Reset value of INTENSET6 register.                                   */
27512 
27513 /* IN0 @Bit 0 : Write '1' to enable interrupt for event IN[0] */
27514   #define GPIOTE_INTENSET6_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
27515   #define GPIOTE_INTENSET6_IN0_Msk (0x1UL << GPIOTE_INTENSET6_IN0_Pos) /*!< Bit mask of IN0 field.                             */
27516   #define GPIOTE_INTENSET6_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
27517   #define GPIOTE_INTENSET6_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
27518   #define GPIOTE_INTENSET6_IN0_Set (0x1UL)           /*!< Enable                                                               */
27519   #define GPIOTE_INTENSET6_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27520   #define GPIOTE_INTENSET6_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27521 
27522 /* IN1 @Bit 1 : Write '1' to enable interrupt for event IN[1] */
27523   #define GPIOTE_INTENSET6_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
27524   #define GPIOTE_INTENSET6_IN1_Msk (0x1UL << GPIOTE_INTENSET6_IN1_Pos) /*!< Bit mask of IN1 field.                             */
27525   #define GPIOTE_INTENSET6_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
27526   #define GPIOTE_INTENSET6_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
27527   #define GPIOTE_INTENSET6_IN1_Set (0x1UL)           /*!< Enable                                                               */
27528   #define GPIOTE_INTENSET6_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27529   #define GPIOTE_INTENSET6_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27530 
27531 /* IN2 @Bit 2 : Write '1' to enable interrupt for event IN[2] */
27532   #define GPIOTE_INTENSET6_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
27533   #define GPIOTE_INTENSET6_IN2_Msk (0x1UL << GPIOTE_INTENSET6_IN2_Pos) /*!< Bit mask of IN2 field.                             */
27534   #define GPIOTE_INTENSET6_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
27535   #define GPIOTE_INTENSET6_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
27536   #define GPIOTE_INTENSET6_IN2_Set (0x1UL)           /*!< Enable                                                               */
27537   #define GPIOTE_INTENSET6_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27538   #define GPIOTE_INTENSET6_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27539 
27540 /* IN3 @Bit 3 : Write '1' to enable interrupt for event IN[3] */
27541   #define GPIOTE_INTENSET6_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
27542   #define GPIOTE_INTENSET6_IN3_Msk (0x1UL << GPIOTE_INTENSET6_IN3_Pos) /*!< Bit mask of IN3 field.                             */
27543   #define GPIOTE_INTENSET6_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
27544   #define GPIOTE_INTENSET6_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
27545   #define GPIOTE_INTENSET6_IN3_Set (0x1UL)           /*!< Enable                                                               */
27546   #define GPIOTE_INTENSET6_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27547   #define GPIOTE_INTENSET6_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27548 
27549 /* IN4 @Bit 4 : Write '1' to enable interrupt for event IN[4] */
27550   #define GPIOTE_INTENSET6_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
27551   #define GPIOTE_INTENSET6_IN4_Msk (0x1UL << GPIOTE_INTENSET6_IN4_Pos) /*!< Bit mask of IN4 field.                             */
27552   #define GPIOTE_INTENSET6_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
27553   #define GPIOTE_INTENSET6_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
27554   #define GPIOTE_INTENSET6_IN4_Set (0x1UL)           /*!< Enable                                                               */
27555   #define GPIOTE_INTENSET6_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27556   #define GPIOTE_INTENSET6_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27557 
27558 /* IN5 @Bit 5 : Write '1' to enable interrupt for event IN[5] */
27559   #define GPIOTE_INTENSET6_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
27560   #define GPIOTE_INTENSET6_IN5_Msk (0x1UL << GPIOTE_INTENSET6_IN5_Pos) /*!< Bit mask of IN5 field.                             */
27561   #define GPIOTE_INTENSET6_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
27562   #define GPIOTE_INTENSET6_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
27563   #define GPIOTE_INTENSET6_IN5_Set (0x1UL)           /*!< Enable                                                               */
27564   #define GPIOTE_INTENSET6_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27565   #define GPIOTE_INTENSET6_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27566 
27567 /* IN6 @Bit 6 : Write '1' to enable interrupt for event IN[6] */
27568   #define GPIOTE_INTENSET6_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
27569   #define GPIOTE_INTENSET6_IN6_Msk (0x1UL << GPIOTE_INTENSET6_IN6_Pos) /*!< Bit mask of IN6 field.                             */
27570   #define GPIOTE_INTENSET6_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
27571   #define GPIOTE_INTENSET6_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
27572   #define GPIOTE_INTENSET6_IN6_Set (0x1UL)           /*!< Enable                                                               */
27573   #define GPIOTE_INTENSET6_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27574   #define GPIOTE_INTENSET6_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27575 
27576 /* IN7 @Bit 7 : Write '1' to enable interrupt for event IN[7] */
27577   #define GPIOTE_INTENSET6_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
27578   #define GPIOTE_INTENSET6_IN7_Msk (0x1UL << GPIOTE_INTENSET6_IN7_Pos) /*!< Bit mask of IN7 field.                             */
27579   #define GPIOTE_INTENSET6_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
27580   #define GPIOTE_INTENSET6_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
27581   #define GPIOTE_INTENSET6_IN7_Set (0x1UL)           /*!< Enable                                                               */
27582   #define GPIOTE_INTENSET6_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27583   #define GPIOTE_INTENSET6_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27584 
27585 /* PORT0NONSECURE @Bit 16 : Write '1' to enable interrupt for event PORT0NONSECURE */
27586   #define GPIOTE_INTENSET6_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
27587   #define GPIOTE_INTENSET6_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
27588                                                                             field.*/
27589   #define GPIOTE_INTENSET6_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
27590   #define GPIOTE_INTENSET6_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
27591   #define GPIOTE_INTENSET6_PORT0NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27592   #define GPIOTE_INTENSET6_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27593   #define GPIOTE_INTENSET6_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27594 
27595 /* PORT0SECURE @Bit 17 : Write '1' to enable interrupt for event PORT0SECURE */
27596   #define GPIOTE_INTENSET6_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
27597   #define GPIOTE_INTENSET6_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
27598   #define GPIOTE_INTENSET6_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
27599   #define GPIOTE_INTENSET6_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
27600   #define GPIOTE_INTENSET6_PORT0SECURE_Set (0x1UL)   /*!< Enable                                                               */
27601   #define GPIOTE_INTENSET6_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27602   #define GPIOTE_INTENSET6_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27603 
27604 /* PORT1NONSECURE @Bit 18 : Write '1' to enable interrupt for event PORT1NONSECURE */
27605   #define GPIOTE_INTENSET6_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
27606   #define GPIOTE_INTENSET6_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
27607                                                                             field.*/
27608   #define GPIOTE_INTENSET6_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
27609   #define GPIOTE_INTENSET6_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
27610   #define GPIOTE_INTENSET6_PORT1NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27611   #define GPIOTE_INTENSET6_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27612   #define GPIOTE_INTENSET6_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27613 
27614 /* PORT1SECURE @Bit 19 : Write '1' to enable interrupt for event PORT1SECURE */
27615   #define GPIOTE_INTENSET6_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
27616   #define GPIOTE_INTENSET6_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
27617   #define GPIOTE_INTENSET6_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
27618   #define GPIOTE_INTENSET6_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
27619   #define GPIOTE_INTENSET6_PORT1SECURE_Set (0x1UL)   /*!< Enable                                                               */
27620   #define GPIOTE_INTENSET6_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27621   #define GPIOTE_INTENSET6_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27622 
27623 /* PORT2NONSECURE @Bit 20 : Write '1' to enable interrupt for event PORT2NONSECURE */
27624   #define GPIOTE_INTENSET6_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
27625   #define GPIOTE_INTENSET6_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
27626                                                                             field.*/
27627   #define GPIOTE_INTENSET6_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
27628   #define GPIOTE_INTENSET6_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
27629   #define GPIOTE_INTENSET6_PORT2NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27630   #define GPIOTE_INTENSET6_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27631   #define GPIOTE_INTENSET6_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27632 
27633 /* PORT2SECURE @Bit 21 : Write '1' to enable interrupt for event PORT2SECURE */
27634   #define GPIOTE_INTENSET6_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
27635   #define GPIOTE_INTENSET6_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
27636   #define GPIOTE_INTENSET6_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
27637   #define GPIOTE_INTENSET6_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
27638   #define GPIOTE_INTENSET6_PORT2SECURE_Set (0x1UL)   /*!< Enable                                                               */
27639   #define GPIOTE_INTENSET6_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27640   #define GPIOTE_INTENSET6_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27641 
27642 /* PORT3NONSECURE @Bit 22 : Write '1' to enable interrupt for event PORT3NONSECURE */
27643   #define GPIOTE_INTENSET6_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
27644   #define GPIOTE_INTENSET6_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
27645                                                                             field.*/
27646   #define GPIOTE_INTENSET6_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
27647   #define GPIOTE_INTENSET6_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
27648   #define GPIOTE_INTENSET6_PORT3NONSECURE_Set (0x1UL) /*!< Enable                                                              */
27649   #define GPIOTE_INTENSET6_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27650   #define GPIOTE_INTENSET6_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27651 
27652 /* PORT3SECURE @Bit 23 : Write '1' to enable interrupt for event PORT3SECURE */
27653   #define GPIOTE_INTENSET6_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
27654   #define GPIOTE_INTENSET6_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENSET6_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
27655   #define GPIOTE_INTENSET6_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
27656   #define GPIOTE_INTENSET6_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
27657   #define GPIOTE_INTENSET6_PORT3SECURE_Set (0x1UL)   /*!< Enable                                                               */
27658   #define GPIOTE_INTENSET6_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27659   #define GPIOTE_INTENSET6_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27660 
27661 
27662 /* GPIOTE_INTENCLR6: Disable interrupt */
27663   #define GPIOTE_INTENCLR6_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR6 register.                                   */
27664 
27665 /* IN0 @Bit 0 : Write '1' to disable interrupt for event IN[0] */
27666   #define GPIOTE_INTENCLR6_IN0_Pos (0UL)             /*!< Position of IN0 field.                                               */
27667   #define GPIOTE_INTENCLR6_IN0_Msk (0x1UL << GPIOTE_INTENCLR6_IN0_Pos) /*!< Bit mask of IN0 field.                             */
27668   #define GPIOTE_INTENCLR6_IN0_Min (0x0UL)           /*!< Min enumerator value of IN0 field.                                   */
27669   #define GPIOTE_INTENCLR6_IN0_Max (0x1UL)           /*!< Max enumerator value of IN0 field.                                   */
27670   #define GPIOTE_INTENCLR6_IN0_Clear (0x1UL)         /*!< Disable                                                              */
27671   #define GPIOTE_INTENCLR6_IN0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27672   #define GPIOTE_INTENCLR6_IN0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27673 
27674 /* IN1 @Bit 1 : Write '1' to disable interrupt for event IN[1] */
27675   #define GPIOTE_INTENCLR6_IN1_Pos (1UL)             /*!< Position of IN1 field.                                               */
27676   #define GPIOTE_INTENCLR6_IN1_Msk (0x1UL << GPIOTE_INTENCLR6_IN1_Pos) /*!< Bit mask of IN1 field.                             */
27677   #define GPIOTE_INTENCLR6_IN1_Min (0x0UL)           /*!< Min enumerator value of IN1 field.                                   */
27678   #define GPIOTE_INTENCLR6_IN1_Max (0x1UL)           /*!< Max enumerator value of IN1 field.                                   */
27679   #define GPIOTE_INTENCLR6_IN1_Clear (0x1UL)         /*!< Disable                                                              */
27680   #define GPIOTE_INTENCLR6_IN1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27681   #define GPIOTE_INTENCLR6_IN1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27682 
27683 /* IN2 @Bit 2 : Write '1' to disable interrupt for event IN[2] */
27684   #define GPIOTE_INTENCLR6_IN2_Pos (2UL)             /*!< Position of IN2 field.                                               */
27685   #define GPIOTE_INTENCLR6_IN2_Msk (0x1UL << GPIOTE_INTENCLR6_IN2_Pos) /*!< Bit mask of IN2 field.                             */
27686   #define GPIOTE_INTENCLR6_IN2_Min (0x0UL)           /*!< Min enumerator value of IN2 field.                                   */
27687   #define GPIOTE_INTENCLR6_IN2_Max (0x1UL)           /*!< Max enumerator value of IN2 field.                                   */
27688   #define GPIOTE_INTENCLR6_IN2_Clear (0x1UL)         /*!< Disable                                                              */
27689   #define GPIOTE_INTENCLR6_IN2_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27690   #define GPIOTE_INTENCLR6_IN2_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27691 
27692 /* IN3 @Bit 3 : Write '1' to disable interrupt for event IN[3] */
27693   #define GPIOTE_INTENCLR6_IN3_Pos (3UL)             /*!< Position of IN3 field.                                               */
27694   #define GPIOTE_INTENCLR6_IN3_Msk (0x1UL << GPIOTE_INTENCLR6_IN3_Pos) /*!< Bit mask of IN3 field.                             */
27695   #define GPIOTE_INTENCLR6_IN3_Min (0x0UL)           /*!< Min enumerator value of IN3 field.                                   */
27696   #define GPIOTE_INTENCLR6_IN3_Max (0x1UL)           /*!< Max enumerator value of IN3 field.                                   */
27697   #define GPIOTE_INTENCLR6_IN3_Clear (0x1UL)         /*!< Disable                                                              */
27698   #define GPIOTE_INTENCLR6_IN3_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27699   #define GPIOTE_INTENCLR6_IN3_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27700 
27701 /* IN4 @Bit 4 : Write '1' to disable interrupt for event IN[4] */
27702   #define GPIOTE_INTENCLR6_IN4_Pos (4UL)             /*!< Position of IN4 field.                                               */
27703   #define GPIOTE_INTENCLR6_IN4_Msk (0x1UL << GPIOTE_INTENCLR6_IN4_Pos) /*!< Bit mask of IN4 field.                             */
27704   #define GPIOTE_INTENCLR6_IN4_Min (0x0UL)           /*!< Min enumerator value of IN4 field.                                   */
27705   #define GPIOTE_INTENCLR6_IN4_Max (0x1UL)           /*!< Max enumerator value of IN4 field.                                   */
27706   #define GPIOTE_INTENCLR6_IN4_Clear (0x1UL)         /*!< Disable                                                              */
27707   #define GPIOTE_INTENCLR6_IN4_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27708   #define GPIOTE_INTENCLR6_IN4_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27709 
27710 /* IN5 @Bit 5 : Write '1' to disable interrupt for event IN[5] */
27711   #define GPIOTE_INTENCLR6_IN5_Pos (5UL)             /*!< Position of IN5 field.                                               */
27712   #define GPIOTE_INTENCLR6_IN5_Msk (0x1UL << GPIOTE_INTENCLR6_IN5_Pos) /*!< Bit mask of IN5 field.                             */
27713   #define GPIOTE_INTENCLR6_IN5_Min (0x0UL)           /*!< Min enumerator value of IN5 field.                                   */
27714   #define GPIOTE_INTENCLR6_IN5_Max (0x1UL)           /*!< Max enumerator value of IN5 field.                                   */
27715   #define GPIOTE_INTENCLR6_IN5_Clear (0x1UL)         /*!< Disable                                                              */
27716   #define GPIOTE_INTENCLR6_IN5_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27717   #define GPIOTE_INTENCLR6_IN5_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27718 
27719 /* IN6 @Bit 6 : Write '1' to disable interrupt for event IN[6] */
27720   #define GPIOTE_INTENCLR6_IN6_Pos (6UL)             /*!< Position of IN6 field.                                               */
27721   #define GPIOTE_INTENCLR6_IN6_Msk (0x1UL << GPIOTE_INTENCLR6_IN6_Pos) /*!< Bit mask of IN6 field.                             */
27722   #define GPIOTE_INTENCLR6_IN6_Min (0x0UL)           /*!< Min enumerator value of IN6 field.                                   */
27723   #define GPIOTE_INTENCLR6_IN6_Max (0x1UL)           /*!< Max enumerator value of IN6 field.                                   */
27724   #define GPIOTE_INTENCLR6_IN6_Clear (0x1UL)         /*!< Disable                                                              */
27725   #define GPIOTE_INTENCLR6_IN6_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27726   #define GPIOTE_INTENCLR6_IN6_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27727 
27728 /* IN7 @Bit 7 : Write '1' to disable interrupt for event IN[7] */
27729   #define GPIOTE_INTENCLR6_IN7_Pos (7UL)             /*!< Position of IN7 field.                                               */
27730   #define GPIOTE_INTENCLR6_IN7_Msk (0x1UL << GPIOTE_INTENCLR6_IN7_Pos) /*!< Bit mask of IN7 field.                             */
27731   #define GPIOTE_INTENCLR6_IN7_Min (0x0UL)           /*!< Min enumerator value of IN7 field.                                   */
27732   #define GPIOTE_INTENCLR6_IN7_Max (0x1UL)           /*!< Max enumerator value of IN7 field.                                   */
27733   #define GPIOTE_INTENCLR6_IN7_Clear (0x1UL)         /*!< Disable                                                              */
27734   #define GPIOTE_INTENCLR6_IN7_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
27735   #define GPIOTE_INTENCLR6_IN7_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
27736 
27737 /* PORT0NONSECURE @Bit 16 : Write '1' to disable interrupt for event PORT0NONSECURE */
27738   #define GPIOTE_INTENCLR6_PORT0NONSECURE_Pos (16UL) /*!< Position of PORT0NONSECURE field.                                    */
27739   #define GPIOTE_INTENCLR6_PORT0NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT0NONSECURE_Pos) /*!< Bit mask of PORT0NONSECURE
27740                                                                             field.*/
27741   #define GPIOTE_INTENCLR6_PORT0NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT0NONSECURE field.                       */
27742   #define GPIOTE_INTENCLR6_PORT0NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT0NONSECURE field.                       */
27743   #define GPIOTE_INTENCLR6_PORT0NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27744   #define GPIOTE_INTENCLR6_PORT0NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27745   #define GPIOTE_INTENCLR6_PORT0NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27746 
27747 /* PORT0SECURE @Bit 17 : Write '1' to disable interrupt for event PORT0SECURE */
27748   #define GPIOTE_INTENCLR6_PORT0SECURE_Pos (17UL)    /*!< Position of PORT0SECURE field.                                       */
27749   #define GPIOTE_INTENCLR6_PORT0SECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT0SECURE_Pos) /*!< Bit mask of PORT0SECURE field.     */
27750   #define GPIOTE_INTENCLR6_PORT0SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT0SECURE field.                           */
27751   #define GPIOTE_INTENCLR6_PORT0SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT0SECURE field.                           */
27752   #define GPIOTE_INTENCLR6_PORT0SECURE_Clear (0x1UL) /*!< Disable                                                              */
27753   #define GPIOTE_INTENCLR6_PORT0SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27754   #define GPIOTE_INTENCLR6_PORT0SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27755 
27756 /* PORT1NONSECURE @Bit 18 : Write '1' to disable interrupt for event PORT1NONSECURE */
27757   #define GPIOTE_INTENCLR6_PORT1NONSECURE_Pos (18UL) /*!< Position of PORT1NONSECURE field.                                    */
27758   #define GPIOTE_INTENCLR6_PORT1NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT1NONSECURE_Pos) /*!< Bit mask of PORT1NONSECURE
27759                                                                             field.*/
27760   #define GPIOTE_INTENCLR6_PORT1NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT1NONSECURE field.                       */
27761   #define GPIOTE_INTENCLR6_PORT1NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT1NONSECURE field.                       */
27762   #define GPIOTE_INTENCLR6_PORT1NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27763   #define GPIOTE_INTENCLR6_PORT1NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27764   #define GPIOTE_INTENCLR6_PORT1NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27765 
27766 /* PORT1SECURE @Bit 19 : Write '1' to disable interrupt for event PORT1SECURE */
27767   #define GPIOTE_INTENCLR6_PORT1SECURE_Pos (19UL)    /*!< Position of PORT1SECURE field.                                       */
27768   #define GPIOTE_INTENCLR6_PORT1SECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT1SECURE_Pos) /*!< Bit mask of PORT1SECURE field.     */
27769   #define GPIOTE_INTENCLR6_PORT1SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT1SECURE field.                           */
27770   #define GPIOTE_INTENCLR6_PORT1SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT1SECURE field.                           */
27771   #define GPIOTE_INTENCLR6_PORT1SECURE_Clear (0x1UL) /*!< Disable                                                              */
27772   #define GPIOTE_INTENCLR6_PORT1SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27773   #define GPIOTE_INTENCLR6_PORT1SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27774 
27775 /* PORT2NONSECURE @Bit 20 : Write '1' to disable interrupt for event PORT2NONSECURE */
27776   #define GPIOTE_INTENCLR6_PORT2NONSECURE_Pos (20UL) /*!< Position of PORT2NONSECURE field.                                    */
27777   #define GPIOTE_INTENCLR6_PORT2NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT2NONSECURE_Pos) /*!< Bit mask of PORT2NONSECURE
27778                                                                             field.*/
27779   #define GPIOTE_INTENCLR6_PORT2NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT2NONSECURE field.                       */
27780   #define GPIOTE_INTENCLR6_PORT2NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT2NONSECURE field.                       */
27781   #define GPIOTE_INTENCLR6_PORT2NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27782   #define GPIOTE_INTENCLR6_PORT2NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27783   #define GPIOTE_INTENCLR6_PORT2NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27784 
27785 /* PORT2SECURE @Bit 21 : Write '1' to disable interrupt for event PORT2SECURE */
27786   #define GPIOTE_INTENCLR6_PORT2SECURE_Pos (21UL)    /*!< Position of PORT2SECURE field.                                       */
27787   #define GPIOTE_INTENCLR6_PORT2SECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT2SECURE_Pos) /*!< Bit mask of PORT2SECURE field.     */
27788   #define GPIOTE_INTENCLR6_PORT2SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT2SECURE field.                           */
27789   #define GPIOTE_INTENCLR6_PORT2SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT2SECURE field.                           */
27790   #define GPIOTE_INTENCLR6_PORT2SECURE_Clear (0x1UL) /*!< Disable                                                              */
27791   #define GPIOTE_INTENCLR6_PORT2SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27792   #define GPIOTE_INTENCLR6_PORT2SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27793 
27794 /* PORT3NONSECURE @Bit 22 : Write '1' to disable interrupt for event PORT3NONSECURE */
27795   #define GPIOTE_INTENCLR6_PORT3NONSECURE_Pos (22UL) /*!< Position of PORT3NONSECURE field.                                    */
27796   #define GPIOTE_INTENCLR6_PORT3NONSECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT3NONSECURE_Pos) /*!< Bit mask of PORT3NONSECURE
27797                                                                             field.*/
27798   #define GPIOTE_INTENCLR6_PORT3NONSECURE_Min (0x0UL) /*!< Min enumerator value of PORT3NONSECURE field.                       */
27799   #define GPIOTE_INTENCLR6_PORT3NONSECURE_Max (0x1UL) /*!< Max enumerator value of PORT3NONSECURE field.                       */
27800   #define GPIOTE_INTENCLR6_PORT3NONSECURE_Clear (0x1UL) /*!< Disable                                                           */
27801   #define GPIOTE_INTENCLR6_PORT3NONSECURE_Disabled (0x0UL) /*!< Read: Disabled                                                 */
27802   #define GPIOTE_INTENCLR6_PORT3NONSECURE_Enabled (0x1UL) /*!< Read: Enabled                                                   */
27803 
27804 /* PORT3SECURE @Bit 23 : Write '1' to disable interrupt for event PORT3SECURE */
27805   #define GPIOTE_INTENCLR6_PORT3SECURE_Pos (23UL)    /*!< Position of PORT3SECURE field.                                       */
27806   #define GPIOTE_INTENCLR6_PORT3SECURE_Msk (0x1UL << GPIOTE_INTENCLR6_PORT3SECURE_Pos) /*!< Bit mask of PORT3SECURE field.     */
27807   #define GPIOTE_INTENCLR6_PORT3SECURE_Min (0x0UL)   /*!< Min enumerator value of PORT3SECURE field.                           */
27808   #define GPIOTE_INTENCLR6_PORT3SECURE_Max (0x1UL)   /*!< Max enumerator value of PORT3SECURE field.                           */
27809   #define GPIOTE_INTENCLR6_PORT3SECURE_Clear (0x1UL) /*!< Disable                                                              */
27810   #define GPIOTE_INTENCLR6_PORT3SECURE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
27811   #define GPIOTE_INTENCLR6_PORT3SECURE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
27812 
27813 
27814 /* GPIOTE_LATENCY: Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. */
27815   #define GPIOTE_LATENCY_ResetValue (0x00000001UL)   /*!< Reset value of LATENCY register.                                     */
27816 
27817 /* LATENCY @Bit 0 : Latency setting */
27818   #define GPIOTE_LATENCY_LATENCY_Pos (0UL)           /*!< Position of LATENCY field.                                           */
27819   #define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos) /*!< Bit mask of LATENCY field.                     */
27820   #define GPIOTE_LATENCY_LATENCY_Min (0x0UL)         /*!< Min enumerator value of LATENCY field.                               */
27821   #define GPIOTE_LATENCY_LATENCY_Max (0x1UL)         /*!< Max enumerator value of LATENCY field.                               */
27822   #define GPIOTE_LATENCY_LATENCY_LowPower (0x0UL)    /*!< Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP;
27823                                                           refer to Electrical specification section*/
27824   #define GPIOTE_LATENCY_LATENCY_LowLatency (0x1UL)  /*!< Low latency setting, for signals with minimum hold time
27825                                                           tGPIOTE,HOLD,LL; refer to Electrical specification section*/
27826 
27827 
27828 /* GPIOTE_CONFIG: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
27829   #define GPIOTE_CONFIG_MaxCount (8UL)               /*!< Max size of CONFIG[8] array.                                         */
27830   #define GPIOTE_CONFIG_MaxIndex (7UL)               /*!< Max index of CONFIG[8] array.                                        */
27831   #define GPIOTE_CONFIG_MinIndex (0UL)               /*!< Min index of CONFIG[8] array.                                        */
27832   #define GPIOTE_CONFIG_ResetValue (0x00000000UL)    /*!< Reset value of CONFIG[8] register.                                   */
27833 
27834 /* MODE @Bits 0..1 : Mode */
27835   #define GPIOTE_CONFIG_MODE_Pos (0UL)               /*!< Position of MODE field.                                              */
27836   #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field.                                */
27837   #define GPIOTE_CONFIG_MODE_Min (0x0UL)             /*!< Min enumerator value of MODE field.                                  */
27838   #define GPIOTE_CONFIG_MODE_Max (0x3UL)             /*!< Max enumerator value of MODE field.                                  */
27839   #define GPIOTE_CONFIG_MODE_Disabled (0x0UL)        /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE
27840                                                           module.*/
27841   #define GPIOTE_CONFIG_MODE_Event (0x1UL)           /*!< Event mode                                                           */
27842   #define GPIOTE_CONFIG_MODE_Task (0x3UL)            /*!< Task mode                                                            */
27843 
27844 /* PSEL @Bits 4..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
27845   #define GPIOTE_CONFIG_PSEL_Pos (4UL)               /*!< Position of PSEL field.                                              */
27846   #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field.                               */
27847   #define GPIOTE_CONFIG_PSEL_Min (0x0UL)             /*!< Min value of PSEL field.                                             */
27848   #define GPIOTE_CONFIG_PSEL_Max (0x1FUL)            /*!< Max size of PSEL field.                                              */
27849 
27850 /* PORT @Bits 9..12 : Port number */
27851   #define GPIOTE_CONFIG_PORT_Pos (9UL)               /*!< Position of PORT field.                                              */
27852   #define GPIOTE_CONFIG_PORT_Msk (0xFUL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field.                                */
27853   #define GPIOTE_CONFIG_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
27854   #define GPIOTE_CONFIG_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
27855 
27856 /* POLARITY @Bits 16..17 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event
27857                            mode: Operation on input that shall trigger IN[n] event. */
27858 
27859   #define GPIOTE_CONFIG_POLARITY_Pos (16UL)          /*!< Position of POLARITY field.                                          */
27860   #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field.                    */
27861   #define GPIOTE_CONFIG_POLARITY_Min (0x0UL)         /*!< Min enumerator value of POLARITY field.                              */
27862   #define GPIOTE_CONFIG_POLARITY_Max (0x3UL)         /*!< Max enumerator value of POLARITY field.                              */
27863   #define GPIOTE_CONFIG_POLARITY_None (0x0UL)        /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n]
27864                                                           event generated on pin activity.*/
27865   #define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL)      /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event
27866                                                           when rising edge on pin.*/
27867   #define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL)      /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n]
27868                                                           event when falling edge on pin.*/
27869   #define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL)      /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any
27870                                                           change on pin.*/
27871 
27872 /* OUTINIT @Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode:
27873                      No effect. */
27874 
27875   #define GPIOTE_CONFIG_OUTINIT_Pos (20UL)           /*!< Position of OUTINIT field.                                           */
27876   #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field.                       */
27877   #define GPIOTE_CONFIG_OUTINIT_Min (0x0UL)          /*!< Min enumerator value of OUTINIT field.                               */
27878   #define GPIOTE_CONFIG_OUTINIT_Max (0x1UL)          /*!< Max enumerator value of OUTINIT field.                               */
27879   #define GPIOTE_CONFIG_OUTINIT_Low (0x0UL)          /*!< Task mode: Initial value of pin before task triggering is low        */
27880   #define GPIOTE_CONFIG_OUTINIT_High (0x1UL)         /*!< Task mode: Initial value of pin before task triggering is high       */
27881 
27882 
27883 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
27884 
27885 /* =========================================================================================================================== */
27886 /* ================                                           GRTC                                           ================ */
27887 /* =========================================================================================================================== */
27888 
27889 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
27890 
27891 /* ===================================================== Struct GRTC_CC ====================================================== */
27892 /**
27893   * @brief CC [GRTC_CC] (unspecified)
27894   */
27895 typedef struct {
27896   __IOM uint32_t  CCL;                               /*!< (@ 0x00000000) The lower 32-bits of Capture/Compare register CC[n]   */
27897   __IOM uint32_t  CCH;                               /*!< (@ 0x00000004) The higher 32-bits of Capture/Compare register CC[n]  */
27898   __IOM uint32_t  CCADD;                             /*!< (@ 0x00000008) Count to add to CC[n]                                 */
27899   __IOM uint32_t  CCEN;                              /*!< (@ 0x0000000C) Configure Capture/Compare register CC[n]              */
27900 } NRF_GRTC_CC_Type;                                  /*!< Size = 16 (0x010)                                                    */
27901   #define GRTC_CC_MaxCount (16UL)                    /*!< Size of CC[16] array.                                                */
27902   #define GRTC_CC_MaxIndex (15UL)                    /*!< Max index of CC[16] array.                                           */
27903   #define GRTC_CC_MinIndex (0UL)                     /*!< Min index of CC[16] array.                                           */
27904 
27905 /* GRTC_CC_CCL: The lower 32-bits of Capture/Compare register CC[n] */
27906   #define GRTC_CC_CCL_ResetValue (0x00000000UL)      /*!< Reset value of CCL register.                                         */
27907 
27908 /* CCL @Bits 0..31 : Capture/Compare low value in 1 us */
27909   #define GRTC_CC_CCL_CCL_Pos (0UL)                  /*!< Position of CCL field.                                               */
27910   #define GRTC_CC_CCL_CCL_Msk (0xFFFFFFFFUL << GRTC_CC_CCL_CCL_Pos) /*!< Bit mask of CCL field.                                */
27911 
27912 
27913 /* GRTC_CC_CCH: The higher 32-bits of Capture/Compare register CC[n] */
27914   #define GRTC_CC_CCH_ResetValue (0x00000000UL)      /*!< Reset value of CCH register.                                         */
27915 
27916 /* CCH @Bits 0..19 : Capture/Compare high value in 1 us */
27917   #define GRTC_CC_CCH_CCH_Pos (0UL)                  /*!< Position of CCH field.                                               */
27918   #define GRTC_CC_CCH_CCH_Msk (0xFFFFFUL << GRTC_CC_CCH_CCH_Pos) /*!< Bit mask of CCH field.                                   */
27919 
27920 
27921 /* GRTC_CC_CCADD: Count to add to CC[n] */
27922   #define GRTC_CC_CCADD_ResetValue (0x00000000UL)    /*!< Reset value of CCADD register.                                       */
27923 
27924 /* VALUE @Bits 0..30 : Count to add to CC[n] */
27925   #define GRTC_CC_CCADD_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
27926   #define GRTC_CC_CCADD_VALUE_Msk (0x7FFFFFFFUL << GRTC_CC_CCADD_VALUE_Pos) /*!< Bit mask of VALUE field.                      */
27927 
27928 /* REFERENCE @Bit 31 : Configure the Capture/Compare register */
27929   #define GRTC_CC_CCADD_REFERENCE_Pos (31UL)         /*!< Position of REFERENCE field.                                         */
27930   #define GRTC_CC_CCADD_REFERENCE_Msk (0x1UL << GRTC_CC_CCADD_REFERENCE_Pos) /*!< Bit mask of REFERENCE field.                 */
27931   #define GRTC_CC_CCADD_REFERENCE_Min (0x0UL)        /*!< Min enumerator value of REFERENCE field.                             */
27932   #define GRTC_CC_CCADD_REFERENCE_Max (0x1UL)        /*!< Max enumerator value of REFERENCE field.                             */
27933   #define GRTC_CC_CCADD_REFERENCE_SYSCOUNTER (0x0UL) /*!< Adds SYSCOUNTER value.                                               */
27934   #define GRTC_CC_CCADD_REFERENCE_CC (0x1UL)         /*!< Adds CC value.                                                       */
27935 
27936 
27937 /* GRTC_CC_CCEN: Configure Capture/Compare register CC[n] */
27938   #define GRTC_CC_CCEN_ResetValue (0x00000000UL)     /*!< Reset value of CCEN register.                                        */
27939 
27940 /* ACTIVE @Bit 0 : Configure the Capture/Compare register */
27941   #define GRTC_CC_CCEN_ACTIVE_Pos (0UL)              /*!< Position of ACTIVE field.                                            */
27942   #define GRTC_CC_CCEN_ACTIVE_Msk (0x1UL << GRTC_CC_CCEN_ACTIVE_Pos) /*!< Bit mask of ACTIVE field.                            */
27943   #define GRTC_CC_CCEN_ACTIVE_Min (0x0UL)            /*!< Min enumerator value of ACTIVE field.                                */
27944   #define GRTC_CC_CCEN_ACTIVE_Max (0x1UL)            /*!< Max enumerator value of ACTIVE field.                                */
27945   #define GRTC_CC_CCEN_ACTIVE_Disable (0x0UL)        /*!< Capture/Compare register CC[n] Disabled.                             */
27946   #define GRTC_CC_CCEN_ACTIVE_Enable (0x1UL)         /*!< Capture/Compare register CC[n] enabled.                              */
27947 
27948 
27949 /* ======================================================= Struct GRTC ======================================================= */
27950 /**
27951   * @brief Global Real-time counter
27952   */
27953   typedef struct {                                   /*!< GRTC Structure                                                       */
27954     __OM uint32_t TASKS_CAPTURE[16];                 /*!< (@ 0x00000000) Capture the counter value to CC[n] register           */
27955     __IM uint32_t RESERVED[16];
27956     __IOM uint32_t SUBSCRIBE_CAPTURE[16];            /*!< (@ 0x00000080) Subscribe configuration for task CAPTURE[n]           */
27957     __IM uint32_t RESERVED1[16];
27958     __IOM uint32_t EVENTS_COMPARE[16];               /*!< (@ 0x00000100) Compare event on CC[n] match                          */
27959     __IM uint32_t RESERVED2[10];
27960     __IOM uint32_t EVENTS_SYSCOUNTERVALID;           /*!< (@ 0x00000168) The SYSCOUNTER is in active state and value is valid  */
27961     __IM uint32_t RESERVED3[5];
27962     __IOM uint32_t PUBLISH_COMPARE[16];              /*!< (@ 0x00000180) Publish configuration for event COMPARE[n]            */
27963     __IM uint32_t RESERVED4[16];
27964     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
27965     __IM uint32_t RESERVED5[63];
27966     __IOM uint32_t INTEN0;                           /*!< (@ 0x00000300) Enable or disable interrupt                           */
27967     __IOM uint32_t INTENSET0;                        /*!< (@ 0x00000304) Enable interrupt                                      */
27968     __IOM uint32_t INTENCLR0;                        /*!< (@ 0x00000308) Disable interrupt                                     */
27969     __IM uint32_t INTPEND0;                          /*!< (@ 0x0000030C) Pending interrupts                                    */
27970     __IOM uint32_t INTEN1;                           /*!< (@ 0x00000310) Enable or disable interrupt                           */
27971     __IOM uint32_t INTENSET1;                        /*!< (@ 0x00000314) Enable interrupt                                      */
27972     __IOM uint32_t INTENCLR1;                        /*!< (@ 0x00000318) Disable interrupt                                     */
27973     __IM uint32_t INTPEND1;                          /*!< (@ 0x0000031C) Pending interrupts                                    */
27974     __IOM uint32_t INTEN2;                           /*!< (@ 0x00000320) Enable or disable interrupt                           */
27975     __IOM uint32_t INTENSET2;                        /*!< (@ 0x00000324) Enable interrupt                                      */
27976     __IOM uint32_t INTENCLR2;                        /*!< (@ 0x00000328) Disable interrupt                                     */
27977     __IM uint32_t INTPEND2;                          /*!< (@ 0x0000032C) Pending interrupts                                    */
27978     __IOM uint32_t INTEN3;                           /*!< (@ 0x00000330) Enable or disable interrupt                           */
27979     __IOM uint32_t INTENSET3;                        /*!< (@ 0x00000334) Enable interrupt                                      */
27980     __IOM uint32_t INTENCLR3;                        /*!< (@ 0x00000338) Disable interrupt                                     */
27981     __IM uint32_t INTPEND3;                          /*!< (@ 0x0000033C) Pending interrupts                                    */
27982     __IOM uint32_t INTEN4;                           /*!< (@ 0x00000340) Enable or disable interrupt                           */
27983     __IOM uint32_t INTENSET4;                        /*!< (@ 0x00000344) Enable interrupt                                      */
27984     __IOM uint32_t INTENCLR4;                        /*!< (@ 0x00000348) Disable interrupt                                     */
27985     __IM uint32_t INTPEND4;                          /*!< (@ 0x0000034C) Pending interrupts                                    */
27986     __IOM uint32_t INTEN5;                           /*!< (@ 0x00000350) Enable or disable interrupt                           */
27987     __IOM uint32_t INTENSET5;                        /*!< (@ 0x00000354) Enable interrupt                                      */
27988     __IOM uint32_t INTENCLR5;                        /*!< (@ 0x00000358) Disable interrupt                                     */
27989     __IM uint32_t INTPEND5;                          /*!< (@ 0x0000035C) Pending interrupts                                    */
27990     __IOM uint32_t INTEN6;                           /*!< (@ 0x00000360) Enable or disable interrupt                           */
27991     __IOM uint32_t INTENSET6;                        /*!< (@ 0x00000364) Enable interrupt                                      */
27992     __IOM uint32_t INTENCLR6;                        /*!< (@ 0x00000368) Disable interrupt                                     */
27993     __IM uint32_t INTPEND6;                          /*!< (@ 0x0000036C) Pending interrupts                                    */
27994     __IOM uint32_t INTEN7;                           /*!< (@ 0x00000370) Enable or disable interrupt                           */
27995     __IOM uint32_t INTENSET7;                        /*!< (@ 0x00000374) Enable interrupt                                      */
27996     __IOM uint32_t INTENCLR7;                        /*!< (@ 0x00000378) Disable interrupt                                     */
27997     __IM uint32_t INTPEND7;                          /*!< (@ 0x0000037C) Pending interrupts                                    */
27998     __IOM uint32_t INTEN8;                           /*!< (@ 0x00000380) Enable or disable interrupt                           */
27999     __IOM uint32_t INTENSET8;                        /*!< (@ 0x00000384) Enable interrupt                                      */
28000     __IOM uint32_t INTENCLR8;                        /*!< (@ 0x00000388) Disable interrupt                                     */
28001     __IM uint32_t INTPEND8;                          /*!< (@ 0x0000038C) Pending interrupts                                    */
28002     __IOM uint32_t INTEN9;                           /*!< (@ 0x00000390) Enable or disable interrupt                           */
28003     __IOM uint32_t INTENSET9;                        /*!< (@ 0x00000394) Enable interrupt                                      */
28004     __IOM uint32_t INTENCLR9;                        /*!< (@ 0x00000398) Disable interrupt                                     */
28005     __IM uint32_t INTPEND9;                          /*!< (@ 0x0000039C) Pending interrupts                                    */
28006     __IOM uint32_t INTEN10;                          /*!< (@ 0x000003A0) Enable or disable interrupt                           */
28007     __IOM uint32_t INTENSET10;                       /*!< (@ 0x000003A4) Enable interrupt                                      */
28008     __IOM uint32_t INTENCLR10;                       /*!< (@ 0x000003A8) Disable interrupt                                     */
28009     __IM uint32_t INTPEND10;                         /*!< (@ 0x000003AC) Pending interrupts                                    */
28010     __IOM uint32_t INTEN11;                          /*!< (@ 0x000003B0) Enable or disable interrupt                           */
28011     __IOM uint32_t INTENSET11;                       /*!< (@ 0x000003B4) Enable interrupt                                      */
28012     __IOM uint32_t INTENCLR11;                       /*!< (@ 0x000003B8) Disable interrupt                                     */
28013     __IM uint32_t INTPEND11;                         /*!< (@ 0x000003BC) Pending interrupts                                    */
28014     __IOM uint32_t INTEN12;                          /*!< (@ 0x000003C0) Enable or disable interrupt                           */
28015     __IOM uint32_t INTENSET12;                       /*!< (@ 0x000003C4) Enable interrupt                                      */
28016     __IOM uint32_t INTENCLR12;                       /*!< (@ 0x000003C8) Disable interrupt                                     */
28017     __IM uint32_t INTPEND12;                         /*!< (@ 0x000003CC) Pending interrupts                                    */
28018     __IOM uint32_t INTEN13;                          /*!< (@ 0x000003D0) Enable or disable interrupt                           */
28019     __IOM uint32_t INTENSET13;                       /*!< (@ 0x000003D4) Enable interrupt                                      */
28020     __IOM uint32_t INTENCLR13;                       /*!< (@ 0x000003D8) Disable interrupt                                     */
28021     __IM uint32_t INTPEND13;                         /*!< (@ 0x000003DC) Pending interrupts                                    */
28022     __IOM uint32_t INTEN14;                          /*!< (@ 0x000003E0) Enable or disable interrupt                           */
28023     __IOM uint32_t INTENSET14;                       /*!< (@ 0x000003E4) Enable interrupt                                      */
28024     __IOM uint32_t INTENCLR14;                       /*!< (@ 0x000003E8) Disable interrupt                                     */
28025     __IM uint32_t INTPEND14;                         /*!< (@ 0x000003EC) Pending interrupts                                    */
28026     __IOM uint32_t INTEN15;                          /*!< (@ 0x000003F0) Enable or disable interrupt                           */
28027     __IOM uint32_t INTENSET15;                       /*!< (@ 0x000003F4) Enable interrupt                                      */
28028     __IOM uint32_t INTENCLR15;                       /*!< (@ 0x000003F8) Disable interrupt                                     */
28029     __IM uint32_t INTPEND15;                         /*!< (@ 0x000003FC) Pending interrupts                                    */
28030     __IM uint32_t RESERVED6[68];
28031     __IOM uint32_t MODE;                             /*!< (@ 0x00000510) Counter mode selection                                */
28032     __IM uint32_t SYSCOUNTERL;                       /*!< (@ 0x00000514) The lower 32-bits of the SYSCOUNTER                   */
28033     __IM uint32_t SYSCOUNTERH;                       /*!< (@ 0x00000518) The higher 20-bits of the SYSCOUNTER                  */
28034     __IM uint32_t RESERVED7;
28035     __IOM NRF_GRTC_CC_Type CC[16];                   /*!< (@ 0x00000520) (unspecified)                                         */
28036     __IM uint32_t RESERVED8[32];
28037     __IOM uint32_t KEEPRUNNING;                      /*!< (@ 0x000006A0) Request to keep the SYSCOUNTER in the active state and
28038                                                                          prevent going to sleep*/
28039     __IOM uint32_t TIMEOUT;                          /*!< (@ 0x000006A4) Timeout after all CPUs gone into sleep state to stop
28040                                                                          the SYSCOUNTER*/
28041     __IOM uint32_t INTERVAL;                         /*!< (@ 0x000006A8) Count to add to CC[0] when the event EVENTS_COMPARE[0]
28042                                                                          triggers.*/
28043   } NRF_GRTC_Type;                                   /*!< Size = 1708 (0x6AC)                                                  */
28044 
28045 /* GRTC_TASKS_CAPTURE: Capture the counter value to CC[n] register */
28046   #define GRTC_TASKS_CAPTURE_MaxCount (16UL)         /*!< Max size of TASKS_CAPTURE[16] array.                                 */
28047   #define GRTC_TASKS_CAPTURE_MaxIndex (15UL)         /*!< Max index of TASKS_CAPTURE[16] array.                                */
28048   #define GRTC_TASKS_CAPTURE_MinIndex (0UL)          /*!< Min index of TASKS_CAPTURE[16] array.                                */
28049   #define GRTC_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[16] register.                         */
28050 
28051 /* TASKS_CAPTURE @Bit 0 : Capture the counter value to CC[n] register */
28052   #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field.                                     */
28053   #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE
28054                                                                             field.*/
28055   #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field.                       */
28056   #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field.                       */
28057   #define GRTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task                                                   */
28058 
28059 
28060 /* GRTC_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */
28061   #define GRTC_SUBSCRIBE_CAPTURE_MaxCount (16UL)     /*!< Max size of SUBSCRIBE_CAPTURE[16] array.                             */
28062   #define GRTC_SUBSCRIBE_CAPTURE_MaxIndex (15UL)     /*!< Max index of SUBSCRIBE_CAPTURE[16] array.                            */
28063   #define GRTC_SUBSCRIBE_CAPTURE_MinIndex (0UL)      /*!< Min index of SUBSCRIBE_CAPTURE[16] array.                            */
28064   #define GRTC_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[16] register.                 */
28065 
28066 /* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */
28067   #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
28068   #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << GRTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
28069   #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
28070   #define GRTC_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
28071 
28072 /* EN @Bit 31 : (unspecified) */
28073   #define GRTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
28074   #define GRTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << GRTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field.                    */
28075   #define GRTC_SUBSCRIBE_CAPTURE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
28076   #define GRTC_SUBSCRIBE_CAPTURE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
28077   #define GRTC_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
28078   #define GRTC_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
28079 
28080 
28081 /* GRTC_EVENTS_COMPARE: Compare event on CC[n] match */
28082   #define GRTC_EVENTS_COMPARE_MaxCount (16UL)        /*!< Max size of EVENTS_COMPARE[16] array.                                */
28083   #define GRTC_EVENTS_COMPARE_MaxIndex (15UL)        /*!< Max index of EVENTS_COMPARE[16] array.                               */
28084   #define GRTC_EVENTS_COMPARE_MinIndex (0UL)         /*!< Min index of EVENTS_COMPARE[16] array.                               */
28085   #define GRTC_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[16] register.                       */
28086 
28087 /* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */
28088   #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field.                                  */
28089   #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of
28090                                                                             EVENTS_COMPARE field.*/
28091   #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field.                    */
28092   #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field.                    */
28093   #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated                                     */
28094   #define GRTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated                                            */
28095 
28096 
28097 /* GRTC_EVENTS_SYSCOUNTERVALID: The SYSCOUNTER is in active state and value is valid */
28098   #define GRTC_EVENTS_SYSCOUNTERVALID_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SYSCOUNTERVALID register.           */
28099 
28100 /* EVENTS_SYSCOUNTERVALID @Bit 0 : The SYSCOUNTER is in active state and value is valid */
28101   #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Pos (0UL) /*!< Position of EVENTS_SYSCOUNTERVALID field.          */
28102   #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Msk (0x1UL << GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Pos)
28103                                                                             /*!< Bit mask of EVENTS_SYSCOUNTERVALID field.*/
28104   #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of EVENTS_SYSCOUNTERVALID
28105                                                                             field.*/
28106   #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of EVENTS_SYSCOUNTERVALID
28107                                                                             field.*/
28108   #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_NotGenerated (0x0UL) /*!< Event not generated                     */
28109   #define GRTC_EVENTS_SYSCOUNTERVALID_EVENTS_SYSCOUNTERVALID_Generated (0x1UL) /*!< Event generated                            */
28110 
28111 
28112 /* GRTC_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */
28113   #define GRTC_PUBLISH_COMPARE_MaxCount (16UL)       /*!< Max size of PUBLISH_COMPARE[16] array.                               */
28114   #define GRTC_PUBLISH_COMPARE_MaxIndex (15UL)       /*!< Max index of PUBLISH_COMPARE[16] array.                              */
28115   #define GRTC_PUBLISH_COMPARE_MinIndex (0UL)        /*!< Min index of PUBLISH_COMPARE[16] array.                              */
28116   #define GRTC_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[16] register.                     */
28117 
28118 /* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */
28119   #define GRTC_PUBLISH_COMPARE_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
28120   #define GRTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << GRTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
28121   #define GRTC_PUBLISH_COMPARE_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
28122   #define GRTC_PUBLISH_COMPARE_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
28123 
28124 /* EN @Bit 31 : (unspecified) */
28125   #define GRTC_PUBLISH_COMPARE_EN_Pos (31UL)         /*!< Position of EN field.                                                */
28126   #define GRTC_PUBLISH_COMPARE_EN_Msk (0x1UL << GRTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field.                        */
28127   #define GRTC_PUBLISH_COMPARE_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
28128   #define GRTC_PUBLISH_COMPARE_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
28129   #define GRTC_PUBLISH_COMPARE_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
28130   #define GRTC_PUBLISH_COMPARE_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
28131 
28132 
28133 /* GRTC_INTEN0: Enable or disable interrupt */
28134   #define GRTC_INTEN0_ResetValue (0x00000000UL)      /*!< Reset value of INTEN0 register.                                      */
28135 
28136 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
28137   #define GRTC_INTEN0_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
28138   #define GRTC_INTEN0_COMPARE0_Msk (0x1UL << GRTC_INTEN0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
28139   #define GRTC_INTEN0_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
28140   #define GRTC_INTEN0_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
28141   #define GRTC_INTEN0_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
28142   #define GRTC_INTEN0_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
28143 
28144 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
28145   #define GRTC_INTEN0_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
28146   #define GRTC_INTEN0_COMPARE1_Msk (0x1UL << GRTC_INTEN0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
28147   #define GRTC_INTEN0_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
28148   #define GRTC_INTEN0_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
28149   #define GRTC_INTEN0_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
28150   #define GRTC_INTEN0_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
28151 
28152 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
28153   #define GRTC_INTEN0_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
28154   #define GRTC_INTEN0_COMPARE2_Msk (0x1UL << GRTC_INTEN0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
28155   #define GRTC_INTEN0_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
28156   #define GRTC_INTEN0_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
28157   #define GRTC_INTEN0_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
28158   #define GRTC_INTEN0_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
28159 
28160 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
28161   #define GRTC_INTEN0_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
28162   #define GRTC_INTEN0_COMPARE3_Msk (0x1UL << GRTC_INTEN0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
28163   #define GRTC_INTEN0_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
28164   #define GRTC_INTEN0_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
28165   #define GRTC_INTEN0_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
28166   #define GRTC_INTEN0_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
28167 
28168 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
28169   #define GRTC_INTEN0_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
28170   #define GRTC_INTEN0_COMPARE4_Msk (0x1UL << GRTC_INTEN0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
28171   #define GRTC_INTEN0_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
28172   #define GRTC_INTEN0_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
28173   #define GRTC_INTEN0_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
28174   #define GRTC_INTEN0_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
28175 
28176 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
28177   #define GRTC_INTEN0_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
28178   #define GRTC_INTEN0_COMPARE5_Msk (0x1UL << GRTC_INTEN0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
28179   #define GRTC_INTEN0_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
28180   #define GRTC_INTEN0_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
28181   #define GRTC_INTEN0_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
28182   #define GRTC_INTEN0_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
28183 
28184 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
28185   #define GRTC_INTEN0_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
28186   #define GRTC_INTEN0_COMPARE6_Msk (0x1UL << GRTC_INTEN0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
28187   #define GRTC_INTEN0_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
28188   #define GRTC_INTEN0_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
28189   #define GRTC_INTEN0_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
28190   #define GRTC_INTEN0_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
28191 
28192 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
28193   #define GRTC_INTEN0_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
28194   #define GRTC_INTEN0_COMPARE7_Msk (0x1UL << GRTC_INTEN0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
28195   #define GRTC_INTEN0_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
28196   #define GRTC_INTEN0_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
28197   #define GRTC_INTEN0_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
28198   #define GRTC_INTEN0_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
28199 
28200 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
28201   #define GRTC_INTEN0_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
28202   #define GRTC_INTEN0_COMPARE8_Msk (0x1UL << GRTC_INTEN0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
28203   #define GRTC_INTEN0_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
28204   #define GRTC_INTEN0_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
28205   #define GRTC_INTEN0_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
28206   #define GRTC_INTEN0_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
28207 
28208 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
28209   #define GRTC_INTEN0_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
28210   #define GRTC_INTEN0_COMPARE9_Msk (0x1UL << GRTC_INTEN0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
28211   #define GRTC_INTEN0_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
28212   #define GRTC_INTEN0_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
28213   #define GRTC_INTEN0_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
28214   #define GRTC_INTEN0_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
28215 
28216 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
28217   #define GRTC_INTEN0_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
28218   #define GRTC_INTEN0_COMPARE10_Msk (0x1UL << GRTC_INTEN0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
28219   #define GRTC_INTEN0_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
28220   #define GRTC_INTEN0_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
28221   #define GRTC_INTEN0_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
28222   #define GRTC_INTEN0_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
28223 
28224 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
28225   #define GRTC_INTEN0_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
28226   #define GRTC_INTEN0_COMPARE11_Msk (0x1UL << GRTC_INTEN0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
28227   #define GRTC_INTEN0_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
28228   #define GRTC_INTEN0_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
28229   #define GRTC_INTEN0_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
28230   #define GRTC_INTEN0_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
28231 
28232 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
28233   #define GRTC_INTEN0_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
28234   #define GRTC_INTEN0_COMPARE12_Msk (0x1UL << GRTC_INTEN0_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
28235   #define GRTC_INTEN0_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
28236   #define GRTC_INTEN0_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
28237   #define GRTC_INTEN0_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
28238   #define GRTC_INTEN0_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
28239 
28240 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
28241   #define GRTC_INTEN0_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
28242   #define GRTC_INTEN0_COMPARE13_Msk (0x1UL << GRTC_INTEN0_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
28243   #define GRTC_INTEN0_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
28244   #define GRTC_INTEN0_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
28245   #define GRTC_INTEN0_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
28246   #define GRTC_INTEN0_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
28247 
28248 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
28249   #define GRTC_INTEN0_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
28250   #define GRTC_INTEN0_COMPARE14_Msk (0x1UL << GRTC_INTEN0_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
28251   #define GRTC_INTEN0_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
28252   #define GRTC_INTEN0_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
28253   #define GRTC_INTEN0_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
28254   #define GRTC_INTEN0_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
28255 
28256 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
28257   #define GRTC_INTEN0_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
28258   #define GRTC_INTEN0_COMPARE15_Msk (0x1UL << GRTC_INTEN0_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
28259   #define GRTC_INTEN0_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
28260   #define GRTC_INTEN0_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
28261   #define GRTC_INTEN0_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
28262   #define GRTC_INTEN0_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
28263 
28264 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
28265   #define GRTC_INTEN0_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
28266   #define GRTC_INTEN0_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN0_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
28267   #define GRTC_INTEN0_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
28268   #define GRTC_INTEN0_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
28269   #define GRTC_INTEN0_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
28270   #define GRTC_INTEN0_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
28271 
28272 
28273 /* GRTC_INTENSET0: Enable interrupt */
28274   #define GRTC_INTENSET0_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET0 register.                                   */
28275 
28276 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
28277   #define GRTC_INTENSET0_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
28278   #define GRTC_INTENSET0_COMPARE0_Msk (0x1UL << GRTC_INTENSET0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
28279   #define GRTC_INTENSET0_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
28280   #define GRTC_INTENSET0_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
28281   #define GRTC_INTENSET0_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
28282   #define GRTC_INTENSET0_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28283   #define GRTC_INTENSET0_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28284 
28285 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
28286   #define GRTC_INTENSET0_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
28287   #define GRTC_INTENSET0_COMPARE1_Msk (0x1UL << GRTC_INTENSET0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
28288   #define GRTC_INTENSET0_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
28289   #define GRTC_INTENSET0_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
28290   #define GRTC_INTENSET0_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
28291   #define GRTC_INTENSET0_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28292   #define GRTC_INTENSET0_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28293 
28294 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
28295   #define GRTC_INTENSET0_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
28296   #define GRTC_INTENSET0_COMPARE2_Msk (0x1UL << GRTC_INTENSET0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
28297   #define GRTC_INTENSET0_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
28298   #define GRTC_INTENSET0_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
28299   #define GRTC_INTENSET0_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
28300   #define GRTC_INTENSET0_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28301   #define GRTC_INTENSET0_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28302 
28303 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
28304   #define GRTC_INTENSET0_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
28305   #define GRTC_INTENSET0_COMPARE3_Msk (0x1UL << GRTC_INTENSET0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
28306   #define GRTC_INTENSET0_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
28307   #define GRTC_INTENSET0_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
28308   #define GRTC_INTENSET0_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
28309   #define GRTC_INTENSET0_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28310   #define GRTC_INTENSET0_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28311 
28312 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
28313   #define GRTC_INTENSET0_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
28314   #define GRTC_INTENSET0_COMPARE4_Msk (0x1UL << GRTC_INTENSET0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
28315   #define GRTC_INTENSET0_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
28316   #define GRTC_INTENSET0_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
28317   #define GRTC_INTENSET0_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
28318   #define GRTC_INTENSET0_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28319   #define GRTC_INTENSET0_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28320 
28321 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
28322   #define GRTC_INTENSET0_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
28323   #define GRTC_INTENSET0_COMPARE5_Msk (0x1UL << GRTC_INTENSET0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
28324   #define GRTC_INTENSET0_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
28325   #define GRTC_INTENSET0_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
28326   #define GRTC_INTENSET0_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
28327   #define GRTC_INTENSET0_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28328   #define GRTC_INTENSET0_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28329 
28330 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
28331   #define GRTC_INTENSET0_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
28332   #define GRTC_INTENSET0_COMPARE6_Msk (0x1UL << GRTC_INTENSET0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
28333   #define GRTC_INTENSET0_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
28334   #define GRTC_INTENSET0_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
28335   #define GRTC_INTENSET0_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
28336   #define GRTC_INTENSET0_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28337   #define GRTC_INTENSET0_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28338 
28339 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
28340   #define GRTC_INTENSET0_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
28341   #define GRTC_INTENSET0_COMPARE7_Msk (0x1UL << GRTC_INTENSET0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
28342   #define GRTC_INTENSET0_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
28343   #define GRTC_INTENSET0_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
28344   #define GRTC_INTENSET0_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
28345   #define GRTC_INTENSET0_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28346   #define GRTC_INTENSET0_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28347 
28348 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
28349   #define GRTC_INTENSET0_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
28350   #define GRTC_INTENSET0_COMPARE8_Msk (0x1UL << GRTC_INTENSET0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
28351   #define GRTC_INTENSET0_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
28352   #define GRTC_INTENSET0_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
28353   #define GRTC_INTENSET0_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
28354   #define GRTC_INTENSET0_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28355   #define GRTC_INTENSET0_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28356 
28357 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
28358   #define GRTC_INTENSET0_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
28359   #define GRTC_INTENSET0_COMPARE9_Msk (0x1UL << GRTC_INTENSET0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
28360   #define GRTC_INTENSET0_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
28361   #define GRTC_INTENSET0_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
28362   #define GRTC_INTENSET0_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
28363   #define GRTC_INTENSET0_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28364   #define GRTC_INTENSET0_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28365 
28366 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
28367   #define GRTC_INTENSET0_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
28368   #define GRTC_INTENSET0_COMPARE10_Msk (0x1UL << GRTC_INTENSET0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
28369   #define GRTC_INTENSET0_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
28370   #define GRTC_INTENSET0_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
28371   #define GRTC_INTENSET0_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
28372   #define GRTC_INTENSET0_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28373   #define GRTC_INTENSET0_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28374 
28375 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
28376   #define GRTC_INTENSET0_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
28377   #define GRTC_INTENSET0_COMPARE11_Msk (0x1UL << GRTC_INTENSET0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
28378   #define GRTC_INTENSET0_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
28379   #define GRTC_INTENSET0_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
28380   #define GRTC_INTENSET0_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
28381   #define GRTC_INTENSET0_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28382   #define GRTC_INTENSET0_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28383 
28384 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
28385   #define GRTC_INTENSET0_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
28386   #define GRTC_INTENSET0_COMPARE12_Msk (0x1UL << GRTC_INTENSET0_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
28387   #define GRTC_INTENSET0_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
28388   #define GRTC_INTENSET0_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
28389   #define GRTC_INTENSET0_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
28390   #define GRTC_INTENSET0_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28391   #define GRTC_INTENSET0_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28392 
28393 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
28394   #define GRTC_INTENSET0_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
28395   #define GRTC_INTENSET0_COMPARE13_Msk (0x1UL << GRTC_INTENSET0_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
28396   #define GRTC_INTENSET0_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
28397   #define GRTC_INTENSET0_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
28398   #define GRTC_INTENSET0_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
28399   #define GRTC_INTENSET0_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28400   #define GRTC_INTENSET0_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28401 
28402 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
28403   #define GRTC_INTENSET0_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
28404   #define GRTC_INTENSET0_COMPARE14_Msk (0x1UL << GRTC_INTENSET0_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
28405   #define GRTC_INTENSET0_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
28406   #define GRTC_INTENSET0_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
28407   #define GRTC_INTENSET0_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
28408   #define GRTC_INTENSET0_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28409   #define GRTC_INTENSET0_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28410 
28411 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
28412   #define GRTC_INTENSET0_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
28413   #define GRTC_INTENSET0_COMPARE15_Msk (0x1UL << GRTC_INTENSET0_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
28414   #define GRTC_INTENSET0_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
28415   #define GRTC_INTENSET0_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
28416   #define GRTC_INTENSET0_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
28417   #define GRTC_INTENSET0_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28418   #define GRTC_INTENSET0_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28419 
28420 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
28421   #define GRTC_INTENSET0_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
28422   #define GRTC_INTENSET0_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET0_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
28423                                                                             field.*/
28424   #define GRTC_INTENSET0_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
28425   #define GRTC_INTENSET0_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
28426   #define GRTC_INTENSET0_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
28427   #define GRTC_INTENSET0_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
28428   #define GRTC_INTENSET0_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
28429 
28430 
28431 /* GRTC_INTENCLR0: Disable interrupt */
28432   #define GRTC_INTENCLR0_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR0 register.                                   */
28433 
28434 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
28435   #define GRTC_INTENCLR0_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
28436   #define GRTC_INTENCLR0_COMPARE0_Msk (0x1UL << GRTC_INTENCLR0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
28437   #define GRTC_INTENCLR0_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
28438   #define GRTC_INTENCLR0_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
28439   #define GRTC_INTENCLR0_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
28440   #define GRTC_INTENCLR0_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28441   #define GRTC_INTENCLR0_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28442 
28443 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
28444   #define GRTC_INTENCLR0_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
28445   #define GRTC_INTENCLR0_COMPARE1_Msk (0x1UL << GRTC_INTENCLR0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
28446   #define GRTC_INTENCLR0_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
28447   #define GRTC_INTENCLR0_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
28448   #define GRTC_INTENCLR0_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
28449   #define GRTC_INTENCLR0_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28450   #define GRTC_INTENCLR0_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28451 
28452 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
28453   #define GRTC_INTENCLR0_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
28454   #define GRTC_INTENCLR0_COMPARE2_Msk (0x1UL << GRTC_INTENCLR0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
28455   #define GRTC_INTENCLR0_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
28456   #define GRTC_INTENCLR0_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
28457   #define GRTC_INTENCLR0_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
28458   #define GRTC_INTENCLR0_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28459   #define GRTC_INTENCLR0_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28460 
28461 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
28462   #define GRTC_INTENCLR0_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
28463   #define GRTC_INTENCLR0_COMPARE3_Msk (0x1UL << GRTC_INTENCLR0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
28464   #define GRTC_INTENCLR0_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
28465   #define GRTC_INTENCLR0_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
28466   #define GRTC_INTENCLR0_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
28467   #define GRTC_INTENCLR0_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28468   #define GRTC_INTENCLR0_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28469 
28470 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
28471   #define GRTC_INTENCLR0_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
28472   #define GRTC_INTENCLR0_COMPARE4_Msk (0x1UL << GRTC_INTENCLR0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
28473   #define GRTC_INTENCLR0_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
28474   #define GRTC_INTENCLR0_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
28475   #define GRTC_INTENCLR0_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
28476   #define GRTC_INTENCLR0_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28477   #define GRTC_INTENCLR0_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28478 
28479 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
28480   #define GRTC_INTENCLR0_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
28481   #define GRTC_INTENCLR0_COMPARE5_Msk (0x1UL << GRTC_INTENCLR0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
28482   #define GRTC_INTENCLR0_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
28483   #define GRTC_INTENCLR0_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
28484   #define GRTC_INTENCLR0_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
28485   #define GRTC_INTENCLR0_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28486   #define GRTC_INTENCLR0_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28487 
28488 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
28489   #define GRTC_INTENCLR0_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
28490   #define GRTC_INTENCLR0_COMPARE6_Msk (0x1UL << GRTC_INTENCLR0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
28491   #define GRTC_INTENCLR0_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
28492   #define GRTC_INTENCLR0_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
28493   #define GRTC_INTENCLR0_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
28494   #define GRTC_INTENCLR0_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28495   #define GRTC_INTENCLR0_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28496 
28497 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
28498   #define GRTC_INTENCLR0_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
28499   #define GRTC_INTENCLR0_COMPARE7_Msk (0x1UL << GRTC_INTENCLR0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
28500   #define GRTC_INTENCLR0_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
28501   #define GRTC_INTENCLR0_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
28502   #define GRTC_INTENCLR0_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
28503   #define GRTC_INTENCLR0_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28504   #define GRTC_INTENCLR0_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28505 
28506 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
28507   #define GRTC_INTENCLR0_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
28508   #define GRTC_INTENCLR0_COMPARE8_Msk (0x1UL << GRTC_INTENCLR0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
28509   #define GRTC_INTENCLR0_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
28510   #define GRTC_INTENCLR0_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
28511   #define GRTC_INTENCLR0_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
28512   #define GRTC_INTENCLR0_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28513   #define GRTC_INTENCLR0_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28514 
28515 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
28516   #define GRTC_INTENCLR0_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
28517   #define GRTC_INTENCLR0_COMPARE9_Msk (0x1UL << GRTC_INTENCLR0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
28518   #define GRTC_INTENCLR0_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
28519   #define GRTC_INTENCLR0_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
28520   #define GRTC_INTENCLR0_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
28521   #define GRTC_INTENCLR0_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28522   #define GRTC_INTENCLR0_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28523 
28524 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
28525   #define GRTC_INTENCLR0_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
28526   #define GRTC_INTENCLR0_COMPARE10_Msk (0x1UL << GRTC_INTENCLR0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
28527   #define GRTC_INTENCLR0_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
28528   #define GRTC_INTENCLR0_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
28529   #define GRTC_INTENCLR0_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
28530   #define GRTC_INTENCLR0_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28531   #define GRTC_INTENCLR0_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28532 
28533 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
28534   #define GRTC_INTENCLR0_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
28535   #define GRTC_INTENCLR0_COMPARE11_Msk (0x1UL << GRTC_INTENCLR0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
28536   #define GRTC_INTENCLR0_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
28537   #define GRTC_INTENCLR0_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
28538   #define GRTC_INTENCLR0_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
28539   #define GRTC_INTENCLR0_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28540   #define GRTC_INTENCLR0_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28541 
28542 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
28543   #define GRTC_INTENCLR0_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
28544   #define GRTC_INTENCLR0_COMPARE12_Msk (0x1UL << GRTC_INTENCLR0_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
28545   #define GRTC_INTENCLR0_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
28546   #define GRTC_INTENCLR0_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
28547   #define GRTC_INTENCLR0_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
28548   #define GRTC_INTENCLR0_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28549   #define GRTC_INTENCLR0_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28550 
28551 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
28552   #define GRTC_INTENCLR0_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
28553   #define GRTC_INTENCLR0_COMPARE13_Msk (0x1UL << GRTC_INTENCLR0_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
28554   #define GRTC_INTENCLR0_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
28555   #define GRTC_INTENCLR0_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
28556   #define GRTC_INTENCLR0_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
28557   #define GRTC_INTENCLR0_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28558   #define GRTC_INTENCLR0_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28559 
28560 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
28561   #define GRTC_INTENCLR0_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
28562   #define GRTC_INTENCLR0_COMPARE14_Msk (0x1UL << GRTC_INTENCLR0_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
28563   #define GRTC_INTENCLR0_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
28564   #define GRTC_INTENCLR0_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
28565   #define GRTC_INTENCLR0_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
28566   #define GRTC_INTENCLR0_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28567   #define GRTC_INTENCLR0_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28568 
28569 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
28570   #define GRTC_INTENCLR0_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
28571   #define GRTC_INTENCLR0_COMPARE15_Msk (0x1UL << GRTC_INTENCLR0_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
28572   #define GRTC_INTENCLR0_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
28573   #define GRTC_INTENCLR0_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
28574   #define GRTC_INTENCLR0_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
28575   #define GRTC_INTENCLR0_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28576   #define GRTC_INTENCLR0_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28577 
28578 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
28579   #define GRTC_INTENCLR0_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
28580   #define GRTC_INTENCLR0_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR0_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
28581                                                                             field.*/
28582   #define GRTC_INTENCLR0_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
28583   #define GRTC_INTENCLR0_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
28584   #define GRTC_INTENCLR0_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
28585   #define GRTC_INTENCLR0_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
28586   #define GRTC_INTENCLR0_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
28587 
28588 
28589 /* GRTC_INTPEND0: Pending interrupts */
28590   #define GRTC_INTPEND0_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND0 register.                                    */
28591 
28592 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
28593   #define GRTC_INTPEND0_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
28594   #define GRTC_INTPEND0_COMPARE0_Msk (0x1UL << GRTC_INTPEND0_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
28595   #define GRTC_INTPEND0_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
28596   #define GRTC_INTPEND0_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
28597   #define GRTC_INTPEND0_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28598   #define GRTC_INTPEND0_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
28599 
28600 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
28601   #define GRTC_INTPEND0_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
28602   #define GRTC_INTPEND0_COMPARE1_Msk (0x1UL << GRTC_INTPEND0_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
28603   #define GRTC_INTPEND0_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
28604   #define GRTC_INTPEND0_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
28605   #define GRTC_INTPEND0_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28606   #define GRTC_INTPEND0_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
28607 
28608 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
28609   #define GRTC_INTPEND0_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
28610   #define GRTC_INTPEND0_COMPARE2_Msk (0x1UL << GRTC_INTPEND0_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
28611   #define GRTC_INTPEND0_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
28612   #define GRTC_INTPEND0_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
28613   #define GRTC_INTPEND0_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28614   #define GRTC_INTPEND0_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
28615 
28616 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
28617   #define GRTC_INTPEND0_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
28618   #define GRTC_INTPEND0_COMPARE3_Msk (0x1UL << GRTC_INTPEND0_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
28619   #define GRTC_INTPEND0_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
28620   #define GRTC_INTPEND0_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
28621   #define GRTC_INTPEND0_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28622   #define GRTC_INTPEND0_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
28623 
28624 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
28625   #define GRTC_INTPEND0_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
28626   #define GRTC_INTPEND0_COMPARE4_Msk (0x1UL << GRTC_INTPEND0_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
28627   #define GRTC_INTPEND0_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
28628   #define GRTC_INTPEND0_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
28629   #define GRTC_INTPEND0_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28630   #define GRTC_INTPEND0_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
28631 
28632 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
28633   #define GRTC_INTPEND0_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
28634   #define GRTC_INTPEND0_COMPARE5_Msk (0x1UL << GRTC_INTPEND0_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
28635   #define GRTC_INTPEND0_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
28636   #define GRTC_INTPEND0_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
28637   #define GRTC_INTPEND0_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28638   #define GRTC_INTPEND0_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
28639 
28640 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
28641   #define GRTC_INTPEND0_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
28642   #define GRTC_INTPEND0_COMPARE6_Msk (0x1UL << GRTC_INTPEND0_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
28643   #define GRTC_INTPEND0_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
28644   #define GRTC_INTPEND0_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
28645   #define GRTC_INTPEND0_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28646   #define GRTC_INTPEND0_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
28647 
28648 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
28649   #define GRTC_INTPEND0_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
28650   #define GRTC_INTPEND0_COMPARE7_Msk (0x1UL << GRTC_INTPEND0_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
28651   #define GRTC_INTPEND0_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
28652   #define GRTC_INTPEND0_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
28653   #define GRTC_INTPEND0_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28654   #define GRTC_INTPEND0_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
28655 
28656 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
28657   #define GRTC_INTPEND0_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
28658   #define GRTC_INTPEND0_COMPARE8_Msk (0x1UL << GRTC_INTPEND0_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
28659   #define GRTC_INTPEND0_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
28660   #define GRTC_INTPEND0_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
28661   #define GRTC_INTPEND0_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28662   #define GRTC_INTPEND0_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
28663 
28664 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
28665   #define GRTC_INTPEND0_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
28666   #define GRTC_INTPEND0_COMPARE9_Msk (0x1UL << GRTC_INTPEND0_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
28667   #define GRTC_INTPEND0_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
28668   #define GRTC_INTPEND0_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
28669   #define GRTC_INTPEND0_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
28670   #define GRTC_INTPEND0_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
28671 
28672 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
28673   #define GRTC_INTPEND0_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
28674   #define GRTC_INTPEND0_COMPARE10_Msk (0x1UL << GRTC_INTPEND0_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
28675   #define GRTC_INTPEND0_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
28676   #define GRTC_INTPEND0_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
28677   #define GRTC_INTPEND0_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
28678   #define GRTC_INTPEND0_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
28679 
28680 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
28681   #define GRTC_INTPEND0_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
28682   #define GRTC_INTPEND0_COMPARE11_Msk (0x1UL << GRTC_INTPEND0_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
28683   #define GRTC_INTPEND0_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
28684   #define GRTC_INTPEND0_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
28685   #define GRTC_INTPEND0_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
28686   #define GRTC_INTPEND0_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
28687 
28688 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
28689   #define GRTC_INTPEND0_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
28690   #define GRTC_INTPEND0_COMPARE12_Msk (0x1UL << GRTC_INTPEND0_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
28691   #define GRTC_INTPEND0_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
28692   #define GRTC_INTPEND0_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
28693   #define GRTC_INTPEND0_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
28694   #define GRTC_INTPEND0_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
28695 
28696 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
28697   #define GRTC_INTPEND0_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
28698   #define GRTC_INTPEND0_COMPARE13_Msk (0x1UL << GRTC_INTPEND0_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
28699   #define GRTC_INTPEND0_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
28700   #define GRTC_INTPEND0_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
28701   #define GRTC_INTPEND0_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
28702   #define GRTC_INTPEND0_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
28703 
28704 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
28705   #define GRTC_INTPEND0_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
28706   #define GRTC_INTPEND0_COMPARE14_Msk (0x1UL << GRTC_INTPEND0_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
28707   #define GRTC_INTPEND0_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
28708   #define GRTC_INTPEND0_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
28709   #define GRTC_INTPEND0_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
28710   #define GRTC_INTPEND0_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
28711 
28712 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
28713   #define GRTC_INTPEND0_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
28714   #define GRTC_INTPEND0_COMPARE15_Msk (0x1UL << GRTC_INTPEND0_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
28715   #define GRTC_INTPEND0_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
28716   #define GRTC_INTPEND0_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
28717   #define GRTC_INTPEND0_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
28718   #define GRTC_INTPEND0_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
28719 
28720 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
28721   #define GRTC_INTPEND0_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
28722   #define GRTC_INTPEND0_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND0_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
28723                                                                             field.*/
28724   #define GRTC_INTPEND0_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
28725   #define GRTC_INTPEND0_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
28726   #define GRTC_INTPEND0_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
28727   #define GRTC_INTPEND0_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
28728 
28729 
28730 /* GRTC_INTEN1: Enable or disable interrupt */
28731   #define GRTC_INTEN1_ResetValue (0x00000000UL)      /*!< Reset value of INTEN1 register.                                      */
28732 
28733 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
28734   #define GRTC_INTEN1_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
28735   #define GRTC_INTEN1_COMPARE0_Msk (0x1UL << GRTC_INTEN1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
28736   #define GRTC_INTEN1_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
28737   #define GRTC_INTEN1_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
28738   #define GRTC_INTEN1_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
28739   #define GRTC_INTEN1_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
28740 
28741 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
28742   #define GRTC_INTEN1_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
28743   #define GRTC_INTEN1_COMPARE1_Msk (0x1UL << GRTC_INTEN1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
28744   #define GRTC_INTEN1_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
28745   #define GRTC_INTEN1_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
28746   #define GRTC_INTEN1_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
28747   #define GRTC_INTEN1_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
28748 
28749 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
28750   #define GRTC_INTEN1_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
28751   #define GRTC_INTEN1_COMPARE2_Msk (0x1UL << GRTC_INTEN1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
28752   #define GRTC_INTEN1_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
28753   #define GRTC_INTEN1_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
28754   #define GRTC_INTEN1_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
28755   #define GRTC_INTEN1_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
28756 
28757 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
28758   #define GRTC_INTEN1_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
28759   #define GRTC_INTEN1_COMPARE3_Msk (0x1UL << GRTC_INTEN1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
28760   #define GRTC_INTEN1_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
28761   #define GRTC_INTEN1_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
28762   #define GRTC_INTEN1_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
28763   #define GRTC_INTEN1_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
28764 
28765 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
28766   #define GRTC_INTEN1_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
28767   #define GRTC_INTEN1_COMPARE4_Msk (0x1UL << GRTC_INTEN1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
28768   #define GRTC_INTEN1_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
28769   #define GRTC_INTEN1_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
28770   #define GRTC_INTEN1_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
28771   #define GRTC_INTEN1_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
28772 
28773 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
28774   #define GRTC_INTEN1_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
28775   #define GRTC_INTEN1_COMPARE5_Msk (0x1UL << GRTC_INTEN1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
28776   #define GRTC_INTEN1_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
28777   #define GRTC_INTEN1_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
28778   #define GRTC_INTEN1_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
28779   #define GRTC_INTEN1_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
28780 
28781 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
28782   #define GRTC_INTEN1_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
28783   #define GRTC_INTEN1_COMPARE6_Msk (0x1UL << GRTC_INTEN1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
28784   #define GRTC_INTEN1_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
28785   #define GRTC_INTEN1_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
28786   #define GRTC_INTEN1_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
28787   #define GRTC_INTEN1_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
28788 
28789 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
28790   #define GRTC_INTEN1_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
28791   #define GRTC_INTEN1_COMPARE7_Msk (0x1UL << GRTC_INTEN1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
28792   #define GRTC_INTEN1_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
28793   #define GRTC_INTEN1_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
28794   #define GRTC_INTEN1_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
28795   #define GRTC_INTEN1_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
28796 
28797 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
28798   #define GRTC_INTEN1_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
28799   #define GRTC_INTEN1_COMPARE8_Msk (0x1UL << GRTC_INTEN1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
28800   #define GRTC_INTEN1_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
28801   #define GRTC_INTEN1_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
28802   #define GRTC_INTEN1_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
28803   #define GRTC_INTEN1_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
28804 
28805 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
28806   #define GRTC_INTEN1_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
28807   #define GRTC_INTEN1_COMPARE9_Msk (0x1UL << GRTC_INTEN1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
28808   #define GRTC_INTEN1_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
28809   #define GRTC_INTEN1_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
28810   #define GRTC_INTEN1_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
28811   #define GRTC_INTEN1_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
28812 
28813 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
28814   #define GRTC_INTEN1_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
28815   #define GRTC_INTEN1_COMPARE10_Msk (0x1UL << GRTC_INTEN1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
28816   #define GRTC_INTEN1_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
28817   #define GRTC_INTEN1_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
28818   #define GRTC_INTEN1_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
28819   #define GRTC_INTEN1_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
28820 
28821 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
28822   #define GRTC_INTEN1_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
28823   #define GRTC_INTEN1_COMPARE11_Msk (0x1UL << GRTC_INTEN1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
28824   #define GRTC_INTEN1_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
28825   #define GRTC_INTEN1_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
28826   #define GRTC_INTEN1_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
28827   #define GRTC_INTEN1_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
28828 
28829 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
28830   #define GRTC_INTEN1_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
28831   #define GRTC_INTEN1_COMPARE12_Msk (0x1UL << GRTC_INTEN1_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
28832   #define GRTC_INTEN1_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
28833   #define GRTC_INTEN1_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
28834   #define GRTC_INTEN1_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
28835   #define GRTC_INTEN1_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
28836 
28837 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
28838   #define GRTC_INTEN1_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
28839   #define GRTC_INTEN1_COMPARE13_Msk (0x1UL << GRTC_INTEN1_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
28840   #define GRTC_INTEN1_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
28841   #define GRTC_INTEN1_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
28842   #define GRTC_INTEN1_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
28843   #define GRTC_INTEN1_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
28844 
28845 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
28846   #define GRTC_INTEN1_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
28847   #define GRTC_INTEN1_COMPARE14_Msk (0x1UL << GRTC_INTEN1_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
28848   #define GRTC_INTEN1_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
28849   #define GRTC_INTEN1_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
28850   #define GRTC_INTEN1_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
28851   #define GRTC_INTEN1_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
28852 
28853 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
28854   #define GRTC_INTEN1_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
28855   #define GRTC_INTEN1_COMPARE15_Msk (0x1UL << GRTC_INTEN1_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
28856   #define GRTC_INTEN1_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
28857   #define GRTC_INTEN1_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
28858   #define GRTC_INTEN1_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
28859   #define GRTC_INTEN1_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
28860 
28861 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
28862   #define GRTC_INTEN1_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
28863   #define GRTC_INTEN1_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN1_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
28864   #define GRTC_INTEN1_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
28865   #define GRTC_INTEN1_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
28866   #define GRTC_INTEN1_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
28867   #define GRTC_INTEN1_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
28868 
28869 
28870 /* GRTC_INTENSET1: Enable interrupt */
28871   #define GRTC_INTENSET1_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET1 register.                                   */
28872 
28873 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
28874   #define GRTC_INTENSET1_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
28875   #define GRTC_INTENSET1_COMPARE0_Msk (0x1UL << GRTC_INTENSET1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
28876   #define GRTC_INTENSET1_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
28877   #define GRTC_INTENSET1_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
28878   #define GRTC_INTENSET1_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
28879   #define GRTC_INTENSET1_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28880   #define GRTC_INTENSET1_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28881 
28882 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
28883   #define GRTC_INTENSET1_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
28884   #define GRTC_INTENSET1_COMPARE1_Msk (0x1UL << GRTC_INTENSET1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
28885   #define GRTC_INTENSET1_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
28886   #define GRTC_INTENSET1_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
28887   #define GRTC_INTENSET1_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
28888   #define GRTC_INTENSET1_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28889   #define GRTC_INTENSET1_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28890 
28891 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
28892   #define GRTC_INTENSET1_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
28893   #define GRTC_INTENSET1_COMPARE2_Msk (0x1UL << GRTC_INTENSET1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
28894   #define GRTC_INTENSET1_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
28895   #define GRTC_INTENSET1_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
28896   #define GRTC_INTENSET1_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
28897   #define GRTC_INTENSET1_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28898   #define GRTC_INTENSET1_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28899 
28900 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
28901   #define GRTC_INTENSET1_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
28902   #define GRTC_INTENSET1_COMPARE3_Msk (0x1UL << GRTC_INTENSET1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
28903   #define GRTC_INTENSET1_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
28904   #define GRTC_INTENSET1_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
28905   #define GRTC_INTENSET1_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
28906   #define GRTC_INTENSET1_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28907   #define GRTC_INTENSET1_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28908 
28909 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
28910   #define GRTC_INTENSET1_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
28911   #define GRTC_INTENSET1_COMPARE4_Msk (0x1UL << GRTC_INTENSET1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
28912   #define GRTC_INTENSET1_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
28913   #define GRTC_INTENSET1_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
28914   #define GRTC_INTENSET1_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
28915   #define GRTC_INTENSET1_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28916   #define GRTC_INTENSET1_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28917 
28918 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
28919   #define GRTC_INTENSET1_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
28920   #define GRTC_INTENSET1_COMPARE5_Msk (0x1UL << GRTC_INTENSET1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
28921   #define GRTC_INTENSET1_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
28922   #define GRTC_INTENSET1_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
28923   #define GRTC_INTENSET1_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
28924   #define GRTC_INTENSET1_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28925   #define GRTC_INTENSET1_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28926 
28927 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
28928   #define GRTC_INTENSET1_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
28929   #define GRTC_INTENSET1_COMPARE6_Msk (0x1UL << GRTC_INTENSET1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
28930   #define GRTC_INTENSET1_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
28931   #define GRTC_INTENSET1_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
28932   #define GRTC_INTENSET1_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
28933   #define GRTC_INTENSET1_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28934   #define GRTC_INTENSET1_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28935 
28936 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
28937   #define GRTC_INTENSET1_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
28938   #define GRTC_INTENSET1_COMPARE7_Msk (0x1UL << GRTC_INTENSET1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
28939   #define GRTC_INTENSET1_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
28940   #define GRTC_INTENSET1_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
28941   #define GRTC_INTENSET1_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
28942   #define GRTC_INTENSET1_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28943   #define GRTC_INTENSET1_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28944 
28945 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
28946   #define GRTC_INTENSET1_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
28947   #define GRTC_INTENSET1_COMPARE8_Msk (0x1UL << GRTC_INTENSET1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
28948   #define GRTC_INTENSET1_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
28949   #define GRTC_INTENSET1_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
28950   #define GRTC_INTENSET1_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
28951   #define GRTC_INTENSET1_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28952   #define GRTC_INTENSET1_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28953 
28954 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
28955   #define GRTC_INTENSET1_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
28956   #define GRTC_INTENSET1_COMPARE9_Msk (0x1UL << GRTC_INTENSET1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
28957   #define GRTC_INTENSET1_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
28958   #define GRTC_INTENSET1_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
28959   #define GRTC_INTENSET1_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
28960   #define GRTC_INTENSET1_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
28961   #define GRTC_INTENSET1_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
28962 
28963 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
28964   #define GRTC_INTENSET1_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
28965   #define GRTC_INTENSET1_COMPARE10_Msk (0x1UL << GRTC_INTENSET1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
28966   #define GRTC_INTENSET1_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
28967   #define GRTC_INTENSET1_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
28968   #define GRTC_INTENSET1_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
28969   #define GRTC_INTENSET1_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28970   #define GRTC_INTENSET1_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28971 
28972 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
28973   #define GRTC_INTENSET1_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
28974   #define GRTC_INTENSET1_COMPARE11_Msk (0x1UL << GRTC_INTENSET1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
28975   #define GRTC_INTENSET1_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
28976   #define GRTC_INTENSET1_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
28977   #define GRTC_INTENSET1_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
28978   #define GRTC_INTENSET1_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28979   #define GRTC_INTENSET1_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28980 
28981 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
28982   #define GRTC_INTENSET1_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
28983   #define GRTC_INTENSET1_COMPARE12_Msk (0x1UL << GRTC_INTENSET1_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
28984   #define GRTC_INTENSET1_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
28985   #define GRTC_INTENSET1_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
28986   #define GRTC_INTENSET1_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
28987   #define GRTC_INTENSET1_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28988   #define GRTC_INTENSET1_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28989 
28990 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
28991   #define GRTC_INTENSET1_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
28992   #define GRTC_INTENSET1_COMPARE13_Msk (0x1UL << GRTC_INTENSET1_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
28993   #define GRTC_INTENSET1_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
28994   #define GRTC_INTENSET1_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
28995   #define GRTC_INTENSET1_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
28996   #define GRTC_INTENSET1_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
28997   #define GRTC_INTENSET1_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
28998 
28999 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
29000   #define GRTC_INTENSET1_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
29001   #define GRTC_INTENSET1_COMPARE14_Msk (0x1UL << GRTC_INTENSET1_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
29002   #define GRTC_INTENSET1_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
29003   #define GRTC_INTENSET1_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
29004   #define GRTC_INTENSET1_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
29005   #define GRTC_INTENSET1_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29006   #define GRTC_INTENSET1_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29007 
29008 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
29009   #define GRTC_INTENSET1_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
29010   #define GRTC_INTENSET1_COMPARE15_Msk (0x1UL << GRTC_INTENSET1_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
29011   #define GRTC_INTENSET1_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
29012   #define GRTC_INTENSET1_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
29013   #define GRTC_INTENSET1_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
29014   #define GRTC_INTENSET1_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29015   #define GRTC_INTENSET1_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29016 
29017 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
29018   #define GRTC_INTENSET1_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
29019   #define GRTC_INTENSET1_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET1_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
29020                                                                             field.*/
29021   #define GRTC_INTENSET1_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
29022   #define GRTC_INTENSET1_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
29023   #define GRTC_INTENSET1_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
29024   #define GRTC_INTENSET1_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
29025   #define GRTC_INTENSET1_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
29026 
29027 
29028 /* GRTC_INTENCLR1: Disable interrupt */
29029   #define GRTC_INTENCLR1_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR1 register.                                   */
29030 
29031 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
29032   #define GRTC_INTENCLR1_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
29033   #define GRTC_INTENCLR1_COMPARE0_Msk (0x1UL << GRTC_INTENCLR1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
29034   #define GRTC_INTENCLR1_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
29035   #define GRTC_INTENCLR1_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
29036   #define GRTC_INTENCLR1_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
29037   #define GRTC_INTENCLR1_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29038   #define GRTC_INTENCLR1_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29039 
29040 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
29041   #define GRTC_INTENCLR1_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
29042   #define GRTC_INTENCLR1_COMPARE1_Msk (0x1UL << GRTC_INTENCLR1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
29043   #define GRTC_INTENCLR1_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
29044   #define GRTC_INTENCLR1_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
29045   #define GRTC_INTENCLR1_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
29046   #define GRTC_INTENCLR1_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29047   #define GRTC_INTENCLR1_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29048 
29049 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
29050   #define GRTC_INTENCLR1_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
29051   #define GRTC_INTENCLR1_COMPARE2_Msk (0x1UL << GRTC_INTENCLR1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
29052   #define GRTC_INTENCLR1_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
29053   #define GRTC_INTENCLR1_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
29054   #define GRTC_INTENCLR1_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
29055   #define GRTC_INTENCLR1_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29056   #define GRTC_INTENCLR1_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29057 
29058 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
29059   #define GRTC_INTENCLR1_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
29060   #define GRTC_INTENCLR1_COMPARE3_Msk (0x1UL << GRTC_INTENCLR1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
29061   #define GRTC_INTENCLR1_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
29062   #define GRTC_INTENCLR1_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
29063   #define GRTC_INTENCLR1_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
29064   #define GRTC_INTENCLR1_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29065   #define GRTC_INTENCLR1_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29066 
29067 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
29068   #define GRTC_INTENCLR1_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
29069   #define GRTC_INTENCLR1_COMPARE4_Msk (0x1UL << GRTC_INTENCLR1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
29070   #define GRTC_INTENCLR1_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
29071   #define GRTC_INTENCLR1_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
29072   #define GRTC_INTENCLR1_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
29073   #define GRTC_INTENCLR1_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29074   #define GRTC_INTENCLR1_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29075 
29076 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
29077   #define GRTC_INTENCLR1_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
29078   #define GRTC_INTENCLR1_COMPARE5_Msk (0x1UL << GRTC_INTENCLR1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
29079   #define GRTC_INTENCLR1_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
29080   #define GRTC_INTENCLR1_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
29081   #define GRTC_INTENCLR1_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
29082   #define GRTC_INTENCLR1_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29083   #define GRTC_INTENCLR1_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29084 
29085 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
29086   #define GRTC_INTENCLR1_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
29087   #define GRTC_INTENCLR1_COMPARE6_Msk (0x1UL << GRTC_INTENCLR1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
29088   #define GRTC_INTENCLR1_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
29089   #define GRTC_INTENCLR1_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
29090   #define GRTC_INTENCLR1_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
29091   #define GRTC_INTENCLR1_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29092   #define GRTC_INTENCLR1_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29093 
29094 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
29095   #define GRTC_INTENCLR1_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
29096   #define GRTC_INTENCLR1_COMPARE7_Msk (0x1UL << GRTC_INTENCLR1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
29097   #define GRTC_INTENCLR1_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
29098   #define GRTC_INTENCLR1_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
29099   #define GRTC_INTENCLR1_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
29100   #define GRTC_INTENCLR1_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29101   #define GRTC_INTENCLR1_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29102 
29103 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
29104   #define GRTC_INTENCLR1_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
29105   #define GRTC_INTENCLR1_COMPARE8_Msk (0x1UL << GRTC_INTENCLR1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
29106   #define GRTC_INTENCLR1_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
29107   #define GRTC_INTENCLR1_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
29108   #define GRTC_INTENCLR1_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
29109   #define GRTC_INTENCLR1_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29110   #define GRTC_INTENCLR1_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29111 
29112 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
29113   #define GRTC_INTENCLR1_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
29114   #define GRTC_INTENCLR1_COMPARE9_Msk (0x1UL << GRTC_INTENCLR1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
29115   #define GRTC_INTENCLR1_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
29116   #define GRTC_INTENCLR1_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
29117   #define GRTC_INTENCLR1_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
29118   #define GRTC_INTENCLR1_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29119   #define GRTC_INTENCLR1_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29120 
29121 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
29122   #define GRTC_INTENCLR1_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
29123   #define GRTC_INTENCLR1_COMPARE10_Msk (0x1UL << GRTC_INTENCLR1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
29124   #define GRTC_INTENCLR1_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
29125   #define GRTC_INTENCLR1_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
29126   #define GRTC_INTENCLR1_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
29127   #define GRTC_INTENCLR1_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29128   #define GRTC_INTENCLR1_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29129 
29130 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
29131   #define GRTC_INTENCLR1_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
29132   #define GRTC_INTENCLR1_COMPARE11_Msk (0x1UL << GRTC_INTENCLR1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
29133   #define GRTC_INTENCLR1_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
29134   #define GRTC_INTENCLR1_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
29135   #define GRTC_INTENCLR1_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
29136   #define GRTC_INTENCLR1_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29137   #define GRTC_INTENCLR1_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29138 
29139 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
29140   #define GRTC_INTENCLR1_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
29141   #define GRTC_INTENCLR1_COMPARE12_Msk (0x1UL << GRTC_INTENCLR1_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
29142   #define GRTC_INTENCLR1_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
29143   #define GRTC_INTENCLR1_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
29144   #define GRTC_INTENCLR1_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
29145   #define GRTC_INTENCLR1_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29146   #define GRTC_INTENCLR1_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29147 
29148 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
29149   #define GRTC_INTENCLR1_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
29150   #define GRTC_INTENCLR1_COMPARE13_Msk (0x1UL << GRTC_INTENCLR1_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
29151   #define GRTC_INTENCLR1_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
29152   #define GRTC_INTENCLR1_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
29153   #define GRTC_INTENCLR1_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
29154   #define GRTC_INTENCLR1_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29155   #define GRTC_INTENCLR1_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29156 
29157 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
29158   #define GRTC_INTENCLR1_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
29159   #define GRTC_INTENCLR1_COMPARE14_Msk (0x1UL << GRTC_INTENCLR1_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
29160   #define GRTC_INTENCLR1_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
29161   #define GRTC_INTENCLR1_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
29162   #define GRTC_INTENCLR1_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
29163   #define GRTC_INTENCLR1_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29164   #define GRTC_INTENCLR1_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29165 
29166 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
29167   #define GRTC_INTENCLR1_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
29168   #define GRTC_INTENCLR1_COMPARE15_Msk (0x1UL << GRTC_INTENCLR1_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
29169   #define GRTC_INTENCLR1_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
29170   #define GRTC_INTENCLR1_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
29171   #define GRTC_INTENCLR1_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
29172   #define GRTC_INTENCLR1_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29173   #define GRTC_INTENCLR1_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29174 
29175 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
29176   #define GRTC_INTENCLR1_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
29177   #define GRTC_INTENCLR1_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR1_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
29178                                                                             field.*/
29179   #define GRTC_INTENCLR1_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
29180   #define GRTC_INTENCLR1_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
29181   #define GRTC_INTENCLR1_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
29182   #define GRTC_INTENCLR1_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
29183   #define GRTC_INTENCLR1_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
29184 
29185 
29186 /* GRTC_INTPEND1: Pending interrupts */
29187   #define GRTC_INTPEND1_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND1 register.                                    */
29188 
29189 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
29190   #define GRTC_INTPEND1_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
29191   #define GRTC_INTPEND1_COMPARE0_Msk (0x1UL << GRTC_INTPEND1_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
29192   #define GRTC_INTPEND1_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
29193   #define GRTC_INTPEND1_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
29194   #define GRTC_INTPEND1_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29195   #define GRTC_INTPEND1_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
29196 
29197 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
29198   #define GRTC_INTPEND1_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
29199   #define GRTC_INTPEND1_COMPARE1_Msk (0x1UL << GRTC_INTPEND1_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
29200   #define GRTC_INTPEND1_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
29201   #define GRTC_INTPEND1_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
29202   #define GRTC_INTPEND1_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29203   #define GRTC_INTPEND1_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
29204 
29205 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
29206   #define GRTC_INTPEND1_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
29207   #define GRTC_INTPEND1_COMPARE2_Msk (0x1UL << GRTC_INTPEND1_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
29208   #define GRTC_INTPEND1_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
29209   #define GRTC_INTPEND1_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
29210   #define GRTC_INTPEND1_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29211   #define GRTC_INTPEND1_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
29212 
29213 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
29214   #define GRTC_INTPEND1_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
29215   #define GRTC_INTPEND1_COMPARE3_Msk (0x1UL << GRTC_INTPEND1_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
29216   #define GRTC_INTPEND1_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
29217   #define GRTC_INTPEND1_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
29218   #define GRTC_INTPEND1_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29219   #define GRTC_INTPEND1_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
29220 
29221 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
29222   #define GRTC_INTPEND1_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
29223   #define GRTC_INTPEND1_COMPARE4_Msk (0x1UL << GRTC_INTPEND1_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
29224   #define GRTC_INTPEND1_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
29225   #define GRTC_INTPEND1_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
29226   #define GRTC_INTPEND1_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29227   #define GRTC_INTPEND1_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
29228 
29229 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
29230   #define GRTC_INTPEND1_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
29231   #define GRTC_INTPEND1_COMPARE5_Msk (0x1UL << GRTC_INTPEND1_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
29232   #define GRTC_INTPEND1_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
29233   #define GRTC_INTPEND1_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
29234   #define GRTC_INTPEND1_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29235   #define GRTC_INTPEND1_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
29236 
29237 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
29238   #define GRTC_INTPEND1_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
29239   #define GRTC_INTPEND1_COMPARE6_Msk (0x1UL << GRTC_INTPEND1_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
29240   #define GRTC_INTPEND1_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
29241   #define GRTC_INTPEND1_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
29242   #define GRTC_INTPEND1_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29243   #define GRTC_INTPEND1_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
29244 
29245 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
29246   #define GRTC_INTPEND1_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
29247   #define GRTC_INTPEND1_COMPARE7_Msk (0x1UL << GRTC_INTPEND1_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
29248   #define GRTC_INTPEND1_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
29249   #define GRTC_INTPEND1_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
29250   #define GRTC_INTPEND1_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29251   #define GRTC_INTPEND1_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
29252 
29253 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
29254   #define GRTC_INTPEND1_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
29255   #define GRTC_INTPEND1_COMPARE8_Msk (0x1UL << GRTC_INTPEND1_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
29256   #define GRTC_INTPEND1_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
29257   #define GRTC_INTPEND1_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
29258   #define GRTC_INTPEND1_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29259   #define GRTC_INTPEND1_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
29260 
29261 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
29262   #define GRTC_INTPEND1_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
29263   #define GRTC_INTPEND1_COMPARE9_Msk (0x1UL << GRTC_INTPEND1_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
29264   #define GRTC_INTPEND1_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
29265   #define GRTC_INTPEND1_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
29266   #define GRTC_INTPEND1_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29267   #define GRTC_INTPEND1_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
29268 
29269 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
29270   #define GRTC_INTPEND1_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
29271   #define GRTC_INTPEND1_COMPARE10_Msk (0x1UL << GRTC_INTPEND1_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
29272   #define GRTC_INTPEND1_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
29273   #define GRTC_INTPEND1_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
29274   #define GRTC_INTPEND1_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29275   #define GRTC_INTPEND1_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
29276 
29277 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
29278   #define GRTC_INTPEND1_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
29279   #define GRTC_INTPEND1_COMPARE11_Msk (0x1UL << GRTC_INTPEND1_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
29280   #define GRTC_INTPEND1_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
29281   #define GRTC_INTPEND1_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
29282   #define GRTC_INTPEND1_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29283   #define GRTC_INTPEND1_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
29284 
29285 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
29286   #define GRTC_INTPEND1_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
29287   #define GRTC_INTPEND1_COMPARE12_Msk (0x1UL << GRTC_INTPEND1_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
29288   #define GRTC_INTPEND1_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
29289   #define GRTC_INTPEND1_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
29290   #define GRTC_INTPEND1_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29291   #define GRTC_INTPEND1_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
29292 
29293 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
29294   #define GRTC_INTPEND1_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
29295   #define GRTC_INTPEND1_COMPARE13_Msk (0x1UL << GRTC_INTPEND1_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
29296   #define GRTC_INTPEND1_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
29297   #define GRTC_INTPEND1_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
29298   #define GRTC_INTPEND1_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29299   #define GRTC_INTPEND1_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
29300 
29301 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
29302   #define GRTC_INTPEND1_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
29303   #define GRTC_INTPEND1_COMPARE14_Msk (0x1UL << GRTC_INTPEND1_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
29304   #define GRTC_INTPEND1_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
29305   #define GRTC_INTPEND1_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
29306   #define GRTC_INTPEND1_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29307   #define GRTC_INTPEND1_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
29308 
29309 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
29310   #define GRTC_INTPEND1_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
29311   #define GRTC_INTPEND1_COMPARE15_Msk (0x1UL << GRTC_INTPEND1_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
29312   #define GRTC_INTPEND1_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
29313   #define GRTC_INTPEND1_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
29314   #define GRTC_INTPEND1_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29315   #define GRTC_INTPEND1_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
29316 
29317 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
29318   #define GRTC_INTPEND1_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
29319   #define GRTC_INTPEND1_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND1_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
29320                                                                             field.*/
29321   #define GRTC_INTPEND1_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
29322   #define GRTC_INTPEND1_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
29323   #define GRTC_INTPEND1_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
29324   #define GRTC_INTPEND1_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
29325 
29326 
29327 /* GRTC_INTEN2: Enable or disable interrupt */
29328   #define GRTC_INTEN2_ResetValue (0x00000000UL)      /*!< Reset value of INTEN2 register.                                      */
29329 
29330 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
29331   #define GRTC_INTEN2_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
29332   #define GRTC_INTEN2_COMPARE0_Msk (0x1UL << GRTC_INTEN2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
29333   #define GRTC_INTEN2_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
29334   #define GRTC_INTEN2_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
29335   #define GRTC_INTEN2_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
29336   #define GRTC_INTEN2_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
29337 
29338 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
29339   #define GRTC_INTEN2_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
29340   #define GRTC_INTEN2_COMPARE1_Msk (0x1UL << GRTC_INTEN2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
29341   #define GRTC_INTEN2_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
29342   #define GRTC_INTEN2_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
29343   #define GRTC_INTEN2_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
29344   #define GRTC_INTEN2_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
29345 
29346 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
29347   #define GRTC_INTEN2_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
29348   #define GRTC_INTEN2_COMPARE2_Msk (0x1UL << GRTC_INTEN2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
29349   #define GRTC_INTEN2_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
29350   #define GRTC_INTEN2_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
29351   #define GRTC_INTEN2_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
29352   #define GRTC_INTEN2_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
29353 
29354 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
29355   #define GRTC_INTEN2_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
29356   #define GRTC_INTEN2_COMPARE3_Msk (0x1UL << GRTC_INTEN2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
29357   #define GRTC_INTEN2_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
29358   #define GRTC_INTEN2_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
29359   #define GRTC_INTEN2_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
29360   #define GRTC_INTEN2_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
29361 
29362 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
29363   #define GRTC_INTEN2_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
29364   #define GRTC_INTEN2_COMPARE4_Msk (0x1UL << GRTC_INTEN2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
29365   #define GRTC_INTEN2_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
29366   #define GRTC_INTEN2_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
29367   #define GRTC_INTEN2_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
29368   #define GRTC_INTEN2_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
29369 
29370 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
29371   #define GRTC_INTEN2_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
29372   #define GRTC_INTEN2_COMPARE5_Msk (0x1UL << GRTC_INTEN2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
29373   #define GRTC_INTEN2_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
29374   #define GRTC_INTEN2_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
29375   #define GRTC_INTEN2_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
29376   #define GRTC_INTEN2_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
29377 
29378 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
29379   #define GRTC_INTEN2_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
29380   #define GRTC_INTEN2_COMPARE6_Msk (0x1UL << GRTC_INTEN2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
29381   #define GRTC_INTEN2_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
29382   #define GRTC_INTEN2_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
29383   #define GRTC_INTEN2_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
29384   #define GRTC_INTEN2_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
29385 
29386 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
29387   #define GRTC_INTEN2_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
29388   #define GRTC_INTEN2_COMPARE7_Msk (0x1UL << GRTC_INTEN2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
29389   #define GRTC_INTEN2_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
29390   #define GRTC_INTEN2_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
29391   #define GRTC_INTEN2_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
29392   #define GRTC_INTEN2_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
29393 
29394 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
29395   #define GRTC_INTEN2_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
29396   #define GRTC_INTEN2_COMPARE8_Msk (0x1UL << GRTC_INTEN2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
29397   #define GRTC_INTEN2_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
29398   #define GRTC_INTEN2_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
29399   #define GRTC_INTEN2_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
29400   #define GRTC_INTEN2_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
29401 
29402 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
29403   #define GRTC_INTEN2_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
29404   #define GRTC_INTEN2_COMPARE9_Msk (0x1UL << GRTC_INTEN2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
29405   #define GRTC_INTEN2_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
29406   #define GRTC_INTEN2_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
29407   #define GRTC_INTEN2_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
29408   #define GRTC_INTEN2_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
29409 
29410 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
29411   #define GRTC_INTEN2_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
29412   #define GRTC_INTEN2_COMPARE10_Msk (0x1UL << GRTC_INTEN2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
29413   #define GRTC_INTEN2_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
29414   #define GRTC_INTEN2_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
29415   #define GRTC_INTEN2_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
29416   #define GRTC_INTEN2_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
29417 
29418 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
29419   #define GRTC_INTEN2_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
29420   #define GRTC_INTEN2_COMPARE11_Msk (0x1UL << GRTC_INTEN2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
29421   #define GRTC_INTEN2_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
29422   #define GRTC_INTEN2_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
29423   #define GRTC_INTEN2_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
29424   #define GRTC_INTEN2_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
29425 
29426 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
29427   #define GRTC_INTEN2_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
29428   #define GRTC_INTEN2_COMPARE12_Msk (0x1UL << GRTC_INTEN2_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
29429   #define GRTC_INTEN2_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
29430   #define GRTC_INTEN2_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
29431   #define GRTC_INTEN2_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
29432   #define GRTC_INTEN2_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
29433 
29434 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
29435   #define GRTC_INTEN2_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
29436   #define GRTC_INTEN2_COMPARE13_Msk (0x1UL << GRTC_INTEN2_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
29437   #define GRTC_INTEN2_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
29438   #define GRTC_INTEN2_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
29439   #define GRTC_INTEN2_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
29440   #define GRTC_INTEN2_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
29441 
29442 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
29443   #define GRTC_INTEN2_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
29444   #define GRTC_INTEN2_COMPARE14_Msk (0x1UL << GRTC_INTEN2_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
29445   #define GRTC_INTEN2_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
29446   #define GRTC_INTEN2_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
29447   #define GRTC_INTEN2_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
29448   #define GRTC_INTEN2_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
29449 
29450 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
29451   #define GRTC_INTEN2_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
29452   #define GRTC_INTEN2_COMPARE15_Msk (0x1UL << GRTC_INTEN2_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
29453   #define GRTC_INTEN2_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
29454   #define GRTC_INTEN2_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
29455   #define GRTC_INTEN2_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
29456   #define GRTC_INTEN2_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
29457 
29458 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
29459   #define GRTC_INTEN2_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
29460   #define GRTC_INTEN2_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN2_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
29461   #define GRTC_INTEN2_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
29462   #define GRTC_INTEN2_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
29463   #define GRTC_INTEN2_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
29464   #define GRTC_INTEN2_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
29465 
29466 
29467 /* GRTC_INTENSET2: Enable interrupt */
29468   #define GRTC_INTENSET2_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET2 register.                                   */
29469 
29470 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
29471   #define GRTC_INTENSET2_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
29472   #define GRTC_INTENSET2_COMPARE0_Msk (0x1UL << GRTC_INTENSET2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
29473   #define GRTC_INTENSET2_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
29474   #define GRTC_INTENSET2_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
29475   #define GRTC_INTENSET2_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
29476   #define GRTC_INTENSET2_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29477   #define GRTC_INTENSET2_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29478 
29479 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
29480   #define GRTC_INTENSET2_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
29481   #define GRTC_INTENSET2_COMPARE1_Msk (0x1UL << GRTC_INTENSET2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
29482   #define GRTC_INTENSET2_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
29483   #define GRTC_INTENSET2_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
29484   #define GRTC_INTENSET2_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
29485   #define GRTC_INTENSET2_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29486   #define GRTC_INTENSET2_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29487 
29488 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
29489   #define GRTC_INTENSET2_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
29490   #define GRTC_INTENSET2_COMPARE2_Msk (0x1UL << GRTC_INTENSET2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
29491   #define GRTC_INTENSET2_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
29492   #define GRTC_INTENSET2_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
29493   #define GRTC_INTENSET2_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
29494   #define GRTC_INTENSET2_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29495   #define GRTC_INTENSET2_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29496 
29497 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
29498   #define GRTC_INTENSET2_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
29499   #define GRTC_INTENSET2_COMPARE3_Msk (0x1UL << GRTC_INTENSET2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
29500   #define GRTC_INTENSET2_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
29501   #define GRTC_INTENSET2_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
29502   #define GRTC_INTENSET2_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
29503   #define GRTC_INTENSET2_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29504   #define GRTC_INTENSET2_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29505 
29506 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
29507   #define GRTC_INTENSET2_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
29508   #define GRTC_INTENSET2_COMPARE4_Msk (0x1UL << GRTC_INTENSET2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
29509   #define GRTC_INTENSET2_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
29510   #define GRTC_INTENSET2_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
29511   #define GRTC_INTENSET2_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
29512   #define GRTC_INTENSET2_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29513   #define GRTC_INTENSET2_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29514 
29515 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
29516   #define GRTC_INTENSET2_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
29517   #define GRTC_INTENSET2_COMPARE5_Msk (0x1UL << GRTC_INTENSET2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
29518   #define GRTC_INTENSET2_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
29519   #define GRTC_INTENSET2_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
29520   #define GRTC_INTENSET2_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
29521   #define GRTC_INTENSET2_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29522   #define GRTC_INTENSET2_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29523 
29524 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
29525   #define GRTC_INTENSET2_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
29526   #define GRTC_INTENSET2_COMPARE6_Msk (0x1UL << GRTC_INTENSET2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
29527   #define GRTC_INTENSET2_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
29528   #define GRTC_INTENSET2_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
29529   #define GRTC_INTENSET2_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
29530   #define GRTC_INTENSET2_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29531   #define GRTC_INTENSET2_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29532 
29533 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
29534   #define GRTC_INTENSET2_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
29535   #define GRTC_INTENSET2_COMPARE7_Msk (0x1UL << GRTC_INTENSET2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
29536   #define GRTC_INTENSET2_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
29537   #define GRTC_INTENSET2_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
29538   #define GRTC_INTENSET2_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
29539   #define GRTC_INTENSET2_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29540   #define GRTC_INTENSET2_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29541 
29542 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
29543   #define GRTC_INTENSET2_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
29544   #define GRTC_INTENSET2_COMPARE8_Msk (0x1UL << GRTC_INTENSET2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
29545   #define GRTC_INTENSET2_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
29546   #define GRTC_INTENSET2_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
29547   #define GRTC_INTENSET2_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
29548   #define GRTC_INTENSET2_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29549   #define GRTC_INTENSET2_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29550 
29551 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
29552   #define GRTC_INTENSET2_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
29553   #define GRTC_INTENSET2_COMPARE9_Msk (0x1UL << GRTC_INTENSET2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
29554   #define GRTC_INTENSET2_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
29555   #define GRTC_INTENSET2_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
29556   #define GRTC_INTENSET2_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
29557   #define GRTC_INTENSET2_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29558   #define GRTC_INTENSET2_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29559 
29560 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
29561   #define GRTC_INTENSET2_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
29562   #define GRTC_INTENSET2_COMPARE10_Msk (0x1UL << GRTC_INTENSET2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
29563   #define GRTC_INTENSET2_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
29564   #define GRTC_INTENSET2_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
29565   #define GRTC_INTENSET2_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
29566   #define GRTC_INTENSET2_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29567   #define GRTC_INTENSET2_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29568 
29569 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
29570   #define GRTC_INTENSET2_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
29571   #define GRTC_INTENSET2_COMPARE11_Msk (0x1UL << GRTC_INTENSET2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
29572   #define GRTC_INTENSET2_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
29573   #define GRTC_INTENSET2_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
29574   #define GRTC_INTENSET2_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
29575   #define GRTC_INTENSET2_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29576   #define GRTC_INTENSET2_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29577 
29578 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
29579   #define GRTC_INTENSET2_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
29580   #define GRTC_INTENSET2_COMPARE12_Msk (0x1UL << GRTC_INTENSET2_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
29581   #define GRTC_INTENSET2_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
29582   #define GRTC_INTENSET2_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
29583   #define GRTC_INTENSET2_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
29584   #define GRTC_INTENSET2_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29585   #define GRTC_INTENSET2_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29586 
29587 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
29588   #define GRTC_INTENSET2_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
29589   #define GRTC_INTENSET2_COMPARE13_Msk (0x1UL << GRTC_INTENSET2_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
29590   #define GRTC_INTENSET2_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
29591   #define GRTC_INTENSET2_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
29592   #define GRTC_INTENSET2_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
29593   #define GRTC_INTENSET2_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29594   #define GRTC_INTENSET2_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29595 
29596 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
29597   #define GRTC_INTENSET2_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
29598   #define GRTC_INTENSET2_COMPARE14_Msk (0x1UL << GRTC_INTENSET2_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
29599   #define GRTC_INTENSET2_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
29600   #define GRTC_INTENSET2_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
29601   #define GRTC_INTENSET2_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
29602   #define GRTC_INTENSET2_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29603   #define GRTC_INTENSET2_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29604 
29605 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
29606   #define GRTC_INTENSET2_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
29607   #define GRTC_INTENSET2_COMPARE15_Msk (0x1UL << GRTC_INTENSET2_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
29608   #define GRTC_INTENSET2_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
29609   #define GRTC_INTENSET2_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
29610   #define GRTC_INTENSET2_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
29611   #define GRTC_INTENSET2_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29612   #define GRTC_INTENSET2_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29613 
29614 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
29615   #define GRTC_INTENSET2_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
29616   #define GRTC_INTENSET2_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET2_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
29617                                                                             field.*/
29618   #define GRTC_INTENSET2_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
29619   #define GRTC_INTENSET2_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
29620   #define GRTC_INTENSET2_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
29621   #define GRTC_INTENSET2_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
29622   #define GRTC_INTENSET2_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
29623 
29624 
29625 /* GRTC_INTENCLR2: Disable interrupt */
29626   #define GRTC_INTENCLR2_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR2 register.                                   */
29627 
29628 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
29629   #define GRTC_INTENCLR2_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
29630   #define GRTC_INTENCLR2_COMPARE0_Msk (0x1UL << GRTC_INTENCLR2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
29631   #define GRTC_INTENCLR2_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
29632   #define GRTC_INTENCLR2_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
29633   #define GRTC_INTENCLR2_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
29634   #define GRTC_INTENCLR2_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29635   #define GRTC_INTENCLR2_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29636 
29637 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
29638   #define GRTC_INTENCLR2_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
29639   #define GRTC_INTENCLR2_COMPARE1_Msk (0x1UL << GRTC_INTENCLR2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
29640   #define GRTC_INTENCLR2_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
29641   #define GRTC_INTENCLR2_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
29642   #define GRTC_INTENCLR2_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
29643   #define GRTC_INTENCLR2_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29644   #define GRTC_INTENCLR2_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29645 
29646 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
29647   #define GRTC_INTENCLR2_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
29648   #define GRTC_INTENCLR2_COMPARE2_Msk (0x1UL << GRTC_INTENCLR2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
29649   #define GRTC_INTENCLR2_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
29650   #define GRTC_INTENCLR2_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
29651   #define GRTC_INTENCLR2_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
29652   #define GRTC_INTENCLR2_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29653   #define GRTC_INTENCLR2_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29654 
29655 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
29656   #define GRTC_INTENCLR2_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
29657   #define GRTC_INTENCLR2_COMPARE3_Msk (0x1UL << GRTC_INTENCLR2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
29658   #define GRTC_INTENCLR2_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
29659   #define GRTC_INTENCLR2_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
29660   #define GRTC_INTENCLR2_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
29661   #define GRTC_INTENCLR2_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29662   #define GRTC_INTENCLR2_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29663 
29664 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
29665   #define GRTC_INTENCLR2_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
29666   #define GRTC_INTENCLR2_COMPARE4_Msk (0x1UL << GRTC_INTENCLR2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
29667   #define GRTC_INTENCLR2_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
29668   #define GRTC_INTENCLR2_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
29669   #define GRTC_INTENCLR2_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
29670   #define GRTC_INTENCLR2_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29671   #define GRTC_INTENCLR2_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29672 
29673 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
29674   #define GRTC_INTENCLR2_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
29675   #define GRTC_INTENCLR2_COMPARE5_Msk (0x1UL << GRTC_INTENCLR2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
29676   #define GRTC_INTENCLR2_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
29677   #define GRTC_INTENCLR2_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
29678   #define GRTC_INTENCLR2_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
29679   #define GRTC_INTENCLR2_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29680   #define GRTC_INTENCLR2_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29681 
29682 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
29683   #define GRTC_INTENCLR2_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
29684   #define GRTC_INTENCLR2_COMPARE6_Msk (0x1UL << GRTC_INTENCLR2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
29685   #define GRTC_INTENCLR2_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
29686   #define GRTC_INTENCLR2_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
29687   #define GRTC_INTENCLR2_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
29688   #define GRTC_INTENCLR2_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29689   #define GRTC_INTENCLR2_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29690 
29691 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
29692   #define GRTC_INTENCLR2_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
29693   #define GRTC_INTENCLR2_COMPARE7_Msk (0x1UL << GRTC_INTENCLR2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
29694   #define GRTC_INTENCLR2_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
29695   #define GRTC_INTENCLR2_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
29696   #define GRTC_INTENCLR2_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
29697   #define GRTC_INTENCLR2_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29698   #define GRTC_INTENCLR2_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29699 
29700 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
29701   #define GRTC_INTENCLR2_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
29702   #define GRTC_INTENCLR2_COMPARE8_Msk (0x1UL << GRTC_INTENCLR2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
29703   #define GRTC_INTENCLR2_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
29704   #define GRTC_INTENCLR2_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
29705   #define GRTC_INTENCLR2_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
29706   #define GRTC_INTENCLR2_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29707   #define GRTC_INTENCLR2_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29708 
29709 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
29710   #define GRTC_INTENCLR2_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
29711   #define GRTC_INTENCLR2_COMPARE9_Msk (0x1UL << GRTC_INTENCLR2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
29712   #define GRTC_INTENCLR2_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
29713   #define GRTC_INTENCLR2_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
29714   #define GRTC_INTENCLR2_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
29715   #define GRTC_INTENCLR2_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
29716   #define GRTC_INTENCLR2_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
29717 
29718 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
29719   #define GRTC_INTENCLR2_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
29720   #define GRTC_INTENCLR2_COMPARE10_Msk (0x1UL << GRTC_INTENCLR2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
29721   #define GRTC_INTENCLR2_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
29722   #define GRTC_INTENCLR2_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
29723   #define GRTC_INTENCLR2_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
29724   #define GRTC_INTENCLR2_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29725   #define GRTC_INTENCLR2_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29726 
29727 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
29728   #define GRTC_INTENCLR2_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
29729   #define GRTC_INTENCLR2_COMPARE11_Msk (0x1UL << GRTC_INTENCLR2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
29730   #define GRTC_INTENCLR2_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
29731   #define GRTC_INTENCLR2_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
29732   #define GRTC_INTENCLR2_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
29733   #define GRTC_INTENCLR2_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29734   #define GRTC_INTENCLR2_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29735 
29736 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
29737   #define GRTC_INTENCLR2_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
29738   #define GRTC_INTENCLR2_COMPARE12_Msk (0x1UL << GRTC_INTENCLR2_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
29739   #define GRTC_INTENCLR2_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
29740   #define GRTC_INTENCLR2_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
29741   #define GRTC_INTENCLR2_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
29742   #define GRTC_INTENCLR2_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29743   #define GRTC_INTENCLR2_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29744 
29745 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
29746   #define GRTC_INTENCLR2_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
29747   #define GRTC_INTENCLR2_COMPARE13_Msk (0x1UL << GRTC_INTENCLR2_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
29748   #define GRTC_INTENCLR2_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
29749   #define GRTC_INTENCLR2_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
29750   #define GRTC_INTENCLR2_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
29751   #define GRTC_INTENCLR2_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29752   #define GRTC_INTENCLR2_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29753 
29754 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
29755   #define GRTC_INTENCLR2_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
29756   #define GRTC_INTENCLR2_COMPARE14_Msk (0x1UL << GRTC_INTENCLR2_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
29757   #define GRTC_INTENCLR2_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
29758   #define GRTC_INTENCLR2_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
29759   #define GRTC_INTENCLR2_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
29760   #define GRTC_INTENCLR2_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29761   #define GRTC_INTENCLR2_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29762 
29763 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
29764   #define GRTC_INTENCLR2_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
29765   #define GRTC_INTENCLR2_COMPARE15_Msk (0x1UL << GRTC_INTENCLR2_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
29766   #define GRTC_INTENCLR2_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
29767   #define GRTC_INTENCLR2_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
29768   #define GRTC_INTENCLR2_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
29769   #define GRTC_INTENCLR2_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
29770   #define GRTC_INTENCLR2_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
29771 
29772 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
29773   #define GRTC_INTENCLR2_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
29774   #define GRTC_INTENCLR2_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR2_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
29775                                                                             field.*/
29776   #define GRTC_INTENCLR2_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
29777   #define GRTC_INTENCLR2_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
29778   #define GRTC_INTENCLR2_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
29779   #define GRTC_INTENCLR2_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
29780   #define GRTC_INTENCLR2_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
29781 
29782 
29783 /* GRTC_INTPEND2: Pending interrupts */
29784   #define GRTC_INTPEND2_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND2 register.                                    */
29785 
29786 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
29787   #define GRTC_INTPEND2_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
29788   #define GRTC_INTPEND2_COMPARE0_Msk (0x1UL << GRTC_INTPEND2_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
29789   #define GRTC_INTPEND2_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
29790   #define GRTC_INTPEND2_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
29791   #define GRTC_INTPEND2_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29792   #define GRTC_INTPEND2_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
29793 
29794 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
29795   #define GRTC_INTPEND2_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
29796   #define GRTC_INTPEND2_COMPARE1_Msk (0x1UL << GRTC_INTPEND2_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
29797   #define GRTC_INTPEND2_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
29798   #define GRTC_INTPEND2_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
29799   #define GRTC_INTPEND2_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29800   #define GRTC_INTPEND2_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
29801 
29802 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
29803   #define GRTC_INTPEND2_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
29804   #define GRTC_INTPEND2_COMPARE2_Msk (0x1UL << GRTC_INTPEND2_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
29805   #define GRTC_INTPEND2_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
29806   #define GRTC_INTPEND2_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
29807   #define GRTC_INTPEND2_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29808   #define GRTC_INTPEND2_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
29809 
29810 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
29811   #define GRTC_INTPEND2_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
29812   #define GRTC_INTPEND2_COMPARE3_Msk (0x1UL << GRTC_INTPEND2_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
29813   #define GRTC_INTPEND2_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
29814   #define GRTC_INTPEND2_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
29815   #define GRTC_INTPEND2_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29816   #define GRTC_INTPEND2_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
29817 
29818 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
29819   #define GRTC_INTPEND2_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
29820   #define GRTC_INTPEND2_COMPARE4_Msk (0x1UL << GRTC_INTPEND2_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
29821   #define GRTC_INTPEND2_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
29822   #define GRTC_INTPEND2_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
29823   #define GRTC_INTPEND2_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29824   #define GRTC_INTPEND2_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
29825 
29826 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
29827   #define GRTC_INTPEND2_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
29828   #define GRTC_INTPEND2_COMPARE5_Msk (0x1UL << GRTC_INTPEND2_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
29829   #define GRTC_INTPEND2_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
29830   #define GRTC_INTPEND2_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
29831   #define GRTC_INTPEND2_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29832   #define GRTC_INTPEND2_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
29833 
29834 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
29835   #define GRTC_INTPEND2_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
29836   #define GRTC_INTPEND2_COMPARE6_Msk (0x1UL << GRTC_INTPEND2_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
29837   #define GRTC_INTPEND2_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
29838   #define GRTC_INTPEND2_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
29839   #define GRTC_INTPEND2_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29840   #define GRTC_INTPEND2_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
29841 
29842 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
29843   #define GRTC_INTPEND2_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
29844   #define GRTC_INTPEND2_COMPARE7_Msk (0x1UL << GRTC_INTPEND2_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
29845   #define GRTC_INTPEND2_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
29846   #define GRTC_INTPEND2_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
29847   #define GRTC_INTPEND2_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29848   #define GRTC_INTPEND2_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
29849 
29850 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
29851   #define GRTC_INTPEND2_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
29852   #define GRTC_INTPEND2_COMPARE8_Msk (0x1UL << GRTC_INTPEND2_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
29853   #define GRTC_INTPEND2_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
29854   #define GRTC_INTPEND2_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
29855   #define GRTC_INTPEND2_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29856   #define GRTC_INTPEND2_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
29857 
29858 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
29859   #define GRTC_INTPEND2_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
29860   #define GRTC_INTPEND2_COMPARE9_Msk (0x1UL << GRTC_INTPEND2_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
29861   #define GRTC_INTPEND2_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
29862   #define GRTC_INTPEND2_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
29863   #define GRTC_INTPEND2_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
29864   #define GRTC_INTPEND2_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
29865 
29866 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
29867   #define GRTC_INTPEND2_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
29868   #define GRTC_INTPEND2_COMPARE10_Msk (0x1UL << GRTC_INTPEND2_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
29869   #define GRTC_INTPEND2_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
29870   #define GRTC_INTPEND2_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
29871   #define GRTC_INTPEND2_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29872   #define GRTC_INTPEND2_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
29873 
29874 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
29875   #define GRTC_INTPEND2_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
29876   #define GRTC_INTPEND2_COMPARE11_Msk (0x1UL << GRTC_INTPEND2_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
29877   #define GRTC_INTPEND2_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
29878   #define GRTC_INTPEND2_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
29879   #define GRTC_INTPEND2_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29880   #define GRTC_INTPEND2_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
29881 
29882 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
29883   #define GRTC_INTPEND2_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
29884   #define GRTC_INTPEND2_COMPARE12_Msk (0x1UL << GRTC_INTPEND2_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
29885   #define GRTC_INTPEND2_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
29886   #define GRTC_INTPEND2_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
29887   #define GRTC_INTPEND2_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29888   #define GRTC_INTPEND2_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
29889 
29890 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
29891   #define GRTC_INTPEND2_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
29892   #define GRTC_INTPEND2_COMPARE13_Msk (0x1UL << GRTC_INTPEND2_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
29893   #define GRTC_INTPEND2_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
29894   #define GRTC_INTPEND2_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
29895   #define GRTC_INTPEND2_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29896   #define GRTC_INTPEND2_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
29897 
29898 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
29899   #define GRTC_INTPEND2_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
29900   #define GRTC_INTPEND2_COMPARE14_Msk (0x1UL << GRTC_INTPEND2_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
29901   #define GRTC_INTPEND2_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
29902   #define GRTC_INTPEND2_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
29903   #define GRTC_INTPEND2_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29904   #define GRTC_INTPEND2_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
29905 
29906 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
29907   #define GRTC_INTPEND2_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
29908   #define GRTC_INTPEND2_COMPARE15_Msk (0x1UL << GRTC_INTPEND2_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
29909   #define GRTC_INTPEND2_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
29910   #define GRTC_INTPEND2_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
29911   #define GRTC_INTPEND2_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
29912   #define GRTC_INTPEND2_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
29913 
29914 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
29915   #define GRTC_INTPEND2_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
29916   #define GRTC_INTPEND2_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND2_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
29917                                                                             field.*/
29918   #define GRTC_INTPEND2_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
29919   #define GRTC_INTPEND2_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
29920   #define GRTC_INTPEND2_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
29921   #define GRTC_INTPEND2_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
29922 
29923 
29924 /* GRTC_INTEN3: Enable or disable interrupt */
29925   #define GRTC_INTEN3_ResetValue (0x00000000UL)      /*!< Reset value of INTEN3 register.                                      */
29926 
29927 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
29928   #define GRTC_INTEN3_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
29929   #define GRTC_INTEN3_COMPARE0_Msk (0x1UL << GRTC_INTEN3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
29930   #define GRTC_INTEN3_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
29931   #define GRTC_INTEN3_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
29932   #define GRTC_INTEN3_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
29933   #define GRTC_INTEN3_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
29934 
29935 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
29936   #define GRTC_INTEN3_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
29937   #define GRTC_INTEN3_COMPARE1_Msk (0x1UL << GRTC_INTEN3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
29938   #define GRTC_INTEN3_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
29939   #define GRTC_INTEN3_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
29940   #define GRTC_INTEN3_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
29941   #define GRTC_INTEN3_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
29942 
29943 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
29944   #define GRTC_INTEN3_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
29945   #define GRTC_INTEN3_COMPARE2_Msk (0x1UL << GRTC_INTEN3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
29946   #define GRTC_INTEN3_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
29947   #define GRTC_INTEN3_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
29948   #define GRTC_INTEN3_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
29949   #define GRTC_INTEN3_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
29950 
29951 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
29952   #define GRTC_INTEN3_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
29953   #define GRTC_INTEN3_COMPARE3_Msk (0x1UL << GRTC_INTEN3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
29954   #define GRTC_INTEN3_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
29955   #define GRTC_INTEN3_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
29956   #define GRTC_INTEN3_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
29957   #define GRTC_INTEN3_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
29958 
29959 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
29960   #define GRTC_INTEN3_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
29961   #define GRTC_INTEN3_COMPARE4_Msk (0x1UL << GRTC_INTEN3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
29962   #define GRTC_INTEN3_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
29963   #define GRTC_INTEN3_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
29964   #define GRTC_INTEN3_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
29965   #define GRTC_INTEN3_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
29966 
29967 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
29968   #define GRTC_INTEN3_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
29969   #define GRTC_INTEN3_COMPARE5_Msk (0x1UL << GRTC_INTEN3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
29970   #define GRTC_INTEN3_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
29971   #define GRTC_INTEN3_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
29972   #define GRTC_INTEN3_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
29973   #define GRTC_INTEN3_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
29974 
29975 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
29976   #define GRTC_INTEN3_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
29977   #define GRTC_INTEN3_COMPARE6_Msk (0x1UL << GRTC_INTEN3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
29978   #define GRTC_INTEN3_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
29979   #define GRTC_INTEN3_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
29980   #define GRTC_INTEN3_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
29981   #define GRTC_INTEN3_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
29982 
29983 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
29984   #define GRTC_INTEN3_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
29985   #define GRTC_INTEN3_COMPARE7_Msk (0x1UL << GRTC_INTEN3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
29986   #define GRTC_INTEN3_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
29987   #define GRTC_INTEN3_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
29988   #define GRTC_INTEN3_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
29989   #define GRTC_INTEN3_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
29990 
29991 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
29992   #define GRTC_INTEN3_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
29993   #define GRTC_INTEN3_COMPARE8_Msk (0x1UL << GRTC_INTEN3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
29994   #define GRTC_INTEN3_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
29995   #define GRTC_INTEN3_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
29996   #define GRTC_INTEN3_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
29997   #define GRTC_INTEN3_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
29998 
29999 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
30000   #define GRTC_INTEN3_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
30001   #define GRTC_INTEN3_COMPARE9_Msk (0x1UL << GRTC_INTEN3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
30002   #define GRTC_INTEN3_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
30003   #define GRTC_INTEN3_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
30004   #define GRTC_INTEN3_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
30005   #define GRTC_INTEN3_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
30006 
30007 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
30008   #define GRTC_INTEN3_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
30009   #define GRTC_INTEN3_COMPARE10_Msk (0x1UL << GRTC_INTEN3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
30010   #define GRTC_INTEN3_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
30011   #define GRTC_INTEN3_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
30012   #define GRTC_INTEN3_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
30013   #define GRTC_INTEN3_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
30014 
30015 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
30016   #define GRTC_INTEN3_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
30017   #define GRTC_INTEN3_COMPARE11_Msk (0x1UL << GRTC_INTEN3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
30018   #define GRTC_INTEN3_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
30019   #define GRTC_INTEN3_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
30020   #define GRTC_INTEN3_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
30021   #define GRTC_INTEN3_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
30022 
30023 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
30024   #define GRTC_INTEN3_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
30025   #define GRTC_INTEN3_COMPARE12_Msk (0x1UL << GRTC_INTEN3_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
30026   #define GRTC_INTEN3_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
30027   #define GRTC_INTEN3_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
30028   #define GRTC_INTEN3_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
30029   #define GRTC_INTEN3_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
30030 
30031 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
30032   #define GRTC_INTEN3_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
30033   #define GRTC_INTEN3_COMPARE13_Msk (0x1UL << GRTC_INTEN3_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
30034   #define GRTC_INTEN3_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
30035   #define GRTC_INTEN3_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
30036   #define GRTC_INTEN3_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
30037   #define GRTC_INTEN3_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
30038 
30039 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
30040   #define GRTC_INTEN3_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
30041   #define GRTC_INTEN3_COMPARE14_Msk (0x1UL << GRTC_INTEN3_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
30042   #define GRTC_INTEN3_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
30043   #define GRTC_INTEN3_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
30044   #define GRTC_INTEN3_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
30045   #define GRTC_INTEN3_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
30046 
30047 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
30048   #define GRTC_INTEN3_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
30049   #define GRTC_INTEN3_COMPARE15_Msk (0x1UL << GRTC_INTEN3_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
30050   #define GRTC_INTEN3_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
30051   #define GRTC_INTEN3_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
30052   #define GRTC_INTEN3_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
30053   #define GRTC_INTEN3_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
30054 
30055 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
30056   #define GRTC_INTEN3_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
30057   #define GRTC_INTEN3_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN3_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
30058   #define GRTC_INTEN3_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
30059   #define GRTC_INTEN3_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
30060   #define GRTC_INTEN3_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
30061   #define GRTC_INTEN3_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
30062 
30063 
30064 /* GRTC_INTENSET3: Enable interrupt */
30065   #define GRTC_INTENSET3_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET3 register.                                   */
30066 
30067 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
30068   #define GRTC_INTENSET3_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
30069   #define GRTC_INTENSET3_COMPARE0_Msk (0x1UL << GRTC_INTENSET3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
30070   #define GRTC_INTENSET3_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
30071   #define GRTC_INTENSET3_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
30072   #define GRTC_INTENSET3_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
30073   #define GRTC_INTENSET3_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30074   #define GRTC_INTENSET3_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30075 
30076 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
30077   #define GRTC_INTENSET3_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
30078   #define GRTC_INTENSET3_COMPARE1_Msk (0x1UL << GRTC_INTENSET3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
30079   #define GRTC_INTENSET3_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
30080   #define GRTC_INTENSET3_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
30081   #define GRTC_INTENSET3_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
30082   #define GRTC_INTENSET3_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30083   #define GRTC_INTENSET3_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30084 
30085 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
30086   #define GRTC_INTENSET3_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
30087   #define GRTC_INTENSET3_COMPARE2_Msk (0x1UL << GRTC_INTENSET3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
30088   #define GRTC_INTENSET3_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
30089   #define GRTC_INTENSET3_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
30090   #define GRTC_INTENSET3_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
30091   #define GRTC_INTENSET3_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30092   #define GRTC_INTENSET3_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30093 
30094 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
30095   #define GRTC_INTENSET3_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
30096   #define GRTC_INTENSET3_COMPARE3_Msk (0x1UL << GRTC_INTENSET3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
30097   #define GRTC_INTENSET3_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
30098   #define GRTC_INTENSET3_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
30099   #define GRTC_INTENSET3_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
30100   #define GRTC_INTENSET3_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30101   #define GRTC_INTENSET3_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30102 
30103 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
30104   #define GRTC_INTENSET3_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
30105   #define GRTC_INTENSET3_COMPARE4_Msk (0x1UL << GRTC_INTENSET3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
30106   #define GRTC_INTENSET3_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
30107   #define GRTC_INTENSET3_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
30108   #define GRTC_INTENSET3_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
30109   #define GRTC_INTENSET3_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30110   #define GRTC_INTENSET3_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30111 
30112 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
30113   #define GRTC_INTENSET3_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
30114   #define GRTC_INTENSET3_COMPARE5_Msk (0x1UL << GRTC_INTENSET3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
30115   #define GRTC_INTENSET3_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
30116   #define GRTC_INTENSET3_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
30117   #define GRTC_INTENSET3_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
30118   #define GRTC_INTENSET3_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30119   #define GRTC_INTENSET3_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30120 
30121 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
30122   #define GRTC_INTENSET3_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
30123   #define GRTC_INTENSET3_COMPARE6_Msk (0x1UL << GRTC_INTENSET3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
30124   #define GRTC_INTENSET3_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
30125   #define GRTC_INTENSET3_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
30126   #define GRTC_INTENSET3_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
30127   #define GRTC_INTENSET3_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30128   #define GRTC_INTENSET3_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30129 
30130 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
30131   #define GRTC_INTENSET3_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
30132   #define GRTC_INTENSET3_COMPARE7_Msk (0x1UL << GRTC_INTENSET3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
30133   #define GRTC_INTENSET3_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
30134   #define GRTC_INTENSET3_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
30135   #define GRTC_INTENSET3_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
30136   #define GRTC_INTENSET3_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30137   #define GRTC_INTENSET3_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30138 
30139 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
30140   #define GRTC_INTENSET3_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
30141   #define GRTC_INTENSET3_COMPARE8_Msk (0x1UL << GRTC_INTENSET3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
30142   #define GRTC_INTENSET3_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
30143   #define GRTC_INTENSET3_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
30144   #define GRTC_INTENSET3_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
30145   #define GRTC_INTENSET3_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30146   #define GRTC_INTENSET3_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30147 
30148 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
30149   #define GRTC_INTENSET3_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
30150   #define GRTC_INTENSET3_COMPARE9_Msk (0x1UL << GRTC_INTENSET3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
30151   #define GRTC_INTENSET3_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
30152   #define GRTC_INTENSET3_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
30153   #define GRTC_INTENSET3_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
30154   #define GRTC_INTENSET3_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30155   #define GRTC_INTENSET3_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30156 
30157 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
30158   #define GRTC_INTENSET3_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
30159   #define GRTC_INTENSET3_COMPARE10_Msk (0x1UL << GRTC_INTENSET3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
30160   #define GRTC_INTENSET3_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
30161   #define GRTC_INTENSET3_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
30162   #define GRTC_INTENSET3_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
30163   #define GRTC_INTENSET3_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30164   #define GRTC_INTENSET3_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30165 
30166 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
30167   #define GRTC_INTENSET3_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
30168   #define GRTC_INTENSET3_COMPARE11_Msk (0x1UL << GRTC_INTENSET3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
30169   #define GRTC_INTENSET3_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
30170   #define GRTC_INTENSET3_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
30171   #define GRTC_INTENSET3_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
30172   #define GRTC_INTENSET3_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30173   #define GRTC_INTENSET3_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30174 
30175 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
30176   #define GRTC_INTENSET3_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
30177   #define GRTC_INTENSET3_COMPARE12_Msk (0x1UL << GRTC_INTENSET3_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
30178   #define GRTC_INTENSET3_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
30179   #define GRTC_INTENSET3_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
30180   #define GRTC_INTENSET3_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
30181   #define GRTC_INTENSET3_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30182   #define GRTC_INTENSET3_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30183 
30184 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
30185   #define GRTC_INTENSET3_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
30186   #define GRTC_INTENSET3_COMPARE13_Msk (0x1UL << GRTC_INTENSET3_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
30187   #define GRTC_INTENSET3_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
30188   #define GRTC_INTENSET3_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
30189   #define GRTC_INTENSET3_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
30190   #define GRTC_INTENSET3_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30191   #define GRTC_INTENSET3_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30192 
30193 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
30194   #define GRTC_INTENSET3_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
30195   #define GRTC_INTENSET3_COMPARE14_Msk (0x1UL << GRTC_INTENSET3_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
30196   #define GRTC_INTENSET3_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
30197   #define GRTC_INTENSET3_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
30198   #define GRTC_INTENSET3_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
30199   #define GRTC_INTENSET3_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30200   #define GRTC_INTENSET3_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30201 
30202 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
30203   #define GRTC_INTENSET3_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
30204   #define GRTC_INTENSET3_COMPARE15_Msk (0x1UL << GRTC_INTENSET3_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
30205   #define GRTC_INTENSET3_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
30206   #define GRTC_INTENSET3_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
30207   #define GRTC_INTENSET3_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
30208   #define GRTC_INTENSET3_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30209   #define GRTC_INTENSET3_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30210 
30211 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
30212   #define GRTC_INTENSET3_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
30213   #define GRTC_INTENSET3_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET3_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
30214                                                                             field.*/
30215   #define GRTC_INTENSET3_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
30216   #define GRTC_INTENSET3_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
30217   #define GRTC_INTENSET3_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
30218   #define GRTC_INTENSET3_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
30219   #define GRTC_INTENSET3_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
30220 
30221 
30222 /* GRTC_INTENCLR3: Disable interrupt */
30223   #define GRTC_INTENCLR3_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR3 register.                                   */
30224 
30225 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
30226   #define GRTC_INTENCLR3_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
30227   #define GRTC_INTENCLR3_COMPARE0_Msk (0x1UL << GRTC_INTENCLR3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
30228   #define GRTC_INTENCLR3_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
30229   #define GRTC_INTENCLR3_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
30230   #define GRTC_INTENCLR3_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
30231   #define GRTC_INTENCLR3_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30232   #define GRTC_INTENCLR3_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30233 
30234 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
30235   #define GRTC_INTENCLR3_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
30236   #define GRTC_INTENCLR3_COMPARE1_Msk (0x1UL << GRTC_INTENCLR3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
30237   #define GRTC_INTENCLR3_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
30238   #define GRTC_INTENCLR3_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
30239   #define GRTC_INTENCLR3_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
30240   #define GRTC_INTENCLR3_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30241   #define GRTC_INTENCLR3_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30242 
30243 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
30244   #define GRTC_INTENCLR3_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
30245   #define GRTC_INTENCLR3_COMPARE2_Msk (0x1UL << GRTC_INTENCLR3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
30246   #define GRTC_INTENCLR3_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
30247   #define GRTC_INTENCLR3_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
30248   #define GRTC_INTENCLR3_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
30249   #define GRTC_INTENCLR3_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30250   #define GRTC_INTENCLR3_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30251 
30252 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
30253   #define GRTC_INTENCLR3_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
30254   #define GRTC_INTENCLR3_COMPARE3_Msk (0x1UL << GRTC_INTENCLR3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
30255   #define GRTC_INTENCLR3_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
30256   #define GRTC_INTENCLR3_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
30257   #define GRTC_INTENCLR3_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
30258   #define GRTC_INTENCLR3_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30259   #define GRTC_INTENCLR3_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30260 
30261 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
30262   #define GRTC_INTENCLR3_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
30263   #define GRTC_INTENCLR3_COMPARE4_Msk (0x1UL << GRTC_INTENCLR3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
30264   #define GRTC_INTENCLR3_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
30265   #define GRTC_INTENCLR3_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
30266   #define GRTC_INTENCLR3_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
30267   #define GRTC_INTENCLR3_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30268   #define GRTC_INTENCLR3_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30269 
30270 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
30271   #define GRTC_INTENCLR3_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
30272   #define GRTC_INTENCLR3_COMPARE5_Msk (0x1UL << GRTC_INTENCLR3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
30273   #define GRTC_INTENCLR3_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
30274   #define GRTC_INTENCLR3_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
30275   #define GRTC_INTENCLR3_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
30276   #define GRTC_INTENCLR3_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30277   #define GRTC_INTENCLR3_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30278 
30279 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
30280   #define GRTC_INTENCLR3_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
30281   #define GRTC_INTENCLR3_COMPARE6_Msk (0x1UL << GRTC_INTENCLR3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
30282   #define GRTC_INTENCLR3_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
30283   #define GRTC_INTENCLR3_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
30284   #define GRTC_INTENCLR3_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
30285   #define GRTC_INTENCLR3_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30286   #define GRTC_INTENCLR3_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30287 
30288 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
30289   #define GRTC_INTENCLR3_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
30290   #define GRTC_INTENCLR3_COMPARE7_Msk (0x1UL << GRTC_INTENCLR3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
30291   #define GRTC_INTENCLR3_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
30292   #define GRTC_INTENCLR3_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
30293   #define GRTC_INTENCLR3_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
30294   #define GRTC_INTENCLR3_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30295   #define GRTC_INTENCLR3_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30296 
30297 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
30298   #define GRTC_INTENCLR3_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
30299   #define GRTC_INTENCLR3_COMPARE8_Msk (0x1UL << GRTC_INTENCLR3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
30300   #define GRTC_INTENCLR3_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
30301   #define GRTC_INTENCLR3_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
30302   #define GRTC_INTENCLR3_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
30303   #define GRTC_INTENCLR3_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30304   #define GRTC_INTENCLR3_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30305 
30306 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
30307   #define GRTC_INTENCLR3_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
30308   #define GRTC_INTENCLR3_COMPARE9_Msk (0x1UL << GRTC_INTENCLR3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
30309   #define GRTC_INTENCLR3_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
30310   #define GRTC_INTENCLR3_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
30311   #define GRTC_INTENCLR3_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
30312   #define GRTC_INTENCLR3_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30313   #define GRTC_INTENCLR3_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30314 
30315 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
30316   #define GRTC_INTENCLR3_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
30317   #define GRTC_INTENCLR3_COMPARE10_Msk (0x1UL << GRTC_INTENCLR3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
30318   #define GRTC_INTENCLR3_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
30319   #define GRTC_INTENCLR3_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
30320   #define GRTC_INTENCLR3_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
30321   #define GRTC_INTENCLR3_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30322   #define GRTC_INTENCLR3_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30323 
30324 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
30325   #define GRTC_INTENCLR3_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
30326   #define GRTC_INTENCLR3_COMPARE11_Msk (0x1UL << GRTC_INTENCLR3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
30327   #define GRTC_INTENCLR3_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
30328   #define GRTC_INTENCLR3_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
30329   #define GRTC_INTENCLR3_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
30330   #define GRTC_INTENCLR3_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30331   #define GRTC_INTENCLR3_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30332 
30333 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
30334   #define GRTC_INTENCLR3_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
30335   #define GRTC_INTENCLR3_COMPARE12_Msk (0x1UL << GRTC_INTENCLR3_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
30336   #define GRTC_INTENCLR3_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
30337   #define GRTC_INTENCLR3_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
30338   #define GRTC_INTENCLR3_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
30339   #define GRTC_INTENCLR3_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30340   #define GRTC_INTENCLR3_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30341 
30342 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
30343   #define GRTC_INTENCLR3_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
30344   #define GRTC_INTENCLR3_COMPARE13_Msk (0x1UL << GRTC_INTENCLR3_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
30345   #define GRTC_INTENCLR3_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
30346   #define GRTC_INTENCLR3_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
30347   #define GRTC_INTENCLR3_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
30348   #define GRTC_INTENCLR3_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30349   #define GRTC_INTENCLR3_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30350 
30351 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
30352   #define GRTC_INTENCLR3_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
30353   #define GRTC_INTENCLR3_COMPARE14_Msk (0x1UL << GRTC_INTENCLR3_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
30354   #define GRTC_INTENCLR3_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
30355   #define GRTC_INTENCLR3_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
30356   #define GRTC_INTENCLR3_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
30357   #define GRTC_INTENCLR3_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30358   #define GRTC_INTENCLR3_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30359 
30360 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
30361   #define GRTC_INTENCLR3_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
30362   #define GRTC_INTENCLR3_COMPARE15_Msk (0x1UL << GRTC_INTENCLR3_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
30363   #define GRTC_INTENCLR3_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
30364   #define GRTC_INTENCLR3_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
30365   #define GRTC_INTENCLR3_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
30366   #define GRTC_INTENCLR3_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30367   #define GRTC_INTENCLR3_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30368 
30369 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
30370   #define GRTC_INTENCLR3_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
30371   #define GRTC_INTENCLR3_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR3_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
30372                                                                             field.*/
30373   #define GRTC_INTENCLR3_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
30374   #define GRTC_INTENCLR3_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
30375   #define GRTC_INTENCLR3_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
30376   #define GRTC_INTENCLR3_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
30377   #define GRTC_INTENCLR3_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
30378 
30379 
30380 /* GRTC_INTPEND3: Pending interrupts */
30381   #define GRTC_INTPEND3_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND3 register.                                    */
30382 
30383 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
30384   #define GRTC_INTPEND3_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
30385   #define GRTC_INTPEND3_COMPARE0_Msk (0x1UL << GRTC_INTPEND3_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
30386   #define GRTC_INTPEND3_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
30387   #define GRTC_INTPEND3_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
30388   #define GRTC_INTPEND3_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30389   #define GRTC_INTPEND3_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
30390 
30391 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
30392   #define GRTC_INTPEND3_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
30393   #define GRTC_INTPEND3_COMPARE1_Msk (0x1UL << GRTC_INTPEND3_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
30394   #define GRTC_INTPEND3_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
30395   #define GRTC_INTPEND3_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
30396   #define GRTC_INTPEND3_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30397   #define GRTC_INTPEND3_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
30398 
30399 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
30400   #define GRTC_INTPEND3_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
30401   #define GRTC_INTPEND3_COMPARE2_Msk (0x1UL << GRTC_INTPEND3_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
30402   #define GRTC_INTPEND3_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
30403   #define GRTC_INTPEND3_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
30404   #define GRTC_INTPEND3_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30405   #define GRTC_INTPEND3_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
30406 
30407 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
30408   #define GRTC_INTPEND3_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
30409   #define GRTC_INTPEND3_COMPARE3_Msk (0x1UL << GRTC_INTPEND3_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
30410   #define GRTC_INTPEND3_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
30411   #define GRTC_INTPEND3_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
30412   #define GRTC_INTPEND3_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30413   #define GRTC_INTPEND3_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
30414 
30415 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
30416   #define GRTC_INTPEND3_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
30417   #define GRTC_INTPEND3_COMPARE4_Msk (0x1UL << GRTC_INTPEND3_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
30418   #define GRTC_INTPEND3_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
30419   #define GRTC_INTPEND3_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
30420   #define GRTC_INTPEND3_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30421   #define GRTC_INTPEND3_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
30422 
30423 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
30424   #define GRTC_INTPEND3_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
30425   #define GRTC_INTPEND3_COMPARE5_Msk (0x1UL << GRTC_INTPEND3_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
30426   #define GRTC_INTPEND3_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
30427   #define GRTC_INTPEND3_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
30428   #define GRTC_INTPEND3_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30429   #define GRTC_INTPEND3_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
30430 
30431 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
30432   #define GRTC_INTPEND3_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
30433   #define GRTC_INTPEND3_COMPARE6_Msk (0x1UL << GRTC_INTPEND3_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
30434   #define GRTC_INTPEND3_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
30435   #define GRTC_INTPEND3_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
30436   #define GRTC_INTPEND3_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30437   #define GRTC_INTPEND3_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
30438 
30439 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
30440   #define GRTC_INTPEND3_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
30441   #define GRTC_INTPEND3_COMPARE7_Msk (0x1UL << GRTC_INTPEND3_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
30442   #define GRTC_INTPEND3_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
30443   #define GRTC_INTPEND3_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
30444   #define GRTC_INTPEND3_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30445   #define GRTC_INTPEND3_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
30446 
30447 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
30448   #define GRTC_INTPEND3_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
30449   #define GRTC_INTPEND3_COMPARE8_Msk (0x1UL << GRTC_INTPEND3_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
30450   #define GRTC_INTPEND3_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
30451   #define GRTC_INTPEND3_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
30452   #define GRTC_INTPEND3_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30453   #define GRTC_INTPEND3_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
30454 
30455 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
30456   #define GRTC_INTPEND3_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
30457   #define GRTC_INTPEND3_COMPARE9_Msk (0x1UL << GRTC_INTPEND3_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
30458   #define GRTC_INTPEND3_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
30459   #define GRTC_INTPEND3_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
30460   #define GRTC_INTPEND3_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30461   #define GRTC_INTPEND3_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
30462 
30463 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
30464   #define GRTC_INTPEND3_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
30465   #define GRTC_INTPEND3_COMPARE10_Msk (0x1UL << GRTC_INTPEND3_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
30466   #define GRTC_INTPEND3_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
30467   #define GRTC_INTPEND3_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
30468   #define GRTC_INTPEND3_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
30469   #define GRTC_INTPEND3_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
30470 
30471 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
30472   #define GRTC_INTPEND3_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
30473   #define GRTC_INTPEND3_COMPARE11_Msk (0x1UL << GRTC_INTPEND3_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
30474   #define GRTC_INTPEND3_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
30475   #define GRTC_INTPEND3_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
30476   #define GRTC_INTPEND3_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
30477   #define GRTC_INTPEND3_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
30478 
30479 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
30480   #define GRTC_INTPEND3_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
30481   #define GRTC_INTPEND3_COMPARE12_Msk (0x1UL << GRTC_INTPEND3_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
30482   #define GRTC_INTPEND3_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
30483   #define GRTC_INTPEND3_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
30484   #define GRTC_INTPEND3_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
30485   #define GRTC_INTPEND3_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
30486 
30487 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
30488   #define GRTC_INTPEND3_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
30489   #define GRTC_INTPEND3_COMPARE13_Msk (0x1UL << GRTC_INTPEND3_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
30490   #define GRTC_INTPEND3_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
30491   #define GRTC_INTPEND3_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
30492   #define GRTC_INTPEND3_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
30493   #define GRTC_INTPEND3_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
30494 
30495 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
30496   #define GRTC_INTPEND3_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
30497   #define GRTC_INTPEND3_COMPARE14_Msk (0x1UL << GRTC_INTPEND3_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
30498   #define GRTC_INTPEND3_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
30499   #define GRTC_INTPEND3_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
30500   #define GRTC_INTPEND3_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
30501   #define GRTC_INTPEND3_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
30502 
30503 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
30504   #define GRTC_INTPEND3_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
30505   #define GRTC_INTPEND3_COMPARE15_Msk (0x1UL << GRTC_INTPEND3_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
30506   #define GRTC_INTPEND3_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
30507   #define GRTC_INTPEND3_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
30508   #define GRTC_INTPEND3_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
30509   #define GRTC_INTPEND3_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
30510 
30511 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
30512   #define GRTC_INTPEND3_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
30513   #define GRTC_INTPEND3_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND3_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
30514                                                                             field.*/
30515   #define GRTC_INTPEND3_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
30516   #define GRTC_INTPEND3_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
30517   #define GRTC_INTPEND3_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
30518   #define GRTC_INTPEND3_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
30519 
30520 
30521 /* GRTC_INTEN4: Enable or disable interrupt */
30522   #define GRTC_INTEN4_ResetValue (0x00000000UL)      /*!< Reset value of INTEN4 register.                                      */
30523 
30524 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
30525   #define GRTC_INTEN4_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
30526   #define GRTC_INTEN4_COMPARE0_Msk (0x1UL << GRTC_INTEN4_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
30527   #define GRTC_INTEN4_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
30528   #define GRTC_INTEN4_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
30529   #define GRTC_INTEN4_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
30530   #define GRTC_INTEN4_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
30531 
30532 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
30533   #define GRTC_INTEN4_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
30534   #define GRTC_INTEN4_COMPARE1_Msk (0x1UL << GRTC_INTEN4_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
30535   #define GRTC_INTEN4_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
30536   #define GRTC_INTEN4_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
30537   #define GRTC_INTEN4_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
30538   #define GRTC_INTEN4_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
30539 
30540 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
30541   #define GRTC_INTEN4_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
30542   #define GRTC_INTEN4_COMPARE2_Msk (0x1UL << GRTC_INTEN4_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
30543   #define GRTC_INTEN4_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
30544   #define GRTC_INTEN4_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
30545   #define GRTC_INTEN4_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
30546   #define GRTC_INTEN4_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
30547 
30548 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
30549   #define GRTC_INTEN4_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
30550   #define GRTC_INTEN4_COMPARE3_Msk (0x1UL << GRTC_INTEN4_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
30551   #define GRTC_INTEN4_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
30552   #define GRTC_INTEN4_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
30553   #define GRTC_INTEN4_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
30554   #define GRTC_INTEN4_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
30555 
30556 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
30557   #define GRTC_INTEN4_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
30558   #define GRTC_INTEN4_COMPARE4_Msk (0x1UL << GRTC_INTEN4_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
30559   #define GRTC_INTEN4_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
30560   #define GRTC_INTEN4_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
30561   #define GRTC_INTEN4_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
30562   #define GRTC_INTEN4_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
30563 
30564 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
30565   #define GRTC_INTEN4_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
30566   #define GRTC_INTEN4_COMPARE5_Msk (0x1UL << GRTC_INTEN4_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
30567   #define GRTC_INTEN4_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
30568   #define GRTC_INTEN4_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
30569   #define GRTC_INTEN4_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
30570   #define GRTC_INTEN4_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
30571 
30572 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
30573   #define GRTC_INTEN4_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
30574   #define GRTC_INTEN4_COMPARE6_Msk (0x1UL << GRTC_INTEN4_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
30575   #define GRTC_INTEN4_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
30576   #define GRTC_INTEN4_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
30577   #define GRTC_INTEN4_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
30578   #define GRTC_INTEN4_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
30579 
30580 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
30581   #define GRTC_INTEN4_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
30582   #define GRTC_INTEN4_COMPARE7_Msk (0x1UL << GRTC_INTEN4_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
30583   #define GRTC_INTEN4_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
30584   #define GRTC_INTEN4_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
30585   #define GRTC_INTEN4_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
30586   #define GRTC_INTEN4_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
30587 
30588 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
30589   #define GRTC_INTEN4_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
30590   #define GRTC_INTEN4_COMPARE8_Msk (0x1UL << GRTC_INTEN4_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
30591   #define GRTC_INTEN4_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
30592   #define GRTC_INTEN4_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
30593   #define GRTC_INTEN4_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
30594   #define GRTC_INTEN4_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
30595 
30596 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
30597   #define GRTC_INTEN4_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
30598   #define GRTC_INTEN4_COMPARE9_Msk (0x1UL << GRTC_INTEN4_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
30599   #define GRTC_INTEN4_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
30600   #define GRTC_INTEN4_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
30601   #define GRTC_INTEN4_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
30602   #define GRTC_INTEN4_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
30603 
30604 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
30605   #define GRTC_INTEN4_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
30606   #define GRTC_INTEN4_COMPARE10_Msk (0x1UL << GRTC_INTEN4_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
30607   #define GRTC_INTEN4_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
30608   #define GRTC_INTEN4_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
30609   #define GRTC_INTEN4_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
30610   #define GRTC_INTEN4_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
30611 
30612 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
30613   #define GRTC_INTEN4_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
30614   #define GRTC_INTEN4_COMPARE11_Msk (0x1UL << GRTC_INTEN4_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
30615   #define GRTC_INTEN4_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
30616   #define GRTC_INTEN4_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
30617   #define GRTC_INTEN4_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
30618   #define GRTC_INTEN4_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
30619 
30620 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
30621   #define GRTC_INTEN4_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
30622   #define GRTC_INTEN4_COMPARE12_Msk (0x1UL << GRTC_INTEN4_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
30623   #define GRTC_INTEN4_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
30624   #define GRTC_INTEN4_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
30625   #define GRTC_INTEN4_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
30626   #define GRTC_INTEN4_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
30627 
30628 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
30629   #define GRTC_INTEN4_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
30630   #define GRTC_INTEN4_COMPARE13_Msk (0x1UL << GRTC_INTEN4_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
30631   #define GRTC_INTEN4_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
30632   #define GRTC_INTEN4_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
30633   #define GRTC_INTEN4_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
30634   #define GRTC_INTEN4_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
30635 
30636 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
30637   #define GRTC_INTEN4_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
30638   #define GRTC_INTEN4_COMPARE14_Msk (0x1UL << GRTC_INTEN4_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
30639   #define GRTC_INTEN4_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
30640   #define GRTC_INTEN4_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
30641   #define GRTC_INTEN4_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
30642   #define GRTC_INTEN4_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
30643 
30644 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
30645   #define GRTC_INTEN4_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
30646   #define GRTC_INTEN4_COMPARE15_Msk (0x1UL << GRTC_INTEN4_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
30647   #define GRTC_INTEN4_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
30648   #define GRTC_INTEN4_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
30649   #define GRTC_INTEN4_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
30650   #define GRTC_INTEN4_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
30651 
30652 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
30653   #define GRTC_INTEN4_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
30654   #define GRTC_INTEN4_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN4_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
30655   #define GRTC_INTEN4_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
30656   #define GRTC_INTEN4_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
30657   #define GRTC_INTEN4_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
30658   #define GRTC_INTEN4_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
30659 
30660 
30661 /* GRTC_INTENSET4: Enable interrupt */
30662   #define GRTC_INTENSET4_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET4 register.                                   */
30663 
30664 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
30665   #define GRTC_INTENSET4_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
30666   #define GRTC_INTENSET4_COMPARE0_Msk (0x1UL << GRTC_INTENSET4_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
30667   #define GRTC_INTENSET4_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
30668   #define GRTC_INTENSET4_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
30669   #define GRTC_INTENSET4_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
30670   #define GRTC_INTENSET4_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30671   #define GRTC_INTENSET4_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30672 
30673 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
30674   #define GRTC_INTENSET4_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
30675   #define GRTC_INTENSET4_COMPARE1_Msk (0x1UL << GRTC_INTENSET4_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
30676   #define GRTC_INTENSET4_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
30677   #define GRTC_INTENSET4_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
30678   #define GRTC_INTENSET4_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
30679   #define GRTC_INTENSET4_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30680   #define GRTC_INTENSET4_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30681 
30682 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
30683   #define GRTC_INTENSET4_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
30684   #define GRTC_INTENSET4_COMPARE2_Msk (0x1UL << GRTC_INTENSET4_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
30685   #define GRTC_INTENSET4_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
30686   #define GRTC_INTENSET4_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
30687   #define GRTC_INTENSET4_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
30688   #define GRTC_INTENSET4_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30689   #define GRTC_INTENSET4_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30690 
30691 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
30692   #define GRTC_INTENSET4_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
30693   #define GRTC_INTENSET4_COMPARE3_Msk (0x1UL << GRTC_INTENSET4_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
30694   #define GRTC_INTENSET4_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
30695   #define GRTC_INTENSET4_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
30696   #define GRTC_INTENSET4_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
30697   #define GRTC_INTENSET4_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30698   #define GRTC_INTENSET4_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30699 
30700 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
30701   #define GRTC_INTENSET4_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
30702   #define GRTC_INTENSET4_COMPARE4_Msk (0x1UL << GRTC_INTENSET4_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
30703   #define GRTC_INTENSET4_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
30704   #define GRTC_INTENSET4_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
30705   #define GRTC_INTENSET4_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
30706   #define GRTC_INTENSET4_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30707   #define GRTC_INTENSET4_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30708 
30709 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
30710   #define GRTC_INTENSET4_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
30711   #define GRTC_INTENSET4_COMPARE5_Msk (0x1UL << GRTC_INTENSET4_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
30712   #define GRTC_INTENSET4_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
30713   #define GRTC_INTENSET4_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
30714   #define GRTC_INTENSET4_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
30715   #define GRTC_INTENSET4_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30716   #define GRTC_INTENSET4_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30717 
30718 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
30719   #define GRTC_INTENSET4_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
30720   #define GRTC_INTENSET4_COMPARE6_Msk (0x1UL << GRTC_INTENSET4_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
30721   #define GRTC_INTENSET4_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
30722   #define GRTC_INTENSET4_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
30723   #define GRTC_INTENSET4_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
30724   #define GRTC_INTENSET4_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30725   #define GRTC_INTENSET4_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30726 
30727 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
30728   #define GRTC_INTENSET4_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
30729   #define GRTC_INTENSET4_COMPARE7_Msk (0x1UL << GRTC_INTENSET4_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
30730   #define GRTC_INTENSET4_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
30731   #define GRTC_INTENSET4_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
30732   #define GRTC_INTENSET4_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
30733   #define GRTC_INTENSET4_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30734   #define GRTC_INTENSET4_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30735 
30736 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
30737   #define GRTC_INTENSET4_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
30738   #define GRTC_INTENSET4_COMPARE8_Msk (0x1UL << GRTC_INTENSET4_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
30739   #define GRTC_INTENSET4_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
30740   #define GRTC_INTENSET4_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
30741   #define GRTC_INTENSET4_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
30742   #define GRTC_INTENSET4_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30743   #define GRTC_INTENSET4_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30744 
30745 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
30746   #define GRTC_INTENSET4_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
30747   #define GRTC_INTENSET4_COMPARE9_Msk (0x1UL << GRTC_INTENSET4_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
30748   #define GRTC_INTENSET4_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
30749   #define GRTC_INTENSET4_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
30750   #define GRTC_INTENSET4_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
30751   #define GRTC_INTENSET4_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30752   #define GRTC_INTENSET4_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30753 
30754 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
30755   #define GRTC_INTENSET4_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
30756   #define GRTC_INTENSET4_COMPARE10_Msk (0x1UL << GRTC_INTENSET4_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
30757   #define GRTC_INTENSET4_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
30758   #define GRTC_INTENSET4_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
30759   #define GRTC_INTENSET4_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
30760   #define GRTC_INTENSET4_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30761   #define GRTC_INTENSET4_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30762 
30763 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
30764   #define GRTC_INTENSET4_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
30765   #define GRTC_INTENSET4_COMPARE11_Msk (0x1UL << GRTC_INTENSET4_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
30766   #define GRTC_INTENSET4_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
30767   #define GRTC_INTENSET4_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
30768   #define GRTC_INTENSET4_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
30769   #define GRTC_INTENSET4_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30770   #define GRTC_INTENSET4_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30771 
30772 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
30773   #define GRTC_INTENSET4_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
30774   #define GRTC_INTENSET4_COMPARE12_Msk (0x1UL << GRTC_INTENSET4_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
30775   #define GRTC_INTENSET4_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
30776   #define GRTC_INTENSET4_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
30777   #define GRTC_INTENSET4_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
30778   #define GRTC_INTENSET4_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30779   #define GRTC_INTENSET4_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30780 
30781 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
30782   #define GRTC_INTENSET4_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
30783   #define GRTC_INTENSET4_COMPARE13_Msk (0x1UL << GRTC_INTENSET4_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
30784   #define GRTC_INTENSET4_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
30785   #define GRTC_INTENSET4_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
30786   #define GRTC_INTENSET4_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
30787   #define GRTC_INTENSET4_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30788   #define GRTC_INTENSET4_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30789 
30790 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
30791   #define GRTC_INTENSET4_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
30792   #define GRTC_INTENSET4_COMPARE14_Msk (0x1UL << GRTC_INTENSET4_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
30793   #define GRTC_INTENSET4_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
30794   #define GRTC_INTENSET4_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
30795   #define GRTC_INTENSET4_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
30796   #define GRTC_INTENSET4_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30797   #define GRTC_INTENSET4_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30798 
30799 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
30800   #define GRTC_INTENSET4_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
30801   #define GRTC_INTENSET4_COMPARE15_Msk (0x1UL << GRTC_INTENSET4_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
30802   #define GRTC_INTENSET4_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
30803   #define GRTC_INTENSET4_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
30804   #define GRTC_INTENSET4_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
30805   #define GRTC_INTENSET4_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30806   #define GRTC_INTENSET4_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30807 
30808 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
30809   #define GRTC_INTENSET4_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
30810   #define GRTC_INTENSET4_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET4_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
30811                                                                             field.*/
30812   #define GRTC_INTENSET4_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
30813   #define GRTC_INTENSET4_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
30814   #define GRTC_INTENSET4_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
30815   #define GRTC_INTENSET4_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
30816   #define GRTC_INTENSET4_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
30817 
30818 
30819 /* GRTC_INTENCLR4: Disable interrupt */
30820   #define GRTC_INTENCLR4_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR4 register.                                   */
30821 
30822 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
30823   #define GRTC_INTENCLR4_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
30824   #define GRTC_INTENCLR4_COMPARE0_Msk (0x1UL << GRTC_INTENCLR4_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
30825   #define GRTC_INTENCLR4_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
30826   #define GRTC_INTENCLR4_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
30827   #define GRTC_INTENCLR4_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
30828   #define GRTC_INTENCLR4_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30829   #define GRTC_INTENCLR4_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30830 
30831 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
30832   #define GRTC_INTENCLR4_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
30833   #define GRTC_INTENCLR4_COMPARE1_Msk (0x1UL << GRTC_INTENCLR4_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
30834   #define GRTC_INTENCLR4_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
30835   #define GRTC_INTENCLR4_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
30836   #define GRTC_INTENCLR4_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
30837   #define GRTC_INTENCLR4_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30838   #define GRTC_INTENCLR4_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30839 
30840 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
30841   #define GRTC_INTENCLR4_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
30842   #define GRTC_INTENCLR4_COMPARE2_Msk (0x1UL << GRTC_INTENCLR4_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
30843   #define GRTC_INTENCLR4_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
30844   #define GRTC_INTENCLR4_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
30845   #define GRTC_INTENCLR4_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
30846   #define GRTC_INTENCLR4_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30847   #define GRTC_INTENCLR4_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30848 
30849 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
30850   #define GRTC_INTENCLR4_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
30851   #define GRTC_INTENCLR4_COMPARE3_Msk (0x1UL << GRTC_INTENCLR4_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
30852   #define GRTC_INTENCLR4_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
30853   #define GRTC_INTENCLR4_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
30854   #define GRTC_INTENCLR4_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
30855   #define GRTC_INTENCLR4_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30856   #define GRTC_INTENCLR4_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30857 
30858 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
30859   #define GRTC_INTENCLR4_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
30860   #define GRTC_INTENCLR4_COMPARE4_Msk (0x1UL << GRTC_INTENCLR4_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
30861   #define GRTC_INTENCLR4_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
30862   #define GRTC_INTENCLR4_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
30863   #define GRTC_INTENCLR4_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
30864   #define GRTC_INTENCLR4_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30865   #define GRTC_INTENCLR4_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30866 
30867 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
30868   #define GRTC_INTENCLR4_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
30869   #define GRTC_INTENCLR4_COMPARE5_Msk (0x1UL << GRTC_INTENCLR4_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
30870   #define GRTC_INTENCLR4_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
30871   #define GRTC_INTENCLR4_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
30872   #define GRTC_INTENCLR4_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
30873   #define GRTC_INTENCLR4_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30874   #define GRTC_INTENCLR4_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30875 
30876 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
30877   #define GRTC_INTENCLR4_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
30878   #define GRTC_INTENCLR4_COMPARE6_Msk (0x1UL << GRTC_INTENCLR4_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
30879   #define GRTC_INTENCLR4_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
30880   #define GRTC_INTENCLR4_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
30881   #define GRTC_INTENCLR4_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
30882   #define GRTC_INTENCLR4_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30883   #define GRTC_INTENCLR4_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30884 
30885 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
30886   #define GRTC_INTENCLR4_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
30887   #define GRTC_INTENCLR4_COMPARE7_Msk (0x1UL << GRTC_INTENCLR4_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
30888   #define GRTC_INTENCLR4_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
30889   #define GRTC_INTENCLR4_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
30890   #define GRTC_INTENCLR4_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
30891   #define GRTC_INTENCLR4_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30892   #define GRTC_INTENCLR4_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30893 
30894 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
30895   #define GRTC_INTENCLR4_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
30896   #define GRTC_INTENCLR4_COMPARE8_Msk (0x1UL << GRTC_INTENCLR4_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
30897   #define GRTC_INTENCLR4_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
30898   #define GRTC_INTENCLR4_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
30899   #define GRTC_INTENCLR4_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
30900   #define GRTC_INTENCLR4_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30901   #define GRTC_INTENCLR4_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30902 
30903 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
30904   #define GRTC_INTENCLR4_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
30905   #define GRTC_INTENCLR4_COMPARE9_Msk (0x1UL << GRTC_INTENCLR4_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
30906   #define GRTC_INTENCLR4_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
30907   #define GRTC_INTENCLR4_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
30908   #define GRTC_INTENCLR4_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
30909   #define GRTC_INTENCLR4_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
30910   #define GRTC_INTENCLR4_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
30911 
30912 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
30913   #define GRTC_INTENCLR4_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
30914   #define GRTC_INTENCLR4_COMPARE10_Msk (0x1UL << GRTC_INTENCLR4_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
30915   #define GRTC_INTENCLR4_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
30916   #define GRTC_INTENCLR4_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
30917   #define GRTC_INTENCLR4_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
30918   #define GRTC_INTENCLR4_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30919   #define GRTC_INTENCLR4_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30920 
30921 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
30922   #define GRTC_INTENCLR4_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
30923   #define GRTC_INTENCLR4_COMPARE11_Msk (0x1UL << GRTC_INTENCLR4_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
30924   #define GRTC_INTENCLR4_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
30925   #define GRTC_INTENCLR4_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
30926   #define GRTC_INTENCLR4_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
30927   #define GRTC_INTENCLR4_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30928   #define GRTC_INTENCLR4_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30929 
30930 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
30931   #define GRTC_INTENCLR4_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
30932   #define GRTC_INTENCLR4_COMPARE12_Msk (0x1UL << GRTC_INTENCLR4_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
30933   #define GRTC_INTENCLR4_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
30934   #define GRTC_INTENCLR4_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
30935   #define GRTC_INTENCLR4_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
30936   #define GRTC_INTENCLR4_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30937   #define GRTC_INTENCLR4_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30938 
30939 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
30940   #define GRTC_INTENCLR4_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
30941   #define GRTC_INTENCLR4_COMPARE13_Msk (0x1UL << GRTC_INTENCLR4_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
30942   #define GRTC_INTENCLR4_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
30943   #define GRTC_INTENCLR4_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
30944   #define GRTC_INTENCLR4_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
30945   #define GRTC_INTENCLR4_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30946   #define GRTC_INTENCLR4_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30947 
30948 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
30949   #define GRTC_INTENCLR4_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
30950   #define GRTC_INTENCLR4_COMPARE14_Msk (0x1UL << GRTC_INTENCLR4_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
30951   #define GRTC_INTENCLR4_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
30952   #define GRTC_INTENCLR4_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
30953   #define GRTC_INTENCLR4_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
30954   #define GRTC_INTENCLR4_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30955   #define GRTC_INTENCLR4_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30956 
30957 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
30958   #define GRTC_INTENCLR4_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
30959   #define GRTC_INTENCLR4_COMPARE15_Msk (0x1UL << GRTC_INTENCLR4_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
30960   #define GRTC_INTENCLR4_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
30961   #define GRTC_INTENCLR4_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
30962   #define GRTC_INTENCLR4_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
30963   #define GRTC_INTENCLR4_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
30964   #define GRTC_INTENCLR4_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
30965 
30966 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
30967   #define GRTC_INTENCLR4_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
30968   #define GRTC_INTENCLR4_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR4_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
30969                                                                             field.*/
30970   #define GRTC_INTENCLR4_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
30971   #define GRTC_INTENCLR4_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
30972   #define GRTC_INTENCLR4_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
30973   #define GRTC_INTENCLR4_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
30974   #define GRTC_INTENCLR4_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
30975 
30976 
30977 /* GRTC_INTPEND4: Pending interrupts */
30978   #define GRTC_INTPEND4_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND4 register.                                    */
30979 
30980 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
30981   #define GRTC_INTPEND4_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
30982   #define GRTC_INTPEND4_COMPARE0_Msk (0x1UL << GRTC_INTPEND4_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
30983   #define GRTC_INTPEND4_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
30984   #define GRTC_INTPEND4_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
30985   #define GRTC_INTPEND4_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30986   #define GRTC_INTPEND4_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
30987 
30988 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
30989   #define GRTC_INTPEND4_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
30990   #define GRTC_INTPEND4_COMPARE1_Msk (0x1UL << GRTC_INTPEND4_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
30991   #define GRTC_INTPEND4_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
30992   #define GRTC_INTPEND4_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
30993   #define GRTC_INTPEND4_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
30994   #define GRTC_INTPEND4_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
30995 
30996 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
30997   #define GRTC_INTPEND4_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
30998   #define GRTC_INTPEND4_COMPARE2_Msk (0x1UL << GRTC_INTPEND4_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
30999   #define GRTC_INTPEND4_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
31000   #define GRTC_INTPEND4_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
31001   #define GRTC_INTPEND4_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31002   #define GRTC_INTPEND4_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
31003 
31004 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
31005   #define GRTC_INTPEND4_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
31006   #define GRTC_INTPEND4_COMPARE3_Msk (0x1UL << GRTC_INTPEND4_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
31007   #define GRTC_INTPEND4_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
31008   #define GRTC_INTPEND4_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
31009   #define GRTC_INTPEND4_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31010   #define GRTC_INTPEND4_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
31011 
31012 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
31013   #define GRTC_INTPEND4_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
31014   #define GRTC_INTPEND4_COMPARE4_Msk (0x1UL << GRTC_INTPEND4_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
31015   #define GRTC_INTPEND4_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
31016   #define GRTC_INTPEND4_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
31017   #define GRTC_INTPEND4_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31018   #define GRTC_INTPEND4_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
31019 
31020 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
31021   #define GRTC_INTPEND4_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
31022   #define GRTC_INTPEND4_COMPARE5_Msk (0x1UL << GRTC_INTPEND4_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
31023   #define GRTC_INTPEND4_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
31024   #define GRTC_INTPEND4_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
31025   #define GRTC_INTPEND4_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31026   #define GRTC_INTPEND4_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
31027 
31028 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
31029   #define GRTC_INTPEND4_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
31030   #define GRTC_INTPEND4_COMPARE6_Msk (0x1UL << GRTC_INTPEND4_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
31031   #define GRTC_INTPEND4_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
31032   #define GRTC_INTPEND4_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
31033   #define GRTC_INTPEND4_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31034   #define GRTC_INTPEND4_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
31035 
31036 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
31037   #define GRTC_INTPEND4_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
31038   #define GRTC_INTPEND4_COMPARE7_Msk (0x1UL << GRTC_INTPEND4_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
31039   #define GRTC_INTPEND4_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
31040   #define GRTC_INTPEND4_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
31041   #define GRTC_INTPEND4_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31042   #define GRTC_INTPEND4_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
31043 
31044 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
31045   #define GRTC_INTPEND4_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
31046   #define GRTC_INTPEND4_COMPARE8_Msk (0x1UL << GRTC_INTPEND4_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
31047   #define GRTC_INTPEND4_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
31048   #define GRTC_INTPEND4_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
31049   #define GRTC_INTPEND4_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31050   #define GRTC_INTPEND4_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
31051 
31052 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
31053   #define GRTC_INTPEND4_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
31054   #define GRTC_INTPEND4_COMPARE9_Msk (0x1UL << GRTC_INTPEND4_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
31055   #define GRTC_INTPEND4_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
31056   #define GRTC_INTPEND4_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
31057   #define GRTC_INTPEND4_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31058   #define GRTC_INTPEND4_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
31059 
31060 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
31061   #define GRTC_INTPEND4_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
31062   #define GRTC_INTPEND4_COMPARE10_Msk (0x1UL << GRTC_INTPEND4_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
31063   #define GRTC_INTPEND4_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
31064   #define GRTC_INTPEND4_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
31065   #define GRTC_INTPEND4_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31066   #define GRTC_INTPEND4_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
31067 
31068 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
31069   #define GRTC_INTPEND4_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
31070   #define GRTC_INTPEND4_COMPARE11_Msk (0x1UL << GRTC_INTPEND4_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
31071   #define GRTC_INTPEND4_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
31072   #define GRTC_INTPEND4_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
31073   #define GRTC_INTPEND4_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31074   #define GRTC_INTPEND4_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
31075 
31076 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
31077   #define GRTC_INTPEND4_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
31078   #define GRTC_INTPEND4_COMPARE12_Msk (0x1UL << GRTC_INTPEND4_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
31079   #define GRTC_INTPEND4_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
31080   #define GRTC_INTPEND4_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
31081   #define GRTC_INTPEND4_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31082   #define GRTC_INTPEND4_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
31083 
31084 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
31085   #define GRTC_INTPEND4_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
31086   #define GRTC_INTPEND4_COMPARE13_Msk (0x1UL << GRTC_INTPEND4_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
31087   #define GRTC_INTPEND4_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
31088   #define GRTC_INTPEND4_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
31089   #define GRTC_INTPEND4_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31090   #define GRTC_INTPEND4_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
31091 
31092 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
31093   #define GRTC_INTPEND4_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
31094   #define GRTC_INTPEND4_COMPARE14_Msk (0x1UL << GRTC_INTPEND4_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
31095   #define GRTC_INTPEND4_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
31096   #define GRTC_INTPEND4_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
31097   #define GRTC_INTPEND4_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31098   #define GRTC_INTPEND4_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
31099 
31100 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
31101   #define GRTC_INTPEND4_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
31102   #define GRTC_INTPEND4_COMPARE15_Msk (0x1UL << GRTC_INTPEND4_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
31103   #define GRTC_INTPEND4_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
31104   #define GRTC_INTPEND4_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
31105   #define GRTC_INTPEND4_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31106   #define GRTC_INTPEND4_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
31107 
31108 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
31109   #define GRTC_INTPEND4_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
31110   #define GRTC_INTPEND4_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND4_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
31111                                                                             field.*/
31112   #define GRTC_INTPEND4_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
31113   #define GRTC_INTPEND4_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
31114   #define GRTC_INTPEND4_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
31115   #define GRTC_INTPEND4_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
31116 
31117 
31118 /* GRTC_INTEN5: Enable or disable interrupt */
31119   #define GRTC_INTEN5_ResetValue (0x00000000UL)      /*!< Reset value of INTEN5 register.                                      */
31120 
31121 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
31122   #define GRTC_INTEN5_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
31123   #define GRTC_INTEN5_COMPARE0_Msk (0x1UL << GRTC_INTEN5_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
31124   #define GRTC_INTEN5_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
31125   #define GRTC_INTEN5_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
31126   #define GRTC_INTEN5_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
31127   #define GRTC_INTEN5_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
31128 
31129 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
31130   #define GRTC_INTEN5_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
31131   #define GRTC_INTEN5_COMPARE1_Msk (0x1UL << GRTC_INTEN5_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
31132   #define GRTC_INTEN5_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
31133   #define GRTC_INTEN5_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
31134   #define GRTC_INTEN5_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
31135   #define GRTC_INTEN5_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
31136 
31137 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
31138   #define GRTC_INTEN5_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
31139   #define GRTC_INTEN5_COMPARE2_Msk (0x1UL << GRTC_INTEN5_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
31140   #define GRTC_INTEN5_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
31141   #define GRTC_INTEN5_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
31142   #define GRTC_INTEN5_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
31143   #define GRTC_INTEN5_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
31144 
31145 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
31146   #define GRTC_INTEN5_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
31147   #define GRTC_INTEN5_COMPARE3_Msk (0x1UL << GRTC_INTEN5_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
31148   #define GRTC_INTEN5_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
31149   #define GRTC_INTEN5_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
31150   #define GRTC_INTEN5_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
31151   #define GRTC_INTEN5_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
31152 
31153 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
31154   #define GRTC_INTEN5_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
31155   #define GRTC_INTEN5_COMPARE4_Msk (0x1UL << GRTC_INTEN5_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
31156   #define GRTC_INTEN5_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
31157   #define GRTC_INTEN5_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
31158   #define GRTC_INTEN5_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
31159   #define GRTC_INTEN5_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
31160 
31161 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
31162   #define GRTC_INTEN5_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
31163   #define GRTC_INTEN5_COMPARE5_Msk (0x1UL << GRTC_INTEN5_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
31164   #define GRTC_INTEN5_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
31165   #define GRTC_INTEN5_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
31166   #define GRTC_INTEN5_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
31167   #define GRTC_INTEN5_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
31168 
31169 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
31170   #define GRTC_INTEN5_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
31171   #define GRTC_INTEN5_COMPARE6_Msk (0x1UL << GRTC_INTEN5_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
31172   #define GRTC_INTEN5_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
31173   #define GRTC_INTEN5_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
31174   #define GRTC_INTEN5_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
31175   #define GRTC_INTEN5_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
31176 
31177 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
31178   #define GRTC_INTEN5_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
31179   #define GRTC_INTEN5_COMPARE7_Msk (0x1UL << GRTC_INTEN5_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
31180   #define GRTC_INTEN5_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
31181   #define GRTC_INTEN5_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
31182   #define GRTC_INTEN5_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
31183   #define GRTC_INTEN5_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
31184 
31185 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
31186   #define GRTC_INTEN5_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
31187   #define GRTC_INTEN5_COMPARE8_Msk (0x1UL << GRTC_INTEN5_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
31188   #define GRTC_INTEN5_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
31189   #define GRTC_INTEN5_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
31190   #define GRTC_INTEN5_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
31191   #define GRTC_INTEN5_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
31192 
31193 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
31194   #define GRTC_INTEN5_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
31195   #define GRTC_INTEN5_COMPARE9_Msk (0x1UL << GRTC_INTEN5_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
31196   #define GRTC_INTEN5_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
31197   #define GRTC_INTEN5_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
31198   #define GRTC_INTEN5_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
31199   #define GRTC_INTEN5_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
31200 
31201 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
31202   #define GRTC_INTEN5_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
31203   #define GRTC_INTEN5_COMPARE10_Msk (0x1UL << GRTC_INTEN5_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
31204   #define GRTC_INTEN5_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
31205   #define GRTC_INTEN5_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
31206   #define GRTC_INTEN5_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
31207   #define GRTC_INTEN5_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
31208 
31209 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
31210   #define GRTC_INTEN5_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
31211   #define GRTC_INTEN5_COMPARE11_Msk (0x1UL << GRTC_INTEN5_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
31212   #define GRTC_INTEN5_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
31213   #define GRTC_INTEN5_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
31214   #define GRTC_INTEN5_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
31215   #define GRTC_INTEN5_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
31216 
31217 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
31218   #define GRTC_INTEN5_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
31219   #define GRTC_INTEN5_COMPARE12_Msk (0x1UL << GRTC_INTEN5_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
31220   #define GRTC_INTEN5_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
31221   #define GRTC_INTEN5_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
31222   #define GRTC_INTEN5_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
31223   #define GRTC_INTEN5_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
31224 
31225 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
31226   #define GRTC_INTEN5_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
31227   #define GRTC_INTEN5_COMPARE13_Msk (0x1UL << GRTC_INTEN5_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
31228   #define GRTC_INTEN5_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
31229   #define GRTC_INTEN5_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
31230   #define GRTC_INTEN5_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
31231   #define GRTC_INTEN5_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
31232 
31233 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
31234   #define GRTC_INTEN5_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
31235   #define GRTC_INTEN5_COMPARE14_Msk (0x1UL << GRTC_INTEN5_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
31236   #define GRTC_INTEN5_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
31237   #define GRTC_INTEN5_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
31238   #define GRTC_INTEN5_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
31239   #define GRTC_INTEN5_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
31240 
31241 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
31242   #define GRTC_INTEN5_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
31243   #define GRTC_INTEN5_COMPARE15_Msk (0x1UL << GRTC_INTEN5_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
31244   #define GRTC_INTEN5_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
31245   #define GRTC_INTEN5_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
31246   #define GRTC_INTEN5_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
31247   #define GRTC_INTEN5_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
31248 
31249 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
31250   #define GRTC_INTEN5_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
31251   #define GRTC_INTEN5_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN5_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
31252   #define GRTC_INTEN5_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
31253   #define GRTC_INTEN5_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
31254   #define GRTC_INTEN5_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
31255   #define GRTC_INTEN5_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
31256 
31257 
31258 /* GRTC_INTENSET5: Enable interrupt */
31259   #define GRTC_INTENSET5_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET5 register.                                   */
31260 
31261 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
31262   #define GRTC_INTENSET5_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
31263   #define GRTC_INTENSET5_COMPARE0_Msk (0x1UL << GRTC_INTENSET5_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
31264   #define GRTC_INTENSET5_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
31265   #define GRTC_INTENSET5_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
31266   #define GRTC_INTENSET5_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
31267   #define GRTC_INTENSET5_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31268   #define GRTC_INTENSET5_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31269 
31270 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
31271   #define GRTC_INTENSET5_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
31272   #define GRTC_INTENSET5_COMPARE1_Msk (0x1UL << GRTC_INTENSET5_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
31273   #define GRTC_INTENSET5_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
31274   #define GRTC_INTENSET5_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
31275   #define GRTC_INTENSET5_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
31276   #define GRTC_INTENSET5_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31277   #define GRTC_INTENSET5_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31278 
31279 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
31280   #define GRTC_INTENSET5_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
31281   #define GRTC_INTENSET5_COMPARE2_Msk (0x1UL << GRTC_INTENSET5_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
31282   #define GRTC_INTENSET5_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
31283   #define GRTC_INTENSET5_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
31284   #define GRTC_INTENSET5_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
31285   #define GRTC_INTENSET5_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31286   #define GRTC_INTENSET5_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31287 
31288 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
31289   #define GRTC_INTENSET5_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
31290   #define GRTC_INTENSET5_COMPARE3_Msk (0x1UL << GRTC_INTENSET5_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
31291   #define GRTC_INTENSET5_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
31292   #define GRTC_INTENSET5_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
31293   #define GRTC_INTENSET5_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
31294   #define GRTC_INTENSET5_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31295   #define GRTC_INTENSET5_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31296 
31297 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
31298   #define GRTC_INTENSET5_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
31299   #define GRTC_INTENSET5_COMPARE4_Msk (0x1UL << GRTC_INTENSET5_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
31300   #define GRTC_INTENSET5_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
31301   #define GRTC_INTENSET5_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
31302   #define GRTC_INTENSET5_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
31303   #define GRTC_INTENSET5_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31304   #define GRTC_INTENSET5_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31305 
31306 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
31307   #define GRTC_INTENSET5_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
31308   #define GRTC_INTENSET5_COMPARE5_Msk (0x1UL << GRTC_INTENSET5_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
31309   #define GRTC_INTENSET5_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
31310   #define GRTC_INTENSET5_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
31311   #define GRTC_INTENSET5_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
31312   #define GRTC_INTENSET5_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31313   #define GRTC_INTENSET5_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31314 
31315 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
31316   #define GRTC_INTENSET5_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
31317   #define GRTC_INTENSET5_COMPARE6_Msk (0x1UL << GRTC_INTENSET5_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
31318   #define GRTC_INTENSET5_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
31319   #define GRTC_INTENSET5_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
31320   #define GRTC_INTENSET5_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
31321   #define GRTC_INTENSET5_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31322   #define GRTC_INTENSET5_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31323 
31324 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
31325   #define GRTC_INTENSET5_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
31326   #define GRTC_INTENSET5_COMPARE7_Msk (0x1UL << GRTC_INTENSET5_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
31327   #define GRTC_INTENSET5_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
31328   #define GRTC_INTENSET5_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
31329   #define GRTC_INTENSET5_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
31330   #define GRTC_INTENSET5_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31331   #define GRTC_INTENSET5_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31332 
31333 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
31334   #define GRTC_INTENSET5_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
31335   #define GRTC_INTENSET5_COMPARE8_Msk (0x1UL << GRTC_INTENSET5_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
31336   #define GRTC_INTENSET5_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
31337   #define GRTC_INTENSET5_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
31338   #define GRTC_INTENSET5_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
31339   #define GRTC_INTENSET5_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31340   #define GRTC_INTENSET5_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31341 
31342 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
31343   #define GRTC_INTENSET5_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
31344   #define GRTC_INTENSET5_COMPARE9_Msk (0x1UL << GRTC_INTENSET5_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
31345   #define GRTC_INTENSET5_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
31346   #define GRTC_INTENSET5_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
31347   #define GRTC_INTENSET5_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
31348   #define GRTC_INTENSET5_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31349   #define GRTC_INTENSET5_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31350 
31351 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
31352   #define GRTC_INTENSET5_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
31353   #define GRTC_INTENSET5_COMPARE10_Msk (0x1UL << GRTC_INTENSET5_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
31354   #define GRTC_INTENSET5_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
31355   #define GRTC_INTENSET5_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
31356   #define GRTC_INTENSET5_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
31357   #define GRTC_INTENSET5_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31358   #define GRTC_INTENSET5_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31359 
31360 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
31361   #define GRTC_INTENSET5_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
31362   #define GRTC_INTENSET5_COMPARE11_Msk (0x1UL << GRTC_INTENSET5_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
31363   #define GRTC_INTENSET5_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
31364   #define GRTC_INTENSET5_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
31365   #define GRTC_INTENSET5_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
31366   #define GRTC_INTENSET5_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31367   #define GRTC_INTENSET5_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31368 
31369 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
31370   #define GRTC_INTENSET5_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
31371   #define GRTC_INTENSET5_COMPARE12_Msk (0x1UL << GRTC_INTENSET5_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
31372   #define GRTC_INTENSET5_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
31373   #define GRTC_INTENSET5_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
31374   #define GRTC_INTENSET5_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
31375   #define GRTC_INTENSET5_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31376   #define GRTC_INTENSET5_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31377 
31378 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
31379   #define GRTC_INTENSET5_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
31380   #define GRTC_INTENSET5_COMPARE13_Msk (0x1UL << GRTC_INTENSET5_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
31381   #define GRTC_INTENSET5_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
31382   #define GRTC_INTENSET5_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
31383   #define GRTC_INTENSET5_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
31384   #define GRTC_INTENSET5_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31385   #define GRTC_INTENSET5_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31386 
31387 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
31388   #define GRTC_INTENSET5_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
31389   #define GRTC_INTENSET5_COMPARE14_Msk (0x1UL << GRTC_INTENSET5_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
31390   #define GRTC_INTENSET5_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
31391   #define GRTC_INTENSET5_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
31392   #define GRTC_INTENSET5_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
31393   #define GRTC_INTENSET5_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31394   #define GRTC_INTENSET5_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31395 
31396 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
31397   #define GRTC_INTENSET5_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
31398   #define GRTC_INTENSET5_COMPARE15_Msk (0x1UL << GRTC_INTENSET5_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
31399   #define GRTC_INTENSET5_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
31400   #define GRTC_INTENSET5_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
31401   #define GRTC_INTENSET5_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
31402   #define GRTC_INTENSET5_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31403   #define GRTC_INTENSET5_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31404 
31405 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
31406   #define GRTC_INTENSET5_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
31407   #define GRTC_INTENSET5_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET5_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
31408                                                                             field.*/
31409   #define GRTC_INTENSET5_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
31410   #define GRTC_INTENSET5_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
31411   #define GRTC_INTENSET5_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
31412   #define GRTC_INTENSET5_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
31413   #define GRTC_INTENSET5_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
31414 
31415 
31416 /* GRTC_INTENCLR5: Disable interrupt */
31417   #define GRTC_INTENCLR5_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR5 register.                                   */
31418 
31419 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
31420   #define GRTC_INTENCLR5_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
31421   #define GRTC_INTENCLR5_COMPARE0_Msk (0x1UL << GRTC_INTENCLR5_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
31422   #define GRTC_INTENCLR5_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
31423   #define GRTC_INTENCLR5_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
31424   #define GRTC_INTENCLR5_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
31425   #define GRTC_INTENCLR5_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31426   #define GRTC_INTENCLR5_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31427 
31428 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
31429   #define GRTC_INTENCLR5_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
31430   #define GRTC_INTENCLR5_COMPARE1_Msk (0x1UL << GRTC_INTENCLR5_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
31431   #define GRTC_INTENCLR5_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
31432   #define GRTC_INTENCLR5_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
31433   #define GRTC_INTENCLR5_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
31434   #define GRTC_INTENCLR5_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31435   #define GRTC_INTENCLR5_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31436 
31437 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
31438   #define GRTC_INTENCLR5_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
31439   #define GRTC_INTENCLR5_COMPARE2_Msk (0x1UL << GRTC_INTENCLR5_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
31440   #define GRTC_INTENCLR5_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
31441   #define GRTC_INTENCLR5_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
31442   #define GRTC_INTENCLR5_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
31443   #define GRTC_INTENCLR5_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31444   #define GRTC_INTENCLR5_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31445 
31446 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
31447   #define GRTC_INTENCLR5_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
31448   #define GRTC_INTENCLR5_COMPARE3_Msk (0x1UL << GRTC_INTENCLR5_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
31449   #define GRTC_INTENCLR5_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
31450   #define GRTC_INTENCLR5_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
31451   #define GRTC_INTENCLR5_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
31452   #define GRTC_INTENCLR5_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31453   #define GRTC_INTENCLR5_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31454 
31455 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
31456   #define GRTC_INTENCLR5_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
31457   #define GRTC_INTENCLR5_COMPARE4_Msk (0x1UL << GRTC_INTENCLR5_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
31458   #define GRTC_INTENCLR5_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
31459   #define GRTC_INTENCLR5_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
31460   #define GRTC_INTENCLR5_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
31461   #define GRTC_INTENCLR5_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31462   #define GRTC_INTENCLR5_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31463 
31464 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
31465   #define GRTC_INTENCLR5_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
31466   #define GRTC_INTENCLR5_COMPARE5_Msk (0x1UL << GRTC_INTENCLR5_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
31467   #define GRTC_INTENCLR5_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
31468   #define GRTC_INTENCLR5_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
31469   #define GRTC_INTENCLR5_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
31470   #define GRTC_INTENCLR5_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31471   #define GRTC_INTENCLR5_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31472 
31473 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
31474   #define GRTC_INTENCLR5_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
31475   #define GRTC_INTENCLR5_COMPARE6_Msk (0x1UL << GRTC_INTENCLR5_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
31476   #define GRTC_INTENCLR5_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
31477   #define GRTC_INTENCLR5_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
31478   #define GRTC_INTENCLR5_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
31479   #define GRTC_INTENCLR5_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31480   #define GRTC_INTENCLR5_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31481 
31482 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
31483   #define GRTC_INTENCLR5_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
31484   #define GRTC_INTENCLR5_COMPARE7_Msk (0x1UL << GRTC_INTENCLR5_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
31485   #define GRTC_INTENCLR5_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
31486   #define GRTC_INTENCLR5_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
31487   #define GRTC_INTENCLR5_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
31488   #define GRTC_INTENCLR5_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31489   #define GRTC_INTENCLR5_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31490 
31491 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
31492   #define GRTC_INTENCLR5_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
31493   #define GRTC_INTENCLR5_COMPARE8_Msk (0x1UL << GRTC_INTENCLR5_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
31494   #define GRTC_INTENCLR5_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
31495   #define GRTC_INTENCLR5_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
31496   #define GRTC_INTENCLR5_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
31497   #define GRTC_INTENCLR5_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31498   #define GRTC_INTENCLR5_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31499 
31500 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
31501   #define GRTC_INTENCLR5_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
31502   #define GRTC_INTENCLR5_COMPARE9_Msk (0x1UL << GRTC_INTENCLR5_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
31503   #define GRTC_INTENCLR5_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
31504   #define GRTC_INTENCLR5_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
31505   #define GRTC_INTENCLR5_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
31506   #define GRTC_INTENCLR5_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31507   #define GRTC_INTENCLR5_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31508 
31509 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
31510   #define GRTC_INTENCLR5_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
31511   #define GRTC_INTENCLR5_COMPARE10_Msk (0x1UL << GRTC_INTENCLR5_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
31512   #define GRTC_INTENCLR5_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
31513   #define GRTC_INTENCLR5_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
31514   #define GRTC_INTENCLR5_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
31515   #define GRTC_INTENCLR5_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31516   #define GRTC_INTENCLR5_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31517 
31518 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
31519   #define GRTC_INTENCLR5_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
31520   #define GRTC_INTENCLR5_COMPARE11_Msk (0x1UL << GRTC_INTENCLR5_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
31521   #define GRTC_INTENCLR5_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
31522   #define GRTC_INTENCLR5_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
31523   #define GRTC_INTENCLR5_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
31524   #define GRTC_INTENCLR5_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31525   #define GRTC_INTENCLR5_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31526 
31527 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
31528   #define GRTC_INTENCLR5_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
31529   #define GRTC_INTENCLR5_COMPARE12_Msk (0x1UL << GRTC_INTENCLR5_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
31530   #define GRTC_INTENCLR5_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
31531   #define GRTC_INTENCLR5_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
31532   #define GRTC_INTENCLR5_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
31533   #define GRTC_INTENCLR5_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31534   #define GRTC_INTENCLR5_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31535 
31536 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
31537   #define GRTC_INTENCLR5_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
31538   #define GRTC_INTENCLR5_COMPARE13_Msk (0x1UL << GRTC_INTENCLR5_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
31539   #define GRTC_INTENCLR5_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
31540   #define GRTC_INTENCLR5_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
31541   #define GRTC_INTENCLR5_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
31542   #define GRTC_INTENCLR5_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31543   #define GRTC_INTENCLR5_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31544 
31545 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
31546   #define GRTC_INTENCLR5_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
31547   #define GRTC_INTENCLR5_COMPARE14_Msk (0x1UL << GRTC_INTENCLR5_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
31548   #define GRTC_INTENCLR5_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
31549   #define GRTC_INTENCLR5_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
31550   #define GRTC_INTENCLR5_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
31551   #define GRTC_INTENCLR5_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31552   #define GRTC_INTENCLR5_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31553 
31554 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
31555   #define GRTC_INTENCLR5_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
31556   #define GRTC_INTENCLR5_COMPARE15_Msk (0x1UL << GRTC_INTENCLR5_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
31557   #define GRTC_INTENCLR5_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
31558   #define GRTC_INTENCLR5_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
31559   #define GRTC_INTENCLR5_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
31560   #define GRTC_INTENCLR5_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31561   #define GRTC_INTENCLR5_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31562 
31563 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
31564   #define GRTC_INTENCLR5_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
31565   #define GRTC_INTENCLR5_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR5_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
31566                                                                             field.*/
31567   #define GRTC_INTENCLR5_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
31568   #define GRTC_INTENCLR5_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
31569   #define GRTC_INTENCLR5_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
31570   #define GRTC_INTENCLR5_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
31571   #define GRTC_INTENCLR5_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
31572 
31573 
31574 /* GRTC_INTPEND5: Pending interrupts */
31575   #define GRTC_INTPEND5_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND5 register.                                    */
31576 
31577 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
31578   #define GRTC_INTPEND5_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
31579   #define GRTC_INTPEND5_COMPARE0_Msk (0x1UL << GRTC_INTPEND5_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
31580   #define GRTC_INTPEND5_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
31581   #define GRTC_INTPEND5_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
31582   #define GRTC_INTPEND5_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31583   #define GRTC_INTPEND5_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
31584 
31585 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
31586   #define GRTC_INTPEND5_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
31587   #define GRTC_INTPEND5_COMPARE1_Msk (0x1UL << GRTC_INTPEND5_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
31588   #define GRTC_INTPEND5_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
31589   #define GRTC_INTPEND5_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
31590   #define GRTC_INTPEND5_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31591   #define GRTC_INTPEND5_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
31592 
31593 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
31594   #define GRTC_INTPEND5_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
31595   #define GRTC_INTPEND5_COMPARE2_Msk (0x1UL << GRTC_INTPEND5_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
31596   #define GRTC_INTPEND5_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
31597   #define GRTC_INTPEND5_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
31598   #define GRTC_INTPEND5_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31599   #define GRTC_INTPEND5_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
31600 
31601 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
31602   #define GRTC_INTPEND5_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
31603   #define GRTC_INTPEND5_COMPARE3_Msk (0x1UL << GRTC_INTPEND5_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
31604   #define GRTC_INTPEND5_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
31605   #define GRTC_INTPEND5_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
31606   #define GRTC_INTPEND5_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31607   #define GRTC_INTPEND5_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
31608 
31609 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
31610   #define GRTC_INTPEND5_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
31611   #define GRTC_INTPEND5_COMPARE4_Msk (0x1UL << GRTC_INTPEND5_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
31612   #define GRTC_INTPEND5_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
31613   #define GRTC_INTPEND5_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
31614   #define GRTC_INTPEND5_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31615   #define GRTC_INTPEND5_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
31616 
31617 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
31618   #define GRTC_INTPEND5_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
31619   #define GRTC_INTPEND5_COMPARE5_Msk (0x1UL << GRTC_INTPEND5_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
31620   #define GRTC_INTPEND5_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
31621   #define GRTC_INTPEND5_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
31622   #define GRTC_INTPEND5_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31623   #define GRTC_INTPEND5_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
31624 
31625 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
31626   #define GRTC_INTPEND5_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
31627   #define GRTC_INTPEND5_COMPARE6_Msk (0x1UL << GRTC_INTPEND5_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
31628   #define GRTC_INTPEND5_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
31629   #define GRTC_INTPEND5_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
31630   #define GRTC_INTPEND5_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31631   #define GRTC_INTPEND5_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
31632 
31633 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
31634   #define GRTC_INTPEND5_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
31635   #define GRTC_INTPEND5_COMPARE7_Msk (0x1UL << GRTC_INTPEND5_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
31636   #define GRTC_INTPEND5_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
31637   #define GRTC_INTPEND5_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
31638   #define GRTC_INTPEND5_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31639   #define GRTC_INTPEND5_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
31640 
31641 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
31642   #define GRTC_INTPEND5_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
31643   #define GRTC_INTPEND5_COMPARE8_Msk (0x1UL << GRTC_INTPEND5_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
31644   #define GRTC_INTPEND5_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
31645   #define GRTC_INTPEND5_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
31646   #define GRTC_INTPEND5_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31647   #define GRTC_INTPEND5_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
31648 
31649 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
31650   #define GRTC_INTPEND5_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
31651   #define GRTC_INTPEND5_COMPARE9_Msk (0x1UL << GRTC_INTPEND5_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
31652   #define GRTC_INTPEND5_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
31653   #define GRTC_INTPEND5_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
31654   #define GRTC_INTPEND5_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
31655   #define GRTC_INTPEND5_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
31656 
31657 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
31658   #define GRTC_INTPEND5_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
31659   #define GRTC_INTPEND5_COMPARE10_Msk (0x1UL << GRTC_INTPEND5_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
31660   #define GRTC_INTPEND5_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
31661   #define GRTC_INTPEND5_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
31662   #define GRTC_INTPEND5_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31663   #define GRTC_INTPEND5_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
31664 
31665 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
31666   #define GRTC_INTPEND5_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
31667   #define GRTC_INTPEND5_COMPARE11_Msk (0x1UL << GRTC_INTPEND5_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
31668   #define GRTC_INTPEND5_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
31669   #define GRTC_INTPEND5_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
31670   #define GRTC_INTPEND5_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31671   #define GRTC_INTPEND5_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
31672 
31673 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
31674   #define GRTC_INTPEND5_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
31675   #define GRTC_INTPEND5_COMPARE12_Msk (0x1UL << GRTC_INTPEND5_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
31676   #define GRTC_INTPEND5_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
31677   #define GRTC_INTPEND5_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
31678   #define GRTC_INTPEND5_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31679   #define GRTC_INTPEND5_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
31680 
31681 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
31682   #define GRTC_INTPEND5_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
31683   #define GRTC_INTPEND5_COMPARE13_Msk (0x1UL << GRTC_INTPEND5_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
31684   #define GRTC_INTPEND5_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
31685   #define GRTC_INTPEND5_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
31686   #define GRTC_INTPEND5_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31687   #define GRTC_INTPEND5_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
31688 
31689 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
31690   #define GRTC_INTPEND5_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
31691   #define GRTC_INTPEND5_COMPARE14_Msk (0x1UL << GRTC_INTPEND5_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
31692   #define GRTC_INTPEND5_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
31693   #define GRTC_INTPEND5_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
31694   #define GRTC_INTPEND5_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31695   #define GRTC_INTPEND5_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
31696 
31697 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
31698   #define GRTC_INTPEND5_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
31699   #define GRTC_INTPEND5_COMPARE15_Msk (0x1UL << GRTC_INTPEND5_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
31700   #define GRTC_INTPEND5_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
31701   #define GRTC_INTPEND5_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
31702   #define GRTC_INTPEND5_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
31703   #define GRTC_INTPEND5_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
31704 
31705 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
31706   #define GRTC_INTPEND5_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
31707   #define GRTC_INTPEND5_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND5_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
31708                                                                             field.*/
31709   #define GRTC_INTPEND5_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
31710   #define GRTC_INTPEND5_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
31711   #define GRTC_INTPEND5_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
31712   #define GRTC_INTPEND5_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
31713 
31714 
31715 /* GRTC_INTEN6: Enable or disable interrupt */
31716   #define GRTC_INTEN6_ResetValue (0x00000000UL)      /*!< Reset value of INTEN6 register.                                      */
31717 
31718 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
31719   #define GRTC_INTEN6_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
31720   #define GRTC_INTEN6_COMPARE0_Msk (0x1UL << GRTC_INTEN6_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
31721   #define GRTC_INTEN6_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
31722   #define GRTC_INTEN6_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
31723   #define GRTC_INTEN6_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
31724   #define GRTC_INTEN6_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
31725 
31726 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
31727   #define GRTC_INTEN6_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
31728   #define GRTC_INTEN6_COMPARE1_Msk (0x1UL << GRTC_INTEN6_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
31729   #define GRTC_INTEN6_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
31730   #define GRTC_INTEN6_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
31731   #define GRTC_INTEN6_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
31732   #define GRTC_INTEN6_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
31733 
31734 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
31735   #define GRTC_INTEN6_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
31736   #define GRTC_INTEN6_COMPARE2_Msk (0x1UL << GRTC_INTEN6_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
31737   #define GRTC_INTEN6_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
31738   #define GRTC_INTEN6_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
31739   #define GRTC_INTEN6_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
31740   #define GRTC_INTEN6_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
31741 
31742 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
31743   #define GRTC_INTEN6_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
31744   #define GRTC_INTEN6_COMPARE3_Msk (0x1UL << GRTC_INTEN6_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
31745   #define GRTC_INTEN6_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
31746   #define GRTC_INTEN6_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
31747   #define GRTC_INTEN6_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
31748   #define GRTC_INTEN6_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
31749 
31750 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
31751   #define GRTC_INTEN6_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
31752   #define GRTC_INTEN6_COMPARE4_Msk (0x1UL << GRTC_INTEN6_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
31753   #define GRTC_INTEN6_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
31754   #define GRTC_INTEN6_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
31755   #define GRTC_INTEN6_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
31756   #define GRTC_INTEN6_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
31757 
31758 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
31759   #define GRTC_INTEN6_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
31760   #define GRTC_INTEN6_COMPARE5_Msk (0x1UL << GRTC_INTEN6_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
31761   #define GRTC_INTEN6_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
31762   #define GRTC_INTEN6_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
31763   #define GRTC_INTEN6_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
31764   #define GRTC_INTEN6_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
31765 
31766 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
31767   #define GRTC_INTEN6_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
31768   #define GRTC_INTEN6_COMPARE6_Msk (0x1UL << GRTC_INTEN6_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
31769   #define GRTC_INTEN6_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
31770   #define GRTC_INTEN6_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
31771   #define GRTC_INTEN6_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
31772   #define GRTC_INTEN6_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
31773 
31774 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
31775   #define GRTC_INTEN6_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
31776   #define GRTC_INTEN6_COMPARE7_Msk (0x1UL << GRTC_INTEN6_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
31777   #define GRTC_INTEN6_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
31778   #define GRTC_INTEN6_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
31779   #define GRTC_INTEN6_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
31780   #define GRTC_INTEN6_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
31781 
31782 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
31783   #define GRTC_INTEN6_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
31784   #define GRTC_INTEN6_COMPARE8_Msk (0x1UL << GRTC_INTEN6_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
31785   #define GRTC_INTEN6_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
31786   #define GRTC_INTEN6_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
31787   #define GRTC_INTEN6_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
31788   #define GRTC_INTEN6_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
31789 
31790 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
31791   #define GRTC_INTEN6_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
31792   #define GRTC_INTEN6_COMPARE9_Msk (0x1UL << GRTC_INTEN6_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
31793   #define GRTC_INTEN6_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
31794   #define GRTC_INTEN6_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
31795   #define GRTC_INTEN6_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
31796   #define GRTC_INTEN6_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
31797 
31798 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
31799   #define GRTC_INTEN6_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
31800   #define GRTC_INTEN6_COMPARE10_Msk (0x1UL << GRTC_INTEN6_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
31801   #define GRTC_INTEN6_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
31802   #define GRTC_INTEN6_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
31803   #define GRTC_INTEN6_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
31804   #define GRTC_INTEN6_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
31805 
31806 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
31807   #define GRTC_INTEN6_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
31808   #define GRTC_INTEN6_COMPARE11_Msk (0x1UL << GRTC_INTEN6_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
31809   #define GRTC_INTEN6_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
31810   #define GRTC_INTEN6_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
31811   #define GRTC_INTEN6_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
31812   #define GRTC_INTEN6_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
31813 
31814 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
31815   #define GRTC_INTEN6_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
31816   #define GRTC_INTEN6_COMPARE12_Msk (0x1UL << GRTC_INTEN6_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
31817   #define GRTC_INTEN6_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
31818   #define GRTC_INTEN6_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
31819   #define GRTC_INTEN6_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
31820   #define GRTC_INTEN6_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
31821 
31822 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
31823   #define GRTC_INTEN6_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
31824   #define GRTC_INTEN6_COMPARE13_Msk (0x1UL << GRTC_INTEN6_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
31825   #define GRTC_INTEN6_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
31826   #define GRTC_INTEN6_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
31827   #define GRTC_INTEN6_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
31828   #define GRTC_INTEN6_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
31829 
31830 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
31831   #define GRTC_INTEN6_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
31832   #define GRTC_INTEN6_COMPARE14_Msk (0x1UL << GRTC_INTEN6_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
31833   #define GRTC_INTEN6_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
31834   #define GRTC_INTEN6_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
31835   #define GRTC_INTEN6_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
31836   #define GRTC_INTEN6_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
31837 
31838 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
31839   #define GRTC_INTEN6_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
31840   #define GRTC_INTEN6_COMPARE15_Msk (0x1UL << GRTC_INTEN6_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
31841   #define GRTC_INTEN6_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
31842   #define GRTC_INTEN6_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
31843   #define GRTC_INTEN6_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
31844   #define GRTC_INTEN6_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
31845 
31846 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
31847   #define GRTC_INTEN6_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
31848   #define GRTC_INTEN6_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN6_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
31849   #define GRTC_INTEN6_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
31850   #define GRTC_INTEN6_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
31851   #define GRTC_INTEN6_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
31852   #define GRTC_INTEN6_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
31853 
31854 
31855 /* GRTC_INTENSET6: Enable interrupt */
31856   #define GRTC_INTENSET6_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET6 register.                                   */
31857 
31858 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
31859   #define GRTC_INTENSET6_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
31860   #define GRTC_INTENSET6_COMPARE0_Msk (0x1UL << GRTC_INTENSET6_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
31861   #define GRTC_INTENSET6_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
31862   #define GRTC_INTENSET6_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
31863   #define GRTC_INTENSET6_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
31864   #define GRTC_INTENSET6_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31865   #define GRTC_INTENSET6_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31866 
31867 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
31868   #define GRTC_INTENSET6_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
31869   #define GRTC_INTENSET6_COMPARE1_Msk (0x1UL << GRTC_INTENSET6_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
31870   #define GRTC_INTENSET6_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
31871   #define GRTC_INTENSET6_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
31872   #define GRTC_INTENSET6_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
31873   #define GRTC_INTENSET6_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31874   #define GRTC_INTENSET6_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31875 
31876 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
31877   #define GRTC_INTENSET6_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
31878   #define GRTC_INTENSET6_COMPARE2_Msk (0x1UL << GRTC_INTENSET6_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
31879   #define GRTC_INTENSET6_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
31880   #define GRTC_INTENSET6_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
31881   #define GRTC_INTENSET6_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
31882   #define GRTC_INTENSET6_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31883   #define GRTC_INTENSET6_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31884 
31885 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
31886   #define GRTC_INTENSET6_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
31887   #define GRTC_INTENSET6_COMPARE3_Msk (0x1UL << GRTC_INTENSET6_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
31888   #define GRTC_INTENSET6_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
31889   #define GRTC_INTENSET6_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
31890   #define GRTC_INTENSET6_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
31891   #define GRTC_INTENSET6_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31892   #define GRTC_INTENSET6_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31893 
31894 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
31895   #define GRTC_INTENSET6_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
31896   #define GRTC_INTENSET6_COMPARE4_Msk (0x1UL << GRTC_INTENSET6_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
31897   #define GRTC_INTENSET6_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
31898   #define GRTC_INTENSET6_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
31899   #define GRTC_INTENSET6_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
31900   #define GRTC_INTENSET6_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31901   #define GRTC_INTENSET6_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31902 
31903 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
31904   #define GRTC_INTENSET6_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
31905   #define GRTC_INTENSET6_COMPARE5_Msk (0x1UL << GRTC_INTENSET6_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
31906   #define GRTC_INTENSET6_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
31907   #define GRTC_INTENSET6_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
31908   #define GRTC_INTENSET6_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
31909   #define GRTC_INTENSET6_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31910   #define GRTC_INTENSET6_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31911 
31912 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
31913   #define GRTC_INTENSET6_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
31914   #define GRTC_INTENSET6_COMPARE6_Msk (0x1UL << GRTC_INTENSET6_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
31915   #define GRTC_INTENSET6_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
31916   #define GRTC_INTENSET6_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
31917   #define GRTC_INTENSET6_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
31918   #define GRTC_INTENSET6_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31919   #define GRTC_INTENSET6_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31920 
31921 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
31922   #define GRTC_INTENSET6_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
31923   #define GRTC_INTENSET6_COMPARE7_Msk (0x1UL << GRTC_INTENSET6_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
31924   #define GRTC_INTENSET6_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
31925   #define GRTC_INTENSET6_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
31926   #define GRTC_INTENSET6_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
31927   #define GRTC_INTENSET6_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31928   #define GRTC_INTENSET6_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31929 
31930 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
31931   #define GRTC_INTENSET6_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
31932   #define GRTC_INTENSET6_COMPARE8_Msk (0x1UL << GRTC_INTENSET6_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
31933   #define GRTC_INTENSET6_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
31934   #define GRTC_INTENSET6_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
31935   #define GRTC_INTENSET6_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
31936   #define GRTC_INTENSET6_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31937   #define GRTC_INTENSET6_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31938 
31939 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
31940   #define GRTC_INTENSET6_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
31941   #define GRTC_INTENSET6_COMPARE9_Msk (0x1UL << GRTC_INTENSET6_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
31942   #define GRTC_INTENSET6_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
31943   #define GRTC_INTENSET6_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
31944   #define GRTC_INTENSET6_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
31945   #define GRTC_INTENSET6_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
31946   #define GRTC_INTENSET6_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
31947 
31948 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
31949   #define GRTC_INTENSET6_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
31950   #define GRTC_INTENSET6_COMPARE10_Msk (0x1UL << GRTC_INTENSET6_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
31951   #define GRTC_INTENSET6_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
31952   #define GRTC_INTENSET6_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
31953   #define GRTC_INTENSET6_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
31954   #define GRTC_INTENSET6_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31955   #define GRTC_INTENSET6_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31956 
31957 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
31958   #define GRTC_INTENSET6_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
31959   #define GRTC_INTENSET6_COMPARE11_Msk (0x1UL << GRTC_INTENSET6_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
31960   #define GRTC_INTENSET6_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
31961   #define GRTC_INTENSET6_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
31962   #define GRTC_INTENSET6_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
31963   #define GRTC_INTENSET6_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31964   #define GRTC_INTENSET6_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31965 
31966 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
31967   #define GRTC_INTENSET6_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
31968   #define GRTC_INTENSET6_COMPARE12_Msk (0x1UL << GRTC_INTENSET6_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
31969   #define GRTC_INTENSET6_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
31970   #define GRTC_INTENSET6_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
31971   #define GRTC_INTENSET6_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
31972   #define GRTC_INTENSET6_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31973   #define GRTC_INTENSET6_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31974 
31975 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
31976   #define GRTC_INTENSET6_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
31977   #define GRTC_INTENSET6_COMPARE13_Msk (0x1UL << GRTC_INTENSET6_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
31978   #define GRTC_INTENSET6_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
31979   #define GRTC_INTENSET6_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
31980   #define GRTC_INTENSET6_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
31981   #define GRTC_INTENSET6_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31982   #define GRTC_INTENSET6_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31983 
31984 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
31985   #define GRTC_INTENSET6_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
31986   #define GRTC_INTENSET6_COMPARE14_Msk (0x1UL << GRTC_INTENSET6_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
31987   #define GRTC_INTENSET6_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
31988   #define GRTC_INTENSET6_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
31989   #define GRTC_INTENSET6_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
31990   #define GRTC_INTENSET6_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
31991   #define GRTC_INTENSET6_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
31992 
31993 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
31994   #define GRTC_INTENSET6_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
31995   #define GRTC_INTENSET6_COMPARE15_Msk (0x1UL << GRTC_INTENSET6_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
31996   #define GRTC_INTENSET6_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
31997   #define GRTC_INTENSET6_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
31998   #define GRTC_INTENSET6_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
31999   #define GRTC_INTENSET6_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32000   #define GRTC_INTENSET6_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32001 
32002 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
32003   #define GRTC_INTENSET6_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
32004   #define GRTC_INTENSET6_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET6_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
32005                                                                             field.*/
32006   #define GRTC_INTENSET6_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
32007   #define GRTC_INTENSET6_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
32008   #define GRTC_INTENSET6_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
32009   #define GRTC_INTENSET6_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
32010   #define GRTC_INTENSET6_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
32011 
32012 
32013 /* GRTC_INTENCLR6: Disable interrupt */
32014   #define GRTC_INTENCLR6_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR6 register.                                   */
32015 
32016 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
32017   #define GRTC_INTENCLR6_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
32018   #define GRTC_INTENCLR6_COMPARE0_Msk (0x1UL << GRTC_INTENCLR6_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
32019   #define GRTC_INTENCLR6_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
32020   #define GRTC_INTENCLR6_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
32021   #define GRTC_INTENCLR6_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
32022   #define GRTC_INTENCLR6_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32023   #define GRTC_INTENCLR6_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32024 
32025 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
32026   #define GRTC_INTENCLR6_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
32027   #define GRTC_INTENCLR6_COMPARE1_Msk (0x1UL << GRTC_INTENCLR6_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
32028   #define GRTC_INTENCLR6_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
32029   #define GRTC_INTENCLR6_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
32030   #define GRTC_INTENCLR6_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
32031   #define GRTC_INTENCLR6_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32032   #define GRTC_INTENCLR6_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32033 
32034 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
32035   #define GRTC_INTENCLR6_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
32036   #define GRTC_INTENCLR6_COMPARE2_Msk (0x1UL << GRTC_INTENCLR6_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
32037   #define GRTC_INTENCLR6_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
32038   #define GRTC_INTENCLR6_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
32039   #define GRTC_INTENCLR6_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
32040   #define GRTC_INTENCLR6_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32041   #define GRTC_INTENCLR6_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32042 
32043 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
32044   #define GRTC_INTENCLR6_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
32045   #define GRTC_INTENCLR6_COMPARE3_Msk (0x1UL << GRTC_INTENCLR6_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
32046   #define GRTC_INTENCLR6_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
32047   #define GRTC_INTENCLR6_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
32048   #define GRTC_INTENCLR6_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
32049   #define GRTC_INTENCLR6_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32050   #define GRTC_INTENCLR6_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32051 
32052 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
32053   #define GRTC_INTENCLR6_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
32054   #define GRTC_INTENCLR6_COMPARE4_Msk (0x1UL << GRTC_INTENCLR6_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
32055   #define GRTC_INTENCLR6_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
32056   #define GRTC_INTENCLR6_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
32057   #define GRTC_INTENCLR6_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
32058   #define GRTC_INTENCLR6_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32059   #define GRTC_INTENCLR6_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32060 
32061 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
32062   #define GRTC_INTENCLR6_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
32063   #define GRTC_INTENCLR6_COMPARE5_Msk (0x1UL << GRTC_INTENCLR6_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
32064   #define GRTC_INTENCLR6_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
32065   #define GRTC_INTENCLR6_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
32066   #define GRTC_INTENCLR6_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
32067   #define GRTC_INTENCLR6_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32068   #define GRTC_INTENCLR6_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32069 
32070 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
32071   #define GRTC_INTENCLR6_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
32072   #define GRTC_INTENCLR6_COMPARE6_Msk (0x1UL << GRTC_INTENCLR6_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
32073   #define GRTC_INTENCLR6_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
32074   #define GRTC_INTENCLR6_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
32075   #define GRTC_INTENCLR6_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
32076   #define GRTC_INTENCLR6_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32077   #define GRTC_INTENCLR6_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32078 
32079 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
32080   #define GRTC_INTENCLR6_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
32081   #define GRTC_INTENCLR6_COMPARE7_Msk (0x1UL << GRTC_INTENCLR6_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
32082   #define GRTC_INTENCLR6_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
32083   #define GRTC_INTENCLR6_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
32084   #define GRTC_INTENCLR6_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
32085   #define GRTC_INTENCLR6_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32086   #define GRTC_INTENCLR6_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32087 
32088 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
32089   #define GRTC_INTENCLR6_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
32090   #define GRTC_INTENCLR6_COMPARE8_Msk (0x1UL << GRTC_INTENCLR6_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
32091   #define GRTC_INTENCLR6_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
32092   #define GRTC_INTENCLR6_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
32093   #define GRTC_INTENCLR6_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
32094   #define GRTC_INTENCLR6_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32095   #define GRTC_INTENCLR6_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32096 
32097 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
32098   #define GRTC_INTENCLR6_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
32099   #define GRTC_INTENCLR6_COMPARE9_Msk (0x1UL << GRTC_INTENCLR6_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
32100   #define GRTC_INTENCLR6_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
32101   #define GRTC_INTENCLR6_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
32102   #define GRTC_INTENCLR6_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
32103   #define GRTC_INTENCLR6_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32104   #define GRTC_INTENCLR6_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32105 
32106 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
32107   #define GRTC_INTENCLR6_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
32108   #define GRTC_INTENCLR6_COMPARE10_Msk (0x1UL << GRTC_INTENCLR6_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
32109   #define GRTC_INTENCLR6_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
32110   #define GRTC_INTENCLR6_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
32111   #define GRTC_INTENCLR6_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
32112   #define GRTC_INTENCLR6_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32113   #define GRTC_INTENCLR6_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32114 
32115 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
32116   #define GRTC_INTENCLR6_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
32117   #define GRTC_INTENCLR6_COMPARE11_Msk (0x1UL << GRTC_INTENCLR6_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
32118   #define GRTC_INTENCLR6_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
32119   #define GRTC_INTENCLR6_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
32120   #define GRTC_INTENCLR6_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
32121   #define GRTC_INTENCLR6_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32122   #define GRTC_INTENCLR6_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32123 
32124 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
32125   #define GRTC_INTENCLR6_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
32126   #define GRTC_INTENCLR6_COMPARE12_Msk (0x1UL << GRTC_INTENCLR6_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
32127   #define GRTC_INTENCLR6_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
32128   #define GRTC_INTENCLR6_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
32129   #define GRTC_INTENCLR6_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
32130   #define GRTC_INTENCLR6_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32131   #define GRTC_INTENCLR6_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32132 
32133 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
32134   #define GRTC_INTENCLR6_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
32135   #define GRTC_INTENCLR6_COMPARE13_Msk (0x1UL << GRTC_INTENCLR6_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
32136   #define GRTC_INTENCLR6_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
32137   #define GRTC_INTENCLR6_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
32138   #define GRTC_INTENCLR6_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
32139   #define GRTC_INTENCLR6_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32140   #define GRTC_INTENCLR6_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32141 
32142 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
32143   #define GRTC_INTENCLR6_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
32144   #define GRTC_INTENCLR6_COMPARE14_Msk (0x1UL << GRTC_INTENCLR6_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
32145   #define GRTC_INTENCLR6_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
32146   #define GRTC_INTENCLR6_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
32147   #define GRTC_INTENCLR6_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
32148   #define GRTC_INTENCLR6_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32149   #define GRTC_INTENCLR6_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32150 
32151 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
32152   #define GRTC_INTENCLR6_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
32153   #define GRTC_INTENCLR6_COMPARE15_Msk (0x1UL << GRTC_INTENCLR6_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
32154   #define GRTC_INTENCLR6_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
32155   #define GRTC_INTENCLR6_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
32156   #define GRTC_INTENCLR6_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
32157   #define GRTC_INTENCLR6_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32158   #define GRTC_INTENCLR6_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32159 
32160 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
32161   #define GRTC_INTENCLR6_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
32162   #define GRTC_INTENCLR6_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR6_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
32163                                                                             field.*/
32164   #define GRTC_INTENCLR6_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
32165   #define GRTC_INTENCLR6_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
32166   #define GRTC_INTENCLR6_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
32167   #define GRTC_INTENCLR6_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
32168   #define GRTC_INTENCLR6_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
32169 
32170 
32171 /* GRTC_INTPEND6: Pending interrupts */
32172   #define GRTC_INTPEND6_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND6 register.                                    */
32173 
32174 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
32175   #define GRTC_INTPEND6_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
32176   #define GRTC_INTPEND6_COMPARE0_Msk (0x1UL << GRTC_INTPEND6_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
32177   #define GRTC_INTPEND6_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
32178   #define GRTC_INTPEND6_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
32179   #define GRTC_INTPEND6_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32180   #define GRTC_INTPEND6_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
32181 
32182 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
32183   #define GRTC_INTPEND6_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
32184   #define GRTC_INTPEND6_COMPARE1_Msk (0x1UL << GRTC_INTPEND6_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
32185   #define GRTC_INTPEND6_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
32186   #define GRTC_INTPEND6_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
32187   #define GRTC_INTPEND6_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32188   #define GRTC_INTPEND6_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
32189 
32190 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
32191   #define GRTC_INTPEND6_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
32192   #define GRTC_INTPEND6_COMPARE2_Msk (0x1UL << GRTC_INTPEND6_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
32193   #define GRTC_INTPEND6_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
32194   #define GRTC_INTPEND6_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
32195   #define GRTC_INTPEND6_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32196   #define GRTC_INTPEND6_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
32197 
32198 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
32199   #define GRTC_INTPEND6_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
32200   #define GRTC_INTPEND6_COMPARE3_Msk (0x1UL << GRTC_INTPEND6_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
32201   #define GRTC_INTPEND6_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
32202   #define GRTC_INTPEND6_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
32203   #define GRTC_INTPEND6_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32204   #define GRTC_INTPEND6_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
32205 
32206 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
32207   #define GRTC_INTPEND6_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
32208   #define GRTC_INTPEND6_COMPARE4_Msk (0x1UL << GRTC_INTPEND6_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
32209   #define GRTC_INTPEND6_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
32210   #define GRTC_INTPEND6_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
32211   #define GRTC_INTPEND6_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32212   #define GRTC_INTPEND6_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
32213 
32214 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
32215   #define GRTC_INTPEND6_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
32216   #define GRTC_INTPEND6_COMPARE5_Msk (0x1UL << GRTC_INTPEND6_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
32217   #define GRTC_INTPEND6_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
32218   #define GRTC_INTPEND6_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
32219   #define GRTC_INTPEND6_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32220   #define GRTC_INTPEND6_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
32221 
32222 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
32223   #define GRTC_INTPEND6_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
32224   #define GRTC_INTPEND6_COMPARE6_Msk (0x1UL << GRTC_INTPEND6_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
32225   #define GRTC_INTPEND6_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
32226   #define GRTC_INTPEND6_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
32227   #define GRTC_INTPEND6_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32228   #define GRTC_INTPEND6_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
32229 
32230 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
32231   #define GRTC_INTPEND6_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
32232   #define GRTC_INTPEND6_COMPARE7_Msk (0x1UL << GRTC_INTPEND6_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
32233   #define GRTC_INTPEND6_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
32234   #define GRTC_INTPEND6_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
32235   #define GRTC_INTPEND6_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32236   #define GRTC_INTPEND6_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
32237 
32238 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
32239   #define GRTC_INTPEND6_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
32240   #define GRTC_INTPEND6_COMPARE8_Msk (0x1UL << GRTC_INTPEND6_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
32241   #define GRTC_INTPEND6_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
32242   #define GRTC_INTPEND6_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
32243   #define GRTC_INTPEND6_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32244   #define GRTC_INTPEND6_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
32245 
32246 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
32247   #define GRTC_INTPEND6_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
32248   #define GRTC_INTPEND6_COMPARE9_Msk (0x1UL << GRTC_INTPEND6_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
32249   #define GRTC_INTPEND6_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
32250   #define GRTC_INTPEND6_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
32251   #define GRTC_INTPEND6_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32252   #define GRTC_INTPEND6_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
32253 
32254 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
32255   #define GRTC_INTPEND6_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
32256   #define GRTC_INTPEND6_COMPARE10_Msk (0x1UL << GRTC_INTPEND6_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
32257   #define GRTC_INTPEND6_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
32258   #define GRTC_INTPEND6_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
32259   #define GRTC_INTPEND6_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32260   #define GRTC_INTPEND6_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
32261 
32262 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
32263   #define GRTC_INTPEND6_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
32264   #define GRTC_INTPEND6_COMPARE11_Msk (0x1UL << GRTC_INTPEND6_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
32265   #define GRTC_INTPEND6_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
32266   #define GRTC_INTPEND6_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
32267   #define GRTC_INTPEND6_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32268   #define GRTC_INTPEND6_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
32269 
32270 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
32271   #define GRTC_INTPEND6_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
32272   #define GRTC_INTPEND6_COMPARE12_Msk (0x1UL << GRTC_INTPEND6_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
32273   #define GRTC_INTPEND6_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
32274   #define GRTC_INTPEND6_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
32275   #define GRTC_INTPEND6_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32276   #define GRTC_INTPEND6_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
32277 
32278 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
32279   #define GRTC_INTPEND6_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
32280   #define GRTC_INTPEND6_COMPARE13_Msk (0x1UL << GRTC_INTPEND6_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
32281   #define GRTC_INTPEND6_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
32282   #define GRTC_INTPEND6_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
32283   #define GRTC_INTPEND6_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32284   #define GRTC_INTPEND6_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
32285 
32286 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
32287   #define GRTC_INTPEND6_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
32288   #define GRTC_INTPEND6_COMPARE14_Msk (0x1UL << GRTC_INTPEND6_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
32289   #define GRTC_INTPEND6_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
32290   #define GRTC_INTPEND6_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
32291   #define GRTC_INTPEND6_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32292   #define GRTC_INTPEND6_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
32293 
32294 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
32295   #define GRTC_INTPEND6_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
32296   #define GRTC_INTPEND6_COMPARE15_Msk (0x1UL << GRTC_INTPEND6_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
32297   #define GRTC_INTPEND6_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
32298   #define GRTC_INTPEND6_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
32299   #define GRTC_INTPEND6_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32300   #define GRTC_INTPEND6_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
32301 
32302 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
32303   #define GRTC_INTPEND6_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
32304   #define GRTC_INTPEND6_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND6_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
32305                                                                             field.*/
32306   #define GRTC_INTPEND6_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
32307   #define GRTC_INTPEND6_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
32308   #define GRTC_INTPEND6_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
32309   #define GRTC_INTPEND6_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
32310 
32311 
32312 /* GRTC_INTEN7: Enable or disable interrupt */
32313   #define GRTC_INTEN7_ResetValue (0x00000000UL)      /*!< Reset value of INTEN7 register.                                      */
32314 
32315 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
32316   #define GRTC_INTEN7_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
32317   #define GRTC_INTEN7_COMPARE0_Msk (0x1UL << GRTC_INTEN7_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
32318   #define GRTC_INTEN7_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
32319   #define GRTC_INTEN7_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
32320   #define GRTC_INTEN7_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
32321   #define GRTC_INTEN7_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
32322 
32323 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
32324   #define GRTC_INTEN7_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
32325   #define GRTC_INTEN7_COMPARE1_Msk (0x1UL << GRTC_INTEN7_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
32326   #define GRTC_INTEN7_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
32327   #define GRTC_INTEN7_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
32328   #define GRTC_INTEN7_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
32329   #define GRTC_INTEN7_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
32330 
32331 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
32332   #define GRTC_INTEN7_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
32333   #define GRTC_INTEN7_COMPARE2_Msk (0x1UL << GRTC_INTEN7_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
32334   #define GRTC_INTEN7_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
32335   #define GRTC_INTEN7_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
32336   #define GRTC_INTEN7_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
32337   #define GRTC_INTEN7_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
32338 
32339 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
32340   #define GRTC_INTEN7_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
32341   #define GRTC_INTEN7_COMPARE3_Msk (0x1UL << GRTC_INTEN7_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
32342   #define GRTC_INTEN7_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
32343   #define GRTC_INTEN7_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
32344   #define GRTC_INTEN7_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
32345   #define GRTC_INTEN7_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
32346 
32347 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
32348   #define GRTC_INTEN7_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
32349   #define GRTC_INTEN7_COMPARE4_Msk (0x1UL << GRTC_INTEN7_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
32350   #define GRTC_INTEN7_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
32351   #define GRTC_INTEN7_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
32352   #define GRTC_INTEN7_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
32353   #define GRTC_INTEN7_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
32354 
32355 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
32356   #define GRTC_INTEN7_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
32357   #define GRTC_INTEN7_COMPARE5_Msk (0x1UL << GRTC_INTEN7_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
32358   #define GRTC_INTEN7_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
32359   #define GRTC_INTEN7_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
32360   #define GRTC_INTEN7_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
32361   #define GRTC_INTEN7_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
32362 
32363 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
32364   #define GRTC_INTEN7_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
32365   #define GRTC_INTEN7_COMPARE6_Msk (0x1UL << GRTC_INTEN7_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
32366   #define GRTC_INTEN7_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
32367   #define GRTC_INTEN7_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
32368   #define GRTC_INTEN7_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
32369   #define GRTC_INTEN7_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
32370 
32371 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
32372   #define GRTC_INTEN7_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
32373   #define GRTC_INTEN7_COMPARE7_Msk (0x1UL << GRTC_INTEN7_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
32374   #define GRTC_INTEN7_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
32375   #define GRTC_INTEN7_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
32376   #define GRTC_INTEN7_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
32377   #define GRTC_INTEN7_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
32378 
32379 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
32380   #define GRTC_INTEN7_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
32381   #define GRTC_INTEN7_COMPARE8_Msk (0x1UL << GRTC_INTEN7_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
32382   #define GRTC_INTEN7_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
32383   #define GRTC_INTEN7_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
32384   #define GRTC_INTEN7_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
32385   #define GRTC_INTEN7_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
32386 
32387 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
32388   #define GRTC_INTEN7_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
32389   #define GRTC_INTEN7_COMPARE9_Msk (0x1UL << GRTC_INTEN7_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
32390   #define GRTC_INTEN7_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
32391   #define GRTC_INTEN7_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
32392   #define GRTC_INTEN7_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
32393   #define GRTC_INTEN7_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
32394 
32395 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
32396   #define GRTC_INTEN7_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
32397   #define GRTC_INTEN7_COMPARE10_Msk (0x1UL << GRTC_INTEN7_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
32398   #define GRTC_INTEN7_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
32399   #define GRTC_INTEN7_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
32400   #define GRTC_INTEN7_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
32401   #define GRTC_INTEN7_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
32402 
32403 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
32404   #define GRTC_INTEN7_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
32405   #define GRTC_INTEN7_COMPARE11_Msk (0x1UL << GRTC_INTEN7_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
32406   #define GRTC_INTEN7_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
32407   #define GRTC_INTEN7_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
32408   #define GRTC_INTEN7_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
32409   #define GRTC_INTEN7_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
32410 
32411 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
32412   #define GRTC_INTEN7_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
32413   #define GRTC_INTEN7_COMPARE12_Msk (0x1UL << GRTC_INTEN7_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
32414   #define GRTC_INTEN7_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
32415   #define GRTC_INTEN7_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
32416   #define GRTC_INTEN7_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
32417   #define GRTC_INTEN7_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
32418 
32419 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
32420   #define GRTC_INTEN7_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
32421   #define GRTC_INTEN7_COMPARE13_Msk (0x1UL << GRTC_INTEN7_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
32422   #define GRTC_INTEN7_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
32423   #define GRTC_INTEN7_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
32424   #define GRTC_INTEN7_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
32425   #define GRTC_INTEN7_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
32426 
32427 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
32428   #define GRTC_INTEN7_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
32429   #define GRTC_INTEN7_COMPARE14_Msk (0x1UL << GRTC_INTEN7_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
32430   #define GRTC_INTEN7_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
32431   #define GRTC_INTEN7_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
32432   #define GRTC_INTEN7_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
32433   #define GRTC_INTEN7_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
32434 
32435 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
32436   #define GRTC_INTEN7_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
32437   #define GRTC_INTEN7_COMPARE15_Msk (0x1UL << GRTC_INTEN7_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
32438   #define GRTC_INTEN7_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
32439   #define GRTC_INTEN7_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
32440   #define GRTC_INTEN7_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
32441   #define GRTC_INTEN7_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
32442 
32443 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
32444   #define GRTC_INTEN7_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
32445   #define GRTC_INTEN7_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN7_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
32446   #define GRTC_INTEN7_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
32447   #define GRTC_INTEN7_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
32448   #define GRTC_INTEN7_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
32449   #define GRTC_INTEN7_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
32450 
32451 
32452 /* GRTC_INTENSET7: Enable interrupt */
32453   #define GRTC_INTENSET7_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET7 register.                                   */
32454 
32455 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
32456   #define GRTC_INTENSET7_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
32457   #define GRTC_INTENSET7_COMPARE0_Msk (0x1UL << GRTC_INTENSET7_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
32458   #define GRTC_INTENSET7_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
32459   #define GRTC_INTENSET7_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
32460   #define GRTC_INTENSET7_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
32461   #define GRTC_INTENSET7_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32462   #define GRTC_INTENSET7_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32463 
32464 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
32465   #define GRTC_INTENSET7_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
32466   #define GRTC_INTENSET7_COMPARE1_Msk (0x1UL << GRTC_INTENSET7_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
32467   #define GRTC_INTENSET7_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
32468   #define GRTC_INTENSET7_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
32469   #define GRTC_INTENSET7_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
32470   #define GRTC_INTENSET7_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32471   #define GRTC_INTENSET7_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32472 
32473 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
32474   #define GRTC_INTENSET7_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
32475   #define GRTC_INTENSET7_COMPARE2_Msk (0x1UL << GRTC_INTENSET7_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
32476   #define GRTC_INTENSET7_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
32477   #define GRTC_INTENSET7_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
32478   #define GRTC_INTENSET7_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
32479   #define GRTC_INTENSET7_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32480   #define GRTC_INTENSET7_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32481 
32482 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
32483   #define GRTC_INTENSET7_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
32484   #define GRTC_INTENSET7_COMPARE3_Msk (0x1UL << GRTC_INTENSET7_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
32485   #define GRTC_INTENSET7_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
32486   #define GRTC_INTENSET7_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
32487   #define GRTC_INTENSET7_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
32488   #define GRTC_INTENSET7_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32489   #define GRTC_INTENSET7_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32490 
32491 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
32492   #define GRTC_INTENSET7_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
32493   #define GRTC_INTENSET7_COMPARE4_Msk (0x1UL << GRTC_INTENSET7_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
32494   #define GRTC_INTENSET7_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
32495   #define GRTC_INTENSET7_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
32496   #define GRTC_INTENSET7_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
32497   #define GRTC_INTENSET7_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32498   #define GRTC_INTENSET7_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32499 
32500 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
32501   #define GRTC_INTENSET7_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
32502   #define GRTC_INTENSET7_COMPARE5_Msk (0x1UL << GRTC_INTENSET7_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
32503   #define GRTC_INTENSET7_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
32504   #define GRTC_INTENSET7_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
32505   #define GRTC_INTENSET7_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
32506   #define GRTC_INTENSET7_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32507   #define GRTC_INTENSET7_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32508 
32509 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
32510   #define GRTC_INTENSET7_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
32511   #define GRTC_INTENSET7_COMPARE6_Msk (0x1UL << GRTC_INTENSET7_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
32512   #define GRTC_INTENSET7_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
32513   #define GRTC_INTENSET7_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
32514   #define GRTC_INTENSET7_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
32515   #define GRTC_INTENSET7_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32516   #define GRTC_INTENSET7_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32517 
32518 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
32519   #define GRTC_INTENSET7_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
32520   #define GRTC_INTENSET7_COMPARE7_Msk (0x1UL << GRTC_INTENSET7_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
32521   #define GRTC_INTENSET7_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
32522   #define GRTC_INTENSET7_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
32523   #define GRTC_INTENSET7_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
32524   #define GRTC_INTENSET7_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32525   #define GRTC_INTENSET7_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32526 
32527 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
32528   #define GRTC_INTENSET7_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
32529   #define GRTC_INTENSET7_COMPARE8_Msk (0x1UL << GRTC_INTENSET7_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
32530   #define GRTC_INTENSET7_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
32531   #define GRTC_INTENSET7_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
32532   #define GRTC_INTENSET7_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
32533   #define GRTC_INTENSET7_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32534   #define GRTC_INTENSET7_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32535 
32536 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
32537   #define GRTC_INTENSET7_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
32538   #define GRTC_INTENSET7_COMPARE9_Msk (0x1UL << GRTC_INTENSET7_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
32539   #define GRTC_INTENSET7_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
32540   #define GRTC_INTENSET7_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
32541   #define GRTC_INTENSET7_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
32542   #define GRTC_INTENSET7_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32543   #define GRTC_INTENSET7_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32544 
32545 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
32546   #define GRTC_INTENSET7_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
32547   #define GRTC_INTENSET7_COMPARE10_Msk (0x1UL << GRTC_INTENSET7_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
32548   #define GRTC_INTENSET7_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
32549   #define GRTC_INTENSET7_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
32550   #define GRTC_INTENSET7_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
32551   #define GRTC_INTENSET7_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32552   #define GRTC_INTENSET7_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32553 
32554 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
32555   #define GRTC_INTENSET7_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
32556   #define GRTC_INTENSET7_COMPARE11_Msk (0x1UL << GRTC_INTENSET7_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
32557   #define GRTC_INTENSET7_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
32558   #define GRTC_INTENSET7_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
32559   #define GRTC_INTENSET7_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
32560   #define GRTC_INTENSET7_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32561   #define GRTC_INTENSET7_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32562 
32563 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
32564   #define GRTC_INTENSET7_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
32565   #define GRTC_INTENSET7_COMPARE12_Msk (0x1UL << GRTC_INTENSET7_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
32566   #define GRTC_INTENSET7_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
32567   #define GRTC_INTENSET7_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
32568   #define GRTC_INTENSET7_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
32569   #define GRTC_INTENSET7_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32570   #define GRTC_INTENSET7_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32571 
32572 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
32573   #define GRTC_INTENSET7_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
32574   #define GRTC_INTENSET7_COMPARE13_Msk (0x1UL << GRTC_INTENSET7_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
32575   #define GRTC_INTENSET7_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
32576   #define GRTC_INTENSET7_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
32577   #define GRTC_INTENSET7_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
32578   #define GRTC_INTENSET7_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32579   #define GRTC_INTENSET7_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32580 
32581 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
32582   #define GRTC_INTENSET7_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
32583   #define GRTC_INTENSET7_COMPARE14_Msk (0x1UL << GRTC_INTENSET7_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
32584   #define GRTC_INTENSET7_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
32585   #define GRTC_INTENSET7_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
32586   #define GRTC_INTENSET7_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
32587   #define GRTC_INTENSET7_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32588   #define GRTC_INTENSET7_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32589 
32590 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
32591   #define GRTC_INTENSET7_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
32592   #define GRTC_INTENSET7_COMPARE15_Msk (0x1UL << GRTC_INTENSET7_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
32593   #define GRTC_INTENSET7_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
32594   #define GRTC_INTENSET7_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
32595   #define GRTC_INTENSET7_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
32596   #define GRTC_INTENSET7_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32597   #define GRTC_INTENSET7_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32598 
32599 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
32600   #define GRTC_INTENSET7_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
32601   #define GRTC_INTENSET7_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET7_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
32602                                                                             field.*/
32603   #define GRTC_INTENSET7_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
32604   #define GRTC_INTENSET7_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
32605   #define GRTC_INTENSET7_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
32606   #define GRTC_INTENSET7_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
32607   #define GRTC_INTENSET7_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
32608 
32609 
32610 /* GRTC_INTENCLR7: Disable interrupt */
32611   #define GRTC_INTENCLR7_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR7 register.                                   */
32612 
32613 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
32614   #define GRTC_INTENCLR7_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
32615   #define GRTC_INTENCLR7_COMPARE0_Msk (0x1UL << GRTC_INTENCLR7_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
32616   #define GRTC_INTENCLR7_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
32617   #define GRTC_INTENCLR7_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
32618   #define GRTC_INTENCLR7_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
32619   #define GRTC_INTENCLR7_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32620   #define GRTC_INTENCLR7_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32621 
32622 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
32623   #define GRTC_INTENCLR7_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
32624   #define GRTC_INTENCLR7_COMPARE1_Msk (0x1UL << GRTC_INTENCLR7_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
32625   #define GRTC_INTENCLR7_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
32626   #define GRTC_INTENCLR7_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
32627   #define GRTC_INTENCLR7_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
32628   #define GRTC_INTENCLR7_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32629   #define GRTC_INTENCLR7_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32630 
32631 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
32632   #define GRTC_INTENCLR7_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
32633   #define GRTC_INTENCLR7_COMPARE2_Msk (0x1UL << GRTC_INTENCLR7_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
32634   #define GRTC_INTENCLR7_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
32635   #define GRTC_INTENCLR7_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
32636   #define GRTC_INTENCLR7_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
32637   #define GRTC_INTENCLR7_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32638   #define GRTC_INTENCLR7_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32639 
32640 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
32641   #define GRTC_INTENCLR7_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
32642   #define GRTC_INTENCLR7_COMPARE3_Msk (0x1UL << GRTC_INTENCLR7_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
32643   #define GRTC_INTENCLR7_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
32644   #define GRTC_INTENCLR7_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
32645   #define GRTC_INTENCLR7_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
32646   #define GRTC_INTENCLR7_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32647   #define GRTC_INTENCLR7_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32648 
32649 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
32650   #define GRTC_INTENCLR7_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
32651   #define GRTC_INTENCLR7_COMPARE4_Msk (0x1UL << GRTC_INTENCLR7_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
32652   #define GRTC_INTENCLR7_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
32653   #define GRTC_INTENCLR7_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
32654   #define GRTC_INTENCLR7_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
32655   #define GRTC_INTENCLR7_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32656   #define GRTC_INTENCLR7_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32657 
32658 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
32659   #define GRTC_INTENCLR7_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
32660   #define GRTC_INTENCLR7_COMPARE5_Msk (0x1UL << GRTC_INTENCLR7_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
32661   #define GRTC_INTENCLR7_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
32662   #define GRTC_INTENCLR7_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
32663   #define GRTC_INTENCLR7_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
32664   #define GRTC_INTENCLR7_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32665   #define GRTC_INTENCLR7_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32666 
32667 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
32668   #define GRTC_INTENCLR7_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
32669   #define GRTC_INTENCLR7_COMPARE6_Msk (0x1UL << GRTC_INTENCLR7_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
32670   #define GRTC_INTENCLR7_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
32671   #define GRTC_INTENCLR7_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
32672   #define GRTC_INTENCLR7_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
32673   #define GRTC_INTENCLR7_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32674   #define GRTC_INTENCLR7_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32675 
32676 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
32677   #define GRTC_INTENCLR7_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
32678   #define GRTC_INTENCLR7_COMPARE7_Msk (0x1UL << GRTC_INTENCLR7_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
32679   #define GRTC_INTENCLR7_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
32680   #define GRTC_INTENCLR7_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
32681   #define GRTC_INTENCLR7_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
32682   #define GRTC_INTENCLR7_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32683   #define GRTC_INTENCLR7_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32684 
32685 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
32686   #define GRTC_INTENCLR7_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
32687   #define GRTC_INTENCLR7_COMPARE8_Msk (0x1UL << GRTC_INTENCLR7_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
32688   #define GRTC_INTENCLR7_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
32689   #define GRTC_INTENCLR7_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
32690   #define GRTC_INTENCLR7_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
32691   #define GRTC_INTENCLR7_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32692   #define GRTC_INTENCLR7_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32693 
32694 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
32695   #define GRTC_INTENCLR7_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
32696   #define GRTC_INTENCLR7_COMPARE9_Msk (0x1UL << GRTC_INTENCLR7_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
32697   #define GRTC_INTENCLR7_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
32698   #define GRTC_INTENCLR7_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
32699   #define GRTC_INTENCLR7_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
32700   #define GRTC_INTENCLR7_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
32701   #define GRTC_INTENCLR7_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
32702 
32703 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
32704   #define GRTC_INTENCLR7_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
32705   #define GRTC_INTENCLR7_COMPARE10_Msk (0x1UL << GRTC_INTENCLR7_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
32706   #define GRTC_INTENCLR7_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
32707   #define GRTC_INTENCLR7_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
32708   #define GRTC_INTENCLR7_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
32709   #define GRTC_INTENCLR7_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32710   #define GRTC_INTENCLR7_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32711 
32712 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
32713   #define GRTC_INTENCLR7_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
32714   #define GRTC_INTENCLR7_COMPARE11_Msk (0x1UL << GRTC_INTENCLR7_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
32715   #define GRTC_INTENCLR7_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
32716   #define GRTC_INTENCLR7_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
32717   #define GRTC_INTENCLR7_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
32718   #define GRTC_INTENCLR7_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32719   #define GRTC_INTENCLR7_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32720 
32721 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
32722   #define GRTC_INTENCLR7_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
32723   #define GRTC_INTENCLR7_COMPARE12_Msk (0x1UL << GRTC_INTENCLR7_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
32724   #define GRTC_INTENCLR7_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
32725   #define GRTC_INTENCLR7_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
32726   #define GRTC_INTENCLR7_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
32727   #define GRTC_INTENCLR7_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32728   #define GRTC_INTENCLR7_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32729 
32730 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
32731   #define GRTC_INTENCLR7_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
32732   #define GRTC_INTENCLR7_COMPARE13_Msk (0x1UL << GRTC_INTENCLR7_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
32733   #define GRTC_INTENCLR7_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
32734   #define GRTC_INTENCLR7_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
32735   #define GRTC_INTENCLR7_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
32736   #define GRTC_INTENCLR7_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32737   #define GRTC_INTENCLR7_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32738 
32739 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
32740   #define GRTC_INTENCLR7_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
32741   #define GRTC_INTENCLR7_COMPARE14_Msk (0x1UL << GRTC_INTENCLR7_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
32742   #define GRTC_INTENCLR7_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
32743   #define GRTC_INTENCLR7_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
32744   #define GRTC_INTENCLR7_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
32745   #define GRTC_INTENCLR7_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32746   #define GRTC_INTENCLR7_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32747 
32748 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
32749   #define GRTC_INTENCLR7_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
32750   #define GRTC_INTENCLR7_COMPARE15_Msk (0x1UL << GRTC_INTENCLR7_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
32751   #define GRTC_INTENCLR7_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
32752   #define GRTC_INTENCLR7_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
32753   #define GRTC_INTENCLR7_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
32754   #define GRTC_INTENCLR7_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
32755   #define GRTC_INTENCLR7_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
32756 
32757 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
32758   #define GRTC_INTENCLR7_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
32759   #define GRTC_INTENCLR7_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR7_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
32760                                                                             field.*/
32761   #define GRTC_INTENCLR7_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
32762   #define GRTC_INTENCLR7_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
32763   #define GRTC_INTENCLR7_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
32764   #define GRTC_INTENCLR7_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
32765   #define GRTC_INTENCLR7_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
32766 
32767 
32768 /* GRTC_INTPEND7: Pending interrupts */
32769   #define GRTC_INTPEND7_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND7 register.                                    */
32770 
32771 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
32772   #define GRTC_INTPEND7_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
32773   #define GRTC_INTPEND7_COMPARE0_Msk (0x1UL << GRTC_INTPEND7_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
32774   #define GRTC_INTPEND7_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
32775   #define GRTC_INTPEND7_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
32776   #define GRTC_INTPEND7_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32777   #define GRTC_INTPEND7_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
32778 
32779 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
32780   #define GRTC_INTPEND7_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
32781   #define GRTC_INTPEND7_COMPARE1_Msk (0x1UL << GRTC_INTPEND7_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
32782   #define GRTC_INTPEND7_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
32783   #define GRTC_INTPEND7_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
32784   #define GRTC_INTPEND7_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32785   #define GRTC_INTPEND7_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
32786 
32787 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
32788   #define GRTC_INTPEND7_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
32789   #define GRTC_INTPEND7_COMPARE2_Msk (0x1UL << GRTC_INTPEND7_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
32790   #define GRTC_INTPEND7_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
32791   #define GRTC_INTPEND7_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
32792   #define GRTC_INTPEND7_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32793   #define GRTC_INTPEND7_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
32794 
32795 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
32796   #define GRTC_INTPEND7_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
32797   #define GRTC_INTPEND7_COMPARE3_Msk (0x1UL << GRTC_INTPEND7_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
32798   #define GRTC_INTPEND7_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
32799   #define GRTC_INTPEND7_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
32800   #define GRTC_INTPEND7_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32801   #define GRTC_INTPEND7_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
32802 
32803 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
32804   #define GRTC_INTPEND7_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
32805   #define GRTC_INTPEND7_COMPARE4_Msk (0x1UL << GRTC_INTPEND7_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
32806   #define GRTC_INTPEND7_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
32807   #define GRTC_INTPEND7_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
32808   #define GRTC_INTPEND7_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32809   #define GRTC_INTPEND7_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
32810 
32811 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
32812   #define GRTC_INTPEND7_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
32813   #define GRTC_INTPEND7_COMPARE5_Msk (0x1UL << GRTC_INTPEND7_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
32814   #define GRTC_INTPEND7_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
32815   #define GRTC_INTPEND7_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
32816   #define GRTC_INTPEND7_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32817   #define GRTC_INTPEND7_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
32818 
32819 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
32820   #define GRTC_INTPEND7_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
32821   #define GRTC_INTPEND7_COMPARE6_Msk (0x1UL << GRTC_INTPEND7_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
32822   #define GRTC_INTPEND7_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
32823   #define GRTC_INTPEND7_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
32824   #define GRTC_INTPEND7_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32825   #define GRTC_INTPEND7_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
32826 
32827 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
32828   #define GRTC_INTPEND7_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
32829   #define GRTC_INTPEND7_COMPARE7_Msk (0x1UL << GRTC_INTPEND7_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
32830   #define GRTC_INTPEND7_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
32831   #define GRTC_INTPEND7_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
32832   #define GRTC_INTPEND7_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32833   #define GRTC_INTPEND7_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
32834 
32835 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
32836   #define GRTC_INTPEND7_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
32837   #define GRTC_INTPEND7_COMPARE8_Msk (0x1UL << GRTC_INTPEND7_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
32838   #define GRTC_INTPEND7_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
32839   #define GRTC_INTPEND7_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
32840   #define GRTC_INTPEND7_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32841   #define GRTC_INTPEND7_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
32842 
32843 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
32844   #define GRTC_INTPEND7_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
32845   #define GRTC_INTPEND7_COMPARE9_Msk (0x1UL << GRTC_INTPEND7_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
32846   #define GRTC_INTPEND7_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
32847   #define GRTC_INTPEND7_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
32848   #define GRTC_INTPEND7_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
32849   #define GRTC_INTPEND7_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
32850 
32851 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
32852   #define GRTC_INTPEND7_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
32853   #define GRTC_INTPEND7_COMPARE10_Msk (0x1UL << GRTC_INTPEND7_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
32854   #define GRTC_INTPEND7_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
32855   #define GRTC_INTPEND7_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
32856   #define GRTC_INTPEND7_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32857   #define GRTC_INTPEND7_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
32858 
32859 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
32860   #define GRTC_INTPEND7_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
32861   #define GRTC_INTPEND7_COMPARE11_Msk (0x1UL << GRTC_INTPEND7_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
32862   #define GRTC_INTPEND7_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
32863   #define GRTC_INTPEND7_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
32864   #define GRTC_INTPEND7_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32865   #define GRTC_INTPEND7_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
32866 
32867 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
32868   #define GRTC_INTPEND7_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
32869   #define GRTC_INTPEND7_COMPARE12_Msk (0x1UL << GRTC_INTPEND7_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
32870   #define GRTC_INTPEND7_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
32871   #define GRTC_INTPEND7_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
32872   #define GRTC_INTPEND7_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32873   #define GRTC_INTPEND7_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
32874 
32875 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
32876   #define GRTC_INTPEND7_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
32877   #define GRTC_INTPEND7_COMPARE13_Msk (0x1UL << GRTC_INTPEND7_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
32878   #define GRTC_INTPEND7_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
32879   #define GRTC_INTPEND7_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
32880   #define GRTC_INTPEND7_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32881   #define GRTC_INTPEND7_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
32882 
32883 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
32884   #define GRTC_INTPEND7_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
32885   #define GRTC_INTPEND7_COMPARE14_Msk (0x1UL << GRTC_INTPEND7_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
32886   #define GRTC_INTPEND7_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
32887   #define GRTC_INTPEND7_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
32888   #define GRTC_INTPEND7_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32889   #define GRTC_INTPEND7_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
32890 
32891 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
32892   #define GRTC_INTPEND7_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
32893   #define GRTC_INTPEND7_COMPARE15_Msk (0x1UL << GRTC_INTPEND7_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
32894   #define GRTC_INTPEND7_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
32895   #define GRTC_INTPEND7_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
32896   #define GRTC_INTPEND7_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
32897   #define GRTC_INTPEND7_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
32898 
32899 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
32900   #define GRTC_INTPEND7_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
32901   #define GRTC_INTPEND7_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND7_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
32902                                                                             field.*/
32903   #define GRTC_INTPEND7_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
32904   #define GRTC_INTPEND7_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
32905   #define GRTC_INTPEND7_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
32906   #define GRTC_INTPEND7_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
32907 
32908 
32909 /* GRTC_INTEN8: Enable or disable interrupt */
32910   #define GRTC_INTEN8_ResetValue (0x00000000UL)      /*!< Reset value of INTEN8 register.                                      */
32911 
32912 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
32913   #define GRTC_INTEN8_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
32914   #define GRTC_INTEN8_COMPARE0_Msk (0x1UL << GRTC_INTEN8_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
32915   #define GRTC_INTEN8_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
32916   #define GRTC_INTEN8_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
32917   #define GRTC_INTEN8_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
32918   #define GRTC_INTEN8_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
32919 
32920 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
32921   #define GRTC_INTEN8_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
32922   #define GRTC_INTEN8_COMPARE1_Msk (0x1UL << GRTC_INTEN8_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
32923   #define GRTC_INTEN8_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
32924   #define GRTC_INTEN8_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
32925   #define GRTC_INTEN8_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
32926   #define GRTC_INTEN8_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
32927 
32928 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
32929   #define GRTC_INTEN8_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
32930   #define GRTC_INTEN8_COMPARE2_Msk (0x1UL << GRTC_INTEN8_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
32931   #define GRTC_INTEN8_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
32932   #define GRTC_INTEN8_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
32933   #define GRTC_INTEN8_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
32934   #define GRTC_INTEN8_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
32935 
32936 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
32937   #define GRTC_INTEN8_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
32938   #define GRTC_INTEN8_COMPARE3_Msk (0x1UL << GRTC_INTEN8_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
32939   #define GRTC_INTEN8_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
32940   #define GRTC_INTEN8_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
32941   #define GRTC_INTEN8_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
32942   #define GRTC_INTEN8_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
32943 
32944 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
32945   #define GRTC_INTEN8_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
32946   #define GRTC_INTEN8_COMPARE4_Msk (0x1UL << GRTC_INTEN8_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
32947   #define GRTC_INTEN8_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
32948   #define GRTC_INTEN8_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
32949   #define GRTC_INTEN8_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
32950   #define GRTC_INTEN8_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
32951 
32952 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
32953   #define GRTC_INTEN8_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
32954   #define GRTC_INTEN8_COMPARE5_Msk (0x1UL << GRTC_INTEN8_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
32955   #define GRTC_INTEN8_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
32956   #define GRTC_INTEN8_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
32957   #define GRTC_INTEN8_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
32958   #define GRTC_INTEN8_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
32959 
32960 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
32961   #define GRTC_INTEN8_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
32962   #define GRTC_INTEN8_COMPARE6_Msk (0x1UL << GRTC_INTEN8_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
32963   #define GRTC_INTEN8_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
32964   #define GRTC_INTEN8_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
32965   #define GRTC_INTEN8_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
32966   #define GRTC_INTEN8_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
32967 
32968 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
32969   #define GRTC_INTEN8_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
32970   #define GRTC_INTEN8_COMPARE7_Msk (0x1UL << GRTC_INTEN8_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
32971   #define GRTC_INTEN8_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
32972   #define GRTC_INTEN8_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
32973   #define GRTC_INTEN8_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
32974   #define GRTC_INTEN8_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
32975 
32976 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
32977   #define GRTC_INTEN8_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
32978   #define GRTC_INTEN8_COMPARE8_Msk (0x1UL << GRTC_INTEN8_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
32979   #define GRTC_INTEN8_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
32980   #define GRTC_INTEN8_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
32981   #define GRTC_INTEN8_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
32982   #define GRTC_INTEN8_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
32983 
32984 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
32985   #define GRTC_INTEN8_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
32986   #define GRTC_INTEN8_COMPARE9_Msk (0x1UL << GRTC_INTEN8_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
32987   #define GRTC_INTEN8_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
32988   #define GRTC_INTEN8_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
32989   #define GRTC_INTEN8_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
32990   #define GRTC_INTEN8_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
32991 
32992 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
32993   #define GRTC_INTEN8_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
32994   #define GRTC_INTEN8_COMPARE10_Msk (0x1UL << GRTC_INTEN8_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
32995   #define GRTC_INTEN8_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
32996   #define GRTC_INTEN8_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
32997   #define GRTC_INTEN8_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
32998   #define GRTC_INTEN8_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
32999 
33000 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
33001   #define GRTC_INTEN8_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
33002   #define GRTC_INTEN8_COMPARE11_Msk (0x1UL << GRTC_INTEN8_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
33003   #define GRTC_INTEN8_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
33004   #define GRTC_INTEN8_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
33005   #define GRTC_INTEN8_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
33006   #define GRTC_INTEN8_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
33007 
33008 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
33009   #define GRTC_INTEN8_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
33010   #define GRTC_INTEN8_COMPARE12_Msk (0x1UL << GRTC_INTEN8_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
33011   #define GRTC_INTEN8_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
33012   #define GRTC_INTEN8_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
33013   #define GRTC_INTEN8_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
33014   #define GRTC_INTEN8_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
33015 
33016 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
33017   #define GRTC_INTEN8_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
33018   #define GRTC_INTEN8_COMPARE13_Msk (0x1UL << GRTC_INTEN8_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
33019   #define GRTC_INTEN8_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
33020   #define GRTC_INTEN8_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
33021   #define GRTC_INTEN8_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
33022   #define GRTC_INTEN8_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
33023 
33024 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
33025   #define GRTC_INTEN8_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
33026   #define GRTC_INTEN8_COMPARE14_Msk (0x1UL << GRTC_INTEN8_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
33027   #define GRTC_INTEN8_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
33028   #define GRTC_INTEN8_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
33029   #define GRTC_INTEN8_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
33030   #define GRTC_INTEN8_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
33031 
33032 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
33033   #define GRTC_INTEN8_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
33034   #define GRTC_INTEN8_COMPARE15_Msk (0x1UL << GRTC_INTEN8_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
33035   #define GRTC_INTEN8_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
33036   #define GRTC_INTEN8_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
33037   #define GRTC_INTEN8_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
33038   #define GRTC_INTEN8_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
33039 
33040 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
33041   #define GRTC_INTEN8_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
33042   #define GRTC_INTEN8_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN8_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
33043   #define GRTC_INTEN8_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
33044   #define GRTC_INTEN8_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
33045   #define GRTC_INTEN8_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
33046   #define GRTC_INTEN8_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
33047 
33048 
33049 /* GRTC_INTENSET8: Enable interrupt */
33050   #define GRTC_INTENSET8_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET8 register.                                   */
33051 
33052 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
33053   #define GRTC_INTENSET8_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
33054   #define GRTC_INTENSET8_COMPARE0_Msk (0x1UL << GRTC_INTENSET8_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
33055   #define GRTC_INTENSET8_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
33056   #define GRTC_INTENSET8_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
33057   #define GRTC_INTENSET8_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
33058   #define GRTC_INTENSET8_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33059   #define GRTC_INTENSET8_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33060 
33061 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
33062   #define GRTC_INTENSET8_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
33063   #define GRTC_INTENSET8_COMPARE1_Msk (0x1UL << GRTC_INTENSET8_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
33064   #define GRTC_INTENSET8_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
33065   #define GRTC_INTENSET8_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
33066   #define GRTC_INTENSET8_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
33067   #define GRTC_INTENSET8_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33068   #define GRTC_INTENSET8_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33069 
33070 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
33071   #define GRTC_INTENSET8_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
33072   #define GRTC_INTENSET8_COMPARE2_Msk (0x1UL << GRTC_INTENSET8_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
33073   #define GRTC_INTENSET8_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
33074   #define GRTC_INTENSET8_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
33075   #define GRTC_INTENSET8_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
33076   #define GRTC_INTENSET8_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33077   #define GRTC_INTENSET8_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33078 
33079 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
33080   #define GRTC_INTENSET8_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
33081   #define GRTC_INTENSET8_COMPARE3_Msk (0x1UL << GRTC_INTENSET8_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
33082   #define GRTC_INTENSET8_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
33083   #define GRTC_INTENSET8_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
33084   #define GRTC_INTENSET8_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
33085   #define GRTC_INTENSET8_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33086   #define GRTC_INTENSET8_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33087 
33088 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
33089   #define GRTC_INTENSET8_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
33090   #define GRTC_INTENSET8_COMPARE4_Msk (0x1UL << GRTC_INTENSET8_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
33091   #define GRTC_INTENSET8_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
33092   #define GRTC_INTENSET8_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
33093   #define GRTC_INTENSET8_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
33094   #define GRTC_INTENSET8_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33095   #define GRTC_INTENSET8_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33096 
33097 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
33098   #define GRTC_INTENSET8_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
33099   #define GRTC_INTENSET8_COMPARE5_Msk (0x1UL << GRTC_INTENSET8_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
33100   #define GRTC_INTENSET8_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
33101   #define GRTC_INTENSET8_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
33102   #define GRTC_INTENSET8_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
33103   #define GRTC_INTENSET8_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33104   #define GRTC_INTENSET8_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33105 
33106 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
33107   #define GRTC_INTENSET8_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
33108   #define GRTC_INTENSET8_COMPARE6_Msk (0x1UL << GRTC_INTENSET8_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
33109   #define GRTC_INTENSET8_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
33110   #define GRTC_INTENSET8_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
33111   #define GRTC_INTENSET8_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
33112   #define GRTC_INTENSET8_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33113   #define GRTC_INTENSET8_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33114 
33115 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
33116   #define GRTC_INTENSET8_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
33117   #define GRTC_INTENSET8_COMPARE7_Msk (0x1UL << GRTC_INTENSET8_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
33118   #define GRTC_INTENSET8_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
33119   #define GRTC_INTENSET8_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
33120   #define GRTC_INTENSET8_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
33121   #define GRTC_INTENSET8_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33122   #define GRTC_INTENSET8_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33123 
33124 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
33125   #define GRTC_INTENSET8_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
33126   #define GRTC_INTENSET8_COMPARE8_Msk (0x1UL << GRTC_INTENSET8_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
33127   #define GRTC_INTENSET8_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
33128   #define GRTC_INTENSET8_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
33129   #define GRTC_INTENSET8_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
33130   #define GRTC_INTENSET8_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33131   #define GRTC_INTENSET8_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33132 
33133 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
33134   #define GRTC_INTENSET8_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
33135   #define GRTC_INTENSET8_COMPARE9_Msk (0x1UL << GRTC_INTENSET8_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
33136   #define GRTC_INTENSET8_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
33137   #define GRTC_INTENSET8_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
33138   #define GRTC_INTENSET8_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
33139   #define GRTC_INTENSET8_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33140   #define GRTC_INTENSET8_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33141 
33142 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
33143   #define GRTC_INTENSET8_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
33144   #define GRTC_INTENSET8_COMPARE10_Msk (0x1UL << GRTC_INTENSET8_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
33145   #define GRTC_INTENSET8_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
33146   #define GRTC_INTENSET8_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
33147   #define GRTC_INTENSET8_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
33148   #define GRTC_INTENSET8_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33149   #define GRTC_INTENSET8_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33150 
33151 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
33152   #define GRTC_INTENSET8_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
33153   #define GRTC_INTENSET8_COMPARE11_Msk (0x1UL << GRTC_INTENSET8_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
33154   #define GRTC_INTENSET8_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
33155   #define GRTC_INTENSET8_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
33156   #define GRTC_INTENSET8_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
33157   #define GRTC_INTENSET8_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33158   #define GRTC_INTENSET8_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33159 
33160 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
33161   #define GRTC_INTENSET8_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
33162   #define GRTC_INTENSET8_COMPARE12_Msk (0x1UL << GRTC_INTENSET8_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
33163   #define GRTC_INTENSET8_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
33164   #define GRTC_INTENSET8_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
33165   #define GRTC_INTENSET8_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
33166   #define GRTC_INTENSET8_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33167   #define GRTC_INTENSET8_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33168 
33169 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
33170   #define GRTC_INTENSET8_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
33171   #define GRTC_INTENSET8_COMPARE13_Msk (0x1UL << GRTC_INTENSET8_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
33172   #define GRTC_INTENSET8_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
33173   #define GRTC_INTENSET8_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
33174   #define GRTC_INTENSET8_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
33175   #define GRTC_INTENSET8_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33176   #define GRTC_INTENSET8_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33177 
33178 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
33179   #define GRTC_INTENSET8_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
33180   #define GRTC_INTENSET8_COMPARE14_Msk (0x1UL << GRTC_INTENSET8_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
33181   #define GRTC_INTENSET8_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
33182   #define GRTC_INTENSET8_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
33183   #define GRTC_INTENSET8_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
33184   #define GRTC_INTENSET8_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33185   #define GRTC_INTENSET8_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33186 
33187 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
33188   #define GRTC_INTENSET8_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
33189   #define GRTC_INTENSET8_COMPARE15_Msk (0x1UL << GRTC_INTENSET8_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
33190   #define GRTC_INTENSET8_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
33191   #define GRTC_INTENSET8_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
33192   #define GRTC_INTENSET8_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
33193   #define GRTC_INTENSET8_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33194   #define GRTC_INTENSET8_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33195 
33196 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
33197   #define GRTC_INTENSET8_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
33198   #define GRTC_INTENSET8_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET8_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
33199                                                                             field.*/
33200   #define GRTC_INTENSET8_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
33201   #define GRTC_INTENSET8_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
33202   #define GRTC_INTENSET8_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
33203   #define GRTC_INTENSET8_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
33204   #define GRTC_INTENSET8_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
33205 
33206 
33207 /* GRTC_INTENCLR8: Disable interrupt */
33208   #define GRTC_INTENCLR8_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR8 register.                                   */
33209 
33210 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
33211   #define GRTC_INTENCLR8_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
33212   #define GRTC_INTENCLR8_COMPARE0_Msk (0x1UL << GRTC_INTENCLR8_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
33213   #define GRTC_INTENCLR8_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
33214   #define GRTC_INTENCLR8_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
33215   #define GRTC_INTENCLR8_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
33216   #define GRTC_INTENCLR8_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33217   #define GRTC_INTENCLR8_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33218 
33219 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
33220   #define GRTC_INTENCLR8_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
33221   #define GRTC_INTENCLR8_COMPARE1_Msk (0x1UL << GRTC_INTENCLR8_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
33222   #define GRTC_INTENCLR8_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
33223   #define GRTC_INTENCLR8_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
33224   #define GRTC_INTENCLR8_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
33225   #define GRTC_INTENCLR8_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33226   #define GRTC_INTENCLR8_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33227 
33228 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
33229   #define GRTC_INTENCLR8_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
33230   #define GRTC_INTENCLR8_COMPARE2_Msk (0x1UL << GRTC_INTENCLR8_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
33231   #define GRTC_INTENCLR8_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
33232   #define GRTC_INTENCLR8_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
33233   #define GRTC_INTENCLR8_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
33234   #define GRTC_INTENCLR8_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33235   #define GRTC_INTENCLR8_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33236 
33237 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
33238   #define GRTC_INTENCLR8_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
33239   #define GRTC_INTENCLR8_COMPARE3_Msk (0x1UL << GRTC_INTENCLR8_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
33240   #define GRTC_INTENCLR8_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
33241   #define GRTC_INTENCLR8_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
33242   #define GRTC_INTENCLR8_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
33243   #define GRTC_INTENCLR8_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33244   #define GRTC_INTENCLR8_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33245 
33246 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
33247   #define GRTC_INTENCLR8_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
33248   #define GRTC_INTENCLR8_COMPARE4_Msk (0x1UL << GRTC_INTENCLR8_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
33249   #define GRTC_INTENCLR8_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
33250   #define GRTC_INTENCLR8_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
33251   #define GRTC_INTENCLR8_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
33252   #define GRTC_INTENCLR8_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33253   #define GRTC_INTENCLR8_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33254 
33255 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
33256   #define GRTC_INTENCLR8_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
33257   #define GRTC_INTENCLR8_COMPARE5_Msk (0x1UL << GRTC_INTENCLR8_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
33258   #define GRTC_INTENCLR8_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
33259   #define GRTC_INTENCLR8_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
33260   #define GRTC_INTENCLR8_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
33261   #define GRTC_INTENCLR8_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33262   #define GRTC_INTENCLR8_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33263 
33264 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
33265   #define GRTC_INTENCLR8_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
33266   #define GRTC_INTENCLR8_COMPARE6_Msk (0x1UL << GRTC_INTENCLR8_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
33267   #define GRTC_INTENCLR8_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
33268   #define GRTC_INTENCLR8_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
33269   #define GRTC_INTENCLR8_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
33270   #define GRTC_INTENCLR8_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33271   #define GRTC_INTENCLR8_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33272 
33273 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
33274   #define GRTC_INTENCLR8_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
33275   #define GRTC_INTENCLR8_COMPARE7_Msk (0x1UL << GRTC_INTENCLR8_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
33276   #define GRTC_INTENCLR8_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
33277   #define GRTC_INTENCLR8_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
33278   #define GRTC_INTENCLR8_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
33279   #define GRTC_INTENCLR8_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33280   #define GRTC_INTENCLR8_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33281 
33282 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
33283   #define GRTC_INTENCLR8_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
33284   #define GRTC_INTENCLR8_COMPARE8_Msk (0x1UL << GRTC_INTENCLR8_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
33285   #define GRTC_INTENCLR8_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
33286   #define GRTC_INTENCLR8_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
33287   #define GRTC_INTENCLR8_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
33288   #define GRTC_INTENCLR8_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33289   #define GRTC_INTENCLR8_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33290 
33291 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
33292   #define GRTC_INTENCLR8_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
33293   #define GRTC_INTENCLR8_COMPARE9_Msk (0x1UL << GRTC_INTENCLR8_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
33294   #define GRTC_INTENCLR8_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
33295   #define GRTC_INTENCLR8_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
33296   #define GRTC_INTENCLR8_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
33297   #define GRTC_INTENCLR8_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33298   #define GRTC_INTENCLR8_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33299 
33300 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
33301   #define GRTC_INTENCLR8_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
33302   #define GRTC_INTENCLR8_COMPARE10_Msk (0x1UL << GRTC_INTENCLR8_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
33303   #define GRTC_INTENCLR8_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
33304   #define GRTC_INTENCLR8_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
33305   #define GRTC_INTENCLR8_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
33306   #define GRTC_INTENCLR8_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33307   #define GRTC_INTENCLR8_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33308 
33309 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
33310   #define GRTC_INTENCLR8_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
33311   #define GRTC_INTENCLR8_COMPARE11_Msk (0x1UL << GRTC_INTENCLR8_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
33312   #define GRTC_INTENCLR8_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
33313   #define GRTC_INTENCLR8_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
33314   #define GRTC_INTENCLR8_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
33315   #define GRTC_INTENCLR8_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33316   #define GRTC_INTENCLR8_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33317 
33318 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
33319   #define GRTC_INTENCLR8_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
33320   #define GRTC_INTENCLR8_COMPARE12_Msk (0x1UL << GRTC_INTENCLR8_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
33321   #define GRTC_INTENCLR8_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
33322   #define GRTC_INTENCLR8_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
33323   #define GRTC_INTENCLR8_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
33324   #define GRTC_INTENCLR8_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33325   #define GRTC_INTENCLR8_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33326 
33327 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
33328   #define GRTC_INTENCLR8_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
33329   #define GRTC_INTENCLR8_COMPARE13_Msk (0x1UL << GRTC_INTENCLR8_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
33330   #define GRTC_INTENCLR8_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
33331   #define GRTC_INTENCLR8_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
33332   #define GRTC_INTENCLR8_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
33333   #define GRTC_INTENCLR8_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33334   #define GRTC_INTENCLR8_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33335 
33336 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
33337   #define GRTC_INTENCLR8_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
33338   #define GRTC_INTENCLR8_COMPARE14_Msk (0x1UL << GRTC_INTENCLR8_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
33339   #define GRTC_INTENCLR8_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
33340   #define GRTC_INTENCLR8_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
33341   #define GRTC_INTENCLR8_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
33342   #define GRTC_INTENCLR8_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33343   #define GRTC_INTENCLR8_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33344 
33345 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
33346   #define GRTC_INTENCLR8_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
33347   #define GRTC_INTENCLR8_COMPARE15_Msk (0x1UL << GRTC_INTENCLR8_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
33348   #define GRTC_INTENCLR8_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
33349   #define GRTC_INTENCLR8_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
33350   #define GRTC_INTENCLR8_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
33351   #define GRTC_INTENCLR8_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33352   #define GRTC_INTENCLR8_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33353 
33354 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
33355   #define GRTC_INTENCLR8_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
33356   #define GRTC_INTENCLR8_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR8_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
33357                                                                             field.*/
33358   #define GRTC_INTENCLR8_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
33359   #define GRTC_INTENCLR8_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
33360   #define GRTC_INTENCLR8_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
33361   #define GRTC_INTENCLR8_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
33362   #define GRTC_INTENCLR8_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
33363 
33364 
33365 /* GRTC_INTPEND8: Pending interrupts */
33366   #define GRTC_INTPEND8_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND8 register.                                    */
33367 
33368 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
33369   #define GRTC_INTPEND8_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
33370   #define GRTC_INTPEND8_COMPARE0_Msk (0x1UL << GRTC_INTPEND8_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
33371   #define GRTC_INTPEND8_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
33372   #define GRTC_INTPEND8_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
33373   #define GRTC_INTPEND8_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33374   #define GRTC_INTPEND8_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
33375 
33376 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
33377   #define GRTC_INTPEND8_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
33378   #define GRTC_INTPEND8_COMPARE1_Msk (0x1UL << GRTC_INTPEND8_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
33379   #define GRTC_INTPEND8_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
33380   #define GRTC_INTPEND8_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
33381   #define GRTC_INTPEND8_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33382   #define GRTC_INTPEND8_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
33383 
33384 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
33385   #define GRTC_INTPEND8_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
33386   #define GRTC_INTPEND8_COMPARE2_Msk (0x1UL << GRTC_INTPEND8_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
33387   #define GRTC_INTPEND8_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
33388   #define GRTC_INTPEND8_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
33389   #define GRTC_INTPEND8_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33390   #define GRTC_INTPEND8_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
33391 
33392 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
33393   #define GRTC_INTPEND8_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
33394   #define GRTC_INTPEND8_COMPARE3_Msk (0x1UL << GRTC_INTPEND8_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
33395   #define GRTC_INTPEND8_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
33396   #define GRTC_INTPEND8_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
33397   #define GRTC_INTPEND8_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33398   #define GRTC_INTPEND8_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
33399 
33400 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
33401   #define GRTC_INTPEND8_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
33402   #define GRTC_INTPEND8_COMPARE4_Msk (0x1UL << GRTC_INTPEND8_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
33403   #define GRTC_INTPEND8_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
33404   #define GRTC_INTPEND8_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
33405   #define GRTC_INTPEND8_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33406   #define GRTC_INTPEND8_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
33407 
33408 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
33409   #define GRTC_INTPEND8_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
33410   #define GRTC_INTPEND8_COMPARE5_Msk (0x1UL << GRTC_INTPEND8_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
33411   #define GRTC_INTPEND8_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
33412   #define GRTC_INTPEND8_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
33413   #define GRTC_INTPEND8_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33414   #define GRTC_INTPEND8_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
33415 
33416 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
33417   #define GRTC_INTPEND8_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
33418   #define GRTC_INTPEND8_COMPARE6_Msk (0x1UL << GRTC_INTPEND8_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
33419   #define GRTC_INTPEND8_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
33420   #define GRTC_INTPEND8_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
33421   #define GRTC_INTPEND8_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33422   #define GRTC_INTPEND8_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
33423 
33424 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
33425   #define GRTC_INTPEND8_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
33426   #define GRTC_INTPEND8_COMPARE7_Msk (0x1UL << GRTC_INTPEND8_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
33427   #define GRTC_INTPEND8_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
33428   #define GRTC_INTPEND8_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
33429   #define GRTC_INTPEND8_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33430   #define GRTC_INTPEND8_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
33431 
33432 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
33433   #define GRTC_INTPEND8_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
33434   #define GRTC_INTPEND8_COMPARE8_Msk (0x1UL << GRTC_INTPEND8_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
33435   #define GRTC_INTPEND8_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
33436   #define GRTC_INTPEND8_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
33437   #define GRTC_INTPEND8_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33438   #define GRTC_INTPEND8_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
33439 
33440 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
33441   #define GRTC_INTPEND8_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
33442   #define GRTC_INTPEND8_COMPARE9_Msk (0x1UL << GRTC_INTPEND8_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
33443   #define GRTC_INTPEND8_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
33444   #define GRTC_INTPEND8_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
33445   #define GRTC_INTPEND8_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33446   #define GRTC_INTPEND8_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
33447 
33448 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
33449   #define GRTC_INTPEND8_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
33450   #define GRTC_INTPEND8_COMPARE10_Msk (0x1UL << GRTC_INTPEND8_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
33451   #define GRTC_INTPEND8_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
33452   #define GRTC_INTPEND8_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
33453   #define GRTC_INTPEND8_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
33454   #define GRTC_INTPEND8_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
33455 
33456 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
33457   #define GRTC_INTPEND8_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
33458   #define GRTC_INTPEND8_COMPARE11_Msk (0x1UL << GRTC_INTPEND8_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
33459   #define GRTC_INTPEND8_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
33460   #define GRTC_INTPEND8_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
33461   #define GRTC_INTPEND8_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
33462   #define GRTC_INTPEND8_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
33463 
33464 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
33465   #define GRTC_INTPEND8_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
33466   #define GRTC_INTPEND8_COMPARE12_Msk (0x1UL << GRTC_INTPEND8_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
33467   #define GRTC_INTPEND8_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
33468   #define GRTC_INTPEND8_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
33469   #define GRTC_INTPEND8_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
33470   #define GRTC_INTPEND8_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
33471 
33472 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
33473   #define GRTC_INTPEND8_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
33474   #define GRTC_INTPEND8_COMPARE13_Msk (0x1UL << GRTC_INTPEND8_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
33475   #define GRTC_INTPEND8_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
33476   #define GRTC_INTPEND8_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
33477   #define GRTC_INTPEND8_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
33478   #define GRTC_INTPEND8_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
33479 
33480 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
33481   #define GRTC_INTPEND8_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
33482   #define GRTC_INTPEND8_COMPARE14_Msk (0x1UL << GRTC_INTPEND8_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
33483   #define GRTC_INTPEND8_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
33484   #define GRTC_INTPEND8_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
33485   #define GRTC_INTPEND8_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
33486   #define GRTC_INTPEND8_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
33487 
33488 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
33489   #define GRTC_INTPEND8_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
33490   #define GRTC_INTPEND8_COMPARE15_Msk (0x1UL << GRTC_INTPEND8_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
33491   #define GRTC_INTPEND8_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
33492   #define GRTC_INTPEND8_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
33493   #define GRTC_INTPEND8_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
33494   #define GRTC_INTPEND8_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
33495 
33496 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
33497   #define GRTC_INTPEND8_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
33498   #define GRTC_INTPEND8_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND8_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
33499                                                                             field.*/
33500   #define GRTC_INTPEND8_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
33501   #define GRTC_INTPEND8_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
33502   #define GRTC_INTPEND8_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
33503   #define GRTC_INTPEND8_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
33504 
33505 
33506 /* GRTC_INTEN9: Enable or disable interrupt */
33507   #define GRTC_INTEN9_ResetValue (0x00000000UL)      /*!< Reset value of INTEN9 register.                                      */
33508 
33509 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
33510   #define GRTC_INTEN9_COMPARE0_Pos (0UL)             /*!< Position of COMPARE0 field.                                          */
33511   #define GRTC_INTEN9_COMPARE0_Msk (0x1UL << GRTC_INTEN9_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
33512   #define GRTC_INTEN9_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
33513   #define GRTC_INTEN9_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
33514   #define GRTC_INTEN9_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
33515   #define GRTC_INTEN9_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
33516 
33517 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
33518   #define GRTC_INTEN9_COMPARE1_Pos (1UL)             /*!< Position of COMPARE1 field.                                          */
33519   #define GRTC_INTEN9_COMPARE1_Msk (0x1UL << GRTC_INTEN9_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
33520   #define GRTC_INTEN9_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
33521   #define GRTC_INTEN9_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
33522   #define GRTC_INTEN9_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
33523   #define GRTC_INTEN9_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
33524 
33525 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
33526   #define GRTC_INTEN9_COMPARE2_Pos (2UL)             /*!< Position of COMPARE2 field.                                          */
33527   #define GRTC_INTEN9_COMPARE2_Msk (0x1UL << GRTC_INTEN9_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
33528   #define GRTC_INTEN9_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
33529   #define GRTC_INTEN9_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
33530   #define GRTC_INTEN9_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
33531   #define GRTC_INTEN9_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
33532 
33533 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
33534   #define GRTC_INTEN9_COMPARE3_Pos (3UL)             /*!< Position of COMPARE3 field.                                          */
33535   #define GRTC_INTEN9_COMPARE3_Msk (0x1UL << GRTC_INTEN9_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
33536   #define GRTC_INTEN9_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
33537   #define GRTC_INTEN9_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
33538   #define GRTC_INTEN9_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
33539   #define GRTC_INTEN9_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
33540 
33541 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
33542   #define GRTC_INTEN9_COMPARE4_Pos (4UL)             /*!< Position of COMPARE4 field.                                          */
33543   #define GRTC_INTEN9_COMPARE4_Msk (0x1UL << GRTC_INTEN9_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
33544   #define GRTC_INTEN9_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
33545   #define GRTC_INTEN9_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
33546   #define GRTC_INTEN9_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
33547   #define GRTC_INTEN9_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
33548 
33549 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
33550   #define GRTC_INTEN9_COMPARE5_Pos (5UL)             /*!< Position of COMPARE5 field.                                          */
33551   #define GRTC_INTEN9_COMPARE5_Msk (0x1UL << GRTC_INTEN9_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
33552   #define GRTC_INTEN9_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
33553   #define GRTC_INTEN9_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
33554   #define GRTC_INTEN9_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
33555   #define GRTC_INTEN9_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
33556 
33557 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
33558   #define GRTC_INTEN9_COMPARE6_Pos (6UL)             /*!< Position of COMPARE6 field.                                          */
33559   #define GRTC_INTEN9_COMPARE6_Msk (0x1UL << GRTC_INTEN9_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
33560   #define GRTC_INTEN9_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
33561   #define GRTC_INTEN9_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
33562   #define GRTC_INTEN9_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
33563   #define GRTC_INTEN9_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
33564 
33565 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
33566   #define GRTC_INTEN9_COMPARE7_Pos (7UL)             /*!< Position of COMPARE7 field.                                          */
33567   #define GRTC_INTEN9_COMPARE7_Msk (0x1UL << GRTC_INTEN9_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
33568   #define GRTC_INTEN9_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
33569   #define GRTC_INTEN9_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
33570   #define GRTC_INTEN9_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
33571   #define GRTC_INTEN9_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
33572 
33573 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
33574   #define GRTC_INTEN9_COMPARE8_Pos (8UL)             /*!< Position of COMPARE8 field.                                          */
33575   #define GRTC_INTEN9_COMPARE8_Msk (0x1UL << GRTC_INTEN9_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                        */
33576   #define GRTC_INTEN9_COMPARE8_Min (0x0UL)           /*!< Min enumerator value of COMPARE8 field.                              */
33577   #define GRTC_INTEN9_COMPARE8_Max (0x1UL)           /*!< Max enumerator value of COMPARE8 field.                              */
33578   #define GRTC_INTEN9_COMPARE8_Disabled (0x0UL)      /*!< Disable                                                              */
33579   #define GRTC_INTEN9_COMPARE8_Enabled (0x1UL)       /*!< Enable                                                               */
33580 
33581 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
33582   #define GRTC_INTEN9_COMPARE9_Pos (9UL)             /*!< Position of COMPARE9 field.                                          */
33583   #define GRTC_INTEN9_COMPARE9_Msk (0x1UL << GRTC_INTEN9_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                        */
33584   #define GRTC_INTEN9_COMPARE9_Min (0x0UL)           /*!< Min enumerator value of COMPARE9 field.                              */
33585   #define GRTC_INTEN9_COMPARE9_Max (0x1UL)           /*!< Max enumerator value of COMPARE9 field.                              */
33586   #define GRTC_INTEN9_COMPARE9_Disabled (0x0UL)      /*!< Disable                                                              */
33587   #define GRTC_INTEN9_COMPARE9_Enabled (0x1UL)       /*!< Enable                                                               */
33588 
33589 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
33590   #define GRTC_INTEN9_COMPARE10_Pos (10UL)           /*!< Position of COMPARE10 field.                                         */
33591   #define GRTC_INTEN9_COMPARE10_Msk (0x1UL << GRTC_INTEN9_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                     */
33592   #define GRTC_INTEN9_COMPARE10_Min (0x0UL)          /*!< Min enumerator value of COMPARE10 field.                             */
33593   #define GRTC_INTEN9_COMPARE10_Max (0x1UL)          /*!< Max enumerator value of COMPARE10 field.                             */
33594   #define GRTC_INTEN9_COMPARE10_Disabled (0x0UL)     /*!< Disable                                                              */
33595   #define GRTC_INTEN9_COMPARE10_Enabled (0x1UL)      /*!< Enable                                                               */
33596 
33597 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
33598   #define GRTC_INTEN9_COMPARE11_Pos (11UL)           /*!< Position of COMPARE11 field.                                         */
33599   #define GRTC_INTEN9_COMPARE11_Msk (0x1UL << GRTC_INTEN9_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                     */
33600   #define GRTC_INTEN9_COMPARE11_Min (0x0UL)          /*!< Min enumerator value of COMPARE11 field.                             */
33601   #define GRTC_INTEN9_COMPARE11_Max (0x1UL)          /*!< Max enumerator value of COMPARE11 field.                             */
33602   #define GRTC_INTEN9_COMPARE11_Disabled (0x0UL)     /*!< Disable                                                              */
33603   #define GRTC_INTEN9_COMPARE11_Enabled (0x1UL)      /*!< Enable                                                               */
33604 
33605 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
33606   #define GRTC_INTEN9_COMPARE12_Pos (12UL)           /*!< Position of COMPARE12 field.                                         */
33607   #define GRTC_INTEN9_COMPARE12_Msk (0x1UL << GRTC_INTEN9_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                     */
33608   #define GRTC_INTEN9_COMPARE12_Min (0x0UL)          /*!< Min enumerator value of COMPARE12 field.                             */
33609   #define GRTC_INTEN9_COMPARE12_Max (0x1UL)          /*!< Max enumerator value of COMPARE12 field.                             */
33610   #define GRTC_INTEN9_COMPARE12_Disabled (0x0UL)     /*!< Disable                                                              */
33611   #define GRTC_INTEN9_COMPARE12_Enabled (0x1UL)      /*!< Enable                                                               */
33612 
33613 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
33614   #define GRTC_INTEN9_COMPARE13_Pos (13UL)           /*!< Position of COMPARE13 field.                                         */
33615   #define GRTC_INTEN9_COMPARE13_Msk (0x1UL << GRTC_INTEN9_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                     */
33616   #define GRTC_INTEN9_COMPARE13_Min (0x0UL)          /*!< Min enumerator value of COMPARE13 field.                             */
33617   #define GRTC_INTEN9_COMPARE13_Max (0x1UL)          /*!< Max enumerator value of COMPARE13 field.                             */
33618   #define GRTC_INTEN9_COMPARE13_Disabled (0x0UL)     /*!< Disable                                                              */
33619   #define GRTC_INTEN9_COMPARE13_Enabled (0x1UL)      /*!< Enable                                                               */
33620 
33621 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
33622   #define GRTC_INTEN9_COMPARE14_Pos (14UL)           /*!< Position of COMPARE14 field.                                         */
33623   #define GRTC_INTEN9_COMPARE14_Msk (0x1UL << GRTC_INTEN9_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                     */
33624   #define GRTC_INTEN9_COMPARE14_Min (0x0UL)          /*!< Min enumerator value of COMPARE14 field.                             */
33625   #define GRTC_INTEN9_COMPARE14_Max (0x1UL)          /*!< Max enumerator value of COMPARE14 field.                             */
33626   #define GRTC_INTEN9_COMPARE14_Disabled (0x0UL)     /*!< Disable                                                              */
33627   #define GRTC_INTEN9_COMPARE14_Enabled (0x1UL)      /*!< Enable                                                               */
33628 
33629 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
33630   #define GRTC_INTEN9_COMPARE15_Pos (15UL)           /*!< Position of COMPARE15 field.                                         */
33631   #define GRTC_INTEN9_COMPARE15_Msk (0x1UL << GRTC_INTEN9_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                     */
33632   #define GRTC_INTEN9_COMPARE15_Min (0x0UL)          /*!< Min enumerator value of COMPARE15 field.                             */
33633   #define GRTC_INTEN9_COMPARE15_Max (0x1UL)          /*!< Max enumerator value of COMPARE15 field.                             */
33634   #define GRTC_INTEN9_COMPARE15_Disabled (0x0UL)     /*!< Disable                                                              */
33635   #define GRTC_INTEN9_COMPARE15_Enabled (0x1UL)      /*!< Enable                                                               */
33636 
33637 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
33638   #define GRTC_INTEN9_SYSCOUNTERVALID_Pos (26UL)     /*!< Position of SYSCOUNTERVALID field.                                   */
33639   #define GRTC_INTEN9_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN9_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field.   */
33640   #define GRTC_INTEN9_SYSCOUNTERVALID_Min (0x0UL)    /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
33641   #define GRTC_INTEN9_SYSCOUNTERVALID_Max (0x1UL)    /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
33642   #define GRTC_INTEN9_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                            */
33643   #define GRTC_INTEN9_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                              */
33644 
33645 
33646 /* GRTC_INTENSET9: Enable interrupt */
33647   #define GRTC_INTENSET9_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET9 register.                                   */
33648 
33649 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
33650   #define GRTC_INTENSET9_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
33651   #define GRTC_INTENSET9_COMPARE0_Msk (0x1UL << GRTC_INTENSET9_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
33652   #define GRTC_INTENSET9_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
33653   #define GRTC_INTENSET9_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
33654   #define GRTC_INTENSET9_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
33655   #define GRTC_INTENSET9_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33656   #define GRTC_INTENSET9_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33657 
33658 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
33659   #define GRTC_INTENSET9_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
33660   #define GRTC_INTENSET9_COMPARE1_Msk (0x1UL << GRTC_INTENSET9_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
33661   #define GRTC_INTENSET9_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
33662   #define GRTC_INTENSET9_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
33663   #define GRTC_INTENSET9_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
33664   #define GRTC_INTENSET9_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33665   #define GRTC_INTENSET9_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33666 
33667 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
33668   #define GRTC_INTENSET9_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
33669   #define GRTC_INTENSET9_COMPARE2_Msk (0x1UL << GRTC_INTENSET9_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
33670   #define GRTC_INTENSET9_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
33671   #define GRTC_INTENSET9_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
33672   #define GRTC_INTENSET9_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
33673   #define GRTC_INTENSET9_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33674   #define GRTC_INTENSET9_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33675 
33676 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
33677   #define GRTC_INTENSET9_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
33678   #define GRTC_INTENSET9_COMPARE3_Msk (0x1UL << GRTC_INTENSET9_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
33679   #define GRTC_INTENSET9_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
33680   #define GRTC_INTENSET9_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
33681   #define GRTC_INTENSET9_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
33682   #define GRTC_INTENSET9_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33683   #define GRTC_INTENSET9_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33684 
33685 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
33686   #define GRTC_INTENSET9_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
33687   #define GRTC_INTENSET9_COMPARE4_Msk (0x1UL << GRTC_INTENSET9_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
33688   #define GRTC_INTENSET9_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
33689   #define GRTC_INTENSET9_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
33690   #define GRTC_INTENSET9_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
33691   #define GRTC_INTENSET9_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33692   #define GRTC_INTENSET9_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33693 
33694 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
33695   #define GRTC_INTENSET9_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
33696   #define GRTC_INTENSET9_COMPARE5_Msk (0x1UL << GRTC_INTENSET9_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
33697   #define GRTC_INTENSET9_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
33698   #define GRTC_INTENSET9_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
33699   #define GRTC_INTENSET9_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
33700   #define GRTC_INTENSET9_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33701   #define GRTC_INTENSET9_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33702 
33703 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
33704   #define GRTC_INTENSET9_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
33705   #define GRTC_INTENSET9_COMPARE6_Msk (0x1UL << GRTC_INTENSET9_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
33706   #define GRTC_INTENSET9_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
33707   #define GRTC_INTENSET9_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
33708   #define GRTC_INTENSET9_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
33709   #define GRTC_INTENSET9_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33710   #define GRTC_INTENSET9_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33711 
33712 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
33713   #define GRTC_INTENSET9_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
33714   #define GRTC_INTENSET9_COMPARE7_Msk (0x1UL << GRTC_INTENSET9_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
33715   #define GRTC_INTENSET9_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
33716   #define GRTC_INTENSET9_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
33717   #define GRTC_INTENSET9_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
33718   #define GRTC_INTENSET9_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33719   #define GRTC_INTENSET9_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33720 
33721 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
33722   #define GRTC_INTENSET9_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
33723   #define GRTC_INTENSET9_COMPARE8_Msk (0x1UL << GRTC_INTENSET9_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
33724   #define GRTC_INTENSET9_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
33725   #define GRTC_INTENSET9_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
33726   #define GRTC_INTENSET9_COMPARE8_Set (0x1UL)        /*!< Enable                                                               */
33727   #define GRTC_INTENSET9_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33728   #define GRTC_INTENSET9_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33729 
33730 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
33731   #define GRTC_INTENSET9_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
33732   #define GRTC_INTENSET9_COMPARE9_Msk (0x1UL << GRTC_INTENSET9_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
33733   #define GRTC_INTENSET9_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
33734   #define GRTC_INTENSET9_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
33735   #define GRTC_INTENSET9_COMPARE9_Set (0x1UL)        /*!< Enable                                                               */
33736   #define GRTC_INTENSET9_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33737   #define GRTC_INTENSET9_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33738 
33739 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
33740   #define GRTC_INTENSET9_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
33741   #define GRTC_INTENSET9_COMPARE10_Msk (0x1UL << GRTC_INTENSET9_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
33742   #define GRTC_INTENSET9_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
33743   #define GRTC_INTENSET9_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
33744   #define GRTC_INTENSET9_COMPARE10_Set (0x1UL)       /*!< Enable                                                               */
33745   #define GRTC_INTENSET9_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33746   #define GRTC_INTENSET9_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33747 
33748 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
33749   #define GRTC_INTENSET9_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
33750   #define GRTC_INTENSET9_COMPARE11_Msk (0x1UL << GRTC_INTENSET9_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
33751   #define GRTC_INTENSET9_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
33752   #define GRTC_INTENSET9_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
33753   #define GRTC_INTENSET9_COMPARE11_Set (0x1UL)       /*!< Enable                                                               */
33754   #define GRTC_INTENSET9_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33755   #define GRTC_INTENSET9_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33756 
33757 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
33758   #define GRTC_INTENSET9_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
33759   #define GRTC_INTENSET9_COMPARE12_Msk (0x1UL << GRTC_INTENSET9_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
33760   #define GRTC_INTENSET9_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
33761   #define GRTC_INTENSET9_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
33762   #define GRTC_INTENSET9_COMPARE12_Set (0x1UL)       /*!< Enable                                                               */
33763   #define GRTC_INTENSET9_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33764   #define GRTC_INTENSET9_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33765 
33766 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
33767   #define GRTC_INTENSET9_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
33768   #define GRTC_INTENSET9_COMPARE13_Msk (0x1UL << GRTC_INTENSET9_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
33769   #define GRTC_INTENSET9_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
33770   #define GRTC_INTENSET9_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
33771   #define GRTC_INTENSET9_COMPARE13_Set (0x1UL)       /*!< Enable                                                               */
33772   #define GRTC_INTENSET9_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33773   #define GRTC_INTENSET9_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33774 
33775 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
33776   #define GRTC_INTENSET9_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
33777   #define GRTC_INTENSET9_COMPARE14_Msk (0x1UL << GRTC_INTENSET9_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
33778   #define GRTC_INTENSET9_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
33779   #define GRTC_INTENSET9_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
33780   #define GRTC_INTENSET9_COMPARE14_Set (0x1UL)       /*!< Enable                                                               */
33781   #define GRTC_INTENSET9_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33782   #define GRTC_INTENSET9_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33783 
33784 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
33785   #define GRTC_INTENSET9_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
33786   #define GRTC_INTENSET9_COMPARE15_Msk (0x1UL << GRTC_INTENSET9_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
33787   #define GRTC_INTENSET9_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
33788   #define GRTC_INTENSET9_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
33789   #define GRTC_INTENSET9_COMPARE15_Set (0x1UL)       /*!< Enable                                                               */
33790   #define GRTC_INTENSET9_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33791   #define GRTC_INTENSET9_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33792 
33793 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
33794   #define GRTC_INTENSET9_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
33795   #define GRTC_INTENSET9_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET9_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
33796                                                                             field.*/
33797   #define GRTC_INTENSET9_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
33798   #define GRTC_INTENSET9_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
33799   #define GRTC_INTENSET9_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                               */
33800   #define GRTC_INTENSET9_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
33801   #define GRTC_INTENSET9_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
33802 
33803 
33804 /* GRTC_INTENCLR9: Disable interrupt */
33805   #define GRTC_INTENCLR9_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR9 register.                                   */
33806 
33807 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
33808   #define GRTC_INTENCLR9_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
33809   #define GRTC_INTENCLR9_COMPARE0_Msk (0x1UL << GRTC_INTENCLR9_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
33810   #define GRTC_INTENCLR9_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
33811   #define GRTC_INTENCLR9_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
33812   #define GRTC_INTENCLR9_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
33813   #define GRTC_INTENCLR9_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33814   #define GRTC_INTENCLR9_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33815 
33816 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
33817   #define GRTC_INTENCLR9_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
33818   #define GRTC_INTENCLR9_COMPARE1_Msk (0x1UL << GRTC_INTENCLR9_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
33819   #define GRTC_INTENCLR9_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
33820   #define GRTC_INTENCLR9_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
33821   #define GRTC_INTENCLR9_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
33822   #define GRTC_INTENCLR9_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33823   #define GRTC_INTENCLR9_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33824 
33825 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
33826   #define GRTC_INTENCLR9_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
33827   #define GRTC_INTENCLR9_COMPARE2_Msk (0x1UL << GRTC_INTENCLR9_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
33828   #define GRTC_INTENCLR9_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
33829   #define GRTC_INTENCLR9_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
33830   #define GRTC_INTENCLR9_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
33831   #define GRTC_INTENCLR9_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33832   #define GRTC_INTENCLR9_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33833 
33834 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
33835   #define GRTC_INTENCLR9_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
33836   #define GRTC_INTENCLR9_COMPARE3_Msk (0x1UL << GRTC_INTENCLR9_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
33837   #define GRTC_INTENCLR9_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
33838   #define GRTC_INTENCLR9_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
33839   #define GRTC_INTENCLR9_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
33840   #define GRTC_INTENCLR9_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33841   #define GRTC_INTENCLR9_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33842 
33843 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
33844   #define GRTC_INTENCLR9_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
33845   #define GRTC_INTENCLR9_COMPARE4_Msk (0x1UL << GRTC_INTENCLR9_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
33846   #define GRTC_INTENCLR9_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
33847   #define GRTC_INTENCLR9_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
33848   #define GRTC_INTENCLR9_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
33849   #define GRTC_INTENCLR9_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33850   #define GRTC_INTENCLR9_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33851 
33852 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
33853   #define GRTC_INTENCLR9_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
33854   #define GRTC_INTENCLR9_COMPARE5_Msk (0x1UL << GRTC_INTENCLR9_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
33855   #define GRTC_INTENCLR9_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
33856   #define GRTC_INTENCLR9_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
33857   #define GRTC_INTENCLR9_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
33858   #define GRTC_INTENCLR9_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33859   #define GRTC_INTENCLR9_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33860 
33861 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
33862   #define GRTC_INTENCLR9_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
33863   #define GRTC_INTENCLR9_COMPARE6_Msk (0x1UL << GRTC_INTENCLR9_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
33864   #define GRTC_INTENCLR9_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
33865   #define GRTC_INTENCLR9_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
33866   #define GRTC_INTENCLR9_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
33867   #define GRTC_INTENCLR9_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33868   #define GRTC_INTENCLR9_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33869 
33870 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
33871   #define GRTC_INTENCLR9_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
33872   #define GRTC_INTENCLR9_COMPARE7_Msk (0x1UL << GRTC_INTENCLR9_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
33873   #define GRTC_INTENCLR9_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
33874   #define GRTC_INTENCLR9_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
33875   #define GRTC_INTENCLR9_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
33876   #define GRTC_INTENCLR9_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33877   #define GRTC_INTENCLR9_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33878 
33879 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
33880   #define GRTC_INTENCLR9_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
33881   #define GRTC_INTENCLR9_COMPARE8_Msk (0x1UL << GRTC_INTENCLR9_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
33882   #define GRTC_INTENCLR9_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
33883   #define GRTC_INTENCLR9_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
33884   #define GRTC_INTENCLR9_COMPARE8_Clear (0x1UL)      /*!< Disable                                                              */
33885   #define GRTC_INTENCLR9_COMPARE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33886   #define GRTC_INTENCLR9_COMPARE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33887 
33888 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
33889   #define GRTC_INTENCLR9_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
33890   #define GRTC_INTENCLR9_COMPARE9_Msk (0x1UL << GRTC_INTENCLR9_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
33891   #define GRTC_INTENCLR9_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
33892   #define GRTC_INTENCLR9_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
33893   #define GRTC_INTENCLR9_COMPARE9_Clear (0x1UL)      /*!< Disable                                                              */
33894   #define GRTC_INTENCLR9_COMPARE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
33895   #define GRTC_INTENCLR9_COMPARE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
33896 
33897 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
33898   #define GRTC_INTENCLR9_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
33899   #define GRTC_INTENCLR9_COMPARE10_Msk (0x1UL << GRTC_INTENCLR9_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
33900   #define GRTC_INTENCLR9_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
33901   #define GRTC_INTENCLR9_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
33902   #define GRTC_INTENCLR9_COMPARE10_Clear (0x1UL)     /*!< Disable                                                              */
33903   #define GRTC_INTENCLR9_COMPARE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33904   #define GRTC_INTENCLR9_COMPARE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33905 
33906 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
33907   #define GRTC_INTENCLR9_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
33908   #define GRTC_INTENCLR9_COMPARE11_Msk (0x1UL << GRTC_INTENCLR9_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
33909   #define GRTC_INTENCLR9_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
33910   #define GRTC_INTENCLR9_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
33911   #define GRTC_INTENCLR9_COMPARE11_Clear (0x1UL)     /*!< Disable                                                              */
33912   #define GRTC_INTENCLR9_COMPARE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33913   #define GRTC_INTENCLR9_COMPARE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33914 
33915 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
33916   #define GRTC_INTENCLR9_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
33917   #define GRTC_INTENCLR9_COMPARE12_Msk (0x1UL << GRTC_INTENCLR9_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
33918   #define GRTC_INTENCLR9_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
33919   #define GRTC_INTENCLR9_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
33920   #define GRTC_INTENCLR9_COMPARE12_Clear (0x1UL)     /*!< Disable                                                              */
33921   #define GRTC_INTENCLR9_COMPARE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33922   #define GRTC_INTENCLR9_COMPARE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33923 
33924 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
33925   #define GRTC_INTENCLR9_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
33926   #define GRTC_INTENCLR9_COMPARE13_Msk (0x1UL << GRTC_INTENCLR9_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
33927   #define GRTC_INTENCLR9_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
33928   #define GRTC_INTENCLR9_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
33929   #define GRTC_INTENCLR9_COMPARE13_Clear (0x1UL)     /*!< Disable                                                              */
33930   #define GRTC_INTENCLR9_COMPARE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33931   #define GRTC_INTENCLR9_COMPARE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33932 
33933 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
33934   #define GRTC_INTENCLR9_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
33935   #define GRTC_INTENCLR9_COMPARE14_Msk (0x1UL << GRTC_INTENCLR9_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
33936   #define GRTC_INTENCLR9_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
33937   #define GRTC_INTENCLR9_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
33938   #define GRTC_INTENCLR9_COMPARE14_Clear (0x1UL)     /*!< Disable                                                              */
33939   #define GRTC_INTENCLR9_COMPARE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33940   #define GRTC_INTENCLR9_COMPARE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33941 
33942 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
33943   #define GRTC_INTENCLR9_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
33944   #define GRTC_INTENCLR9_COMPARE15_Msk (0x1UL << GRTC_INTENCLR9_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
33945   #define GRTC_INTENCLR9_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
33946   #define GRTC_INTENCLR9_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
33947   #define GRTC_INTENCLR9_COMPARE15_Clear (0x1UL)     /*!< Disable                                                              */
33948   #define GRTC_INTENCLR9_COMPARE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
33949   #define GRTC_INTENCLR9_COMPARE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
33950 
33951 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
33952   #define GRTC_INTENCLR9_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
33953   #define GRTC_INTENCLR9_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR9_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
33954                                                                             field.*/
33955   #define GRTC_INTENCLR9_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
33956   #define GRTC_INTENCLR9_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
33957   #define GRTC_INTENCLR9_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                            */
33958   #define GRTC_INTENCLR9_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                  */
33959   #define GRTC_INTENCLR9_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                    */
33960 
33961 
33962 /* GRTC_INTPEND9: Pending interrupts */
33963   #define GRTC_INTPEND9_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND9 register.                                    */
33964 
33965 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
33966   #define GRTC_INTPEND9_COMPARE0_Pos (0UL)           /*!< Position of COMPARE0 field.                                          */
33967   #define GRTC_INTPEND9_COMPARE0_Msk (0x1UL << GRTC_INTPEND9_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                    */
33968   #define GRTC_INTPEND9_COMPARE0_Min (0x0UL)         /*!< Min enumerator value of COMPARE0 field.                              */
33969   #define GRTC_INTPEND9_COMPARE0_Max (0x1UL)         /*!< Max enumerator value of COMPARE0 field.                              */
33970   #define GRTC_INTPEND9_COMPARE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33971   #define GRTC_INTPEND9_COMPARE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
33972 
33973 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
33974   #define GRTC_INTPEND9_COMPARE1_Pos (1UL)           /*!< Position of COMPARE1 field.                                          */
33975   #define GRTC_INTPEND9_COMPARE1_Msk (0x1UL << GRTC_INTPEND9_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                    */
33976   #define GRTC_INTPEND9_COMPARE1_Min (0x0UL)         /*!< Min enumerator value of COMPARE1 field.                              */
33977   #define GRTC_INTPEND9_COMPARE1_Max (0x1UL)         /*!< Max enumerator value of COMPARE1 field.                              */
33978   #define GRTC_INTPEND9_COMPARE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33979   #define GRTC_INTPEND9_COMPARE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
33980 
33981 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
33982   #define GRTC_INTPEND9_COMPARE2_Pos (2UL)           /*!< Position of COMPARE2 field.                                          */
33983   #define GRTC_INTPEND9_COMPARE2_Msk (0x1UL << GRTC_INTPEND9_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                    */
33984   #define GRTC_INTPEND9_COMPARE2_Min (0x0UL)         /*!< Min enumerator value of COMPARE2 field.                              */
33985   #define GRTC_INTPEND9_COMPARE2_Max (0x1UL)         /*!< Max enumerator value of COMPARE2 field.                              */
33986   #define GRTC_INTPEND9_COMPARE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33987   #define GRTC_INTPEND9_COMPARE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
33988 
33989 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
33990   #define GRTC_INTPEND9_COMPARE3_Pos (3UL)           /*!< Position of COMPARE3 field.                                          */
33991   #define GRTC_INTPEND9_COMPARE3_Msk (0x1UL << GRTC_INTPEND9_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                    */
33992   #define GRTC_INTPEND9_COMPARE3_Min (0x0UL)         /*!< Min enumerator value of COMPARE3 field.                              */
33993   #define GRTC_INTPEND9_COMPARE3_Max (0x1UL)         /*!< Max enumerator value of COMPARE3 field.                              */
33994   #define GRTC_INTPEND9_COMPARE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
33995   #define GRTC_INTPEND9_COMPARE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
33996 
33997 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
33998   #define GRTC_INTPEND9_COMPARE4_Pos (4UL)           /*!< Position of COMPARE4 field.                                          */
33999   #define GRTC_INTPEND9_COMPARE4_Msk (0x1UL << GRTC_INTPEND9_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                    */
34000   #define GRTC_INTPEND9_COMPARE4_Min (0x0UL)         /*!< Min enumerator value of COMPARE4 field.                              */
34001   #define GRTC_INTPEND9_COMPARE4_Max (0x1UL)         /*!< Max enumerator value of COMPARE4 field.                              */
34002   #define GRTC_INTPEND9_COMPARE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
34003   #define GRTC_INTPEND9_COMPARE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
34004 
34005 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
34006   #define GRTC_INTPEND9_COMPARE5_Pos (5UL)           /*!< Position of COMPARE5 field.                                          */
34007   #define GRTC_INTPEND9_COMPARE5_Msk (0x1UL << GRTC_INTPEND9_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                    */
34008   #define GRTC_INTPEND9_COMPARE5_Min (0x0UL)         /*!< Min enumerator value of COMPARE5 field.                              */
34009   #define GRTC_INTPEND9_COMPARE5_Max (0x1UL)         /*!< Max enumerator value of COMPARE5 field.                              */
34010   #define GRTC_INTPEND9_COMPARE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
34011   #define GRTC_INTPEND9_COMPARE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
34012 
34013 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
34014   #define GRTC_INTPEND9_COMPARE6_Pos (6UL)           /*!< Position of COMPARE6 field.                                          */
34015   #define GRTC_INTPEND9_COMPARE6_Msk (0x1UL << GRTC_INTPEND9_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                    */
34016   #define GRTC_INTPEND9_COMPARE6_Min (0x0UL)         /*!< Min enumerator value of COMPARE6 field.                              */
34017   #define GRTC_INTPEND9_COMPARE6_Max (0x1UL)         /*!< Max enumerator value of COMPARE6 field.                              */
34018   #define GRTC_INTPEND9_COMPARE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
34019   #define GRTC_INTPEND9_COMPARE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
34020 
34021 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
34022   #define GRTC_INTPEND9_COMPARE7_Pos (7UL)           /*!< Position of COMPARE7 field.                                          */
34023   #define GRTC_INTPEND9_COMPARE7_Msk (0x1UL << GRTC_INTPEND9_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                    */
34024   #define GRTC_INTPEND9_COMPARE7_Min (0x0UL)         /*!< Min enumerator value of COMPARE7 field.                              */
34025   #define GRTC_INTPEND9_COMPARE7_Max (0x1UL)         /*!< Max enumerator value of COMPARE7 field.                              */
34026   #define GRTC_INTPEND9_COMPARE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
34027   #define GRTC_INTPEND9_COMPARE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
34028 
34029 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
34030   #define GRTC_INTPEND9_COMPARE8_Pos (8UL)           /*!< Position of COMPARE8 field.                                          */
34031   #define GRTC_INTPEND9_COMPARE8_Msk (0x1UL << GRTC_INTPEND9_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                    */
34032   #define GRTC_INTPEND9_COMPARE8_Min (0x0UL)         /*!< Min enumerator value of COMPARE8 field.                              */
34033   #define GRTC_INTPEND9_COMPARE8_Max (0x1UL)         /*!< Max enumerator value of COMPARE8 field.                              */
34034   #define GRTC_INTPEND9_COMPARE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
34035   #define GRTC_INTPEND9_COMPARE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
34036 
34037 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
34038   #define GRTC_INTPEND9_COMPARE9_Pos (9UL)           /*!< Position of COMPARE9 field.                                          */
34039   #define GRTC_INTPEND9_COMPARE9_Msk (0x1UL << GRTC_INTPEND9_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                    */
34040   #define GRTC_INTPEND9_COMPARE9_Min (0x0UL)         /*!< Min enumerator value of COMPARE9 field.                              */
34041   #define GRTC_INTPEND9_COMPARE9_Max (0x1UL)         /*!< Max enumerator value of COMPARE9 field.                              */
34042   #define GRTC_INTPEND9_COMPARE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
34043   #define GRTC_INTPEND9_COMPARE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
34044 
34045 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
34046   #define GRTC_INTPEND9_COMPARE10_Pos (10UL)         /*!< Position of COMPARE10 field.                                         */
34047   #define GRTC_INTPEND9_COMPARE10_Msk (0x1UL << GRTC_INTPEND9_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                 */
34048   #define GRTC_INTPEND9_COMPARE10_Min (0x0UL)        /*!< Min enumerator value of COMPARE10 field.                             */
34049   #define GRTC_INTPEND9_COMPARE10_Max (0x1UL)        /*!< Max enumerator value of COMPARE10 field.                             */
34050   #define GRTC_INTPEND9_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34051   #define GRTC_INTPEND9_COMPARE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
34052 
34053 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
34054   #define GRTC_INTPEND9_COMPARE11_Pos (11UL)         /*!< Position of COMPARE11 field.                                         */
34055   #define GRTC_INTPEND9_COMPARE11_Msk (0x1UL << GRTC_INTPEND9_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                 */
34056   #define GRTC_INTPEND9_COMPARE11_Min (0x0UL)        /*!< Min enumerator value of COMPARE11 field.                             */
34057   #define GRTC_INTPEND9_COMPARE11_Max (0x1UL)        /*!< Max enumerator value of COMPARE11 field.                             */
34058   #define GRTC_INTPEND9_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34059   #define GRTC_INTPEND9_COMPARE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
34060 
34061 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
34062   #define GRTC_INTPEND9_COMPARE12_Pos (12UL)         /*!< Position of COMPARE12 field.                                         */
34063   #define GRTC_INTPEND9_COMPARE12_Msk (0x1UL << GRTC_INTPEND9_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                 */
34064   #define GRTC_INTPEND9_COMPARE12_Min (0x0UL)        /*!< Min enumerator value of COMPARE12 field.                             */
34065   #define GRTC_INTPEND9_COMPARE12_Max (0x1UL)        /*!< Max enumerator value of COMPARE12 field.                             */
34066   #define GRTC_INTPEND9_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34067   #define GRTC_INTPEND9_COMPARE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
34068 
34069 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
34070   #define GRTC_INTPEND9_COMPARE13_Pos (13UL)         /*!< Position of COMPARE13 field.                                         */
34071   #define GRTC_INTPEND9_COMPARE13_Msk (0x1UL << GRTC_INTPEND9_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                 */
34072   #define GRTC_INTPEND9_COMPARE13_Min (0x0UL)        /*!< Min enumerator value of COMPARE13 field.                             */
34073   #define GRTC_INTPEND9_COMPARE13_Max (0x1UL)        /*!< Max enumerator value of COMPARE13 field.                             */
34074   #define GRTC_INTPEND9_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34075   #define GRTC_INTPEND9_COMPARE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
34076 
34077 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
34078   #define GRTC_INTPEND9_COMPARE14_Pos (14UL)         /*!< Position of COMPARE14 field.                                         */
34079   #define GRTC_INTPEND9_COMPARE14_Msk (0x1UL << GRTC_INTPEND9_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                 */
34080   #define GRTC_INTPEND9_COMPARE14_Min (0x0UL)        /*!< Min enumerator value of COMPARE14 field.                             */
34081   #define GRTC_INTPEND9_COMPARE14_Max (0x1UL)        /*!< Max enumerator value of COMPARE14 field.                             */
34082   #define GRTC_INTPEND9_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34083   #define GRTC_INTPEND9_COMPARE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
34084 
34085 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
34086   #define GRTC_INTPEND9_COMPARE15_Pos (15UL)         /*!< Position of COMPARE15 field.                                         */
34087   #define GRTC_INTPEND9_COMPARE15_Msk (0x1UL << GRTC_INTPEND9_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                 */
34088   #define GRTC_INTPEND9_COMPARE15_Min (0x0UL)        /*!< Min enumerator value of COMPARE15 field.                             */
34089   #define GRTC_INTPEND9_COMPARE15_Max (0x1UL)        /*!< Max enumerator value of COMPARE15 field.                             */
34090   #define GRTC_INTPEND9_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34091   #define GRTC_INTPEND9_COMPARE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
34092 
34093 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
34094   #define GRTC_INTPEND9_SYSCOUNTERVALID_Pos (26UL)   /*!< Position of SYSCOUNTERVALID field.                                   */
34095   #define GRTC_INTPEND9_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND9_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
34096                                                                             field.*/
34097   #define GRTC_INTPEND9_SYSCOUNTERVALID_Min (0x0UL)  /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
34098   #define GRTC_INTPEND9_SYSCOUNTERVALID_Max (0x1UL)  /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
34099   #define GRTC_INTPEND9_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                              */
34100   #define GRTC_INTPEND9_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                     */
34101 
34102 
34103 /* GRTC_INTEN10: Enable or disable interrupt */
34104   #define GRTC_INTEN10_ResetValue (0x00000000UL)     /*!< Reset value of INTEN10 register.                                     */
34105 
34106 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
34107   #define GRTC_INTEN10_COMPARE0_Pos (0UL)            /*!< Position of COMPARE0 field.                                          */
34108   #define GRTC_INTEN10_COMPARE0_Msk (0x1UL << GRTC_INTEN10_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
34109   #define GRTC_INTEN10_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
34110   #define GRTC_INTEN10_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
34111   #define GRTC_INTEN10_COMPARE0_Disabled (0x0UL)     /*!< Disable                                                              */
34112   #define GRTC_INTEN10_COMPARE0_Enabled (0x1UL)      /*!< Enable                                                               */
34113 
34114 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
34115   #define GRTC_INTEN10_COMPARE1_Pos (1UL)            /*!< Position of COMPARE1 field.                                          */
34116   #define GRTC_INTEN10_COMPARE1_Msk (0x1UL << GRTC_INTEN10_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
34117   #define GRTC_INTEN10_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
34118   #define GRTC_INTEN10_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
34119   #define GRTC_INTEN10_COMPARE1_Disabled (0x0UL)     /*!< Disable                                                              */
34120   #define GRTC_INTEN10_COMPARE1_Enabled (0x1UL)      /*!< Enable                                                               */
34121 
34122 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
34123   #define GRTC_INTEN10_COMPARE2_Pos (2UL)            /*!< Position of COMPARE2 field.                                          */
34124   #define GRTC_INTEN10_COMPARE2_Msk (0x1UL << GRTC_INTEN10_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
34125   #define GRTC_INTEN10_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
34126   #define GRTC_INTEN10_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
34127   #define GRTC_INTEN10_COMPARE2_Disabled (0x0UL)     /*!< Disable                                                              */
34128   #define GRTC_INTEN10_COMPARE2_Enabled (0x1UL)      /*!< Enable                                                               */
34129 
34130 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
34131   #define GRTC_INTEN10_COMPARE3_Pos (3UL)            /*!< Position of COMPARE3 field.                                          */
34132   #define GRTC_INTEN10_COMPARE3_Msk (0x1UL << GRTC_INTEN10_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
34133   #define GRTC_INTEN10_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
34134   #define GRTC_INTEN10_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
34135   #define GRTC_INTEN10_COMPARE3_Disabled (0x0UL)     /*!< Disable                                                              */
34136   #define GRTC_INTEN10_COMPARE3_Enabled (0x1UL)      /*!< Enable                                                               */
34137 
34138 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
34139   #define GRTC_INTEN10_COMPARE4_Pos (4UL)            /*!< Position of COMPARE4 field.                                          */
34140   #define GRTC_INTEN10_COMPARE4_Msk (0x1UL << GRTC_INTEN10_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
34141   #define GRTC_INTEN10_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
34142   #define GRTC_INTEN10_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
34143   #define GRTC_INTEN10_COMPARE4_Disabled (0x0UL)     /*!< Disable                                                              */
34144   #define GRTC_INTEN10_COMPARE4_Enabled (0x1UL)      /*!< Enable                                                               */
34145 
34146 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
34147   #define GRTC_INTEN10_COMPARE5_Pos (5UL)            /*!< Position of COMPARE5 field.                                          */
34148   #define GRTC_INTEN10_COMPARE5_Msk (0x1UL << GRTC_INTEN10_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
34149   #define GRTC_INTEN10_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
34150   #define GRTC_INTEN10_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
34151   #define GRTC_INTEN10_COMPARE5_Disabled (0x0UL)     /*!< Disable                                                              */
34152   #define GRTC_INTEN10_COMPARE5_Enabled (0x1UL)      /*!< Enable                                                               */
34153 
34154 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
34155   #define GRTC_INTEN10_COMPARE6_Pos (6UL)            /*!< Position of COMPARE6 field.                                          */
34156   #define GRTC_INTEN10_COMPARE6_Msk (0x1UL << GRTC_INTEN10_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
34157   #define GRTC_INTEN10_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
34158   #define GRTC_INTEN10_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
34159   #define GRTC_INTEN10_COMPARE6_Disabled (0x0UL)     /*!< Disable                                                              */
34160   #define GRTC_INTEN10_COMPARE6_Enabled (0x1UL)      /*!< Enable                                                               */
34161 
34162 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
34163   #define GRTC_INTEN10_COMPARE7_Pos (7UL)            /*!< Position of COMPARE7 field.                                          */
34164   #define GRTC_INTEN10_COMPARE7_Msk (0x1UL << GRTC_INTEN10_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
34165   #define GRTC_INTEN10_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
34166   #define GRTC_INTEN10_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
34167   #define GRTC_INTEN10_COMPARE7_Disabled (0x0UL)     /*!< Disable                                                              */
34168   #define GRTC_INTEN10_COMPARE7_Enabled (0x1UL)      /*!< Enable                                                               */
34169 
34170 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
34171   #define GRTC_INTEN10_COMPARE8_Pos (8UL)            /*!< Position of COMPARE8 field.                                          */
34172   #define GRTC_INTEN10_COMPARE8_Msk (0x1UL << GRTC_INTEN10_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                      */
34173   #define GRTC_INTEN10_COMPARE8_Min (0x0UL)          /*!< Min enumerator value of COMPARE8 field.                              */
34174   #define GRTC_INTEN10_COMPARE8_Max (0x1UL)          /*!< Max enumerator value of COMPARE8 field.                              */
34175   #define GRTC_INTEN10_COMPARE8_Disabled (0x0UL)     /*!< Disable                                                              */
34176   #define GRTC_INTEN10_COMPARE8_Enabled (0x1UL)      /*!< Enable                                                               */
34177 
34178 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
34179   #define GRTC_INTEN10_COMPARE9_Pos (9UL)            /*!< Position of COMPARE9 field.                                          */
34180   #define GRTC_INTEN10_COMPARE9_Msk (0x1UL << GRTC_INTEN10_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                      */
34181   #define GRTC_INTEN10_COMPARE9_Min (0x0UL)          /*!< Min enumerator value of COMPARE9 field.                              */
34182   #define GRTC_INTEN10_COMPARE9_Max (0x1UL)          /*!< Max enumerator value of COMPARE9 field.                              */
34183   #define GRTC_INTEN10_COMPARE9_Disabled (0x0UL)     /*!< Disable                                                              */
34184   #define GRTC_INTEN10_COMPARE9_Enabled (0x1UL)      /*!< Enable                                                               */
34185 
34186 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
34187   #define GRTC_INTEN10_COMPARE10_Pos (10UL)          /*!< Position of COMPARE10 field.                                         */
34188   #define GRTC_INTEN10_COMPARE10_Msk (0x1UL << GRTC_INTEN10_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                   */
34189   #define GRTC_INTEN10_COMPARE10_Min (0x0UL)         /*!< Min enumerator value of COMPARE10 field.                             */
34190   #define GRTC_INTEN10_COMPARE10_Max (0x1UL)         /*!< Max enumerator value of COMPARE10 field.                             */
34191   #define GRTC_INTEN10_COMPARE10_Disabled (0x0UL)    /*!< Disable                                                              */
34192   #define GRTC_INTEN10_COMPARE10_Enabled (0x1UL)     /*!< Enable                                                               */
34193 
34194 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
34195   #define GRTC_INTEN10_COMPARE11_Pos (11UL)          /*!< Position of COMPARE11 field.                                         */
34196   #define GRTC_INTEN10_COMPARE11_Msk (0x1UL << GRTC_INTEN10_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                   */
34197   #define GRTC_INTEN10_COMPARE11_Min (0x0UL)         /*!< Min enumerator value of COMPARE11 field.                             */
34198   #define GRTC_INTEN10_COMPARE11_Max (0x1UL)         /*!< Max enumerator value of COMPARE11 field.                             */
34199   #define GRTC_INTEN10_COMPARE11_Disabled (0x0UL)    /*!< Disable                                                              */
34200   #define GRTC_INTEN10_COMPARE11_Enabled (0x1UL)     /*!< Enable                                                               */
34201 
34202 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
34203   #define GRTC_INTEN10_COMPARE12_Pos (12UL)          /*!< Position of COMPARE12 field.                                         */
34204   #define GRTC_INTEN10_COMPARE12_Msk (0x1UL << GRTC_INTEN10_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                   */
34205   #define GRTC_INTEN10_COMPARE12_Min (0x0UL)         /*!< Min enumerator value of COMPARE12 field.                             */
34206   #define GRTC_INTEN10_COMPARE12_Max (0x1UL)         /*!< Max enumerator value of COMPARE12 field.                             */
34207   #define GRTC_INTEN10_COMPARE12_Disabled (0x0UL)    /*!< Disable                                                              */
34208   #define GRTC_INTEN10_COMPARE12_Enabled (0x1UL)     /*!< Enable                                                               */
34209 
34210 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
34211   #define GRTC_INTEN10_COMPARE13_Pos (13UL)          /*!< Position of COMPARE13 field.                                         */
34212   #define GRTC_INTEN10_COMPARE13_Msk (0x1UL << GRTC_INTEN10_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                   */
34213   #define GRTC_INTEN10_COMPARE13_Min (0x0UL)         /*!< Min enumerator value of COMPARE13 field.                             */
34214   #define GRTC_INTEN10_COMPARE13_Max (0x1UL)         /*!< Max enumerator value of COMPARE13 field.                             */
34215   #define GRTC_INTEN10_COMPARE13_Disabled (0x0UL)    /*!< Disable                                                              */
34216   #define GRTC_INTEN10_COMPARE13_Enabled (0x1UL)     /*!< Enable                                                               */
34217 
34218 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
34219   #define GRTC_INTEN10_COMPARE14_Pos (14UL)          /*!< Position of COMPARE14 field.                                         */
34220   #define GRTC_INTEN10_COMPARE14_Msk (0x1UL << GRTC_INTEN10_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                   */
34221   #define GRTC_INTEN10_COMPARE14_Min (0x0UL)         /*!< Min enumerator value of COMPARE14 field.                             */
34222   #define GRTC_INTEN10_COMPARE14_Max (0x1UL)         /*!< Max enumerator value of COMPARE14 field.                             */
34223   #define GRTC_INTEN10_COMPARE14_Disabled (0x0UL)    /*!< Disable                                                              */
34224   #define GRTC_INTEN10_COMPARE14_Enabled (0x1UL)     /*!< Enable                                                               */
34225 
34226 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
34227   #define GRTC_INTEN10_COMPARE15_Pos (15UL)          /*!< Position of COMPARE15 field.                                         */
34228   #define GRTC_INTEN10_COMPARE15_Msk (0x1UL << GRTC_INTEN10_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                   */
34229   #define GRTC_INTEN10_COMPARE15_Min (0x0UL)         /*!< Min enumerator value of COMPARE15 field.                             */
34230   #define GRTC_INTEN10_COMPARE15_Max (0x1UL)         /*!< Max enumerator value of COMPARE15 field.                             */
34231   #define GRTC_INTEN10_COMPARE15_Disabled (0x0UL)    /*!< Disable                                                              */
34232   #define GRTC_INTEN10_COMPARE15_Enabled (0x1UL)     /*!< Enable                                                               */
34233 
34234 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
34235   #define GRTC_INTEN10_SYSCOUNTERVALID_Pos (26UL)    /*!< Position of SYSCOUNTERVALID field.                                   */
34236   #define GRTC_INTEN10_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN10_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */
34237   #define GRTC_INTEN10_SYSCOUNTERVALID_Min (0x0UL)   /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
34238   #define GRTC_INTEN10_SYSCOUNTERVALID_Max (0x1UL)   /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
34239   #define GRTC_INTEN10_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                           */
34240   #define GRTC_INTEN10_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                             */
34241 
34242 
34243 /* GRTC_INTENSET10: Enable interrupt */
34244   #define GRTC_INTENSET10_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET10 register.                                  */
34245 
34246 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
34247   #define GRTC_INTENSET10_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
34248   #define GRTC_INTENSET10_COMPARE0_Msk (0x1UL << GRTC_INTENSET10_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
34249   #define GRTC_INTENSET10_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
34250   #define GRTC_INTENSET10_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
34251   #define GRTC_INTENSET10_COMPARE0_Set (0x1UL)       /*!< Enable                                                               */
34252   #define GRTC_INTENSET10_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34253   #define GRTC_INTENSET10_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34254 
34255 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
34256   #define GRTC_INTENSET10_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
34257   #define GRTC_INTENSET10_COMPARE1_Msk (0x1UL << GRTC_INTENSET10_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
34258   #define GRTC_INTENSET10_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
34259   #define GRTC_INTENSET10_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
34260   #define GRTC_INTENSET10_COMPARE1_Set (0x1UL)       /*!< Enable                                                               */
34261   #define GRTC_INTENSET10_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34262   #define GRTC_INTENSET10_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34263 
34264 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
34265   #define GRTC_INTENSET10_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
34266   #define GRTC_INTENSET10_COMPARE2_Msk (0x1UL << GRTC_INTENSET10_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
34267   #define GRTC_INTENSET10_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
34268   #define GRTC_INTENSET10_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
34269   #define GRTC_INTENSET10_COMPARE2_Set (0x1UL)       /*!< Enable                                                               */
34270   #define GRTC_INTENSET10_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34271   #define GRTC_INTENSET10_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34272 
34273 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
34274   #define GRTC_INTENSET10_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
34275   #define GRTC_INTENSET10_COMPARE3_Msk (0x1UL << GRTC_INTENSET10_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
34276   #define GRTC_INTENSET10_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
34277   #define GRTC_INTENSET10_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
34278   #define GRTC_INTENSET10_COMPARE3_Set (0x1UL)       /*!< Enable                                                               */
34279   #define GRTC_INTENSET10_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34280   #define GRTC_INTENSET10_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34281 
34282 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
34283   #define GRTC_INTENSET10_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
34284   #define GRTC_INTENSET10_COMPARE4_Msk (0x1UL << GRTC_INTENSET10_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
34285   #define GRTC_INTENSET10_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
34286   #define GRTC_INTENSET10_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
34287   #define GRTC_INTENSET10_COMPARE4_Set (0x1UL)       /*!< Enable                                                               */
34288   #define GRTC_INTENSET10_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34289   #define GRTC_INTENSET10_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34290 
34291 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
34292   #define GRTC_INTENSET10_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
34293   #define GRTC_INTENSET10_COMPARE5_Msk (0x1UL << GRTC_INTENSET10_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
34294   #define GRTC_INTENSET10_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
34295   #define GRTC_INTENSET10_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
34296   #define GRTC_INTENSET10_COMPARE5_Set (0x1UL)       /*!< Enable                                                               */
34297   #define GRTC_INTENSET10_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34298   #define GRTC_INTENSET10_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34299 
34300 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
34301   #define GRTC_INTENSET10_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
34302   #define GRTC_INTENSET10_COMPARE6_Msk (0x1UL << GRTC_INTENSET10_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
34303   #define GRTC_INTENSET10_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
34304   #define GRTC_INTENSET10_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
34305   #define GRTC_INTENSET10_COMPARE6_Set (0x1UL)       /*!< Enable                                                               */
34306   #define GRTC_INTENSET10_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34307   #define GRTC_INTENSET10_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34308 
34309 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
34310   #define GRTC_INTENSET10_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
34311   #define GRTC_INTENSET10_COMPARE7_Msk (0x1UL << GRTC_INTENSET10_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
34312   #define GRTC_INTENSET10_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
34313   #define GRTC_INTENSET10_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
34314   #define GRTC_INTENSET10_COMPARE7_Set (0x1UL)       /*!< Enable                                                               */
34315   #define GRTC_INTENSET10_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34316   #define GRTC_INTENSET10_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34317 
34318 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
34319   #define GRTC_INTENSET10_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
34320   #define GRTC_INTENSET10_COMPARE8_Msk (0x1UL << GRTC_INTENSET10_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
34321   #define GRTC_INTENSET10_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
34322   #define GRTC_INTENSET10_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
34323   #define GRTC_INTENSET10_COMPARE8_Set (0x1UL)       /*!< Enable                                                               */
34324   #define GRTC_INTENSET10_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34325   #define GRTC_INTENSET10_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34326 
34327 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
34328   #define GRTC_INTENSET10_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
34329   #define GRTC_INTENSET10_COMPARE9_Msk (0x1UL << GRTC_INTENSET10_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
34330   #define GRTC_INTENSET10_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
34331   #define GRTC_INTENSET10_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
34332   #define GRTC_INTENSET10_COMPARE9_Set (0x1UL)       /*!< Enable                                                               */
34333   #define GRTC_INTENSET10_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34334   #define GRTC_INTENSET10_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34335 
34336 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
34337   #define GRTC_INTENSET10_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
34338   #define GRTC_INTENSET10_COMPARE10_Msk (0x1UL << GRTC_INTENSET10_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
34339   #define GRTC_INTENSET10_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
34340   #define GRTC_INTENSET10_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
34341   #define GRTC_INTENSET10_COMPARE10_Set (0x1UL)      /*!< Enable                                                               */
34342   #define GRTC_INTENSET10_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34343   #define GRTC_INTENSET10_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34344 
34345 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
34346   #define GRTC_INTENSET10_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
34347   #define GRTC_INTENSET10_COMPARE11_Msk (0x1UL << GRTC_INTENSET10_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
34348   #define GRTC_INTENSET10_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
34349   #define GRTC_INTENSET10_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
34350   #define GRTC_INTENSET10_COMPARE11_Set (0x1UL)      /*!< Enable                                                               */
34351   #define GRTC_INTENSET10_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34352   #define GRTC_INTENSET10_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34353 
34354 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
34355   #define GRTC_INTENSET10_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
34356   #define GRTC_INTENSET10_COMPARE12_Msk (0x1UL << GRTC_INTENSET10_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
34357   #define GRTC_INTENSET10_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
34358   #define GRTC_INTENSET10_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
34359   #define GRTC_INTENSET10_COMPARE12_Set (0x1UL)      /*!< Enable                                                               */
34360   #define GRTC_INTENSET10_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34361   #define GRTC_INTENSET10_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34362 
34363 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
34364   #define GRTC_INTENSET10_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
34365   #define GRTC_INTENSET10_COMPARE13_Msk (0x1UL << GRTC_INTENSET10_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
34366   #define GRTC_INTENSET10_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
34367   #define GRTC_INTENSET10_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
34368   #define GRTC_INTENSET10_COMPARE13_Set (0x1UL)      /*!< Enable                                                               */
34369   #define GRTC_INTENSET10_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34370   #define GRTC_INTENSET10_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34371 
34372 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
34373   #define GRTC_INTENSET10_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
34374   #define GRTC_INTENSET10_COMPARE14_Msk (0x1UL << GRTC_INTENSET10_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
34375   #define GRTC_INTENSET10_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
34376   #define GRTC_INTENSET10_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
34377   #define GRTC_INTENSET10_COMPARE14_Set (0x1UL)      /*!< Enable                                                               */
34378   #define GRTC_INTENSET10_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34379   #define GRTC_INTENSET10_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34380 
34381 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
34382   #define GRTC_INTENSET10_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
34383   #define GRTC_INTENSET10_COMPARE15_Msk (0x1UL << GRTC_INTENSET10_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
34384   #define GRTC_INTENSET10_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
34385   #define GRTC_INTENSET10_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
34386   #define GRTC_INTENSET10_COMPARE15_Set (0x1UL)      /*!< Enable                                                               */
34387   #define GRTC_INTENSET10_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34388   #define GRTC_INTENSET10_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34389 
34390 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
34391   #define GRTC_INTENSET10_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
34392   #define GRTC_INTENSET10_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET10_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
34393                                                                             field.*/
34394   #define GRTC_INTENSET10_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
34395   #define GRTC_INTENSET10_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
34396   #define GRTC_INTENSET10_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                              */
34397   #define GRTC_INTENSET10_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
34398   #define GRTC_INTENSET10_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
34399 
34400 
34401 /* GRTC_INTENCLR10: Disable interrupt */
34402   #define GRTC_INTENCLR10_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR10 register.                                  */
34403 
34404 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
34405   #define GRTC_INTENCLR10_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
34406   #define GRTC_INTENCLR10_COMPARE0_Msk (0x1UL << GRTC_INTENCLR10_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
34407   #define GRTC_INTENCLR10_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
34408   #define GRTC_INTENCLR10_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
34409   #define GRTC_INTENCLR10_COMPARE0_Clear (0x1UL)     /*!< Disable                                                              */
34410   #define GRTC_INTENCLR10_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34411   #define GRTC_INTENCLR10_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34412 
34413 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
34414   #define GRTC_INTENCLR10_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
34415   #define GRTC_INTENCLR10_COMPARE1_Msk (0x1UL << GRTC_INTENCLR10_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
34416   #define GRTC_INTENCLR10_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
34417   #define GRTC_INTENCLR10_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
34418   #define GRTC_INTENCLR10_COMPARE1_Clear (0x1UL)     /*!< Disable                                                              */
34419   #define GRTC_INTENCLR10_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34420   #define GRTC_INTENCLR10_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34421 
34422 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
34423   #define GRTC_INTENCLR10_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
34424   #define GRTC_INTENCLR10_COMPARE2_Msk (0x1UL << GRTC_INTENCLR10_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
34425   #define GRTC_INTENCLR10_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
34426   #define GRTC_INTENCLR10_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
34427   #define GRTC_INTENCLR10_COMPARE2_Clear (0x1UL)     /*!< Disable                                                              */
34428   #define GRTC_INTENCLR10_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34429   #define GRTC_INTENCLR10_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34430 
34431 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
34432   #define GRTC_INTENCLR10_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
34433   #define GRTC_INTENCLR10_COMPARE3_Msk (0x1UL << GRTC_INTENCLR10_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
34434   #define GRTC_INTENCLR10_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
34435   #define GRTC_INTENCLR10_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
34436   #define GRTC_INTENCLR10_COMPARE3_Clear (0x1UL)     /*!< Disable                                                              */
34437   #define GRTC_INTENCLR10_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34438   #define GRTC_INTENCLR10_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34439 
34440 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
34441   #define GRTC_INTENCLR10_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
34442   #define GRTC_INTENCLR10_COMPARE4_Msk (0x1UL << GRTC_INTENCLR10_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
34443   #define GRTC_INTENCLR10_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
34444   #define GRTC_INTENCLR10_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
34445   #define GRTC_INTENCLR10_COMPARE4_Clear (0x1UL)     /*!< Disable                                                              */
34446   #define GRTC_INTENCLR10_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34447   #define GRTC_INTENCLR10_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34448 
34449 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
34450   #define GRTC_INTENCLR10_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
34451   #define GRTC_INTENCLR10_COMPARE5_Msk (0x1UL << GRTC_INTENCLR10_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
34452   #define GRTC_INTENCLR10_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
34453   #define GRTC_INTENCLR10_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
34454   #define GRTC_INTENCLR10_COMPARE5_Clear (0x1UL)     /*!< Disable                                                              */
34455   #define GRTC_INTENCLR10_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34456   #define GRTC_INTENCLR10_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34457 
34458 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
34459   #define GRTC_INTENCLR10_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
34460   #define GRTC_INTENCLR10_COMPARE6_Msk (0x1UL << GRTC_INTENCLR10_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
34461   #define GRTC_INTENCLR10_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
34462   #define GRTC_INTENCLR10_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
34463   #define GRTC_INTENCLR10_COMPARE6_Clear (0x1UL)     /*!< Disable                                                              */
34464   #define GRTC_INTENCLR10_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34465   #define GRTC_INTENCLR10_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34466 
34467 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
34468   #define GRTC_INTENCLR10_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
34469   #define GRTC_INTENCLR10_COMPARE7_Msk (0x1UL << GRTC_INTENCLR10_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
34470   #define GRTC_INTENCLR10_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
34471   #define GRTC_INTENCLR10_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
34472   #define GRTC_INTENCLR10_COMPARE7_Clear (0x1UL)     /*!< Disable                                                              */
34473   #define GRTC_INTENCLR10_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34474   #define GRTC_INTENCLR10_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34475 
34476 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
34477   #define GRTC_INTENCLR10_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
34478   #define GRTC_INTENCLR10_COMPARE8_Msk (0x1UL << GRTC_INTENCLR10_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
34479   #define GRTC_INTENCLR10_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
34480   #define GRTC_INTENCLR10_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
34481   #define GRTC_INTENCLR10_COMPARE8_Clear (0x1UL)     /*!< Disable                                                              */
34482   #define GRTC_INTENCLR10_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34483   #define GRTC_INTENCLR10_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34484 
34485 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
34486   #define GRTC_INTENCLR10_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
34487   #define GRTC_INTENCLR10_COMPARE9_Msk (0x1UL << GRTC_INTENCLR10_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
34488   #define GRTC_INTENCLR10_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
34489   #define GRTC_INTENCLR10_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
34490   #define GRTC_INTENCLR10_COMPARE9_Clear (0x1UL)     /*!< Disable                                                              */
34491   #define GRTC_INTENCLR10_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34492   #define GRTC_INTENCLR10_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34493 
34494 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
34495   #define GRTC_INTENCLR10_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
34496   #define GRTC_INTENCLR10_COMPARE10_Msk (0x1UL << GRTC_INTENCLR10_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
34497   #define GRTC_INTENCLR10_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
34498   #define GRTC_INTENCLR10_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
34499   #define GRTC_INTENCLR10_COMPARE10_Clear (0x1UL)    /*!< Disable                                                              */
34500   #define GRTC_INTENCLR10_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34501   #define GRTC_INTENCLR10_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34502 
34503 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
34504   #define GRTC_INTENCLR10_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
34505   #define GRTC_INTENCLR10_COMPARE11_Msk (0x1UL << GRTC_INTENCLR10_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
34506   #define GRTC_INTENCLR10_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
34507   #define GRTC_INTENCLR10_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
34508   #define GRTC_INTENCLR10_COMPARE11_Clear (0x1UL)    /*!< Disable                                                              */
34509   #define GRTC_INTENCLR10_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34510   #define GRTC_INTENCLR10_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34511 
34512 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
34513   #define GRTC_INTENCLR10_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
34514   #define GRTC_INTENCLR10_COMPARE12_Msk (0x1UL << GRTC_INTENCLR10_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
34515   #define GRTC_INTENCLR10_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
34516   #define GRTC_INTENCLR10_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
34517   #define GRTC_INTENCLR10_COMPARE12_Clear (0x1UL)    /*!< Disable                                                              */
34518   #define GRTC_INTENCLR10_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34519   #define GRTC_INTENCLR10_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34520 
34521 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
34522   #define GRTC_INTENCLR10_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
34523   #define GRTC_INTENCLR10_COMPARE13_Msk (0x1UL << GRTC_INTENCLR10_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
34524   #define GRTC_INTENCLR10_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
34525   #define GRTC_INTENCLR10_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
34526   #define GRTC_INTENCLR10_COMPARE13_Clear (0x1UL)    /*!< Disable                                                              */
34527   #define GRTC_INTENCLR10_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34528   #define GRTC_INTENCLR10_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34529 
34530 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
34531   #define GRTC_INTENCLR10_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
34532   #define GRTC_INTENCLR10_COMPARE14_Msk (0x1UL << GRTC_INTENCLR10_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
34533   #define GRTC_INTENCLR10_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
34534   #define GRTC_INTENCLR10_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
34535   #define GRTC_INTENCLR10_COMPARE14_Clear (0x1UL)    /*!< Disable                                                              */
34536   #define GRTC_INTENCLR10_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34537   #define GRTC_INTENCLR10_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34538 
34539 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
34540   #define GRTC_INTENCLR10_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
34541   #define GRTC_INTENCLR10_COMPARE15_Msk (0x1UL << GRTC_INTENCLR10_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
34542   #define GRTC_INTENCLR10_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
34543   #define GRTC_INTENCLR10_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
34544   #define GRTC_INTENCLR10_COMPARE15_Clear (0x1UL)    /*!< Disable                                                              */
34545   #define GRTC_INTENCLR10_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34546   #define GRTC_INTENCLR10_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34547 
34548 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
34549   #define GRTC_INTENCLR10_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
34550   #define GRTC_INTENCLR10_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR10_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
34551                                                                             field.*/
34552   #define GRTC_INTENCLR10_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
34553   #define GRTC_INTENCLR10_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
34554   #define GRTC_INTENCLR10_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                           */
34555   #define GRTC_INTENCLR10_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
34556   #define GRTC_INTENCLR10_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
34557 
34558 
34559 /* GRTC_INTPEND10: Pending interrupts */
34560   #define GRTC_INTPEND10_ResetValue (0x00000000UL)   /*!< Reset value of INTPEND10 register.                                   */
34561 
34562 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
34563   #define GRTC_INTPEND10_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
34564   #define GRTC_INTPEND10_COMPARE0_Msk (0x1UL << GRTC_INTPEND10_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
34565   #define GRTC_INTPEND10_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
34566   #define GRTC_INTPEND10_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
34567   #define GRTC_INTPEND10_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34568   #define GRTC_INTPEND10_COMPARE0_Pending (0x1UL)    /*!< Read: Pending                                                        */
34569 
34570 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
34571   #define GRTC_INTPEND10_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
34572   #define GRTC_INTPEND10_COMPARE1_Msk (0x1UL << GRTC_INTPEND10_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
34573   #define GRTC_INTPEND10_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
34574   #define GRTC_INTPEND10_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
34575   #define GRTC_INTPEND10_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34576   #define GRTC_INTPEND10_COMPARE1_Pending (0x1UL)    /*!< Read: Pending                                                        */
34577 
34578 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
34579   #define GRTC_INTPEND10_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
34580   #define GRTC_INTPEND10_COMPARE2_Msk (0x1UL << GRTC_INTPEND10_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
34581   #define GRTC_INTPEND10_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
34582   #define GRTC_INTPEND10_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
34583   #define GRTC_INTPEND10_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34584   #define GRTC_INTPEND10_COMPARE2_Pending (0x1UL)    /*!< Read: Pending                                                        */
34585 
34586 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
34587   #define GRTC_INTPEND10_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
34588   #define GRTC_INTPEND10_COMPARE3_Msk (0x1UL << GRTC_INTPEND10_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
34589   #define GRTC_INTPEND10_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
34590   #define GRTC_INTPEND10_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
34591   #define GRTC_INTPEND10_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34592   #define GRTC_INTPEND10_COMPARE3_Pending (0x1UL)    /*!< Read: Pending                                                        */
34593 
34594 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
34595   #define GRTC_INTPEND10_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
34596   #define GRTC_INTPEND10_COMPARE4_Msk (0x1UL << GRTC_INTPEND10_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
34597   #define GRTC_INTPEND10_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
34598   #define GRTC_INTPEND10_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
34599   #define GRTC_INTPEND10_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34600   #define GRTC_INTPEND10_COMPARE4_Pending (0x1UL)    /*!< Read: Pending                                                        */
34601 
34602 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
34603   #define GRTC_INTPEND10_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
34604   #define GRTC_INTPEND10_COMPARE5_Msk (0x1UL << GRTC_INTPEND10_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
34605   #define GRTC_INTPEND10_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
34606   #define GRTC_INTPEND10_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
34607   #define GRTC_INTPEND10_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34608   #define GRTC_INTPEND10_COMPARE5_Pending (0x1UL)    /*!< Read: Pending                                                        */
34609 
34610 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
34611   #define GRTC_INTPEND10_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
34612   #define GRTC_INTPEND10_COMPARE6_Msk (0x1UL << GRTC_INTPEND10_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
34613   #define GRTC_INTPEND10_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
34614   #define GRTC_INTPEND10_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
34615   #define GRTC_INTPEND10_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34616   #define GRTC_INTPEND10_COMPARE6_Pending (0x1UL)    /*!< Read: Pending                                                        */
34617 
34618 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
34619   #define GRTC_INTPEND10_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
34620   #define GRTC_INTPEND10_COMPARE7_Msk (0x1UL << GRTC_INTPEND10_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
34621   #define GRTC_INTPEND10_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
34622   #define GRTC_INTPEND10_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
34623   #define GRTC_INTPEND10_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34624   #define GRTC_INTPEND10_COMPARE7_Pending (0x1UL)    /*!< Read: Pending                                                        */
34625 
34626 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
34627   #define GRTC_INTPEND10_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
34628   #define GRTC_INTPEND10_COMPARE8_Msk (0x1UL << GRTC_INTPEND10_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
34629   #define GRTC_INTPEND10_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
34630   #define GRTC_INTPEND10_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
34631   #define GRTC_INTPEND10_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34632   #define GRTC_INTPEND10_COMPARE8_Pending (0x1UL)    /*!< Read: Pending                                                        */
34633 
34634 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
34635   #define GRTC_INTPEND10_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
34636   #define GRTC_INTPEND10_COMPARE9_Msk (0x1UL << GRTC_INTPEND10_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
34637   #define GRTC_INTPEND10_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
34638   #define GRTC_INTPEND10_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
34639   #define GRTC_INTPEND10_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending                                                    */
34640   #define GRTC_INTPEND10_COMPARE9_Pending (0x1UL)    /*!< Read: Pending                                                        */
34641 
34642 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
34643   #define GRTC_INTPEND10_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
34644   #define GRTC_INTPEND10_COMPARE10_Msk (0x1UL << GRTC_INTPEND10_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
34645   #define GRTC_INTPEND10_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
34646   #define GRTC_INTPEND10_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
34647   #define GRTC_INTPEND10_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                   */
34648   #define GRTC_INTPEND10_COMPARE10_Pending (0x1UL)   /*!< Read: Pending                                                        */
34649 
34650 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
34651   #define GRTC_INTPEND10_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
34652   #define GRTC_INTPEND10_COMPARE11_Msk (0x1UL << GRTC_INTPEND10_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
34653   #define GRTC_INTPEND10_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
34654   #define GRTC_INTPEND10_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
34655   #define GRTC_INTPEND10_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                   */
34656   #define GRTC_INTPEND10_COMPARE11_Pending (0x1UL)   /*!< Read: Pending                                                        */
34657 
34658 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
34659   #define GRTC_INTPEND10_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
34660   #define GRTC_INTPEND10_COMPARE12_Msk (0x1UL << GRTC_INTPEND10_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
34661   #define GRTC_INTPEND10_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
34662   #define GRTC_INTPEND10_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
34663   #define GRTC_INTPEND10_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                   */
34664   #define GRTC_INTPEND10_COMPARE12_Pending (0x1UL)   /*!< Read: Pending                                                        */
34665 
34666 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
34667   #define GRTC_INTPEND10_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
34668   #define GRTC_INTPEND10_COMPARE13_Msk (0x1UL << GRTC_INTPEND10_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
34669   #define GRTC_INTPEND10_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
34670   #define GRTC_INTPEND10_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
34671   #define GRTC_INTPEND10_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                   */
34672   #define GRTC_INTPEND10_COMPARE13_Pending (0x1UL)   /*!< Read: Pending                                                        */
34673 
34674 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
34675   #define GRTC_INTPEND10_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
34676   #define GRTC_INTPEND10_COMPARE14_Msk (0x1UL << GRTC_INTPEND10_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
34677   #define GRTC_INTPEND10_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
34678   #define GRTC_INTPEND10_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
34679   #define GRTC_INTPEND10_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                   */
34680   #define GRTC_INTPEND10_COMPARE14_Pending (0x1UL)   /*!< Read: Pending                                                        */
34681 
34682 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
34683   #define GRTC_INTPEND10_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
34684   #define GRTC_INTPEND10_COMPARE15_Msk (0x1UL << GRTC_INTPEND10_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
34685   #define GRTC_INTPEND10_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
34686   #define GRTC_INTPEND10_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
34687   #define GRTC_INTPEND10_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                   */
34688   #define GRTC_INTPEND10_COMPARE15_Pending (0x1UL)   /*!< Read: Pending                                                        */
34689 
34690 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
34691   #define GRTC_INTPEND10_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
34692   #define GRTC_INTPEND10_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND10_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
34693                                                                             field.*/
34694   #define GRTC_INTPEND10_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
34695   #define GRTC_INTPEND10_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
34696   #define GRTC_INTPEND10_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                             */
34697   #define GRTC_INTPEND10_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                    */
34698 
34699 
34700 /* GRTC_INTEN11: Enable or disable interrupt */
34701   #define GRTC_INTEN11_ResetValue (0x00000000UL)     /*!< Reset value of INTEN11 register.                                     */
34702 
34703 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
34704   #define GRTC_INTEN11_COMPARE0_Pos (0UL)            /*!< Position of COMPARE0 field.                                          */
34705   #define GRTC_INTEN11_COMPARE0_Msk (0x1UL << GRTC_INTEN11_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
34706   #define GRTC_INTEN11_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
34707   #define GRTC_INTEN11_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
34708   #define GRTC_INTEN11_COMPARE0_Disabled (0x0UL)     /*!< Disable                                                              */
34709   #define GRTC_INTEN11_COMPARE0_Enabled (0x1UL)      /*!< Enable                                                               */
34710 
34711 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
34712   #define GRTC_INTEN11_COMPARE1_Pos (1UL)            /*!< Position of COMPARE1 field.                                          */
34713   #define GRTC_INTEN11_COMPARE1_Msk (0x1UL << GRTC_INTEN11_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
34714   #define GRTC_INTEN11_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
34715   #define GRTC_INTEN11_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
34716   #define GRTC_INTEN11_COMPARE1_Disabled (0x0UL)     /*!< Disable                                                              */
34717   #define GRTC_INTEN11_COMPARE1_Enabled (0x1UL)      /*!< Enable                                                               */
34718 
34719 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
34720   #define GRTC_INTEN11_COMPARE2_Pos (2UL)            /*!< Position of COMPARE2 field.                                          */
34721   #define GRTC_INTEN11_COMPARE2_Msk (0x1UL << GRTC_INTEN11_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
34722   #define GRTC_INTEN11_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
34723   #define GRTC_INTEN11_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
34724   #define GRTC_INTEN11_COMPARE2_Disabled (0x0UL)     /*!< Disable                                                              */
34725   #define GRTC_INTEN11_COMPARE2_Enabled (0x1UL)      /*!< Enable                                                               */
34726 
34727 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
34728   #define GRTC_INTEN11_COMPARE3_Pos (3UL)            /*!< Position of COMPARE3 field.                                          */
34729   #define GRTC_INTEN11_COMPARE3_Msk (0x1UL << GRTC_INTEN11_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
34730   #define GRTC_INTEN11_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
34731   #define GRTC_INTEN11_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
34732   #define GRTC_INTEN11_COMPARE3_Disabled (0x0UL)     /*!< Disable                                                              */
34733   #define GRTC_INTEN11_COMPARE3_Enabled (0x1UL)      /*!< Enable                                                               */
34734 
34735 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
34736   #define GRTC_INTEN11_COMPARE4_Pos (4UL)            /*!< Position of COMPARE4 field.                                          */
34737   #define GRTC_INTEN11_COMPARE4_Msk (0x1UL << GRTC_INTEN11_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
34738   #define GRTC_INTEN11_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
34739   #define GRTC_INTEN11_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
34740   #define GRTC_INTEN11_COMPARE4_Disabled (0x0UL)     /*!< Disable                                                              */
34741   #define GRTC_INTEN11_COMPARE4_Enabled (0x1UL)      /*!< Enable                                                               */
34742 
34743 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
34744   #define GRTC_INTEN11_COMPARE5_Pos (5UL)            /*!< Position of COMPARE5 field.                                          */
34745   #define GRTC_INTEN11_COMPARE5_Msk (0x1UL << GRTC_INTEN11_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
34746   #define GRTC_INTEN11_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
34747   #define GRTC_INTEN11_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
34748   #define GRTC_INTEN11_COMPARE5_Disabled (0x0UL)     /*!< Disable                                                              */
34749   #define GRTC_INTEN11_COMPARE5_Enabled (0x1UL)      /*!< Enable                                                               */
34750 
34751 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
34752   #define GRTC_INTEN11_COMPARE6_Pos (6UL)            /*!< Position of COMPARE6 field.                                          */
34753   #define GRTC_INTEN11_COMPARE6_Msk (0x1UL << GRTC_INTEN11_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
34754   #define GRTC_INTEN11_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
34755   #define GRTC_INTEN11_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
34756   #define GRTC_INTEN11_COMPARE6_Disabled (0x0UL)     /*!< Disable                                                              */
34757   #define GRTC_INTEN11_COMPARE6_Enabled (0x1UL)      /*!< Enable                                                               */
34758 
34759 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
34760   #define GRTC_INTEN11_COMPARE7_Pos (7UL)            /*!< Position of COMPARE7 field.                                          */
34761   #define GRTC_INTEN11_COMPARE7_Msk (0x1UL << GRTC_INTEN11_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
34762   #define GRTC_INTEN11_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
34763   #define GRTC_INTEN11_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
34764   #define GRTC_INTEN11_COMPARE7_Disabled (0x0UL)     /*!< Disable                                                              */
34765   #define GRTC_INTEN11_COMPARE7_Enabled (0x1UL)      /*!< Enable                                                               */
34766 
34767 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
34768   #define GRTC_INTEN11_COMPARE8_Pos (8UL)            /*!< Position of COMPARE8 field.                                          */
34769   #define GRTC_INTEN11_COMPARE8_Msk (0x1UL << GRTC_INTEN11_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                      */
34770   #define GRTC_INTEN11_COMPARE8_Min (0x0UL)          /*!< Min enumerator value of COMPARE8 field.                              */
34771   #define GRTC_INTEN11_COMPARE8_Max (0x1UL)          /*!< Max enumerator value of COMPARE8 field.                              */
34772   #define GRTC_INTEN11_COMPARE8_Disabled (0x0UL)     /*!< Disable                                                              */
34773   #define GRTC_INTEN11_COMPARE8_Enabled (0x1UL)      /*!< Enable                                                               */
34774 
34775 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
34776   #define GRTC_INTEN11_COMPARE9_Pos (9UL)            /*!< Position of COMPARE9 field.                                          */
34777   #define GRTC_INTEN11_COMPARE9_Msk (0x1UL << GRTC_INTEN11_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                      */
34778   #define GRTC_INTEN11_COMPARE9_Min (0x0UL)          /*!< Min enumerator value of COMPARE9 field.                              */
34779   #define GRTC_INTEN11_COMPARE9_Max (0x1UL)          /*!< Max enumerator value of COMPARE9 field.                              */
34780   #define GRTC_INTEN11_COMPARE9_Disabled (0x0UL)     /*!< Disable                                                              */
34781   #define GRTC_INTEN11_COMPARE9_Enabled (0x1UL)      /*!< Enable                                                               */
34782 
34783 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
34784   #define GRTC_INTEN11_COMPARE10_Pos (10UL)          /*!< Position of COMPARE10 field.                                         */
34785   #define GRTC_INTEN11_COMPARE10_Msk (0x1UL << GRTC_INTEN11_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                   */
34786   #define GRTC_INTEN11_COMPARE10_Min (0x0UL)         /*!< Min enumerator value of COMPARE10 field.                             */
34787   #define GRTC_INTEN11_COMPARE10_Max (0x1UL)         /*!< Max enumerator value of COMPARE10 field.                             */
34788   #define GRTC_INTEN11_COMPARE10_Disabled (0x0UL)    /*!< Disable                                                              */
34789   #define GRTC_INTEN11_COMPARE10_Enabled (0x1UL)     /*!< Enable                                                               */
34790 
34791 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
34792   #define GRTC_INTEN11_COMPARE11_Pos (11UL)          /*!< Position of COMPARE11 field.                                         */
34793   #define GRTC_INTEN11_COMPARE11_Msk (0x1UL << GRTC_INTEN11_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                   */
34794   #define GRTC_INTEN11_COMPARE11_Min (0x0UL)         /*!< Min enumerator value of COMPARE11 field.                             */
34795   #define GRTC_INTEN11_COMPARE11_Max (0x1UL)         /*!< Max enumerator value of COMPARE11 field.                             */
34796   #define GRTC_INTEN11_COMPARE11_Disabled (0x0UL)    /*!< Disable                                                              */
34797   #define GRTC_INTEN11_COMPARE11_Enabled (0x1UL)     /*!< Enable                                                               */
34798 
34799 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
34800   #define GRTC_INTEN11_COMPARE12_Pos (12UL)          /*!< Position of COMPARE12 field.                                         */
34801   #define GRTC_INTEN11_COMPARE12_Msk (0x1UL << GRTC_INTEN11_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                   */
34802   #define GRTC_INTEN11_COMPARE12_Min (0x0UL)         /*!< Min enumerator value of COMPARE12 field.                             */
34803   #define GRTC_INTEN11_COMPARE12_Max (0x1UL)         /*!< Max enumerator value of COMPARE12 field.                             */
34804   #define GRTC_INTEN11_COMPARE12_Disabled (0x0UL)    /*!< Disable                                                              */
34805   #define GRTC_INTEN11_COMPARE12_Enabled (0x1UL)     /*!< Enable                                                               */
34806 
34807 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
34808   #define GRTC_INTEN11_COMPARE13_Pos (13UL)          /*!< Position of COMPARE13 field.                                         */
34809   #define GRTC_INTEN11_COMPARE13_Msk (0x1UL << GRTC_INTEN11_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                   */
34810   #define GRTC_INTEN11_COMPARE13_Min (0x0UL)         /*!< Min enumerator value of COMPARE13 field.                             */
34811   #define GRTC_INTEN11_COMPARE13_Max (0x1UL)         /*!< Max enumerator value of COMPARE13 field.                             */
34812   #define GRTC_INTEN11_COMPARE13_Disabled (0x0UL)    /*!< Disable                                                              */
34813   #define GRTC_INTEN11_COMPARE13_Enabled (0x1UL)     /*!< Enable                                                               */
34814 
34815 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
34816   #define GRTC_INTEN11_COMPARE14_Pos (14UL)          /*!< Position of COMPARE14 field.                                         */
34817   #define GRTC_INTEN11_COMPARE14_Msk (0x1UL << GRTC_INTEN11_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                   */
34818   #define GRTC_INTEN11_COMPARE14_Min (0x0UL)         /*!< Min enumerator value of COMPARE14 field.                             */
34819   #define GRTC_INTEN11_COMPARE14_Max (0x1UL)         /*!< Max enumerator value of COMPARE14 field.                             */
34820   #define GRTC_INTEN11_COMPARE14_Disabled (0x0UL)    /*!< Disable                                                              */
34821   #define GRTC_INTEN11_COMPARE14_Enabled (0x1UL)     /*!< Enable                                                               */
34822 
34823 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
34824   #define GRTC_INTEN11_COMPARE15_Pos (15UL)          /*!< Position of COMPARE15 field.                                         */
34825   #define GRTC_INTEN11_COMPARE15_Msk (0x1UL << GRTC_INTEN11_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                   */
34826   #define GRTC_INTEN11_COMPARE15_Min (0x0UL)         /*!< Min enumerator value of COMPARE15 field.                             */
34827   #define GRTC_INTEN11_COMPARE15_Max (0x1UL)         /*!< Max enumerator value of COMPARE15 field.                             */
34828   #define GRTC_INTEN11_COMPARE15_Disabled (0x0UL)    /*!< Disable                                                              */
34829   #define GRTC_INTEN11_COMPARE15_Enabled (0x1UL)     /*!< Enable                                                               */
34830 
34831 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
34832   #define GRTC_INTEN11_SYSCOUNTERVALID_Pos (26UL)    /*!< Position of SYSCOUNTERVALID field.                                   */
34833   #define GRTC_INTEN11_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN11_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */
34834   #define GRTC_INTEN11_SYSCOUNTERVALID_Min (0x0UL)   /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
34835   #define GRTC_INTEN11_SYSCOUNTERVALID_Max (0x1UL)   /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
34836   #define GRTC_INTEN11_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                           */
34837   #define GRTC_INTEN11_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                             */
34838 
34839 
34840 /* GRTC_INTENSET11: Enable interrupt */
34841   #define GRTC_INTENSET11_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET11 register.                                  */
34842 
34843 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
34844   #define GRTC_INTENSET11_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
34845   #define GRTC_INTENSET11_COMPARE0_Msk (0x1UL << GRTC_INTENSET11_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
34846   #define GRTC_INTENSET11_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
34847   #define GRTC_INTENSET11_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
34848   #define GRTC_INTENSET11_COMPARE0_Set (0x1UL)       /*!< Enable                                                               */
34849   #define GRTC_INTENSET11_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34850   #define GRTC_INTENSET11_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34851 
34852 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
34853   #define GRTC_INTENSET11_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
34854   #define GRTC_INTENSET11_COMPARE1_Msk (0x1UL << GRTC_INTENSET11_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
34855   #define GRTC_INTENSET11_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
34856   #define GRTC_INTENSET11_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
34857   #define GRTC_INTENSET11_COMPARE1_Set (0x1UL)       /*!< Enable                                                               */
34858   #define GRTC_INTENSET11_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34859   #define GRTC_INTENSET11_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34860 
34861 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
34862   #define GRTC_INTENSET11_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
34863   #define GRTC_INTENSET11_COMPARE2_Msk (0x1UL << GRTC_INTENSET11_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
34864   #define GRTC_INTENSET11_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
34865   #define GRTC_INTENSET11_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
34866   #define GRTC_INTENSET11_COMPARE2_Set (0x1UL)       /*!< Enable                                                               */
34867   #define GRTC_INTENSET11_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34868   #define GRTC_INTENSET11_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34869 
34870 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
34871   #define GRTC_INTENSET11_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
34872   #define GRTC_INTENSET11_COMPARE3_Msk (0x1UL << GRTC_INTENSET11_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
34873   #define GRTC_INTENSET11_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
34874   #define GRTC_INTENSET11_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
34875   #define GRTC_INTENSET11_COMPARE3_Set (0x1UL)       /*!< Enable                                                               */
34876   #define GRTC_INTENSET11_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34877   #define GRTC_INTENSET11_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34878 
34879 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
34880   #define GRTC_INTENSET11_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
34881   #define GRTC_INTENSET11_COMPARE4_Msk (0x1UL << GRTC_INTENSET11_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
34882   #define GRTC_INTENSET11_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
34883   #define GRTC_INTENSET11_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
34884   #define GRTC_INTENSET11_COMPARE4_Set (0x1UL)       /*!< Enable                                                               */
34885   #define GRTC_INTENSET11_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34886   #define GRTC_INTENSET11_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34887 
34888 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
34889   #define GRTC_INTENSET11_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
34890   #define GRTC_INTENSET11_COMPARE5_Msk (0x1UL << GRTC_INTENSET11_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
34891   #define GRTC_INTENSET11_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
34892   #define GRTC_INTENSET11_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
34893   #define GRTC_INTENSET11_COMPARE5_Set (0x1UL)       /*!< Enable                                                               */
34894   #define GRTC_INTENSET11_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34895   #define GRTC_INTENSET11_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34896 
34897 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
34898   #define GRTC_INTENSET11_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
34899   #define GRTC_INTENSET11_COMPARE6_Msk (0x1UL << GRTC_INTENSET11_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
34900   #define GRTC_INTENSET11_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
34901   #define GRTC_INTENSET11_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
34902   #define GRTC_INTENSET11_COMPARE6_Set (0x1UL)       /*!< Enable                                                               */
34903   #define GRTC_INTENSET11_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34904   #define GRTC_INTENSET11_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34905 
34906 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
34907   #define GRTC_INTENSET11_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
34908   #define GRTC_INTENSET11_COMPARE7_Msk (0x1UL << GRTC_INTENSET11_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
34909   #define GRTC_INTENSET11_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
34910   #define GRTC_INTENSET11_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
34911   #define GRTC_INTENSET11_COMPARE7_Set (0x1UL)       /*!< Enable                                                               */
34912   #define GRTC_INTENSET11_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34913   #define GRTC_INTENSET11_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34914 
34915 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
34916   #define GRTC_INTENSET11_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
34917   #define GRTC_INTENSET11_COMPARE8_Msk (0x1UL << GRTC_INTENSET11_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
34918   #define GRTC_INTENSET11_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
34919   #define GRTC_INTENSET11_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
34920   #define GRTC_INTENSET11_COMPARE8_Set (0x1UL)       /*!< Enable                                                               */
34921   #define GRTC_INTENSET11_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34922   #define GRTC_INTENSET11_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34923 
34924 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
34925   #define GRTC_INTENSET11_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
34926   #define GRTC_INTENSET11_COMPARE9_Msk (0x1UL << GRTC_INTENSET11_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
34927   #define GRTC_INTENSET11_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
34928   #define GRTC_INTENSET11_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
34929   #define GRTC_INTENSET11_COMPARE9_Set (0x1UL)       /*!< Enable                                                               */
34930   #define GRTC_INTENSET11_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
34931   #define GRTC_INTENSET11_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
34932 
34933 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
34934   #define GRTC_INTENSET11_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
34935   #define GRTC_INTENSET11_COMPARE10_Msk (0x1UL << GRTC_INTENSET11_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
34936   #define GRTC_INTENSET11_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
34937   #define GRTC_INTENSET11_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
34938   #define GRTC_INTENSET11_COMPARE10_Set (0x1UL)      /*!< Enable                                                               */
34939   #define GRTC_INTENSET11_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34940   #define GRTC_INTENSET11_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34941 
34942 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
34943   #define GRTC_INTENSET11_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
34944   #define GRTC_INTENSET11_COMPARE11_Msk (0x1UL << GRTC_INTENSET11_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
34945   #define GRTC_INTENSET11_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
34946   #define GRTC_INTENSET11_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
34947   #define GRTC_INTENSET11_COMPARE11_Set (0x1UL)      /*!< Enable                                                               */
34948   #define GRTC_INTENSET11_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34949   #define GRTC_INTENSET11_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34950 
34951 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
34952   #define GRTC_INTENSET11_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
34953   #define GRTC_INTENSET11_COMPARE12_Msk (0x1UL << GRTC_INTENSET11_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
34954   #define GRTC_INTENSET11_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
34955   #define GRTC_INTENSET11_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
34956   #define GRTC_INTENSET11_COMPARE12_Set (0x1UL)      /*!< Enable                                                               */
34957   #define GRTC_INTENSET11_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34958   #define GRTC_INTENSET11_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34959 
34960 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
34961   #define GRTC_INTENSET11_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
34962   #define GRTC_INTENSET11_COMPARE13_Msk (0x1UL << GRTC_INTENSET11_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
34963   #define GRTC_INTENSET11_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
34964   #define GRTC_INTENSET11_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
34965   #define GRTC_INTENSET11_COMPARE13_Set (0x1UL)      /*!< Enable                                                               */
34966   #define GRTC_INTENSET11_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34967   #define GRTC_INTENSET11_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34968 
34969 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
34970   #define GRTC_INTENSET11_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
34971   #define GRTC_INTENSET11_COMPARE14_Msk (0x1UL << GRTC_INTENSET11_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
34972   #define GRTC_INTENSET11_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
34973   #define GRTC_INTENSET11_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
34974   #define GRTC_INTENSET11_COMPARE14_Set (0x1UL)      /*!< Enable                                                               */
34975   #define GRTC_INTENSET11_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34976   #define GRTC_INTENSET11_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34977 
34978 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
34979   #define GRTC_INTENSET11_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
34980   #define GRTC_INTENSET11_COMPARE15_Msk (0x1UL << GRTC_INTENSET11_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
34981   #define GRTC_INTENSET11_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
34982   #define GRTC_INTENSET11_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
34983   #define GRTC_INTENSET11_COMPARE15_Set (0x1UL)      /*!< Enable                                                               */
34984   #define GRTC_INTENSET11_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
34985   #define GRTC_INTENSET11_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
34986 
34987 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
34988   #define GRTC_INTENSET11_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
34989   #define GRTC_INTENSET11_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET11_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
34990                                                                             field.*/
34991   #define GRTC_INTENSET11_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
34992   #define GRTC_INTENSET11_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
34993   #define GRTC_INTENSET11_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                              */
34994   #define GRTC_INTENSET11_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
34995   #define GRTC_INTENSET11_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
34996 
34997 
34998 /* GRTC_INTENCLR11: Disable interrupt */
34999   #define GRTC_INTENCLR11_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR11 register.                                  */
35000 
35001 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
35002   #define GRTC_INTENCLR11_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
35003   #define GRTC_INTENCLR11_COMPARE0_Msk (0x1UL << GRTC_INTENCLR11_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
35004   #define GRTC_INTENCLR11_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
35005   #define GRTC_INTENCLR11_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
35006   #define GRTC_INTENCLR11_COMPARE0_Clear (0x1UL)     /*!< Disable                                                              */
35007   #define GRTC_INTENCLR11_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35008   #define GRTC_INTENCLR11_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35009 
35010 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
35011   #define GRTC_INTENCLR11_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
35012   #define GRTC_INTENCLR11_COMPARE1_Msk (0x1UL << GRTC_INTENCLR11_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
35013   #define GRTC_INTENCLR11_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
35014   #define GRTC_INTENCLR11_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
35015   #define GRTC_INTENCLR11_COMPARE1_Clear (0x1UL)     /*!< Disable                                                              */
35016   #define GRTC_INTENCLR11_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35017   #define GRTC_INTENCLR11_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35018 
35019 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
35020   #define GRTC_INTENCLR11_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
35021   #define GRTC_INTENCLR11_COMPARE2_Msk (0x1UL << GRTC_INTENCLR11_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
35022   #define GRTC_INTENCLR11_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
35023   #define GRTC_INTENCLR11_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
35024   #define GRTC_INTENCLR11_COMPARE2_Clear (0x1UL)     /*!< Disable                                                              */
35025   #define GRTC_INTENCLR11_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35026   #define GRTC_INTENCLR11_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35027 
35028 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
35029   #define GRTC_INTENCLR11_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
35030   #define GRTC_INTENCLR11_COMPARE3_Msk (0x1UL << GRTC_INTENCLR11_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
35031   #define GRTC_INTENCLR11_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
35032   #define GRTC_INTENCLR11_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
35033   #define GRTC_INTENCLR11_COMPARE3_Clear (0x1UL)     /*!< Disable                                                              */
35034   #define GRTC_INTENCLR11_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35035   #define GRTC_INTENCLR11_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35036 
35037 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
35038   #define GRTC_INTENCLR11_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
35039   #define GRTC_INTENCLR11_COMPARE4_Msk (0x1UL << GRTC_INTENCLR11_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
35040   #define GRTC_INTENCLR11_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
35041   #define GRTC_INTENCLR11_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
35042   #define GRTC_INTENCLR11_COMPARE4_Clear (0x1UL)     /*!< Disable                                                              */
35043   #define GRTC_INTENCLR11_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35044   #define GRTC_INTENCLR11_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35045 
35046 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
35047   #define GRTC_INTENCLR11_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
35048   #define GRTC_INTENCLR11_COMPARE5_Msk (0x1UL << GRTC_INTENCLR11_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
35049   #define GRTC_INTENCLR11_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
35050   #define GRTC_INTENCLR11_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
35051   #define GRTC_INTENCLR11_COMPARE5_Clear (0x1UL)     /*!< Disable                                                              */
35052   #define GRTC_INTENCLR11_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35053   #define GRTC_INTENCLR11_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35054 
35055 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
35056   #define GRTC_INTENCLR11_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
35057   #define GRTC_INTENCLR11_COMPARE6_Msk (0x1UL << GRTC_INTENCLR11_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
35058   #define GRTC_INTENCLR11_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
35059   #define GRTC_INTENCLR11_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
35060   #define GRTC_INTENCLR11_COMPARE6_Clear (0x1UL)     /*!< Disable                                                              */
35061   #define GRTC_INTENCLR11_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35062   #define GRTC_INTENCLR11_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35063 
35064 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
35065   #define GRTC_INTENCLR11_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
35066   #define GRTC_INTENCLR11_COMPARE7_Msk (0x1UL << GRTC_INTENCLR11_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
35067   #define GRTC_INTENCLR11_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
35068   #define GRTC_INTENCLR11_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
35069   #define GRTC_INTENCLR11_COMPARE7_Clear (0x1UL)     /*!< Disable                                                              */
35070   #define GRTC_INTENCLR11_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35071   #define GRTC_INTENCLR11_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35072 
35073 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
35074   #define GRTC_INTENCLR11_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
35075   #define GRTC_INTENCLR11_COMPARE8_Msk (0x1UL << GRTC_INTENCLR11_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
35076   #define GRTC_INTENCLR11_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
35077   #define GRTC_INTENCLR11_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
35078   #define GRTC_INTENCLR11_COMPARE8_Clear (0x1UL)     /*!< Disable                                                              */
35079   #define GRTC_INTENCLR11_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35080   #define GRTC_INTENCLR11_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35081 
35082 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
35083   #define GRTC_INTENCLR11_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
35084   #define GRTC_INTENCLR11_COMPARE9_Msk (0x1UL << GRTC_INTENCLR11_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
35085   #define GRTC_INTENCLR11_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
35086   #define GRTC_INTENCLR11_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
35087   #define GRTC_INTENCLR11_COMPARE9_Clear (0x1UL)     /*!< Disable                                                              */
35088   #define GRTC_INTENCLR11_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35089   #define GRTC_INTENCLR11_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35090 
35091 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
35092   #define GRTC_INTENCLR11_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
35093   #define GRTC_INTENCLR11_COMPARE10_Msk (0x1UL << GRTC_INTENCLR11_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
35094   #define GRTC_INTENCLR11_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
35095   #define GRTC_INTENCLR11_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
35096   #define GRTC_INTENCLR11_COMPARE10_Clear (0x1UL)    /*!< Disable                                                              */
35097   #define GRTC_INTENCLR11_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35098   #define GRTC_INTENCLR11_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35099 
35100 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
35101   #define GRTC_INTENCLR11_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
35102   #define GRTC_INTENCLR11_COMPARE11_Msk (0x1UL << GRTC_INTENCLR11_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
35103   #define GRTC_INTENCLR11_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
35104   #define GRTC_INTENCLR11_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
35105   #define GRTC_INTENCLR11_COMPARE11_Clear (0x1UL)    /*!< Disable                                                              */
35106   #define GRTC_INTENCLR11_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35107   #define GRTC_INTENCLR11_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35108 
35109 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
35110   #define GRTC_INTENCLR11_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
35111   #define GRTC_INTENCLR11_COMPARE12_Msk (0x1UL << GRTC_INTENCLR11_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
35112   #define GRTC_INTENCLR11_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
35113   #define GRTC_INTENCLR11_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
35114   #define GRTC_INTENCLR11_COMPARE12_Clear (0x1UL)    /*!< Disable                                                              */
35115   #define GRTC_INTENCLR11_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35116   #define GRTC_INTENCLR11_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35117 
35118 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
35119   #define GRTC_INTENCLR11_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
35120   #define GRTC_INTENCLR11_COMPARE13_Msk (0x1UL << GRTC_INTENCLR11_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
35121   #define GRTC_INTENCLR11_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
35122   #define GRTC_INTENCLR11_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
35123   #define GRTC_INTENCLR11_COMPARE13_Clear (0x1UL)    /*!< Disable                                                              */
35124   #define GRTC_INTENCLR11_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35125   #define GRTC_INTENCLR11_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35126 
35127 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
35128   #define GRTC_INTENCLR11_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
35129   #define GRTC_INTENCLR11_COMPARE14_Msk (0x1UL << GRTC_INTENCLR11_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
35130   #define GRTC_INTENCLR11_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
35131   #define GRTC_INTENCLR11_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
35132   #define GRTC_INTENCLR11_COMPARE14_Clear (0x1UL)    /*!< Disable                                                              */
35133   #define GRTC_INTENCLR11_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35134   #define GRTC_INTENCLR11_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35135 
35136 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
35137   #define GRTC_INTENCLR11_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
35138   #define GRTC_INTENCLR11_COMPARE15_Msk (0x1UL << GRTC_INTENCLR11_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
35139   #define GRTC_INTENCLR11_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
35140   #define GRTC_INTENCLR11_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
35141   #define GRTC_INTENCLR11_COMPARE15_Clear (0x1UL)    /*!< Disable                                                              */
35142   #define GRTC_INTENCLR11_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35143   #define GRTC_INTENCLR11_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35144 
35145 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
35146   #define GRTC_INTENCLR11_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
35147   #define GRTC_INTENCLR11_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR11_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
35148                                                                             field.*/
35149   #define GRTC_INTENCLR11_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
35150   #define GRTC_INTENCLR11_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
35151   #define GRTC_INTENCLR11_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                           */
35152   #define GRTC_INTENCLR11_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
35153   #define GRTC_INTENCLR11_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
35154 
35155 
35156 /* GRTC_INTPEND11: Pending interrupts */
35157   #define GRTC_INTPEND11_ResetValue (0x00000000UL)   /*!< Reset value of INTPEND11 register.                                   */
35158 
35159 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
35160   #define GRTC_INTPEND11_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
35161   #define GRTC_INTPEND11_COMPARE0_Msk (0x1UL << GRTC_INTPEND11_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
35162   #define GRTC_INTPEND11_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
35163   #define GRTC_INTPEND11_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
35164   #define GRTC_INTPEND11_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35165   #define GRTC_INTPEND11_COMPARE0_Pending (0x1UL)    /*!< Read: Pending                                                        */
35166 
35167 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
35168   #define GRTC_INTPEND11_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
35169   #define GRTC_INTPEND11_COMPARE1_Msk (0x1UL << GRTC_INTPEND11_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
35170   #define GRTC_INTPEND11_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
35171   #define GRTC_INTPEND11_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
35172   #define GRTC_INTPEND11_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35173   #define GRTC_INTPEND11_COMPARE1_Pending (0x1UL)    /*!< Read: Pending                                                        */
35174 
35175 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
35176   #define GRTC_INTPEND11_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
35177   #define GRTC_INTPEND11_COMPARE2_Msk (0x1UL << GRTC_INTPEND11_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
35178   #define GRTC_INTPEND11_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
35179   #define GRTC_INTPEND11_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
35180   #define GRTC_INTPEND11_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35181   #define GRTC_INTPEND11_COMPARE2_Pending (0x1UL)    /*!< Read: Pending                                                        */
35182 
35183 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
35184   #define GRTC_INTPEND11_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
35185   #define GRTC_INTPEND11_COMPARE3_Msk (0x1UL << GRTC_INTPEND11_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
35186   #define GRTC_INTPEND11_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
35187   #define GRTC_INTPEND11_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
35188   #define GRTC_INTPEND11_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35189   #define GRTC_INTPEND11_COMPARE3_Pending (0x1UL)    /*!< Read: Pending                                                        */
35190 
35191 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
35192   #define GRTC_INTPEND11_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
35193   #define GRTC_INTPEND11_COMPARE4_Msk (0x1UL << GRTC_INTPEND11_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
35194   #define GRTC_INTPEND11_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
35195   #define GRTC_INTPEND11_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
35196   #define GRTC_INTPEND11_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35197   #define GRTC_INTPEND11_COMPARE4_Pending (0x1UL)    /*!< Read: Pending                                                        */
35198 
35199 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
35200   #define GRTC_INTPEND11_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
35201   #define GRTC_INTPEND11_COMPARE5_Msk (0x1UL << GRTC_INTPEND11_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
35202   #define GRTC_INTPEND11_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
35203   #define GRTC_INTPEND11_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
35204   #define GRTC_INTPEND11_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35205   #define GRTC_INTPEND11_COMPARE5_Pending (0x1UL)    /*!< Read: Pending                                                        */
35206 
35207 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
35208   #define GRTC_INTPEND11_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
35209   #define GRTC_INTPEND11_COMPARE6_Msk (0x1UL << GRTC_INTPEND11_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
35210   #define GRTC_INTPEND11_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
35211   #define GRTC_INTPEND11_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
35212   #define GRTC_INTPEND11_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35213   #define GRTC_INTPEND11_COMPARE6_Pending (0x1UL)    /*!< Read: Pending                                                        */
35214 
35215 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
35216   #define GRTC_INTPEND11_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
35217   #define GRTC_INTPEND11_COMPARE7_Msk (0x1UL << GRTC_INTPEND11_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
35218   #define GRTC_INTPEND11_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
35219   #define GRTC_INTPEND11_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
35220   #define GRTC_INTPEND11_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35221   #define GRTC_INTPEND11_COMPARE7_Pending (0x1UL)    /*!< Read: Pending                                                        */
35222 
35223 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
35224   #define GRTC_INTPEND11_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
35225   #define GRTC_INTPEND11_COMPARE8_Msk (0x1UL << GRTC_INTPEND11_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
35226   #define GRTC_INTPEND11_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
35227   #define GRTC_INTPEND11_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
35228   #define GRTC_INTPEND11_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35229   #define GRTC_INTPEND11_COMPARE8_Pending (0x1UL)    /*!< Read: Pending                                                        */
35230 
35231 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
35232   #define GRTC_INTPEND11_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
35233   #define GRTC_INTPEND11_COMPARE9_Msk (0x1UL << GRTC_INTPEND11_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
35234   #define GRTC_INTPEND11_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
35235   #define GRTC_INTPEND11_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
35236   #define GRTC_INTPEND11_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35237   #define GRTC_INTPEND11_COMPARE9_Pending (0x1UL)    /*!< Read: Pending                                                        */
35238 
35239 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
35240   #define GRTC_INTPEND11_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
35241   #define GRTC_INTPEND11_COMPARE10_Msk (0x1UL << GRTC_INTPEND11_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
35242   #define GRTC_INTPEND11_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
35243   #define GRTC_INTPEND11_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
35244   #define GRTC_INTPEND11_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35245   #define GRTC_INTPEND11_COMPARE10_Pending (0x1UL)   /*!< Read: Pending                                                        */
35246 
35247 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
35248   #define GRTC_INTPEND11_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
35249   #define GRTC_INTPEND11_COMPARE11_Msk (0x1UL << GRTC_INTPEND11_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
35250   #define GRTC_INTPEND11_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
35251   #define GRTC_INTPEND11_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
35252   #define GRTC_INTPEND11_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35253   #define GRTC_INTPEND11_COMPARE11_Pending (0x1UL)   /*!< Read: Pending                                                        */
35254 
35255 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
35256   #define GRTC_INTPEND11_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
35257   #define GRTC_INTPEND11_COMPARE12_Msk (0x1UL << GRTC_INTPEND11_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
35258   #define GRTC_INTPEND11_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
35259   #define GRTC_INTPEND11_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
35260   #define GRTC_INTPEND11_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35261   #define GRTC_INTPEND11_COMPARE12_Pending (0x1UL)   /*!< Read: Pending                                                        */
35262 
35263 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
35264   #define GRTC_INTPEND11_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
35265   #define GRTC_INTPEND11_COMPARE13_Msk (0x1UL << GRTC_INTPEND11_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
35266   #define GRTC_INTPEND11_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
35267   #define GRTC_INTPEND11_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
35268   #define GRTC_INTPEND11_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35269   #define GRTC_INTPEND11_COMPARE13_Pending (0x1UL)   /*!< Read: Pending                                                        */
35270 
35271 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
35272   #define GRTC_INTPEND11_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
35273   #define GRTC_INTPEND11_COMPARE14_Msk (0x1UL << GRTC_INTPEND11_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
35274   #define GRTC_INTPEND11_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
35275   #define GRTC_INTPEND11_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
35276   #define GRTC_INTPEND11_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35277   #define GRTC_INTPEND11_COMPARE14_Pending (0x1UL)   /*!< Read: Pending                                                        */
35278 
35279 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
35280   #define GRTC_INTPEND11_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
35281   #define GRTC_INTPEND11_COMPARE15_Msk (0x1UL << GRTC_INTPEND11_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
35282   #define GRTC_INTPEND11_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
35283   #define GRTC_INTPEND11_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
35284   #define GRTC_INTPEND11_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35285   #define GRTC_INTPEND11_COMPARE15_Pending (0x1UL)   /*!< Read: Pending                                                        */
35286 
35287 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
35288   #define GRTC_INTPEND11_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
35289   #define GRTC_INTPEND11_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND11_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
35290                                                                             field.*/
35291   #define GRTC_INTPEND11_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
35292   #define GRTC_INTPEND11_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
35293   #define GRTC_INTPEND11_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                             */
35294   #define GRTC_INTPEND11_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                    */
35295 
35296 
35297 /* GRTC_INTEN12: Enable or disable interrupt */
35298   #define GRTC_INTEN12_ResetValue (0x00000000UL)     /*!< Reset value of INTEN12 register.                                     */
35299 
35300 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
35301   #define GRTC_INTEN12_COMPARE0_Pos (0UL)            /*!< Position of COMPARE0 field.                                          */
35302   #define GRTC_INTEN12_COMPARE0_Msk (0x1UL << GRTC_INTEN12_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
35303   #define GRTC_INTEN12_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
35304   #define GRTC_INTEN12_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
35305   #define GRTC_INTEN12_COMPARE0_Disabled (0x0UL)     /*!< Disable                                                              */
35306   #define GRTC_INTEN12_COMPARE0_Enabled (0x1UL)      /*!< Enable                                                               */
35307 
35308 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
35309   #define GRTC_INTEN12_COMPARE1_Pos (1UL)            /*!< Position of COMPARE1 field.                                          */
35310   #define GRTC_INTEN12_COMPARE1_Msk (0x1UL << GRTC_INTEN12_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
35311   #define GRTC_INTEN12_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
35312   #define GRTC_INTEN12_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
35313   #define GRTC_INTEN12_COMPARE1_Disabled (0x0UL)     /*!< Disable                                                              */
35314   #define GRTC_INTEN12_COMPARE1_Enabled (0x1UL)      /*!< Enable                                                               */
35315 
35316 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
35317   #define GRTC_INTEN12_COMPARE2_Pos (2UL)            /*!< Position of COMPARE2 field.                                          */
35318   #define GRTC_INTEN12_COMPARE2_Msk (0x1UL << GRTC_INTEN12_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
35319   #define GRTC_INTEN12_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
35320   #define GRTC_INTEN12_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
35321   #define GRTC_INTEN12_COMPARE2_Disabled (0x0UL)     /*!< Disable                                                              */
35322   #define GRTC_INTEN12_COMPARE2_Enabled (0x1UL)      /*!< Enable                                                               */
35323 
35324 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
35325   #define GRTC_INTEN12_COMPARE3_Pos (3UL)            /*!< Position of COMPARE3 field.                                          */
35326   #define GRTC_INTEN12_COMPARE3_Msk (0x1UL << GRTC_INTEN12_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
35327   #define GRTC_INTEN12_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
35328   #define GRTC_INTEN12_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
35329   #define GRTC_INTEN12_COMPARE3_Disabled (0x0UL)     /*!< Disable                                                              */
35330   #define GRTC_INTEN12_COMPARE3_Enabled (0x1UL)      /*!< Enable                                                               */
35331 
35332 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
35333   #define GRTC_INTEN12_COMPARE4_Pos (4UL)            /*!< Position of COMPARE4 field.                                          */
35334   #define GRTC_INTEN12_COMPARE4_Msk (0x1UL << GRTC_INTEN12_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
35335   #define GRTC_INTEN12_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
35336   #define GRTC_INTEN12_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
35337   #define GRTC_INTEN12_COMPARE4_Disabled (0x0UL)     /*!< Disable                                                              */
35338   #define GRTC_INTEN12_COMPARE4_Enabled (0x1UL)      /*!< Enable                                                               */
35339 
35340 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
35341   #define GRTC_INTEN12_COMPARE5_Pos (5UL)            /*!< Position of COMPARE5 field.                                          */
35342   #define GRTC_INTEN12_COMPARE5_Msk (0x1UL << GRTC_INTEN12_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
35343   #define GRTC_INTEN12_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
35344   #define GRTC_INTEN12_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
35345   #define GRTC_INTEN12_COMPARE5_Disabled (0x0UL)     /*!< Disable                                                              */
35346   #define GRTC_INTEN12_COMPARE5_Enabled (0x1UL)      /*!< Enable                                                               */
35347 
35348 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
35349   #define GRTC_INTEN12_COMPARE6_Pos (6UL)            /*!< Position of COMPARE6 field.                                          */
35350   #define GRTC_INTEN12_COMPARE6_Msk (0x1UL << GRTC_INTEN12_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
35351   #define GRTC_INTEN12_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
35352   #define GRTC_INTEN12_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
35353   #define GRTC_INTEN12_COMPARE6_Disabled (0x0UL)     /*!< Disable                                                              */
35354   #define GRTC_INTEN12_COMPARE6_Enabled (0x1UL)      /*!< Enable                                                               */
35355 
35356 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
35357   #define GRTC_INTEN12_COMPARE7_Pos (7UL)            /*!< Position of COMPARE7 field.                                          */
35358   #define GRTC_INTEN12_COMPARE7_Msk (0x1UL << GRTC_INTEN12_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
35359   #define GRTC_INTEN12_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
35360   #define GRTC_INTEN12_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
35361   #define GRTC_INTEN12_COMPARE7_Disabled (0x0UL)     /*!< Disable                                                              */
35362   #define GRTC_INTEN12_COMPARE7_Enabled (0x1UL)      /*!< Enable                                                               */
35363 
35364 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
35365   #define GRTC_INTEN12_COMPARE8_Pos (8UL)            /*!< Position of COMPARE8 field.                                          */
35366   #define GRTC_INTEN12_COMPARE8_Msk (0x1UL << GRTC_INTEN12_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                      */
35367   #define GRTC_INTEN12_COMPARE8_Min (0x0UL)          /*!< Min enumerator value of COMPARE8 field.                              */
35368   #define GRTC_INTEN12_COMPARE8_Max (0x1UL)          /*!< Max enumerator value of COMPARE8 field.                              */
35369   #define GRTC_INTEN12_COMPARE8_Disabled (0x0UL)     /*!< Disable                                                              */
35370   #define GRTC_INTEN12_COMPARE8_Enabled (0x1UL)      /*!< Enable                                                               */
35371 
35372 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
35373   #define GRTC_INTEN12_COMPARE9_Pos (9UL)            /*!< Position of COMPARE9 field.                                          */
35374   #define GRTC_INTEN12_COMPARE9_Msk (0x1UL << GRTC_INTEN12_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                      */
35375   #define GRTC_INTEN12_COMPARE9_Min (0x0UL)          /*!< Min enumerator value of COMPARE9 field.                              */
35376   #define GRTC_INTEN12_COMPARE9_Max (0x1UL)          /*!< Max enumerator value of COMPARE9 field.                              */
35377   #define GRTC_INTEN12_COMPARE9_Disabled (0x0UL)     /*!< Disable                                                              */
35378   #define GRTC_INTEN12_COMPARE9_Enabled (0x1UL)      /*!< Enable                                                               */
35379 
35380 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
35381   #define GRTC_INTEN12_COMPARE10_Pos (10UL)          /*!< Position of COMPARE10 field.                                         */
35382   #define GRTC_INTEN12_COMPARE10_Msk (0x1UL << GRTC_INTEN12_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                   */
35383   #define GRTC_INTEN12_COMPARE10_Min (0x0UL)         /*!< Min enumerator value of COMPARE10 field.                             */
35384   #define GRTC_INTEN12_COMPARE10_Max (0x1UL)         /*!< Max enumerator value of COMPARE10 field.                             */
35385   #define GRTC_INTEN12_COMPARE10_Disabled (0x0UL)    /*!< Disable                                                              */
35386   #define GRTC_INTEN12_COMPARE10_Enabled (0x1UL)     /*!< Enable                                                               */
35387 
35388 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
35389   #define GRTC_INTEN12_COMPARE11_Pos (11UL)          /*!< Position of COMPARE11 field.                                         */
35390   #define GRTC_INTEN12_COMPARE11_Msk (0x1UL << GRTC_INTEN12_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                   */
35391   #define GRTC_INTEN12_COMPARE11_Min (0x0UL)         /*!< Min enumerator value of COMPARE11 field.                             */
35392   #define GRTC_INTEN12_COMPARE11_Max (0x1UL)         /*!< Max enumerator value of COMPARE11 field.                             */
35393   #define GRTC_INTEN12_COMPARE11_Disabled (0x0UL)    /*!< Disable                                                              */
35394   #define GRTC_INTEN12_COMPARE11_Enabled (0x1UL)     /*!< Enable                                                               */
35395 
35396 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
35397   #define GRTC_INTEN12_COMPARE12_Pos (12UL)          /*!< Position of COMPARE12 field.                                         */
35398   #define GRTC_INTEN12_COMPARE12_Msk (0x1UL << GRTC_INTEN12_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                   */
35399   #define GRTC_INTEN12_COMPARE12_Min (0x0UL)         /*!< Min enumerator value of COMPARE12 field.                             */
35400   #define GRTC_INTEN12_COMPARE12_Max (0x1UL)         /*!< Max enumerator value of COMPARE12 field.                             */
35401   #define GRTC_INTEN12_COMPARE12_Disabled (0x0UL)    /*!< Disable                                                              */
35402   #define GRTC_INTEN12_COMPARE12_Enabled (0x1UL)     /*!< Enable                                                               */
35403 
35404 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
35405   #define GRTC_INTEN12_COMPARE13_Pos (13UL)          /*!< Position of COMPARE13 field.                                         */
35406   #define GRTC_INTEN12_COMPARE13_Msk (0x1UL << GRTC_INTEN12_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                   */
35407   #define GRTC_INTEN12_COMPARE13_Min (0x0UL)         /*!< Min enumerator value of COMPARE13 field.                             */
35408   #define GRTC_INTEN12_COMPARE13_Max (0x1UL)         /*!< Max enumerator value of COMPARE13 field.                             */
35409   #define GRTC_INTEN12_COMPARE13_Disabled (0x0UL)    /*!< Disable                                                              */
35410   #define GRTC_INTEN12_COMPARE13_Enabled (0x1UL)     /*!< Enable                                                               */
35411 
35412 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
35413   #define GRTC_INTEN12_COMPARE14_Pos (14UL)          /*!< Position of COMPARE14 field.                                         */
35414   #define GRTC_INTEN12_COMPARE14_Msk (0x1UL << GRTC_INTEN12_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                   */
35415   #define GRTC_INTEN12_COMPARE14_Min (0x0UL)         /*!< Min enumerator value of COMPARE14 field.                             */
35416   #define GRTC_INTEN12_COMPARE14_Max (0x1UL)         /*!< Max enumerator value of COMPARE14 field.                             */
35417   #define GRTC_INTEN12_COMPARE14_Disabled (0x0UL)    /*!< Disable                                                              */
35418   #define GRTC_INTEN12_COMPARE14_Enabled (0x1UL)     /*!< Enable                                                               */
35419 
35420 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
35421   #define GRTC_INTEN12_COMPARE15_Pos (15UL)          /*!< Position of COMPARE15 field.                                         */
35422   #define GRTC_INTEN12_COMPARE15_Msk (0x1UL << GRTC_INTEN12_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                   */
35423   #define GRTC_INTEN12_COMPARE15_Min (0x0UL)         /*!< Min enumerator value of COMPARE15 field.                             */
35424   #define GRTC_INTEN12_COMPARE15_Max (0x1UL)         /*!< Max enumerator value of COMPARE15 field.                             */
35425   #define GRTC_INTEN12_COMPARE15_Disabled (0x0UL)    /*!< Disable                                                              */
35426   #define GRTC_INTEN12_COMPARE15_Enabled (0x1UL)     /*!< Enable                                                               */
35427 
35428 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
35429   #define GRTC_INTEN12_SYSCOUNTERVALID_Pos (26UL)    /*!< Position of SYSCOUNTERVALID field.                                   */
35430   #define GRTC_INTEN12_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN12_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */
35431   #define GRTC_INTEN12_SYSCOUNTERVALID_Min (0x0UL)   /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
35432   #define GRTC_INTEN12_SYSCOUNTERVALID_Max (0x1UL)   /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
35433   #define GRTC_INTEN12_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                           */
35434   #define GRTC_INTEN12_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                             */
35435 
35436 
35437 /* GRTC_INTENSET12: Enable interrupt */
35438   #define GRTC_INTENSET12_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET12 register.                                  */
35439 
35440 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
35441   #define GRTC_INTENSET12_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
35442   #define GRTC_INTENSET12_COMPARE0_Msk (0x1UL << GRTC_INTENSET12_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
35443   #define GRTC_INTENSET12_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
35444   #define GRTC_INTENSET12_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
35445   #define GRTC_INTENSET12_COMPARE0_Set (0x1UL)       /*!< Enable                                                               */
35446   #define GRTC_INTENSET12_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35447   #define GRTC_INTENSET12_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35448 
35449 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
35450   #define GRTC_INTENSET12_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
35451   #define GRTC_INTENSET12_COMPARE1_Msk (0x1UL << GRTC_INTENSET12_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
35452   #define GRTC_INTENSET12_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
35453   #define GRTC_INTENSET12_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
35454   #define GRTC_INTENSET12_COMPARE1_Set (0x1UL)       /*!< Enable                                                               */
35455   #define GRTC_INTENSET12_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35456   #define GRTC_INTENSET12_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35457 
35458 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
35459   #define GRTC_INTENSET12_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
35460   #define GRTC_INTENSET12_COMPARE2_Msk (0x1UL << GRTC_INTENSET12_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
35461   #define GRTC_INTENSET12_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
35462   #define GRTC_INTENSET12_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
35463   #define GRTC_INTENSET12_COMPARE2_Set (0x1UL)       /*!< Enable                                                               */
35464   #define GRTC_INTENSET12_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35465   #define GRTC_INTENSET12_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35466 
35467 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
35468   #define GRTC_INTENSET12_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
35469   #define GRTC_INTENSET12_COMPARE3_Msk (0x1UL << GRTC_INTENSET12_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
35470   #define GRTC_INTENSET12_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
35471   #define GRTC_INTENSET12_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
35472   #define GRTC_INTENSET12_COMPARE3_Set (0x1UL)       /*!< Enable                                                               */
35473   #define GRTC_INTENSET12_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35474   #define GRTC_INTENSET12_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35475 
35476 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
35477   #define GRTC_INTENSET12_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
35478   #define GRTC_INTENSET12_COMPARE4_Msk (0x1UL << GRTC_INTENSET12_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
35479   #define GRTC_INTENSET12_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
35480   #define GRTC_INTENSET12_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
35481   #define GRTC_INTENSET12_COMPARE4_Set (0x1UL)       /*!< Enable                                                               */
35482   #define GRTC_INTENSET12_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35483   #define GRTC_INTENSET12_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35484 
35485 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
35486   #define GRTC_INTENSET12_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
35487   #define GRTC_INTENSET12_COMPARE5_Msk (0x1UL << GRTC_INTENSET12_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
35488   #define GRTC_INTENSET12_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
35489   #define GRTC_INTENSET12_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
35490   #define GRTC_INTENSET12_COMPARE5_Set (0x1UL)       /*!< Enable                                                               */
35491   #define GRTC_INTENSET12_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35492   #define GRTC_INTENSET12_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35493 
35494 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
35495   #define GRTC_INTENSET12_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
35496   #define GRTC_INTENSET12_COMPARE6_Msk (0x1UL << GRTC_INTENSET12_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
35497   #define GRTC_INTENSET12_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
35498   #define GRTC_INTENSET12_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
35499   #define GRTC_INTENSET12_COMPARE6_Set (0x1UL)       /*!< Enable                                                               */
35500   #define GRTC_INTENSET12_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35501   #define GRTC_INTENSET12_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35502 
35503 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
35504   #define GRTC_INTENSET12_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
35505   #define GRTC_INTENSET12_COMPARE7_Msk (0x1UL << GRTC_INTENSET12_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
35506   #define GRTC_INTENSET12_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
35507   #define GRTC_INTENSET12_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
35508   #define GRTC_INTENSET12_COMPARE7_Set (0x1UL)       /*!< Enable                                                               */
35509   #define GRTC_INTENSET12_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35510   #define GRTC_INTENSET12_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35511 
35512 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
35513   #define GRTC_INTENSET12_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
35514   #define GRTC_INTENSET12_COMPARE8_Msk (0x1UL << GRTC_INTENSET12_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
35515   #define GRTC_INTENSET12_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
35516   #define GRTC_INTENSET12_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
35517   #define GRTC_INTENSET12_COMPARE8_Set (0x1UL)       /*!< Enable                                                               */
35518   #define GRTC_INTENSET12_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35519   #define GRTC_INTENSET12_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35520 
35521 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
35522   #define GRTC_INTENSET12_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
35523   #define GRTC_INTENSET12_COMPARE9_Msk (0x1UL << GRTC_INTENSET12_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
35524   #define GRTC_INTENSET12_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
35525   #define GRTC_INTENSET12_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
35526   #define GRTC_INTENSET12_COMPARE9_Set (0x1UL)       /*!< Enable                                                               */
35527   #define GRTC_INTENSET12_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35528   #define GRTC_INTENSET12_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35529 
35530 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
35531   #define GRTC_INTENSET12_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
35532   #define GRTC_INTENSET12_COMPARE10_Msk (0x1UL << GRTC_INTENSET12_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
35533   #define GRTC_INTENSET12_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
35534   #define GRTC_INTENSET12_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
35535   #define GRTC_INTENSET12_COMPARE10_Set (0x1UL)      /*!< Enable                                                               */
35536   #define GRTC_INTENSET12_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35537   #define GRTC_INTENSET12_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35538 
35539 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
35540   #define GRTC_INTENSET12_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
35541   #define GRTC_INTENSET12_COMPARE11_Msk (0x1UL << GRTC_INTENSET12_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
35542   #define GRTC_INTENSET12_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
35543   #define GRTC_INTENSET12_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
35544   #define GRTC_INTENSET12_COMPARE11_Set (0x1UL)      /*!< Enable                                                               */
35545   #define GRTC_INTENSET12_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35546   #define GRTC_INTENSET12_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35547 
35548 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
35549   #define GRTC_INTENSET12_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
35550   #define GRTC_INTENSET12_COMPARE12_Msk (0x1UL << GRTC_INTENSET12_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
35551   #define GRTC_INTENSET12_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
35552   #define GRTC_INTENSET12_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
35553   #define GRTC_INTENSET12_COMPARE12_Set (0x1UL)      /*!< Enable                                                               */
35554   #define GRTC_INTENSET12_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35555   #define GRTC_INTENSET12_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35556 
35557 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
35558   #define GRTC_INTENSET12_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
35559   #define GRTC_INTENSET12_COMPARE13_Msk (0x1UL << GRTC_INTENSET12_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
35560   #define GRTC_INTENSET12_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
35561   #define GRTC_INTENSET12_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
35562   #define GRTC_INTENSET12_COMPARE13_Set (0x1UL)      /*!< Enable                                                               */
35563   #define GRTC_INTENSET12_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35564   #define GRTC_INTENSET12_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35565 
35566 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
35567   #define GRTC_INTENSET12_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
35568   #define GRTC_INTENSET12_COMPARE14_Msk (0x1UL << GRTC_INTENSET12_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
35569   #define GRTC_INTENSET12_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
35570   #define GRTC_INTENSET12_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
35571   #define GRTC_INTENSET12_COMPARE14_Set (0x1UL)      /*!< Enable                                                               */
35572   #define GRTC_INTENSET12_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35573   #define GRTC_INTENSET12_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35574 
35575 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
35576   #define GRTC_INTENSET12_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
35577   #define GRTC_INTENSET12_COMPARE15_Msk (0x1UL << GRTC_INTENSET12_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
35578   #define GRTC_INTENSET12_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
35579   #define GRTC_INTENSET12_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
35580   #define GRTC_INTENSET12_COMPARE15_Set (0x1UL)      /*!< Enable                                                               */
35581   #define GRTC_INTENSET12_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35582   #define GRTC_INTENSET12_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35583 
35584 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
35585   #define GRTC_INTENSET12_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
35586   #define GRTC_INTENSET12_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET12_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
35587                                                                             field.*/
35588   #define GRTC_INTENSET12_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
35589   #define GRTC_INTENSET12_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
35590   #define GRTC_INTENSET12_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                              */
35591   #define GRTC_INTENSET12_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
35592   #define GRTC_INTENSET12_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
35593 
35594 
35595 /* GRTC_INTENCLR12: Disable interrupt */
35596   #define GRTC_INTENCLR12_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR12 register.                                  */
35597 
35598 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
35599   #define GRTC_INTENCLR12_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
35600   #define GRTC_INTENCLR12_COMPARE0_Msk (0x1UL << GRTC_INTENCLR12_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
35601   #define GRTC_INTENCLR12_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
35602   #define GRTC_INTENCLR12_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
35603   #define GRTC_INTENCLR12_COMPARE0_Clear (0x1UL)     /*!< Disable                                                              */
35604   #define GRTC_INTENCLR12_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35605   #define GRTC_INTENCLR12_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35606 
35607 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
35608   #define GRTC_INTENCLR12_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
35609   #define GRTC_INTENCLR12_COMPARE1_Msk (0x1UL << GRTC_INTENCLR12_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
35610   #define GRTC_INTENCLR12_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
35611   #define GRTC_INTENCLR12_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
35612   #define GRTC_INTENCLR12_COMPARE1_Clear (0x1UL)     /*!< Disable                                                              */
35613   #define GRTC_INTENCLR12_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35614   #define GRTC_INTENCLR12_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35615 
35616 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
35617   #define GRTC_INTENCLR12_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
35618   #define GRTC_INTENCLR12_COMPARE2_Msk (0x1UL << GRTC_INTENCLR12_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
35619   #define GRTC_INTENCLR12_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
35620   #define GRTC_INTENCLR12_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
35621   #define GRTC_INTENCLR12_COMPARE2_Clear (0x1UL)     /*!< Disable                                                              */
35622   #define GRTC_INTENCLR12_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35623   #define GRTC_INTENCLR12_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35624 
35625 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
35626   #define GRTC_INTENCLR12_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
35627   #define GRTC_INTENCLR12_COMPARE3_Msk (0x1UL << GRTC_INTENCLR12_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
35628   #define GRTC_INTENCLR12_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
35629   #define GRTC_INTENCLR12_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
35630   #define GRTC_INTENCLR12_COMPARE3_Clear (0x1UL)     /*!< Disable                                                              */
35631   #define GRTC_INTENCLR12_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35632   #define GRTC_INTENCLR12_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35633 
35634 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
35635   #define GRTC_INTENCLR12_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
35636   #define GRTC_INTENCLR12_COMPARE4_Msk (0x1UL << GRTC_INTENCLR12_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
35637   #define GRTC_INTENCLR12_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
35638   #define GRTC_INTENCLR12_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
35639   #define GRTC_INTENCLR12_COMPARE4_Clear (0x1UL)     /*!< Disable                                                              */
35640   #define GRTC_INTENCLR12_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35641   #define GRTC_INTENCLR12_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35642 
35643 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
35644   #define GRTC_INTENCLR12_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
35645   #define GRTC_INTENCLR12_COMPARE5_Msk (0x1UL << GRTC_INTENCLR12_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
35646   #define GRTC_INTENCLR12_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
35647   #define GRTC_INTENCLR12_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
35648   #define GRTC_INTENCLR12_COMPARE5_Clear (0x1UL)     /*!< Disable                                                              */
35649   #define GRTC_INTENCLR12_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35650   #define GRTC_INTENCLR12_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35651 
35652 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
35653   #define GRTC_INTENCLR12_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
35654   #define GRTC_INTENCLR12_COMPARE6_Msk (0x1UL << GRTC_INTENCLR12_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
35655   #define GRTC_INTENCLR12_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
35656   #define GRTC_INTENCLR12_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
35657   #define GRTC_INTENCLR12_COMPARE6_Clear (0x1UL)     /*!< Disable                                                              */
35658   #define GRTC_INTENCLR12_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35659   #define GRTC_INTENCLR12_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35660 
35661 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
35662   #define GRTC_INTENCLR12_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
35663   #define GRTC_INTENCLR12_COMPARE7_Msk (0x1UL << GRTC_INTENCLR12_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
35664   #define GRTC_INTENCLR12_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
35665   #define GRTC_INTENCLR12_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
35666   #define GRTC_INTENCLR12_COMPARE7_Clear (0x1UL)     /*!< Disable                                                              */
35667   #define GRTC_INTENCLR12_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35668   #define GRTC_INTENCLR12_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35669 
35670 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
35671   #define GRTC_INTENCLR12_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
35672   #define GRTC_INTENCLR12_COMPARE8_Msk (0x1UL << GRTC_INTENCLR12_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
35673   #define GRTC_INTENCLR12_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
35674   #define GRTC_INTENCLR12_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
35675   #define GRTC_INTENCLR12_COMPARE8_Clear (0x1UL)     /*!< Disable                                                              */
35676   #define GRTC_INTENCLR12_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35677   #define GRTC_INTENCLR12_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35678 
35679 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
35680   #define GRTC_INTENCLR12_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
35681   #define GRTC_INTENCLR12_COMPARE9_Msk (0x1UL << GRTC_INTENCLR12_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
35682   #define GRTC_INTENCLR12_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
35683   #define GRTC_INTENCLR12_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
35684   #define GRTC_INTENCLR12_COMPARE9_Clear (0x1UL)     /*!< Disable                                                              */
35685   #define GRTC_INTENCLR12_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
35686   #define GRTC_INTENCLR12_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
35687 
35688 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
35689   #define GRTC_INTENCLR12_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
35690   #define GRTC_INTENCLR12_COMPARE10_Msk (0x1UL << GRTC_INTENCLR12_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
35691   #define GRTC_INTENCLR12_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
35692   #define GRTC_INTENCLR12_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
35693   #define GRTC_INTENCLR12_COMPARE10_Clear (0x1UL)    /*!< Disable                                                              */
35694   #define GRTC_INTENCLR12_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35695   #define GRTC_INTENCLR12_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35696 
35697 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
35698   #define GRTC_INTENCLR12_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
35699   #define GRTC_INTENCLR12_COMPARE11_Msk (0x1UL << GRTC_INTENCLR12_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
35700   #define GRTC_INTENCLR12_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
35701   #define GRTC_INTENCLR12_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
35702   #define GRTC_INTENCLR12_COMPARE11_Clear (0x1UL)    /*!< Disable                                                              */
35703   #define GRTC_INTENCLR12_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35704   #define GRTC_INTENCLR12_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35705 
35706 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
35707   #define GRTC_INTENCLR12_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
35708   #define GRTC_INTENCLR12_COMPARE12_Msk (0x1UL << GRTC_INTENCLR12_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
35709   #define GRTC_INTENCLR12_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
35710   #define GRTC_INTENCLR12_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
35711   #define GRTC_INTENCLR12_COMPARE12_Clear (0x1UL)    /*!< Disable                                                              */
35712   #define GRTC_INTENCLR12_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35713   #define GRTC_INTENCLR12_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35714 
35715 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
35716   #define GRTC_INTENCLR12_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
35717   #define GRTC_INTENCLR12_COMPARE13_Msk (0x1UL << GRTC_INTENCLR12_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
35718   #define GRTC_INTENCLR12_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
35719   #define GRTC_INTENCLR12_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
35720   #define GRTC_INTENCLR12_COMPARE13_Clear (0x1UL)    /*!< Disable                                                              */
35721   #define GRTC_INTENCLR12_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35722   #define GRTC_INTENCLR12_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35723 
35724 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
35725   #define GRTC_INTENCLR12_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
35726   #define GRTC_INTENCLR12_COMPARE14_Msk (0x1UL << GRTC_INTENCLR12_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
35727   #define GRTC_INTENCLR12_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
35728   #define GRTC_INTENCLR12_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
35729   #define GRTC_INTENCLR12_COMPARE14_Clear (0x1UL)    /*!< Disable                                                              */
35730   #define GRTC_INTENCLR12_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35731   #define GRTC_INTENCLR12_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35732 
35733 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
35734   #define GRTC_INTENCLR12_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
35735   #define GRTC_INTENCLR12_COMPARE15_Msk (0x1UL << GRTC_INTENCLR12_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
35736   #define GRTC_INTENCLR12_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
35737   #define GRTC_INTENCLR12_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
35738   #define GRTC_INTENCLR12_COMPARE15_Clear (0x1UL)    /*!< Disable                                                              */
35739   #define GRTC_INTENCLR12_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
35740   #define GRTC_INTENCLR12_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
35741 
35742 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
35743   #define GRTC_INTENCLR12_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
35744   #define GRTC_INTENCLR12_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR12_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
35745                                                                             field.*/
35746   #define GRTC_INTENCLR12_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
35747   #define GRTC_INTENCLR12_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
35748   #define GRTC_INTENCLR12_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                           */
35749   #define GRTC_INTENCLR12_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
35750   #define GRTC_INTENCLR12_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
35751 
35752 
35753 /* GRTC_INTPEND12: Pending interrupts */
35754   #define GRTC_INTPEND12_ResetValue (0x00000000UL)   /*!< Reset value of INTPEND12 register.                                   */
35755 
35756 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
35757   #define GRTC_INTPEND12_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
35758   #define GRTC_INTPEND12_COMPARE0_Msk (0x1UL << GRTC_INTPEND12_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
35759   #define GRTC_INTPEND12_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
35760   #define GRTC_INTPEND12_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
35761   #define GRTC_INTPEND12_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35762   #define GRTC_INTPEND12_COMPARE0_Pending (0x1UL)    /*!< Read: Pending                                                        */
35763 
35764 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
35765   #define GRTC_INTPEND12_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
35766   #define GRTC_INTPEND12_COMPARE1_Msk (0x1UL << GRTC_INTPEND12_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
35767   #define GRTC_INTPEND12_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
35768   #define GRTC_INTPEND12_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
35769   #define GRTC_INTPEND12_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35770   #define GRTC_INTPEND12_COMPARE1_Pending (0x1UL)    /*!< Read: Pending                                                        */
35771 
35772 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
35773   #define GRTC_INTPEND12_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
35774   #define GRTC_INTPEND12_COMPARE2_Msk (0x1UL << GRTC_INTPEND12_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
35775   #define GRTC_INTPEND12_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
35776   #define GRTC_INTPEND12_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
35777   #define GRTC_INTPEND12_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35778   #define GRTC_INTPEND12_COMPARE2_Pending (0x1UL)    /*!< Read: Pending                                                        */
35779 
35780 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
35781   #define GRTC_INTPEND12_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
35782   #define GRTC_INTPEND12_COMPARE3_Msk (0x1UL << GRTC_INTPEND12_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
35783   #define GRTC_INTPEND12_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
35784   #define GRTC_INTPEND12_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
35785   #define GRTC_INTPEND12_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35786   #define GRTC_INTPEND12_COMPARE3_Pending (0x1UL)    /*!< Read: Pending                                                        */
35787 
35788 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
35789   #define GRTC_INTPEND12_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
35790   #define GRTC_INTPEND12_COMPARE4_Msk (0x1UL << GRTC_INTPEND12_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
35791   #define GRTC_INTPEND12_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
35792   #define GRTC_INTPEND12_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
35793   #define GRTC_INTPEND12_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35794   #define GRTC_INTPEND12_COMPARE4_Pending (0x1UL)    /*!< Read: Pending                                                        */
35795 
35796 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
35797   #define GRTC_INTPEND12_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
35798   #define GRTC_INTPEND12_COMPARE5_Msk (0x1UL << GRTC_INTPEND12_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
35799   #define GRTC_INTPEND12_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
35800   #define GRTC_INTPEND12_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
35801   #define GRTC_INTPEND12_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35802   #define GRTC_INTPEND12_COMPARE5_Pending (0x1UL)    /*!< Read: Pending                                                        */
35803 
35804 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
35805   #define GRTC_INTPEND12_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
35806   #define GRTC_INTPEND12_COMPARE6_Msk (0x1UL << GRTC_INTPEND12_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
35807   #define GRTC_INTPEND12_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
35808   #define GRTC_INTPEND12_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
35809   #define GRTC_INTPEND12_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35810   #define GRTC_INTPEND12_COMPARE6_Pending (0x1UL)    /*!< Read: Pending                                                        */
35811 
35812 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
35813   #define GRTC_INTPEND12_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
35814   #define GRTC_INTPEND12_COMPARE7_Msk (0x1UL << GRTC_INTPEND12_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
35815   #define GRTC_INTPEND12_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
35816   #define GRTC_INTPEND12_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
35817   #define GRTC_INTPEND12_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35818   #define GRTC_INTPEND12_COMPARE7_Pending (0x1UL)    /*!< Read: Pending                                                        */
35819 
35820 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
35821   #define GRTC_INTPEND12_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
35822   #define GRTC_INTPEND12_COMPARE8_Msk (0x1UL << GRTC_INTPEND12_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
35823   #define GRTC_INTPEND12_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
35824   #define GRTC_INTPEND12_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
35825   #define GRTC_INTPEND12_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35826   #define GRTC_INTPEND12_COMPARE8_Pending (0x1UL)    /*!< Read: Pending                                                        */
35827 
35828 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
35829   #define GRTC_INTPEND12_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
35830   #define GRTC_INTPEND12_COMPARE9_Msk (0x1UL << GRTC_INTPEND12_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
35831   #define GRTC_INTPEND12_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
35832   #define GRTC_INTPEND12_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
35833   #define GRTC_INTPEND12_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending                                                    */
35834   #define GRTC_INTPEND12_COMPARE9_Pending (0x1UL)    /*!< Read: Pending                                                        */
35835 
35836 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
35837   #define GRTC_INTPEND12_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
35838   #define GRTC_INTPEND12_COMPARE10_Msk (0x1UL << GRTC_INTPEND12_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
35839   #define GRTC_INTPEND12_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
35840   #define GRTC_INTPEND12_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
35841   #define GRTC_INTPEND12_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35842   #define GRTC_INTPEND12_COMPARE10_Pending (0x1UL)   /*!< Read: Pending                                                        */
35843 
35844 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
35845   #define GRTC_INTPEND12_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
35846   #define GRTC_INTPEND12_COMPARE11_Msk (0x1UL << GRTC_INTPEND12_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
35847   #define GRTC_INTPEND12_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
35848   #define GRTC_INTPEND12_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
35849   #define GRTC_INTPEND12_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35850   #define GRTC_INTPEND12_COMPARE11_Pending (0x1UL)   /*!< Read: Pending                                                        */
35851 
35852 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
35853   #define GRTC_INTPEND12_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
35854   #define GRTC_INTPEND12_COMPARE12_Msk (0x1UL << GRTC_INTPEND12_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
35855   #define GRTC_INTPEND12_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
35856   #define GRTC_INTPEND12_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
35857   #define GRTC_INTPEND12_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35858   #define GRTC_INTPEND12_COMPARE12_Pending (0x1UL)   /*!< Read: Pending                                                        */
35859 
35860 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
35861   #define GRTC_INTPEND12_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
35862   #define GRTC_INTPEND12_COMPARE13_Msk (0x1UL << GRTC_INTPEND12_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
35863   #define GRTC_INTPEND12_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
35864   #define GRTC_INTPEND12_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
35865   #define GRTC_INTPEND12_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35866   #define GRTC_INTPEND12_COMPARE13_Pending (0x1UL)   /*!< Read: Pending                                                        */
35867 
35868 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
35869   #define GRTC_INTPEND12_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
35870   #define GRTC_INTPEND12_COMPARE14_Msk (0x1UL << GRTC_INTPEND12_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
35871   #define GRTC_INTPEND12_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
35872   #define GRTC_INTPEND12_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
35873   #define GRTC_INTPEND12_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35874   #define GRTC_INTPEND12_COMPARE14_Pending (0x1UL)   /*!< Read: Pending                                                        */
35875 
35876 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
35877   #define GRTC_INTPEND12_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
35878   #define GRTC_INTPEND12_COMPARE15_Msk (0x1UL << GRTC_INTPEND12_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
35879   #define GRTC_INTPEND12_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
35880   #define GRTC_INTPEND12_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
35881   #define GRTC_INTPEND12_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                   */
35882   #define GRTC_INTPEND12_COMPARE15_Pending (0x1UL)   /*!< Read: Pending                                                        */
35883 
35884 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
35885   #define GRTC_INTPEND12_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
35886   #define GRTC_INTPEND12_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND12_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
35887                                                                             field.*/
35888   #define GRTC_INTPEND12_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
35889   #define GRTC_INTPEND12_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
35890   #define GRTC_INTPEND12_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                             */
35891   #define GRTC_INTPEND12_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                    */
35892 
35893 
35894 /* GRTC_INTEN13: Enable or disable interrupt */
35895   #define GRTC_INTEN13_ResetValue (0x00000000UL)     /*!< Reset value of INTEN13 register.                                     */
35896 
35897 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
35898   #define GRTC_INTEN13_COMPARE0_Pos (0UL)            /*!< Position of COMPARE0 field.                                          */
35899   #define GRTC_INTEN13_COMPARE0_Msk (0x1UL << GRTC_INTEN13_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
35900   #define GRTC_INTEN13_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
35901   #define GRTC_INTEN13_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
35902   #define GRTC_INTEN13_COMPARE0_Disabled (0x0UL)     /*!< Disable                                                              */
35903   #define GRTC_INTEN13_COMPARE0_Enabled (0x1UL)      /*!< Enable                                                               */
35904 
35905 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
35906   #define GRTC_INTEN13_COMPARE1_Pos (1UL)            /*!< Position of COMPARE1 field.                                          */
35907   #define GRTC_INTEN13_COMPARE1_Msk (0x1UL << GRTC_INTEN13_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
35908   #define GRTC_INTEN13_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
35909   #define GRTC_INTEN13_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
35910   #define GRTC_INTEN13_COMPARE1_Disabled (0x0UL)     /*!< Disable                                                              */
35911   #define GRTC_INTEN13_COMPARE1_Enabled (0x1UL)      /*!< Enable                                                               */
35912 
35913 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
35914   #define GRTC_INTEN13_COMPARE2_Pos (2UL)            /*!< Position of COMPARE2 field.                                          */
35915   #define GRTC_INTEN13_COMPARE2_Msk (0x1UL << GRTC_INTEN13_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
35916   #define GRTC_INTEN13_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
35917   #define GRTC_INTEN13_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
35918   #define GRTC_INTEN13_COMPARE2_Disabled (0x0UL)     /*!< Disable                                                              */
35919   #define GRTC_INTEN13_COMPARE2_Enabled (0x1UL)      /*!< Enable                                                               */
35920 
35921 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
35922   #define GRTC_INTEN13_COMPARE3_Pos (3UL)            /*!< Position of COMPARE3 field.                                          */
35923   #define GRTC_INTEN13_COMPARE3_Msk (0x1UL << GRTC_INTEN13_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
35924   #define GRTC_INTEN13_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
35925   #define GRTC_INTEN13_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
35926   #define GRTC_INTEN13_COMPARE3_Disabled (0x0UL)     /*!< Disable                                                              */
35927   #define GRTC_INTEN13_COMPARE3_Enabled (0x1UL)      /*!< Enable                                                               */
35928 
35929 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
35930   #define GRTC_INTEN13_COMPARE4_Pos (4UL)            /*!< Position of COMPARE4 field.                                          */
35931   #define GRTC_INTEN13_COMPARE4_Msk (0x1UL << GRTC_INTEN13_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
35932   #define GRTC_INTEN13_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
35933   #define GRTC_INTEN13_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
35934   #define GRTC_INTEN13_COMPARE4_Disabled (0x0UL)     /*!< Disable                                                              */
35935   #define GRTC_INTEN13_COMPARE4_Enabled (0x1UL)      /*!< Enable                                                               */
35936 
35937 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
35938   #define GRTC_INTEN13_COMPARE5_Pos (5UL)            /*!< Position of COMPARE5 field.                                          */
35939   #define GRTC_INTEN13_COMPARE5_Msk (0x1UL << GRTC_INTEN13_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
35940   #define GRTC_INTEN13_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
35941   #define GRTC_INTEN13_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
35942   #define GRTC_INTEN13_COMPARE5_Disabled (0x0UL)     /*!< Disable                                                              */
35943   #define GRTC_INTEN13_COMPARE5_Enabled (0x1UL)      /*!< Enable                                                               */
35944 
35945 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
35946   #define GRTC_INTEN13_COMPARE6_Pos (6UL)            /*!< Position of COMPARE6 field.                                          */
35947   #define GRTC_INTEN13_COMPARE6_Msk (0x1UL << GRTC_INTEN13_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
35948   #define GRTC_INTEN13_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
35949   #define GRTC_INTEN13_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
35950   #define GRTC_INTEN13_COMPARE6_Disabled (0x0UL)     /*!< Disable                                                              */
35951   #define GRTC_INTEN13_COMPARE6_Enabled (0x1UL)      /*!< Enable                                                               */
35952 
35953 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
35954   #define GRTC_INTEN13_COMPARE7_Pos (7UL)            /*!< Position of COMPARE7 field.                                          */
35955   #define GRTC_INTEN13_COMPARE7_Msk (0x1UL << GRTC_INTEN13_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
35956   #define GRTC_INTEN13_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
35957   #define GRTC_INTEN13_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
35958   #define GRTC_INTEN13_COMPARE7_Disabled (0x0UL)     /*!< Disable                                                              */
35959   #define GRTC_INTEN13_COMPARE7_Enabled (0x1UL)      /*!< Enable                                                               */
35960 
35961 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
35962   #define GRTC_INTEN13_COMPARE8_Pos (8UL)            /*!< Position of COMPARE8 field.                                          */
35963   #define GRTC_INTEN13_COMPARE8_Msk (0x1UL << GRTC_INTEN13_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                      */
35964   #define GRTC_INTEN13_COMPARE8_Min (0x0UL)          /*!< Min enumerator value of COMPARE8 field.                              */
35965   #define GRTC_INTEN13_COMPARE8_Max (0x1UL)          /*!< Max enumerator value of COMPARE8 field.                              */
35966   #define GRTC_INTEN13_COMPARE8_Disabled (0x0UL)     /*!< Disable                                                              */
35967   #define GRTC_INTEN13_COMPARE8_Enabled (0x1UL)      /*!< Enable                                                               */
35968 
35969 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
35970   #define GRTC_INTEN13_COMPARE9_Pos (9UL)            /*!< Position of COMPARE9 field.                                          */
35971   #define GRTC_INTEN13_COMPARE9_Msk (0x1UL << GRTC_INTEN13_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                      */
35972   #define GRTC_INTEN13_COMPARE9_Min (0x0UL)          /*!< Min enumerator value of COMPARE9 field.                              */
35973   #define GRTC_INTEN13_COMPARE9_Max (0x1UL)          /*!< Max enumerator value of COMPARE9 field.                              */
35974   #define GRTC_INTEN13_COMPARE9_Disabled (0x0UL)     /*!< Disable                                                              */
35975   #define GRTC_INTEN13_COMPARE9_Enabled (0x1UL)      /*!< Enable                                                               */
35976 
35977 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
35978   #define GRTC_INTEN13_COMPARE10_Pos (10UL)          /*!< Position of COMPARE10 field.                                         */
35979   #define GRTC_INTEN13_COMPARE10_Msk (0x1UL << GRTC_INTEN13_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                   */
35980   #define GRTC_INTEN13_COMPARE10_Min (0x0UL)         /*!< Min enumerator value of COMPARE10 field.                             */
35981   #define GRTC_INTEN13_COMPARE10_Max (0x1UL)         /*!< Max enumerator value of COMPARE10 field.                             */
35982   #define GRTC_INTEN13_COMPARE10_Disabled (0x0UL)    /*!< Disable                                                              */
35983   #define GRTC_INTEN13_COMPARE10_Enabled (0x1UL)     /*!< Enable                                                               */
35984 
35985 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
35986   #define GRTC_INTEN13_COMPARE11_Pos (11UL)          /*!< Position of COMPARE11 field.                                         */
35987   #define GRTC_INTEN13_COMPARE11_Msk (0x1UL << GRTC_INTEN13_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                   */
35988   #define GRTC_INTEN13_COMPARE11_Min (0x0UL)         /*!< Min enumerator value of COMPARE11 field.                             */
35989   #define GRTC_INTEN13_COMPARE11_Max (0x1UL)         /*!< Max enumerator value of COMPARE11 field.                             */
35990   #define GRTC_INTEN13_COMPARE11_Disabled (0x0UL)    /*!< Disable                                                              */
35991   #define GRTC_INTEN13_COMPARE11_Enabled (0x1UL)     /*!< Enable                                                               */
35992 
35993 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
35994   #define GRTC_INTEN13_COMPARE12_Pos (12UL)          /*!< Position of COMPARE12 field.                                         */
35995   #define GRTC_INTEN13_COMPARE12_Msk (0x1UL << GRTC_INTEN13_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                   */
35996   #define GRTC_INTEN13_COMPARE12_Min (0x0UL)         /*!< Min enumerator value of COMPARE12 field.                             */
35997   #define GRTC_INTEN13_COMPARE12_Max (0x1UL)         /*!< Max enumerator value of COMPARE12 field.                             */
35998   #define GRTC_INTEN13_COMPARE12_Disabled (0x0UL)    /*!< Disable                                                              */
35999   #define GRTC_INTEN13_COMPARE12_Enabled (0x1UL)     /*!< Enable                                                               */
36000 
36001 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
36002   #define GRTC_INTEN13_COMPARE13_Pos (13UL)          /*!< Position of COMPARE13 field.                                         */
36003   #define GRTC_INTEN13_COMPARE13_Msk (0x1UL << GRTC_INTEN13_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                   */
36004   #define GRTC_INTEN13_COMPARE13_Min (0x0UL)         /*!< Min enumerator value of COMPARE13 field.                             */
36005   #define GRTC_INTEN13_COMPARE13_Max (0x1UL)         /*!< Max enumerator value of COMPARE13 field.                             */
36006   #define GRTC_INTEN13_COMPARE13_Disabled (0x0UL)    /*!< Disable                                                              */
36007   #define GRTC_INTEN13_COMPARE13_Enabled (0x1UL)     /*!< Enable                                                               */
36008 
36009 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
36010   #define GRTC_INTEN13_COMPARE14_Pos (14UL)          /*!< Position of COMPARE14 field.                                         */
36011   #define GRTC_INTEN13_COMPARE14_Msk (0x1UL << GRTC_INTEN13_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                   */
36012   #define GRTC_INTEN13_COMPARE14_Min (0x0UL)         /*!< Min enumerator value of COMPARE14 field.                             */
36013   #define GRTC_INTEN13_COMPARE14_Max (0x1UL)         /*!< Max enumerator value of COMPARE14 field.                             */
36014   #define GRTC_INTEN13_COMPARE14_Disabled (0x0UL)    /*!< Disable                                                              */
36015   #define GRTC_INTEN13_COMPARE14_Enabled (0x1UL)     /*!< Enable                                                               */
36016 
36017 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
36018   #define GRTC_INTEN13_COMPARE15_Pos (15UL)          /*!< Position of COMPARE15 field.                                         */
36019   #define GRTC_INTEN13_COMPARE15_Msk (0x1UL << GRTC_INTEN13_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                   */
36020   #define GRTC_INTEN13_COMPARE15_Min (0x0UL)         /*!< Min enumerator value of COMPARE15 field.                             */
36021   #define GRTC_INTEN13_COMPARE15_Max (0x1UL)         /*!< Max enumerator value of COMPARE15 field.                             */
36022   #define GRTC_INTEN13_COMPARE15_Disabled (0x0UL)    /*!< Disable                                                              */
36023   #define GRTC_INTEN13_COMPARE15_Enabled (0x1UL)     /*!< Enable                                                               */
36024 
36025 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
36026   #define GRTC_INTEN13_SYSCOUNTERVALID_Pos (26UL)    /*!< Position of SYSCOUNTERVALID field.                                   */
36027   #define GRTC_INTEN13_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN13_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */
36028   #define GRTC_INTEN13_SYSCOUNTERVALID_Min (0x0UL)   /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
36029   #define GRTC_INTEN13_SYSCOUNTERVALID_Max (0x1UL)   /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
36030   #define GRTC_INTEN13_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                           */
36031   #define GRTC_INTEN13_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                             */
36032 
36033 
36034 /* GRTC_INTENSET13: Enable interrupt */
36035   #define GRTC_INTENSET13_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET13 register.                                  */
36036 
36037 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
36038   #define GRTC_INTENSET13_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
36039   #define GRTC_INTENSET13_COMPARE0_Msk (0x1UL << GRTC_INTENSET13_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
36040   #define GRTC_INTENSET13_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
36041   #define GRTC_INTENSET13_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
36042   #define GRTC_INTENSET13_COMPARE0_Set (0x1UL)       /*!< Enable                                                               */
36043   #define GRTC_INTENSET13_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36044   #define GRTC_INTENSET13_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36045 
36046 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
36047   #define GRTC_INTENSET13_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
36048   #define GRTC_INTENSET13_COMPARE1_Msk (0x1UL << GRTC_INTENSET13_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
36049   #define GRTC_INTENSET13_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
36050   #define GRTC_INTENSET13_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
36051   #define GRTC_INTENSET13_COMPARE1_Set (0x1UL)       /*!< Enable                                                               */
36052   #define GRTC_INTENSET13_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36053   #define GRTC_INTENSET13_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36054 
36055 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
36056   #define GRTC_INTENSET13_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
36057   #define GRTC_INTENSET13_COMPARE2_Msk (0x1UL << GRTC_INTENSET13_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
36058   #define GRTC_INTENSET13_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
36059   #define GRTC_INTENSET13_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
36060   #define GRTC_INTENSET13_COMPARE2_Set (0x1UL)       /*!< Enable                                                               */
36061   #define GRTC_INTENSET13_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36062   #define GRTC_INTENSET13_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36063 
36064 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
36065   #define GRTC_INTENSET13_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
36066   #define GRTC_INTENSET13_COMPARE3_Msk (0x1UL << GRTC_INTENSET13_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
36067   #define GRTC_INTENSET13_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
36068   #define GRTC_INTENSET13_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
36069   #define GRTC_INTENSET13_COMPARE3_Set (0x1UL)       /*!< Enable                                                               */
36070   #define GRTC_INTENSET13_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36071   #define GRTC_INTENSET13_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36072 
36073 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
36074   #define GRTC_INTENSET13_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
36075   #define GRTC_INTENSET13_COMPARE4_Msk (0x1UL << GRTC_INTENSET13_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
36076   #define GRTC_INTENSET13_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
36077   #define GRTC_INTENSET13_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
36078   #define GRTC_INTENSET13_COMPARE4_Set (0x1UL)       /*!< Enable                                                               */
36079   #define GRTC_INTENSET13_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36080   #define GRTC_INTENSET13_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36081 
36082 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
36083   #define GRTC_INTENSET13_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
36084   #define GRTC_INTENSET13_COMPARE5_Msk (0x1UL << GRTC_INTENSET13_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
36085   #define GRTC_INTENSET13_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
36086   #define GRTC_INTENSET13_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
36087   #define GRTC_INTENSET13_COMPARE5_Set (0x1UL)       /*!< Enable                                                               */
36088   #define GRTC_INTENSET13_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36089   #define GRTC_INTENSET13_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36090 
36091 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
36092   #define GRTC_INTENSET13_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
36093   #define GRTC_INTENSET13_COMPARE6_Msk (0x1UL << GRTC_INTENSET13_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
36094   #define GRTC_INTENSET13_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
36095   #define GRTC_INTENSET13_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
36096   #define GRTC_INTENSET13_COMPARE6_Set (0x1UL)       /*!< Enable                                                               */
36097   #define GRTC_INTENSET13_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36098   #define GRTC_INTENSET13_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36099 
36100 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
36101   #define GRTC_INTENSET13_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
36102   #define GRTC_INTENSET13_COMPARE7_Msk (0x1UL << GRTC_INTENSET13_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
36103   #define GRTC_INTENSET13_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
36104   #define GRTC_INTENSET13_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
36105   #define GRTC_INTENSET13_COMPARE7_Set (0x1UL)       /*!< Enable                                                               */
36106   #define GRTC_INTENSET13_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36107   #define GRTC_INTENSET13_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36108 
36109 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
36110   #define GRTC_INTENSET13_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
36111   #define GRTC_INTENSET13_COMPARE8_Msk (0x1UL << GRTC_INTENSET13_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
36112   #define GRTC_INTENSET13_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
36113   #define GRTC_INTENSET13_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
36114   #define GRTC_INTENSET13_COMPARE8_Set (0x1UL)       /*!< Enable                                                               */
36115   #define GRTC_INTENSET13_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36116   #define GRTC_INTENSET13_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36117 
36118 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
36119   #define GRTC_INTENSET13_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
36120   #define GRTC_INTENSET13_COMPARE9_Msk (0x1UL << GRTC_INTENSET13_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
36121   #define GRTC_INTENSET13_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
36122   #define GRTC_INTENSET13_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
36123   #define GRTC_INTENSET13_COMPARE9_Set (0x1UL)       /*!< Enable                                                               */
36124   #define GRTC_INTENSET13_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36125   #define GRTC_INTENSET13_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36126 
36127 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
36128   #define GRTC_INTENSET13_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
36129   #define GRTC_INTENSET13_COMPARE10_Msk (0x1UL << GRTC_INTENSET13_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
36130   #define GRTC_INTENSET13_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
36131   #define GRTC_INTENSET13_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
36132   #define GRTC_INTENSET13_COMPARE10_Set (0x1UL)      /*!< Enable                                                               */
36133   #define GRTC_INTENSET13_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36134   #define GRTC_INTENSET13_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36135 
36136 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
36137   #define GRTC_INTENSET13_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
36138   #define GRTC_INTENSET13_COMPARE11_Msk (0x1UL << GRTC_INTENSET13_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
36139   #define GRTC_INTENSET13_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
36140   #define GRTC_INTENSET13_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
36141   #define GRTC_INTENSET13_COMPARE11_Set (0x1UL)      /*!< Enable                                                               */
36142   #define GRTC_INTENSET13_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36143   #define GRTC_INTENSET13_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36144 
36145 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
36146   #define GRTC_INTENSET13_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
36147   #define GRTC_INTENSET13_COMPARE12_Msk (0x1UL << GRTC_INTENSET13_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
36148   #define GRTC_INTENSET13_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
36149   #define GRTC_INTENSET13_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
36150   #define GRTC_INTENSET13_COMPARE12_Set (0x1UL)      /*!< Enable                                                               */
36151   #define GRTC_INTENSET13_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36152   #define GRTC_INTENSET13_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36153 
36154 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
36155   #define GRTC_INTENSET13_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
36156   #define GRTC_INTENSET13_COMPARE13_Msk (0x1UL << GRTC_INTENSET13_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
36157   #define GRTC_INTENSET13_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
36158   #define GRTC_INTENSET13_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
36159   #define GRTC_INTENSET13_COMPARE13_Set (0x1UL)      /*!< Enable                                                               */
36160   #define GRTC_INTENSET13_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36161   #define GRTC_INTENSET13_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36162 
36163 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
36164   #define GRTC_INTENSET13_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
36165   #define GRTC_INTENSET13_COMPARE14_Msk (0x1UL << GRTC_INTENSET13_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
36166   #define GRTC_INTENSET13_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
36167   #define GRTC_INTENSET13_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
36168   #define GRTC_INTENSET13_COMPARE14_Set (0x1UL)      /*!< Enable                                                               */
36169   #define GRTC_INTENSET13_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36170   #define GRTC_INTENSET13_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36171 
36172 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
36173   #define GRTC_INTENSET13_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
36174   #define GRTC_INTENSET13_COMPARE15_Msk (0x1UL << GRTC_INTENSET13_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
36175   #define GRTC_INTENSET13_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
36176   #define GRTC_INTENSET13_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
36177   #define GRTC_INTENSET13_COMPARE15_Set (0x1UL)      /*!< Enable                                                               */
36178   #define GRTC_INTENSET13_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36179   #define GRTC_INTENSET13_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36180 
36181 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
36182   #define GRTC_INTENSET13_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
36183   #define GRTC_INTENSET13_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET13_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
36184                                                                             field.*/
36185   #define GRTC_INTENSET13_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
36186   #define GRTC_INTENSET13_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
36187   #define GRTC_INTENSET13_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                              */
36188   #define GRTC_INTENSET13_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
36189   #define GRTC_INTENSET13_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
36190 
36191 
36192 /* GRTC_INTENCLR13: Disable interrupt */
36193   #define GRTC_INTENCLR13_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR13 register.                                  */
36194 
36195 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
36196   #define GRTC_INTENCLR13_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
36197   #define GRTC_INTENCLR13_COMPARE0_Msk (0x1UL << GRTC_INTENCLR13_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
36198   #define GRTC_INTENCLR13_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
36199   #define GRTC_INTENCLR13_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
36200   #define GRTC_INTENCLR13_COMPARE0_Clear (0x1UL)     /*!< Disable                                                              */
36201   #define GRTC_INTENCLR13_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36202   #define GRTC_INTENCLR13_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36203 
36204 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
36205   #define GRTC_INTENCLR13_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
36206   #define GRTC_INTENCLR13_COMPARE1_Msk (0x1UL << GRTC_INTENCLR13_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
36207   #define GRTC_INTENCLR13_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
36208   #define GRTC_INTENCLR13_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
36209   #define GRTC_INTENCLR13_COMPARE1_Clear (0x1UL)     /*!< Disable                                                              */
36210   #define GRTC_INTENCLR13_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36211   #define GRTC_INTENCLR13_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36212 
36213 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
36214   #define GRTC_INTENCLR13_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
36215   #define GRTC_INTENCLR13_COMPARE2_Msk (0x1UL << GRTC_INTENCLR13_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
36216   #define GRTC_INTENCLR13_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
36217   #define GRTC_INTENCLR13_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
36218   #define GRTC_INTENCLR13_COMPARE2_Clear (0x1UL)     /*!< Disable                                                              */
36219   #define GRTC_INTENCLR13_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36220   #define GRTC_INTENCLR13_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36221 
36222 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
36223   #define GRTC_INTENCLR13_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
36224   #define GRTC_INTENCLR13_COMPARE3_Msk (0x1UL << GRTC_INTENCLR13_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
36225   #define GRTC_INTENCLR13_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
36226   #define GRTC_INTENCLR13_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
36227   #define GRTC_INTENCLR13_COMPARE3_Clear (0x1UL)     /*!< Disable                                                              */
36228   #define GRTC_INTENCLR13_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36229   #define GRTC_INTENCLR13_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36230 
36231 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
36232   #define GRTC_INTENCLR13_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
36233   #define GRTC_INTENCLR13_COMPARE4_Msk (0x1UL << GRTC_INTENCLR13_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
36234   #define GRTC_INTENCLR13_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
36235   #define GRTC_INTENCLR13_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
36236   #define GRTC_INTENCLR13_COMPARE4_Clear (0x1UL)     /*!< Disable                                                              */
36237   #define GRTC_INTENCLR13_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36238   #define GRTC_INTENCLR13_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36239 
36240 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
36241   #define GRTC_INTENCLR13_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
36242   #define GRTC_INTENCLR13_COMPARE5_Msk (0x1UL << GRTC_INTENCLR13_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
36243   #define GRTC_INTENCLR13_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
36244   #define GRTC_INTENCLR13_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
36245   #define GRTC_INTENCLR13_COMPARE5_Clear (0x1UL)     /*!< Disable                                                              */
36246   #define GRTC_INTENCLR13_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36247   #define GRTC_INTENCLR13_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36248 
36249 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
36250   #define GRTC_INTENCLR13_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
36251   #define GRTC_INTENCLR13_COMPARE6_Msk (0x1UL << GRTC_INTENCLR13_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
36252   #define GRTC_INTENCLR13_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
36253   #define GRTC_INTENCLR13_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
36254   #define GRTC_INTENCLR13_COMPARE6_Clear (0x1UL)     /*!< Disable                                                              */
36255   #define GRTC_INTENCLR13_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36256   #define GRTC_INTENCLR13_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36257 
36258 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
36259   #define GRTC_INTENCLR13_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
36260   #define GRTC_INTENCLR13_COMPARE7_Msk (0x1UL << GRTC_INTENCLR13_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
36261   #define GRTC_INTENCLR13_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
36262   #define GRTC_INTENCLR13_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
36263   #define GRTC_INTENCLR13_COMPARE7_Clear (0x1UL)     /*!< Disable                                                              */
36264   #define GRTC_INTENCLR13_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36265   #define GRTC_INTENCLR13_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36266 
36267 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
36268   #define GRTC_INTENCLR13_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
36269   #define GRTC_INTENCLR13_COMPARE8_Msk (0x1UL << GRTC_INTENCLR13_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
36270   #define GRTC_INTENCLR13_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
36271   #define GRTC_INTENCLR13_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
36272   #define GRTC_INTENCLR13_COMPARE8_Clear (0x1UL)     /*!< Disable                                                              */
36273   #define GRTC_INTENCLR13_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36274   #define GRTC_INTENCLR13_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36275 
36276 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
36277   #define GRTC_INTENCLR13_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
36278   #define GRTC_INTENCLR13_COMPARE9_Msk (0x1UL << GRTC_INTENCLR13_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
36279   #define GRTC_INTENCLR13_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
36280   #define GRTC_INTENCLR13_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
36281   #define GRTC_INTENCLR13_COMPARE9_Clear (0x1UL)     /*!< Disable                                                              */
36282   #define GRTC_INTENCLR13_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36283   #define GRTC_INTENCLR13_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36284 
36285 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
36286   #define GRTC_INTENCLR13_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
36287   #define GRTC_INTENCLR13_COMPARE10_Msk (0x1UL << GRTC_INTENCLR13_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
36288   #define GRTC_INTENCLR13_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
36289   #define GRTC_INTENCLR13_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
36290   #define GRTC_INTENCLR13_COMPARE10_Clear (0x1UL)    /*!< Disable                                                              */
36291   #define GRTC_INTENCLR13_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36292   #define GRTC_INTENCLR13_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36293 
36294 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
36295   #define GRTC_INTENCLR13_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
36296   #define GRTC_INTENCLR13_COMPARE11_Msk (0x1UL << GRTC_INTENCLR13_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
36297   #define GRTC_INTENCLR13_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
36298   #define GRTC_INTENCLR13_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
36299   #define GRTC_INTENCLR13_COMPARE11_Clear (0x1UL)    /*!< Disable                                                              */
36300   #define GRTC_INTENCLR13_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36301   #define GRTC_INTENCLR13_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36302 
36303 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
36304   #define GRTC_INTENCLR13_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
36305   #define GRTC_INTENCLR13_COMPARE12_Msk (0x1UL << GRTC_INTENCLR13_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
36306   #define GRTC_INTENCLR13_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
36307   #define GRTC_INTENCLR13_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
36308   #define GRTC_INTENCLR13_COMPARE12_Clear (0x1UL)    /*!< Disable                                                              */
36309   #define GRTC_INTENCLR13_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36310   #define GRTC_INTENCLR13_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36311 
36312 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
36313   #define GRTC_INTENCLR13_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
36314   #define GRTC_INTENCLR13_COMPARE13_Msk (0x1UL << GRTC_INTENCLR13_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
36315   #define GRTC_INTENCLR13_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
36316   #define GRTC_INTENCLR13_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
36317   #define GRTC_INTENCLR13_COMPARE13_Clear (0x1UL)    /*!< Disable                                                              */
36318   #define GRTC_INTENCLR13_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36319   #define GRTC_INTENCLR13_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36320 
36321 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
36322   #define GRTC_INTENCLR13_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
36323   #define GRTC_INTENCLR13_COMPARE14_Msk (0x1UL << GRTC_INTENCLR13_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
36324   #define GRTC_INTENCLR13_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
36325   #define GRTC_INTENCLR13_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
36326   #define GRTC_INTENCLR13_COMPARE14_Clear (0x1UL)    /*!< Disable                                                              */
36327   #define GRTC_INTENCLR13_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36328   #define GRTC_INTENCLR13_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36329 
36330 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
36331   #define GRTC_INTENCLR13_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
36332   #define GRTC_INTENCLR13_COMPARE15_Msk (0x1UL << GRTC_INTENCLR13_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
36333   #define GRTC_INTENCLR13_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
36334   #define GRTC_INTENCLR13_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
36335   #define GRTC_INTENCLR13_COMPARE15_Clear (0x1UL)    /*!< Disable                                                              */
36336   #define GRTC_INTENCLR13_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36337   #define GRTC_INTENCLR13_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36338 
36339 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
36340   #define GRTC_INTENCLR13_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
36341   #define GRTC_INTENCLR13_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR13_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
36342                                                                             field.*/
36343   #define GRTC_INTENCLR13_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
36344   #define GRTC_INTENCLR13_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
36345   #define GRTC_INTENCLR13_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                           */
36346   #define GRTC_INTENCLR13_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
36347   #define GRTC_INTENCLR13_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
36348 
36349 
36350 /* GRTC_INTPEND13: Pending interrupts */
36351   #define GRTC_INTPEND13_ResetValue (0x00000000UL)   /*!< Reset value of INTPEND13 register.                                   */
36352 
36353 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
36354   #define GRTC_INTPEND13_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
36355   #define GRTC_INTPEND13_COMPARE0_Msk (0x1UL << GRTC_INTPEND13_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
36356   #define GRTC_INTPEND13_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
36357   #define GRTC_INTPEND13_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
36358   #define GRTC_INTPEND13_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36359   #define GRTC_INTPEND13_COMPARE0_Pending (0x1UL)    /*!< Read: Pending                                                        */
36360 
36361 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
36362   #define GRTC_INTPEND13_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
36363   #define GRTC_INTPEND13_COMPARE1_Msk (0x1UL << GRTC_INTPEND13_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
36364   #define GRTC_INTPEND13_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
36365   #define GRTC_INTPEND13_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
36366   #define GRTC_INTPEND13_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36367   #define GRTC_INTPEND13_COMPARE1_Pending (0x1UL)    /*!< Read: Pending                                                        */
36368 
36369 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
36370   #define GRTC_INTPEND13_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
36371   #define GRTC_INTPEND13_COMPARE2_Msk (0x1UL << GRTC_INTPEND13_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
36372   #define GRTC_INTPEND13_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
36373   #define GRTC_INTPEND13_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
36374   #define GRTC_INTPEND13_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36375   #define GRTC_INTPEND13_COMPARE2_Pending (0x1UL)    /*!< Read: Pending                                                        */
36376 
36377 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
36378   #define GRTC_INTPEND13_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
36379   #define GRTC_INTPEND13_COMPARE3_Msk (0x1UL << GRTC_INTPEND13_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
36380   #define GRTC_INTPEND13_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
36381   #define GRTC_INTPEND13_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
36382   #define GRTC_INTPEND13_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36383   #define GRTC_INTPEND13_COMPARE3_Pending (0x1UL)    /*!< Read: Pending                                                        */
36384 
36385 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
36386   #define GRTC_INTPEND13_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
36387   #define GRTC_INTPEND13_COMPARE4_Msk (0x1UL << GRTC_INTPEND13_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
36388   #define GRTC_INTPEND13_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
36389   #define GRTC_INTPEND13_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
36390   #define GRTC_INTPEND13_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36391   #define GRTC_INTPEND13_COMPARE4_Pending (0x1UL)    /*!< Read: Pending                                                        */
36392 
36393 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
36394   #define GRTC_INTPEND13_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
36395   #define GRTC_INTPEND13_COMPARE5_Msk (0x1UL << GRTC_INTPEND13_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
36396   #define GRTC_INTPEND13_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
36397   #define GRTC_INTPEND13_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
36398   #define GRTC_INTPEND13_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36399   #define GRTC_INTPEND13_COMPARE5_Pending (0x1UL)    /*!< Read: Pending                                                        */
36400 
36401 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
36402   #define GRTC_INTPEND13_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
36403   #define GRTC_INTPEND13_COMPARE6_Msk (0x1UL << GRTC_INTPEND13_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
36404   #define GRTC_INTPEND13_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
36405   #define GRTC_INTPEND13_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
36406   #define GRTC_INTPEND13_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36407   #define GRTC_INTPEND13_COMPARE6_Pending (0x1UL)    /*!< Read: Pending                                                        */
36408 
36409 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
36410   #define GRTC_INTPEND13_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
36411   #define GRTC_INTPEND13_COMPARE7_Msk (0x1UL << GRTC_INTPEND13_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
36412   #define GRTC_INTPEND13_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
36413   #define GRTC_INTPEND13_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
36414   #define GRTC_INTPEND13_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36415   #define GRTC_INTPEND13_COMPARE7_Pending (0x1UL)    /*!< Read: Pending                                                        */
36416 
36417 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
36418   #define GRTC_INTPEND13_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
36419   #define GRTC_INTPEND13_COMPARE8_Msk (0x1UL << GRTC_INTPEND13_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
36420   #define GRTC_INTPEND13_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
36421   #define GRTC_INTPEND13_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
36422   #define GRTC_INTPEND13_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36423   #define GRTC_INTPEND13_COMPARE8_Pending (0x1UL)    /*!< Read: Pending                                                        */
36424 
36425 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
36426   #define GRTC_INTPEND13_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
36427   #define GRTC_INTPEND13_COMPARE9_Msk (0x1UL << GRTC_INTPEND13_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
36428   #define GRTC_INTPEND13_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
36429   #define GRTC_INTPEND13_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
36430   #define GRTC_INTPEND13_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36431   #define GRTC_INTPEND13_COMPARE9_Pending (0x1UL)    /*!< Read: Pending                                                        */
36432 
36433 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
36434   #define GRTC_INTPEND13_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
36435   #define GRTC_INTPEND13_COMPARE10_Msk (0x1UL << GRTC_INTPEND13_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
36436   #define GRTC_INTPEND13_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
36437   #define GRTC_INTPEND13_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
36438   #define GRTC_INTPEND13_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                   */
36439   #define GRTC_INTPEND13_COMPARE10_Pending (0x1UL)   /*!< Read: Pending                                                        */
36440 
36441 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
36442   #define GRTC_INTPEND13_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
36443   #define GRTC_INTPEND13_COMPARE11_Msk (0x1UL << GRTC_INTPEND13_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
36444   #define GRTC_INTPEND13_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
36445   #define GRTC_INTPEND13_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
36446   #define GRTC_INTPEND13_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                   */
36447   #define GRTC_INTPEND13_COMPARE11_Pending (0x1UL)   /*!< Read: Pending                                                        */
36448 
36449 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
36450   #define GRTC_INTPEND13_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
36451   #define GRTC_INTPEND13_COMPARE12_Msk (0x1UL << GRTC_INTPEND13_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
36452   #define GRTC_INTPEND13_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
36453   #define GRTC_INTPEND13_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
36454   #define GRTC_INTPEND13_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                   */
36455   #define GRTC_INTPEND13_COMPARE12_Pending (0x1UL)   /*!< Read: Pending                                                        */
36456 
36457 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
36458   #define GRTC_INTPEND13_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
36459   #define GRTC_INTPEND13_COMPARE13_Msk (0x1UL << GRTC_INTPEND13_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
36460   #define GRTC_INTPEND13_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
36461   #define GRTC_INTPEND13_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
36462   #define GRTC_INTPEND13_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                   */
36463   #define GRTC_INTPEND13_COMPARE13_Pending (0x1UL)   /*!< Read: Pending                                                        */
36464 
36465 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
36466   #define GRTC_INTPEND13_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
36467   #define GRTC_INTPEND13_COMPARE14_Msk (0x1UL << GRTC_INTPEND13_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
36468   #define GRTC_INTPEND13_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
36469   #define GRTC_INTPEND13_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
36470   #define GRTC_INTPEND13_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                   */
36471   #define GRTC_INTPEND13_COMPARE14_Pending (0x1UL)   /*!< Read: Pending                                                        */
36472 
36473 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
36474   #define GRTC_INTPEND13_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
36475   #define GRTC_INTPEND13_COMPARE15_Msk (0x1UL << GRTC_INTPEND13_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
36476   #define GRTC_INTPEND13_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
36477   #define GRTC_INTPEND13_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
36478   #define GRTC_INTPEND13_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                   */
36479   #define GRTC_INTPEND13_COMPARE15_Pending (0x1UL)   /*!< Read: Pending                                                        */
36480 
36481 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
36482   #define GRTC_INTPEND13_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
36483   #define GRTC_INTPEND13_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND13_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
36484                                                                             field.*/
36485   #define GRTC_INTPEND13_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
36486   #define GRTC_INTPEND13_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
36487   #define GRTC_INTPEND13_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                             */
36488   #define GRTC_INTPEND13_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                    */
36489 
36490 
36491 /* GRTC_INTEN14: Enable or disable interrupt */
36492   #define GRTC_INTEN14_ResetValue (0x00000000UL)     /*!< Reset value of INTEN14 register.                                     */
36493 
36494 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
36495   #define GRTC_INTEN14_COMPARE0_Pos (0UL)            /*!< Position of COMPARE0 field.                                          */
36496   #define GRTC_INTEN14_COMPARE0_Msk (0x1UL << GRTC_INTEN14_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
36497   #define GRTC_INTEN14_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
36498   #define GRTC_INTEN14_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
36499   #define GRTC_INTEN14_COMPARE0_Disabled (0x0UL)     /*!< Disable                                                              */
36500   #define GRTC_INTEN14_COMPARE0_Enabled (0x1UL)      /*!< Enable                                                               */
36501 
36502 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
36503   #define GRTC_INTEN14_COMPARE1_Pos (1UL)            /*!< Position of COMPARE1 field.                                          */
36504   #define GRTC_INTEN14_COMPARE1_Msk (0x1UL << GRTC_INTEN14_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
36505   #define GRTC_INTEN14_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
36506   #define GRTC_INTEN14_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
36507   #define GRTC_INTEN14_COMPARE1_Disabled (0x0UL)     /*!< Disable                                                              */
36508   #define GRTC_INTEN14_COMPARE1_Enabled (0x1UL)      /*!< Enable                                                               */
36509 
36510 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
36511   #define GRTC_INTEN14_COMPARE2_Pos (2UL)            /*!< Position of COMPARE2 field.                                          */
36512   #define GRTC_INTEN14_COMPARE2_Msk (0x1UL << GRTC_INTEN14_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
36513   #define GRTC_INTEN14_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
36514   #define GRTC_INTEN14_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
36515   #define GRTC_INTEN14_COMPARE2_Disabled (0x0UL)     /*!< Disable                                                              */
36516   #define GRTC_INTEN14_COMPARE2_Enabled (0x1UL)      /*!< Enable                                                               */
36517 
36518 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
36519   #define GRTC_INTEN14_COMPARE3_Pos (3UL)            /*!< Position of COMPARE3 field.                                          */
36520   #define GRTC_INTEN14_COMPARE3_Msk (0x1UL << GRTC_INTEN14_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
36521   #define GRTC_INTEN14_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
36522   #define GRTC_INTEN14_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
36523   #define GRTC_INTEN14_COMPARE3_Disabled (0x0UL)     /*!< Disable                                                              */
36524   #define GRTC_INTEN14_COMPARE3_Enabled (0x1UL)      /*!< Enable                                                               */
36525 
36526 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
36527   #define GRTC_INTEN14_COMPARE4_Pos (4UL)            /*!< Position of COMPARE4 field.                                          */
36528   #define GRTC_INTEN14_COMPARE4_Msk (0x1UL << GRTC_INTEN14_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
36529   #define GRTC_INTEN14_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
36530   #define GRTC_INTEN14_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
36531   #define GRTC_INTEN14_COMPARE4_Disabled (0x0UL)     /*!< Disable                                                              */
36532   #define GRTC_INTEN14_COMPARE4_Enabled (0x1UL)      /*!< Enable                                                               */
36533 
36534 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
36535   #define GRTC_INTEN14_COMPARE5_Pos (5UL)            /*!< Position of COMPARE5 field.                                          */
36536   #define GRTC_INTEN14_COMPARE5_Msk (0x1UL << GRTC_INTEN14_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
36537   #define GRTC_INTEN14_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
36538   #define GRTC_INTEN14_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
36539   #define GRTC_INTEN14_COMPARE5_Disabled (0x0UL)     /*!< Disable                                                              */
36540   #define GRTC_INTEN14_COMPARE5_Enabled (0x1UL)      /*!< Enable                                                               */
36541 
36542 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
36543   #define GRTC_INTEN14_COMPARE6_Pos (6UL)            /*!< Position of COMPARE6 field.                                          */
36544   #define GRTC_INTEN14_COMPARE6_Msk (0x1UL << GRTC_INTEN14_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
36545   #define GRTC_INTEN14_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
36546   #define GRTC_INTEN14_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
36547   #define GRTC_INTEN14_COMPARE6_Disabled (0x0UL)     /*!< Disable                                                              */
36548   #define GRTC_INTEN14_COMPARE6_Enabled (0x1UL)      /*!< Enable                                                               */
36549 
36550 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
36551   #define GRTC_INTEN14_COMPARE7_Pos (7UL)            /*!< Position of COMPARE7 field.                                          */
36552   #define GRTC_INTEN14_COMPARE7_Msk (0x1UL << GRTC_INTEN14_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
36553   #define GRTC_INTEN14_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
36554   #define GRTC_INTEN14_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
36555   #define GRTC_INTEN14_COMPARE7_Disabled (0x0UL)     /*!< Disable                                                              */
36556   #define GRTC_INTEN14_COMPARE7_Enabled (0x1UL)      /*!< Enable                                                               */
36557 
36558 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
36559   #define GRTC_INTEN14_COMPARE8_Pos (8UL)            /*!< Position of COMPARE8 field.                                          */
36560   #define GRTC_INTEN14_COMPARE8_Msk (0x1UL << GRTC_INTEN14_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                      */
36561   #define GRTC_INTEN14_COMPARE8_Min (0x0UL)          /*!< Min enumerator value of COMPARE8 field.                              */
36562   #define GRTC_INTEN14_COMPARE8_Max (0x1UL)          /*!< Max enumerator value of COMPARE8 field.                              */
36563   #define GRTC_INTEN14_COMPARE8_Disabled (0x0UL)     /*!< Disable                                                              */
36564   #define GRTC_INTEN14_COMPARE8_Enabled (0x1UL)      /*!< Enable                                                               */
36565 
36566 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
36567   #define GRTC_INTEN14_COMPARE9_Pos (9UL)            /*!< Position of COMPARE9 field.                                          */
36568   #define GRTC_INTEN14_COMPARE9_Msk (0x1UL << GRTC_INTEN14_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                      */
36569   #define GRTC_INTEN14_COMPARE9_Min (0x0UL)          /*!< Min enumerator value of COMPARE9 field.                              */
36570   #define GRTC_INTEN14_COMPARE9_Max (0x1UL)          /*!< Max enumerator value of COMPARE9 field.                              */
36571   #define GRTC_INTEN14_COMPARE9_Disabled (0x0UL)     /*!< Disable                                                              */
36572   #define GRTC_INTEN14_COMPARE9_Enabled (0x1UL)      /*!< Enable                                                               */
36573 
36574 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
36575   #define GRTC_INTEN14_COMPARE10_Pos (10UL)          /*!< Position of COMPARE10 field.                                         */
36576   #define GRTC_INTEN14_COMPARE10_Msk (0x1UL << GRTC_INTEN14_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                   */
36577   #define GRTC_INTEN14_COMPARE10_Min (0x0UL)         /*!< Min enumerator value of COMPARE10 field.                             */
36578   #define GRTC_INTEN14_COMPARE10_Max (0x1UL)         /*!< Max enumerator value of COMPARE10 field.                             */
36579   #define GRTC_INTEN14_COMPARE10_Disabled (0x0UL)    /*!< Disable                                                              */
36580   #define GRTC_INTEN14_COMPARE10_Enabled (0x1UL)     /*!< Enable                                                               */
36581 
36582 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
36583   #define GRTC_INTEN14_COMPARE11_Pos (11UL)          /*!< Position of COMPARE11 field.                                         */
36584   #define GRTC_INTEN14_COMPARE11_Msk (0x1UL << GRTC_INTEN14_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                   */
36585   #define GRTC_INTEN14_COMPARE11_Min (0x0UL)         /*!< Min enumerator value of COMPARE11 field.                             */
36586   #define GRTC_INTEN14_COMPARE11_Max (0x1UL)         /*!< Max enumerator value of COMPARE11 field.                             */
36587   #define GRTC_INTEN14_COMPARE11_Disabled (0x0UL)    /*!< Disable                                                              */
36588   #define GRTC_INTEN14_COMPARE11_Enabled (0x1UL)     /*!< Enable                                                               */
36589 
36590 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
36591   #define GRTC_INTEN14_COMPARE12_Pos (12UL)          /*!< Position of COMPARE12 field.                                         */
36592   #define GRTC_INTEN14_COMPARE12_Msk (0x1UL << GRTC_INTEN14_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                   */
36593   #define GRTC_INTEN14_COMPARE12_Min (0x0UL)         /*!< Min enumerator value of COMPARE12 field.                             */
36594   #define GRTC_INTEN14_COMPARE12_Max (0x1UL)         /*!< Max enumerator value of COMPARE12 field.                             */
36595   #define GRTC_INTEN14_COMPARE12_Disabled (0x0UL)    /*!< Disable                                                              */
36596   #define GRTC_INTEN14_COMPARE12_Enabled (0x1UL)     /*!< Enable                                                               */
36597 
36598 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
36599   #define GRTC_INTEN14_COMPARE13_Pos (13UL)          /*!< Position of COMPARE13 field.                                         */
36600   #define GRTC_INTEN14_COMPARE13_Msk (0x1UL << GRTC_INTEN14_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                   */
36601   #define GRTC_INTEN14_COMPARE13_Min (0x0UL)         /*!< Min enumerator value of COMPARE13 field.                             */
36602   #define GRTC_INTEN14_COMPARE13_Max (0x1UL)         /*!< Max enumerator value of COMPARE13 field.                             */
36603   #define GRTC_INTEN14_COMPARE13_Disabled (0x0UL)    /*!< Disable                                                              */
36604   #define GRTC_INTEN14_COMPARE13_Enabled (0x1UL)     /*!< Enable                                                               */
36605 
36606 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
36607   #define GRTC_INTEN14_COMPARE14_Pos (14UL)          /*!< Position of COMPARE14 field.                                         */
36608   #define GRTC_INTEN14_COMPARE14_Msk (0x1UL << GRTC_INTEN14_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                   */
36609   #define GRTC_INTEN14_COMPARE14_Min (0x0UL)         /*!< Min enumerator value of COMPARE14 field.                             */
36610   #define GRTC_INTEN14_COMPARE14_Max (0x1UL)         /*!< Max enumerator value of COMPARE14 field.                             */
36611   #define GRTC_INTEN14_COMPARE14_Disabled (0x0UL)    /*!< Disable                                                              */
36612   #define GRTC_INTEN14_COMPARE14_Enabled (0x1UL)     /*!< Enable                                                               */
36613 
36614 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
36615   #define GRTC_INTEN14_COMPARE15_Pos (15UL)          /*!< Position of COMPARE15 field.                                         */
36616   #define GRTC_INTEN14_COMPARE15_Msk (0x1UL << GRTC_INTEN14_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                   */
36617   #define GRTC_INTEN14_COMPARE15_Min (0x0UL)         /*!< Min enumerator value of COMPARE15 field.                             */
36618   #define GRTC_INTEN14_COMPARE15_Max (0x1UL)         /*!< Max enumerator value of COMPARE15 field.                             */
36619   #define GRTC_INTEN14_COMPARE15_Disabled (0x0UL)    /*!< Disable                                                              */
36620   #define GRTC_INTEN14_COMPARE15_Enabled (0x1UL)     /*!< Enable                                                               */
36621 
36622 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
36623   #define GRTC_INTEN14_SYSCOUNTERVALID_Pos (26UL)    /*!< Position of SYSCOUNTERVALID field.                                   */
36624   #define GRTC_INTEN14_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN14_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */
36625   #define GRTC_INTEN14_SYSCOUNTERVALID_Min (0x0UL)   /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
36626   #define GRTC_INTEN14_SYSCOUNTERVALID_Max (0x1UL)   /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
36627   #define GRTC_INTEN14_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                           */
36628   #define GRTC_INTEN14_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                             */
36629 
36630 
36631 /* GRTC_INTENSET14: Enable interrupt */
36632   #define GRTC_INTENSET14_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET14 register.                                  */
36633 
36634 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
36635   #define GRTC_INTENSET14_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
36636   #define GRTC_INTENSET14_COMPARE0_Msk (0x1UL << GRTC_INTENSET14_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
36637   #define GRTC_INTENSET14_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
36638   #define GRTC_INTENSET14_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
36639   #define GRTC_INTENSET14_COMPARE0_Set (0x1UL)       /*!< Enable                                                               */
36640   #define GRTC_INTENSET14_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36641   #define GRTC_INTENSET14_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36642 
36643 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
36644   #define GRTC_INTENSET14_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
36645   #define GRTC_INTENSET14_COMPARE1_Msk (0x1UL << GRTC_INTENSET14_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
36646   #define GRTC_INTENSET14_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
36647   #define GRTC_INTENSET14_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
36648   #define GRTC_INTENSET14_COMPARE1_Set (0x1UL)       /*!< Enable                                                               */
36649   #define GRTC_INTENSET14_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36650   #define GRTC_INTENSET14_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36651 
36652 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
36653   #define GRTC_INTENSET14_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
36654   #define GRTC_INTENSET14_COMPARE2_Msk (0x1UL << GRTC_INTENSET14_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
36655   #define GRTC_INTENSET14_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
36656   #define GRTC_INTENSET14_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
36657   #define GRTC_INTENSET14_COMPARE2_Set (0x1UL)       /*!< Enable                                                               */
36658   #define GRTC_INTENSET14_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36659   #define GRTC_INTENSET14_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36660 
36661 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
36662   #define GRTC_INTENSET14_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
36663   #define GRTC_INTENSET14_COMPARE3_Msk (0x1UL << GRTC_INTENSET14_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
36664   #define GRTC_INTENSET14_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
36665   #define GRTC_INTENSET14_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
36666   #define GRTC_INTENSET14_COMPARE3_Set (0x1UL)       /*!< Enable                                                               */
36667   #define GRTC_INTENSET14_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36668   #define GRTC_INTENSET14_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36669 
36670 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
36671   #define GRTC_INTENSET14_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
36672   #define GRTC_INTENSET14_COMPARE4_Msk (0x1UL << GRTC_INTENSET14_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
36673   #define GRTC_INTENSET14_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
36674   #define GRTC_INTENSET14_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
36675   #define GRTC_INTENSET14_COMPARE4_Set (0x1UL)       /*!< Enable                                                               */
36676   #define GRTC_INTENSET14_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36677   #define GRTC_INTENSET14_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36678 
36679 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
36680   #define GRTC_INTENSET14_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
36681   #define GRTC_INTENSET14_COMPARE5_Msk (0x1UL << GRTC_INTENSET14_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
36682   #define GRTC_INTENSET14_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
36683   #define GRTC_INTENSET14_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
36684   #define GRTC_INTENSET14_COMPARE5_Set (0x1UL)       /*!< Enable                                                               */
36685   #define GRTC_INTENSET14_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36686   #define GRTC_INTENSET14_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36687 
36688 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
36689   #define GRTC_INTENSET14_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
36690   #define GRTC_INTENSET14_COMPARE6_Msk (0x1UL << GRTC_INTENSET14_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
36691   #define GRTC_INTENSET14_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
36692   #define GRTC_INTENSET14_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
36693   #define GRTC_INTENSET14_COMPARE6_Set (0x1UL)       /*!< Enable                                                               */
36694   #define GRTC_INTENSET14_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36695   #define GRTC_INTENSET14_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36696 
36697 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
36698   #define GRTC_INTENSET14_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
36699   #define GRTC_INTENSET14_COMPARE7_Msk (0x1UL << GRTC_INTENSET14_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
36700   #define GRTC_INTENSET14_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
36701   #define GRTC_INTENSET14_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
36702   #define GRTC_INTENSET14_COMPARE7_Set (0x1UL)       /*!< Enable                                                               */
36703   #define GRTC_INTENSET14_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36704   #define GRTC_INTENSET14_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36705 
36706 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
36707   #define GRTC_INTENSET14_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
36708   #define GRTC_INTENSET14_COMPARE8_Msk (0x1UL << GRTC_INTENSET14_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
36709   #define GRTC_INTENSET14_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
36710   #define GRTC_INTENSET14_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
36711   #define GRTC_INTENSET14_COMPARE8_Set (0x1UL)       /*!< Enable                                                               */
36712   #define GRTC_INTENSET14_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36713   #define GRTC_INTENSET14_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36714 
36715 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
36716   #define GRTC_INTENSET14_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
36717   #define GRTC_INTENSET14_COMPARE9_Msk (0x1UL << GRTC_INTENSET14_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
36718   #define GRTC_INTENSET14_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
36719   #define GRTC_INTENSET14_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
36720   #define GRTC_INTENSET14_COMPARE9_Set (0x1UL)       /*!< Enable                                                               */
36721   #define GRTC_INTENSET14_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36722   #define GRTC_INTENSET14_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36723 
36724 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
36725   #define GRTC_INTENSET14_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
36726   #define GRTC_INTENSET14_COMPARE10_Msk (0x1UL << GRTC_INTENSET14_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
36727   #define GRTC_INTENSET14_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
36728   #define GRTC_INTENSET14_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
36729   #define GRTC_INTENSET14_COMPARE10_Set (0x1UL)      /*!< Enable                                                               */
36730   #define GRTC_INTENSET14_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36731   #define GRTC_INTENSET14_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36732 
36733 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
36734   #define GRTC_INTENSET14_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
36735   #define GRTC_INTENSET14_COMPARE11_Msk (0x1UL << GRTC_INTENSET14_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
36736   #define GRTC_INTENSET14_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
36737   #define GRTC_INTENSET14_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
36738   #define GRTC_INTENSET14_COMPARE11_Set (0x1UL)      /*!< Enable                                                               */
36739   #define GRTC_INTENSET14_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36740   #define GRTC_INTENSET14_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36741 
36742 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
36743   #define GRTC_INTENSET14_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
36744   #define GRTC_INTENSET14_COMPARE12_Msk (0x1UL << GRTC_INTENSET14_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
36745   #define GRTC_INTENSET14_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
36746   #define GRTC_INTENSET14_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
36747   #define GRTC_INTENSET14_COMPARE12_Set (0x1UL)      /*!< Enable                                                               */
36748   #define GRTC_INTENSET14_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36749   #define GRTC_INTENSET14_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36750 
36751 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
36752   #define GRTC_INTENSET14_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
36753   #define GRTC_INTENSET14_COMPARE13_Msk (0x1UL << GRTC_INTENSET14_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
36754   #define GRTC_INTENSET14_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
36755   #define GRTC_INTENSET14_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
36756   #define GRTC_INTENSET14_COMPARE13_Set (0x1UL)      /*!< Enable                                                               */
36757   #define GRTC_INTENSET14_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36758   #define GRTC_INTENSET14_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36759 
36760 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
36761   #define GRTC_INTENSET14_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
36762   #define GRTC_INTENSET14_COMPARE14_Msk (0x1UL << GRTC_INTENSET14_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
36763   #define GRTC_INTENSET14_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
36764   #define GRTC_INTENSET14_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
36765   #define GRTC_INTENSET14_COMPARE14_Set (0x1UL)      /*!< Enable                                                               */
36766   #define GRTC_INTENSET14_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36767   #define GRTC_INTENSET14_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36768 
36769 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
36770   #define GRTC_INTENSET14_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
36771   #define GRTC_INTENSET14_COMPARE15_Msk (0x1UL << GRTC_INTENSET14_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
36772   #define GRTC_INTENSET14_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
36773   #define GRTC_INTENSET14_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
36774   #define GRTC_INTENSET14_COMPARE15_Set (0x1UL)      /*!< Enable                                                               */
36775   #define GRTC_INTENSET14_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36776   #define GRTC_INTENSET14_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36777 
36778 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
36779   #define GRTC_INTENSET14_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
36780   #define GRTC_INTENSET14_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET14_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
36781                                                                             field.*/
36782   #define GRTC_INTENSET14_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
36783   #define GRTC_INTENSET14_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
36784   #define GRTC_INTENSET14_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                              */
36785   #define GRTC_INTENSET14_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
36786   #define GRTC_INTENSET14_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
36787 
36788 
36789 /* GRTC_INTENCLR14: Disable interrupt */
36790   #define GRTC_INTENCLR14_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR14 register.                                  */
36791 
36792 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
36793   #define GRTC_INTENCLR14_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
36794   #define GRTC_INTENCLR14_COMPARE0_Msk (0x1UL << GRTC_INTENCLR14_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
36795   #define GRTC_INTENCLR14_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
36796   #define GRTC_INTENCLR14_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
36797   #define GRTC_INTENCLR14_COMPARE0_Clear (0x1UL)     /*!< Disable                                                              */
36798   #define GRTC_INTENCLR14_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36799   #define GRTC_INTENCLR14_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36800 
36801 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
36802   #define GRTC_INTENCLR14_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
36803   #define GRTC_INTENCLR14_COMPARE1_Msk (0x1UL << GRTC_INTENCLR14_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
36804   #define GRTC_INTENCLR14_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
36805   #define GRTC_INTENCLR14_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
36806   #define GRTC_INTENCLR14_COMPARE1_Clear (0x1UL)     /*!< Disable                                                              */
36807   #define GRTC_INTENCLR14_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36808   #define GRTC_INTENCLR14_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36809 
36810 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
36811   #define GRTC_INTENCLR14_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
36812   #define GRTC_INTENCLR14_COMPARE2_Msk (0x1UL << GRTC_INTENCLR14_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
36813   #define GRTC_INTENCLR14_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
36814   #define GRTC_INTENCLR14_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
36815   #define GRTC_INTENCLR14_COMPARE2_Clear (0x1UL)     /*!< Disable                                                              */
36816   #define GRTC_INTENCLR14_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36817   #define GRTC_INTENCLR14_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36818 
36819 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
36820   #define GRTC_INTENCLR14_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
36821   #define GRTC_INTENCLR14_COMPARE3_Msk (0x1UL << GRTC_INTENCLR14_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
36822   #define GRTC_INTENCLR14_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
36823   #define GRTC_INTENCLR14_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
36824   #define GRTC_INTENCLR14_COMPARE3_Clear (0x1UL)     /*!< Disable                                                              */
36825   #define GRTC_INTENCLR14_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36826   #define GRTC_INTENCLR14_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36827 
36828 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
36829   #define GRTC_INTENCLR14_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
36830   #define GRTC_INTENCLR14_COMPARE4_Msk (0x1UL << GRTC_INTENCLR14_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
36831   #define GRTC_INTENCLR14_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
36832   #define GRTC_INTENCLR14_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
36833   #define GRTC_INTENCLR14_COMPARE4_Clear (0x1UL)     /*!< Disable                                                              */
36834   #define GRTC_INTENCLR14_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36835   #define GRTC_INTENCLR14_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36836 
36837 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
36838   #define GRTC_INTENCLR14_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
36839   #define GRTC_INTENCLR14_COMPARE5_Msk (0x1UL << GRTC_INTENCLR14_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
36840   #define GRTC_INTENCLR14_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
36841   #define GRTC_INTENCLR14_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
36842   #define GRTC_INTENCLR14_COMPARE5_Clear (0x1UL)     /*!< Disable                                                              */
36843   #define GRTC_INTENCLR14_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36844   #define GRTC_INTENCLR14_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36845 
36846 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
36847   #define GRTC_INTENCLR14_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
36848   #define GRTC_INTENCLR14_COMPARE6_Msk (0x1UL << GRTC_INTENCLR14_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
36849   #define GRTC_INTENCLR14_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
36850   #define GRTC_INTENCLR14_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
36851   #define GRTC_INTENCLR14_COMPARE6_Clear (0x1UL)     /*!< Disable                                                              */
36852   #define GRTC_INTENCLR14_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36853   #define GRTC_INTENCLR14_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36854 
36855 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
36856   #define GRTC_INTENCLR14_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
36857   #define GRTC_INTENCLR14_COMPARE7_Msk (0x1UL << GRTC_INTENCLR14_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
36858   #define GRTC_INTENCLR14_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
36859   #define GRTC_INTENCLR14_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
36860   #define GRTC_INTENCLR14_COMPARE7_Clear (0x1UL)     /*!< Disable                                                              */
36861   #define GRTC_INTENCLR14_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36862   #define GRTC_INTENCLR14_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36863 
36864 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
36865   #define GRTC_INTENCLR14_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
36866   #define GRTC_INTENCLR14_COMPARE8_Msk (0x1UL << GRTC_INTENCLR14_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
36867   #define GRTC_INTENCLR14_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
36868   #define GRTC_INTENCLR14_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
36869   #define GRTC_INTENCLR14_COMPARE8_Clear (0x1UL)     /*!< Disable                                                              */
36870   #define GRTC_INTENCLR14_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36871   #define GRTC_INTENCLR14_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36872 
36873 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
36874   #define GRTC_INTENCLR14_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
36875   #define GRTC_INTENCLR14_COMPARE9_Msk (0x1UL << GRTC_INTENCLR14_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
36876   #define GRTC_INTENCLR14_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
36877   #define GRTC_INTENCLR14_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
36878   #define GRTC_INTENCLR14_COMPARE9_Clear (0x1UL)     /*!< Disable                                                              */
36879   #define GRTC_INTENCLR14_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
36880   #define GRTC_INTENCLR14_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
36881 
36882 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
36883   #define GRTC_INTENCLR14_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
36884   #define GRTC_INTENCLR14_COMPARE10_Msk (0x1UL << GRTC_INTENCLR14_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
36885   #define GRTC_INTENCLR14_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
36886   #define GRTC_INTENCLR14_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
36887   #define GRTC_INTENCLR14_COMPARE10_Clear (0x1UL)    /*!< Disable                                                              */
36888   #define GRTC_INTENCLR14_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36889   #define GRTC_INTENCLR14_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36890 
36891 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
36892   #define GRTC_INTENCLR14_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
36893   #define GRTC_INTENCLR14_COMPARE11_Msk (0x1UL << GRTC_INTENCLR14_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
36894   #define GRTC_INTENCLR14_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
36895   #define GRTC_INTENCLR14_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
36896   #define GRTC_INTENCLR14_COMPARE11_Clear (0x1UL)    /*!< Disable                                                              */
36897   #define GRTC_INTENCLR14_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36898   #define GRTC_INTENCLR14_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36899 
36900 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
36901   #define GRTC_INTENCLR14_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
36902   #define GRTC_INTENCLR14_COMPARE12_Msk (0x1UL << GRTC_INTENCLR14_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
36903   #define GRTC_INTENCLR14_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
36904   #define GRTC_INTENCLR14_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
36905   #define GRTC_INTENCLR14_COMPARE12_Clear (0x1UL)    /*!< Disable                                                              */
36906   #define GRTC_INTENCLR14_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36907   #define GRTC_INTENCLR14_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36908 
36909 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
36910   #define GRTC_INTENCLR14_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
36911   #define GRTC_INTENCLR14_COMPARE13_Msk (0x1UL << GRTC_INTENCLR14_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
36912   #define GRTC_INTENCLR14_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
36913   #define GRTC_INTENCLR14_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
36914   #define GRTC_INTENCLR14_COMPARE13_Clear (0x1UL)    /*!< Disable                                                              */
36915   #define GRTC_INTENCLR14_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36916   #define GRTC_INTENCLR14_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36917 
36918 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
36919   #define GRTC_INTENCLR14_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
36920   #define GRTC_INTENCLR14_COMPARE14_Msk (0x1UL << GRTC_INTENCLR14_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
36921   #define GRTC_INTENCLR14_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
36922   #define GRTC_INTENCLR14_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
36923   #define GRTC_INTENCLR14_COMPARE14_Clear (0x1UL)    /*!< Disable                                                              */
36924   #define GRTC_INTENCLR14_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36925   #define GRTC_INTENCLR14_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36926 
36927 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
36928   #define GRTC_INTENCLR14_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
36929   #define GRTC_INTENCLR14_COMPARE15_Msk (0x1UL << GRTC_INTENCLR14_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
36930   #define GRTC_INTENCLR14_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
36931   #define GRTC_INTENCLR14_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
36932   #define GRTC_INTENCLR14_COMPARE15_Clear (0x1UL)    /*!< Disable                                                              */
36933   #define GRTC_INTENCLR14_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
36934   #define GRTC_INTENCLR14_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
36935 
36936 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
36937   #define GRTC_INTENCLR14_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
36938   #define GRTC_INTENCLR14_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR14_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
36939                                                                             field.*/
36940   #define GRTC_INTENCLR14_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
36941   #define GRTC_INTENCLR14_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
36942   #define GRTC_INTENCLR14_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                           */
36943   #define GRTC_INTENCLR14_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
36944   #define GRTC_INTENCLR14_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
36945 
36946 
36947 /* GRTC_INTPEND14: Pending interrupts */
36948   #define GRTC_INTPEND14_ResetValue (0x00000000UL)   /*!< Reset value of INTPEND14 register.                                   */
36949 
36950 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
36951   #define GRTC_INTPEND14_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
36952   #define GRTC_INTPEND14_COMPARE0_Msk (0x1UL << GRTC_INTPEND14_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
36953   #define GRTC_INTPEND14_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
36954   #define GRTC_INTPEND14_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
36955   #define GRTC_INTPEND14_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36956   #define GRTC_INTPEND14_COMPARE0_Pending (0x1UL)    /*!< Read: Pending                                                        */
36957 
36958 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
36959   #define GRTC_INTPEND14_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
36960   #define GRTC_INTPEND14_COMPARE1_Msk (0x1UL << GRTC_INTPEND14_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
36961   #define GRTC_INTPEND14_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
36962   #define GRTC_INTPEND14_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
36963   #define GRTC_INTPEND14_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36964   #define GRTC_INTPEND14_COMPARE1_Pending (0x1UL)    /*!< Read: Pending                                                        */
36965 
36966 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
36967   #define GRTC_INTPEND14_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
36968   #define GRTC_INTPEND14_COMPARE2_Msk (0x1UL << GRTC_INTPEND14_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
36969   #define GRTC_INTPEND14_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
36970   #define GRTC_INTPEND14_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
36971   #define GRTC_INTPEND14_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36972   #define GRTC_INTPEND14_COMPARE2_Pending (0x1UL)    /*!< Read: Pending                                                        */
36973 
36974 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
36975   #define GRTC_INTPEND14_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
36976   #define GRTC_INTPEND14_COMPARE3_Msk (0x1UL << GRTC_INTPEND14_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
36977   #define GRTC_INTPEND14_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
36978   #define GRTC_INTPEND14_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
36979   #define GRTC_INTPEND14_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36980   #define GRTC_INTPEND14_COMPARE3_Pending (0x1UL)    /*!< Read: Pending                                                        */
36981 
36982 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
36983   #define GRTC_INTPEND14_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
36984   #define GRTC_INTPEND14_COMPARE4_Msk (0x1UL << GRTC_INTPEND14_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
36985   #define GRTC_INTPEND14_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
36986   #define GRTC_INTPEND14_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
36987   #define GRTC_INTPEND14_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36988   #define GRTC_INTPEND14_COMPARE4_Pending (0x1UL)    /*!< Read: Pending                                                        */
36989 
36990 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
36991   #define GRTC_INTPEND14_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
36992   #define GRTC_INTPEND14_COMPARE5_Msk (0x1UL << GRTC_INTPEND14_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
36993   #define GRTC_INTPEND14_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
36994   #define GRTC_INTPEND14_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
36995   #define GRTC_INTPEND14_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending                                                    */
36996   #define GRTC_INTPEND14_COMPARE5_Pending (0x1UL)    /*!< Read: Pending                                                        */
36997 
36998 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
36999   #define GRTC_INTPEND14_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
37000   #define GRTC_INTPEND14_COMPARE6_Msk (0x1UL << GRTC_INTPEND14_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
37001   #define GRTC_INTPEND14_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
37002   #define GRTC_INTPEND14_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
37003   #define GRTC_INTPEND14_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37004   #define GRTC_INTPEND14_COMPARE6_Pending (0x1UL)    /*!< Read: Pending                                                        */
37005 
37006 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
37007   #define GRTC_INTPEND14_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
37008   #define GRTC_INTPEND14_COMPARE7_Msk (0x1UL << GRTC_INTPEND14_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
37009   #define GRTC_INTPEND14_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
37010   #define GRTC_INTPEND14_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
37011   #define GRTC_INTPEND14_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37012   #define GRTC_INTPEND14_COMPARE7_Pending (0x1UL)    /*!< Read: Pending                                                        */
37013 
37014 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
37015   #define GRTC_INTPEND14_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
37016   #define GRTC_INTPEND14_COMPARE8_Msk (0x1UL << GRTC_INTPEND14_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
37017   #define GRTC_INTPEND14_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
37018   #define GRTC_INTPEND14_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
37019   #define GRTC_INTPEND14_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37020   #define GRTC_INTPEND14_COMPARE8_Pending (0x1UL)    /*!< Read: Pending                                                        */
37021 
37022 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
37023   #define GRTC_INTPEND14_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
37024   #define GRTC_INTPEND14_COMPARE9_Msk (0x1UL << GRTC_INTPEND14_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
37025   #define GRTC_INTPEND14_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
37026   #define GRTC_INTPEND14_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
37027   #define GRTC_INTPEND14_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37028   #define GRTC_INTPEND14_COMPARE9_Pending (0x1UL)    /*!< Read: Pending                                                        */
37029 
37030 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
37031   #define GRTC_INTPEND14_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
37032   #define GRTC_INTPEND14_COMPARE10_Msk (0x1UL << GRTC_INTPEND14_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
37033   #define GRTC_INTPEND14_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
37034   #define GRTC_INTPEND14_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
37035   #define GRTC_INTPEND14_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37036   #define GRTC_INTPEND14_COMPARE10_Pending (0x1UL)   /*!< Read: Pending                                                        */
37037 
37038 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
37039   #define GRTC_INTPEND14_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
37040   #define GRTC_INTPEND14_COMPARE11_Msk (0x1UL << GRTC_INTPEND14_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
37041   #define GRTC_INTPEND14_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
37042   #define GRTC_INTPEND14_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
37043   #define GRTC_INTPEND14_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37044   #define GRTC_INTPEND14_COMPARE11_Pending (0x1UL)   /*!< Read: Pending                                                        */
37045 
37046 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
37047   #define GRTC_INTPEND14_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
37048   #define GRTC_INTPEND14_COMPARE12_Msk (0x1UL << GRTC_INTPEND14_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
37049   #define GRTC_INTPEND14_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
37050   #define GRTC_INTPEND14_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
37051   #define GRTC_INTPEND14_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37052   #define GRTC_INTPEND14_COMPARE12_Pending (0x1UL)   /*!< Read: Pending                                                        */
37053 
37054 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
37055   #define GRTC_INTPEND14_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
37056   #define GRTC_INTPEND14_COMPARE13_Msk (0x1UL << GRTC_INTPEND14_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
37057   #define GRTC_INTPEND14_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
37058   #define GRTC_INTPEND14_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
37059   #define GRTC_INTPEND14_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37060   #define GRTC_INTPEND14_COMPARE13_Pending (0x1UL)   /*!< Read: Pending                                                        */
37061 
37062 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
37063   #define GRTC_INTPEND14_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
37064   #define GRTC_INTPEND14_COMPARE14_Msk (0x1UL << GRTC_INTPEND14_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
37065   #define GRTC_INTPEND14_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
37066   #define GRTC_INTPEND14_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
37067   #define GRTC_INTPEND14_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37068   #define GRTC_INTPEND14_COMPARE14_Pending (0x1UL)   /*!< Read: Pending                                                        */
37069 
37070 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
37071   #define GRTC_INTPEND14_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
37072   #define GRTC_INTPEND14_COMPARE15_Msk (0x1UL << GRTC_INTPEND14_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
37073   #define GRTC_INTPEND14_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
37074   #define GRTC_INTPEND14_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
37075   #define GRTC_INTPEND14_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37076   #define GRTC_INTPEND14_COMPARE15_Pending (0x1UL)   /*!< Read: Pending                                                        */
37077 
37078 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
37079   #define GRTC_INTPEND14_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
37080   #define GRTC_INTPEND14_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND14_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
37081                                                                             field.*/
37082   #define GRTC_INTPEND14_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
37083   #define GRTC_INTPEND14_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
37084   #define GRTC_INTPEND14_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                             */
37085   #define GRTC_INTPEND14_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                    */
37086 
37087 
37088 /* GRTC_INTEN15: Enable or disable interrupt */
37089   #define GRTC_INTEN15_ResetValue (0x00000000UL)     /*!< Reset value of INTEN15 register.                                     */
37090 
37091 /* COMPARE0 @Bit 0 : Enable or disable interrupt for event COMPARE[0] */
37092   #define GRTC_INTEN15_COMPARE0_Pos (0UL)            /*!< Position of COMPARE0 field.                                          */
37093   #define GRTC_INTEN15_COMPARE0_Msk (0x1UL << GRTC_INTEN15_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
37094   #define GRTC_INTEN15_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
37095   #define GRTC_INTEN15_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
37096   #define GRTC_INTEN15_COMPARE0_Disabled (0x0UL)     /*!< Disable                                                              */
37097   #define GRTC_INTEN15_COMPARE0_Enabled (0x1UL)      /*!< Enable                                                               */
37098 
37099 /* COMPARE1 @Bit 1 : Enable or disable interrupt for event COMPARE[1] */
37100   #define GRTC_INTEN15_COMPARE1_Pos (1UL)            /*!< Position of COMPARE1 field.                                          */
37101   #define GRTC_INTEN15_COMPARE1_Msk (0x1UL << GRTC_INTEN15_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
37102   #define GRTC_INTEN15_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
37103   #define GRTC_INTEN15_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
37104   #define GRTC_INTEN15_COMPARE1_Disabled (0x0UL)     /*!< Disable                                                              */
37105   #define GRTC_INTEN15_COMPARE1_Enabled (0x1UL)      /*!< Enable                                                               */
37106 
37107 /* COMPARE2 @Bit 2 : Enable or disable interrupt for event COMPARE[2] */
37108   #define GRTC_INTEN15_COMPARE2_Pos (2UL)            /*!< Position of COMPARE2 field.                                          */
37109   #define GRTC_INTEN15_COMPARE2_Msk (0x1UL << GRTC_INTEN15_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
37110   #define GRTC_INTEN15_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
37111   #define GRTC_INTEN15_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
37112   #define GRTC_INTEN15_COMPARE2_Disabled (0x0UL)     /*!< Disable                                                              */
37113   #define GRTC_INTEN15_COMPARE2_Enabled (0x1UL)      /*!< Enable                                                               */
37114 
37115 /* COMPARE3 @Bit 3 : Enable or disable interrupt for event COMPARE[3] */
37116   #define GRTC_INTEN15_COMPARE3_Pos (3UL)            /*!< Position of COMPARE3 field.                                          */
37117   #define GRTC_INTEN15_COMPARE3_Msk (0x1UL << GRTC_INTEN15_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
37118   #define GRTC_INTEN15_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
37119   #define GRTC_INTEN15_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
37120   #define GRTC_INTEN15_COMPARE3_Disabled (0x0UL)     /*!< Disable                                                              */
37121   #define GRTC_INTEN15_COMPARE3_Enabled (0x1UL)      /*!< Enable                                                               */
37122 
37123 /* COMPARE4 @Bit 4 : Enable or disable interrupt for event COMPARE[4] */
37124   #define GRTC_INTEN15_COMPARE4_Pos (4UL)            /*!< Position of COMPARE4 field.                                          */
37125   #define GRTC_INTEN15_COMPARE4_Msk (0x1UL << GRTC_INTEN15_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
37126   #define GRTC_INTEN15_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
37127   #define GRTC_INTEN15_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
37128   #define GRTC_INTEN15_COMPARE4_Disabled (0x0UL)     /*!< Disable                                                              */
37129   #define GRTC_INTEN15_COMPARE4_Enabled (0x1UL)      /*!< Enable                                                               */
37130 
37131 /* COMPARE5 @Bit 5 : Enable or disable interrupt for event COMPARE[5] */
37132   #define GRTC_INTEN15_COMPARE5_Pos (5UL)            /*!< Position of COMPARE5 field.                                          */
37133   #define GRTC_INTEN15_COMPARE5_Msk (0x1UL << GRTC_INTEN15_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
37134   #define GRTC_INTEN15_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
37135   #define GRTC_INTEN15_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
37136   #define GRTC_INTEN15_COMPARE5_Disabled (0x0UL)     /*!< Disable                                                              */
37137   #define GRTC_INTEN15_COMPARE5_Enabled (0x1UL)      /*!< Enable                                                               */
37138 
37139 /* COMPARE6 @Bit 6 : Enable or disable interrupt for event COMPARE[6] */
37140   #define GRTC_INTEN15_COMPARE6_Pos (6UL)            /*!< Position of COMPARE6 field.                                          */
37141   #define GRTC_INTEN15_COMPARE6_Msk (0x1UL << GRTC_INTEN15_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
37142   #define GRTC_INTEN15_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
37143   #define GRTC_INTEN15_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
37144   #define GRTC_INTEN15_COMPARE6_Disabled (0x0UL)     /*!< Disable                                                              */
37145   #define GRTC_INTEN15_COMPARE6_Enabled (0x1UL)      /*!< Enable                                                               */
37146 
37147 /* COMPARE7 @Bit 7 : Enable or disable interrupt for event COMPARE[7] */
37148   #define GRTC_INTEN15_COMPARE7_Pos (7UL)            /*!< Position of COMPARE7 field.                                          */
37149   #define GRTC_INTEN15_COMPARE7_Msk (0x1UL << GRTC_INTEN15_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
37150   #define GRTC_INTEN15_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
37151   #define GRTC_INTEN15_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
37152   #define GRTC_INTEN15_COMPARE7_Disabled (0x0UL)     /*!< Disable                                                              */
37153   #define GRTC_INTEN15_COMPARE7_Enabled (0x1UL)      /*!< Enable                                                               */
37154 
37155 /* COMPARE8 @Bit 8 : Enable or disable interrupt for event COMPARE[8] */
37156   #define GRTC_INTEN15_COMPARE8_Pos (8UL)            /*!< Position of COMPARE8 field.                                          */
37157   #define GRTC_INTEN15_COMPARE8_Msk (0x1UL << GRTC_INTEN15_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                      */
37158   #define GRTC_INTEN15_COMPARE8_Min (0x0UL)          /*!< Min enumerator value of COMPARE8 field.                              */
37159   #define GRTC_INTEN15_COMPARE8_Max (0x1UL)          /*!< Max enumerator value of COMPARE8 field.                              */
37160   #define GRTC_INTEN15_COMPARE8_Disabled (0x0UL)     /*!< Disable                                                              */
37161   #define GRTC_INTEN15_COMPARE8_Enabled (0x1UL)      /*!< Enable                                                               */
37162 
37163 /* COMPARE9 @Bit 9 : Enable or disable interrupt for event COMPARE[9] */
37164   #define GRTC_INTEN15_COMPARE9_Pos (9UL)            /*!< Position of COMPARE9 field.                                          */
37165   #define GRTC_INTEN15_COMPARE9_Msk (0x1UL << GRTC_INTEN15_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                      */
37166   #define GRTC_INTEN15_COMPARE9_Min (0x0UL)          /*!< Min enumerator value of COMPARE9 field.                              */
37167   #define GRTC_INTEN15_COMPARE9_Max (0x1UL)          /*!< Max enumerator value of COMPARE9 field.                              */
37168   #define GRTC_INTEN15_COMPARE9_Disabled (0x0UL)     /*!< Disable                                                              */
37169   #define GRTC_INTEN15_COMPARE9_Enabled (0x1UL)      /*!< Enable                                                               */
37170 
37171 /* COMPARE10 @Bit 10 : Enable or disable interrupt for event COMPARE[10] */
37172   #define GRTC_INTEN15_COMPARE10_Pos (10UL)          /*!< Position of COMPARE10 field.                                         */
37173   #define GRTC_INTEN15_COMPARE10_Msk (0x1UL << GRTC_INTEN15_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.                   */
37174   #define GRTC_INTEN15_COMPARE10_Min (0x0UL)         /*!< Min enumerator value of COMPARE10 field.                             */
37175   #define GRTC_INTEN15_COMPARE10_Max (0x1UL)         /*!< Max enumerator value of COMPARE10 field.                             */
37176   #define GRTC_INTEN15_COMPARE10_Disabled (0x0UL)    /*!< Disable                                                              */
37177   #define GRTC_INTEN15_COMPARE10_Enabled (0x1UL)     /*!< Enable                                                               */
37178 
37179 /* COMPARE11 @Bit 11 : Enable or disable interrupt for event COMPARE[11] */
37180   #define GRTC_INTEN15_COMPARE11_Pos (11UL)          /*!< Position of COMPARE11 field.                                         */
37181   #define GRTC_INTEN15_COMPARE11_Msk (0x1UL << GRTC_INTEN15_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.                   */
37182   #define GRTC_INTEN15_COMPARE11_Min (0x0UL)         /*!< Min enumerator value of COMPARE11 field.                             */
37183   #define GRTC_INTEN15_COMPARE11_Max (0x1UL)         /*!< Max enumerator value of COMPARE11 field.                             */
37184   #define GRTC_INTEN15_COMPARE11_Disabled (0x0UL)    /*!< Disable                                                              */
37185   #define GRTC_INTEN15_COMPARE11_Enabled (0x1UL)     /*!< Enable                                                               */
37186 
37187 /* COMPARE12 @Bit 12 : Enable or disable interrupt for event COMPARE[12] */
37188   #define GRTC_INTEN15_COMPARE12_Pos (12UL)          /*!< Position of COMPARE12 field.                                         */
37189   #define GRTC_INTEN15_COMPARE12_Msk (0x1UL << GRTC_INTEN15_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.                   */
37190   #define GRTC_INTEN15_COMPARE12_Min (0x0UL)         /*!< Min enumerator value of COMPARE12 field.                             */
37191   #define GRTC_INTEN15_COMPARE12_Max (0x1UL)         /*!< Max enumerator value of COMPARE12 field.                             */
37192   #define GRTC_INTEN15_COMPARE12_Disabled (0x0UL)    /*!< Disable                                                              */
37193   #define GRTC_INTEN15_COMPARE12_Enabled (0x1UL)     /*!< Enable                                                               */
37194 
37195 /* COMPARE13 @Bit 13 : Enable or disable interrupt for event COMPARE[13] */
37196   #define GRTC_INTEN15_COMPARE13_Pos (13UL)          /*!< Position of COMPARE13 field.                                         */
37197   #define GRTC_INTEN15_COMPARE13_Msk (0x1UL << GRTC_INTEN15_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.                   */
37198   #define GRTC_INTEN15_COMPARE13_Min (0x0UL)         /*!< Min enumerator value of COMPARE13 field.                             */
37199   #define GRTC_INTEN15_COMPARE13_Max (0x1UL)         /*!< Max enumerator value of COMPARE13 field.                             */
37200   #define GRTC_INTEN15_COMPARE13_Disabled (0x0UL)    /*!< Disable                                                              */
37201   #define GRTC_INTEN15_COMPARE13_Enabled (0x1UL)     /*!< Enable                                                               */
37202 
37203 /* COMPARE14 @Bit 14 : Enable or disable interrupt for event COMPARE[14] */
37204   #define GRTC_INTEN15_COMPARE14_Pos (14UL)          /*!< Position of COMPARE14 field.                                         */
37205   #define GRTC_INTEN15_COMPARE14_Msk (0x1UL << GRTC_INTEN15_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.                   */
37206   #define GRTC_INTEN15_COMPARE14_Min (0x0UL)         /*!< Min enumerator value of COMPARE14 field.                             */
37207   #define GRTC_INTEN15_COMPARE14_Max (0x1UL)         /*!< Max enumerator value of COMPARE14 field.                             */
37208   #define GRTC_INTEN15_COMPARE14_Disabled (0x0UL)    /*!< Disable                                                              */
37209   #define GRTC_INTEN15_COMPARE14_Enabled (0x1UL)     /*!< Enable                                                               */
37210 
37211 /* COMPARE15 @Bit 15 : Enable or disable interrupt for event COMPARE[15] */
37212   #define GRTC_INTEN15_COMPARE15_Pos (15UL)          /*!< Position of COMPARE15 field.                                         */
37213   #define GRTC_INTEN15_COMPARE15_Msk (0x1UL << GRTC_INTEN15_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.                   */
37214   #define GRTC_INTEN15_COMPARE15_Min (0x0UL)         /*!< Min enumerator value of COMPARE15 field.                             */
37215   #define GRTC_INTEN15_COMPARE15_Max (0x1UL)         /*!< Max enumerator value of COMPARE15 field.                             */
37216   #define GRTC_INTEN15_COMPARE15_Disabled (0x0UL)    /*!< Disable                                                              */
37217   #define GRTC_INTEN15_COMPARE15_Enabled (0x1UL)     /*!< Enable                                                               */
37218 
37219 /* SYSCOUNTERVALID @Bit 26 : Enable or disable interrupt for event SYSCOUNTERVALID */
37220   #define GRTC_INTEN15_SYSCOUNTERVALID_Pos (26UL)    /*!< Position of SYSCOUNTERVALID field.                                   */
37221   #define GRTC_INTEN15_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTEN15_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID field. */
37222   #define GRTC_INTEN15_SYSCOUNTERVALID_Min (0x0UL)   /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
37223   #define GRTC_INTEN15_SYSCOUNTERVALID_Max (0x1UL)   /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
37224   #define GRTC_INTEN15_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Disable                                                           */
37225   #define GRTC_INTEN15_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Enable                                                             */
37226 
37227 
37228 /* GRTC_INTENSET15: Enable interrupt */
37229   #define GRTC_INTENSET15_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET15 register.                                  */
37230 
37231 /* COMPARE0 @Bit 0 : Write '1' to enable interrupt for event COMPARE[0] */
37232   #define GRTC_INTENSET15_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
37233   #define GRTC_INTENSET15_COMPARE0_Msk (0x1UL << GRTC_INTENSET15_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
37234   #define GRTC_INTENSET15_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
37235   #define GRTC_INTENSET15_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
37236   #define GRTC_INTENSET15_COMPARE0_Set (0x1UL)       /*!< Enable                                                               */
37237   #define GRTC_INTENSET15_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37238   #define GRTC_INTENSET15_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37239 
37240 /* COMPARE1 @Bit 1 : Write '1' to enable interrupt for event COMPARE[1] */
37241   #define GRTC_INTENSET15_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
37242   #define GRTC_INTENSET15_COMPARE1_Msk (0x1UL << GRTC_INTENSET15_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
37243   #define GRTC_INTENSET15_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
37244   #define GRTC_INTENSET15_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
37245   #define GRTC_INTENSET15_COMPARE1_Set (0x1UL)       /*!< Enable                                                               */
37246   #define GRTC_INTENSET15_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37247   #define GRTC_INTENSET15_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37248 
37249 /* COMPARE2 @Bit 2 : Write '1' to enable interrupt for event COMPARE[2] */
37250   #define GRTC_INTENSET15_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
37251   #define GRTC_INTENSET15_COMPARE2_Msk (0x1UL << GRTC_INTENSET15_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
37252   #define GRTC_INTENSET15_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
37253   #define GRTC_INTENSET15_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
37254   #define GRTC_INTENSET15_COMPARE2_Set (0x1UL)       /*!< Enable                                                               */
37255   #define GRTC_INTENSET15_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37256   #define GRTC_INTENSET15_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37257 
37258 /* COMPARE3 @Bit 3 : Write '1' to enable interrupt for event COMPARE[3] */
37259   #define GRTC_INTENSET15_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
37260   #define GRTC_INTENSET15_COMPARE3_Msk (0x1UL << GRTC_INTENSET15_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
37261   #define GRTC_INTENSET15_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
37262   #define GRTC_INTENSET15_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
37263   #define GRTC_INTENSET15_COMPARE3_Set (0x1UL)       /*!< Enable                                                               */
37264   #define GRTC_INTENSET15_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37265   #define GRTC_INTENSET15_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37266 
37267 /* COMPARE4 @Bit 4 : Write '1' to enable interrupt for event COMPARE[4] */
37268   #define GRTC_INTENSET15_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
37269   #define GRTC_INTENSET15_COMPARE4_Msk (0x1UL << GRTC_INTENSET15_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
37270   #define GRTC_INTENSET15_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
37271   #define GRTC_INTENSET15_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
37272   #define GRTC_INTENSET15_COMPARE4_Set (0x1UL)       /*!< Enable                                                               */
37273   #define GRTC_INTENSET15_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37274   #define GRTC_INTENSET15_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37275 
37276 /* COMPARE5 @Bit 5 : Write '1' to enable interrupt for event COMPARE[5] */
37277   #define GRTC_INTENSET15_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
37278   #define GRTC_INTENSET15_COMPARE5_Msk (0x1UL << GRTC_INTENSET15_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
37279   #define GRTC_INTENSET15_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
37280   #define GRTC_INTENSET15_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
37281   #define GRTC_INTENSET15_COMPARE5_Set (0x1UL)       /*!< Enable                                                               */
37282   #define GRTC_INTENSET15_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37283   #define GRTC_INTENSET15_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37284 
37285 /* COMPARE6 @Bit 6 : Write '1' to enable interrupt for event COMPARE[6] */
37286   #define GRTC_INTENSET15_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
37287   #define GRTC_INTENSET15_COMPARE6_Msk (0x1UL << GRTC_INTENSET15_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
37288   #define GRTC_INTENSET15_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
37289   #define GRTC_INTENSET15_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
37290   #define GRTC_INTENSET15_COMPARE6_Set (0x1UL)       /*!< Enable                                                               */
37291   #define GRTC_INTENSET15_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37292   #define GRTC_INTENSET15_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37293 
37294 /* COMPARE7 @Bit 7 : Write '1' to enable interrupt for event COMPARE[7] */
37295   #define GRTC_INTENSET15_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
37296   #define GRTC_INTENSET15_COMPARE7_Msk (0x1UL << GRTC_INTENSET15_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
37297   #define GRTC_INTENSET15_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
37298   #define GRTC_INTENSET15_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
37299   #define GRTC_INTENSET15_COMPARE7_Set (0x1UL)       /*!< Enable                                                               */
37300   #define GRTC_INTENSET15_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37301   #define GRTC_INTENSET15_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37302 
37303 /* COMPARE8 @Bit 8 : Write '1' to enable interrupt for event COMPARE[8] */
37304   #define GRTC_INTENSET15_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
37305   #define GRTC_INTENSET15_COMPARE8_Msk (0x1UL << GRTC_INTENSET15_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
37306   #define GRTC_INTENSET15_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
37307   #define GRTC_INTENSET15_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
37308   #define GRTC_INTENSET15_COMPARE8_Set (0x1UL)       /*!< Enable                                                               */
37309   #define GRTC_INTENSET15_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37310   #define GRTC_INTENSET15_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37311 
37312 /* COMPARE9 @Bit 9 : Write '1' to enable interrupt for event COMPARE[9] */
37313   #define GRTC_INTENSET15_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
37314   #define GRTC_INTENSET15_COMPARE9_Msk (0x1UL << GRTC_INTENSET15_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
37315   #define GRTC_INTENSET15_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
37316   #define GRTC_INTENSET15_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
37317   #define GRTC_INTENSET15_COMPARE9_Set (0x1UL)       /*!< Enable                                                               */
37318   #define GRTC_INTENSET15_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37319   #define GRTC_INTENSET15_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37320 
37321 /* COMPARE10 @Bit 10 : Write '1' to enable interrupt for event COMPARE[10] */
37322   #define GRTC_INTENSET15_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
37323   #define GRTC_INTENSET15_COMPARE10_Msk (0x1UL << GRTC_INTENSET15_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
37324   #define GRTC_INTENSET15_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
37325   #define GRTC_INTENSET15_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
37326   #define GRTC_INTENSET15_COMPARE10_Set (0x1UL)      /*!< Enable                                                               */
37327   #define GRTC_INTENSET15_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37328   #define GRTC_INTENSET15_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37329 
37330 /* COMPARE11 @Bit 11 : Write '1' to enable interrupt for event COMPARE[11] */
37331   #define GRTC_INTENSET15_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
37332   #define GRTC_INTENSET15_COMPARE11_Msk (0x1UL << GRTC_INTENSET15_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
37333   #define GRTC_INTENSET15_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
37334   #define GRTC_INTENSET15_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
37335   #define GRTC_INTENSET15_COMPARE11_Set (0x1UL)      /*!< Enable                                                               */
37336   #define GRTC_INTENSET15_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37337   #define GRTC_INTENSET15_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37338 
37339 /* COMPARE12 @Bit 12 : Write '1' to enable interrupt for event COMPARE[12] */
37340   #define GRTC_INTENSET15_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
37341   #define GRTC_INTENSET15_COMPARE12_Msk (0x1UL << GRTC_INTENSET15_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
37342   #define GRTC_INTENSET15_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
37343   #define GRTC_INTENSET15_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
37344   #define GRTC_INTENSET15_COMPARE12_Set (0x1UL)      /*!< Enable                                                               */
37345   #define GRTC_INTENSET15_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37346   #define GRTC_INTENSET15_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37347 
37348 /* COMPARE13 @Bit 13 : Write '1' to enable interrupt for event COMPARE[13] */
37349   #define GRTC_INTENSET15_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
37350   #define GRTC_INTENSET15_COMPARE13_Msk (0x1UL << GRTC_INTENSET15_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
37351   #define GRTC_INTENSET15_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
37352   #define GRTC_INTENSET15_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
37353   #define GRTC_INTENSET15_COMPARE13_Set (0x1UL)      /*!< Enable                                                               */
37354   #define GRTC_INTENSET15_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37355   #define GRTC_INTENSET15_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37356 
37357 /* COMPARE14 @Bit 14 : Write '1' to enable interrupt for event COMPARE[14] */
37358   #define GRTC_INTENSET15_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
37359   #define GRTC_INTENSET15_COMPARE14_Msk (0x1UL << GRTC_INTENSET15_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
37360   #define GRTC_INTENSET15_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
37361   #define GRTC_INTENSET15_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
37362   #define GRTC_INTENSET15_COMPARE14_Set (0x1UL)      /*!< Enable                                                               */
37363   #define GRTC_INTENSET15_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37364   #define GRTC_INTENSET15_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37365 
37366 /* COMPARE15 @Bit 15 : Write '1' to enable interrupt for event COMPARE[15] */
37367   #define GRTC_INTENSET15_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
37368   #define GRTC_INTENSET15_COMPARE15_Msk (0x1UL << GRTC_INTENSET15_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
37369   #define GRTC_INTENSET15_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
37370   #define GRTC_INTENSET15_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
37371   #define GRTC_INTENSET15_COMPARE15_Set (0x1UL)      /*!< Enable                                                               */
37372   #define GRTC_INTENSET15_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37373   #define GRTC_INTENSET15_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37374 
37375 /* SYSCOUNTERVALID @Bit 26 : Write '1' to enable interrupt for event SYSCOUNTERVALID */
37376   #define GRTC_INTENSET15_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
37377   #define GRTC_INTENSET15_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENSET15_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
37378                                                                             field.*/
37379   #define GRTC_INTENSET15_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
37380   #define GRTC_INTENSET15_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
37381   #define GRTC_INTENSET15_SYSCOUNTERVALID_Set (0x1UL) /*!< Enable                                                              */
37382   #define GRTC_INTENSET15_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
37383   #define GRTC_INTENSET15_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
37384 
37385 
37386 /* GRTC_INTENCLR15: Disable interrupt */
37387   #define GRTC_INTENCLR15_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR15 register.                                  */
37388 
37389 /* COMPARE0 @Bit 0 : Write '1' to disable interrupt for event COMPARE[0] */
37390   #define GRTC_INTENCLR15_COMPARE0_Pos (0UL)         /*!< Position of COMPARE0 field.                                          */
37391   #define GRTC_INTENCLR15_COMPARE0_Msk (0x1UL << GRTC_INTENCLR15_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                */
37392   #define GRTC_INTENCLR15_COMPARE0_Min (0x0UL)       /*!< Min enumerator value of COMPARE0 field.                              */
37393   #define GRTC_INTENCLR15_COMPARE0_Max (0x1UL)       /*!< Max enumerator value of COMPARE0 field.                              */
37394   #define GRTC_INTENCLR15_COMPARE0_Clear (0x1UL)     /*!< Disable                                                              */
37395   #define GRTC_INTENCLR15_COMPARE0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37396   #define GRTC_INTENCLR15_COMPARE0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37397 
37398 /* COMPARE1 @Bit 1 : Write '1' to disable interrupt for event COMPARE[1] */
37399   #define GRTC_INTENCLR15_COMPARE1_Pos (1UL)         /*!< Position of COMPARE1 field.                                          */
37400   #define GRTC_INTENCLR15_COMPARE1_Msk (0x1UL << GRTC_INTENCLR15_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                */
37401   #define GRTC_INTENCLR15_COMPARE1_Min (0x0UL)       /*!< Min enumerator value of COMPARE1 field.                              */
37402   #define GRTC_INTENCLR15_COMPARE1_Max (0x1UL)       /*!< Max enumerator value of COMPARE1 field.                              */
37403   #define GRTC_INTENCLR15_COMPARE1_Clear (0x1UL)     /*!< Disable                                                              */
37404   #define GRTC_INTENCLR15_COMPARE1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37405   #define GRTC_INTENCLR15_COMPARE1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37406 
37407 /* COMPARE2 @Bit 2 : Write '1' to disable interrupt for event COMPARE[2] */
37408   #define GRTC_INTENCLR15_COMPARE2_Pos (2UL)         /*!< Position of COMPARE2 field.                                          */
37409   #define GRTC_INTENCLR15_COMPARE2_Msk (0x1UL << GRTC_INTENCLR15_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                */
37410   #define GRTC_INTENCLR15_COMPARE2_Min (0x0UL)       /*!< Min enumerator value of COMPARE2 field.                              */
37411   #define GRTC_INTENCLR15_COMPARE2_Max (0x1UL)       /*!< Max enumerator value of COMPARE2 field.                              */
37412   #define GRTC_INTENCLR15_COMPARE2_Clear (0x1UL)     /*!< Disable                                                              */
37413   #define GRTC_INTENCLR15_COMPARE2_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37414   #define GRTC_INTENCLR15_COMPARE2_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37415 
37416 /* COMPARE3 @Bit 3 : Write '1' to disable interrupt for event COMPARE[3] */
37417   #define GRTC_INTENCLR15_COMPARE3_Pos (3UL)         /*!< Position of COMPARE3 field.                                          */
37418   #define GRTC_INTENCLR15_COMPARE3_Msk (0x1UL << GRTC_INTENCLR15_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                */
37419   #define GRTC_INTENCLR15_COMPARE3_Min (0x0UL)       /*!< Min enumerator value of COMPARE3 field.                              */
37420   #define GRTC_INTENCLR15_COMPARE3_Max (0x1UL)       /*!< Max enumerator value of COMPARE3 field.                              */
37421   #define GRTC_INTENCLR15_COMPARE3_Clear (0x1UL)     /*!< Disable                                                              */
37422   #define GRTC_INTENCLR15_COMPARE3_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37423   #define GRTC_INTENCLR15_COMPARE3_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37424 
37425 /* COMPARE4 @Bit 4 : Write '1' to disable interrupt for event COMPARE[4] */
37426   #define GRTC_INTENCLR15_COMPARE4_Pos (4UL)         /*!< Position of COMPARE4 field.                                          */
37427   #define GRTC_INTENCLR15_COMPARE4_Msk (0x1UL << GRTC_INTENCLR15_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                */
37428   #define GRTC_INTENCLR15_COMPARE4_Min (0x0UL)       /*!< Min enumerator value of COMPARE4 field.                              */
37429   #define GRTC_INTENCLR15_COMPARE4_Max (0x1UL)       /*!< Max enumerator value of COMPARE4 field.                              */
37430   #define GRTC_INTENCLR15_COMPARE4_Clear (0x1UL)     /*!< Disable                                                              */
37431   #define GRTC_INTENCLR15_COMPARE4_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37432   #define GRTC_INTENCLR15_COMPARE4_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37433 
37434 /* COMPARE5 @Bit 5 : Write '1' to disable interrupt for event COMPARE[5] */
37435   #define GRTC_INTENCLR15_COMPARE5_Pos (5UL)         /*!< Position of COMPARE5 field.                                          */
37436   #define GRTC_INTENCLR15_COMPARE5_Msk (0x1UL << GRTC_INTENCLR15_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                */
37437   #define GRTC_INTENCLR15_COMPARE5_Min (0x0UL)       /*!< Min enumerator value of COMPARE5 field.                              */
37438   #define GRTC_INTENCLR15_COMPARE5_Max (0x1UL)       /*!< Max enumerator value of COMPARE5 field.                              */
37439   #define GRTC_INTENCLR15_COMPARE5_Clear (0x1UL)     /*!< Disable                                                              */
37440   #define GRTC_INTENCLR15_COMPARE5_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37441   #define GRTC_INTENCLR15_COMPARE5_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37442 
37443 /* COMPARE6 @Bit 6 : Write '1' to disable interrupt for event COMPARE[6] */
37444   #define GRTC_INTENCLR15_COMPARE6_Pos (6UL)         /*!< Position of COMPARE6 field.                                          */
37445   #define GRTC_INTENCLR15_COMPARE6_Msk (0x1UL << GRTC_INTENCLR15_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                */
37446   #define GRTC_INTENCLR15_COMPARE6_Min (0x0UL)       /*!< Min enumerator value of COMPARE6 field.                              */
37447   #define GRTC_INTENCLR15_COMPARE6_Max (0x1UL)       /*!< Max enumerator value of COMPARE6 field.                              */
37448   #define GRTC_INTENCLR15_COMPARE6_Clear (0x1UL)     /*!< Disable                                                              */
37449   #define GRTC_INTENCLR15_COMPARE6_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37450   #define GRTC_INTENCLR15_COMPARE6_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37451 
37452 /* COMPARE7 @Bit 7 : Write '1' to disable interrupt for event COMPARE[7] */
37453   #define GRTC_INTENCLR15_COMPARE7_Pos (7UL)         /*!< Position of COMPARE7 field.                                          */
37454   #define GRTC_INTENCLR15_COMPARE7_Msk (0x1UL << GRTC_INTENCLR15_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                */
37455   #define GRTC_INTENCLR15_COMPARE7_Min (0x0UL)       /*!< Min enumerator value of COMPARE7 field.                              */
37456   #define GRTC_INTENCLR15_COMPARE7_Max (0x1UL)       /*!< Max enumerator value of COMPARE7 field.                              */
37457   #define GRTC_INTENCLR15_COMPARE7_Clear (0x1UL)     /*!< Disable                                                              */
37458   #define GRTC_INTENCLR15_COMPARE7_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37459   #define GRTC_INTENCLR15_COMPARE7_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37460 
37461 /* COMPARE8 @Bit 8 : Write '1' to disable interrupt for event COMPARE[8] */
37462   #define GRTC_INTENCLR15_COMPARE8_Pos (8UL)         /*!< Position of COMPARE8 field.                                          */
37463   #define GRTC_INTENCLR15_COMPARE8_Msk (0x1UL << GRTC_INTENCLR15_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                */
37464   #define GRTC_INTENCLR15_COMPARE8_Min (0x0UL)       /*!< Min enumerator value of COMPARE8 field.                              */
37465   #define GRTC_INTENCLR15_COMPARE8_Max (0x1UL)       /*!< Max enumerator value of COMPARE8 field.                              */
37466   #define GRTC_INTENCLR15_COMPARE8_Clear (0x1UL)     /*!< Disable                                                              */
37467   #define GRTC_INTENCLR15_COMPARE8_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37468   #define GRTC_INTENCLR15_COMPARE8_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37469 
37470 /* COMPARE9 @Bit 9 : Write '1' to disable interrupt for event COMPARE[9] */
37471   #define GRTC_INTENCLR15_COMPARE9_Pos (9UL)         /*!< Position of COMPARE9 field.                                          */
37472   #define GRTC_INTENCLR15_COMPARE9_Msk (0x1UL << GRTC_INTENCLR15_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                */
37473   #define GRTC_INTENCLR15_COMPARE9_Min (0x0UL)       /*!< Min enumerator value of COMPARE9 field.                              */
37474   #define GRTC_INTENCLR15_COMPARE9_Max (0x1UL)       /*!< Max enumerator value of COMPARE9 field.                              */
37475   #define GRTC_INTENCLR15_COMPARE9_Clear (0x1UL)     /*!< Disable                                                              */
37476   #define GRTC_INTENCLR15_COMPARE9_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
37477   #define GRTC_INTENCLR15_COMPARE9_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
37478 
37479 /* COMPARE10 @Bit 10 : Write '1' to disable interrupt for event COMPARE[10] */
37480   #define GRTC_INTENCLR15_COMPARE10_Pos (10UL)       /*!< Position of COMPARE10 field.                                         */
37481   #define GRTC_INTENCLR15_COMPARE10_Msk (0x1UL << GRTC_INTENCLR15_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.             */
37482   #define GRTC_INTENCLR15_COMPARE10_Min (0x0UL)      /*!< Min enumerator value of COMPARE10 field.                             */
37483   #define GRTC_INTENCLR15_COMPARE10_Max (0x1UL)      /*!< Max enumerator value of COMPARE10 field.                             */
37484   #define GRTC_INTENCLR15_COMPARE10_Clear (0x1UL)    /*!< Disable                                                              */
37485   #define GRTC_INTENCLR15_COMPARE10_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37486   #define GRTC_INTENCLR15_COMPARE10_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37487 
37488 /* COMPARE11 @Bit 11 : Write '1' to disable interrupt for event COMPARE[11] */
37489   #define GRTC_INTENCLR15_COMPARE11_Pos (11UL)       /*!< Position of COMPARE11 field.                                         */
37490   #define GRTC_INTENCLR15_COMPARE11_Msk (0x1UL << GRTC_INTENCLR15_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.             */
37491   #define GRTC_INTENCLR15_COMPARE11_Min (0x0UL)      /*!< Min enumerator value of COMPARE11 field.                             */
37492   #define GRTC_INTENCLR15_COMPARE11_Max (0x1UL)      /*!< Max enumerator value of COMPARE11 field.                             */
37493   #define GRTC_INTENCLR15_COMPARE11_Clear (0x1UL)    /*!< Disable                                                              */
37494   #define GRTC_INTENCLR15_COMPARE11_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37495   #define GRTC_INTENCLR15_COMPARE11_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37496 
37497 /* COMPARE12 @Bit 12 : Write '1' to disable interrupt for event COMPARE[12] */
37498   #define GRTC_INTENCLR15_COMPARE12_Pos (12UL)       /*!< Position of COMPARE12 field.                                         */
37499   #define GRTC_INTENCLR15_COMPARE12_Msk (0x1UL << GRTC_INTENCLR15_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.             */
37500   #define GRTC_INTENCLR15_COMPARE12_Min (0x0UL)      /*!< Min enumerator value of COMPARE12 field.                             */
37501   #define GRTC_INTENCLR15_COMPARE12_Max (0x1UL)      /*!< Max enumerator value of COMPARE12 field.                             */
37502   #define GRTC_INTENCLR15_COMPARE12_Clear (0x1UL)    /*!< Disable                                                              */
37503   #define GRTC_INTENCLR15_COMPARE12_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37504   #define GRTC_INTENCLR15_COMPARE12_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37505 
37506 /* COMPARE13 @Bit 13 : Write '1' to disable interrupt for event COMPARE[13] */
37507   #define GRTC_INTENCLR15_COMPARE13_Pos (13UL)       /*!< Position of COMPARE13 field.                                         */
37508   #define GRTC_INTENCLR15_COMPARE13_Msk (0x1UL << GRTC_INTENCLR15_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.             */
37509   #define GRTC_INTENCLR15_COMPARE13_Min (0x0UL)      /*!< Min enumerator value of COMPARE13 field.                             */
37510   #define GRTC_INTENCLR15_COMPARE13_Max (0x1UL)      /*!< Max enumerator value of COMPARE13 field.                             */
37511   #define GRTC_INTENCLR15_COMPARE13_Clear (0x1UL)    /*!< Disable                                                              */
37512   #define GRTC_INTENCLR15_COMPARE13_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37513   #define GRTC_INTENCLR15_COMPARE13_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37514 
37515 /* COMPARE14 @Bit 14 : Write '1' to disable interrupt for event COMPARE[14] */
37516   #define GRTC_INTENCLR15_COMPARE14_Pos (14UL)       /*!< Position of COMPARE14 field.                                         */
37517   #define GRTC_INTENCLR15_COMPARE14_Msk (0x1UL << GRTC_INTENCLR15_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.             */
37518   #define GRTC_INTENCLR15_COMPARE14_Min (0x0UL)      /*!< Min enumerator value of COMPARE14 field.                             */
37519   #define GRTC_INTENCLR15_COMPARE14_Max (0x1UL)      /*!< Max enumerator value of COMPARE14 field.                             */
37520   #define GRTC_INTENCLR15_COMPARE14_Clear (0x1UL)    /*!< Disable                                                              */
37521   #define GRTC_INTENCLR15_COMPARE14_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37522   #define GRTC_INTENCLR15_COMPARE14_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37523 
37524 /* COMPARE15 @Bit 15 : Write '1' to disable interrupt for event COMPARE[15] */
37525   #define GRTC_INTENCLR15_COMPARE15_Pos (15UL)       /*!< Position of COMPARE15 field.                                         */
37526   #define GRTC_INTENCLR15_COMPARE15_Msk (0x1UL << GRTC_INTENCLR15_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.             */
37527   #define GRTC_INTENCLR15_COMPARE15_Min (0x0UL)      /*!< Min enumerator value of COMPARE15 field.                             */
37528   #define GRTC_INTENCLR15_COMPARE15_Max (0x1UL)      /*!< Max enumerator value of COMPARE15 field.                             */
37529   #define GRTC_INTENCLR15_COMPARE15_Clear (0x1UL)    /*!< Disable                                                              */
37530   #define GRTC_INTENCLR15_COMPARE15_Disabled (0x0UL) /*!< Read: Disabled                                                       */
37531   #define GRTC_INTENCLR15_COMPARE15_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
37532 
37533 /* SYSCOUNTERVALID @Bit 26 : Write '1' to disable interrupt for event SYSCOUNTERVALID */
37534   #define GRTC_INTENCLR15_SYSCOUNTERVALID_Pos (26UL) /*!< Position of SYSCOUNTERVALID field.                                   */
37535   #define GRTC_INTENCLR15_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTENCLR15_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
37536                                                                             field.*/
37537   #define GRTC_INTENCLR15_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                      */
37538   #define GRTC_INTENCLR15_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                      */
37539   #define GRTC_INTENCLR15_SYSCOUNTERVALID_Clear (0x1UL) /*!< Disable                                                           */
37540   #define GRTC_INTENCLR15_SYSCOUNTERVALID_Disabled (0x0UL) /*!< Read: Disabled                                                 */
37541   #define GRTC_INTENCLR15_SYSCOUNTERVALID_Enabled (0x1UL) /*!< Read: Enabled                                                   */
37542 
37543 
37544 /* GRTC_INTPEND15: Pending interrupts */
37545   #define GRTC_INTPEND15_ResetValue (0x00000000UL)   /*!< Reset value of INTPEND15 register.                                   */
37546 
37547 /* COMPARE0 @Bit 0 : Read pending status of interrupt for event COMPARE[0] */
37548   #define GRTC_INTPEND15_COMPARE0_Pos (0UL)          /*!< Position of COMPARE0 field.                                          */
37549   #define GRTC_INTPEND15_COMPARE0_Msk (0x1UL << GRTC_INTPEND15_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
37550   #define GRTC_INTPEND15_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
37551   #define GRTC_INTPEND15_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
37552   #define GRTC_INTPEND15_COMPARE0_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37553   #define GRTC_INTPEND15_COMPARE0_Pending (0x1UL)    /*!< Read: Pending                                                        */
37554 
37555 /* COMPARE1 @Bit 1 : Read pending status of interrupt for event COMPARE[1] */
37556   #define GRTC_INTPEND15_COMPARE1_Pos (1UL)          /*!< Position of COMPARE1 field.                                          */
37557   #define GRTC_INTPEND15_COMPARE1_Msk (0x1UL << GRTC_INTPEND15_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
37558   #define GRTC_INTPEND15_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
37559   #define GRTC_INTPEND15_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
37560   #define GRTC_INTPEND15_COMPARE1_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37561   #define GRTC_INTPEND15_COMPARE1_Pending (0x1UL)    /*!< Read: Pending                                                        */
37562 
37563 /* COMPARE2 @Bit 2 : Read pending status of interrupt for event COMPARE[2] */
37564   #define GRTC_INTPEND15_COMPARE2_Pos (2UL)          /*!< Position of COMPARE2 field.                                          */
37565   #define GRTC_INTPEND15_COMPARE2_Msk (0x1UL << GRTC_INTPEND15_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
37566   #define GRTC_INTPEND15_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
37567   #define GRTC_INTPEND15_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
37568   #define GRTC_INTPEND15_COMPARE2_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37569   #define GRTC_INTPEND15_COMPARE2_Pending (0x1UL)    /*!< Read: Pending                                                        */
37570 
37571 /* COMPARE3 @Bit 3 : Read pending status of interrupt for event COMPARE[3] */
37572   #define GRTC_INTPEND15_COMPARE3_Pos (3UL)          /*!< Position of COMPARE3 field.                                          */
37573   #define GRTC_INTPEND15_COMPARE3_Msk (0x1UL << GRTC_INTPEND15_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
37574   #define GRTC_INTPEND15_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
37575   #define GRTC_INTPEND15_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
37576   #define GRTC_INTPEND15_COMPARE3_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37577   #define GRTC_INTPEND15_COMPARE3_Pending (0x1UL)    /*!< Read: Pending                                                        */
37578 
37579 /* COMPARE4 @Bit 4 : Read pending status of interrupt for event COMPARE[4] */
37580   #define GRTC_INTPEND15_COMPARE4_Pos (4UL)          /*!< Position of COMPARE4 field.                                          */
37581   #define GRTC_INTPEND15_COMPARE4_Msk (0x1UL << GRTC_INTPEND15_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
37582   #define GRTC_INTPEND15_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
37583   #define GRTC_INTPEND15_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
37584   #define GRTC_INTPEND15_COMPARE4_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37585   #define GRTC_INTPEND15_COMPARE4_Pending (0x1UL)    /*!< Read: Pending                                                        */
37586 
37587 /* COMPARE5 @Bit 5 : Read pending status of interrupt for event COMPARE[5] */
37588   #define GRTC_INTPEND15_COMPARE5_Pos (5UL)          /*!< Position of COMPARE5 field.                                          */
37589   #define GRTC_INTPEND15_COMPARE5_Msk (0x1UL << GRTC_INTPEND15_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
37590   #define GRTC_INTPEND15_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
37591   #define GRTC_INTPEND15_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
37592   #define GRTC_INTPEND15_COMPARE5_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37593   #define GRTC_INTPEND15_COMPARE5_Pending (0x1UL)    /*!< Read: Pending                                                        */
37594 
37595 /* COMPARE6 @Bit 6 : Read pending status of interrupt for event COMPARE[6] */
37596   #define GRTC_INTPEND15_COMPARE6_Pos (6UL)          /*!< Position of COMPARE6 field.                                          */
37597   #define GRTC_INTPEND15_COMPARE6_Msk (0x1UL << GRTC_INTPEND15_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
37598   #define GRTC_INTPEND15_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
37599   #define GRTC_INTPEND15_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
37600   #define GRTC_INTPEND15_COMPARE6_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37601   #define GRTC_INTPEND15_COMPARE6_Pending (0x1UL)    /*!< Read: Pending                                                        */
37602 
37603 /* COMPARE7 @Bit 7 : Read pending status of interrupt for event COMPARE[7] */
37604   #define GRTC_INTPEND15_COMPARE7_Pos (7UL)          /*!< Position of COMPARE7 field.                                          */
37605   #define GRTC_INTPEND15_COMPARE7_Msk (0x1UL << GRTC_INTPEND15_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
37606   #define GRTC_INTPEND15_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
37607   #define GRTC_INTPEND15_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
37608   #define GRTC_INTPEND15_COMPARE7_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37609   #define GRTC_INTPEND15_COMPARE7_Pending (0x1UL)    /*!< Read: Pending                                                        */
37610 
37611 /* COMPARE8 @Bit 8 : Read pending status of interrupt for event COMPARE[8] */
37612   #define GRTC_INTPEND15_COMPARE8_Pos (8UL)          /*!< Position of COMPARE8 field.                                          */
37613   #define GRTC_INTPEND15_COMPARE8_Msk (0x1UL << GRTC_INTPEND15_COMPARE8_Pos) /*!< Bit mask of COMPARE8 field.                  */
37614   #define GRTC_INTPEND15_COMPARE8_Min (0x0UL)        /*!< Min enumerator value of COMPARE8 field.                              */
37615   #define GRTC_INTPEND15_COMPARE8_Max (0x1UL)        /*!< Max enumerator value of COMPARE8 field.                              */
37616   #define GRTC_INTPEND15_COMPARE8_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37617   #define GRTC_INTPEND15_COMPARE8_Pending (0x1UL)    /*!< Read: Pending                                                        */
37618 
37619 /* COMPARE9 @Bit 9 : Read pending status of interrupt for event COMPARE[9] */
37620   #define GRTC_INTPEND15_COMPARE9_Pos (9UL)          /*!< Position of COMPARE9 field.                                          */
37621   #define GRTC_INTPEND15_COMPARE9_Msk (0x1UL << GRTC_INTPEND15_COMPARE9_Pos) /*!< Bit mask of COMPARE9 field.                  */
37622   #define GRTC_INTPEND15_COMPARE9_Min (0x0UL)        /*!< Min enumerator value of COMPARE9 field.                              */
37623   #define GRTC_INTPEND15_COMPARE9_Max (0x1UL)        /*!< Max enumerator value of COMPARE9 field.                              */
37624   #define GRTC_INTPEND15_COMPARE9_NotPending (0x0UL) /*!< Read: Not pending                                                    */
37625   #define GRTC_INTPEND15_COMPARE9_Pending (0x1UL)    /*!< Read: Pending                                                        */
37626 
37627 /* COMPARE10 @Bit 10 : Read pending status of interrupt for event COMPARE[10] */
37628   #define GRTC_INTPEND15_COMPARE10_Pos (10UL)        /*!< Position of COMPARE10 field.                                         */
37629   #define GRTC_INTPEND15_COMPARE10_Msk (0x1UL << GRTC_INTPEND15_COMPARE10_Pos) /*!< Bit mask of COMPARE10 field.               */
37630   #define GRTC_INTPEND15_COMPARE10_Min (0x0UL)       /*!< Min enumerator value of COMPARE10 field.                             */
37631   #define GRTC_INTPEND15_COMPARE10_Max (0x1UL)       /*!< Max enumerator value of COMPARE10 field.                             */
37632   #define GRTC_INTPEND15_COMPARE10_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37633   #define GRTC_INTPEND15_COMPARE10_Pending (0x1UL)   /*!< Read: Pending                                                        */
37634 
37635 /* COMPARE11 @Bit 11 : Read pending status of interrupt for event COMPARE[11] */
37636   #define GRTC_INTPEND15_COMPARE11_Pos (11UL)        /*!< Position of COMPARE11 field.                                         */
37637   #define GRTC_INTPEND15_COMPARE11_Msk (0x1UL << GRTC_INTPEND15_COMPARE11_Pos) /*!< Bit mask of COMPARE11 field.               */
37638   #define GRTC_INTPEND15_COMPARE11_Min (0x0UL)       /*!< Min enumerator value of COMPARE11 field.                             */
37639   #define GRTC_INTPEND15_COMPARE11_Max (0x1UL)       /*!< Max enumerator value of COMPARE11 field.                             */
37640   #define GRTC_INTPEND15_COMPARE11_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37641   #define GRTC_INTPEND15_COMPARE11_Pending (0x1UL)   /*!< Read: Pending                                                        */
37642 
37643 /* COMPARE12 @Bit 12 : Read pending status of interrupt for event COMPARE[12] */
37644   #define GRTC_INTPEND15_COMPARE12_Pos (12UL)        /*!< Position of COMPARE12 field.                                         */
37645   #define GRTC_INTPEND15_COMPARE12_Msk (0x1UL << GRTC_INTPEND15_COMPARE12_Pos) /*!< Bit mask of COMPARE12 field.               */
37646   #define GRTC_INTPEND15_COMPARE12_Min (0x0UL)       /*!< Min enumerator value of COMPARE12 field.                             */
37647   #define GRTC_INTPEND15_COMPARE12_Max (0x1UL)       /*!< Max enumerator value of COMPARE12 field.                             */
37648   #define GRTC_INTPEND15_COMPARE12_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37649   #define GRTC_INTPEND15_COMPARE12_Pending (0x1UL)   /*!< Read: Pending                                                        */
37650 
37651 /* COMPARE13 @Bit 13 : Read pending status of interrupt for event COMPARE[13] */
37652   #define GRTC_INTPEND15_COMPARE13_Pos (13UL)        /*!< Position of COMPARE13 field.                                         */
37653   #define GRTC_INTPEND15_COMPARE13_Msk (0x1UL << GRTC_INTPEND15_COMPARE13_Pos) /*!< Bit mask of COMPARE13 field.               */
37654   #define GRTC_INTPEND15_COMPARE13_Min (0x0UL)       /*!< Min enumerator value of COMPARE13 field.                             */
37655   #define GRTC_INTPEND15_COMPARE13_Max (0x1UL)       /*!< Max enumerator value of COMPARE13 field.                             */
37656   #define GRTC_INTPEND15_COMPARE13_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37657   #define GRTC_INTPEND15_COMPARE13_Pending (0x1UL)   /*!< Read: Pending                                                        */
37658 
37659 /* COMPARE14 @Bit 14 : Read pending status of interrupt for event COMPARE[14] */
37660   #define GRTC_INTPEND15_COMPARE14_Pos (14UL)        /*!< Position of COMPARE14 field.                                         */
37661   #define GRTC_INTPEND15_COMPARE14_Msk (0x1UL << GRTC_INTPEND15_COMPARE14_Pos) /*!< Bit mask of COMPARE14 field.               */
37662   #define GRTC_INTPEND15_COMPARE14_Min (0x0UL)       /*!< Min enumerator value of COMPARE14 field.                             */
37663   #define GRTC_INTPEND15_COMPARE14_Max (0x1UL)       /*!< Max enumerator value of COMPARE14 field.                             */
37664   #define GRTC_INTPEND15_COMPARE14_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37665   #define GRTC_INTPEND15_COMPARE14_Pending (0x1UL)   /*!< Read: Pending                                                        */
37666 
37667 /* COMPARE15 @Bit 15 : Read pending status of interrupt for event COMPARE[15] */
37668   #define GRTC_INTPEND15_COMPARE15_Pos (15UL)        /*!< Position of COMPARE15 field.                                         */
37669   #define GRTC_INTPEND15_COMPARE15_Msk (0x1UL << GRTC_INTPEND15_COMPARE15_Pos) /*!< Bit mask of COMPARE15 field.               */
37670   #define GRTC_INTPEND15_COMPARE15_Min (0x0UL)       /*!< Min enumerator value of COMPARE15 field.                             */
37671   #define GRTC_INTPEND15_COMPARE15_Max (0x1UL)       /*!< Max enumerator value of COMPARE15 field.                             */
37672   #define GRTC_INTPEND15_COMPARE15_NotPending (0x0UL) /*!< Read: Not pending                                                   */
37673   #define GRTC_INTPEND15_COMPARE15_Pending (0x1UL)   /*!< Read: Pending                                                        */
37674 
37675 /* SYSCOUNTERVALID @Bit 26 : Read pending status of interrupt for event SYSCOUNTERVALID */
37676   #define GRTC_INTPEND15_SYSCOUNTERVALID_Pos (26UL)  /*!< Position of SYSCOUNTERVALID field.                                   */
37677   #define GRTC_INTPEND15_SYSCOUNTERVALID_Msk (0x1UL << GRTC_INTPEND15_SYSCOUNTERVALID_Pos) /*!< Bit mask of SYSCOUNTERVALID
37678                                                                             field.*/
37679   #define GRTC_INTPEND15_SYSCOUNTERVALID_Min (0x0UL) /*!< Min enumerator value of SYSCOUNTERVALID field.                       */
37680   #define GRTC_INTPEND15_SYSCOUNTERVALID_Max (0x1UL) /*!< Max enumerator value of SYSCOUNTERVALID field.                       */
37681   #define GRTC_INTPEND15_SYSCOUNTERVALID_NotPending (0x0UL) /*!< Read: Not pending                                             */
37682   #define GRTC_INTPEND15_SYSCOUNTERVALID_Pending (0x1UL) /*!< Read: Pending                                                    */
37683 
37684 
37685 /* GRTC_MODE: Counter mode selection */
37686   #define GRTC_MODE_ResetValue (0x00000000UL)        /*!< Reset value of MODE register.                                        */
37687 
37688 /* AUTOEN @Bit 0 : Automatic enable to keep the SYSCOUNTER active. */
37689   #define GRTC_MODE_AUTOEN_Pos (0UL)                 /*!< Position of AUTOEN field.                                            */
37690   #define GRTC_MODE_AUTOEN_Msk (0x1UL << GRTC_MODE_AUTOEN_Pos) /*!< Bit mask of AUTOEN field.                                  */
37691   #define GRTC_MODE_AUTOEN_Min (0x0UL)               /*!< Min enumerator value of AUTOEN field.                                */
37692   #define GRTC_MODE_AUTOEN_Max (0x1UL)               /*!< Max enumerator value of AUTOEN field.                                */
37693   #define GRTC_MODE_AUTOEN_Default (0x0UL)           /*!< Default configuration to keep the SYSCOUNTER active.                 */
37694   #define GRTC_MODE_AUTOEN_CpuActive (0x1UL)         /*!< In addition to the above mode, any local CPU that is not sleeping keep
37695                                                           the SYSCOUNTER active.*/
37696 
37697 /* SYSCOUNTEREN @Bit 1 : Enable the SYSCOUNTER */
37698   #define GRTC_MODE_SYSCOUNTEREN_Pos (1UL)           /*!< Position of SYSCOUNTEREN field.                                      */
37699   #define GRTC_MODE_SYSCOUNTEREN_Msk (0x1UL << GRTC_MODE_SYSCOUNTEREN_Pos) /*!< Bit mask of SYSCOUNTEREN field.                */
37700   #define GRTC_MODE_SYSCOUNTEREN_Min (0x0UL)         /*!< Min enumerator value of SYSCOUNTEREN field.                          */
37701   #define GRTC_MODE_SYSCOUNTEREN_Max (0x1UL)         /*!< Max enumerator value of SYSCOUNTEREN field.                          */
37702   #define GRTC_MODE_SYSCOUNTEREN_Disabled (0x0UL)    /*!< SYSCOUNTER disabled                                                  */
37703   #define GRTC_MODE_SYSCOUNTEREN_Enabled (0x1UL)     /*!< SYSCOUNTER enabled                                                   */
37704 
37705 
37706 /* GRTC_SYSCOUNTERL: The lower 32-bits of the SYSCOUNTER */
37707   #define GRTC_SYSCOUNTERL_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTERL register.                                 */
37708 
37709 /* VALUE @Bits 0..31 : The lower 32-bits of the SYSCOUNTER value. */
37710   #define GRTC_SYSCOUNTERL_VALUE_Pos (0UL)           /*!< Position of VALUE field.                                             */
37711   #define GRTC_SYSCOUNTERL_VALUE_Msk (0xFFFFFFFFUL << GRTC_SYSCOUNTERL_VALUE_Pos) /*!< Bit mask of VALUE field.                */
37712 
37713 
37714 /* GRTC_SYSCOUNTERH: The higher 20-bits of the SYSCOUNTER */
37715   #define GRTC_SYSCOUNTERH_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTERH register.                                 */
37716 
37717 /* VALUE @Bits 0..19 : The higher 20-bits of the SYSCOUNTER value. */
37718   #define GRTC_SYSCOUNTERH_VALUE_Pos (0UL)           /*!< Position of VALUE field.                                             */
37719   #define GRTC_SYSCOUNTERH_VALUE_Msk (0xFFFFFUL << GRTC_SYSCOUNTERH_VALUE_Pos) /*!< Bit mask of VALUE field.                   */
37720 
37721 /* OVERFLOW @Bit 31 : The SYSCOUNTERL overflow indication after reading it. */
37722   #define GRTC_SYSCOUNTERH_OVERFLOW_Pos (31UL)       /*!< Position of OVERFLOW field.                                          */
37723   #define GRTC_SYSCOUNTERH_OVERFLOW_Msk (0x1UL << GRTC_SYSCOUNTERH_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field.              */
37724   #define GRTC_SYSCOUNTERH_OVERFLOW_Min (0x0UL)      /*!< Min enumerator value of OVERFLOW field.                              */
37725   #define GRTC_SYSCOUNTERH_OVERFLOW_Max (0x1UL)      /*!< Max enumerator value of OVERFLOW field.                              */
37726   #define GRTC_SYSCOUNTERH_OVERFLOW_NoOverflow (0x0UL) /*!< SYSCOUNTERL is not overflown                                       */
37727   #define GRTC_SYSCOUNTERH_OVERFLOW_Overflow (0x1UL) /*!< SYSCOUNTERL overflown                                                */
37728 
37729 
37730 /* GRTC_KEEPRUNNING: Request to keep the SYSCOUNTER in the active state and prevent going to sleep */
37731   #define GRTC_KEEPRUNNING_ResetValue (0x00000000UL) /*!< Reset value of KEEPRUNNING register.                                 */
37732 
37733 /* DOMAIN0 @Bit 0 : Request from the Domain [0] */
37734   #define GRTC_KEEPRUNNING_DOMAIN0_Pos (0UL)         /*!< Position of DOMAIN0 field.                                           */
37735   #define GRTC_KEEPRUNNING_DOMAIN0_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN0_Pos) /*!< Bit mask of DOMAIN0 field.                 */
37736   #define GRTC_KEEPRUNNING_DOMAIN0_Min (0x0UL)       /*!< Min enumerator value of DOMAIN0 field.                               */
37737   #define GRTC_KEEPRUNNING_DOMAIN0_Max (0x1UL)       /*!< Max enumerator value of DOMAIN0 field.                               */
37738   #define GRTC_KEEPRUNNING_DOMAIN0_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37739   #define GRTC_KEEPRUNNING_DOMAIN0_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37740 
37741 /* DOMAIN1 @Bit 1 : Request from the Domain [1] */
37742   #define GRTC_KEEPRUNNING_DOMAIN1_Pos (1UL)         /*!< Position of DOMAIN1 field.                                           */
37743   #define GRTC_KEEPRUNNING_DOMAIN1_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN1_Pos) /*!< Bit mask of DOMAIN1 field.                 */
37744   #define GRTC_KEEPRUNNING_DOMAIN1_Min (0x0UL)       /*!< Min enumerator value of DOMAIN1 field.                               */
37745   #define GRTC_KEEPRUNNING_DOMAIN1_Max (0x1UL)       /*!< Max enumerator value of DOMAIN1 field.                               */
37746   #define GRTC_KEEPRUNNING_DOMAIN1_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37747   #define GRTC_KEEPRUNNING_DOMAIN1_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37748 
37749 /* DOMAIN2 @Bit 2 : Request from the Domain [2] */
37750   #define GRTC_KEEPRUNNING_DOMAIN2_Pos (2UL)         /*!< Position of DOMAIN2 field.                                           */
37751   #define GRTC_KEEPRUNNING_DOMAIN2_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN2_Pos) /*!< Bit mask of DOMAIN2 field.                 */
37752   #define GRTC_KEEPRUNNING_DOMAIN2_Min (0x0UL)       /*!< Min enumerator value of DOMAIN2 field.                               */
37753   #define GRTC_KEEPRUNNING_DOMAIN2_Max (0x1UL)       /*!< Max enumerator value of DOMAIN2 field.                               */
37754   #define GRTC_KEEPRUNNING_DOMAIN2_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37755   #define GRTC_KEEPRUNNING_DOMAIN2_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37756 
37757 /* DOMAIN3 @Bit 3 : Request from the Domain [3] */
37758   #define GRTC_KEEPRUNNING_DOMAIN3_Pos (3UL)         /*!< Position of DOMAIN3 field.                                           */
37759   #define GRTC_KEEPRUNNING_DOMAIN3_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN3_Pos) /*!< Bit mask of DOMAIN3 field.                 */
37760   #define GRTC_KEEPRUNNING_DOMAIN3_Min (0x0UL)       /*!< Min enumerator value of DOMAIN3 field.                               */
37761   #define GRTC_KEEPRUNNING_DOMAIN3_Max (0x1UL)       /*!< Max enumerator value of DOMAIN3 field.                               */
37762   #define GRTC_KEEPRUNNING_DOMAIN3_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37763   #define GRTC_KEEPRUNNING_DOMAIN3_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37764 
37765 /* DOMAIN4 @Bit 4 : Request from the Domain [4] */
37766   #define GRTC_KEEPRUNNING_DOMAIN4_Pos (4UL)         /*!< Position of DOMAIN4 field.                                           */
37767   #define GRTC_KEEPRUNNING_DOMAIN4_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN4_Pos) /*!< Bit mask of DOMAIN4 field.                 */
37768   #define GRTC_KEEPRUNNING_DOMAIN4_Min (0x0UL)       /*!< Min enumerator value of DOMAIN4 field.                               */
37769   #define GRTC_KEEPRUNNING_DOMAIN4_Max (0x1UL)       /*!< Max enumerator value of DOMAIN4 field.                               */
37770   #define GRTC_KEEPRUNNING_DOMAIN4_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37771   #define GRTC_KEEPRUNNING_DOMAIN4_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37772 
37773 /* DOMAIN5 @Bit 5 : Request from the Domain [5] */
37774   #define GRTC_KEEPRUNNING_DOMAIN5_Pos (5UL)         /*!< Position of DOMAIN5 field.                                           */
37775   #define GRTC_KEEPRUNNING_DOMAIN5_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN5_Pos) /*!< Bit mask of DOMAIN5 field.                 */
37776   #define GRTC_KEEPRUNNING_DOMAIN5_Min (0x0UL)       /*!< Min enumerator value of DOMAIN5 field.                               */
37777   #define GRTC_KEEPRUNNING_DOMAIN5_Max (0x1UL)       /*!< Max enumerator value of DOMAIN5 field.                               */
37778   #define GRTC_KEEPRUNNING_DOMAIN5_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37779   #define GRTC_KEEPRUNNING_DOMAIN5_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37780 
37781 /* DOMAIN6 @Bit 6 : Request from the Domain [6] */
37782   #define GRTC_KEEPRUNNING_DOMAIN6_Pos (6UL)         /*!< Position of DOMAIN6 field.                                           */
37783   #define GRTC_KEEPRUNNING_DOMAIN6_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN6_Pos) /*!< Bit mask of DOMAIN6 field.                 */
37784   #define GRTC_KEEPRUNNING_DOMAIN6_Min (0x0UL)       /*!< Min enumerator value of DOMAIN6 field.                               */
37785   #define GRTC_KEEPRUNNING_DOMAIN6_Max (0x1UL)       /*!< Max enumerator value of DOMAIN6 field.                               */
37786   #define GRTC_KEEPRUNNING_DOMAIN6_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37787   #define GRTC_KEEPRUNNING_DOMAIN6_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37788 
37789 /* DOMAIN7 @Bit 7 : Request from the Domain [7] */
37790   #define GRTC_KEEPRUNNING_DOMAIN7_Pos (7UL)         /*!< Position of DOMAIN7 field.                                           */
37791   #define GRTC_KEEPRUNNING_DOMAIN7_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN7_Pos) /*!< Bit mask of DOMAIN7 field.                 */
37792   #define GRTC_KEEPRUNNING_DOMAIN7_Min (0x0UL)       /*!< Min enumerator value of DOMAIN7 field.                               */
37793   #define GRTC_KEEPRUNNING_DOMAIN7_Max (0x1UL)       /*!< Max enumerator value of DOMAIN7 field.                               */
37794   #define GRTC_KEEPRUNNING_DOMAIN7_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37795   #define GRTC_KEEPRUNNING_DOMAIN7_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37796 
37797 /* DOMAIN8 @Bit 8 : Request from the Domain [8] */
37798   #define GRTC_KEEPRUNNING_DOMAIN8_Pos (8UL)         /*!< Position of DOMAIN8 field.                                           */
37799   #define GRTC_KEEPRUNNING_DOMAIN8_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN8_Pos) /*!< Bit mask of DOMAIN8 field.                 */
37800   #define GRTC_KEEPRUNNING_DOMAIN8_Min (0x0UL)       /*!< Min enumerator value of DOMAIN8 field.                               */
37801   #define GRTC_KEEPRUNNING_DOMAIN8_Max (0x1UL)       /*!< Max enumerator value of DOMAIN8 field.                               */
37802   #define GRTC_KEEPRUNNING_DOMAIN8_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37803   #define GRTC_KEEPRUNNING_DOMAIN8_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37804 
37805 /* DOMAIN9 @Bit 9 : Request from the Domain [9] */
37806   #define GRTC_KEEPRUNNING_DOMAIN9_Pos (9UL)         /*!< Position of DOMAIN9 field.                                           */
37807   #define GRTC_KEEPRUNNING_DOMAIN9_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN9_Pos) /*!< Bit mask of DOMAIN9 field.                 */
37808   #define GRTC_KEEPRUNNING_DOMAIN9_Min (0x0UL)       /*!< Min enumerator value of DOMAIN9 field.                               */
37809   #define GRTC_KEEPRUNNING_DOMAIN9_Max (0x1UL)       /*!< Max enumerator value of DOMAIN9 field.                               */
37810   #define GRTC_KEEPRUNNING_DOMAIN9_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                      */
37811   #define GRTC_KEEPRUNNING_DOMAIN9_Active (0x1UL)    /*!< Keep SYSCOUNTER active                                               */
37812 
37813 /* DOMAIN10 @Bit 10 : Request from the Domain [10] */
37814   #define GRTC_KEEPRUNNING_DOMAIN10_Pos (10UL)       /*!< Position of DOMAIN10 field.                                          */
37815   #define GRTC_KEEPRUNNING_DOMAIN10_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN10_Pos) /*!< Bit mask of DOMAIN10 field.              */
37816   #define GRTC_KEEPRUNNING_DOMAIN10_Min (0x0UL)      /*!< Min enumerator value of DOMAIN10 field.                              */
37817   #define GRTC_KEEPRUNNING_DOMAIN10_Max (0x1UL)      /*!< Max enumerator value of DOMAIN10 field.                              */
37818   #define GRTC_KEEPRUNNING_DOMAIN10_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                     */
37819   #define GRTC_KEEPRUNNING_DOMAIN10_Active (0x1UL)   /*!< Keep SYSCOUNTER active                                               */
37820 
37821 /* DOMAIN11 @Bit 11 : Request from the Domain [11] */
37822   #define GRTC_KEEPRUNNING_DOMAIN11_Pos (11UL)       /*!< Position of DOMAIN11 field.                                          */
37823   #define GRTC_KEEPRUNNING_DOMAIN11_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN11_Pos) /*!< Bit mask of DOMAIN11 field.              */
37824   #define GRTC_KEEPRUNNING_DOMAIN11_Min (0x0UL)      /*!< Min enumerator value of DOMAIN11 field.                              */
37825   #define GRTC_KEEPRUNNING_DOMAIN11_Max (0x1UL)      /*!< Max enumerator value of DOMAIN11 field.                              */
37826   #define GRTC_KEEPRUNNING_DOMAIN11_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                     */
37827   #define GRTC_KEEPRUNNING_DOMAIN11_Active (0x1UL)   /*!< Keep SYSCOUNTER active                                               */
37828 
37829 /* DOMAIN12 @Bit 12 : Request from the Domain [12] */
37830   #define GRTC_KEEPRUNNING_DOMAIN12_Pos (12UL)       /*!< Position of DOMAIN12 field.                                          */
37831   #define GRTC_KEEPRUNNING_DOMAIN12_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN12_Pos) /*!< Bit mask of DOMAIN12 field.              */
37832   #define GRTC_KEEPRUNNING_DOMAIN12_Min (0x0UL)      /*!< Min enumerator value of DOMAIN12 field.                              */
37833   #define GRTC_KEEPRUNNING_DOMAIN12_Max (0x1UL)      /*!< Max enumerator value of DOMAIN12 field.                              */
37834   #define GRTC_KEEPRUNNING_DOMAIN12_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                     */
37835   #define GRTC_KEEPRUNNING_DOMAIN12_Active (0x1UL)   /*!< Keep SYSCOUNTER active                                               */
37836 
37837 /* DOMAIN13 @Bit 13 : Request from the Domain [13] */
37838   #define GRTC_KEEPRUNNING_DOMAIN13_Pos (13UL)       /*!< Position of DOMAIN13 field.                                          */
37839   #define GRTC_KEEPRUNNING_DOMAIN13_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN13_Pos) /*!< Bit mask of DOMAIN13 field.              */
37840   #define GRTC_KEEPRUNNING_DOMAIN13_Min (0x0UL)      /*!< Min enumerator value of DOMAIN13 field.                              */
37841   #define GRTC_KEEPRUNNING_DOMAIN13_Max (0x1UL)      /*!< Max enumerator value of DOMAIN13 field.                              */
37842   #define GRTC_KEEPRUNNING_DOMAIN13_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                     */
37843   #define GRTC_KEEPRUNNING_DOMAIN13_Active (0x1UL)   /*!< Keep SYSCOUNTER active                                               */
37844 
37845 /* DOMAIN14 @Bit 14 : Request from the Domain [14] */
37846   #define GRTC_KEEPRUNNING_DOMAIN14_Pos (14UL)       /*!< Position of DOMAIN14 field.                                          */
37847   #define GRTC_KEEPRUNNING_DOMAIN14_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN14_Pos) /*!< Bit mask of DOMAIN14 field.              */
37848   #define GRTC_KEEPRUNNING_DOMAIN14_Min (0x0UL)      /*!< Min enumerator value of DOMAIN14 field.                              */
37849   #define GRTC_KEEPRUNNING_DOMAIN14_Max (0x1UL)      /*!< Max enumerator value of DOMAIN14 field.                              */
37850   #define GRTC_KEEPRUNNING_DOMAIN14_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                     */
37851   #define GRTC_KEEPRUNNING_DOMAIN14_Active (0x1UL)   /*!< Keep SYSCOUNTER active                                               */
37852 
37853 /* DOMAIN15 @Bit 15 : Request from the Domain [15] */
37854   #define GRTC_KEEPRUNNING_DOMAIN15_Pos (15UL)       /*!< Position of DOMAIN15 field.                                          */
37855   #define GRTC_KEEPRUNNING_DOMAIN15_Msk (0x1UL << GRTC_KEEPRUNNING_DOMAIN15_Pos) /*!< Bit mask of DOMAIN15 field.              */
37856   #define GRTC_KEEPRUNNING_DOMAIN15_Min (0x0UL)      /*!< Min enumerator value of DOMAIN15 field.                              */
37857   #define GRTC_KEEPRUNNING_DOMAIN15_Max (0x1UL)      /*!< Max enumerator value of DOMAIN15 field.                              */
37858   #define GRTC_KEEPRUNNING_DOMAIN15_NotActive (0x0UL) /*!< Allow SYSCOUNTER to go to sleep                                     */
37859   #define GRTC_KEEPRUNNING_DOMAIN15_Active (0x1UL)   /*!< Keep SYSCOUNTER active                                               */
37860 
37861 
37862 /* GRTC_TIMEOUT: Timeout after all CPUs gone into sleep state to stop the SYSCOUNTER */
37863   #define GRTC_TIMEOUT_ResetValue (0x00000000UL)     /*!< Reset value of TIMEOUT register.                                     */
37864 
37865 /* VALUE @Bits 0..15 : Number of 32Ki cycles */
37866   #define GRTC_TIMEOUT_VALUE_Pos (0UL)               /*!< Position of VALUE field.                                             */
37867   #define GRTC_TIMEOUT_VALUE_Msk (0xFFFFUL << GRTC_TIMEOUT_VALUE_Pos) /*!< Bit mask of VALUE field.                            */
37868 
37869 
37870 /* GRTC_INTERVAL: Count to add to CC[0] when the event EVENTS_COMPARE[0] triggers. */
37871   #define GRTC_INTERVAL_ResetValue (0x00000000UL)    /*!< Reset value of INTERVAL register.                                    */
37872 
37873 /* VALUE @Bits 0..15 : Count to add to CC[0] */
37874   #define GRTC_INTERVAL_VALUE_Pos (0UL)              /*!< Position of VALUE field.                                             */
37875   #define GRTC_INTERVAL_VALUE_Msk (0xFFFFUL << GRTC_INTERVAL_VALUE_Pos) /*!< Bit mask of VALUE field.                          */
37876 
37877 
37878 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
37879 
37880 /* =========================================================================================================================== */
37881 /* ================                                           HSFLL                                           ================ */
37882 /* =========================================================================================================================== */
37883 
37884 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
37885 
37886 /* =================================================== Struct HSFLL_FREQM ==================================================== */
37887 /**
37888   * @brief FREQM [HSFLL_FREQM] (unspecified)
37889   */
37890 typedef struct {
37891   __IM  uint32_t  DONE;                              /*!< (@ 0x00000000) Frequency measurement done status                     */
37892   __IM  uint32_t  ERROR;                             /*!< (@ 0x00000004) Frequency measurement error status                    */
37893   __IM  uint32_t  MEAS;                              /*!< (@ 0x00000008) Frequency measurement                                 */
37894 } NRF_HSFLL_FREQM_Type;                              /*!< Size = 12 (0x00C)                                                    */
37895 
37896 /* HSFLL_FREQM_DONE: Frequency measurement done status */
37897   #define HSFLL_FREQM_DONE_ResetValue (0x00000000UL) /*!< Reset value of DONE register.                                        */
37898 
37899 /* DONE @Bit 0 : Measurement done. */
37900   #define HSFLL_FREQM_DONE_DONE_Pos (0UL)            /*!< Position of DONE field.                                              */
37901   #define HSFLL_FREQM_DONE_DONE_Msk (0x1UL << HSFLL_FREQM_DONE_DONE_Pos) /*!< Bit mask of DONE field.                          */
37902   #define HSFLL_FREQM_DONE_DONE_Min (0x0UL)          /*!< Min enumerator value of DONE field.                                  */
37903   #define HSFLL_FREQM_DONE_DONE_Max (0x1UL)          /*!< Max enumerator value of DONE field.                                  */
37904   #define HSFLL_FREQM_DONE_DONE_InProgress (0x0UL)   /*!< Frequency measurement is in progress.                                */
37905   #define HSFLL_FREQM_DONE_DONE_Completed (0x1UL)    /*!< Frequency measurement is completed.                                  */
37906 
37907 
37908 /* HSFLL_FREQM_ERROR: Frequency measurement error status */
37909   #define HSFLL_FREQM_ERROR_ResetValue (0x00000000UL) /*!< Reset value of ERROR register.                                      */
37910 
37911 /* ERROR @Bit 0 : Trim error status. */
37912   #define HSFLL_FREQM_ERROR_ERROR_Pos (0UL)          /*!< Position of ERROR field.                                             */
37913   #define HSFLL_FREQM_ERROR_ERROR_Msk (0x1UL << HSFLL_FREQM_ERROR_ERROR_Pos) /*!< Bit mask of ERROR field.                     */
37914   #define HSFLL_FREQM_ERROR_ERROR_Min (0x0UL)        /*!< Min enumerator value of ERROR field.                                 */
37915   #define HSFLL_FREQM_ERROR_ERROR_Max (0x1UL)        /*!< Max enumerator value of ERROR field.                                 */
37916   #define HSFLL_FREQM_ERROR_ERROR_OutsideLimit (0x1UL) /*!< Frequency exceeded the accuracy 2 percent in closed loop mode.     */
37917   #define HSFLL_FREQM_ERROR_ERROR_WithinLimit (0x0UL) /*!< Frequency stayed within accuracy 2 percent in closed loop mode.     */
37918 
37919 /* TRIMUNDERFLOW @Bit 1 : Underflow error status. */
37920   #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Pos (1UL)  /*!< Position of TRIMUNDERFLOW field.                                     */
37921   #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Msk (0x1UL << HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Pos) /*!< Bit mask of TRIMUNDERFLOW
37922                                                                             field.*/
37923   #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Min (0x0UL) /*!< Min enumerator value of TRIMUNDERFLOW field.                        */
37924   #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_Max (0x1UL) /*!< Max enumerator value of TRIMUNDERFLOW field.                        */
37925   #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_OutsideLimit (0x1UL) /*!< Underflow                                                  */
37926   #define HSFLL_FREQM_ERROR_TRIMUNDERFLOW_WithinLimit (0x0UL) /*!< No underflow                                                */
37927 
37928 /* TRIMOVERFLOW @Bit 2 : Overflow error status. */
37929   #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_Pos (2UL)   /*!< Position of TRIMOVERFLOW field.                                      */
37930   #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_Msk (0x1UL << HSFLL_FREQM_ERROR_TRIMOVERFLOW_Pos) /*!< Bit mask of TRIMOVERFLOW field.*/
37931   #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_Min (0x0UL) /*!< Min enumerator value of TRIMOVERFLOW field.                          */
37932   #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_Max (0x1UL) /*!< Max enumerator value of TRIMOVERFLOW field.                          */
37933   #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_OutsideLimit (0x1UL) /*!< Overflow                                                    */
37934   #define HSFLL_FREQM_ERROR_TRIMOVERFLOW_WithinLimit (0x0UL) /*!< No overflow                                                  */
37935 
37936 
37937 /* HSFLL_FREQM_MEAS: Frequency measurement */
37938   #define HSFLL_FREQM_MEAS_ResetValue (0x00000000UL) /*!< Reset value of MEAS register.                                        */
37939 
37940 /* VALUE @Bits 0..7 : Last frequency measurement value. */
37941   #define HSFLL_FREQM_MEAS_VALUE_Pos (0UL)           /*!< Position of VALUE field.                                             */
37942   #define HSFLL_FREQM_MEAS_VALUE_Msk (0xFFUL << HSFLL_FREQM_MEAS_VALUE_Pos) /*!< Bit mask of VALUE field.                      */
37943 
37944 
37945 
37946 /* ==================================================== Struct HSFLL_TRIM ==================================================== */
37947 /**
37948   * @brief TRIM [HSFLL_TRIM] (unspecified)
37949   */
37950 typedef struct {
37951   __IOM uint32_t  VSUP;                              /*!< (@ 0x00000000) Internal regulator voltage supply level trimming      */
37952   __IOM uint32_t  COARSE;                            /*!< (@ 0x00000004) Coarse frequency trimming                             */
37953   __IOM uint32_t  FINE;                              /*!< (@ 0x00000008) Fine frequency trimming                               */
37954   __IM  uint32_t  RESERVED[2];
37955 } NRF_HSFLL_TRIM_Type;                               /*!< Size = 20 (0x014)                                                    */
37956 
37957 /* HSFLL_TRIM_VSUP: Internal regulator voltage supply level trimming */
37958   #define HSFLL_TRIM_VSUP_ResetValue (0x00000010UL)  /*!< Reset value of VSUP register.                                        */
37959 
37960 /* VALUE @Bits 0..4 : Trim value */
37961   #define HSFLL_TRIM_VSUP_VALUE_Pos (0UL)            /*!< Position of VALUE field.                                             */
37962   #define HSFLL_TRIM_VSUP_VALUE_Msk (0x1FUL << HSFLL_TRIM_VSUP_VALUE_Pos) /*!< Bit mask of VALUE field.                        */
37963 
37964 
37965 /* HSFLL_TRIM_COARSE: Coarse frequency trimming */
37966   #define HSFLL_TRIM_COARSE_ResetValue (0x00000004UL) /*!< Reset value of COARSE register.                                     */
37967 
37968 /* VALUE @Bits 0..9 : Coarse frequency trimming value. */
37969   #define HSFLL_TRIM_COARSE_VALUE_Pos (0UL)          /*!< Position of VALUE field.                                             */
37970   #define HSFLL_TRIM_COARSE_VALUE_Msk (0x3FFUL << HSFLL_TRIM_COARSE_VALUE_Pos) /*!< Bit mask of VALUE field.                   */
37971 
37972 
37973 /* HSFLL_TRIM_FINE: Fine frequency trimming */
37974   #define HSFLL_TRIM_FINE_ResetValue (0x0000001EUL)  /*!< Reset value of FINE register.                                        */
37975 
37976 /* VALUE @Bits 0..10 : Fine frequency trimming value */
37977   #define HSFLL_TRIM_FINE_VALUE_Pos (0UL)            /*!< Position of VALUE field.                                             */
37978   #define HSFLL_TRIM_FINE_VALUE_Msk (0x7FFUL << HSFLL_TRIM_FINE_VALUE_Pos) /*!< Bit mask of VALUE field.                       */
37979 
37980 
37981 
37982 /* ================================================= Struct HSFLL_CLOCKCTRL ================================================== */
37983 /**
37984   * @brief CLOCKCTRL [HSFLL_CLOCKCTRL] (unspecified)
37985   */
37986 typedef struct {
37987   __IOM uint32_t  MODE;                              /*!< (@ 0x00000000) Clock control                                         */
37988   __IOM uint32_t  DITHERING;                         /*!< (@ 0x00000004) Clock dithering configuration                         */
37989   __IOM uint32_t  MULT;                              /*!< (@ 0x00000008) Multiplication factor                                 */
37990   __IOM uint32_t  SLEEP;                             /*!< (@ 0x0000000C) Sleep configuration                                   */
37991   __IOM uint32_t  RETAINFINETRIM;                    /*!< (@ 0x00000010) Fine trim retain control                              */
37992   __IOM uint32_t  OVERRIDELOCKED;                    /*!< (@ 0x00000014) Override the LOCKED signal                            */
37993 } NRF_HSFLL_CLOCKCTRL_Type;                          /*!< Size = 24 (0x018)                                                    */
37994 
37995 /* HSFLL_CLOCKCTRL_MODE: Clock control */
37996   #define HSFLL_CLOCKCTRL_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register.                                    */
37997 
37998 /* MODE @Bits 0..1 : The HSFLL operating mode. */
37999   #define HSFLL_CLOCKCTRL_MODE_MODE_Pos (0UL)        /*!< Position of MODE field.                                              */
38000   #define HSFLL_CLOCKCTRL_MODE_MODE_Msk (0x3UL << HSFLL_CLOCKCTRL_MODE_MODE_Pos) /*!< Bit mask of MODE field.                  */
38001   #define HSFLL_CLOCKCTRL_MODE_MODE_Min (0x0UL)      /*!< Min enumerator value of MODE field.                                  */
38002   #define HSFLL_CLOCKCTRL_MODE_MODE_Max (0x3UL)      /*!< Max enumerator value of MODE field.                                  */
38003   #define HSFLL_CLOCKCTRL_MODE_MODE_Auto (0x0UL)     /*!< The PCGC controls the mode automatically.                            */
38004   #define HSFLL_CLOCKCTRL_MODE_MODE_OpenLoop (0x1UL) /*!< Open loop mode.                                                      */
38005   #define HSFLL_CLOCKCTRL_MODE_MODE_ClosedLoop (0x2UL) /*!< Closed loop mode.                                                  */
38006   #define HSFLL_CLOCKCTRL_MODE_MODE_Bypass (0x3UL)   /*!< Bypass mode.                                                         */
38007 
38008 /* OVERRIDE @Bit 4 : HSFLL override mode. */
38009   #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Pos (4UL)    /*!< Position of OVERRIDE field.                                          */
38010   #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Msk (0x1UL << HSFLL_CLOCKCTRL_MODE_OVERRIDE_Pos) /*!< Bit mask of OVERRIDE field.      */
38011   #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Min (0x0UL)  /*!< Min enumerator value of OVERRIDE field.                              */
38012   #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Max (0x1UL)  /*!< Max enumerator value of OVERRIDE field.                              */
38013   #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Disabled (0x0UL) /*!< Override mode disabled.                                          */
38014   #define HSFLL_CLOCKCTRL_MODE_OVERRIDE_Enabled (0x1UL) /*!< Override mode enabled.                                            */
38015 
38016 
38017 /* HSFLL_CLOCKCTRL_DITHERING: Clock dithering configuration */
38018   #define HSFLL_CLOCKCTRL_DITHERING_ResetValue (0x00096733UL) /*!< Reset value of DITHERING register.                          */
38019 
38020 /* CYCLECOUNT @Bits 0..2 : Cycle count configuration for clock dithering */
38021   #define HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Pos (0UL) /*!< Position of CYCLECOUNT field.                                    */
38022   #define HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Msk (0x7UL << HSFLL_CLOCKCTRL_DITHERING_CYCLECOUNT_Pos) /*!< Bit mask of
38023                                                                             CYCLECOUNT field.*/
38024 
38025 /* MAXOFFSET @Bits 4..6 : Maximum offset configuration for clock dithering */
38026   #define HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos (4UL) /*!< Position of MAXOFFSET field.                                      */
38027   #define HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Msk (0x7UL << HSFLL_CLOCKCTRL_DITHERING_MAXOFFSET_Pos) /*!< Bit mask of MAXOFFSET
38028                                                                             field.*/
38029 
38030 /* INITVALUE @Bits 8..19 : Initial value for the dithering */
38031   #define HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Pos (8UL) /*!< Position of INITVALUE field.                                      */
38032   #define HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Msk (0xFFFUL << HSFLL_CLOCKCTRL_DITHERING_INITVALUE_Pos) /*!< Bit mask of
38033                                                                             INITVALUE field.*/
38034 
38035 /* EN @Bit 31 : Enable the clock dithering */
38036   #define HSFLL_CLOCKCTRL_DITHERING_EN_Pos (31UL)    /*!< Position of EN field.                                                */
38037   #define HSFLL_CLOCKCTRL_DITHERING_EN_Msk (0x1UL << HSFLL_CLOCKCTRL_DITHERING_EN_Pos) /*!< Bit mask of EN field.              */
38038   #define HSFLL_CLOCKCTRL_DITHERING_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
38039   #define HSFLL_CLOCKCTRL_DITHERING_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
38040   #define HSFLL_CLOCKCTRL_DITHERING_EN_Disabled (0x0UL) /*!< Clock dithering is disabled                                       */
38041   #define HSFLL_CLOCKCTRL_DITHERING_EN_Enabled (0x1UL) /*!< Clock dithering is enabled                                         */
38042 
38043 
38044 /* HSFLL_CLOCKCTRL_MULT: Multiplication factor */
38045   #define HSFLL_CLOCKCTRL_MULT_ResetValue (0x00000006UL) /*!< Reset value of MULT register.                                    */
38046 
38047 /* VAL @Bits 0..4 : Multiplication factor value. Valid range: 4 to 25. Output frequency is a multiplication of 16 MHz reference
38048                     and the multiplication factor. */
38049 
38050   #define HSFLL_CLOCKCTRL_MULT_VAL_Pos (0UL)         /*!< Position of VAL field.                                               */
38051   #define HSFLL_CLOCKCTRL_MULT_VAL_Msk (0x1FUL << HSFLL_CLOCKCTRL_MULT_VAL_Pos) /*!< Bit mask of VAL field.                    */
38052 
38053 
38054 /* HSFLL_CLOCKCTRL_SLEEP: Sleep configuration */
38055   #define HSFLL_CLOCKCTRL_SLEEP_ResetValue (0x00000001UL) /*!< Reset value of SLEEP register.                                  */
38056 
38057 /* MODE @Bit 0 : HSFLL sleep mode. */
38058   #define HSFLL_CLOCKCTRL_SLEEP_MODE_Pos (0UL)       /*!< Position of MODE field.                                              */
38059   #define HSFLL_CLOCKCTRL_SLEEP_MODE_Msk (0x1UL << HSFLL_CLOCKCTRL_SLEEP_MODE_Pos) /*!< Bit mask of MODE field.                */
38060   #define HSFLL_CLOCKCTRL_SLEEP_MODE_Min (0x0UL)     /*!< Min enumerator value of MODE field.                                  */
38061   #define HSFLL_CLOCKCTRL_SLEEP_MODE_Max (0x1UL)     /*!< Max enumerator value of MODE field.                                  */
38062   #define HSFLL_CLOCKCTRL_SLEEP_MODE_Normal (0x0UL)  /*!< Normal mode operation                                                */
38063   #define HSFLL_CLOCKCTRL_SLEEP_MODE_Sleep (0x1UL)   /*!< Power down the HSFLL core                                            */
38064 
38065 /* RETAIN @Bit 1 : Retain. */
38066   #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Pos (1UL)     /*!< Position of RETAIN field.                                            */
38067   #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Msk (0x1UL << HSFLL_CLOCKCTRL_SLEEP_RETAIN_Pos) /*!< Bit mask of RETAIN field.          */
38068   #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Min (0x0UL)   /*!< Min enumerator value of RETAIN field.                                */
38069   #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Max (0x1UL)   /*!< Max enumerator value of RETAIN field.                                */
38070   #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Disabled (0x0UL) /*!< No retention while powered down                                   */
38071   #define HSFLL_CLOCKCTRL_SLEEP_RETAIN_Enabled (0x1UL) /*!< Retain all inputs while powered down                               */
38072 
38073 
38074 /* HSFLL_CLOCKCTRL_RETAINFINETRIM: Fine trim retain control */
38075   #define HSFLL_CLOCKCTRL_RETAINFINETRIM_ResetValue (0x00000000UL) /*!< Reset value of RETAINFINETRIM register.                */
38076 
38077 /* RETAIN @Bit 0 : Retain control */
38078   #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Pos (0UL) /*!< Position of RETAIN field.                                       */
38079   #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Msk (0x1UL << HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Pos) /*!< Bit mask of RETAIN
38080                                                                             field.*/
38081   #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Min (0x0UL) /*!< Min enumerator value of RETAIN field.                         */
38082   #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Max (0x1UL) /*!< Max enumerator value of RETAIN field.                         */
38083   #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_NoRetain (0x0UL) /*!< No retain.                                               */
38084   #define HSFLL_CLOCKCTRL_RETAINFINETRIM_RETAIN_Retain (0x1UL) /*!< Retain control when HSFLL goes to open-loop mode.          */
38085 
38086 
38087 /* HSFLL_CLOCKCTRL_OVERRIDELOCKED: Override the LOCKED signal */
38088   #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_ResetValue (0x00000000UL) /*!< Reset value of OVERRIDELOCKED register.                */
38089 
38090 /* OVERRIDE @Bit 0 : Override */
38091   #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Pos (0UL) /*!< Position of OVERRIDE field.                                   */
38092   #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Msk (0x1UL << HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Pos) /*!< Bit mask of
38093                                                                             OVERRIDE field.*/
38094   #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Min (0x0UL) /*!< Min enumerator value of OVERRIDE field.                     */
38095   #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Max (0x1UL) /*!< Max enumerator value of OVERRIDE field.                     */
38096   #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_NoOperation (0x0UL) /*!< No Operation.                                       */
38097   #define HSFLL_CLOCKCTRL_OVERRIDELOCKED_OVERRIDE_Override (0x1UL) /*!< Override                                               */
38098 
38099 
38100 /* ====================================================== Struct HSFLL ======================================================= */
38101 /**
38102   * @brief HSFLL
38103   */
38104   typedef struct {                                   /*!< HSFLL Structure                                                      */
38105     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start the HSFLL                                       */
38106     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop the HSFLL                                        */
38107     __IM uint32_t RESERVED[2];
38108     __OM uint32_t TASKS_FREQMEAS;                    /*!< (@ 0x00000010) Start frequency measurement in software-controlled
38109                                                                          mode*/
38110     __OM uint32_t TASKS_FREQCHANGE;                  /*!< (@ 0x00000014) Trigger frequency change                              */
38111     __IM uint32_t RESERVED1[58];
38112     __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000100) HSFLL started                                         */
38113     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) HSFLL stopped                                         */
38114     __IM uint32_t RESERVED2;
38115     __IOM uint32_t EVENTS_FREQMDONE;                 /*!< (@ 0x0000010C) Frequency measurement done                            */
38116     __IOM uint32_t EVENTS_FREQCHANGED;               /*!< (@ 0x00000110) Frequency change done                                 */
38117     __IM uint32_t RESERVED3[187];
38118     __IM uint32_t CLOCKSTATUS;                       /*!< (@ 0x00000400) Clock status                                          */
38119     __IM uint32_t RESERVED4[7];
38120     __IOM NRF_HSFLL_FREQM_Type FREQM;                /*!< (@ 0x00000420) (unspecified)                                         */
38121     __IM uint32_t RESERVED5[5];
38122     __IOM NRF_HSFLL_TRIM_Type TRIM;                  /*!< (@ 0x00000440) (unspecified)                                         */
38123     __IM uint32_t RESERVED6[3];
38124     __IOM NRF_HSFLL_CLOCKCTRL_Type CLOCKCTRL;        /*!< (@ 0x00000460) (unspecified)                                         */
38125     __IM uint32_t RESERVED7[2];
38126     __IOM uint32_t MIRROR;                           /*!< (@ 0x00000480) Enable LOCK for mirrored registers                    */
38127   } NRF_HSFLL_Type;                                  /*!< Size = 1156 (0x484)                                                  */
38128 
38129 /* HSFLL_TASKS_START: Start the HSFLL */
38130   #define HSFLL_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */
38131 
38132 /* TASKS_START @Bit 0 : Start the HSFLL */
38133   #define HSFLL_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
38134   #define HSFLL_TASKS_START_TASKS_START_Msk (0x1UL << HSFLL_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
38135   #define HSFLL_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
38136   #define HSFLL_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
38137   #define HSFLL_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */
38138 
38139 
38140 /* HSFLL_TASKS_STOP: Stop the HSFLL */
38141   #define HSFLL_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */
38142 
38143 /* TASKS_STOP @Bit 0 : Stop the HSFLL */
38144   #define HSFLL_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
38145   #define HSFLL_TASKS_STOP_TASKS_STOP_Msk (0x1UL << HSFLL_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
38146   #define HSFLL_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
38147   #define HSFLL_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
38148   #define HSFLL_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */
38149 
38150 
38151 /* HSFLL_TASKS_FREQMEAS: Start frequency measurement in software-controlled mode */
38152   #define HSFLL_TASKS_FREQMEAS_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FREQMEAS register.                          */
38153 
38154 /* TASKS_FREQMEAS @Bit 0 : Start frequency measurement in software-controlled mode */
38155   #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Pos (0UL) /*!< Position of TASKS_FREQMEAS field.                                 */
38156   #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Msk (0x1UL << HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Pos) /*!< Bit mask of
38157                                                                             TASKS_FREQMEAS field.*/
38158   #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Min (0x1UL) /*!< Min enumerator value of TASKS_FREQMEAS field.                   */
38159   #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Max (0x1UL) /*!< Max enumerator value of TASKS_FREQMEAS field.                   */
38160   #define HSFLL_TASKS_FREQMEAS_TASKS_FREQMEAS_Trigger (0x1UL) /*!< Trigger task                                                */
38161 
38162 
38163 /* HSFLL_TASKS_FREQCHANGE: Trigger frequency change */
38164   #define HSFLL_TASKS_FREQCHANGE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FREQCHANGE register.                      */
38165 
38166 /* TASKS_FREQCHANGE @Bit 0 : Trigger frequency change */
38167   #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Pos (0UL) /*!< Position of TASKS_FREQCHANGE field.                           */
38168   #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Msk (0x1UL << HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Pos) /*!< Bit mask of
38169                                                                             TASKS_FREQCHANGE field.*/
38170   #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Min (0x1UL) /*!< Min enumerator value of TASKS_FREQCHANGE field.             */
38171   #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Max (0x1UL) /*!< Max enumerator value of TASKS_FREQCHANGE field.             */
38172   #define HSFLL_TASKS_FREQCHANGE_TASKS_FREQCHANGE_Trigger (0x1UL) /*!< Trigger task                                            */
38173 
38174 
38175 /* HSFLL_EVENTS_STARTED: HSFLL started */
38176   #define HSFLL_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                          */
38177 
38178 /* EVENTS_STARTED @Bit 0 : HSFLL started */
38179   #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                 */
38180   #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << HSFLL_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of
38181                                                                             EVENTS_STARTED field.*/
38182   #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                   */
38183   #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                   */
38184   #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                    */
38185   #define HSFLL_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                           */
38186 
38187 
38188 /* HSFLL_EVENTS_STOPPED: HSFLL stopped */
38189   #define HSFLL_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                          */
38190 
38191 /* EVENTS_STOPPED @Bit 0 : HSFLL stopped */
38192   #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                 */
38193   #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
38194                                                                             EVENTS_STOPPED field.*/
38195   #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                   */
38196   #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                   */
38197   #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                    */
38198   #define HSFLL_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                           */
38199 
38200 
38201 /* HSFLL_EVENTS_FREQMDONE: Frequency measurement done */
38202   #define HSFLL_EVENTS_FREQMDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FREQMDONE register.                      */
38203 
38204 /* EVENTS_FREQMDONE @Bit 0 : Frequency measurement done */
38205   #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Pos (0UL) /*!< Position of EVENTS_FREQMDONE field.                           */
38206   #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Msk (0x1UL << HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Pos) /*!< Bit mask of
38207                                                                             EVENTS_FREQMDONE field.*/
38208   #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_FREQMDONE field.             */
38209   #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_FREQMDONE field.             */
38210   #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_NotGenerated (0x0UL) /*!< Event not generated                                */
38211   #define HSFLL_EVENTS_FREQMDONE_EVENTS_FREQMDONE_Generated (0x1UL) /*!< Event generated                                       */
38212 
38213 
38214 /* HSFLL_EVENTS_FREQCHANGED: Frequency change done */
38215   #define HSFLL_EVENTS_FREQCHANGED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FREQCHANGED register.                  */
38216 
38217 /* EVENTS_FREQCHANGED @Bit 0 : Frequency change done */
38218   #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Pos (0UL) /*!< Position of EVENTS_FREQCHANGED field.                     */
38219   #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Msk (0x1UL << HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Pos) /*!< Bit
38220                                                                             mask of EVENTS_FREQCHANGED field.*/
38221   #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Min (0x0UL) /*!< Min enumerator value of EVENTS_FREQCHANGED field.       */
38222   #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Max (0x1UL) /*!< Max enumerator value of EVENTS_FREQCHANGED field.       */
38223   #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_NotGenerated (0x0UL) /*!< Event not generated                            */
38224   #define HSFLL_EVENTS_FREQCHANGED_EVENTS_FREQCHANGED_Generated (0x1UL) /*!< Event generated                                   */
38225 
38226 
38227 /* HSFLL_CLOCKSTATUS: Clock status */
38228   #define HSFLL_CLOCKSTATUS_ResetValue (0x00000000UL) /*!< Reset value of CLOCKSTATUS register.                                */
38229 
38230 /* MODE @Bits 0..1 : The HSFLL operating mode. */
38231   #define HSFLL_CLOCKSTATUS_MODE_Pos (0UL)           /*!< Position of MODE field.                                              */
38232   #define HSFLL_CLOCKSTATUS_MODE_Msk (0x3UL << HSFLL_CLOCKSTATUS_MODE_Pos) /*!< Bit mask of MODE field.                        */
38233   #define HSFLL_CLOCKSTATUS_MODE_Min (0x0UL)         /*!< Min enumerator value of MODE field.                                  */
38234   #define HSFLL_CLOCKSTATUS_MODE_Max (0x2UL)         /*!< Max enumerator value of MODE field.                                  */
38235   #define HSFLL_CLOCKSTATUS_MODE_OpenLoop (0x0UL)    /*!< Open loop mode.                                                      */
38236   #define HSFLL_CLOCKSTATUS_MODE_ClosedLoop (0x1UL)  /*!< Closed loop mode.                                                    */
38237   #define HSFLL_CLOCKSTATUS_MODE_Bypass (0x2UL)      /*!< Bypass mode.                                                         */
38238 
38239 /* OVERRIDE @Bit 4 : HSFLL Override mode. */
38240   #define HSFLL_CLOCKSTATUS_OVERRIDE_Pos (4UL)       /*!< Position of OVERRIDE field.                                          */
38241   #define HSFLL_CLOCKSTATUS_OVERRIDE_Msk (0x1UL << HSFLL_CLOCKSTATUS_OVERRIDE_Pos) /*!< Bit mask of OVERRIDE field.            */
38242   #define HSFLL_CLOCKSTATUS_OVERRIDE_Min (0x0UL)     /*!< Min enumerator value of OVERRIDE field.                              */
38243   #define HSFLL_CLOCKSTATUS_OVERRIDE_Max (0x1UL)     /*!< Max enumerator value of OVERRIDE field.                              */
38244   #define HSFLL_CLOCKSTATUS_OVERRIDE_Disabled (0x0UL) /*!< Override mode disabled.                                             */
38245   #define HSFLL_CLOCKSTATUS_OVERRIDE_Enabled (0x1UL) /*!< Override mode enabled.                                               */
38246 
38247 /* ACCURACY @Bit 9 : Clock accuracy. */
38248   #define HSFLL_CLOCKSTATUS_ACCURACY_Pos (9UL)       /*!< Position of ACCURACY field.                                          */
38249   #define HSFLL_CLOCKSTATUS_ACCURACY_Msk (0x1UL << HSFLL_CLOCKSTATUS_ACCURACY_Pos) /*!< Bit mask of ACCURACY field.            */
38250   #define HSFLL_CLOCKSTATUS_ACCURACY_Min (0x0UL)     /*!< Min enumerator value of ACCURACY field.                              */
38251   #define HSFLL_CLOCKSTATUS_ACCURACY_Max (0x1UL)     /*!< Max enumerator value of ACCURACY field.                              */
38252   #define HSFLL_CLOCKSTATUS_ACCURACY_OutsideLimit (0x0UL) /*!< Clock accuracy is outside 2 percent.                            */
38253   #define HSFLL_CLOCKSTATUS_ACCURACY_WithinLimit (0x1UL) /*!< Clock accuracy is within 2 percent.                              */
38254 
38255 /* LOCKED @Bit 10 : The HSFLL lock status. */
38256   #define HSFLL_CLOCKSTATUS_LOCKED_Pos (10UL)        /*!< Position of LOCKED field.                                            */
38257   #define HSFLL_CLOCKSTATUS_LOCKED_Msk (0x1UL << HSFLL_CLOCKSTATUS_LOCKED_Pos) /*!< Bit mask of LOCKED field.                  */
38258   #define HSFLL_CLOCKSTATUS_LOCKED_Min (0x0UL)       /*!< Min enumerator value of LOCKED field.                                */
38259   #define HSFLL_CLOCKSTATUS_LOCKED_Max (0x1UL)       /*!< Max enumerator value of LOCKED field.                                */
38260   #define HSFLL_CLOCKSTATUS_LOCKED_NotLocked (0x0UL) /*!< Not locked to reference clock                                        */
38261   #define HSFLL_CLOCKSTATUS_LOCKED_Locked (0x1UL)    /*!< Locked to reference clock.                                           */
38262 
38263 
38264 /* HSFLL_MIRROR: Enable LOCK for mirrored registers */
38265   #define HSFLL_MIRROR_ResetValue (0x00000001UL)     /*!< Reset value of MIRROR register.                                      */
38266 
38267 /* LOCK @Bit 0 : Lock for mirrored registers */
38268   #define HSFLL_MIRROR_LOCK_Pos (0UL)                /*!< Position of LOCK field.                                              */
38269   #define HSFLL_MIRROR_LOCK_Msk (0x1UL << HSFLL_MIRROR_LOCK_Pos) /*!< Bit mask of LOCK field.                                  */
38270   #define HSFLL_MIRROR_LOCK_Min (0x0UL)              /*!< Min enumerator value of LOCK field.                                  */
38271   #define HSFLL_MIRROR_LOCK_Max (0x1UL)              /*!< Max enumerator value of LOCK field.                                  */
38272   #define HSFLL_MIRROR_LOCK_Disabled (0x0UL)         /*!< Lock disabled                                                        */
38273   #define HSFLL_MIRROR_LOCK_Enabled (0x1UL)          /*!< Lock enabled                                                         */
38274 
38275 
38276 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
38277 
38278 /* =========================================================================================================================== */
38279 /* ================                                            I2S                                            ================ */
38280 /* =========================================================================================================================== */
38281 
38282 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
38283 
38284 /* ==================================================== Struct I2S_CONFIG ==================================================== */
38285 /**
38286   * @brief CONFIG [I2S_CONFIG] (unspecified)
38287   */
38288 typedef struct {
38289   __IOM uint32_t  MODE;                              /*!< (@ 0x00000000) I2S mode                                              */
38290   __IOM uint32_t  RXEN;                              /*!< (@ 0x00000004) Reception (RX) enable                                 */
38291   __IOM uint32_t  TXEN;                              /*!< (@ 0x00000008) Transmission (TX) enable                              */
38292   __IOM uint32_t  MCKEN;                             /*!< (@ 0x0000000C) Master clock generator enable                         */
38293   __IOM uint32_t  MCKFREQ;                           /*!< (@ 0x00000010) I2S clock generator control                           */
38294   __IOM uint32_t  RATIO;                             /*!< (@ 0x00000014) MCK / LRCK ratio                                      */
38295   __IOM uint32_t  SWIDTH;                            /*!< (@ 0x00000018) Sample width                                          */
38296   __IOM uint32_t  ALIGN;                             /*!< (@ 0x0000001C) Alignment of sample within a frame                    */
38297   __IOM uint32_t  FORMAT;                            /*!< (@ 0x00000020) Frame format                                          */
38298   __IOM uint32_t  CHANNELS;                          /*!< (@ 0x00000024) Enable channels                                       */
38299   __IOM uint32_t  CLKCONFIG;                         /*!< (@ 0x00000028) Clock source selection for the I2S module             */
38300 } NRF_I2S_CONFIG_Type;                               /*!< Size = 44 (0x02C)                                                    */
38301 
38302 /* I2S_CONFIG_MODE: I2S mode */
38303   #define I2S_CONFIG_MODE_ResetValue (0x00000000UL)  /*!< Reset value of MODE register.                                        */
38304 
38305 /* MODE @Bit 0 : I2S mode */
38306   #define I2S_CONFIG_MODE_MODE_Pos (0UL)             /*!< Position of MODE field.                                              */
38307   #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field.                            */
38308   #define I2S_CONFIG_MODE_MODE_Min (0x0UL)           /*!< Min enumerator value of MODE field.                                  */
38309   #define I2S_CONFIG_MODE_MODE_Max (0x1UL)           /*!< Max enumerator value of MODE field.                                  */
38310   #define I2S_CONFIG_MODE_MODE_Master (0x0UL)        /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK)
38311                                                           and output on pins defined by PSEL.xxx.*/
38312   #define I2S_CONFIG_MODE_MODE_Slave (0x1UL)         /*!< Slave mode. SCK and LRCK generated by external master and received on
38313                                                           pins defined by PSEL.xxx*/
38314 
38315 
38316 /* I2S_CONFIG_RXEN: Reception (RX) enable */
38317   #define I2S_CONFIG_RXEN_ResetValue (0x00000000UL)  /*!< Reset value of RXEN register.                                        */
38318 
38319 /* RXEN @Bit 0 : Reception (RX) enable */
38320   #define I2S_CONFIG_RXEN_RXEN_Pos (0UL)             /*!< Position of RXEN field.                                              */
38321   #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field.                            */
38322   #define I2S_CONFIG_RXEN_RXEN_Min (0x0UL)           /*!< Min enumerator value of RXEN field.                                  */
38323   #define I2S_CONFIG_RXEN_RXEN_Max (0x1UL)           /*!< Max enumerator value of RXEN field.                                  */
38324   #define I2S_CONFIG_RXEN_RXEN_Disabled (0x0UL)      /*!< Reception disabled and now data will be written to the RXD.PTR
38325                                                           address.*/
38326   #define I2S_CONFIG_RXEN_RXEN_Enabled (0x1UL)       /*!< Reception enabled.                                                   */
38327 
38328 
38329 /* I2S_CONFIG_TXEN: Transmission (TX) enable */
38330   #define I2S_CONFIG_TXEN_ResetValue (0x00000001UL)  /*!< Reset value of TXEN register.                                        */
38331 
38332 /* TXEN @Bit 0 : Transmission (TX) enable */
38333   #define I2S_CONFIG_TXEN_TXEN_Pos (0UL)             /*!< Position of TXEN field.                                              */
38334   #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field.                            */
38335   #define I2S_CONFIG_TXEN_TXEN_Min (0x0UL)           /*!< Min enumerator value of TXEN field.                                  */
38336   #define I2S_CONFIG_TXEN_TXEN_Max (0x1UL)           /*!< Max enumerator value of TXEN field.                                  */
38337   #define I2S_CONFIG_TXEN_TXEN_Disabled (0x0UL)      /*!< Transmission disabled and now data will be read from the RXD.TXD
38338                                                           address.*/
38339   #define I2S_CONFIG_TXEN_TXEN_Enabled (0x1UL)       /*!< Transmission enabled.                                                */
38340 
38341 
38342 /* I2S_CONFIG_MCKEN: Master clock generator enable */
38343   #define I2S_CONFIG_MCKEN_ResetValue (0x00000001UL) /*!< Reset value of MCKEN register.                                       */
38344 
38345 /* MCKEN @Bit 0 : Master clock generator enable */
38346   #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL)           /*!< Position of MCKEN field.                                             */
38347   #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field.                       */
38348   #define I2S_CONFIG_MCKEN_MCKEN_Min (0x0UL)         /*!< Min enumerator value of MCKEN field.                                 */
38349   #define I2S_CONFIG_MCKEN_MCKEN_Max (0x1UL)         /*!< Max enumerator value of MCKEN field.                                 */
38350   #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0x0UL)    /*!< Master clock generator disabled and PSEL.MCK not connected(available
38351                                                           as GPIO).*/
38352   #define I2S_CONFIG_MCKEN_MCKEN_Enabled (0x1UL)     /*!< Master clock generator running and MCK output on PSEL.MCK.           */
38353 
38354 
38355 /* I2S_CONFIG_MCKFREQ: I2S clock generator control */
38356   #define I2S_CONFIG_MCKFREQ_ResetValue (0x20000000UL) /*!< Reset value of MCKFREQ register.                                   */
38357 
38358 /* MCKFREQ @Bits 0..31 : I2S MCK frequency configuration NOTE: Enumerations are deprecated, use MCKFREQ equation. NOTE: The 12
38359                          least significant bits of the register are ignored and shall be set to zero. */
38360 
38361   #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL)       /*!< Position of MCKFREQ field.                                           */
38362   #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field.      */
38363   #define I2S_CONFIG_MCKFREQ_MCKFREQ_Min (0x20C0000UL) /*!< Min enumerator value of MCKFREQ field.                             */
38364   #define I2S_CONFIG_MCKFREQ_MCKFREQ_Max (0x80000000UL) /*!< Max enumerator value of MCKFREQ field.                            */
38365   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz Deprecated, use MCKFREQ equation.       */
38366   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz Deprecated, use MCKFREQ equation. */
38367   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz Deprecated, use MCKFREQ equation.        */
38368   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz Deprecated, use MCKFREQ equation.        */
38369   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz Deprecated, use MCKFREQ equation.  */
38370   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz Deprecated, use MCKFREQ equation.        */
38371   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz Deprecated, use MCKFREQ equation.      */
38372   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation.*/
38373   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation.*/
38374   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation.      */
38375   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation.*/
38376   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation.*/
38377   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation.*/
38378   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation.*/
38379   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz Deprecated, use MCKFREQ equation.      */
38380   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz Deprecated, use MCKFREQ equation.*/
38381   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz Deprecated, use MCKFREQ equation.*/
38382   #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz Deprecated, use MCKFREQ equation.  */
38383 
38384 
38385 /* I2S_CONFIG_RATIO: MCK / LRCK ratio */
38386   #define I2S_CONFIG_RATIO_ResetValue (0x00000006UL) /*!< Reset value of RATIO register.                                       */
38387 
38388 /* RATIO @Bits 0..3 : MCK / LRCK ratio */
38389   #define I2S_CONFIG_RATIO_RATIO_Pos (0UL)           /*!< Position of RATIO field.                                             */
38390   #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field.                       */
38391   #define I2S_CONFIG_RATIO_RATIO_Min (0x0UL)         /*!< Min enumerator value of RATIO field.                                 */
38392   #define I2S_CONFIG_RATIO_RATIO_Max (0x8UL)         /*!< Max enumerator value of RATIO field.                                 */
38393   #define I2S_CONFIG_RATIO_RATIO_32X (0x0UL)         /*!< LRCK = MCK / 32                                                      */
38394   #define I2S_CONFIG_RATIO_RATIO_48X (0x1UL)         /*!< LRCK = MCK / 48                                                      */
38395   #define I2S_CONFIG_RATIO_RATIO_64X (0x2UL)         /*!< LRCK = MCK / 64                                                      */
38396   #define I2S_CONFIG_RATIO_RATIO_96X (0x3UL)         /*!< LRCK = MCK / 96                                                      */
38397   #define I2S_CONFIG_RATIO_RATIO_128X (0x4UL)        /*!< LRCK = MCK / 128                                                     */
38398   #define I2S_CONFIG_RATIO_RATIO_192X (0x5UL)        /*!< LRCK = MCK / 192                                                     */
38399   #define I2S_CONFIG_RATIO_RATIO_256X (0x6UL)        /*!< LRCK = MCK / 256                                                     */
38400   #define I2S_CONFIG_RATIO_RATIO_384X (0x7UL)        /*!< LRCK = MCK / 384                                                     */
38401   #define I2S_CONFIG_RATIO_RATIO_512X (0x8UL)        /*!< LRCK = MCK / 512                                                     */
38402 
38403 
38404 /* I2S_CONFIG_SWIDTH: Sample width */
38405   #define I2S_CONFIG_SWIDTH_ResetValue (0x00000001UL) /*!< Reset value of SWIDTH register.                                     */
38406 
38407 /* SWIDTH @Bits 0..2 : Sample and half-frame width */
38408   #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL)         /*!< Position of SWIDTH field.                                            */
38409   #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x7UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field.                  */
38410   #define I2S_CONFIG_SWIDTH_SWIDTH_Min (0x0UL)       /*!< Min enumerator value of SWIDTH field.                                */
38411   #define I2S_CONFIG_SWIDTH_SWIDTH_Max (0x7UL)       /*!< Max enumerator value of SWIDTH field.                                */
38412   #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL)      /*!< 8 bit sample.                                                        */
38413   #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL)     /*!< 16 bit sample.                                                       */
38414   #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL)     /*!< 24 bit sample.                                                       */
38415   #define I2S_CONFIG_SWIDTH_SWIDTH_32Bit (0x3UL)     /*!< 32 bit sample.                                                       */
38416   #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16 (0x4UL)  /*!< 8 bit sample in a 16-bit half-frame.                                 */
38417   #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32 (0x5UL)  /*!< 8 bit sample in a 32-bit half-frame.                                 */
38418   #define I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32 (0x6UL) /*!< 16 bit sample in a 32-bit half-frame.                                */
38419   #define I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32 (0x7UL) /*!< 24 bit sample in a 32-bit half-frame.                                */
38420 
38421 
38422 /* I2S_CONFIG_ALIGN: Alignment of sample within a frame */
38423   #define I2S_CONFIG_ALIGN_ResetValue (0x00000000UL) /*!< Reset value of ALIGN register.                                       */
38424 
38425 /* ALIGN @Bit 0 : Alignment of sample within a frame */
38426   #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL)           /*!< Position of ALIGN field.                                             */
38427   #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field.                       */
38428   #define I2S_CONFIG_ALIGN_ALIGN_Min (0x0UL)         /*!< Min enumerator value of ALIGN field.                                 */
38429   #define I2S_CONFIG_ALIGN_ALIGN_Max (0x1UL)         /*!< Max enumerator value of ALIGN field.                                 */
38430   #define I2S_CONFIG_ALIGN_ALIGN_Left (0x0UL)        /*!< Left-aligned.                                                        */
38431   #define I2S_CONFIG_ALIGN_ALIGN_Right (0x1UL)       /*!< Right-aligned.                                                       */
38432 
38433 
38434 /* I2S_CONFIG_FORMAT: Frame format */
38435   #define I2S_CONFIG_FORMAT_ResetValue (0x00000000UL) /*!< Reset value of FORMAT register.                                     */
38436 
38437 /* FORMAT @Bit 0 : Frame format */
38438   #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL)         /*!< Position of FORMAT field.                                            */
38439   #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field.                  */
38440   #define I2S_CONFIG_FORMAT_FORMAT_Min (0x0UL)       /*!< Min enumerator value of FORMAT field.                                */
38441   #define I2S_CONFIG_FORMAT_FORMAT_Max (0x1UL)       /*!< Max enumerator value of FORMAT field.                                */
38442   #define I2S_CONFIG_FORMAT_FORMAT_I2S (0x0UL)       /*!< Original I2S format.                                                 */
38443   #define I2S_CONFIG_FORMAT_FORMAT_Aligned (0x1UL)   /*!< Alternate (left- or right-aligned) format.                           */
38444 
38445 
38446 /* I2S_CONFIG_CHANNELS: Enable channels */
38447   #define I2S_CONFIG_CHANNELS_ResetValue (0x00000000UL) /*!< Reset value of CHANNELS register.                                 */
38448 
38449 /* CHANNELS @Bits 0..1 : Enable channels */
38450   #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL)     /*!< Position of CHANNELS field.                                          */
38451   #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field.        */
38452   #define I2S_CONFIG_CHANNELS_CHANNELS_Min (0x0UL)   /*!< Min enumerator value of CHANNELS field.                              */
38453   #define I2S_CONFIG_CHANNELS_CHANNELS_Max (0x2UL)   /*!< Max enumerator value of CHANNELS field.                              */
38454   #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0x0UL) /*!< Stereo.                                                             */
38455   #define I2S_CONFIG_CHANNELS_CHANNELS_Left (0x1UL)  /*!< Left only.                                                           */
38456   #define I2S_CONFIG_CHANNELS_CHANNELS_Right (0x2UL) /*!< Right only.                                                          */
38457 
38458 
38459 /* I2S_CONFIG_CLKCONFIG: Clock source selection for the I2S module */
38460   #define I2S_CONFIG_CLKCONFIG_ResetValue (0x00000000UL) /*!< Reset value of CLKCONFIG register.                               */
38461 
38462 /* CLKSRC @Bit 0 : Clock source selection */
38463   #define I2S_CONFIG_CLKCONFIG_CLKSRC_Pos (0UL)      /*!< Position of CLKSRC field.                                            */
38464   #define I2S_CONFIG_CLKCONFIG_CLKSRC_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_CLKSRC_Pos) /*!< Bit mask of CLKSRC field.            */
38465   #define I2S_CONFIG_CLKCONFIG_CLKSRC_Min (0x0UL)    /*!< Min enumerator value of CLKSRC field.                                */
38466   #define I2S_CONFIG_CLKCONFIG_CLKSRC_Max (0x1UL)    /*!< Max enumerator value of CLKSRC field.                                */
38467   #define I2S_CONFIG_CLKCONFIG_CLKSRC_PCLK32M (0x0UL) /*!< 32MHz peripheral clock                                              */
38468   #define I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK (0x1UL)   /*!< Audio PLL clock                                                      */
38469 
38470 /* BYPASS @Bit 8 : Bypass clock generator. MCK will be equal to source input. If bypass is enabled the MCKFREQ setting has no
38471                    effect. */
38472 
38473   #define I2S_CONFIG_CLKCONFIG_BYPASS_Pos (8UL)      /*!< Position of BYPASS field.                                            */
38474   #define I2S_CONFIG_CLKCONFIG_BYPASS_Msk (0x1UL << I2S_CONFIG_CLKCONFIG_BYPASS_Pos) /*!< Bit mask of BYPASS field.            */
38475   #define I2S_CONFIG_CLKCONFIG_BYPASS_Min (0x0UL)    /*!< Min enumerator value of BYPASS field.                                */
38476   #define I2S_CONFIG_CLKCONFIG_BYPASS_Max (0x1UL)    /*!< Max enumerator value of BYPASS field.                                */
38477   #define I2S_CONFIG_CLKCONFIG_BYPASS_Disable (0x0UL) /*!< Disable bypass                                                      */
38478   #define I2S_CONFIG_CLKCONFIG_BYPASS_Enable (0x1UL) /*!< Enable bypass                                                        */
38479 
38480 
38481 
38482 /* ===================================================== Struct I2S_RXD ====================================================== */
38483 /**
38484   * @brief RXD [I2S_RXD] (unspecified)
38485   */
38486 typedef struct {
38487   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Receive buffer RAM start address.                     */
38488 } NRF_I2S_RXD_Type;                                  /*!< Size = 4 (0x004)                                                     */
38489 
38490 /* I2S_RXD_PTR: Receive buffer RAM start address. */
38491   #define I2S_RXD_PTR_ResetValue (0x00000000UL)      /*!< Reset value of PTR register.                                         */
38492 
38493 /* PTR @Bits 0..31 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this
38494                      address. This address is a word aligned Data RAM address. */
38495 
38496   #define I2S_RXD_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
38497   #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */
38498 
38499 
38500 
38501 /* ===================================================== Struct I2S_TXD ====================================================== */
38502 /**
38503   * @brief TXD [I2S_TXD] (unspecified)
38504   */
38505 typedef struct {
38506   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Transmit buffer RAM start address                     */
38507 } NRF_I2S_TXD_Type;                                  /*!< Size = 4 (0x004)                                                     */
38508 
38509 /* I2S_TXD_PTR: Transmit buffer RAM start address */
38510   #define I2S_TXD_PTR_ResetValue (0x00000000UL)      /*!< Reset value of PTR register.                                         */
38511 
38512 /* PTR @Bits 0..31 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from
38513                      this address. This address is a word aligned Data RAM address. */
38514 
38515   #define I2S_TXD_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
38516   #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */
38517 
38518 
38519 
38520 /* ==================================================== Struct I2S_RXTXD ===================================================== */
38521 /**
38522   * @brief RXTXD [I2S_RXTXD] (unspecified)
38523   */
38524 typedef struct {
38525   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000000) Size of RXD and TXD buffers                           */
38526   __IM  uint32_t  RESERVED;
38527 } NRF_I2S_RXTXD_Type;                                /*!< Size = 8 (0x008)                                                     */
38528 
38529 /* I2S_RXTXD_MAXCNT: Size of RXD and TXD buffers */
38530   #define I2S_RXTXD_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                      */
38531 
38532 /* MAXCNT @Bits 0..13 : Size of RXD and TXD buffers in number of 32 bit words */
38533   #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL)          /*!< Position of MAXCNT field.                                            */
38534   #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                 */
38535 
38536 
38537 
38538 /* ===================================================== Struct I2S_PSEL ===================================================== */
38539 /**
38540   * @brief PSEL [I2S_PSEL] (unspecified)
38541   */
38542 typedef struct {
38543   __IOM uint32_t  MCK;                               /*!< (@ 0x00000000) Pin select for MCK signal                             */
38544   __IOM uint32_t  SCK;                               /*!< (@ 0x00000004) Pin select for SCK signal                             */
38545   __IOM uint32_t  LRCK;                              /*!< (@ 0x00000008) Pin select for LRCK signal                            */
38546   __IOM uint32_t  SDIN;                              /*!< (@ 0x0000000C) Pin select for SDIN signal                            */
38547   __IOM uint32_t  SDOUT;                             /*!< (@ 0x00000010) Pin select for SDOUT signal                           */
38548 } NRF_I2S_PSEL_Type;                                 /*!< Size = 20 (0x014)                                                    */
38549 
38550 /* I2S_PSEL_MCK: Pin select for MCK signal */
38551   #define I2S_PSEL_MCK_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of MCK register.                                         */
38552 
38553 /* PIN @Bits 0..4 : Pin number */
38554   #define I2S_PSEL_MCK_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
38555   #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field.                                    */
38556   #define I2S_PSEL_MCK_PIN_Min (0x0UL)               /*!< Min value of PIN field.                                              */
38557   #define I2S_PSEL_MCK_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */
38558 
38559 /* PORT @Bits 5..8 : Port number */
38560   #define I2S_PSEL_MCK_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
38561   #define I2S_PSEL_MCK_PORT_Msk (0xFUL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field.                                  */
38562   #define I2S_PSEL_MCK_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
38563   #define I2S_PSEL_MCK_PORT_Max (0xFUL)              /*!< Max size of PORT field.                                              */
38564 
38565 /* CONNECT @Bit 31 : Connection */
38566   #define I2S_PSEL_MCK_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
38567   #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
38568   #define I2S_PSEL_MCK_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
38569   #define I2S_PSEL_MCK_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
38570   #define I2S_PSEL_MCK_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
38571   #define I2S_PSEL_MCK_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */
38572 
38573 
38574 /* I2S_PSEL_SCK: Pin select for SCK signal */
38575   #define I2S_PSEL_SCK_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of SCK register.                                         */
38576 
38577 /* PIN @Bits 0..4 : Pin number */
38578   #define I2S_PSEL_SCK_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
38579   #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field.                                    */
38580   #define I2S_PSEL_SCK_PIN_Min (0x0UL)               /*!< Min value of PIN field.                                              */
38581   #define I2S_PSEL_SCK_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */
38582 
38583 /* PORT @Bits 5..8 : Port number */
38584   #define I2S_PSEL_SCK_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
38585   #define I2S_PSEL_SCK_PORT_Msk (0xFUL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field.                                  */
38586   #define I2S_PSEL_SCK_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
38587   #define I2S_PSEL_SCK_PORT_Max (0xFUL)              /*!< Max size of PORT field.                                              */
38588 
38589 /* CONNECT @Bit 31 : Connection */
38590   #define I2S_PSEL_SCK_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
38591   #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
38592   #define I2S_PSEL_SCK_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
38593   #define I2S_PSEL_SCK_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
38594   #define I2S_PSEL_SCK_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
38595   #define I2S_PSEL_SCK_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */
38596 
38597 
38598 /* I2S_PSEL_LRCK: Pin select for LRCK signal */
38599   #define I2S_PSEL_LRCK_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of LRCK register.                                        */
38600 
38601 /* PIN @Bits 0..4 : Pin number */
38602   #define I2S_PSEL_LRCK_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
38603   #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field.                                  */
38604   #define I2S_PSEL_LRCK_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
38605   #define I2S_PSEL_LRCK_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
38606 
38607 /* PORT @Bits 5..8 : Port number */
38608   #define I2S_PSEL_LRCK_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
38609   #define I2S_PSEL_LRCK_PORT_Msk (0xFUL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field.                                */
38610   #define I2S_PSEL_LRCK_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
38611   #define I2S_PSEL_LRCK_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
38612 
38613 /* CONNECT @Bit 31 : Connection */
38614   #define I2S_PSEL_LRCK_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
38615   #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
38616   #define I2S_PSEL_LRCK_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
38617   #define I2S_PSEL_LRCK_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
38618   #define I2S_PSEL_LRCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
38619   #define I2S_PSEL_LRCK_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
38620 
38621 
38622 /* I2S_PSEL_SDIN: Pin select for SDIN signal */
38623   #define I2S_PSEL_SDIN_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SDIN register.                                        */
38624 
38625 /* PIN @Bits 0..4 : Pin number */
38626   #define I2S_PSEL_SDIN_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
38627   #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field.                                  */
38628   #define I2S_PSEL_SDIN_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
38629   #define I2S_PSEL_SDIN_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
38630 
38631 /* PORT @Bits 5..8 : Port number */
38632   #define I2S_PSEL_SDIN_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
38633   #define I2S_PSEL_SDIN_PORT_Msk (0xFUL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field.                                */
38634   #define I2S_PSEL_SDIN_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
38635   #define I2S_PSEL_SDIN_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
38636 
38637 /* CONNECT @Bit 31 : Connection */
38638   #define I2S_PSEL_SDIN_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
38639   #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
38640   #define I2S_PSEL_SDIN_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
38641   #define I2S_PSEL_SDIN_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
38642   #define I2S_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
38643   #define I2S_PSEL_SDIN_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
38644 
38645 
38646 /* I2S_PSEL_SDOUT: Pin select for SDOUT signal */
38647   #define I2S_PSEL_SDOUT_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of SDOUT register.                                       */
38648 
38649 /* PIN @Bits 0..4 : Pin number */
38650   #define I2S_PSEL_SDOUT_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
38651   #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field.                                */
38652   #define I2S_PSEL_SDOUT_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
38653   #define I2S_PSEL_SDOUT_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
38654 
38655 /* PORT @Bits 5..8 : Port number */
38656   #define I2S_PSEL_SDOUT_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
38657   #define I2S_PSEL_SDOUT_PORT_Msk (0xFUL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field.                              */
38658   #define I2S_PSEL_SDOUT_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
38659   #define I2S_PSEL_SDOUT_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
38660 
38661 /* CONNECT @Bit 31 : Connection */
38662   #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
38663   #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
38664   #define I2S_PSEL_SDOUT_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
38665   #define I2S_PSEL_SDOUT_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
38666   #define I2S_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
38667   #define I2S_PSEL_SDOUT_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
38668 
38669 
38670 /* ======================================================= Struct I2S ======================================================== */
38671 /**
38672   * @brief Inter-IC Sound
38673   */
38674   typedef struct {                                   /*!< I2S Structure                                                        */
38675     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK
38676                                                                          generator when this is enabled*/
38677     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stops I2S transfer and MCK generator. Triggering this
38678                                                                          task will cause the event STOPPED to be generated.*/
38679     __IM uint32_t RESERVED[30];
38680     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
38681     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
38682     __IM uint32_t RESERVED1[31];
38683     __IOM uint32_t EVENTS_RXPTRUPD;                  /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal
38684                                                                          double-buffers. When the I2S module is started and RX
38685                                                                          is enabled, this event will be generated for every
38686                                                                          RXTXD.MAXCNT words received on the SDIN pin.*/
38687     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000108) I2S transfer stopped.                                 */
38688     __IM uint32_t RESERVED2[2];
38689     __IOM uint32_t EVENTS_TXPTRUPD;                  /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal
38690                                                                          double-buffers. When the I2S module is started and TX
38691                                                                          is enabled, this event will be generated for every
38692                                                                          RXTXD.MAXCNT words that are sent on the SDOUT pin.*/
38693     __IM uint32_t RESERVED3;
38694     __IOM uint32_t EVENTS_FRAMESTART;                /*!< (@ 0x0000011C) Frame start event, generated on the active edge of
38695                                                                          LRCK*/
38696     __IM uint32_t RESERVED4[25];
38697     __IOM uint32_t PUBLISH_RXPTRUPD;                 /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD              */
38698     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000188) Publish configuration for event STOPPED               */
38699     __IM uint32_t RESERVED5[2];
38700     __IOM uint32_t PUBLISH_TXPTRUPD;                 /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD              */
38701     __IM uint32_t RESERVED6;
38702     __IOM uint32_t PUBLISH_FRAMESTART;               /*!< (@ 0x0000019C) Publish configuration for event FRAMESTART            */
38703     __IM uint32_t RESERVED7[88];
38704     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
38705     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
38706     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
38707     __IM uint32_t RESERVED8[125];
38708     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable I2S module                                     */
38709     __IOM NRF_I2S_CONFIG_Type CONFIG;                /*!< (@ 0x00000504) (unspecified)                                         */
38710     __IM uint32_t RESERVED9[2];
38711     __IOM NRF_I2S_RXD_Type RXD;                      /*!< (@ 0x00000538) (unspecified)                                         */
38712     __IM uint32_t RESERVED10;
38713     __IOM NRF_I2S_TXD_Type TXD;                      /*!< (@ 0x00000540) (unspecified)                                         */
38714     __IM uint32_t RESERVED11[3];
38715     __IOM NRF_I2S_RXTXD_Type RXTXD;                  /*!< (@ 0x00000550) (unspecified)                                         */
38716     __IM uint32_t RESERVED12[2];
38717     __IOM NRF_I2S_PSEL_Type PSEL;                    /*!< (@ 0x00000560) (unspecified)                                         */
38718   } NRF_I2S_Type;                                    /*!< Size = 1396 (0x574)                                                  */
38719 
38720 /* I2S_TASKS_START: Starts continuous I2S transfer. Also starts MCK generator when this is enabled */
38721   #define I2S_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
38722 
38723 /* TASKS_START @Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled */
38724   #define I2S_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
38725   #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
38726   #define I2S_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
38727   #define I2S_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
38728   #define I2S_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
38729 
38730 
38731 /* I2S_TASKS_STOP: Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */
38732   #define I2S_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
38733 
38734 /* TASKS_STOP @Bit 0 : Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated.
38735                        */
38736 
38737   #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
38738   #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
38739   #define I2S_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
38740   #define I2S_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
38741   #define I2S_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
38742 
38743 
38744 /* I2S_SUBSCRIBE_START: Subscribe configuration for task START */
38745   #define I2S_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */
38746 
38747 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
38748   #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
38749   #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
38750   #define I2S_SUBSCRIBE_START_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
38751   #define I2S_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
38752 
38753 /* EN @Bit 31 : (unspecified) */
38754   #define I2S_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
38755   #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
38756   #define I2S_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
38757   #define I2S_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
38758   #define I2S_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
38759   #define I2S_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
38760 
38761 
38762 /* I2S_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
38763   #define I2S_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */
38764 
38765 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
38766   #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
38767   #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
38768   #define I2S_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
38769   #define I2S_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
38770 
38771 /* EN @Bit 31 : (unspecified) */
38772   #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
38773   #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
38774   #define I2S_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
38775   #define I2S_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
38776   #define I2S_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
38777   #define I2S_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
38778 
38779 
38780 /* I2S_EVENTS_RXPTRUPD: The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX
38781                          is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */
38782 
38783   #define I2S_EVENTS_RXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXPTRUPD register.                          */
38784 
38785 /* EVENTS_RXPTRUPD @Bit 0 : The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and
38786                             RX is enabled, this event will be generated for every RXTXD.MAXCNT words received on the SDIN pin. */
38787 
38788   #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field.                                */
38789   #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of
38790                                                                             EVENTS_RXPTRUPD field.*/
38791   #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXPTRUPD field.                  */
38792   #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXPTRUPD field.                  */
38793   #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated                                    */
38794   #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated                                           */
38795 
38796 
38797 /* I2S_EVENTS_STOPPED: I2S transfer stopped. */
38798   #define I2S_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                            */
38799 
38800 /* EVENTS_STOPPED @Bit 0 : I2S transfer stopped. */
38801   #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                   */
38802   #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED
38803                                                                             field.*/
38804   #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                     */
38805   #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                     */
38806   #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                      */
38807   #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                             */
38808 
38809 
38810 /* I2S_EVENTS_TXPTRUPD: The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX
38811                          is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */
38812 
38813   #define I2S_EVENTS_TXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXPTRUPD register.                          */
38814 
38815 /* EVENTS_TXPTRUPD @Bit 0 : The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and
38816                             TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT
38817                             pin. */
38818 
38819   #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field.                                */
38820   #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of
38821                                                                             EVENTS_TXPTRUPD field.*/
38822   #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXPTRUPD field.                  */
38823   #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXPTRUPD field.                  */
38824   #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated                                    */
38825   #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated                                           */
38826 
38827 
38828 /* I2S_EVENTS_FRAMESTART: Frame start event, generated on the active edge of LRCK */
38829   #define I2S_EVENTS_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMESTART register.                      */
38830 
38831 /* EVENTS_FRAMESTART @Bit 0 : Frame start event, generated on the active edge of LRCK */
38832   #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field.                          */
38833   #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of
38834                                                                             EVENTS_FRAMESTART field.*/
38835   #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMESTART field.            */
38836   #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMESTART field.            */
38837   #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated                                */
38838   #define I2S_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated                                       */
38839 
38840 
38841 /* I2S_PUBLISH_RXPTRUPD: Publish configuration for event RXPTRUPD */
38842   #define I2S_PUBLISH_RXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXPTRUPD register.                        */
38843 
38844 /* CHIDX @Bits 0..7 : DPPI channel that event RXPTRUPD will publish to */
38845   #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
38846   #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
38847   #define I2S_PUBLISH_RXPTRUPD_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
38848   #define I2S_PUBLISH_RXPTRUPD_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
38849 
38850 /* EN @Bit 31 : (unspecified) */
38851   #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL)         /*!< Position of EN field.                                                */
38852   #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field.                        */
38853   #define I2S_PUBLISH_RXPTRUPD_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
38854   #define I2S_PUBLISH_RXPTRUPD_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
38855   #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
38856   #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
38857 
38858 
38859 /* I2S_PUBLISH_STOPPED: Publish configuration for event STOPPED */
38860   #define I2S_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                          */
38861 
38862 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
38863   #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
38864   #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
38865   #define I2S_PUBLISH_STOPPED_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
38866   #define I2S_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
38867 
38868 /* EN @Bit 31 : (unspecified) */
38869   #define I2S_PUBLISH_STOPPED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
38870   #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                          */
38871   #define I2S_PUBLISH_STOPPED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
38872   #define I2S_PUBLISH_STOPPED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
38873   #define I2S_PUBLISH_STOPPED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
38874   #define I2S_PUBLISH_STOPPED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
38875 
38876 
38877 /* I2S_PUBLISH_TXPTRUPD: Publish configuration for event TXPTRUPD */
38878   #define I2S_PUBLISH_TXPTRUPD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXPTRUPD register.                        */
38879 
38880 /* CHIDX @Bits 0..7 : DPPI channel that event TXPTRUPD will publish to */
38881   #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
38882   #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
38883   #define I2S_PUBLISH_TXPTRUPD_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
38884   #define I2S_PUBLISH_TXPTRUPD_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
38885 
38886 /* EN @Bit 31 : (unspecified) */
38887   #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL)         /*!< Position of EN field.                                                */
38888   #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field.                        */
38889   #define I2S_PUBLISH_TXPTRUPD_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
38890   #define I2S_PUBLISH_TXPTRUPD_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
38891   #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
38892   #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
38893 
38894 
38895 /* I2S_PUBLISH_FRAMESTART: Publish configuration for event FRAMESTART */
38896   #define I2S_PUBLISH_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMESTART register.                    */
38897 
38898 /* CHIDX @Bits 0..7 : DPPI channel that event FRAMESTART will publish to */
38899   #define I2S_PUBLISH_FRAMESTART_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
38900   #define I2S_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << I2S_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
38901   #define I2S_PUBLISH_FRAMESTART_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
38902   #define I2S_PUBLISH_FRAMESTART_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
38903 
38904 /* EN @Bit 31 : (unspecified) */
38905   #define I2S_PUBLISH_FRAMESTART_EN_Pos (31UL)       /*!< Position of EN field.                                                */
38906   #define I2S_PUBLISH_FRAMESTART_EN_Msk (0x1UL << I2S_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field.                    */
38907   #define I2S_PUBLISH_FRAMESTART_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
38908   #define I2S_PUBLISH_FRAMESTART_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
38909   #define I2S_PUBLISH_FRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
38910   #define I2S_PUBLISH_FRAMESTART_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
38911 
38912 
38913 /* I2S_INTEN: Enable or disable interrupt */
38914   #define I2S_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
38915 
38916 /* RXPTRUPD @Bit 1 : Enable or disable interrupt for event RXPTRUPD */
38917   #define I2S_INTEN_RXPTRUPD_Pos (1UL)               /*!< Position of RXPTRUPD field.                                          */
38918   #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field.                            */
38919   #define I2S_INTEN_RXPTRUPD_Min (0x0UL)             /*!< Min enumerator value of RXPTRUPD field.                              */
38920   #define I2S_INTEN_RXPTRUPD_Max (0x1UL)             /*!< Max enumerator value of RXPTRUPD field.                              */
38921   #define I2S_INTEN_RXPTRUPD_Disabled (0x0UL)        /*!< Disable                                                              */
38922   #define I2S_INTEN_RXPTRUPD_Enabled (0x1UL)         /*!< Enable                                                               */
38923 
38924 /* STOPPED @Bit 2 : Enable or disable interrupt for event STOPPED */
38925   #define I2S_INTEN_STOPPED_Pos (2UL)                /*!< Position of STOPPED field.                                           */
38926   #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                               */
38927   #define I2S_INTEN_STOPPED_Min (0x0UL)              /*!< Min enumerator value of STOPPED field.                               */
38928   #define I2S_INTEN_STOPPED_Max (0x1UL)              /*!< Max enumerator value of STOPPED field.                               */
38929   #define I2S_INTEN_STOPPED_Disabled (0x0UL)         /*!< Disable                                                              */
38930   #define I2S_INTEN_STOPPED_Enabled (0x1UL)          /*!< Enable                                                               */
38931 
38932 /* TXPTRUPD @Bit 5 : Enable or disable interrupt for event TXPTRUPD */
38933   #define I2S_INTEN_TXPTRUPD_Pos (5UL)               /*!< Position of TXPTRUPD field.                                          */
38934   #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field.                            */
38935   #define I2S_INTEN_TXPTRUPD_Min (0x0UL)             /*!< Min enumerator value of TXPTRUPD field.                              */
38936   #define I2S_INTEN_TXPTRUPD_Max (0x1UL)             /*!< Max enumerator value of TXPTRUPD field.                              */
38937   #define I2S_INTEN_TXPTRUPD_Disabled (0x0UL)        /*!< Disable                                                              */
38938   #define I2S_INTEN_TXPTRUPD_Enabled (0x1UL)         /*!< Enable                                                               */
38939 
38940 /* FRAMESTART @Bit 7 : Enable or disable interrupt for event FRAMESTART */
38941   #define I2S_INTEN_FRAMESTART_Pos (7UL)             /*!< Position of FRAMESTART field.                                        */
38942   #define I2S_INTEN_FRAMESTART_Msk (0x1UL << I2S_INTEN_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.                      */
38943   #define I2S_INTEN_FRAMESTART_Min (0x0UL)           /*!< Min enumerator value of FRAMESTART field.                            */
38944   #define I2S_INTEN_FRAMESTART_Max (0x1UL)           /*!< Max enumerator value of FRAMESTART field.                            */
38945   #define I2S_INTEN_FRAMESTART_Disabled (0x0UL)      /*!< Disable                                                              */
38946   #define I2S_INTEN_FRAMESTART_Enabled (0x1UL)       /*!< Enable                                                               */
38947 
38948 
38949 /* I2S_INTENSET: Enable interrupt */
38950   #define I2S_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
38951 
38952 /* RXPTRUPD @Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */
38953   #define I2S_INTENSET_RXPTRUPD_Pos (1UL)            /*!< Position of RXPTRUPD field.                                          */
38954   #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field.                      */
38955   #define I2S_INTENSET_RXPTRUPD_Min (0x0UL)          /*!< Min enumerator value of RXPTRUPD field.                              */
38956   #define I2S_INTENSET_RXPTRUPD_Max (0x1UL)          /*!< Max enumerator value of RXPTRUPD field.                              */
38957   #define I2S_INTENSET_RXPTRUPD_Set (0x1UL)          /*!< Enable                                                               */
38958   #define I2S_INTENSET_RXPTRUPD_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
38959   #define I2S_INTENSET_RXPTRUPD_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
38960 
38961 /* STOPPED @Bit 2 : Write '1' to enable interrupt for event STOPPED */
38962   #define I2S_INTENSET_STOPPED_Pos (2UL)             /*!< Position of STOPPED field.                                           */
38963   #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
38964   #define I2S_INTENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
38965   #define I2S_INTENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
38966   #define I2S_INTENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
38967   #define I2S_INTENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
38968   #define I2S_INTENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
38969 
38970 /* TXPTRUPD @Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */
38971   #define I2S_INTENSET_TXPTRUPD_Pos (5UL)            /*!< Position of TXPTRUPD field.                                          */
38972   #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field.                      */
38973   #define I2S_INTENSET_TXPTRUPD_Min (0x0UL)          /*!< Min enumerator value of TXPTRUPD field.                              */
38974   #define I2S_INTENSET_TXPTRUPD_Max (0x1UL)          /*!< Max enumerator value of TXPTRUPD field.                              */
38975   #define I2S_INTENSET_TXPTRUPD_Set (0x1UL)          /*!< Enable                                                               */
38976   #define I2S_INTENSET_TXPTRUPD_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
38977   #define I2S_INTENSET_TXPTRUPD_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
38978 
38979 /* FRAMESTART @Bit 7 : Write '1' to enable interrupt for event FRAMESTART */
38980   #define I2S_INTENSET_FRAMESTART_Pos (7UL)          /*!< Position of FRAMESTART field.                                        */
38981   #define I2S_INTENSET_FRAMESTART_Msk (0x1UL << I2S_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.                */
38982   #define I2S_INTENSET_FRAMESTART_Min (0x0UL)        /*!< Min enumerator value of FRAMESTART field.                            */
38983   #define I2S_INTENSET_FRAMESTART_Max (0x1UL)        /*!< Max enumerator value of FRAMESTART field.                            */
38984   #define I2S_INTENSET_FRAMESTART_Set (0x1UL)        /*!< Enable                                                               */
38985   #define I2S_INTENSET_FRAMESTART_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
38986   #define I2S_INTENSET_FRAMESTART_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
38987 
38988 
38989 /* I2S_INTENCLR: Disable interrupt */
38990   #define I2S_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
38991 
38992 /* RXPTRUPD @Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */
38993   #define I2S_INTENCLR_RXPTRUPD_Pos (1UL)            /*!< Position of RXPTRUPD field.                                          */
38994   #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field.                      */
38995   #define I2S_INTENCLR_RXPTRUPD_Min (0x0UL)          /*!< Min enumerator value of RXPTRUPD field.                              */
38996   #define I2S_INTENCLR_RXPTRUPD_Max (0x1UL)          /*!< Max enumerator value of RXPTRUPD field.                              */
38997   #define I2S_INTENCLR_RXPTRUPD_Clear (0x1UL)        /*!< Disable                                                              */
38998   #define I2S_INTENCLR_RXPTRUPD_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
38999   #define I2S_INTENCLR_RXPTRUPD_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
39000 
39001 /* STOPPED @Bit 2 : Write '1' to disable interrupt for event STOPPED */
39002   #define I2S_INTENCLR_STOPPED_Pos (2UL)             /*!< Position of STOPPED field.                                           */
39003   #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
39004   #define I2S_INTENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
39005   #define I2S_INTENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
39006   #define I2S_INTENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
39007   #define I2S_INTENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
39008   #define I2S_INTENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
39009 
39010 /* TXPTRUPD @Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */
39011   #define I2S_INTENCLR_TXPTRUPD_Pos (5UL)            /*!< Position of TXPTRUPD field.                                          */
39012   #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field.                      */
39013   #define I2S_INTENCLR_TXPTRUPD_Min (0x0UL)          /*!< Min enumerator value of TXPTRUPD field.                              */
39014   #define I2S_INTENCLR_TXPTRUPD_Max (0x1UL)          /*!< Max enumerator value of TXPTRUPD field.                              */
39015   #define I2S_INTENCLR_TXPTRUPD_Clear (0x1UL)        /*!< Disable                                                              */
39016   #define I2S_INTENCLR_TXPTRUPD_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
39017   #define I2S_INTENCLR_TXPTRUPD_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
39018 
39019 /* FRAMESTART @Bit 7 : Write '1' to disable interrupt for event FRAMESTART */
39020   #define I2S_INTENCLR_FRAMESTART_Pos (7UL)          /*!< Position of FRAMESTART field.                                        */
39021   #define I2S_INTENCLR_FRAMESTART_Msk (0x1UL << I2S_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.                */
39022   #define I2S_INTENCLR_FRAMESTART_Min (0x0UL)        /*!< Min enumerator value of FRAMESTART field.                            */
39023   #define I2S_INTENCLR_FRAMESTART_Max (0x1UL)        /*!< Max enumerator value of FRAMESTART field.                            */
39024   #define I2S_INTENCLR_FRAMESTART_Clear (0x1UL)      /*!< Disable                                                              */
39025   #define I2S_INTENCLR_FRAMESTART_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
39026   #define I2S_INTENCLR_FRAMESTART_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
39027 
39028 
39029 /* I2S_ENABLE: Enable I2S module */
39030   #define I2S_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */
39031 
39032 /* ENABLE @Bit 0 : Enable I2S module */
39033   #define I2S_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
39034   #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
39035   #define I2S_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
39036   #define I2S_ENABLE_ENABLE_Max (0x1UL)              /*!< Max enumerator value of ENABLE field.                                */
39037   #define I2S_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disable                                                              */
39038   #define I2S_ENABLE_ENABLE_Enabled (0x1UL)          /*!< Enable                                                               */
39039 
39040 
39041 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
39042 
39043 /* =========================================================================================================================== */
39044 /* ================                                            I3C                                            ================ */
39045 /* =========================================================================================================================== */
39046 
39047 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
39048 
39049 /* ===================================================== Struct I3C_CDR ====================================================== */
39050 /**
39051   * @brief CDR [I3C_CDR] (unspecified)
39052   */
39053 typedef struct {
39054   __IOM uint32_t  STARTOFFSET;                       /*!< (@ 0x00000000) Start offset of recovered clock                       */
39055   __IOM uint32_t  MAXCYCLERATIO;                     /*!< (@ 0x00000004) Maximum cycle ratio between SDA/SCL and CDR (clock and
39056                                                                          data recovery) clock*/
39057   __IOM uint32_t  MAXSKEW;                           /*!< (@ 0x00000008) Maximum skew between SCL and SCL in CDR clock cycles  */
39058 } NRF_I3C_CDR_Type;                                  /*!< Size = 12 (0x00C)                                                    */
39059 
39060 /* I3C_CDR_STARTOFFSET: Start offset of recovered clock */
39061   #define I3C_CDR_STARTOFFSET_ResetValue (0x00000004UL) /*!< Reset value of STARTOFFSET register.                              */
39062 
39063 /* VAL @Bits 0..15 : Value */
39064   #define I3C_CDR_STARTOFFSET_VAL_Pos (0UL)          /*!< Position of VAL field.                                               */
39065   #define I3C_CDR_STARTOFFSET_VAL_Msk (0xFFFFUL << I3C_CDR_STARTOFFSET_VAL_Pos) /*!< Bit mask of VAL field.                    */
39066 
39067 
39068 /* I3C_CDR_MAXCYCLERATIO: Maximum cycle ratio between SDA/SCL and CDR (clock and data recovery) clock */
39069   #define I3C_CDR_MAXCYCLERATIO_ResetValue (0x00000028UL) /*!< Reset value of MAXCYCLERATIO register.                          */
39070 
39071 /* VAL @Bits 0..15 : Value */
39072   #define I3C_CDR_MAXCYCLERATIO_VAL_Pos (0UL)        /*!< Position of VAL field.                                               */
39073   #define I3C_CDR_MAXCYCLERATIO_VAL_Msk (0xFFFFUL << I3C_CDR_MAXCYCLERATIO_VAL_Pos) /*!< Bit mask of VAL field.                */
39074 
39075 
39076 /* I3C_CDR_MAXSKEW: Maximum skew between SCL and SCL in CDR clock cycles */
39077   #define I3C_CDR_MAXSKEW_ResetValue (0x00000005UL)  /*!< Reset value of MAXSKEW register.                                     */
39078 
39079 /* VAL @Bits 0..7 : Value */
39080   #define I3C_CDR_MAXSKEW_VAL_Pos (0UL)              /*!< Position of VAL field.                                               */
39081   #define I3C_CDR_MAXSKEW_VAL_Msk (0xFFUL << I3C_CDR_MAXSKEW_VAL_Pos) /*!< Bit mask of VAL field.                              */
39082 
39083 
39084 /* ======================================================= Struct I3C ======================================================== */
39085 /**
39086   * @brief I3C
39087   */
39088   typedef struct {                                   /*!< I3C Structure                                                        */
39089     __IM uint32_t RESERVED[64];
39090     __IOM uint32_t EVENTS_CORE;                      /*!< (@ 0x00000100) Event indicating that interrupt triggered at I3C core */
39091     __IOM uint32_t EVENTS_DMA;                       /*!< (@ 0x00000104) Event indicating that interrupt triggered at I3C DMA  */
39092     __IM uint32_t RESERVED1[126];
39093     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
39094     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
39095     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
39096     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
39097     __IM uint32_t RESERVED2[60];
39098     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000400) Enable I3C peripheral.                                */
39099     __IOM NRF_I3C_CDR_Type CDR;                      /*!< (@ 0x00000404) (unspecified)                                         */
39100     __IOM uint32_t SLAVEIF0;                         /*!< (@ 0x00000410) I3C slave interface 0                                 */
39101     __IOM uint32_t SLAVEIF1;                         /*!< (@ 0x00000414) I3C slave interface 1                                 */
39102     __IOM uint32_t SLAVEPID0;                        /*!< (@ 0x00000418) Slave Device Provisioned ID 0                         */
39103     __IOM uint32_t SLAVEPID1;                        /*!< (@ 0x0000041C) Slave Device Provisioned ID 1                         */
39104     __IOM uint32_t KEEPSDA;                          /*!< (@ 0x00000420) Enable or disable the SDA high-keeper used for
39105                                                                          Master-to-Slave and Slave-to-Master bus hand-off.*/
39106     __IOM uint32_t KEEPSCL;                          /*!< (@ 0x00000424) Enable or disable the SCL high-keeper used for
39107                                                                          Master-to-Slave and Slave-to-Master bus hand-off.*/
39108   } NRF_I3C_Type;                                    /*!< Size = 1064 (0x428)                                                  */
39109 
39110 /* I3C_EVENTS_CORE: Event indicating that interrupt triggered at I3C core */
39111   #define I3C_EVENTS_CORE_ResetValue (0x00000000UL)  /*!< Reset value of EVENTS_CORE register.                                 */
39112 
39113 /* EVENTS_CORE @Bit 0 : Event indicating that interrupt triggered at I3C core */
39114   #define I3C_EVENTS_CORE_EVENTS_CORE_Pos (0UL)      /*!< Position of EVENTS_CORE field.                                       */
39115   #define I3C_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << I3C_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field.       */
39116   #define I3C_EVENTS_CORE_EVENTS_CORE_Min (0x0UL)    /*!< Min enumerator value of EVENTS_CORE field.                           */
39117   #define I3C_EVENTS_CORE_EVENTS_CORE_Max (0x1UL)    /*!< Max enumerator value of EVENTS_CORE field.                           */
39118   #define I3C_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL) /*!< Event not generated                                            */
39119   #define I3C_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL) /*!< Event generated                                                   */
39120 
39121 
39122 /* I3C_EVENTS_DMA: Event indicating that interrupt triggered at I3C DMA */
39123   #define I3C_EVENTS_DMA_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_DMA register.                                  */
39124 
39125 /* EVENTS_DMA @Bit 0 : Event indicating that interrupt triggered at I3C DMA */
39126   #define I3C_EVENTS_DMA_EVENTS_DMA_Pos (0UL)        /*!< Position of EVENTS_DMA field.                                        */
39127   #define I3C_EVENTS_DMA_EVENTS_DMA_Msk (0x1UL << I3C_EVENTS_DMA_EVENTS_DMA_Pos) /*!< Bit mask of EVENTS_DMA field.            */
39128   #define I3C_EVENTS_DMA_EVENTS_DMA_Min (0x0UL)      /*!< Min enumerator value of EVENTS_DMA field.                            */
39129   #define I3C_EVENTS_DMA_EVENTS_DMA_Max (0x1UL)      /*!< Max enumerator value of EVENTS_DMA field.                            */
39130   #define I3C_EVENTS_DMA_EVENTS_DMA_NotGenerated (0x0UL) /*!< Event not generated                                              */
39131   #define I3C_EVENTS_DMA_EVENTS_DMA_Generated (0x1UL) /*!< Event generated                                                     */
39132 
39133 
39134 /* I3C_INTEN: Enable or disable interrupt */
39135   #define I3C_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
39136 
39137 /* CORE @Bit 0 : Enable or disable interrupt for event CORE */
39138   #define I3C_INTEN_CORE_Pos (0UL)                   /*!< Position of CORE field.                                              */
39139   #define I3C_INTEN_CORE_Msk (0x1UL << I3C_INTEN_CORE_Pos) /*!< Bit mask of CORE field.                                        */
39140   #define I3C_INTEN_CORE_Min (0x0UL)                 /*!< Min enumerator value of CORE field.                                  */
39141   #define I3C_INTEN_CORE_Max (0x1UL)                 /*!< Max enumerator value of CORE field.                                  */
39142   #define I3C_INTEN_CORE_Disabled (0x0UL)            /*!< Disable                                                              */
39143   #define I3C_INTEN_CORE_Enabled (0x1UL)             /*!< Enable                                                               */
39144 
39145 /* DMA @Bit 1 : Enable or disable interrupt for event DMA */
39146   #define I3C_INTEN_DMA_Pos (1UL)                    /*!< Position of DMA field.                                               */
39147   #define I3C_INTEN_DMA_Msk (0x1UL << I3C_INTEN_DMA_Pos) /*!< Bit mask of DMA field.                                           */
39148   #define I3C_INTEN_DMA_Min (0x0UL)                  /*!< Min enumerator value of DMA field.                                   */
39149   #define I3C_INTEN_DMA_Max (0x1UL)                  /*!< Max enumerator value of DMA field.                                   */
39150   #define I3C_INTEN_DMA_Disabled (0x0UL)             /*!< Disable                                                              */
39151   #define I3C_INTEN_DMA_Enabled (0x1UL)              /*!< Enable                                                               */
39152 
39153 
39154 /* I3C_INTENSET: Enable interrupt */
39155   #define I3C_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
39156 
39157 /* CORE @Bit 0 : Write '1' to enable interrupt for event CORE */
39158   #define I3C_INTENSET_CORE_Pos (0UL)                /*!< Position of CORE field.                                              */
39159   #define I3C_INTENSET_CORE_Msk (0x1UL << I3C_INTENSET_CORE_Pos) /*!< Bit mask of CORE field.                                  */
39160   #define I3C_INTENSET_CORE_Min (0x0UL)              /*!< Min enumerator value of CORE field.                                  */
39161   #define I3C_INTENSET_CORE_Max (0x1UL)              /*!< Max enumerator value of CORE field.                                  */
39162   #define I3C_INTENSET_CORE_Set (0x1UL)              /*!< Enable                                                               */
39163   #define I3C_INTENSET_CORE_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
39164   #define I3C_INTENSET_CORE_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
39165 
39166 /* DMA @Bit 1 : Write '1' to enable interrupt for event DMA */
39167   #define I3C_INTENSET_DMA_Pos (1UL)                 /*!< Position of DMA field.                                               */
39168   #define I3C_INTENSET_DMA_Msk (0x1UL << I3C_INTENSET_DMA_Pos) /*!< Bit mask of DMA field.                                     */
39169   #define I3C_INTENSET_DMA_Min (0x0UL)               /*!< Min enumerator value of DMA field.                                   */
39170   #define I3C_INTENSET_DMA_Max (0x1UL)               /*!< Max enumerator value of DMA field.                                   */
39171   #define I3C_INTENSET_DMA_Set (0x1UL)               /*!< Enable                                                               */
39172   #define I3C_INTENSET_DMA_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
39173   #define I3C_INTENSET_DMA_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
39174 
39175 
39176 /* I3C_INTENCLR: Disable interrupt */
39177   #define I3C_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
39178 
39179 /* CORE @Bit 0 : Write '1' to disable interrupt for event CORE */
39180   #define I3C_INTENCLR_CORE_Pos (0UL)                /*!< Position of CORE field.                                              */
39181   #define I3C_INTENCLR_CORE_Msk (0x1UL << I3C_INTENCLR_CORE_Pos) /*!< Bit mask of CORE field.                                  */
39182   #define I3C_INTENCLR_CORE_Min (0x0UL)              /*!< Min enumerator value of CORE field.                                  */
39183   #define I3C_INTENCLR_CORE_Max (0x1UL)              /*!< Max enumerator value of CORE field.                                  */
39184   #define I3C_INTENCLR_CORE_Clear (0x1UL)            /*!< Disable                                                              */
39185   #define I3C_INTENCLR_CORE_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
39186   #define I3C_INTENCLR_CORE_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
39187 
39188 /* DMA @Bit 1 : Write '1' to disable interrupt for event DMA */
39189   #define I3C_INTENCLR_DMA_Pos (1UL)                 /*!< Position of DMA field.                                               */
39190   #define I3C_INTENCLR_DMA_Msk (0x1UL << I3C_INTENCLR_DMA_Pos) /*!< Bit mask of DMA field.                                     */
39191   #define I3C_INTENCLR_DMA_Min (0x0UL)               /*!< Min enumerator value of DMA field.                                   */
39192   #define I3C_INTENCLR_DMA_Max (0x1UL)               /*!< Max enumerator value of DMA field.                                   */
39193   #define I3C_INTENCLR_DMA_Clear (0x1UL)             /*!< Disable                                                              */
39194   #define I3C_INTENCLR_DMA_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
39195   #define I3C_INTENCLR_DMA_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
39196 
39197 
39198 /* I3C_INTPEND: Pending interrupts */
39199   #define I3C_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */
39200 
39201 /* CORE @Bit 0 : Read pending status of interrupt for event CORE */
39202   #define I3C_INTPEND_CORE_Pos (0UL)                 /*!< Position of CORE field.                                              */
39203   #define I3C_INTPEND_CORE_Msk (0x1UL << I3C_INTPEND_CORE_Pos) /*!< Bit mask of CORE field.                                    */
39204   #define I3C_INTPEND_CORE_Min (0x0UL)               /*!< Min enumerator value of CORE field.                                  */
39205   #define I3C_INTPEND_CORE_Max (0x1UL)               /*!< Max enumerator value of CORE field.                                  */
39206   #define I3C_INTPEND_CORE_NotPending (0x0UL)        /*!< Read: Not pending                                                    */
39207   #define I3C_INTPEND_CORE_Pending (0x1UL)           /*!< Read: Pending                                                        */
39208 
39209 /* DMA @Bit 1 : Read pending status of interrupt for event DMA */
39210   #define I3C_INTPEND_DMA_Pos (1UL)                  /*!< Position of DMA field.                                               */
39211   #define I3C_INTPEND_DMA_Msk (0x1UL << I3C_INTPEND_DMA_Pos) /*!< Bit mask of DMA field.                                       */
39212   #define I3C_INTPEND_DMA_Min (0x0UL)                /*!< Min enumerator value of DMA field.                                   */
39213   #define I3C_INTPEND_DMA_Max (0x1UL)                /*!< Max enumerator value of DMA field.                                   */
39214   #define I3C_INTPEND_DMA_NotPending (0x0UL)         /*!< Read: Not pending                                                    */
39215   #define I3C_INTPEND_DMA_Pending (0x1UL)            /*!< Read: Pending                                                        */
39216 
39217 
39218 /* I3C_ENABLE: Enable I3C peripheral. */
39219   #define I3C_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */
39220 
39221 /* EN @Bit 0 : Enable */
39222   #define I3C_ENABLE_EN_Pos (0UL)                    /*!< Position of EN field.                                                */
39223   #define I3C_ENABLE_EN_Msk (0x1UL << I3C_ENABLE_EN_Pos) /*!< Bit mask of EN field.                                            */
39224   #define I3C_ENABLE_EN_Min (0x0UL)                  /*!< Min enumerator value of EN field.                                    */
39225   #define I3C_ENABLE_EN_Max (0x1UL)                  /*!< Max enumerator value of EN field.                                    */
39226   #define I3C_ENABLE_EN_Disabled (0x0UL)             /*!< I3C peripheral disabled.                                             */
39227   #define I3C_ENABLE_EN_Enabled (0x1UL)              /*!< I3C peripheral enabled.                                              */
39228 
39229 
39230 /* I3C_SLAVEIF0: I3C slave interface 0 */
39231   #define I3C_SLAVEIF0_ResetValue (0x00000000UL)     /*!< Reset value of SLAVEIF0 register.                                    */
39232 
39233 /* MODEI2C @Bit 0 : I2C or I3C mode select signal */
39234   #define I3C_SLAVEIF0_MODEI2C_Pos (0UL)             /*!< Position of MODEI2C field.                                           */
39235   #define I3C_SLAVEIF0_MODEI2C_Msk (0x1UL << I3C_SLAVEIF0_MODEI2C_Pos) /*!< Bit mask of MODEI2C field.                         */
39236   #define I3C_SLAVEIF0_MODEI2C_Min (0x0UL)           /*!< Min enumerator value of MODEI2C field.                               */
39237   #define I3C_SLAVEIF0_MODEI2C_Max (0x1UL)           /*!< Max enumerator value of MODEI2C field.                               */
39238   #define I3C_SLAVEIF0_MODEI2C_DISABLED (0x0UL)      /*!< (unspecified)                                                        */
39239   #define I3C_SLAVEIF0_MODEI2C_ENABLED (0x1UL)       /*!< (unspecified)                                                        */
39240 
39241 /* ACTMODE @Bits 1..2 : Slave activity mode for GETSTATUS CCC */
39242   #define I3C_SLAVEIF0_ACTMODE_Pos (1UL)             /*!< Position of ACTMODE field.                                           */
39243   #define I3C_SLAVEIF0_ACTMODE_Msk (0x3UL << I3C_SLAVEIF0_ACTMODE_Pos) /*!< Bit mask of ACTMODE field.                         */
39244 
39245 /* PENDINGINT @Bits 3..6 : Pending interrupt information for GETSTATUS CCC */
39246   #define I3C_SLAVEIF0_PENDINGINT_Pos (3UL)          /*!< Position of PENDINGINT field.                                        */
39247   #define I3C_SLAVEIF0_PENDINGINT_Msk (0xFUL << I3C_SLAVEIF0_PENDINGINT_Pos) /*!< Bit mask of PENDINGINT field.                */
39248 
39249 /* STATICADDREN @Bit 7 : Slave static address valid */
39250   #define I3C_SLAVEIF0_STATICADDREN_Pos (7UL)        /*!< Position of STATICADDREN field.                                      */
39251   #define I3C_SLAVEIF0_STATICADDREN_Msk (0x1UL << I3C_SLAVEIF0_STATICADDREN_Pos) /*!< Bit mask of STATICADDREN field.          */
39252   #define I3C_SLAVEIF0_STATICADDREN_Min (0x0UL)      /*!< Min enumerator value of STATICADDREN field.                          */
39253   #define I3C_SLAVEIF0_STATICADDREN_Max (0x1UL)      /*!< Max enumerator value of STATICADDREN field.                          */
39254   #define I3C_SLAVEIF0_STATICADDREN_DISABLED (0x0UL) /*!< (unspecified)                                                        */
39255   #define I3C_SLAVEIF0_STATICADDREN_ENABLED (0x1UL)  /*!< (unspecified)                                                        */
39256 
39257 /* STATICADDR @Bits 8..14 : Slave static address */
39258   #define I3C_SLAVEIF0_STATICADDR_Pos (8UL)          /*!< Position of STATICADDR field.                                        */
39259   #define I3C_SLAVEIF0_STATICADDR_Msk (0x7FUL << I3C_SLAVEIF0_STATICADDR_Pos) /*!< Bit mask of STATICADDR field.               */
39260 
39261 /* SLAVEMAXRDSPEED @Bits 15..17 : Slave maximum read data rate */
39262   #define I3C_SLAVEIF0_SLAVEMAXRDSPEED_Pos (15UL)    /*!< Position of SLAVEMAXRDSPEED field.                                   */
39263   #define I3C_SLAVEIF0_SLAVEMAXRDSPEED_Msk (0x7UL << I3C_SLAVEIF0_SLAVEMAXRDSPEED_Pos) /*!< Bit mask of SLAVEMAXRDSPEED field. */
39264 
39265 /* SLAVEMAXWRSPEED @Bits 18..20 : Slave maximum write write rate */
39266   #define I3C_SLAVEIF0_SLAVEMAXWRSPEED_Pos (18UL)    /*!< Position of SLAVEMAXWRSPEED field.                                   */
39267   #define I3C_SLAVEIF0_SLAVEMAXWRSPEED_Msk (0x7UL << I3C_SLAVEIF0_SLAVEMAXWRSPEED_Pos) /*!< Bit mask of SLAVEMAXWRSPEED field. */
39268 
39269 /* SLAVECLKDATATURNTIME @Bits 21..23 : Slave maximum clock data turnaround time */
39270   #define I3C_SLAVEIF0_SLAVECLKDATATURNTIME_Pos (21UL) /*!< Position of SLAVECLKDATATURNTIME field.                            */
39271   #define I3C_SLAVEIF0_SLAVECLKDATATURNTIME_Msk (0x7UL << I3C_SLAVEIF0_SLAVECLKDATATURNTIME_Pos) /*!< Bit mask of
39272                                                                             SLAVECLKDATATURNTIME field.*/
39273 
39274 /* SLAVEDCR @Bits 24..31 : Device Characteristic Register value */
39275   #define I3C_SLAVEIF0_SLAVEDCR_Pos (24UL)           /*!< Position of SLAVEDCR field.                                          */
39276   #define I3C_SLAVEIF0_SLAVEDCR_Msk (0xFFUL << I3C_SLAVEIF0_SLAVEDCR_Pos) /*!< Bit mask of SLAVEDCR field.                     */
39277 
39278 
39279 /* I3C_SLAVEIF1: I3C slave interface 1 */
39280   #define I3C_SLAVEIF1_ResetValue (0x00000000UL)     /*!< Reset value of SLAVEIF1 register.                                    */
39281 
39282 /* WAKEUP @Bit 0 : Slave wakeup signal */
39283   #define I3C_SLAVEIF1_WAKEUP_Pos (0UL)              /*!< Position of WAKEUP field.                                            */
39284   #define I3C_SLAVEIF1_WAKEUP_Msk (0x1UL << I3C_SLAVEIF1_WAKEUP_Pos) /*!< Bit mask of WAKEUP field.                            */
39285   #define I3C_SLAVEIF1_WAKEUP_Min (0x0UL)            /*!< Min enumerator value of WAKEUP field.                                */
39286   #define I3C_SLAVEIF1_WAKEUP_Max (0x1UL)            /*!< Max enumerator value of WAKEUP field.                                */
39287   #define I3C_SLAVEIF1_WAKEUP_DISABLED (0x0UL)       /*!< (unspecified)                                                        */
39288   #define I3C_SLAVEIF1_WAKEUP_ENABLED (0x1UL)        /*!< (unspecified)                                                        */
39289 
39290 
39291 /* I3C_SLAVEPID0: Slave Device Provisioned ID 0 */
39292   #define I3C_SLAVEPID0_ResetValue (0x00000000UL)    /*!< Reset value of SLAVEPID0 register.                                   */
39293 
39294 /* ADDMEANING @Bits 0..11 : Additional Meaning */
39295   #define I3C_SLAVEPID0_ADDMEANING_Pos (0UL)         /*!< Position of ADDMEANING field.                                        */
39296   #define I3C_SLAVEPID0_ADDMEANING_Msk (0xFFFUL << I3C_SLAVEPID0_ADDMEANING_Pos) /*!< Bit mask of ADDMEANING field.            */
39297 
39298 /* INSTANCEID @Bits 12..15 : Instance ID */
39299   #define I3C_SLAVEPID0_INSTANCEID_Pos (12UL)        /*!< Position of INSTANCEID field.                                        */
39300   #define I3C_SLAVEPID0_INSTANCEID_Msk (0xFUL << I3C_SLAVEPID0_INSTANCEID_Pos) /*!< Bit mask of INSTANCEID field.              */
39301 
39302 /* PARTID @Bits 16..31 : Part ID */
39303   #define I3C_SLAVEPID0_PARTID_Pos (16UL)            /*!< Position of PARTID field.                                            */
39304   #define I3C_SLAVEPID0_PARTID_Msk (0xFFFFUL << I3C_SLAVEPID0_PARTID_Pos) /*!< Bit mask of PARTID field.                       */
39305 
39306 
39307 /* I3C_SLAVEPID1: Slave Device Provisioned ID 1 */
39308   #define I3C_SLAVEPID1_ResetValue (0x00000000UL)    /*!< Reset value of SLAVEPID1 register.                                   */
39309 
39310 /* PROVID @Bit 0 : Provisional ID Type Selector */
39311   #define I3C_SLAVEPID1_PROVID_Pos (0UL)             /*!< Position of PROVID field.                                            */
39312   #define I3C_SLAVEPID1_PROVID_Msk (0x1UL << I3C_SLAVEPID1_PROVID_Pos) /*!< Bit mask of PROVID field.                          */
39313 
39314 /* MIPIMID @Bits 1..15 : MIPI Manufacturer ID */
39315   #define I3C_SLAVEPID1_MIPIMID_Pos (1UL)            /*!< Position of MIPIMID field.                                           */
39316   #define I3C_SLAVEPID1_MIPIMID_Msk (0x7FFFUL << I3C_SLAVEPID1_MIPIMID_Pos) /*!< Bit mask of MIPIMID field.                    */
39317 
39318 
39319 /* I3C_KEEPSDA: Enable or disable the SDA high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. */
39320   #define I3C_KEEPSDA_ResetValue (0x00000000UL)      /*!< Reset value of KEEPSDA register.                                     */
39321 
39322 /* ENABLE @Bit 0 : Enable or disable the SDA high-keeper */
39323   #define I3C_KEEPSDA_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
39324   #define I3C_KEEPSDA_ENABLE_Msk (0x1UL << I3C_KEEPSDA_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
39325   #define I3C_KEEPSDA_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
39326   #define I3C_KEEPSDA_ENABLE_Max (0x1UL)             /*!< Max enumerator value of ENABLE field.                                */
39327   #define I3C_KEEPSDA_ENABLE_Disabled (0x0UL)        /*!< High-keeper disabled.                                                */
39328   #define I3C_KEEPSDA_ENABLE_Enabled (0x1UL)         /*!< High-keeper enabled.                                                 */
39329 
39330 
39331 /* I3C_KEEPSCL: Enable or disable the SCL high-keeper used for Master-to-Slave and Slave-to-Master bus hand-off. */
39332   #define I3C_KEEPSCL_ResetValue (0x00000000UL)      /*!< Reset value of KEEPSCL register.                                     */
39333 
39334 /* ENABLE @Bit 0 : Enable or disable the SCL high-keeper */
39335   #define I3C_KEEPSCL_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
39336   #define I3C_KEEPSCL_ENABLE_Msk (0x1UL << I3C_KEEPSCL_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
39337   #define I3C_KEEPSCL_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
39338   #define I3C_KEEPSCL_ENABLE_Max (0x1UL)             /*!< Max enumerator value of ENABLE field.                                */
39339   #define I3C_KEEPSCL_ENABLE_Disabled (0x0UL)        /*!< High-keeper disabled.                                                */
39340   #define I3C_KEEPSCL_ENABLE_Enabled (0x1UL)         /*!< High-keeper enabled.                                                 */
39341 
39342 
39343 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
39344 
39345 /* =========================================================================================================================== */
39346 /* ================                                          I3CCORE                                          ================ */
39347 /* =========================================================================================================================== */
39348 
39349 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
39350 
39351 /* ============================================ Struct I3CCORE_CORE_DEVCHARTABLE ============================================= */
39352 /**
39353   * @brief DEVCHARTABLE [I3CCORE_CORE_DEVCHARTABLE] (unspecified)
39354   */
39355 typedef struct {
39356   __IOM uint32_t  LOC1;                              /*!< (@ 0x00000000) Device Characteristic Table Location-1 of Device [n]  */
39357   __IOM uint32_t  LOC2;                              /*!< (@ 0x00000004) Device Characteristic Table Location-2 of Device [n]  */
39358   __IOM uint32_t  LOC3;                              /*!< (@ 0x00000008) Device Characteristic Table Location-3 of Device [n]  */
39359   __IOM uint32_t  LOC4;                              /*!< (@ 0x0000000C) Device Characteristic Table Location-4 of Device [n]  */
39360 } NRF_I3CCORE_CORE_DEVCHARTABLE_Type;                /*!< Size = 16 (0x010)                                                    */
39361   #define I3CCORE_CORE_DEVCHARTABLE_MaxCount (10UL)  /*!< Size of DEVCHARTABLE[10] array.                                      */
39362   #define I3CCORE_CORE_DEVCHARTABLE_MaxIndex (9UL)   /*!< Max index of DEVCHARTABLE[10] array.                                 */
39363   #define I3CCORE_CORE_DEVCHARTABLE_MinIndex (0UL)   /*!< Min index of DEVCHARTABLE[10] array.                                 */
39364 
39365 /* I3CCORE_CORE_DEVCHARTABLE_LOC1: Device Characteristic Table Location-1 of Device [n] */
39366   #define I3CCORE_CORE_DEVCHARTABLE_LOC1_ResetValue (0x00000000UL) /*!< Reset value of LOC1 register.                          */
39367 
39368 /* LSBPROVISIONALID @Bits 0..31 : The LSB 32-bit value of Provisional-ID */
39369   #define I3CCORE_CORE_DEVCHARTABLE_LOC1_LSBPROVISIONALID_Pos (0UL) /*!< Position of LSBPROVISIONALID field.                   */
39370   #define I3CCORE_CORE_DEVCHARTABLE_LOC1_LSBPROVISIONALID_Msk (0xFFFFFFFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC1_LSBPROVISIONALID_Pos)
39371                                                                             /*!< Bit mask of LSBPROVISIONALID field.*/
39372 
39373 
39374 /* I3CCORE_CORE_DEVCHARTABLE_LOC2: Device Characteristic Table Location-2 of Device [n] */
39375   #define I3CCORE_CORE_DEVCHARTABLE_LOC2_ResetValue (0x00000000UL) /*!< Reset value of LOC2 register.                          */
39376 
39377 /* MSBPROVISIONALID @Bits 0..15 : The MSB 16-bit value of Provisional-ID */
39378   #define I3CCORE_CORE_DEVCHARTABLE_LOC2_MSBPROVISIONALID_Pos (0UL) /*!< Position of MSBPROVISIONALID field.                   */
39379   #define I3CCORE_CORE_DEVCHARTABLE_LOC2_MSBPROVISIONALID_Msk (0xFFFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC2_MSBPROVISIONALID_Pos)
39380                                                                             /*!< Bit mask of MSBPROVISIONALID field.*/
39381 
39382 
39383 /* I3CCORE_CORE_DEVCHARTABLE_LOC3: Device Characteristic Table Location-3 of Device [n] */
39384   #define I3CCORE_CORE_DEVCHARTABLE_LOC3_ResetValue (0x00000000UL) /*!< Reset value of LOC3 register.                          */
39385 
39386 /* DCR @Bits 0..7 : Device Characteristic Value */
39387   #define I3CCORE_CORE_DEVCHARTABLE_LOC3_DCR_Pos (0UL) /*!< Position of DCR field.                                             */
39388   #define I3CCORE_CORE_DEVCHARTABLE_LOC3_DCR_Msk (0xFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC3_DCR_Pos) /*!< Bit mask of DCR field.*/
39389 
39390 /* BCR @Bits 8..15 : Bus Characteristic Value */
39391   #define I3CCORE_CORE_DEVCHARTABLE_LOC3_BCR_Pos (8UL) /*!< Position of BCR field.                                             */
39392   #define I3CCORE_CORE_DEVCHARTABLE_LOC3_BCR_Msk (0xFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC3_BCR_Pos) /*!< Bit mask of BCR field.*/
39393 
39394 
39395 /* I3CCORE_CORE_DEVCHARTABLE_LOC4: Device Characteristic Table Location-4 of Device [n] */
39396   #define I3CCORE_CORE_DEVCHARTABLE_LOC4_ResetValue (0x00000000UL) /*!< Reset value of LOC4 register.                          */
39397 
39398 /* DEVDYNAMICADDR @Bits 0..7 : Device Dynamic Address assigned. */
39399   #define I3CCORE_CORE_DEVCHARTABLE_LOC4_DEVDYNAMICADDR_Pos (0UL) /*!< Position of DEVDYNAMICADDR field.                       */
39400   #define I3CCORE_CORE_DEVCHARTABLE_LOC4_DEVDYNAMICADDR_Msk (0xFFUL << I3CCORE_CORE_DEVCHARTABLE_LOC4_DEVDYNAMICADDR_Pos) /*!<
39401                                                                             Bit mask of DEVDYNAMICADDR field.*/
39402 
39403 
39404 
39405 /* =================================================== Struct I3CCORE_CORE =================================================== */
39406 /**
39407   * @brief CORE [I3CCORE_CORE] (unspecified)
39408   */
39409 typedef struct {
39410   __IOM uint32_t  DEVICECTRL;                        /*!< (@ 0x00000000) DWC_mipi_i3c control Register                         */
39411   __IOM uint32_t  DEVICEADDR;                        /*!< (@ 0x00000004) In the master mode of operation this Register is used
39412                                                                          to program the Device Dynamic Addresses and its
39413                                                                          respective valid bit.*/
39414   __IOM uint32_t  HWCAPABILITY;                      /*!< (@ 0x00000008) Hardware Capability register                          */
39415   __IOM uint32_t  COMMANDQUEUEPORT;                  /*!< (@ 0x0000000C) Command Queue Port.                                   */
39416   __IOM uint32_t  RESPONSEQUEUEPORT;                 /*!< (@ 0x00000010) Response Queue Port                                   */
39417   #if defined(_GNUC_)
39418     #pragma GCC diagnostic push
39419     #pragma GCC diagnostic ignored "-Wpedantic"
39420   #endif
39421   union {
39422     __IOM uint32_t RXDATAPORT;                       /*!< (@ 0x00000014) Receive Data Port Register                            */
39423     __IOM uint32_t TXDATAPORT;                       /*!< (@ 0x00000014) Transmit Data Port Register                           */
39424   };
39425   #if defined(_GNUC_)
39426     #pragma GCC diagnostic pop
39427   #endif
39428   #if defined(_GNUC_)
39429     #pragma GCC diagnostic push
39430     #pragma GCC diagnostic ignored "-Wpedantic"
39431   #endif
39432   union {
39433     __IOM uint32_t IBIQUEUEDATA;                     /*!< (@ 0x00000018) In-Band Interrupt Queue Data Register                 */
39434     __IOM uint32_t IBIQUEUESTATUS;                   /*!< (@ 0x00000018) In-Band Interrupt Queue Status Register               */
39435   };
39436   #if defined(_GNUC_)
39437     #pragma GCC diagnostic pop
39438   #endif
39439   __IOM uint32_t  QUEUETHLDCTRL;                     /*!< (@ 0x0000001C) Queue Threshold Control Register                      */
39440   __IOM uint32_t  DATABUFFERTHLDCTRL;                /*!< (@ 0x00000020) Data Buffer Threshold Control Register                */
39441   __IOM uint32_t  IBIQUEUECTRL;                      /*!< (@ 0x00000024) This Register is used to control whether or not to
39442                                                                          intimate the application if an IBI request is rejected
39443                                                                          (Nacked).*/
39444   __IM  uint32_t  RESERVED;
39445   __IOM uint32_t  IBIMRREQREJECT;                    /*!< (@ 0x0000002C) IBI Master Request Rejection Control Register.        */
39446   __IOM uint32_t  IBISIRREQREJECT;                   /*!< (@ 0x00000030) IBI SIR Request Rejection Control                     */
39447   __IOM uint32_t  RESETCTRL;                         /*!< (@ 0x00000034) This Register is used for general software reset and
39448                                                                          for individual buffer reset.*/
39449   __IOM uint32_t  SLVEVENTSTATUS;                    /*!< (@ 0x00000038) This register indicates the status/values of some
39450                                                                          events/controls that are relavant to slave mode of
39451                                                                          operation.*/
39452   __IOM uint32_t  INTRSTATUS;                        /*!< (@ 0x0000003C) Interrupt Status Register                             */
39453   __IOM uint32_t  INTRSTATUSEN;                      /*!< (@ 0x00000040) Interrupt Status Enable Register.                     */
39454   __IOM uint32_t  INTRSIGNALEN;                      /*!< (@ 0x00000044) Interrupt Signal Enable Register                      */
39455   __IOM uint32_t  INTRFORCE;                         /*!< (@ 0x00000048) Interrupt Force Enable Register                       */
39456   __IOM uint32_t  QUEUESTATUSLEVEL;                  /*!< (@ 0x0000004C) Queue Status Level Register.                          */
39457   __IOM uint32_t  DATABUFFERSTATUSLEVEL;             /*!< (@ 0x00000050) Data Buffer Status Level Register.                    */
39458   #if defined(_GNUC_)
39459     #pragma GCC diagnostic push
39460     #pragma GCC diagnostic ignored "-Wpedantic"
39461   #endif
39462   union {
39463     __IOM uint32_t PRESENTSTATEM;                    /*!< (@ 0x00000054) The user can get status of the DWC_mipi_i3c Controller
39464                                                                          from this 32-bit read only register (Master).*/
39465     __IOM uint32_t PRESENTSTATES;                    /*!< (@ 0x00000054) The user can get status of the DWC_mipi_i3c Controller
39466                                                                          from this 32-bit read only register (Slave).*/
39467   };
39468   #if defined(_GNUC_)
39469     #pragma GCC diagnostic pop
39470   #endif
39471   __IOM uint32_t  CCCDEVICESTATUS;                   /*!< (@ 0x00000058) Device Operating Status Register.                     */
39472   __IOM uint32_t  DEVICEADDRTABLEPOINTER;            /*!< (@ 0x0000005C) Pointer for Device Address Table                      */
39473   __IOM uint32_t  DEVCHARTABLEPOINTER;               /*!< (@ 0x00000060) Pointer for Device Characteristics Table              */
39474   __IM  uint32_t  RESERVED1[2];
39475   __IOM uint32_t  VENDORSPECIFICREGPOINTER;          /*!< (@ 0x0000006C) Pointer for Vendor Specific Registers.                */
39476   __IOM uint32_t  SLVMIPIIDVALUE;                    /*!< (@ 0x00000070) I3C MIPI Manufacturer ID Register.                    */
39477   __IOM uint32_t  SLVPIDVALUE;                       /*!< (@ 0x00000074) I3C Normal Provisional ID Register.                   */
39478   __IOM uint32_t  SLVCHARCTRL;                       /*!< (@ 0x00000078) I3C Slave Characteristic Register.                    */
39479   __IOM uint32_t  SLVMAXLEN;                         /*!< (@ 0x0000007C) I3C Max Write/Read Length Register.                   */
39480   __IOM uint32_t  MAXREADTURNAROUND;                 /*!< (@ 0x00000080) MXDS Maximum Read Turnaround Time.                    */
39481   __IOM uint32_t  MAXDATASPEED;                      /*!< (@ 0x00000084) The values in this register are returned by the slave
39482                                                                          as GETACCMST CCC data.*/
39483   __IM  uint32_t  RESERVED2;
39484   __IOM uint32_t  SLVINTRREQ;                        /*!< (@ 0x0000008C) This register is used in slave mode of operation.     */
39485   __IOM uint32_t  SLVTSXSYMBLTIMING;                 /*!< (@ 0x00000090) TSP/TSL Symbol Timing Register                        */
39486   __IM  uint32_t  RESERVED3[7];
39487   __IOM uint32_t  DEVICECTRLEXTENDED;                /*!< (@ 0x000000B0) Device Control Extended register.                     */
39488   __IOM uint32_t  SCLI3CODTIMING;                    /*!< (@ 0x000000B4) SCL I3C Open Drain Timing Register                    */
39489   __IOM uint32_t  SCLI3CPPTIMING;                    /*!< (@ 0x000000B8) SCL I3C Push Pull Timing Register                     */
39490   __IOM uint32_t  SCLI2CFMTIMING;                    /*!< (@ 0x000000BC) SCL I2C Fast Mode Timing Register                     */
39491   __IOM uint32_t  SCLI2CFMPTIMING;                   /*!< (@ 0x000000C0) SCL I2C Fast Mode Plus Timing Register                */
39492   __IM  uint32_t  RESERVED4;
39493   __IOM uint32_t  SCLEXTLCNTTIMING;                  /*!< (@ 0x000000C8) SCL Extended Low Count Timing Register.               */
39494   __IOM uint32_t  SCLEXTTERMNLCNTTIMING;             /*!< (@ 0x000000CC) SCL Termination Bit Low Count Timing Register         */
39495   __IOM uint32_t  SDAHOLDSWITCHDLYTIMING;            /*!< (@ 0x000000D0) SDA Hold and Mode Switch Delay Timing Register        */
39496   __IOM uint32_t  BUSFREEAVAILTIMING;                /*!< (@ 0x000000D4) Bus Free and Available Timing Register                */
39497   __IOM uint32_t  BUSIDLETIMING;                     /*!< (@ 0x000000D8) Bus Idle Timing Register                              */
39498   __IOM uint32_t  SCLLOWMSTEXTTIMEOUT;               /*!< (@ 0x000000DC) The SCL Low Master Extended Timeout register is used to
39499                                                                          define the duration of the SCL Low Bus Reset Pattern.*/
39500   __IOM uint32_t  I3CVERID;                          /*!< (@ 0x000000E0) This register reflects the current release number of
39501                                                                          DWC_mipi_i3c*/
39502   __IOM uint32_t  I3CVERTYPE;                        /*!< (@ 0x000000E4) This register reflects the current release type of
39503                                                                          DWC_mipi_i3c.*/
39504   __IOM uint32_t  QUEUESIZECAPABILITY;               /*!< (@ 0x000000E8) This register reflects the configured size of the Data
39505                                                                          Buffer and Queues in DWC_mipi_i3c.*/
39506   __IM  uint32_t  RESERVED5[69];
39507   #if defined(_GNUC_)
39508     #pragma GCC diagnostic push
39509     #pragma GCC diagnostic ignored "-Wpedantic"
39510   #endif
39511   union {
39512     __IOM NRF_I3CCORE_CORE_DEVCHARTABLE_Type DEVCHARTABLE[10]; /*!< (@ 0x00000200) (unspecified)                               */
39513     __IOM uint32_t SECDEVCHARTABLE[32];              /*!< (@ 0x00000200) Secondary Master Device Characteristic Table Location
39514                                                                          of Device [n]*/
39515     __IM uint32_t RESERVED6[40];
39516   };
39517   #if defined(_GNUC_)
39518     #pragma GCC diagnostic pop
39519   #endif
39520   __IM  uint32_t  RESERVED7[8];
39521   __IOM uint32_t  DEVADDRTABLELOC[10];               /*!< (@ 0x000002C0) Device Address Table of Device [n]                    */
39522 } NRF_I3CCORE_CORE_Type;                             /*!< Size = 744 (0x2E8)                                                   */
39523 
39524 /* I3CCORE_CORE_DEVICECTRL: DWC_mipi_i3c control Register */
39525   #define I3CCORE_CORE_DEVICECTRL_ResetValue (0x00000000UL) /*!< Reset value of DEVICECTRL register.                           */
39526 
39527 /* IBAINCLUDE @Bit 0 : I3C Broadcast Address include */
39528   #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Pos (0UL) /*!< Position of IBAINCLUDE field.                                      */
39529   #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Pos) /*!< Bit mask of IBAINCLUDE
39530                                                                             field.*/
39531   #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Min (0x0UL) /*!< Min enumerator value of IBAINCLUDE field.                        */
39532   #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_Max (0x1UL) /*!< Max enumerator value of IBAINCLUDE field.                        */
39533   #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_NOT_INCLUDED (0x0UL) /*!< (unspecified)                                           */
39534   #define I3CCORE_CORE_DEVICECTRL_IBAINCLUDE_INCLUDED (0x1UL) /*!< (unspecified)                                               */
39535 
39536 /* I2CSLAVEPRESENT @Bit 7 : I2C Slave Present */
39537   #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Pos (7UL) /*!< Position of I2CSLAVEPRESENT field.                            */
39538   #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Pos) /*!< Bit mask of
39539                                                                             I2CSLAVEPRESENT field.*/
39540   #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Min (0x0UL) /*!< Min enumerator value of I2CSLAVEPRESENT field.              */
39541   #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_Max (0x1UL) /*!< Max enumerator value of I2CSLAVEPRESENT field.              */
39542   #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_DISABLED (0x0UL) /*!< (unspecified)                                          */
39543   #define I3CCORE_CORE_DEVICECTRL_I2CSLAVEPRESENT_ENABLED (0x1UL) /*!< (unspecified)                                           */
39544 
39545 /* HOTJOINCTRL @Bit 8 : Hot-Join ACK/NACK Control */
39546   #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Pos (8UL) /*!< Position of HOTJOINCTRL field.                                    */
39547   #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Pos) /*!< Bit mask of
39548                                                                             HOTJOINCTRL field.*/
39549   #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Min (0x0UL) /*!< Min enumerator value of HOTJOINCTRL field.                      */
39550   #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_Max (0x1UL) /*!< Max enumerator value of HOTJOINCTRL field.                      */
39551   #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_DISABLED (0x0UL) /*!< (unspecified)                                              */
39552   #define I3CCORE_CORE_DEVICECTRL_HOTJOINCTRL_ENABLED (0x1UL) /*!< (unspecified)                                               */
39553 
39554 /* IDLECNTMULTPLIER @Bits 24..25 : Idle Count Multiplier */
39555   #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Pos (24UL) /*!< Position of IDLECNTMULTPLIER field.                         */
39556   #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Msk (0x3UL << I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Pos) /*!< Bit mask of
39557                                                                             IDLECNTMULTPLIER field.*/
39558   #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Min (0x0UL) /*!< Min enumerator value of IDLECNTMULTPLIER field.            */
39559   #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_Max (0x3UL) /*!< Max enumerator value of IDLECNTMULTPLIER field.            */
39560   #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_MultiplyBy1 (0x0UL) /*!< (unspecified)                                      */
39561   #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_MultiplyBy2 (0x1UL) /*!< (unspecified)                                      */
39562   #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_MultiplyBy4 (0x2UL) /*!< (unspecified)                                      */
39563   #define I3CCORE_CORE_DEVICECTRL_IDLECNTMULTPLIER_MultiplyBy8 (0x3UL) /*!< (unspecified)                                      */
39564 
39565 /* ADAPTIVEI2CI3C @Bit 27 : This field is used in Slave mode of operation. */
39566   #define I3CCORE_CORE_DEVICECTRL_ADAPTIVEI2CI3C_Pos (27UL) /*!< Position of ADAPTIVEI2CI3C field.                             */
39567   #define I3CCORE_CORE_DEVICECTRL_ADAPTIVEI2CI3C_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_ADAPTIVEI2CI3C_Pos) /*!< Bit mask of
39568                                                                             ADAPTIVEI2CI3C field.*/
39569 
39570 /* DMAENABLE @Bit 28 : DMA Handshake Interface Enable */
39571   #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_Pos (28UL) /*!< Position of DMAENABLE field.                                       */
39572   #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_DMAENABLE_Pos) /*!< Bit mask of DMAENABLE
39573                                                                             field.*/
39574   #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_Min (0x0UL) /*!< Min enumerator value of DMAENABLE field.                          */
39575   #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_Max (0x1UL) /*!< Max enumerator value of DMAENABLE field.                          */
39576   #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_DISABLE (0x0UL) /*!< The DMA handshake control has no significance.                */
39577   #define I3CCORE_CORE_DEVICECTRL_DMAENABLE_ENABLE (0x1UL) /*!< Enables the DMA handshake control to interact with external
39578                                                                 DMA.*/
39579 
39580 /* ABORT @Bit 29 : DWC_mipi_i3c Abort */
39581   #define I3CCORE_CORE_DEVICECTRL_ABORT_Pos (29UL)   /*!< Position of ABORT field.                                             */
39582   #define I3CCORE_CORE_DEVICECTRL_ABORT_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_ABORT_Pos) /*!< Bit mask of ABORT field.         */
39583 
39584 /* RESUME @Bit 30 : DWC_mipi_i3c Resume */
39585   #define I3CCORE_CORE_DEVICECTRL_RESUME_Pos (30UL)  /*!< Position of RESUME field.                                            */
39586   #define I3CCORE_CORE_DEVICECTRL_RESUME_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_RESUME_Pos) /*!< Bit mask of RESUME field.      */
39587 
39588 /* ENABLE @Bit 31 : Controls whether or not DWC_mipi_i3c is enabled. */
39589   #define I3CCORE_CORE_DEVICECTRL_ENABLE_Pos (31UL)  /*!< Position of ENABLE field.                                            */
39590   #define I3CCORE_CORE_DEVICECTRL_ENABLE_Msk (0x1UL << I3CCORE_CORE_DEVICECTRL_ENABLE_Pos) /*!< Bit mask of ENABLE field.      */
39591   #define I3CCORE_CORE_DEVICECTRL_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                                */
39592   #define I3CCORE_CORE_DEVICECTRL_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                                */
39593   #define I3CCORE_CORE_DEVICECTRL_ENABLE_DISABLE (0x0UL) /*!< Disables the DWC_mipi_i3c controller                             */
39594   #define I3CCORE_CORE_DEVICECTRL_ENABLE_ENABLE (0x1UL) /*!< Enables the DWC_mipi_i3c controller.                              */
39595 
39596 
39597 /* I3CCORE_CORE_DEVICEADDR: In the master mode of operation this Register is used to program the Device Dynamic Addresses and
39598                              its respective valid bit. */
39599 
39600   #define I3CCORE_CORE_DEVICEADDR_ResetValue (0x80000000UL) /*!< Reset value of DEVICEADDR register.                           */
39601 
39602 /* STATICADDR @Bits 0..6 : Device Static Address. */
39603   #define I3CCORE_CORE_DEVICEADDR_STATICADDR_Pos (0UL) /*!< Position of STATICADDR field.                                      */
39604   #define I3CCORE_CORE_DEVICEADDR_STATICADDR_Msk (0x7FUL << I3CCORE_CORE_DEVICEADDR_STATICADDR_Pos) /*!< Bit mask of STATICADDR
39605                                                                             field.*/
39606 
39607 /* STATICADDRVALID @Bit 15 : Static Address Valid. */
39608   #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Pos (15UL) /*!< Position of STATICADDRVALID field.                           */
39609   #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Msk (0x1UL << I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Pos) /*!< Bit mask of
39610                                                                             STATICADDRVALID field.*/
39611   #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Min (0x0UL) /*!< Min enumerator value of STATICADDRVALID field.              */
39612   #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_Max (0x1UL) /*!< Max enumerator value of STATICADDRVALID field.              */
39613   #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_INVALID (0x0UL) /*!< (unspecified)                                           */
39614   #define I3CCORE_CORE_DEVICEADDR_STATICADDRVALID_VALID (0x1UL) /*!< (unspecified)                                             */
39615 
39616 /* DYNAMICADDR @Bits 16..22 : Device Dynamic Address. */
39617   #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDR_Pos (16UL) /*!< Position of DYNAMICADDR field.                                   */
39618   #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDR_Msk (0x7FUL << I3CCORE_CORE_DEVICEADDR_DYNAMICADDR_Pos) /*!< Bit mask of
39619                                                                             DYNAMICADDR field.*/
39620 
39621 /* DYNAMICADDRVALID @Bit 31 : Dynamic Address Valid */
39622   #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Pos (31UL) /*!< Position of DYNAMICADDRVALID field.                         */
39623   #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Msk (0x1UL << I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Pos) /*!< Bit mask of
39624                                                                             DYNAMICADDRVALID field.*/
39625   #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Min (0x0UL) /*!< Min enumerator value of DYNAMICADDRVALID field.            */
39626   #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_Max (0x1UL) /*!< Max enumerator value of DYNAMICADDRVALID field.            */
39627   #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_INVALID (0x0UL) /*!< (unspecified)                                          */
39628   #define I3CCORE_CORE_DEVICEADDR_DYNAMICADDRVALID_VALID (0x1UL) /*!< (unspecified)                                            */
39629 
39630 
39631 /* I3CCORE_CORE_HWCAPABILITY: Hardware Capability register */
39632   #define I3CCORE_CORE_HWCAPABILITY_ResetValue (0x000E187BUL) /*!< Reset value of HWCAPABILITY register.                       */
39633 
39634 /* DEVICEROLECONFIG @Bits 0..2 : Reflects the IC_DEVICE_ROLE Configurable Parameter. */
39635   #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Pos (0UL) /*!< Position of DEVICEROLECONFIG field.                        */
39636   #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Msk (0x7UL << I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Pos) /*!< Bit mask
39637                                                                             of DEVICEROLECONFIG field.*/
39638   #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Min (0x1UL) /*!< Min enumerator value of DEVICEROLECONFIG field.          */
39639   #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_Max (0x4UL) /*!< Max enumerator value of DEVICEROLECONFIG field.          */
39640   #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_MASTER (0x1UL) /*!< Master Only                                           */
39641   #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_PMASTERSLAVE (0x2UL) /*!< Programmable Master-Slave                       */
39642   #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_SECONDARYMASTER (0x3UL) /*!< Secondary Master                             */
39643   #define I3CCORE_CORE_HWCAPABILITY_DEVICEROLECONFIG_SLAVE (0x4UL) /*!< Slave Only                                             */
39644 
39645 /* HDRDDREN @Bit 3 : Reflects the IC_SPEED_HDR_DDR Configurable Parameter. */
39646   #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Pos (3UL) /*!< Position of HDRDDREN field.                                        */
39647   #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Pos) /*!< Bit mask of HDRDDREN
39648                                                                             field.*/
39649   #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Min (0x0UL) /*!< Min enumerator value of HDRDDREN field.                          */
39650   #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_Max (0x1UL) /*!< Max enumerator value of HDRDDREN field.                          */
39651   #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_NOTSUPPORTED (0x0UL) /*!< HDR-DDR not supported                                   */
39652   #define I3CCORE_CORE_HWCAPABILITY_HDRDDREN_SUPPORTED (0x1UL) /*!< HDR-DDR supported                                          */
39653 
39654 /* HDRTSEN @Bit 4 : Reflects the IC_SPEED_HDR_TS Configurable Parameter. */
39655   #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Pos (4UL) /*!< Position of HDRTSEN field.                                          */
39656   #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Pos) /*!< Bit mask of HDRTSEN
39657                                                                             field.*/
39658   #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Min (0x0UL) /*!< Min enumerator value of HDRTSEN field.                            */
39659   #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_Max (0x1UL) /*!< Max enumerator value of HDRTSEN field.                            */
39660   #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_NOTSUPPORTED (0x0UL) /*!< HDR-TS not supported                                     */
39661   #define I3CCORE_CORE_HWCAPABILITY_HDRTSEN_SUPPORTED (0x1UL) /*!< HDR-TS supported                                            */
39662 
39663 /* CLOCKPERIOD @Bits 5..10 : Reflects the IC_CLK_PERIOD Configurable Parameter */
39664   #define I3CCORE_CORE_HWCAPABILITY_CLOCKPERIOD_Pos (5UL) /*!< Position of CLOCKPERIOD field.                                  */
39665   #define I3CCORE_CORE_HWCAPABILITY_CLOCKPERIOD_Msk (0x3FUL << I3CCORE_CORE_HWCAPABILITY_CLOCKPERIOD_Pos) /*!< Bit mask of
39666                                                                             CLOCKPERIOD field.*/
39667 
39668 /* HDRTXCLOCKPERIOD @Bits 11..16 : Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter. */
39669   #define I3CCORE_CORE_HWCAPABILITY_HDRTXCLOCKPERIOD_Pos (11UL) /*!< Position of HDRTXCLOCKPERIOD field.                       */
39670   #define I3CCORE_CORE_HWCAPABILITY_HDRTXCLOCKPERIOD_Msk (0x3FUL << I3CCORE_CORE_HWCAPABILITY_HDRTXCLOCKPERIOD_Pos) /*!< Bit
39671                                                                             mask of HDRTXCLOCKPERIOD field.*/
39672 
39673 /* DMAEN @Bit 17 : Reflects the IC_HAS_DMA Configurable Parameter. */
39674   #define I3CCORE_CORE_HWCAPABILITY_DMAEN_Pos (17UL) /*!< Position of DMAEN field.                                             */
39675   #define I3CCORE_CORE_HWCAPABILITY_DMAEN_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_DMAEN_Pos) /*!< Bit mask of DMAEN field.     */
39676 
39677 /* SLVHJCAP @Bit 18 : Reflects the IC_SLV_HJ Configurable Parameter. */
39678   #define I3CCORE_CORE_HWCAPABILITY_SLVHJCAP_Pos (18UL) /*!< Position of SLVHJCAP field.                                       */
39679   #define I3CCORE_CORE_HWCAPABILITY_SLVHJCAP_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_SLVHJCAP_Pos) /*!< Bit mask of SLVHJCAP
39680                                                                             field.*/
39681 
39682 /* SLVIBICAP @Bit 19 : Reflects the IC_SLV_IBI Configurable Parameter. */
39683   #define I3CCORE_CORE_HWCAPABILITY_SLVIBICAP_Pos (19UL) /*!< Position of SLVIBICAP field.                                     */
39684   #define I3CCORE_CORE_HWCAPABILITY_SLVIBICAP_Msk (0x1UL << I3CCORE_CORE_HWCAPABILITY_SLVIBICAP_Pos) /*!< Bit mask of SLVIBICAP
39685                                                                             field.*/
39686 
39687 
39688 /* I3CCORE_CORE_COMMANDQUEUEPORT: Command Queue Port. */
39689   #define I3CCORE_CORE_COMMANDQUEUEPORT_ResetValue (0x00000000UL) /*!< Reset value of COMMANDQUEUEPORT register.               */
39690 
39691 /* COMMAND @Bits 0..31 : 32 bit command */
39692   #define I3CCORE_CORE_COMMANDQUEUEPORT_COMMAND_Pos (0UL) /*!< Position of COMMAND field.                                      */
39693   #define I3CCORE_CORE_COMMANDQUEUEPORT_COMMAND_Msk (0xFFFFFFFFUL << I3CCORE_CORE_COMMANDQUEUEPORT_COMMAND_Pos) /*!< Bit mask of
39694                                                                             COMMAND field.*/
39695 
39696 
39697 /* I3CCORE_CORE_RESPONSEQUEUEPORT: Response Queue Port */
39698   #define I3CCORE_CORE_RESPONSEQUEUEPORT_ResetValue (0x00000000UL) /*!< Reset value of RESPONSEQUEUEPORT register.             */
39699 
39700 /* RESPONSE @Bits 0..31 : 32 bit Response */
39701   #define I3CCORE_CORE_RESPONSEQUEUEPORT_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field.                                   */
39702   #define I3CCORE_CORE_RESPONSEQUEUEPORT_RESPONSE_Msk (0xFFFFFFFFUL << I3CCORE_CORE_RESPONSEQUEUEPORT_RESPONSE_Pos) /*!< Bit
39703                                                                             mask of RESPONSE field.*/
39704 
39705 
39706 /* I3CCORE_CORE_RXDATAPORT: Receive Data Port Register */
39707   #define I3CCORE_CORE_RXDATAPORT_ResetValue (0x00000000UL) /*!< Reset value of RXDATAPORT register.                           */
39708 
39709 /* RXDATAPORT @Bits 0..31 : Receive Data Port. */
39710   #define I3CCORE_CORE_RXDATAPORT_RXDATAPORT_Pos (0UL) /*!< Position of RXDATAPORT field.                                      */
39711   #define I3CCORE_CORE_RXDATAPORT_RXDATAPORT_Msk (0xFFFFFFFFUL << I3CCORE_CORE_RXDATAPORT_RXDATAPORT_Pos) /*!< Bit mask of
39712                                                                             RXDATAPORT field.*/
39713 
39714 
39715 /* I3CCORE_CORE_TXDATAPORT: Transmit Data Port Register */
39716   #define I3CCORE_CORE_TXDATAPORT_ResetValue (0x00000000UL) /*!< Reset value of TXDATAPORT register.                           */
39717 
39718 /* TXDATAPORT @Bits 0..31 : Transmit Data Port */
39719   #define I3CCORE_CORE_TXDATAPORT_TXDATAPORT_Pos (0UL) /*!< Position of TXDATAPORT field.                                      */
39720   #define I3CCORE_CORE_TXDATAPORT_TXDATAPORT_Msk (0xFFFFFFFFUL << I3CCORE_CORE_TXDATAPORT_TXDATAPORT_Pos) /*!< Bit mask of
39721                                                                             TXDATAPORT field.*/
39722 
39723 
39724 /* I3CCORE_CORE_IBIQUEUEDATA: In-Band Interrupt Queue Data Register */
39725   #define I3CCORE_CORE_IBIQUEUEDATA_ResetValue (0x00000000UL) /*!< Reset value of IBIQUEUEDATA register.                       */
39726 
39727 /* IBIDATA @Bits 0..31 : In-Band Interrupt Data */
39728   #define I3CCORE_CORE_IBIQUEUEDATA_IBIDATA_Pos (0UL) /*!< Position of IBIDATA field.                                          */
39729   #define I3CCORE_CORE_IBIQUEUEDATA_IBIDATA_Msk (0xFFFFFFFFUL << I3CCORE_CORE_IBIQUEUEDATA_IBIDATA_Pos) /*!< Bit mask of IBIDATA
39730                                                                             field.*/
39731 
39732 
39733 /* I3CCORE_CORE_IBIQUEUESTATUS: In-Band Interrupt Queue Status Register */
39734   #define I3CCORE_CORE_IBIQUEUESTATUS_ResetValue (0x00000000UL) /*!< Reset value of IBIQUEUESTATUS register.                   */
39735 
39736 /* DATALENGTH @Bits 0..7 : In-Band Interrupt data length. */
39737   #define I3CCORE_CORE_IBIQUEUESTATUS_DATALENGTH_Pos (0UL) /*!< Position of DATALENGTH field.                                  */
39738   #define I3CCORE_CORE_IBIQUEUESTATUS_DATALENGTH_Msk (0xFFUL << I3CCORE_CORE_IBIQUEUESTATUS_DATALENGTH_Pos) /*!< Bit mask of
39739                                                                             DATALENGTH field.*/
39740 
39741 /* IBIID @Bits 8..15 : IBI Identifier. */
39742   #define I3CCORE_CORE_IBIQUEUESTATUS_IBIID_Pos (8UL) /*!< Position of IBIID field.                                            */
39743   #define I3CCORE_CORE_IBIQUEUESTATUS_IBIID_Msk (0xFFUL << I3CCORE_CORE_IBIQUEUESTATUS_IBIID_Pos) /*!< Bit mask of IBIID field.*/
39744 
39745 /* IBIACK @Bit 31 : The acknowledge bit of the IBI Received Status (IBISTS) bitfield. */
39746   #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Pos (31UL) /*!< Position of IBIACK field.                                         */
39747   #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Msk (0x1UL << I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Pos) /*!< Bit mask of IBIACK
39748                                                                             field.*/
39749   #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Min (0x0UL) /*!< Min enumerator value of IBIACK field.                            */
39750   #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_Max (0x1UL) /*!< Max enumerator value of IBIACK field.                            */
39751   #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_ACK (0x0UL) /*!< Responded with ACK                                               */
39752   #define I3CCORE_CORE_IBIQUEUESTATUS_IBIACK_NACK (0x1UL) /*!< Responded with NACK                                             */
39753 
39754 
39755 /* I3CCORE_CORE_QUEUETHLDCTRL: Queue Threshold Control Register */
39756   #define I3CCORE_CORE_QUEUETHLDCTRL_ResetValue (0x01000101UL) /*!< Reset value of QUEUETHLDCTRL register.                     */
39757 
39758 /* CMDEMPTYBUFTHLD @Bits 0..7 : Command Buffer Empty Threshold Value. */
39759   #define I3CCORE_CORE_QUEUETHLDCTRL_CMDEMPTYBUFTHLD_Pos (0UL) /*!< Position of CMDEMPTYBUFTHLD field.                         */
39760   #define I3CCORE_CORE_QUEUETHLDCTRL_CMDEMPTYBUFTHLD_Msk (0xFFUL << I3CCORE_CORE_QUEUETHLDCTRL_CMDEMPTYBUFTHLD_Pos) /*!< Bit
39761                                                                             mask of CMDEMPTYBUFTHLD field.*/
39762 
39763 /* RESPBUFTHLD @Bits 8..15 : Response Buffer Threshold Value. */
39764   #define I3CCORE_CORE_QUEUETHLDCTRL_RESPBUFTHLD_Pos (8UL) /*!< Position of RESPBUFTHLD field.                                 */
39765   #define I3CCORE_CORE_QUEUETHLDCTRL_RESPBUFTHLD_Msk (0xFFUL << I3CCORE_CORE_QUEUETHLDCTRL_RESPBUFTHLD_Pos) /*!< Bit mask of
39766                                                                             RESPBUFTHLD field.*/
39767 
39768 /* IBISTATUSTHLD @Bits 24..31 : In-Band Interrupt Status Threshold Value. */
39769   #define I3CCORE_CORE_QUEUETHLDCTRL_IBISTATUSTHLD_Pos (24UL) /*!< Position of IBISTATUSTHLD field.                            */
39770   #define I3CCORE_CORE_QUEUETHLDCTRL_IBISTATUSTHLD_Msk (0xFFUL << I3CCORE_CORE_QUEUETHLDCTRL_IBISTATUSTHLD_Pos) /*!< Bit mask of
39771                                                                             IBISTATUSTHLD field.*/
39772 
39773 
39774 /* I3CCORE_CORE_DATABUFFERTHLDCTRL: Data Buffer Threshold Control Register */
39775   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_ResetValue (0x01010101UL) /*!< Reset value of DATABUFFERTHLDCTRL register.           */
39776 
39777 /* TXEMPTYBUFTHLD @Bits 0..2 : Transmit Buffer Threshold Value */
39778   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Pos (0UL) /*!< Position of TXEMPTYBUFTHLD field.                      */
39779   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Msk (0x7UL << I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Pos) /*!<
39780                                                                             Bit mask of TXEMPTYBUFTHLD field.*/
39781   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Min (0x0UL) /*!< Min enumerator value of TXEMPTYBUFTHLD field.        */
39782   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_Max (0x5UL) /*!< Max enumerator value of TXEMPTYBUFTHLD field.        */
39783   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD1 (0x0UL) /*!< (unspecified)                                 */
39784   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD14 (0x1UL) /*!< (unspecified)                                */
39785   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD18 (0x2UL) /*!< (unspecified)                                */
39786   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD116 (0x3UL) /*!< (unspecified)                               */
39787   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD132 (0x4UL) /*!< (unspecified)                               */
39788   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXEMPTYBUFTHLD_THRESHOLD164 (0x5UL) /*!< (unspecified)                               */
39789 
39790 /* RXBUFTHLD @Bits 8..10 : Receive Buffer Threshold Value */
39791   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Pos (8UL) /*!< Position of RXBUFTHLD field.                                */
39792   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Msk (0x7UL << I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Pos) /*!< Bit mask
39793                                                                             of RXBUFTHLD field.*/
39794   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Min (0x0UL) /*!< Min enumerator value of RXBUFTHLD field.                  */
39795   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_Max (0x5UL) /*!< Max enumerator value of RXBUFTHLD field.                  */
39796   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD1 (0x0UL) /*!< (unspecified)                                      */
39797   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD4 (0x1UL) /*!< (unspecified)                                      */
39798   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD8 (0x2UL) /*!< (unspecified)                                      */
39799   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD16 (0x3UL) /*!< (unspecified)                                     */
39800   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD32 (0x4UL) /*!< (unspecified)                                     */
39801   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXBUFTHLD_THRESHOLD64 (0x5UL) /*!< (unspecified)                                     */
39802 
39803 /* TXSTARTTHLD @Bits 16..18 : Transfer Start Threshold Value */
39804   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Pos (16UL) /*!< Position of TXSTARTTHLD field.                           */
39805   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Msk (0x7UL << I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Pos) /*!< Bit
39806                                                                             mask of TXSTARTTHLD field.*/
39807   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Min (0x0UL) /*!< Min enumerator value of TXSTARTTHLD field.              */
39808   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_Max (0x5UL) /*!< Max enumerator value of TXSTARTTHLD field.              */
39809   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD1 (0x0UL) /*!< (unspecified)                                    */
39810   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD4 (0x1UL) /*!< (unspecified)                                    */
39811   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD8 (0x2UL) /*!< (unspecified)                                    */
39812   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD16 (0x3UL) /*!< (unspecified)                                   */
39813   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD32 (0x4UL) /*!< (unspecified)                                   */
39814   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_TXSTARTTHLD_THRESHOLD64 (0x5UL) /*!< (unspecified)                                   */
39815 
39816 /* RXSTARTTHLD @Bits 24..26 : Receive Start Threshold Value */
39817   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Pos (24UL) /*!< Position of RXSTARTTHLD field.                           */
39818   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Msk (0x7UL << I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Pos) /*!< Bit
39819                                                                             mask of RXSTARTTHLD field.*/
39820   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Min (0x0UL) /*!< Min enumerator value of RXSTARTTHLD field.              */
39821   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_Max (0x5UL) /*!< Max enumerator value of RXSTARTTHLD field.              */
39822   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD1 (0x0UL) /*!< (unspecified)                                    */
39823   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD4 (0x1UL) /*!< (unspecified)                                    */
39824   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD8 (0x2UL) /*!< (unspecified)                                    */
39825   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD16 (0x3UL) /*!< (unspecified)                                   */
39826   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD32 (0x4UL) /*!< (unspecified)                                   */
39827   #define I3CCORE_CORE_DATABUFFERTHLDCTRL_RXSTARTTHLD_THRESHOLD64 (0x5UL) /*!< (unspecified)                                   */
39828 
39829 
39830 /* I3CCORE_CORE_IBIQUEUECTRL: This Register is used to control whether or not to intimate the application if an IBI request is
39831                                rejected (Nacked). */
39832 
39833   #define I3CCORE_CORE_IBIQUEUECTRL_ResetValue (0x00000000UL) /*!< Reset value of IBIQUEUECTRL register.                       */
39834 
39835 /* NOTIFYHJREJECTED @Bit 0 : Notify Rejected Hot-Join Control. */
39836   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Pos (0UL) /*!< Position of NOTIFYHJREJECTED field.                        */
39837   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Msk (0x1UL << I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Pos) /*!< Bit mask
39838                                                                             of NOTIFYHJREJECTED field.*/
39839   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Min (0x0UL) /*!< Min enumerator value of NOTIFYHJREJECTED field.          */
39840   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_Max (0x1UL) /*!< Max enumerator value of NOTIFYHJREJECTED field.          */
39841   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_DISABLED (0x0UL) /*!< (unspecified)                                       */
39842   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYHJREJECTED_ENABLED (0x1UL) /*!< (unspecified)                                        */
39843 
39844 /* NOTIFYMRREJECTED @Bit 1 : Notify Rejected Master Request Control. */
39845   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Pos (1UL) /*!< Position of NOTIFYMRREJECTED field.                        */
39846   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Msk (0x1UL << I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Pos) /*!< Bit mask
39847                                                                             of NOTIFYMRREJECTED field.*/
39848   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Min (0x0UL) /*!< Min enumerator value of NOTIFYMRREJECTED field.          */
39849   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_Max (0x1UL) /*!< Max enumerator value of NOTIFYMRREJECTED field.          */
39850   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_DISABLED (0x0UL) /*!< Suppress passing the IBI Status to the IBI FIFO
39851                                                                            (hence not notifying the application) when a MR
39852                                                                            Request is NACKed and auto-disabled based on the
39853                                                                            IBI_MR_REQ_REJECT Register.*/
39854   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYMRREJECTED_ENABLED (0x1UL) /*!< Writes IBI Status to the IBI FIFO (hence notifying the
39855                                                                           application) when a MR Request is NACKed and
39856                                                                           auto-disabled based on the IBI_MR_REQ_REJECT
39857                                                                           Register.*/
39858 
39859 /* NOTIFYSIRREJECTED @Bit 3 : Notify Rejected Slave Interrupt Request Control. */
39860   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Pos (3UL) /*!< Position of NOTIFYSIRREJECTED field.                      */
39861   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Msk (0x1UL << I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Pos) /*!< Bit
39862                                                                             mask of NOTIFYSIRREJECTED field.*/
39863   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Min (0x0UL) /*!< Min enumerator value of NOTIFYSIRREJECTED field.        */
39864   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_Max (0x1UL) /*!< Max enumerator value of NOTIFYSIRREJECTED field.        */
39865   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_DISABLED (0x0UL) /*!< Suppress passing the IBI Status to the IBI FIFO
39866                                                                             (hence not notifying the application) when a Slave
39867                                                                             Interrupt Request is NACKed and auto-disabled based
39868                                                                             on the IBI_SIR_REQ_REJECT Register.*/
39869   #define I3CCORE_CORE_IBIQUEUECTRL_NOTIFYSIRREJECTED_ENABLED (0x1UL) /*!< Writes IBI Status to the IBI FIFO (hence notifying
39870                                                                            the application) when a Slave Interrupt Request is
39871                                                                            NACKed and auto-disabled based on the
39872                                                                            IBI_SIR_REQ_REJECT Register.*/
39873 
39874 
39875 /* I3CCORE_CORE_IBIMRREQREJECT: IBI Master Request Rejection Control Register. */
39876   #define I3CCORE_CORE_IBIMRREQREJECT_ResetValue (0x00000000UL) /*!< Reset value of IBIMRREQREJECT register.                   */
39877 
39878 /* MRREQREJECT @Bits 0..31 : In-band Master Request Reject. */
39879   #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Pos (0UL) /*!< Position of MRREQREJECT field.                                */
39880   #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Msk (0xFFFFFFFFUL << I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Pos) /*!< Bit
39881                                                                             mask of MRREQREJECT field.*/
39882   #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Min (0x0UL) /*!< Min enumerator value of MRREQREJECT field.                  */
39883   #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_Max (0x1UL) /*!< Max enumerator value of MRREQREJECT field.                  */
39884   #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_ACK (0x00000000UL) /*!< ACK Master Request.                                  */
39885   #define I3CCORE_CORE_IBIMRREQREJECT_MRREQREJECT_NACK (0x00000001UL) /*!< NACK and send Directed DISEC CCC to disable the
39886                                                                            interrupting slave.*/
39887 
39888 
39889 /* I3CCORE_CORE_IBISIRREQREJECT: IBI SIR Request Rejection Control */
39890   #define I3CCORE_CORE_IBISIRREQREJECT_ResetValue (0x00000000UL) /*!< Reset value of IBISIRREQREJECT register.                 */
39891 
39892 /* SIRREQREJECT @Bits 0..31 : In-band Slave Interrupt Request Reject */
39893   #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Pos (0UL) /*!< Position of SIRREQREJECT field.                             */
39894   #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Msk (0xFFFFFFFFUL << I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Pos) /*!< Bit
39895                                                                             mask of SIRREQREJECT field.*/
39896   #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Min (0x0UL) /*!< Min enumerator value of SIRREQREJECT field.               */
39897   #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_Max (0x1UL) /*!< Max enumerator value of SIRREQREJECT field.               */
39898   #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_ACK (0x00000000UL) /*!< ACK the SIR Request.                               */
39899   #define I3CCORE_CORE_IBISIRREQREJECT_SIRREQREJECT_NACK (0x00000001UL) /*!< NACK and send directed auto disable CCC.          */
39900 
39901 
39902 /* I3CCORE_CORE_RESETCTRL: This Register is used for general software reset and for individual buffer reset. */
39903   #define I3CCORE_CORE_RESETCTRL_ResetValue (0x00000000UL) /*!< Reset value of RESETCTRL register.                             */
39904 
39905 /* SOFTRST @Bit 0 : Core Software Reset. */
39906   #define I3CCORE_CORE_RESETCTRL_SOFTRST_Pos (0UL)   /*!< Position of SOFTRST field.                                           */
39907   #define I3CCORE_CORE_RESETCTRL_SOFTRST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_SOFTRST_Pos) /*!< Bit mask of SOFTRST field.     */
39908 
39909 /* CMDQUEUERST @Bit 1 : Command Queue Software Reset */
39910   #define I3CCORE_CORE_RESETCTRL_CMDQUEUERST_Pos (1UL) /*!< Position of CMDQUEUERST field.                                     */
39911   #define I3CCORE_CORE_RESETCTRL_CMDQUEUERST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_CMDQUEUERST_Pos) /*!< Bit mask of CMDQUEUERST
39912                                                                             field.*/
39913 
39914 /* RESPQUEUERST @Bit 2 : Response Queue Software Reset */
39915   #define I3CCORE_CORE_RESETCTRL_RESPQUEUERST_Pos (2UL) /*!< Position of RESPQUEUERST field.                                   */
39916   #define I3CCORE_CORE_RESETCTRL_RESPQUEUERST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_RESPQUEUERST_Pos) /*!< Bit mask of
39917                                                                             RESPQUEUERST field.*/
39918 
39919 /* TXFIFORST @Bit 3 : Transmit Buffer Software Reset */
39920   #define I3CCORE_CORE_RESETCTRL_TXFIFORST_Pos (3UL) /*!< Position of TXFIFORST field.                                         */
39921   #define I3CCORE_CORE_RESETCTRL_TXFIFORST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_TXFIFORST_Pos) /*!< Bit mask of TXFIFORST
39922                                                                             field.*/
39923 
39924 /* RXFIFORST @Bit 4 : Receive Buffer Software Reset. */
39925   #define I3CCORE_CORE_RESETCTRL_RXFIFORST_Pos (4UL) /*!< Position of RXFIFORST field.                                         */
39926   #define I3CCORE_CORE_RESETCTRL_RXFIFORST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_RXFIFORST_Pos) /*!< Bit mask of RXFIFORST
39927                                                                             field.*/
39928 
39929 /* IBIQUEUERST @Bit 5 : IBI Queue Software Reset. */
39930   #define I3CCORE_CORE_RESETCTRL_IBIQUEUERST_Pos (5UL) /*!< Position of IBIQUEUERST field.                                     */
39931   #define I3CCORE_CORE_RESETCTRL_IBIQUEUERST_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_IBIQUEUERST_Pos) /*!< Bit mask of IBIQUEUERST
39932                                                                             field.*/
39933 
39934 /* BUSRESETTYPE @Bits 29..30 : Bus Reset type */
39935   #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Pos (29UL) /*!< Position of BUSRESETTYPE field.                                  */
39936   #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Msk (0x3UL << I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Pos) /*!< Bit mask of
39937                                                                             BUSRESETTYPE field.*/
39938   #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Min (0x0UL) /*!< Min enumerator value of BUSRESETTYPE field.                     */
39939   #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_Max (0x3UL) /*!< Max enumerator value of BUSRESETTYPE field.                     */
39940   #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_EXIT (0x0UL) /*!< Exit Pattern.                                                  */
39941   #define I3CCORE_CORE_RESETCTRL_BUSRESETTYPE_SCL_LOW_RESET (0x3UL) /*!< SCL_LOW_RESET Pattern.                                */
39942 
39943 /* BUSRESET @Bit 31 : Bus Reset. */
39944   #define I3CCORE_CORE_RESETCTRL_BUSRESET_Pos (31UL) /*!< Position of BUSRESET field.                                          */
39945   #define I3CCORE_CORE_RESETCTRL_BUSRESET_Msk (0x1UL << I3CCORE_CORE_RESETCTRL_BUSRESET_Pos) /*!< Bit mask of BUSRESET field.  */
39946 
39947 
39948 /* I3CCORE_CORE_SLVEVENTSTATUS: This register indicates the status/values of some events/controls that are relavant to slave
39949                                  mode of operation. */
39950 
39951   #define I3CCORE_CORE_SLVEVENTSTATUS_ResetValue (0x0000000BUL) /*!< Reset value of SLVEVENTSTATUS register.                   */
39952 
39953 /* SIREN @Bit 0 : Slave Interrupt Request Enable. */
39954   #define I3CCORE_CORE_SLVEVENTSTATUS_SIREN_Pos (0UL) /*!< Position of SIREN field.                                            */
39955   #define I3CCORE_CORE_SLVEVENTSTATUS_SIREN_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_SIREN_Pos) /*!< Bit mask of SIREN field. */
39956 
39957 /* MREN @Bit 1 : Master Request Enable. */
39958   #define I3CCORE_CORE_SLVEVENTSTATUS_MREN_Pos (1UL) /*!< Position of MREN field.                                              */
39959   #define I3CCORE_CORE_SLVEVENTSTATUS_MREN_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_MREN_Pos) /*!< Bit mask of MREN field.    */
39960 
39961 /* HJEN @Bit 3 : Hot-Join Interrupt Enable */
39962   #define I3CCORE_CORE_SLVEVENTSTATUS_HJEN_Pos (3UL) /*!< Position of HJEN field.                                              */
39963   #define I3CCORE_CORE_SLVEVENTSTATUS_HJEN_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_HJEN_Pos) /*!< Bit mask of HJEN field.    */
39964 
39965 /* ACTIVITYSTATE @Bits 4..5 : Activity State Status. */
39966   #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Pos (4UL) /*!< Position of ACTIVITYSTATE field.                            */
39967   #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Msk (0x3UL << I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Pos) /*!< Bit mask
39968                                                                             of ACTIVITYSTATE field.*/
39969   #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Min (0x0UL) /*!< Min enumerator value of ACTIVITYSTATE field.              */
39970   #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_Max (0x3UL) /*!< Max enumerator value of ACTIVITYSTATE field.              */
39971   #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_ENTAS0 (0x0UL) /*!< (unspecified)                                          */
39972   #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_ENTAS1 (0x1UL) /*!< (unspecified)                                          */
39973   #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_ENTAS2 (0x2UL) /*!< (unspecified)                                          */
39974   #define I3CCORE_CORE_SLVEVENTSTATUS_ACTIVITYSTATE_ENTAS3 (0x3UL) /*!< (unspecified)                                          */
39975 
39976 /* MRLUPDATED @Bit 6 : MRL Updated Status. */
39977   #define I3CCORE_CORE_SLVEVENTSTATUS_MRLUPDATED_Pos (6UL) /*!< Position of MRLUPDATED field.                                  */
39978   #define I3CCORE_CORE_SLVEVENTSTATUS_MRLUPDATED_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_MRLUPDATED_Pos) /*!< Bit mask of
39979                                                                             MRLUPDATED field.*/
39980 
39981 /* MWLUPDATED @Bit 7 : MWL Updated Status. */
39982   #define I3CCORE_CORE_SLVEVENTSTATUS_MWLUPDATED_Pos (7UL) /*!< Position of MWLUPDATED field.                                  */
39983   #define I3CCORE_CORE_SLVEVENTSTATUS_MWLUPDATED_Msk (0x1UL << I3CCORE_CORE_SLVEVENTSTATUS_MWLUPDATED_Pos) /*!< Bit mask of
39984                                                                             MWLUPDATED field.*/
39985 
39986 
39987 /* I3CCORE_CORE_INTRSTATUS: Interrupt Status Register */
39988   #define I3CCORE_CORE_INTRSTATUS_ResetValue (0x00000000UL) /*!< Reset value of INTRSTATUS register.                           */
39989 
39990 /* TXTHLDSTS @Bit 0 : Transmit Buffer Threshold Status */
39991   #define I3CCORE_CORE_INTRSTATUS_TXTHLDSTS_Pos (0UL) /*!< Position of TXTHLDSTS field.                                        */
39992   #define I3CCORE_CORE_INTRSTATUS_TXTHLDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_TXTHLDSTS_Pos) /*!< Bit mask of TXTHLDSTS
39993                                                                             field.*/
39994 
39995 /* RXTHLDSTS @Bit 1 : Receive Buffer Threshold Status. */
39996   #define I3CCORE_CORE_INTRSTATUS_RXTHLDSTS_Pos (1UL) /*!< Position of RXTHLDSTS field.                                        */
39997   #define I3CCORE_CORE_INTRSTATUS_RXTHLDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_RXTHLDSTS_Pos) /*!< Bit mask of RXTHLDSTS
39998                                                                             field.*/
39999 
40000 /* IBITHLDSTS @Bit 2 : IBI Buffer Threshold Status. */
40001   #define I3CCORE_CORE_INTRSTATUS_IBITHLDSTS_Pos (2UL) /*!< Position of IBITHLDSTS field.                                      */
40002   #define I3CCORE_CORE_INTRSTATUS_IBITHLDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_IBITHLDSTS_Pos) /*!< Bit mask of IBITHLDSTS
40003                                                                             field.*/
40004 
40005 /* CMDQUEUEREADYSTS @Bit 3 : Command Queue Ready. */
40006   #define I3CCORE_CORE_INTRSTATUS_CMDQUEUEREADYSTS_Pos (3UL) /*!< Position of CMDQUEUEREADYSTS field.                          */
40007   #define I3CCORE_CORE_INTRSTATUS_CMDQUEUEREADYSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_CMDQUEUEREADYSTS_Pos) /*!< Bit mask of
40008                                                                             CMDQUEUEREADYSTS field.*/
40009 
40010 /* RESPREADYSTS @Bit 4 : Response Queue Ready Status. */
40011   #define I3CCORE_CORE_INTRSTATUS_RESPREADYSTS_Pos (4UL) /*!< Position of RESPREADYSTS field.                                  */
40012   #define I3CCORE_CORE_INTRSTATUS_RESPREADYSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_RESPREADYSTS_Pos) /*!< Bit mask of
40013                                                                             RESPREADYSTS field.*/
40014 
40015 /* TRANSFERABORTSTS @Bit 5 : Transfer Abort Status. */
40016   #define I3CCORE_CORE_INTRSTATUS_TRANSFERABORTSTS_Pos (5UL) /*!< Position of TRANSFERABORTSTS field.                          */
40017   #define I3CCORE_CORE_INTRSTATUS_TRANSFERABORTSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_TRANSFERABORTSTS_Pos) /*!< Bit mask of
40018                                                                             TRANSFERABORTSTS field.*/
40019 
40020 /* CCCUPDATEDSTS @Bit 6 : CCC Table Updated Status. */
40021   #define I3CCORE_CORE_INTRSTATUS_CCCUPDATEDSTS_Pos (6UL) /*!< Position of CCCUPDATEDSTS field.                                */
40022   #define I3CCORE_CORE_INTRSTATUS_CCCUPDATEDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_CCCUPDATEDSTS_Pos) /*!< Bit mask of
40023                                                                             CCCUPDATEDSTS field.*/
40024 
40025 /* DYNADDRASSGNSTS @Bit 8 : Dynamic Address Assigned Status. */
40026   #define I3CCORE_CORE_INTRSTATUS_DYNADDRASSGNSTS_Pos (8UL) /*!< Position of DYNADDRASSGNSTS field.                            */
40027   #define I3CCORE_CORE_INTRSTATUS_DYNADDRASSGNSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_DYNADDRASSGNSTS_Pos) /*!< Bit mask of
40028                                                                             DYNADDRASSGNSTS field.*/
40029 
40030 /* TRANSFERERRSTS @Bit 9 : Transfer Error Status. */
40031   #define I3CCORE_CORE_INTRSTATUS_TRANSFERERRSTS_Pos (9UL) /*!< Position of TRANSFERERRSTS field.                              */
40032   #define I3CCORE_CORE_INTRSTATUS_TRANSFERERRSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_TRANSFERERRSTS_Pos) /*!< Bit mask of
40033                                                                             TRANSFERERRSTS field.*/
40034 
40035 /* DEFSLVSTS @Bit 10 : Define Slave CCC Received Status. */
40036   #define I3CCORE_CORE_INTRSTATUS_DEFSLVSTS_Pos (10UL) /*!< Position of DEFSLVSTS field.                                       */
40037   #define I3CCORE_CORE_INTRSTATUS_DEFSLVSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_DEFSLVSTS_Pos) /*!< Bit mask of DEFSLVSTS
40038                                                                             field.*/
40039 
40040 /* READREQRECVSTS @Bit 11 : Read Request Received. */
40041   #define I3CCORE_CORE_INTRSTATUS_READREQRECVSTS_Pos (11UL) /*!< Position of READREQRECVSTS field.                             */
40042   #define I3CCORE_CORE_INTRSTATUS_READREQRECVSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_READREQRECVSTS_Pos) /*!< Bit mask of
40043                                                                             READREQRECVSTS field.*/
40044 
40045 /* IBIUPDATEDSTS @Bit 12 : IBI status is updated. */
40046   #define I3CCORE_CORE_INTRSTATUS_IBIUPDATEDSTS_Pos (12UL) /*!< Position of IBIUPDATEDSTS field.                               */
40047   #define I3CCORE_CORE_INTRSTATUS_IBIUPDATEDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_IBIUPDATEDSTS_Pos) /*!< Bit mask of
40048                                                                             IBIUPDATEDSTS field.*/
40049 
40050 /* BUSOWNERUPDATEDSTS @Bit 13 : This interrupt is set when the role of the controller changes from being a Master to Slave or
40051                                 vice versa. */
40052 
40053   #define I3CCORE_CORE_INTRSTATUS_BUSOWNERUPDATEDSTS_Pos (13UL) /*!< Position of BUSOWNERUPDATEDSTS field.                     */
40054   #define I3CCORE_CORE_INTRSTATUS_BUSOWNERUPDATEDSTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_BUSOWNERUPDATEDSTS_Pos) /*!< Bit mask
40055                                                                             of BUSOWNERUPDATEDSTS field.*/
40056 
40057 /* BUSRESETDONESTS @Bit 15 : Bus Reset Pattern Generation Done Status. */
40058   #define I3CCORE_CORE_INTRSTATUS_BUSRESETDONESTS_Pos (15UL) /*!< Position of BUSRESETDONESTS field.                           */
40059   #define I3CCORE_CORE_INTRSTATUS_BUSRESETDONESTS_Msk (0x1UL << I3CCORE_CORE_INTRSTATUS_BUSRESETDONESTS_Pos) /*!< Bit mask of
40060                                                                             BUSRESETDONESTS field.*/
40061 
40062 
40063 /* I3CCORE_CORE_INTRSTATUSEN: Interrupt Status Enable Register. */
40064   #define I3CCORE_CORE_INTRSTATUSEN_ResetValue (0x00000000UL) /*!< Reset value of INTRSTATUSEN register.                       */
40065 
40066 /* TXTHLDSTSEN @Bit 0 : Transmit Buffer Threshold Status Enable. */
40067   #define I3CCORE_CORE_INTRSTATUSEN_TXTHLDSTSEN_Pos (0UL) /*!< Position of TXTHLDSTSEN field.                                  */
40068   #define I3CCORE_CORE_INTRSTATUSEN_TXTHLDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_TXTHLDSTSEN_Pos) /*!< Bit mask of
40069                                                                             TXTHLDSTSEN field.*/
40070 
40071 /* RXTHLDSTSEN @Bit 1 : Receive Buffer Threshold Status Enable */
40072   #define I3CCORE_CORE_INTRSTATUSEN_RXTHLDSTSEN_Pos (1UL) /*!< Position of RXTHLDSTSEN field.                                  */
40073   #define I3CCORE_CORE_INTRSTATUSEN_RXTHLDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_RXTHLDSTSEN_Pos) /*!< Bit mask of
40074                                                                             RXTHLDSTSEN field.*/
40075 
40076 /* IBITHLDSTSEN @Bit 2 : IBI Buffer Threshold Status Enable. */
40077   #define I3CCORE_CORE_INTRSTATUSEN_IBITHLDSTSEN_Pos (2UL) /*!< Position of IBITHLDSTSEN field.                                */
40078   #define I3CCORE_CORE_INTRSTATUSEN_IBITHLDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_IBITHLDSTSEN_Pos) /*!< Bit mask of
40079                                                                             IBITHLDSTSEN field.*/
40080 
40081 /* CMDQUEUEREADYSTSEN @Bit 3 : Command Queue Ready Status Enable */
40082   #define I3CCORE_CORE_INTRSTATUSEN_CMDQUEUEREADYSTSEN_Pos (3UL) /*!< Position of CMDQUEUEREADYSTSEN field.                    */
40083   #define I3CCORE_CORE_INTRSTATUSEN_CMDQUEUEREADYSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_CMDQUEUEREADYSTSEN_Pos) /*!< Bit
40084                                                                             mask of CMDQUEUEREADYSTSEN field.*/
40085 
40086 /* RESPREADYSTSEN @Bit 4 : Response Queue Ready Status Enable */
40087   #define I3CCORE_CORE_INTRSTATUSEN_RESPREADYSTSEN_Pos (4UL) /*!< Position of RESPREADYSTSEN field.                            */
40088   #define I3CCORE_CORE_INTRSTATUSEN_RESPREADYSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_RESPREADYSTSEN_Pos) /*!< Bit mask of
40089                                                                             RESPREADYSTSEN field.*/
40090 
40091 /* TRANSFERABORTSTSEN @Bit 5 : Transfer Abort Status Enable. */
40092   #define I3CCORE_CORE_INTRSTATUSEN_TRANSFERABORTSTSEN_Pos (5UL) /*!< Position of TRANSFERABORTSTSEN field.                    */
40093   #define I3CCORE_CORE_INTRSTATUSEN_TRANSFERABORTSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_TRANSFERABORTSTSEN_Pos) /*!< Bit
40094                                                                             mask of TRANSFERABORTSTSEN field.*/
40095 
40096 /* CCCUPDATEDSTSEN @Bit 6 : CCC Table Updated Status Enable. */
40097   #define I3CCORE_CORE_INTRSTATUSEN_CCCUPDATEDSTSEN_Pos (6UL) /*!< Position of CCCUPDATEDSTSEN field.                          */
40098   #define I3CCORE_CORE_INTRSTATUSEN_CCCUPDATEDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_CCCUPDATEDSTSEN_Pos) /*!< Bit mask
40099                                                                             of CCCUPDATEDSTSEN field.*/
40100 
40101 /* DYNADDRASSGNSTSEN @Bit 8 : Dynamic Address Assigned Status Enable */
40102   #define I3CCORE_CORE_INTRSTATUSEN_DYNADDRASSGNSTSEN_Pos (8UL) /*!< Position of DYNADDRASSGNSTSEN field.                      */
40103   #define I3CCORE_CORE_INTRSTATUSEN_DYNADDRASSGNSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_DYNADDRASSGNSTSEN_Pos) /*!< Bit
40104                                                                             mask of DYNADDRASSGNSTSEN field.*/
40105 
40106 /* TRANSFERERRSTSEN @Bit 9 : Transfer Error Status Enable */
40107   #define I3CCORE_CORE_INTRSTATUSEN_TRANSFERERRSTSEN_Pos (9UL) /*!< Position of TRANSFERERRSTSEN field.                        */
40108   #define I3CCORE_CORE_INTRSTATUSEN_TRANSFERERRSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_TRANSFERERRSTSEN_Pos) /*!< Bit mask
40109                                                                             of TRANSFERERRSTSEN field.*/
40110 
40111 /* DEFSLVSTSEN @Bit 10 : Define Slave CCC Received Status Enable */
40112   #define I3CCORE_CORE_INTRSTATUSEN_DEFSLVSTSEN_Pos (10UL) /*!< Position of DEFSLVSTSEN field.                                 */
40113   #define I3CCORE_CORE_INTRSTATUSEN_DEFSLVSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_DEFSLVSTSEN_Pos) /*!< Bit mask of
40114                                                                             DEFSLVSTSEN field.*/
40115 
40116 /* READREQRECVSTSEN @Bit 11 : Read Request Received Status Enable */
40117   #define I3CCORE_CORE_INTRSTATUSEN_READREQRECVSTSEN_Pos (11UL) /*!< Position of READREQRECVSTSEN field.                       */
40118   #define I3CCORE_CORE_INTRSTATUSEN_READREQRECVSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_READREQRECVSTSEN_Pos) /*!< Bit mask
40119                                                                             of READREQRECVSTSEN field.*/
40120 
40121 /* IBIUPDATEDSTSEN @Bit 12 : IBI Updated Status Enable */
40122   #define I3CCORE_CORE_INTRSTATUSEN_IBIUPDATEDSTSEN_Pos (12UL) /*!< Position of IBIUPDATEDSTSEN field.                         */
40123   #define I3CCORE_CORE_INTRSTATUSEN_IBIUPDATEDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_IBIUPDATEDSTSEN_Pos) /*!< Bit mask
40124                                                                             of IBIUPDATEDSTSEN field.*/
40125 
40126 /* BUSOWNERUPDATEDSTSEN @Bit 13 : Bus owner Updated Status Enable */
40127   #define I3CCORE_CORE_INTRSTATUSEN_BUSOWNERUPDATEDSTSEN_Pos (13UL) /*!< Position of BUSOWNERUPDATEDSTSEN field.               */
40128   #define I3CCORE_CORE_INTRSTATUSEN_BUSOWNERUPDATEDSTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_BUSOWNERUPDATEDSTSEN_Pos) /*!<
40129                                                                             Bit mask of BUSOWNERUPDATEDSTSEN field.*/
40130 
40131 /* BUSRESETDONESTSEN @Bit 15 : Bus Reset Pattern Generation Done Status Enable. */
40132   #define I3CCORE_CORE_INTRSTATUSEN_BUSRESETDONESTSEN_Pos (15UL) /*!< Position of BUSRESETDONESTSEN field.                     */
40133   #define I3CCORE_CORE_INTRSTATUSEN_BUSRESETDONESTSEN_Msk (0x1UL << I3CCORE_CORE_INTRSTATUSEN_BUSRESETDONESTSEN_Pos) /*!< Bit
40134                                                                             mask of BUSRESETDONESTSEN field.*/
40135 
40136 
40137 /* I3CCORE_CORE_INTRSIGNALEN: Interrupt Signal Enable Register */
40138   #define I3CCORE_CORE_INTRSIGNALEN_ResetValue (0x00000000UL) /*!< Reset value of INTRSIGNALEN register.                       */
40139 
40140 /* TXTHLDSIGNALEN @Bit 0 : Transmit Buffer Threshold Signal Enable */
40141   #define I3CCORE_CORE_INTRSIGNALEN_TXTHLDSIGNALEN_Pos (0UL) /*!< Position of TXTHLDSIGNALEN field.                            */
40142   #define I3CCORE_CORE_INTRSIGNALEN_TXTHLDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_TXTHLDSIGNALEN_Pos) /*!< Bit mask of
40143                                                                             TXTHLDSIGNALEN field.*/
40144 
40145 /* RXTHLDSIGNALEN @Bit 1 : Receive Buffer Threshold Signal Enable */
40146   #define I3CCORE_CORE_INTRSIGNALEN_RXTHLDSIGNALEN_Pos (1UL) /*!< Position of RXTHLDSIGNALEN field.                            */
40147   #define I3CCORE_CORE_INTRSIGNALEN_RXTHLDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_RXTHLDSIGNALEN_Pos) /*!< Bit mask of
40148                                                                             RXTHLDSIGNALEN field.*/
40149 
40150 /* IBITHLDSIGNALEN @Bit 2 : IBI Buffer Threshold Signal Enable */
40151   #define I3CCORE_CORE_INTRSIGNALEN_IBITHLDSIGNALEN_Pos (2UL) /*!< Position of IBITHLDSIGNALEN field.                          */
40152   #define I3CCORE_CORE_INTRSIGNALEN_IBITHLDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_IBITHLDSIGNALEN_Pos) /*!< Bit mask
40153                                                                             of IBITHLDSIGNALEN field.*/
40154 
40155 /* CMDQUEUEREADYSIGNALEN @Bit 3 : Command Queue Ready Signal Enable */
40156   #define I3CCORE_CORE_INTRSIGNALEN_CMDQUEUEREADYSIGNALEN_Pos (3UL) /*!< Position of CMDQUEUEREADYSIGNALEN field.              */
40157   #define I3CCORE_CORE_INTRSIGNALEN_CMDQUEUEREADYSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_CMDQUEUEREADYSIGNALEN_Pos)
40158                                                                             /*!< Bit mask of CMDQUEUEREADYSIGNALEN field.*/
40159 
40160 /* RESPREADYSIGNALEN @Bit 4 : Response Queue Ready Signal Enable */
40161   #define I3CCORE_CORE_INTRSIGNALEN_RESPREADYSIGNALEN_Pos (4UL) /*!< Position of RESPREADYSIGNALEN field.                      */
40162   #define I3CCORE_CORE_INTRSIGNALEN_RESPREADYSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_RESPREADYSIGNALEN_Pos) /*!< Bit
40163                                                                             mask of RESPREADYSIGNALEN field.*/
40164 
40165 /* TRANSFERABORTSIGNALEN @Bit 5 : Transfer Abort Signal Enable */
40166   #define I3CCORE_CORE_INTRSIGNALEN_TRANSFERABORTSIGNALEN_Pos (5UL) /*!< Position of TRANSFERABORTSIGNALEN field.              */
40167   #define I3CCORE_CORE_INTRSIGNALEN_TRANSFERABORTSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_TRANSFERABORTSIGNALEN_Pos)
40168                                                                             /*!< Bit mask of TRANSFERABORTSIGNALEN field.*/
40169 
40170 /* CCCUPDATEDSIGNALEN @Bit 6 : CCC Table Updated Signal Enable */
40171   #define I3CCORE_CORE_INTRSIGNALEN_CCCUPDATEDSIGNALEN_Pos (6UL) /*!< Position of CCCUPDATEDSIGNALEN field.                    */
40172   #define I3CCORE_CORE_INTRSIGNALEN_CCCUPDATEDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_CCCUPDATEDSIGNALEN_Pos) /*!< Bit
40173                                                                             mask of CCCUPDATEDSIGNALEN field.*/
40174 
40175 /* DYNADDRASSGNSIGNALEN @Bit 8 : Dynamic Address Assigned Signal Enable */
40176   #define I3CCORE_CORE_INTRSIGNALEN_DYNADDRASSGNSIGNALEN_Pos (8UL) /*!< Position of DYNADDRASSGNSIGNALEN field.                */
40177   #define I3CCORE_CORE_INTRSIGNALEN_DYNADDRASSGNSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_DYNADDRASSGNSIGNALEN_Pos) /*!<
40178                                                                             Bit mask of DYNADDRASSGNSIGNALEN field.*/
40179 
40180 /* TRANSFERERRSIGNALEN @Bit 9 : Transfer Error Signal Enable */
40181   #define I3CCORE_CORE_INTRSIGNALEN_TRANSFERERRSIGNALEN_Pos (9UL) /*!< Position of TRANSFERERRSIGNALEN field.                  */
40182   #define I3CCORE_CORE_INTRSIGNALEN_TRANSFERERRSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_TRANSFERERRSIGNALEN_Pos) /*!<
40183                                                                             Bit mask of TRANSFERERRSIGNALEN field.*/
40184 
40185 /* DEFSLVSIGNALEN @Bit 10 : Define Slave CCC Received Signal Enable */
40186   #define I3CCORE_CORE_INTRSIGNALEN_DEFSLVSIGNALEN_Pos (10UL) /*!< Position of DEFSLVSIGNALEN field.                           */
40187   #define I3CCORE_CORE_INTRSIGNALEN_DEFSLVSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_DEFSLVSIGNALEN_Pos) /*!< Bit mask of
40188                                                                             DEFSLVSIGNALEN field.*/
40189 
40190 /* READREQRECVSIGNALEN @Bit 11 : Read Request Received Signal Enable */
40191   #define I3CCORE_CORE_INTRSIGNALEN_READREQRECVSIGNALEN_Pos (11UL) /*!< Position of READREQRECVSIGNALEN field.                 */
40192   #define I3CCORE_CORE_INTRSIGNALEN_READREQRECVSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_READREQRECVSIGNALEN_Pos) /*!<
40193                                                                             Bit mask of READREQRECVSIGNALEN field.*/
40194 
40195 /* IBIUPDATEDSIGNALEN @Bit 12 : IBI Updated Signal Enable */
40196   #define I3CCORE_CORE_INTRSIGNALEN_IBIUPDATEDSIGNALEN_Pos (12UL) /*!< Position of IBIUPDATEDSIGNALEN field.                   */
40197   #define I3CCORE_CORE_INTRSIGNALEN_IBIUPDATEDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_IBIUPDATEDSIGNALEN_Pos) /*!< Bit
40198                                                                             mask of IBIUPDATEDSIGNALEN field.*/
40199 
40200 /* BUSOWNERUPDATEDSIGNALEN @Bit 13 : Bus owner Updated Signal Enable */
40201   #define I3CCORE_CORE_INTRSIGNALEN_BUSOWNERUPDATEDSIGNALEN_Pos (13UL) /*!< Position of BUSOWNERUPDATEDSIGNALEN field.         */
40202   #define I3CCORE_CORE_INTRSIGNALEN_BUSOWNERUPDATEDSIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_BUSOWNERUPDATEDSIGNALEN_Pos)
40203                                                                             /*!< Bit mask of BUSOWNERUPDATEDSIGNALEN field.*/
40204 
40205 /* BUSRESETDONESIGNALEN @Bit 15 : Bus Reset Pattern Generation Done Signal Enable. */
40206   #define I3CCORE_CORE_INTRSIGNALEN_BUSRESETDONESIGNALEN_Pos (15UL) /*!< Position of BUSRESETDONESIGNALEN field.               */
40207   #define I3CCORE_CORE_INTRSIGNALEN_BUSRESETDONESIGNALEN_Msk (0x1UL << I3CCORE_CORE_INTRSIGNALEN_BUSRESETDONESIGNALEN_Pos) /*!<
40208                                                                             Bit mask of BUSRESETDONESIGNALEN field.*/
40209 
40210 
40211 /* I3CCORE_CORE_INTRFORCE: Interrupt Force Enable Register */
40212   #define I3CCORE_CORE_INTRFORCE_ResetValue (0x00000000UL) /*!< Reset value of INTRFORCE register.                             */
40213 
40214 /* TXTHLDFORCEEN @Bit 0 : Transmit Buffer Threshold Force Enable */
40215   #define I3CCORE_CORE_INTRFORCE_TXTHLDFORCEEN_Pos (0UL) /*!< Position of TXTHLDFORCEEN field.                                 */
40216   #define I3CCORE_CORE_INTRFORCE_TXTHLDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_TXTHLDFORCEEN_Pos) /*!< Bit mask of
40217                                                                             TXTHLDFORCEEN field.*/
40218 
40219 /* RXTHLDFORCEEN @Bit 1 : Receive Buffer Threshold Force Enable */
40220   #define I3CCORE_CORE_INTRFORCE_RXTHLDFORCEEN_Pos (1UL) /*!< Position of RXTHLDFORCEEN field.                                 */
40221   #define I3CCORE_CORE_INTRFORCE_RXTHLDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_RXTHLDFORCEEN_Pos) /*!< Bit mask of
40222                                                                             RXTHLDFORCEEN field.*/
40223 
40224 /* IBITHLDFORCEEN @Bit 2 : IBI Buffer Threshold Force Enable */
40225   #define I3CCORE_CORE_INTRFORCE_IBITHLDFORCEEN_Pos (2UL) /*!< Position of IBITHLDFORCEEN field.                               */
40226   #define I3CCORE_CORE_INTRFORCE_IBITHLDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_IBITHLDFORCEEN_Pos) /*!< Bit mask of
40227                                                                             IBITHLDFORCEEN field.*/
40228 
40229 /* CMDQUEUEREADYFORCEEN @Bit 3 : Command Queue Ready Force Enable */
40230   #define I3CCORE_CORE_INTRFORCE_CMDQUEUEREADYFORCEEN_Pos (3UL) /*!< Position of CMDQUEUEREADYFORCEEN field.                   */
40231   #define I3CCORE_CORE_INTRFORCE_CMDQUEUEREADYFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_CMDQUEUEREADYFORCEEN_Pos) /*!< Bit
40232                                                                             mask of CMDQUEUEREADYFORCEEN field.*/
40233 
40234 /* RESPREADYFORCEEN @Bit 4 : Response Queue Ready Force Enable */
40235   #define I3CCORE_CORE_INTRFORCE_RESPREADYFORCEEN_Pos (4UL) /*!< Position of RESPREADYFORCEEN field.                           */
40236   #define I3CCORE_CORE_INTRFORCE_RESPREADYFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_RESPREADYFORCEEN_Pos) /*!< Bit mask of
40237                                                                             RESPREADYFORCEEN field.*/
40238 
40239 /* TRANSFERABORTFORCEEN @Bit 5 : Transfer Abort Force Enable */
40240   #define I3CCORE_CORE_INTRFORCE_TRANSFERABORTFORCEEN_Pos (5UL) /*!< Position of TRANSFERABORTFORCEEN field.                   */
40241   #define I3CCORE_CORE_INTRFORCE_TRANSFERABORTFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_TRANSFERABORTFORCEEN_Pos) /*!< Bit
40242                                                                             mask of TRANSFERABORTFORCEEN field.*/
40243 
40244 /* CCCUPDATEDFORCEEN @Bit 6 : CCC Table Updated Force Enable */
40245   #define I3CCORE_CORE_INTRFORCE_CCCUPDATEDFORCEEN_Pos (6UL) /*!< Position of CCCUPDATEDFORCEEN field.                         */
40246   #define I3CCORE_CORE_INTRFORCE_CCCUPDATEDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_CCCUPDATEDFORCEEN_Pos) /*!< Bit mask of
40247                                                                             CCCUPDATEDFORCEEN field.*/
40248 
40249 /* DYNADDRASSGNFORCEEN @Bit 8 : Dynamic Address Assigned Force Enable */
40250   #define I3CCORE_CORE_INTRFORCE_DYNADDRASSGNFORCEEN_Pos (8UL) /*!< Position of DYNADDRASSGNFORCEEN field.                     */
40251   #define I3CCORE_CORE_INTRFORCE_DYNADDRASSGNFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_DYNADDRASSGNFORCEEN_Pos) /*!< Bit mask
40252                                                                             of DYNADDRASSGNFORCEEN field.*/
40253 
40254 /* TRANSFERERRFORCEEN @Bit 9 : Transfer Error Force Enable */
40255   #define I3CCORE_CORE_INTRFORCE_TRANSFERERRFORCEEN_Pos (9UL) /*!< Position of TRANSFERERRFORCEEN field.                       */
40256   #define I3CCORE_CORE_INTRFORCE_TRANSFERERRFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_TRANSFERERRFORCEEN_Pos) /*!< Bit mask
40257                                                                             of TRANSFERERRFORCEEN field.*/
40258 
40259 /* DEFSLVFORCEEN @Bit 10 : Define Slave CCC Received Force Enable */
40260   #define I3CCORE_CORE_INTRFORCE_DEFSLVFORCEEN_Pos (10UL) /*!< Position of DEFSLVFORCEEN field.                                */
40261   #define I3CCORE_CORE_INTRFORCE_DEFSLVFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_DEFSLVFORCEEN_Pos) /*!< Bit mask of
40262                                                                             DEFSLVFORCEEN field.*/
40263 
40264 /* READREQFORCEEN @Bit 11 : Read Request Received Force Enable */
40265   #define I3CCORE_CORE_INTRFORCE_READREQFORCEEN_Pos (11UL) /*!< Position of READREQFORCEEN field.                              */
40266   #define I3CCORE_CORE_INTRFORCE_READREQFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_READREQFORCEEN_Pos) /*!< Bit mask of
40267                                                                             READREQFORCEEN field.*/
40268 
40269 /* IBIUPDATEDFORCEEN @Bit 12 : IBI Updated Force Enable */
40270   #define I3CCORE_CORE_INTRFORCE_IBIUPDATEDFORCEEN_Pos (12UL) /*!< Position of IBIUPDATEDFORCEEN field.                        */
40271   #define I3CCORE_CORE_INTRFORCE_IBIUPDATEDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_IBIUPDATEDFORCEEN_Pos) /*!< Bit mask of
40272                                                                             IBIUPDATEDFORCEEN field.*/
40273 
40274 /* BUSOWNERUPDATEDFORCEEN @Bit 13 : Bus owner Updated Force Enable */
40275   #define I3CCORE_CORE_INTRFORCE_BUSOWNERUPDATEDFORCEEN_Pos (13UL) /*!< Position of BUSOWNERUPDATEDFORCEEN field.              */
40276   #define I3CCORE_CORE_INTRFORCE_BUSOWNERUPDATEDFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_BUSOWNERUPDATEDFORCEEN_Pos) /*!<
40277                                                                             Bit mask of BUSOWNERUPDATEDFORCEEN field.*/
40278 
40279 /* BUSRESETDONEFORCEEN @Bit 15 : Bus Reset Pattern Generation Done Force Enable. */
40280   #define I3CCORE_CORE_INTRFORCE_BUSRESETDONEFORCEEN_Pos (15UL) /*!< Position of BUSRESETDONEFORCEEN field.                    */
40281   #define I3CCORE_CORE_INTRFORCE_BUSRESETDONEFORCEEN_Msk (0x1UL << I3CCORE_CORE_INTRFORCE_BUSRESETDONEFORCEEN_Pos) /*!< Bit mask
40282                                                                             of BUSRESETDONEFORCEEN field.*/
40283 
40284 
40285 /* I3CCORE_CORE_QUEUESTATUSLEVEL: Queue Status Level Register. */
40286   #define I3CCORE_CORE_QUEUESTATUSLEVEL_ResetValue (0x00000010UL) /*!< Reset value of QUEUESTATUSLEVEL register.               */
40287 
40288 /* CMDQUEUEEMPTYLOC @Bits 0..7 : Command Queue Empty Locations. */
40289   #define I3CCORE_CORE_QUEUESTATUSLEVEL_CMDQUEUEEMPTYLOC_Pos (0UL) /*!< Position of CMDQUEUEEMPTYLOC field.                    */
40290   #define I3CCORE_CORE_QUEUESTATUSLEVEL_CMDQUEUEEMPTYLOC_Msk (0xFFUL << I3CCORE_CORE_QUEUESTATUSLEVEL_CMDQUEUEEMPTYLOC_Pos) /*!<
40291                                                                             Bit mask of CMDQUEUEEMPTYLOC field.*/
40292 
40293 /* RESPBUFBLR @Bits 8..15 : Response Buffer Level Value. */
40294   #define I3CCORE_CORE_QUEUESTATUSLEVEL_RESPBUFBLR_Pos (8UL) /*!< Position of RESPBUFBLR field.                                */
40295   #define I3CCORE_CORE_QUEUESTATUSLEVEL_RESPBUFBLR_Msk (0xFFUL << I3CCORE_CORE_QUEUESTATUSLEVEL_RESPBUFBLR_Pos) /*!< Bit mask of
40296                                                                             RESPBUFBLR field.*/
40297 
40298 /* IBIBUFBLR @Bits 16..23 : IBI Buffer Level Value. */
40299   #define I3CCORE_CORE_QUEUESTATUSLEVEL_IBIBUFBLR_Pos (16UL) /*!< Position of IBIBUFBLR field.                                 */
40300   #define I3CCORE_CORE_QUEUESTATUSLEVEL_IBIBUFBLR_Msk (0xFFUL << I3CCORE_CORE_QUEUESTATUSLEVEL_IBIBUFBLR_Pos) /*!< Bit mask of
40301                                                                             IBIBUFBLR field.*/
40302 
40303 /* IBISTSCNT @Bits 24..28 : IBI Buffer Status Count. */
40304   #define I3CCORE_CORE_QUEUESTATUSLEVEL_IBISTSCNT_Pos (24UL) /*!< Position of IBISTSCNT field.                                 */
40305   #define I3CCORE_CORE_QUEUESTATUSLEVEL_IBISTSCNT_Msk (0x1FUL << I3CCORE_CORE_QUEUESTATUSLEVEL_IBISTSCNT_Pos) /*!< Bit mask of
40306                                                                             IBISTSCNT field.*/
40307 
40308 
40309 /* I3CCORE_CORE_DATABUFFERSTATUSLEVEL: Data Buffer Status Level Register. */
40310   #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_ResetValue (0x00000040UL) /*!< Reset value of DATABUFFERSTATUSLEVEL register.     */
40311 
40312 /* TXBUFEMPTYLOC @Bits 0..7 : Transmit Buffer Empty Level Value. */
40313   #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_TXBUFEMPTYLOC_Pos (0UL) /*!< Position of TXBUFEMPTYLOC field.                     */
40314   #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_TXBUFEMPTYLOC_Msk (0xFFUL << I3CCORE_CORE_DATABUFFERSTATUSLEVEL_TXBUFEMPTYLOC_Pos)
40315                                                                             /*!< Bit mask of TXBUFEMPTYLOC field.*/
40316 
40317 /* RXBUFBLR @Bits 16..23 : Receive Buffer Level Value. */
40318   #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_RXBUFBLR_Pos (16UL) /*!< Position of RXBUFBLR field.                              */
40319   #define I3CCORE_CORE_DATABUFFERSTATUSLEVEL_RXBUFBLR_Msk (0xFFUL << I3CCORE_CORE_DATABUFFERSTATUSLEVEL_RXBUFBLR_Pos) /*!< Bit
40320                                                                             mask of RXBUFBLR field.*/
40321 
40322 
40323 /* I3CCORE_CORE_PRESENTSTATEM: The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register
40324                                 (Master). */
40325 
40326   #define I3CCORE_CORE_PRESENTSTATEM_ResetValue (0x10000003UL) /*!< Reset value of PRESENTSTATEM register.                     */
40327 
40328 /* SCLLINESIGNALLEVEL @Bit 0 : This bit is used to check the SCL line level to recover from errors and for debugging. */
40329   #define I3CCORE_CORE_PRESENTSTATEM_SCLLINESIGNALLEVEL_Pos (0UL) /*!< Position of SCLLINESIGNALLEVEL field.                   */
40330   #define I3CCORE_CORE_PRESENTSTATEM_SCLLINESIGNALLEVEL_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATEM_SCLLINESIGNALLEVEL_Pos) /*!<
40331                                                                             Bit mask of SCLLINESIGNALLEVEL field.*/
40332 
40333 /* SDALINESIGNALLEVEL @Bit 1 : This bit is used to check the SDA line level to recover from errors and for debugging. */
40334   #define I3CCORE_CORE_PRESENTSTATEM_SDALINESIGNALLEVEL_Pos (1UL) /*!< Position of SDALINESIGNALLEVEL field.                   */
40335   #define I3CCORE_CORE_PRESENTSTATEM_SDALINESIGNALLEVEL_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATEM_SDALINESIGNALLEVEL_Pos) /*!<
40336                                                                             Bit mask of SDALINESIGNALLEVEL field.*/
40337 
40338 /* CURRENTMASTER @Bit 2 : This Bit is used to check whether the Master is Current Master or not. */
40339   #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Pos (2UL) /*!< Position of CURRENTMASTER field.                             */
40340   #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Pos) /*!< Bit mask of
40341                                                                             CURRENTMASTER field.*/
40342   #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Min (0x0UL) /*!< Min enumerator value of CURRENTMASTER field.               */
40343   #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_Max (0x1UL) /*!< Max enumerator value of CURRENTMASTER field.               */
40344   #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_NOT_BUS_OWNER (0x0UL) /*!< Master is not Current Master                     */
40345   #define I3CCORE_CORE_PRESENTSTATEM_CURRENTMASTER_BUS_OWNER (0x1UL) /*!< Master is Current Master                             */
40346 
40347 /* CMTFRSTS @Bits 8..13 : Transfer Type Status */
40348   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Pos (8UL) /*!< Position of CMTFRSTS field.                                       */
40349   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Msk (0x3FUL << I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Pos) /*!< Bit mask of CMTFRSTS
40350                                                                             field.*/
40351   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Min (0x0UL) /*!< Min enumerator value of CMTFRSTS field.                         */
40352   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_Max (0xFUL) /*!< Max enumerator value of CMTFRSTS field.                         */
40353   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_IDLE (0x00UL) /*!< Controller is in Idle state, waiting for commands from
40354                                                                  application or Slave initated In-band Interrupt.*/
40355   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_BCCCWTRANSFER (0x01UL) /*!< Broadcast CCC Write Transfer.                        */
40356   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_DCCCWTRANSFER (0x02UL) /*!< Directed CCC Write Transfer.                         */
40357   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_DCCCRTRANSFER (0x03UL) /*!< Directed CCC Read Transfer.                          */
40358   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_ENTDAATRANSFER (0x04UL) /*!< ENTDAA Address Assignment Transfer.                 */
40359   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SETDASATRANSFER (0x05UL) /*!< SETDASA Address Assignment Transfer.               */
40360   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SDRWTRANSFER (0x06UL) /*!< Private I3C SDR Write Transfer.                       */
40361   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SDRRTRANSFER (0x07UL) /*!< Private I3C SDR Read Transfer.                        */
40362   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SDRWTRANSFERI2C (0x08UL) /*!< Private I2C SDR Write Transfer.                    */
40363   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_SDRRTRANSFERI2C (0x09UL) /*!< Private I2C SDR Read Transfer.                     */
40364   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_TSWTRANSFER (0x0AUL) /*!< Private HDR Ternary Symbol(TS) Write Transfer.         */
40365   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_TSRTRANSFER (0x0BUL) /*!< Private HDR Ternary Symbol(TS) Read Transfer.          */
40366   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_DDRWTRANSFER (0x0CUL) /*!< Private HDR Double-Data Rate(DDR) Write Transfer.     */
40367   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_DDRRTRANSFER (0x0DUL) /*!< Private HDR Double-Data Rate(DDR) Read Transfer.      */
40368   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_IBITRANSFER (0x0EUL) /*!< Servicing In-Band Interrupt Transfer.                  */
40369   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTS_HALT (0x0FUL) /*!< Halt state. Controller is in Halt State, waiting for the
40370                                                                  application to resume through DEVICE_CTRL Register.*/
40371 
40372 /* CMTFRSTSTS @Bits 16..21 : Current Master Transfer State Status. */
40373   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Pos (16UL) /*!< Position of CMTFRSTSTS field.                                  */
40374   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Msk (0x3FUL << I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Pos) /*!< Bit mask of
40375                                                                             CMTFRSTSTS field.*/
40376   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Min (0x0UL) /*!< Min enumerator value of CMTFRSTSTS field.                     */
40377   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_Max (0x13UL) /*!< Max enumerator value of CMTFRSTSTS field.                    */
40378   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_IDLE (0x00UL) /*!< Controller is Idle state, waiting for commands from
40379                                                                    application or Slave initated In-band Interrupt.*/
40380   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_START (0x01UL) /*!< START Generation State.                                    */
40381   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_RESTART (0x02UL) /*!< RESTART Generation State.                                */
40382   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_STOP (0x03UL) /*!< STOP Genration State.                                       */
40383   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_STARTH (0x04UL) /*!< START Hold Generation for the Slave Initiated START State.*/
40384   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_BWADDRGEN (0x05UL) /*!< Broadcast Write Address Header(7h7E,W) Generation
40385                                                                         State.*/
40386   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_BRADDRGEN (0x06UL) /*!< Broadcast Read Address Header(7h7E,R) Generation State.*/
40387   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_DAA (0x07UL) /*!< Dynamic Address Assignment State.                            */
40388   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_ADDRGEN (0x08UL) /*!< Slave Address Generation State.                          */
40389   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_CCCBYTEGEN (0x0BUL) /*!< CCC Byte Generation State.                            */
40390   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_HDRCMDGEN (0x0CUL) /*!< HDR Command Generation State.                          */
40391   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_WTRANSFER (0x0DUL) /*!< Write Data Transfer State.                             */
40392   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_RTRANSFER (0x0EUL) /*!< Read Data Transfer State.                              */
40393   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_RIBI (0x0FUL) /*!< In-Band Interrupt(SIR) Read Data State.                     */
40394   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_IBIAUTODISABLE (0x10UL) /*!< In-Band Interrupt Auto-Disable State              */
40395   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_DDRCRCGEN (0x11UL) /*!< HDR-DDR CRC Data Generation/Receive State.             */
40396   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_CLKEXTEND (0x12UL) /*!< Clock Extension State.                                 */
40397   #define I3CCORE_CORE_PRESENTSTATEM_CMTFRSTSTS_HALT (0x13UL) /*!< Halt State.                                                 */
40398 
40399 /* CMDTID @Bits 24..27 : This field reflects the Transaction-ID of the current executing command. */
40400   #define I3CCORE_CORE_PRESENTSTATEM_CMDTID_Pos (24UL) /*!< Position of CMDTID field.                                          */
40401   #define I3CCORE_CORE_PRESENTSTATEM_CMDTID_Msk (0xFUL << I3CCORE_CORE_PRESENTSTATEM_CMDTID_Pos) /*!< Bit mask of CMDTID field.*/
40402 
40403 /* MASTERIDLE @Bit 28 : This field reflects whether the Master Controller is in Idle state or not. */
40404   #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Pos (28UL) /*!< Position of MASTERIDLE field.                                  */
40405   #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Pos) /*!< Bit mask of
40406                                                                             MASTERIDLE field.*/
40407   #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Min (0x0UL) /*!< Min enumerator value of MASTERIDLE field.                     */
40408   #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_Max (0x1UL) /*!< Max enumerator value of MASTERIDLE field.                     */
40409   #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_MST_NOT_IDLE (0x0UL) /*!< (unspecified)                                        */
40410   #define I3CCORE_CORE_PRESENTSTATEM_MASTERIDLE_MST_IDLE (0x1UL) /*!< (unspecified)                                            */
40411 
40412 
40413 /* I3CCORE_CORE_PRESENTSTATES: The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register
40414                                 (Slave). */
40415 
40416   #define I3CCORE_CORE_PRESENTSTATES_ResetValue (0x10000003UL) /*!< Reset value of PRESENTSTATES register.                     */
40417 
40418 /* SCLLINESIGNALLEVEL @Bit 0 : This bit is used to check the SCL line level to recover from errors and for debugging. */
40419   #define I3CCORE_CORE_PRESENTSTATES_SCLLINESIGNALLEVEL_Pos (0UL) /*!< Position of SCLLINESIGNALLEVEL field.                   */
40420   #define I3CCORE_CORE_PRESENTSTATES_SCLLINESIGNALLEVEL_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATES_SCLLINESIGNALLEVEL_Pos) /*!<
40421                                                                             Bit mask of SCLLINESIGNALLEVEL field.*/
40422 
40423 /* SDALINESIGNALLEVEL @Bit 1 : This bit is used to check the SDA line level to recover from errors and for debugging. */
40424   #define I3CCORE_CORE_PRESENTSTATES_SDALINESIGNALLEVEL_Pos (1UL) /*!< Position of SDALINESIGNALLEVEL field.                   */
40425   #define I3CCORE_CORE_PRESENTSTATES_SDALINESIGNALLEVEL_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATES_SDALINESIGNALLEVEL_Pos) /*!<
40426                                                                             Bit mask of SDALINESIGNALLEVEL field.*/
40427 
40428 /* CURRENTMASTER @Bit 2 : This Bit is used to check whether the Master is Current Master or not. */
40429   #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Pos (2UL) /*!< Position of CURRENTMASTER field.                             */
40430   #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Pos) /*!< Bit mask of
40431                                                                             CURRENTMASTER field.*/
40432   #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Min (0x0UL) /*!< Min enumerator value of CURRENTMASTER field.               */
40433   #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_Max (0x1UL) /*!< Max enumerator value of CURRENTMASTER field.               */
40434   #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_NOT_BUS_OWNER (0x0UL) /*!< Master is not Current Master                     */
40435   #define I3CCORE_CORE_PRESENTSTATES_CURRENTMASTER_BUS_OWNER (0x1UL) /*!< Master is Current Master                             */
40436 
40437 /* CMTFRSTS @Bits 8..13 : Transfer Type Status */
40438   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Pos (8UL) /*!< Position of CMTFRSTS field.                                       */
40439   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Msk (0x3FUL << I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Pos) /*!< Bit mask of CMTFRSTS
40440                                                                             field.*/
40441   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Min (0x0UL) /*!< Min enumerator value of CMTFRSTS field.                         */
40442   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_Max (0x6UL) /*!< Max enumerator value of CMTFRSTS field.                         */
40443   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEIDLE (0x00UL) /*!< Controller is in Idle state.                             */
40444   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEHOTJOIN (0x01UL) /*!< Hot-Join transfer state.                              */
40445   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEIBITRANSFER (0x02UL) /*!< IBI transfer state.                               */
40446   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEWTRANSFER (0x03UL) /*!< Master write transfer ongoing.                      */
40447   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVERPREFETCH (0x04UL) /*!< Read data prefetch state.                           */
40448   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVERTRANSFER (0x05UL) /*!< Master read transfer ongoing.                       */
40449   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTS_SLAVEHALT (0x06UL) /*!< Slave controller in Halt State waiting for resume from
40450                                                                       application.*/
40451 
40452 /* CMTFRSTSTS @Bits 16..21 : Current Master Transfer State Status. */
40453   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTSTS_Pos (16UL) /*!< Position of CMTFRSTSTS field.                                  */
40454   #define I3CCORE_CORE_PRESENTSTATES_CMTFRSTSTS_Msk (0x3FUL << I3CCORE_CORE_PRESENTSTATES_CMTFRSTSTS_Pos) /*!< Bit mask of
40455                                                                             CMTFRSTSTS field.*/
40456 
40457 /* CMDTID @Bits 24..27 : This field reflects the Transaction-ID of the current executing command. */
40458   #define I3CCORE_CORE_PRESENTSTATES_CMDTID_Pos (24UL) /*!< Position of CMDTID field.                                          */
40459   #define I3CCORE_CORE_PRESENTSTATES_CMDTID_Msk (0xFUL << I3CCORE_CORE_PRESENTSTATES_CMDTID_Pos) /*!< Bit mask of CMDTID field.*/
40460 
40461 /* MASTERIDLE @Bit 28 : This field reflects whether the Master Controller is in Idle state or not. */
40462   #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Pos (28UL) /*!< Position of MASTERIDLE field.                                  */
40463   #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Msk (0x1UL << I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Pos) /*!< Bit mask of
40464                                                                             MASTERIDLE field.*/
40465   #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Min (0x0UL) /*!< Min enumerator value of MASTERIDLE field.                     */
40466   #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_Max (0x1UL) /*!< Max enumerator value of MASTERIDLE field.                     */
40467   #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_MST_NOT_IDLE (0x0UL) /*!< (unspecified)                                        */
40468   #define I3CCORE_CORE_PRESENTSTATES_MASTERIDLE_MST_IDLE (0x1UL) /*!< (unspecified)                                            */
40469 
40470 
40471 /* I3CCORE_CORE_CCCDEVICESTATUS: Device Operating Status Register. */
40472   #define I3CCORE_CORE_CCCDEVICESTATUS_ResetValue (0x00000000UL) /*!< Reset value of CCCDEVICESTATUS register.                 */
40473 
40474 /* PENDINGINTR @Bits 0..3 : Pending Interrupt */
40475   #define I3CCORE_CORE_CCCDEVICESTATUS_PENDINGINTR_Pos (0UL) /*!< Position of PENDINGINTR field.                               */
40476   #define I3CCORE_CORE_CCCDEVICESTATUS_PENDINGINTR_Msk (0xFUL << I3CCORE_CORE_CCCDEVICESTATUS_PENDINGINTR_Pos) /*!< Bit mask of
40477                                                                             PENDINGINTR field.*/
40478 
40479 /* PROTOCOLERR @Bit 5 : Protocol Error */
40480   #define I3CCORE_CORE_CCCDEVICESTATUS_PROTOCOLERR_Pos (5UL) /*!< Position of PROTOCOLERR field.                               */
40481   #define I3CCORE_CORE_CCCDEVICESTATUS_PROTOCOLERR_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_PROTOCOLERR_Pos) /*!< Bit mask of
40482                                                                             PROTOCOLERR field.*/
40483 
40484 /* ACTIVITYMODE @Bits 6..7 : Activity Mode */
40485   #define I3CCORE_CORE_CCCDEVICESTATUS_ACTIVITYMODE_Pos (6UL) /*!< Position of ACTIVITYMODE field.                             */
40486   #define I3CCORE_CORE_CCCDEVICESTATUS_ACTIVITYMODE_Msk (0x3UL << I3CCORE_CORE_CCCDEVICESTATUS_ACTIVITYMODE_Pos) /*!< Bit mask
40487                                                                             of ACTIVITYMODE field.*/
40488 
40489 /* UNDERFLOWERR @Bit 8 : Underflow error */
40490   #define I3CCORE_CORE_CCCDEVICESTATUS_UNDERFLOWERR_Pos (8UL) /*!< Position of UNDERFLOWERR field.                             */
40491   #define I3CCORE_CORE_CCCDEVICESTATUS_UNDERFLOWERR_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_UNDERFLOWERR_Pos) /*!< Bit mask
40492                                                                             of UNDERFLOWERR field.*/
40493 
40494 /* SLAVEBUSY @Bit 9 : Slave Busy */
40495   #define I3CCORE_CORE_CCCDEVICESTATUS_SLAVEBUSY_Pos (9UL) /*!< Position of SLAVEBUSY field.                                   */
40496   #define I3CCORE_CORE_CCCDEVICESTATUS_SLAVEBUSY_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_SLAVEBUSY_Pos) /*!< Bit mask of
40497                                                                             SLAVEBUSY field.*/
40498 
40499 /* OVERFLOWERR @Bit 10 : Overflow Error */
40500   #define I3CCORE_CORE_CCCDEVICESTATUS_OVERFLOWERR_Pos (10UL) /*!< Position of OVERFLOWERR field.                              */
40501   #define I3CCORE_CORE_CCCDEVICESTATUS_OVERFLOWERR_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_OVERFLOWERR_Pos) /*!< Bit mask of
40502                                                                             OVERFLOWERR field.*/
40503 
40504 /* DATANOTREADY @Bit 11 : Data not ready */
40505   #define I3CCORE_CORE_CCCDEVICESTATUS_DATANOTREADY_Pos (11UL) /*!< Position of DATANOTREADY field.                            */
40506   #define I3CCORE_CORE_CCCDEVICESTATUS_DATANOTREADY_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_DATANOTREADY_Pos) /*!< Bit mask
40507                                                                             of DATANOTREADY field.*/
40508 
40509 /* BUFFERNOTAVAIL @Bit 12 : Buffer not available */
40510   #define I3CCORE_CORE_CCCDEVICESTATUS_BUFFERNOTAVAIL_Pos (12UL) /*!< Position of BUFFERNOTAVAIL field.                        */
40511   #define I3CCORE_CORE_CCCDEVICESTATUS_BUFFERNOTAVAIL_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_BUFFERNOTAVAIL_Pos) /*!< Bit
40512                                                                             mask of BUFFERNOTAVAIL field.*/
40513 
40514 /* FRAMEERROR @Bit 13 : Frame Error */
40515   #define I3CCORE_CORE_CCCDEVICESTATUS_FRAMEERROR_Pos (13UL) /*!< Position of FRAMEERROR field.                                */
40516   #define I3CCORE_CORE_CCCDEVICESTATUS_FRAMEERROR_Msk (0x1UL << I3CCORE_CORE_CCCDEVICESTATUS_FRAMEERROR_Pos) /*!< Bit mask of
40517                                                                             FRAMEERROR field.*/
40518 
40519 
40520 /* I3CCORE_CORE_DEVICEADDRTABLEPOINTER: Pointer for Device Address Table */
40521   #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_ResetValue (0x000A02C0UL) /*!< Reset value of DEVICEADDRTABLEPOINTER register.   */
40522 
40523 /* PDEVADDRTABLESTARTADDR @Bits 0..15 : Start Address of Device Address Table. */
40524   #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_PDEVADDRTABLESTARTADDR_Pos (0UL) /*!< Position of PDEVADDRTABLESTARTADDR field.  */
40525   #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_PDEVADDRTABLESTARTADDR_Msk (0xFFFFUL << I3CCORE_CORE_DEVICEADDRTABLEPOINTER_PDEVADDRTABLESTARTADDR_Pos)
40526                                                                             /*!< Bit mask of PDEVADDRTABLESTARTADDR field.*/
40527 
40528 /* DEVADDRTABLEDEPTH @Bits 16..31 : Depth of Device Address Table */
40529   #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_DEVADDRTABLEDEPTH_Pos (16UL) /*!< Position of DEVADDRTABLEDEPTH field.           */
40530   #define I3CCORE_CORE_DEVICEADDRTABLEPOINTER_DEVADDRTABLEDEPTH_Msk (0xFFFFUL << I3CCORE_CORE_DEVICEADDRTABLEPOINTER_DEVADDRTABLEDEPTH_Pos)
40531                                                                             /*!< Bit mask of DEVADDRTABLEDEPTH field.*/
40532 
40533 
40534 /* I3CCORE_CORE_DEVCHARTABLEPOINTER: Pointer for Device Characteristics Table */
40535   #define I3CCORE_CORE_DEVCHARTABLEPOINTER_ResetValue (0x00028200UL) /*!< Reset value of DEVCHARTABLEPOINTER register.         */
40536 
40537 /* PDEVCHARTABLESTARTADDR @Bits 0..11 : Start Address of Device Characteristics Table. */
40538   #define I3CCORE_CORE_DEVCHARTABLEPOINTER_PDEVCHARTABLESTARTADDR_Pos (0UL) /*!< Position of PDEVCHARTABLESTARTADDR field.     */
40539   #define I3CCORE_CORE_DEVCHARTABLEPOINTER_PDEVCHARTABLESTARTADDR_Msk (0xFFFUL << I3CCORE_CORE_DEVCHARTABLEPOINTER_PDEVCHARTABLESTARTADDR_Pos)
40540                                                                             /*!< Bit mask of PDEVCHARTABLESTARTADDR field.*/
40541 
40542 /* DEVCHARTABLEDEPTH @Bits 12..18 : Depth of Device Characteristics Table */
40543   #define I3CCORE_CORE_DEVCHARTABLEPOINTER_DEVCHARTABLEDEPTH_Pos (12UL) /*!< Position of DEVCHARTABLEDEPTH field.              */
40544   #define I3CCORE_CORE_DEVCHARTABLEPOINTER_DEVCHARTABLEDEPTH_Msk (0x7FUL << I3CCORE_CORE_DEVCHARTABLEPOINTER_DEVCHARTABLEDEPTH_Pos)
40545                                                                             /*!< Bit mask of DEVCHARTABLEDEPTH field.*/
40546 
40547 /* PRESENTDEVCHARTABLEINDX @Bits 19..22 : Current index of Device Characteristics Table. */
40548   #define I3CCORE_CORE_DEVCHARTABLEPOINTER_PRESENTDEVCHARTABLEINDX_Pos (19UL) /*!< Position of PRESENTDEVCHARTABLEINDX field.  */
40549   #define I3CCORE_CORE_DEVCHARTABLEPOINTER_PRESENTDEVCHARTABLEINDX_Msk (0xFUL << I3CCORE_CORE_DEVCHARTABLEPOINTER_PRESENTDEVCHARTABLEINDX_Pos)
40550                                                                             /*!< Bit mask of PRESENTDEVCHARTABLEINDX field.*/
40551 
40552 
40553 /* I3CCORE_CORE_VENDORSPECIFICREGPOINTER: Pointer for Vendor Specific Registers. */
40554   #define I3CCORE_CORE_VENDORSPECIFICREGPOINTER_ResetValue (0x000000B0UL) /*!< Reset value of VENDORSPECIFICREGPOINTER
40555                                                                             register.*/
40556 
40557 /* PVENDORREGSTARTADDR @Bits 0..15 : Start Address of Vendor specific registers. */
40558   #define I3CCORE_CORE_VENDORSPECIFICREGPOINTER_PVENDORREGSTARTADDR_Pos (0UL) /*!< Position of PVENDORREGSTARTADDR field.      */
40559   #define I3CCORE_CORE_VENDORSPECIFICREGPOINTER_PVENDORREGSTARTADDR_Msk (0xFFFFUL << I3CCORE_CORE_VENDORSPECIFICREGPOINTER_PVENDORREGSTARTADDR_Pos)
40560                                                                             /*!< Bit mask of PVENDORREGSTARTADDR field.*/
40561 
40562 
40563 /* I3CCORE_CORE_SLVMIPIIDVALUE: I3C MIPI Manufacturer ID Register. */
40564   #define I3CCORE_CORE_SLVMIPIIDVALUE_ResetValue (0x00000000UL) /*!< Reset value of SLVMIPIIDVALUE register.                   */
40565 
40566 /* SLVPROVIDSEL @Bit 0 : Specifies the Provisional ID Type Selector (PID[32]). */
40567   #define I3CCORE_CORE_SLVMIPIIDVALUE_SLVPROVIDSEL_Pos (0UL) /*!< Position of SLVPROVIDSEL field.                              */
40568   #define I3CCORE_CORE_SLVMIPIIDVALUE_SLVPROVIDSEL_Msk (0x1UL << I3CCORE_CORE_SLVMIPIIDVALUE_SLVPROVIDSEL_Pos) /*!< Bit mask of
40569                                                                             SLVPROVIDSEL field.*/
40570 
40571 /* SLVMIPIMFGID @Bits 1..15 : Specifies the MIPI Manufacturer ID. */
40572   #define I3CCORE_CORE_SLVMIPIIDVALUE_SLVMIPIMFGID_Pos (1UL) /*!< Position of SLVMIPIMFGID field.                              */
40573   #define I3CCORE_CORE_SLVMIPIIDVALUE_SLVMIPIMFGID_Msk (0x7FFFUL << I3CCORE_CORE_SLVMIPIIDVALUE_SLVMIPIMFGID_Pos) /*!< Bit mask
40574                                                                             of SLVMIPIMFGID field.*/
40575 
40576 
40577 /* I3CCORE_CORE_SLVPIDVALUE: I3C Normal Provisional ID Register. */
40578   #define I3CCORE_CORE_SLVPIDVALUE_ResetValue (0x00000000UL) /*!< Reset value of SLVPIDVALUE register.                         */
40579 
40580 /* SLVPIDDCR @Bits 0..11 : Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0]). */
40581   #define I3CCORE_CORE_SLVPIDVALUE_SLVPIDDCR_Pos (0UL) /*!< Position of SLVPIDDCR field.                                       */
40582   #define I3CCORE_CORE_SLVPIDVALUE_SLVPIDDCR_Msk (0xFFFUL << I3CCORE_CORE_SLVPIDVALUE_SLVPIDDCR_Pos) /*!< Bit mask of SLVPIDDCR
40583                                                                             field.*/
40584 
40585 /* SLVINSTID @Bits 12..15 : This field is used to program the instance ID of the Slave. */
40586   #define I3CCORE_CORE_SLVPIDVALUE_SLVINSTID_Pos (12UL) /*!< Position of SLVINSTID field.                                      */
40587   #define I3CCORE_CORE_SLVPIDVALUE_SLVINSTID_Msk (0xFUL << I3CCORE_CORE_SLVPIDVALUE_SLVINSTID_Pos) /*!< Bit mask of SLVINSTID
40588                                                                             field.*/
40589 
40590 /* SLVPARTID @Bits 16..31 : Specifies the Part ID of DWC_mipi_i3c device (PID[31:16]) */
40591   #define I3CCORE_CORE_SLVPIDVALUE_SLVPARTID_Pos (16UL) /*!< Position of SLVPARTID field.                                      */
40592   #define I3CCORE_CORE_SLVPIDVALUE_SLVPARTID_Msk (0xFFFFUL << I3CCORE_CORE_SLVPIDVALUE_SLVPARTID_Pos) /*!< Bit mask of SLVPARTID
40593                                                                             field.*/
40594 
40595 
40596 /* I3CCORE_CORE_SLVCHARCTRL: I3C Slave Characteristic Register. */
40597   #define I3CCORE_CORE_SLVCHARCTRL_ResetValue (0x00070062UL) /*!< Reset value of SLVCHARCTRL register.                         */
40598 
40599 /* MAXDATASPEEDLIMIT @Bit 0 : Max Data Speed Limitation field in Bus Characteristic Register (BCR[0]). */
40600   #define I3CCORE_CORE_SLVCHARCTRL_MAXDATASPEEDLIMIT_Pos (0UL) /*!< Position of MAXDATASPEEDLIMIT field.                       */
40601   #define I3CCORE_CORE_SLVCHARCTRL_MAXDATASPEEDLIMIT_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_MAXDATASPEEDLIMIT_Pos) /*!< Bit mask
40602                                                                             of MAXDATASPEEDLIMIT field.*/
40603 
40604 /* IBIREQUESTCAPABLE @Bit 1 : IBI Request Capable field in Bus Characteristic Register (BCR[1]). */
40605   #define I3CCORE_CORE_SLVCHARCTRL_IBIREQUESTCAPABLE_Pos (1UL) /*!< Position of IBIREQUESTCAPABLE field.                       */
40606   #define I3CCORE_CORE_SLVCHARCTRL_IBIREQUESTCAPABLE_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_IBIREQUESTCAPABLE_Pos) /*!< Bit mask
40607                                                                             of IBIREQUESTCAPABLE field.*/
40608 
40609 /* IBIPAYLOAD @Bit 2 : IBI Payload field in Bus Characteristic Register (BCR[2]). */
40610   #define I3CCORE_CORE_SLVCHARCTRL_IBIPAYLOAD_Pos (2UL) /*!< Position of IBIPAYLOAD field.                                     */
40611   #define I3CCORE_CORE_SLVCHARCTRL_IBIPAYLOAD_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_IBIPAYLOAD_Pos) /*!< Bit mask of IBIPAYLOAD
40612                                                                             field.*/
40613 
40614 /* OFFLINECAPABLE @Bit 3 : Offline Capable field in Bus Characteristic Register (BCR[3]). */
40615   #define I3CCORE_CORE_SLVCHARCTRL_OFFLINECAPABLE_Pos (3UL) /*!< Position of OFFLINECAPABLE field.                             */
40616   #define I3CCORE_CORE_SLVCHARCTRL_OFFLINECAPABLE_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_OFFLINECAPABLE_Pos) /*!< Bit mask of
40617                                                                             OFFLINECAPABLE field.*/
40618 
40619 /* BRIDGEIDENTIFIER @Bit 4 : Bridge Identifier field in Bus Characteristic Register (BCR[4]). */
40620   #define I3CCORE_CORE_SLVCHARCTRL_BRIDGEIDENTIFIER_Pos (4UL) /*!< Position of BRIDGEIDENTIFIER field.                         */
40621   #define I3CCORE_CORE_SLVCHARCTRL_BRIDGEIDENTIFIER_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_BRIDGEIDENTIFIER_Pos) /*!< Bit mask
40622                                                                             of BRIDGEIDENTIFIER field.*/
40623 
40624 /* HDRCAPABLE @Bit 5 : SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5]). */
40625   #define I3CCORE_CORE_SLVCHARCTRL_HDRCAPABLE_Pos (5UL) /*!< Position of HDRCAPABLE field.                                     */
40626   #define I3CCORE_CORE_SLVCHARCTRL_HDRCAPABLE_Msk (0x1UL << I3CCORE_CORE_SLVCHARCTRL_HDRCAPABLE_Pos) /*!< Bit mask of HDRCAPABLE
40627                                                                             field.*/
40628 
40629 /* DEVICEROLE @Bits 6..7 : Device Role field in Bus Characteristic Register (BCR[7:6]). */
40630   #define I3CCORE_CORE_SLVCHARCTRL_DEVICEROLE_Pos (6UL) /*!< Position of DEVICEROLE field.                                     */
40631   #define I3CCORE_CORE_SLVCHARCTRL_DEVICEROLE_Msk (0x3UL << I3CCORE_CORE_SLVCHARCTRL_DEVICEROLE_Pos) /*!< Bit mask of DEVICEROLE
40632                                                                             field.*/
40633 
40634 /* DCR @Bits 8..15 : I3C Device Characteristic Value. */
40635   #define I3CCORE_CORE_SLVCHARCTRL_DCR_Pos (8UL)     /*!< Position of DCR field.                                               */
40636   #define I3CCORE_CORE_SLVCHARCTRL_DCR_Msk (0xFFUL << I3CCORE_CORE_SLVCHARCTRL_DCR_Pos) /*!< Bit mask of DCR field.            */
40637 
40638 /* HDRCAP @Bits 16..23 : I3C Device HDR Capability Register Value. */
40639   #define I3CCORE_CORE_SLVCHARCTRL_HDRCAP_Pos (16UL) /*!< Position of HDRCAP field.                                            */
40640   #define I3CCORE_CORE_SLVCHARCTRL_HDRCAP_Msk (0xFFUL << I3CCORE_CORE_SLVCHARCTRL_HDRCAP_Pos) /*!< Bit mask of HDRCAP field.   */
40641 
40642 
40643 /* I3CCORE_CORE_SLVMAXLEN: I3C Max Write/Read Length Register. */
40644   #define I3CCORE_CORE_SLVMAXLEN_ResetValue (0x00FF00FFUL) /*!< Reset value of SLVMAXLEN register.                             */
40645 
40646 /* MWL @Bits 0..15 : I3C Device Max Write Length */
40647   #define I3CCORE_CORE_SLVMAXLEN_MWL_Pos (0UL)       /*!< Position of MWL field.                                               */
40648   #define I3CCORE_CORE_SLVMAXLEN_MWL_Msk (0xFFFFUL << I3CCORE_CORE_SLVMAXLEN_MWL_Pos) /*!< Bit mask of MWL field.              */
40649 
40650 /* MRL @Bits 16..31 : I3C Device Max Read Length. */
40651   #define I3CCORE_CORE_SLVMAXLEN_MRL_Pos (16UL)      /*!< Position of MRL field.                                               */
40652   #define I3CCORE_CORE_SLVMAXLEN_MRL_Msk (0xFFFFUL << I3CCORE_CORE_SLVMAXLEN_MRL_Pos) /*!< Bit mask of MRL field.              */
40653 
40654 
40655 /* I3CCORE_CORE_MAXREADTURNAROUND: MXDS Maximum Read Turnaround Time. */
40656   #define I3CCORE_CORE_MAXREADTURNAROUND_ResetValue (0x00000000UL) /*!< Reset value of MAXREADTURNAROUND register.             */
40657 
40658 /* MXDSMAXRDTURN @Bits 0..23 : Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Slave. */
40659   #define I3CCORE_CORE_MAXREADTURNAROUND_MXDSMAXRDTURN_Pos (0UL) /*!< Position of MXDSMAXRDTURN field.                         */
40660   #define I3CCORE_CORE_MAXREADTURNAROUND_MXDSMAXRDTURN_Msk (0xFFFFFFUL << I3CCORE_CORE_MAXREADTURNAROUND_MXDSMAXRDTURN_Pos) /*!<
40661                                                                             Bit mask of MXDSMAXRDTURN field.*/
40662 
40663 
40664 /* I3CCORE_CORE_MAXDATASPEED: The values in this register are returned by the slave as GETACCMST CCC data. */
40665   #define I3CCORE_CORE_MAXDATASPEED_ResetValue (0x00000000UL) /*!< Reset value of MAXDATASPEED register.                       */
40666 
40667 /* MXDSMAXWRSPEED @Bits 0..2 : Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device to
40668                                DWC_mipi_i3c Slave device */
40669 
40670   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Pos (0UL) /*!< Position of MXDSMAXWRSPEED field.                            */
40671   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Msk (0x7UL << I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Pos) /*!< Bit mask of
40672                                                                             MXDSMAXWRSPEED field.*/
40673   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Min (0x0UL) /*!< Min enumerator value of MXDSMAXWRSPEED field.              */
40674   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_Max (0x4UL) /*!< Max enumerator value of MXDSMAXWRSPEED field.              */
40675   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_12M5HZ (0x0UL) /*!< 12.5MHz                                                 */
40676   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_8MHZ (0x1UL) /*!< 8MHZ                                                      */
40677   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_6MHZ (0x2UL) /*!< 6MHz                                                      */
40678   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_4MHZ (0x3UL) /*!< 4MHz                                                      */
40679   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXWRSPEED_2MHZ (0x4UL) /*!< 2MHz                                                      */
40680 
40681 /* MXDSMAXRDSPEED @Bits 8..10 : Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c Slave Device
40682                                 to Master Device */
40683 
40684   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Pos (8UL) /*!< Position of MXDSMAXRDSPEED field.                            */
40685   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Msk (0x7UL << I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Pos) /*!< Bit mask of
40686                                                                             MXDSMAXRDSPEED field.*/
40687   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Min (0x0UL) /*!< Min enumerator value of MXDSMAXRDSPEED field.              */
40688   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_Max (0x4UL) /*!< Max enumerator value of MXDSMAXRDSPEED field.              */
40689   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_12M5HZ (0x0UL) /*!< 12.5MHz                                                 */
40690   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_8MHZ (0x1UL) /*!< 8MHZ                                                      */
40691   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_6MHZ (0x2UL) /*!< 6MHz                                                      */
40692   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_4MHZ (0x3UL) /*!< 4MHz                                                      */
40693   #define I3CCORE_CORE_MAXDATASPEED_MXDSMAXRDSPEED_2MHZ (0x4UL) /*!< 2MHz                                                      */
40694 
40695 /* MXDSCLKDATATURN @Bits 16..18 : Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave device */
40696   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Pos (16UL) /*!< Position of MXDSCLKDATATURN field.                         */
40697   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Msk (0x7UL << I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Pos) /*!< Bit mask
40698                                                                             of MXDSCLKDATATURN field.*/
40699   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Min (0x0UL) /*!< Min enumerator value of MXDSCLKDATATURN field.            */
40700   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_Max (0x4UL) /*!< Max enumerator value of MXDSCLKDATATURN field.            */
40701   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_8NS (0x0UL) /*!< 8ns                                                       */
40702   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_9NS (0x1UL) /*!< 9ns                                                       */
40703   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_10NS (0x2UL) /*!< 10ns                                                     */
40704   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_11NS (0x3UL) /*!< 11ns                                                     */
40705   #define I3CCORE_CORE_MAXDATASPEED_MXDSCLKDATATURN_12NS (0x4UL) /*!< 12ns                                                     */
40706 
40707 
40708 /* I3CCORE_CORE_SLVINTRREQ: This register is used in slave mode of operation. */
40709   #define I3CCORE_CORE_SLVINTRREQ_ResetValue (0x00000000UL) /*!< Reset value of SLVINTRREQ register.                           */
40710 
40711 /* SIR @Bit 0 : Slave Interrupt Request */
40712   #define I3CCORE_CORE_SLVINTRREQ_SIR_Pos (0UL)      /*!< Position of SIR field.                                               */
40713   #define I3CCORE_CORE_SLVINTRREQ_SIR_Msk (0x1UL << I3CCORE_CORE_SLVINTRREQ_SIR_Pos) /*!< Bit mask of SIR field.               */
40714 
40715 /* SIRCTRL @Bits 1..2 : Slave Interrupt Request Control */
40716   #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Pos (1UL)  /*!< Position of SIRCTRL field.                                           */
40717   #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Msk (0x3UL << I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Pos) /*!< Bit mask of SIRCTRL field.   */
40718   #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Min (0x0UL) /*!< Min enumerator value of SIRCTRL field.                              */
40719   #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_Max (0x0UL) /*!< Max enumerator value of SIRCTRL field.                              */
40720   #define I3CCORE_CORE_SLVINTRREQ_SIRCTRL_SEND (0x0UL) /*!< Send the Assigned Dynamic Address                                  */
40721 
40722 /* MR @Bit 3 : Master Request */
40723   #define I3CCORE_CORE_SLVINTRREQ_MR_Pos (3UL)       /*!< Position of MR field.                                                */
40724   #define I3CCORE_CORE_SLVINTRREQ_MR_Msk (0x1UL << I3CCORE_CORE_SLVINTRREQ_MR_Pos) /*!< Bit mask of MR field.                  */
40725 
40726 /* IBISTS @Bits 8..9 : IBI Completion Status */
40727   #define I3CCORE_CORE_SLVINTRREQ_IBISTS_Pos (8UL)   /*!< Position of IBISTS field.                                            */
40728   #define I3CCORE_CORE_SLVINTRREQ_IBISTS_Msk (0x3UL << I3CCORE_CORE_SLVINTRREQ_IBISTS_Pos) /*!< Bit mask of IBISTS field.      */
40729   #define I3CCORE_CORE_SLVINTRREQ_IBISTS_Min (0x1UL) /*!< Min enumerator value of IBISTS field.                                */
40730   #define I3CCORE_CORE_SLVINTRREQ_IBISTS_Max (0x3UL) /*!< Max enumerator value of IBISTS field.                                */
40731   #define I3CCORE_CORE_SLVINTRREQ_IBISTS_ACCEPTED (0x1UL) /*!< IBI accepted by the Master (ACK response received)              */
40732   #define I3CCORE_CORE_SLVINTRREQ_IBISTS_NOATTEMPT (0x3UL) /*!< IBI Not Attempted                                              */
40733 
40734 
40735 /* I3CCORE_CORE_SLVTSXSYMBLTIMING: TSP/TSL Symbol Timing Register */
40736   #define I3CCORE_CORE_SLVTSXSYMBLTIMING_ResetValue (0x0000003FUL) /*!< Reset value of SLVTSXSYMBLTIMING register.             */
40737 
40738 /* SLVTSXSYMBLCNT @Bits 0..5 : TSP/TSL Symbol Count Value. */
40739   #define I3CCORE_CORE_SLVTSXSYMBLTIMING_SLVTSXSYMBLCNT_Pos (0UL) /*!< Position of SLVTSXSYMBLCNT field.                       */
40740   #define I3CCORE_CORE_SLVTSXSYMBLTIMING_SLVTSXSYMBLCNT_Msk (0x3FUL << I3CCORE_CORE_SLVTSXSYMBLTIMING_SLVTSXSYMBLCNT_Pos) /*!<
40741                                                                             Bit mask of SLVTSXSYMBLCNT field.*/
40742 
40743 
40744 /* I3CCORE_CORE_DEVICECTRLEXTENDED: Device Control Extended register. */
40745   #define I3CCORE_CORE_DEVICECTRLEXTENDED_ResetValue (0x00000000UL) /*!< Reset value of DEVICECTRLEXTENDED register.           */
40746 
40747 /* DEVOPERATIONMODE @Bits 0..1 : This bit is used to select the Device Operation Mode before the controller is enabled. */
40748   #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Pos (0UL) /*!< Position of DEVOPERATIONMODE field.                  */
40749   #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Msk (0x3UL << I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Pos)
40750                                                                             /*!< Bit mask of DEVOPERATIONMODE field.*/
40751   #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Min (0x0UL) /*!< Min enumerator value of DEVOPERATIONMODE field.    */
40752   #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_Max (0x1UL) /*!< Max enumerator value of DEVOPERATIONMODE field.    */
40753   #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_MASTER (0x0UL) /*!< (unspecified)                                   */
40754   #define I3CCORE_CORE_DEVICECTRLEXTENDED_DEVOPERATIONMODE_SLAVE (0x1UL) /*!< (unspecified)                                    */
40755 
40756 /* REQMSTACKCTRL @Bit 3 : In Slave mode of operation, this bit serves as a control to ACK/NACK GETACCMST CCC from current
40757                           master. */
40758 
40759   #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Pos (3UL) /*!< Position of REQMSTACKCTRL field.                        */
40760   #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Msk (0x1UL << I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Pos) /*!<
40761                                                                             Bit mask of REQMSTACKCTRL field.*/
40762   #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Min (0x0UL) /*!< Min enumerator value of REQMSTACKCTRL field.          */
40763   #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_Max (0x1UL) /*!< Max enumerator value of REQMSTACKCTRL field.          */
40764   #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_ACK (0x0UL) /*!< ACK GETACCMST CCC                                     */
40765   #define I3CCORE_CORE_DEVICECTRLEXTENDED_REQMSTACKCTRL_NACK (0x1UL) /*!< NACK GETACCMST CCC                                   */
40766 
40767 
40768 /* I3CCORE_CORE_SCLI3CODTIMING: SCL I3C Open Drain Timing Register */
40769   #define I3CCORE_CORE_SCLI3CODTIMING_ResetValue (0x000A0010UL) /*!< Reset value of SCLI3CODTIMING register.                   */
40770 
40771 /* I3CODLCNT @Bits 0..7 : I3C Open Drain Low Count. */
40772   #define I3CCORE_CORE_SCLI3CODTIMING_I3CODLCNT_Pos (0UL) /*!< Position of I3CODLCNT field.                                    */
40773   #define I3CCORE_CORE_SCLI3CODTIMING_I3CODLCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI3CODTIMING_I3CODLCNT_Pos) /*!< Bit mask of
40774                                                                             I3CODLCNT field.*/
40775 
40776 /* I3CODHCNT @Bits 16..23 : I3C Open Drain High Count. */
40777   #define I3CCORE_CORE_SCLI3CODTIMING_I3CODHCNT_Pos (16UL) /*!< Position of I3CODHCNT field.                                   */
40778   #define I3CCORE_CORE_SCLI3CODTIMING_I3CODHCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI3CODTIMING_I3CODHCNT_Pos) /*!< Bit mask of
40779                                                                             I3CODHCNT field.*/
40780 
40781 
40782 /* I3CCORE_CORE_SCLI3CPPTIMING: SCL I3C Push Pull Timing Register */
40783   #define I3CCORE_CORE_SCLI3CPPTIMING_ResetValue (0x000A000AUL) /*!< Reset value of SCLI3CPPTIMING register.                   */
40784 
40785 /* I3CPPLCNT @Bits 0..7 : I3C Push Pull Low Count. */
40786   #define I3CCORE_CORE_SCLI3CPPTIMING_I3CPPLCNT_Pos (0UL) /*!< Position of I3CPPLCNT field.                                    */
40787   #define I3CCORE_CORE_SCLI3CPPTIMING_I3CPPLCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI3CPPTIMING_I3CPPLCNT_Pos) /*!< Bit mask of
40788                                                                             I3CPPLCNT field.*/
40789 
40790 /* I3CPPHCNT @Bits 16..23 : I3C Push Pull High Count. */
40791   #define I3CCORE_CORE_SCLI3CPPTIMING_I3CPPHCNT_Pos (16UL) /*!< Position of I3CPPHCNT field.                                   */
40792   #define I3CCORE_CORE_SCLI3CPPTIMING_I3CPPHCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI3CPPTIMING_I3CPPHCNT_Pos) /*!< Bit mask of
40793                                                                             I3CPPHCNT field.*/
40794 
40795 
40796 /* I3CCORE_CORE_SCLI2CFMTIMING: SCL I2C Fast Mode Timing Register */
40797   #define I3CCORE_CORE_SCLI2CFMTIMING_ResetValue (0x00100010UL) /*!< Reset value of SCLI2CFMTIMING register.                   */
40798 
40799 /* I2CFMLCNT @Bits 0..15 : I2C Fast Mode Low Count */
40800   #define I3CCORE_CORE_SCLI2CFMTIMING_I2CFMLCNT_Pos (0UL) /*!< Position of I2CFMLCNT field.                                    */
40801   #define I3CCORE_CORE_SCLI2CFMTIMING_I2CFMLCNT_Msk (0xFFFFUL << I3CCORE_CORE_SCLI2CFMTIMING_I2CFMLCNT_Pos) /*!< Bit mask of
40802                                                                             I2CFMLCNT field.*/
40803 
40804 /* I2CFMHCNT @Bits 16..31 : I2C Fast Mode High Count */
40805   #define I3CCORE_CORE_SCLI2CFMTIMING_I2CFMHCNT_Pos (16UL) /*!< Position of I2CFMHCNT field.                                   */
40806   #define I3CCORE_CORE_SCLI2CFMTIMING_I2CFMHCNT_Msk (0xFFFFUL << I3CCORE_CORE_SCLI2CFMTIMING_I2CFMHCNT_Pos) /*!< Bit mask of
40807                                                                             I2CFMHCNT field.*/
40808 
40809 
40810 /* I3CCORE_CORE_SCLI2CFMPTIMING: SCL I2C Fast Mode Plus Timing Register */
40811   #define I3CCORE_CORE_SCLI2CFMPTIMING_ResetValue (0x00100010UL) /*!< Reset value of SCLI2CFMPTIMING register.                 */
40812 
40813 /* I2CFMPLCNT @Bits 0..15 : I2C Fast Mode Plus Low Count */
40814   #define I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPLCNT_Pos (0UL) /*!< Position of I2CFMPLCNT field.                                 */
40815   #define I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPLCNT_Msk (0xFFFFUL << I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPLCNT_Pos) /*!< Bit mask of
40816                                                                             I2CFMPLCNT field.*/
40817 
40818 /* I2CFMPHCNT @Bits 16..23 : I2C Fast Mode Plus High Count */
40819   #define I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPHCNT_Pos (16UL) /*!< Position of I2CFMPHCNT field.                                */
40820   #define I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPHCNT_Msk (0xFFUL << I3CCORE_CORE_SCLI2CFMPTIMING_I2CFMPHCNT_Pos) /*!< Bit mask of
40821                                                                             I2CFMPHCNT field.*/
40822 
40823 
40824 /* I3CCORE_CORE_SCLEXTLCNTTIMING: SCL Extended Low Count Timing Register. */
40825   #define I3CCORE_CORE_SCLEXTLCNTTIMING_ResetValue (0x20202020UL) /*!< Reset value of SCLEXTLCNTTIMING register.               */
40826 
40827 /* I3CEXTLCNT1 @Bits 0..7 : I3C Extended Low Count Register 1 */
40828   #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT1_Pos (0UL) /*!< Position of I3CEXTLCNT1 field.                              */
40829   #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT1_Msk (0xFFUL << I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT1_Pos) /*!< Bit mask
40830                                                                             of I3CEXTLCNT1 field.*/
40831 
40832 /* I3CEXTLCNT2 @Bits 8..15 : I3C Extended Low Count Register 2 */
40833   #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT2_Pos (8UL) /*!< Position of I3CEXTLCNT2 field.                              */
40834   #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT2_Msk (0xFFUL << I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT2_Pos) /*!< Bit mask
40835                                                                             of I3CEXTLCNT2 field.*/
40836 
40837 /* I3CEXTLCNT3 @Bits 16..23 : I3C Extended Low Count Register 3 */
40838   #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT3_Pos (16UL) /*!< Position of I3CEXTLCNT3 field.                             */
40839   #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT3_Msk (0xFFUL << I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT3_Pos) /*!< Bit mask
40840                                                                             of I3CEXTLCNT3 field.*/
40841 
40842 /* I3CEXTLCNT4 @Bits 24..31 : I3C Extended Low Count Register 4 */
40843   #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT4_Pos (24UL) /*!< Position of I3CEXTLCNT4 field.                             */
40844   #define I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT4_Msk (0xFFUL << I3CCORE_CORE_SCLEXTLCNTTIMING_I3CEXTLCNT4_Pos) /*!< Bit mask
40845                                                                             of I3CEXTLCNT4 field.*/
40846 
40847 
40848 /* I3CCORE_CORE_SCLEXTTERMNLCNTTIMING: SCL Termination Bit Low Count Timing Register */
40849   #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_ResetValue (0x00030000UL) /*!< Reset value of SCLEXTTERMNLCNTTIMING register.     */
40850 
40851 /* I3CEXTTERMNLCNT @Bits 0..3 : I3C Read Termination Bit Low count. */
40852   #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CEXTTERMNLCNT_Pos (0UL) /*!< Position of I3CEXTTERMNLCNT field.                 */
40853   #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CEXTTERMNLCNT_Msk (0xFUL << I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CEXTTERMNLCNT_Pos)
40854                                                                             /*!< Bit mask of I3CEXTTERMNLCNT field.*/
40855 
40856 /* I3CTSSKEWCNT @Bits 16..19 : I3C HDR Ternary Skew Count. */
40857   #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CTSSKEWCNT_Pos (16UL) /*!< Position of I3CTSSKEWCNT field.                      */
40858   #define I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CTSSKEWCNT_Msk (0xFUL << I3CCORE_CORE_SCLEXTTERMNLCNTTIMING_I3CTSSKEWCNT_Pos)
40859                                                                             /*!< Bit mask of I3CTSSKEWCNT field.*/
40860 
40861 
40862 /* I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING: SDA Hold and Mode Switch Delay Timing Register */
40863   #define I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING_ResetValue (0x00010000UL) /*!< Reset value of SDAHOLDSWITCHDLYTIMING register.   */
40864 
40865 /* SDATXHOLD @Bits 16..18 : This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with
40866                             */
40867 
40868   #define I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING_SDATXHOLD_Pos (16UL) /*!< Position of SDATXHOLD field.                           */
40869   #define I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING_SDATXHOLD_Msk (0x7UL << I3CCORE_CORE_SDAHOLDSWITCHDLYTIMING_SDATXHOLD_Pos) /*!<
40870                                                                             Bit mask of SDATXHOLD field.*/
40871 
40872 
40873 /* I3CCORE_CORE_BUSFREEAVAILTIMING: Bus Free and Available Timing Register */
40874   #define I3CCORE_CORE_BUSFREEAVAILTIMING_ResetValue (0x00200020UL) /*!< Reset value of BUSFREEAVAILTIMING register.           */
40875 
40876 /* BUSFREETIME @Bits 0..15 : This register field is used only in Master mode of operation */
40877   #define I3CCORE_CORE_BUSFREEAVAILTIMING_BUSFREETIME_Pos (0UL) /*!< Position of BUSFREETIME field.                            */
40878   #define I3CCORE_CORE_BUSFREEAVAILTIMING_BUSFREETIME_Msk (0xFFFFUL << I3CCORE_CORE_BUSFREEAVAILTIMING_BUSFREETIME_Pos) /*!< Bit
40879                                                                             mask of BUSFREETIME field.*/
40880 
40881 /* BUSAVAILABLETIME @Bits 16..31 : This register field is used only in Slave mode of operation */
40882   #define I3CCORE_CORE_BUSFREEAVAILTIMING_BUSAVAILABLETIME_Pos (16UL) /*!< Position of BUSAVAILABLETIME field.                 */
40883   #define I3CCORE_CORE_BUSFREEAVAILTIMING_BUSAVAILABLETIME_Msk (0xFFFFUL << I3CCORE_CORE_BUSFREEAVAILTIMING_BUSAVAILABLETIME_Pos)
40884                                                                             /*!< Bit mask of BUSAVAILABLETIME field.*/
40885 
40886 
40887 /* I3CCORE_CORE_BUSIDLETIMING: Bus Idle Timing Register */
40888   #define I3CCORE_CORE_BUSIDLETIMING_ResetValue (0x00000020UL) /*!< Reset value of BUSIDLETIMING register.                     */
40889 
40890 /* BUSIDLETIME @Bits 0..19 : Bus Idle Count Value. */
40891   #define I3CCORE_CORE_BUSIDLETIMING_BUSIDLETIME_Pos (0UL) /*!< Position of BUSIDLETIME field.                                 */
40892   #define I3CCORE_CORE_BUSIDLETIMING_BUSIDLETIME_Msk (0xFFFFFUL << I3CCORE_CORE_BUSIDLETIMING_BUSIDLETIME_Pos) /*!< Bit mask of
40893                                                                             BUSIDLETIME field.*/
40894 
40895 
40896 /* I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT: The SCL Low Master Extended Timeout register is used to define the duration of the SCL Low
40897                                       Bus Reset Pattern. */
40898 
40899   #define I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT_ResetValue (0x003567E0UL) /*!< Reset value of SCLLOWMSTEXTTIMEOUT register.         */
40900 
40901 /* SCLLOWMSTTIMEOUTCOUNT @Bits 0..25 : This count defines the number of core clock periods to count for generation of the SCL
40902                                        Low Bus Reset Pattern. */
40903 
40904   #define I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT_SCLLOWMSTTIMEOUTCOUNT_Pos (0UL) /*!< Position of SCLLOWMSTTIMEOUTCOUNT field.       */
40905   #define I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT_SCLLOWMSTTIMEOUTCOUNT_Msk (0x3FFFFFFUL << I3CCORE_CORE_SCLLOWMSTEXTTIMEOUT_SCLLOWMSTTIMEOUTCOUNT_Pos)
40906                                                                             /*!< Bit mask of SCLLOWMSTTIMEOUTCOUNT field.*/
40907 
40908 
40909 /* I3CCORE_CORE_I3CVERID: This register reflects the current release number of DWC_mipi_i3c */
40910   #define I3CCORE_CORE_I3CVERID_ResetValue (0x3130302AUL) /*!< Reset value of I3CVERID register.                               */
40911 
40912 /* I3CVERID @Bits 0..31 : Current release number */
40913   #define I3CCORE_CORE_I3CVERID_I3CVERID_Pos (0UL)   /*!< Position of I3CVERID field.                                          */
40914   #define I3CCORE_CORE_I3CVERID_I3CVERID_Msk (0xFFFFFFFFUL << I3CCORE_CORE_I3CVERID_I3CVERID_Pos) /*!< Bit mask of I3CVERID
40915                                                                             field.*/
40916 
40917 
40918 /* I3CCORE_CORE_I3CVERTYPE: This register reflects the current release type of DWC_mipi_i3c. */
40919   #define I3CCORE_CORE_I3CVERTYPE_ResetValue (0x6C633033UL) /*!< Reset value of I3CVERTYPE register.                           */
40920 
40921 /* I3CVERTYPE @Bits 0..31 : Current release type */
40922   #define I3CCORE_CORE_I3CVERTYPE_I3CVERTYPE_Pos (0UL) /*!< Position of I3CVERTYPE field.                                      */
40923   #define I3CCORE_CORE_I3CVERTYPE_I3CVERTYPE_Msk (0xFFFFFFFFUL << I3CCORE_CORE_I3CVERTYPE_I3CVERTYPE_Pos) /*!< Bit mask of
40924                                                                             I3CVERTYPE field.*/
40925 
40926 
40927 /* I3CCORE_CORE_QUEUESIZECAPABILITY: This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c. */
40928   #define I3CCORE_CORE_QUEUESIZECAPABILITY_ResetValue (0x00022355UL) /*!< Reset value of QUEUESIZECAPABILITY register.         */
40929 
40930 /* TXBUFSIZE @Bits 0..3 : Transmit Data Buffer Size */
40931   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Pos (0UL) /*!< Position of TXBUFSIZE field.                               */
40932   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Pos) /*!< Bit mask
40933                                                                             of TXBUFSIZE field.*/
40934   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Min (0x0UL) /*!< Min enumerator value of TXBUFSIZE field.                 */
40935   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_Max (0x5UL) /*!< Max enumerator value of TXBUFSIZE field.                 */
40936   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS                                              */
40937   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS                                              */
40938   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS                                              */
40939   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS                                            */
40940   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_32DWORD (0x4UL) /*!< 32 DWORDS                                            */
40941   #define I3CCORE_CORE_QUEUESIZECAPABILITY_TXBUFSIZE_64DWORD (0x5UL) /*!< 64 DWORDS                                            */
40942 
40943 /* RXBUFSIZE @Bits 4..7 : Receive Data Buffer Size */
40944   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Pos (4UL) /*!< Position of RXBUFSIZE field.                               */
40945   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Pos) /*!< Bit mask
40946                                                                             of RXBUFSIZE field.*/
40947   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Min (0x0UL) /*!< Min enumerator value of RXBUFSIZE field.                 */
40948   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_Max (0x5UL) /*!< Max enumerator value of RXBUFSIZE field.                 */
40949   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS                                              */
40950   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS                                              */
40951   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS                                              */
40952   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS                                            */
40953   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_32DWORD (0x4UL) /*!< 32 DWORDS                                            */
40954   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RXBUFSIZE_64DWORD (0x5UL) /*!< 64 DWORDS                                            */
40955 
40956 /* CMDBUFSIZE @Bits 8..11 : Command Queue Size */
40957   #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Pos (8UL) /*!< Position of CMDBUFSIZE field.                             */
40958   #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Pos) /*!< Bit
40959                                                                             mask of CMDBUFSIZE field.*/
40960   #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Min (0x0UL) /*!< Min enumerator value of CMDBUFSIZE field.               */
40961   #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_Max (0x3UL) /*!< Max enumerator value of CMDBUFSIZE field.               */
40962   #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS                                             */
40963   #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS                                             */
40964   #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS                                             */
40965   #define I3CCORE_CORE_QUEUESIZECAPABILITY_CMDBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS                                           */
40966 
40967 /* RESPBUFSIZE @Bits 12..15 : Response Queue Size */
40968   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Pos (12UL) /*!< Position of RESPBUFSIZE field.                          */
40969   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Pos) /*!< Bit
40970                                                                             mask of RESPBUFSIZE field.*/
40971   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Min (0x0UL) /*!< Min enumerator value of RESPBUFSIZE field.             */
40972   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_Max (0x3UL) /*!< Max enumerator value of RESPBUFSIZE field.             */
40973   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS                                            */
40974   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS                                            */
40975   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS                                            */
40976   #define I3CCORE_CORE_QUEUESIZECAPABILITY_RESPBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS                                          */
40977 
40978 /* IBIBUFSIZE @Bits 16..19 : IBI Queue Size */
40979   #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Pos (16UL) /*!< Position of IBIBUFSIZE field.                            */
40980   #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Msk (0xFUL << I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Pos) /*!< Bit
40981                                                                             mask of IBIBUFSIZE field.*/
40982   #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Min (0x0UL) /*!< Min enumerator value of IBIBUFSIZE field.               */
40983   #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_Max (0x3UL) /*!< Max enumerator value of IBIBUFSIZE field.               */
40984   #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_2DWORD (0x0UL) /*!< 2 DWORDS                                             */
40985   #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_4DWORD (0x1UL) /*!< 4 DWORDS                                             */
40986   #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_8DWORD (0x2UL) /*!< 8 DWORDS                                             */
40987   #define I3CCORE_CORE_QUEUESIZECAPABILITY_IBIBUFSIZE_16DWORD (0x3UL) /*!< 16 DWORDS                                           */
40988 
40989 
40990 /* I3CCORE_CORE_SECDEVCHARTABLE: Secondary Master Device Characteristic Table Location of Device [n] */
40991   #define I3CCORE_CORE_SECDEVCHARTABLE_MaxCount (32UL) /*!< Max size of SECDEVCHARTABLE[32] array.                             */
40992   #define I3CCORE_CORE_SECDEVCHARTABLE_MaxIndex (31UL) /*!< Max index of SECDEVCHARTABLE[32] array.                            */
40993   #define I3CCORE_CORE_SECDEVCHARTABLE_MinIndex (0UL) /*!< Min index of SECDEVCHARTABLE[32] array.                             */
40994   #define I3CCORE_CORE_SECDEVCHARTABLE_ResetValue (0x00000000UL) /*!< Reset value of SECDEVCHARTABLE[32] register.             */
40995 
40996 /* DYNAMICADDR @Bits 0..7 : The Dynamic Addr of Device [n] */
40997   #define I3CCORE_CORE_SECDEVCHARTABLE_DYNAMICADDR_Pos (0UL) /*!< Position of DYNAMICADDR field.                               */
40998   #define I3CCORE_CORE_SECDEVCHARTABLE_DYNAMICADDR_Msk (0xFFUL << I3CCORE_CORE_SECDEVCHARTABLE_DYNAMICADDR_Pos) /*!< Bit mask of
40999                                                                             DYNAMICADDR field.*/
41000 
41001 /* DCRTYPE @Bits 8..15 : The DCR TYPE of Device [n] */
41002   #define I3CCORE_CORE_SECDEVCHARTABLE_DCRTYPE_Pos (8UL) /*!< Position of DCRTYPE field.                                       */
41003   #define I3CCORE_CORE_SECDEVCHARTABLE_DCRTYPE_Msk (0xFFUL << I3CCORE_CORE_SECDEVCHARTABLE_DCRTYPE_Pos) /*!< Bit mask of DCRTYPE
41004                                                                             field.*/
41005 
41006 /* BCRTYPE @Bits 16..23 : The BCR TYPE of Device [n] */
41007   #define I3CCORE_CORE_SECDEVCHARTABLE_BCRTYPE_Pos (16UL) /*!< Position of BCRTYPE field.                                      */
41008   #define I3CCORE_CORE_SECDEVCHARTABLE_BCRTYPE_Msk (0xFFUL << I3CCORE_CORE_SECDEVCHARTABLE_BCRTYPE_Pos) /*!< Bit mask of BCRTYPE
41009                                                                             field.*/
41010 
41011 /* STATICADDR @Bits 24..31 : The Static Addr of Device [n] */
41012   #define I3CCORE_CORE_SECDEVCHARTABLE_STATICADDR_Pos (24UL) /*!< Position of STATICADDR field.                                */
41013   #define I3CCORE_CORE_SECDEVCHARTABLE_STATICADDR_Msk (0xFFUL << I3CCORE_CORE_SECDEVCHARTABLE_STATICADDR_Pos) /*!< Bit mask of
41014                                                                             STATICADDR field.*/
41015 
41016 
41017 /* I3CCORE_CORE_DEVADDRTABLELOC: Device Address Table of Device [n] */
41018   #define I3CCORE_CORE_DEVADDRTABLELOC_MaxCount (10UL) /*!< Max size of DEVADDRTABLELOC[10] array.                             */
41019   #define I3CCORE_CORE_DEVADDRTABLELOC_MaxIndex (9UL) /*!< Max index of DEVADDRTABLELOC[10] array.                             */
41020   #define I3CCORE_CORE_DEVADDRTABLELOC_MinIndex (0UL) /*!< Min index of DEVADDRTABLELOC[10] array.                             */
41021   #define I3CCORE_CORE_DEVADDRTABLELOC_ResetValue (0x00000000UL) /*!< Reset value of DEVADDRTABLELOC[10] register.             */
41022 
41023 /* DEVSTATICADDR @Bits 0..6 : Device Static Address. */
41024   #define I3CCORE_CORE_DEVADDRTABLELOC_DEVSTATICADDR_Pos (0UL) /*!< Position of DEVSTATICADDR field.                           */
41025   #define I3CCORE_CORE_DEVADDRTABLELOC_DEVSTATICADDR_Msk (0x7FUL << I3CCORE_CORE_DEVADDRTABLELOC_DEVSTATICADDR_Pos) /*!< Bit
41026                                                                             mask of DEVSTATICADDR field.*/
41027 
41028 /* DEVDYNAMICADDR @Bits 16..23 : Device Dynamic Address with parity. */
41029   #define I3CCORE_CORE_DEVADDRTABLELOC_DEVDYNAMICADDR_Pos (16UL) /*!< Position of DEVDYNAMICADDR field.                        */
41030   #define I3CCORE_CORE_DEVADDRTABLELOC_DEVDYNAMICADDR_Msk (0xFFUL << I3CCORE_CORE_DEVADDRTABLELOC_DEVDYNAMICADDR_Pos) /*!< Bit
41031                                                                             mask of DEVDYNAMICADDR field.*/
41032 
41033 /* DEVNACKRETRYCNT @Bits 29..30 : This field is used to set the Device NACK Retry count for the particular device. */
41034   #define I3CCORE_CORE_DEVADDRTABLELOC_DEVNACKRETRYCNT_Pos (29UL) /*!< Position of DEVNACKRETRYCNT field.                      */
41035   #define I3CCORE_CORE_DEVADDRTABLELOC_DEVNACKRETRYCNT_Msk (0x3UL << I3CCORE_CORE_DEVADDRTABLELOC_DEVNACKRETRYCNT_Pos) /*!< Bit
41036                                                                             mask of DEVNACKRETRYCNT field.*/
41037 
41038 /* LEGACYI2CDEVICE @Bit 31 : Legacy I2C device or not. */
41039   #define I3CCORE_CORE_DEVADDRTABLELOC_LEGACYI2CDEVICE_Pos (31UL) /*!< Position of LEGACYI2CDEVICE field.                      */
41040   #define I3CCORE_CORE_DEVADDRTABLELOC_LEGACYI2CDEVICE_Msk (0x1UL << I3CCORE_CORE_DEVADDRTABLELOC_LEGACYI2CDEVICE_Pos) /*!< Bit
41041                                                                             mask of LEGACYI2CDEVICE field.*/
41042 
41043 
41044 
41045 /* ================================================= Struct I3CCORE_DMA_CH0 ================================================== */
41046 /**
41047   * @brief CH0 [I3CCORE_DMA_CH0] (unspecified)
41048   */
41049 typedef struct {
41050   __IOM uint32_t  SAR0;                              /*!< (@ 0x00000000) This register contains the source address of the DMA
41051                                                                          transfer.*/
41052   __IM  uint32_t  RESERVED;
41053   __IOM uint32_t  DAR0;                              /*!< (@ 0x00000008) This register contains the destination address of the
41054                                                                          DMA transfer.*/
41055   __IM  uint32_t  RESERVED1[3];
41056   __IOM uint32_t  CTL00;                             /*!< (@ 0x00000018) This register contains fields that control the DMA
41057                                                                          transfer.*/
41058   __IOM uint32_t  CTL01;                             /*!< (@ 0x0000001C) This register contains fields that control the DMA
41059                                                                          transfer.*/
41060   __IM  uint32_t  RESERVED2[8];
41061   __IOM uint32_t  CFG0L;                             /*!< (@ 0x00000040) This register contains fields that configure the DMA
41062                                                                          transfer.*/
41063   __IOM uint32_t  CFG0H;                             /*!< (@ 0x00000044) This register contains fields that configure the DMA
41064                                                                          transfer.*/
41065   __IM  uint32_t  RESERVED3[2];
41066   __IOM uint32_t  DSR0;                              /*!< (@ 0x00000050) Destination Scatter register.                         */
41067 } NRF_I3CCORE_DMA_CH0_Type;                          /*!< Size = 84 (0x054)                                                    */
41068 
41069 /* I3CCORE_DMA_CH0_SAR0: This register contains the source address of the DMA transfer. */
41070   #define I3CCORE_DMA_CH0_SAR0_ResetValue (0x00000000UL) /*!< Reset value of SAR0 register.                                    */
41071 
41072 /* SAR @Bits 0..31 : Current Source Address of DMA transfer. */
41073   #define I3CCORE_DMA_CH0_SAR0_SAR_Pos (0UL)         /*!< Position of SAR field.                                               */
41074   #define I3CCORE_DMA_CH0_SAR0_SAR_Msk (0xFFFFFFFFUL << I3CCORE_DMA_CH0_SAR0_SAR_Pos) /*!< Bit mask of SAR field.              */
41075 
41076 
41077 /* I3CCORE_DMA_CH0_DAR0: This register contains the destination address of the DMA transfer. */
41078   #define I3CCORE_DMA_CH0_DAR0_ResetValue (0x00000000UL) /*!< Reset value of DAR0 register.                                    */
41079 
41080 /* DAR @Bits 0..31 : Current Destination address of DMA transfer. */
41081   #define I3CCORE_DMA_CH0_DAR0_DAR_Pos (0UL)         /*!< Position of DAR field.                                               */
41082   #define I3CCORE_DMA_CH0_DAR0_DAR_Msk (0xFFFFFFFFUL << I3CCORE_DMA_CH0_DAR0_DAR_Pos) /*!< Bit mask of DAR field.              */
41083 
41084 
41085 /* I3CCORE_DMA_CH0_CTL00: This register contains fields that control the DMA transfer. */
41086   #define I3CCORE_DMA_CH0_CTL00_ResetValue (0x02504821UL) /*!< Reset value of CTL00 register.                                  */
41087 
41088 /* INTEN @Bit 0 : Interrupt Enable Bit. */
41089   #define I3CCORE_DMA_CH0_CTL00_INTEN_Pos (0UL)      /*!< Position of INTEN field.                                             */
41090   #define I3CCORE_DMA_CH0_CTL00_INTEN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_INTEN_Pos) /*!< Bit mask of INTEN field.             */
41091   #define I3CCORE_DMA_CH0_CTL00_INTEN_Min (0x0UL)    /*!< Min enumerator value of INTEN field.                                 */
41092   #define I3CCORE_DMA_CH0_CTL00_INTEN_Max (0x1UL)    /*!< Max enumerator value of INTEN field.                                 */
41093   #define I3CCORE_DMA_CH0_CTL00_INTEN_INTERRUPT_DISABLE (0x0UL) /*!< (unspecified)                                             */
41094   #define I3CCORE_DMA_CH0_CTL00_INTEN_INTERRUPT_ENABLE (0x1UL) /*!< (unspecified)                                              */
41095 
41096 /* DSTTRWIDTH @Bits 1..3 : Destination Transfer Width. */
41097   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Pos (1UL) /*!< Position of DSTTRWIDTH field.                                        */
41098   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Pos) /*!< Bit mask of DSTTRWIDTH
41099                                                                             field.*/
41100   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Min (0x0UL) /*!< Min enumerator value of DSTTRWIDTH field.                          */
41101   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_Max (0x7UL) /*!< Max enumerator value of DSTTRWIDTH field.                          */
41102   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_0 (0x0UL) /*!< (unspecified)                                           */
41103   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_1 (0x1UL) /*!< (unspecified)                                           */
41104   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_2 (0x2UL) /*!< (unspecified)                                           */
41105   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_3 (0x3UL) /*!< (unspecified)                                           */
41106   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_4 (0x4UL) /*!< (unspecified)                                           */
41107   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_5 (0x5UL) /*!< (unspecified)                                           */
41108   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_6 (0x6UL) /*!< (unspecified)                                           */
41109   #define I3CCORE_DMA_CH0_CTL00_DSTTRWIDTH_DST_TR_WIDTH_7 (0x7UL) /*!< (unspecified)                                           */
41110 
41111 /* RSVDSRCTRWIDTH @Bits 4..6 : Reserved field - read-only */
41112   #define I3CCORE_DMA_CH0_CTL00_RSVDSRCTRWIDTH_Pos (4UL) /*!< Position of RSVDSRCTRWIDTH field.                                */
41113   #define I3CCORE_DMA_CH0_CTL00_RSVDSRCTRWIDTH_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_RSVDSRCTRWIDTH_Pos) /*!< Bit mask of
41114                                                                             RSVDSRCTRWIDTH field.*/
41115 
41116 /* DINC @Bits 7..8 : Destination Address Increment. */
41117   #define I3CCORE_DMA_CH0_CTL00_DINC_Pos (7UL)       /*!< Position of DINC field.                                              */
41118   #define I3CCORE_DMA_CH0_CTL00_DINC_Msk (0x3UL << I3CCORE_DMA_CH0_CTL00_DINC_Pos) /*!< Bit mask of DINC field.                */
41119   #define I3CCORE_DMA_CH0_CTL00_DINC_Min (0x0UL)     /*!< Min enumerator value of DINC field.                                  */
41120   #define I3CCORE_DMA_CH0_CTL00_DINC_Max (0x3UL)     /*!< Max enumerator value of DINC field.                                  */
41121   #define I3CCORE_DMA_CH0_CTL00_DINC_DINC_0 (0x0UL)  /*!< (unspecified)                                                        */
41122   #define I3CCORE_DMA_CH0_CTL00_DINC_DINC_1 (0x1UL)  /*!< (unspecified)                                                        */
41123   #define I3CCORE_DMA_CH0_CTL00_DINC_DINC_2 (0x2UL)  /*!< (unspecified)                                                        */
41124   #define I3CCORE_DMA_CH0_CTL00_DINC_DINC_3 (0x3UL)  /*!< (unspecified)                                                        */
41125 
41126 /* SINC @Bits 9..10 : Source Address Increment. */
41127   #define I3CCORE_DMA_CH0_CTL00_SINC_Pos (9UL)       /*!< Position of SINC field.                                              */
41128   #define I3CCORE_DMA_CH0_CTL00_SINC_Msk (0x3UL << I3CCORE_DMA_CH0_CTL00_SINC_Pos) /*!< Bit mask of SINC field.                */
41129   #define I3CCORE_DMA_CH0_CTL00_SINC_Min (0x0UL)     /*!< Min enumerator value of SINC field.                                  */
41130   #define I3CCORE_DMA_CH0_CTL00_SINC_Max (0x3UL)     /*!< Max enumerator value of SINC field.                                  */
41131   #define I3CCORE_DMA_CH0_CTL00_SINC_SINC_0 (0x0UL)  /*!< (unspecified)                                                        */
41132   #define I3CCORE_DMA_CH0_CTL00_SINC_SINC_1 (0x1UL)  /*!< (unspecified)                                                        */
41133   #define I3CCORE_DMA_CH0_CTL00_SINC_SINC_2 (0x2UL)  /*!< (unspecified)                                                        */
41134   #define I3CCORE_DMA_CH0_CTL00_SINC_SINC_3 (0x3UL)  /*!< (unspecified)                                                        */
41135 
41136 /* DESTMSIZE @Bits 11..13 : Destination Burst Transaction Length. */
41137   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Pos (11UL) /*!< Position of DESTMSIZE field.                                         */
41138   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Pos) /*!< Bit mask of DESTMSIZE field. */
41139   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Min (0x0UL) /*!< Min enumerator value of DESTMSIZE field.                            */
41140   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_Max (0x7UL) /*!< Max enumerator value of DESTMSIZE field.                            */
41141   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_0 (0x0UL) /*!< (unspecified)                                              */
41142   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_1 (0x1UL) /*!< (unspecified)                                              */
41143   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_2 (0x2UL) /*!< (unspecified)                                              */
41144   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_3 (0x3UL) /*!< (unspecified)                                              */
41145   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_4 (0x4UL) /*!< (unspecified)                                              */
41146   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_5 (0x5UL) /*!< (unspecified)                                              */
41147   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_6 (0x6UL) /*!< (unspecified)                                              */
41148   #define I3CCORE_DMA_CH0_CTL00_DESTMSIZE_DEST_MSIZE_7 (0x7UL) /*!< (unspecified)                                              */
41149 
41150 /* SRCMSIZE @Bits 14..16 : Source Burst Transaction Length. */
41151   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Pos (14UL)  /*!< Position of SRCMSIZE field.                                          */
41152   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Pos) /*!< Bit mask of SRCMSIZE field.    */
41153   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Min (0x0UL) /*!< Min enumerator value of SRCMSIZE field.                              */
41154   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_Max (0x7UL) /*!< Max enumerator value of SRCMSIZE field.                              */
41155   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_0 (0x0UL) /*!< (unspecified)                                                */
41156   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_1 (0x1UL) /*!< (unspecified)                                                */
41157   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_2 (0x2UL) /*!< (unspecified)                                                */
41158   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_3 (0x3UL) /*!< (unspecified)                                                */
41159   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_4 (0x4UL) /*!< (unspecified)                                                */
41160   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_5 (0x5UL) /*!< (unspecified)                                                */
41161   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_6 (0x6UL) /*!< (unspecified)                                                */
41162   #define I3CCORE_DMA_CH0_CTL00_SRCMSIZE_SRC_MSIZE_7 (0x7UL) /*!< (unspecified)                                                */
41163 
41164 /* RSVDSRCGATHEREN @Bit 17 : Reserved field - read-only */
41165   #define I3CCORE_DMA_CH0_CTL00_RSVDSRCGATHEREN_Pos (17UL) /*!< Position of RSVDSRCGATHEREN field.                             */
41166   #define I3CCORE_DMA_CH0_CTL00_RSVDSRCGATHEREN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_RSVDSRCGATHEREN_Pos) /*!< Bit mask of
41167                                                                             RSVDSRCGATHEREN field.*/
41168 
41169 /* DSTSCATTEREN @Bit 18 : Destination scatter enable. */
41170   #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Pos (18UL) /*!< Position of DSTSCATTEREN field.                                   */
41171   #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Pos) /*!< Bit mask of DSTSCATTEREN
41172                                                                             field.*/
41173   #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Min (0x0UL) /*!< Min enumerator value of DSTSCATTEREN field.                      */
41174   #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_Max (0x1UL) /*!< Max enumerator value of DSTSCATTEREN field.                      */
41175   #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_DST_SCATTER_DISABLE (0x0UL) /*!< (unspecified)                                    */
41176   #define I3CCORE_DMA_CH0_CTL00_DSTSCATTEREN_DST_SCATTER_ENABLE (0x1UL) /*!< (unspecified)                                     */
41177 
41178 /* RSVDCTL @Bit 19 : Reserved field - read-only */
41179   #define I3CCORE_DMA_CH0_CTL00_RSVDCTL_Pos (19UL)   /*!< Position of RSVDCTL field.                                           */
41180   #define I3CCORE_DMA_CH0_CTL00_RSVDCTL_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_RSVDCTL_Pos) /*!< Bit mask of RSVDCTL field.       */
41181 
41182 /* TTFC @Bits 20..22 : Transfer Type and Flow Control. */
41183   #define I3CCORE_DMA_CH0_CTL00_TTFC_Pos (20UL)      /*!< Position of TTFC field.                                              */
41184   #define I3CCORE_DMA_CH0_CTL00_TTFC_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_TTFC_Pos) /*!< Bit mask of TTFC field.                */
41185   #define I3CCORE_DMA_CH0_CTL00_TTFC_Min (0x0UL)     /*!< Min enumerator value of TTFC field.                                  */
41186   #define I3CCORE_DMA_CH0_CTL00_TTFC_Max (0x7UL)     /*!< Max enumerator value of TTFC field.                                  */
41187   #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_0 (0x0UL) /*!< (unspecified)                                                        */
41188   #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_1 (0x1UL) /*!< (unspecified)                                                        */
41189   #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_2 (0x2UL) /*!< (unspecified)                                                        */
41190   #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_3 (0x3UL) /*!< (unspecified)                                                        */
41191   #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_4 (0x4UL) /*!< (unspecified)                                                        */
41192   #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_5 (0x5UL) /*!< (unspecified)                                                        */
41193   #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_6 (0x6UL) /*!< (unspecified)                                                        */
41194   #define I3CCORE_DMA_CH0_CTL00_TTFC_TT_FC_7 (0x7UL) /*!< (unspecified)                                                        */
41195 
41196 /* RSVDDMS @Bits 23..24 : Reserved field - read-only */
41197   #define I3CCORE_DMA_CH0_CTL00_RSVDDMS_Pos (23UL)   /*!< Position of RSVDDMS field.                                           */
41198   #define I3CCORE_DMA_CH0_CTL00_RSVDDMS_Msk (0x3UL << I3CCORE_DMA_CH0_CTL00_RSVDDMS_Pos) /*!< Bit mask of RSVDDMS field.       */
41199 
41200 /* RSVDSMS @Bits 25..26 : Reserved field - read-only */
41201   #define I3CCORE_DMA_CH0_CTL00_RSVDSMS_Pos (25UL)   /*!< Position of RSVDSMS field.                                           */
41202   #define I3CCORE_DMA_CH0_CTL00_RSVDSMS_Msk (0x3UL << I3CCORE_DMA_CH0_CTL00_RSVDSMS_Pos) /*!< Bit mask of RSVDSMS field.       */
41203 
41204 /* RSVDLLPDSTEN @Bit 27 : Reserved field - read-only */
41205   #define I3CCORE_DMA_CH0_CTL00_RSVDLLPDSTEN_Pos (27UL) /*!< Position of RSVDLLPDSTEN field.                                   */
41206   #define I3CCORE_DMA_CH0_CTL00_RSVDLLPDSTEN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_RSVDLLPDSTEN_Pos) /*!< Bit mask of RSVDLLPDSTEN
41207                                                                             field.*/
41208 
41209 /* RSVDLLPSRCEN @Bit 28 : Reserved field - read-only */
41210   #define I3CCORE_DMA_CH0_CTL00_RSVDLLPSRCEN_Pos (28UL) /*!< Position of RSVDLLPSRCEN field.                                   */
41211   #define I3CCORE_DMA_CH0_CTL00_RSVDLLPSRCEN_Msk (0x1UL << I3CCORE_DMA_CH0_CTL00_RSVDLLPSRCEN_Pos) /*!< Bit mask of RSVDLLPSRCEN
41212                                                                             field.*/
41213 
41214 /* RSVD1CTL @Bits 29..31 : Reserved field - read-only */
41215   #define I3CCORE_DMA_CH0_CTL00_RSVD1CTL_Pos (29UL)  /*!< Position of RSVD1CTL field.                                          */
41216   #define I3CCORE_DMA_CH0_CTL00_RSVD1CTL_Msk (0x7UL << I3CCORE_DMA_CH0_CTL00_RSVD1CTL_Pos) /*!< Bit mask of RSVD1CTL field.    */
41217 
41218 
41219 /* I3CCORE_DMA_CH0_CTL01: This register contains fields that control the DMA transfer. */
41220   #define I3CCORE_DMA_CH0_CTL01_ResetValue (0x00000002UL) /*!< Reset value of CTL01 register.                                  */
41221 
41222 /* BLOCKTS @Bits 0..4 : Block Transfer Size. */
41223   #define I3CCORE_DMA_CH0_CTL01_BLOCKTS_Pos (0UL)    /*!< Position of BLOCKTS field.                                           */
41224   #define I3CCORE_DMA_CH0_CTL01_BLOCKTS_Msk (0x1FUL << I3CCORE_DMA_CH0_CTL01_BLOCKTS_Pos) /*!< Bit mask of BLOCKTS field.      */
41225 
41226 /* RSVD2CTL @Bits 5..11 : Reserved field - read-only */
41227   #define I3CCORE_DMA_CH0_CTL01_RSVD2CTL_Pos (5UL)   /*!< Position of RSVD2CTL field.                                          */
41228   #define I3CCORE_DMA_CH0_CTL01_RSVD2CTL_Msk (0x7FUL << I3CCORE_DMA_CH0_CTL01_RSVD2CTL_Pos) /*!< Bit mask of RSVD2CTL field.   */
41229 
41230 /* DONE @Bit 12 : Done bit. */
41231   #define I3CCORE_DMA_CH0_CTL01_DONE_Pos (12UL)      /*!< Position of DONE field.                                              */
41232   #define I3CCORE_DMA_CH0_CTL01_DONE_Msk (0x1UL << I3CCORE_DMA_CH0_CTL01_DONE_Pos) /*!< Bit mask of DONE field.                */
41233   #define I3CCORE_DMA_CH0_CTL01_DONE_Min (0x0UL)     /*!< Min enumerator value of DONE field.                                  */
41234   #define I3CCORE_DMA_CH0_CTL01_DONE_Max (0x1UL)     /*!< Max enumerator value of DONE field.                                  */
41235   #define I3CCORE_DMA_CH0_CTL01_DONE_DISABLED (0x0UL) /*!< (unspecified)                                                       */
41236   #define I3CCORE_DMA_CH0_CTL01_DONE_ENABLED (0x1UL) /*!< (unspecified)                                                        */
41237 
41238 
41239 /* I3CCORE_DMA_CH0_CFG0L: This register contains fields that configure the DMA transfer. */
41240   #define I3CCORE_DMA_CH0_CFG0L_ResetValue (0x00000E00UL) /*!< Reset value of CFG0L register.                                  */
41241 
41242 /* RSVDCFG @Bits 0..4 : Reserved field - read-only */
41243   #define I3CCORE_DMA_CH0_CFG0L_RSVDCFG_Pos (0UL)    /*!< Position of RSVDCFG field.                                           */
41244   #define I3CCORE_DMA_CH0_CFG0L_RSVDCFG_Msk (0x1FUL << I3CCORE_DMA_CH0_CFG0L_RSVDCFG_Pos) /*!< Bit mask of RSVDCFG field.      */
41245 
41246 /* CHPRIOR @Bits 5..7 : Channel Priority. */
41247   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Pos (5UL)    /*!< Position of CHPRIOR field.                                           */
41248   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Msk (0x7UL << I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Pos) /*!< Bit mask of CHPRIOR field.       */
41249   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Min (0x0UL)  /*!< Min enumerator value of CHPRIOR field.                               */
41250   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_Max (0x7UL)  /*!< Max enumerator value of CHPRIOR field.                               */
41251   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_0 (0x0UL) /*!< (unspecified)                                                  */
41252   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_1 (0x1UL) /*!< (unspecified)                                                  */
41253   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_2 (0x2UL) /*!< (unspecified)                                                  */
41254   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_3 (0x3UL) /*!< (unspecified)                                                  */
41255   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_4 (0x4UL) /*!< (unspecified)                                                  */
41256   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_5 (0x5UL) /*!< (unspecified)                                                  */
41257   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_6 (0x6UL) /*!< (unspecified)                                                  */
41258   #define I3CCORE_DMA_CH0_CFG0L_CHPRIOR_CH_PRIOR_7 (0x7UL) /*!< (unspecified)                                                  */
41259 
41260 /* CHSUSP @Bit 8 : Channel Suspend. */
41261   #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_Pos (8UL)     /*!< Position of CHSUSP field.                                            */
41262   #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_CHSUSP_Pos) /*!< Bit mask of CHSUSP field.          */
41263   #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_Min (0x0UL)   /*!< Min enumerator value of CHSUSP field.                                */
41264   #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_Max (0x1UL)   /*!< Max enumerator value of CHSUSP field.                                */
41265   #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_NOT_SUSPENDED (0x0UL) /*!< (unspecified)                                                */
41266   #define I3CCORE_DMA_CH0_CFG0L_CHSUSP_SUSPENDED (0x1UL) /*!< (unspecified)                                                    */
41267 
41268 /* FIFOEMPTY @Bit 9 : Channel FIFO status. */
41269   #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Pos (9UL)  /*!< Position of FIFOEMPTY field.                                         */
41270   #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Pos) /*!< Bit mask of FIFOEMPTY field. */
41271   #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Min (0x0UL) /*!< Min enumerator value of FIFOEMPTY field.                            */
41272   #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_Max (0x1UL) /*!< Max enumerator value of FIFOEMPTY field.                            */
41273   #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_NOT_EMPTY (0x0UL) /*!< (unspecified)                                                 */
41274   #define I3CCORE_DMA_CH0_CFG0L_FIFOEMPTY_EMPTY (0x1UL) /*!< (unspecified)                                                     */
41275 
41276 /* HSSELDST @Bit 10 : Destination Software or Hardware Handshaking Select. */
41277   #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_Pos (10UL)  /*!< Position of HSSELDST field.                                          */
41278   #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_HSSELDST_Pos) /*!< Bit mask of HSSELDST field.    */
41279   #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_Min (0x0UL) /*!< Min enumerator value of HSSELDST field.                              */
41280   #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_Max (0x1UL) /*!< Max enumerator value of HSSELDST field.                              */
41281   #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_HARDWARE_HS (0x0UL) /*!< (unspecified)                                                */
41282   #define I3CCORE_DMA_CH0_CFG0L_HSSELDST_SOFTWARE_HS (0x1UL) /*!< (unspecified)                                                */
41283 
41284 /* HSSELSRC @Bit 11 : Source Software or Hardware Handshaking Select. */
41285   #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Pos (11UL)  /*!< Position of HSSELSRC field.                                          */
41286   #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Pos) /*!< Bit mask of HSSELSRC field.    */
41287   #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Min (0x0UL) /*!< Min enumerator value of HSSELSRC field.                              */
41288   #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_Max (0x1UL) /*!< Max enumerator value of HSSELSRC field.                              */
41289   #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_HARDWARE_HS (0x0UL) /*!< (unspecified)                                                */
41290   #define I3CCORE_DMA_CH0_CFG0L_HSSELSRC_SOFTWARE_HS (0x1UL) /*!< (unspecified)                                                */
41291 
41292 /* RSVDLOCKCHL @Bits 12..13 : Reserved field - read-only */
41293   #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCHL_Pos (12UL) /*!< Position of RSVDLOCKCHL field.                                     */
41294   #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCHL_Msk (0x3UL << I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCHL_Pos) /*!< Bit mask of RSVDLOCKCHL
41295                                                                             field.*/
41296 
41297 /* RSVDLOCKBL @Bits 14..15 : Reserved field - read-only */
41298   #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKBL_Pos (14UL) /*!< Position of RSVDLOCKBL field.                                       */
41299   #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKBL_Msk (0x3UL << I3CCORE_DMA_CH0_CFG0L_RSVDLOCKBL_Pos) /*!< Bit mask of RSVDLOCKBL
41300                                                                             field.*/
41301 
41302 /* RSVDLOCKCH @Bit 16 : Reserved field - read-only */
41303   #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCH_Pos (16UL) /*!< Position of RSVDLOCKCH field.                                       */
41304   #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCH_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_RSVDLOCKCH_Pos) /*!< Bit mask of RSVDLOCKCH
41305                                                                             field.*/
41306 
41307 /* RSVDLOCKB @Bit 17 : Reserved field - read-only */
41308   #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKB_Pos (17UL) /*!< Position of RSVDLOCKB field.                                         */
41309   #define I3CCORE_DMA_CH0_CFG0L_RSVDLOCKB_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_RSVDLOCKB_Pos) /*!< Bit mask of RSVDLOCKB field. */
41310 
41311 /* DSTHSPOL @Bit 18 : Destination Handshaking Interface Polarity. */
41312   #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Pos (18UL)  /*!< Position of DSTHSPOL field.                                          */
41313   #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Pos) /*!< Bit mask of DSTHSPOL field.    */
41314   #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Min (0x0UL) /*!< Min enumerator value of DSTHSPOL field.                              */
41315   #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_Max (0x1UL) /*!< Max enumerator value of DSTHSPOL field.                              */
41316   #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_ACTIVE_HIGH (0x0UL) /*!< (unspecified)                                                */
41317   #define I3CCORE_DMA_CH0_CFG0L_DSTHSPOL_ACTIVE_LOW (0x1UL) /*!< (unspecified)                                                 */
41318 
41319 /* SRCHSPOL @Bit 19 : Source Handshaking Interface Polarity. */
41320   #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Pos (19UL)  /*!< Position of SRCHSPOL field.                                          */
41321   #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Pos) /*!< Bit mask of SRCHSPOL field.    */
41322   #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Min (0x0UL) /*!< Min enumerator value of SRCHSPOL field.                              */
41323   #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_Max (0x1UL) /*!< Max enumerator value of SRCHSPOL field.                              */
41324   #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_ACTIVE_HIGH (0x0UL) /*!< (unspecified)                                                */
41325   #define I3CCORE_DMA_CH0_CFG0L_SRCHSPOL_ACTIVE_LOW (0x1UL) /*!< (unspecified)                                                 */
41326 
41327 /* MAXABRST @Bits 20..29 : Maximum AMBA Burst Length. */
41328   #define I3CCORE_DMA_CH0_CFG0L_MAXABRST_Pos (20UL)  /*!< Position of MAXABRST field.                                          */
41329   #define I3CCORE_DMA_CH0_CFG0L_MAXABRST_Msk (0x3FFUL << I3CCORE_DMA_CH0_CFG0L_MAXABRST_Pos) /*!< Bit mask of MAXABRST field.  */
41330 
41331 /* RSVDRELOADSRC @Bit 30 : Reserved field - read-only */
41332   #define I3CCORE_DMA_CH0_CFG0L_RSVDRELOADSRC_Pos (30UL) /*!< Position of RSVDRELOADSRC field.                                 */
41333   #define I3CCORE_DMA_CH0_CFG0L_RSVDRELOADSRC_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_RSVDRELOADSRC_Pos) /*!< Bit mask of
41334                                                                             RSVDRELOADSRC field.*/
41335 
41336 /* RSVDRELOADDST @Bit 31 : Reserved field- read-only */
41337   #define I3CCORE_DMA_CH0_CFG0L_RSVDRELOADDST_Pos (31UL) /*!< Position of RSVDRELOADDST field.                                 */
41338   #define I3CCORE_DMA_CH0_CFG0L_RSVDRELOADDST_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0L_RSVDRELOADDST_Pos) /*!< Bit mask of
41339                                                                             RSVDRELOADDST field.*/
41340 
41341 
41342 /* I3CCORE_DMA_CH0_CFG0H: This register contains fields that configure the DMA transfer. */
41343   #define I3CCORE_DMA_CH0_CFG0H_ResetValue (0x00000004UL) /*!< Reset value of CFG0H register.                                  */
41344 
41345 /* FCMODE @Bit 0 : Flow Control Mode. */
41346   #define I3CCORE_DMA_CH0_CFG0H_FCMODE_Pos (0UL)     /*!< Position of FCMODE field.                                            */
41347   #define I3CCORE_DMA_CH0_CFG0H_FCMODE_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_FCMODE_Pos) /*!< Bit mask of FCMODE field.          */
41348   #define I3CCORE_DMA_CH0_CFG0H_FCMODE_Min (0x0UL)   /*!< Min enumerator value of FCMODE field.                                */
41349   #define I3CCORE_DMA_CH0_CFG0H_FCMODE_Max (0x1UL)   /*!< Max enumerator value of FCMODE field.                                */
41350   #define I3CCORE_DMA_CH0_CFG0H_FCMODE_FCMODE_0 (0x0UL) /*!< (unspecified)                                                     */
41351   #define I3CCORE_DMA_CH0_CFG0H_FCMODE_FCMODE_1 (0x1UL) /*!< (unspecified)                                                     */
41352 
41353 /* FIFOMODE @Bit 1 : FIFO Mode Select. */
41354   #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Pos (1UL)   /*!< Position of FIFOMODE field.                                          */
41355   #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Pos) /*!< Bit mask of FIFOMODE field.    */
41356   #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Min (0x0UL) /*!< Min enumerator value of FIFOMODE field.                              */
41357   #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_Max (0x1UL) /*!< Max enumerator value of FIFOMODE field.                              */
41358   #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_FIFO_MODE_0 (0x0UL) /*!< (unspecified)                                                */
41359   #define I3CCORE_DMA_CH0_CFG0H_FIFOMODE_FIFO_MODE_1 (0x1UL) /*!< (unspecified)                                                */
41360 
41361 /* PROTCTL @Bits 2..4 : Protection Control bits used to drive the AHB HPROT[3:1] bus. */
41362   #define I3CCORE_DMA_CH0_CFG0H_PROTCTL_Pos (2UL)    /*!< Position of PROTCTL field.                                           */
41363   #define I3CCORE_DMA_CH0_CFG0H_PROTCTL_Msk (0x7UL << I3CCORE_DMA_CH0_CFG0H_PROTCTL_Pos) /*!< Bit mask of PROTCTL field.       */
41364 
41365 /* RSVDDSUPDEN @Bit 5 : Reserved field- read-only */
41366   #define I3CCORE_DMA_CH0_CFG0H_RSVDDSUPDEN_Pos (5UL) /*!< Position of RSVDDSUPDEN field.                                      */
41367   #define I3CCORE_DMA_CH0_CFG0H_RSVDDSUPDEN_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_RSVDDSUPDEN_Pos) /*!< Bit mask of RSVDDSUPDEN
41368                                                                             field.*/
41369 
41370 /* RSVDSSUPDEN @Bit 6 : Reserved field- read-only */
41371   #define I3CCORE_DMA_CH0_CFG0H_RSVDSSUPDEN_Pos (6UL) /*!< Position of RSVDSSUPDEN field.                                      */
41372   #define I3CCORE_DMA_CH0_CFG0H_RSVDSSUPDEN_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_RSVDSSUPDEN_Pos) /*!< Bit mask of RSVDSSUPDEN
41373                                                                             field.*/
41374 
41375 /* SRCPER @Bit 7 : Source Hardware Interface. */
41376   #define I3CCORE_DMA_CH0_CFG0H_SRCPER_Pos (7UL)     /*!< Position of SRCPER field.                                            */
41377   #define I3CCORE_DMA_CH0_CFG0H_SRCPER_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_SRCPER_Pos) /*!< Bit mask of SRCPER field.          */
41378 
41379 /* RSVD1CFG @Bits 8..10 : Reserved field - read-only */
41380   #define I3CCORE_DMA_CH0_CFG0H_RSVD1CFG_Pos (8UL)   /*!< Position of RSVD1CFG field.                                          */
41381   #define I3CCORE_DMA_CH0_CFG0H_RSVD1CFG_Msk (0x7UL << I3CCORE_DMA_CH0_CFG0H_RSVD1CFG_Pos) /*!< Bit mask of RSVD1CFG field.    */
41382 
41383 /* DESTPER @Bit 11 : Destination hardware interface. */
41384   #define I3CCORE_DMA_CH0_CFG0H_DESTPER_Pos (11UL)   /*!< Position of DESTPER field.                                           */
41385   #define I3CCORE_DMA_CH0_CFG0H_DESTPER_Msk (0x1UL << I3CCORE_DMA_CH0_CFG0H_DESTPER_Pos) /*!< Bit mask of DESTPER field.       */
41386 
41387 /* RSVD2CFG @Bits 12..14 : Reserved field - read-only */
41388   #define I3CCORE_DMA_CH0_CFG0H_RSVD2CFG_Pos (12UL)  /*!< Position of RSVD2CFG field.                                          */
41389   #define I3CCORE_DMA_CH0_CFG0H_RSVD2CFG_Msk (0x7UL << I3CCORE_DMA_CH0_CFG0H_RSVD2CFG_Pos) /*!< Bit mask of RSVD2CFG field.    */
41390 
41391 /* RSVD3CFG @Bits 15..31 : Reserved field - read-only */
41392   #define I3CCORE_DMA_CH0_CFG0H_RSVD3CFG_Pos (15UL)  /*!< Position of RSVD3CFG field.                                          */
41393   #define I3CCORE_DMA_CH0_CFG0H_RSVD3CFG_Msk (0x1FFFFUL << I3CCORE_DMA_CH0_CFG0H_RSVD3CFG_Pos) /*!< Bit mask of RSVD3CFG field.*/
41394 
41395 
41396 /* I3CCORE_DMA_CH0_DSR0: Destination Scatter register. */
41397   #define I3CCORE_DMA_CH0_DSR0_ResetValue (0x00000000UL) /*!< Reset value of DSR0 register.                                    */
41398 
41399 /* DSI @Bits 0..19 : Destination Scatter Interval. */
41400   #define I3CCORE_DMA_CH0_DSR0_DSI_Pos (0UL)         /*!< Position of DSI field.                                               */
41401   #define I3CCORE_DMA_CH0_DSR0_DSI_Msk (0xFFFFFUL << I3CCORE_DMA_CH0_DSR0_DSI_Pos) /*!< Bit mask of DSI field.                 */
41402 
41403 /* DSC @Bits 20..24 : Destination Scatter Count. */
41404   #define I3CCORE_DMA_CH0_DSR0_DSC_Pos (20UL)        /*!< Position of DSC field.                                               */
41405   #define I3CCORE_DMA_CH0_DSR0_DSC_Msk (0x1FUL << I3CCORE_DMA_CH0_DSR0_DSC_Pos) /*!< Bit mask of DSC field.                    */
41406 
41407 
41408 
41409 /* ================================================= Struct I3CCORE_DMA_CH1 ================================================== */
41410 /**
41411   * @brief CH1 [I3CCORE_DMA_CH1] (unspecified)
41412   */
41413 typedef struct {
41414   __IOM uint32_t  SAR1;                              /*!< (@ 0x00000000) This register contains the source address of the DMA
41415                                                                          transfer.*/
41416   __IM  uint32_t  RESERVED;
41417   __IOM uint32_t  DAR1;                              /*!< (@ 0x00000008) This register contains the destination address of the
41418                                                                          DMA transfer.*/
41419   __IM  uint32_t  RESERVED1[3];
41420   __IOM uint32_t  CTL1L;                             /*!< (@ 0x00000018) This register contains fields that control the DMA
41421                                                                          transfer.*/
41422   __IOM uint32_t  CTL1H;                             /*!< (@ 0x0000001C) This register contains fields that control the DMA
41423                                                                          transfer.*/
41424   __IM  uint32_t  RESERVED2[8];
41425   __IOM uint32_t  CFG1L;                             /*!< (@ 0x00000040) This register contains fields that configure the DMA
41426                                                                          transfer.*/
41427   __IOM uint32_t  CFG1H;                             /*!< (@ 0x00000044) This register contains fields that configure the DMA
41428                                                                          transfer.*/
41429   __IOM uint32_t  SGR1;                              /*!< (@ 0x00000048) Source Gather register                                */
41430 } NRF_I3CCORE_DMA_CH1_Type;                          /*!< Size = 76 (0x04C)                                                    */
41431 
41432 /* I3CCORE_DMA_CH1_SAR1: This register contains the source address of the DMA transfer. */
41433   #define I3CCORE_DMA_CH1_SAR1_ResetValue (0x00000000UL) /*!< Reset value of SAR1 register.                                    */
41434 
41435 /* SAR @Bits 0..31 : Current Source Address of DMA transfer. */
41436   #define I3CCORE_DMA_CH1_SAR1_SAR_Pos (0UL)         /*!< Position of SAR field.                                               */
41437   #define I3CCORE_DMA_CH1_SAR1_SAR_Msk (0xFFFFFFFFUL << I3CCORE_DMA_CH1_SAR1_SAR_Pos) /*!< Bit mask of SAR field.              */
41438 
41439 
41440 /* I3CCORE_DMA_CH1_DAR1: This register contains the destination address of the DMA transfer. */
41441   #define I3CCORE_DMA_CH1_DAR1_ResetValue (0x00000000UL) /*!< Reset value of DAR1 register.                                    */
41442 
41443 /* DAR @Bits 0..31 : Current Destination address of DMA transfer. */
41444   #define I3CCORE_DMA_CH1_DAR1_DAR_Pos (0UL)         /*!< Position of DAR field.                                               */
41445   #define I3CCORE_DMA_CH1_DAR1_DAR_Msk (0xFFFFFFFFUL << I3CCORE_DMA_CH1_DAR1_DAR_Pos) /*!< Bit mask of DAR field.              */
41446 
41447 
41448 /* I3CCORE_DMA_CH1_CTL1L: This register contains fields that control the DMA transfer. */
41449   #define I3CCORE_DMA_CH1_CTL1L_ResetValue (0x00F04805UL) /*!< Reset value of CTL1L register.                                  */
41450 
41451 /* INTEN @Bit 0 : Interrupt Enable Bit. */
41452   #define I3CCORE_DMA_CH1_CTL1L_INTEN_Pos (0UL)      /*!< Position of INTEN field.                                             */
41453   #define I3CCORE_DMA_CH1_CTL1L_INTEN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_INTEN_Pos) /*!< Bit mask of INTEN field.             */
41454   #define I3CCORE_DMA_CH1_CTL1L_INTEN_Min (0x0UL)    /*!< Min enumerator value of INTEN field.                                 */
41455   #define I3CCORE_DMA_CH1_CTL1L_INTEN_Max (0x1UL)    /*!< Max enumerator value of INTEN field.                                 */
41456   #define I3CCORE_DMA_CH1_CTL1L_INTEN_INTERRUPT_DISABLE (0x0UL) /*!< (unspecified)                                             */
41457   #define I3CCORE_DMA_CH1_CTL1L_INTEN_INTERRUPT_ENABLE (0x1UL) /*!< (unspecified)                                              */
41458 
41459 /* RSVDDSTTRWIDTH @Bits 1..3 : Reserved field - read-only */
41460   #define I3CCORE_DMA_CH1_CTL1L_RSVDDSTTRWIDTH_Pos (1UL) /*!< Position of RSVDDSTTRWIDTH field.                                */
41461   #define I3CCORE_DMA_CH1_CTL1L_RSVDDSTTRWIDTH_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_RSVDDSTTRWIDTH_Pos) /*!< Bit mask of
41462                                                                             RSVDDSTTRWIDTH field.*/
41463 
41464 /* SRCTRWIDTH @Bits 4..6 : Source Transfer Width. */
41465   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Pos (4UL) /*!< Position of SRCTRWIDTH field.                                        */
41466   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Pos) /*!< Bit mask of SRCTRWIDTH
41467                                                                             field.*/
41468   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Min (0x0UL) /*!< Min enumerator value of SRCTRWIDTH field.                          */
41469   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_Max (0x7UL) /*!< Max enumerator value of SRCTRWIDTH field.                          */
41470   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_0 (0x0UL) /*!< (unspecified)                                           */
41471   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_1 (0x1UL) /*!< (unspecified)                                           */
41472   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_2 (0x2UL) /*!< (unspecified)                                           */
41473   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_3 (0x3UL) /*!< (unspecified)                                           */
41474   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_4 (0x4UL) /*!< (unspecified)                                           */
41475   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_5 (0x5UL) /*!< (unspecified)                                           */
41476   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_6 (0x6UL) /*!< (unspecified)                                           */
41477   #define I3CCORE_DMA_CH1_CTL1L_SRCTRWIDTH_SRC_TR_WIDTH_7 (0x7UL) /*!< (unspecified)                                           */
41478 
41479 /* DINC @Bits 7..8 : Destination Address Increment. */
41480   #define I3CCORE_DMA_CH1_CTL1L_DINC_Pos (7UL)       /*!< Position of DINC field.                                              */
41481   #define I3CCORE_DMA_CH1_CTL1L_DINC_Msk (0x3UL << I3CCORE_DMA_CH1_CTL1L_DINC_Pos) /*!< Bit mask of DINC field.                */
41482   #define I3CCORE_DMA_CH1_CTL1L_DINC_Min (0x0UL)     /*!< Min enumerator value of DINC field.                                  */
41483   #define I3CCORE_DMA_CH1_CTL1L_DINC_Max (0x3UL)     /*!< Max enumerator value of DINC field.                                  */
41484   #define I3CCORE_DMA_CH1_CTL1L_DINC_DINC_0 (0x0UL)  /*!< (unspecified)                                                        */
41485   #define I3CCORE_DMA_CH1_CTL1L_DINC_DINC_1 (0x1UL)  /*!< (unspecified)                                                        */
41486   #define I3CCORE_DMA_CH1_CTL1L_DINC_DINC_2 (0x2UL)  /*!< (unspecified)                                                        */
41487   #define I3CCORE_DMA_CH1_CTL1L_DINC_DINC_3 (0x3UL)  /*!< (unspecified)                                                        */
41488 
41489 /* SINC @Bits 9..10 : Source Address Increment. */
41490   #define I3CCORE_DMA_CH1_CTL1L_SINC_Pos (9UL)       /*!< Position of SINC field.                                              */
41491   #define I3CCORE_DMA_CH1_CTL1L_SINC_Msk (0x3UL << I3CCORE_DMA_CH1_CTL1L_SINC_Pos) /*!< Bit mask of SINC field.                */
41492   #define I3CCORE_DMA_CH1_CTL1L_SINC_Min (0x0UL)     /*!< Min enumerator value of SINC field.                                  */
41493   #define I3CCORE_DMA_CH1_CTL1L_SINC_Max (0x3UL)     /*!< Max enumerator value of SINC field.                                  */
41494   #define I3CCORE_DMA_CH1_CTL1L_SINC_SINC_0 (0x0UL)  /*!< (unspecified)                                                        */
41495   #define I3CCORE_DMA_CH1_CTL1L_SINC_SINC_1 (0x1UL)  /*!< (unspecified)                                                        */
41496   #define I3CCORE_DMA_CH1_CTL1L_SINC_SINC_2 (0x2UL)  /*!< (unspecified)                                                        */
41497   #define I3CCORE_DMA_CH1_CTL1L_SINC_SINC_3 (0x3UL)  /*!< (unspecified)                                                        */
41498 
41499 /* DESTMSIZE @Bits 11..13 : Destination Burst Transaction Length. */
41500   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Pos (11UL) /*!< Position of DESTMSIZE field.                                         */
41501   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Pos) /*!< Bit mask of DESTMSIZE field. */
41502   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Min (0x0UL) /*!< Min enumerator value of DESTMSIZE field.                            */
41503   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_Max (0x7UL) /*!< Max enumerator value of DESTMSIZE field.                            */
41504   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_0 (0x0UL) /*!< (unspecified)                                              */
41505   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_1 (0x1UL) /*!< (unspecified)                                              */
41506   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_2 (0x2UL) /*!< (unspecified)                                              */
41507   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_3 (0x3UL) /*!< (unspecified)                                              */
41508   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_4 (0x4UL) /*!< (unspecified)                                              */
41509   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_5 (0x5UL) /*!< (unspecified)                                              */
41510   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_6 (0x6UL) /*!< (unspecified)                                              */
41511   #define I3CCORE_DMA_CH1_CTL1L_DESTMSIZE_DEST_MSIZE_7 (0x7UL) /*!< (unspecified)                                              */
41512 
41513 /* SRCMSIZE @Bits 14..16 : Source Burst Transaction Length. */
41514   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Pos (14UL)  /*!< Position of SRCMSIZE field.                                          */
41515   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Pos) /*!< Bit mask of SRCMSIZE field.    */
41516   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Min (0x0UL) /*!< Min enumerator value of SRCMSIZE field.                              */
41517   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_Max (0x7UL) /*!< Max enumerator value of SRCMSIZE field.                              */
41518   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_0 (0x0UL) /*!< (unspecified)                                                */
41519   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_1 (0x1UL) /*!< (unspecified)                                                */
41520   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_2 (0x2UL) /*!< (unspecified)                                                */
41521   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_3 (0x3UL) /*!< (unspecified)                                                */
41522   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_4 (0x4UL) /*!< (unspecified)                                                */
41523   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_5 (0x5UL) /*!< (unspecified)                                                */
41524   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_6 (0x6UL) /*!< (unspecified)                                                */
41525   #define I3CCORE_DMA_CH1_CTL1L_SRCMSIZE_SRC_MSIZE_7 (0x7UL) /*!< (unspecified)                                                */
41526 
41527 /* SRCGATHEREN @Bit 17 : Source gather enable. */
41528   #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Pos (17UL) /*!< Position of SRCGATHEREN field.                                     */
41529   #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Pos) /*!< Bit mask of SRCGATHEREN
41530                                                                             field.*/
41531   #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Min (0x0UL) /*!< Min enumerator value of SRCGATHEREN field.                        */
41532   #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_Max (0x1UL) /*!< Max enumerator value of SRCGATHEREN field.                        */
41533   #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_SRC_GATHER_DISABLE (0x0UL) /*!< (unspecified)                                      */
41534   #define I3CCORE_DMA_CH1_CTL1L_SRCGATHEREN_SRC_GATHER_ENABLE (0x1UL) /*!< (unspecified)                                       */
41535 
41536 /* RSVDDSTSCATTEREN @Bit 18 : Reserved field - read-only */
41537   #define I3CCORE_DMA_CH1_CTL1L_RSVDDSTSCATTEREN_Pos (18UL) /*!< Position of RSVDDSTSCATTEREN field.                           */
41538   #define I3CCORE_DMA_CH1_CTL1L_RSVDDSTSCATTEREN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_RSVDDSTSCATTEREN_Pos) /*!< Bit mask of
41539                                                                             RSVDDSTSCATTEREN field.*/
41540 
41541 /* RSVDCTL @Bit 19 : Reserved field - read-only */
41542   #define I3CCORE_DMA_CH1_CTL1L_RSVDCTL_Pos (19UL)   /*!< Position of RSVDCTL field.                                           */
41543   #define I3CCORE_DMA_CH1_CTL1L_RSVDCTL_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_RSVDCTL_Pos) /*!< Bit mask of RSVDCTL field.       */
41544 
41545 /* TTFC @Bits 20..22 : Transfer Type and Flow Control. */
41546   #define I3CCORE_DMA_CH1_CTL1L_TTFC_Pos (20UL)      /*!< Position of TTFC field.                                              */
41547   #define I3CCORE_DMA_CH1_CTL1L_TTFC_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_TTFC_Pos) /*!< Bit mask of TTFC field.                */
41548   #define I3CCORE_DMA_CH1_CTL1L_TTFC_Min (0x0UL)     /*!< Min enumerator value of TTFC field.                                  */
41549   #define I3CCORE_DMA_CH1_CTL1L_TTFC_Max (0x7UL)     /*!< Max enumerator value of TTFC field.                                  */
41550   #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_0 (0x0UL) /*!< (unspecified)                                                        */
41551   #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_1 (0x1UL) /*!< (unspecified)                                                        */
41552   #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_2 (0x2UL) /*!< (unspecified)                                                        */
41553   #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_3 (0x3UL) /*!< (unspecified)                                                        */
41554   #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_4 (0x4UL) /*!< (unspecified)                                                        */
41555   #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_5 (0x5UL) /*!< (unspecified)                                                        */
41556   #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_6 (0x6UL) /*!< (unspecified)                                                        */
41557   #define I3CCORE_DMA_CH1_CTL1L_TTFC_TT_FC_7 (0x7UL) /*!< (unspecified)                                                        */
41558 
41559 /* RSVDDMS @Bits 23..24 : Reserved field - read-only */
41560   #define I3CCORE_DMA_CH1_CTL1L_RSVDDMS_Pos (23UL)   /*!< Position of RSVDDMS field.                                           */
41561   #define I3CCORE_DMA_CH1_CTL1L_RSVDDMS_Msk (0x3UL << I3CCORE_DMA_CH1_CTL1L_RSVDDMS_Pos) /*!< Bit mask of RSVDDMS field.       */
41562 
41563 /* RSVDSMS @Bits 25..26 : Reserved field - read-only */
41564   #define I3CCORE_DMA_CH1_CTL1L_RSVDSMS_Pos (25UL)   /*!< Position of RSVDSMS field.                                           */
41565   #define I3CCORE_DMA_CH1_CTL1L_RSVDSMS_Msk (0x3UL << I3CCORE_DMA_CH1_CTL1L_RSVDSMS_Pos) /*!< Bit mask of RSVDSMS field.       */
41566 
41567 /* RSVDLLPDSTEN @Bit 27 : Reserved field - read-only */
41568   #define I3CCORE_DMA_CH1_CTL1L_RSVDLLPDSTEN_Pos (27UL) /*!< Position of RSVDLLPDSTEN field.                                   */
41569   #define I3CCORE_DMA_CH1_CTL1L_RSVDLLPDSTEN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_RSVDLLPDSTEN_Pos) /*!< Bit mask of RSVDLLPDSTEN
41570                                                                             field.*/
41571 
41572 /* RSVDLLPSRCEN @Bit 28 : Reserved field - read-only */
41573   #define I3CCORE_DMA_CH1_CTL1L_RSVDLLPSRCEN_Pos (28UL) /*!< Position of RSVDLLPSRCEN field.                                   */
41574   #define I3CCORE_DMA_CH1_CTL1L_RSVDLLPSRCEN_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1L_RSVDLLPSRCEN_Pos) /*!< Bit mask of RSVDLLPSRCEN
41575                                                                             field.*/
41576 
41577 /* RSVD1CTL @Bits 29..31 : Reserved field - read-only */
41578   #define I3CCORE_DMA_CH1_CTL1L_RSVD1CTL_Pos (29UL)  /*!< Position of RSVD1CTL field.                                          */
41579   #define I3CCORE_DMA_CH1_CTL1L_RSVD1CTL_Msk (0x7UL << I3CCORE_DMA_CH1_CTL1L_RSVD1CTL_Pos) /*!< Bit mask of RSVD1CTL field.    */
41580 
41581 
41582 /* I3CCORE_DMA_CH1_CTL1H: This register contains fields that control the DMA transfer. */
41583   #define I3CCORE_DMA_CH1_CTL1H_ResetValue (0x00000002UL) /*!< Reset value of CTL1H register.                                  */
41584 
41585 /* BLOCKTS @Bits 0..4 : Block Transfer Size. */
41586   #define I3CCORE_DMA_CH1_CTL1H_BLOCKTS_Pos (0UL)    /*!< Position of BLOCKTS field.                                           */
41587   #define I3CCORE_DMA_CH1_CTL1H_BLOCKTS_Msk (0x1FUL << I3CCORE_DMA_CH1_CTL1H_BLOCKTS_Pos) /*!< Bit mask of BLOCKTS field.      */
41588 
41589 /* RSVD2CTL @Bits 5..11 : Reserved field - read-only */
41590   #define I3CCORE_DMA_CH1_CTL1H_RSVD2CTL_Pos (5UL)   /*!< Position of RSVD2CTL field.                                          */
41591   #define I3CCORE_DMA_CH1_CTL1H_RSVD2CTL_Msk (0x7FUL << I3CCORE_DMA_CH1_CTL1H_RSVD2CTL_Pos) /*!< Bit mask of RSVD2CTL field.   */
41592 
41593 /* DONE @Bit 12 : Done bit. */
41594   #define I3CCORE_DMA_CH1_CTL1H_DONE_Pos (12UL)      /*!< Position of DONE field.                                              */
41595   #define I3CCORE_DMA_CH1_CTL1H_DONE_Msk (0x1UL << I3CCORE_DMA_CH1_CTL1H_DONE_Pos) /*!< Bit mask of DONE field.                */
41596   #define I3CCORE_DMA_CH1_CTL1H_DONE_Min (0x0UL)     /*!< Min enumerator value of DONE field.                                  */
41597   #define I3CCORE_DMA_CH1_CTL1H_DONE_Max (0x1UL)     /*!< Max enumerator value of DONE field.                                  */
41598   #define I3CCORE_DMA_CH1_CTL1H_DONE_DISABLED (0x0UL) /*!< (unspecified)                                                       */
41599   #define I3CCORE_DMA_CH1_CTL1H_DONE_ENABLED (0x1UL) /*!< (unspecified)                                                        */
41600 
41601 
41602 /* I3CCORE_DMA_CH1_CFG1L: This register contains fields that configure the DMA transfer. */
41603   #define I3CCORE_DMA_CH1_CFG1L_ResetValue (0x00000E20UL) /*!< Reset value of CFG1L register.                                  */
41604 
41605 /* RSVDCFG @Bits 0..4 : Reserved field - read-only */
41606   #define I3CCORE_DMA_CH1_CFG1L_RSVDCFG_Pos (0UL)    /*!< Position of RSVDCFG field.                                           */
41607   #define I3CCORE_DMA_CH1_CFG1L_RSVDCFG_Msk (0x1FUL << I3CCORE_DMA_CH1_CFG1L_RSVDCFG_Pos) /*!< Bit mask of RSVDCFG field.      */
41608 
41609 /* CHPRIOR @Bits 5..7 : Channel Priority. */
41610   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Pos (5UL)    /*!< Position of CHPRIOR field.                                           */
41611   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Msk (0x7UL << I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Pos) /*!< Bit mask of CHPRIOR field.       */
41612   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Min (0x0UL)  /*!< Min enumerator value of CHPRIOR field.                               */
41613   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_Max (0x7UL)  /*!< Max enumerator value of CHPRIOR field.                               */
41614   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_0 (0x0UL) /*!< (unspecified)                                                  */
41615   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_1 (0x1UL) /*!< (unspecified)                                                  */
41616   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_2 (0x2UL) /*!< (unspecified)                                                  */
41617   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_3 (0x3UL) /*!< (unspecified)                                                  */
41618   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_4 (0x4UL) /*!< (unspecified)                                                  */
41619   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_5 (0x5UL) /*!< (unspecified)                                                  */
41620   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_6 (0x6UL) /*!< (unspecified)                                                  */
41621   #define I3CCORE_DMA_CH1_CFG1L_CHPRIOR_CH_PRIOR_7 (0x7UL) /*!< (unspecified)                                                  */
41622 
41623 /* CHSUSP @Bit 8 : Channel Suspend. */
41624   #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_Pos (8UL)     /*!< Position of CHSUSP field.                                            */
41625   #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_CHSUSP_Pos) /*!< Bit mask of CHSUSP field.          */
41626   #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_Min (0x0UL)   /*!< Min enumerator value of CHSUSP field.                                */
41627   #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_Max (0x1UL)   /*!< Max enumerator value of CHSUSP field.                                */
41628   #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_NOT_SUSPENDED (0x0UL) /*!< (unspecified)                                                */
41629   #define I3CCORE_DMA_CH1_CFG1L_CHSUSP_SUSPENDED (0x1UL) /*!< (unspecified)                                                    */
41630 
41631 /* FIFOEMPTY @Bit 9 : Channel FIFO status. */
41632   #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Pos (9UL)  /*!< Position of FIFOEMPTY field.                                         */
41633   #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Pos) /*!< Bit mask of FIFOEMPTY field. */
41634   #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Min (0x0UL) /*!< Min enumerator value of FIFOEMPTY field.                            */
41635   #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_Max (0x1UL) /*!< Max enumerator value of FIFOEMPTY field.                            */
41636   #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_NOT_EMPTY (0x0UL) /*!< (unspecified)                                                 */
41637   #define I3CCORE_DMA_CH1_CFG1L_FIFOEMPTY_EMPTY (0x1UL) /*!< (unspecified)                                                     */
41638 
41639 /* HSSELDST @Bit 10 : Destination Software or Hardware Handshaking Select. */
41640   #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_Pos (10UL)  /*!< Position of HSSELDST field.                                          */
41641   #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_HSSELDST_Pos) /*!< Bit mask of HSSELDST field.    */
41642   #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_Min (0x0UL) /*!< Min enumerator value of HSSELDST field.                              */
41643   #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_Max (0x1UL) /*!< Max enumerator value of HSSELDST field.                              */
41644   #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_HARDWARE_HS (0x0UL) /*!< (unspecified)                                                */
41645   #define I3CCORE_DMA_CH1_CFG1L_HSSELDST_SOFTWARE_HS (0x1UL) /*!< (unspecified)                                                */
41646 
41647 /* HSSELSRC @Bit 11 : Source Software or Hardware Handshaking Select. */
41648   #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Pos (11UL)  /*!< Position of HSSELSRC field.                                          */
41649   #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Pos) /*!< Bit mask of HSSELSRC field.    */
41650   #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Min (0x0UL) /*!< Min enumerator value of HSSELSRC field.                              */
41651   #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_Max (0x1UL) /*!< Max enumerator value of HSSELSRC field.                              */
41652   #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_HARDWARE_HS (0x0UL) /*!< (unspecified)                                                */
41653   #define I3CCORE_DMA_CH1_CFG1L_HSSELSRC_SOFTWARE_HS (0x1UL) /*!< (unspecified)                                                */
41654 
41655 /* RSVDLOCKCHL @Bits 12..13 : Reserved field - read-only */
41656   #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCHL_Pos (12UL) /*!< Position of RSVDLOCKCHL field.                                     */
41657   #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCHL_Msk (0x3UL << I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCHL_Pos) /*!< Bit mask of RSVDLOCKCHL
41658                                                                             field.*/
41659 
41660 /* RSVDLOCKBL @Bits 14..15 : Reserved field - read-only */
41661   #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKBL_Pos (14UL) /*!< Position of RSVDLOCKBL field.                                       */
41662   #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKBL_Msk (0x3UL << I3CCORE_DMA_CH1_CFG1L_RSVDLOCKBL_Pos) /*!< Bit mask of RSVDLOCKBL
41663                                                                             field.*/
41664 
41665 /* RSVDLOCKCH @Bit 16 : Reserved field - read-only */
41666   #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCH_Pos (16UL) /*!< Position of RSVDLOCKCH field.                                       */
41667   #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCH_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_RSVDLOCKCH_Pos) /*!< Bit mask of RSVDLOCKCH
41668                                                                             field.*/
41669 
41670 /* RSVDLOCKB @Bit 17 : Reserved field - read-only */
41671   #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKB_Pos (17UL) /*!< Position of RSVDLOCKB field.                                         */
41672   #define I3CCORE_DMA_CH1_CFG1L_RSVDLOCKB_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_RSVDLOCKB_Pos) /*!< Bit mask of RSVDLOCKB field. */
41673 
41674 /* DSTHSPOL @Bit 18 : Destination Handshaking Interface Polarity. */
41675   #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Pos (18UL)  /*!< Position of DSTHSPOL field.                                          */
41676   #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Pos) /*!< Bit mask of DSTHSPOL field.    */
41677   #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Min (0x0UL) /*!< Min enumerator value of DSTHSPOL field.                              */
41678   #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_Max (0x1UL) /*!< Max enumerator value of DSTHSPOL field.                              */
41679   #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_ACTIVE_HIGH (0x0UL) /*!< (unspecified)                                                */
41680   #define I3CCORE_DMA_CH1_CFG1L_DSTHSPOL_ACTIVE_LOW (0x1UL) /*!< (unspecified)                                                 */
41681 
41682 /* SRCHSPOL @Bit 19 : Source Handshaking Interface Polarity. */
41683   #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Pos (19UL)  /*!< Position of SRCHSPOL field.                                          */
41684   #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Pos) /*!< Bit mask of SRCHSPOL field.    */
41685   #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Min (0x0UL) /*!< Min enumerator value of SRCHSPOL field.                              */
41686   #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_Max (0x1UL) /*!< Max enumerator value of SRCHSPOL field.                              */
41687   #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_ACTIVE_HIGH (0x0UL) /*!< (unspecified)                                                */
41688   #define I3CCORE_DMA_CH1_CFG1L_SRCHSPOL_ACTIVE_LOW (0x1UL) /*!< (unspecified)                                                 */
41689 
41690 /* MAXABRST @Bits 20..29 : Maximum AMBA Burst Length. */
41691   #define I3CCORE_DMA_CH1_CFG1L_MAXABRST_Pos (20UL)  /*!< Position of MAXABRST field.                                          */
41692   #define I3CCORE_DMA_CH1_CFG1L_MAXABRST_Msk (0x3FFUL << I3CCORE_DMA_CH1_CFG1L_MAXABRST_Pos) /*!< Bit mask of MAXABRST field.  */
41693 
41694 /* RSVDRELOADSRC @Bit 30 : Reserved field - read-only */
41695   #define I3CCORE_DMA_CH1_CFG1L_RSVDRELOADSRC_Pos (30UL) /*!< Position of RSVDRELOADSRC field.                                 */
41696   #define I3CCORE_DMA_CH1_CFG1L_RSVDRELOADSRC_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_RSVDRELOADSRC_Pos) /*!< Bit mask of
41697                                                                             RSVDRELOADSRC field.*/
41698 
41699 /* RSVDRELOADDST @Bit 31 : Reserved field- read-only */
41700   #define I3CCORE_DMA_CH1_CFG1L_RSVDRELOADDST_Pos (31UL) /*!< Position of RSVDRELOADDST field.                                 */
41701   #define I3CCORE_DMA_CH1_CFG1L_RSVDRELOADDST_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1L_RSVDRELOADDST_Pos) /*!< Bit mask of
41702                                                                             RSVDRELOADDST field.*/
41703 
41704 
41705 /* I3CCORE_DMA_CH1_CFG1H: This register contains fields that configure the DMA transfer. */
41706   #define I3CCORE_DMA_CH1_CFG1H_ResetValue (0x00000004UL) /*!< Reset value of CFG1H register.                                  */
41707 
41708 /* FCMODE @Bit 0 : Flow Control Mode. */
41709   #define I3CCORE_DMA_CH1_CFG1H_FCMODE_Pos (0UL)     /*!< Position of FCMODE field.                                            */
41710   #define I3CCORE_DMA_CH1_CFG1H_FCMODE_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_FCMODE_Pos) /*!< Bit mask of FCMODE field.          */
41711   #define I3CCORE_DMA_CH1_CFG1H_FCMODE_Min (0x0UL)   /*!< Min enumerator value of FCMODE field.                                */
41712   #define I3CCORE_DMA_CH1_CFG1H_FCMODE_Max (0x1UL)   /*!< Max enumerator value of FCMODE field.                                */
41713   #define I3CCORE_DMA_CH1_CFG1H_FCMODE_FCMODE_0 (0x0UL) /*!< (unspecified)                                                     */
41714   #define I3CCORE_DMA_CH1_CFG1H_FCMODE_FCMODE_1 (0x1UL) /*!< (unspecified)                                                     */
41715 
41716 /* FIFOMODE @Bit 1 : FIFO Mode Select. */
41717   #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Pos (1UL)   /*!< Position of FIFOMODE field.                                          */
41718   #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Pos) /*!< Bit mask of FIFOMODE field.    */
41719   #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Min (0x0UL) /*!< Min enumerator value of FIFOMODE field.                              */
41720   #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_Max (0x1UL) /*!< Max enumerator value of FIFOMODE field.                              */
41721   #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_FIFO_MODE_0 (0x0UL) /*!< (unspecified)                                                */
41722   #define I3CCORE_DMA_CH1_CFG1H_FIFOMODE_FIFO_MODE_1 (0x1UL) /*!< (unspecified)                                                */
41723 
41724 /* PROTCTL @Bits 2..4 : Protection Control bits used to drive the AHB HPROT[3:1] bus. */
41725   #define I3CCORE_DMA_CH1_CFG1H_PROTCTL_Pos (2UL)    /*!< Position of PROTCTL field.                                           */
41726   #define I3CCORE_DMA_CH1_CFG1H_PROTCTL_Msk (0x7UL << I3CCORE_DMA_CH1_CFG1H_PROTCTL_Pos) /*!< Bit mask of PROTCTL field.       */
41727 
41728 /* RSVDDSUPDEN @Bit 5 : Reserved field- read-only */
41729   #define I3CCORE_DMA_CH1_CFG1H_RSVDDSUPDEN_Pos (5UL) /*!< Position of RSVDDSUPDEN field.                                      */
41730   #define I3CCORE_DMA_CH1_CFG1H_RSVDDSUPDEN_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_RSVDDSUPDEN_Pos) /*!< Bit mask of RSVDDSUPDEN
41731                                                                             field.*/
41732 
41733 /* RSVDSSUPDEN @Bit 6 : Reserved field- read-only */
41734   #define I3CCORE_DMA_CH1_CFG1H_RSVDSSUPDEN_Pos (6UL) /*!< Position of RSVDSSUPDEN field.                                      */
41735   #define I3CCORE_DMA_CH1_CFG1H_RSVDSSUPDEN_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_RSVDSSUPDEN_Pos) /*!< Bit mask of RSVDSSUPDEN
41736                                                                             field.*/
41737 
41738 /* SRCPER @Bit 7 : Source Hardware Interface. */
41739   #define I3CCORE_DMA_CH1_CFG1H_SRCPER_Pos (7UL)     /*!< Position of SRCPER field.                                            */
41740   #define I3CCORE_DMA_CH1_CFG1H_SRCPER_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_SRCPER_Pos) /*!< Bit mask of SRCPER field.          */
41741 
41742 /* RSVD1CFG @Bits 8..10 : Reserved field - read-only */
41743   #define I3CCORE_DMA_CH1_CFG1H_RSVD1CFG_Pos (8UL)   /*!< Position of RSVD1CFG field.                                          */
41744   #define I3CCORE_DMA_CH1_CFG1H_RSVD1CFG_Msk (0x7UL << I3CCORE_DMA_CH1_CFG1H_RSVD1CFG_Pos) /*!< Bit mask of RSVD1CFG field.    */
41745 
41746 /* DESTPER @Bit 11 : Destination hardware interface. */
41747   #define I3CCORE_DMA_CH1_CFG1H_DESTPER_Pos (11UL)   /*!< Position of DESTPER field.                                           */
41748   #define I3CCORE_DMA_CH1_CFG1H_DESTPER_Msk (0x1UL << I3CCORE_DMA_CH1_CFG1H_DESTPER_Pos) /*!< Bit mask of DESTPER field.       */
41749 
41750 
41751 /* I3CCORE_DMA_CH1_SGR1: Source Gather register */
41752   #define I3CCORE_DMA_CH1_SGR1_ResetValue (0x00000000UL) /*!< Reset value of SGR1 register.                                    */
41753 
41754 /* SGI @Bits 0..19 : Source Gather Interval. */
41755   #define I3CCORE_DMA_CH1_SGR1_SGI_Pos (0UL)         /*!< Position of SGI field.                                               */
41756   #define I3CCORE_DMA_CH1_SGR1_SGI_Msk (0xFFFFFUL << I3CCORE_DMA_CH1_SGR1_SGI_Pos) /*!< Bit mask of SGI field.                 */
41757 
41758 /* SGC @Bits 20..24 : Source Gather Count. */
41759   #define I3CCORE_DMA_CH1_SGR1_SGC_Pos (20UL)        /*!< Position of SGC field.                                               */
41760   #define I3CCORE_DMA_CH1_SGR1_SGC_Msk (0x1FUL << I3CCORE_DMA_CH1_SGR1_SGC_Pos) /*!< Bit mask of SGC field.                    */
41761 
41762 
41763 
41764 /* ================================================= Struct I3CCORE_DMA_INT ================================================== */
41765 /**
41766   * @brief INT [I3CCORE_DMA_INT] (unspecified)
41767   */
41768 typedef struct {
41769   __IOM uint32_t  RAWTFR;                            /*!< (@ 0x00000000) Interrupt events are stored in this Raw Interrupt
41770                                                                          Status register before masking.*/
41771   __IM  uint32_t  RESERVED;
41772   __IOM uint32_t  RAWBLOCK;                          /*!< (@ 0x00000008) Interrupt events are stored in this Raw Interrupt
41773                                                                          Status register before masking.*/
41774   __IM  uint32_t  RESERVED1;
41775   __IOM uint32_t  RAWSRCTRAN;                        /*!< (@ 0x00000010) Interrupt events are stored in this Raw Interrupt
41776                                                                          Status register before masking.*/
41777   __IM  uint32_t  RESERVED2;
41778   __IOM uint32_t  RAWDSTTRAN;                        /*!< (@ 0x00000018) Interrupt events are stored in this Raw Interrupt
41779                                                                          Status register before masking.*/
41780   __IM  uint32_t  RESERVED3;
41781   __IOM uint32_t  RAWERR;                            /*!< (@ 0x00000020) Interrupt events are stored in this Raw Interrupt
41782                                                                          Status register before masking.*/
41783   __IM  uint32_t  RESERVED4;
41784   __IOM uint32_t  STATUSTFR;                         /*!< (@ 0x00000028) Channel DMA Transfer complete interrupt event from all
41785                                                                          channels is stored in this Interrupt Status register
41786                                                                          after masking.*/
41787   __IM  uint32_t  RESERVED5;
41788   __IOM uint32_t  STATUSBLOCK;                       /*!< (@ 0x00000030) Channel Block complete interrupt event from all
41789                                                                          channels is stored in this Interrupt Status register
41790                                                                          after masking.*/
41791   __IM  uint32_t  RESERVED6;
41792   __IOM uint32_t  STATUSSRCTRAN;                     /*!< (@ 0x00000038) Channel Source Transaction complete interrupt event
41793                                                                          from all channels is stored in this Interrupt Status
41794                                                                          register after masking.*/
41795   __IM  uint32_t  RESERVED7;
41796   __IOM uint32_t  STATUSDSTTRAN;                     /*!< (@ 0x00000040) Channel destination transaction complete interrupt
41797                                                                          event from all channels is stored in this Interrupt
41798                                                                          Status register after masking.*/
41799   __IM  uint32_t  RESERVED8;
41800   __IOM uint32_t  STATUSERR;                         /*!< (@ 0x00000048) Channel Error interrupt event from all channels is
41801                                                                          stored in this Interrupt Status register after
41802                                                                          masking.*/
41803   __IM  uint32_t  RESERVED9;
41804   __IOM uint32_t  MASKTFR;                           /*!< (@ 0x00000050) The contents of the Raw Status register RawTfr is
41805                                                                          masked with the contents of the Mask register MaskTfr.*/
41806   __IM  uint32_t  RESERVED10;
41807   __IOM uint32_t  MASKBLOCK;                         /*!< (@ 0x00000058) The contents of the Raw Status register RawBlock is
41808                                                                          masked with the contents of the Mask register
41809                                                                          MaskBlock.*/
41810   __IM  uint32_t  RESERVED11;
41811   __IOM uint32_t  MASKSRCTRAN;                       /*!< (@ 0x00000060) The contents of the Raw Status register RawSrcTran is
41812                                                                          masked with the contents of the Mask register
41813                                                                          MaskSrcTran.*/
41814   __IM  uint32_t  RESERVED12;
41815   __IOM uint32_t  MASKDSTTRAN;                       /*!< (@ 0x00000068) The contents of the Raw Status register RawDstTran is
41816                                                                          masked with the contents of the Mask register
41817                                                                          MaskDstTran.*/
41818   __IM  uint32_t  RESERVED13;
41819   __IOM uint32_t  MASKERR;                           /*!< (@ 0x00000070) The contents of the Raw Status register RawErr is
41820                                                                          masked with the contents of the Mask register MaskErr.*/
41821   __IM  uint32_t  RESERVED14;
41822   __IOM uint32_t  CLEARTFR;                          /*!< (@ 0x00000078) Each bit in the RawTfr and StatusTfr is cleared on the
41823                                                                          same cycle by writing a 1 to the corresponding location
41824                                                                          in the this registers.*/
41825   __IM  uint32_t  RESERVED15;
41826   __IOM uint32_t  CLEARBLOCK;                        /*!< (@ 0x00000080) Each bit in the RawBlock and StatusBlock is cleared on
41827                                                                          the same cycle by writing a 1 to the corresponding
41828                                                                          location in the this registers.*/
41829   __IM  uint32_t  RESERVED16;
41830   __IOM uint32_t  CLEARSRCTRAN;                      /*!< (@ 0x00000088) Each bit in the RawSrcTran and StatusSrcTran is cleared
41831                                                                          on the same cycle by writing a 1 to the corresponding
41832                                                                          location in the this registers.*/
41833   __IM  uint32_t  RESERVED17;
41834   __IOM uint32_t  CLEARDSTTRAN;                      /*!< (@ 0x00000090) Each bit in the RawDstTran and StatusDstTran is cleared
41835                                                                          on the same cycle by writing a 1 to the corresponding
41836                                                                          location in the this registers.*/
41837   __IM  uint32_t  RESERVED18;
41838   __IOM uint32_t  CLEARERR;                          /*!< (@ 0x00000098) Each bit in the RawErr and StatusErr is cleared on the
41839                                                                          same cycle by writing a 1 to the corresponding location
41840                                                                          in the this registers.*/
41841   __IM  uint32_t  RESERVED19;
41842   __IOM uint32_t  STATUSINT;                         /*!< (@ 0x000000A0) The contents of each of the five Status registers
41843                                                                          StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran,
41844                                                                          StatusErr is ORed to produce a single bit for each
41845                                                                          interrupt type in the Combined Status register
41846                                                                          (StatusInt).*/
41847 } NRF_I3CCORE_DMA_INT_Type;                          /*!< Size = 164 (0x0A4)                                                   */
41848 
41849 /* I3CCORE_DMA_INT_RAWTFR: Interrupt events are stored in this Raw Interrupt Status register before masking. */
41850   #define I3CCORE_DMA_INT_RAWTFR_ResetValue (0x00000000UL) /*!< Reset value of RAWTFR register.                                */
41851 
41852 /* RAW @Bits 0..1 : Raw Status for IntTfr Interrupt */
41853   #define I3CCORE_DMA_INT_RAWTFR_RAW_Pos (0UL)       /*!< Position of RAW field.                                               */
41854   #define I3CCORE_DMA_INT_RAWTFR_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWTFR_RAW_Pos) /*!< Bit mask of RAW field.                 */
41855   #define I3CCORE_DMA_INT_RAWTFR_RAW_Min (0x0UL)     /*!< Min enumerator value of RAW field.                                   */
41856   #define I3CCORE_DMA_INT_RAWTFR_RAW_Max (0x1UL)     /*!< Max enumerator value of RAW field.                                   */
41857   #define I3CCORE_DMA_INT_RAWTFR_RAW_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
41858   #define I3CCORE_DMA_INT_RAWTFR_RAW_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
41859 
41860 
41861 /* I3CCORE_DMA_INT_RAWBLOCK: Interrupt events are stored in this Raw Interrupt Status register before masking. */
41862   #define I3CCORE_DMA_INT_RAWBLOCK_ResetValue (0x00000000UL) /*!< Reset value of RAWBLOCK register.                            */
41863 
41864 /* RAW @Bits 0..1 : Raw Status for IntBlock Interrupt */
41865   #define I3CCORE_DMA_INT_RAWBLOCK_RAW_Pos (0UL)     /*!< Position of RAW field.                                               */
41866   #define I3CCORE_DMA_INT_RAWBLOCK_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWBLOCK_RAW_Pos) /*!< Bit mask of RAW field.             */
41867   #define I3CCORE_DMA_INT_RAWBLOCK_RAW_Min (0x0UL)   /*!< Min enumerator value of RAW field.                                   */
41868   #define I3CCORE_DMA_INT_RAWBLOCK_RAW_Max (0x1UL)   /*!< Max enumerator value of RAW field.                                   */
41869   #define I3CCORE_DMA_INT_RAWBLOCK_RAW_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
41870   #define I3CCORE_DMA_INT_RAWBLOCK_RAW_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
41871 
41872 
41873 /* I3CCORE_DMA_INT_RAWSRCTRAN: Interrupt events are stored in this Raw Interrupt Status register before masking. */
41874   #define I3CCORE_DMA_INT_RAWSRCTRAN_ResetValue (0x00000000UL) /*!< Reset value of RAWSRCTRAN register.                        */
41875 
41876 /* RAW @Bits 0..1 : Raw Status for IntSrcTran Interrupt */
41877   #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Pos (0UL)   /*!< Position of RAW field.                                               */
41878   #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Pos) /*!< Bit mask of RAW field.         */
41879   #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Min (0x0UL) /*!< Min enumerator value of RAW field.                                   */
41880   #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_Max (0x1UL) /*!< Max enumerator value of RAW field.                                   */
41881   #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
41882   #define I3CCORE_DMA_INT_RAWSRCTRAN_RAW_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
41883 
41884 
41885 /* I3CCORE_DMA_INT_RAWDSTTRAN: Interrupt events are stored in this Raw Interrupt Status register before masking. */
41886   #define I3CCORE_DMA_INT_RAWDSTTRAN_ResetValue (0x00000000UL) /*!< Reset value of RAWDSTTRAN register.                        */
41887 
41888 /* RAW @Bits 0..1 : Raw Status for IntDstTran Interrupt */
41889   #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Pos (0UL)   /*!< Position of RAW field.                                               */
41890   #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Pos) /*!< Bit mask of RAW field.         */
41891   #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Min (0x0UL) /*!< Min enumerator value of RAW field.                                   */
41892   #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_Max (0x1UL) /*!< Max enumerator value of RAW field.                                   */
41893   #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
41894   #define I3CCORE_DMA_INT_RAWDSTTRAN_RAW_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
41895 
41896 
41897 /* I3CCORE_DMA_INT_RAWERR: Interrupt events are stored in this Raw Interrupt Status register before masking. */
41898   #define I3CCORE_DMA_INT_RAWERR_ResetValue (0x00000000UL) /*!< Reset value of RAWERR register.                                */
41899 
41900 /* RAW @Bits 0..1 : Raw Status for IntErr Interrupt */
41901   #define I3CCORE_DMA_INT_RAWERR_RAW_Pos (0UL)       /*!< Position of RAW field.                                               */
41902   #define I3CCORE_DMA_INT_RAWERR_RAW_Msk (0x3UL << I3CCORE_DMA_INT_RAWERR_RAW_Pos) /*!< Bit mask of RAW field.                 */
41903   #define I3CCORE_DMA_INT_RAWERR_RAW_Min (0x0UL)     /*!< Min enumerator value of RAW field.                                   */
41904   #define I3CCORE_DMA_INT_RAWERR_RAW_Max (0x1UL)     /*!< Max enumerator value of RAW field.                                   */
41905   #define I3CCORE_DMA_INT_RAWERR_RAW_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
41906   #define I3CCORE_DMA_INT_RAWERR_RAW_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
41907 
41908 
41909 /* I3CCORE_DMA_INT_STATUSTFR: Channel DMA Transfer complete interrupt event from all channels is stored in this Interrupt Status
41910                                register after masking. */
41911 
41912   #define I3CCORE_DMA_INT_STATUSTFR_ResetValue (0x00000000UL) /*!< Reset value of STATUSTFR register.                          */
41913 
41914 /* STATUS @Bits 0..1 : Status for IntTfr Interrupt */
41915   #define I3CCORE_DMA_INT_STATUSTFR_STATUS_Pos (0UL) /*!< Position of STATUS field.                                            */
41916   #define I3CCORE_DMA_INT_STATUSTFR_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSTFR_STATUS_Pos) /*!< Bit mask of STATUS field.  */
41917   #define I3CCORE_DMA_INT_STATUSTFR_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field.                              */
41918   #define I3CCORE_DMA_INT_STATUSTFR_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field.                              */
41919   #define I3CCORE_DMA_INT_STATUSTFR_STATUS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
41920   #define I3CCORE_DMA_INT_STATUSTFR_STATUS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
41921 
41922 
41923 /* I3CCORE_DMA_INT_STATUSBLOCK: Channel Block complete interrupt event from all channels is stored in this Interrupt Status
41924                                  register after masking. */
41925 
41926   #define I3CCORE_DMA_INT_STATUSBLOCK_ResetValue (0x00000000UL) /*!< Reset value of STATUSBLOCK register.                      */
41927 
41928 /* STATUS @Bits 0..1 : Status for IntBlock Interrupt */
41929   #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Pos (0UL) /*!< Position of STATUS field.                                          */
41930   #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Pos) /*!< Bit mask of STATUS
41931                                                                             field.*/
41932   #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field.                            */
41933   #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field.                            */
41934   #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_INACTIVE (0x0UL) /*!< (unspecified)                                               */
41935   #define I3CCORE_DMA_INT_STATUSBLOCK_STATUS_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
41936 
41937 
41938 /* I3CCORE_DMA_INT_STATUSSRCTRAN: Channel Source Transaction complete interrupt event from all channels is stored in this
41939                                    Interrupt Status register after masking. */
41940 
41941   #define I3CCORE_DMA_INT_STATUSSRCTRAN_ResetValue (0x00000000UL) /*!< Reset value of STATUSSRCTRAN register.                  */
41942 
41943 /* STATUS @Bits 0..1 : Status for IntSrcTran Interrupt */
41944   #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Pos (0UL) /*!< Position of STATUS field.                                        */
41945   #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Pos) /*!< Bit mask of STATUS
41946                                                                             field.*/
41947   #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field.                          */
41948   #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field.                          */
41949   #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_INACTIVE (0x0UL) /*!< (unspecified)                                             */
41950   #define I3CCORE_DMA_INT_STATUSSRCTRAN_STATUS_ACTIVE (0x1UL) /*!< (unspecified)                                               */
41951 
41952 
41953 /* I3CCORE_DMA_INT_STATUSDSTTRAN: Channel destination transaction complete interrupt event from all channels is stored in this
41954                                    Interrupt Status register after masking. */
41955 
41956   #define I3CCORE_DMA_INT_STATUSDSTTRAN_ResetValue (0x00000000UL) /*!< Reset value of STATUSDSTTRAN register.                  */
41957 
41958 /* STATUS @Bits 0..1 : Status for IntDstTran Interrupt */
41959   #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Pos (0UL) /*!< Position of STATUS field.                                        */
41960   #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Pos) /*!< Bit mask of STATUS
41961                                                                             field.*/
41962   #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field.                          */
41963   #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field.                          */
41964   #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_INACTIVE (0x0UL) /*!< (unspecified)                                             */
41965   #define I3CCORE_DMA_INT_STATUSDSTTRAN_STATUS_ACTIVE (0x1UL) /*!< (unspecified)                                               */
41966 
41967 
41968 /* I3CCORE_DMA_INT_STATUSERR: Channel Error interrupt event from all channels is stored in this Interrupt Status register after
41969                                masking. */
41970 
41971   #define I3CCORE_DMA_INT_STATUSERR_ResetValue (0x00000000UL) /*!< Reset value of STATUSERR register.                          */
41972 
41973 /* STATUS @Bits 0..1 : Status for IntErr Interrupt */
41974   #define I3CCORE_DMA_INT_STATUSERR_STATUS_Pos (0UL) /*!< Position of STATUS field.                                            */
41975   #define I3CCORE_DMA_INT_STATUSERR_STATUS_Msk (0x3UL << I3CCORE_DMA_INT_STATUSERR_STATUS_Pos) /*!< Bit mask of STATUS field.  */
41976   #define I3CCORE_DMA_INT_STATUSERR_STATUS_Min (0x0UL) /*!< Min enumerator value of STATUS field.                              */
41977   #define I3CCORE_DMA_INT_STATUSERR_STATUS_Max (0x1UL) /*!< Max enumerator value of STATUS field.                              */
41978   #define I3CCORE_DMA_INT_STATUSERR_STATUS_INACTIVE (0x0UL) /*!< (unspecified)                                                 */
41979   #define I3CCORE_DMA_INT_STATUSERR_STATUS_ACTIVE (0x1UL) /*!< (unspecified)                                                   */
41980 
41981 
41982 /* I3CCORE_DMA_INT_MASKTFR: The contents of the Raw Status register RawTfr is masked with the contents of the Mask register
41983                              MaskTfr. */
41984 
41985   #define I3CCORE_DMA_INT_MASKTFR_ResetValue (0x00000000UL) /*!< Reset value of MASKTFR register.                              */
41986 
41987 /* INTMASK @Bits 0..1 : Mask for IntTfr Interrupt */
41988   #define I3CCORE_DMA_INT_MASKTFR_INTMASK_Pos (0UL)  /*!< Position of INTMASK field.                                           */
41989   #define I3CCORE_DMA_INT_MASKTFR_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKTFR_INTMASK_Pos) /*!< Bit mask of INTMASK field.   */
41990   #define I3CCORE_DMA_INT_MASKTFR_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field.                              */
41991   #define I3CCORE_DMA_INT_MASKTFR_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field.                              */
41992   #define I3CCORE_DMA_INT_MASKTFR_INTMASK_MASK (0x0UL) /*!< (unspecified)                                                      */
41993   #define I3CCORE_DMA_INT_MASKTFR_INTMASK_UNMASK (0x1UL) /*!< (unspecified)                                                    */
41994 
41995 /* RSVDMASKTFR @Bits 2..7 : Reserved field - read-only */
41996   #define I3CCORE_DMA_INT_MASKTFR_RSVDMASKTFR_Pos (2UL) /*!< Position of RSVDMASKTFR field.                                    */
41997   #define I3CCORE_DMA_INT_MASKTFR_RSVDMASKTFR_Msk (0x3FUL << I3CCORE_DMA_INT_MASKTFR_RSVDMASKTFR_Pos) /*!< Bit mask of
41998                                                                             RSVDMASKTFR field.*/
41999 
42000 /* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */
42001   #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field.                                        */
42002   #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Pos) /*!< Bit mask of INTMASKWE
42003                                                                             field.*/
42004   #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field.                          */
42005   #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field.                          */
42006   #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified)                                                */
42007   #define I3CCORE_DMA_INT_MASKTFR_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified)                                                 */
42008 
42009 
42010 /* I3CCORE_DMA_INT_MASKBLOCK: The contents of the Raw Status register RawBlock is masked with the contents of the Mask register
42011                                MaskBlock. */
42012 
42013   #define I3CCORE_DMA_INT_MASKBLOCK_ResetValue (0x00000000UL) /*!< Reset value of MASKBLOCK register.                          */
42014 
42015 /* INTMASK @Bits 0..1 : Mask for IntBlock Interrupt */
42016   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Pos (0UL) /*!< Position of INTMASK field.                                          */
42017   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Pos) /*!< Bit mask of INTMASK
42018                                                                             field.*/
42019   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field.                            */
42020   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field.                            */
42021   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_MASK (0x0UL) /*!< (unspecified)                                                    */
42022   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASK_UNMASK (0x1UL) /*!< (unspecified)                                                  */
42023 
42024 /* RSVDMASKBLOCK @Bits 2..7 : Reserved field- read-only */
42025   #define I3CCORE_DMA_INT_MASKBLOCK_RSVDMASKBLOCK_Pos (2UL) /*!< Position of RSVDMASKBLOCK field.                              */
42026   #define I3CCORE_DMA_INT_MASKBLOCK_RSVDMASKBLOCK_Msk (0x3FUL << I3CCORE_DMA_INT_MASKBLOCK_RSVDMASKBLOCK_Pos) /*!< Bit mask of
42027                                                                             RSVDMASKBLOCK field.*/
42028 
42029 /* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */
42030   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field.                                      */
42031   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Pos) /*!< Bit mask of INTMASKWE
42032                                                                             field.*/
42033   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field.                        */
42034   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field.                        */
42035   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified)                                              */
42036   #define I3CCORE_DMA_INT_MASKBLOCK_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified)                                               */
42037 
42038 
42039 /* I3CCORE_DMA_INT_MASKSRCTRAN: The contents of the Raw Status register RawSrcTran is masked with the contents of the Mask
42040                                  register MaskSrcTran. */
42041 
42042   #define I3CCORE_DMA_INT_MASKSRCTRAN_ResetValue (0x00000000UL) /*!< Reset value of MASKSRCTRAN register.                      */
42043 
42044 /* INTMASK @Bits 0..1 : Mask for IntSrcTran Interrupt */
42045   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Pos (0UL) /*!< Position of INTMASK field.                                        */
42046   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Pos) /*!< Bit mask of INTMASK
42047                                                                             field.*/
42048   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field.                          */
42049   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field.                          */
42050   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_MASK (0x0UL) /*!< (unspecified)                                                  */
42051   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASK_UNMASK (0x1UL) /*!< (unspecified)                                                */
42052 
42053 /* RSVDMASKSRCTRAN @Bits 2..7 : Reserved field- read-only */
42054   #define I3CCORE_DMA_INT_MASKSRCTRAN_RSVDMASKSRCTRAN_Pos (2UL) /*!< Position of RSVDMASKSRCTRAN field.                        */
42055   #define I3CCORE_DMA_INT_MASKSRCTRAN_RSVDMASKSRCTRAN_Msk (0x3FUL << I3CCORE_DMA_INT_MASKSRCTRAN_RSVDMASKSRCTRAN_Pos) /*!< Bit
42056                                                                             mask of RSVDMASKSRCTRAN field.*/
42057 
42058 /* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */
42059   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field.                                    */
42060   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Pos) /*!< Bit mask of
42061                                                                             INTMASKWE field.*/
42062   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field.                      */
42063   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field.                      */
42064   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified)                                            */
42065   #define I3CCORE_DMA_INT_MASKSRCTRAN_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified)                                             */
42066 
42067 
42068 /* I3CCORE_DMA_INT_MASKDSTTRAN: The contents of the Raw Status register RawDstTran is masked with the contents of the Mask
42069                                  register MaskDstTran. */
42070 
42071   #define I3CCORE_DMA_INT_MASKDSTTRAN_ResetValue (0x00000000UL) /*!< Reset value of MASKDSTTRAN register.                      */
42072 
42073 /* INTMASK @Bits 0..1 : Mask for IntDstTran Interrupt */
42074   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Pos (0UL) /*!< Position of INTMASK field.                                        */
42075   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Pos) /*!< Bit mask of INTMASK
42076                                                                             field.*/
42077   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field.                          */
42078   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field.                          */
42079   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_MASK (0x0UL) /*!< (unspecified)                                                  */
42080   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASK_UNMASK (0x1UL) /*!< (unspecified)                                                */
42081 
42082 /* RSVDMASKDSTTRAN @Bits 2..7 : Reserved field - read-only */
42083   #define I3CCORE_DMA_INT_MASKDSTTRAN_RSVDMASKDSTTRAN_Pos (2UL) /*!< Position of RSVDMASKDSTTRAN field.                        */
42084   #define I3CCORE_DMA_INT_MASKDSTTRAN_RSVDMASKDSTTRAN_Msk (0x3FUL << I3CCORE_DMA_INT_MASKDSTTRAN_RSVDMASKDSTTRAN_Pos) /*!< Bit
42085                                                                             mask of RSVDMASKDSTTRAN field.*/
42086 
42087 /* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */
42088   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field.                                    */
42089   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Pos) /*!< Bit mask of
42090                                                                             INTMASKWE field.*/
42091   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field.                      */
42092   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field.                      */
42093   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified)                                            */
42094   #define I3CCORE_DMA_INT_MASKDSTTRAN_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified)                                             */
42095 
42096 
42097 /* I3CCORE_DMA_INT_MASKERR: The contents of the Raw Status register RawErr is masked with the contents of the Mask register
42098                              MaskErr. */
42099 
42100   #define I3CCORE_DMA_INT_MASKERR_ResetValue (0x00000000UL) /*!< Reset value of MASKERR register.                              */
42101 
42102 /* INTMASK @Bits 0..1 : Mask for IntErr Interrupt */
42103   #define I3CCORE_DMA_INT_MASKERR_INTMASK_Pos (0UL)  /*!< Position of INTMASK field.                                           */
42104   #define I3CCORE_DMA_INT_MASKERR_INTMASK_Msk (0x3UL << I3CCORE_DMA_INT_MASKERR_INTMASK_Pos) /*!< Bit mask of INTMASK field.   */
42105   #define I3CCORE_DMA_INT_MASKERR_INTMASK_Min (0x0UL) /*!< Min enumerator value of INTMASK field.                              */
42106   #define I3CCORE_DMA_INT_MASKERR_INTMASK_Max (0x1UL) /*!< Max enumerator value of INTMASK field.                              */
42107   #define I3CCORE_DMA_INT_MASKERR_INTMASK_MASK (0x0UL) /*!< (unspecified)                                                      */
42108   #define I3CCORE_DMA_INT_MASKERR_INTMASK_UNMASK (0x1UL) /*!< (unspecified)                                                    */
42109 
42110 /* RSVDMASKERR @Bits 2..7 : Reserved field- read-only */
42111   #define I3CCORE_DMA_INT_MASKERR_RSVDMASKERR_Pos (2UL) /*!< Position of RSVDMASKERR field.                                    */
42112   #define I3CCORE_DMA_INT_MASKERR_RSVDMASKERR_Msk (0x3FUL << I3CCORE_DMA_INT_MASKERR_RSVDMASKERR_Pos) /*!< Bit mask of
42113                                                                             RSVDMASKERR field.*/
42114 
42115 /* INTMASKWE @Bits 8..9 : Interrupt Mask Write Enable */
42116   #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_Pos (8UL) /*!< Position of INTMASKWE field.                                        */
42117   #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_Msk (0x3UL << I3CCORE_DMA_INT_MASKERR_INTMASKWE_Pos) /*!< Bit mask of INTMASKWE
42118                                                                             field.*/
42119   #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_Min (0x0UL) /*!< Min enumerator value of INTMASKWE field.                          */
42120   #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_Max (0x1UL) /*!< Max enumerator value of INTMASKWE field.                          */
42121   #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_DISABLED (0x0UL) /*!< (unspecified)                                                */
42122   #define I3CCORE_DMA_INT_MASKERR_INTMASKWE_ENABLED (0x1UL) /*!< (unspecified)                                                 */
42123 
42124 
42125 /* I3CCORE_DMA_INT_CLEARTFR: Each bit in the RawTfr and StatusTfr is cleared on the same cycle by writing a 1 to the
42126                               corresponding location in the this registers. */
42127 
42128   #define I3CCORE_DMA_INT_CLEARTFR_ResetValue (0x00000000UL) /*!< Reset value of CLEARTFR register.                            */
42129 
42130 /* CLEAR @Bits 0..1 : Clear for IntTfr Interrupt */
42131   #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_Pos (0UL)   /*!< Position of CLEAR field.                                             */
42132   #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARTFR_CLEAR_Pos) /*!< Bit mask of CLEAR field.       */
42133   #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_Min (0x0UL) /*!< Min enumerator value of CLEAR field.                                 */
42134   #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field.                                 */
42135   #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_NOT_CLEAR (0x0UL) /*!< (unspecified)                                                  */
42136   #define I3CCORE_DMA_INT_CLEARTFR_CLEAR_CLEAR (0x1UL) /*!< (unspecified)                                                      */
42137 
42138 
42139 /* I3CCORE_DMA_INT_CLEARBLOCK: Each bit in the RawBlock and StatusBlock is cleared on the same cycle by writing a 1 to the
42140                                 corresponding location in the this registers. */
42141 
42142   #define I3CCORE_DMA_INT_CLEARBLOCK_ResetValue (0x00000000UL) /*!< Reset value of CLEARBLOCK register.                        */
42143 
42144 /* CLEAR @Bits 0..1 : Clear for IntBlock Interrupt */
42145   #define I3CCORE_DMA_INT_CLEARBLOCK_CLEAR_Pos (0UL) /*!< Position of CLEAR field.                                             */
42146   #define I3CCORE_DMA_INT_CLEARBLOCK_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARBLOCK_CLEAR_Pos) /*!< Bit mask of CLEAR field.   */
42147 
42148 
42149 /* I3CCORE_DMA_INT_CLEARSRCTRAN: Each bit in the RawSrcTran and StatusSrcTran is cleared on the same cycle by writing a 1 to the
42150                                   corresponding location in the this registers. */
42151 
42152   #define I3CCORE_DMA_INT_CLEARSRCTRAN_ResetValue (0x00000000UL) /*!< Reset value of CLEARSRCTRAN register.                    */
42153 
42154 /* CLEAR @Bits 0..1 : Clear for IntSrcTran Interrupt */
42155   #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Pos (0UL) /*!< Position of CLEAR field.                                           */
42156   #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Pos) /*!< Bit mask of CLEAR
42157                                                                             field.*/
42158   #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Min (0x0UL) /*!< Min enumerator value of CLEAR field.                             */
42159   #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field.                             */
42160   #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_NOT_CLEAR (0x0UL) /*!< (unspecified)                                              */
42161   #define I3CCORE_DMA_INT_CLEARSRCTRAN_CLEAR_CLEAR (0x1UL) /*!< (unspecified)                                                  */
42162 
42163 
42164 /* I3CCORE_DMA_INT_CLEARDSTTRAN: Each bit in the RawDstTran and StatusDstTran is cleared on the same cycle by writing a 1 to the
42165                                   corresponding location in the this registers. */
42166 
42167   #define I3CCORE_DMA_INT_CLEARDSTTRAN_ResetValue (0x00000000UL) /*!< Reset value of CLEARDSTTRAN register.                    */
42168 
42169 /* CLEAR @Bits 0..1 : Clear for IntDstTran Interrupt */
42170   #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Pos (0UL) /*!< Position of CLEAR field.                                           */
42171   #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Pos) /*!< Bit mask of CLEAR
42172                                                                             field.*/
42173   #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Min (0x0UL) /*!< Min enumerator value of CLEAR field.                             */
42174   #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field.                             */
42175   #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_NOT_CLEAR (0x0UL) /*!< (unspecified)                                              */
42176   #define I3CCORE_DMA_INT_CLEARDSTTRAN_CLEAR_CLEAR (0x1UL) /*!< (unspecified)                                                  */
42177 
42178 
42179 /* I3CCORE_DMA_INT_CLEARERR: Each bit in the RawErr and StatusErr is cleared on the same cycle by writing a 1 to the
42180                               corresponding location in the this registers. */
42181 
42182   #define I3CCORE_DMA_INT_CLEARERR_ResetValue (0x00000000UL) /*!< Reset value of CLEARERR register.                            */
42183 
42184 /* CLEAR @Bits 0..1 : Clear for IntErr Interrupt */
42185   #define I3CCORE_DMA_INT_CLEARERR_CLEAR_Pos (0UL)   /*!< Position of CLEAR field.                                             */
42186   #define I3CCORE_DMA_INT_CLEARERR_CLEAR_Msk (0x3UL << I3CCORE_DMA_INT_CLEARERR_CLEAR_Pos) /*!< Bit mask of CLEAR field.       */
42187   #define I3CCORE_DMA_INT_CLEARERR_CLEAR_Min (0x0UL) /*!< Min enumerator value of CLEAR field.                                 */
42188   #define I3CCORE_DMA_INT_CLEARERR_CLEAR_Max (0x1UL) /*!< Max enumerator value of CLEAR field.                                 */
42189   #define I3CCORE_DMA_INT_CLEARERR_CLEAR_NOT_CLEAR (0x0UL) /*!< (unspecified)                                                  */
42190   #define I3CCORE_DMA_INT_CLEARERR_CLEAR_CLEAR (0x1UL) /*!< (unspecified)                                                      */
42191 
42192 
42193 /* I3CCORE_DMA_INT_STATUSINT: The contents of each of the five Status registers StatusTfr, StatusBlock, StatusSrcTran,
42194                                StatusDstTran, StatusErr is ORed to produce a single bit for each interrupt type in the Combined
42195                                Status register (StatusInt). */
42196 
42197   #define I3CCORE_DMA_INT_STATUSINT_ResetValue (0x00000000UL) /*!< Reset value of STATUSINT register.                          */
42198 
42199 /* TFR @Bit 0 : OR of the contents of StatusTfr register */
42200   #define I3CCORE_DMA_INT_STATUSINT_TFR_Pos (0UL)    /*!< Position of TFR field.                                               */
42201   #define I3CCORE_DMA_INT_STATUSINT_TFR_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_TFR_Pos) /*!< Bit mask of TFR field.           */
42202   #define I3CCORE_DMA_INT_STATUSINT_TFR_Min (0x0UL)  /*!< Min enumerator value of TFR field.                                   */
42203   #define I3CCORE_DMA_INT_STATUSINT_TFR_Max (0x1UL)  /*!< Max enumerator value of TFR field.                                   */
42204   #define I3CCORE_DMA_INT_STATUSINT_TFR_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
42205   #define I3CCORE_DMA_INT_STATUSINT_TFR_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
42206 
42207 /* BLOCK @Bit 1 : OR of the contents of StatusBlock register */
42208   #define I3CCORE_DMA_INT_STATUSINT_BLOCK_Pos (1UL)  /*!< Position of BLOCK field.                                             */
42209   #define I3CCORE_DMA_INT_STATUSINT_BLOCK_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_BLOCK_Pos) /*!< Bit mask of BLOCK field.     */
42210   #define I3CCORE_DMA_INT_STATUSINT_BLOCK_Min (0x0UL) /*!< Min enumerator value of BLOCK field.                                */
42211   #define I3CCORE_DMA_INT_STATUSINT_BLOCK_Max (0x1UL) /*!< Max enumerator value of BLOCK field.                                */
42212   #define I3CCORE_DMA_INT_STATUSINT_BLOCK_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
42213   #define I3CCORE_DMA_INT_STATUSINT_BLOCK_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
42214 
42215 /* SRCT @Bit 2 : OR of the contents of StatusSrcTran */
42216   #define I3CCORE_DMA_INT_STATUSINT_SRCT_Pos (2UL)   /*!< Position of SRCT field.                                              */
42217   #define I3CCORE_DMA_INT_STATUSINT_SRCT_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_SRCT_Pos) /*!< Bit mask of SRCT field.        */
42218   #define I3CCORE_DMA_INT_STATUSINT_SRCT_Min (0x0UL) /*!< Min enumerator value of SRCT field.                                  */
42219   #define I3CCORE_DMA_INT_STATUSINT_SRCT_Max (0x1UL) /*!< Max enumerator value of SRCT field.                                  */
42220   #define I3CCORE_DMA_INT_STATUSINT_SRCT_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
42221   #define I3CCORE_DMA_INT_STATUSINT_SRCT_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
42222 
42223 /* DSTT @Bit 3 : OR of the contents of StatusDstTran */
42224   #define I3CCORE_DMA_INT_STATUSINT_DSTT_Pos (3UL)   /*!< Position of DSTT field.                                              */
42225   #define I3CCORE_DMA_INT_STATUSINT_DSTT_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_DSTT_Pos) /*!< Bit mask of DSTT field.        */
42226   #define I3CCORE_DMA_INT_STATUSINT_DSTT_Min (0x0UL) /*!< Min enumerator value of DSTT field.                                  */
42227   #define I3CCORE_DMA_INT_STATUSINT_DSTT_Max (0x1UL) /*!< Max enumerator value of DSTT field.                                  */
42228   #define I3CCORE_DMA_INT_STATUSINT_DSTT_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
42229   #define I3CCORE_DMA_INT_STATUSINT_DSTT_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
42230 
42231 /* ERR @Bit 4 : OR of the contents of StatusErr */
42232   #define I3CCORE_DMA_INT_STATUSINT_ERR_Pos (4UL)    /*!< Position of ERR field.                                               */
42233   #define I3CCORE_DMA_INT_STATUSINT_ERR_Msk (0x1UL << I3CCORE_DMA_INT_STATUSINT_ERR_Pos) /*!< Bit mask of ERR field.           */
42234   #define I3CCORE_DMA_INT_STATUSINT_ERR_Min (0x0UL)  /*!< Min enumerator value of ERR field.                                   */
42235   #define I3CCORE_DMA_INT_STATUSINT_ERR_Max (0x1UL)  /*!< Max enumerator value of ERR field.                                   */
42236   #define I3CCORE_DMA_INT_STATUSINT_ERR_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
42237   #define I3CCORE_DMA_INT_STATUSINT_ERR_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
42238 
42239 
42240 
42241 /* ============================================= Struct I3CCORE_DMA_SWHANDSHAKE ============================================== */
42242 /**
42243   * @brief SWHANDSHAKE [I3CCORE_DMA_SWHANDSHAKE] (unspecified)
42244   */
42245 typedef struct {
42246   __IOM uint32_t  REQSRCREG;                         /*!< (@ 0x00000000) A bit is assigned for each channel in this register.  */
42247   __IM  uint32_t  RESERVED;
42248   __IOM uint32_t  REQDSTREG;                         /*!< (@ 0x00000008) A bit is assigned for each channel in this register.  */
42249   __IM  uint32_t  RESERVED1;
42250   __IOM uint32_t  SGLRQSRCREG;                       /*!< (@ 0x00000010) A bit is assigned for each channel in this register.  */
42251   __IM  uint32_t  RESERVED2;
42252   __IOM uint32_t  SGLRQDSTREG;                       /*!< (@ 0x00000018) A bit is assigned for each channel in this register.  */
42253   __IM  uint32_t  RESERVED3;
42254   __IOM uint32_t  LSTSRCREG;                         /*!< (@ 0x00000020) A bit is assigned for each channel in this register.  */
42255   __IM  uint32_t  RESERVED4;
42256   __IOM uint32_t  LSTDSTREG;                         /*!< (@ 0x00000028) A bit is assigned for each channel in this register.  */
42257 } NRF_I3CCORE_DMA_SWHANDSHAKE_Type;                  /*!< Size = 44 (0x02C)                                                    */
42258 
42259 /* I3CCORE_DMA_SWHANDSHAKE_REQSRCREG: A bit is assigned for each channel in this register. */
42260   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_ResetValue (0x00000000UL) /*!< Reset value of REQSRCREG register.                  */
42261 
42262 /* SRCREQ @Bits 0..1 : Source Software Transaction Request */
42263   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Pos (0UL) /*!< Position of SRCREQ field.                                    */
42264   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Pos) /*!< Bit mask of
42265                                                                             SRCREQ field.*/
42266   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Min (0x0UL) /*!< Min enumerator value of SRCREQ field.                      */
42267   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_Max (0x1UL) /*!< Max enumerator value of SRCREQ field.                      */
42268   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_INACTIVE (0x0UL) /*!< (unspecified)                                         */
42269   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQ_ACTIVE (0x1UL) /*!< (unspecified)                                           */
42270 
42271 /* RSVDREQSRCREG @Bits 2..7 : Reserved field - read-only */
42272   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_RSVDREQSRCREG_Pos (2UL) /*!< Position of RSVDREQSRCREG field.                      */
42273   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_RSVDREQSRCREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_RSVDREQSRCREG_Pos)
42274                                                                             /*!< Bit mask of RSVDREQSRCREG field.*/
42275 
42276 /* SRCREQWE @Bits 8..9 : Source Software Transaction Request write enable */
42277   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Pos (8UL) /*!< Position of SRCREQWE field.                                */
42278   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Pos) /*!< Bit mask
42279                                                                             of SRCREQWE field.*/
42280   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Min (0x0UL) /*!< Min enumerator value of SRCREQWE field.                  */
42281   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_Max (0x1UL) /*!< Max enumerator value of SRCREQWE field.                  */
42282   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_DISABLED (0x0UL) /*!< (unspecified)                                       */
42283   #define I3CCORE_DMA_SWHANDSHAKE_REQSRCREG_SRCREQWE_ENABLED (0x1UL) /*!< (unspecified)                                        */
42284 
42285 
42286 /* I3CCORE_DMA_SWHANDSHAKE_REQDSTREG: A bit is assigned for each channel in this register. */
42287   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_ResetValue (0x00000000UL) /*!< Reset value of REQDSTREG register.                  */
42288 
42289 /* DSTREQ @Bits 0..1 : Destination Software Transaction Request */
42290   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Pos (0UL) /*!< Position of DSTREQ field.                                    */
42291   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Pos) /*!< Bit mask of
42292                                                                             DSTREQ field.*/
42293   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Min (0x0UL) /*!< Min enumerator value of DSTREQ field.                      */
42294   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_Max (0x1UL) /*!< Max enumerator value of DSTREQ field.                      */
42295   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_INACTIVE (0x0UL) /*!< (unspecified)                                         */
42296   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQ_ACTIVE (0x1UL) /*!< (unspecified)                                           */
42297 
42298 /* RSVDREQDSTREG @Bits 2..7 : Reserved field - read-only */
42299   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_RSVDREQDSTREG_Pos (2UL) /*!< Position of RSVDREQDSTREG field.                      */
42300   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_RSVDREQDSTREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_RSVDREQDSTREG_Pos)
42301                                                                             /*!< Bit mask of RSVDREQDSTREG field.*/
42302 
42303 /* DSTREQWE @Bits 8..9 : Destination Software Transaction Request write enable */
42304   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Pos (8UL) /*!< Position of DSTREQWE field.                                */
42305   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Pos) /*!< Bit mask
42306                                                                             of DSTREQWE field.*/
42307   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Min (0x0UL) /*!< Min enumerator value of DSTREQWE field.                  */
42308   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_Max (0x1UL) /*!< Max enumerator value of DSTREQWE field.                  */
42309   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_DISABLED (0x0UL) /*!< (unspecified)                                       */
42310   #define I3CCORE_DMA_SWHANDSHAKE_REQDSTREG_DSTREQWE_ENABLED (0x1UL) /*!< (unspecified)                                        */
42311 
42312 
42313 /* I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG: A bit is assigned for each channel in this register. */
42314   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_ResetValue (0x00000000UL) /*!< Reset value of SGLRQSRCREG register.              */
42315 
42316 /* SRCSGLREQ @Bits 0..1 : Source Single Transaction Request */
42317   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Pos (0UL) /*!< Position of SRCSGLREQ field.                            */
42318   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Pos) /*!<
42319                                                                             Bit mask of SRCSGLREQ field.*/
42320   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Min (0x0UL) /*!< Min enumerator value of SRCSGLREQ field.              */
42321   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_Max (0x1UL) /*!< Max enumerator value of SRCSGLREQ field.              */
42322   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_INACTIVE (0x0UL) /*!< (unspecified)                                    */
42323   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQ_ACTIVE (0x1UL) /*!< (unspecified)                                      */
42324 
42325 /* RSVDSGLRQSRCREG @Bits 2..7 : Reserved field - read-only */
42326   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_RSVDSGLRQSRCREG_Pos (2UL) /*!< Position of RSVDSGLRQSRCREG field.                */
42327   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_RSVDSGLRQSRCREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_RSVDSGLRQSRCREG_Pos)
42328                                                                             /*!< Bit mask of RSVDSGLRQSRCREG field.*/
42329 
42330 /* SRCSGLREQWE @Bits 8..9 : Source Single Transaction Request write enable */
42331   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Pos (8UL) /*!< Position of SRCSGLREQWE field.                        */
42332   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Pos)
42333                                                                             /*!< Bit mask of SRCSGLREQWE field.*/
42334   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Min (0x0UL) /*!< Min enumerator value of SRCSGLREQWE field.          */
42335   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_Max (0x1UL) /*!< Max enumerator value of SRCSGLREQWE field.          */
42336   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_DISABLED (0x0UL) /*!< (unspecified)                                  */
42337   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQSRCREG_SRCSGLREQWE_ENABLED (0x1UL) /*!< (unspecified)                                   */
42338 
42339 
42340 /* I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG: A bit is assigned for each channel in this register. */
42341   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_ResetValue (0x00000000UL) /*!< Reset value of SGLRQDSTREG register.              */
42342 
42343 /* DSTSGLREQ @Bits 0..1 : Destination Single Transaction Request */
42344   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Pos (0UL) /*!< Position of DSTSGLREQ field.                            */
42345   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Pos) /*!<
42346                                                                             Bit mask of DSTSGLREQ field.*/
42347   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Min (0x0UL) /*!< Min enumerator value of DSTSGLREQ field.              */
42348   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_Max (0x1UL) /*!< Max enumerator value of DSTSGLREQ field.              */
42349   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_INACTIVE (0x0UL) /*!< (unspecified)                                    */
42350   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQ_ACTIVE (0x1UL) /*!< (unspecified)                                      */
42351 
42352 /* RSVDSGLRQDSTREG @Bits 2..7 : Reserved field - read-only */
42353   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_RSVDSGLRQDSTREG_Pos (2UL) /*!< Position of RSVDSGLRQDSTREG field.                */
42354   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_RSVDSGLRQDSTREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_RSVDSGLRQDSTREG_Pos)
42355                                                                             /*!< Bit mask of RSVDSGLRQDSTREG field.*/
42356 
42357 /* DSTSGLREQWE @Bits 8..9 : Destination Single Transaction Request write enable */
42358   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Pos (8UL) /*!< Position of DSTSGLREQWE field.                        */
42359   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Pos)
42360                                                                             /*!< Bit mask of DSTSGLREQWE field.*/
42361   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Min (0x0UL) /*!< Min enumerator value of DSTSGLREQWE field.          */
42362   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_Max (0x1UL) /*!< Max enumerator value of DSTSGLREQWE field.          */
42363   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_DISABLED (0x0UL) /*!< (unspecified)                                  */
42364   #define I3CCORE_DMA_SWHANDSHAKE_SGLRQDSTREG_DSTSGLREQWE_ENABLED (0x1UL) /*!< (unspecified)                                   */
42365 
42366 
42367 /* I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG: A bit is assigned for each channel in this register. */
42368   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_ResetValue (0x00000000UL) /*!< Reset value of LSTSRCREG register.                  */
42369 
42370 /* LSTSRC @Bits 0..1 : Source Last Transaction Request register */
42371   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Pos (0UL) /*!< Position of LSTSRC field.                                    */
42372   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Pos) /*!< Bit mask of
42373                                                                             LSTSRC field.*/
42374   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Min (0x0UL) /*!< Min enumerator value of LSTSRC field.                      */
42375   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_Max (0x1UL) /*!< Max enumerator value of LSTSRC field.                      */
42376   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_NOT_LAST (0x0UL) /*!< (unspecified)                                         */
42377   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRC_LAST (0x1UL) /*!< (unspecified)                                             */
42378 
42379 /* RSVDLSTSRCREG @Bits 2..7 : Reserved field- read-only */
42380   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_RSVDLSTSRCREG_Pos (2UL) /*!< Position of RSVDLSTSRCREG field.                      */
42381   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_RSVDLSTSRCREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_RSVDLSTSRCREG_Pos)
42382                                                                             /*!< Bit mask of RSVDLSTSRCREG field.*/
42383 
42384 /* LSTSRCWE @Bits 8..9 : Source Last Transaction Request write enable */
42385   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Pos (8UL) /*!< Position of LSTSRCWE field.                                */
42386   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Pos) /*!< Bit mask
42387                                                                             of LSTSRCWE field.*/
42388   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Min (0x0UL) /*!< Min enumerator value of LSTSRCWE field.                  */
42389   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_Max (0x1UL) /*!< Max enumerator value of LSTSRCWE field.                  */
42390   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_DISABLED (0x0UL) /*!< (unspecified)                                       */
42391   #define I3CCORE_DMA_SWHANDSHAKE_LSTSRCREG_LSTSRCWE_ENABLED (0x1UL) /*!< (unspecified)                                        */
42392 
42393 
42394 /* I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG: A bit is assigned for each channel in this register. */
42395   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_ResetValue (0x00000000UL) /*!< Reset value of LSTDSTREG register.                  */
42396 
42397 /* LSTDST @Bits 0..1 : Destination Last Transaction Request */
42398   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Pos (0UL) /*!< Position of LSTDST field.                                    */
42399   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Pos) /*!< Bit mask of
42400                                                                             LSTDST field.*/
42401   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Min (0x0UL) /*!< Min enumerator value of LSTDST field.                      */
42402   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_Max (0x1UL) /*!< Max enumerator value of LSTDST field.                      */
42403   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_NOT_LAST (0x0UL) /*!< (unspecified)                                         */
42404   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDST_LAST (0x1UL) /*!< (unspecified)                                             */
42405 
42406 /* RSVDLSTDSTREG @Bits 2..7 : Reserved field - read-only */
42407   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_RSVDLSTDSTREG_Pos (2UL) /*!< Position of RSVDLSTDSTREG field.                      */
42408   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_RSVDLSTDSTREG_Msk (0x3FUL << I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_RSVDLSTDSTREG_Pos)
42409                                                                             /*!< Bit mask of RSVDLSTDSTREG field.*/
42410 
42411 /* LSTDSTWE @Bits 8..9 : Source Last Transaction Request write enable */
42412   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Pos (8UL) /*!< Position of LSTDSTWE field.                                */
42413   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Msk (0x3UL << I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Pos) /*!< Bit mask
42414                                                                             of LSTDSTWE field.*/
42415   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Min (0x0UL) /*!< Min enumerator value of LSTDSTWE field.                  */
42416   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_Max (0x1UL) /*!< Max enumerator value of LSTDSTWE field.                  */
42417   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_DISABLED (0x0UL) /*!< (unspecified)                                       */
42418   #define I3CCORE_DMA_SWHANDSHAKE_LSTDSTREG_LSTDSTWE_ENABLED (0x1UL) /*!< (unspecified)                                        */
42419 
42420 
42421 
42422 /* ================================================= Struct I3CCORE_DMA_MISC ================================================= */
42423 /**
42424   * @brief MISC [I3CCORE_DMA_MISC] (unspecified)
42425   */
42426 typedef struct {
42427   __IOM uint32_t  DMACFGREG;                         /*!< (@ 0x00000000) This register is used to enable the DW_ahb_dmac, which
42428                                                                          must be done before any channel activity can begin.*/
42429   __IM  uint32_t  RESERVED;
42430   __IOM uint32_t  CHENREG;                           /*!< (@ 0x00000008) This is the DW_ahb_dmac Channel Enable Register.      */
42431   __IM  uint32_t  RESERVED1;
42432   __IOM uint32_t  DMAIDREG;                          /*!< (@ 0x00000010) This is the DW_ahb_dmac ID register, which is a
42433                                                                          read-only register that reads back the
42434                                                                          coreConsultant-configured hardcoded ID number,
42435                                                                          DMAH_ID_NUM.*/
42436   __IM  uint32_t  RESERVED2;
42437   __IOM uint32_t  DMATESTREG;                        /*!< (@ 0x00000018) This register is used to put the AHB slave interface
42438                                                                          into test mode, during which the readback value of the
42439                                                                          writable registers match the value written, assuming
42440                                                                          the DW_ahb_dmac configuration has not optimized the
42441                                                                          same registers.*/
42442   __IM  uint32_t  RESERVED3;
42443   __IOM uint32_t  DMALPTIMEOUTREG;                   /*!< (@ 0x00000020) This register holds the timeout value of Low Power
42444                                                                          Counter.*/
42445   __IM  uint32_t  RESERVED4[4];
42446   __IOM uint32_t  DMACOMPPARAMS6L;                   /*!< (@ 0x00000034) DMA_COMP_PARAMS_6L is a constant read-only register
42447                                                                          that contains encoded information about the component
42448                                                                          parameter settings for Channel 7.*/
42449   __IOM uint32_t  DMACOMPPARAMS5L;                   /*!< (@ 0x00000038) DMA_COMP_PARAMS_5 is a constant read-only register that
42450                                                                          contains encoded information about the component
42451                                                                          parameter settings for Channel 5 and Channel 6.*/
42452   __IOM uint32_t  DMACOMPPARAMS5H;                   /*!< (@ 0x0000003C) DMA_COMP_PARAMS_5 is a constant read-only register that
42453                                                                          contains encoded information about the component
42454                                                                          parameter settings for Channel 5 and Channel 6.*/
42455   __IOM uint32_t  DMACOMPPARAMS4L;                   /*!< (@ 0x00000040) DMA_COMP_PARAMS_4 is a constant read-only register that
42456                                                                          contains encoded information about the component
42457                                                                          parameter settings for Channel 3 and Channel 4.*/
42458   __IOM uint32_t  DMACOMPPARAMS4H;                   /*!< (@ 0x00000044) DMA_COMP_PARAMS_4 is a constant read-only register that
42459                                                                          contains encoded information about the component
42460                                                                          parameter settings for Channel 3 and Channel 4.*/
42461   __IOM uint32_t  DMACOMPPARAMS3L;                   /*!< (@ 0x00000048) DMA_COMP_PARAMS_3 is a constant read-only register that
42462                                                                          contains encoded information about the component
42463                                                                          parameter settings for Channel 1 and Channel 2.*/
42464   __IOM uint32_t  DMACOMPPARAMS3H;                   /*!< (@ 0x0000004C) DMA_COMP_PARAMS_3 is a constant read-only register that
42465                                                                          contains encoded information about the component
42466                                                                          parameter settings for Channel 1 and Channel 2.*/
42467   __IOM uint32_t  DMACOMPPARAMS2L;                   /*!< (@ 0x00000050) DMA_COMP_PARAMS_2 is a constant read-only register that
42468                                                                          contains encoded information about the component
42469                                                                          parameter settings.*/
42470   __IOM uint32_t  DMACOMPPARAMS2H;                   /*!< (@ 0x00000054) DMA_COMP_PARAMS_2 is a constant read-only register that
42471                                                                          contains encoded information about the component
42472                                                                          parameter settings.*/
42473   __IOM uint32_t  DMACOMPPARAMS1L;                   /*!< (@ 0x00000058) DMA_COMP_PARAMS_1 is a constant read-only register that
42474                                                                          contains encoded information about the component
42475                                                                          parameter settings.*/
42476   __IOM uint32_t  DMACOMPPARAMS1H;                   /*!< (@ 0x0000005C) DMA_COMP_PARAMS_1 is a constant read-only register that
42477                                                                          contains encoded information about the component
42478                                                                          parameter settings.*/
42479   __IOM uint32_t  DMACOMPSID0;                       /*!< (@ 0x00000060) This is the DW_ahb_dmac Component Version register,
42480                                                                          which is a read-only register that specifies the
42481                                                                          component type.*/
42482   __IOM uint32_t  DMACOMPSID1;                       /*!< (@ 0x00000064) This is the DW_ahb_dmac Component Version register,
42483                                                                          which is a read-only register that specifies the
42484                                                                          version of the packaged component.*/
42485 } NRF_I3CCORE_DMA_MISC_Type;                         /*!< Size = 104 (0x068)                                                   */
42486 
42487 /* I3CCORE_DMA_MISC_DMACFGREG: This register is used to enable the DW_ahb_dmac, which must be done before any channel activity
42488                                 can begin. */
42489 
42490   #define I3CCORE_DMA_MISC_DMACFGREG_ResetValue (0x00000000UL) /*!< Reset value of DMACFGREG register.                         */
42491 
42492 /* DMAEN @Bit 0 : DW_ahb_dmac Enable bit. */
42493   #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Pos (0UL) /*!< Position of DMAEN field.                                             */
42494   #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Pos) /*!< Bit mask of DMAEN field.   */
42495   #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Min (0x0UL) /*!< Min enumerator value of DMAEN field.                               */
42496   #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_Max (0x1UL) /*!< Max enumerator value of DMAEN field.                               */
42497   #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_DISABLED (0x0UL) /*!< (unspecified)                                                 */
42498   #define I3CCORE_DMA_MISC_DMACFGREG_DMAEN_ENABLED (0x1UL) /*!< (unspecified)                                                  */
42499 
42500 
42501 /* I3CCORE_DMA_MISC_CHENREG: This is the DW_ahb_dmac Channel Enable Register. */
42502   #define I3CCORE_DMA_MISC_CHENREG_ResetValue (0x00000000UL) /*!< Reset value of CHENREG register.                             */
42503 
42504 /* CHEN @Bits 0..1 : Channel Enable. */
42505   #define I3CCORE_DMA_MISC_CHENREG_CHEN_Pos (0UL)    /*!< Position of CHEN field.                                              */
42506   #define I3CCORE_DMA_MISC_CHENREG_CHEN_Msk (0x3UL << I3CCORE_DMA_MISC_CHENREG_CHEN_Pos) /*!< Bit mask of CHEN field.          */
42507   #define I3CCORE_DMA_MISC_CHENREG_CHEN_Min (0x0UL)  /*!< Min enumerator value of CHEN field.                                  */
42508   #define I3CCORE_DMA_MISC_CHENREG_CHEN_Max (0x1UL)  /*!< Max enumerator value of CHEN field.                                  */
42509   #define I3CCORE_DMA_MISC_CHENREG_CHEN_DISABLED (0x0UL) /*!< (unspecified)                                                    */
42510   #define I3CCORE_DMA_MISC_CHENREG_CHEN_ENABLED (0x1UL) /*!< (unspecified)                                                     */
42511 
42512 /* RSVDCHENREG @Bits 2..7 : Reserved field - read-only */
42513   #define I3CCORE_DMA_MISC_CHENREG_RSVDCHENREG_Pos (2UL) /*!< Position of RSVDCHENREG field.                                   */
42514   #define I3CCORE_DMA_MISC_CHENREG_RSVDCHENREG_Msk (0x3FUL << I3CCORE_DMA_MISC_CHENREG_RSVDCHENREG_Pos) /*!< Bit mask of
42515                                                                             RSVDCHENREG field.*/
42516 
42517 /* CHENWE @Bits 8..9 : Channel enable register */
42518   #define I3CCORE_DMA_MISC_CHENREG_CHENWE_Pos (8UL)  /*!< Position of CHENWE field.                                            */
42519   #define I3CCORE_DMA_MISC_CHENREG_CHENWE_Msk (0x3UL << I3CCORE_DMA_MISC_CHENREG_CHENWE_Pos) /*!< Bit mask of CHENWE field.    */
42520 
42521 
42522 /* I3CCORE_DMA_MISC_DMAIDREG: This is the DW_ahb_dmac ID register, which is a read-only register that reads back the
42523                                coreConsultant-configured hardcoded ID number, DMAH_ID_NUM. */
42524 
42525   #define I3CCORE_DMA_MISC_DMAIDREG_ResetValue (0x00000000UL) /*!< Reset value of DMAIDREG register.                           */
42526 
42527 /* DMAID @Bits 0..31 : Hardcoded DW_ahb_dmac peripheral ID. */
42528   #define I3CCORE_DMA_MISC_DMAIDREG_DMAID_Pos (0UL)  /*!< Position of DMAID field.                                             */
42529   #define I3CCORE_DMA_MISC_DMAIDREG_DMAID_Msk (0xFFFFFFFFUL << I3CCORE_DMA_MISC_DMAIDREG_DMAID_Pos) /*!< Bit mask of DMAID
42530                                                                             field.*/
42531 
42532 
42533 /* I3CCORE_DMA_MISC_DMATESTREG: This register is used to put the AHB slave interface into test mode, during which the readback
42534                                  value of the writable registers match the value written, assuming the DW_ahb_dmac configuration
42535                                  has not optimized the same registers. */
42536 
42537   #define I3CCORE_DMA_MISC_DMATESTREG_ResetValue (0x00000000UL) /*!< Reset value of DMATESTREG register.                       */
42538 
42539 /* TESTSLVIF @Bit 0 : DMA Test register */
42540   #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Pos (0UL) /*!< Position of TESTSLVIF field.                                    */
42541   #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Msk (0x1UL << I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Pos) /*!< Bit mask of
42542                                                                             TESTSLVIF field.*/
42543   #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Min (0x0UL) /*!< Min enumerator value of TESTSLVIF field.                      */
42544   #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_Max (0x1UL) /*!< Max enumerator value of TESTSLVIF field.                      */
42545   #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_NORMAL_MODE (0x0UL) /*!< (unspecified)                                         */
42546   #define I3CCORE_DMA_MISC_DMATESTREG_TESTSLVIF_TEST_MODE (0x1UL) /*!< (unspecified)                                           */
42547 
42548 
42549 /* I3CCORE_DMA_MISC_DMALPTIMEOUTREG: This register holds the timeout value of Low Power Counter. */
42550   #define I3CCORE_DMA_MISC_DMALPTIMEOUTREG_ResetValue (0x00000008UL) /*!< Reset value of DMALPTIMEOUTREG register.             */
42551 
42552 /* DMALPTIMEOUT @Bits 0..3 : This field holds timeout value of low power counter register. */
42553   #define I3CCORE_DMA_MISC_DMALPTIMEOUTREG_DMALPTIMEOUT_Pos (0UL) /*!< Position of DMALPTIMEOUT field.                         */
42554   #define I3CCORE_DMA_MISC_DMALPTIMEOUTREG_DMALPTIMEOUT_Msk (0xFUL << I3CCORE_DMA_MISC_DMALPTIMEOUTREG_DMALPTIMEOUT_Pos) /*!<
42555                                                                             Bit mask of DMALPTIMEOUT field.*/
42556 
42557 
42558 /* I3CCORE_DMA_MISC_DMACOMPPARAMS6L: DMA_COMP_PARAMS_6L is a constant read-only register that contains encoded information about
42559                                       the component parameter settings for Channel 7. */
42560 
42561   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS6L register.             */
42562 
42563 /* CH7DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH7_DTW coreConsultant parameter. */
42564   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Pos (0UL) /*!< Position of CH7DTW field.                                     */
42565   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Pos) /*!< Bit mask of
42566                                                                             CH7DTW field.*/
42567   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Min (0x0UL) /*!< Min enumerator value of CH7DTW field.                       */
42568   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_Max (0x6UL) /*!< Max enumerator value of CH7DTW field.                       */
42569   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_NO_HARDCODE (0x0UL) /*!< (unspecified)                                       */
42570   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_8 (0x1UL) /*!< (unspecified)                                             */
42571   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_16 (0x2UL) /*!< (unspecified)                                            */
42572   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_32 (0x3UL) /*!< (unspecified)                                            */
42573   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_64 (0x4UL) /*!< (unspecified)                                            */
42574   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_128 (0x5UL) /*!< (unspecified)                                           */
42575   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DTW_DTW_256 (0x6UL) /*!< (unspecified)                                           */
42576 
42577 /* CH7STW @Bits 3..5 : The value of this register is derived from the DMAH_CH7_STW coreConsultant parameter. */
42578   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Pos (3UL) /*!< Position of CH7STW field.                                     */
42579   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Pos) /*!< Bit mask of
42580                                                                             CH7STW field.*/
42581   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Min (0x0UL) /*!< Min enumerator value of CH7STW field.                       */
42582   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_Max (0x6UL) /*!< Max enumerator value of CH7STW field.                       */
42583   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_NO_HARDCODE (0x0UL) /*!< (unspecified)                                       */
42584   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_8 (0x1UL) /*!< (unspecified)                                             */
42585   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_16 (0x2UL) /*!< (unspecified)                                            */
42586   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_32 (0x3UL) /*!< (unspecified)                                            */
42587   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_64 (0x4UL) /*!< (unspecified)                                            */
42588   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_128 (0x5UL) /*!< (unspecified)                                           */
42589   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STW_STW_256 (0x6UL) /*!< (unspecified)                                           */
42590 
42591 /* CH7STATDST @Bit 6 : The value of this register is derived from the DMAH_CH7_STAT_DST coreConsultant parameter. */
42592   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Pos (6UL) /*!< Position of CH7STATDST field.                             */
42593   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Pos) /*!< Bit
42594                                                                             mask of CH7STATDST field.*/
42595   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Min (0x0UL) /*!< Min enumerator value of CH7STATDST field.               */
42596   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_Max (0x1UL) /*!< Max enumerator value of CH7STATDST field.               */
42597   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_FALSE (0x0UL) /*!< (unspecified)                                         */
42598   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATDST_TRUE (0x1UL) /*!< (unspecified)                                          */
42599 
42600 /* CH7STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH7_STAT_SRC coreConsultant parameter. */
42601   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Pos (7UL) /*!< Position of CH7STATSRC field.                             */
42602   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Pos) /*!< Bit
42603                                                                             mask of CH7STATSRC field.*/
42604   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Min (0x0UL) /*!< Min enumerator value of CH7STATSRC field.               */
42605   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_Max (0x1UL) /*!< Max enumerator value of CH7STATSRC field.               */
42606   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_FALSE (0x0UL) /*!< (unspecified)                                         */
42607   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7STATSRC_TRUE (0x1UL) /*!< (unspecified)                                          */
42608 
42609 /* CH7DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH7_DST_SCA_EN coreConsultant parameter. */
42610   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Pos (8UL) /*!< Position of CH7DSTSCAEN field.                           */
42611   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Pos) /*!< Bit
42612                                                                             mask of CH7DSTSCAEN field.*/
42613   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH7DSTSCAEN field.             */
42614   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH7DSTSCAEN field.             */
42615   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_FALSE (0x0UL) /*!< (unspecified)                                        */
42616   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DSTSCAEN_TRUE (0x1UL) /*!< (unspecified)                                         */
42617 
42618 /* CH7SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH7_SRC_GAT_EN coreConsultant parameter. */
42619   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Pos (9UL) /*!< Position of CH7SRCGATEN field.                           */
42620   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Pos) /*!< Bit
42621                                                                             mask of CH7SRCGATEN field.*/
42622   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH7SRCGATEN field.             */
42623   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH7SRCGATEN field.             */
42624   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_FALSE (0x0UL) /*!< (unspecified)                                        */
42625   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SRCGATEN_TRUE (0x1UL) /*!< (unspecified)                                         */
42626 
42627 /* CH7LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH7_LOCK_EN coreConsultant parameter. */
42628   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Pos (10UL) /*!< Position of CH7LOCKEN field.                              */
42629   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Pos) /*!< Bit mask
42630                                                                             of CH7LOCKEN field.*/
42631   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH7LOCKEN field.                 */
42632   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH7LOCKEN field.                 */
42633   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_FALSE (0x0UL) /*!< (unspecified)                                          */
42634   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LOCKEN_TRUE (0x1UL) /*!< (unspecified)                                           */
42635 
42636 /* CH7MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH7_MULTI_BLK_EN coreConsultant parameter. */
42637   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Pos (11UL) /*!< Position of CH7MULTIBLKEN field.                      */
42638   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Pos) /*!<
42639                                                                             Bit mask of CH7MULTIBLKEN field.*/
42640   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH7MULTIBLKEN field.         */
42641   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH7MULTIBLKEN field.         */
42642   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified)                                      */
42643   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified)                                       */
42644 
42645 /* CH7CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH7_CTL_WB_EN coreConsultant parameter. */
42646   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Pos (12UL) /*!< Position of CH7CTLWBEN field.                            */
42647   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Pos) /*!< Bit
42648                                                                             mask of CH7CTLWBEN field.*/
42649   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH7CTLWBEN field.               */
42650   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH7CTLWBEN field.               */
42651   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_FALSE (0x0UL) /*!< (unspecified)                                         */
42652   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7CTLWBEN_TRUE (0x1UL) /*!< (unspecified)                                          */
42653 
42654 /* CH7HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH7_HC_LLP coreConsultant parameter. */
42655   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Pos (13UL) /*!< Position of CH7HCLLP field.                                */
42656   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Pos) /*!< Bit mask
42657                                                                             of CH7HCLLP field.*/
42658   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Min (0x0UL) /*!< Min enumerator value of CH7HCLLP field.                   */
42659   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_Max (0x1UL) /*!< Max enumerator value of CH7HCLLP field.                   */
42660   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified)                                    */
42661   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7HCLLP_HARDCODED (0x1UL) /*!< (unspecified)                                       */
42662 
42663 /* CH7FC @Bits 14..15 : The value of this register is derived from the DMAH_CH7_FC coreConsultant parameter. */
42664   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Pos (14UL) /*!< Position of CH7FC field.                                      */
42665   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Pos) /*!< Bit mask of
42666                                                                             CH7FC field.*/
42667   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Min (0x0UL) /*!< Min enumerator value of CH7FC field.                         */
42668   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_Max (0x3UL) /*!< Max enumerator value of CH7FC field.                         */
42669   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_FC_DMA (0x0UL) /*!< (unspecified)                                             */
42670   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_FC_SRC (0x1UL) /*!< (unspecified)                                             */
42671   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_FC_DST (0x2UL) /*!< (unspecified)                                             */
42672   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FC_FC_ANY (0x3UL) /*!< (unspecified)                                             */
42673 
42674 /* CH7MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH7_MULT_SIZE coreConsultant parameter. */
42675   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Pos (16UL) /*!< Position of CH7MAXMULTSIZE field.                    */
42676   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Pos)
42677                                                                             /*!< Bit mask of CH7MAXMULTSIZE field.*/
42678   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH7MAXMULTSIZE field.       */
42679   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH7MAXMULTSIZE field.       */
42680   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified)                           */
42681   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified)                           */
42682   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified)                          */
42683   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified)                          */
42684   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified)                          */
42685   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified)                         */
42686   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified)                         */
42687 
42688 /* CH7DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH7_DMS coreConsultant parameter. */
42689   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Pos (19UL) /*!< Position of CH7DMS field.                                    */
42690   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Pos) /*!< Bit mask of
42691                                                                             CH7DMS field.*/
42692   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Min (0x0UL) /*!< Min enumerator value of CH7DMS field.                       */
42693   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_Max (0x4UL) /*!< Max enumerator value of CH7DMS field.                       */
42694   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
42695   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
42696   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
42697   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
42698   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
42699 
42700 /* CH7LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH7_LMS coreConsultant parameter. */
42701   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Pos (22UL) /*!< Position of CH7LMS field.                                    */
42702   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Pos) /*!< Bit mask of
42703                                                                             CH7LMS field.*/
42704   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Min (0x0UL) /*!< Min enumerator value of CH7LMS field.                       */
42705   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_Max (0x4UL) /*!< Max enumerator value of CH7LMS field.                       */
42706   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
42707   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
42708   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
42709   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
42710   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
42711 
42712 /* CH7SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH7_SMS coreConsultant parameter. */
42713   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Pos (25UL) /*!< Position of CH7SMS field.                                    */
42714   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Pos) /*!< Bit mask of
42715                                                                             CH7SMS field.*/
42716   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Min (0x0UL) /*!< Min enumerator value of CH7SMS field.                       */
42717   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_Max (0x4UL) /*!< Max enumerator value of CH7SMS field.                       */
42718   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
42719   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
42720   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
42721   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
42722   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
42723 
42724 /* CH7FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH7_FIFO_DEPTH coreConsultant parameter. */
42725   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Pos (28UL) /*!< Position of CH7FIFODEPTH field.                        */
42726   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Pos) /*!<
42727                                                                             Bit mask of CH7FIFODEPTH field.*/
42728   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH7FIFODEPTH field.           */
42729   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH7FIFODEPTH field.           */
42730   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified)                                */
42731   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified)                               */
42732   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified)                               */
42733   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified)                               */
42734   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified)                              */
42735   #define I3CCORE_DMA_MISC_DMACOMPPARAMS6L_CH7FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified)                              */
42736 
42737 
42738 /* I3CCORE_DMA_MISC_DMACOMPPARAMS5L: DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about
42739                                       the component parameter settings for Channel 5 and Channel 6. */
42740 
42741   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS5L register.             */
42742 
42743 /* CH6DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH6_DTW coreConsultant parameter. */
42744   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Pos (0UL) /*!< Position of CH6DTW field.                                     */
42745   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Pos) /*!< Bit mask of
42746                                                                             CH6DTW field.*/
42747   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Min (0x0UL) /*!< Min enumerator value of CH6DTW field.                       */
42748   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_Max (0x6UL) /*!< Max enumerator value of CH6DTW field.                       */
42749   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
42750   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
42751   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
42752   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
42753   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
42754   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
42755   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
42756 
42757 /* CH6STW @Bits 3..5 : The value of this register is derived from the DMAH_CH6_STW coreConsultant parameter. */
42758   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Pos (3UL) /*!< Position of CH6STW field.                                     */
42759   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Pos) /*!< Bit mask of
42760                                                                             CH6STW field.*/
42761   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Min (0x0UL) /*!< Min enumerator value of CH6STW field.                       */
42762   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_Max (0x6UL) /*!< Max enumerator value of CH6STW field.                       */
42763   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
42764   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
42765   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
42766   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
42767   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
42768   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
42769   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
42770 
42771 /* CH6STATDST @Bit 6 : The value of this register is derived from the DMAH_CH6_STAT_DST coreConsultant parameter. */
42772   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Pos (6UL) /*!< Position of CH6STATDST field.                             */
42773   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Pos) /*!< Bit
42774                                                                             mask of CH6STATDST field.*/
42775   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Min (0x0UL) /*!< Min enumerator value of CH6STATDST field.               */
42776   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_Max (0x1UL) /*!< Max enumerator value of CH6STATDST field.               */
42777   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_FALSE (0x0UL) /*!< (unspecified)                                         */
42778   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATDST_TRUE (0x1UL) /*!< (unspecified)                                          */
42779 
42780 /* CH6STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH6_STAT_SRC coreConsultant parameter. */
42781   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Pos (7UL) /*!< Position of CH6STATSRC field.                             */
42782   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Pos) /*!< Bit
42783                                                                             mask of CH6STATSRC field.*/
42784   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Min (0x0UL) /*!< Min enumerator value of CH6STATSRC field.               */
42785   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_Max (0x1UL) /*!< Max enumerator value of CH6STATSRC field.               */
42786   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_FALSE (0x0UL) /*!< (unspecified)                                         */
42787   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6STATSRC_TRUE (0x1UL) /*!< (unspecified)                                          */
42788 
42789 /* CH6DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH6_DST_SCA_EN coreConsultant parameter. */
42790   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Pos (8UL) /*!< Position of CH6DSTSCAEN field.                           */
42791   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Pos) /*!< Bit
42792                                                                             mask of CH6DSTSCAEN field.*/
42793   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH6DSTSCAEN field.             */
42794   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH6DSTSCAEN field.             */
42795   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_FALSE (0x0UL) /*!< (unspecified)                                        */
42796   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DSTSCAEN_TRUE (0x1UL) /*!< (unspecified)                                         */
42797 
42798 /* CH6SRCGATEN @Bit 9 : The value of this register is derived from the CH6_SRC_GAT_EN coreConsultant parameter. */
42799   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Pos (9UL) /*!< Position of CH6SRCGATEN field.                           */
42800   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Pos) /*!< Bit
42801                                                                             mask of CH6SRCGATEN field.*/
42802   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH6SRCGATEN field.             */
42803   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH6SRCGATEN field.             */
42804   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_FALSE (0x0UL) /*!< (unspecified)                                        */
42805   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SRCGATEN_TRUE (0x1UL) /*!< (unspecified)                                         */
42806 
42807 /* CH6LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH6_LOCK_EN coreConsultant parameter. */
42808   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Pos (10UL) /*!< Position of CH6LOCKEN field.                              */
42809   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Pos) /*!< Bit mask
42810                                                                             of CH6LOCKEN field.*/
42811   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH6LOCKEN field.                 */
42812   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH6LOCKEN field.                 */
42813   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_FALSE (0x0UL) /*!< (unspecified)                                          */
42814   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LOCKEN_TRUE (0x1UL) /*!< (unspecified)                                           */
42815 
42816 /* CH6MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH6_MULTI_BLK_EN coreConsultant parameter. */
42817   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Pos (11UL) /*!< Position of CH6MULTIBLKEN field.                      */
42818   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Pos) /*!<
42819                                                                             Bit mask of CH6MULTIBLKEN field.*/
42820   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH6MULTIBLKEN field.         */
42821   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH6MULTIBLKEN field.         */
42822   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified)                                      */
42823   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified)                                       */
42824 
42825 /* CH6CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH6_CTL_WB_EN coreConsultant parameter. */
42826   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Pos (12UL) /*!< Position of CH6CTLWBEN field.                            */
42827   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Pos) /*!< Bit
42828                                                                             mask of CH6CTLWBEN field.*/
42829   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH6CTLWBEN field.               */
42830   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH6CTLWBEN field.               */
42831   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_FALSE (0x0UL) /*!< (unspecified)                                         */
42832   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6CTLWBEN_TRUE (0x1UL) /*!< (unspecified)                                          */
42833 
42834 /* CH6HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH6_HC_LLP coreConsultant parameter. */
42835   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Pos (13UL) /*!< Position of CH6HCLLP field.                                */
42836   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Pos) /*!< Bit mask
42837                                                                             of CH6HCLLP field.*/
42838   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Min (0x0UL) /*!< Min enumerator value of CH6HCLLP field.                   */
42839   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_Max (0x1UL) /*!< Max enumerator value of CH6HCLLP field.                   */
42840   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified)                                    */
42841   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6HCLLP_HARDCODED (0x1UL) /*!< (unspecified)                                       */
42842 
42843 /* CH6FC @Bits 14..15 : The value of this register is derived from the DMAH_CH6_FC coreConsultant parameter. */
42844   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Pos (14UL) /*!< Position of CH6FC field.                                      */
42845   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Pos) /*!< Bit mask of
42846                                                                             CH6FC field.*/
42847   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Min (0x0UL) /*!< Min enumerator value of CH6FC field.                         */
42848   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_Max (0x3UL) /*!< Max enumerator value of CH6FC field.                         */
42849   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_FC_DMA (0x0UL) /*!< (unspecified)                                             */
42850   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_FC_SRC (0x1UL) /*!< (unspecified)                                             */
42851   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_FC_DST (0x2UL) /*!< (unspecified)                                             */
42852   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FC_FC_ANY (0x3UL) /*!< (unspecified)                                             */
42853 
42854 /* CH6MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH6_MULT_SIZE coreConsultant parameter. */
42855   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Pos (16UL) /*!< Position of CH6MAXMULTSIZE field.                    */
42856   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Pos)
42857                                                                             /*!< Bit mask of CH6MAXMULTSIZE field.*/
42858   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH6MAXMULTSIZE field.       */
42859   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH6MAXMULTSIZE field.       */
42860   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified)                           */
42861   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified)                           */
42862   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified)                          */
42863   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified)                          */
42864   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified)                          */
42865   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified)                         */
42866   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified)                         */
42867 
42868 /* CH6DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH6_DMS coreConsultant parameter. */
42869   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Pos (19UL) /*!< Position of CH6DMS field.                                    */
42870   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Pos) /*!< Bit mask of
42871                                                                             CH6DMS field.*/
42872   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Min (0x0UL) /*!< Min enumerator value of CH6DMS field.                       */
42873   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_Max (0x4UL) /*!< Max enumerator value of CH6DMS field.                       */
42874   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
42875   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
42876   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
42877   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
42878   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
42879 
42880 /* CH6LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH6_LMS coreConsultant parameter. */
42881   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Pos (22UL) /*!< Position of CH6LMS field.                                    */
42882   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Pos) /*!< Bit mask of
42883                                                                             CH6LMS field.*/
42884   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Min (0x0UL) /*!< Min enumerator value of CH6LMS field.                       */
42885   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_Max (0x4UL) /*!< Max enumerator value of CH6LMS field.                       */
42886   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
42887   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
42888   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
42889   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
42890   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
42891 
42892 /* CH6SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH6_SMS coreConsultant parameter. */
42893   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Pos (25UL) /*!< Position of CH6SMS field.                                    */
42894   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Pos) /*!< Bit mask of
42895                                                                             CH6SMS field.*/
42896   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Min (0x0UL) /*!< Min enumerator value of CH6SMS field.                       */
42897   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_Max (0x4UL) /*!< Max enumerator value of CH6SMS field.                       */
42898   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
42899   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
42900   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
42901   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
42902   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
42903 
42904 /* CH6FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH6_FIFO_DEPTH coreConsultant parameter. */
42905   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Pos (28UL) /*!< Position of CH6FIFODEPTH field.                        */
42906   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Pos) /*!<
42907                                                                             Bit mask of CH6FIFODEPTH field.*/
42908   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH6FIFODEPTH field.           */
42909   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH6FIFODEPTH field.           */
42910   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_IFO_DEPTH_8 (0x0UL) /*!< (unspecified)                                 */
42911   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified)                               */
42912   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified)                               */
42913   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified)                               */
42914   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified)                              */
42915   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5L_CH6FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified)                              */
42916 
42917 
42918 /* I3CCORE_DMA_MISC_DMACOMPPARAMS5H: DMA_COMP_PARAMS_5 is a constant read-only register that contains encoded information about
42919                                       the component parameter settings for Channel 5 and Channel 6. */
42920 
42921   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS5H register.             */
42922 
42923 /* CH5DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH5_DTW coreConsultant parameter. */
42924   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Pos (0UL) /*!< Position of CH5DTW field.                                     */
42925   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Pos) /*!< Bit mask of
42926                                                                             CH5DTW field.*/
42927   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Min (0x0UL) /*!< Min enumerator value of CH5DTW field.                       */
42928   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_Max (0x6UL) /*!< Max enumerator value of CH5DTW field.                       */
42929   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
42930   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
42931   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
42932   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
42933   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
42934   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
42935   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
42936 
42937 /* CH5STW @Bits 3..5 : The value of this register is derived from the DMAH_CH5_STW coreConsultant parameter. */
42938   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Pos (3UL) /*!< Position of CH5STW field.                                     */
42939   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Pos) /*!< Bit mask of
42940                                                                             CH5STW field.*/
42941   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Min (0x0UL) /*!< Min enumerator value of CH5STW field.                       */
42942   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_Max (0x6UL) /*!< Max enumerator value of CH5STW field.                       */
42943   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
42944   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
42945   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
42946   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
42947   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
42948   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
42949   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
42950 
42951 /* CH5STATDST @Bit 6 : The value of this register is derived from the DMAH_CH5_STAT_DST coreConsultant parameter. */
42952   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Pos (6UL) /*!< Position of CH5STATDST field.                             */
42953   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Pos) /*!< Bit
42954                                                                             mask of CH5STATDST field.*/
42955   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Min (0x0UL) /*!< Min enumerator value of CH5STATDST field.               */
42956   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_Max (0x1UL) /*!< Max enumerator value of CH5STATDST field.               */
42957   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_FALSE (0x0UL) /*!< (unspecified)                                         */
42958   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATDST_TRUE (0x1UL) /*!< (unspecified)                                          */
42959 
42960 /* CH5STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH5_STAT_SRC coreConsultant parameter. */
42961   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Pos (7UL) /*!< Position of CH5STATSRC field.                             */
42962   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Pos) /*!< Bit
42963                                                                             mask of CH5STATSRC field.*/
42964   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Min (0x0UL) /*!< Min enumerator value of CH5STATSRC field.               */
42965   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_Max (0x1UL) /*!< Max enumerator value of CH5STATSRC field.               */
42966   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_FALSE (0x0UL) /*!< (unspecified)                                         */
42967   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5STATSRC_TRUE (0x1UL) /*!< (unspecified)                                          */
42968 
42969 /* CH5DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH5_DST_SCA_EN coreConsultant parameter. */
42970   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Pos (8UL) /*!< Position of CH5DSTSCAEN field.                           */
42971   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Pos) /*!< Bit
42972                                                                             mask of CH5DSTSCAEN field.*/
42973   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH5DSTSCAEN field.             */
42974   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH5DSTSCAEN field.             */
42975   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_FALSE (0x0UL) /*!< (unspecified)                                        */
42976   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DSTSCAEN_TRUE (0x1UL) /*!< (unspecified)                                         */
42977 
42978 /* CH5SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH5_SRC_GAT_EN coreConsultant parameter. */
42979   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Pos (9UL) /*!< Position of CH5SRCGATEN field.                           */
42980   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Pos) /*!< Bit
42981                                                                             mask of CH5SRCGATEN field.*/
42982   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH5SRCGATEN field.             */
42983   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH5SRCGATEN field.             */
42984   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_FALSE (0x0UL) /*!< (unspecified)                                        */
42985   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SRCGATEN_TRUE (0x1UL) /*!< (unspecified)                                         */
42986 
42987 /* CH5LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH5_LOCK_EN coreConsultant parameter. */
42988   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Pos (10UL) /*!< Position of CH5LOCKEN field.                              */
42989   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Pos) /*!< Bit mask
42990                                                                             of CH5LOCKEN field.*/
42991   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH5LOCKEN field.                 */
42992   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH5LOCKEN field.                 */
42993   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_FALSE (0x0UL) /*!< (unspecified)                                          */
42994   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LOCKEN_TRUE (0x1UL) /*!< (unspecified)                                           */
42995 
42996 /* CH5MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH5_MULTI_BLK_EN coreConsultant parameter. */
42997   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Pos (11UL) /*!< Position of CH5MULTIBLKEN field.                      */
42998   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Pos) /*!<
42999                                                                             Bit mask of CH5MULTIBLKEN field.*/
43000   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH5MULTIBLKEN field.         */
43001   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH5MULTIBLKEN field.         */
43002   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified)                                      */
43003   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified)                                       */
43004 
43005 /* CH5CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH5_CTL_WB_EN coreConsultant parameter. */
43006   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Pos (12UL) /*!< Position of CH5CTLWBEN field.                            */
43007   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Pos) /*!< Bit
43008                                                                             mask of CH5CTLWBEN field.*/
43009   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH5CTLWBEN field.               */
43010   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH5CTLWBEN field.               */
43011   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_FALSE (0x0UL) /*!< (unspecified)                                         */
43012   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5CTLWBEN_TRUE (0x1UL) /*!< (unspecified)                                          */
43013 
43014 /* CH5HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH5_HC_LLP coreConsultant parameter. */
43015   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Pos (13UL) /*!< Position of CH5HCLLP field.                                */
43016   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Pos) /*!< Bit mask
43017                                                                             of CH5HCLLP field.*/
43018   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Min (0x0UL) /*!< Min enumerator value of CH5HCLLP field.                   */
43019   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_Max (0x1UL) /*!< Max enumerator value of CH5HCLLP field.                   */
43020   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified)                                    */
43021   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5HCLLP_HARDCODED (0x1UL) /*!< (unspecified)                                       */
43022 
43023 /* CH5FC @Bits 14..15 : The value of this register is derived from the DMAH_CH5_FC coreConsultant parameter. */
43024   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Pos (14UL) /*!< Position of CH5FC field.                                      */
43025   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Pos) /*!< Bit mask of
43026                                                                             CH5FC field.*/
43027   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Min (0x0UL) /*!< Min enumerator value of CH5FC field.                         */
43028   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_Max (0x3UL) /*!< Max enumerator value of CH5FC field.                         */
43029   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_FC_DMA (0x0UL) /*!< (unspecified)                                             */
43030   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_FC_SRC (0x1UL) /*!< (unspecified)                                             */
43031   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_FC_DST (0x2UL) /*!< (unspecified)                                             */
43032   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FC_FC_ANY (0x3UL) /*!< (unspecified)                                             */
43033 
43034 /* CH5MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH5_MULT_SIZE coreConsultant parameter. */
43035   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Pos (16UL) /*!< Position of CH5MAXMULTSIZE field.                    */
43036   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Pos)
43037                                                                             /*!< Bit mask of CH5MAXMULTSIZE field.*/
43038   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH5MAXMULTSIZE field.       */
43039   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH5MAXMULTSIZE field.       */
43040   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified)                           */
43041   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified)                           */
43042   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified)                          */
43043   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified)                          */
43044   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified)                          */
43045   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified)                         */
43046   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified)                         */
43047 
43048 /* CH5DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH5_DMS coreConsultant parameter. */
43049   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Pos (19UL) /*!< Position of CH5DMS field.                                    */
43050   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Pos) /*!< Bit mask of
43051                                                                             CH5DMS field.*/
43052   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Min (0x0UL) /*!< Min enumerator value of CH5DMS field.                       */
43053   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_Max (0x4UL) /*!< Max enumerator value of CH5DMS field.                       */
43054   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43055   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43056   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43057   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43058   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43059 
43060 /* CH5LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH5_LMS coreConsultant parameter. */
43061   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Pos (22UL) /*!< Position of CH5LMS field.                                    */
43062   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Pos) /*!< Bit mask of
43063                                                                             CH5LMS field.*/
43064   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Min (0x0UL) /*!< Min enumerator value of CH5LMS field.                       */
43065   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_Max (0x4UL) /*!< Max enumerator value of CH5LMS field.                       */
43066   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43067   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43068   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43069   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43070   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43071 
43072 /* CH5SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH5_SMS coreConsultant parameter. */
43073   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Pos (25UL) /*!< Position of CH5SMS field.                                    */
43074   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Pos) /*!< Bit mask of
43075                                                                             CH5SMS field.*/
43076   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Min (0x0UL) /*!< Min enumerator value of CH5SMS field.                       */
43077   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_Max (0x4UL) /*!< Max enumerator value of CH5SMS field.                       */
43078   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43079   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43080   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43081   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43082   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43083 
43084 /* CH5FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH5_FIFO_DEPTH coreConsultant parameter. */
43085   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Pos (28UL) /*!< Position of CH5FIFODEPTH field.                        */
43086   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Pos) /*!<
43087                                                                             Bit mask of CH5FIFODEPTH field.*/
43088   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH5FIFODEPTH field.           */
43089   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH5FIFODEPTH field.           */
43090   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified)                                */
43091   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified)                               */
43092   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified)                               */
43093   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified)                               */
43094   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified)                              */
43095   #define I3CCORE_DMA_MISC_DMACOMPPARAMS5H_CH5FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified)                              */
43096 
43097 
43098 /* I3CCORE_DMA_MISC_DMACOMPPARAMS4L: DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about
43099                                       the component parameter settings for Channel 3 and Channel 4. */
43100 
43101   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS4L register.             */
43102 
43103 /* CH4DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH4_DTW coreConsultant parameter. */
43104   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Pos (0UL) /*!< Position of CH4DTW field.                                     */
43105   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Pos) /*!< Bit mask of
43106                                                                             CH4DTW field.*/
43107   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Min (0x0UL) /*!< Min enumerator value of CH4DTW field.                       */
43108   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_Max (0x6UL) /*!< Max enumerator value of CH4DTW field.                       */
43109   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43110   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43111   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43112   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43113   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43114   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43115   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43116 
43117 /* CH4STW @Bits 3..5 : The value of this register is derived from the DMAH_CH4_STW coreConsultant parameter. */
43118   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Pos (3UL) /*!< Position of CH4STW field.                                     */
43119   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Pos) /*!< Bit mask of
43120                                                                             CH4STW field.*/
43121   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Min (0x0UL) /*!< Min enumerator value of CH4STW field.                       */
43122   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_Max (0x6UL) /*!< Max enumerator value of CH4STW field.                       */
43123   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43124   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43125   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43126   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43127   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43128   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43129   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43130 
43131 /* CH4STATDST @Bit 6 : The value of this register is derived from the DMAH_CH4_STAT_DST coreConsultant parameter. */
43132   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Pos (6UL) /*!< Position of CH4STATDST field.                             */
43133   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Pos) /*!< Bit
43134                                                                             mask of CH4STATDST field.*/
43135   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Min (0x0UL) /*!< Min enumerator value of CH4STATDST field.               */
43136   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_Max (0x1UL) /*!< Max enumerator value of CH4STATDST field.               */
43137   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_FALSE (0x0UL) /*!< (unspecified)                                         */
43138   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATDST_TRUE (0x1UL) /*!< (unspecified)                                          */
43139 
43140 /* CH4STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH4_STAT_SRC coreConsultant parameter. */
43141   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Pos (7UL) /*!< Position of CH4STATSRC field.                             */
43142   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Pos) /*!< Bit
43143                                                                             mask of CH4STATSRC field.*/
43144   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Min (0x0UL) /*!< Min enumerator value of CH4STATSRC field.               */
43145   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_Max (0x1UL) /*!< Max enumerator value of CH4STATSRC field.               */
43146   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_FALSE (0x0UL) /*!< (unspecified)                                         */
43147   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4STATSRC_TRUE (0x1UL) /*!< (unspecified)                                          */
43148 
43149 /* CH4DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH4_DST_SCA_EN coreConsultant parameter. */
43150   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Pos (8UL) /*!< Position of CH4DSTSCAEN field.                           */
43151   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Pos) /*!< Bit
43152                                                                             mask of CH4DSTSCAEN field.*/
43153   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH4DSTSCAEN field.             */
43154   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH4DSTSCAEN field.             */
43155   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43156   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DSTSCAEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43157 
43158 /* CH4SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH4_SRC_GAT_EN coreConsultant parameter. */
43159   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Pos (9UL) /*!< Position of CH4SRCGATEN field.                           */
43160   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Pos) /*!< Bit
43161                                                                             mask of CH4SRCGATEN field.*/
43162   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH4SRCGATEN field.             */
43163   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH4SRCGATEN field.             */
43164   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43165   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SRCGATEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43166 
43167 /* CH4LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH4_LOCK_EN coreConsultant parameter. */
43168   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Pos (10UL) /*!< Position of CH4LOCKEN field.                              */
43169   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Pos) /*!< Bit mask
43170                                                                             of CH4LOCKEN field.*/
43171   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH4LOCKEN field.                 */
43172   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH4LOCKEN field.                 */
43173   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_FALSE (0x0UL) /*!< (unspecified)                                          */
43174   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LOCKEN_TRUE (0x1UL) /*!< (unspecified)                                           */
43175 
43176 /* CH4MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH4_MULTI_BLK_EN coreConsultant parameter. */
43177   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Pos (11UL) /*!< Position of CH4MULTIBLKEN field.                      */
43178   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Pos) /*!<
43179                                                                             Bit mask of CH4MULTIBLKEN field.*/
43180   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH4MULTIBLKEN field.         */
43181   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH4MULTIBLKEN field.         */
43182   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified)                                      */
43183   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified)                                       */
43184 
43185 /* CH4CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH4_CTL_WB_EN coreConsultant parameter. */
43186   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Pos (12UL) /*!< Position of CH4CTLWBEN field.                            */
43187   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Pos) /*!< Bit
43188                                                                             mask of CH4CTLWBEN field.*/
43189   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH4CTLWBEN field.               */
43190   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH4CTLWBEN field.               */
43191   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_FALSE (0x0UL) /*!< (unspecified)                                         */
43192   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4CTLWBEN_TRUE (0x1UL) /*!< (unspecified)                                          */
43193 
43194 /* CH4HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH4_HC_LLP coreConsultant parameter. */
43195   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Pos (13UL) /*!< Position of CH4HCLLP field.                                */
43196   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Pos) /*!< Bit mask
43197                                                                             of CH4HCLLP field.*/
43198   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Min (0x0UL) /*!< Min enumerator value of CH4HCLLP field.                   */
43199   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_Max (0x1UL) /*!< Max enumerator value of CH4HCLLP field.                   */
43200   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified)                                    */
43201   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4HCLLP_HARDCODED (0x1UL) /*!< (unspecified)                                       */
43202 
43203 /* CH4FC @Bits 14..15 : The value of this register is derived from the DMAH_CH4_FC coreConsultant parameter. */
43204   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Pos (14UL) /*!< Position of CH4FC field.                                      */
43205   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Pos) /*!< Bit mask of
43206                                                                             CH4FC field.*/
43207   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Min (0x0UL) /*!< Min enumerator value of CH4FC field.                         */
43208   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_Max (0x3UL) /*!< Max enumerator value of CH4FC field.                         */
43209   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_FC_DMA (0x0UL) /*!< (unspecified)                                             */
43210   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_FC_SRC (0x1UL) /*!< (unspecified)                                             */
43211   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_FC_DST (0x2UL) /*!< (unspecified)                                             */
43212   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FC_FC_ANY (0x3UL) /*!< (unspecified)                                             */
43213 
43214 /* CH4MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH4_MULT_SIZE coreConsultant parameter. */
43215   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Pos (16UL) /*!< Position of CH4MAXMULTSIZE field.                    */
43216   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Pos)
43217                                                                             /*!< Bit mask of CH4MAXMULTSIZE field.*/
43218   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH4MAXMULTSIZE field.       */
43219   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH4MAXMULTSIZE field.       */
43220   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified)                           */
43221   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified)                           */
43222   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified)                          */
43223   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified)                          */
43224   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified)                          */
43225   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified)                         */
43226   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified)                         */
43227 
43228 /* CH4DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH4_DMS coreConsultant parameter. */
43229   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Pos (19UL) /*!< Position of CH4DMS field.                                    */
43230   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Pos) /*!< Bit mask of
43231                                                                             CH4DMS field.*/
43232   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Min (0x0UL) /*!< Min enumerator value of CH4DMS field.                       */
43233   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_Max (0x4UL) /*!< Max enumerator value of CH4DMS field.                       */
43234   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43235   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43236   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43237   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43238   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43239 
43240 /* CH4LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH4_LMS coreConsultant parameter. */
43241   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Pos (22UL) /*!< Position of CH4LMS field.                                    */
43242   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Pos) /*!< Bit mask of
43243                                                                             CH4LMS field.*/
43244   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Min (0x0UL) /*!< Min enumerator value of CH4LMS field.                       */
43245   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_Max (0x4UL) /*!< Max enumerator value of CH4LMS field.                       */
43246   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43247   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43248   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43249   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43250   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43251 
43252 /* CH4SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH4_SMS coreConsultant parameter. */
43253   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Pos (25UL) /*!< Position of CH4SMS field.                                    */
43254   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Pos) /*!< Bit mask of
43255                                                                             CH4SMS field.*/
43256   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Min (0x0UL) /*!< Min enumerator value of CH4SMS field.                       */
43257   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_Max (0x4UL) /*!< Max enumerator value of CH4SMS field.                       */
43258   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43259   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43260   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43261   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43262   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43263 
43264 /* CH4FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH4_FIFO_DEPTH coreConsultant parameter. */
43265   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Pos (28UL) /*!< Position of CH4FIFODEPTH field.                        */
43266   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Pos) /*!<
43267                                                                             Bit mask of CH4FIFODEPTH field.*/
43268   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH4FIFODEPTH field.           */
43269   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH4FIFODEPTH field.           */
43270   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified)                                */
43271   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified)                               */
43272   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified)                               */
43273   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified)                               */
43274   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified)                              */
43275   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4L_CH4FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified)                              */
43276 
43277 
43278 /* I3CCORE_DMA_MISC_DMACOMPPARAMS4H: DMA_COMP_PARAMS_4 is a constant read-only register that contains encoded information about
43279                                       the component parameter settings for Channel 3 and Channel 4. */
43280 
43281   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS4H register.             */
43282 
43283 /* CH3DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH3_DTW coreConsultant parameter. */
43284   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Pos (0UL) /*!< Position of CH3DTW field.                                     */
43285   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Pos) /*!< Bit mask of
43286                                                                             CH3DTW field.*/
43287   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Min (0x0UL) /*!< Min enumerator value of CH3DTW field.                       */
43288   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_Max (0x6UL) /*!< Max enumerator value of CH3DTW field.                       */
43289   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43290   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43291   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43292   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43293   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43294   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43295   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43296 
43297 /* CH3STW @Bits 3..5 : The value of this register is derived from the DMAH_CH3_STW coreConsultant parameter. */
43298   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Pos (3UL) /*!< Position of CH3STW field.                                     */
43299   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Pos) /*!< Bit mask of
43300                                                                             CH3STW field.*/
43301   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Min (0x0UL) /*!< Min enumerator value of CH3STW field.                       */
43302   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_Max (0x6UL) /*!< Max enumerator value of CH3STW field.                       */
43303   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43304   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43305   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43306   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43307   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43308   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43309   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43310 
43311 /* CH3STATDST @Bit 6 : The value of this register is derived from the DMAH_CH3_STAT_DST coreConsultant parameter. */
43312   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Pos (6UL) /*!< Position of CH3STATDST field.                             */
43313   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Pos) /*!< Bit
43314                                                                             mask of CH3STATDST field.*/
43315   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Min (0x0UL) /*!< Min enumerator value of CH3STATDST field.               */
43316   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_Max (0x1UL) /*!< Max enumerator value of CH3STATDST field.               */
43317   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_FALSE (0x0UL) /*!< (unspecified)                                         */
43318   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATDST_TRUE (0x1UL) /*!< (unspecified)                                          */
43319 
43320 /* CH3STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH3_STAT_SRC coreConsultant parameter. */
43321   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Pos (7UL) /*!< Position of CH3STATSRC field.                             */
43322   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Pos) /*!< Bit
43323                                                                             mask of CH3STATSRC field.*/
43324   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Min (0x0UL) /*!< Min enumerator value of CH3STATSRC field.               */
43325   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_Max (0x1UL) /*!< Max enumerator value of CH3STATSRC field.               */
43326   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_FALSE (0x0UL) /*!< (unspecified)                                         */
43327   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3STATSRC_TRUE (0x1UL) /*!< (unspecified)                                          */
43328 
43329 /* CH3DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH3_DST_SCA_EN coreConsultant parameter. */
43330   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Pos (8UL) /*!< Position of CH3DSTSCAEN field.                           */
43331   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Pos) /*!< Bit
43332                                                                             mask of CH3DSTSCAEN field.*/
43333   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH3DSTSCAEN field.             */
43334   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH3DSTSCAEN field.             */
43335   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43336   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DSTSCAEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43337 
43338 /* CH3SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH3_SRC_GAT_EN coreConsultant parameter. */
43339   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Pos (9UL) /*!< Position of CH3SRCGATEN field.                           */
43340   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Pos) /*!< Bit
43341                                                                             mask of CH3SRCGATEN field.*/
43342   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH3SRCGATEN field.             */
43343   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH3SRCGATEN field.             */
43344   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43345   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SRCGATEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43346 
43347 /* CH3LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH3_LOCK_EN coreConsultant parameter. */
43348   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Pos (10UL) /*!< Position of CH3LOCKEN field.                              */
43349   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Pos) /*!< Bit mask
43350                                                                             of CH3LOCKEN field.*/
43351   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH3LOCKEN field.                 */
43352   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH3LOCKEN field.                 */
43353   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_FALSE (0x0UL) /*!< (unspecified)                                          */
43354   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LOCKEN_TRUE (0x1UL) /*!< (unspecified)                                           */
43355 
43356 /* CH3MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH3_MULTI_BLK_EN coreConsultant parameter. */
43357   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Pos (11UL) /*!< Position of CH3MULTIBLKEN field.                      */
43358   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Pos) /*!<
43359                                                                             Bit mask of CH3MULTIBLKEN field.*/
43360   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH3MULTIBLKEN field.         */
43361   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH3MULTIBLKEN field.         */
43362   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified)                                      */
43363   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified)                                       */
43364 
43365 /* CH3CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH3_CTL_WB_EN coreConsultant parameter. */
43366   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Pos (12UL) /*!< Position of CH3CTLWBEN field.                            */
43367   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Pos) /*!< Bit
43368                                                                             mask of CH3CTLWBEN field.*/
43369   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH3CTLWBEN field.               */
43370   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH3CTLWBEN field.               */
43371   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_FALSE (0x0UL) /*!< (unspecified)                                         */
43372   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3CTLWBEN_TRUE (0x1UL) /*!< (unspecified)                                          */
43373 
43374 /* CH3HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH3_HC_LLP coreConsultant parameter. */
43375   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Pos (13UL) /*!< Position of CH3HCLLP field.                                */
43376   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Pos) /*!< Bit mask
43377                                                                             of CH3HCLLP field.*/
43378   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Min (0x0UL) /*!< Min enumerator value of CH3HCLLP field.                   */
43379   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_Max (0x1UL) /*!< Max enumerator value of CH3HCLLP field.                   */
43380   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified)                                    */
43381   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3HCLLP_HARDCODED (0x1UL) /*!< (unspecified)                                       */
43382 
43383 /* CH3FC @Bits 14..15 : The value of this register is derived from the DMAH_CH3_FC coreConsultant parameter. */
43384   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Pos (14UL) /*!< Position of CH3FC field.                                      */
43385   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Pos) /*!< Bit mask of
43386                                                                             CH3FC field.*/
43387   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Min (0x0UL) /*!< Min enumerator value of CH3FC field.                         */
43388   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_Max (0x3UL) /*!< Max enumerator value of CH3FC field.                         */
43389   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_FC_DMA (0x0UL) /*!< (unspecified)                                             */
43390   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_FC_SRC (0x1UL) /*!< (unspecified)                                             */
43391   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_FC_DST (0x2UL) /*!< (unspecified)                                             */
43392   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FC_FC_ANY (0x3UL) /*!< (unspecified)                                             */
43393 
43394 /* CH3MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH3_MULT_SIZE coreConsultant parameter. */
43395   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Pos (16UL) /*!< Position of CH3MAXMULTSIZE field.                    */
43396   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Pos)
43397                                                                             /*!< Bit mask of CH3MAXMULTSIZE field.*/
43398   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH3MAXMULTSIZE field.       */
43399   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH3MAXMULTSIZE field.       */
43400   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified)                           */
43401   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified)                           */
43402   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified)                          */
43403   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified)                          */
43404   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified)                          */
43405   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified)                         */
43406   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified)                         */
43407 
43408 /* CH3DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH3_DMS coreConsultant parameter. */
43409   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Pos (19UL) /*!< Position of CH3DMS field.                                    */
43410   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Pos) /*!< Bit mask of
43411                                                                             CH3DMS field.*/
43412   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Min (0x0UL) /*!< Min enumerator value of CH3DMS field.                       */
43413   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_Max (0x4UL) /*!< Max enumerator value of CH3DMS field.                       */
43414   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43415   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43416   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43417   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43418   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43419 
43420 /* CH3LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH3_LMS coreConsultant parameter. */
43421   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Pos (22UL) /*!< Position of CH3LMS field.                                    */
43422   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Pos) /*!< Bit mask of
43423                                                                             CH3LMS field.*/
43424   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Min (0x0UL) /*!< Min enumerator value of CH3LMS field.                       */
43425   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_Max (0x4UL) /*!< Max enumerator value of CH3LMS field.                       */
43426   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43427   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43428   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43429   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43430   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43431 
43432 /* CH3SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH3_SMS coreConsultant parameter. */
43433   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Pos (25UL) /*!< Position of CH3SMS field.                                    */
43434   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Pos) /*!< Bit mask of
43435                                                                             CH3SMS field.*/
43436   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Min (0x0UL) /*!< Min enumerator value of CH3SMS field.                       */
43437   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_Max (0x4UL) /*!< Max enumerator value of CH3SMS field.                       */
43438   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43439   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43440   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43441   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43442   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43443 
43444 /* CH3FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH3_FIFO_DEPTH coreConsultant parameter. */
43445   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Pos (28UL) /*!< Position of CH3FIFODEPTH field.                        */
43446   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Pos) /*!<
43447                                                                             Bit mask of CH3FIFODEPTH field.*/
43448   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH3FIFODEPTH field.           */
43449   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH3FIFODEPTH field.           */
43450   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified)                                */
43451   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified)                               */
43452   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified)                               */
43453   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified)                               */
43454   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified)                              */
43455   #define I3CCORE_DMA_MISC_DMACOMPPARAMS4H_CH3FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified)                              */
43456 
43457 
43458 /* I3CCORE_DMA_MISC_DMACOMPPARAMS3L: DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about
43459                                       the component parameter settings for Channel 1 and Channel 2. */
43460 
43461   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS3L register.             */
43462 
43463 /* CH2DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH2_DTW coreConsultant parameter. */
43464   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Pos (0UL) /*!< Position of CH2DTW field.                                     */
43465   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Pos) /*!< Bit mask of
43466                                                                             CH2DTW field.*/
43467   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Min (0x0UL) /*!< Min enumerator value of CH2DTW field.                       */
43468   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_Max (0x6UL) /*!< Max enumerator value of CH2DTW field.                       */
43469   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43470   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43471   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43472   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43473   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43474   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43475   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43476 
43477 /* CH2STW @Bits 3..5 : The value of this register is derived from the DMAH_CH2_STW coreConsultant parameter. */
43478   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Pos (3UL) /*!< Position of CH2STW field.                                     */
43479   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Pos) /*!< Bit mask of
43480                                                                             CH2STW field.*/
43481   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Min (0x0UL) /*!< Min enumerator value of CH2STW field.                       */
43482   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_Max (0x6UL) /*!< Max enumerator value of CH2STW field.                       */
43483   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43484   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43485   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43486   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43487   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43488   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43489   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43490 
43491 /* CH2STATDST @Bit 6 : The value of this register is derived from the DMAH_CH2_STAT_DST coreConsultant parameter. */
43492   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Pos (6UL) /*!< Position of CH2STATDST field.                             */
43493   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Pos) /*!< Bit
43494                                                                             mask of CH2STATDST field.*/
43495   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Min (0x0UL) /*!< Min enumerator value of CH2STATDST field.               */
43496   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_Max (0x1UL) /*!< Max enumerator value of CH2STATDST field.               */
43497   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_FALSE (0x0UL) /*!< (unspecified)                                         */
43498   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATDST_TRUE (0x1UL) /*!< (unspecified)                                          */
43499 
43500 /* CH2STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH2_STAT_SRC coreConsultant parameter. */
43501   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Pos (7UL) /*!< Position of CH2STATSRC field.                             */
43502   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Pos) /*!< Bit
43503                                                                             mask of CH2STATSRC field.*/
43504   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Min (0x0UL) /*!< Min enumerator value of CH2STATSRC field.               */
43505   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_Max (0x1UL) /*!< Max enumerator value of CH2STATSRC field.               */
43506   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_FALSE (0x0UL) /*!< (unspecified)                                         */
43507   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2STATSRC_TRUE (0x1UL) /*!< (unspecified)                                          */
43508 
43509 /* CH2DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH2_DST_SCA_EN coreConsultant parameter. */
43510   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Pos (8UL) /*!< Position of CH2DSTSCAEN field.                           */
43511   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Pos) /*!< Bit
43512                                                                             mask of CH2DSTSCAEN field.*/
43513   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH2DSTSCAEN field.             */
43514   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH2DSTSCAEN field.             */
43515   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43516   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DSTSCAEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43517 
43518 /* CH2SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH2_SRC_GAT_EN coreConsultant parameter. */
43519   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Pos (9UL) /*!< Position of CH2SRCGATEN field.                           */
43520   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Pos) /*!< Bit
43521                                                                             mask of CH2SRCGATEN field.*/
43522   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH2SRCGATEN field.             */
43523   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH2SRCGATEN field.             */
43524   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43525   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SRCGATEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43526 
43527 /* CH2LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH2_LOCK_EN coreConsultant parameter. */
43528   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Pos (10UL) /*!< Position of CH2LOCKEN field.                              */
43529   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Pos) /*!< Bit mask
43530                                                                             of CH2LOCKEN field.*/
43531   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH2LOCKEN field.                 */
43532   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH2LOCKEN field.                 */
43533   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_FALSE (0x0UL) /*!< (unspecified)                                          */
43534   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LOCKEN_TRUE (0x1UL) /*!< (unspecified)                                           */
43535 
43536 /* CH2MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH2_MULTI_BLK_EN coreConsultant parameter. */
43537   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Pos (11UL) /*!< Position of CH2MULTIBLKEN field.                      */
43538   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Pos) /*!<
43539                                                                             Bit mask of CH2MULTIBLKEN field.*/
43540   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH2MULTIBLKEN field.         */
43541   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH2MULTIBLKEN field.         */
43542   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified)                                      */
43543   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified)                                       */
43544 
43545 /* CH2CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH2_CTL_WB_EN coreConsultant parameter. */
43546   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Pos (12UL) /*!< Position of CH2CTLWBEN field.                            */
43547   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Pos) /*!< Bit
43548                                                                             mask of CH2CTLWBEN field.*/
43549   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH2CTLWBEN field.               */
43550   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH2CTLWBEN field.               */
43551   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_FALSE (0x0UL) /*!< (unspecified)                                         */
43552   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2CTLWBEN_TRUE (0x1UL) /*!< (unspecified)                                          */
43553 
43554 /* CH2HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH2_HC_LLP coreConsultant parameter. */
43555   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Pos (13UL) /*!< Position of CH2HCLLP field.                                */
43556   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Pos) /*!< Bit mask
43557                                                                             of CH2HCLLP field.*/
43558   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Min (0x0UL) /*!< Min enumerator value of CH2HCLLP field.                   */
43559   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_Max (0x1UL) /*!< Max enumerator value of CH2HCLLP field.                   */
43560   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified)                                    */
43561   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2HCLLP_HARDCODED (0x1UL) /*!< (unspecified)                                       */
43562 
43563 /* CH2FC @Bits 14..15 : The value of this register is derived from the DMAH_CH2_FC coreConsultant parameter. */
43564   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Pos (14UL) /*!< Position of CH2FC field.                                      */
43565   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Pos) /*!< Bit mask of
43566                                                                             CH2FC field.*/
43567   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Min (0x0UL) /*!< Min enumerator value of CH2FC field.                         */
43568   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_Max (0x3UL) /*!< Max enumerator value of CH2FC field.                         */
43569   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_FC_DMA (0x0UL) /*!< (unspecified)                                             */
43570   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_FC_SRC (0x1UL) /*!< (unspecified)                                             */
43571   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_FC_DST (0x2UL) /*!< (unspecified)                                             */
43572   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FC_FC_ANY (0x3UL) /*!< (unspecified)                                             */
43573 
43574 /* CH2MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH2_MULT_SIZE coreConsultant parameter. */
43575   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Pos (16UL) /*!< Position of CH2MAXMULTSIZE field.                    */
43576   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Pos)
43577                                                                             /*!< Bit mask of CH2MAXMULTSIZE field.*/
43578   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH2MAXMULTSIZE field.       */
43579   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH2MAXMULTSIZE field.       */
43580   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified)                           */
43581   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified)                           */
43582   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified)                          */
43583   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified)                          */
43584   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified)                          */
43585   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified)                         */
43586   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified)                         */
43587 
43588 /* CH2DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH2_DMS coreConsultant parameter. */
43589   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Pos (19UL) /*!< Position of CH2DMS field.                                    */
43590   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Pos) /*!< Bit mask of
43591                                                                             CH2DMS field.*/
43592   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Min (0x0UL) /*!< Min enumerator value of CH2DMS field.                       */
43593   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_Max (0x4UL) /*!< Max enumerator value of CH2DMS field.                       */
43594   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43595   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43596   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43597   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43598   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43599 
43600 /* CH2LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH2_LMS coreConsultant parameter. */
43601   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Pos (22UL) /*!< Position of CH2LMS field.                                    */
43602   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Pos) /*!< Bit mask of
43603                                                                             CH2LMS field.*/
43604   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Min (0x0UL) /*!< Min enumerator value of CH2LMS field.                       */
43605   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_Max (0x4UL) /*!< Max enumerator value of CH2LMS field.                       */
43606   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43607   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43608   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43609   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43610   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2LMS_PROGRAMMALE (0x4UL) /*!< (unspecified)                                       */
43611 
43612 /* CH2SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH2_SMS coreConsultant parameter. */
43613   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Pos (25UL) /*!< Position of CH2SMS field.                                    */
43614   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Pos) /*!< Bit mask of
43615                                                                             CH2SMS field.*/
43616   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Min (0x0UL) /*!< Min enumerator value of CH2SMS field.                       */
43617   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_Max (0x4UL) /*!< Max enumerator value of CH2SMS field.                       */
43618   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43619   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43620   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43621   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43622   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2SMS_PROGRAMMALE (0x4UL) /*!< (unspecified)                                       */
43623 
43624 /* CH2FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH2_FIFO_DEPTH coreConsultant parameter. */
43625   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Pos (28UL) /*!< Position of CH2FIFODEPTH field.                        */
43626   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Pos) /*!<
43627                                                                             Bit mask of CH2FIFODEPTH field.*/
43628   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH2FIFODEPTH field.           */
43629   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH2FIFODEPTH field.           */
43630   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified)                                */
43631   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified)                               */
43632   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified)                               */
43633   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified)                               */
43634   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified)                              */
43635   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3L_CH2FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified)                              */
43636 
43637 
43638 /* I3CCORE_DMA_MISC_DMACOMPPARAMS3H: DMA_COMP_PARAMS_3 is a constant read-only register that contains encoded information about
43639                                       the component parameter settings for Channel 1 and Channel 2. */
43640 
43641   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_ResetValue (0x1109A203UL) /*!< Reset value of DMACOMPPARAMS3H register.             */
43642 
43643 /* CH1DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH1_DTW coreConsultant parameter. */
43644   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Pos (0UL) /*!< Position of CH1DTW field.                                     */
43645   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Pos) /*!< Bit mask of
43646                                                                             CH1DTW field.*/
43647   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Min (0x0UL) /*!< Min enumerator value of CH1DTW field.                       */
43648   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_Max (0x6UL) /*!< Max enumerator value of CH1DTW field.                       */
43649   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43650   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43651   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43652   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43653   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43654   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43655   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43656 
43657 /* CH1STW @Bits 3..5 : The value of this register is derived from the DMAH_CH1_STW coreConsultant parameter. */
43658   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Pos (3UL) /*!< Position of CH1STW field.                                     */
43659   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Pos) /*!< Bit mask of
43660                                                                             CH1STW field.*/
43661   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Min (0x0UL) /*!< Min enumerator value of CH1STW field.                       */
43662   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_Max (0x6UL) /*!< Max enumerator value of CH1STW field.                       */
43663   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43664   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43665   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43666   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43667   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43668   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43669   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43670 
43671 /* CH1STATDST @Bit 6 : The value of this register is derived from the DMAH_CH1_STAT_DST coreConsultant parameter. */
43672   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Pos (6UL) /*!< Position of CH1STATDST field.                             */
43673   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Pos) /*!< Bit
43674                                                                             mask of CH1STATDST field.*/
43675   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Min (0x0UL) /*!< Min enumerator value of CH1STATDST field.               */
43676   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_Max (0x1UL) /*!< Max enumerator value of CH1STATDST field.               */
43677   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_FALSE (0x0UL) /*!< (unspecified)                                         */
43678   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATDST_TRUE (0x1UL) /*!< (unspecified)                                          */
43679 
43680 /* CH1STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH1_STAT_SRC coreConsultant parameter. */
43681   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Pos (7UL) /*!< Position of CH1STATSRC field.                             */
43682   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Pos) /*!< Bit
43683                                                                             mask of CH1STATSRC field.*/
43684   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Min (0x0UL) /*!< Min enumerator value of CH1STATSRC field.               */
43685   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_Max (0x1UL) /*!< Max enumerator value of CH1STATSRC field.               */
43686   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_FALSE (0x0UL) /*!< (unspecified)                                         */
43687   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1STATSRC_TRUE (0x1UL) /*!< (unspecified)                                          */
43688 
43689 /* CH1DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH1_DST_SCA_EN coreConsultant parameter. */
43690   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Pos (8UL) /*!< Position of CH1DSTSCAEN field.                           */
43691   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Pos) /*!< Bit
43692                                                                             mask of CH1DSTSCAEN field.*/
43693   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH1DSTSCAEN field.             */
43694   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH1DSTSCAEN field.             */
43695   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43696   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DSTSCAEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43697 
43698 /* CH1SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH1_SRC_GAT_EN coreConsultant parameter. */
43699   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Pos (9UL) /*!< Position of CH1SRCGATEN field.                           */
43700   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Pos) /*!< Bit
43701                                                                             mask of CH1SRCGATEN field.*/
43702   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH1SRCGATEN field.             */
43703   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH1SRCGATEN field.             */
43704   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43705   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SRCGATEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43706 
43707 /* CH1LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH1_LOCK_EN coreConsultant parameter. */
43708   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Pos (10UL) /*!< Position of CH1LOCKEN field.                              */
43709   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Pos) /*!< Bit mask
43710                                                                             of CH1LOCKEN field.*/
43711   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH1LOCKEN field.                 */
43712   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH1LOCKEN field.                 */
43713   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_FALSE (0x0UL) /*!< (unspecified)                                          */
43714   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LOCKEN_TRUE (0x1UL) /*!< (unspecified)                                           */
43715 
43716 /* CH1MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH1_MULTI_BLK_EN coreConsultant parameter. */
43717   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Pos (11UL) /*!< Position of CH1MULTIBLKEN field.                      */
43718   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Pos) /*!<
43719                                                                             Bit mask of CH1MULTIBLKEN field.*/
43720   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH1MULTIBLKEN field.         */
43721   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH1MULTIBLKEN field.         */
43722   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified)                                      */
43723   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified)                                       */
43724 
43725 /* CH1CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH1_CTL_WB_EN coreConsultant parameter. */
43726   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Pos (12UL) /*!< Position of CH1CTLWBEN field.                            */
43727   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Pos) /*!< Bit
43728                                                                             mask of CH1CTLWBEN field.*/
43729   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH1CTLWBEN field.               */
43730   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH1CTLWBEN field.               */
43731   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_FALSE (0x0UL) /*!< (unspecified)                                         */
43732   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1CTLWBEN_TRUE (0x1UL) /*!< (unspecified)                                          */
43733 
43734 /* CH1HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH1_HC_LLP coreConsultant parameter. */
43735   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Pos (13UL) /*!< Position of CH1HCLLP field.                                */
43736   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Pos) /*!< Bit mask
43737                                                                             of CH1HCLLP field.*/
43738   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Min (0x0UL) /*!< Min enumerator value of CH1HCLLP field.                   */
43739   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_Max (0x1UL) /*!< Max enumerator value of CH1HCLLP field.                   */
43740   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified)                                    */
43741   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1HCLLP_HARDCODED (0x1UL) /*!< (unspecified)                                       */
43742 
43743 /* CH1FC @Bits 14..15 : The value of this register is derived from the DMAH_CH1_FC coreConsultant parameter. */
43744   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Pos (14UL) /*!< Position of CH1FC field.                                      */
43745   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Pos) /*!< Bit mask of
43746                                                                             CH1FC field.*/
43747   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Min (0x0UL) /*!< Min enumerator value of CH1FC field.                         */
43748   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_Max (0x3UL) /*!< Max enumerator value of CH1FC field.                         */
43749   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_FC_DMA (0x0UL) /*!< (unspecified)                                             */
43750   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_FC_SRC (0x1UL) /*!< (unspecified)                                             */
43751   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_FC_DST (0x2UL) /*!< (unspecified)                                             */
43752   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FC_FC_ANY (0x3UL) /*!< (unspecified)                                             */
43753 
43754 /* CH1MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH1_MULT_SIZE coreConsultant parameter. */
43755   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Pos (16UL) /*!< Position of CH1MAXMULTSIZE field.                    */
43756   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Pos)
43757                                                                             /*!< Bit mask of CH1MAXMULTSIZE field.*/
43758   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH1MAXMULTSIZE field.       */
43759   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH1MAXMULTSIZE field.       */
43760   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified)                           */
43761   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified)                           */
43762   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified)                          */
43763   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified)                          */
43764   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified)                          */
43765   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified)                         */
43766   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified)                         */
43767 
43768 /* CH1DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH1_DMS coreConsultant parameter. */
43769   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Pos (19UL) /*!< Position of CH1DMS field.                                    */
43770   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Pos) /*!< Bit mask of
43771                                                                             CH1DMS field.*/
43772   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Min (0x0UL) /*!< Min enumerator value of CH1DMS field.                       */
43773   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_Max (0x4UL) /*!< Max enumerator value of CH1DMS field.                       */
43774   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43775   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43776   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43777   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43778   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43779 
43780 /* CH1LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH1_LMS coreConsultant parameter. */
43781   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Pos (22UL) /*!< Position of CH1LMS field.                                    */
43782   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Pos) /*!< Bit mask of
43783                                                                             CH1LMS field.*/
43784   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Min (0x0UL) /*!< Min enumerator value of CH1LMS field.                       */
43785   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_Max (0x4UL) /*!< Max enumerator value of CH1LMS field.                       */
43786   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43787   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43788   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43789   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43790   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43791 
43792 /* CH1SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH1_SMS coreConsultant parameter. */
43793   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Pos (25UL) /*!< Position of CH1SMS field.                                    */
43794   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Pos) /*!< Bit mask of
43795                                                                             CH1SMS field.*/
43796   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Min (0x0UL) /*!< Min enumerator value of CH1SMS field.                       */
43797   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_Max (0x4UL) /*!< Max enumerator value of CH1SMS field.                       */
43798   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43799   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43800   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43801   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43802   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43803 
43804 /* CH1FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH1_FIFO_DEPTH coreConsultant parameter. */
43805   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Pos (28UL) /*!< Position of CH1FIFODEPTH field.                        */
43806   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Pos) /*!<
43807                                                                             Bit mask of CH1FIFODEPTH field.*/
43808   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH1FIFODEPTH field.           */
43809   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH1FIFODEPTH field.           */
43810   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified)                                */
43811   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified)                               */
43812   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified)                               */
43813   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified)                               */
43814   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified)                              */
43815   #define I3CCORE_DMA_MISC_DMACOMPPARAMS3H_CH1FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified)                              */
43816 
43817 
43818 /* I3CCORE_DMA_MISC_DMACOMPPARAMS2L: DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about
43819                                       the component parameter settings. */
43820 
43821   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_ResetValue (0x13016118UL) /*!< Reset value of DMACOMPPARAMS2L register.             */
43822 
43823 /* CH0DTW @Bits 0..2 : The value of this register is derived from the DMAH_CH0_DTW coreConsultant parameter. */
43824   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Pos (0UL) /*!< Position of CH0DTW field.                                     */
43825   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Pos) /*!< Bit mask of
43826                                                                             CH0DTW field.*/
43827   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Min (0x0UL) /*!< Min enumerator value of CH0DTW field.                       */
43828   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_Max (0x6UL) /*!< Max enumerator value of CH0DTW field.                       */
43829   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43830   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43831   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43832   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43833   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43834   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43835   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DTW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43836 
43837 /* CH0STW @Bits 3..5 : The value of this register is derived from the DMAH_CH0_STW coreConsultant parameter. */
43838   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Pos (3UL) /*!< Position of CH0STW field.                                     */
43839   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Pos) /*!< Bit mask of
43840                                                                             CH0STW field.*/
43841   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Min (0x0UL) /*!< Min enumerator value of CH0STW field.                       */
43842   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_Max (0x6UL) /*!< Max enumerator value of CH0STW field.                       */
43843   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_PROGRAMMABLE (0x0UL) /*!< (unspecified)                          */
43844   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_8 (0x1UL) /*!< (unspecified)                                     */
43845   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_16 (0x2UL) /*!< (unspecified)                                    */
43846   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_32 (0x3UL) /*!< (unspecified)                                    */
43847   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_64 (0x4UL) /*!< (unspecified)                                    */
43848   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_128 (0x5UL) /*!< (unspecified)                                   */
43849   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STW_TRANS_WIDTH_256 (0x6UL) /*!< (unspecified)                                   */
43850 
43851 /* CH0STATDST @Bit 6 : The value of this register is derived from the DMAH_CH0_STAT_DST coreConsultant parameter. */
43852   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Pos (6UL) /*!< Position of CH0STATDST field.                             */
43853   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Pos) /*!< Bit
43854                                                                             mask of CH0STATDST field.*/
43855   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Min (0x0UL) /*!< Min enumerator value of CH0STATDST field.               */
43856   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_Max (0x1UL) /*!< Max enumerator value of CH0STATDST field.               */
43857   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_FALSE (0x0UL) /*!< (unspecified)                                         */
43858   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATDST_TRUE (0x1UL) /*!< (unspecified)                                          */
43859 
43860 /* CH0STATSRC @Bit 7 : The value of this register is derived from the DMAH_CH0_STAT_SRC coreConsultant parameter. */
43861   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Pos (7UL) /*!< Position of CH0STATSRC field.                             */
43862   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Pos) /*!< Bit
43863                                                                             mask of CH0STATSRC field.*/
43864   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Min (0x0UL) /*!< Min enumerator value of CH0STATSRC field.               */
43865   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_Max (0x1UL) /*!< Max enumerator value of CH0STATSRC field.               */
43866   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_FALSE (0x0UL) /*!< (unspecified)                                         */
43867   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0STATSRC_TRUE (0x1UL) /*!< (unspecified)                                          */
43868 
43869 /* CH0DSTSCAEN @Bit 8 : The value of this register is derived from the DMAH_CH0_DST_SCA_EN coreConsultant parameter. */
43870   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Pos (8UL) /*!< Position of CH0DSTSCAEN field.                           */
43871   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Pos) /*!< Bit
43872                                                                             mask of CH0DSTSCAEN field.*/
43873   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Min (0x0UL) /*!< Min enumerator value of CH0DSTSCAEN field.             */
43874   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_Max (0x1UL) /*!< Max enumerator value of CH0DSTSCAEN field.             */
43875   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43876   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DSTSCAEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43877 
43878 /* CH0SRCGATEN @Bit 9 : The value of this register is derived from the DMAH_CH0_SRC_GAT_EN coreConsultant parameter. */
43879   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Pos (9UL) /*!< Position of CH0SRCGATEN field.                           */
43880   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Pos) /*!< Bit
43881                                                                             mask of CH0SRCGATEN field.*/
43882   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Min (0x0UL) /*!< Min enumerator value of CH0SRCGATEN field.             */
43883   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_Max (0x1UL) /*!< Max enumerator value of CH0SRCGATEN field.             */
43884   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_FALSE (0x0UL) /*!< (unspecified)                                        */
43885   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SRCGATEN_TRUE (0x1UL) /*!< (unspecified)                                         */
43886 
43887 /* CH0LOCKEN @Bit 10 : The value of this register is derived from the DMAH_CH0_LOCK_EN coreConsultant parameter. */
43888   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Pos (10UL) /*!< Position of CH0LOCKEN field.                              */
43889   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Pos) /*!< Bit mask
43890                                                                             of CH0LOCKEN field.*/
43891   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Min (0x0UL) /*!< Min enumerator value of CH0LOCKEN field.                 */
43892   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_Max (0x1UL) /*!< Max enumerator value of CH0LOCKEN field.                 */
43893   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_FALSE (0x0UL) /*!< (unspecified)                                          */
43894   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LOCKEN_TRUE (0x1UL) /*!< (unspecified)                                           */
43895 
43896 /* CH0MULTIBLKEN @Bit 11 : The value of this register is derived from the DMAH_CH0_MULTI_BLK_EN coreConsultant parameter. */
43897   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Pos (11UL) /*!< Position of CH0MULTIBLKEN field.                      */
43898   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Pos) /*!<
43899                                                                             Bit mask of CH0MULTIBLKEN field.*/
43900   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Min (0x0UL) /*!< Min enumerator value of CH0MULTIBLKEN field.         */
43901   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_Max (0x1UL) /*!< Max enumerator value of CH0MULTIBLKEN field.         */
43902   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_FALSE (0x0UL) /*!< (unspecified)                                      */
43903   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MULTIBLKEN_TRUE (0x1UL) /*!< (unspecified)                                       */
43904 
43905 /* CH0CTLWBEN @Bit 12 : The value of this register is derived from the DMAH_CH0_CTL_WB_EN coreConsultant parameter. */
43906   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Pos (12UL) /*!< Position of CH0CTLWBEN field.                            */
43907   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Pos) /*!< Bit
43908                                                                             mask of CH0CTLWBEN field.*/
43909   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Min (0x0UL) /*!< Min enumerator value of CH0CTLWBEN field.               */
43910   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_Max (0x1UL) /*!< Max enumerator value of CH0CTLWBEN field.               */
43911   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_FALSE (0x0UL) /*!< (unspecified)                                         */
43912   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0CTLWBEN_TRUE (0x1UL) /*!< (unspecified)                                          */
43913 
43914 /* CH0HCLLP @Bit 13 : The value of this register is derived from the DMAH_CH0_HC_LLP coreConsultant parameter. */
43915   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Pos (13UL) /*!< Position of CH0HCLLP field.                                */
43916   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Pos) /*!< Bit mask
43917                                                                             of CH0HCLLP field.*/
43918   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Min (0x0UL) /*!< Min enumerator value of CH0HCLLP field.                   */
43919   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_Max (0x1UL) /*!< Max enumerator value of CH0HCLLP field.                   */
43920   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_PROGRAMMABLE (0x0UL) /*!< (unspecified)                                    */
43921   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0HCLLP_HARDCODED (0x1UL) /*!< (unspecified)                                       */
43922 
43923 /* CH0FC @Bits 14..15 : The value of this register is derived from the DMAH_CH0_FC coreConsultant parameter. */
43924   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Pos (14UL) /*!< Position of CH0FC field.                                      */
43925   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Pos) /*!< Bit mask of
43926                                                                             CH0FC field.*/
43927   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Min (0x0UL) /*!< Min enumerator value of CH0FC field.                         */
43928   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_Max (0x3UL) /*!< Max enumerator value of CH0FC field.                         */
43929   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_FC_DMA (0x0UL) /*!< (unspecified)                                             */
43930   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_FC_SRC (0x1UL) /*!< (unspecified)                                             */
43931   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_FC_DST (0x2UL) /*!< (unspecified)                                             */
43932   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FC_FC_ANY (0x3UL) /*!< (unspecified)                                             */
43933 
43934 /* CH0MAXMULTSIZE @Bits 16..18 : The value of this register is derived from the DMAH_CH0_MULT_SIZE coreConsultant parameter. */
43935   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Pos (16UL) /*!< Position of CH0MAXMULTSIZE field.                    */
43936   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Pos)
43937                                                                             /*!< Bit mask of CH0MAXMULTSIZE field.*/
43938   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Min (0x0UL) /*!< Min enumerator value of CH0MAXMULTSIZE field.       */
43939   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_Max (0x6UL) /*!< Max enumerator value of CH0MAXMULTSIZE field.       */
43940   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_4 (0x0UL) /*!< (unspecified)                           */
43941   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_8 (0x1UL) /*!< (unspecified)                           */
43942   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_16 (0x2UL) /*!< (unspecified)                          */
43943   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_32 (0x3UL) /*!< (unspecified)                          */
43944   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_64 (0x4UL) /*!< (unspecified)                          */
43945   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_128 (0x5UL) /*!< (unspecified)                         */
43946   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0MAXMULTSIZE_MAX_MULT_SIZE_256 (0x6UL) /*!< (unspecified)                         */
43947 
43948 /* CH0DMS @Bits 19..21 : The value of this register is derived from the DMAH_CH0_DMS coreConsultant parameter. */
43949   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Pos (19UL) /*!< Position of CH0DMS field.                                    */
43950   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Pos) /*!< Bit mask of
43951                                                                             CH0DMS field.*/
43952   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Min (0x0UL) /*!< Min enumerator value of CH0DMS field.                       */
43953   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_Max (0x4UL) /*!< Max enumerator value of CH0DMS field.                       */
43954   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43955   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43956   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43957   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43958   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0DMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43959 
43960 /* CH0LMS @Bits 22..24 : The value of this register is derived from the DMAH_CH0_LMS coreConsultant parameter. */
43961   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Pos (22UL) /*!< Position of CH0LMS field.                                    */
43962   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Pos) /*!< Bit mask of
43963                                                                             CH0LMS field.*/
43964   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Min (0x0UL) /*!< Min enumerator value of CH0LMS field.                       */
43965   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_Max (0x4UL) /*!< Max enumerator value of CH0LMS field.                       */
43966   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43967   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43968   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43969   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43970   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0LMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43971 
43972 /* CH0SMS @Bits 25..27 : The value of this register is derived from the DMAH_CH0_SMS coreConsultant parameter. */
43973   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Pos (25UL) /*!< Position of CH0SMS field.                                    */
43974   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Pos) /*!< Bit mask of
43975                                                                             CH0SMS field.*/
43976   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Min (0x0UL) /*!< Min enumerator value of CH0SMS field.                       */
43977   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_Max (0x4UL) /*!< Max enumerator value of CH0SMS field.                       */
43978   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_MASTER_1 (0x0UL) /*!< (unspecified)                                          */
43979   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_MASTER_2 (0x1UL) /*!< (unspecified)                                          */
43980   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_MASTER_3 (0x2UL) /*!< (unspecified)                                          */
43981   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_MASTER_4 (0x3UL) /*!< (unspecified)                                          */
43982   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0SMS_PROGRAMMABLE (0x4UL) /*!< (unspecified)                                      */
43983 
43984 /* CH0FIFODEPTH @Bits 28..30 : The value of this register is derived from the DMAH_CH0_FIFO_DEPTH coreConsultant parameter. */
43985   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Pos (28UL) /*!< Position of CH0FIFODEPTH field.                        */
43986   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Pos) /*!<
43987                                                                             Bit mask of CH0FIFODEPTH field.*/
43988   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Min (0x0UL) /*!< Min enumerator value of CH0FIFODEPTH field.           */
43989   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_Max (0x5UL) /*!< Max enumerator value of CH0FIFODEPTH field.           */
43990   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_8 (0x0UL) /*!< (unspecified)                                */
43991   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_16 (0x1UL) /*!< (unspecified)                               */
43992   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_32 (0x2UL) /*!< (unspecified)                               */
43993   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_64 (0x3UL) /*!< (unspecified)                               */
43994   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_128 (0x4UL) /*!< (unspecified)                              */
43995   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2L_CH0FIFODEPTH_FIFO_DEPTH_256 (0x5UL) /*!< (unspecified)                              */
43996 
43997 
43998 /* I3CCORE_DMA_MISC_DMACOMPPARAMS2H: DMA_COMP_PARAMS_2 is a constant read-only register that contains encoded information about
43999                                       the component parameter settings. */
44000 
44001   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_ResetValue (0x00000000UL) /*!< Reset value of DMACOMPPARAMS2H register.             */
44002 
44003 /* CHOMULTIBLKTYPE @Bits 0..3 : The values of these bit fields are derived from the DMAH_CH0_MULTI_BLK_TYPE coreConsultant
44004                                 parameter. */
44005 
44006   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Pos (0UL) /*!< Position of CHOMULTIBLKTYPE field.                   */
44007   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Pos)
44008                                                                             /*!< Bit mask of CHOMULTIBLKTYPE field.*/
44009   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CHOMULTIBLKTYPE field.     */
44010   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CHOMULTIBLKTYPE field.     */
44011   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified)                             */
44012   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified)                              */
44013   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified)                              */
44014   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified)                            */
44015   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified)                                 */
44016   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified)                               */
44017   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified)                                  */
44018   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified)                               */
44019   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CHOMULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified)                                  */
44020 
44021 /* CH1MULTIBLKTYPE @Bits 4..7 : The values of these bit fields are derived from the DMAH_CH1_MULTI_BLK_TYPE coreConsultant
44022                                 parameter. */
44023 
44024   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Pos (4UL) /*!< Position of CH1MULTIBLKTYPE field.                   */
44025   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Pos)
44026                                                                             /*!< Bit mask of CH1MULTIBLKTYPE field.*/
44027   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH1MULTIBLKTYPE field.     */
44028   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH1MULTIBLKTYPE field.     */
44029   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified)                             */
44030   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified)                              */
44031   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified)                              */
44032   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified)                            */
44033   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified)                                 */
44034   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified)                               */
44035   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified)                                  */
44036   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified)                               */
44037   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH1MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified)                                  */
44038 
44039 /* CH2MULTIBLKTYPE @Bits 8..11 : The values of these bit fields are derived from the DMAH_CH2_MULTI_BLK_TYPE coreConsultant
44040                                  parameter. */
44041 
44042   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Pos (8UL) /*!< Position of CH2MULTIBLKTYPE field.                   */
44043   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Pos)
44044                                                                             /*!< Bit mask of CH2MULTIBLKTYPE field.*/
44045   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH2MULTIBLKTYPE field.     */
44046   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH2MULTIBLKTYPE field.     */
44047   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified)                             */
44048   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified)                              */
44049   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified)                              */
44050   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified)                            */
44051   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified)                                 */
44052   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified)                               */
44053   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified)                                  */
44054   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified)                               */
44055   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH2MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified)                                  */
44056 
44057 /* CH3MULTIBLKTYPE @Bits 12..15 : The values of these bit fields are derived from the DMAH_CH3_MULTI_BLK_TYPE coreConsultant
44058                                   parameter. */
44059 
44060   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Pos (12UL) /*!< Position of CH3MULTIBLKTYPE field.                  */
44061   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Pos)
44062                                                                             /*!< Bit mask of CH3MULTIBLKTYPE field.*/
44063   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH3MULTIBLKTYPE field.     */
44064   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH3MULTIBLKTYPE field.     */
44065   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified)                             */
44066   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified)                              */
44067   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified)                              */
44068   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified)                            */
44069   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified)                                 */
44070   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified)                               */
44071   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified)                                  */
44072   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified)                               */
44073   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH3MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified)                                  */
44074 
44075 /* CH4MULTIBLKTYPE @Bits 16..19 : The values of these bit fields are derived from the DMAH_CH4_MULTI_BLK_TYPE coreConsultant
44076                                   parameter. */
44077 
44078   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Pos (16UL) /*!< Position of CH4MULTIBLKTYPE field.                  */
44079   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Pos)
44080                                                                             /*!< Bit mask of CH4MULTIBLKTYPE field.*/
44081   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH4MULTIBLKTYPE field.     */
44082   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH4MULTIBLKTYPE field.     */
44083   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified)                             */
44084   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified)                              */
44085   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified)                              */
44086   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified)                            */
44087   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified)                                 */
44088   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified)                               */
44089   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified)                                  */
44090   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified)                               */
44091   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH4MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified)                                  */
44092 
44093 /* CH5MULTIBLKTYPE @Bits 20..23 : The values of these bit fields are derived from the DMAH_CH5_MULTI_BLK_TYPE coreConsultant
44094                                   parameter. */
44095 
44096   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Pos (20UL) /*!< Position of CH5MULTIBLKTYPE field.                  */
44097   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Pos)
44098                                                                             /*!< Bit mask of CH5MULTIBLKTYPE field.*/
44099   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH5MULTIBLKTYPE field.     */
44100   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH5MULTIBLKTYPE field.     */
44101   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified)                             */
44102   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified)                              */
44103   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified)                              */
44104   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified)                            */
44105   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified)                                 */
44106   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified)                               */
44107   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified)                                  */
44108   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified)                               */
44109   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH5MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified)                                  */
44110 
44111 /* CH6MULTIBLKTYPE @Bits 24..27 : The values of these bit fields are derived from the DMAH_CH6_MULTI_BLK_TYPE coreConsultant
44112                                   parameter. */
44113 
44114   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Pos (24UL) /*!< Position of CH6MULTIBLKTYPE field.                  */
44115   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Pos)
44116                                                                             /*!< Bit mask of CH6MULTIBLKTYPE field.*/
44117   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH6MULTIBLKTYPE field.     */
44118   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH6MULTIBLKTYPE field.     */
44119   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified)                             */
44120   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified)                              */
44121   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified)                              */
44122   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified)                            */
44123   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified)                                 */
44124   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified)                               */
44125   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified)                                  */
44126   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified)                               */
44127   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH6MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified)                                  */
44128 
44129 /* CH7MULTIBLKTYPE @Bits 28..31 : The values of these bit fields are derived from the DMAH_CH7_MULTI_BLK_TYPE coreConsultant
44130                                   parameter. */
44131 
44132   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Pos (28UL) /*!< Position of CH7MULTIBLKTYPE field.                  */
44133   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Pos)
44134                                                                             /*!< Bit mask of CH7MULTIBLKTYPE field.*/
44135   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Min (0x0UL) /*!< Min enumerator value of CH7MULTIBLKTYPE field.     */
44136   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_Max (0x8UL) /*!< Max enumerator value of CH7MULTIBLKTYPE field.     */
44137   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_PROGRAMMABLE (0x0UL) /*!< (unspecified)                             */
44138   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_CONT_RELOAD (0x1UL) /*!< (unspecified)                              */
44139   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_RELOAD_CONT (0x2UL) /*!< (unspecified)                              */
44140   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_RELOAD_RELOAD (0x3UL) /*!< (unspecified)                            */
44141   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_CONT_LLP (0x4UL) /*!< (unspecified)                                 */
44142   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_RELOAD_LLP (0x5UL) /*!< (unspecified)                               */
44143   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_CNT_LLP (0x6UL) /*!< (unspecified)                                  */
44144   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_LLP_RELOAD (0x7UL) /*!< (unspecified)                               */
44145   #define I3CCORE_DMA_MISC_DMACOMPPARAMS2H_CH7MULTIBLKTYPE_LLP_LLP (0x8UL) /*!< (unspecified)                                  */
44146 
44147 
44148 /* I3CCORE_DMA_MISC_DMACOMPPARAMS1L: DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about
44149                                       the component parameter settings. */
44150 
44151   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_ResetValue (0x33333333UL) /*!< Reset value of DMACOMPPARAMS1L register.             */
44152 
44153 /* CHOMAXBLKSIZE @Bits 0..3 : The values of these bit fields are derived from the DMAH_CH0_MAX_BLK_SIZE coreConsultant
44154                               parameter. */
44155 
44156   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Pos (0UL) /*!< Position of CHOMAXBLKSIZE field.                       */
44157   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Pos) /*!<
44158                                                                             Bit mask of CHOMAXBLKSIZE field.*/
44159   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CHOMAXBLKSIZE field.         */
44160   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CHOMAXBLKSIZE field.         */
44161   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified)                           */
44162   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified)                           */
44163   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified)                          */
44164   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified)                          */
44165   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified)                          */
44166   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified)                         */
44167   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified)                         */
44168   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified)                         */
44169   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified)                        */
44170   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified)                        */
44171   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CHOMAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified)                        */
44172 
44173 /* CH1MAXBLKSIZE @Bits 4..7 : The values of these bit fields are derived from the DMAH_CH1_MAX_BLK_SIZE coreConsultant
44174                               parameter. */
44175 
44176   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Pos (4UL) /*!< Position of CH1MAXBLKSIZE field.                       */
44177   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Pos) /*!<
44178                                                                             Bit mask of CH1MAXBLKSIZE field.*/
44179   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH1MAXBLKSIZE field.         */
44180   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH1MAXBLKSIZE field.         */
44181   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified)                           */
44182   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified)                           */
44183   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified)                          */
44184   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified)                          */
44185   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified)                          */
44186   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified)                         */
44187   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified)                         */
44188   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified)                         */
44189   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified)                        */
44190   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified)                        */
44191   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH1MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified)                        */
44192 
44193 /* CH2MAXBLKSIZE @Bits 8..11 : The values of these bit fields are derived from the DMAH_CH2_MAX_BLK_SIZE coreConsultant
44194                                parameter. */
44195 
44196   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Pos (8UL) /*!< Position of CH2MAXBLKSIZE field.                       */
44197   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Pos) /*!<
44198                                                                             Bit mask of CH2MAXBLKSIZE field.*/
44199   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH2MAXBLKSIZE field.         */
44200   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH2MAXBLKSIZE field.         */
44201   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified)                           */
44202   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified)                           */
44203   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified)                          */
44204   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified)                          */
44205   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified)                          */
44206   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified)                         */
44207   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified)                         */
44208   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified)                         */
44209   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified)                        */
44210   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified)                        */
44211   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH2MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified)                        */
44212 
44213 /* CH3MAXBLKSIZE @Bits 12..15 : The values of these bit fields are derived from the DMAH_CH3_MAX_BLK_SIZE coreConsultant
44214                                 parameter. */
44215 
44216   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Pos (12UL) /*!< Position of CH3MAXBLKSIZE field.                      */
44217   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Pos) /*!<
44218                                                                             Bit mask of CH3MAXBLKSIZE field.*/
44219   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH3MAXBLKSIZE field.         */
44220   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH3MAXBLKSIZE field.         */
44221   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified)                           */
44222   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified)                           */
44223   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified)                          */
44224   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified)                          */
44225   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified)                          */
44226   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified)                         */
44227   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified)                         */
44228   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified)                         */
44229   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified)                        */
44230   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified)                        */
44231   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH3MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified)                        */
44232 
44233 /* CH4MAXBLKSIZE @Bits 16..19 : The values of these bit fields are derived from the DMAH_CH4_MAX_BLK_SIZE coreConsultant
44234                                 parameter. */
44235 
44236   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Pos (16UL) /*!< Position of CH4MAXBLKSIZE field.                      */
44237   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Pos) /*!<
44238                                                                             Bit mask of CH4MAXBLKSIZE field.*/
44239   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH4MAXBLKSIZE field.         */
44240   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH4MAXBLKSIZE field.         */
44241   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified)                           */
44242   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified)                           */
44243   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified)                          */
44244   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified)                          */
44245   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified)                          */
44246   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified)                         */
44247   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified)                         */
44248   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified)                         */
44249   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified)                        */
44250   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified)                        */
44251   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH4MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified)                        */
44252 
44253 /* CH5MAXBLKSIZE @Bits 20..23 : The values of these bit fields are derived from the DMAH_CH5_MAX_BLK_SIZE coreConsultant
44254                                 parameter. */
44255 
44256   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Pos (20UL) /*!< Position of CH5MAXBLKSIZE field.                      */
44257   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Pos) /*!<
44258                                                                             Bit mask of CH5MAXBLKSIZE field.*/
44259   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH5MAXBLKSIZE field.         */
44260   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH5MAXBLKSIZE field.         */
44261   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified)                           */
44262   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified)                           */
44263   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified)                          */
44264   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified)                          */
44265   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified)                          */
44266   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified)                         */
44267   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified)                         */
44268   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified)                         */
44269   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified)                        */
44270   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified)                        */
44271   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH5MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified)                        */
44272 
44273 /* CH6MAXBLKSIZE @Bits 24..27 : The values of these bit fields are derived from the DMAH_CH6_MAX_BLK_SIZE coreConsultant
44274                                 parameter. */
44275 
44276   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Pos (24UL) /*!< Position of CH6MAXBLKSIZE field.                      */
44277   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Pos) /*!<
44278                                                                             Bit mask of CH6MAXBLKSIZE field.*/
44279   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH6MAXBLKSIZE field.         */
44280   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH6MAXBLKSIZE field.         */
44281   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified)                           */
44282   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified)                           */
44283   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified)                          */
44284   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified)                          */
44285   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified)                          */
44286   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified)                         */
44287   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified)                         */
44288   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified)                         */
44289   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified)                        */
44290   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified)                        */
44291   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH6MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified)                        */
44292 
44293 /* CH7MAXBLKSIZE @Bits 28..31 : The values of these bit fields are derived from the DMAH_CH7_MAX_BLK_SIZE coreConsultant
44294                                 parameter. */
44295 
44296   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Pos (28UL) /*!< Position of CH7MAXBLKSIZE field.                      */
44297   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Pos) /*!<
44298                                                                             Bit mask of CH7MAXBLKSIZE field.*/
44299   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Min (0x0UL) /*!< Min enumerator value of CH7MAXBLKSIZE field.         */
44300   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_Max (0xAUL) /*!< Max enumerator value of CH7MAXBLKSIZE field.         */
44301   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_3 (0x0UL) /*!< (unspecified)                           */
44302   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_7 (0x1UL) /*!< (unspecified)                           */
44303   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_15 (0x2UL) /*!< (unspecified)                          */
44304   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_31 (0x3UL) /*!< (unspecified)                          */
44305   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_63 (0x4UL) /*!< (unspecified)                          */
44306   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_127 (0x5UL) /*!< (unspecified)                         */
44307   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_255 (0x6UL) /*!< (unspecified)                         */
44308   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_511 (0x7UL) /*!< (unspecified)                         */
44309   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_1023 (0x8UL) /*!< (unspecified)                        */
44310   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_2047 (0x9UL) /*!< (unspecified)                        */
44311   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1L_CH7MAXBLKSIZE_MAX_BLOCK_SIZE_4095 (0xAUL) /*!< (unspecified)                        */
44312 
44313 
44314 /* I3CCORE_DMA_MISC_DMACOMPPARAMS1H: DMA_COMP_PARAMS_1 is a constant read-only register that contains encoded information about
44315                                       the component parameter settings. */
44316 
44317   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ResetValue (0x3120090CUL) /*!< Reset value of DMACOMPPARAMS1H register.             */
44318 
44319 /* BIGENDIAN @Bit 0 : The value of this register is derived from the DMAH_BIG_ENDIAN coreConsultant parameter. */
44320   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Pos (0UL) /*!< Position of BIGENDIAN field.                               */
44321   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Pos) /*!< Bit mask
44322                                                                             of BIGENDIAN field.*/
44323   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Min (0x0UL) /*!< Min enumerator value of BIGENDIAN field.                 */
44324   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_Max (0x1UL) /*!< Max enumerator value of BIGENDIAN field.                 */
44325   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_FALSE (0x0UL) /*!< (unspecified)                                          */
44326   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_BIGENDIAN_TRUE (0x1UL) /*!< (unspecified)                                           */
44327 
44328 /* INTRIO @Bits 1..2 : The value of this register is derived from the DMAH_INTR_IO coreConsultant parameter. */
44329   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Pos (1UL) /*!< Position of INTRIO field.                                     */
44330   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Pos) /*!< Bit mask of
44331                                                                             INTRIO field.*/
44332   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Min (0x0UL) /*!< Min enumerator value of INTRIO field.                       */
44333   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_Max (0x2UL) /*!< Max enumerator value of INTRIO field.                       */
44334   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_ALL_INT (0x0UL) /*!< (unspecified)                                           */
44335   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_TYPE_INT (0x1UL) /*!< (unspecified)                                          */
44336   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_INTRIO_COMBINED_INT (0x2UL) /*!< (unspecified)                                      */
44337 
44338 /* MAXABRST @Bit 3 : The value of this register is derived from the DMAH_MABRST coreConsultant parameter. */
44339   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Pos (3UL) /*!< Position of MAXABRST field.                                 */
44340   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Pos) /*!< Bit mask
44341                                                                             of MAXABRST field.*/
44342   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Min (0x0UL) /*!< Min enumerator value of MAXABRST field.                   */
44343   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_Max (0x1UL) /*!< Max enumerator value of MAXABRST field.                   */
44344   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_FALSE (0x0UL) /*!< (unspecified)                                           */
44345   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_MAXABRST_TRUE (0x1UL) /*!< (unspecified)                                            */
44346 
44347 /* RSVDDMACOMPPARAMS1 @Bits 4..7 : Reserved field- read-only */
44348   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_RSVDDMACOMPPARAMS1_Pos (4UL) /*!< Position of RSVDDMACOMPPARAMS1 field.             */
44349   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_RSVDDMACOMPPARAMS1_Msk (0xFUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_RSVDDMACOMPPARAMS1_Pos)
44350                                                                             /*!< Bit mask of RSVDDMACOMPPARAMS1 field.*/
44351 
44352 /* NUMCHANNELS @Bits 8..10 : The value of this register is derived from the DMAH_NUM_CHANNELS coreConsultant parameter. */
44353   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Pos (8UL) /*!< Position of NUMCHANNELS field.                           */
44354   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Msk (0x7UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Pos) /*!< Bit
44355                                                                             mask of NUMCHANNELS field.*/
44356   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Min (0x0UL) /*!< Min enumerator value of NUMCHANNELS field.             */
44357   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_Max (0x7UL) /*!< Max enumerator value of NUMCHANNELS field.             */
44358   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_1 (0x0UL) /*!< (unspecified)                                */
44359   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_2 (0x1UL) /*!< (unspecified)                                */
44360   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_3 (0x2UL) /*!< (unspecified)                                */
44361   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_4 (0x3UL) /*!< (unspecified)                                */
44362   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_5 (0x4UL) /*!< (unspecified)                                */
44363   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_6 (0x5UL) /*!< (unspecified)                                */
44364   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_7 (0x6UL) /*!< (unspecified)                                */
44365   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMCHANNELS_NUM_CHANNEL_8 (0x7UL) /*!< (unspecified)                                */
44366 
44367 /* NUMMASTERINT @Bits 11..12 : The value of this register is derived from the DMAH_NUM_MASTER_INT coreConsultant parameter. */
44368   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Pos (11UL) /*!< Position of NUMMASTERINT field.                        */
44369   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Pos) /*!<
44370                                                                             Bit mask of NUMMASTERINT field.*/
44371   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Min (0x0UL) /*!< Min enumerator value of NUMMASTERINT field.           */
44372   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_Max (0x3UL) /*!< Max enumerator value of NUMMASTERINT field.           */
44373   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_NUM_MST_INTERFACE_1 (0x0UL) /*!< (unspecified)                         */
44374   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_NUM_MST_INTERFACE_2 (0x1UL) /*!< (unspecified)                         */
44375   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_NUM_MST_INTERFACE_3 (0x2UL) /*!< (unspecified)                         */
44376   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMMASTERINT_NUM_MST_INTERFACE_4 (0x3UL) /*!< (unspecified)                         */
44377 
44378 /* SHDATAWIDTH @Bits 13..14 : The value of this register is derived from the DMAH_S_HDATA_WIDTH coreConsultant parameter. */
44379   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Pos (13UL) /*!< Position of SHDATAWIDTH field.                          */
44380   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Pos) /*!< Bit
44381                                                                             mask of SHDATAWIDTH field.*/
44382   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of SHDATAWIDTH field.             */
44383   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of SHDATAWIDTH field.             */
44384   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified)                            */
44385   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified)                            */
44386   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified)                           */
44387   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_SHDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified)                           */
44388 
44389 /* M4HDATAWIDTH @Bits 15..16 : The value of this register is derived from the DMAH_M4_HDATA_WIDTH coreConsultant parameter. */
44390   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Pos (15UL) /*!< Position of M4HDATAWIDTH field.                        */
44391   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Pos) /*!<
44392                                                                             Bit mask of M4HDATAWIDTH field.*/
44393   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of M4HDATAWIDTH field.           */
44394   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of M4HDATAWIDTH field.           */
44395   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified)                           */
44396   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified)                           */
44397   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified)                          */
44398   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M4HDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified)                          */
44399 
44400 /* M3HDATAWIDTH @Bits 17..18 : The value of this register is derived from the DMAH_M3_HDATA_WIDTH coreConsultant parameter. */
44401   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Pos (17UL) /*!< Position of M3HDATAWIDTH field.                        */
44402   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Pos) /*!<
44403                                                                             Bit mask of M3HDATAWIDTH field.*/
44404   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of M3HDATAWIDTH field.           */
44405   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of M3HDATAWIDTH field.           */
44406   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified)                           */
44407   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified)                           */
44408   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified)                          */
44409   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M3HDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified)                          */
44410 
44411 /* M2HDATAWIDTH @Bits 19..20 : The value of this register is derived from the DMAH_M2_HDATA_WIDTH coreConsultant parameter. */
44412   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Pos (19UL) /*!< Position of M2HDATAWIDTH field.                        */
44413   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Pos) /*!<
44414                                                                             Bit mask of M2HDATAWIDTH field.*/
44415   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of M2HDATAWIDTH field.           */
44416   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of M2HDATAWIDTH field.           */
44417   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified)                           */
44418   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified)                           */
44419   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified)                          */
44420   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M2HDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified)                          */
44421 
44422 /* M1HDATAWIDTH @Bits 21..22 : The value of this register is derived from the DMAH_M1_HDATA_WIDTH coreConsultant parameter. */
44423   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Pos (21UL) /*!< Position of M1HDATAWIDTH field.                        */
44424   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Msk (0x3UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Pos) /*!<
44425                                                                             Bit mask of M1HDATAWIDTH field.*/
44426   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of M1HDATAWIDTH field.           */
44427   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_Max (0x3UL) /*!< Max enumerator value of M1HDATAWIDTH field.           */
44428   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_DATA_BUS_WIDTH_32 (0x0UL) /*!< (unspecified)                           */
44429   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_DATA_BUS_WIDTH_64 (0x1UL) /*!< (unspecified)                           */
44430   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_DATA_BUS_WIDTH_128 (0x2UL) /*!< (unspecified)                          */
44431   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_M1HDATAWIDTH_DATA_BUS_WIDTH_256 (0x3UL) /*!< (unspecified)                          */
44432 
44433 /* NUMHSINT @Bits 23..27 : The value of this register is derived from the DMAH_NUM_HS_INT coreConsultant parameter. */
44434   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Pos (23UL) /*!< Position of NUMHSINT field.                                */
44435   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Msk (0x1FUL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Pos) /*!< Bit mask
44436                                                                             of NUMHSINT field.*/
44437   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Min (0x0UL) /*!< Min enumerator value of NUMHSINT field.                   */
44438   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_Max (0x10UL) /*!< Max enumerator value of NUMHSINT field.                  */
44439   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_0 (0x00UL) /*!< (unspecified)                                 */
44440   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_1 (0x01UL) /*!< (unspecified)                                 */
44441   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_2 (0x02UL) /*!< (unspecified)                                 */
44442   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_3 (0x03UL) /*!< (unspecified)                                 */
44443   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_4 (0x04UL) /*!< (unspecified)                                 */
44444   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_5 (0x05UL) /*!< (unspecified)                                 */
44445   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_6 (0x06UL) /*!< (unspecified)                                 */
44446   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_7 (0x07UL) /*!< (unspecified)                                 */
44447   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_8 (0x08UL) /*!< (unspecified)                                 */
44448   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_9 (0x09UL) /*!< (unspecified)                                 */
44449   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_a (0x0AUL) /*!< (unspecified)                                 */
44450   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_b (0x0BUL) /*!< (unspecified)                                 */
44451   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_c (0x0CUL) /*!< (unspecified)                                 */
44452   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_d (0x0DUL) /*!< (unspecified)                                 */
44453   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_e (0x0EUL) /*!< (unspecified)                                 */
44454   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_f (0x0FUL) /*!< (unspecified)                                 */
44455   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_NUMHSINT_HS_INTERFACE_10 (0x10UL) /*!< (unspecified)                                */
44456 
44457 /* ADDENCODEDPARAMS @Bit 28 : The value of this register is derived from the DMAH_ADD_ENCODED_PARAMS coreConsultant parameter. */
44458   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Pos (28UL) /*!< Position of ADDENCODEDPARAMS field.                */
44459   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Pos)
44460                                                                             /*!< Bit mask of ADDENCODEDPARAMS field.*/
44461   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Min (0x0UL) /*!< Min enumerator value of ADDENCODEDPARAMS field.   */
44462   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_Max (0x1UL) /*!< Max enumerator value of ADDENCODEDPARAMS field.   */
44463   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_FALSE (0x0UL) /*!< (unspecified)                                   */
44464   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_ADDENCODEDPARAMS_TRUE (0x1UL) /*!< (unspecified)                                    */
44465 
44466 /* STATICENDIANSELECT @Bit 29 : The value of this register is derived from the DMAH_STATIC_ENDIAN_SELECT coreConsultant
44467                                 parameter. */
44468 
44469   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_STATICENDIANSELECT_Pos (29UL) /*!< Position of STATICENDIANSELECT field.            */
44470   #define I3CCORE_DMA_MISC_DMACOMPPARAMS1H_STATICENDIANSELECT_Msk (0x1UL << I3CCORE_DMA_MISC_DMACOMPPARAMS1H_STATICENDIANSELECT_Pos)
44471                                                                             /*!< Bit mask of STATICENDIANSELECT field.*/
44472 
44473 
44474 /* I3CCORE_DMA_MISC_DMACOMPSID0: This is the DW_ahb_dmac Component Version register, which is a read-only register that
44475                                   specifies the component type. */
44476 
44477   #define I3CCORE_DMA_MISC_DMACOMPSID0_ResetValue (0x44571110UL) /*!< Reset value of DMACOMPSID0 register.                     */
44478 
44479 /* DMACOMPTYPE @Bits 0..31 : DMA Component Type Number = `h44571110. */
44480   #define I3CCORE_DMA_MISC_DMACOMPSID0_DMACOMPTYPE_Pos (0UL) /*!< Position of DMACOMPTYPE field.                               */
44481   #define I3CCORE_DMA_MISC_DMACOMPSID0_DMACOMPTYPE_Msk (0xFFFFFFFFUL << I3CCORE_DMA_MISC_DMACOMPSID0_DMACOMPTYPE_Pos) /*!< Bit
44482                                                                             mask of DMACOMPTYPE field.*/
44483 
44484 
44485 /* I3CCORE_DMA_MISC_DMACOMPSID1: This is the DW_ahb_dmac Component Version register, which is a read-only register that
44486                                   specifies the version of the packaged component. */
44487 
44488   #define I3CCORE_DMA_MISC_DMACOMPSID1_ResetValue (0x3232322AUL) /*!< Reset value of DMACOMPSID1 register.                     */
44489 
44490 /* DMACOMPVERSION @Bits 0..31 : DMA Component Version. */
44491   #define I3CCORE_DMA_MISC_DMACOMPSID1_DMACOMPVERSION_Pos (0UL) /*!< Position of DMACOMPVERSION field.                         */
44492   #define I3CCORE_DMA_MISC_DMACOMPSID1_DMACOMPVERSION_Msk (0xFFFFFFFFUL << I3CCORE_DMA_MISC_DMACOMPSID1_DMACOMPVERSION_Pos) /*!<
44493                                                                             Bit mask of DMACOMPVERSION field.*/
44494 
44495 
44496 
44497 /* =================================================== Struct I3CCORE_DMA ==================================================== */
44498 /**
44499   * @brief DMA [I3CCORE_DMA] (unspecified)
44500   */
44501 typedef struct {
44502   __IOM NRF_I3CCORE_DMA_CH0_Type CH0;                /*!< (@ 0x00000000) (unspecified)                                         */
44503   __IM  uint32_t  RESERVED;
44504   __IOM NRF_I3CCORE_DMA_CH1_Type CH1;                /*!< (@ 0x00000058) (unspecified)                                         */
44505   __IM  uint32_t  RESERVED1[135];
44506   __IOM NRF_I3CCORE_DMA_INT_Type INT;                /*!< (@ 0x000002C0) (unspecified)                                         */
44507   __IM  uint32_t  RESERVED2;
44508   __IOM NRF_I3CCORE_DMA_SWHANDSHAKE_Type SWHANDSHAKE; /*!< (@ 0x00000368) (unspecified)                                        */
44509   __IM  uint32_t  RESERVED3;
44510   __IOM NRF_I3CCORE_DMA_MISC_Type MISC;              /*!< (@ 0x00000398) (unspecified)                                         */
44511 } NRF_I3CCORE_DMA_Type;                              /*!< Size = 1024 (0x400)                                                  */
44512 
44513 /* ===================================================== Struct I3CCORE ====================================================== */
44514 /**
44515   * @brief I3CCORE
44516   */
44517   typedef struct {                                   /*!< I3CCORE Structure                                                    */
44518     __IOM NRF_I3CCORE_CORE_Type CORE;                /*!< (@ 0x00000000) (unspecified)                                         */
44519     __IM uint32_t RESERVED[390];
44520     __IOM NRF_I3CCORE_DMA_Type DMA;                  /*!< (@ 0x00000900) (unspecified)                                         */
44521   } NRF_I3CCORE_Type;                                /*!< Size = 3328 (0xD00)                                                  */
44522 
44523 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
44524 
44525 /* =========================================================================================================================== */
44526 /* ================                                           IPCT                                           ================ */
44527 /* =========================================================================================================================== */
44528 
44529 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
44530 
44531 /* ================================================== Struct IPCT_OVERFLOW =================================================== */
44532 /**
44533   * @brief OVERFLOW [IPCT_OVERFLOW] (unspecified)
44534   */
44535 typedef struct {
44536   __IOM uint32_t  SEND;                              /*!< (@ 0x00000000) Overflow status for SEND tasks Write 0 to clear       */
44537 } NRF_IPCT_OVERFLOW_Type;                            /*!< Size = 4 (0x004)                                                     */
44538 
44539 /* IPCT_OVERFLOW_SEND: Overflow status for SEND tasks Write 0 to clear */
44540   #define IPCT_OVERFLOW_SEND_ResetValue (0x00000000UL) /*!< Reset value of SEND register.                                      */
44541 
44542 /* SEND0 @Bit 0 : Overflow status for SEND[0] task */
44543   #define IPCT_OVERFLOW_SEND_SEND0_Pos (0UL)         /*!< Position of SEND0 field.                                             */
44544   #define IPCT_OVERFLOW_SEND_SEND0_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND0_Pos) /*!< Bit mask of SEND0 field.                   */
44545   #define IPCT_OVERFLOW_SEND_SEND0_Min (0x0UL)       /*!< Min enumerator value of SEND0 field.                                 */
44546   #define IPCT_OVERFLOW_SEND_SEND0_Max (0x1UL)       /*!< Max enumerator value of SEND0 field.                                 */
44547   #define IPCT_OVERFLOW_SEND_SEND0_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44548   #define IPCT_OVERFLOW_SEND_SEND0_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44549 
44550 /* SEND1 @Bit 1 : Overflow status for SEND[1] task */
44551   #define IPCT_OVERFLOW_SEND_SEND1_Pos (1UL)         /*!< Position of SEND1 field.                                             */
44552   #define IPCT_OVERFLOW_SEND_SEND1_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND1_Pos) /*!< Bit mask of SEND1 field.                   */
44553   #define IPCT_OVERFLOW_SEND_SEND1_Min (0x0UL)       /*!< Min enumerator value of SEND1 field.                                 */
44554   #define IPCT_OVERFLOW_SEND_SEND1_Max (0x1UL)       /*!< Max enumerator value of SEND1 field.                                 */
44555   #define IPCT_OVERFLOW_SEND_SEND1_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44556   #define IPCT_OVERFLOW_SEND_SEND1_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44557 
44558 /* SEND2 @Bit 2 : Overflow status for SEND[2] task */
44559   #define IPCT_OVERFLOW_SEND_SEND2_Pos (2UL)         /*!< Position of SEND2 field.                                             */
44560   #define IPCT_OVERFLOW_SEND_SEND2_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND2_Pos) /*!< Bit mask of SEND2 field.                   */
44561   #define IPCT_OVERFLOW_SEND_SEND2_Min (0x0UL)       /*!< Min enumerator value of SEND2 field.                                 */
44562   #define IPCT_OVERFLOW_SEND_SEND2_Max (0x1UL)       /*!< Max enumerator value of SEND2 field.                                 */
44563   #define IPCT_OVERFLOW_SEND_SEND2_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44564   #define IPCT_OVERFLOW_SEND_SEND2_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44565 
44566 /* SEND3 @Bit 3 : Overflow status for SEND[3] task */
44567   #define IPCT_OVERFLOW_SEND_SEND3_Pos (3UL)         /*!< Position of SEND3 field.                                             */
44568   #define IPCT_OVERFLOW_SEND_SEND3_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND3_Pos) /*!< Bit mask of SEND3 field.                   */
44569   #define IPCT_OVERFLOW_SEND_SEND3_Min (0x0UL)       /*!< Min enumerator value of SEND3 field.                                 */
44570   #define IPCT_OVERFLOW_SEND_SEND3_Max (0x1UL)       /*!< Max enumerator value of SEND3 field.                                 */
44571   #define IPCT_OVERFLOW_SEND_SEND3_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44572   #define IPCT_OVERFLOW_SEND_SEND3_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44573 
44574 /* SEND4 @Bit 4 : Overflow status for SEND[4] task */
44575   #define IPCT_OVERFLOW_SEND_SEND4_Pos (4UL)         /*!< Position of SEND4 field.                                             */
44576   #define IPCT_OVERFLOW_SEND_SEND4_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND4_Pos) /*!< Bit mask of SEND4 field.                   */
44577   #define IPCT_OVERFLOW_SEND_SEND4_Min (0x0UL)       /*!< Min enumerator value of SEND4 field.                                 */
44578   #define IPCT_OVERFLOW_SEND_SEND4_Max (0x1UL)       /*!< Max enumerator value of SEND4 field.                                 */
44579   #define IPCT_OVERFLOW_SEND_SEND4_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44580   #define IPCT_OVERFLOW_SEND_SEND4_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44581 
44582 /* SEND5 @Bit 5 : Overflow status for SEND[5] task */
44583   #define IPCT_OVERFLOW_SEND_SEND5_Pos (5UL)         /*!< Position of SEND5 field.                                             */
44584   #define IPCT_OVERFLOW_SEND_SEND5_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND5_Pos) /*!< Bit mask of SEND5 field.                   */
44585   #define IPCT_OVERFLOW_SEND_SEND5_Min (0x0UL)       /*!< Min enumerator value of SEND5 field.                                 */
44586   #define IPCT_OVERFLOW_SEND_SEND5_Max (0x1UL)       /*!< Max enumerator value of SEND5 field.                                 */
44587   #define IPCT_OVERFLOW_SEND_SEND5_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44588   #define IPCT_OVERFLOW_SEND_SEND5_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44589 
44590 /* SEND6 @Bit 6 : Overflow status for SEND[6] task */
44591   #define IPCT_OVERFLOW_SEND_SEND6_Pos (6UL)         /*!< Position of SEND6 field.                                             */
44592   #define IPCT_OVERFLOW_SEND_SEND6_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND6_Pos) /*!< Bit mask of SEND6 field.                   */
44593   #define IPCT_OVERFLOW_SEND_SEND6_Min (0x0UL)       /*!< Min enumerator value of SEND6 field.                                 */
44594   #define IPCT_OVERFLOW_SEND_SEND6_Max (0x1UL)       /*!< Max enumerator value of SEND6 field.                                 */
44595   #define IPCT_OVERFLOW_SEND_SEND6_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44596   #define IPCT_OVERFLOW_SEND_SEND6_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44597 
44598 /* SEND7 @Bit 7 : Overflow status for SEND[7] task */
44599   #define IPCT_OVERFLOW_SEND_SEND7_Pos (7UL)         /*!< Position of SEND7 field.                                             */
44600   #define IPCT_OVERFLOW_SEND_SEND7_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND7_Pos) /*!< Bit mask of SEND7 field.                   */
44601   #define IPCT_OVERFLOW_SEND_SEND7_Min (0x0UL)       /*!< Min enumerator value of SEND7 field.                                 */
44602   #define IPCT_OVERFLOW_SEND_SEND7_Max (0x1UL)       /*!< Max enumerator value of SEND7 field.                                 */
44603   #define IPCT_OVERFLOW_SEND_SEND7_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44604   #define IPCT_OVERFLOW_SEND_SEND7_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44605 
44606 /* SEND8 @Bit 8 : Overflow status for SEND[8] task */
44607   #define IPCT_OVERFLOW_SEND_SEND8_Pos (8UL)         /*!< Position of SEND8 field.                                             */
44608   #define IPCT_OVERFLOW_SEND_SEND8_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND8_Pos) /*!< Bit mask of SEND8 field.                   */
44609   #define IPCT_OVERFLOW_SEND_SEND8_Min (0x0UL)       /*!< Min enumerator value of SEND8 field.                                 */
44610   #define IPCT_OVERFLOW_SEND_SEND8_Max (0x1UL)       /*!< Max enumerator value of SEND8 field.                                 */
44611   #define IPCT_OVERFLOW_SEND_SEND8_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44612   #define IPCT_OVERFLOW_SEND_SEND8_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44613 
44614 /* SEND9 @Bit 9 : Overflow status for SEND[9] task */
44615   #define IPCT_OVERFLOW_SEND_SEND9_Pos (9UL)         /*!< Position of SEND9 field.                                             */
44616   #define IPCT_OVERFLOW_SEND_SEND9_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND9_Pos) /*!< Bit mask of SEND9 field.                   */
44617   #define IPCT_OVERFLOW_SEND_SEND9_Min (0x0UL)       /*!< Min enumerator value of SEND9 field.                                 */
44618   #define IPCT_OVERFLOW_SEND_SEND9_Max (0x1UL)       /*!< Max enumerator value of SEND9 field.                                 */
44619   #define IPCT_OVERFLOW_SEND_SEND9_Overflow (0x1UL)  /*!< Task overflow has happened                                           */
44620   #define IPCT_OVERFLOW_SEND_SEND9_NoOverflow (0x0UL) /*!< Task overflow has not happened                                      */
44621 
44622 /* SEND10 @Bit 10 : Overflow status for SEND[10] task */
44623   #define IPCT_OVERFLOW_SEND_SEND10_Pos (10UL)       /*!< Position of SEND10 field.                                            */
44624   #define IPCT_OVERFLOW_SEND_SEND10_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND10_Pos) /*!< Bit mask of SEND10 field.                */
44625   #define IPCT_OVERFLOW_SEND_SEND10_Min (0x0UL)      /*!< Min enumerator value of SEND10 field.                                */
44626   #define IPCT_OVERFLOW_SEND_SEND10_Max (0x1UL)      /*!< Max enumerator value of SEND10 field.                                */
44627   #define IPCT_OVERFLOW_SEND_SEND10_Overflow (0x1UL) /*!< Task overflow has happened                                           */
44628   #define IPCT_OVERFLOW_SEND_SEND10_NoOverflow (0x0UL) /*!< Task overflow has not happened                                     */
44629 
44630 /* SEND11 @Bit 11 : Overflow status for SEND[11] task */
44631   #define IPCT_OVERFLOW_SEND_SEND11_Pos (11UL)       /*!< Position of SEND11 field.                                            */
44632   #define IPCT_OVERFLOW_SEND_SEND11_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND11_Pos) /*!< Bit mask of SEND11 field.                */
44633   #define IPCT_OVERFLOW_SEND_SEND11_Min (0x0UL)      /*!< Min enumerator value of SEND11 field.                                */
44634   #define IPCT_OVERFLOW_SEND_SEND11_Max (0x1UL)      /*!< Max enumerator value of SEND11 field.                                */
44635   #define IPCT_OVERFLOW_SEND_SEND11_Overflow (0x1UL) /*!< Task overflow has happened                                           */
44636   #define IPCT_OVERFLOW_SEND_SEND11_NoOverflow (0x0UL) /*!< Task overflow has not happened                                     */
44637 
44638 /* SEND12 @Bit 12 : Overflow status for SEND[12] task */
44639   #define IPCT_OVERFLOW_SEND_SEND12_Pos (12UL)       /*!< Position of SEND12 field.                                            */
44640   #define IPCT_OVERFLOW_SEND_SEND12_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND12_Pos) /*!< Bit mask of SEND12 field.                */
44641   #define IPCT_OVERFLOW_SEND_SEND12_Min (0x0UL)      /*!< Min enumerator value of SEND12 field.                                */
44642   #define IPCT_OVERFLOW_SEND_SEND12_Max (0x1UL)      /*!< Max enumerator value of SEND12 field.                                */
44643   #define IPCT_OVERFLOW_SEND_SEND12_Overflow (0x1UL) /*!< Task overflow has happened                                           */
44644   #define IPCT_OVERFLOW_SEND_SEND12_NoOverflow (0x0UL) /*!< Task overflow has not happened                                     */
44645 
44646 /* SEND13 @Bit 13 : Overflow status for SEND[13] task */
44647   #define IPCT_OVERFLOW_SEND_SEND13_Pos (13UL)       /*!< Position of SEND13 field.                                            */
44648   #define IPCT_OVERFLOW_SEND_SEND13_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND13_Pos) /*!< Bit mask of SEND13 field.                */
44649   #define IPCT_OVERFLOW_SEND_SEND13_Min (0x0UL)      /*!< Min enumerator value of SEND13 field.                                */
44650   #define IPCT_OVERFLOW_SEND_SEND13_Max (0x1UL)      /*!< Max enumerator value of SEND13 field.                                */
44651   #define IPCT_OVERFLOW_SEND_SEND13_Overflow (0x1UL) /*!< Task overflow has happened                                           */
44652   #define IPCT_OVERFLOW_SEND_SEND13_NoOverflow (0x0UL) /*!< Task overflow has not happened                                     */
44653 
44654 /* SEND14 @Bit 14 : Overflow status for SEND[14] task */
44655   #define IPCT_OVERFLOW_SEND_SEND14_Pos (14UL)       /*!< Position of SEND14 field.                                            */
44656   #define IPCT_OVERFLOW_SEND_SEND14_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND14_Pos) /*!< Bit mask of SEND14 field.                */
44657   #define IPCT_OVERFLOW_SEND_SEND14_Min (0x0UL)      /*!< Min enumerator value of SEND14 field.                                */
44658   #define IPCT_OVERFLOW_SEND_SEND14_Max (0x1UL)      /*!< Max enumerator value of SEND14 field.                                */
44659   #define IPCT_OVERFLOW_SEND_SEND14_Overflow (0x1UL) /*!< Task overflow has happened                                           */
44660   #define IPCT_OVERFLOW_SEND_SEND14_NoOverflow (0x0UL) /*!< Task overflow has not happened                                     */
44661 
44662 /* SEND15 @Bit 15 : Overflow status for SEND[15] task */
44663   #define IPCT_OVERFLOW_SEND_SEND15_Pos (15UL)       /*!< Position of SEND15 field.                                            */
44664   #define IPCT_OVERFLOW_SEND_SEND15_Msk (0x1UL << IPCT_OVERFLOW_SEND_SEND15_Pos) /*!< Bit mask of SEND15 field.                */
44665   #define IPCT_OVERFLOW_SEND_SEND15_Min (0x0UL)      /*!< Min enumerator value of SEND15 field.                                */
44666   #define IPCT_OVERFLOW_SEND_SEND15_Max (0x1UL)      /*!< Max enumerator value of SEND15 field.                                */
44667   #define IPCT_OVERFLOW_SEND_SEND15_Overflow (0x1UL) /*!< Task overflow has happened                                           */
44668   #define IPCT_OVERFLOW_SEND_SEND15_NoOverflow (0x0UL) /*!< Task overflow has not happened                                     */
44669 
44670 
44671 /* ======================================================= Struct IPCT ======================================================= */
44672 /**
44673   * @brief IPCT APB registers
44674   */
44675   typedef struct {                                   /*!< IPCT Structure                                                       */
44676     __OM uint32_t TASKS_SEND[16];                    /*!< (@ 0x00000000) Trigger event on IPCT source channel n if there are no
44677                                                                          active signals present on that channel*/
44678     __OM uint32_t TASKS_ACK[16];                     /*!< (@ 0x00000040) Flush IPCT sink channel n. Any pending IPCT signal on
44679                                                                          that channel will re-trigger the RECEIVE[n] event. The
44680                                                                          flush can happen automatically by configuring the
44681                                                                          SHORTS register accordingly.*/
44682     __IOM uint32_t SUBSCRIBE_SEND[16];               /*!< (@ 0x00000080) Subscribe configuration for task SEND[n]              */
44683     __IOM uint32_t SUBSCRIBE_ACK[16];                /*!< (@ 0x000000C0) Subscribe configuration for task ACK[n]               */
44684     __IOM uint32_t EVENTS_RECEIVE[16];               /*!< (@ 0x00000100) Event received on IPCT sink channel n                 */
44685     __IOM uint32_t EVENTS_ACKED[16];                 /*!< (@ 0x00000140) Event received when hardware handshake of SEND task for
44686                                                                          IPCT source channel n is complete and a new signal can
44687                                                                          be triggered on that channel.*/
44688     __IOM uint32_t PUBLISH_RECEIVE[16];              /*!< (@ 0x00000180) Publish configuration for event RECEIVE[n]            */
44689     __IOM uint32_t PUBLISH_ACKED[16];                /*!< (@ 0x000001C0) Publish configuration for event ACKED[n]              */
44690     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
44691     __IM uint32_t RESERVED[63];
44692     __IOM uint32_t INTEN0;                           /*!< (@ 0x00000300) Enable or disable interrupt                           */
44693     __IOM uint32_t INTENSET0;                        /*!< (@ 0x00000304) Enable interrupt                                      */
44694     __IOM uint32_t INTENCLR0;                        /*!< (@ 0x00000308) Disable interrupt                                     */
44695     __IM uint32_t INTPEND0;                          /*!< (@ 0x0000030C) Pending interrupts                                    */
44696     __IOM uint32_t INTEN1;                           /*!< (@ 0x00000310) Enable or disable interrupt                           */
44697     __IOM uint32_t INTENSET1;                        /*!< (@ 0x00000314) Enable interrupt                                      */
44698     __IOM uint32_t INTENCLR1;                        /*!< (@ 0x00000318) Disable interrupt                                     */
44699     __IM uint32_t INTPEND1;                          /*!< (@ 0x0000031C) Pending interrupts                                    */
44700     __IOM uint32_t INTEN2;                           /*!< (@ 0x00000320) Enable or disable interrupt                           */
44701     __IOM uint32_t INTENSET2;                        /*!< (@ 0x00000324) Enable interrupt                                      */
44702     __IOM uint32_t INTENCLR2;                        /*!< (@ 0x00000328) Disable interrupt                                     */
44703     __IM uint32_t INTPEND2;                          /*!< (@ 0x0000032C) Pending interrupts                                    */
44704     __IOM uint32_t INTEN3;                           /*!< (@ 0x00000330) Enable or disable interrupt                           */
44705     __IOM uint32_t INTENSET3;                        /*!< (@ 0x00000334) Enable interrupt                                      */
44706     __IOM uint32_t INTENCLR3;                        /*!< (@ 0x00000338) Disable interrupt                                     */
44707     __IM uint32_t INTPEND3;                          /*!< (@ 0x0000033C) Pending interrupts                                    */
44708     __IOM uint32_t INTEN4;                           /*!< (@ 0x00000340) Enable or disable interrupt                           */
44709     __IOM uint32_t INTENSET4;                        /*!< (@ 0x00000344) Enable interrupt                                      */
44710     __IOM uint32_t INTENCLR4;                        /*!< (@ 0x00000348) Disable interrupt                                     */
44711     __IM uint32_t INTPEND4;                          /*!< (@ 0x0000034C) Pending interrupts                                    */
44712     __IOM uint32_t INTEN5;                           /*!< (@ 0x00000350) Enable or disable interrupt                           */
44713     __IOM uint32_t INTENSET5;                        /*!< (@ 0x00000354) Enable interrupt                                      */
44714     __IOM uint32_t INTENCLR5;                        /*!< (@ 0x00000358) Disable interrupt                                     */
44715     __IM uint32_t INTPEND5;                          /*!< (@ 0x0000035C) Pending interrupts                                    */
44716     __IOM uint32_t INTEN6;                           /*!< (@ 0x00000360) Enable or disable interrupt                           */
44717     __IOM uint32_t INTENSET6;                        /*!< (@ 0x00000364) Enable interrupt                                      */
44718     __IOM uint32_t INTENCLR6;                        /*!< (@ 0x00000368) Disable interrupt                                     */
44719     __IM uint32_t INTPEND6;                          /*!< (@ 0x0000036C) Pending interrupts                                    */
44720     __IOM uint32_t INTEN7;                           /*!< (@ 0x00000370) Enable or disable interrupt                           */
44721     __IOM uint32_t INTENSET7;                        /*!< (@ 0x00000374) Enable interrupt                                      */
44722     __IOM uint32_t INTENCLR7;                        /*!< (@ 0x00000378) Disable interrupt                                     */
44723     __IM uint32_t INTPEND7;                          /*!< (@ 0x0000037C) Pending interrupts                                    */
44724     __IM uint32_t RESERVED1[32];
44725     __IOM NRF_IPCT_OVERFLOW_Type OVERFLOW;           /*!< (@ 0x00000400) (unspecified)                                         */
44726   } NRF_IPCT_Type;                                   /*!< Size = 1028 (0x404)                                                  */
44727 
44728 /* IPCT_TASKS_SEND: Trigger event on IPCT source channel n if there are no active signals present on that channel */
44729   #define IPCT_TASKS_SEND_MaxCount (16UL)            /*!< Max size of TASKS_SEND[16] array.                                    */
44730   #define IPCT_TASKS_SEND_MaxIndex (15UL)            /*!< Max index of TASKS_SEND[16] array.                                   */
44731   #define IPCT_TASKS_SEND_MinIndex (0UL)             /*!< Min index of TASKS_SEND[16] array.                                   */
44732   #define IPCT_TASKS_SEND_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_SEND[16] register.                              */
44733 
44734 /* TASKS_SEND @Bit 0 : Trigger event on IPCT source channel n if there are no active signals present on that channel */
44735   #define IPCT_TASKS_SEND_TASKS_SEND_Pos (0UL)       /*!< Position of TASKS_SEND field.                                        */
44736   #define IPCT_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPCT_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field.          */
44737   #define IPCT_TASKS_SEND_TASKS_SEND_Min (0x1UL)     /*!< Min enumerator value of TASKS_SEND field.                            */
44738   #define IPCT_TASKS_SEND_TASKS_SEND_Max (0x1UL)     /*!< Max enumerator value of TASKS_SEND field.                            */
44739   #define IPCT_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task                                                         */
44740 
44741 
44742 /* IPCT_TASKS_ACK: Flush IPCT sink channel n. Any pending IPCT signal on that channel will re-trigger the RECEIVE[n] event. The
44743                     flush can happen automatically by configuring the SHORTS register accordingly. */
44744 
44745   #define IPCT_TASKS_ACK_MaxCount (16UL)             /*!< Max size of TASKS_ACK[16] array.                                     */
44746   #define IPCT_TASKS_ACK_MaxIndex (15UL)             /*!< Max index of TASKS_ACK[16] array.                                    */
44747   #define IPCT_TASKS_ACK_MinIndex (0UL)              /*!< Min index of TASKS_ACK[16] array.                                    */
44748   #define IPCT_TASKS_ACK_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_ACK[16] register.                               */
44749 
44750 /* TASKS_ACK @Bit 0 : Flush IPCT sink channel n. Any pending IPCT signal on that channel will re-trigger the RECEIVE[n] event.
44751                       The flush can happen automatically by configuring the SHORTS register accordingly. */
44752 
44753   #define IPCT_TASKS_ACK_TASKS_ACK_Pos (0UL)         /*!< Position of TASKS_ACK field.                                         */
44754   #define IPCT_TASKS_ACK_TASKS_ACK_Msk (0x1UL << IPCT_TASKS_ACK_TASKS_ACK_Pos) /*!< Bit mask of TASKS_ACK field.               */
44755   #define IPCT_TASKS_ACK_TASKS_ACK_Min (0x1UL)       /*!< Min enumerator value of TASKS_ACK field.                             */
44756   #define IPCT_TASKS_ACK_TASKS_ACK_Max (0x1UL)       /*!< Max enumerator value of TASKS_ACK field.                             */
44757   #define IPCT_TASKS_ACK_TASKS_ACK_Trigger (0x1UL)   /*!< Trigger task                                                         */
44758 
44759 
44760 /* IPCT_SUBSCRIBE_SEND: Subscribe configuration for task SEND[n] */
44761   #define IPCT_SUBSCRIBE_SEND_MaxCount (16UL)        /*!< Max size of SUBSCRIBE_SEND[16] array.                                */
44762   #define IPCT_SUBSCRIBE_SEND_MaxIndex (15UL)        /*!< Max index of SUBSCRIBE_SEND[16] array.                               */
44763   #define IPCT_SUBSCRIBE_SEND_MinIndex (0UL)         /*!< Min index of SUBSCRIBE_SEND[16] array.                               */
44764   #define IPCT_SUBSCRIBE_SEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SEND[16] register.                       */
44765 
44766 /* CHIDX @Bits 0..7 : DPPI channel that task SEND[n] will subscribe to */
44767   #define IPCT_SUBSCRIBE_SEND_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
44768   #define IPCT_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPCT_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
44769   #define IPCT_SUBSCRIBE_SEND_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
44770   #define IPCT_SUBSCRIBE_SEND_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
44771 
44772 /* EN @Bit 31 : (unspecified) */
44773   #define IPCT_SUBSCRIBE_SEND_EN_Pos (31UL)          /*!< Position of EN field.                                                */
44774   #define IPCT_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPCT_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field.                          */
44775   #define IPCT_SUBSCRIBE_SEND_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
44776   #define IPCT_SUBSCRIBE_SEND_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
44777   #define IPCT_SUBSCRIBE_SEND_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
44778   #define IPCT_SUBSCRIBE_SEND_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
44779 
44780 
44781 /* IPCT_SUBSCRIBE_ACK: Subscribe configuration for task ACK[n] */
44782   #define IPCT_SUBSCRIBE_ACK_MaxCount (16UL)         /*!< Max size of SUBSCRIBE_ACK[16] array.                                 */
44783   #define IPCT_SUBSCRIBE_ACK_MaxIndex (15UL)         /*!< Max index of SUBSCRIBE_ACK[16] array.                                */
44784   #define IPCT_SUBSCRIBE_ACK_MinIndex (0UL)          /*!< Min index of SUBSCRIBE_ACK[16] array.                                */
44785   #define IPCT_SUBSCRIBE_ACK_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ACK[16] register.                         */
44786 
44787 /* CHIDX @Bits 0..7 : DPPI channel that task ACK[n] will subscribe to */
44788   #define IPCT_SUBSCRIBE_ACK_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
44789   #define IPCT_SUBSCRIBE_ACK_CHIDX_Msk (0xFFUL << IPCT_SUBSCRIBE_ACK_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
44790   #define IPCT_SUBSCRIBE_ACK_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
44791   #define IPCT_SUBSCRIBE_ACK_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
44792 
44793 /* EN @Bit 31 : (unspecified) */
44794   #define IPCT_SUBSCRIBE_ACK_EN_Pos (31UL)           /*!< Position of EN field.                                                */
44795   #define IPCT_SUBSCRIBE_ACK_EN_Msk (0x1UL << IPCT_SUBSCRIBE_ACK_EN_Pos) /*!< Bit mask of EN field.                            */
44796   #define IPCT_SUBSCRIBE_ACK_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
44797   #define IPCT_SUBSCRIBE_ACK_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
44798   #define IPCT_SUBSCRIBE_ACK_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
44799   #define IPCT_SUBSCRIBE_ACK_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
44800 
44801 
44802 /* IPCT_EVENTS_RECEIVE: Event received on IPCT sink channel n */
44803   #define IPCT_EVENTS_RECEIVE_MaxCount (16UL)        /*!< Max size of EVENTS_RECEIVE[16] array.                                */
44804   #define IPCT_EVENTS_RECEIVE_MaxIndex (15UL)        /*!< Max index of EVENTS_RECEIVE[16] array.                               */
44805   #define IPCT_EVENTS_RECEIVE_MinIndex (0UL)         /*!< Min index of EVENTS_RECEIVE[16] array.                               */
44806   #define IPCT_EVENTS_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RECEIVE[16] register.                       */
44807 
44808 /* EVENTS_RECEIVE @Bit 0 : Event received on IPCT sink channel n */
44809   #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field.                                  */
44810   #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of
44811                                                                             EVENTS_RECEIVE field.*/
44812   #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RECEIVE field.                    */
44813   #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RECEIVE field.                    */
44814   #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated                                     */
44815   #define IPCT_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated                                            */
44816 
44817 
44818 /* IPCT_EVENTS_ACKED: Event received when hardware handshake of SEND task for IPCT source channel n is complete and a new signal
44819                        can be triggered on that channel. */
44820 
44821   #define IPCT_EVENTS_ACKED_MaxCount (16UL)          /*!< Max size of EVENTS_ACKED[16] array.                                  */
44822   #define IPCT_EVENTS_ACKED_MaxIndex (15UL)          /*!< Max index of EVENTS_ACKED[16] array.                                 */
44823   #define IPCT_EVENTS_ACKED_MinIndex (0UL)           /*!< Min index of EVENTS_ACKED[16] array.                                 */
44824   #define IPCT_EVENTS_ACKED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACKED[16] register.                           */
44825 
44826 /* EVENTS_ACKED @Bit 0 : Event received when hardware handshake of SEND task for IPCT source channel n is complete and a new
44827                          signal can be triggered on that channel. */
44828 
44829   #define IPCT_EVENTS_ACKED_EVENTS_ACKED_Pos (0UL)   /*!< Position of EVENTS_ACKED field.                                      */
44830   #define IPCT_EVENTS_ACKED_EVENTS_ACKED_Msk (0x1UL << IPCT_EVENTS_ACKED_EVENTS_ACKED_Pos) /*!< Bit mask of EVENTS_ACKED field.*/
44831   #define IPCT_EVENTS_ACKED_EVENTS_ACKED_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACKED field.                          */
44832   #define IPCT_EVENTS_ACKED_EVENTS_ACKED_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACKED field.                          */
44833   #define IPCT_EVENTS_ACKED_EVENTS_ACKED_NotGenerated (0x0UL) /*!< Event not generated                                         */
44834   #define IPCT_EVENTS_ACKED_EVENTS_ACKED_Generated (0x1UL) /*!< Event generated                                                */
44835 
44836 
44837 /* IPCT_PUBLISH_RECEIVE: Publish configuration for event RECEIVE[n] */
44838   #define IPCT_PUBLISH_RECEIVE_MaxCount (16UL)       /*!< Max size of PUBLISH_RECEIVE[16] array.                               */
44839   #define IPCT_PUBLISH_RECEIVE_MaxIndex (15UL)       /*!< Max index of PUBLISH_RECEIVE[16] array.                              */
44840   #define IPCT_PUBLISH_RECEIVE_MinIndex (0UL)        /*!< Min index of PUBLISH_RECEIVE[16] array.                              */
44841   #define IPCT_PUBLISH_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RECEIVE[16] register.                     */
44842 
44843 /* CHIDX @Bits 0..7 : DPPI channel that event RECEIVE[n] will publish to */
44844   #define IPCT_PUBLISH_RECEIVE_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
44845   #define IPCT_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPCT_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
44846   #define IPCT_PUBLISH_RECEIVE_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
44847   #define IPCT_PUBLISH_RECEIVE_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
44848 
44849 /* EN @Bit 31 : (unspecified) */
44850   #define IPCT_PUBLISH_RECEIVE_EN_Pos (31UL)         /*!< Position of EN field.                                                */
44851   #define IPCT_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPCT_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field.                        */
44852   #define IPCT_PUBLISH_RECEIVE_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
44853   #define IPCT_PUBLISH_RECEIVE_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
44854   #define IPCT_PUBLISH_RECEIVE_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
44855   #define IPCT_PUBLISH_RECEIVE_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
44856 
44857 
44858 /* IPCT_PUBLISH_ACKED: Publish configuration for event ACKED[n] */
44859   #define IPCT_PUBLISH_ACKED_MaxCount (16UL)         /*!< Max size of PUBLISH_ACKED[16] array.                                 */
44860   #define IPCT_PUBLISH_ACKED_MaxIndex (15UL)         /*!< Max index of PUBLISH_ACKED[16] array.                                */
44861   #define IPCT_PUBLISH_ACKED_MinIndex (0UL)          /*!< Min index of PUBLISH_ACKED[16] array.                                */
44862   #define IPCT_PUBLISH_ACKED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACKED[16] register.                         */
44863 
44864 /* CHIDX @Bits 0..7 : DPPI channel that event ACKED[n] will publish to */
44865   #define IPCT_PUBLISH_ACKED_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
44866   #define IPCT_PUBLISH_ACKED_CHIDX_Msk (0xFFUL << IPCT_PUBLISH_ACKED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
44867   #define IPCT_PUBLISH_ACKED_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
44868   #define IPCT_PUBLISH_ACKED_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
44869 
44870 /* EN @Bit 31 : (unspecified) */
44871   #define IPCT_PUBLISH_ACKED_EN_Pos (31UL)           /*!< Position of EN field.                                                */
44872   #define IPCT_PUBLISH_ACKED_EN_Msk (0x1UL << IPCT_PUBLISH_ACKED_EN_Pos) /*!< Bit mask of EN field.                            */
44873   #define IPCT_PUBLISH_ACKED_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
44874   #define IPCT_PUBLISH_ACKED_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
44875   #define IPCT_PUBLISH_ACKED_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
44876   #define IPCT_PUBLISH_ACKED_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
44877 
44878 
44879 /* IPCT_SHORTS: Shortcuts between local events and tasks */
44880   #define IPCT_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */
44881 
44882 /* RECEIVE0_ACK0 @Bit 0 : Shortcut between event RECEIVE[0] and task ACK[0] */
44883   #define IPCT_SHORTS_RECEIVE0_ACK0_Pos (0UL)        /*!< Position of RECEIVE0_ACK0 field.                                     */
44884   #define IPCT_SHORTS_RECEIVE0_ACK0_Msk (0x1UL << IPCT_SHORTS_RECEIVE0_ACK0_Pos) /*!< Bit mask of RECEIVE0_ACK0 field.         */
44885   #define IPCT_SHORTS_RECEIVE0_ACK0_Min (0x0UL)      /*!< Min enumerator value of RECEIVE0_ACK0 field.                         */
44886   #define IPCT_SHORTS_RECEIVE0_ACK0_Max (0x1UL)      /*!< Max enumerator value of RECEIVE0_ACK0 field.                         */
44887   #define IPCT_SHORTS_RECEIVE0_ACK0_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44888   #define IPCT_SHORTS_RECEIVE0_ACK0_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44889 
44890 /* RECEIVE1_ACK1 @Bit 1 : Shortcut between event RECEIVE[1] and task ACK[1] */
44891   #define IPCT_SHORTS_RECEIVE1_ACK1_Pos (1UL)        /*!< Position of RECEIVE1_ACK1 field.                                     */
44892   #define IPCT_SHORTS_RECEIVE1_ACK1_Msk (0x1UL << IPCT_SHORTS_RECEIVE1_ACK1_Pos) /*!< Bit mask of RECEIVE1_ACK1 field.         */
44893   #define IPCT_SHORTS_RECEIVE1_ACK1_Min (0x0UL)      /*!< Min enumerator value of RECEIVE1_ACK1 field.                         */
44894   #define IPCT_SHORTS_RECEIVE1_ACK1_Max (0x1UL)      /*!< Max enumerator value of RECEIVE1_ACK1 field.                         */
44895   #define IPCT_SHORTS_RECEIVE1_ACK1_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44896   #define IPCT_SHORTS_RECEIVE1_ACK1_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44897 
44898 /* RECEIVE2_ACK2 @Bit 2 : Shortcut between event RECEIVE[2] and task ACK[2] */
44899   #define IPCT_SHORTS_RECEIVE2_ACK2_Pos (2UL)        /*!< Position of RECEIVE2_ACK2 field.                                     */
44900   #define IPCT_SHORTS_RECEIVE2_ACK2_Msk (0x1UL << IPCT_SHORTS_RECEIVE2_ACK2_Pos) /*!< Bit mask of RECEIVE2_ACK2 field.         */
44901   #define IPCT_SHORTS_RECEIVE2_ACK2_Min (0x0UL)      /*!< Min enumerator value of RECEIVE2_ACK2 field.                         */
44902   #define IPCT_SHORTS_RECEIVE2_ACK2_Max (0x1UL)      /*!< Max enumerator value of RECEIVE2_ACK2 field.                         */
44903   #define IPCT_SHORTS_RECEIVE2_ACK2_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44904   #define IPCT_SHORTS_RECEIVE2_ACK2_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44905 
44906 /* RECEIVE3_ACK3 @Bit 3 : Shortcut between event RECEIVE[3] and task ACK[3] */
44907   #define IPCT_SHORTS_RECEIVE3_ACK3_Pos (3UL)        /*!< Position of RECEIVE3_ACK3 field.                                     */
44908   #define IPCT_SHORTS_RECEIVE3_ACK3_Msk (0x1UL << IPCT_SHORTS_RECEIVE3_ACK3_Pos) /*!< Bit mask of RECEIVE3_ACK3 field.         */
44909   #define IPCT_SHORTS_RECEIVE3_ACK3_Min (0x0UL)      /*!< Min enumerator value of RECEIVE3_ACK3 field.                         */
44910   #define IPCT_SHORTS_RECEIVE3_ACK3_Max (0x1UL)      /*!< Max enumerator value of RECEIVE3_ACK3 field.                         */
44911   #define IPCT_SHORTS_RECEIVE3_ACK3_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44912   #define IPCT_SHORTS_RECEIVE3_ACK3_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44913 
44914 /* RECEIVE4_ACK4 @Bit 4 : Shortcut between event RECEIVE[4] and task ACK[4] */
44915   #define IPCT_SHORTS_RECEIVE4_ACK4_Pos (4UL)        /*!< Position of RECEIVE4_ACK4 field.                                     */
44916   #define IPCT_SHORTS_RECEIVE4_ACK4_Msk (0x1UL << IPCT_SHORTS_RECEIVE4_ACK4_Pos) /*!< Bit mask of RECEIVE4_ACK4 field.         */
44917   #define IPCT_SHORTS_RECEIVE4_ACK4_Min (0x0UL)      /*!< Min enumerator value of RECEIVE4_ACK4 field.                         */
44918   #define IPCT_SHORTS_RECEIVE4_ACK4_Max (0x1UL)      /*!< Max enumerator value of RECEIVE4_ACK4 field.                         */
44919   #define IPCT_SHORTS_RECEIVE4_ACK4_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44920   #define IPCT_SHORTS_RECEIVE4_ACK4_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44921 
44922 /* RECEIVE5_ACK5 @Bit 5 : Shortcut between event RECEIVE[5] and task ACK[5] */
44923   #define IPCT_SHORTS_RECEIVE5_ACK5_Pos (5UL)        /*!< Position of RECEIVE5_ACK5 field.                                     */
44924   #define IPCT_SHORTS_RECEIVE5_ACK5_Msk (0x1UL << IPCT_SHORTS_RECEIVE5_ACK5_Pos) /*!< Bit mask of RECEIVE5_ACK5 field.         */
44925   #define IPCT_SHORTS_RECEIVE5_ACK5_Min (0x0UL)      /*!< Min enumerator value of RECEIVE5_ACK5 field.                         */
44926   #define IPCT_SHORTS_RECEIVE5_ACK5_Max (0x1UL)      /*!< Max enumerator value of RECEIVE5_ACK5 field.                         */
44927   #define IPCT_SHORTS_RECEIVE5_ACK5_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44928   #define IPCT_SHORTS_RECEIVE5_ACK5_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44929 
44930 /* RECEIVE6_ACK6 @Bit 6 : Shortcut between event RECEIVE[6] and task ACK[6] */
44931   #define IPCT_SHORTS_RECEIVE6_ACK6_Pos (6UL)        /*!< Position of RECEIVE6_ACK6 field.                                     */
44932   #define IPCT_SHORTS_RECEIVE6_ACK6_Msk (0x1UL << IPCT_SHORTS_RECEIVE6_ACK6_Pos) /*!< Bit mask of RECEIVE6_ACK6 field.         */
44933   #define IPCT_SHORTS_RECEIVE6_ACK6_Min (0x0UL)      /*!< Min enumerator value of RECEIVE6_ACK6 field.                         */
44934   #define IPCT_SHORTS_RECEIVE6_ACK6_Max (0x1UL)      /*!< Max enumerator value of RECEIVE6_ACK6 field.                         */
44935   #define IPCT_SHORTS_RECEIVE6_ACK6_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44936   #define IPCT_SHORTS_RECEIVE6_ACK6_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44937 
44938 /* RECEIVE7_ACK7 @Bit 7 : Shortcut between event RECEIVE[7] and task ACK[7] */
44939   #define IPCT_SHORTS_RECEIVE7_ACK7_Pos (7UL)        /*!< Position of RECEIVE7_ACK7 field.                                     */
44940   #define IPCT_SHORTS_RECEIVE7_ACK7_Msk (0x1UL << IPCT_SHORTS_RECEIVE7_ACK7_Pos) /*!< Bit mask of RECEIVE7_ACK7 field.         */
44941   #define IPCT_SHORTS_RECEIVE7_ACK7_Min (0x0UL)      /*!< Min enumerator value of RECEIVE7_ACK7 field.                         */
44942   #define IPCT_SHORTS_RECEIVE7_ACK7_Max (0x1UL)      /*!< Max enumerator value of RECEIVE7_ACK7 field.                         */
44943   #define IPCT_SHORTS_RECEIVE7_ACK7_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44944   #define IPCT_SHORTS_RECEIVE7_ACK7_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44945 
44946 /* RECEIVE8_ACK8 @Bit 8 : Shortcut between event RECEIVE[8] and task ACK[8] */
44947   #define IPCT_SHORTS_RECEIVE8_ACK8_Pos (8UL)        /*!< Position of RECEIVE8_ACK8 field.                                     */
44948   #define IPCT_SHORTS_RECEIVE8_ACK8_Msk (0x1UL << IPCT_SHORTS_RECEIVE8_ACK8_Pos) /*!< Bit mask of RECEIVE8_ACK8 field.         */
44949   #define IPCT_SHORTS_RECEIVE8_ACK8_Min (0x0UL)      /*!< Min enumerator value of RECEIVE8_ACK8 field.                         */
44950   #define IPCT_SHORTS_RECEIVE8_ACK8_Max (0x1UL)      /*!< Max enumerator value of RECEIVE8_ACK8 field.                         */
44951   #define IPCT_SHORTS_RECEIVE8_ACK8_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44952   #define IPCT_SHORTS_RECEIVE8_ACK8_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44953 
44954 /* RECEIVE9_ACK9 @Bit 9 : Shortcut between event RECEIVE[9] and task ACK[9] */
44955   #define IPCT_SHORTS_RECEIVE9_ACK9_Pos (9UL)        /*!< Position of RECEIVE9_ACK9 field.                                     */
44956   #define IPCT_SHORTS_RECEIVE9_ACK9_Msk (0x1UL << IPCT_SHORTS_RECEIVE9_ACK9_Pos) /*!< Bit mask of RECEIVE9_ACK9 field.         */
44957   #define IPCT_SHORTS_RECEIVE9_ACK9_Min (0x0UL)      /*!< Min enumerator value of RECEIVE9_ACK9 field.                         */
44958   #define IPCT_SHORTS_RECEIVE9_ACK9_Max (0x1UL)      /*!< Max enumerator value of RECEIVE9_ACK9 field.                         */
44959   #define IPCT_SHORTS_RECEIVE9_ACK9_Disabled (0x0UL) /*!< Disable shortcut                                                     */
44960   #define IPCT_SHORTS_RECEIVE9_ACK9_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
44961 
44962 /* RECEIVE10_ACK10 @Bit 10 : Shortcut between event RECEIVE[10] and task ACK[10] */
44963   #define IPCT_SHORTS_RECEIVE10_ACK10_Pos (10UL)     /*!< Position of RECEIVE10_ACK10 field.                                   */
44964   #define IPCT_SHORTS_RECEIVE10_ACK10_Msk (0x1UL << IPCT_SHORTS_RECEIVE10_ACK10_Pos) /*!< Bit mask of RECEIVE10_ACK10 field.   */
44965   #define IPCT_SHORTS_RECEIVE10_ACK10_Min (0x0UL)    /*!< Min enumerator value of RECEIVE10_ACK10 field.                       */
44966   #define IPCT_SHORTS_RECEIVE10_ACK10_Max (0x1UL)    /*!< Max enumerator value of RECEIVE10_ACK10 field.                       */
44967   #define IPCT_SHORTS_RECEIVE10_ACK10_Disabled (0x0UL) /*!< Disable shortcut                                                   */
44968   #define IPCT_SHORTS_RECEIVE10_ACK10_Enabled (0x1UL) /*!< Enable shortcut                                                     */
44969 
44970 /* RECEIVE11_ACK11 @Bit 11 : Shortcut between event RECEIVE[11] and task ACK[11] */
44971   #define IPCT_SHORTS_RECEIVE11_ACK11_Pos (11UL)     /*!< Position of RECEIVE11_ACK11 field.                                   */
44972   #define IPCT_SHORTS_RECEIVE11_ACK11_Msk (0x1UL << IPCT_SHORTS_RECEIVE11_ACK11_Pos) /*!< Bit mask of RECEIVE11_ACK11 field.   */
44973   #define IPCT_SHORTS_RECEIVE11_ACK11_Min (0x0UL)    /*!< Min enumerator value of RECEIVE11_ACK11 field.                       */
44974   #define IPCT_SHORTS_RECEIVE11_ACK11_Max (0x1UL)    /*!< Max enumerator value of RECEIVE11_ACK11 field.                       */
44975   #define IPCT_SHORTS_RECEIVE11_ACK11_Disabled (0x0UL) /*!< Disable shortcut                                                   */
44976   #define IPCT_SHORTS_RECEIVE11_ACK11_Enabled (0x1UL) /*!< Enable shortcut                                                     */
44977 
44978 /* RECEIVE12_ACK12 @Bit 12 : Shortcut between event RECEIVE[12] and task ACK[12] */
44979   #define IPCT_SHORTS_RECEIVE12_ACK12_Pos (12UL)     /*!< Position of RECEIVE12_ACK12 field.                                   */
44980   #define IPCT_SHORTS_RECEIVE12_ACK12_Msk (0x1UL << IPCT_SHORTS_RECEIVE12_ACK12_Pos) /*!< Bit mask of RECEIVE12_ACK12 field.   */
44981   #define IPCT_SHORTS_RECEIVE12_ACK12_Min (0x0UL)    /*!< Min enumerator value of RECEIVE12_ACK12 field.                       */
44982   #define IPCT_SHORTS_RECEIVE12_ACK12_Max (0x1UL)    /*!< Max enumerator value of RECEIVE12_ACK12 field.                       */
44983   #define IPCT_SHORTS_RECEIVE12_ACK12_Disabled (0x0UL) /*!< Disable shortcut                                                   */
44984   #define IPCT_SHORTS_RECEIVE12_ACK12_Enabled (0x1UL) /*!< Enable shortcut                                                     */
44985 
44986 /* RECEIVE13_ACK13 @Bit 13 : Shortcut between event RECEIVE[13] and task ACK[13] */
44987   #define IPCT_SHORTS_RECEIVE13_ACK13_Pos (13UL)     /*!< Position of RECEIVE13_ACK13 field.                                   */
44988   #define IPCT_SHORTS_RECEIVE13_ACK13_Msk (0x1UL << IPCT_SHORTS_RECEIVE13_ACK13_Pos) /*!< Bit mask of RECEIVE13_ACK13 field.   */
44989   #define IPCT_SHORTS_RECEIVE13_ACK13_Min (0x0UL)    /*!< Min enumerator value of RECEIVE13_ACK13 field.                       */
44990   #define IPCT_SHORTS_RECEIVE13_ACK13_Max (0x1UL)    /*!< Max enumerator value of RECEIVE13_ACK13 field.                       */
44991   #define IPCT_SHORTS_RECEIVE13_ACK13_Disabled (0x0UL) /*!< Disable shortcut                                                   */
44992   #define IPCT_SHORTS_RECEIVE13_ACK13_Enabled (0x1UL) /*!< Enable shortcut                                                     */
44993 
44994 /* RECEIVE14_ACK14 @Bit 14 : Shortcut between event RECEIVE[14] and task ACK[14] */
44995   #define IPCT_SHORTS_RECEIVE14_ACK14_Pos (14UL)     /*!< Position of RECEIVE14_ACK14 field.                                   */
44996   #define IPCT_SHORTS_RECEIVE14_ACK14_Msk (0x1UL << IPCT_SHORTS_RECEIVE14_ACK14_Pos) /*!< Bit mask of RECEIVE14_ACK14 field.   */
44997   #define IPCT_SHORTS_RECEIVE14_ACK14_Min (0x0UL)    /*!< Min enumerator value of RECEIVE14_ACK14 field.                       */
44998   #define IPCT_SHORTS_RECEIVE14_ACK14_Max (0x1UL)    /*!< Max enumerator value of RECEIVE14_ACK14 field.                       */
44999   #define IPCT_SHORTS_RECEIVE14_ACK14_Disabled (0x0UL) /*!< Disable shortcut                                                   */
45000   #define IPCT_SHORTS_RECEIVE14_ACK14_Enabled (0x1UL) /*!< Enable shortcut                                                     */
45001 
45002 /* RECEIVE15_ACK15 @Bit 15 : Shortcut between event RECEIVE[15] and task ACK[15] */
45003   #define IPCT_SHORTS_RECEIVE15_ACK15_Pos (15UL)     /*!< Position of RECEIVE15_ACK15 field.                                   */
45004   #define IPCT_SHORTS_RECEIVE15_ACK15_Msk (0x1UL << IPCT_SHORTS_RECEIVE15_ACK15_Pos) /*!< Bit mask of RECEIVE15_ACK15 field.   */
45005   #define IPCT_SHORTS_RECEIVE15_ACK15_Min (0x0UL)    /*!< Min enumerator value of RECEIVE15_ACK15 field.                       */
45006   #define IPCT_SHORTS_RECEIVE15_ACK15_Max (0x1UL)    /*!< Max enumerator value of RECEIVE15_ACK15 field.                       */
45007   #define IPCT_SHORTS_RECEIVE15_ACK15_Disabled (0x0UL) /*!< Disable shortcut                                                   */
45008   #define IPCT_SHORTS_RECEIVE15_ACK15_Enabled (0x1UL) /*!< Enable shortcut                                                     */
45009 
45010 
45011 /* IPCT_INTEN0: Enable or disable interrupt */
45012   #define IPCT_INTEN0_ResetValue (0x00000000UL)      /*!< Reset value of INTEN0 register.                                      */
45013 
45014 /* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
45015   #define IPCT_INTEN0_RECEIVE0_Pos (0UL)             /*!< Position of RECEIVE0 field.                                          */
45016   #define IPCT_INTEN0_RECEIVE0_Msk (0x1UL << IPCT_INTEN0_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                        */
45017   #define IPCT_INTEN0_RECEIVE0_Min (0x0UL)           /*!< Min enumerator value of RECEIVE0 field.                              */
45018   #define IPCT_INTEN0_RECEIVE0_Max (0x1UL)           /*!< Max enumerator value of RECEIVE0 field.                              */
45019   #define IPCT_INTEN0_RECEIVE0_Disabled (0x0UL)      /*!< Disable                                                              */
45020   #define IPCT_INTEN0_RECEIVE0_Enabled (0x1UL)       /*!< Enable                                                               */
45021 
45022 /* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
45023   #define IPCT_INTEN0_RECEIVE1_Pos (1UL)             /*!< Position of RECEIVE1 field.                                          */
45024   #define IPCT_INTEN0_RECEIVE1_Msk (0x1UL << IPCT_INTEN0_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                        */
45025   #define IPCT_INTEN0_RECEIVE1_Min (0x0UL)           /*!< Min enumerator value of RECEIVE1 field.                              */
45026   #define IPCT_INTEN0_RECEIVE1_Max (0x1UL)           /*!< Max enumerator value of RECEIVE1 field.                              */
45027   #define IPCT_INTEN0_RECEIVE1_Disabled (0x0UL)      /*!< Disable                                                              */
45028   #define IPCT_INTEN0_RECEIVE1_Enabled (0x1UL)       /*!< Enable                                                               */
45029 
45030 /* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
45031   #define IPCT_INTEN0_RECEIVE2_Pos (2UL)             /*!< Position of RECEIVE2 field.                                          */
45032   #define IPCT_INTEN0_RECEIVE2_Msk (0x1UL << IPCT_INTEN0_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                        */
45033   #define IPCT_INTEN0_RECEIVE2_Min (0x0UL)           /*!< Min enumerator value of RECEIVE2 field.                              */
45034   #define IPCT_INTEN0_RECEIVE2_Max (0x1UL)           /*!< Max enumerator value of RECEIVE2 field.                              */
45035   #define IPCT_INTEN0_RECEIVE2_Disabled (0x0UL)      /*!< Disable                                                              */
45036   #define IPCT_INTEN0_RECEIVE2_Enabled (0x1UL)       /*!< Enable                                                               */
45037 
45038 /* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
45039   #define IPCT_INTEN0_RECEIVE3_Pos (3UL)             /*!< Position of RECEIVE3 field.                                          */
45040   #define IPCT_INTEN0_RECEIVE3_Msk (0x1UL << IPCT_INTEN0_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                        */
45041   #define IPCT_INTEN0_RECEIVE3_Min (0x0UL)           /*!< Min enumerator value of RECEIVE3 field.                              */
45042   #define IPCT_INTEN0_RECEIVE3_Max (0x1UL)           /*!< Max enumerator value of RECEIVE3 field.                              */
45043   #define IPCT_INTEN0_RECEIVE3_Disabled (0x0UL)      /*!< Disable                                                              */
45044   #define IPCT_INTEN0_RECEIVE3_Enabled (0x1UL)       /*!< Enable                                                               */
45045 
45046 /* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
45047   #define IPCT_INTEN0_RECEIVE4_Pos (4UL)             /*!< Position of RECEIVE4 field.                                          */
45048   #define IPCT_INTEN0_RECEIVE4_Msk (0x1UL << IPCT_INTEN0_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                        */
45049   #define IPCT_INTEN0_RECEIVE4_Min (0x0UL)           /*!< Min enumerator value of RECEIVE4 field.                              */
45050   #define IPCT_INTEN0_RECEIVE4_Max (0x1UL)           /*!< Max enumerator value of RECEIVE4 field.                              */
45051   #define IPCT_INTEN0_RECEIVE4_Disabled (0x0UL)      /*!< Disable                                                              */
45052   #define IPCT_INTEN0_RECEIVE4_Enabled (0x1UL)       /*!< Enable                                                               */
45053 
45054 /* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
45055   #define IPCT_INTEN0_RECEIVE5_Pos (5UL)             /*!< Position of RECEIVE5 field.                                          */
45056   #define IPCT_INTEN0_RECEIVE5_Msk (0x1UL << IPCT_INTEN0_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                        */
45057   #define IPCT_INTEN0_RECEIVE5_Min (0x0UL)           /*!< Min enumerator value of RECEIVE5 field.                              */
45058   #define IPCT_INTEN0_RECEIVE5_Max (0x1UL)           /*!< Max enumerator value of RECEIVE5 field.                              */
45059   #define IPCT_INTEN0_RECEIVE5_Disabled (0x0UL)      /*!< Disable                                                              */
45060   #define IPCT_INTEN0_RECEIVE5_Enabled (0x1UL)       /*!< Enable                                                               */
45061 
45062 /* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
45063   #define IPCT_INTEN0_RECEIVE6_Pos (6UL)             /*!< Position of RECEIVE6 field.                                          */
45064   #define IPCT_INTEN0_RECEIVE6_Msk (0x1UL << IPCT_INTEN0_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                        */
45065   #define IPCT_INTEN0_RECEIVE6_Min (0x0UL)           /*!< Min enumerator value of RECEIVE6 field.                              */
45066   #define IPCT_INTEN0_RECEIVE6_Max (0x1UL)           /*!< Max enumerator value of RECEIVE6 field.                              */
45067   #define IPCT_INTEN0_RECEIVE6_Disabled (0x0UL)      /*!< Disable                                                              */
45068   #define IPCT_INTEN0_RECEIVE6_Enabled (0x1UL)       /*!< Enable                                                               */
45069 
45070 /* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
45071   #define IPCT_INTEN0_RECEIVE7_Pos (7UL)             /*!< Position of RECEIVE7 field.                                          */
45072   #define IPCT_INTEN0_RECEIVE7_Msk (0x1UL << IPCT_INTEN0_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                        */
45073   #define IPCT_INTEN0_RECEIVE7_Min (0x0UL)           /*!< Min enumerator value of RECEIVE7 field.                              */
45074   #define IPCT_INTEN0_RECEIVE7_Max (0x1UL)           /*!< Max enumerator value of RECEIVE7 field.                              */
45075   #define IPCT_INTEN0_RECEIVE7_Disabled (0x0UL)      /*!< Disable                                                              */
45076   #define IPCT_INTEN0_RECEIVE7_Enabled (0x1UL)       /*!< Enable                                                               */
45077 
45078 /* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
45079   #define IPCT_INTEN0_RECEIVE8_Pos (8UL)             /*!< Position of RECEIVE8 field.                                          */
45080   #define IPCT_INTEN0_RECEIVE8_Msk (0x1UL << IPCT_INTEN0_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                        */
45081   #define IPCT_INTEN0_RECEIVE8_Min (0x0UL)           /*!< Min enumerator value of RECEIVE8 field.                              */
45082   #define IPCT_INTEN0_RECEIVE8_Max (0x1UL)           /*!< Max enumerator value of RECEIVE8 field.                              */
45083   #define IPCT_INTEN0_RECEIVE8_Disabled (0x0UL)      /*!< Disable                                                              */
45084   #define IPCT_INTEN0_RECEIVE8_Enabled (0x1UL)       /*!< Enable                                                               */
45085 
45086 /* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
45087   #define IPCT_INTEN0_RECEIVE9_Pos (9UL)             /*!< Position of RECEIVE9 field.                                          */
45088   #define IPCT_INTEN0_RECEIVE9_Msk (0x1UL << IPCT_INTEN0_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                        */
45089   #define IPCT_INTEN0_RECEIVE9_Min (0x0UL)           /*!< Min enumerator value of RECEIVE9 field.                              */
45090   #define IPCT_INTEN0_RECEIVE9_Max (0x1UL)           /*!< Max enumerator value of RECEIVE9 field.                              */
45091   #define IPCT_INTEN0_RECEIVE9_Disabled (0x0UL)      /*!< Disable                                                              */
45092   #define IPCT_INTEN0_RECEIVE9_Enabled (0x1UL)       /*!< Enable                                                               */
45093 
45094 /* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
45095   #define IPCT_INTEN0_RECEIVE10_Pos (10UL)           /*!< Position of RECEIVE10 field.                                         */
45096   #define IPCT_INTEN0_RECEIVE10_Msk (0x1UL << IPCT_INTEN0_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                     */
45097   #define IPCT_INTEN0_RECEIVE10_Min (0x0UL)          /*!< Min enumerator value of RECEIVE10 field.                             */
45098   #define IPCT_INTEN0_RECEIVE10_Max (0x1UL)          /*!< Max enumerator value of RECEIVE10 field.                             */
45099   #define IPCT_INTEN0_RECEIVE10_Disabled (0x0UL)     /*!< Disable                                                              */
45100   #define IPCT_INTEN0_RECEIVE10_Enabled (0x1UL)      /*!< Enable                                                               */
45101 
45102 /* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
45103   #define IPCT_INTEN0_RECEIVE11_Pos (11UL)           /*!< Position of RECEIVE11 field.                                         */
45104   #define IPCT_INTEN0_RECEIVE11_Msk (0x1UL << IPCT_INTEN0_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                     */
45105   #define IPCT_INTEN0_RECEIVE11_Min (0x0UL)          /*!< Min enumerator value of RECEIVE11 field.                             */
45106   #define IPCT_INTEN0_RECEIVE11_Max (0x1UL)          /*!< Max enumerator value of RECEIVE11 field.                             */
45107   #define IPCT_INTEN0_RECEIVE11_Disabled (0x0UL)     /*!< Disable                                                              */
45108   #define IPCT_INTEN0_RECEIVE11_Enabled (0x1UL)      /*!< Enable                                                               */
45109 
45110 /* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
45111   #define IPCT_INTEN0_RECEIVE12_Pos (12UL)           /*!< Position of RECEIVE12 field.                                         */
45112   #define IPCT_INTEN0_RECEIVE12_Msk (0x1UL << IPCT_INTEN0_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                     */
45113   #define IPCT_INTEN0_RECEIVE12_Min (0x0UL)          /*!< Min enumerator value of RECEIVE12 field.                             */
45114   #define IPCT_INTEN0_RECEIVE12_Max (0x1UL)          /*!< Max enumerator value of RECEIVE12 field.                             */
45115   #define IPCT_INTEN0_RECEIVE12_Disabled (0x0UL)     /*!< Disable                                                              */
45116   #define IPCT_INTEN0_RECEIVE12_Enabled (0x1UL)      /*!< Enable                                                               */
45117 
45118 /* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
45119   #define IPCT_INTEN0_RECEIVE13_Pos (13UL)           /*!< Position of RECEIVE13 field.                                         */
45120   #define IPCT_INTEN0_RECEIVE13_Msk (0x1UL << IPCT_INTEN0_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                     */
45121   #define IPCT_INTEN0_RECEIVE13_Min (0x0UL)          /*!< Min enumerator value of RECEIVE13 field.                             */
45122   #define IPCT_INTEN0_RECEIVE13_Max (0x1UL)          /*!< Max enumerator value of RECEIVE13 field.                             */
45123   #define IPCT_INTEN0_RECEIVE13_Disabled (0x0UL)     /*!< Disable                                                              */
45124   #define IPCT_INTEN0_RECEIVE13_Enabled (0x1UL)      /*!< Enable                                                               */
45125 
45126 /* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
45127   #define IPCT_INTEN0_RECEIVE14_Pos (14UL)           /*!< Position of RECEIVE14 field.                                         */
45128   #define IPCT_INTEN0_RECEIVE14_Msk (0x1UL << IPCT_INTEN0_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                     */
45129   #define IPCT_INTEN0_RECEIVE14_Min (0x0UL)          /*!< Min enumerator value of RECEIVE14 field.                             */
45130   #define IPCT_INTEN0_RECEIVE14_Max (0x1UL)          /*!< Max enumerator value of RECEIVE14 field.                             */
45131   #define IPCT_INTEN0_RECEIVE14_Disabled (0x0UL)     /*!< Disable                                                              */
45132   #define IPCT_INTEN0_RECEIVE14_Enabled (0x1UL)      /*!< Enable                                                               */
45133 
45134 /* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
45135   #define IPCT_INTEN0_RECEIVE15_Pos (15UL)           /*!< Position of RECEIVE15 field.                                         */
45136   #define IPCT_INTEN0_RECEIVE15_Msk (0x1UL << IPCT_INTEN0_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                     */
45137   #define IPCT_INTEN0_RECEIVE15_Min (0x0UL)          /*!< Min enumerator value of RECEIVE15 field.                             */
45138   #define IPCT_INTEN0_RECEIVE15_Max (0x1UL)          /*!< Max enumerator value of RECEIVE15 field.                             */
45139   #define IPCT_INTEN0_RECEIVE15_Disabled (0x0UL)     /*!< Disable                                                              */
45140   #define IPCT_INTEN0_RECEIVE15_Enabled (0x1UL)      /*!< Enable                                                               */
45141 
45142 /* ACKED0 @Bit 16 : Enable or disable interrupt for event ACKED[0] */
45143   #define IPCT_INTEN0_ACKED0_Pos (16UL)              /*!< Position of ACKED0 field.                                            */
45144   #define IPCT_INTEN0_ACKED0_Msk (0x1UL << IPCT_INTEN0_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                              */
45145   #define IPCT_INTEN0_ACKED0_Min (0x0UL)             /*!< Min enumerator value of ACKED0 field.                                */
45146   #define IPCT_INTEN0_ACKED0_Max (0x1UL)             /*!< Max enumerator value of ACKED0 field.                                */
45147   #define IPCT_INTEN0_ACKED0_Disabled (0x0UL)        /*!< Disable                                                              */
45148   #define IPCT_INTEN0_ACKED0_Enabled (0x1UL)         /*!< Enable                                                               */
45149 
45150 /* ACKED1 @Bit 17 : Enable or disable interrupt for event ACKED[1] */
45151   #define IPCT_INTEN0_ACKED1_Pos (17UL)              /*!< Position of ACKED1 field.                                            */
45152   #define IPCT_INTEN0_ACKED1_Msk (0x1UL << IPCT_INTEN0_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                              */
45153   #define IPCT_INTEN0_ACKED1_Min (0x0UL)             /*!< Min enumerator value of ACKED1 field.                                */
45154   #define IPCT_INTEN0_ACKED1_Max (0x1UL)             /*!< Max enumerator value of ACKED1 field.                                */
45155   #define IPCT_INTEN0_ACKED1_Disabled (0x0UL)        /*!< Disable                                                              */
45156   #define IPCT_INTEN0_ACKED1_Enabled (0x1UL)         /*!< Enable                                                               */
45157 
45158 /* ACKED2 @Bit 18 : Enable or disable interrupt for event ACKED[2] */
45159   #define IPCT_INTEN0_ACKED2_Pos (18UL)              /*!< Position of ACKED2 field.                                            */
45160   #define IPCT_INTEN0_ACKED2_Msk (0x1UL << IPCT_INTEN0_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                              */
45161   #define IPCT_INTEN0_ACKED2_Min (0x0UL)             /*!< Min enumerator value of ACKED2 field.                                */
45162   #define IPCT_INTEN0_ACKED2_Max (0x1UL)             /*!< Max enumerator value of ACKED2 field.                                */
45163   #define IPCT_INTEN0_ACKED2_Disabled (0x0UL)        /*!< Disable                                                              */
45164   #define IPCT_INTEN0_ACKED2_Enabled (0x1UL)         /*!< Enable                                                               */
45165 
45166 /* ACKED3 @Bit 19 : Enable or disable interrupt for event ACKED[3] */
45167   #define IPCT_INTEN0_ACKED3_Pos (19UL)              /*!< Position of ACKED3 field.                                            */
45168   #define IPCT_INTEN0_ACKED3_Msk (0x1UL << IPCT_INTEN0_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                              */
45169   #define IPCT_INTEN0_ACKED3_Min (0x0UL)             /*!< Min enumerator value of ACKED3 field.                                */
45170   #define IPCT_INTEN0_ACKED3_Max (0x1UL)             /*!< Max enumerator value of ACKED3 field.                                */
45171   #define IPCT_INTEN0_ACKED3_Disabled (0x0UL)        /*!< Disable                                                              */
45172   #define IPCT_INTEN0_ACKED3_Enabled (0x1UL)         /*!< Enable                                                               */
45173 
45174 /* ACKED4 @Bit 20 : Enable or disable interrupt for event ACKED[4] */
45175   #define IPCT_INTEN0_ACKED4_Pos (20UL)              /*!< Position of ACKED4 field.                                            */
45176   #define IPCT_INTEN0_ACKED4_Msk (0x1UL << IPCT_INTEN0_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                              */
45177   #define IPCT_INTEN0_ACKED4_Min (0x0UL)             /*!< Min enumerator value of ACKED4 field.                                */
45178   #define IPCT_INTEN0_ACKED4_Max (0x1UL)             /*!< Max enumerator value of ACKED4 field.                                */
45179   #define IPCT_INTEN0_ACKED4_Disabled (0x0UL)        /*!< Disable                                                              */
45180   #define IPCT_INTEN0_ACKED4_Enabled (0x1UL)         /*!< Enable                                                               */
45181 
45182 /* ACKED5 @Bit 21 : Enable or disable interrupt for event ACKED[5] */
45183   #define IPCT_INTEN0_ACKED5_Pos (21UL)              /*!< Position of ACKED5 field.                                            */
45184   #define IPCT_INTEN0_ACKED5_Msk (0x1UL << IPCT_INTEN0_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                              */
45185   #define IPCT_INTEN0_ACKED5_Min (0x0UL)             /*!< Min enumerator value of ACKED5 field.                                */
45186   #define IPCT_INTEN0_ACKED5_Max (0x1UL)             /*!< Max enumerator value of ACKED5 field.                                */
45187   #define IPCT_INTEN0_ACKED5_Disabled (0x0UL)        /*!< Disable                                                              */
45188   #define IPCT_INTEN0_ACKED5_Enabled (0x1UL)         /*!< Enable                                                               */
45189 
45190 /* ACKED6 @Bit 22 : Enable or disable interrupt for event ACKED[6] */
45191   #define IPCT_INTEN0_ACKED6_Pos (22UL)              /*!< Position of ACKED6 field.                                            */
45192   #define IPCT_INTEN0_ACKED6_Msk (0x1UL << IPCT_INTEN0_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                              */
45193   #define IPCT_INTEN0_ACKED6_Min (0x0UL)             /*!< Min enumerator value of ACKED6 field.                                */
45194   #define IPCT_INTEN0_ACKED6_Max (0x1UL)             /*!< Max enumerator value of ACKED6 field.                                */
45195   #define IPCT_INTEN0_ACKED6_Disabled (0x0UL)        /*!< Disable                                                              */
45196   #define IPCT_INTEN0_ACKED6_Enabled (0x1UL)         /*!< Enable                                                               */
45197 
45198 /* ACKED7 @Bit 23 : Enable or disable interrupt for event ACKED[7] */
45199   #define IPCT_INTEN0_ACKED7_Pos (23UL)              /*!< Position of ACKED7 field.                                            */
45200   #define IPCT_INTEN0_ACKED7_Msk (0x1UL << IPCT_INTEN0_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                              */
45201   #define IPCT_INTEN0_ACKED7_Min (0x0UL)             /*!< Min enumerator value of ACKED7 field.                                */
45202   #define IPCT_INTEN0_ACKED7_Max (0x1UL)             /*!< Max enumerator value of ACKED7 field.                                */
45203   #define IPCT_INTEN0_ACKED7_Disabled (0x0UL)        /*!< Disable                                                              */
45204   #define IPCT_INTEN0_ACKED7_Enabled (0x1UL)         /*!< Enable                                                               */
45205 
45206 /* ACKED8 @Bit 24 : Enable or disable interrupt for event ACKED[8] */
45207   #define IPCT_INTEN0_ACKED8_Pos (24UL)              /*!< Position of ACKED8 field.                                            */
45208   #define IPCT_INTEN0_ACKED8_Msk (0x1UL << IPCT_INTEN0_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                              */
45209   #define IPCT_INTEN0_ACKED8_Min (0x0UL)             /*!< Min enumerator value of ACKED8 field.                                */
45210   #define IPCT_INTEN0_ACKED8_Max (0x1UL)             /*!< Max enumerator value of ACKED8 field.                                */
45211   #define IPCT_INTEN0_ACKED8_Disabled (0x0UL)        /*!< Disable                                                              */
45212   #define IPCT_INTEN0_ACKED8_Enabled (0x1UL)         /*!< Enable                                                               */
45213 
45214 /* ACKED9 @Bit 25 : Enable or disable interrupt for event ACKED[9] */
45215   #define IPCT_INTEN0_ACKED9_Pos (25UL)              /*!< Position of ACKED9 field.                                            */
45216   #define IPCT_INTEN0_ACKED9_Msk (0x1UL << IPCT_INTEN0_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                              */
45217   #define IPCT_INTEN0_ACKED9_Min (0x0UL)             /*!< Min enumerator value of ACKED9 field.                                */
45218   #define IPCT_INTEN0_ACKED9_Max (0x1UL)             /*!< Max enumerator value of ACKED9 field.                                */
45219   #define IPCT_INTEN0_ACKED9_Disabled (0x0UL)        /*!< Disable                                                              */
45220   #define IPCT_INTEN0_ACKED9_Enabled (0x1UL)         /*!< Enable                                                               */
45221 
45222 /* ACKED10 @Bit 26 : Enable or disable interrupt for event ACKED[10] */
45223   #define IPCT_INTEN0_ACKED10_Pos (26UL)             /*!< Position of ACKED10 field.                                           */
45224   #define IPCT_INTEN0_ACKED10_Msk (0x1UL << IPCT_INTEN0_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                           */
45225   #define IPCT_INTEN0_ACKED10_Min (0x0UL)            /*!< Min enumerator value of ACKED10 field.                               */
45226   #define IPCT_INTEN0_ACKED10_Max (0x1UL)            /*!< Max enumerator value of ACKED10 field.                               */
45227   #define IPCT_INTEN0_ACKED10_Disabled (0x0UL)       /*!< Disable                                                              */
45228   #define IPCT_INTEN0_ACKED10_Enabled (0x1UL)        /*!< Enable                                                               */
45229 
45230 /* ACKED11 @Bit 27 : Enable or disable interrupt for event ACKED[11] */
45231   #define IPCT_INTEN0_ACKED11_Pos (27UL)             /*!< Position of ACKED11 field.                                           */
45232   #define IPCT_INTEN0_ACKED11_Msk (0x1UL << IPCT_INTEN0_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                           */
45233   #define IPCT_INTEN0_ACKED11_Min (0x0UL)            /*!< Min enumerator value of ACKED11 field.                               */
45234   #define IPCT_INTEN0_ACKED11_Max (0x1UL)            /*!< Max enumerator value of ACKED11 field.                               */
45235   #define IPCT_INTEN0_ACKED11_Disabled (0x0UL)       /*!< Disable                                                              */
45236   #define IPCT_INTEN0_ACKED11_Enabled (0x1UL)        /*!< Enable                                                               */
45237 
45238 /* ACKED12 @Bit 28 : Enable or disable interrupt for event ACKED[12] */
45239   #define IPCT_INTEN0_ACKED12_Pos (28UL)             /*!< Position of ACKED12 field.                                           */
45240   #define IPCT_INTEN0_ACKED12_Msk (0x1UL << IPCT_INTEN0_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                           */
45241   #define IPCT_INTEN0_ACKED12_Min (0x0UL)            /*!< Min enumerator value of ACKED12 field.                               */
45242   #define IPCT_INTEN0_ACKED12_Max (0x1UL)            /*!< Max enumerator value of ACKED12 field.                               */
45243   #define IPCT_INTEN0_ACKED12_Disabled (0x0UL)       /*!< Disable                                                              */
45244   #define IPCT_INTEN0_ACKED12_Enabled (0x1UL)        /*!< Enable                                                               */
45245 
45246 /* ACKED13 @Bit 29 : Enable or disable interrupt for event ACKED[13] */
45247   #define IPCT_INTEN0_ACKED13_Pos (29UL)             /*!< Position of ACKED13 field.                                           */
45248   #define IPCT_INTEN0_ACKED13_Msk (0x1UL << IPCT_INTEN0_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                           */
45249   #define IPCT_INTEN0_ACKED13_Min (0x0UL)            /*!< Min enumerator value of ACKED13 field.                               */
45250   #define IPCT_INTEN0_ACKED13_Max (0x1UL)            /*!< Max enumerator value of ACKED13 field.                               */
45251   #define IPCT_INTEN0_ACKED13_Disabled (0x0UL)       /*!< Disable                                                              */
45252   #define IPCT_INTEN0_ACKED13_Enabled (0x1UL)        /*!< Enable                                                               */
45253 
45254 /* ACKED14 @Bit 30 : Enable or disable interrupt for event ACKED[14] */
45255   #define IPCT_INTEN0_ACKED14_Pos (30UL)             /*!< Position of ACKED14 field.                                           */
45256   #define IPCT_INTEN0_ACKED14_Msk (0x1UL << IPCT_INTEN0_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                           */
45257   #define IPCT_INTEN0_ACKED14_Min (0x0UL)            /*!< Min enumerator value of ACKED14 field.                               */
45258   #define IPCT_INTEN0_ACKED14_Max (0x1UL)            /*!< Max enumerator value of ACKED14 field.                               */
45259   #define IPCT_INTEN0_ACKED14_Disabled (0x0UL)       /*!< Disable                                                              */
45260   #define IPCT_INTEN0_ACKED14_Enabled (0x1UL)        /*!< Enable                                                               */
45261 
45262 /* ACKED15 @Bit 31 : Enable or disable interrupt for event ACKED[15] */
45263   #define IPCT_INTEN0_ACKED15_Pos (31UL)             /*!< Position of ACKED15 field.                                           */
45264   #define IPCT_INTEN0_ACKED15_Msk (0x1UL << IPCT_INTEN0_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                           */
45265   #define IPCT_INTEN0_ACKED15_Min (0x0UL)            /*!< Min enumerator value of ACKED15 field.                               */
45266   #define IPCT_INTEN0_ACKED15_Max (0x1UL)            /*!< Max enumerator value of ACKED15 field.                               */
45267   #define IPCT_INTEN0_ACKED15_Disabled (0x0UL)       /*!< Disable                                                              */
45268   #define IPCT_INTEN0_ACKED15_Enabled (0x1UL)        /*!< Enable                                                               */
45269 
45270 
45271 /* IPCT_INTENSET0: Enable interrupt */
45272   #define IPCT_INTENSET0_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET0 register.                                   */
45273 
45274 /* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
45275   #define IPCT_INTENSET0_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
45276   #define IPCT_INTENSET0_RECEIVE0_Msk (0x1UL << IPCT_INTENSET0_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
45277   #define IPCT_INTENSET0_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
45278   #define IPCT_INTENSET0_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
45279   #define IPCT_INTENSET0_RECEIVE0_Set (0x1UL)        /*!< Enable                                                               */
45280   #define IPCT_INTENSET0_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45281   #define IPCT_INTENSET0_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45282 
45283 /* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
45284   #define IPCT_INTENSET0_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
45285   #define IPCT_INTENSET0_RECEIVE1_Msk (0x1UL << IPCT_INTENSET0_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
45286   #define IPCT_INTENSET0_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
45287   #define IPCT_INTENSET0_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
45288   #define IPCT_INTENSET0_RECEIVE1_Set (0x1UL)        /*!< Enable                                                               */
45289   #define IPCT_INTENSET0_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45290   #define IPCT_INTENSET0_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45291 
45292 /* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
45293   #define IPCT_INTENSET0_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
45294   #define IPCT_INTENSET0_RECEIVE2_Msk (0x1UL << IPCT_INTENSET0_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
45295   #define IPCT_INTENSET0_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
45296   #define IPCT_INTENSET0_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
45297   #define IPCT_INTENSET0_RECEIVE2_Set (0x1UL)        /*!< Enable                                                               */
45298   #define IPCT_INTENSET0_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45299   #define IPCT_INTENSET0_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45300 
45301 /* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
45302   #define IPCT_INTENSET0_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
45303   #define IPCT_INTENSET0_RECEIVE3_Msk (0x1UL << IPCT_INTENSET0_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
45304   #define IPCT_INTENSET0_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
45305   #define IPCT_INTENSET0_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
45306   #define IPCT_INTENSET0_RECEIVE3_Set (0x1UL)        /*!< Enable                                                               */
45307   #define IPCT_INTENSET0_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45308   #define IPCT_INTENSET0_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45309 
45310 /* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
45311   #define IPCT_INTENSET0_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
45312   #define IPCT_INTENSET0_RECEIVE4_Msk (0x1UL << IPCT_INTENSET0_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
45313   #define IPCT_INTENSET0_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
45314   #define IPCT_INTENSET0_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
45315   #define IPCT_INTENSET0_RECEIVE4_Set (0x1UL)        /*!< Enable                                                               */
45316   #define IPCT_INTENSET0_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45317   #define IPCT_INTENSET0_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45318 
45319 /* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
45320   #define IPCT_INTENSET0_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
45321   #define IPCT_INTENSET0_RECEIVE5_Msk (0x1UL << IPCT_INTENSET0_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
45322   #define IPCT_INTENSET0_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
45323   #define IPCT_INTENSET0_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
45324   #define IPCT_INTENSET0_RECEIVE5_Set (0x1UL)        /*!< Enable                                                               */
45325   #define IPCT_INTENSET0_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45326   #define IPCT_INTENSET0_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45327 
45328 /* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
45329   #define IPCT_INTENSET0_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
45330   #define IPCT_INTENSET0_RECEIVE6_Msk (0x1UL << IPCT_INTENSET0_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
45331   #define IPCT_INTENSET0_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
45332   #define IPCT_INTENSET0_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
45333   #define IPCT_INTENSET0_RECEIVE6_Set (0x1UL)        /*!< Enable                                                               */
45334   #define IPCT_INTENSET0_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45335   #define IPCT_INTENSET0_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45336 
45337 /* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
45338   #define IPCT_INTENSET0_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
45339   #define IPCT_INTENSET0_RECEIVE7_Msk (0x1UL << IPCT_INTENSET0_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
45340   #define IPCT_INTENSET0_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
45341   #define IPCT_INTENSET0_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
45342   #define IPCT_INTENSET0_RECEIVE7_Set (0x1UL)        /*!< Enable                                                               */
45343   #define IPCT_INTENSET0_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45344   #define IPCT_INTENSET0_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45345 
45346 /* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
45347   #define IPCT_INTENSET0_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
45348   #define IPCT_INTENSET0_RECEIVE8_Msk (0x1UL << IPCT_INTENSET0_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
45349   #define IPCT_INTENSET0_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
45350   #define IPCT_INTENSET0_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
45351   #define IPCT_INTENSET0_RECEIVE8_Set (0x1UL)        /*!< Enable                                                               */
45352   #define IPCT_INTENSET0_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45353   #define IPCT_INTENSET0_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45354 
45355 /* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
45356   #define IPCT_INTENSET0_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
45357   #define IPCT_INTENSET0_RECEIVE9_Msk (0x1UL << IPCT_INTENSET0_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
45358   #define IPCT_INTENSET0_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
45359   #define IPCT_INTENSET0_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
45360   #define IPCT_INTENSET0_RECEIVE9_Set (0x1UL)        /*!< Enable                                                               */
45361   #define IPCT_INTENSET0_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45362   #define IPCT_INTENSET0_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45363 
45364 /* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
45365   #define IPCT_INTENSET0_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
45366   #define IPCT_INTENSET0_RECEIVE10_Msk (0x1UL << IPCT_INTENSET0_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
45367   #define IPCT_INTENSET0_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
45368   #define IPCT_INTENSET0_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
45369   #define IPCT_INTENSET0_RECEIVE10_Set (0x1UL)       /*!< Enable                                                               */
45370   #define IPCT_INTENSET0_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45371   #define IPCT_INTENSET0_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45372 
45373 /* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
45374   #define IPCT_INTENSET0_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
45375   #define IPCT_INTENSET0_RECEIVE11_Msk (0x1UL << IPCT_INTENSET0_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
45376   #define IPCT_INTENSET0_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
45377   #define IPCT_INTENSET0_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
45378   #define IPCT_INTENSET0_RECEIVE11_Set (0x1UL)       /*!< Enable                                                               */
45379   #define IPCT_INTENSET0_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45380   #define IPCT_INTENSET0_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45381 
45382 /* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
45383   #define IPCT_INTENSET0_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
45384   #define IPCT_INTENSET0_RECEIVE12_Msk (0x1UL << IPCT_INTENSET0_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
45385   #define IPCT_INTENSET0_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
45386   #define IPCT_INTENSET0_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
45387   #define IPCT_INTENSET0_RECEIVE12_Set (0x1UL)       /*!< Enable                                                               */
45388   #define IPCT_INTENSET0_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45389   #define IPCT_INTENSET0_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45390 
45391 /* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
45392   #define IPCT_INTENSET0_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
45393   #define IPCT_INTENSET0_RECEIVE13_Msk (0x1UL << IPCT_INTENSET0_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
45394   #define IPCT_INTENSET0_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
45395   #define IPCT_INTENSET0_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
45396   #define IPCT_INTENSET0_RECEIVE13_Set (0x1UL)       /*!< Enable                                                               */
45397   #define IPCT_INTENSET0_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45398   #define IPCT_INTENSET0_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45399 
45400 /* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
45401   #define IPCT_INTENSET0_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
45402   #define IPCT_INTENSET0_RECEIVE14_Msk (0x1UL << IPCT_INTENSET0_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
45403   #define IPCT_INTENSET0_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
45404   #define IPCT_INTENSET0_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
45405   #define IPCT_INTENSET0_RECEIVE14_Set (0x1UL)       /*!< Enable                                                               */
45406   #define IPCT_INTENSET0_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45407   #define IPCT_INTENSET0_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45408 
45409 /* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
45410   #define IPCT_INTENSET0_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
45411   #define IPCT_INTENSET0_RECEIVE15_Msk (0x1UL << IPCT_INTENSET0_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
45412   #define IPCT_INTENSET0_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
45413   #define IPCT_INTENSET0_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
45414   #define IPCT_INTENSET0_RECEIVE15_Set (0x1UL)       /*!< Enable                                                               */
45415   #define IPCT_INTENSET0_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45416   #define IPCT_INTENSET0_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45417 
45418 /* ACKED0 @Bit 16 : Write '1' to enable interrupt for event ACKED[0] */
45419   #define IPCT_INTENSET0_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
45420   #define IPCT_INTENSET0_ACKED0_Msk (0x1UL << IPCT_INTENSET0_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
45421   #define IPCT_INTENSET0_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
45422   #define IPCT_INTENSET0_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
45423   #define IPCT_INTENSET0_ACKED0_Set (0x1UL)          /*!< Enable                                                               */
45424   #define IPCT_INTENSET0_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45425   #define IPCT_INTENSET0_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45426 
45427 /* ACKED1 @Bit 17 : Write '1' to enable interrupt for event ACKED[1] */
45428   #define IPCT_INTENSET0_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
45429   #define IPCT_INTENSET0_ACKED1_Msk (0x1UL << IPCT_INTENSET0_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
45430   #define IPCT_INTENSET0_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
45431   #define IPCT_INTENSET0_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
45432   #define IPCT_INTENSET0_ACKED1_Set (0x1UL)          /*!< Enable                                                               */
45433   #define IPCT_INTENSET0_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45434   #define IPCT_INTENSET0_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45435 
45436 /* ACKED2 @Bit 18 : Write '1' to enable interrupt for event ACKED[2] */
45437   #define IPCT_INTENSET0_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
45438   #define IPCT_INTENSET0_ACKED2_Msk (0x1UL << IPCT_INTENSET0_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
45439   #define IPCT_INTENSET0_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
45440   #define IPCT_INTENSET0_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
45441   #define IPCT_INTENSET0_ACKED2_Set (0x1UL)          /*!< Enable                                                               */
45442   #define IPCT_INTENSET0_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45443   #define IPCT_INTENSET0_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45444 
45445 /* ACKED3 @Bit 19 : Write '1' to enable interrupt for event ACKED[3] */
45446   #define IPCT_INTENSET0_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
45447   #define IPCT_INTENSET0_ACKED3_Msk (0x1UL << IPCT_INTENSET0_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
45448   #define IPCT_INTENSET0_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
45449   #define IPCT_INTENSET0_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
45450   #define IPCT_INTENSET0_ACKED3_Set (0x1UL)          /*!< Enable                                                               */
45451   #define IPCT_INTENSET0_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45452   #define IPCT_INTENSET0_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45453 
45454 /* ACKED4 @Bit 20 : Write '1' to enable interrupt for event ACKED[4] */
45455   #define IPCT_INTENSET0_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
45456   #define IPCT_INTENSET0_ACKED4_Msk (0x1UL << IPCT_INTENSET0_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
45457   #define IPCT_INTENSET0_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
45458   #define IPCT_INTENSET0_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
45459   #define IPCT_INTENSET0_ACKED4_Set (0x1UL)          /*!< Enable                                                               */
45460   #define IPCT_INTENSET0_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45461   #define IPCT_INTENSET0_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45462 
45463 /* ACKED5 @Bit 21 : Write '1' to enable interrupt for event ACKED[5] */
45464   #define IPCT_INTENSET0_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
45465   #define IPCT_INTENSET0_ACKED5_Msk (0x1UL << IPCT_INTENSET0_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
45466   #define IPCT_INTENSET0_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
45467   #define IPCT_INTENSET0_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
45468   #define IPCT_INTENSET0_ACKED5_Set (0x1UL)          /*!< Enable                                                               */
45469   #define IPCT_INTENSET0_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45470   #define IPCT_INTENSET0_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45471 
45472 /* ACKED6 @Bit 22 : Write '1' to enable interrupt for event ACKED[6] */
45473   #define IPCT_INTENSET0_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
45474   #define IPCT_INTENSET0_ACKED6_Msk (0x1UL << IPCT_INTENSET0_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
45475   #define IPCT_INTENSET0_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
45476   #define IPCT_INTENSET0_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
45477   #define IPCT_INTENSET0_ACKED6_Set (0x1UL)          /*!< Enable                                                               */
45478   #define IPCT_INTENSET0_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45479   #define IPCT_INTENSET0_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45480 
45481 /* ACKED7 @Bit 23 : Write '1' to enable interrupt for event ACKED[7] */
45482   #define IPCT_INTENSET0_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
45483   #define IPCT_INTENSET0_ACKED7_Msk (0x1UL << IPCT_INTENSET0_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
45484   #define IPCT_INTENSET0_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
45485   #define IPCT_INTENSET0_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
45486   #define IPCT_INTENSET0_ACKED7_Set (0x1UL)          /*!< Enable                                                               */
45487   #define IPCT_INTENSET0_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45488   #define IPCT_INTENSET0_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45489 
45490 /* ACKED8 @Bit 24 : Write '1' to enable interrupt for event ACKED[8] */
45491   #define IPCT_INTENSET0_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
45492   #define IPCT_INTENSET0_ACKED8_Msk (0x1UL << IPCT_INTENSET0_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
45493   #define IPCT_INTENSET0_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
45494   #define IPCT_INTENSET0_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
45495   #define IPCT_INTENSET0_ACKED8_Set (0x1UL)          /*!< Enable                                                               */
45496   #define IPCT_INTENSET0_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45497   #define IPCT_INTENSET0_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45498 
45499 /* ACKED9 @Bit 25 : Write '1' to enable interrupt for event ACKED[9] */
45500   #define IPCT_INTENSET0_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
45501   #define IPCT_INTENSET0_ACKED9_Msk (0x1UL << IPCT_INTENSET0_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
45502   #define IPCT_INTENSET0_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
45503   #define IPCT_INTENSET0_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
45504   #define IPCT_INTENSET0_ACKED9_Set (0x1UL)          /*!< Enable                                                               */
45505   #define IPCT_INTENSET0_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45506   #define IPCT_INTENSET0_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45507 
45508 /* ACKED10 @Bit 26 : Write '1' to enable interrupt for event ACKED[10] */
45509   #define IPCT_INTENSET0_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
45510   #define IPCT_INTENSET0_ACKED10_Msk (0x1UL << IPCT_INTENSET0_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
45511   #define IPCT_INTENSET0_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
45512   #define IPCT_INTENSET0_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
45513   #define IPCT_INTENSET0_ACKED10_Set (0x1UL)         /*!< Enable                                                               */
45514   #define IPCT_INTENSET0_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45515   #define IPCT_INTENSET0_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45516 
45517 /* ACKED11 @Bit 27 : Write '1' to enable interrupt for event ACKED[11] */
45518   #define IPCT_INTENSET0_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
45519   #define IPCT_INTENSET0_ACKED11_Msk (0x1UL << IPCT_INTENSET0_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
45520   #define IPCT_INTENSET0_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
45521   #define IPCT_INTENSET0_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
45522   #define IPCT_INTENSET0_ACKED11_Set (0x1UL)         /*!< Enable                                                               */
45523   #define IPCT_INTENSET0_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45524   #define IPCT_INTENSET0_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45525 
45526 /* ACKED12 @Bit 28 : Write '1' to enable interrupt for event ACKED[12] */
45527   #define IPCT_INTENSET0_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
45528   #define IPCT_INTENSET0_ACKED12_Msk (0x1UL << IPCT_INTENSET0_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
45529   #define IPCT_INTENSET0_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
45530   #define IPCT_INTENSET0_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
45531   #define IPCT_INTENSET0_ACKED12_Set (0x1UL)         /*!< Enable                                                               */
45532   #define IPCT_INTENSET0_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45533   #define IPCT_INTENSET0_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45534 
45535 /* ACKED13 @Bit 29 : Write '1' to enable interrupt for event ACKED[13] */
45536   #define IPCT_INTENSET0_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
45537   #define IPCT_INTENSET0_ACKED13_Msk (0x1UL << IPCT_INTENSET0_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
45538   #define IPCT_INTENSET0_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
45539   #define IPCT_INTENSET0_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
45540   #define IPCT_INTENSET0_ACKED13_Set (0x1UL)         /*!< Enable                                                               */
45541   #define IPCT_INTENSET0_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45542   #define IPCT_INTENSET0_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45543 
45544 /* ACKED14 @Bit 30 : Write '1' to enable interrupt for event ACKED[14] */
45545   #define IPCT_INTENSET0_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
45546   #define IPCT_INTENSET0_ACKED14_Msk (0x1UL << IPCT_INTENSET0_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
45547   #define IPCT_INTENSET0_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
45548   #define IPCT_INTENSET0_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
45549   #define IPCT_INTENSET0_ACKED14_Set (0x1UL)         /*!< Enable                                                               */
45550   #define IPCT_INTENSET0_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45551   #define IPCT_INTENSET0_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45552 
45553 /* ACKED15 @Bit 31 : Write '1' to enable interrupt for event ACKED[15] */
45554   #define IPCT_INTENSET0_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
45555   #define IPCT_INTENSET0_ACKED15_Msk (0x1UL << IPCT_INTENSET0_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
45556   #define IPCT_INTENSET0_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
45557   #define IPCT_INTENSET0_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
45558   #define IPCT_INTENSET0_ACKED15_Set (0x1UL)         /*!< Enable                                                               */
45559   #define IPCT_INTENSET0_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45560   #define IPCT_INTENSET0_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45561 
45562 
45563 /* IPCT_INTENCLR0: Disable interrupt */
45564   #define IPCT_INTENCLR0_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR0 register.                                   */
45565 
45566 /* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
45567   #define IPCT_INTENCLR0_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
45568   #define IPCT_INTENCLR0_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
45569   #define IPCT_INTENCLR0_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
45570   #define IPCT_INTENCLR0_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
45571   #define IPCT_INTENCLR0_RECEIVE0_Clear (0x1UL)      /*!< Disable                                                              */
45572   #define IPCT_INTENCLR0_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45573   #define IPCT_INTENCLR0_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45574 
45575 /* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
45576   #define IPCT_INTENCLR0_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
45577   #define IPCT_INTENCLR0_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
45578   #define IPCT_INTENCLR0_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
45579   #define IPCT_INTENCLR0_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
45580   #define IPCT_INTENCLR0_RECEIVE1_Clear (0x1UL)      /*!< Disable                                                              */
45581   #define IPCT_INTENCLR0_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45582   #define IPCT_INTENCLR0_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45583 
45584 /* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
45585   #define IPCT_INTENCLR0_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
45586   #define IPCT_INTENCLR0_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
45587   #define IPCT_INTENCLR0_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
45588   #define IPCT_INTENCLR0_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
45589   #define IPCT_INTENCLR0_RECEIVE2_Clear (0x1UL)      /*!< Disable                                                              */
45590   #define IPCT_INTENCLR0_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45591   #define IPCT_INTENCLR0_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45592 
45593 /* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
45594   #define IPCT_INTENCLR0_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
45595   #define IPCT_INTENCLR0_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
45596   #define IPCT_INTENCLR0_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
45597   #define IPCT_INTENCLR0_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
45598   #define IPCT_INTENCLR0_RECEIVE3_Clear (0x1UL)      /*!< Disable                                                              */
45599   #define IPCT_INTENCLR0_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45600   #define IPCT_INTENCLR0_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45601 
45602 /* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
45603   #define IPCT_INTENCLR0_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
45604   #define IPCT_INTENCLR0_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
45605   #define IPCT_INTENCLR0_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
45606   #define IPCT_INTENCLR0_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
45607   #define IPCT_INTENCLR0_RECEIVE4_Clear (0x1UL)      /*!< Disable                                                              */
45608   #define IPCT_INTENCLR0_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45609   #define IPCT_INTENCLR0_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45610 
45611 /* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
45612   #define IPCT_INTENCLR0_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
45613   #define IPCT_INTENCLR0_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
45614   #define IPCT_INTENCLR0_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
45615   #define IPCT_INTENCLR0_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
45616   #define IPCT_INTENCLR0_RECEIVE5_Clear (0x1UL)      /*!< Disable                                                              */
45617   #define IPCT_INTENCLR0_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45618   #define IPCT_INTENCLR0_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45619 
45620 /* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
45621   #define IPCT_INTENCLR0_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
45622   #define IPCT_INTENCLR0_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
45623   #define IPCT_INTENCLR0_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
45624   #define IPCT_INTENCLR0_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
45625   #define IPCT_INTENCLR0_RECEIVE6_Clear (0x1UL)      /*!< Disable                                                              */
45626   #define IPCT_INTENCLR0_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45627   #define IPCT_INTENCLR0_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45628 
45629 /* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
45630   #define IPCT_INTENCLR0_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
45631   #define IPCT_INTENCLR0_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
45632   #define IPCT_INTENCLR0_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
45633   #define IPCT_INTENCLR0_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
45634   #define IPCT_INTENCLR0_RECEIVE7_Clear (0x1UL)      /*!< Disable                                                              */
45635   #define IPCT_INTENCLR0_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45636   #define IPCT_INTENCLR0_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45637 
45638 /* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
45639   #define IPCT_INTENCLR0_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
45640   #define IPCT_INTENCLR0_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
45641   #define IPCT_INTENCLR0_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
45642   #define IPCT_INTENCLR0_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
45643   #define IPCT_INTENCLR0_RECEIVE8_Clear (0x1UL)      /*!< Disable                                                              */
45644   #define IPCT_INTENCLR0_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45645   #define IPCT_INTENCLR0_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45646 
45647 /* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
45648   #define IPCT_INTENCLR0_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
45649   #define IPCT_INTENCLR0_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
45650   #define IPCT_INTENCLR0_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
45651   #define IPCT_INTENCLR0_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
45652   #define IPCT_INTENCLR0_RECEIVE9_Clear (0x1UL)      /*!< Disable                                                              */
45653   #define IPCT_INTENCLR0_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
45654   #define IPCT_INTENCLR0_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
45655 
45656 /* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
45657   #define IPCT_INTENCLR0_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
45658   #define IPCT_INTENCLR0_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
45659   #define IPCT_INTENCLR0_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
45660   #define IPCT_INTENCLR0_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
45661   #define IPCT_INTENCLR0_RECEIVE10_Clear (0x1UL)     /*!< Disable                                                              */
45662   #define IPCT_INTENCLR0_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45663   #define IPCT_INTENCLR0_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45664 
45665 /* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
45666   #define IPCT_INTENCLR0_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
45667   #define IPCT_INTENCLR0_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
45668   #define IPCT_INTENCLR0_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
45669   #define IPCT_INTENCLR0_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
45670   #define IPCT_INTENCLR0_RECEIVE11_Clear (0x1UL)     /*!< Disable                                                              */
45671   #define IPCT_INTENCLR0_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45672   #define IPCT_INTENCLR0_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45673 
45674 /* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
45675   #define IPCT_INTENCLR0_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
45676   #define IPCT_INTENCLR0_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
45677   #define IPCT_INTENCLR0_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
45678   #define IPCT_INTENCLR0_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
45679   #define IPCT_INTENCLR0_RECEIVE12_Clear (0x1UL)     /*!< Disable                                                              */
45680   #define IPCT_INTENCLR0_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45681   #define IPCT_INTENCLR0_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45682 
45683 /* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
45684   #define IPCT_INTENCLR0_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
45685   #define IPCT_INTENCLR0_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
45686   #define IPCT_INTENCLR0_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
45687   #define IPCT_INTENCLR0_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
45688   #define IPCT_INTENCLR0_RECEIVE13_Clear (0x1UL)     /*!< Disable                                                              */
45689   #define IPCT_INTENCLR0_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45690   #define IPCT_INTENCLR0_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45691 
45692 /* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
45693   #define IPCT_INTENCLR0_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
45694   #define IPCT_INTENCLR0_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
45695   #define IPCT_INTENCLR0_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
45696   #define IPCT_INTENCLR0_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
45697   #define IPCT_INTENCLR0_RECEIVE14_Clear (0x1UL)     /*!< Disable                                                              */
45698   #define IPCT_INTENCLR0_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45699   #define IPCT_INTENCLR0_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45700 
45701 /* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
45702   #define IPCT_INTENCLR0_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
45703   #define IPCT_INTENCLR0_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR0_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
45704   #define IPCT_INTENCLR0_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
45705   #define IPCT_INTENCLR0_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
45706   #define IPCT_INTENCLR0_RECEIVE15_Clear (0x1UL)     /*!< Disable                                                              */
45707   #define IPCT_INTENCLR0_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
45708   #define IPCT_INTENCLR0_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
45709 
45710 /* ACKED0 @Bit 16 : Write '1' to disable interrupt for event ACKED[0] */
45711   #define IPCT_INTENCLR0_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
45712   #define IPCT_INTENCLR0_ACKED0_Msk (0x1UL << IPCT_INTENCLR0_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
45713   #define IPCT_INTENCLR0_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
45714   #define IPCT_INTENCLR0_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
45715   #define IPCT_INTENCLR0_ACKED0_Clear (0x1UL)        /*!< Disable                                                              */
45716   #define IPCT_INTENCLR0_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45717   #define IPCT_INTENCLR0_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45718 
45719 /* ACKED1 @Bit 17 : Write '1' to disable interrupt for event ACKED[1] */
45720   #define IPCT_INTENCLR0_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
45721   #define IPCT_INTENCLR0_ACKED1_Msk (0x1UL << IPCT_INTENCLR0_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
45722   #define IPCT_INTENCLR0_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
45723   #define IPCT_INTENCLR0_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
45724   #define IPCT_INTENCLR0_ACKED1_Clear (0x1UL)        /*!< Disable                                                              */
45725   #define IPCT_INTENCLR0_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45726   #define IPCT_INTENCLR0_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45727 
45728 /* ACKED2 @Bit 18 : Write '1' to disable interrupt for event ACKED[2] */
45729   #define IPCT_INTENCLR0_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
45730   #define IPCT_INTENCLR0_ACKED2_Msk (0x1UL << IPCT_INTENCLR0_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
45731   #define IPCT_INTENCLR0_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
45732   #define IPCT_INTENCLR0_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
45733   #define IPCT_INTENCLR0_ACKED2_Clear (0x1UL)        /*!< Disable                                                              */
45734   #define IPCT_INTENCLR0_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45735   #define IPCT_INTENCLR0_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45736 
45737 /* ACKED3 @Bit 19 : Write '1' to disable interrupt for event ACKED[3] */
45738   #define IPCT_INTENCLR0_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
45739   #define IPCT_INTENCLR0_ACKED3_Msk (0x1UL << IPCT_INTENCLR0_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
45740   #define IPCT_INTENCLR0_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
45741   #define IPCT_INTENCLR0_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
45742   #define IPCT_INTENCLR0_ACKED3_Clear (0x1UL)        /*!< Disable                                                              */
45743   #define IPCT_INTENCLR0_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45744   #define IPCT_INTENCLR0_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45745 
45746 /* ACKED4 @Bit 20 : Write '1' to disable interrupt for event ACKED[4] */
45747   #define IPCT_INTENCLR0_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
45748   #define IPCT_INTENCLR0_ACKED4_Msk (0x1UL << IPCT_INTENCLR0_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
45749   #define IPCT_INTENCLR0_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
45750   #define IPCT_INTENCLR0_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
45751   #define IPCT_INTENCLR0_ACKED4_Clear (0x1UL)        /*!< Disable                                                              */
45752   #define IPCT_INTENCLR0_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45753   #define IPCT_INTENCLR0_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45754 
45755 /* ACKED5 @Bit 21 : Write '1' to disable interrupt for event ACKED[5] */
45756   #define IPCT_INTENCLR0_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
45757   #define IPCT_INTENCLR0_ACKED5_Msk (0x1UL << IPCT_INTENCLR0_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
45758   #define IPCT_INTENCLR0_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
45759   #define IPCT_INTENCLR0_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
45760   #define IPCT_INTENCLR0_ACKED5_Clear (0x1UL)        /*!< Disable                                                              */
45761   #define IPCT_INTENCLR0_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45762   #define IPCT_INTENCLR0_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45763 
45764 /* ACKED6 @Bit 22 : Write '1' to disable interrupt for event ACKED[6] */
45765   #define IPCT_INTENCLR0_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
45766   #define IPCT_INTENCLR0_ACKED6_Msk (0x1UL << IPCT_INTENCLR0_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
45767   #define IPCT_INTENCLR0_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
45768   #define IPCT_INTENCLR0_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
45769   #define IPCT_INTENCLR0_ACKED6_Clear (0x1UL)        /*!< Disable                                                              */
45770   #define IPCT_INTENCLR0_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45771   #define IPCT_INTENCLR0_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45772 
45773 /* ACKED7 @Bit 23 : Write '1' to disable interrupt for event ACKED[7] */
45774   #define IPCT_INTENCLR0_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
45775   #define IPCT_INTENCLR0_ACKED7_Msk (0x1UL << IPCT_INTENCLR0_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
45776   #define IPCT_INTENCLR0_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
45777   #define IPCT_INTENCLR0_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
45778   #define IPCT_INTENCLR0_ACKED7_Clear (0x1UL)        /*!< Disable                                                              */
45779   #define IPCT_INTENCLR0_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45780   #define IPCT_INTENCLR0_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45781 
45782 /* ACKED8 @Bit 24 : Write '1' to disable interrupt for event ACKED[8] */
45783   #define IPCT_INTENCLR0_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
45784   #define IPCT_INTENCLR0_ACKED8_Msk (0x1UL << IPCT_INTENCLR0_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
45785   #define IPCT_INTENCLR0_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
45786   #define IPCT_INTENCLR0_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
45787   #define IPCT_INTENCLR0_ACKED8_Clear (0x1UL)        /*!< Disable                                                              */
45788   #define IPCT_INTENCLR0_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45789   #define IPCT_INTENCLR0_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45790 
45791 /* ACKED9 @Bit 25 : Write '1' to disable interrupt for event ACKED[9] */
45792   #define IPCT_INTENCLR0_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
45793   #define IPCT_INTENCLR0_ACKED9_Msk (0x1UL << IPCT_INTENCLR0_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
45794   #define IPCT_INTENCLR0_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
45795   #define IPCT_INTENCLR0_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
45796   #define IPCT_INTENCLR0_ACKED9_Clear (0x1UL)        /*!< Disable                                                              */
45797   #define IPCT_INTENCLR0_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
45798   #define IPCT_INTENCLR0_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
45799 
45800 /* ACKED10 @Bit 26 : Write '1' to disable interrupt for event ACKED[10] */
45801   #define IPCT_INTENCLR0_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
45802   #define IPCT_INTENCLR0_ACKED10_Msk (0x1UL << IPCT_INTENCLR0_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
45803   #define IPCT_INTENCLR0_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
45804   #define IPCT_INTENCLR0_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
45805   #define IPCT_INTENCLR0_ACKED10_Clear (0x1UL)       /*!< Disable                                                              */
45806   #define IPCT_INTENCLR0_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45807   #define IPCT_INTENCLR0_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45808 
45809 /* ACKED11 @Bit 27 : Write '1' to disable interrupt for event ACKED[11] */
45810   #define IPCT_INTENCLR0_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
45811   #define IPCT_INTENCLR0_ACKED11_Msk (0x1UL << IPCT_INTENCLR0_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
45812   #define IPCT_INTENCLR0_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
45813   #define IPCT_INTENCLR0_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
45814   #define IPCT_INTENCLR0_ACKED11_Clear (0x1UL)       /*!< Disable                                                              */
45815   #define IPCT_INTENCLR0_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45816   #define IPCT_INTENCLR0_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45817 
45818 /* ACKED12 @Bit 28 : Write '1' to disable interrupt for event ACKED[12] */
45819   #define IPCT_INTENCLR0_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
45820   #define IPCT_INTENCLR0_ACKED12_Msk (0x1UL << IPCT_INTENCLR0_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
45821   #define IPCT_INTENCLR0_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
45822   #define IPCT_INTENCLR0_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
45823   #define IPCT_INTENCLR0_ACKED12_Clear (0x1UL)       /*!< Disable                                                              */
45824   #define IPCT_INTENCLR0_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45825   #define IPCT_INTENCLR0_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45826 
45827 /* ACKED13 @Bit 29 : Write '1' to disable interrupt for event ACKED[13] */
45828   #define IPCT_INTENCLR0_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
45829   #define IPCT_INTENCLR0_ACKED13_Msk (0x1UL << IPCT_INTENCLR0_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
45830   #define IPCT_INTENCLR0_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
45831   #define IPCT_INTENCLR0_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
45832   #define IPCT_INTENCLR0_ACKED13_Clear (0x1UL)       /*!< Disable                                                              */
45833   #define IPCT_INTENCLR0_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45834   #define IPCT_INTENCLR0_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45835 
45836 /* ACKED14 @Bit 30 : Write '1' to disable interrupt for event ACKED[14] */
45837   #define IPCT_INTENCLR0_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
45838   #define IPCT_INTENCLR0_ACKED14_Msk (0x1UL << IPCT_INTENCLR0_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
45839   #define IPCT_INTENCLR0_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
45840   #define IPCT_INTENCLR0_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
45841   #define IPCT_INTENCLR0_ACKED14_Clear (0x1UL)       /*!< Disable                                                              */
45842   #define IPCT_INTENCLR0_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45843   #define IPCT_INTENCLR0_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45844 
45845 /* ACKED15 @Bit 31 : Write '1' to disable interrupt for event ACKED[15] */
45846   #define IPCT_INTENCLR0_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
45847   #define IPCT_INTENCLR0_ACKED15_Msk (0x1UL << IPCT_INTENCLR0_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
45848   #define IPCT_INTENCLR0_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
45849   #define IPCT_INTENCLR0_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
45850   #define IPCT_INTENCLR0_ACKED15_Clear (0x1UL)       /*!< Disable                                                              */
45851   #define IPCT_INTENCLR0_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
45852   #define IPCT_INTENCLR0_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
45853 
45854 
45855 /* IPCT_INTPEND0: Pending interrupts */
45856   #define IPCT_INTPEND0_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND0 register.                                    */
45857 
45858 /* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
45859   #define IPCT_INTPEND0_RECEIVE0_Pos (0UL)           /*!< Position of RECEIVE0 field.                                          */
45860   #define IPCT_INTPEND0_RECEIVE0_Msk (0x1UL << IPCT_INTPEND0_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                    */
45861   #define IPCT_INTPEND0_RECEIVE0_Min (0x0UL)         /*!< Min enumerator value of RECEIVE0 field.                              */
45862   #define IPCT_INTPEND0_RECEIVE0_Max (0x1UL)         /*!< Max enumerator value of RECEIVE0 field.                              */
45863   #define IPCT_INTPEND0_RECEIVE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45864   #define IPCT_INTPEND0_RECEIVE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
45865 
45866 /* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
45867   #define IPCT_INTPEND0_RECEIVE1_Pos (1UL)           /*!< Position of RECEIVE1 field.                                          */
45868   #define IPCT_INTPEND0_RECEIVE1_Msk (0x1UL << IPCT_INTPEND0_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                    */
45869   #define IPCT_INTPEND0_RECEIVE1_Min (0x0UL)         /*!< Min enumerator value of RECEIVE1 field.                              */
45870   #define IPCT_INTPEND0_RECEIVE1_Max (0x1UL)         /*!< Max enumerator value of RECEIVE1 field.                              */
45871   #define IPCT_INTPEND0_RECEIVE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45872   #define IPCT_INTPEND0_RECEIVE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
45873 
45874 /* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
45875   #define IPCT_INTPEND0_RECEIVE2_Pos (2UL)           /*!< Position of RECEIVE2 field.                                          */
45876   #define IPCT_INTPEND0_RECEIVE2_Msk (0x1UL << IPCT_INTPEND0_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                    */
45877   #define IPCT_INTPEND0_RECEIVE2_Min (0x0UL)         /*!< Min enumerator value of RECEIVE2 field.                              */
45878   #define IPCT_INTPEND0_RECEIVE2_Max (0x1UL)         /*!< Max enumerator value of RECEIVE2 field.                              */
45879   #define IPCT_INTPEND0_RECEIVE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45880   #define IPCT_INTPEND0_RECEIVE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
45881 
45882 /* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
45883   #define IPCT_INTPEND0_RECEIVE3_Pos (3UL)           /*!< Position of RECEIVE3 field.                                          */
45884   #define IPCT_INTPEND0_RECEIVE3_Msk (0x1UL << IPCT_INTPEND0_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                    */
45885   #define IPCT_INTPEND0_RECEIVE3_Min (0x0UL)         /*!< Min enumerator value of RECEIVE3 field.                              */
45886   #define IPCT_INTPEND0_RECEIVE3_Max (0x1UL)         /*!< Max enumerator value of RECEIVE3 field.                              */
45887   #define IPCT_INTPEND0_RECEIVE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45888   #define IPCT_INTPEND0_RECEIVE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
45889 
45890 /* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
45891   #define IPCT_INTPEND0_RECEIVE4_Pos (4UL)           /*!< Position of RECEIVE4 field.                                          */
45892   #define IPCT_INTPEND0_RECEIVE4_Msk (0x1UL << IPCT_INTPEND0_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                    */
45893   #define IPCT_INTPEND0_RECEIVE4_Min (0x0UL)         /*!< Min enumerator value of RECEIVE4 field.                              */
45894   #define IPCT_INTPEND0_RECEIVE4_Max (0x1UL)         /*!< Max enumerator value of RECEIVE4 field.                              */
45895   #define IPCT_INTPEND0_RECEIVE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45896   #define IPCT_INTPEND0_RECEIVE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
45897 
45898 /* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
45899   #define IPCT_INTPEND0_RECEIVE5_Pos (5UL)           /*!< Position of RECEIVE5 field.                                          */
45900   #define IPCT_INTPEND0_RECEIVE5_Msk (0x1UL << IPCT_INTPEND0_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                    */
45901   #define IPCT_INTPEND0_RECEIVE5_Min (0x0UL)         /*!< Min enumerator value of RECEIVE5 field.                              */
45902   #define IPCT_INTPEND0_RECEIVE5_Max (0x1UL)         /*!< Max enumerator value of RECEIVE5 field.                              */
45903   #define IPCT_INTPEND0_RECEIVE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45904   #define IPCT_INTPEND0_RECEIVE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
45905 
45906 /* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
45907   #define IPCT_INTPEND0_RECEIVE6_Pos (6UL)           /*!< Position of RECEIVE6 field.                                          */
45908   #define IPCT_INTPEND0_RECEIVE6_Msk (0x1UL << IPCT_INTPEND0_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                    */
45909   #define IPCT_INTPEND0_RECEIVE6_Min (0x0UL)         /*!< Min enumerator value of RECEIVE6 field.                              */
45910   #define IPCT_INTPEND0_RECEIVE6_Max (0x1UL)         /*!< Max enumerator value of RECEIVE6 field.                              */
45911   #define IPCT_INTPEND0_RECEIVE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45912   #define IPCT_INTPEND0_RECEIVE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
45913 
45914 /* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
45915   #define IPCT_INTPEND0_RECEIVE7_Pos (7UL)           /*!< Position of RECEIVE7 field.                                          */
45916   #define IPCT_INTPEND0_RECEIVE7_Msk (0x1UL << IPCT_INTPEND0_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                    */
45917   #define IPCT_INTPEND0_RECEIVE7_Min (0x0UL)         /*!< Min enumerator value of RECEIVE7 field.                              */
45918   #define IPCT_INTPEND0_RECEIVE7_Max (0x1UL)         /*!< Max enumerator value of RECEIVE7 field.                              */
45919   #define IPCT_INTPEND0_RECEIVE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45920   #define IPCT_INTPEND0_RECEIVE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
45921 
45922 /* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
45923   #define IPCT_INTPEND0_RECEIVE8_Pos (8UL)           /*!< Position of RECEIVE8 field.                                          */
45924   #define IPCT_INTPEND0_RECEIVE8_Msk (0x1UL << IPCT_INTPEND0_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                    */
45925   #define IPCT_INTPEND0_RECEIVE8_Min (0x0UL)         /*!< Min enumerator value of RECEIVE8 field.                              */
45926   #define IPCT_INTPEND0_RECEIVE8_Max (0x1UL)         /*!< Max enumerator value of RECEIVE8 field.                              */
45927   #define IPCT_INTPEND0_RECEIVE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45928   #define IPCT_INTPEND0_RECEIVE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
45929 
45930 /* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
45931   #define IPCT_INTPEND0_RECEIVE9_Pos (9UL)           /*!< Position of RECEIVE9 field.                                          */
45932   #define IPCT_INTPEND0_RECEIVE9_Msk (0x1UL << IPCT_INTPEND0_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                    */
45933   #define IPCT_INTPEND0_RECEIVE9_Min (0x0UL)         /*!< Min enumerator value of RECEIVE9 field.                              */
45934   #define IPCT_INTPEND0_RECEIVE9_Max (0x1UL)         /*!< Max enumerator value of RECEIVE9 field.                              */
45935   #define IPCT_INTPEND0_RECEIVE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
45936   #define IPCT_INTPEND0_RECEIVE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
45937 
45938 /* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
45939   #define IPCT_INTPEND0_RECEIVE10_Pos (10UL)         /*!< Position of RECEIVE10 field.                                         */
45940   #define IPCT_INTPEND0_RECEIVE10_Msk (0x1UL << IPCT_INTPEND0_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                 */
45941   #define IPCT_INTPEND0_RECEIVE10_Min (0x0UL)        /*!< Min enumerator value of RECEIVE10 field.                             */
45942   #define IPCT_INTPEND0_RECEIVE10_Max (0x1UL)        /*!< Max enumerator value of RECEIVE10 field.                             */
45943   #define IPCT_INTPEND0_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
45944   #define IPCT_INTPEND0_RECEIVE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
45945 
45946 /* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
45947   #define IPCT_INTPEND0_RECEIVE11_Pos (11UL)         /*!< Position of RECEIVE11 field.                                         */
45948   #define IPCT_INTPEND0_RECEIVE11_Msk (0x1UL << IPCT_INTPEND0_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                 */
45949   #define IPCT_INTPEND0_RECEIVE11_Min (0x0UL)        /*!< Min enumerator value of RECEIVE11 field.                             */
45950   #define IPCT_INTPEND0_RECEIVE11_Max (0x1UL)        /*!< Max enumerator value of RECEIVE11 field.                             */
45951   #define IPCT_INTPEND0_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
45952   #define IPCT_INTPEND0_RECEIVE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
45953 
45954 /* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
45955   #define IPCT_INTPEND0_RECEIVE12_Pos (12UL)         /*!< Position of RECEIVE12 field.                                         */
45956   #define IPCT_INTPEND0_RECEIVE12_Msk (0x1UL << IPCT_INTPEND0_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                 */
45957   #define IPCT_INTPEND0_RECEIVE12_Min (0x0UL)        /*!< Min enumerator value of RECEIVE12 field.                             */
45958   #define IPCT_INTPEND0_RECEIVE12_Max (0x1UL)        /*!< Max enumerator value of RECEIVE12 field.                             */
45959   #define IPCT_INTPEND0_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
45960   #define IPCT_INTPEND0_RECEIVE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
45961 
45962 /* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
45963   #define IPCT_INTPEND0_RECEIVE13_Pos (13UL)         /*!< Position of RECEIVE13 field.                                         */
45964   #define IPCT_INTPEND0_RECEIVE13_Msk (0x1UL << IPCT_INTPEND0_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                 */
45965   #define IPCT_INTPEND0_RECEIVE13_Min (0x0UL)        /*!< Min enumerator value of RECEIVE13 field.                             */
45966   #define IPCT_INTPEND0_RECEIVE13_Max (0x1UL)        /*!< Max enumerator value of RECEIVE13 field.                             */
45967   #define IPCT_INTPEND0_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
45968   #define IPCT_INTPEND0_RECEIVE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
45969 
45970 /* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
45971   #define IPCT_INTPEND0_RECEIVE14_Pos (14UL)         /*!< Position of RECEIVE14 field.                                         */
45972   #define IPCT_INTPEND0_RECEIVE14_Msk (0x1UL << IPCT_INTPEND0_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                 */
45973   #define IPCT_INTPEND0_RECEIVE14_Min (0x0UL)        /*!< Min enumerator value of RECEIVE14 field.                             */
45974   #define IPCT_INTPEND0_RECEIVE14_Max (0x1UL)        /*!< Max enumerator value of RECEIVE14 field.                             */
45975   #define IPCT_INTPEND0_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
45976   #define IPCT_INTPEND0_RECEIVE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
45977 
45978 /* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
45979   #define IPCT_INTPEND0_RECEIVE15_Pos (15UL)         /*!< Position of RECEIVE15 field.                                         */
45980   #define IPCT_INTPEND0_RECEIVE15_Msk (0x1UL << IPCT_INTPEND0_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                 */
45981   #define IPCT_INTPEND0_RECEIVE15_Min (0x0UL)        /*!< Min enumerator value of RECEIVE15 field.                             */
45982   #define IPCT_INTPEND0_RECEIVE15_Max (0x1UL)        /*!< Max enumerator value of RECEIVE15 field.                             */
45983   #define IPCT_INTPEND0_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
45984   #define IPCT_INTPEND0_RECEIVE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
45985 
45986 /* ACKED0 @Bit 16 : Read pending status of interrupt for event ACKED[0] */
45987   #define IPCT_INTPEND0_ACKED0_Pos (16UL)            /*!< Position of ACKED0 field.                                            */
45988   #define IPCT_INTPEND0_ACKED0_Msk (0x1UL << IPCT_INTPEND0_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                          */
45989   #define IPCT_INTPEND0_ACKED0_Min (0x0UL)           /*!< Min enumerator value of ACKED0 field.                                */
45990   #define IPCT_INTPEND0_ACKED0_Max (0x1UL)           /*!< Max enumerator value of ACKED0 field.                                */
45991   #define IPCT_INTPEND0_ACKED0_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
45992   #define IPCT_INTPEND0_ACKED0_Pending (0x1UL)       /*!< Read: Pending                                                        */
45993 
45994 /* ACKED1 @Bit 17 : Read pending status of interrupt for event ACKED[1] */
45995   #define IPCT_INTPEND0_ACKED1_Pos (17UL)            /*!< Position of ACKED1 field.                                            */
45996   #define IPCT_INTPEND0_ACKED1_Msk (0x1UL << IPCT_INTPEND0_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                          */
45997   #define IPCT_INTPEND0_ACKED1_Min (0x0UL)           /*!< Min enumerator value of ACKED1 field.                                */
45998   #define IPCT_INTPEND0_ACKED1_Max (0x1UL)           /*!< Max enumerator value of ACKED1 field.                                */
45999   #define IPCT_INTPEND0_ACKED1_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46000   #define IPCT_INTPEND0_ACKED1_Pending (0x1UL)       /*!< Read: Pending                                                        */
46001 
46002 /* ACKED2 @Bit 18 : Read pending status of interrupt for event ACKED[2] */
46003   #define IPCT_INTPEND0_ACKED2_Pos (18UL)            /*!< Position of ACKED2 field.                                            */
46004   #define IPCT_INTPEND0_ACKED2_Msk (0x1UL << IPCT_INTPEND0_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                          */
46005   #define IPCT_INTPEND0_ACKED2_Min (0x0UL)           /*!< Min enumerator value of ACKED2 field.                                */
46006   #define IPCT_INTPEND0_ACKED2_Max (0x1UL)           /*!< Max enumerator value of ACKED2 field.                                */
46007   #define IPCT_INTPEND0_ACKED2_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46008   #define IPCT_INTPEND0_ACKED2_Pending (0x1UL)       /*!< Read: Pending                                                        */
46009 
46010 /* ACKED3 @Bit 19 : Read pending status of interrupt for event ACKED[3] */
46011   #define IPCT_INTPEND0_ACKED3_Pos (19UL)            /*!< Position of ACKED3 field.                                            */
46012   #define IPCT_INTPEND0_ACKED3_Msk (0x1UL << IPCT_INTPEND0_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                          */
46013   #define IPCT_INTPEND0_ACKED3_Min (0x0UL)           /*!< Min enumerator value of ACKED3 field.                                */
46014   #define IPCT_INTPEND0_ACKED3_Max (0x1UL)           /*!< Max enumerator value of ACKED3 field.                                */
46015   #define IPCT_INTPEND0_ACKED3_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46016   #define IPCT_INTPEND0_ACKED3_Pending (0x1UL)       /*!< Read: Pending                                                        */
46017 
46018 /* ACKED4 @Bit 20 : Read pending status of interrupt for event ACKED[4] */
46019   #define IPCT_INTPEND0_ACKED4_Pos (20UL)            /*!< Position of ACKED4 field.                                            */
46020   #define IPCT_INTPEND0_ACKED4_Msk (0x1UL << IPCT_INTPEND0_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                          */
46021   #define IPCT_INTPEND0_ACKED4_Min (0x0UL)           /*!< Min enumerator value of ACKED4 field.                                */
46022   #define IPCT_INTPEND0_ACKED4_Max (0x1UL)           /*!< Max enumerator value of ACKED4 field.                                */
46023   #define IPCT_INTPEND0_ACKED4_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46024   #define IPCT_INTPEND0_ACKED4_Pending (0x1UL)       /*!< Read: Pending                                                        */
46025 
46026 /* ACKED5 @Bit 21 : Read pending status of interrupt for event ACKED[5] */
46027   #define IPCT_INTPEND0_ACKED5_Pos (21UL)            /*!< Position of ACKED5 field.                                            */
46028   #define IPCT_INTPEND0_ACKED5_Msk (0x1UL << IPCT_INTPEND0_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                          */
46029   #define IPCT_INTPEND0_ACKED5_Min (0x0UL)           /*!< Min enumerator value of ACKED5 field.                                */
46030   #define IPCT_INTPEND0_ACKED5_Max (0x1UL)           /*!< Max enumerator value of ACKED5 field.                                */
46031   #define IPCT_INTPEND0_ACKED5_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46032   #define IPCT_INTPEND0_ACKED5_Pending (0x1UL)       /*!< Read: Pending                                                        */
46033 
46034 /* ACKED6 @Bit 22 : Read pending status of interrupt for event ACKED[6] */
46035   #define IPCT_INTPEND0_ACKED6_Pos (22UL)            /*!< Position of ACKED6 field.                                            */
46036   #define IPCT_INTPEND0_ACKED6_Msk (0x1UL << IPCT_INTPEND0_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                          */
46037   #define IPCT_INTPEND0_ACKED6_Min (0x0UL)           /*!< Min enumerator value of ACKED6 field.                                */
46038   #define IPCT_INTPEND0_ACKED6_Max (0x1UL)           /*!< Max enumerator value of ACKED6 field.                                */
46039   #define IPCT_INTPEND0_ACKED6_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46040   #define IPCT_INTPEND0_ACKED6_Pending (0x1UL)       /*!< Read: Pending                                                        */
46041 
46042 /* ACKED7 @Bit 23 : Read pending status of interrupt for event ACKED[7] */
46043   #define IPCT_INTPEND0_ACKED7_Pos (23UL)            /*!< Position of ACKED7 field.                                            */
46044   #define IPCT_INTPEND0_ACKED7_Msk (0x1UL << IPCT_INTPEND0_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                          */
46045   #define IPCT_INTPEND0_ACKED7_Min (0x0UL)           /*!< Min enumerator value of ACKED7 field.                                */
46046   #define IPCT_INTPEND0_ACKED7_Max (0x1UL)           /*!< Max enumerator value of ACKED7 field.                                */
46047   #define IPCT_INTPEND0_ACKED7_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46048   #define IPCT_INTPEND0_ACKED7_Pending (0x1UL)       /*!< Read: Pending                                                        */
46049 
46050 /* ACKED8 @Bit 24 : Read pending status of interrupt for event ACKED[8] */
46051   #define IPCT_INTPEND0_ACKED8_Pos (24UL)            /*!< Position of ACKED8 field.                                            */
46052   #define IPCT_INTPEND0_ACKED8_Msk (0x1UL << IPCT_INTPEND0_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                          */
46053   #define IPCT_INTPEND0_ACKED8_Min (0x0UL)           /*!< Min enumerator value of ACKED8 field.                                */
46054   #define IPCT_INTPEND0_ACKED8_Max (0x1UL)           /*!< Max enumerator value of ACKED8 field.                                */
46055   #define IPCT_INTPEND0_ACKED8_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46056   #define IPCT_INTPEND0_ACKED8_Pending (0x1UL)       /*!< Read: Pending                                                        */
46057 
46058 /* ACKED9 @Bit 25 : Read pending status of interrupt for event ACKED[9] */
46059   #define IPCT_INTPEND0_ACKED9_Pos (25UL)            /*!< Position of ACKED9 field.                                            */
46060   #define IPCT_INTPEND0_ACKED9_Msk (0x1UL << IPCT_INTPEND0_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                          */
46061   #define IPCT_INTPEND0_ACKED9_Min (0x0UL)           /*!< Min enumerator value of ACKED9 field.                                */
46062   #define IPCT_INTPEND0_ACKED9_Max (0x1UL)           /*!< Max enumerator value of ACKED9 field.                                */
46063   #define IPCT_INTPEND0_ACKED9_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
46064   #define IPCT_INTPEND0_ACKED9_Pending (0x1UL)       /*!< Read: Pending                                                        */
46065 
46066 /* ACKED10 @Bit 26 : Read pending status of interrupt for event ACKED[10] */
46067   #define IPCT_INTPEND0_ACKED10_Pos (26UL)           /*!< Position of ACKED10 field.                                           */
46068   #define IPCT_INTPEND0_ACKED10_Msk (0x1UL << IPCT_INTPEND0_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                       */
46069   #define IPCT_INTPEND0_ACKED10_Min (0x0UL)          /*!< Min enumerator value of ACKED10 field.                               */
46070   #define IPCT_INTPEND0_ACKED10_Max (0x1UL)          /*!< Max enumerator value of ACKED10 field.                               */
46071   #define IPCT_INTPEND0_ACKED10_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
46072   #define IPCT_INTPEND0_ACKED10_Pending (0x1UL)      /*!< Read: Pending                                                        */
46073 
46074 /* ACKED11 @Bit 27 : Read pending status of interrupt for event ACKED[11] */
46075   #define IPCT_INTPEND0_ACKED11_Pos (27UL)           /*!< Position of ACKED11 field.                                           */
46076   #define IPCT_INTPEND0_ACKED11_Msk (0x1UL << IPCT_INTPEND0_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                       */
46077   #define IPCT_INTPEND0_ACKED11_Min (0x0UL)          /*!< Min enumerator value of ACKED11 field.                               */
46078   #define IPCT_INTPEND0_ACKED11_Max (0x1UL)          /*!< Max enumerator value of ACKED11 field.                               */
46079   #define IPCT_INTPEND0_ACKED11_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
46080   #define IPCT_INTPEND0_ACKED11_Pending (0x1UL)      /*!< Read: Pending                                                        */
46081 
46082 /* ACKED12 @Bit 28 : Read pending status of interrupt for event ACKED[12] */
46083   #define IPCT_INTPEND0_ACKED12_Pos (28UL)           /*!< Position of ACKED12 field.                                           */
46084   #define IPCT_INTPEND0_ACKED12_Msk (0x1UL << IPCT_INTPEND0_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                       */
46085   #define IPCT_INTPEND0_ACKED12_Min (0x0UL)          /*!< Min enumerator value of ACKED12 field.                               */
46086   #define IPCT_INTPEND0_ACKED12_Max (0x1UL)          /*!< Max enumerator value of ACKED12 field.                               */
46087   #define IPCT_INTPEND0_ACKED12_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
46088   #define IPCT_INTPEND0_ACKED12_Pending (0x1UL)      /*!< Read: Pending                                                        */
46089 
46090 /* ACKED13 @Bit 29 : Read pending status of interrupt for event ACKED[13] */
46091   #define IPCT_INTPEND0_ACKED13_Pos (29UL)           /*!< Position of ACKED13 field.                                           */
46092   #define IPCT_INTPEND0_ACKED13_Msk (0x1UL << IPCT_INTPEND0_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                       */
46093   #define IPCT_INTPEND0_ACKED13_Min (0x0UL)          /*!< Min enumerator value of ACKED13 field.                               */
46094   #define IPCT_INTPEND0_ACKED13_Max (0x1UL)          /*!< Max enumerator value of ACKED13 field.                               */
46095   #define IPCT_INTPEND0_ACKED13_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
46096   #define IPCT_INTPEND0_ACKED13_Pending (0x1UL)      /*!< Read: Pending                                                        */
46097 
46098 /* ACKED14 @Bit 30 : Read pending status of interrupt for event ACKED[14] */
46099   #define IPCT_INTPEND0_ACKED14_Pos (30UL)           /*!< Position of ACKED14 field.                                           */
46100   #define IPCT_INTPEND0_ACKED14_Msk (0x1UL << IPCT_INTPEND0_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                       */
46101   #define IPCT_INTPEND0_ACKED14_Min (0x0UL)          /*!< Min enumerator value of ACKED14 field.                               */
46102   #define IPCT_INTPEND0_ACKED14_Max (0x1UL)          /*!< Max enumerator value of ACKED14 field.                               */
46103   #define IPCT_INTPEND0_ACKED14_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
46104   #define IPCT_INTPEND0_ACKED14_Pending (0x1UL)      /*!< Read: Pending                                                        */
46105 
46106 /* ACKED15 @Bit 31 : Read pending status of interrupt for event ACKED[15] */
46107   #define IPCT_INTPEND0_ACKED15_Pos (31UL)           /*!< Position of ACKED15 field.                                           */
46108   #define IPCT_INTPEND0_ACKED15_Msk (0x1UL << IPCT_INTPEND0_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                       */
46109   #define IPCT_INTPEND0_ACKED15_Min (0x0UL)          /*!< Min enumerator value of ACKED15 field.                               */
46110   #define IPCT_INTPEND0_ACKED15_Max (0x1UL)          /*!< Max enumerator value of ACKED15 field.                               */
46111   #define IPCT_INTPEND0_ACKED15_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
46112   #define IPCT_INTPEND0_ACKED15_Pending (0x1UL)      /*!< Read: Pending                                                        */
46113 
46114 
46115 /* IPCT_INTEN1: Enable or disable interrupt */
46116   #define IPCT_INTEN1_ResetValue (0x00000000UL)      /*!< Reset value of INTEN1 register.                                      */
46117 
46118 /* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
46119   #define IPCT_INTEN1_RECEIVE0_Pos (0UL)             /*!< Position of RECEIVE0 field.                                          */
46120   #define IPCT_INTEN1_RECEIVE0_Msk (0x1UL << IPCT_INTEN1_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                        */
46121   #define IPCT_INTEN1_RECEIVE0_Min (0x0UL)           /*!< Min enumerator value of RECEIVE0 field.                              */
46122   #define IPCT_INTEN1_RECEIVE0_Max (0x1UL)           /*!< Max enumerator value of RECEIVE0 field.                              */
46123   #define IPCT_INTEN1_RECEIVE0_Disabled (0x0UL)      /*!< Disable                                                              */
46124   #define IPCT_INTEN1_RECEIVE0_Enabled (0x1UL)       /*!< Enable                                                               */
46125 
46126 /* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
46127   #define IPCT_INTEN1_RECEIVE1_Pos (1UL)             /*!< Position of RECEIVE1 field.                                          */
46128   #define IPCT_INTEN1_RECEIVE1_Msk (0x1UL << IPCT_INTEN1_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                        */
46129   #define IPCT_INTEN1_RECEIVE1_Min (0x0UL)           /*!< Min enumerator value of RECEIVE1 field.                              */
46130   #define IPCT_INTEN1_RECEIVE1_Max (0x1UL)           /*!< Max enumerator value of RECEIVE1 field.                              */
46131   #define IPCT_INTEN1_RECEIVE1_Disabled (0x0UL)      /*!< Disable                                                              */
46132   #define IPCT_INTEN1_RECEIVE1_Enabled (0x1UL)       /*!< Enable                                                               */
46133 
46134 /* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
46135   #define IPCT_INTEN1_RECEIVE2_Pos (2UL)             /*!< Position of RECEIVE2 field.                                          */
46136   #define IPCT_INTEN1_RECEIVE2_Msk (0x1UL << IPCT_INTEN1_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                        */
46137   #define IPCT_INTEN1_RECEIVE2_Min (0x0UL)           /*!< Min enumerator value of RECEIVE2 field.                              */
46138   #define IPCT_INTEN1_RECEIVE2_Max (0x1UL)           /*!< Max enumerator value of RECEIVE2 field.                              */
46139   #define IPCT_INTEN1_RECEIVE2_Disabled (0x0UL)      /*!< Disable                                                              */
46140   #define IPCT_INTEN1_RECEIVE2_Enabled (0x1UL)       /*!< Enable                                                               */
46141 
46142 /* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
46143   #define IPCT_INTEN1_RECEIVE3_Pos (3UL)             /*!< Position of RECEIVE3 field.                                          */
46144   #define IPCT_INTEN1_RECEIVE3_Msk (0x1UL << IPCT_INTEN1_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                        */
46145   #define IPCT_INTEN1_RECEIVE3_Min (0x0UL)           /*!< Min enumerator value of RECEIVE3 field.                              */
46146   #define IPCT_INTEN1_RECEIVE3_Max (0x1UL)           /*!< Max enumerator value of RECEIVE3 field.                              */
46147   #define IPCT_INTEN1_RECEIVE3_Disabled (0x0UL)      /*!< Disable                                                              */
46148   #define IPCT_INTEN1_RECEIVE3_Enabled (0x1UL)       /*!< Enable                                                               */
46149 
46150 /* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
46151   #define IPCT_INTEN1_RECEIVE4_Pos (4UL)             /*!< Position of RECEIVE4 field.                                          */
46152   #define IPCT_INTEN1_RECEIVE4_Msk (0x1UL << IPCT_INTEN1_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                        */
46153   #define IPCT_INTEN1_RECEIVE4_Min (0x0UL)           /*!< Min enumerator value of RECEIVE4 field.                              */
46154   #define IPCT_INTEN1_RECEIVE4_Max (0x1UL)           /*!< Max enumerator value of RECEIVE4 field.                              */
46155   #define IPCT_INTEN1_RECEIVE4_Disabled (0x0UL)      /*!< Disable                                                              */
46156   #define IPCT_INTEN1_RECEIVE4_Enabled (0x1UL)       /*!< Enable                                                               */
46157 
46158 /* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
46159   #define IPCT_INTEN1_RECEIVE5_Pos (5UL)             /*!< Position of RECEIVE5 field.                                          */
46160   #define IPCT_INTEN1_RECEIVE5_Msk (0x1UL << IPCT_INTEN1_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                        */
46161   #define IPCT_INTEN1_RECEIVE5_Min (0x0UL)           /*!< Min enumerator value of RECEIVE5 field.                              */
46162   #define IPCT_INTEN1_RECEIVE5_Max (0x1UL)           /*!< Max enumerator value of RECEIVE5 field.                              */
46163   #define IPCT_INTEN1_RECEIVE5_Disabled (0x0UL)      /*!< Disable                                                              */
46164   #define IPCT_INTEN1_RECEIVE5_Enabled (0x1UL)       /*!< Enable                                                               */
46165 
46166 /* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
46167   #define IPCT_INTEN1_RECEIVE6_Pos (6UL)             /*!< Position of RECEIVE6 field.                                          */
46168   #define IPCT_INTEN1_RECEIVE6_Msk (0x1UL << IPCT_INTEN1_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                        */
46169   #define IPCT_INTEN1_RECEIVE6_Min (0x0UL)           /*!< Min enumerator value of RECEIVE6 field.                              */
46170   #define IPCT_INTEN1_RECEIVE6_Max (0x1UL)           /*!< Max enumerator value of RECEIVE6 field.                              */
46171   #define IPCT_INTEN1_RECEIVE6_Disabled (0x0UL)      /*!< Disable                                                              */
46172   #define IPCT_INTEN1_RECEIVE6_Enabled (0x1UL)       /*!< Enable                                                               */
46173 
46174 /* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
46175   #define IPCT_INTEN1_RECEIVE7_Pos (7UL)             /*!< Position of RECEIVE7 field.                                          */
46176   #define IPCT_INTEN1_RECEIVE7_Msk (0x1UL << IPCT_INTEN1_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                        */
46177   #define IPCT_INTEN1_RECEIVE7_Min (0x0UL)           /*!< Min enumerator value of RECEIVE7 field.                              */
46178   #define IPCT_INTEN1_RECEIVE7_Max (0x1UL)           /*!< Max enumerator value of RECEIVE7 field.                              */
46179   #define IPCT_INTEN1_RECEIVE7_Disabled (0x0UL)      /*!< Disable                                                              */
46180   #define IPCT_INTEN1_RECEIVE7_Enabled (0x1UL)       /*!< Enable                                                               */
46181 
46182 /* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
46183   #define IPCT_INTEN1_RECEIVE8_Pos (8UL)             /*!< Position of RECEIVE8 field.                                          */
46184   #define IPCT_INTEN1_RECEIVE8_Msk (0x1UL << IPCT_INTEN1_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                        */
46185   #define IPCT_INTEN1_RECEIVE8_Min (0x0UL)           /*!< Min enumerator value of RECEIVE8 field.                              */
46186   #define IPCT_INTEN1_RECEIVE8_Max (0x1UL)           /*!< Max enumerator value of RECEIVE8 field.                              */
46187   #define IPCT_INTEN1_RECEIVE8_Disabled (0x0UL)      /*!< Disable                                                              */
46188   #define IPCT_INTEN1_RECEIVE8_Enabled (0x1UL)       /*!< Enable                                                               */
46189 
46190 /* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
46191   #define IPCT_INTEN1_RECEIVE9_Pos (9UL)             /*!< Position of RECEIVE9 field.                                          */
46192   #define IPCT_INTEN1_RECEIVE9_Msk (0x1UL << IPCT_INTEN1_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                        */
46193   #define IPCT_INTEN1_RECEIVE9_Min (0x0UL)           /*!< Min enumerator value of RECEIVE9 field.                              */
46194   #define IPCT_INTEN1_RECEIVE9_Max (0x1UL)           /*!< Max enumerator value of RECEIVE9 field.                              */
46195   #define IPCT_INTEN1_RECEIVE9_Disabled (0x0UL)      /*!< Disable                                                              */
46196   #define IPCT_INTEN1_RECEIVE9_Enabled (0x1UL)       /*!< Enable                                                               */
46197 
46198 /* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
46199   #define IPCT_INTEN1_RECEIVE10_Pos (10UL)           /*!< Position of RECEIVE10 field.                                         */
46200   #define IPCT_INTEN1_RECEIVE10_Msk (0x1UL << IPCT_INTEN1_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                     */
46201   #define IPCT_INTEN1_RECEIVE10_Min (0x0UL)          /*!< Min enumerator value of RECEIVE10 field.                             */
46202   #define IPCT_INTEN1_RECEIVE10_Max (0x1UL)          /*!< Max enumerator value of RECEIVE10 field.                             */
46203   #define IPCT_INTEN1_RECEIVE10_Disabled (0x0UL)     /*!< Disable                                                              */
46204   #define IPCT_INTEN1_RECEIVE10_Enabled (0x1UL)      /*!< Enable                                                               */
46205 
46206 /* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
46207   #define IPCT_INTEN1_RECEIVE11_Pos (11UL)           /*!< Position of RECEIVE11 field.                                         */
46208   #define IPCT_INTEN1_RECEIVE11_Msk (0x1UL << IPCT_INTEN1_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                     */
46209   #define IPCT_INTEN1_RECEIVE11_Min (0x0UL)          /*!< Min enumerator value of RECEIVE11 field.                             */
46210   #define IPCT_INTEN1_RECEIVE11_Max (0x1UL)          /*!< Max enumerator value of RECEIVE11 field.                             */
46211   #define IPCT_INTEN1_RECEIVE11_Disabled (0x0UL)     /*!< Disable                                                              */
46212   #define IPCT_INTEN1_RECEIVE11_Enabled (0x1UL)      /*!< Enable                                                               */
46213 
46214 /* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
46215   #define IPCT_INTEN1_RECEIVE12_Pos (12UL)           /*!< Position of RECEIVE12 field.                                         */
46216   #define IPCT_INTEN1_RECEIVE12_Msk (0x1UL << IPCT_INTEN1_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                     */
46217   #define IPCT_INTEN1_RECEIVE12_Min (0x0UL)          /*!< Min enumerator value of RECEIVE12 field.                             */
46218   #define IPCT_INTEN1_RECEIVE12_Max (0x1UL)          /*!< Max enumerator value of RECEIVE12 field.                             */
46219   #define IPCT_INTEN1_RECEIVE12_Disabled (0x0UL)     /*!< Disable                                                              */
46220   #define IPCT_INTEN1_RECEIVE12_Enabled (0x1UL)      /*!< Enable                                                               */
46221 
46222 /* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
46223   #define IPCT_INTEN1_RECEIVE13_Pos (13UL)           /*!< Position of RECEIVE13 field.                                         */
46224   #define IPCT_INTEN1_RECEIVE13_Msk (0x1UL << IPCT_INTEN1_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                     */
46225   #define IPCT_INTEN1_RECEIVE13_Min (0x0UL)          /*!< Min enumerator value of RECEIVE13 field.                             */
46226   #define IPCT_INTEN1_RECEIVE13_Max (0x1UL)          /*!< Max enumerator value of RECEIVE13 field.                             */
46227   #define IPCT_INTEN1_RECEIVE13_Disabled (0x0UL)     /*!< Disable                                                              */
46228   #define IPCT_INTEN1_RECEIVE13_Enabled (0x1UL)      /*!< Enable                                                               */
46229 
46230 /* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
46231   #define IPCT_INTEN1_RECEIVE14_Pos (14UL)           /*!< Position of RECEIVE14 field.                                         */
46232   #define IPCT_INTEN1_RECEIVE14_Msk (0x1UL << IPCT_INTEN1_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                     */
46233   #define IPCT_INTEN1_RECEIVE14_Min (0x0UL)          /*!< Min enumerator value of RECEIVE14 field.                             */
46234   #define IPCT_INTEN1_RECEIVE14_Max (0x1UL)          /*!< Max enumerator value of RECEIVE14 field.                             */
46235   #define IPCT_INTEN1_RECEIVE14_Disabled (0x0UL)     /*!< Disable                                                              */
46236   #define IPCT_INTEN1_RECEIVE14_Enabled (0x1UL)      /*!< Enable                                                               */
46237 
46238 /* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
46239   #define IPCT_INTEN1_RECEIVE15_Pos (15UL)           /*!< Position of RECEIVE15 field.                                         */
46240   #define IPCT_INTEN1_RECEIVE15_Msk (0x1UL << IPCT_INTEN1_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                     */
46241   #define IPCT_INTEN1_RECEIVE15_Min (0x0UL)          /*!< Min enumerator value of RECEIVE15 field.                             */
46242   #define IPCT_INTEN1_RECEIVE15_Max (0x1UL)          /*!< Max enumerator value of RECEIVE15 field.                             */
46243   #define IPCT_INTEN1_RECEIVE15_Disabled (0x0UL)     /*!< Disable                                                              */
46244   #define IPCT_INTEN1_RECEIVE15_Enabled (0x1UL)      /*!< Enable                                                               */
46245 
46246 /* ACKED0 @Bit 16 : Enable or disable interrupt for event ACKED[0] */
46247   #define IPCT_INTEN1_ACKED0_Pos (16UL)              /*!< Position of ACKED0 field.                                            */
46248   #define IPCT_INTEN1_ACKED0_Msk (0x1UL << IPCT_INTEN1_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                              */
46249   #define IPCT_INTEN1_ACKED0_Min (0x0UL)             /*!< Min enumerator value of ACKED0 field.                                */
46250   #define IPCT_INTEN1_ACKED0_Max (0x1UL)             /*!< Max enumerator value of ACKED0 field.                                */
46251   #define IPCT_INTEN1_ACKED0_Disabled (0x0UL)        /*!< Disable                                                              */
46252   #define IPCT_INTEN1_ACKED0_Enabled (0x1UL)         /*!< Enable                                                               */
46253 
46254 /* ACKED1 @Bit 17 : Enable or disable interrupt for event ACKED[1] */
46255   #define IPCT_INTEN1_ACKED1_Pos (17UL)              /*!< Position of ACKED1 field.                                            */
46256   #define IPCT_INTEN1_ACKED1_Msk (0x1UL << IPCT_INTEN1_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                              */
46257   #define IPCT_INTEN1_ACKED1_Min (0x0UL)             /*!< Min enumerator value of ACKED1 field.                                */
46258   #define IPCT_INTEN1_ACKED1_Max (0x1UL)             /*!< Max enumerator value of ACKED1 field.                                */
46259   #define IPCT_INTEN1_ACKED1_Disabled (0x0UL)        /*!< Disable                                                              */
46260   #define IPCT_INTEN1_ACKED1_Enabled (0x1UL)         /*!< Enable                                                               */
46261 
46262 /* ACKED2 @Bit 18 : Enable or disable interrupt for event ACKED[2] */
46263   #define IPCT_INTEN1_ACKED2_Pos (18UL)              /*!< Position of ACKED2 field.                                            */
46264   #define IPCT_INTEN1_ACKED2_Msk (0x1UL << IPCT_INTEN1_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                              */
46265   #define IPCT_INTEN1_ACKED2_Min (0x0UL)             /*!< Min enumerator value of ACKED2 field.                                */
46266   #define IPCT_INTEN1_ACKED2_Max (0x1UL)             /*!< Max enumerator value of ACKED2 field.                                */
46267   #define IPCT_INTEN1_ACKED2_Disabled (0x0UL)        /*!< Disable                                                              */
46268   #define IPCT_INTEN1_ACKED2_Enabled (0x1UL)         /*!< Enable                                                               */
46269 
46270 /* ACKED3 @Bit 19 : Enable or disable interrupt for event ACKED[3] */
46271   #define IPCT_INTEN1_ACKED3_Pos (19UL)              /*!< Position of ACKED3 field.                                            */
46272   #define IPCT_INTEN1_ACKED3_Msk (0x1UL << IPCT_INTEN1_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                              */
46273   #define IPCT_INTEN1_ACKED3_Min (0x0UL)             /*!< Min enumerator value of ACKED3 field.                                */
46274   #define IPCT_INTEN1_ACKED3_Max (0x1UL)             /*!< Max enumerator value of ACKED3 field.                                */
46275   #define IPCT_INTEN1_ACKED3_Disabled (0x0UL)        /*!< Disable                                                              */
46276   #define IPCT_INTEN1_ACKED3_Enabled (0x1UL)         /*!< Enable                                                               */
46277 
46278 /* ACKED4 @Bit 20 : Enable or disable interrupt for event ACKED[4] */
46279   #define IPCT_INTEN1_ACKED4_Pos (20UL)              /*!< Position of ACKED4 field.                                            */
46280   #define IPCT_INTEN1_ACKED4_Msk (0x1UL << IPCT_INTEN1_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                              */
46281   #define IPCT_INTEN1_ACKED4_Min (0x0UL)             /*!< Min enumerator value of ACKED4 field.                                */
46282   #define IPCT_INTEN1_ACKED4_Max (0x1UL)             /*!< Max enumerator value of ACKED4 field.                                */
46283   #define IPCT_INTEN1_ACKED4_Disabled (0x0UL)        /*!< Disable                                                              */
46284   #define IPCT_INTEN1_ACKED4_Enabled (0x1UL)         /*!< Enable                                                               */
46285 
46286 /* ACKED5 @Bit 21 : Enable or disable interrupt for event ACKED[5] */
46287   #define IPCT_INTEN1_ACKED5_Pos (21UL)              /*!< Position of ACKED5 field.                                            */
46288   #define IPCT_INTEN1_ACKED5_Msk (0x1UL << IPCT_INTEN1_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                              */
46289   #define IPCT_INTEN1_ACKED5_Min (0x0UL)             /*!< Min enumerator value of ACKED5 field.                                */
46290   #define IPCT_INTEN1_ACKED5_Max (0x1UL)             /*!< Max enumerator value of ACKED5 field.                                */
46291   #define IPCT_INTEN1_ACKED5_Disabled (0x0UL)        /*!< Disable                                                              */
46292   #define IPCT_INTEN1_ACKED5_Enabled (0x1UL)         /*!< Enable                                                               */
46293 
46294 /* ACKED6 @Bit 22 : Enable or disable interrupt for event ACKED[6] */
46295   #define IPCT_INTEN1_ACKED6_Pos (22UL)              /*!< Position of ACKED6 field.                                            */
46296   #define IPCT_INTEN1_ACKED6_Msk (0x1UL << IPCT_INTEN1_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                              */
46297   #define IPCT_INTEN1_ACKED6_Min (0x0UL)             /*!< Min enumerator value of ACKED6 field.                                */
46298   #define IPCT_INTEN1_ACKED6_Max (0x1UL)             /*!< Max enumerator value of ACKED6 field.                                */
46299   #define IPCT_INTEN1_ACKED6_Disabled (0x0UL)        /*!< Disable                                                              */
46300   #define IPCT_INTEN1_ACKED6_Enabled (0x1UL)         /*!< Enable                                                               */
46301 
46302 /* ACKED7 @Bit 23 : Enable or disable interrupt for event ACKED[7] */
46303   #define IPCT_INTEN1_ACKED7_Pos (23UL)              /*!< Position of ACKED7 field.                                            */
46304   #define IPCT_INTEN1_ACKED7_Msk (0x1UL << IPCT_INTEN1_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                              */
46305   #define IPCT_INTEN1_ACKED7_Min (0x0UL)             /*!< Min enumerator value of ACKED7 field.                                */
46306   #define IPCT_INTEN1_ACKED7_Max (0x1UL)             /*!< Max enumerator value of ACKED7 field.                                */
46307   #define IPCT_INTEN1_ACKED7_Disabled (0x0UL)        /*!< Disable                                                              */
46308   #define IPCT_INTEN1_ACKED7_Enabled (0x1UL)         /*!< Enable                                                               */
46309 
46310 /* ACKED8 @Bit 24 : Enable or disable interrupt for event ACKED[8] */
46311   #define IPCT_INTEN1_ACKED8_Pos (24UL)              /*!< Position of ACKED8 field.                                            */
46312   #define IPCT_INTEN1_ACKED8_Msk (0x1UL << IPCT_INTEN1_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                              */
46313   #define IPCT_INTEN1_ACKED8_Min (0x0UL)             /*!< Min enumerator value of ACKED8 field.                                */
46314   #define IPCT_INTEN1_ACKED8_Max (0x1UL)             /*!< Max enumerator value of ACKED8 field.                                */
46315   #define IPCT_INTEN1_ACKED8_Disabled (0x0UL)        /*!< Disable                                                              */
46316   #define IPCT_INTEN1_ACKED8_Enabled (0x1UL)         /*!< Enable                                                               */
46317 
46318 /* ACKED9 @Bit 25 : Enable or disable interrupt for event ACKED[9] */
46319   #define IPCT_INTEN1_ACKED9_Pos (25UL)              /*!< Position of ACKED9 field.                                            */
46320   #define IPCT_INTEN1_ACKED9_Msk (0x1UL << IPCT_INTEN1_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                              */
46321   #define IPCT_INTEN1_ACKED9_Min (0x0UL)             /*!< Min enumerator value of ACKED9 field.                                */
46322   #define IPCT_INTEN1_ACKED9_Max (0x1UL)             /*!< Max enumerator value of ACKED9 field.                                */
46323   #define IPCT_INTEN1_ACKED9_Disabled (0x0UL)        /*!< Disable                                                              */
46324   #define IPCT_INTEN1_ACKED9_Enabled (0x1UL)         /*!< Enable                                                               */
46325 
46326 /* ACKED10 @Bit 26 : Enable or disable interrupt for event ACKED[10] */
46327   #define IPCT_INTEN1_ACKED10_Pos (26UL)             /*!< Position of ACKED10 field.                                           */
46328   #define IPCT_INTEN1_ACKED10_Msk (0x1UL << IPCT_INTEN1_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                           */
46329   #define IPCT_INTEN1_ACKED10_Min (0x0UL)            /*!< Min enumerator value of ACKED10 field.                               */
46330   #define IPCT_INTEN1_ACKED10_Max (0x1UL)            /*!< Max enumerator value of ACKED10 field.                               */
46331   #define IPCT_INTEN1_ACKED10_Disabled (0x0UL)       /*!< Disable                                                              */
46332   #define IPCT_INTEN1_ACKED10_Enabled (0x1UL)        /*!< Enable                                                               */
46333 
46334 /* ACKED11 @Bit 27 : Enable or disable interrupt for event ACKED[11] */
46335   #define IPCT_INTEN1_ACKED11_Pos (27UL)             /*!< Position of ACKED11 field.                                           */
46336   #define IPCT_INTEN1_ACKED11_Msk (0x1UL << IPCT_INTEN1_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                           */
46337   #define IPCT_INTEN1_ACKED11_Min (0x0UL)            /*!< Min enumerator value of ACKED11 field.                               */
46338   #define IPCT_INTEN1_ACKED11_Max (0x1UL)            /*!< Max enumerator value of ACKED11 field.                               */
46339   #define IPCT_INTEN1_ACKED11_Disabled (0x0UL)       /*!< Disable                                                              */
46340   #define IPCT_INTEN1_ACKED11_Enabled (0x1UL)        /*!< Enable                                                               */
46341 
46342 /* ACKED12 @Bit 28 : Enable or disable interrupt for event ACKED[12] */
46343   #define IPCT_INTEN1_ACKED12_Pos (28UL)             /*!< Position of ACKED12 field.                                           */
46344   #define IPCT_INTEN1_ACKED12_Msk (0x1UL << IPCT_INTEN1_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                           */
46345   #define IPCT_INTEN1_ACKED12_Min (0x0UL)            /*!< Min enumerator value of ACKED12 field.                               */
46346   #define IPCT_INTEN1_ACKED12_Max (0x1UL)            /*!< Max enumerator value of ACKED12 field.                               */
46347   #define IPCT_INTEN1_ACKED12_Disabled (0x0UL)       /*!< Disable                                                              */
46348   #define IPCT_INTEN1_ACKED12_Enabled (0x1UL)        /*!< Enable                                                               */
46349 
46350 /* ACKED13 @Bit 29 : Enable or disable interrupt for event ACKED[13] */
46351   #define IPCT_INTEN1_ACKED13_Pos (29UL)             /*!< Position of ACKED13 field.                                           */
46352   #define IPCT_INTEN1_ACKED13_Msk (0x1UL << IPCT_INTEN1_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                           */
46353   #define IPCT_INTEN1_ACKED13_Min (0x0UL)            /*!< Min enumerator value of ACKED13 field.                               */
46354   #define IPCT_INTEN1_ACKED13_Max (0x1UL)            /*!< Max enumerator value of ACKED13 field.                               */
46355   #define IPCT_INTEN1_ACKED13_Disabled (0x0UL)       /*!< Disable                                                              */
46356   #define IPCT_INTEN1_ACKED13_Enabled (0x1UL)        /*!< Enable                                                               */
46357 
46358 /* ACKED14 @Bit 30 : Enable or disable interrupt for event ACKED[14] */
46359   #define IPCT_INTEN1_ACKED14_Pos (30UL)             /*!< Position of ACKED14 field.                                           */
46360   #define IPCT_INTEN1_ACKED14_Msk (0x1UL << IPCT_INTEN1_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                           */
46361   #define IPCT_INTEN1_ACKED14_Min (0x0UL)            /*!< Min enumerator value of ACKED14 field.                               */
46362   #define IPCT_INTEN1_ACKED14_Max (0x1UL)            /*!< Max enumerator value of ACKED14 field.                               */
46363   #define IPCT_INTEN1_ACKED14_Disabled (0x0UL)       /*!< Disable                                                              */
46364   #define IPCT_INTEN1_ACKED14_Enabled (0x1UL)        /*!< Enable                                                               */
46365 
46366 /* ACKED15 @Bit 31 : Enable or disable interrupt for event ACKED[15] */
46367   #define IPCT_INTEN1_ACKED15_Pos (31UL)             /*!< Position of ACKED15 field.                                           */
46368   #define IPCT_INTEN1_ACKED15_Msk (0x1UL << IPCT_INTEN1_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                           */
46369   #define IPCT_INTEN1_ACKED15_Min (0x0UL)            /*!< Min enumerator value of ACKED15 field.                               */
46370   #define IPCT_INTEN1_ACKED15_Max (0x1UL)            /*!< Max enumerator value of ACKED15 field.                               */
46371   #define IPCT_INTEN1_ACKED15_Disabled (0x0UL)       /*!< Disable                                                              */
46372   #define IPCT_INTEN1_ACKED15_Enabled (0x1UL)        /*!< Enable                                                               */
46373 
46374 
46375 /* IPCT_INTENSET1: Enable interrupt */
46376   #define IPCT_INTENSET1_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET1 register.                                   */
46377 
46378 /* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
46379   #define IPCT_INTENSET1_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
46380   #define IPCT_INTENSET1_RECEIVE0_Msk (0x1UL << IPCT_INTENSET1_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
46381   #define IPCT_INTENSET1_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
46382   #define IPCT_INTENSET1_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
46383   #define IPCT_INTENSET1_RECEIVE0_Set (0x1UL)        /*!< Enable                                                               */
46384   #define IPCT_INTENSET1_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46385   #define IPCT_INTENSET1_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46386 
46387 /* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
46388   #define IPCT_INTENSET1_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
46389   #define IPCT_INTENSET1_RECEIVE1_Msk (0x1UL << IPCT_INTENSET1_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
46390   #define IPCT_INTENSET1_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
46391   #define IPCT_INTENSET1_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
46392   #define IPCT_INTENSET1_RECEIVE1_Set (0x1UL)        /*!< Enable                                                               */
46393   #define IPCT_INTENSET1_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46394   #define IPCT_INTENSET1_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46395 
46396 /* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
46397   #define IPCT_INTENSET1_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
46398   #define IPCT_INTENSET1_RECEIVE2_Msk (0x1UL << IPCT_INTENSET1_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
46399   #define IPCT_INTENSET1_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
46400   #define IPCT_INTENSET1_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
46401   #define IPCT_INTENSET1_RECEIVE2_Set (0x1UL)        /*!< Enable                                                               */
46402   #define IPCT_INTENSET1_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46403   #define IPCT_INTENSET1_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46404 
46405 /* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
46406   #define IPCT_INTENSET1_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
46407   #define IPCT_INTENSET1_RECEIVE3_Msk (0x1UL << IPCT_INTENSET1_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
46408   #define IPCT_INTENSET1_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
46409   #define IPCT_INTENSET1_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
46410   #define IPCT_INTENSET1_RECEIVE3_Set (0x1UL)        /*!< Enable                                                               */
46411   #define IPCT_INTENSET1_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46412   #define IPCT_INTENSET1_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46413 
46414 /* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
46415   #define IPCT_INTENSET1_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
46416   #define IPCT_INTENSET1_RECEIVE4_Msk (0x1UL << IPCT_INTENSET1_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
46417   #define IPCT_INTENSET1_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
46418   #define IPCT_INTENSET1_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
46419   #define IPCT_INTENSET1_RECEIVE4_Set (0x1UL)        /*!< Enable                                                               */
46420   #define IPCT_INTENSET1_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46421   #define IPCT_INTENSET1_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46422 
46423 /* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
46424   #define IPCT_INTENSET1_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
46425   #define IPCT_INTENSET1_RECEIVE5_Msk (0x1UL << IPCT_INTENSET1_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
46426   #define IPCT_INTENSET1_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
46427   #define IPCT_INTENSET1_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
46428   #define IPCT_INTENSET1_RECEIVE5_Set (0x1UL)        /*!< Enable                                                               */
46429   #define IPCT_INTENSET1_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46430   #define IPCT_INTENSET1_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46431 
46432 /* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
46433   #define IPCT_INTENSET1_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
46434   #define IPCT_INTENSET1_RECEIVE6_Msk (0x1UL << IPCT_INTENSET1_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
46435   #define IPCT_INTENSET1_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
46436   #define IPCT_INTENSET1_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
46437   #define IPCT_INTENSET1_RECEIVE6_Set (0x1UL)        /*!< Enable                                                               */
46438   #define IPCT_INTENSET1_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46439   #define IPCT_INTENSET1_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46440 
46441 /* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
46442   #define IPCT_INTENSET1_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
46443   #define IPCT_INTENSET1_RECEIVE7_Msk (0x1UL << IPCT_INTENSET1_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
46444   #define IPCT_INTENSET1_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
46445   #define IPCT_INTENSET1_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
46446   #define IPCT_INTENSET1_RECEIVE7_Set (0x1UL)        /*!< Enable                                                               */
46447   #define IPCT_INTENSET1_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46448   #define IPCT_INTENSET1_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46449 
46450 /* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
46451   #define IPCT_INTENSET1_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
46452   #define IPCT_INTENSET1_RECEIVE8_Msk (0x1UL << IPCT_INTENSET1_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
46453   #define IPCT_INTENSET1_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
46454   #define IPCT_INTENSET1_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
46455   #define IPCT_INTENSET1_RECEIVE8_Set (0x1UL)        /*!< Enable                                                               */
46456   #define IPCT_INTENSET1_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46457   #define IPCT_INTENSET1_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46458 
46459 /* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
46460   #define IPCT_INTENSET1_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
46461   #define IPCT_INTENSET1_RECEIVE9_Msk (0x1UL << IPCT_INTENSET1_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
46462   #define IPCT_INTENSET1_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
46463   #define IPCT_INTENSET1_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
46464   #define IPCT_INTENSET1_RECEIVE9_Set (0x1UL)        /*!< Enable                                                               */
46465   #define IPCT_INTENSET1_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46466   #define IPCT_INTENSET1_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46467 
46468 /* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
46469   #define IPCT_INTENSET1_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
46470   #define IPCT_INTENSET1_RECEIVE10_Msk (0x1UL << IPCT_INTENSET1_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
46471   #define IPCT_INTENSET1_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
46472   #define IPCT_INTENSET1_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
46473   #define IPCT_INTENSET1_RECEIVE10_Set (0x1UL)       /*!< Enable                                                               */
46474   #define IPCT_INTENSET1_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46475   #define IPCT_INTENSET1_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46476 
46477 /* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
46478   #define IPCT_INTENSET1_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
46479   #define IPCT_INTENSET1_RECEIVE11_Msk (0x1UL << IPCT_INTENSET1_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
46480   #define IPCT_INTENSET1_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
46481   #define IPCT_INTENSET1_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
46482   #define IPCT_INTENSET1_RECEIVE11_Set (0x1UL)       /*!< Enable                                                               */
46483   #define IPCT_INTENSET1_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46484   #define IPCT_INTENSET1_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46485 
46486 /* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
46487   #define IPCT_INTENSET1_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
46488   #define IPCT_INTENSET1_RECEIVE12_Msk (0x1UL << IPCT_INTENSET1_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
46489   #define IPCT_INTENSET1_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
46490   #define IPCT_INTENSET1_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
46491   #define IPCT_INTENSET1_RECEIVE12_Set (0x1UL)       /*!< Enable                                                               */
46492   #define IPCT_INTENSET1_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46493   #define IPCT_INTENSET1_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46494 
46495 /* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
46496   #define IPCT_INTENSET1_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
46497   #define IPCT_INTENSET1_RECEIVE13_Msk (0x1UL << IPCT_INTENSET1_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
46498   #define IPCT_INTENSET1_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
46499   #define IPCT_INTENSET1_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
46500   #define IPCT_INTENSET1_RECEIVE13_Set (0x1UL)       /*!< Enable                                                               */
46501   #define IPCT_INTENSET1_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46502   #define IPCT_INTENSET1_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46503 
46504 /* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
46505   #define IPCT_INTENSET1_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
46506   #define IPCT_INTENSET1_RECEIVE14_Msk (0x1UL << IPCT_INTENSET1_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
46507   #define IPCT_INTENSET1_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
46508   #define IPCT_INTENSET1_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
46509   #define IPCT_INTENSET1_RECEIVE14_Set (0x1UL)       /*!< Enable                                                               */
46510   #define IPCT_INTENSET1_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46511   #define IPCT_INTENSET1_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46512 
46513 /* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
46514   #define IPCT_INTENSET1_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
46515   #define IPCT_INTENSET1_RECEIVE15_Msk (0x1UL << IPCT_INTENSET1_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
46516   #define IPCT_INTENSET1_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
46517   #define IPCT_INTENSET1_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
46518   #define IPCT_INTENSET1_RECEIVE15_Set (0x1UL)       /*!< Enable                                                               */
46519   #define IPCT_INTENSET1_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46520   #define IPCT_INTENSET1_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46521 
46522 /* ACKED0 @Bit 16 : Write '1' to enable interrupt for event ACKED[0] */
46523   #define IPCT_INTENSET1_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
46524   #define IPCT_INTENSET1_ACKED0_Msk (0x1UL << IPCT_INTENSET1_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
46525   #define IPCT_INTENSET1_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
46526   #define IPCT_INTENSET1_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
46527   #define IPCT_INTENSET1_ACKED0_Set (0x1UL)          /*!< Enable                                                               */
46528   #define IPCT_INTENSET1_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46529   #define IPCT_INTENSET1_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46530 
46531 /* ACKED1 @Bit 17 : Write '1' to enable interrupt for event ACKED[1] */
46532   #define IPCT_INTENSET1_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
46533   #define IPCT_INTENSET1_ACKED1_Msk (0x1UL << IPCT_INTENSET1_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
46534   #define IPCT_INTENSET1_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
46535   #define IPCT_INTENSET1_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
46536   #define IPCT_INTENSET1_ACKED1_Set (0x1UL)          /*!< Enable                                                               */
46537   #define IPCT_INTENSET1_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46538   #define IPCT_INTENSET1_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46539 
46540 /* ACKED2 @Bit 18 : Write '1' to enable interrupt for event ACKED[2] */
46541   #define IPCT_INTENSET1_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
46542   #define IPCT_INTENSET1_ACKED2_Msk (0x1UL << IPCT_INTENSET1_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
46543   #define IPCT_INTENSET1_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
46544   #define IPCT_INTENSET1_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
46545   #define IPCT_INTENSET1_ACKED2_Set (0x1UL)          /*!< Enable                                                               */
46546   #define IPCT_INTENSET1_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46547   #define IPCT_INTENSET1_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46548 
46549 /* ACKED3 @Bit 19 : Write '1' to enable interrupt for event ACKED[3] */
46550   #define IPCT_INTENSET1_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
46551   #define IPCT_INTENSET1_ACKED3_Msk (0x1UL << IPCT_INTENSET1_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
46552   #define IPCT_INTENSET1_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
46553   #define IPCT_INTENSET1_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
46554   #define IPCT_INTENSET1_ACKED3_Set (0x1UL)          /*!< Enable                                                               */
46555   #define IPCT_INTENSET1_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46556   #define IPCT_INTENSET1_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46557 
46558 /* ACKED4 @Bit 20 : Write '1' to enable interrupt for event ACKED[4] */
46559   #define IPCT_INTENSET1_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
46560   #define IPCT_INTENSET1_ACKED4_Msk (0x1UL << IPCT_INTENSET1_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
46561   #define IPCT_INTENSET1_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
46562   #define IPCT_INTENSET1_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
46563   #define IPCT_INTENSET1_ACKED4_Set (0x1UL)          /*!< Enable                                                               */
46564   #define IPCT_INTENSET1_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46565   #define IPCT_INTENSET1_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46566 
46567 /* ACKED5 @Bit 21 : Write '1' to enable interrupt for event ACKED[5] */
46568   #define IPCT_INTENSET1_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
46569   #define IPCT_INTENSET1_ACKED5_Msk (0x1UL << IPCT_INTENSET1_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
46570   #define IPCT_INTENSET1_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
46571   #define IPCT_INTENSET1_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
46572   #define IPCT_INTENSET1_ACKED5_Set (0x1UL)          /*!< Enable                                                               */
46573   #define IPCT_INTENSET1_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46574   #define IPCT_INTENSET1_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46575 
46576 /* ACKED6 @Bit 22 : Write '1' to enable interrupt for event ACKED[6] */
46577   #define IPCT_INTENSET1_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
46578   #define IPCT_INTENSET1_ACKED6_Msk (0x1UL << IPCT_INTENSET1_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
46579   #define IPCT_INTENSET1_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
46580   #define IPCT_INTENSET1_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
46581   #define IPCT_INTENSET1_ACKED6_Set (0x1UL)          /*!< Enable                                                               */
46582   #define IPCT_INTENSET1_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46583   #define IPCT_INTENSET1_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46584 
46585 /* ACKED7 @Bit 23 : Write '1' to enable interrupt for event ACKED[7] */
46586   #define IPCT_INTENSET1_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
46587   #define IPCT_INTENSET1_ACKED7_Msk (0x1UL << IPCT_INTENSET1_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
46588   #define IPCT_INTENSET1_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
46589   #define IPCT_INTENSET1_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
46590   #define IPCT_INTENSET1_ACKED7_Set (0x1UL)          /*!< Enable                                                               */
46591   #define IPCT_INTENSET1_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46592   #define IPCT_INTENSET1_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46593 
46594 /* ACKED8 @Bit 24 : Write '1' to enable interrupt for event ACKED[8] */
46595   #define IPCT_INTENSET1_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
46596   #define IPCT_INTENSET1_ACKED8_Msk (0x1UL << IPCT_INTENSET1_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
46597   #define IPCT_INTENSET1_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
46598   #define IPCT_INTENSET1_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
46599   #define IPCT_INTENSET1_ACKED8_Set (0x1UL)          /*!< Enable                                                               */
46600   #define IPCT_INTENSET1_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46601   #define IPCT_INTENSET1_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46602 
46603 /* ACKED9 @Bit 25 : Write '1' to enable interrupt for event ACKED[9] */
46604   #define IPCT_INTENSET1_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
46605   #define IPCT_INTENSET1_ACKED9_Msk (0x1UL << IPCT_INTENSET1_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
46606   #define IPCT_INTENSET1_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
46607   #define IPCT_INTENSET1_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
46608   #define IPCT_INTENSET1_ACKED9_Set (0x1UL)          /*!< Enable                                                               */
46609   #define IPCT_INTENSET1_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46610   #define IPCT_INTENSET1_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46611 
46612 /* ACKED10 @Bit 26 : Write '1' to enable interrupt for event ACKED[10] */
46613   #define IPCT_INTENSET1_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
46614   #define IPCT_INTENSET1_ACKED10_Msk (0x1UL << IPCT_INTENSET1_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
46615   #define IPCT_INTENSET1_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
46616   #define IPCT_INTENSET1_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
46617   #define IPCT_INTENSET1_ACKED10_Set (0x1UL)         /*!< Enable                                                               */
46618   #define IPCT_INTENSET1_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46619   #define IPCT_INTENSET1_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46620 
46621 /* ACKED11 @Bit 27 : Write '1' to enable interrupt for event ACKED[11] */
46622   #define IPCT_INTENSET1_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
46623   #define IPCT_INTENSET1_ACKED11_Msk (0x1UL << IPCT_INTENSET1_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
46624   #define IPCT_INTENSET1_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
46625   #define IPCT_INTENSET1_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
46626   #define IPCT_INTENSET1_ACKED11_Set (0x1UL)         /*!< Enable                                                               */
46627   #define IPCT_INTENSET1_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46628   #define IPCT_INTENSET1_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46629 
46630 /* ACKED12 @Bit 28 : Write '1' to enable interrupt for event ACKED[12] */
46631   #define IPCT_INTENSET1_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
46632   #define IPCT_INTENSET1_ACKED12_Msk (0x1UL << IPCT_INTENSET1_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
46633   #define IPCT_INTENSET1_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
46634   #define IPCT_INTENSET1_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
46635   #define IPCT_INTENSET1_ACKED12_Set (0x1UL)         /*!< Enable                                                               */
46636   #define IPCT_INTENSET1_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46637   #define IPCT_INTENSET1_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46638 
46639 /* ACKED13 @Bit 29 : Write '1' to enable interrupt for event ACKED[13] */
46640   #define IPCT_INTENSET1_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
46641   #define IPCT_INTENSET1_ACKED13_Msk (0x1UL << IPCT_INTENSET1_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
46642   #define IPCT_INTENSET1_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
46643   #define IPCT_INTENSET1_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
46644   #define IPCT_INTENSET1_ACKED13_Set (0x1UL)         /*!< Enable                                                               */
46645   #define IPCT_INTENSET1_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46646   #define IPCT_INTENSET1_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46647 
46648 /* ACKED14 @Bit 30 : Write '1' to enable interrupt for event ACKED[14] */
46649   #define IPCT_INTENSET1_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
46650   #define IPCT_INTENSET1_ACKED14_Msk (0x1UL << IPCT_INTENSET1_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
46651   #define IPCT_INTENSET1_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
46652   #define IPCT_INTENSET1_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
46653   #define IPCT_INTENSET1_ACKED14_Set (0x1UL)         /*!< Enable                                                               */
46654   #define IPCT_INTENSET1_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46655   #define IPCT_INTENSET1_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46656 
46657 /* ACKED15 @Bit 31 : Write '1' to enable interrupt for event ACKED[15] */
46658   #define IPCT_INTENSET1_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
46659   #define IPCT_INTENSET1_ACKED15_Msk (0x1UL << IPCT_INTENSET1_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
46660   #define IPCT_INTENSET1_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
46661   #define IPCT_INTENSET1_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
46662   #define IPCT_INTENSET1_ACKED15_Set (0x1UL)         /*!< Enable                                                               */
46663   #define IPCT_INTENSET1_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46664   #define IPCT_INTENSET1_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46665 
46666 
46667 /* IPCT_INTENCLR1: Disable interrupt */
46668   #define IPCT_INTENCLR1_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR1 register.                                   */
46669 
46670 /* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
46671   #define IPCT_INTENCLR1_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
46672   #define IPCT_INTENCLR1_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
46673   #define IPCT_INTENCLR1_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
46674   #define IPCT_INTENCLR1_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
46675   #define IPCT_INTENCLR1_RECEIVE0_Clear (0x1UL)      /*!< Disable                                                              */
46676   #define IPCT_INTENCLR1_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46677   #define IPCT_INTENCLR1_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46678 
46679 /* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
46680   #define IPCT_INTENCLR1_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
46681   #define IPCT_INTENCLR1_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
46682   #define IPCT_INTENCLR1_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
46683   #define IPCT_INTENCLR1_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
46684   #define IPCT_INTENCLR1_RECEIVE1_Clear (0x1UL)      /*!< Disable                                                              */
46685   #define IPCT_INTENCLR1_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46686   #define IPCT_INTENCLR1_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46687 
46688 /* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
46689   #define IPCT_INTENCLR1_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
46690   #define IPCT_INTENCLR1_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
46691   #define IPCT_INTENCLR1_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
46692   #define IPCT_INTENCLR1_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
46693   #define IPCT_INTENCLR1_RECEIVE2_Clear (0x1UL)      /*!< Disable                                                              */
46694   #define IPCT_INTENCLR1_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46695   #define IPCT_INTENCLR1_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46696 
46697 /* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
46698   #define IPCT_INTENCLR1_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
46699   #define IPCT_INTENCLR1_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
46700   #define IPCT_INTENCLR1_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
46701   #define IPCT_INTENCLR1_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
46702   #define IPCT_INTENCLR1_RECEIVE3_Clear (0x1UL)      /*!< Disable                                                              */
46703   #define IPCT_INTENCLR1_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46704   #define IPCT_INTENCLR1_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46705 
46706 /* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
46707   #define IPCT_INTENCLR1_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
46708   #define IPCT_INTENCLR1_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
46709   #define IPCT_INTENCLR1_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
46710   #define IPCT_INTENCLR1_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
46711   #define IPCT_INTENCLR1_RECEIVE4_Clear (0x1UL)      /*!< Disable                                                              */
46712   #define IPCT_INTENCLR1_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46713   #define IPCT_INTENCLR1_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46714 
46715 /* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
46716   #define IPCT_INTENCLR1_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
46717   #define IPCT_INTENCLR1_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
46718   #define IPCT_INTENCLR1_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
46719   #define IPCT_INTENCLR1_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
46720   #define IPCT_INTENCLR1_RECEIVE5_Clear (0x1UL)      /*!< Disable                                                              */
46721   #define IPCT_INTENCLR1_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46722   #define IPCT_INTENCLR1_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46723 
46724 /* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
46725   #define IPCT_INTENCLR1_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
46726   #define IPCT_INTENCLR1_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
46727   #define IPCT_INTENCLR1_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
46728   #define IPCT_INTENCLR1_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
46729   #define IPCT_INTENCLR1_RECEIVE6_Clear (0x1UL)      /*!< Disable                                                              */
46730   #define IPCT_INTENCLR1_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46731   #define IPCT_INTENCLR1_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46732 
46733 /* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
46734   #define IPCT_INTENCLR1_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
46735   #define IPCT_INTENCLR1_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
46736   #define IPCT_INTENCLR1_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
46737   #define IPCT_INTENCLR1_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
46738   #define IPCT_INTENCLR1_RECEIVE7_Clear (0x1UL)      /*!< Disable                                                              */
46739   #define IPCT_INTENCLR1_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46740   #define IPCT_INTENCLR1_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46741 
46742 /* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
46743   #define IPCT_INTENCLR1_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
46744   #define IPCT_INTENCLR1_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
46745   #define IPCT_INTENCLR1_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
46746   #define IPCT_INTENCLR1_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
46747   #define IPCT_INTENCLR1_RECEIVE8_Clear (0x1UL)      /*!< Disable                                                              */
46748   #define IPCT_INTENCLR1_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46749   #define IPCT_INTENCLR1_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46750 
46751 /* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
46752   #define IPCT_INTENCLR1_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
46753   #define IPCT_INTENCLR1_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
46754   #define IPCT_INTENCLR1_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
46755   #define IPCT_INTENCLR1_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
46756   #define IPCT_INTENCLR1_RECEIVE9_Clear (0x1UL)      /*!< Disable                                                              */
46757   #define IPCT_INTENCLR1_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
46758   #define IPCT_INTENCLR1_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
46759 
46760 /* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
46761   #define IPCT_INTENCLR1_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
46762   #define IPCT_INTENCLR1_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
46763   #define IPCT_INTENCLR1_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
46764   #define IPCT_INTENCLR1_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
46765   #define IPCT_INTENCLR1_RECEIVE10_Clear (0x1UL)     /*!< Disable                                                              */
46766   #define IPCT_INTENCLR1_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46767   #define IPCT_INTENCLR1_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46768 
46769 /* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
46770   #define IPCT_INTENCLR1_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
46771   #define IPCT_INTENCLR1_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
46772   #define IPCT_INTENCLR1_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
46773   #define IPCT_INTENCLR1_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
46774   #define IPCT_INTENCLR1_RECEIVE11_Clear (0x1UL)     /*!< Disable                                                              */
46775   #define IPCT_INTENCLR1_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46776   #define IPCT_INTENCLR1_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46777 
46778 /* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
46779   #define IPCT_INTENCLR1_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
46780   #define IPCT_INTENCLR1_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
46781   #define IPCT_INTENCLR1_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
46782   #define IPCT_INTENCLR1_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
46783   #define IPCT_INTENCLR1_RECEIVE12_Clear (0x1UL)     /*!< Disable                                                              */
46784   #define IPCT_INTENCLR1_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46785   #define IPCT_INTENCLR1_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46786 
46787 /* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
46788   #define IPCT_INTENCLR1_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
46789   #define IPCT_INTENCLR1_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
46790   #define IPCT_INTENCLR1_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
46791   #define IPCT_INTENCLR1_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
46792   #define IPCT_INTENCLR1_RECEIVE13_Clear (0x1UL)     /*!< Disable                                                              */
46793   #define IPCT_INTENCLR1_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46794   #define IPCT_INTENCLR1_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46795 
46796 /* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
46797   #define IPCT_INTENCLR1_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
46798   #define IPCT_INTENCLR1_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
46799   #define IPCT_INTENCLR1_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
46800   #define IPCT_INTENCLR1_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
46801   #define IPCT_INTENCLR1_RECEIVE14_Clear (0x1UL)     /*!< Disable                                                              */
46802   #define IPCT_INTENCLR1_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46803   #define IPCT_INTENCLR1_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46804 
46805 /* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
46806   #define IPCT_INTENCLR1_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
46807   #define IPCT_INTENCLR1_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR1_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
46808   #define IPCT_INTENCLR1_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
46809   #define IPCT_INTENCLR1_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
46810   #define IPCT_INTENCLR1_RECEIVE15_Clear (0x1UL)     /*!< Disable                                                              */
46811   #define IPCT_INTENCLR1_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
46812   #define IPCT_INTENCLR1_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
46813 
46814 /* ACKED0 @Bit 16 : Write '1' to disable interrupt for event ACKED[0] */
46815   #define IPCT_INTENCLR1_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
46816   #define IPCT_INTENCLR1_ACKED0_Msk (0x1UL << IPCT_INTENCLR1_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
46817   #define IPCT_INTENCLR1_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
46818   #define IPCT_INTENCLR1_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
46819   #define IPCT_INTENCLR1_ACKED0_Clear (0x1UL)        /*!< Disable                                                              */
46820   #define IPCT_INTENCLR1_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46821   #define IPCT_INTENCLR1_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46822 
46823 /* ACKED1 @Bit 17 : Write '1' to disable interrupt for event ACKED[1] */
46824   #define IPCT_INTENCLR1_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
46825   #define IPCT_INTENCLR1_ACKED1_Msk (0x1UL << IPCT_INTENCLR1_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
46826   #define IPCT_INTENCLR1_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
46827   #define IPCT_INTENCLR1_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
46828   #define IPCT_INTENCLR1_ACKED1_Clear (0x1UL)        /*!< Disable                                                              */
46829   #define IPCT_INTENCLR1_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46830   #define IPCT_INTENCLR1_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46831 
46832 /* ACKED2 @Bit 18 : Write '1' to disable interrupt for event ACKED[2] */
46833   #define IPCT_INTENCLR1_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
46834   #define IPCT_INTENCLR1_ACKED2_Msk (0x1UL << IPCT_INTENCLR1_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
46835   #define IPCT_INTENCLR1_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
46836   #define IPCT_INTENCLR1_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
46837   #define IPCT_INTENCLR1_ACKED2_Clear (0x1UL)        /*!< Disable                                                              */
46838   #define IPCT_INTENCLR1_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46839   #define IPCT_INTENCLR1_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46840 
46841 /* ACKED3 @Bit 19 : Write '1' to disable interrupt for event ACKED[3] */
46842   #define IPCT_INTENCLR1_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
46843   #define IPCT_INTENCLR1_ACKED3_Msk (0x1UL << IPCT_INTENCLR1_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
46844   #define IPCT_INTENCLR1_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
46845   #define IPCT_INTENCLR1_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
46846   #define IPCT_INTENCLR1_ACKED3_Clear (0x1UL)        /*!< Disable                                                              */
46847   #define IPCT_INTENCLR1_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46848   #define IPCT_INTENCLR1_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46849 
46850 /* ACKED4 @Bit 20 : Write '1' to disable interrupt for event ACKED[4] */
46851   #define IPCT_INTENCLR1_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
46852   #define IPCT_INTENCLR1_ACKED4_Msk (0x1UL << IPCT_INTENCLR1_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
46853   #define IPCT_INTENCLR1_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
46854   #define IPCT_INTENCLR1_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
46855   #define IPCT_INTENCLR1_ACKED4_Clear (0x1UL)        /*!< Disable                                                              */
46856   #define IPCT_INTENCLR1_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46857   #define IPCT_INTENCLR1_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46858 
46859 /* ACKED5 @Bit 21 : Write '1' to disable interrupt for event ACKED[5] */
46860   #define IPCT_INTENCLR1_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
46861   #define IPCT_INTENCLR1_ACKED5_Msk (0x1UL << IPCT_INTENCLR1_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
46862   #define IPCT_INTENCLR1_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
46863   #define IPCT_INTENCLR1_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
46864   #define IPCT_INTENCLR1_ACKED5_Clear (0x1UL)        /*!< Disable                                                              */
46865   #define IPCT_INTENCLR1_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46866   #define IPCT_INTENCLR1_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46867 
46868 /* ACKED6 @Bit 22 : Write '1' to disable interrupt for event ACKED[6] */
46869   #define IPCT_INTENCLR1_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
46870   #define IPCT_INTENCLR1_ACKED6_Msk (0x1UL << IPCT_INTENCLR1_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
46871   #define IPCT_INTENCLR1_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
46872   #define IPCT_INTENCLR1_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
46873   #define IPCT_INTENCLR1_ACKED6_Clear (0x1UL)        /*!< Disable                                                              */
46874   #define IPCT_INTENCLR1_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46875   #define IPCT_INTENCLR1_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46876 
46877 /* ACKED7 @Bit 23 : Write '1' to disable interrupt for event ACKED[7] */
46878   #define IPCT_INTENCLR1_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
46879   #define IPCT_INTENCLR1_ACKED7_Msk (0x1UL << IPCT_INTENCLR1_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
46880   #define IPCT_INTENCLR1_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
46881   #define IPCT_INTENCLR1_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
46882   #define IPCT_INTENCLR1_ACKED7_Clear (0x1UL)        /*!< Disable                                                              */
46883   #define IPCT_INTENCLR1_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46884   #define IPCT_INTENCLR1_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46885 
46886 /* ACKED8 @Bit 24 : Write '1' to disable interrupt for event ACKED[8] */
46887   #define IPCT_INTENCLR1_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
46888   #define IPCT_INTENCLR1_ACKED8_Msk (0x1UL << IPCT_INTENCLR1_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
46889   #define IPCT_INTENCLR1_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
46890   #define IPCT_INTENCLR1_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
46891   #define IPCT_INTENCLR1_ACKED8_Clear (0x1UL)        /*!< Disable                                                              */
46892   #define IPCT_INTENCLR1_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46893   #define IPCT_INTENCLR1_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46894 
46895 /* ACKED9 @Bit 25 : Write '1' to disable interrupt for event ACKED[9] */
46896   #define IPCT_INTENCLR1_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
46897   #define IPCT_INTENCLR1_ACKED9_Msk (0x1UL << IPCT_INTENCLR1_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
46898   #define IPCT_INTENCLR1_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
46899   #define IPCT_INTENCLR1_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
46900   #define IPCT_INTENCLR1_ACKED9_Clear (0x1UL)        /*!< Disable                                                              */
46901   #define IPCT_INTENCLR1_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
46902   #define IPCT_INTENCLR1_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
46903 
46904 /* ACKED10 @Bit 26 : Write '1' to disable interrupt for event ACKED[10] */
46905   #define IPCT_INTENCLR1_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
46906   #define IPCT_INTENCLR1_ACKED10_Msk (0x1UL << IPCT_INTENCLR1_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
46907   #define IPCT_INTENCLR1_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
46908   #define IPCT_INTENCLR1_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
46909   #define IPCT_INTENCLR1_ACKED10_Clear (0x1UL)       /*!< Disable                                                              */
46910   #define IPCT_INTENCLR1_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46911   #define IPCT_INTENCLR1_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46912 
46913 /* ACKED11 @Bit 27 : Write '1' to disable interrupt for event ACKED[11] */
46914   #define IPCT_INTENCLR1_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
46915   #define IPCT_INTENCLR1_ACKED11_Msk (0x1UL << IPCT_INTENCLR1_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
46916   #define IPCT_INTENCLR1_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
46917   #define IPCT_INTENCLR1_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
46918   #define IPCT_INTENCLR1_ACKED11_Clear (0x1UL)       /*!< Disable                                                              */
46919   #define IPCT_INTENCLR1_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46920   #define IPCT_INTENCLR1_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46921 
46922 /* ACKED12 @Bit 28 : Write '1' to disable interrupt for event ACKED[12] */
46923   #define IPCT_INTENCLR1_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
46924   #define IPCT_INTENCLR1_ACKED12_Msk (0x1UL << IPCT_INTENCLR1_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
46925   #define IPCT_INTENCLR1_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
46926   #define IPCT_INTENCLR1_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
46927   #define IPCT_INTENCLR1_ACKED12_Clear (0x1UL)       /*!< Disable                                                              */
46928   #define IPCT_INTENCLR1_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46929   #define IPCT_INTENCLR1_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46930 
46931 /* ACKED13 @Bit 29 : Write '1' to disable interrupt for event ACKED[13] */
46932   #define IPCT_INTENCLR1_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
46933   #define IPCT_INTENCLR1_ACKED13_Msk (0x1UL << IPCT_INTENCLR1_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
46934   #define IPCT_INTENCLR1_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
46935   #define IPCT_INTENCLR1_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
46936   #define IPCT_INTENCLR1_ACKED13_Clear (0x1UL)       /*!< Disable                                                              */
46937   #define IPCT_INTENCLR1_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46938   #define IPCT_INTENCLR1_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46939 
46940 /* ACKED14 @Bit 30 : Write '1' to disable interrupt for event ACKED[14] */
46941   #define IPCT_INTENCLR1_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
46942   #define IPCT_INTENCLR1_ACKED14_Msk (0x1UL << IPCT_INTENCLR1_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
46943   #define IPCT_INTENCLR1_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
46944   #define IPCT_INTENCLR1_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
46945   #define IPCT_INTENCLR1_ACKED14_Clear (0x1UL)       /*!< Disable                                                              */
46946   #define IPCT_INTENCLR1_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46947   #define IPCT_INTENCLR1_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46948 
46949 /* ACKED15 @Bit 31 : Write '1' to disable interrupt for event ACKED[15] */
46950   #define IPCT_INTENCLR1_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
46951   #define IPCT_INTENCLR1_ACKED15_Msk (0x1UL << IPCT_INTENCLR1_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
46952   #define IPCT_INTENCLR1_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
46953   #define IPCT_INTENCLR1_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
46954   #define IPCT_INTENCLR1_ACKED15_Clear (0x1UL)       /*!< Disable                                                              */
46955   #define IPCT_INTENCLR1_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
46956   #define IPCT_INTENCLR1_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
46957 
46958 
46959 /* IPCT_INTPEND1: Pending interrupts */
46960   #define IPCT_INTPEND1_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND1 register.                                    */
46961 
46962 /* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
46963   #define IPCT_INTPEND1_RECEIVE0_Pos (0UL)           /*!< Position of RECEIVE0 field.                                          */
46964   #define IPCT_INTPEND1_RECEIVE0_Msk (0x1UL << IPCT_INTPEND1_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                    */
46965   #define IPCT_INTPEND1_RECEIVE0_Min (0x0UL)         /*!< Min enumerator value of RECEIVE0 field.                              */
46966   #define IPCT_INTPEND1_RECEIVE0_Max (0x1UL)         /*!< Max enumerator value of RECEIVE0 field.                              */
46967   #define IPCT_INTPEND1_RECEIVE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
46968   #define IPCT_INTPEND1_RECEIVE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
46969 
46970 /* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
46971   #define IPCT_INTPEND1_RECEIVE1_Pos (1UL)           /*!< Position of RECEIVE1 field.                                          */
46972   #define IPCT_INTPEND1_RECEIVE1_Msk (0x1UL << IPCT_INTPEND1_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                    */
46973   #define IPCT_INTPEND1_RECEIVE1_Min (0x0UL)         /*!< Min enumerator value of RECEIVE1 field.                              */
46974   #define IPCT_INTPEND1_RECEIVE1_Max (0x1UL)         /*!< Max enumerator value of RECEIVE1 field.                              */
46975   #define IPCT_INTPEND1_RECEIVE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
46976   #define IPCT_INTPEND1_RECEIVE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
46977 
46978 /* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
46979   #define IPCT_INTPEND1_RECEIVE2_Pos (2UL)           /*!< Position of RECEIVE2 field.                                          */
46980   #define IPCT_INTPEND1_RECEIVE2_Msk (0x1UL << IPCT_INTPEND1_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                    */
46981   #define IPCT_INTPEND1_RECEIVE2_Min (0x0UL)         /*!< Min enumerator value of RECEIVE2 field.                              */
46982   #define IPCT_INTPEND1_RECEIVE2_Max (0x1UL)         /*!< Max enumerator value of RECEIVE2 field.                              */
46983   #define IPCT_INTPEND1_RECEIVE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
46984   #define IPCT_INTPEND1_RECEIVE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
46985 
46986 /* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
46987   #define IPCT_INTPEND1_RECEIVE3_Pos (3UL)           /*!< Position of RECEIVE3 field.                                          */
46988   #define IPCT_INTPEND1_RECEIVE3_Msk (0x1UL << IPCT_INTPEND1_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                    */
46989   #define IPCT_INTPEND1_RECEIVE3_Min (0x0UL)         /*!< Min enumerator value of RECEIVE3 field.                              */
46990   #define IPCT_INTPEND1_RECEIVE3_Max (0x1UL)         /*!< Max enumerator value of RECEIVE3 field.                              */
46991   #define IPCT_INTPEND1_RECEIVE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
46992   #define IPCT_INTPEND1_RECEIVE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
46993 
46994 /* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
46995   #define IPCT_INTPEND1_RECEIVE4_Pos (4UL)           /*!< Position of RECEIVE4 field.                                          */
46996   #define IPCT_INTPEND1_RECEIVE4_Msk (0x1UL << IPCT_INTPEND1_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                    */
46997   #define IPCT_INTPEND1_RECEIVE4_Min (0x0UL)         /*!< Min enumerator value of RECEIVE4 field.                              */
46998   #define IPCT_INTPEND1_RECEIVE4_Max (0x1UL)         /*!< Max enumerator value of RECEIVE4 field.                              */
46999   #define IPCT_INTPEND1_RECEIVE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
47000   #define IPCT_INTPEND1_RECEIVE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
47001 
47002 /* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
47003   #define IPCT_INTPEND1_RECEIVE5_Pos (5UL)           /*!< Position of RECEIVE5 field.                                          */
47004   #define IPCT_INTPEND1_RECEIVE5_Msk (0x1UL << IPCT_INTPEND1_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                    */
47005   #define IPCT_INTPEND1_RECEIVE5_Min (0x0UL)         /*!< Min enumerator value of RECEIVE5 field.                              */
47006   #define IPCT_INTPEND1_RECEIVE5_Max (0x1UL)         /*!< Max enumerator value of RECEIVE5 field.                              */
47007   #define IPCT_INTPEND1_RECEIVE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
47008   #define IPCT_INTPEND1_RECEIVE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
47009 
47010 /* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
47011   #define IPCT_INTPEND1_RECEIVE6_Pos (6UL)           /*!< Position of RECEIVE6 field.                                          */
47012   #define IPCT_INTPEND1_RECEIVE6_Msk (0x1UL << IPCT_INTPEND1_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                    */
47013   #define IPCT_INTPEND1_RECEIVE6_Min (0x0UL)         /*!< Min enumerator value of RECEIVE6 field.                              */
47014   #define IPCT_INTPEND1_RECEIVE6_Max (0x1UL)         /*!< Max enumerator value of RECEIVE6 field.                              */
47015   #define IPCT_INTPEND1_RECEIVE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
47016   #define IPCT_INTPEND1_RECEIVE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
47017 
47018 /* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
47019   #define IPCT_INTPEND1_RECEIVE7_Pos (7UL)           /*!< Position of RECEIVE7 field.                                          */
47020   #define IPCT_INTPEND1_RECEIVE7_Msk (0x1UL << IPCT_INTPEND1_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                    */
47021   #define IPCT_INTPEND1_RECEIVE7_Min (0x0UL)         /*!< Min enumerator value of RECEIVE7 field.                              */
47022   #define IPCT_INTPEND1_RECEIVE7_Max (0x1UL)         /*!< Max enumerator value of RECEIVE7 field.                              */
47023   #define IPCT_INTPEND1_RECEIVE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
47024   #define IPCT_INTPEND1_RECEIVE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
47025 
47026 /* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
47027   #define IPCT_INTPEND1_RECEIVE8_Pos (8UL)           /*!< Position of RECEIVE8 field.                                          */
47028   #define IPCT_INTPEND1_RECEIVE8_Msk (0x1UL << IPCT_INTPEND1_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                    */
47029   #define IPCT_INTPEND1_RECEIVE8_Min (0x0UL)         /*!< Min enumerator value of RECEIVE8 field.                              */
47030   #define IPCT_INTPEND1_RECEIVE8_Max (0x1UL)         /*!< Max enumerator value of RECEIVE8 field.                              */
47031   #define IPCT_INTPEND1_RECEIVE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
47032   #define IPCT_INTPEND1_RECEIVE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
47033 
47034 /* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
47035   #define IPCT_INTPEND1_RECEIVE9_Pos (9UL)           /*!< Position of RECEIVE9 field.                                          */
47036   #define IPCT_INTPEND1_RECEIVE9_Msk (0x1UL << IPCT_INTPEND1_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                    */
47037   #define IPCT_INTPEND1_RECEIVE9_Min (0x0UL)         /*!< Min enumerator value of RECEIVE9 field.                              */
47038   #define IPCT_INTPEND1_RECEIVE9_Max (0x1UL)         /*!< Max enumerator value of RECEIVE9 field.                              */
47039   #define IPCT_INTPEND1_RECEIVE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
47040   #define IPCT_INTPEND1_RECEIVE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
47041 
47042 /* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
47043   #define IPCT_INTPEND1_RECEIVE10_Pos (10UL)         /*!< Position of RECEIVE10 field.                                         */
47044   #define IPCT_INTPEND1_RECEIVE10_Msk (0x1UL << IPCT_INTPEND1_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                 */
47045   #define IPCT_INTPEND1_RECEIVE10_Min (0x0UL)        /*!< Min enumerator value of RECEIVE10 field.                             */
47046   #define IPCT_INTPEND1_RECEIVE10_Max (0x1UL)        /*!< Max enumerator value of RECEIVE10 field.                             */
47047   #define IPCT_INTPEND1_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
47048   #define IPCT_INTPEND1_RECEIVE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
47049 
47050 /* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
47051   #define IPCT_INTPEND1_RECEIVE11_Pos (11UL)         /*!< Position of RECEIVE11 field.                                         */
47052   #define IPCT_INTPEND1_RECEIVE11_Msk (0x1UL << IPCT_INTPEND1_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                 */
47053   #define IPCT_INTPEND1_RECEIVE11_Min (0x0UL)        /*!< Min enumerator value of RECEIVE11 field.                             */
47054   #define IPCT_INTPEND1_RECEIVE11_Max (0x1UL)        /*!< Max enumerator value of RECEIVE11 field.                             */
47055   #define IPCT_INTPEND1_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
47056   #define IPCT_INTPEND1_RECEIVE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
47057 
47058 /* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
47059   #define IPCT_INTPEND1_RECEIVE12_Pos (12UL)         /*!< Position of RECEIVE12 field.                                         */
47060   #define IPCT_INTPEND1_RECEIVE12_Msk (0x1UL << IPCT_INTPEND1_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                 */
47061   #define IPCT_INTPEND1_RECEIVE12_Min (0x0UL)        /*!< Min enumerator value of RECEIVE12 field.                             */
47062   #define IPCT_INTPEND1_RECEIVE12_Max (0x1UL)        /*!< Max enumerator value of RECEIVE12 field.                             */
47063   #define IPCT_INTPEND1_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
47064   #define IPCT_INTPEND1_RECEIVE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
47065 
47066 /* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
47067   #define IPCT_INTPEND1_RECEIVE13_Pos (13UL)         /*!< Position of RECEIVE13 field.                                         */
47068   #define IPCT_INTPEND1_RECEIVE13_Msk (0x1UL << IPCT_INTPEND1_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                 */
47069   #define IPCT_INTPEND1_RECEIVE13_Min (0x0UL)        /*!< Min enumerator value of RECEIVE13 field.                             */
47070   #define IPCT_INTPEND1_RECEIVE13_Max (0x1UL)        /*!< Max enumerator value of RECEIVE13 field.                             */
47071   #define IPCT_INTPEND1_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
47072   #define IPCT_INTPEND1_RECEIVE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
47073 
47074 /* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
47075   #define IPCT_INTPEND1_RECEIVE14_Pos (14UL)         /*!< Position of RECEIVE14 field.                                         */
47076   #define IPCT_INTPEND1_RECEIVE14_Msk (0x1UL << IPCT_INTPEND1_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                 */
47077   #define IPCT_INTPEND1_RECEIVE14_Min (0x0UL)        /*!< Min enumerator value of RECEIVE14 field.                             */
47078   #define IPCT_INTPEND1_RECEIVE14_Max (0x1UL)        /*!< Max enumerator value of RECEIVE14 field.                             */
47079   #define IPCT_INTPEND1_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
47080   #define IPCT_INTPEND1_RECEIVE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
47081 
47082 /* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
47083   #define IPCT_INTPEND1_RECEIVE15_Pos (15UL)         /*!< Position of RECEIVE15 field.                                         */
47084   #define IPCT_INTPEND1_RECEIVE15_Msk (0x1UL << IPCT_INTPEND1_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                 */
47085   #define IPCT_INTPEND1_RECEIVE15_Min (0x0UL)        /*!< Min enumerator value of RECEIVE15 field.                             */
47086   #define IPCT_INTPEND1_RECEIVE15_Max (0x1UL)        /*!< Max enumerator value of RECEIVE15 field.                             */
47087   #define IPCT_INTPEND1_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
47088   #define IPCT_INTPEND1_RECEIVE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
47089 
47090 /* ACKED0 @Bit 16 : Read pending status of interrupt for event ACKED[0] */
47091   #define IPCT_INTPEND1_ACKED0_Pos (16UL)            /*!< Position of ACKED0 field.                                            */
47092   #define IPCT_INTPEND1_ACKED0_Msk (0x1UL << IPCT_INTPEND1_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                          */
47093   #define IPCT_INTPEND1_ACKED0_Min (0x0UL)           /*!< Min enumerator value of ACKED0 field.                                */
47094   #define IPCT_INTPEND1_ACKED0_Max (0x1UL)           /*!< Max enumerator value of ACKED0 field.                                */
47095   #define IPCT_INTPEND1_ACKED0_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47096   #define IPCT_INTPEND1_ACKED0_Pending (0x1UL)       /*!< Read: Pending                                                        */
47097 
47098 /* ACKED1 @Bit 17 : Read pending status of interrupt for event ACKED[1] */
47099   #define IPCT_INTPEND1_ACKED1_Pos (17UL)            /*!< Position of ACKED1 field.                                            */
47100   #define IPCT_INTPEND1_ACKED1_Msk (0x1UL << IPCT_INTPEND1_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                          */
47101   #define IPCT_INTPEND1_ACKED1_Min (0x0UL)           /*!< Min enumerator value of ACKED1 field.                                */
47102   #define IPCT_INTPEND1_ACKED1_Max (0x1UL)           /*!< Max enumerator value of ACKED1 field.                                */
47103   #define IPCT_INTPEND1_ACKED1_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47104   #define IPCT_INTPEND1_ACKED1_Pending (0x1UL)       /*!< Read: Pending                                                        */
47105 
47106 /* ACKED2 @Bit 18 : Read pending status of interrupt for event ACKED[2] */
47107   #define IPCT_INTPEND1_ACKED2_Pos (18UL)            /*!< Position of ACKED2 field.                                            */
47108   #define IPCT_INTPEND1_ACKED2_Msk (0x1UL << IPCT_INTPEND1_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                          */
47109   #define IPCT_INTPEND1_ACKED2_Min (0x0UL)           /*!< Min enumerator value of ACKED2 field.                                */
47110   #define IPCT_INTPEND1_ACKED2_Max (0x1UL)           /*!< Max enumerator value of ACKED2 field.                                */
47111   #define IPCT_INTPEND1_ACKED2_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47112   #define IPCT_INTPEND1_ACKED2_Pending (0x1UL)       /*!< Read: Pending                                                        */
47113 
47114 /* ACKED3 @Bit 19 : Read pending status of interrupt for event ACKED[3] */
47115   #define IPCT_INTPEND1_ACKED3_Pos (19UL)            /*!< Position of ACKED3 field.                                            */
47116   #define IPCT_INTPEND1_ACKED3_Msk (0x1UL << IPCT_INTPEND1_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                          */
47117   #define IPCT_INTPEND1_ACKED3_Min (0x0UL)           /*!< Min enumerator value of ACKED3 field.                                */
47118   #define IPCT_INTPEND1_ACKED3_Max (0x1UL)           /*!< Max enumerator value of ACKED3 field.                                */
47119   #define IPCT_INTPEND1_ACKED3_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47120   #define IPCT_INTPEND1_ACKED3_Pending (0x1UL)       /*!< Read: Pending                                                        */
47121 
47122 /* ACKED4 @Bit 20 : Read pending status of interrupt for event ACKED[4] */
47123   #define IPCT_INTPEND1_ACKED4_Pos (20UL)            /*!< Position of ACKED4 field.                                            */
47124   #define IPCT_INTPEND1_ACKED4_Msk (0x1UL << IPCT_INTPEND1_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                          */
47125   #define IPCT_INTPEND1_ACKED4_Min (0x0UL)           /*!< Min enumerator value of ACKED4 field.                                */
47126   #define IPCT_INTPEND1_ACKED4_Max (0x1UL)           /*!< Max enumerator value of ACKED4 field.                                */
47127   #define IPCT_INTPEND1_ACKED4_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47128   #define IPCT_INTPEND1_ACKED4_Pending (0x1UL)       /*!< Read: Pending                                                        */
47129 
47130 /* ACKED5 @Bit 21 : Read pending status of interrupt for event ACKED[5] */
47131   #define IPCT_INTPEND1_ACKED5_Pos (21UL)            /*!< Position of ACKED5 field.                                            */
47132   #define IPCT_INTPEND1_ACKED5_Msk (0x1UL << IPCT_INTPEND1_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                          */
47133   #define IPCT_INTPEND1_ACKED5_Min (0x0UL)           /*!< Min enumerator value of ACKED5 field.                                */
47134   #define IPCT_INTPEND1_ACKED5_Max (0x1UL)           /*!< Max enumerator value of ACKED5 field.                                */
47135   #define IPCT_INTPEND1_ACKED5_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47136   #define IPCT_INTPEND1_ACKED5_Pending (0x1UL)       /*!< Read: Pending                                                        */
47137 
47138 /* ACKED6 @Bit 22 : Read pending status of interrupt for event ACKED[6] */
47139   #define IPCT_INTPEND1_ACKED6_Pos (22UL)            /*!< Position of ACKED6 field.                                            */
47140   #define IPCT_INTPEND1_ACKED6_Msk (0x1UL << IPCT_INTPEND1_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                          */
47141   #define IPCT_INTPEND1_ACKED6_Min (0x0UL)           /*!< Min enumerator value of ACKED6 field.                                */
47142   #define IPCT_INTPEND1_ACKED6_Max (0x1UL)           /*!< Max enumerator value of ACKED6 field.                                */
47143   #define IPCT_INTPEND1_ACKED6_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47144   #define IPCT_INTPEND1_ACKED6_Pending (0x1UL)       /*!< Read: Pending                                                        */
47145 
47146 /* ACKED7 @Bit 23 : Read pending status of interrupt for event ACKED[7] */
47147   #define IPCT_INTPEND1_ACKED7_Pos (23UL)            /*!< Position of ACKED7 field.                                            */
47148   #define IPCT_INTPEND1_ACKED7_Msk (0x1UL << IPCT_INTPEND1_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                          */
47149   #define IPCT_INTPEND1_ACKED7_Min (0x0UL)           /*!< Min enumerator value of ACKED7 field.                                */
47150   #define IPCT_INTPEND1_ACKED7_Max (0x1UL)           /*!< Max enumerator value of ACKED7 field.                                */
47151   #define IPCT_INTPEND1_ACKED7_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47152   #define IPCT_INTPEND1_ACKED7_Pending (0x1UL)       /*!< Read: Pending                                                        */
47153 
47154 /* ACKED8 @Bit 24 : Read pending status of interrupt for event ACKED[8] */
47155   #define IPCT_INTPEND1_ACKED8_Pos (24UL)            /*!< Position of ACKED8 field.                                            */
47156   #define IPCT_INTPEND1_ACKED8_Msk (0x1UL << IPCT_INTPEND1_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                          */
47157   #define IPCT_INTPEND1_ACKED8_Min (0x0UL)           /*!< Min enumerator value of ACKED8 field.                                */
47158   #define IPCT_INTPEND1_ACKED8_Max (0x1UL)           /*!< Max enumerator value of ACKED8 field.                                */
47159   #define IPCT_INTPEND1_ACKED8_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47160   #define IPCT_INTPEND1_ACKED8_Pending (0x1UL)       /*!< Read: Pending                                                        */
47161 
47162 /* ACKED9 @Bit 25 : Read pending status of interrupt for event ACKED[9] */
47163   #define IPCT_INTPEND1_ACKED9_Pos (25UL)            /*!< Position of ACKED9 field.                                            */
47164   #define IPCT_INTPEND1_ACKED9_Msk (0x1UL << IPCT_INTPEND1_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                          */
47165   #define IPCT_INTPEND1_ACKED9_Min (0x0UL)           /*!< Min enumerator value of ACKED9 field.                                */
47166   #define IPCT_INTPEND1_ACKED9_Max (0x1UL)           /*!< Max enumerator value of ACKED9 field.                                */
47167   #define IPCT_INTPEND1_ACKED9_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
47168   #define IPCT_INTPEND1_ACKED9_Pending (0x1UL)       /*!< Read: Pending                                                        */
47169 
47170 /* ACKED10 @Bit 26 : Read pending status of interrupt for event ACKED[10] */
47171   #define IPCT_INTPEND1_ACKED10_Pos (26UL)           /*!< Position of ACKED10 field.                                           */
47172   #define IPCT_INTPEND1_ACKED10_Msk (0x1UL << IPCT_INTPEND1_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                       */
47173   #define IPCT_INTPEND1_ACKED10_Min (0x0UL)          /*!< Min enumerator value of ACKED10 field.                               */
47174   #define IPCT_INTPEND1_ACKED10_Max (0x1UL)          /*!< Max enumerator value of ACKED10 field.                               */
47175   #define IPCT_INTPEND1_ACKED10_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
47176   #define IPCT_INTPEND1_ACKED10_Pending (0x1UL)      /*!< Read: Pending                                                        */
47177 
47178 /* ACKED11 @Bit 27 : Read pending status of interrupt for event ACKED[11] */
47179   #define IPCT_INTPEND1_ACKED11_Pos (27UL)           /*!< Position of ACKED11 field.                                           */
47180   #define IPCT_INTPEND1_ACKED11_Msk (0x1UL << IPCT_INTPEND1_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                       */
47181   #define IPCT_INTPEND1_ACKED11_Min (0x0UL)          /*!< Min enumerator value of ACKED11 field.                               */
47182   #define IPCT_INTPEND1_ACKED11_Max (0x1UL)          /*!< Max enumerator value of ACKED11 field.                               */
47183   #define IPCT_INTPEND1_ACKED11_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
47184   #define IPCT_INTPEND1_ACKED11_Pending (0x1UL)      /*!< Read: Pending                                                        */
47185 
47186 /* ACKED12 @Bit 28 : Read pending status of interrupt for event ACKED[12] */
47187   #define IPCT_INTPEND1_ACKED12_Pos (28UL)           /*!< Position of ACKED12 field.                                           */
47188   #define IPCT_INTPEND1_ACKED12_Msk (0x1UL << IPCT_INTPEND1_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                       */
47189   #define IPCT_INTPEND1_ACKED12_Min (0x0UL)          /*!< Min enumerator value of ACKED12 field.                               */
47190   #define IPCT_INTPEND1_ACKED12_Max (0x1UL)          /*!< Max enumerator value of ACKED12 field.                               */
47191   #define IPCT_INTPEND1_ACKED12_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
47192   #define IPCT_INTPEND1_ACKED12_Pending (0x1UL)      /*!< Read: Pending                                                        */
47193 
47194 /* ACKED13 @Bit 29 : Read pending status of interrupt for event ACKED[13] */
47195   #define IPCT_INTPEND1_ACKED13_Pos (29UL)           /*!< Position of ACKED13 field.                                           */
47196   #define IPCT_INTPEND1_ACKED13_Msk (0x1UL << IPCT_INTPEND1_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                       */
47197   #define IPCT_INTPEND1_ACKED13_Min (0x0UL)          /*!< Min enumerator value of ACKED13 field.                               */
47198   #define IPCT_INTPEND1_ACKED13_Max (0x1UL)          /*!< Max enumerator value of ACKED13 field.                               */
47199   #define IPCT_INTPEND1_ACKED13_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
47200   #define IPCT_INTPEND1_ACKED13_Pending (0x1UL)      /*!< Read: Pending                                                        */
47201 
47202 /* ACKED14 @Bit 30 : Read pending status of interrupt for event ACKED[14] */
47203   #define IPCT_INTPEND1_ACKED14_Pos (30UL)           /*!< Position of ACKED14 field.                                           */
47204   #define IPCT_INTPEND1_ACKED14_Msk (0x1UL << IPCT_INTPEND1_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                       */
47205   #define IPCT_INTPEND1_ACKED14_Min (0x0UL)          /*!< Min enumerator value of ACKED14 field.                               */
47206   #define IPCT_INTPEND1_ACKED14_Max (0x1UL)          /*!< Max enumerator value of ACKED14 field.                               */
47207   #define IPCT_INTPEND1_ACKED14_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
47208   #define IPCT_INTPEND1_ACKED14_Pending (0x1UL)      /*!< Read: Pending                                                        */
47209 
47210 /* ACKED15 @Bit 31 : Read pending status of interrupt for event ACKED[15] */
47211   #define IPCT_INTPEND1_ACKED15_Pos (31UL)           /*!< Position of ACKED15 field.                                           */
47212   #define IPCT_INTPEND1_ACKED15_Msk (0x1UL << IPCT_INTPEND1_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                       */
47213   #define IPCT_INTPEND1_ACKED15_Min (0x0UL)          /*!< Min enumerator value of ACKED15 field.                               */
47214   #define IPCT_INTPEND1_ACKED15_Max (0x1UL)          /*!< Max enumerator value of ACKED15 field.                               */
47215   #define IPCT_INTPEND1_ACKED15_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
47216   #define IPCT_INTPEND1_ACKED15_Pending (0x1UL)      /*!< Read: Pending                                                        */
47217 
47218 
47219 /* IPCT_INTEN2: Enable or disable interrupt */
47220   #define IPCT_INTEN2_ResetValue (0x00000000UL)      /*!< Reset value of INTEN2 register.                                      */
47221 
47222 /* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
47223   #define IPCT_INTEN2_RECEIVE0_Pos (0UL)             /*!< Position of RECEIVE0 field.                                          */
47224   #define IPCT_INTEN2_RECEIVE0_Msk (0x1UL << IPCT_INTEN2_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                        */
47225   #define IPCT_INTEN2_RECEIVE0_Min (0x0UL)           /*!< Min enumerator value of RECEIVE0 field.                              */
47226   #define IPCT_INTEN2_RECEIVE0_Max (0x1UL)           /*!< Max enumerator value of RECEIVE0 field.                              */
47227   #define IPCT_INTEN2_RECEIVE0_Disabled (0x0UL)      /*!< Disable                                                              */
47228   #define IPCT_INTEN2_RECEIVE0_Enabled (0x1UL)       /*!< Enable                                                               */
47229 
47230 /* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
47231   #define IPCT_INTEN2_RECEIVE1_Pos (1UL)             /*!< Position of RECEIVE1 field.                                          */
47232   #define IPCT_INTEN2_RECEIVE1_Msk (0x1UL << IPCT_INTEN2_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                        */
47233   #define IPCT_INTEN2_RECEIVE1_Min (0x0UL)           /*!< Min enumerator value of RECEIVE1 field.                              */
47234   #define IPCT_INTEN2_RECEIVE1_Max (0x1UL)           /*!< Max enumerator value of RECEIVE1 field.                              */
47235   #define IPCT_INTEN2_RECEIVE1_Disabled (0x0UL)      /*!< Disable                                                              */
47236   #define IPCT_INTEN2_RECEIVE1_Enabled (0x1UL)       /*!< Enable                                                               */
47237 
47238 /* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
47239   #define IPCT_INTEN2_RECEIVE2_Pos (2UL)             /*!< Position of RECEIVE2 field.                                          */
47240   #define IPCT_INTEN2_RECEIVE2_Msk (0x1UL << IPCT_INTEN2_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                        */
47241   #define IPCT_INTEN2_RECEIVE2_Min (0x0UL)           /*!< Min enumerator value of RECEIVE2 field.                              */
47242   #define IPCT_INTEN2_RECEIVE2_Max (0x1UL)           /*!< Max enumerator value of RECEIVE2 field.                              */
47243   #define IPCT_INTEN2_RECEIVE2_Disabled (0x0UL)      /*!< Disable                                                              */
47244   #define IPCT_INTEN2_RECEIVE2_Enabled (0x1UL)       /*!< Enable                                                               */
47245 
47246 /* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
47247   #define IPCT_INTEN2_RECEIVE3_Pos (3UL)             /*!< Position of RECEIVE3 field.                                          */
47248   #define IPCT_INTEN2_RECEIVE3_Msk (0x1UL << IPCT_INTEN2_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                        */
47249   #define IPCT_INTEN2_RECEIVE3_Min (0x0UL)           /*!< Min enumerator value of RECEIVE3 field.                              */
47250   #define IPCT_INTEN2_RECEIVE3_Max (0x1UL)           /*!< Max enumerator value of RECEIVE3 field.                              */
47251   #define IPCT_INTEN2_RECEIVE3_Disabled (0x0UL)      /*!< Disable                                                              */
47252   #define IPCT_INTEN2_RECEIVE3_Enabled (0x1UL)       /*!< Enable                                                               */
47253 
47254 /* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
47255   #define IPCT_INTEN2_RECEIVE4_Pos (4UL)             /*!< Position of RECEIVE4 field.                                          */
47256   #define IPCT_INTEN2_RECEIVE4_Msk (0x1UL << IPCT_INTEN2_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                        */
47257   #define IPCT_INTEN2_RECEIVE4_Min (0x0UL)           /*!< Min enumerator value of RECEIVE4 field.                              */
47258   #define IPCT_INTEN2_RECEIVE4_Max (0x1UL)           /*!< Max enumerator value of RECEIVE4 field.                              */
47259   #define IPCT_INTEN2_RECEIVE4_Disabled (0x0UL)      /*!< Disable                                                              */
47260   #define IPCT_INTEN2_RECEIVE4_Enabled (0x1UL)       /*!< Enable                                                               */
47261 
47262 /* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
47263   #define IPCT_INTEN2_RECEIVE5_Pos (5UL)             /*!< Position of RECEIVE5 field.                                          */
47264   #define IPCT_INTEN2_RECEIVE5_Msk (0x1UL << IPCT_INTEN2_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                        */
47265   #define IPCT_INTEN2_RECEIVE5_Min (0x0UL)           /*!< Min enumerator value of RECEIVE5 field.                              */
47266   #define IPCT_INTEN2_RECEIVE5_Max (0x1UL)           /*!< Max enumerator value of RECEIVE5 field.                              */
47267   #define IPCT_INTEN2_RECEIVE5_Disabled (0x0UL)      /*!< Disable                                                              */
47268   #define IPCT_INTEN2_RECEIVE5_Enabled (0x1UL)       /*!< Enable                                                               */
47269 
47270 /* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
47271   #define IPCT_INTEN2_RECEIVE6_Pos (6UL)             /*!< Position of RECEIVE6 field.                                          */
47272   #define IPCT_INTEN2_RECEIVE6_Msk (0x1UL << IPCT_INTEN2_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                        */
47273   #define IPCT_INTEN2_RECEIVE6_Min (0x0UL)           /*!< Min enumerator value of RECEIVE6 field.                              */
47274   #define IPCT_INTEN2_RECEIVE6_Max (0x1UL)           /*!< Max enumerator value of RECEIVE6 field.                              */
47275   #define IPCT_INTEN2_RECEIVE6_Disabled (0x0UL)      /*!< Disable                                                              */
47276   #define IPCT_INTEN2_RECEIVE6_Enabled (0x1UL)       /*!< Enable                                                               */
47277 
47278 /* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
47279   #define IPCT_INTEN2_RECEIVE7_Pos (7UL)             /*!< Position of RECEIVE7 field.                                          */
47280   #define IPCT_INTEN2_RECEIVE7_Msk (0x1UL << IPCT_INTEN2_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                        */
47281   #define IPCT_INTEN2_RECEIVE7_Min (0x0UL)           /*!< Min enumerator value of RECEIVE7 field.                              */
47282   #define IPCT_INTEN2_RECEIVE7_Max (0x1UL)           /*!< Max enumerator value of RECEIVE7 field.                              */
47283   #define IPCT_INTEN2_RECEIVE7_Disabled (0x0UL)      /*!< Disable                                                              */
47284   #define IPCT_INTEN2_RECEIVE7_Enabled (0x1UL)       /*!< Enable                                                               */
47285 
47286 /* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
47287   #define IPCT_INTEN2_RECEIVE8_Pos (8UL)             /*!< Position of RECEIVE8 field.                                          */
47288   #define IPCT_INTEN2_RECEIVE8_Msk (0x1UL << IPCT_INTEN2_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                        */
47289   #define IPCT_INTEN2_RECEIVE8_Min (0x0UL)           /*!< Min enumerator value of RECEIVE8 field.                              */
47290   #define IPCT_INTEN2_RECEIVE8_Max (0x1UL)           /*!< Max enumerator value of RECEIVE8 field.                              */
47291   #define IPCT_INTEN2_RECEIVE8_Disabled (0x0UL)      /*!< Disable                                                              */
47292   #define IPCT_INTEN2_RECEIVE8_Enabled (0x1UL)       /*!< Enable                                                               */
47293 
47294 /* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
47295   #define IPCT_INTEN2_RECEIVE9_Pos (9UL)             /*!< Position of RECEIVE9 field.                                          */
47296   #define IPCT_INTEN2_RECEIVE9_Msk (0x1UL << IPCT_INTEN2_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                        */
47297   #define IPCT_INTEN2_RECEIVE9_Min (0x0UL)           /*!< Min enumerator value of RECEIVE9 field.                              */
47298   #define IPCT_INTEN2_RECEIVE9_Max (0x1UL)           /*!< Max enumerator value of RECEIVE9 field.                              */
47299   #define IPCT_INTEN2_RECEIVE9_Disabled (0x0UL)      /*!< Disable                                                              */
47300   #define IPCT_INTEN2_RECEIVE9_Enabled (0x1UL)       /*!< Enable                                                               */
47301 
47302 /* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
47303   #define IPCT_INTEN2_RECEIVE10_Pos (10UL)           /*!< Position of RECEIVE10 field.                                         */
47304   #define IPCT_INTEN2_RECEIVE10_Msk (0x1UL << IPCT_INTEN2_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                     */
47305   #define IPCT_INTEN2_RECEIVE10_Min (0x0UL)          /*!< Min enumerator value of RECEIVE10 field.                             */
47306   #define IPCT_INTEN2_RECEIVE10_Max (0x1UL)          /*!< Max enumerator value of RECEIVE10 field.                             */
47307   #define IPCT_INTEN2_RECEIVE10_Disabled (0x0UL)     /*!< Disable                                                              */
47308   #define IPCT_INTEN2_RECEIVE10_Enabled (0x1UL)      /*!< Enable                                                               */
47309 
47310 /* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
47311   #define IPCT_INTEN2_RECEIVE11_Pos (11UL)           /*!< Position of RECEIVE11 field.                                         */
47312   #define IPCT_INTEN2_RECEIVE11_Msk (0x1UL << IPCT_INTEN2_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                     */
47313   #define IPCT_INTEN2_RECEIVE11_Min (0x0UL)          /*!< Min enumerator value of RECEIVE11 field.                             */
47314   #define IPCT_INTEN2_RECEIVE11_Max (0x1UL)          /*!< Max enumerator value of RECEIVE11 field.                             */
47315   #define IPCT_INTEN2_RECEIVE11_Disabled (0x0UL)     /*!< Disable                                                              */
47316   #define IPCT_INTEN2_RECEIVE11_Enabled (0x1UL)      /*!< Enable                                                               */
47317 
47318 /* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
47319   #define IPCT_INTEN2_RECEIVE12_Pos (12UL)           /*!< Position of RECEIVE12 field.                                         */
47320   #define IPCT_INTEN2_RECEIVE12_Msk (0x1UL << IPCT_INTEN2_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                     */
47321   #define IPCT_INTEN2_RECEIVE12_Min (0x0UL)          /*!< Min enumerator value of RECEIVE12 field.                             */
47322   #define IPCT_INTEN2_RECEIVE12_Max (0x1UL)          /*!< Max enumerator value of RECEIVE12 field.                             */
47323   #define IPCT_INTEN2_RECEIVE12_Disabled (0x0UL)     /*!< Disable                                                              */
47324   #define IPCT_INTEN2_RECEIVE12_Enabled (0x1UL)      /*!< Enable                                                               */
47325 
47326 /* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
47327   #define IPCT_INTEN2_RECEIVE13_Pos (13UL)           /*!< Position of RECEIVE13 field.                                         */
47328   #define IPCT_INTEN2_RECEIVE13_Msk (0x1UL << IPCT_INTEN2_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                     */
47329   #define IPCT_INTEN2_RECEIVE13_Min (0x0UL)          /*!< Min enumerator value of RECEIVE13 field.                             */
47330   #define IPCT_INTEN2_RECEIVE13_Max (0x1UL)          /*!< Max enumerator value of RECEIVE13 field.                             */
47331   #define IPCT_INTEN2_RECEIVE13_Disabled (0x0UL)     /*!< Disable                                                              */
47332   #define IPCT_INTEN2_RECEIVE13_Enabled (0x1UL)      /*!< Enable                                                               */
47333 
47334 /* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
47335   #define IPCT_INTEN2_RECEIVE14_Pos (14UL)           /*!< Position of RECEIVE14 field.                                         */
47336   #define IPCT_INTEN2_RECEIVE14_Msk (0x1UL << IPCT_INTEN2_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                     */
47337   #define IPCT_INTEN2_RECEIVE14_Min (0x0UL)          /*!< Min enumerator value of RECEIVE14 field.                             */
47338   #define IPCT_INTEN2_RECEIVE14_Max (0x1UL)          /*!< Max enumerator value of RECEIVE14 field.                             */
47339   #define IPCT_INTEN2_RECEIVE14_Disabled (0x0UL)     /*!< Disable                                                              */
47340   #define IPCT_INTEN2_RECEIVE14_Enabled (0x1UL)      /*!< Enable                                                               */
47341 
47342 /* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
47343   #define IPCT_INTEN2_RECEIVE15_Pos (15UL)           /*!< Position of RECEIVE15 field.                                         */
47344   #define IPCT_INTEN2_RECEIVE15_Msk (0x1UL << IPCT_INTEN2_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                     */
47345   #define IPCT_INTEN2_RECEIVE15_Min (0x0UL)          /*!< Min enumerator value of RECEIVE15 field.                             */
47346   #define IPCT_INTEN2_RECEIVE15_Max (0x1UL)          /*!< Max enumerator value of RECEIVE15 field.                             */
47347   #define IPCT_INTEN2_RECEIVE15_Disabled (0x0UL)     /*!< Disable                                                              */
47348   #define IPCT_INTEN2_RECEIVE15_Enabled (0x1UL)      /*!< Enable                                                               */
47349 
47350 /* ACKED0 @Bit 16 : Enable or disable interrupt for event ACKED[0] */
47351   #define IPCT_INTEN2_ACKED0_Pos (16UL)              /*!< Position of ACKED0 field.                                            */
47352   #define IPCT_INTEN2_ACKED0_Msk (0x1UL << IPCT_INTEN2_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                              */
47353   #define IPCT_INTEN2_ACKED0_Min (0x0UL)             /*!< Min enumerator value of ACKED0 field.                                */
47354   #define IPCT_INTEN2_ACKED0_Max (0x1UL)             /*!< Max enumerator value of ACKED0 field.                                */
47355   #define IPCT_INTEN2_ACKED0_Disabled (0x0UL)        /*!< Disable                                                              */
47356   #define IPCT_INTEN2_ACKED0_Enabled (0x1UL)         /*!< Enable                                                               */
47357 
47358 /* ACKED1 @Bit 17 : Enable or disable interrupt for event ACKED[1] */
47359   #define IPCT_INTEN2_ACKED1_Pos (17UL)              /*!< Position of ACKED1 field.                                            */
47360   #define IPCT_INTEN2_ACKED1_Msk (0x1UL << IPCT_INTEN2_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                              */
47361   #define IPCT_INTEN2_ACKED1_Min (0x0UL)             /*!< Min enumerator value of ACKED1 field.                                */
47362   #define IPCT_INTEN2_ACKED1_Max (0x1UL)             /*!< Max enumerator value of ACKED1 field.                                */
47363   #define IPCT_INTEN2_ACKED1_Disabled (0x0UL)        /*!< Disable                                                              */
47364   #define IPCT_INTEN2_ACKED1_Enabled (0x1UL)         /*!< Enable                                                               */
47365 
47366 /* ACKED2 @Bit 18 : Enable or disable interrupt for event ACKED[2] */
47367   #define IPCT_INTEN2_ACKED2_Pos (18UL)              /*!< Position of ACKED2 field.                                            */
47368   #define IPCT_INTEN2_ACKED2_Msk (0x1UL << IPCT_INTEN2_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                              */
47369   #define IPCT_INTEN2_ACKED2_Min (0x0UL)             /*!< Min enumerator value of ACKED2 field.                                */
47370   #define IPCT_INTEN2_ACKED2_Max (0x1UL)             /*!< Max enumerator value of ACKED2 field.                                */
47371   #define IPCT_INTEN2_ACKED2_Disabled (0x0UL)        /*!< Disable                                                              */
47372   #define IPCT_INTEN2_ACKED2_Enabled (0x1UL)         /*!< Enable                                                               */
47373 
47374 /* ACKED3 @Bit 19 : Enable or disable interrupt for event ACKED[3] */
47375   #define IPCT_INTEN2_ACKED3_Pos (19UL)              /*!< Position of ACKED3 field.                                            */
47376   #define IPCT_INTEN2_ACKED3_Msk (0x1UL << IPCT_INTEN2_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                              */
47377   #define IPCT_INTEN2_ACKED3_Min (0x0UL)             /*!< Min enumerator value of ACKED3 field.                                */
47378   #define IPCT_INTEN2_ACKED3_Max (0x1UL)             /*!< Max enumerator value of ACKED3 field.                                */
47379   #define IPCT_INTEN2_ACKED3_Disabled (0x0UL)        /*!< Disable                                                              */
47380   #define IPCT_INTEN2_ACKED3_Enabled (0x1UL)         /*!< Enable                                                               */
47381 
47382 /* ACKED4 @Bit 20 : Enable or disable interrupt for event ACKED[4] */
47383   #define IPCT_INTEN2_ACKED4_Pos (20UL)              /*!< Position of ACKED4 field.                                            */
47384   #define IPCT_INTEN2_ACKED4_Msk (0x1UL << IPCT_INTEN2_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                              */
47385   #define IPCT_INTEN2_ACKED4_Min (0x0UL)             /*!< Min enumerator value of ACKED4 field.                                */
47386   #define IPCT_INTEN2_ACKED4_Max (0x1UL)             /*!< Max enumerator value of ACKED4 field.                                */
47387   #define IPCT_INTEN2_ACKED4_Disabled (0x0UL)        /*!< Disable                                                              */
47388   #define IPCT_INTEN2_ACKED4_Enabled (0x1UL)         /*!< Enable                                                               */
47389 
47390 /* ACKED5 @Bit 21 : Enable or disable interrupt for event ACKED[5] */
47391   #define IPCT_INTEN2_ACKED5_Pos (21UL)              /*!< Position of ACKED5 field.                                            */
47392   #define IPCT_INTEN2_ACKED5_Msk (0x1UL << IPCT_INTEN2_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                              */
47393   #define IPCT_INTEN2_ACKED5_Min (0x0UL)             /*!< Min enumerator value of ACKED5 field.                                */
47394   #define IPCT_INTEN2_ACKED5_Max (0x1UL)             /*!< Max enumerator value of ACKED5 field.                                */
47395   #define IPCT_INTEN2_ACKED5_Disabled (0x0UL)        /*!< Disable                                                              */
47396   #define IPCT_INTEN2_ACKED5_Enabled (0x1UL)         /*!< Enable                                                               */
47397 
47398 /* ACKED6 @Bit 22 : Enable or disable interrupt for event ACKED[6] */
47399   #define IPCT_INTEN2_ACKED6_Pos (22UL)              /*!< Position of ACKED6 field.                                            */
47400   #define IPCT_INTEN2_ACKED6_Msk (0x1UL << IPCT_INTEN2_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                              */
47401   #define IPCT_INTEN2_ACKED6_Min (0x0UL)             /*!< Min enumerator value of ACKED6 field.                                */
47402   #define IPCT_INTEN2_ACKED6_Max (0x1UL)             /*!< Max enumerator value of ACKED6 field.                                */
47403   #define IPCT_INTEN2_ACKED6_Disabled (0x0UL)        /*!< Disable                                                              */
47404   #define IPCT_INTEN2_ACKED6_Enabled (0x1UL)         /*!< Enable                                                               */
47405 
47406 /* ACKED7 @Bit 23 : Enable or disable interrupt for event ACKED[7] */
47407   #define IPCT_INTEN2_ACKED7_Pos (23UL)              /*!< Position of ACKED7 field.                                            */
47408   #define IPCT_INTEN2_ACKED7_Msk (0x1UL << IPCT_INTEN2_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                              */
47409   #define IPCT_INTEN2_ACKED7_Min (0x0UL)             /*!< Min enumerator value of ACKED7 field.                                */
47410   #define IPCT_INTEN2_ACKED7_Max (0x1UL)             /*!< Max enumerator value of ACKED7 field.                                */
47411   #define IPCT_INTEN2_ACKED7_Disabled (0x0UL)        /*!< Disable                                                              */
47412   #define IPCT_INTEN2_ACKED7_Enabled (0x1UL)         /*!< Enable                                                               */
47413 
47414 /* ACKED8 @Bit 24 : Enable or disable interrupt for event ACKED[8] */
47415   #define IPCT_INTEN2_ACKED8_Pos (24UL)              /*!< Position of ACKED8 field.                                            */
47416   #define IPCT_INTEN2_ACKED8_Msk (0x1UL << IPCT_INTEN2_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                              */
47417   #define IPCT_INTEN2_ACKED8_Min (0x0UL)             /*!< Min enumerator value of ACKED8 field.                                */
47418   #define IPCT_INTEN2_ACKED8_Max (0x1UL)             /*!< Max enumerator value of ACKED8 field.                                */
47419   #define IPCT_INTEN2_ACKED8_Disabled (0x0UL)        /*!< Disable                                                              */
47420   #define IPCT_INTEN2_ACKED8_Enabled (0x1UL)         /*!< Enable                                                               */
47421 
47422 /* ACKED9 @Bit 25 : Enable or disable interrupt for event ACKED[9] */
47423   #define IPCT_INTEN2_ACKED9_Pos (25UL)              /*!< Position of ACKED9 field.                                            */
47424   #define IPCT_INTEN2_ACKED9_Msk (0x1UL << IPCT_INTEN2_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                              */
47425   #define IPCT_INTEN2_ACKED9_Min (0x0UL)             /*!< Min enumerator value of ACKED9 field.                                */
47426   #define IPCT_INTEN2_ACKED9_Max (0x1UL)             /*!< Max enumerator value of ACKED9 field.                                */
47427   #define IPCT_INTEN2_ACKED9_Disabled (0x0UL)        /*!< Disable                                                              */
47428   #define IPCT_INTEN2_ACKED9_Enabled (0x1UL)         /*!< Enable                                                               */
47429 
47430 /* ACKED10 @Bit 26 : Enable or disable interrupt for event ACKED[10] */
47431   #define IPCT_INTEN2_ACKED10_Pos (26UL)             /*!< Position of ACKED10 field.                                           */
47432   #define IPCT_INTEN2_ACKED10_Msk (0x1UL << IPCT_INTEN2_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                           */
47433   #define IPCT_INTEN2_ACKED10_Min (0x0UL)            /*!< Min enumerator value of ACKED10 field.                               */
47434   #define IPCT_INTEN2_ACKED10_Max (0x1UL)            /*!< Max enumerator value of ACKED10 field.                               */
47435   #define IPCT_INTEN2_ACKED10_Disabled (0x0UL)       /*!< Disable                                                              */
47436   #define IPCT_INTEN2_ACKED10_Enabled (0x1UL)        /*!< Enable                                                               */
47437 
47438 /* ACKED11 @Bit 27 : Enable or disable interrupt for event ACKED[11] */
47439   #define IPCT_INTEN2_ACKED11_Pos (27UL)             /*!< Position of ACKED11 field.                                           */
47440   #define IPCT_INTEN2_ACKED11_Msk (0x1UL << IPCT_INTEN2_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                           */
47441   #define IPCT_INTEN2_ACKED11_Min (0x0UL)            /*!< Min enumerator value of ACKED11 field.                               */
47442   #define IPCT_INTEN2_ACKED11_Max (0x1UL)            /*!< Max enumerator value of ACKED11 field.                               */
47443   #define IPCT_INTEN2_ACKED11_Disabled (0x0UL)       /*!< Disable                                                              */
47444   #define IPCT_INTEN2_ACKED11_Enabled (0x1UL)        /*!< Enable                                                               */
47445 
47446 /* ACKED12 @Bit 28 : Enable or disable interrupt for event ACKED[12] */
47447   #define IPCT_INTEN2_ACKED12_Pos (28UL)             /*!< Position of ACKED12 field.                                           */
47448   #define IPCT_INTEN2_ACKED12_Msk (0x1UL << IPCT_INTEN2_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                           */
47449   #define IPCT_INTEN2_ACKED12_Min (0x0UL)            /*!< Min enumerator value of ACKED12 field.                               */
47450   #define IPCT_INTEN2_ACKED12_Max (0x1UL)            /*!< Max enumerator value of ACKED12 field.                               */
47451   #define IPCT_INTEN2_ACKED12_Disabled (0x0UL)       /*!< Disable                                                              */
47452   #define IPCT_INTEN2_ACKED12_Enabled (0x1UL)        /*!< Enable                                                               */
47453 
47454 /* ACKED13 @Bit 29 : Enable or disable interrupt for event ACKED[13] */
47455   #define IPCT_INTEN2_ACKED13_Pos (29UL)             /*!< Position of ACKED13 field.                                           */
47456   #define IPCT_INTEN2_ACKED13_Msk (0x1UL << IPCT_INTEN2_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                           */
47457   #define IPCT_INTEN2_ACKED13_Min (0x0UL)            /*!< Min enumerator value of ACKED13 field.                               */
47458   #define IPCT_INTEN2_ACKED13_Max (0x1UL)            /*!< Max enumerator value of ACKED13 field.                               */
47459   #define IPCT_INTEN2_ACKED13_Disabled (0x0UL)       /*!< Disable                                                              */
47460   #define IPCT_INTEN2_ACKED13_Enabled (0x1UL)        /*!< Enable                                                               */
47461 
47462 /* ACKED14 @Bit 30 : Enable or disable interrupt for event ACKED[14] */
47463   #define IPCT_INTEN2_ACKED14_Pos (30UL)             /*!< Position of ACKED14 field.                                           */
47464   #define IPCT_INTEN2_ACKED14_Msk (0x1UL << IPCT_INTEN2_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                           */
47465   #define IPCT_INTEN2_ACKED14_Min (0x0UL)            /*!< Min enumerator value of ACKED14 field.                               */
47466   #define IPCT_INTEN2_ACKED14_Max (0x1UL)            /*!< Max enumerator value of ACKED14 field.                               */
47467   #define IPCT_INTEN2_ACKED14_Disabled (0x0UL)       /*!< Disable                                                              */
47468   #define IPCT_INTEN2_ACKED14_Enabled (0x1UL)        /*!< Enable                                                               */
47469 
47470 /* ACKED15 @Bit 31 : Enable or disable interrupt for event ACKED[15] */
47471   #define IPCT_INTEN2_ACKED15_Pos (31UL)             /*!< Position of ACKED15 field.                                           */
47472   #define IPCT_INTEN2_ACKED15_Msk (0x1UL << IPCT_INTEN2_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                           */
47473   #define IPCT_INTEN2_ACKED15_Min (0x0UL)            /*!< Min enumerator value of ACKED15 field.                               */
47474   #define IPCT_INTEN2_ACKED15_Max (0x1UL)            /*!< Max enumerator value of ACKED15 field.                               */
47475   #define IPCT_INTEN2_ACKED15_Disabled (0x0UL)       /*!< Disable                                                              */
47476   #define IPCT_INTEN2_ACKED15_Enabled (0x1UL)        /*!< Enable                                                               */
47477 
47478 
47479 /* IPCT_INTENSET2: Enable interrupt */
47480   #define IPCT_INTENSET2_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET2 register.                                   */
47481 
47482 /* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
47483   #define IPCT_INTENSET2_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
47484   #define IPCT_INTENSET2_RECEIVE0_Msk (0x1UL << IPCT_INTENSET2_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
47485   #define IPCT_INTENSET2_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
47486   #define IPCT_INTENSET2_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
47487   #define IPCT_INTENSET2_RECEIVE0_Set (0x1UL)        /*!< Enable                                                               */
47488   #define IPCT_INTENSET2_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47489   #define IPCT_INTENSET2_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47490 
47491 /* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
47492   #define IPCT_INTENSET2_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
47493   #define IPCT_INTENSET2_RECEIVE1_Msk (0x1UL << IPCT_INTENSET2_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
47494   #define IPCT_INTENSET2_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
47495   #define IPCT_INTENSET2_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
47496   #define IPCT_INTENSET2_RECEIVE1_Set (0x1UL)        /*!< Enable                                                               */
47497   #define IPCT_INTENSET2_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47498   #define IPCT_INTENSET2_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47499 
47500 /* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
47501   #define IPCT_INTENSET2_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
47502   #define IPCT_INTENSET2_RECEIVE2_Msk (0x1UL << IPCT_INTENSET2_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
47503   #define IPCT_INTENSET2_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
47504   #define IPCT_INTENSET2_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
47505   #define IPCT_INTENSET2_RECEIVE2_Set (0x1UL)        /*!< Enable                                                               */
47506   #define IPCT_INTENSET2_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47507   #define IPCT_INTENSET2_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47508 
47509 /* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
47510   #define IPCT_INTENSET2_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
47511   #define IPCT_INTENSET2_RECEIVE3_Msk (0x1UL << IPCT_INTENSET2_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
47512   #define IPCT_INTENSET2_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
47513   #define IPCT_INTENSET2_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
47514   #define IPCT_INTENSET2_RECEIVE3_Set (0x1UL)        /*!< Enable                                                               */
47515   #define IPCT_INTENSET2_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47516   #define IPCT_INTENSET2_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47517 
47518 /* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
47519   #define IPCT_INTENSET2_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
47520   #define IPCT_INTENSET2_RECEIVE4_Msk (0x1UL << IPCT_INTENSET2_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
47521   #define IPCT_INTENSET2_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
47522   #define IPCT_INTENSET2_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
47523   #define IPCT_INTENSET2_RECEIVE4_Set (0x1UL)        /*!< Enable                                                               */
47524   #define IPCT_INTENSET2_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47525   #define IPCT_INTENSET2_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47526 
47527 /* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
47528   #define IPCT_INTENSET2_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
47529   #define IPCT_INTENSET2_RECEIVE5_Msk (0x1UL << IPCT_INTENSET2_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
47530   #define IPCT_INTENSET2_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
47531   #define IPCT_INTENSET2_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
47532   #define IPCT_INTENSET2_RECEIVE5_Set (0x1UL)        /*!< Enable                                                               */
47533   #define IPCT_INTENSET2_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47534   #define IPCT_INTENSET2_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47535 
47536 /* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
47537   #define IPCT_INTENSET2_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
47538   #define IPCT_INTENSET2_RECEIVE6_Msk (0x1UL << IPCT_INTENSET2_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
47539   #define IPCT_INTENSET2_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
47540   #define IPCT_INTENSET2_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
47541   #define IPCT_INTENSET2_RECEIVE6_Set (0x1UL)        /*!< Enable                                                               */
47542   #define IPCT_INTENSET2_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47543   #define IPCT_INTENSET2_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47544 
47545 /* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
47546   #define IPCT_INTENSET2_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
47547   #define IPCT_INTENSET2_RECEIVE7_Msk (0x1UL << IPCT_INTENSET2_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
47548   #define IPCT_INTENSET2_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
47549   #define IPCT_INTENSET2_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
47550   #define IPCT_INTENSET2_RECEIVE7_Set (0x1UL)        /*!< Enable                                                               */
47551   #define IPCT_INTENSET2_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47552   #define IPCT_INTENSET2_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47553 
47554 /* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
47555   #define IPCT_INTENSET2_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
47556   #define IPCT_INTENSET2_RECEIVE8_Msk (0x1UL << IPCT_INTENSET2_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
47557   #define IPCT_INTENSET2_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
47558   #define IPCT_INTENSET2_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
47559   #define IPCT_INTENSET2_RECEIVE8_Set (0x1UL)        /*!< Enable                                                               */
47560   #define IPCT_INTENSET2_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47561   #define IPCT_INTENSET2_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47562 
47563 /* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
47564   #define IPCT_INTENSET2_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
47565   #define IPCT_INTENSET2_RECEIVE9_Msk (0x1UL << IPCT_INTENSET2_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
47566   #define IPCT_INTENSET2_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
47567   #define IPCT_INTENSET2_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
47568   #define IPCT_INTENSET2_RECEIVE9_Set (0x1UL)        /*!< Enable                                                               */
47569   #define IPCT_INTENSET2_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47570   #define IPCT_INTENSET2_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47571 
47572 /* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
47573   #define IPCT_INTENSET2_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
47574   #define IPCT_INTENSET2_RECEIVE10_Msk (0x1UL << IPCT_INTENSET2_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
47575   #define IPCT_INTENSET2_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
47576   #define IPCT_INTENSET2_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
47577   #define IPCT_INTENSET2_RECEIVE10_Set (0x1UL)       /*!< Enable                                                               */
47578   #define IPCT_INTENSET2_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47579   #define IPCT_INTENSET2_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47580 
47581 /* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
47582   #define IPCT_INTENSET2_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
47583   #define IPCT_INTENSET2_RECEIVE11_Msk (0x1UL << IPCT_INTENSET2_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
47584   #define IPCT_INTENSET2_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
47585   #define IPCT_INTENSET2_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
47586   #define IPCT_INTENSET2_RECEIVE11_Set (0x1UL)       /*!< Enable                                                               */
47587   #define IPCT_INTENSET2_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47588   #define IPCT_INTENSET2_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47589 
47590 /* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
47591   #define IPCT_INTENSET2_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
47592   #define IPCT_INTENSET2_RECEIVE12_Msk (0x1UL << IPCT_INTENSET2_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
47593   #define IPCT_INTENSET2_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
47594   #define IPCT_INTENSET2_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
47595   #define IPCT_INTENSET2_RECEIVE12_Set (0x1UL)       /*!< Enable                                                               */
47596   #define IPCT_INTENSET2_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47597   #define IPCT_INTENSET2_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47598 
47599 /* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
47600   #define IPCT_INTENSET2_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
47601   #define IPCT_INTENSET2_RECEIVE13_Msk (0x1UL << IPCT_INTENSET2_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
47602   #define IPCT_INTENSET2_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
47603   #define IPCT_INTENSET2_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
47604   #define IPCT_INTENSET2_RECEIVE13_Set (0x1UL)       /*!< Enable                                                               */
47605   #define IPCT_INTENSET2_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47606   #define IPCT_INTENSET2_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47607 
47608 /* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
47609   #define IPCT_INTENSET2_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
47610   #define IPCT_INTENSET2_RECEIVE14_Msk (0x1UL << IPCT_INTENSET2_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
47611   #define IPCT_INTENSET2_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
47612   #define IPCT_INTENSET2_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
47613   #define IPCT_INTENSET2_RECEIVE14_Set (0x1UL)       /*!< Enable                                                               */
47614   #define IPCT_INTENSET2_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47615   #define IPCT_INTENSET2_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47616 
47617 /* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
47618   #define IPCT_INTENSET2_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
47619   #define IPCT_INTENSET2_RECEIVE15_Msk (0x1UL << IPCT_INTENSET2_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
47620   #define IPCT_INTENSET2_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
47621   #define IPCT_INTENSET2_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
47622   #define IPCT_INTENSET2_RECEIVE15_Set (0x1UL)       /*!< Enable                                                               */
47623   #define IPCT_INTENSET2_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47624   #define IPCT_INTENSET2_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47625 
47626 /* ACKED0 @Bit 16 : Write '1' to enable interrupt for event ACKED[0] */
47627   #define IPCT_INTENSET2_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
47628   #define IPCT_INTENSET2_ACKED0_Msk (0x1UL << IPCT_INTENSET2_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
47629   #define IPCT_INTENSET2_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
47630   #define IPCT_INTENSET2_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
47631   #define IPCT_INTENSET2_ACKED0_Set (0x1UL)          /*!< Enable                                                               */
47632   #define IPCT_INTENSET2_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47633   #define IPCT_INTENSET2_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47634 
47635 /* ACKED1 @Bit 17 : Write '1' to enable interrupt for event ACKED[1] */
47636   #define IPCT_INTENSET2_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
47637   #define IPCT_INTENSET2_ACKED1_Msk (0x1UL << IPCT_INTENSET2_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
47638   #define IPCT_INTENSET2_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
47639   #define IPCT_INTENSET2_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
47640   #define IPCT_INTENSET2_ACKED1_Set (0x1UL)          /*!< Enable                                                               */
47641   #define IPCT_INTENSET2_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47642   #define IPCT_INTENSET2_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47643 
47644 /* ACKED2 @Bit 18 : Write '1' to enable interrupt for event ACKED[2] */
47645   #define IPCT_INTENSET2_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
47646   #define IPCT_INTENSET2_ACKED2_Msk (0x1UL << IPCT_INTENSET2_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
47647   #define IPCT_INTENSET2_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
47648   #define IPCT_INTENSET2_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
47649   #define IPCT_INTENSET2_ACKED2_Set (0x1UL)          /*!< Enable                                                               */
47650   #define IPCT_INTENSET2_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47651   #define IPCT_INTENSET2_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47652 
47653 /* ACKED3 @Bit 19 : Write '1' to enable interrupt for event ACKED[3] */
47654   #define IPCT_INTENSET2_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
47655   #define IPCT_INTENSET2_ACKED3_Msk (0x1UL << IPCT_INTENSET2_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
47656   #define IPCT_INTENSET2_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
47657   #define IPCT_INTENSET2_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
47658   #define IPCT_INTENSET2_ACKED3_Set (0x1UL)          /*!< Enable                                                               */
47659   #define IPCT_INTENSET2_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47660   #define IPCT_INTENSET2_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47661 
47662 /* ACKED4 @Bit 20 : Write '1' to enable interrupt for event ACKED[4] */
47663   #define IPCT_INTENSET2_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
47664   #define IPCT_INTENSET2_ACKED4_Msk (0x1UL << IPCT_INTENSET2_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
47665   #define IPCT_INTENSET2_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
47666   #define IPCT_INTENSET2_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
47667   #define IPCT_INTENSET2_ACKED4_Set (0x1UL)          /*!< Enable                                                               */
47668   #define IPCT_INTENSET2_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47669   #define IPCT_INTENSET2_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47670 
47671 /* ACKED5 @Bit 21 : Write '1' to enable interrupt for event ACKED[5] */
47672   #define IPCT_INTENSET2_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
47673   #define IPCT_INTENSET2_ACKED5_Msk (0x1UL << IPCT_INTENSET2_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
47674   #define IPCT_INTENSET2_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
47675   #define IPCT_INTENSET2_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
47676   #define IPCT_INTENSET2_ACKED5_Set (0x1UL)          /*!< Enable                                                               */
47677   #define IPCT_INTENSET2_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47678   #define IPCT_INTENSET2_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47679 
47680 /* ACKED6 @Bit 22 : Write '1' to enable interrupt for event ACKED[6] */
47681   #define IPCT_INTENSET2_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
47682   #define IPCT_INTENSET2_ACKED6_Msk (0x1UL << IPCT_INTENSET2_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
47683   #define IPCT_INTENSET2_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
47684   #define IPCT_INTENSET2_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
47685   #define IPCT_INTENSET2_ACKED6_Set (0x1UL)          /*!< Enable                                                               */
47686   #define IPCT_INTENSET2_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47687   #define IPCT_INTENSET2_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47688 
47689 /* ACKED7 @Bit 23 : Write '1' to enable interrupt for event ACKED[7] */
47690   #define IPCT_INTENSET2_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
47691   #define IPCT_INTENSET2_ACKED7_Msk (0x1UL << IPCT_INTENSET2_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
47692   #define IPCT_INTENSET2_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
47693   #define IPCT_INTENSET2_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
47694   #define IPCT_INTENSET2_ACKED7_Set (0x1UL)          /*!< Enable                                                               */
47695   #define IPCT_INTENSET2_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47696   #define IPCT_INTENSET2_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47697 
47698 /* ACKED8 @Bit 24 : Write '1' to enable interrupt for event ACKED[8] */
47699   #define IPCT_INTENSET2_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
47700   #define IPCT_INTENSET2_ACKED8_Msk (0x1UL << IPCT_INTENSET2_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
47701   #define IPCT_INTENSET2_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
47702   #define IPCT_INTENSET2_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
47703   #define IPCT_INTENSET2_ACKED8_Set (0x1UL)          /*!< Enable                                                               */
47704   #define IPCT_INTENSET2_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47705   #define IPCT_INTENSET2_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47706 
47707 /* ACKED9 @Bit 25 : Write '1' to enable interrupt for event ACKED[9] */
47708   #define IPCT_INTENSET2_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
47709   #define IPCT_INTENSET2_ACKED9_Msk (0x1UL << IPCT_INTENSET2_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
47710   #define IPCT_INTENSET2_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
47711   #define IPCT_INTENSET2_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
47712   #define IPCT_INTENSET2_ACKED9_Set (0x1UL)          /*!< Enable                                                               */
47713   #define IPCT_INTENSET2_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47714   #define IPCT_INTENSET2_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47715 
47716 /* ACKED10 @Bit 26 : Write '1' to enable interrupt for event ACKED[10] */
47717   #define IPCT_INTENSET2_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
47718   #define IPCT_INTENSET2_ACKED10_Msk (0x1UL << IPCT_INTENSET2_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
47719   #define IPCT_INTENSET2_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
47720   #define IPCT_INTENSET2_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
47721   #define IPCT_INTENSET2_ACKED10_Set (0x1UL)         /*!< Enable                                                               */
47722   #define IPCT_INTENSET2_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
47723   #define IPCT_INTENSET2_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
47724 
47725 /* ACKED11 @Bit 27 : Write '1' to enable interrupt for event ACKED[11] */
47726   #define IPCT_INTENSET2_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
47727   #define IPCT_INTENSET2_ACKED11_Msk (0x1UL << IPCT_INTENSET2_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
47728   #define IPCT_INTENSET2_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
47729   #define IPCT_INTENSET2_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
47730   #define IPCT_INTENSET2_ACKED11_Set (0x1UL)         /*!< Enable                                                               */
47731   #define IPCT_INTENSET2_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
47732   #define IPCT_INTENSET2_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
47733 
47734 /* ACKED12 @Bit 28 : Write '1' to enable interrupt for event ACKED[12] */
47735   #define IPCT_INTENSET2_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
47736   #define IPCT_INTENSET2_ACKED12_Msk (0x1UL << IPCT_INTENSET2_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
47737   #define IPCT_INTENSET2_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
47738   #define IPCT_INTENSET2_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
47739   #define IPCT_INTENSET2_ACKED12_Set (0x1UL)         /*!< Enable                                                               */
47740   #define IPCT_INTENSET2_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
47741   #define IPCT_INTENSET2_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
47742 
47743 /* ACKED13 @Bit 29 : Write '1' to enable interrupt for event ACKED[13] */
47744   #define IPCT_INTENSET2_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
47745   #define IPCT_INTENSET2_ACKED13_Msk (0x1UL << IPCT_INTENSET2_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
47746   #define IPCT_INTENSET2_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
47747   #define IPCT_INTENSET2_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
47748   #define IPCT_INTENSET2_ACKED13_Set (0x1UL)         /*!< Enable                                                               */
47749   #define IPCT_INTENSET2_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
47750   #define IPCT_INTENSET2_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
47751 
47752 /* ACKED14 @Bit 30 : Write '1' to enable interrupt for event ACKED[14] */
47753   #define IPCT_INTENSET2_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
47754   #define IPCT_INTENSET2_ACKED14_Msk (0x1UL << IPCT_INTENSET2_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
47755   #define IPCT_INTENSET2_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
47756   #define IPCT_INTENSET2_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
47757   #define IPCT_INTENSET2_ACKED14_Set (0x1UL)         /*!< Enable                                                               */
47758   #define IPCT_INTENSET2_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
47759   #define IPCT_INTENSET2_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
47760 
47761 /* ACKED15 @Bit 31 : Write '1' to enable interrupt for event ACKED[15] */
47762   #define IPCT_INTENSET2_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
47763   #define IPCT_INTENSET2_ACKED15_Msk (0x1UL << IPCT_INTENSET2_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
47764   #define IPCT_INTENSET2_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
47765   #define IPCT_INTENSET2_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
47766   #define IPCT_INTENSET2_ACKED15_Set (0x1UL)         /*!< Enable                                                               */
47767   #define IPCT_INTENSET2_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
47768   #define IPCT_INTENSET2_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
47769 
47770 
47771 /* IPCT_INTENCLR2: Disable interrupt */
47772   #define IPCT_INTENCLR2_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR2 register.                                   */
47773 
47774 /* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
47775   #define IPCT_INTENCLR2_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
47776   #define IPCT_INTENCLR2_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
47777   #define IPCT_INTENCLR2_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
47778   #define IPCT_INTENCLR2_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
47779   #define IPCT_INTENCLR2_RECEIVE0_Clear (0x1UL)      /*!< Disable                                                              */
47780   #define IPCT_INTENCLR2_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47781   #define IPCT_INTENCLR2_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47782 
47783 /* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
47784   #define IPCT_INTENCLR2_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
47785   #define IPCT_INTENCLR2_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
47786   #define IPCT_INTENCLR2_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
47787   #define IPCT_INTENCLR2_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
47788   #define IPCT_INTENCLR2_RECEIVE1_Clear (0x1UL)      /*!< Disable                                                              */
47789   #define IPCT_INTENCLR2_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47790   #define IPCT_INTENCLR2_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47791 
47792 /* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
47793   #define IPCT_INTENCLR2_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
47794   #define IPCT_INTENCLR2_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
47795   #define IPCT_INTENCLR2_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
47796   #define IPCT_INTENCLR2_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
47797   #define IPCT_INTENCLR2_RECEIVE2_Clear (0x1UL)      /*!< Disable                                                              */
47798   #define IPCT_INTENCLR2_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47799   #define IPCT_INTENCLR2_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47800 
47801 /* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
47802   #define IPCT_INTENCLR2_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
47803   #define IPCT_INTENCLR2_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
47804   #define IPCT_INTENCLR2_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
47805   #define IPCT_INTENCLR2_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
47806   #define IPCT_INTENCLR2_RECEIVE3_Clear (0x1UL)      /*!< Disable                                                              */
47807   #define IPCT_INTENCLR2_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47808   #define IPCT_INTENCLR2_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47809 
47810 /* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
47811   #define IPCT_INTENCLR2_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
47812   #define IPCT_INTENCLR2_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
47813   #define IPCT_INTENCLR2_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
47814   #define IPCT_INTENCLR2_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
47815   #define IPCT_INTENCLR2_RECEIVE4_Clear (0x1UL)      /*!< Disable                                                              */
47816   #define IPCT_INTENCLR2_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47817   #define IPCT_INTENCLR2_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47818 
47819 /* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
47820   #define IPCT_INTENCLR2_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
47821   #define IPCT_INTENCLR2_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
47822   #define IPCT_INTENCLR2_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
47823   #define IPCT_INTENCLR2_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
47824   #define IPCT_INTENCLR2_RECEIVE5_Clear (0x1UL)      /*!< Disable                                                              */
47825   #define IPCT_INTENCLR2_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47826   #define IPCT_INTENCLR2_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47827 
47828 /* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
47829   #define IPCT_INTENCLR2_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
47830   #define IPCT_INTENCLR2_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
47831   #define IPCT_INTENCLR2_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
47832   #define IPCT_INTENCLR2_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
47833   #define IPCT_INTENCLR2_RECEIVE6_Clear (0x1UL)      /*!< Disable                                                              */
47834   #define IPCT_INTENCLR2_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47835   #define IPCT_INTENCLR2_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47836 
47837 /* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
47838   #define IPCT_INTENCLR2_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
47839   #define IPCT_INTENCLR2_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
47840   #define IPCT_INTENCLR2_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
47841   #define IPCT_INTENCLR2_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
47842   #define IPCT_INTENCLR2_RECEIVE7_Clear (0x1UL)      /*!< Disable                                                              */
47843   #define IPCT_INTENCLR2_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47844   #define IPCT_INTENCLR2_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47845 
47846 /* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
47847   #define IPCT_INTENCLR2_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
47848   #define IPCT_INTENCLR2_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
47849   #define IPCT_INTENCLR2_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
47850   #define IPCT_INTENCLR2_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
47851   #define IPCT_INTENCLR2_RECEIVE8_Clear (0x1UL)      /*!< Disable                                                              */
47852   #define IPCT_INTENCLR2_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47853   #define IPCT_INTENCLR2_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47854 
47855 /* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
47856   #define IPCT_INTENCLR2_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
47857   #define IPCT_INTENCLR2_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
47858   #define IPCT_INTENCLR2_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
47859   #define IPCT_INTENCLR2_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
47860   #define IPCT_INTENCLR2_RECEIVE9_Clear (0x1UL)      /*!< Disable                                                              */
47861   #define IPCT_INTENCLR2_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
47862   #define IPCT_INTENCLR2_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
47863 
47864 /* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
47865   #define IPCT_INTENCLR2_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
47866   #define IPCT_INTENCLR2_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
47867   #define IPCT_INTENCLR2_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
47868   #define IPCT_INTENCLR2_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
47869   #define IPCT_INTENCLR2_RECEIVE10_Clear (0x1UL)     /*!< Disable                                                              */
47870   #define IPCT_INTENCLR2_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47871   #define IPCT_INTENCLR2_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47872 
47873 /* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
47874   #define IPCT_INTENCLR2_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
47875   #define IPCT_INTENCLR2_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
47876   #define IPCT_INTENCLR2_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
47877   #define IPCT_INTENCLR2_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
47878   #define IPCT_INTENCLR2_RECEIVE11_Clear (0x1UL)     /*!< Disable                                                              */
47879   #define IPCT_INTENCLR2_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47880   #define IPCT_INTENCLR2_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47881 
47882 /* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
47883   #define IPCT_INTENCLR2_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
47884   #define IPCT_INTENCLR2_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
47885   #define IPCT_INTENCLR2_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
47886   #define IPCT_INTENCLR2_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
47887   #define IPCT_INTENCLR2_RECEIVE12_Clear (0x1UL)     /*!< Disable                                                              */
47888   #define IPCT_INTENCLR2_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47889   #define IPCT_INTENCLR2_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47890 
47891 /* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
47892   #define IPCT_INTENCLR2_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
47893   #define IPCT_INTENCLR2_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
47894   #define IPCT_INTENCLR2_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
47895   #define IPCT_INTENCLR2_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
47896   #define IPCT_INTENCLR2_RECEIVE13_Clear (0x1UL)     /*!< Disable                                                              */
47897   #define IPCT_INTENCLR2_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47898   #define IPCT_INTENCLR2_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47899 
47900 /* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
47901   #define IPCT_INTENCLR2_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
47902   #define IPCT_INTENCLR2_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
47903   #define IPCT_INTENCLR2_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
47904   #define IPCT_INTENCLR2_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
47905   #define IPCT_INTENCLR2_RECEIVE14_Clear (0x1UL)     /*!< Disable                                                              */
47906   #define IPCT_INTENCLR2_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47907   #define IPCT_INTENCLR2_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47908 
47909 /* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
47910   #define IPCT_INTENCLR2_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
47911   #define IPCT_INTENCLR2_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR2_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
47912   #define IPCT_INTENCLR2_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
47913   #define IPCT_INTENCLR2_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
47914   #define IPCT_INTENCLR2_RECEIVE15_Clear (0x1UL)     /*!< Disable                                                              */
47915   #define IPCT_INTENCLR2_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
47916   #define IPCT_INTENCLR2_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
47917 
47918 /* ACKED0 @Bit 16 : Write '1' to disable interrupt for event ACKED[0] */
47919   #define IPCT_INTENCLR2_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
47920   #define IPCT_INTENCLR2_ACKED0_Msk (0x1UL << IPCT_INTENCLR2_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
47921   #define IPCT_INTENCLR2_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
47922   #define IPCT_INTENCLR2_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
47923   #define IPCT_INTENCLR2_ACKED0_Clear (0x1UL)        /*!< Disable                                                              */
47924   #define IPCT_INTENCLR2_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47925   #define IPCT_INTENCLR2_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47926 
47927 /* ACKED1 @Bit 17 : Write '1' to disable interrupt for event ACKED[1] */
47928   #define IPCT_INTENCLR2_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
47929   #define IPCT_INTENCLR2_ACKED1_Msk (0x1UL << IPCT_INTENCLR2_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
47930   #define IPCT_INTENCLR2_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
47931   #define IPCT_INTENCLR2_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
47932   #define IPCT_INTENCLR2_ACKED1_Clear (0x1UL)        /*!< Disable                                                              */
47933   #define IPCT_INTENCLR2_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47934   #define IPCT_INTENCLR2_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47935 
47936 /* ACKED2 @Bit 18 : Write '1' to disable interrupt for event ACKED[2] */
47937   #define IPCT_INTENCLR2_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
47938   #define IPCT_INTENCLR2_ACKED2_Msk (0x1UL << IPCT_INTENCLR2_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
47939   #define IPCT_INTENCLR2_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
47940   #define IPCT_INTENCLR2_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
47941   #define IPCT_INTENCLR2_ACKED2_Clear (0x1UL)        /*!< Disable                                                              */
47942   #define IPCT_INTENCLR2_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47943   #define IPCT_INTENCLR2_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47944 
47945 /* ACKED3 @Bit 19 : Write '1' to disable interrupt for event ACKED[3] */
47946   #define IPCT_INTENCLR2_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
47947   #define IPCT_INTENCLR2_ACKED3_Msk (0x1UL << IPCT_INTENCLR2_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
47948   #define IPCT_INTENCLR2_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
47949   #define IPCT_INTENCLR2_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
47950   #define IPCT_INTENCLR2_ACKED3_Clear (0x1UL)        /*!< Disable                                                              */
47951   #define IPCT_INTENCLR2_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47952   #define IPCT_INTENCLR2_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47953 
47954 /* ACKED4 @Bit 20 : Write '1' to disable interrupt for event ACKED[4] */
47955   #define IPCT_INTENCLR2_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
47956   #define IPCT_INTENCLR2_ACKED4_Msk (0x1UL << IPCT_INTENCLR2_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
47957   #define IPCT_INTENCLR2_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
47958   #define IPCT_INTENCLR2_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
47959   #define IPCT_INTENCLR2_ACKED4_Clear (0x1UL)        /*!< Disable                                                              */
47960   #define IPCT_INTENCLR2_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47961   #define IPCT_INTENCLR2_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47962 
47963 /* ACKED5 @Bit 21 : Write '1' to disable interrupt for event ACKED[5] */
47964   #define IPCT_INTENCLR2_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
47965   #define IPCT_INTENCLR2_ACKED5_Msk (0x1UL << IPCT_INTENCLR2_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
47966   #define IPCT_INTENCLR2_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
47967   #define IPCT_INTENCLR2_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
47968   #define IPCT_INTENCLR2_ACKED5_Clear (0x1UL)        /*!< Disable                                                              */
47969   #define IPCT_INTENCLR2_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47970   #define IPCT_INTENCLR2_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47971 
47972 /* ACKED6 @Bit 22 : Write '1' to disable interrupt for event ACKED[6] */
47973   #define IPCT_INTENCLR2_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
47974   #define IPCT_INTENCLR2_ACKED6_Msk (0x1UL << IPCT_INTENCLR2_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
47975   #define IPCT_INTENCLR2_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
47976   #define IPCT_INTENCLR2_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
47977   #define IPCT_INTENCLR2_ACKED6_Clear (0x1UL)        /*!< Disable                                                              */
47978   #define IPCT_INTENCLR2_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47979   #define IPCT_INTENCLR2_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47980 
47981 /* ACKED7 @Bit 23 : Write '1' to disable interrupt for event ACKED[7] */
47982   #define IPCT_INTENCLR2_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
47983   #define IPCT_INTENCLR2_ACKED7_Msk (0x1UL << IPCT_INTENCLR2_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
47984   #define IPCT_INTENCLR2_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
47985   #define IPCT_INTENCLR2_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
47986   #define IPCT_INTENCLR2_ACKED7_Clear (0x1UL)        /*!< Disable                                                              */
47987   #define IPCT_INTENCLR2_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47988   #define IPCT_INTENCLR2_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47989 
47990 /* ACKED8 @Bit 24 : Write '1' to disable interrupt for event ACKED[8] */
47991   #define IPCT_INTENCLR2_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
47992   #define IPCT_INTENCLR2_ACKED8_Msk (0x1UL << IPCT_INTENCLR2_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
47993   #define IPCT_INTENCLR2_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
47994   #define IPCT_INTENCLR2_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
47995   #define IPCT_INTENCLR2_ACKED8_Clear (0x1UL)        /*!< Disable                                                              */
47996   #define IPCT_INTENCLR2_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
47997   #define IPCT_INTENCLR2_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
47998 
47999 /* ACKED9 @Bit 25 : Write '1' to disable interrupt for event ACKED[9] */
48000   #define IPCT_INTENCLR2_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
48001   #define IPCT_INTENCLR2_ACKED9_Msk (0x1UL << IPCT_INTENCLR2_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
48002   #define IPCT_INTENCLR2_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
48003   #define IPCT_INTENCLR2_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
48004   #define IPCT_INTENCLR2_ACKED9_Clear (0x1UL)        /*!< Disable                                                              */
48005   #define IPCT_INTENCLR2_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48006   #define IPCT_INTENCLR2_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48007 
48008 /* ACKED10 @Bit 26 : Write '1' to disable interrupt for event ACKED[10] */
48009   #define IPCT_INTENCLR2_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
48010   #define IPCT_INTENCLR2_ACKED10_Msk (0x1UL << IPCT_INTENCLR2_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
48011   #define IPCT_INTENCLR2_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
48012   #define IPCT_INTENCLR2_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
48013   #define IPCT_INTENCLR2_ACKED10_Clear (0x1UL)       /*!< Disable                                                              */
48014   #define IPCT_INTENCLR2_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48015   #define IPCT_INTENCLR2_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48016 
48017 /* ACKED11 @Bit 27 : Write '1' to disable interrupt for event ACKED[11] */
48018   #define IPCT_INTENCLR2_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
48019   #define IPCT_INTENCLR2_ACKED11_Msk (0x1UL << IPCT_INTENCLR2_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
48020   #define IPCT_INTENCLR2_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
48021   #define IPCT_INTENCLR2_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
48022   #define IPCT_INTENCLR2_ACKED11_Clear (0x1UL)       /*!< Disable                                                              */
48023   #define IPCT_INTENCLR2_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48024   #define IPCT_INTENCLR2_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48025 
48026 /* ACKED12 @Bit 28 : Write '1' to disable interrupt for event ACKED[12] */
48027   #define IPCT_INTENCLR2_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
48028   #define IPCT_INTENCLR2_ACKED12_Msk (0x1UL << IPCT_INTENCLR2_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
48029   #define IPCT_INTENCLR2_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
48030   #define IPCT_INTENCLR2_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
48031   #define IPCT_INTENCLR2_ACKED12_Clear (0x1UL)       /*!< Disable                                                              */
48032   #define IPCT_INTENCLR2_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48033   #define IPCT_INTENCLR2_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48034 
48035 /* ACKED13 @Bit 29 : Write '1' to disable interrupt for event ACKED[13] */
48036   #define IPCT_INTENCLR2_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
48037   #define IPCT_INTENCLR2_ACKED13_Msk (0x1UL << IPCT_INTENCLR2_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
48038   #define IPCT_INTENCLR2_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
48039   #define IPCT_INTENCLR2_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
48040   #define IPCT_INTENCLR2_ACKED13_Clear (0x1UL)       /*!< Disable                                                              */
48041   #define IPCT_INTENCLR2_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48042   #define IPCT_INTENCLR2_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48043 
48044 /* ACKED14 @Bit 30 : Write '1' to disable interrupt for event ACKED[14] */
48045   #define IPCT_INTENCLR2_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
48046   #define IPCT_INTENCLR2_ACKED14_Msk (0x1UL << IPCT_INTENCLR2_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
48047   #define IPCT_INTENCLR2_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
48048   #define IPCT_INTENCLR2_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
48049   #define IPCT_INTENCLR2_ACKED14_Clear (0x1UL)       /*!< Disable                                                              */
48050   #define IPCT_INTENCLR2_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48051   #define IPCT_INTENCLR2_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48052 
48053 /* ACKED15 @Bit 31 : Write '1' to disable interrupt for event ACKED[15] */
48054   #define IPCT_INTENCLR2_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
48055   #define IPCT_INTENCLR2_ACKED15_Msk (0x1UL << IPCT_INTENCLR2_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
48056   #define IPCT_INTENCLR2_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
48057   #define IPCT_INTENCLR2_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
48058   #define IPCT_INTENCLR2_ACKED15_Clear (0x1UL)       /*!< Disable                                                              */
48059   #define IPCT_INTENCLR2_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48060   #define IPCT_INTENCLR2_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48061 
48062 
48063 /* IPCT_INTPEND2: Pending interrupts */
48064   #define IPCT_INTPEND2_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND2 register.                                    */
48065 
48066 /* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
48067   #define IPCT_INTPEND2_RECEIVE0_Pos (0UL)           /*!< Position of RECEIVE0 field.                                          */
48068   #define IPCT_INTPEND2_RECEIVE0_Msk (0x1UL << IPCT_INTPEND2_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                    */
48069   #define IPCT_INTPEND2_RECEIVE0_Min (0x0UL)         /*!< Min enumerator value of RECEIVE0 field.                              */
48070   #define IPCT_INTPEND2_RECEIVE0_Max (0x1UL)         /*!< Max enumerator value of RECEIVE0 field.                              */
48071   #define IPCT_INTPEND2_RECEIVE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48072   #define IPCT_INTPEND2_RECEIVE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
48073 
48074 /* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
48075   #define IPCT_INTPEND2_RECEIVE1_Pos (1UL)           /*!< Position of RECEIVE1 field.                                          */
48076   #define IPCT_INTPEND2_RECEIVE1_Msk (0x1UL << IPCT_INTPEND2_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                    */
48077   #define IPCT_INTPEND2_RECEIVE1_Min (0x0UL)         /*!< Min enumerator value of RECEIVE1 field.                              */
48078   #define IPCT_INTPEND2_RECEIVE1_Max (0x1UL)         /*!< Max enumerator value of RECEIVE1 field.                              */
48079   #define IPCT_INTPEND2_RECEIVE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48080   #define IPCT_INTPEND2_RECEIVE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
48081 
48082 /* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
48083   #define IPCT_INTPEND2_RECEIVE2_Pos (2UL)           /*!< Position of RECEIVE2 field.                                          */
48084   #define IPCT_INTPEND2_RECEIVE2_Msk (0x1UL << IPCT_INTPEND2_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                    */
48085   #define IPCT_INTPEND2_RECEIVE2_Min (0x0UL)         /*!< Min enumerator value of RECEIVE2 field.                              */
48086   #define IPCT_INTPEND2_RECEIVE2_Max (0x1UL)         /*!< Max enumerator value of RECEIVE2 field.                              */
48087   #define IPCT_INTPEND2_RECEIVE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48088   #define IPCT_INTPEND2_RECEIVE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
48089 
48090 /* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
48091   #define IPCT_INTPEND2_RECEIVE3_Pos (3UL)           /*!< Position of RECEIVE3 field.                                          */
48092   #define IPCT_INTPEND2_RECEIVE3_Msk (0x1UL << IPCT_INTPEND2_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                    */
48093   #define IPCT_INTPEND2_RECEIVE3_Min (0x0UL)         /*!< Min enumerator value of RECEIVE3 field.                              */
48094   #define IPCT_INTPEND2_RECEIVE3_Max (0x1UL)         /*!< Max enumerator value of RECEIVE3 field.                              */
48095   #define IPCT_INTPEND2_RECEIVE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48096   #define IPCT_INTPEND2_RECEIVE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
48097 
48098 /* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
48099   #define IPCT_INTPEND2_RECEIVE4_Pos (4UL)           /*!< Position of RECEIVE4 field.                                          */
48100   #define IPCT_INTPEND2_RECEIVE4_Msk (0x1UL << IPCT_INTPEND2_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                    */
48101   #define IPCT_INTPEND2_RECEIVE4_Min (0x0UL)         /*!< Min enumerator value of RECEIVE4 field.                              */
48102   #define IPCT_INTPEND2_RECEIVE4_Max (0x1UL)         /*!< Max enumerator value of RECEIVE4 field.                              */
48103   #define IPCT_INTPEND2_RECEIVE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48104   #define IPCT_INTPEND2_RECEIVE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
48105 
48106 /* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
48107   #define IPCT_INTPEND2_RECEIVE5_Pos (5UL)           /*!< Position of RECEIVE5 field.                                          */
48108   #define IPCT_INTPEND2_RECEIVE5_Msk (0x1UL << IPCT_INTPEND2_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                    */
48109   #define IPCT_INTPEND2_RECEIVE5_Min (0x0UL)         /*!< Min enumerator value of RECEIVE5 field.                              */
48110   #define IPCT_INTPEND2_RECEIVE5_Max (0x1UL)         /*!< Max enumerator value of RECEIVE5 field.                              */
48111   #define IPCT_INTPEND2_RECEIVE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48112   #define IPCT_INTPEND2_RECEIVE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
48113 
48114 /* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
48115   #define IPCT_INTPEND2_RECEIVE6_Pos (6UL)           /*!< Position of RECEIVE6 field.                                          */
48116   #define IPCT_INTPEND2_RECEIVE6_Msk (0x1UL << IPCT_INTPEND2_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                    */
48117   #define IPCT_INTPEND2_RECEIVE6_Min (0x0UL)         /*!< Min enumerator value of RECEIVE6 field.                              */
48118   #define IPCT_INTPEND2_RECEIVE6_Max (0x1UL)         /*!< Max enumerator value of RECEIVE6 field.                              */
48119   #define IPCT_INTPEND2_RECEIVE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48120   #define IPCT_INTPEND2_RECEIVE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
48121 
48122 /* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
48123   #define IPCT_INTPEND2_RECEIVE7_Pos (7UL)           /*!< Position of RECEIVE7 field.                                          */
48124   #define IPCT_INTPEND2_RECEIVE7_Msk (0x1UL << IPCT_INTPEND2_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                    */
48125   #define IPCT_INTPEND2_RECEIVE7_Min (0x0UL)         /*!< Min enumerator value of RECEIVE7 field.                              */
48126   #define IPCT_INTPEND2_RECEIVE7_Max (0x1UL)         /*!< Max enumerator value of RECEIVE7 field.                              */
48127   #define IPCT_INTPEND2_RECEIVE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48128   #define IPCT_INTPEND2_RECEIVE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
48129 
48130 /* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
48131   #define IPCT_INTPEND2_RECEIVE8_Pos (8UL)           /*!< Position of RECEIVE8 field.                                          */
48132   #define IPCT_INTPEND2_RECEIVE8_Msk (0x1UL << IPCT_INTPEND2_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                    */
48133   #define IPCT_INTPEND2_RECEIVE8_Min (0x0UL)         /*!< Min enumerator value of RECEIVE8 field.                              */
48134   #define IPCT_INTPEND2_RECEIVE8_Max (0x1UL)         /*!< Max enumerator value of RECEIVE8 field.                              */
48135   #define IPCT_INTPEND2_RECEIVE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48136   #define IPCT_INTPEND2_RECEIVE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
48137 
48138 /* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
48139   #define IPCT_INTPEND2_RECEIVE9_Pos (9UL)           /*!< Position of RECEIVE9 field.                                          */
48140   #define IPCT_INTPEND2_RECEIVE9_Msk (0x1UL << IPCT_INTPEND2_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                    */
48141   #define IPCT_INTPEND2_RECEIVE9_Min (0x0UL)         /*!< Min enumerator value of RECEIVE9 field.                              */
48142   #define IPCT_INTPEND2_RECEIVE9_Max (0x1UL)         /*!< Max enumerator value of RECEIVE9 field.                              */
48143   #define IPCT_INTPEND2_RECEIVE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
48144   #define IPCT_INTPEND2_RECEIVE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
48145 
48146 /* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
48147   #define IPCT_INTPEND2_RECEIVE10_Pos (10UL)         /*!< Position of RECEIVE10 field.                                         */
48148   #define IPCT_INTPEND2_RECEIVE10_Msk (0x1UL << IPCT_INTPEND2_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                 */
48149   #define IPCT_INTPEND2_RECEIVE10_Min (0x0UL)        /*!< Min enumerator value of RECEIVE10 field.                             */
48150   #define IPCT_INTPEND2_RECEIVE10_Max (0x1UL)        /*!< Max enumerator value of RECEIVE10 field.                             */
48151   #define IPCT_INTPEND2_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
48152   #define IPCT_INTPEND2_RECEIVE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
48153 
48154 /* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
48155   #define IPCT_INTPEND2_RECEIVE11_Pos (11UL)         /*!< Position of RECEIVE11 field.                                         */
48156   #define IPCT_INTPEND2_RECEIVE11_Msk (0x1UL << IPCT_INTPEND2_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                 */
48157   #define IPCT_INTPEND2_RECEIVE11_Min (0x0UL)        /*!< Min enumerator value of RECEIVE11 field.                             */
48158   #define IPCT_INTPEND2_RECEIVE11_Max (0x1UL)        /*!< Max enumerator value of RECEIVE11 field.                             */
48159   #define IPCT_INTPEND2_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
48160   #define IPCT_INTPEND2_RECEIVE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
48161 
48162 /* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
48163   #define IPCT_INTPEND2_RECEIVE12_Pos (12UL)         /*!< Position of RECEIVE12 field.                                         */
48164   #define IPCT_INTPEND2_RECEIVE12_Msk (0x1UL << IPCT_INTPEND2_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                 */
48165   #define IPCT_INTPEND2_RECEIVE12_Min (0x0UL)        /*!< Min enumerator value of RECEIVE12 field.                             */
48166   #define IPCT_INTPEND2_RECEIVE12_Max (0x1UL)        /*!< Max enumerator value of RECEIVE12 field.                             */
48167   #define IPCT_INTPEND2_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
48168   #define IPCT_INTPEND2_RECEIVE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
48169 
48170 /* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
48171   #define IPCT_INTPEND2_RECEIVE13_Pos (13UL)         /*!< Position of RECEIVE13 field.                                         */
48172   #define IPCT_INTPEND2_RECEIVE13_Msk (0x1UL << IPCT_INTPEND2_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                 */
48173   #define IPCT_INTPEND2_RECEIVE13_Min (0x0UL)        /*!< Min enumerator value of RECEIVE13 field.                             */
48174   #define IPCT_INTPEND2_RECEIVE13_Max (0x1UL)        /*!< Max enumerator value of RECEIVE13 field.                             */
48175   #define IPCT_INTPEND2_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
48176   #define IPCT_INTPEND2_RECEIVE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
48177 
48178 /* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
48179   #define IPCT_INTPEND2_RECEIVE14_Pos (14UL)         /*!< Position of RECEIVE14 field.                                         */
48180   #define IPCT_INTPEND2_RECEIVE14_Msk (0x1UL << IPCT_INTPEND2_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                 */
48181   #define IPCT_INTPEND2_RECEIVE14_Min (0x0UL)        /*!< Min enumerator value of RECEIVE14 field.                             */
48182   #define IPCT_INTPEND2_RECEIVE14_Max (0x1UL)        /*!< Max enumerator value of RECEIVE14 field.                             */
48183   #define IPCT_INTPEND2_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
48184   #define IPCT_INTPEND2_RECEIVE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
48185 
48186 /* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
48187   #define IPCT_INTPEND2_RECEIVE15_Pos (15UL)         /*!< Position of RECEIVE15 field.                                         */
48188   #define IPCT_INTPEND2_RECEIVE15_Msk (0x1UL << IPCT_INTPEND2_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                 */
48189   #define IPCT_INTPEND2_RECEIVE15_Min (0x0UL)        /*!< Min enumerator value of RECEIVE15 field.                             */
48190   #define IPCT_INTPEND2_RECEIVE15_Max (0x1UL)        /*!< Max enumerator value of RECEIVE15 field.                             */
48191   #define IPCT_INTPEND2_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
48192   #define IPCT_INTPEND2_RECEIVE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
48193 
48194 /* ACKED0 @Bit 16 : Read pending status of interrupt for event ACKED[0] */
48195   #define IPCT_INTPEND2_ACKED0_Pos (16UL)            /*!< Position of ACKED0 field.                                            */
48196   #define IPCT_INTPEND2_ACKED0_Msk (0x1UL << IPCT_INTPEND2_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                          */
48197   #define IPCT_INTPEND2_ACKED0_Min (0x0UL)           /*!< Min enumerator value of ACKED0 field.                                */
48198   #define IPCT_INTPEND2_ACKED0_Max (0x1UL)           /*!< Max enumerator value of ACKED0 field.                                */
48199   #define IPCT_INTPEND2_ACKED0_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48200   #define IPCT_INTPEND2_ACKED0_Pending (0x1UL)       /*!< Read: Pending                                                        */
48201 
48202 /* ACKED1 @Bit 17 : Read pending status of interrupt for event ACKED[1] */
48203   #define IPCT_INTPEND2_ACKED1_Pos (17UL)            /*!< Position of ACKED1 field.                                            */
48204   #define IPCT_INTPEND2_ACKED1_Msk (0x1UL << IPCT_INTPEND2_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                          */
48205   #define IPCT_INTPEND2_ACKED1_Min (0x0UL)           /*!< Min enumerator value of ACKED1 field.                                */
48206   #define IPCT_INTPEND2_ACKED1_Max (0x1UL)           /*!< Max enumerator value of ACKED1 field.                                */
48207   #define IPCT_INTPEND2_ACKED1_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48208   #define IPCT_INTPEND2_ACKED1_Pending (0x1UL)       /*!< Read: Pending                                                        */
48209 
48210 /* ACKED2 @Bit 18 : Read pending status of interrupt for event ACKED[2] */
48211   #define IPCT_INTPEND2_ACKED2_Pos (18UL)            /*!< Position of ACKED2 field.                                            */
48212   #define IPCT_INTPEND2_ACKED2_Msk (0x1UL << IPCT_INTPEND2_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                          */
48213   #define IPCT_INTPEND2_ACKED2_Min (0x0UL)           /*!< Min enumerator value of ACKED2 field.                                */
48214   #define IPCT_INTPEND2_ACKED2_Max (0x1UL)           /*!< Max enumerator value of ACKED2 field.                                */
48215   #define IPCT_INTPEND2_ACKED2_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48216   #define IPCT_INTPEND2_ACKED2_Pending (0x1UL)       /*!< Read: Pending                                                        */
48217 
48218 /* ACKED3 @Bit 19 : Read pending status of interrupt for event ACKED[3] */
48219   #define IPCT_INTPEND2_ACKED3_Pos (19UL)            /*!< Position of ACKED3 field.                                            */
48220   #define IPCT_INTPEND2_ACKED3_Msk (0x1UL << IPCT_INTPEND2_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                          */
48221   #define IPCT_INTPEND2_ACKED3_Min (0x0UL)           /*!< Min enumerator value of ACKED3 field.                                */
48222   #define IPCT_INTPEND2_ACKED3_Max (0x1UL)           /*!< Max enumerator value of ACKED3 field.                                */
48223   #define IPCT_INTPEND2_ACKED3_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48224   #define IPCT_INTPEND2_ACKED3_Pending (0x1UL)       /*!< Read: Pending                                                        */
48225 
48226 /* ACKED4 @Bit 20 : Read pending status of interrupt for event ACKED[4] */
48227   #define IPCT_INTPEND2_ACKED4_Pos (20UL)            /*!< Position of ACKED4 field.                                            */
48228   #define IPCT_INTPEND2_ACKED4_Msk (0x1UL << IPCT_INTPEND2_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                          */
48229   #define IPCT_INTPEND2_ACKED4_Min (0x0UL)           /*!< Min enumerator value of ACKED4 field.                                */
48230   #define IPCT_INTPEND2_ACKED4_Max (0x1UL)           /*!< Max enumerator value of ACKED4 field.                                */
48231   #define IPCT_INTPEND2_ACKED4_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48232   #define IPCT_INTPEND2_ACKED4_Pending (0x1UL)       /*!< Read: Pending                                                        */
48233 
48234 /* ACKED5 @Bit 21 : Read pending status of interrupt for event ACKED[5] */
48235   #define IPCT_INTPEND2_ACKED5_Pos (21UL)            /*!< Position of ACKED5 field.                                            */
48236   #define IPCT_INTPEND2_ACKED5_Msk (0x1UL << IPCT_INTPEND2_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                          */
48237   #define IPCT_INTPEND2_ACKED5_Min (0x0UL)           /*!< Min enumerator value of ACKED5 field.                                */
48238   #define IPCT_INTPEND2_ACKED5_Max (0x1UL)           /*!< Max enumerator value of ACKED5 field.                                */
48239   #define IPCT_INTPEND2_ACKED5_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48240   #define IPCT_INTPEND2_ACKED5_Pending (0x1UL)       /*!< Read: Pending                                                        */
48241 
48242 /* ACKED6 @Bit 22 : Read pending status of interrupt for event ACKED[6] */
48243   #define IPCT_INTPEND2_ACKED6_Pos (22UL)            /*!< Position of ACKED6 field.                                            */
48244   #define IPCT_INTPEND2_ACKED6_Msk (0x1UL << IPCT_INTPEND2_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                          */
48245   #define IPCT_INTPEND2_ACKED6_Min (0x0UL)           /*!< Min enumerator value of ACKED6 field.                                */
48246   #define IPCT_INTPEND2_ACKED6_Max (0x1UL)           /*!< Max enumerator value of ACKED6 field.                                */
48247   #define IPCT_INTPEND2_ACKED6_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48248   #define IPCT_INTPEND2_ACKED6_Pending (0x1UL)       /*!< Read: Pending                                                        */
48249 
48250 /* ACKED7 @Bit 23 : Read pending status of interrupt for event ACKED[7] */
48251   #define IPCT_INTPEND2_ACKED7_Pos (23UL)            /*!< Position of ACKED7 field.                                            */
48252   #define IPCT_INTPEND2_ACKED7_Msk (0x1UL << IPCT_INTPEND2_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                          */
48253   #define IPCT_INTPEND2_ACKED7_Min (0x0UL)           /*!< Min enumerator value of ACKED7 field.                                */
48254   #define IPCT_INTPEND2_ACKED7_Max (0x1UL)           /*!< Max enumerator value of ACKED7 field.                                */
48255   #define IPCT_INTPEND2_ACKED7_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48256   #define IPCT_INTPEND2_ACKED7_Pending (0x1UL)       /*!< Read: Pending                                                        */
48257 
48258 /* ACKED8 @Bit 24 : Read pending status of interrupt for event ACKED[8] */
48259   #define IPCT_INTPEND2_ACKED8_Pos (24UL)            /*!< Position of ACKED8 field.                                            */
48260   #define IPCT_INTPEND2_ACKED8_Msk (0x1UL << IPCT_INTPEND2_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                          */
48261   #define IPCT_INTPEND2_ACKED8_Min (0x0UL)           /*!< Min enumerator value of ACKED8 field.                                */
48262   #define IPCT_INTPEND2_ACKED8_Max (0x1UL)           /*!< Max enumerator value of ACKED8 field.                                */
48263   #define IPCT_INTPEND2_ACKED8_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48264   #define IPCT_INTPEND2_ACKED8_Pending (0x1UL)       /*!< Read: Pending                                                        */
48265 
48266 /* ACKED9 @Bit 25 : Read pending status of interrupt for event ACKED[9] */
48267   #define IPCT_INTPEND2_ACKED9_Pos (25UL)            /*!< Position of ACKED9 field.                                            */
48268   #define IPCT_INTPEND2_ACKED9_Msk (0x1UL << IPCT_INTPEND2_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                          */
48269   #define IPCT_INTPEND2_ACKED9_Min (0x0UL)           /*!< Min enumerator value of ACKED9 field.                                */
48270   #define IPCT_INTPEND2_ACKED9_Max (0x1UL)           /*!< Max enumerator value of ACKED9 field.                                */
48271   #define IPCT_INTPEND2_ACKED9_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
48272   #define IPCT_INTPEND2_ACKED9_Pending (0x1UL)       /*!< Read: Pending                                                        */
48273 
48274 /* ACKED10 @Bit 26 : Read pending status of interrupt for event ACKED[10] */
48275   #define IPCT_INTPEND2_ACKED10_Pos (26UL)           /*!< Position of ACKED10 field.                                           */
48276   #define IPCT_INTPEND2_ACKED10_Msk (0x1UL << IPCT_INTPEND2_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                       */
48277   #define IPCT_INTPEND2_ACKED10_Min (0x0UL)          /*!< Min enumerator value of ACKED10 field.                               */
48278   #define IPCT_INTPEND2_ACKED10_Max (0x1UL)          /*!< Max enumerator value of ACKED10 field.                               */
48279   #define IPCT_INTPEND2_ACKED10_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
48280   #define IPCT_INTPEND2_ACKED10_Pending (0x1UL)      /*!< Read: Pending                                                        */
48281 
48282 /* ACKED11 @Bit 27 : Read pending status of interrupt for event ACKED[11] */
48283   #define IPCT_INTPEND2_ACKED11_Pos (27UL)           /*!< Position of ACKED11 field.                                           */
48284   #define IPCT_INTPEND2_ACKED11_Msk (0x1UL << IPCT_INTPEND2_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                       */
48285   #define IPCT_INTPEND2_ACKED11_Min (0x0UL)          /*!< Min enumerator value of ACKED11 field.                               */
48286   #define IPCT_INTPEND2_ACKED11_Max (0x1UL)          /*!< Max enumerator value of ACKED11 field.                               */
48287   #define IPCT_INTPEND2_ACKED11_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
48288   #define IPCT_INTPEND2_ACKED11_Pending (0x1UL)      /*!< Read: Pending                                                        */
48289 
48290 /* ACKED12 @Bit 28 : Read pending status of interrupt for event ACKED[12] */
48291   #define IPCT_INTPEND2_ACKED12_Pos (28UL)           /*!< Position of ACKED12 field.                                           */
48292   #define IPCT_INTPEND2_ACKED12_Msk (0x1UL << IPCT_INTPEND2_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                       */
48293   #define IPCT_INTPEND2_ACKED12_Min (0x0UL)          /*!< Min enumerator value of ACKED12 field.                               */
48294   #define IPCT_INTPEND2_ACKED12_Max (0x1UL)          /*!< Max enumerator value of ACKED12 field.                               */
48295   #define IPCT_INTPEND2_ACKED12_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
48296   #define IPCT_INTPEND2_ACKED12_Pending (0x1UL)      /*!< Read: Pending                                                        */
48297 
48298 /* ACKED13 @Bit 29 : Read pending status of interrupt for event ACKED[13] */
48299   #define IPCT_INTPEND2_ACKED13_Pos (29UL)           /*!< Position of ACKED13 field.                                           */
48300   #define IPCT_INTPEND2_ACKED13_Msk (0x1UL << IPCT_INTPEND2_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                       */
48301   #define IPCT_INTPEND2_ACKED13_Min (0x0UL)          /*!< Min enumerator value of ACKED13 field.                               */
48302   #define IPCT_INTPEND2_ACKED13_Max (0x1UL)          /*!< Max enumerator value of ACKED13 field.                               */
48303   #define IPCT_INTPEND2_ACKED13_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
48304   #define IPCT_INTPEND2_ACKED13_Pending (0x1UL)      /*!< Read: Pending                                                        */
48305 
48306 /* ACKED14 @Bit 30 : Read pending status of interrupt for event ACKED[14] */
48307   #define IPCT_INTPEND2_ACKED14_Pos (30UL)           /*!< Position of ACKED14 field.                                           */
48308   #define IPCT_INTPEND2_ACKED14_Msk (0x1UL << IPCT_INTPEND2_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                       */
48309   #define IPCT_INTPEND2_ACKED14_Min (0x0UL)          /*!< Min enumerator value of ACKED14 field.                               */
48310   #define IPCT_INTPEND2_ACKED14_Max (0x1UL)          /*!< Max enumerator value of ACKED14 field.                               */
48311   #define IPCT_INTPEND2_ACKED14_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
48312   #define IPCT_INTPEND2_ACKED14_Pending (0x1UL)      /*!< Read: Pending                                                        */
48313 
48314 /* ACKED15 @Bit 31 : Read pending status of interrupt for event ACKED[15] */
48315   #define IPCT_INTPEND2_ACKED15_Pos (31UL)           /*!< Position of ACKED15 field.                                           */
48316   #define IPCT_INTPEND2_ACKED15_Msk (0x1UL << IPCT_INTPEND2_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                       */
48317   #define IPCT_INTPEND2_ACKED15_Min (0x0UL)          /*!< Min enumerator value of ACKED15 field.                               */
48318   #define IPCT_INTPEND2_ACKED15_Max (0x1UL)          /*!< Max enumerator value of ACKED15 field.                               */
48319   #define IPCT_INTPEND2_ACKED15_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
48320   #define IPCT_INTPEND2_ACKED15_Pending (0x1UL)      /*!< Read: Pending                                                        */
48321 
48322 
48323 /* IPCT_INTEN3: Enable or disable interrupt */
48324   #define IPCT_INTEN3_ResetValue (0x00000000UL)      /*!< Reset value of INTEN3 register.                                      */
48325 
48326 /* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
48327   #define IPCT_INTEN3_RECEIVE0_Pos (0UL)             /*!< Position of RECEIVE0 field.                                          */
48328   #define IPCT_INTEN3_RECEIVE0_Msk (0x1UL << IPCT_INTEN3_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                        */
48329   #define IPCT_INTEN3_RECEIVE0_Min (0x0UL)           /*!< Min enumerator value of RECEIVE0 field.                              */
48330   #define IPCT_INTEN3_RECEIVE0_Max (0x1UL)           /*!< Max enumerator value of RECEIVE0 field.                              */
48331   #define IPCT_INTEN3_RECEIVE0_Disabled (0x0UL)      /*!< Disable                                                              */
48332   #define IPCT_INTEN3_RECEIVE0_Enabled (0x1UL)       /*!< Enable                                                               */
48333 
48334 /* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
48335   #define IPCT_INTEN3_RECEIVE1_Pos (1UL)             /*!< Position of RECEIVE1 field.                                          */
48336   #define IPCT_INTEN3_RECEIVE1_Msk (0x1UL << IPCT_INTEN3_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                        */
48337   #define IPCT_INTEN3_RECEIVE1_Min (0x0UL)           /*!< Min enumerator value of RECEIVE1 field.                              */
48338   #define IPCT_INTEN3_RECEIVE1_Max (0x1UL)           /*!< Max enumerator value of RECEIVE1 field.                              */
48339   #define IPCT_INTEN3_RECEIVE1_Disabled (0x0UL)      /*!< Disable                                                              */
48340   #define IPCT_INTEN3_RECEIVE1_Enabled (0x1UL)       /*!< Enable                                                               */
48341 
48342 /* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
48343   #define IPCT_INTEN3_RECEIVE2_Pos (2UL)             /*!< Position of RECEIVE2 field.                                          */
48344   #define IPCT_INTEN3_RECEIVE2_Msk (0x1UL << IPCT_INTEN3_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                        */
48345   #define IPCT_INTEN3_RECEIVE2_Min (0x0UL)           /*!< Min enumerator value of RECEIVE2 field.                              */
48346   #define IPCT_INTEN3_RECEIVE2_Max (0x1UL)           /*!< Max enumerator value of RECEIVE2 field.                              */
48347   #define IPCT_INTEN3_RECEIVE2_Disabled (0x0UL)      /*!< Disable                                                              */
48348   #define IPCT_INTEN3_RECEIVE2_Enabled (0x1UL)       /*!< Enable                                                               */
48349 
48350 /* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
48351   #define IPCT_INTEN3_RECEIVE3_Pos (3UL)             /*!< Position of RECEIVE3 field.                                          */
48352   #define IPCT_INTEN3_RECEIVE3_Msk (0x1UL << IPCT_INTEN3_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                        */
48353   #define IPCT_INTEN3_RECEIVE3_Min (0x0UL)           /*!< Min enumerator value of RECEIVE3 field.                              */
48354   #define IPCT_INTEN3_RECEIVE3_Max (0x1UL)           /*!< Max enumerator value of RECEIVE3 field.                              */
48355   #define IPCT_INTEN3_RECEIVE3_Disabled (0x0UL)      /*!< Disable                                                              */
48356   #define IPCT_INTEN3_RECEIVE3_Enabled (0x1UL)       /*!< Enable                                                               */
48357 
48358 /* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
48359   #define IPCT_INTEN3_RECEIVE4_Pos (4UL)             /*!< Position of RECEIVE4 field.                                          */
48360   #define IPCT_INTEN3_RECEIVE4_Msk (0x1UL << IPCT_INTEN3_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                        */
48361   #define IPCT_INTEN3_RECEIVE4_Min (0x0UL)           /*!< Min enumerator value of RECEIVE4 field.                              */
48362   #define IPCT_INTEN3_RECEIVE4_Max (0x1UL)           /*!< Max enumerator value of RECEIVE4 field.                              */
48363   #define IPCT_INTEN3_RECEIVE4_Disabled (0x0UL)      /*!< Disable                                                              */
48364   #define IPCT_INTEN3_RECEIVE4_Enabled (0x1UL)       /*!< Enable                                                               */
48365 
48366 /* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
48367   #define IPCT_INTEN3_RECEIVE5_Pos (5UL)             /*!< Position of RECEIVE5 field.                                          */
48368   #define IPCT_INTEN3_RECEIVE5_Msk (0x1UL << IPCT_INTEN3_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                        */
48369   #define IPCT_INTEN3_RECEIVE5_Min (0x0UL)           /*!< Min enumerator value of RECEIVE5 field.                              */
48370   #define IPCT_INTEN3_RECEIVE5_Max (0x1UL)           /*!< Max enumerator value of RECEIVE5 field.                              */
48371   #define IPCT_INTEN3_RECEIVE5_Disabled (0x0UL)      /*!< Disable                                                              */
48372   #define IPCT_INTEN3_RECEIVE5_Enabled (0x1UL)       /*!< Enable                                                               */
48373 
48374 /* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
48375   #define IPCT_INTEN3_RECEIVE6_Pos (6UL)             /*!< Position of RECEIVE6 field.                                          */
48376   #define IPCT_INTEN3_RECEIVE6_Msk (0x1UL << IPCT_INTEN3_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                        */
48377   #define IPCT_INTEN3_RECEIVE6_Min (0x0UL)           /*!< Min enumerator value of RECEIVE6 field.                              */
48378   #define IPCT_INTEN3_RECEIVE6_Max (0x1UL)           /*!< Max enumerator value of RECEIVE6 field.                              */
48379   #define IPCT_INTEN3_RECEIVE6_Disabled (0x0UL)      /*!< Disable                                                              */
48380   #define IPCT_INTEN3_RECEIVE6_Enabled (0x1UL)       /*!< Enable                                                               */
48381 
48382 /* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
48383   #define IPCT_INTEN3_RECEIVE7_Pos (7UL)             /*!< Position of RECEIVE7 field.                                          */
48384   #define IPCT_INTEN3_RECEIVE7_Msk (0x1UL << IPCT_INTEN3_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                        */
48385   #define IPCT_INTEN3_RECEIVE7_Min (0x0UL)           /*!< Min enumerator value of RECEIVE7 field.                              */
48386   #define IPCT_INTEN3_RECEIVE7_Max (0x1UL)           /*!< Max enumerator value of RECEIVE7 field.                              */
48387   #define IPCT_INTEN3_RECEIVE7_Disabled (0x0UL)      /*!< Disable                                                              */
48388   #define IPCT_INTEN3_RECEIVE7_Enabled (0x1UL)       /*!< Enable                                                               */
48389 
48390 /* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
48391   #define IPCT_INTEN3_RECEIVE8_Pos (8UL)             /*!< Position of RECEIVE8 field.                                          */
48392   #define IPCT_INTEN3_RECEIVE8_Msk (0x1UL << IPCT_INTEN3_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                        */
48393   #define IPCT_INTEN3_RECEIVE8_Min (0x0UL)           /*!< Min enumerator value of RECEIVE8 field.                              */
48394   #define IPCT_INTEN3_RECEIVE8_Max (0x1UL)           /*!< Max enumerator value of RECEIVE8 field.                              */
48395   #define IPCT_INTEN3_RECEIVE8_Disabled (0x0UL)      /*!< Disable                                                              */
48396   #define IPCT_INTEN3_RECEIVE8_Enabled (0x1UL)       /*!< Enable                                                               */
48397 
48398 /* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
48399   #define IPCT_INTEN3_RECEIVE9_Pos (9UL)             /*!< Position of RECEIVE9 field.                                          */
48400   #define IPCT_INTEN3_RECEIVE9_Msk (0x1UL << IPCT_INTEN3_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                        */
48401   #define IPCT_INTEN3_RECEIVE9_Min (0x0UL)           /*!< Min enumerator value of RECEIVE9 field.                              */
48402   #define IPCT_INTEN3_RECEIVE9_Max (0x1UL)           /*!< Max enumerator value of RECEIVE9 field.                              */
48403   #define IPCT_INTEN3_RECEIVE9_Disabled (0x0UL)      /*!< Disable                                                              */
48404   #define IPCT_INTEN3_RECEIVE9_Enabled (0x1UL)       /*!< Enable                                                               */
48405 
48406 /* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
48407   #define IPCT_INTEN3_RECEIVE10_Pos (10UL)           /*!< Position of RECEIVE10 field.                                         */
48408   #define IPCT_INTEN3_RECEIVE10_Msk (0x1UL << IPCT_INTEN3_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                     */
48409   #define IPCT_INTEN3_RECEIVE10_Min (0x0UL)          /*!< Min enumerator value of RECEIVE10 field.                             */
48410   #define IPCT_INTEN3_RECEIVE10_Max (0x1UL)          /*!< Max enumerator value of RECEIVE10 field.                             */
48411   #define IPCT_INTEN3_RECEIVE10_Disabled (0x0UL)     /*!< Disable                                                              */
48412   #define IPCT_INTEN3_RECEIVE10_Enabled (0x1UL)      /*!< Enable                                                               */
48413 
48414 /* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
48415   #define IPCT_INTEN3_RECEIVE11_Pos (11UL)           /*!< Position of RECEIVE11 field.                                         */
48416   #define IPCT_INTEN3_RECEIVE11_Msk (0x1UL << IPCT_INTEN3_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                     */
48417   #define IPCT_INTEN3_RECEIVE11_Min (0x0UL)          /*!< Min enumerator value of RECEIVE11 field.                             */
48418   #define IPCT_INTEN3_RECEIVE11_Max (0x1UL)          /*!< Max enumerator value of RECEIVE11 field.                             */
48419   #define IPCT_INTEN3_RECEIVE11_Disabled (0x0UL)     /*!< Disable                                                              */
48420   #define IPCT_INTEN3_RECEIVE11_Enabled (0x1UL)      /*!< Enable                                                               */
48421 
48422 /* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
48423   #define IPCT_INTEN3_RECEIVE12_Pos (12UL)           /*!< Position of RECEIVE12 field.                                         */
48424   #define IPCT_INTEN3_RECEIVE12_Msk (0x1UL << IPCT_INTEN3_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                     */
48425   #define IPCT_INTEN3_RECEIVE12_Min (0x0UL)          /*!< Min enumerator value of RECEIVE12 field.                             */
48426   #define IPCT_INTEN3_RECEIVE12_Max (0x1UL)          /*!< Max enumerator value of RECEIVE12 field.                             */
48427   #define IPCT_INTEN3_RECEIVE12_Disabled (0x0UL)     /*!< Disable                                                              */
48428   #define IPCT_INTEN3_RECEIVE12_Enabled (0x1UL)      /*!< Enable                                                               */
48429 
48430 /* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
48431   #define IPCT_INTEN3_RECEIVE13_Pos (13UL)           /*!< Position of RECEIVE13 field.                                         */
48432   #define IPCT_INTEN3_RECEIVE13_Msk (0x1UL << IPCT_INTEN3_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                     */
48433   #define IPCT_INTEN3_RECEIVE13_Min (0x0UL)          /*!< Min enumerator value of RECEIVE13 field.                             */
48434   #define IPCT_INTEN3_RECEIVE13_Max (0x1UL)          /*!< Max enumerator value of RECEIVE13 field.                             */
48435   #define IPCT_INTEN3_RECEIVE13_Disabled (0x0UL)     /*!< Disable                                                              */
48436   #define IPCT_INTEN3_RECEIVE13_Enabled (0x1UL)      /*!< Enable                                                               */
48437 
48438 /* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
48439   #define IPCT_INTEN3_RECEIVE14_Pos (14UL)           /*!< Position of RECEIVE14 field.                                         */
48440   #define IPCT_INTEN3_RECEIVE14_Msk (0x1UL << IPCT_INTEN3_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                     */
48441   #define IPCT_INTEN3_RECEIVE14_Min (0x0UL)          /*!< Min enumerator value of RECEIVE14 field.                             */
48442   #define IPCT_INTEN3_RECEIVE14_Max (0x1UL)          /*!< Max enumerator value of RECEIVE14 field.                             */
48443   #define IPCT_INTEN3_RECEIVE14_Disabled (0x0UL)     /*!< Disable                                                              */
48444   #define IPCT_INTEN3_RECEIVE14_Enabled (0x1UL)      /*!< Enable                                                               */
48445 
48446 /* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
48447   #define IPCT_INTEN3_RECEIVE15_Pos (15UL)           /*!< Position of RECEIVE15 field.                                         */
48448   #define IPCT_INTEN3_RECEIVE15_Msk (0x1UL << IPCT_INTEN3_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                     */
48449   #define IPCT_INTEN3_RECEIVE15_Min (0x0UL)          /*!< Min enumerator value of RECEIVE15 field.                             */
48450   #define IPCT_INTEN3_RECEIVE15_Max (0x1UL)          /*!< Max enumerator value of RECEIVE15 field.                             */
48451   #define IPCT_INTEN3_RECEIVE15_Disabled (0x0UL)     /*!< Disable                                                              */
48452   #define IPCT_INTEN3_RECEIVE15_Enabled (0x1UL)      /*!< Enable                                                               */
48453 
48454 /* ACKED0 @Bit 16 : Enable or disable interrupt for event ACKED[0] */
48455   #define IPCT_INTEN3_ACKED0_Pos (16UL)              /*!< Position of ACKED0 field.                                            */
48456   #define IPCT_INTEN3_ACKED0_Msk (0x1UL << IPCT_INTEN3_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                              */
48457   #define IPCT_INTEN3_ACKED0_Min (0x0UL)             /*!< Min enumerator value of ACKED0 field.                                */
48458   #define IPCT_INTEN3_ACKED0_Max (0x1UL)             /*!< Max enumerator value of ACKED0 field.                                */
48459   #define IPCT_INTEN3_ACKED0_Disabled (0x0UL)        /*!< Disable                                                              */
48460   #define IPCT_INTEN3_ACKED0_Enabled (0x1UL)         /*!< Enable                                                               */
48461 
48462 /* ACKED1 @Bit 17 : Enable or disable interrupt for event ACKED[1] */
48463   #define IPCT_INTEN3_ACKED1_Pos (17UL)              /*!< Position of ACKED1 field.                                            */
48464   #define IPCT_INTEN3_ACKED1_Msk (0x1UL << IPCT_INTEN3_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                              */
48465   #define IPCT_INTEN3_ACKED1_Min (0x0UL)             /*!< Min enumerator value of ACKED1 field.                                */
48466   #define IPCT_INTEN3_ACKED1_Max (0x1UL)             /*!< Max enumerator value of ACKED1 field.                                */
48467   #define IPCT_INTEN3_ACKED1_Disabled (0x0UL)        /*!< Disable                                                              */
48468   #define IPCT_INTEN3_ACKED1_Enabled (0x1UL)         /*!< Enable                                                               */
48469 
48470 /* ACKED2 @Bit 18 : Enable or disable interrupt for event ACKED[2] */
48471   #define IPCT_INTEN3_ACKED2_Pos (18UL)              /*!< Position of ACKED2 field.                                            */
48472   #define IPCT_INTEN3_ACKED2_Msk (0x1UL << IPCT_INTEN3_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                              */
48473   #define IPCT_INTEN3_ACKED2_Min (0x0UL)             /*!< Min enumerator value of ACKED2 field.                                */
48474   #define IPCT_INTEN3_ACKED2_Max (0x1UL)             /*!< Max enumerator value of ACKED2 field.                                */
48475   #define IPCT_INTEN3_ACKED2_Disabled (0x0UL)        /*!< Disable                                                              */
48476   #define IPCT_INTEN3_ACKED2_Enabled (0x1UL)         /*!< Enable                                                               */
48477 
48478 /* ACKED3 @Bit 19 : Enable or disable interrupt for event ACKED[3] */
48479   #define IPCT_INTEN3_ACKED3_Pos (19UL)              /*!< Position of ACKED3 field.                                            */
48480   #define IPCT_INTEN3_ACKED3_Msk (0x1UL << IPCT_INTEN3_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                              */
48481   #define IPCT_INTEN3_ACKED3_Min (0x0UL)             /*!< Min enumerator value of ACKED3 field.                                */
48482   #define IPCT_INTEN3_ACKED3_Max (0x1UL)             /*!< Max enumerator value of ACKED3 field.                                */
48483   #define IPCT_INTEN3_ACKED3_Disabled (0x0UL)        /*!< Disable                                                              */
48484   #define IPCT_INTEN3_ACKED3_Enabled (0x1UL)         /*!< Enable                                                               */
48485 
48486 /* ACKED4 @Bit 20 : Enable or disable interrupt for event ACKED[4] */
48487   #define IPCT_INTEN3_ACKED4_Pos (20UL)              /*!< Position of ACKED4 field.                                            */
48488   #define IPCT_INTEN3_ACKED4_Msk (0x1UL << IPCT_INTEN3_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                              */
48489   #define IPCT_INTEN3_ACKED4_Min (0x0UL)             /*!< Min enumerator value of ACKED4 field.                                */
48490   #define IPCT_INTEN3_ACKED4_Max (0x1UL)             /*!< Max enumerator value of ACKED4 field.                                */
48491   #define IPCT_INTEN3_ACKED4_Disabled (0x0UL)        /*!< Disable                                                              */
48492   #define IPCT_INTEN3_ACKED4_Enabled (0x1UL)         /*!< Enable                                                               */
48493 
48494 /* ACKED5 @Bit 21 : Enable or disable interrupt for event ACKED[5] */
48495   #define IPCT_INTEN3_ACKED5_Pos (21UL)              /*!< Position of ACKED5 field.                                            */
48496   #define IPCT_INTEN3_ACKED5_Msk (0x1UL << IPCT_INTEN3_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                              */
48497   #define IPCT_INTEN3_ACKED5_Min (0x0UL)             /*!< Min enumerator value of ACKED5 field.                                */
48498   #define IPCT_INTEN3_ACKED5_Max (0x1UL)             /*!< Max enumerator value of ACKED5 field.                                */
48499   #define IPCT_INTEN3_ACKED5_Disabled (0x0UL)        /*!< Disable                                                              */
48500   #define IPCT_INTEN3_ACKED5_Enabled (0x1UL)         /*!< Enable                                                               */
48501 
48502 /* ACKED6 @Bit 22 : Enable or disable interrupt for event ACKED[6] */
48503   #define IPCT_INTEN3_ACKED6_Pos (22UL)              /*!< Position of ACKED6 field.                                            */
48504   #define IPCT_INTEN3_ACKED6_Msk (0x1UL << IPCT_INTEN3_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                              */
48505   #define IPCT_INTEN3_ACKED6_Min (0x0UL)             /*!< Min enumerator value of ACKED6 field.                                */
48506   #define IPCT_INTEN3_ACKED6_Max (0x1UL)             /*!< Max enumerator value of ACKED6 field.                                */
48507   #define IPCT_INTEN3_ACKED6_Disabled (0x0UL)        /*!< Disable                                                              */
48508   #define IPCT_INTEN3_ACKED6_Enabled (0x1UL)         /*!< Enable                                                               */
48509 
48510 /* ACKED7 @Bit 23 : Enable or disable interrupt for event ACKED[7] */
48511   #define IPCT_INTEN3_ACKED7_Pos (23UL)              /*!< Position of ACKED7 field.                                            */
48512   #define IPCT_INTEN3_ACKED7_Msk (0x1UL << IPCT_INTEN3_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                              */
48513   #define IPCT_INTEN3_ACKED7_Min (0x0UL)             /*!< Min enumerator value of ACKED7 field.                                */
48514   #define IPCT_INTEN3_ACKED7_Max (0x1UL)             /*!< Max enumerator value of ACKED7 field.                                */
48515   #define IPCT_INTEN3_ACKED7_Disabled (0x0UL)        /*!< Disable                                                              */
48516   #define IPCT_INTEN3_ACKED7_Enabled (0x1UL)         /*!< Enable                                                               */
48517 
48518 /* ACKED8 @Bit 24 : Enable or disable interrupt for event ACKED[8] */
48519   #define IPCT_INTEN3_ACKED8_Pos (24UL)              /*!< Position of ACKED8 field.                                            */
48520   #define IPCT_INTEN3_ACKED8_Msk (0x1UL << IPCT_INTEN3_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                              */
48521   #define IPCT_INTEN3_ACKED8_Min (0x0UL)             /*!< Min enumerator value of ACKED8 field.                                */
48522   #define IPCT_INTEN3_ACKED8_Max (0x1UL)             /*!< Max enumerator value of ACKED8 field.                                */
48523   #define IPCT_INTEN3_ACKED8_Disabled (0x0UL)        /*!< Disable                                                              */
48524   #define IPCT_INTEN3_ACKED8_Enabled (0x1UL)         /*!< Enable                                                               */
48525 
48526 /* ACKED9 @Bit 25 : Enable or disable interrupt for event ACKED[9] */
48527   #define IPCT_INTEN3_ACKED9_Pos (25UL)              /*!< Position of ACKED9 field.                                            */
48528   #define IPCT_INTEN3_ACKED9_Msk (0x1UL << IPCT_INTEN3_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                              */
48529   #define IPCT_INTEN3_ACKED9_Min (0x0UL)             /*!< Min enumerator value of ACKED9 field.                                */
48530   #define IPCT_INTEN3_ACKED9_Max (0x1UL)             /*!< Max enumerator value of ACKED9 field.                                */
48531   #define IPCT_INTEN3_ACKED9_Disabled (0x0UL)        /*!< Disable                                                              */
48532   #define IPCT_INTEN3_ACKED9_Enabled (0x1UL)         /*!< Enable                                                               */
48533 
48534 /* ACKED10 @Bit 26 : Enable or disable interrupt for event ACKED[10] */
48535   #define IPCT_INTEN3_ACKED10_Pos (26UL)             /*!< Position of ACKED10 field.                                           */
48536   #define IPCT_INTEN3_ACKED10_Msk (0x1UL << IPCT_INTEN3_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                           */
48537   #define IPCT_INTEN3_ACKED10_Min (0x0UL)            /*!< Min enumerator value of ACKED10 field.                               */
48538   #define IPCT_INTEN3_ACKED10_Max (0x1UL)            /*!< Max enumerator value of ACKED10 field.                               */
48539   #define IPCT_INTEN3_ACKED10_Disabled (0x0UL)       /*!< Disable                                                              */
48540   #define IPCT_INTEN3_ACKED10_Enabled (0x1UL)        /*!< Enable                                                               */
48541 
48542 /* ACKED11 @Bit 27 : Enable or disable interrupt for event ACKED[11] */
48543   #define IPCT_INTEN3_ACKED11_Pos (27UL)             /*!< Position of ACKED11 field.                                           */
48544   #define IPCT_INTEN3_ACKED11_Msk (0x1UL << IPCT_INTEN3_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                           */
48545   #define IPCT_INTEN3_ACKED11_Min (0x0UL)            /*!< Min enumerator value of ACKED11 field.                               */
48546   #define IPCT_INTEN3_ACKED11_Max (0x1UL)            /*!< Max enumerator value of ACKED11 field.                               */
48547   #define IPCT_INTEN3_ACKED11_Disabled (0x0UL)       /*!< Disable                                                              */
48548   #define IPCT_INTEN3_ACKED11_Enabled (0x1UL)        /*!< Enable                                                               */
48549 
48550 /* ACKED12 @Bit 28 : Enable or disable interrupt for event ACKED[12] */
48551   #define IPCT_INTEN3_ACKED12_Pos (28UL)             /*!< Position of ACKED12 field.                                           */
48552   #define IPCT_INTEN3_ACKED12_Msk (0x1UL << IPCT_INTEN3_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                           */
48553   #define IPCT_INTEN3_ACKED12_Min (0x0UL)            /*!< Min enumerator value of ACKED12 field.                               */
48554   #define IPCT_INTEN3_ACKED12_Max (0x1UL)            /*!< Max enumerator value of ACKED12 field.                               */
48555   #define IPCT_INTEN3_ACKED12_Disabled (0x0UL)       /*!< Disable                                                              */
48556   #define IPCT_INTEN3_ACKED12_Enabled (0x1UL)        /*!< Enable                                                               */
48557 
48558 /* ACKED13 @Bit 29 : Enable or disable interrupt for event ACKED[13] */
48559   #define IPCT_INTEN3_ACKED13_Pos (29UL)             /*!< Position of ACKED13 field.                                           */
48560   #define IPCT_INTEN3_ACKED13_Msk (0x1UL << IPCT_INTEN3_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                           */
48561   #define IPCT_INTEN3_ACKED13_Min (0x0UL)            /*!< Min enumerator value of ACKED13 field.                               */
48562   #define IPCT_INTEN3_ACKED13_Max (0x1UL)            /*!< Max enumerator value of ACKED13 field.                               */
48563   #define IPCT_INTEN3_ACKED13_Disabled (0x0UL)       /*!< Disable                                                              */
48564   #define IPCT_INTEN3_ACKED13_Enabled (0x1UL)        /*!< Enable                                                               */
48565 
48566 /* ACKED14 @Bit 30 : Enable or disable interrupt for event ACKED[14] */
48567   #define IPCT_INTEN3_ACKED14_Pos (30UL)             /*!< Position of ACKED14 field.                                           */
48568   #define IPCT_INTEN3_ACKED14_Msk (0x1UL << IPCT_INTEN3_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                           */
48569   #define IPCT_INTEN3_ACKED14_Min (0x0UL)            /*!< Min enumerator value of ACKED14 field.                               */
48570   #define IPCT_INTEN3_ACKED14_Max (0x1UL)            /*!< Max enumerator value of ACKED14 field.                               */
48571   #define IPCT_INTEN3_ACKED14_Disabled (0x0UL)       /*!< Disable                                                              */
48572   #define IPCT_INTEN3_ACKED14_Enabled (0x1UL)        /*!< Enable                                                               */
48573 
48574 /* ACKED15 @Bit 31 : Enable or disable interrupt for event ACKED[15] */
48575   #define IPCT_INTEN3_ACKED15_Pos (31UL)             /*!< Position of ACKED15 field.                                           */
48576   #define IPCT_INTEN3_ACKED15_Msk (0x1UL << IPCT_INTEN3_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                           */
48577   #define IPCT_INTEN3_ACKED15_Min (0x0UL)            /*!< Min enumerator value of ACKED15 field.                               */
48578   #define IPCT_INTEN3_ACKED15_Max (0x1UL)            /*!< Max enumerator value of ACKED15 field.                               */
48579   #define IPCT_INTEN3_ACKED15_Disabled (0x0UL)       /*!< Disable                                                              */
48580   #define IPCT_INTEN3_ACKED15_Enabled (0x1UL)        /*!< Enable                                                               */
48581 
48582 
48583 /* IPCT_INTENSET3: Enable interrupt */
48584   #define IPCT_INTENSET3_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET3 register.                                   */
48585 
48586 /* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
48587   #define IPCT_INTENSET3_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
48588   #define IPCT_INTENSET3_RECEIVE0_Msk (0x1UL << IPCT_INTENSET3_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
48589   #define IPCT_INTENSET3_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
48590   #define IPCT_INTENSET3_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
48591   #define IPCT_INTENSET3_RECEIVE0_Set (0x1UL)        /*!< Enable                                                               */
48592   #define IPCT_INTENSET3_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48593   #define IPCT_INTENSET3_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48594 
48595 /* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
48596   #define IPCT_INTENSET3_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
48597   #define IPCT_INTENSET3_RECEIVE1_Msk (0x1UL << IPCT_INTENSET3_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
48598   #define IPCT_INTENSET3_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
48599   #define IPCT_INTENSET3_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
48600   #define IPCT_INTENSET3_RECEIVE1_Set (0x1UL)        /*!< Enable                                                               */
48601   #define IPCT_INTENSET3_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48602   #define IPCT_INTENSET3_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48603 
48604 /* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
48605   #define IPCT_INTENSET3_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
48606   #define IPCT_INTENSET3_RECEIVE2_Msk (0x1UL << IPCT_INTENSET3_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
48607   #define IPCT_INTENSET3_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
48608   #define IPCT_INTENSET3_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
48609   #define IPCT_INTENSET3_RECEIVE2_Set (0x1UL)        /*!< Enable                                                               */
48610   #define IPCT_INTENSET3_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48611   #define IPCT_INTENSET3_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48612 
48613 /* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
48614   #define IPCT_INTENSET3_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
48615   #define IPCT_INTENSET3_RECEIVE3_Msk (0x1UL << IPCT_INTENSET3_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
48616   #define IPCT_INTENSET3_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
48617   #define IPCT_INTENSET3_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
48618   #define IPCT_INTENSET3_RECEIVE3_Set (0x1UL)        /*!< Enable                                                               */
48619   #define IPCT_INTENSET3_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48620   #define IPCT_INTENSET3_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48621 
48622 /* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
48623   #define IPCT_INTENSET3_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
48624   #define IPCT_INTENSET3_RECEIVE4_Msk (0x1UL << IPCT_INTENSET3_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
48625   #define IPCT_INTENSET3_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
48626   #define IPCT_INTENSET3_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
48627   #define IPCT_INTENSET3_RECEIVE4_Set (0x1UL)        /*!< Enable                                                               */
48628   #define IPCT_INTENSET3_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48629   #define IPCT_INTENSET3_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48630 
48631 /* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
48632   #define IPCT_INTENSET3_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
48633   #define IPCT_INTENSET3_RECEIVE5_Msk (0x1UL << IPCT_INTENSET3_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
48634   #define IPCT_INTENSET3_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
48635   #define IPCT_INTENSET3_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
48636   #define IPCT_INTENSET3_RECEIVE5_Set (0x1UL)        /*!< Enable                                                               */
48637   #define IPCT_INTENSET3_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48638   #define IPCT_INTENSET3_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48639 
48640 /* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
48641   #define IPCT_INTENSET3_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
48642   #define IPCT_INTENSET3_RECEIVE6_Msk (0x1UL << IPCT_INTENSET3_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
48643   #define IPCT_INTENSET3_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
48644   #define IPCT_INTENSET3_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
48645   #define IPCT_INTENSET3_RECEIVE6_Set (0x1UL)        /*!< Enable                                                               */
48646   #define IPCT_INTENSET3_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48647   #define IPCT_INTENSET3_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48648 
48649 /* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
48650   #define IPCT_INTENSET3_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
48651   #define IPCT_INTENSET3_RECEIVE7_Msk (0x1UL << IPCT_INTENSET3_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
48652   #define IPCT_INTENSET3_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
48653   #define IPCT_INTENSET3_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
48654   #define IPCT_INTENSET3_RECEIVE7_Set (0x1UL)        /*!< Enable                                                               */
48655   #define IPCT_INTENSET3_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48656   #define IPCT_INTENSET3_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48657 
48658 /* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
48659   #define IPCT_INTENSET3_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
48660   #define IPCT_INTENSET3_RECEIVE8_Msk (0x1UL << IPCT_INTENSET3_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
48661   #define IPCT_INTENSET3_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
48662   #define IPCT_INTENSET3_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
48663   #define IPCT_INTENSET3_RECEIVE8_Set (0x1UL)        /*!< Enable                                                               */
48664   #define IPCT_INTENSET3_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48665   #define IPCT_INTENSET3_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48666 
48667 /* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
48668   #define IPCT_INTENSET3_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
48669   #define IPCT_INTENSET3_RECEIVE9_Msk (0x1UL << IPCT_INTENSET3_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
48670   #define IPCT_INTENSET3_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
48671   #define IPCT_INTENSET3_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
48672   #define IPCT_INTENSET3_RECEIVE9_Set (0x1UL)        /*!< Enable                                                               */
48673   #define IPCT_INTENSET3_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48674   #define IPCT_INTENSET3_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48675 
48676 /* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
48677   #define IPCT_INTENSET3_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
48678   #define IPCT_INTENSET3_RECEIVE10_Msk (0x1UL << IPCT_INTENSET3_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
48679   #define IPCT_INTENSET3_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
48680   #define IPCT_INTENSET3_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
48681   #define IPCT_INTENSET3_RECEIVE10_Set (0x1UL)       /*!< Enable                                                               */
48682   #define IPCT_INTENSET3_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48683   #define IPCT_INTENSET3_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48684 
48685 /* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
48686   #define IPCT_INTENSET3_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
48687   #define IPCT_INTENSET3_RECEIVE11_Msk (0x1UL << IPCT_INTENSET3_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
48688   #define IPCT_INTENSET3_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
48689   #define IPCT_INTENSET3_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
48690   #define IPCT_INTENSET3_RECEIVE11_Set (0x1UL)       /*!< Enable                                                               */
48691   #define IPCT_INTENSET3_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48692   #define IPCT_INTENSET3_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48693 
48694 /* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
48695   #define IPCT_INTENSET3_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
48696   #define IPCT_INTENSET3_RECEIVE12_Msk (0x1UL << IPCT_INTENSET3_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
48697   #define IPCT_INTENSET3_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
48698   #define IPCT_INTENSET3_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
48699   #define IPCT_INTENSET3_RECEIVE12_Set (0x1UL)       /*!< Enable                                                               */
48700   #define IPCT_INTENSET3_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48701   #define IPCT_INTENSET3_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48702 
48703 /* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
48704   #define IPCT_INTENSET3_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
48705   #define IPCT_INTENSET3_RECEIVE13_Msk (0x1UL << IPCT_INTENSET3_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
48706   #define IPCT_INTENSET3_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
48707   #define IPCT_INTENSET3_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
48708   #define IPCT_INTENSET3_RECEIVE13_Set (0x1UL)       /*!< Enable                                                               */
48709   #define IPCT_INTENSET3_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48710   #define IPCT_INTENSET3_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48711 
48712 /* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
48713   #define IPCT_INTENSET3_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
48714   #define IPCT_INTENSET3_RECEIVE14_Msk (0x1UL << IPCT_INTENSET3_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
48715   #define IPCT_INTENSET3_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
48716   #define IPCT_INTENSET3_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
48717   #define IPCT_INTENSET3_RECEIVE14_Set (0x1UL)       /*!< Enable                                                               */
48718   #define IPCT_INTENSET3_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48719   #define IPCT_INTENSET3_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48720 
48721 /* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
48722   #define IPCT_INTENSET3_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
48723   #define IPCT_INTENSET3_RECEIVE15_Msk (0x1UL << IPCT_INTENSET3_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
48724   #define IPCT_INTENSET3_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
48725   #define IPCT_INTENSET3_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
48726   #define IPCT_INTENSET3_RECEIVE15_Set (0x1UL)       /*!< Enable                                                               */
48727   #define IPCT_INTENSET3_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48728   #define IPCT_INTENSET3_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48729 
48730 /* ACKED0 @Bit 16 : Write '1' to enable interrupt for event ACKED[0] */
48731   #define IPCT_INTENSET3_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
48732   #define IPCT_INTENSET3_ACKED0_Msk (0x1UL << IPCT_INTENSET3_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
48733   #define IPCT_INTENSET3_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
48734   #define IPCT_INTENSET3_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
48735   #define IPCT_INTENSET3_ACKED0_Set (0x1UL)          /*!< Enable                                                               */
48736   #define IPCT_INTENSET3_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48737   #define IPCT_INTENSET3_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48738 
48739 /* ACKED1 @Bit 17 : Write '1' to enable interrupt for event ACKED[1] */
48740   #define IPCT_INTENSET3_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
48741   #define IPCT_INTENSET3_ACKED1_Msk (0x1UL << IPCT_INTENSET3_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
48742   #define IPCT_INTENSET3_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
48743   #define IPCT_INTENSET3_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
48744   #define IPCT_INTENSET3_ACKED1_Set (0x1UL)          /*!< Enable                                                               */
48745   #define IPCT_INTENSET3_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48746   #define IPCT_INTENSET3_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48747 
48748 /* ACKED2 @Bit 18 : Write '1' to enable interrupt for event ACKED[2] */
48749   #define IPCT_INTENSET3_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
48750   #define IPCT_INTENSET3_ACKED2_Msk (0x1UL << IPCT_INTENSET3_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
48751   #define IPCT_INTENSET3_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
48752   #define IPCT_INTENSET3_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
48753   #define IPCT_INTENSET3_ACKED2_Set (0x1UL)          /*!< Enable                                                               */
48754   #define IPCT_INTENSET3_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48755   #define IPCT_INTENSET3_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48756 
48757 /* ACKED3 @Bit 19 : Write '1' to enable interrupt for event ACKED[3] */
48758   #define IPCT_INTENSET3_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
48759   #define IPCT_INTENSET3_ACKED3_Msk (0x1UL << IPCT_INTENSET3_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
48760   #define IPCT_INTENSET3_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
48761   #define IPCT_INTENSET3_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
48762   #define IPCT_INTENSET3_ACKED3_Set (0x1UL)          /*!< Enable                                                               */
48763   #define IPCT_INTENSET3_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48764   #define IPCT_INTENSET3_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48765 
48766 /* ACKED4 @Bit 20 : Write '1' to enable interrupt for event ACKED[4] */
48767   #define IPCT_INTENSET3_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
48768   #define IPCT_INTENSET3_ACKED4_Msk (0x1UL << IPCT_INTENSET3_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
48769   #define IPCT_INTENSET3_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
48770   #define IPCT_INTENSET3_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
48771   #define IPCT_INTENSET3_ACKED4_Set (0x1UL)          /*!< Enable                                                               */
48772   #define IPCT_INTENSET3_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48773   #define IPCT_INTENSET3_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48774 
48775 /* ACKED5 @Bit 21 : Write '1' to enable interrupt for event ACKED[5] */
48776   #define IPCT_INTENSET3_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
48777   #define IPCT_INTENSET3_ACKED5_Msk (0x1UL << IPCT_INTENSET3_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
48778   #define IPCT_INTENSET3_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
48779   #define IPCT_INTENSET3_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
48780   #define IPCT_INTENSET3_ACKED5_Set (0x1UL)          /*!< Enable                                                               */
48781   #define IPCT_INTENSET3_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48782   #define IPCT_INTENSET3_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48783 
48784 /* ACKED6 @Bit 22 : Write '1' to enable interrupt for event ACKED[6] */
48785   #define IPCT_INTENSET3_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
48786   #define IPCT_INTENSET3_ACKED6_Msk (0x1UL << IPCT_INTENSET3_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
48787   #define IPCT_INTENSET3_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
48788   #define IPCT_INTENSET3_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
48789   #define IPCT_INTENSET3_ACKED6_Set (0x1UL)          /*!< Enable                                                               */
48790   #define IPCT_INTENSET3_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48791   #define IPCT_INTENSET3_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48792 
48793 /* ACKED7 @Bit 23 : Write '1' to enable interrupt for event ACKED[7] */
48794   #define IPCT_INTENSET3_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
48795   #define IPCT_INTENSET3_ACKED7_Msk (0x1UL << IPCT_INTENSET3_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
48796   #define IPCT_INTENSET3_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
48797   #define IPCT_INTENSET3_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
48798   #define IPCT_INTENSET3_ACKED7_Set (0x1UL)          /*!< Enable                                                               */
48799   #define IPCT_INTENSET3_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48800   #define IPCT_INTENSET3_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48801 
48802 /* ACKED8 @Bit 24 : Write '1' to enable interrupt for event ACKED[8] */
48803   #define IPCT_INTENSET3_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
48804   #define IPCT_INTENSET3_ACKED8_Msk (0x1UL << IPCT_INTENSET3_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
48805   #define IPCT_INTENSET3_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
48806   #define IPCT_INTENSET3_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
48807   #define IPCT_INTENSET3_ACKED8_Set (0x1UL)          /*!< Enable                                                               */
48808   #define IPCT_INTENSET3_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48809   #define IPCT_INTENSET3_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48810 
48811 /* ACKED9 @Bit 25 : Write '1' to enable interrupt for event ACKED[9] */
48812   #define IPCT_INTENSET3_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
48813   #define IPCT_INTENSET3_ACKED9_Msk (0x1UL << IPCT_INTENSET3_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
48814   #define IPCT_INTENSET3_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
48815   #define IPCT_INTENSET3_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
48816   #define IPCT_INTENSET3_ACKED9_Set (0x1UL)          /*!< Enable                                                               */
48817   #define IPCT_INTENSET3_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
48818   #define IPCT_INTENSET3_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
48819 
48820 /* ACKED10 @Bit 26 : Write '1' to enable interrupt for event ACKED[10] */
48821   #define IPCT_INTENSET3_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
48822   #define IPCT_INTENSET3_ACKED10_Msk (0x1UL << IPCT_INTENSET3_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
48823   #define IPCT_INTENSET3_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
48824   #define IPCT_INTENSET3_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
48825   #define IPCT_INTENSET3_ACKED10_Set (0x1UL)         /*!< Enable                                                               */
48826   #define IPCT_INTENSET3_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48827   #define IPCT_INTENSET3_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48828 
48829 /* ACKED11 @Bit 27 : Write '1' to enable interrupt for event ACKED[11] */
48830   #define IPCT_INTENSET3_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
48831   #define IPCT_INTENSET3_ACKED11_Msk (0x1UL << IPCT_INTENSET3_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
48832   #define IPCT_INTENSET3_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
48833   #define IPCT_INTENSET3_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
48834   #define IPCT_INTENSET3_ACKED11_Set (0x1UL)         /*!< Enable                                                               */
48835   #define IPCT_INTENSET3_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48836   #define IPCT_INTENSET3_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48837 
48838 /* ACKED12 @Bit 28 : Write '1' to enable interrupt for event ACKED[12] */
48839   #define IPCT_INTENSET3_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
48840   #define IPCT_INTENSET3_ACKED12_Msk (0x1UL << IPCT_INTENSET3_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
48841   #define IPCT_INTENSET3_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
48842   #define IPCT_INTENSET3_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
48843   #define IPCT_INTENSET3_ACKED12_Set (0x1UL)         /*!< Enable                                                               */
48844   #define IPCT_INTENSET3_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48845   #define IPCT_INTENSET3_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48846 
48847 /* ACKED13 @Bit 29 : Write '1' to enable interrupt for event ACKED[13] */
48848   #define IPCT_INTENSET3_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
48849   #define IPCT_INTENSET3_ACKED13_Msk (0x1UL << IPCT_INTENSET3_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
48850   #define IPCT_INTENSET3_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
48851   #define IPCT_INTENSET3_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
48852   #define IPCT_INTENSET3_ACKED13_Set (0x1UL)         /*!< Enable                                                               */
48853   #define IPCT_INTENSET3_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48854   #define IPCT_INTENSET3_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48855 
48856 /* ACKED14 @Bit 30 : Write '1' to enable interrupt for event ACKED[14] */
48857   #define IPCT_INTENSET3_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
48858   #define IPCT_INTENSET3_ACKED14_Msk (0x1UL << IPCT_INTENSET3_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
48859   #define IPCT_INTENSET3_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
48860   #define IPCT_INTENSET3_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
48861   #define IPCT_INTENSET3_ACKED14_Set (0x1UL)         /*!< Enable                                                               */
48862   #define IPCT_INTENSET3_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48863   #define IPCT_INTENSET3_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48864 
48865 /* ACKED15 @Bit 31 : Write '1' to enable interrupt for event ACKED[15] */
48866   #define IPCT_INTENSET3_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
48867   #define IPCT_INTENSET3_ACKED15_Msk (0x1UL << IPCT_INTENSET3_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
48868   #define IPCT_INTENSET3_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
48869   #define IPCT_INTENSET3_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
48870   #define IPCT_INTENSET3_ACKED15_Set (0x1UL)         /*!< Enable                                                               */
48871   #define IPCT_INTENSET3_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
48872   #define IPCT_INTENSET3_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
48873 
48874 
48875 /* IPCT_INTENCLR3: Disable interrupt */
48876   #define IPCT_INTENCLR3_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR3 register.                                   */
48877 
48878 /* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
48879   #define IPCT_INTENCLR3_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
48880   #define IPCT_INTENCLR3_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
48881   #define IPCT_INTENCLR3_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
48882   #define IPCT_INTENCLR3_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
48883   #define IPCT_INTENCLR3_RECEIVE0_Clear (0x1UL)      /*!< Disable                                                              */
48884   #define IPCT_INTENCLR3_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48885   #define IPCT_INTENCLR3_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48886 
48887 /* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
48888   #define IPCT_INTENCLR3_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
48889   #define IPCT_INTENCLR3_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
48890   #define IPCT_INTENCLR3_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
48891   #define IPCT_INTENCLR3_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
48892   #define IPCT_INTENCLR3_RECEIVE1_Clear (0x1UL)      /*!< Disable                                                              */
48893   #define IPCT_INTENCLR3_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48894   #define IPCT_INTENCLR3_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48895 
48896 /* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
48897   #define IPCT_INTENCLR3_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
48898   #define IPCT_INTENCLR3_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
48899   #define IPCT_INTENCLR3_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
48900   #define IPCT_INTENCLR3_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
48901   #define IPCT_INTENCLR3_RECEIVE2_Clear (0x1UL)      /*!< Disable                                                              */
48902   #define IPCT_INTENCLR3_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48903   #define IPCT_INTENCLR3_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48904 
48905 /* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
48906   #define IPCT_INTENCLR3_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
48907   #define IPCT_INTENCLR3_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
48908   #define IPCT_INTENCLR3_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
48909   #define IPCT_INTENCLR3_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
48910   #define IPCT_INTENCLR3_RECEIVE3_Clear (0x1UL)      /*!< Disable                                                              */
48911   #define IPCT_INTENCLR3_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48912   #define IPCT_INTENCLR3_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48913 
48914 /* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
48915   #define IPCT_INTENCLR3_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
48916   #define IPCT_INTENCLR3_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
48917   #define IPCT_INTENCLR3_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
48918   #define IPCT_INTENCLR3_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
48919   #define IPCT_INTENCLR3_RECEIVE4_Clear (0x1UL)      /*!< Disable                                                              */
48920   #define IPCT_INTENCLR3_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48921   #define IPCT_INTENCLR3_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48922 
48923 /* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
48924   #define IPCT_INTENCLR3_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
48925   #define IPCT_INTENCLR3_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
48926   #define IPCT_INTENCLR3_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
48927   #define IPCT_INTENCLR3_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
48928   #define IPCT_INTENCLR3_RECEIVE5_Clear (0x1UL)      /*!< Disable                                                              */
48929   #define IPCT_INTENCLR3_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48930   #define IPCT_INTENCLR3_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48931 
48932 /* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
48933   #define IPCT_INTENCLR3_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
48934   #define IPCT_INTENCLR3_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
48935   #define IPCT_INTENCLR3_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
48936   #define IPCT_INTENCLR3_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
48937   #define IPCT_INTENCLR3_RECEIVE6_Clear (0x1UL)      /*!< Disable                                                              */
48938   #define IPCT_INTENCLR3_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48939   #define IPCT_INTENCLR3_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48940 
48941 /* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
48942   #define IPCT_INTENCLR3_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
48943   #define IPCT_INTENCLR3_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
48944   #define IPCT_INTENCLR3_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
48945   #define IPCT_INTENCLR3_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
48946   #define IPCT_INTENCLR3_RECEIVE7_Clear (0x1UL)      /*!< Disable                                                              */
48947   #define IPCT_INTENCLR3_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48948   #define IPCT_INTENCLR3_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48949 
48950 /* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
48951   #define IPCT_INTENCLR3_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
48952   #define IPCT_INTENCLR3_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
48953   #define IPCT_INTENCLR3_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
48954   #define IPCT_INTENCLR3_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
48955   #define IPCT_INTENCLR3_RECEIVE8_Clear (0x1UL)      /*!< Disable                                                              */
48956   #define IPCT_INTENCLR3_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48957   #define IPCT_INTENCLR3_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48958 
48959 /* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
48960   #define IPCT_INTENCLR3_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
48961   #define IPCT_INTENCLR3_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
48962   #define IPCT_INTENCLR3_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
48963   #define IPCT_INTENCLR3_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
48964   #define IPCT_INTENCLR3_RECEIVE9_Clear (0x1UL)      /*!< Disable                                                              */
48965   #define IPCT_INTENCLR3_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
48966   #define IPCT_INTENCLR3_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
48967 
48968 /* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
48969   #define IPCT_INTENCLR3_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
48970   #define IPCT_INTENCLR3_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
48971   #define IPCT_INTENCLR3_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
48972   #define IPCT_INTENCLR3_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
48973   #define IPCT_INTENCLR3_RECEIVE10_Clear (0x1UL)     /*!< Disable                                                              */
48974   #define IPCT_INTENCLR3_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48975   #define IPCT_INTENCLR3_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48976 
48977 /* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
48978   #define IPCT_INTENCLR3_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
48979   #define IPCT_INTENCLR3_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
48980   #define IPCT_INTENCLR3_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
48981   #define IPCT_INTENCLR3_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
48982   #define IPCT_INTENCLR3_RECEIVE11_Clear (0x1UL)     /*!< Disable                                                              */
48983   #define IPCT_INTENCLR3_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48984   #define IPCT_INTENCLR3_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48985 
48986 /* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
48987   #define IPCT_INTENCLR3_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
48988   #define IPCT_INTENCLR3_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
48989   #define IPCT_INTENCLR3_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
48990   #define IPCT_INTENCLR3_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
48991   #define IPCT_INTENCLR3_RECEIVE12_Clear (0x1UL)     /*!< Disable                                                              */
48992   #define IPCT_INTENCLR3_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
48993   #define IPCT_INTENCLR3_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
48994 
48995 /* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
48996   #define IPCT_INTENCLR3_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
48997   #define IPCT_INTENCLR3_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
48998   #define IPCT_INTENCLR3_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
48999   #define IPCT_INTENCLR3_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
49000   #define IPCT_INTENCLR3_RECEIVE13_Clear (0x1UL)     /*!< Disable                                                              */
49001   #define IPCT_INTENCLR3_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49002   #define IPCT_INTENCLR3_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49003 
49004 /* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
49005   #define IPCT_INTENCLR3_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
49006   #define IPCT_INTENCLR3_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
49007   #define IPCT_INTENCLR3_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
49008   #define IPCT_INTENCLR3_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
49009   #define IPCT_INTENCLR3_RECEIVE14_Clear (0x1UL)     /*!< Disable                                                              */
49010   #define IPCT_INTENCLR3_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49011   #define IPCT_INTENCLR3_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49012 
49013 /* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
49014   #define IPCT_INTENCLR3_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
49015   #define IPCT_INTENCLR3_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR3_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
49016   #define IPCT_INTENCLR3_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
49017   #define IPCT_INTENCLR3_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
49018   #define IPCT_INTENCLR3_RECEIVE15_Clear (0x1UL)     /*!< Disable                                                              */
49019   #define IPCT_INTENCLR3_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49020   #define IPCT_INTENCLR3_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49021 
49022 /* ACKED0 @Bit 16 : Write '1' to disable interrupt for event ACKED[0] */
49023   #define IPCT_INTENCLR3_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
49024   #define IPCT_INTENCLR3_ACKED0_Msk (0x1UL << IPCT_INTENCLR3_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
49025   #define IPCT_INTENCLR3_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
49026   #define IPCT_INTENCLR3_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
49027   #define IPCT_INTENCLR3_ACKED0_Clear (0x1UL)        /*!< Disable                                                              */
49028   #define IPCT_INTENCLR3_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49029   #define IPCT_INTENCLR3_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49030 
49031 /* ACKED1 @Bit 17 : Write '1' to disable interrupt for event ACKED[1] */
49032   #define IPCT_INTENCLR3_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
49033   #define IPCT_INTENCLR3_ACKED1_Msk (0x1UL << IPCT_INTENCLR3_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
49034   #define IPCT_INTENCLR3_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
49035   #define IPCT_INTENCLR3_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
49036   #define IPCT_INTENCLR3_ACKED1_Clear (0x1UL)        /*!< Disable                                                              */
49037   #define IPCT_INTENCLR3_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49038   #define IPCT_INTENCLR3_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49039 
49040 /* ACKED2 @Bit 18 : Write '1' to disable interrupt for event ACKED[2] */
49041   #define IPCT_INTENCLR3_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
49042   #define IPCT_INTENCLR3_ACKED2_Msk (0x1UL << IPCT_INTENCLR3_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
49043   #define IPCT_INTENCLR3_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
49044   #define IPCT_INTENCLR3_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
49045   #define IPCT_INTENCLR3_ACKED2_Clear (0x1UL)        /*!< Disable                                                              */
49046   #define IPCT_INTENCLR3_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49047   #define IPCT_INTENCLR3_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49048 
49049 /* ACKED3 @Bit 19 : Write '1' to disable interrupt for event ACKED[3] */
49050   #define IPCT_INTENCLR3_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
49051   #define IPCT_INTENCLR3_ACKED3_Msk (0x1UL << IPCT_INTENCLR3_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
49052   #define IPCT_INTENCLR3_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
49053   #define IPCT_INTENCLR3_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
49054   #define IPCT_INTENCLR3_ACKED3_Clear (0x1UL)        /*!< Disable                                                              */
49055   #define IPCT_INTENCLR3_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49056   #define IPCT_INTENCLR3_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49057 
49058 /* ACKED4 @Bit 20 : Write '1' to disable interrupt for event ACKED[4] */
49059   #define IPCT_INTENCLR3_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
49060   #define IPCT_INTENCLR3_ACKED4_Msk (0x1UL << IPCT_INTENCLR3_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
49061   #define IPCT_INTENCLR3_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
49062   #define IPCT_INTENCLR3_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
49063   #define IPCT_INTENCLR3_ACKED4_Clear (0x1UL)        /*!< Disable                                                              */
49064   #define IPCT_INTENCLR3_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49065   #define IPCT_INTENCLR3_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49066 
49067 /* ACKED5 @Bit 21 : Write '1' to disable interrupt for event ACKED[5] */
49068   #define IPCT_INTENCLR3_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
49069   #define IPCT_INTENCLR3_ACKED5_Msk (0x1UL << IPCT_INTENCLR3_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
49070   #define IPCT_INTENCLR3_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
49071   #define IPCT_INTENCLR3_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
49072   #define IPCT_INTENCLR3_ACKED5_Clear (0x1UL)        /*!< Disable                                                              */
49073   #define IPCT_INTENCLR3_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49074   #define IPCT_INTENCLR3_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49075 
49076 /* ACKED6 @Bit 22 : Write '1' to disable interrupt for event ACKED[6] */
49077   #define IPCT_INTENCLR3_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
49078   #define IPCT_INTENCLR3_ACKED6_Msk (0x1UL << IPCT_INTENCLR3_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
49079   #define IPCT_INTENCLR3_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
49080   #define IPCT_INTENCLR3_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
49081   #define IPCT_INTENCLR3_ACKED6_Clear (0x1UL)        /*!< Disable                                                              */
49082   #define IPCT_INTENCLR3_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49083   #define IPCT_INTENCLR3_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49084 
49085 /* ACKED7 @Bit 23 : Write '1' to disable interrupt for event ACKED[7] */
49086   #define IPCT_INTENCLR3_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
49087   #define IPCT_INTENCLR3_ACKED7_Msk (0x1UL << IPCT_INTENCLR3_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
49088   #define IPCT_INTENCLR3_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
49089   #define IPCT_INTENCLR3_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
49090   #define IPCT_INTENCLR3_ACKED7_Clear (0x1UL)        /*!< Disable                                                              */
49091   #define IPCT_INTENCLR3_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49092   #define IPCT_INTENCLR3_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49093 
49094 /* ACKED8 @Bit 24 : Write '1' to disable interrupt for event ACKED[8] */
49095   #define IPCT_INTENCLR3_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
49096   #define IPCT_INTENCLR3_ACKED8_Msk (0x1UL << IPCT_INTENCLR3_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
49097   #define IPCT_INTENCLR3_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
49098   #define IPCT_INTENCLR3_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
49099   #define IPCT_INTENCLR3_ACKED8_Clear (0x1UL)        /*!< Disable                                                              */
49100   #define IPCT_INTENCLR3_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49101   #define IPCT_INTENCLR3_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49102 
49103 /* ACKED9 @Bit 25 : Write '1' to disable interrupt for event ACKED[9] */
49104   #define IPCT_INTENCLR3_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
49105   #define IPCT_INTENCLR3_ACKED9_Msk (0x1UL << IPCT_INTENCLR3_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
49106   #define IPCT_INTENCLR3_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
49107   #define IPCT_INTENCLR3_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
49108   #define IPCT_INTENCLR3_ACKED9_Clear (0x1UL)        /*!< Disable                                                              */
49109   #define IPCT_INTENCLR3_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49110   #define IPCT_INTENCLR3_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49111 
49112 /* ACKED10 @Bit 26 : Write '1' to disable interrupt for event ACKED[10] */
49113   #define IPCT_INTENCLR3_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
49114   #define IPCT_INTENCLR3_ACKED10_Msk (0x1UL << IPCT_INTENCLR3_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
49115   #define IPCT_INTENCLR3_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
49116   #define IPCT_INTENCLR3_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
49117   #define IPCT_INTENCLR3_ACKED10_Clear (0x1UL)       /*!< Disable                                                              */
49118   #define IPCT_INTENCLR3_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49119   #define IPCT_INTENCLR3_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49120 
49121 /* ACKED11 @Bit 27 : Write '1' to disable interrupt for event ACKED[11] */
49122   #define IPCT_INTENCLR3_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
49123   #define IPCT_INTENCLR3_ACKED11_Msk (0x1UL << IPCT_INTENCLR3_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
49124   #define IPCT_INTENCLR3_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
49125   #define IPCT_INTENCLR3_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
49126   #define IPCT_INTENCLR3_ACKED11_Clear (0x1UL)       /*!< Disable                                                              */
49127   #define IPCT_INTENCLR3_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49128   #define IPCT_INTENCLR3_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49129 
49130 /* ACKED12 @Bit 28 : Write '1' to disable interrupt for event ACKED[12] */
49131   #define IPCT_INTENCLR3_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
49132   #define IPCT_INTENCLR3_ACKED12_Msk (0x1UL << IPCT_INTENCLR3_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
49133   #define IPCT_INTENCLR3_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
49134   #define IPCT_INTENCLR3_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
49135   #define IPCT_INTENCLR3_ACKED12_Clear (0x1UL)       /*!< Disable                                                              */
49136   #define IPCT_INTENCLR3_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49137   #define IPCT_INTENCLR3_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49138 
49139 /* ACKED13 @Bit 29 : Write '1' to disable interrupt for event ACKED[13] */
49140   #define IPCT_INTENCLR3_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
49141   #define IPCT_INTENCLR3_ACKED13_Msk (0x1UL << IPCT_INTENCLR3_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
49142   #define IPCT_INTENCLR3_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
49143   #define IPCT_INTENCLR3_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
49144   #define IPCT_INTENCLR3_ACKED13_Clear (0x1UL)       /*!< Disable                                                              */
49145   #define IPCT_INTENCLR3_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49146   #define IPCT_INTENCLR3_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49147 
49148 /* ACKED14 @Bit 30 : Write '1' to disable interrupt for event ACKED[14] */
49149   #define IPCT_INTENCLR3_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
49150   #define IPCT_INTENCLR3_ACKED14_Msk (0x1UL << IPCT_INTENCLR3_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
49151   #define IPCT_INTENCLR3_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
49152   #define IPCT_INTENCLR3_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
49153   #define IPCT_INTENCLR3_ACKED14_Clear (0x1UL)       /*!< Disable                                                              */
49154   #define IPCT_INTENCLR3_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49155   #define IPCT_INTENCLR3_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49156 
49157 /* ACKED15 @Bit 31 : Write '1' to disable interrupt for event ACKED[15] */
49158   #define IPCT_INTENCLR3_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
49159   #define IPCT_INTENCLR3_ACKED15_Msk (0x1UL << IPCT_INTENCLR3_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
49160   #define IPCT_INTENCLR3_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
49161   #define IPCT_INTENCLR3_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
49162   #define IPCT_INTENCLR3_ACKED15_Clear (0x1UL)       /*!< Disable                                                              */
49163   #define IPCT_INTENCLR3_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49164   #define IPCT_INTENCLR3_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49165 
49166 
49167 /* IPCT_INTPEND3: Pending interrupts */
49168   #define IPCT_INTPEND3_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND3 register.                                    */
49169 
49170 /* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
49171   #define IPCT_INTPEND3_RECEIVE0_Pos (0UL)           /*!< Position of RECEIVE0 field.                                          */
49172   #define IPCT_INTPEND3_RECEIVE0_Msk (0x1UL << IPCT_INTPEND3_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                    */
49173   #define IPCT_INTPEND3_RECEIVE0_Min (0x0UL)         /*!< Min enumerator value of RECEIVE0 field.                              */
49174   #define IPCT_INTPEND3_RECEIVE0_Max (0x1UL)         /*!< Max enumerator value of RECEIVE0 field.                              */
49175   #define IPCT_INTPEND3_RECEIVE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49176   #define IPCT_INTPEND3_RECEIVE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
49177 
49178 /* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
49179   #define IPCT_INTPEND3_RECEIVE1_Pos (1UL)           /*!< Position of RECEIVE1 field.                                          */
49180   #define IPCT_INTPEND3_RECEIVE1_Msk (0x1UL << IPCT_INTPEND3_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                    */
49181   #define IPCT_INTPEND3_RECEIVE1_Min (0x0UL)         /*!< Min enumerator value of RECEIVE1 field.                              */
49182   #define IPCT_INTPEND3_RECEIVE1_Max (0x1UL)         /*!< Max enumerator value of RECEIVE1 field.                              */
49183   #define IPCT_INTPEND3_RECEIVE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49184   #define IPCT_INTPEND3_RECEIVE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
49185 
49186 /* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
49187   #define IPCT_INTPEND3_RECEIVE2_Pos (2UL)           /*!< Position of RECEIVE2 field.                                          */
49188   #define IPCT_INTPEND3_RECEIVE2_Msk (0x1UL << IPCT_INTPEND3_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                    */
49189   #define IPCT_INTPEND3_RECEIVE2_Min (0x0UL)         /*!< Min enumerator value of RECEIVE2 field.                              */
49190   #define IPCT_INTPEND3_RECEIVE2_Max (0x1UL)         /*!< Max enumerator value of RECEIVE2 field.                              */
49191   #define IPCT_INTPEND3_RECEIVE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49192   #define IPCT_INTPEND3_RECEIVE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
49193 
49194 /* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
49195   #define IPCT_INTPEND3_RECEIVE3_Pos (3UL)           /*!< Position of RECEIVE3 field.                                          */
49196   #define IPCT_INTPEND3_RECEIVE3_Msk (0x1UL << IPCT_INTPEND3_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                    */
49197   #define IPCT_INTPEND3_RECEIVE3_Min (0x0UL)         /*!< Min enumerator value of RECEIVE3 field.                              */
49198   #define IPCT_INTPEND3_RECEIVE3_Max (0x1UL)         /*!< Max enumerator value of RECEIVE3 field.                              */
49199   #define IPCT_INTPEND3_RECEIVE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49200   #define IPCT_INTPEND3_RECEIVE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
49201 
49202 /* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
49203   #define IPCT_INTPEND3_RECEIVE4_Pos (4UL)           /*!< Position of RECEIVE4 field.                                          */
49204   #define IPCT_INTPEND3_RECEIVE4_Msk (0x1UL << IPCT_INTPEND3_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                    */
49205   #define IPCT_INTPEND3_RECEIVE4_Min (0x0UL)         /*!< Min enumerator value of RECEIVE4 field.                              */
49206   #define IPCT_INTPEND3_RECEIVE4_Max (0x1UL)         /*!< Max enumerator value of RECEIVE4 field.                              */
49207   #define IPCT_INTPEND3_RECEIVE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49208   #define IPCT_INTPEND3_RECEIVE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
49209 
49210 /* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
49211   #define IPCT_INTPEND3_RECEIVE5_Pos (5UL)           /*!< Position of RECEIVE5 field.                                          */
49212   #define IPCT_INTPEND3_RECEIVE5_Msk (0x1UL << IPCT_INTPEND3_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                    */
49213   #define IPCT_INTPEND3_RECEIVE5_Min (0x0UL)         /*!< Min enumerator value of RECEIVE5 field.                              */
49214   #define IPCT_INTPEND3_RECEIVE5_Max (0x1UL)         /*!< Max enumerator value of RECEIVE5 field.                              */
49215   #define IPCT_INTPEND3_RECEIVE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49216   #define IPCT_INTPEND3_RECEIVE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
49217 
49218 /* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
49219   #define IPCT_INTPEND3_RECEIVE6_Pos (6UL)           /*!< Position of RECEIVE6 field.                                          */
49220   #define IPCT_INTPEND3_RECEIVE6_Msk (0x1UL << IPCT_INTPEND3_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                    */
49221   #define IPCT_INTPEND3_RECEIVE6_Min (0x0UL)         /*!< Min enumerator value of RECEIVE6 field.                              */
49222   #define IPCT_INTPEND3_RECEIVE6_Max (0x1UL)         /*!< Max enumerator value of RECEIVE6 field.                              */
49223   #define IPCT_INTPEND3_RECEIVE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49224   #define IPCT_INTPEND3_RECEIVE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
49225 
49226 /* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
49227   #define IPCT_INTPEND3_RECEIVE7_Pos (7UL)           /*!< Position of RECEIVE7 field.                                          */
49228   #define IPCT_INTPEND3_RECEIVE7_Msk (0x1UL << IPCT_INTPEND3_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                    */
49229   #define IPCT_INTPEND3_RECEIVE7_Min (0x0UL)         /*!< Min enumerator value of RECEIVE7 field.                              */
49230   #define IPCT_INTPEND3_RECEIVE7_Max (0x1UL)         /*!< Max enumerator value of RECEIVE7 field.                              */
49231   #define IPCT_INTPEND3_RECEIVE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49232   #define IPCT_INTPEND3_RECEIVE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
49233 
49234 /* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
49235   #define IPCT_INTPEND3_RECEIVE8_Pos (8UL)           /*!< Position of RECEIVE8 field.                                          */
49236   #define IPCT_INTPEND3_RECEIVE8_Msk (0x1UL << IPCT_INTPEND3_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                    */
49237   #define IPCT_INTPEND3_RECEIVE8_Min (0x0UL)         /*!< Min enumerator value of RECEIVE8 field.                              */
49238   #define IPCT_INTPEND3_RECEIVE8_Max (0x1UL)         /*!< Max enumerator value of RECEIVE8 field.                              */
49239   #define IPCT_INTPEND3_RECEIVE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49240   #define IPCT_INTPEND3_RECEIVE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
49241 
49242 /* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
49243   #define IPCT_INTPEND3_RECEIVE9_Pos (9UL)           /*!< Position of RECEIVE9 field.                                          */
49244   #define IPCT_INTPEND3_RECEIVE9_Msk (0x1UL << IPCT_INTPEND3_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                    */
49245   #define IPCT_INTPEND3_RECEIVE9_Min (0x0UL)         /*!< Min enumerator value of RECEIVE9 field.                              */
49246   #define IPCT_INTPEND3_RECEIVE9_Max (0x1UL)         /*!< Max enumerator value of RECEIVE9 field.                              */
49247   #define IPCT_INTPEND3_RECEIVE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
49248   #define IPCT_INTPEND3_RECEIVE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
49249 
49250 /* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
49251   #define IPCT_INTPEND3_RECEIVE10_Pos (10UL)         /*!< Position of RECEIVE10 field.                                         */
49252   #define IPCT_INTPEND3_RECEIVE10_Msk (0x1UL << IPCT_INTPEND3_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                 */
49253   #define IPCT_INTPEND3_RECEIVE10_Min (0x0UL)        /*!< Min enumerator value of RECEIVE10 field.                             */
49254   #define IPCT_INTPEND3_RECEIVE10_Max (0x1UL)        /*!< Max enumerator value of RECEIVE10 field.                             */
49255   #define IPCT_INTPEND3_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
49256   #define IPCT_INTPEND3_RECEIVE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
49257 
49258 /* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
49259   #define IPCT_INTPEND3_RECEIVE11_Pos (11UL)         /*!< Position of RECEIVE11 field.                                         */
49260   #define IPCT_INTPEND3_RECEIVE11_Msk (0x1UL << IPCT_INTPEND3_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                 */
49261   #define IPCT_INTPEND3_RECEIVE11_Min (0x0UL)        /*!< Min enumerator value of RECEIVE11 field.                             */
49262   #define IPCT_INTPEND3_RECEIVE11_Max (0x1UL)        /*!< Max enumerator value of RECEIVE11 field.                             */
49263   #define IPCT_INTPEND3_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
49264   #define IPCT_INTPEND3_RECEIVE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
49265 
49266 /* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
49267   #define IPCT_INTPEND3_RECEIVE12_Pos (12UL)         /*!< Position of RECEIVE12 field.                                         */
49268   #define IPCT_INTPEND3_RECEIVE12_Msk (0x1UL << IPCT_INTPEND3_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                 */
49269   #define IPCT_INTPEND3_RECEIVE12_Min (0x0UL)        /*!< Min enumerator value of RECEIVE12 field.                             */
49270   #define IPCT_INTPEND3_RECEIVE12_Max (0x1UL)        /*!< Max enumerator value of RECEIVE12 field.                             */
49271   #define IPCT_INTPEND3_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
49272   #define IPCT_INTPEND3_RECEIVE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
49273 
49274 /* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
49275   #define IPCT_INTPEND3_RECEIVE13_Pos (13UL)         /*!< Position of RECEIVE13 field.                                         */
49276   #define IPCT_INTPEND3_RECEIVE13_Msk (0x1UL << IPCT_INTPEND3_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                 */
49277   #define IPCT_INTPEND3_RECEIVE13_Min (0x0UL)        /*!< Min enumerator value of RECEIVE13 field.                             */
49278   #define IPCT_INTPEND3_RECEIVE13_Max (0x1UL)        /*!< Max enumerator value of RECEIVE13 field.                             */
49279   #define IPCT_INTPEND3_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
49280   #define IPCT_INTPEND3_RECEIVE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
49281 
49282 /* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
49283   #define IPCT_INTPEND3_RECEIVE14_Pos (14UL)         /*!< Position of RECEIVE14 field.                                         */
49284   #define IPCT_INTPEND3_RECEIVE14_Msk (0x1UL << IPCT_INTPEND3_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                 */
49285   #define IPCT_INTPEND3_RECEIVE14_Min (0x0UL)        /*!< Min enumerator value of RECEIVE14 field.                             */
49286   #define IPCT_INTPEND3_RECEIVE14_Max (0x1UL)        /*!< Max enumerator value of RECEIVE14 field.                             */
49287   #define IPCT_INTPEND3_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
49288   #define IPCT_INTPEND3_RECEIVE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
49289 
49290 /* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
49291   #define IPCT_INTPEND3_RECEIVE15_Pos (15UL)         /*!< Position of RECEIVE15 field.                                         */
49292   #define IPCT_INTPEND3_RECEIVE15_Msk (0x1UL << IPCT_INTPEND3_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                 */
49293   #define IPCT_INTPEND3_RECEIVE15_Min (0x0UL)        /*!< Min enumerator value of RECEIVE15 field.                             */
49294   #define IPCT_INTPEND3_RECEIVE15_Max (0x1UL)        /*!< Max enumerator value of RECEIVE15 field.                             */
49295   #define IPCT_INTPEND3_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
49296   #define IPCT_INTPEND3_RECEIVE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
49297 
49298 /* ACKED0 @Bit 16 : Read pending status of interrupt for event ACKED[0] */
49299   #define IPCT_INTPEND3_ACKED0_Pos (16UL)            /*!< Position of ACKED0 field.                                            */
49300   #define IPCT_INTPEND3_ACKED0_Msk (0x1UL << IPCT_INTPEND3_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                          */
49301   #define IPCT_INTPEND3_ACKED0_Min (0x0UL)           /*!< Min enumerator value of ACKED0 field.                                */
49302   #define IPCT_INTPEND3_ACKED0_Max (0x1UL)           /*!< Max enumerator value of ACKED0 field.                                */
49303   #define IPCT_INTPEND3_ACKED0_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49304   #define IPCT_INTPEND3_ACKED0_Pending (0x1UL)       /*!< Read: Pending                                                        */
49305 
49306 /* ACKED1 @Bit 17 : Read pending status of interrupt for event ACKED[1] */
49307   #define IPCT_INTPEND3_ACKED1_Pos (17UL)            /*!< Position of ACKED1 field.                                            */
49308   #define IPCT_INTPEND3_ACKED1_Msk (0x1UL << IPCT_INTPEND3_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                          */
49309   #define IPCT_INTPEND3_ACKED1_Min (0x0UL)           /*!< Min enumerator value of ACKED1 field.                                */
49310   #define IPCT_INTPEND3_ACKED1_Max (0x1UL)           /*!< Max enumerator value of ACKED1 field.                                */
49311   #define IPCT_INTPEND3_ACKED1_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49312   #define IPCT_INTPEND3_ACKED1_Pending (0x1UL)       /*!< Read: Pending                                                        */
49313 
49314 /* ACKED2 @Bit 18 : Read pending status of interrupt for event ACKED[2] */
49315   #define IPCT_INTPEND3_ACKED2_Pos (18UL)            /*!< Position of ACKED2 field.                                            */
49316   #define IPCT_INTPEND3_ACKED2_Msk (0x1UL << IPCT_INTPEND3_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                          */
49317   #define IPCT_INTPEND3_ACKED2_Min (0x0UL)           /*!< Min enumerator value of ACKED2 field.                                */
49318   #define IPCT_INTPEND3_ACKED2_Max (0x1UL)           /*!< Max enumerator value of ACKED2 field.                                */
49319   #define IPCT_INTPEND3_ACKED2_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49320   #define IPCT_INTPEND3_ACKED2_Pending (0x1UL)       /*!< Read: Pending                                                        */
49321 
49322 /* ACKED3 @Bit 19 : Read pending status of interrupt for event ACKED[3] */
49323   #define IPCT_INTPEND3_ACKED3_Pos (19UL)            /*!< Position of ACKED3 field.                                            */
49324   #define IPCT_INTPEND3_ACKED3_Msk (0x1UL << IPCT_INTPEND3_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                          */
49325   #define IPCT_INTPEND3_ACKED3_Min (0x0UL)           /*!< Min enumerator value of ACKED3 field.                                */
49326   #define IPCT_INTPEND3_ACKED3_Max (0x1UL)           /*!< Max enumerator value of ACKED3 field.                                */
49327   #define IPCT_INTPEND3_ACKED3_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49328   #define IPCT_INTPEND3_ACKED3_Pending (0x1UL)       /*!< Read: Pending                                                        */
49329 
49330 /* ACKED4 @Bit 20 : Read pending status of interrupt for event ACKED[4] */
49331   #define IPCT_INTPEND3_ACKED4_Pos (20UL)            /*!< Position of ACKED4 field.                                            */
49332   #define IPCT_INTPEND3_ACKED4_Msk (0x1UL << IPCT_INTPEND3_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                          */
49333   #define IPCT_INTPEND3_ACKED4_Min (0x0UL)           /*!< Min enumerator value of ACKED4 field.                                */
49334   #define IPCT_INTPEND3_ACKED4_Max (0x1UL)           /*!< Max enumerator value of ACKED4 field.                                */
49335   #define IPCT_INTPEND3_ACKED4_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49336   #define IPCT_INTPEND3_ACKED4_Pending (0x1UL)       /*!< Read: Pending                                                        */
49337 
49338 /* ACKED5 @Bit 21 : Read pending status of interrupt for event ACKED[5] */
49339   #define IPCT_INTPEND3_ACKED5_Pos (21UL)            /*!< Position of ACKED5 field.                                            */
49340   #define IPCT_INTPEND3_ACKED5_Msk (0x1UL << IPCT_INTPEND3_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                          */
49341   #define IPCT_INTPEND3_ACKED5_Min (0x0UL)           /*!< Min enumerator value of ACKED5 field.                                */
49342   #define IPCT_INTPEND3_ACKED5_Max (0x1UL)           /*!< Max enumerator value of ACKED5 field.                                */
49343   #define IPCT_INTPEND3_ACKED5_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49344   #define IPCT_INTPEND3_ACKED5_Pending (0x1UL)       /*!< Read: Pending                                                        */
49345 
49346 /* ACKED6 @Bit 22 : Read pending status of interrupt for event ACKED[6] */
49347   #define IPCT_INTPEND3_ACKED6_Pos (22UL)            /*!< Position of ACKED6 field.                                            */
49348   #define IPCT_INTPEND3_ACKED6_Msk (0x1UL << IPCT_INTPEND3_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                          */
49349   #define IPCT_INTPEND3_ACKED6_Min (0x0UL)           /*!< Min enumerator value of ACKED6 field.                                */
49350   #define IPCT_INTPEND3_ACKED6_Max (0x1UL)           /*!< Max enumerator value of ACKED6 field.                                */
49351   #define IPCT_INTPEND3_ACKED6_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49352   #define IPCT_INTPEND3_ACKED6_Pending (0x1UL)       /*!< Read: Pending                                                        */
49353 
49354 /* ACKED7 @Bit 23 : Read pending status of interrupt for event ACKED[7] */
49355   #define IPCT_INTPEND3_ACKED7_Pos (23UL)            /*!< Position of ACKED7 field.                                            */
49356   #define IPCT_INTPEND3_ACKED7_Msk (0x1UL << IPCT_INTPEND3_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                          */
49357   #define IPCT_INTPEND3_ACKED7_Min (0x0UL)           /*!< Min enumerator value of ACKED7 field.                                */
49358   #define IPCT_INTPEND3_ACKED7_Max (0x1UL)           /*!< Max enumerator value of ACKED7 field.                                */
49359   #define IPCT_INTPEND3_ACKED7_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49360   #define IPCT_INTPEND3_ACKED7_Pending (0x1UL)       /*!< Read: Pending                                                        */
49361 
49362 /* ACKED8 @Bit 24 : Read pending status of interrupt for event ACKED[8] */
49363   #define IPCT_INTPEND3_ACKED8_Pos (24UL)            /*!< Position of ACKED8 field.                                            */
49364   #define IPCT_INTPEND3_ACKED8_Msk (0x1UL << IPCT_INTPEND3_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                          */
49365   #define IPCT_INTPEND3_ACKED8_Min (0x0UL)           /*!< Min enumerator value of ACKED8 field.                                */
49366   #define IPCT_INTPEND3_ACKED8_Max (0x1UL)           /*!< Max enumerator value of ACKED8 field.                                */
49367   #define IPCT_INTPEND3_ACKED8_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49368   #define IPCT_INTPEND3_ACKED8_Pending (0x1UL)       /*!< Read: Pending                                                        */
49369 
49370 /* ACKED9 @Bit 25 : Read pending status of interrupt for event ACKED[9] */
49371   #define IPCT_INTPEND3_ACKED9_Pos (25UL)            /*!< Position of ACKED9 field.                                            */
49372   #define IPCT_INTPEND3_ACKED9_Msk (0x1UL << IPCT_INTPEND3_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                          */
49373   #define IPCT_INTPEND3_ACKED9_Min (0x0UL)           /*!< Min enumerator value of ACKED9 field.                                */
49374   #define IPCT_INTPEND3_ACKED9_Max (0x1UL)           /*!< Max enumerator value of ACKED9 field.                                */
49375   #define IPCT_INTPEND3_ACKED9_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
49376   #define IPCT_INTPEND3_ACKED9_Pending (0x1UL)       /*!< Read: Pending                                                        */
49377 
49378 /* ACKED10 @Bit 26 : Read pending status of interrupt for event ACKED[10] */
49379   #define IPCT_INTPEND3_ACKED10_Pos (26UL)           /*!< Position of ACKED10 field.                                           */
49380   #define IPCT_INTPEND3_ACKED10_Msk (0x1UL << IPCT_INTPEND3_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                       */
49381   #define IPCT_INTPEND3_ACKED10_Min (0x0UL)          /*!< Min enumerator value of ACKED10 field.                               */
49382   #define IPCT_INTPEND3_ACKED10_Max (0x1UL)          /*!< Max enumerator value of ACKED10 field.                               */
49383   #define IPCT_INTPEND3_ACKED10_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
49384   #define IPCT_INTPEND3_ACKED10_Pending (0x1UL)      /*!< Read: Pending                                                        */
49385 
49386 /* ACKED11 @Bit 27 : Read pending status of interrupt for event ACKED[11] */
49387   #define IPCT_INTPEND3_ACKED11_Pos (27UL)           /*!< Position of ACKED11 field.                                           */
49388   #define IPCT_INTPEND3_ACKED11_Msk (0x1UL << IPCT_INTPEND3_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                       */
49389   #define IPCT_INTPEND3_ACKED11_Min (0x0UL)          /*!< Min enumerator value of ACKED11 field.                               */
49390   #define IPCT_INTPEND3_ACKED11_Max (0x1UL)          /*!< Max enumerator value of ACKED11 field.                               */
49391   #define IPCT_INTPEND3_ACKED11_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
49392   #define IPCT_INTPEND3_ACKED11_Pending (0x1UL)      /*!< Read: Pending                                                        */
49393 
49394 /* ACKED12 @Bit 28 : Read pending status of interrupt for event ACKED[12] */
49395   #define IPCT_INTPEND3_ACKED12_Pos (28UL)           /*!< Position of ACKED12 field.                                           */
49396   #define IPCT_INTPEND3_ACKED12_Msk (0x1UL << IPCT_INTPEND3_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                       */
49397   #define IPCT_INTPEND3_ACKED12_Min (0x0UL)          /*!< Min enumerator value of ACKED12 field.                               */
49398   #define IPCT_INTPEND3_ACKED12_Max (0x1UL)          /*!< Max enumerator value of ACKED12 field.                               */
49399   #define IPCT_INTPEND3_ACKED12_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
49400   #define IPCT_INTPEND3_ACKED12_Pending (0x1UL)      /*!< Read: Pending                                                        */
49401 
49402 /* ACKED13 @Bit 29 : Read pending status of interrupt for event ACKED[13] */
49403   #define IPCT_INTPEND3_ACKED13_Pos (29UL)           /*!< Position of ACKED13 field.                                           */
49404   #define IPCT_INTPEND3_ACKED13_Msk (0x1UL << IPCT_INTPEND3_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                       */
49405   #define IPCT_INTPEND3_ACKED13_Min (0x0UL)          /*!< Min enumerator value of ACKED13 field.                               */
49406   #define IPCT_INTPEND3_ACKED13_Max (0x1UL)          /*!< Max enumerator value of ACKED13 field.                               */
49407   #define IPCT_INTPEND3_ACKED13_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
49408   #define IPCT_INTPEND3_ACKED13_Pending (0x1UL)      /*!< Read: Pending                                                        */
49409 
49410 /* ACKED14 @Bit 30 : Read pending status of interrupt for event ACKED[14] */
49411   #define IPCT_INTPEND3_ACKED14_Pos (30UL)           /*!< Position of ACKED14 field.                                           */
49412   #define IPCT_INTPEND3_ACKED14_Msk (0x1UL << IPCT_INTPEND3_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                       */
49413   #define IPCT_INTPEND3_ACKED14_Min (0x0UL)          /*!< Min enumerator value of ACKED14 field.                               */
49414   #define IPCT_INTPEND3_ACKED14_Max (0x1UL)          /*!< Max enumerator value of ACKED14 field.                               */
49415   #define IPCT_INTPEND3_ACKED14_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
49416   #define IPCT_INTPEND3_ACKED14_Pending (0x1UL)      /*!< Read: Pending                                                        */
49417 
49418 /* ACKED15 @Bit 31 : Read pending status of interrupt for event ACKED[15] */
49419   #define IPCT_INTPEND3_ACKED15_Pos (31UL)           /*!< Position of ACKED15 field.                                           */
49420   #define IPCT_INTPEND3_ACKED15_Msk (0x1UL << IPCT_INTPEND3_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                       */
49421   #define IPCT_INTPEND3_ACKED15_Min (0x0UL)          /*!< Min enumerator value of ACKED15 field.                               */
49422   #define IPCT_INTPEND3_ACKED15_Max (0x1UL)          /*!< Max enumerator value of ACKED15 field.                               */
49423   #define IPCT_INTPEND3_ACKED15_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
49424   #define IPCT_INTPEND3_ACKED15_Pending (0x1UL)      /*!< Read: Pending                                                        */
49425 
49426 
49427 /* IPCT_INTEN4: Enable or disable interrupt */
49428   #define IPCT_INTEN4_ResetValue (0x00000000UL)      /*!< Reset value of INTEN4 register.                                      */
49429 
49430 /* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
49431   #define IPCT_INTEN4_RECEIVE0_Pos (0UL)             /*!< Position of RECEIVE0 field.                                          */
49432   #define IPCT_INTEN4_RECEIVE0_Msk (0x1UL << IPCT_INTEN4_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                        */
49433   #define IPCT_INTEN4_RECEIVE0_Min (0x0UL)           /*!< Min enumerator value of RECEIVE0 field.                              */
49434   #define IPCT_INTEN4_RECEIVE0_Max (0x1UL)           /*!< Max enumerator value of RECEIVE0 field.                              */
49435   #define IPCT_INTEN4_RECEIVE0_Disabled (0x0UL)      /*!< Disable                                                              */
49436   #define IPCT_INTEN4_RECEIVE0_Enabled (0x1UL)       /*!< Enable                                                               */
49437 
49438 /* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
49439   #define IPCT_INTEN4_RECEIVE1_Pos (1UL)             /*!< Position of RECEIVE1 field.                                          */
49440   #define IPCT_INTEN4_RECEIVE1_Msk (0x1UL << IPCT_INTEN4_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                        */
49441   #define IPCT_INTEN4_RECEIVE1_Min (0x0UL)           /*!< Min enumerator value of RECEIVE1 field.                              */
49442   #define IPCT_INTEN4_RECEIVE1_Max (0x1UL)           /*!< Max enumerator value of RECEIVE1 field.                              */
49443   #define IPCT_INTEN4_RECEIVE1_Disabled (0x0UL)      /*!< Disable                                                              */
49444   #define IPCT_INTEN4_RECEIVE1_Enabled (0x1UL)       /*!< Enable                                                               */
49445 
49446 /* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
49447   #define IPCT_INTEN4_RECEIVE2_Pos (2UL)             /*!< Position of RECEIVE2 field.                                          */
49448   #define IPCT_INTEN4_RECEIVE2_Msk (0x1UL << IPCT_INTEN4_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                        */
49449   #define IPCT_INTEN4_RECEIVE2_Min (0x0UL)           /*!< Min enumerator value of RECEIVE2 field.                              */
49450   #define IPCT_INTEN4_RECEIVE2_Max (0x1UL)           /*!< Max enumerator value of RECEIVE2 field.                              */
49451   #define IPCT_INTEN4_RECEIVE2_Disabled (0x0UL)      /*!< Disable                                                              */
49452   #define IPCT_INTEN4_RECEIVE2_Enabled (0x1UL)       /*!< Enable                                                               */
49453 
49454 /* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
49455   #define IPCT_INTEN4_RECEIVE3_Pos (3UL)             /*!< Position of RECEIVE3 field.                                          */
49456   #define IPCT_INTEN4_RECEIVE3_Msk (0x1UL << IPCT_INTEN4_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                        */
49457   #define IPCT_INTEN4_RECEIVE3_Min (0x0UL)           /*!< Min enumerator value of RECEIVE3 field.                              */
49458   #define IPCT_INTEN4_RECEIVE3_Max (0x1UL)           /*!< Max enumerator value of RECEIVE3 field.                              */
49459   #define IPCT_INTEN4_RECEIVE3_Disabled (0x0UL)      /*!< Disable                                                              */
49460   #define IPCT_INTEN4_RECEIVE3_Enabled (0x1UL)       /*!< Enable                                                               */
49461 
49462 /* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
49463   #define IPCT_INTEN4_RECEIVE4_Pos (4UL)             /*!< Position of RECEIVE4 field.                                          */
49464   #define IPCT_INTEN4_RECEIVE4_Msk (0x1UL << IPCT_INTEN4_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                        */
49465   #define IPCT_INTEN4_RECEIVE4_Min (0x0UL)           /*!< Min enumerator value of RECEIVE4 field.                              */
49466   #define IPCT_INTEN4_RECEIVE4_Max (0x1UL)           /*!< Max enumerator value of RECEIVE4 field.                              */
49467   #define IPCT_INTEN4_RECEIVE4_Disabled (0x0UL)      /*!< Disable                                                              */
49468   #define IPCT_INTEN4_RECEIVE4_Enabled (0x1UL)       /*!< Enable                                                               */
49469 
49470 /* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
49471   #define IPCT_INTEN4_RECEIVE5_Pos (5UL)             /*!< Position of RECEIVE5 field.                                          */
49472   #define IPCT_INTEN4_RECEIVE5_Msk (0x1UL << IPCT_INTEN4_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                        */
49473   #define IPCT_INTEN4_RECEIVE5_Min (0x0UL)           /*!< Min enumerator value of RECEIVE5 field.                              */
49474   #define IPCT_INTEN4_RECEIVE5_Max (0x1UL)           /*!< Max enumerator value of RECEIVE5 field.                              */
49475   #define IPCT_INTEN4_RECEIVE5_Disabled (0x0UL)      /*!< Disable                                                              */
49476   #define IPCT_INTEN4_RECEIVE5_Enabled (0x1UL)       /*!< Enable                                                               */
49477 
49478 /* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
49479   #define IPCT_INTEN4_RECEIVE6_Pos (6UL)             /*!< Position of RECEIVE6 field.                                          */
49480   #define IPCT_INTEN4_RECEIVE6_Msk (0x1UL << IPCT_INTEN4_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                        */
49481   #define IPCT_INTEN4_RECEIVE6_Min (0x0UL)           /*!< Min enumerator value of RECEIVE6 field.                              */
49482   #define IPCT_INTEN4_RECEIVE6_Max (0x1UL)           /*!< Max enumerator value of RECEIVE6 field.                              */
49483   #define IPCT_INTEN4_RECEIVE6_Disabled (0x0UL)      /*!< Disable                                                              */
49484   #define IPCT_INTEN4_RECEIVE6_Enabled (0x1UL)       /*!< Enable                                                               */
49485 
49486 /* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
49487   #define IPCT_INTEN4_RECEIVE7_Pos (7UL)             /*!< Position of RECEIVE7 field.                                          */
49488   #define IPCT_INTEN4_RECEIVE7_Msk (0x1UL << IPCT_INTEN4_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                        */
49489   #define IPCT_INTEN4_RECEIVE7_Min (0x0UL)           /*!< Min enumerator value of RECEIVE7 field.                              */
49490   #define IPCT_INTEN4_RECEIVE7_Max (0x1UL)           /*!< Max enumerator value of RECEIVE7 field.                              */
49491   #define IPCT_INTEN4_RECEIVE7_Disabled (0x0UL)      /*!< Disable                                                              */
49492   #define IPCT_INTEN4_RECEIVE7_Enabled (0x1UL)       /*!< Enable                                                               */
49493 
49494 /* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
49495   #define IPCT_INTEN4_RECEIVE8_Pos (8UL)             /*!< Position of RECEIVE8 field.                                          */
49496   #define IPCT_INTEN4_RECEIVE8_Msk (0x1UL << IPCT_INTEN4_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                        */
49497   #define IPCT_INTEN4_RECEIVE8_Min (0x0UL)           /*!< Min enumerator value of RECEIVE8 field.                              */
49498   #define IPCT_INTEN4_RECEIVE8_Max (0x1UL)           /*!< Max enumerator value of RECEIVE8 field.                              */
49499   #define IPCT_INTEN4_RECEIVE8_Disabled (0x0UL)      /*!< Disable                                                              */
49500   #define IPCT_INTEN4_RECEIVE8_Enabled (0x1UL)       /*!< Enable                                                               */
49501 
49502 /* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
49503   #define IPCT_INTEN4_RECEIVE9_Pos (9UL)             /*!< Position of RECEIVE9 field.                                          */
49504   #define IPCT_INTEN4_RECEIVE9_Msk (0x1UL << IPCT_INTEN4_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                        */
49505   #define IPCT_INTEN4_RECEIVE9_Min (0x0UL)           /*!< Min enumerator value of RECEIVE9 field.                              */
49506   #define IPCT_INTEN4_RECEIVE9_Max (0x1UL)           /*!< Max enumerator value of RECEIVE9 field.                              */
49507   #define IPCT_INTEN4_RECEIVE9_Disabled (0x0UL)      /*!< Disable                                                              */
49508   #define IPCT_INTEN4_RECEIVE9_Enabled (0x1UL)       /*!< Enable                                                               */
49509 
49510 /* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
49511   #define IPCT_INTEN4_RECEIVE10_Pos (10UL)           /*!< Position of RECEIVE10 field.                                         */
49512   #define IPCT_INTEN4_RECEIVE10_Msk (0x1UL << IPCT_INTEN4_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                     */
49513   #define IPCT_INTEN4_RECEIVE10_Min (0x0UL)          /*!< Min enumerator value of RECEIVE10 field.                             */
49514   #define IPCT_INTEN4_RECEIVE10_Max (0x1UL)          /*!< Max enumerator value of RECEIVE10 field.                             */
49515   #define IPCT_INTEN4_RECEIVE10_Disabled (0x0UL)     /*!< Disable                                                              */
49516   #define IPCT_INTEN4_RECEIVE10_Enabled (0x1UL)      /*!< Enable                                                               */
49517 
49518 /* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
49519   #define IPCT_INTEN4_RECEIVE11_Pos (11UL)           /*!< Position of RECEIVE11 field.                                         */
49520   #define IPCT_INTEN4_RECEIVE11_Msk (0x1UL << IPCT_INTEN4_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                     */
49521   #define IPCT_INTEN4_RECEIVE11_Min (0x0UL)          /*!< Min enumerator value of RECEIVE11 field.                             */
49522   #define IPCT_INTEN4_RECEIVE11_Max (0x1UL)          /*!< Max enumerator value of RECEIVE11 field.                             */
49523   #define IPCT_INTEN4_RECEIVE11_Disabled (0x0UL)     /*!< Disable                                                              */
49524   #define IPCT_INTEN4_RECEIVE11_Enabled (0x1UL)      /*!< Enable                                                               */
49525 
49526 /* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
49527   #define IPCT_INTEN4_RECEIVE12_Pos (12UL)           /*!< Position of RECEIVE12 field.                                         */
49528   #define IPCT_INTEN4_RECEIVE12_Msk (0x1UL << IPCT_INTEN4_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                     */
49529   #define IPCT_INTEN4_RECEIVE12_Min (0x0UL)          /*!< Min enumerator value of RECEIVE12 field.                             */
49530   #define IPCT_INTEN4_RECEIVE12_Max (0x1UL)          /*!< Max enumerator value of RECEIVE12 field.                             */
49531   #define IPCT_INTEN4_RECEIVE12_Disabled (0x0UL)     /*!< Disable                                                              */
49532   #define IPCT_INTEN4_RECEIVE12_Enabled (0x1UL)      /*!< Enable                                                               */
49533 
49534 /* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
49535   #define IPCT_INTEN4_RECEIVE13_Pos (13UL)           /*!< Position of RECEIVE13 field.                                         */
49536   #define IPCT_INTEN4_RECEIVE13_Msk (0x1UL << IPCT_INTEN4_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                     */
49537   #define IPCT_INTEN4_RECEIVE13_Min (0x0UL)          /*!< Min enumerator value of RECEIVE13 field.                             */
49538   #define IPCT_INTEN4_RECEIVE13_Max (0x1UL)          /*!< Max enumerator value of RECEIVE13 field.                             */
49539   #define IPCT_INTEN4_RECEIVE13_Disabled (0x0UL)     /*!< Disable                                                              */
49540   #define IPCT_INTEN4_RECEIVE13_Enabled (0x1UL)      /*!< Enable                                                               */
49541 
49542 /* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
49543   #define IPCT_INTEN4_RECEIVE14_Pos (14UL)           /*!< Position of RECEIVE14 field.                                         */
49544   #define IPCT_INTEN4_RECEIVE14_Msk (0x1UL << IPCT_INTEN4_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                     */
49545   #define IPCT_INTEN4_RECEIVE14_Min (0x0UL)          /*!< Min enumerator value of RECEIVE14 field.                             */
49546   #define IPCT_INTEN4_RECEIVE14_Max (0x1UL)          /*!< Max enumerator value of RECEIVE14 field.                             */
49547   #define IPCT_INTEN4_RECEIVE14_Disabled (0x0UL)     /*!< Disable                                                              */
49548   #define IPCT_INTEN4_RECEIVE14_Enabled (0x1UL)      /*!< Enable                                                               */
49549 
49550 /* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
49551   #define IPCT_INTEN4_RECEIVE15_Pos (15UL)           /*!< Position of RECEIVE15 field.                                         */
49552   #define IPCT_INTEN4_RECEIVE15_Msk (0x1UL << IPCT_INTEN4_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                     */
49553   #define IPCT_INTEN4_RECEIVE15_Min (0x0UL)          /*!< Min enumerator value of RECEIVE15 field.                             */
49554   #define IPCT_INTEN4_RECEIVE15_Max (0x1UL)          /*!< Max enumerator value of RECEIVE15 field.                             */
49555   #define IPCT_INTEN4_RECEIVE15_Disabled (0x0UL)     /*!< Disable                                                              */
49556   #define IPCT_INTEN4_RECEIVE15_Enabled (0x1UL)      /*!< Enable                                                               */
49557 
49558 /* ACKED0 @Bit 16 : Enable or disable interrupt for event ACKED[0] */
49559   #define IPCT_INTEN4_ACKED0_Pos (16UL)              /*!< Position of ACKED0 field.                                            */
49560   #define IPCT_INTEN4_ACKED0_Msk (0x1UL << IPCT_INTEN4_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                              */
49561   #define IPCT_INTEN4_ACKED0_Min (0x0UL)             /*!< Min enumerator value of ACKED0 field.                                */
49562   #define IPCT_INTEN4_ACKED0_Max (0x1UL)             /*!< Max enumerator value of ACKED0 field.                                */
49563   #define IPCT_INTEN4_ACKED0_Disabled (0x0UL)        /*!< Disable                                                              */
49564   #define IPCT_INTEN4_ACKED0_Enabled (0x1UL)         /*!< Enable                                                               */
49565 
49566 /* ACKED1 @Bit 17 : Enable or disable interrupt for event ACKED[1] */
49567   #define IPCT_INTEN4_ACKED1_Pos (17UL)              /*!< Position of ACKED1 field.                                            */
49568   #define IPCT_INTEN4_ACKED1_Msk (0x1UL << IPCT_INTEN4_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                              */
49569   #define IPCT_INTEN4_ACKED1_Min (0x0UL)             /*!< Min enumerator value of ACKED1 field.                                */
49570   #define IPCT_INTEN4_ACKED1_Max (0x1UL)             /*!< Max enumerator value of ACKED1 field.                                */
49571   #define IPCT_INTEN4_ACKED1_Disabled (0x0UL)        /*!< Disable                                                              */
49572   #define IPCT_INTEN4_ACKED1_Enabled (0x1UL)         /*!< Enable                                                               */
49573 
49574 /* ACKED2 @Bit 18 : Enable or disable interrupt for event ACKED[2] */
49575   #define IPCT_INTEN4_ACKED2_Pos (18UL)              /*!< Position of ACKED2 field.                                            */
49576   #define IPCT_INTEN4_ACKED2_Msk (0x1UL << IPCT_INTEN4_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                              */
49577   #define IPCT_INTEN4_ACKED2_Min (0x0UL)             /*!< Min enumerator value of ACKED2 field.                                */
49578   #define IPCT_INTEN4_ACKED2_Max (0x1UL)             /*!< Max enumerator value of ACKED2 field.                                */
49579   #define IPCT_INTEN4_ACKED2_Disabled (0x0UL)        /*!< Disable                                                              */
49580   #define IPCT_INTEN4_ACKED2_Enabled (0x1UL)         /*!< Enable                                                               */
49581 
49582 /* ACKED3 @Bit 19 : Enable or disable interrupt for event ACKED[3] */
49583   #define IPCT_INTEN4_ACKED3_Pos (19UL)              /*!< Position of ACKED3 field.                                            */
49584   #define IPCT_INTEN4_ACKED3_Msk (0x1UL << IPCT_INTEN4_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                              */
49585   #define IPCT_INTEN4_ACKED3_Min (0x0UL)             /*!< Min enumerator value of ACKED3 field.                                */
49586   #define IPCT_INTEN4_ACKED3_Max (0x1UL)             /*!< Max enumerator value of ACKED3 field.                                */
49587   #define IPCT_INTEN4_ACKED3_Disabled (0x0UL)        /*!< Disable                                                              */
49588   #define IPCT_INTEN4_ACKED3_Enabled (0x1UL)         /*!< Enable                                                               */
49589 
49590 /* ACKED4 @Bit 20 : Enable or disable interrupt for event ACKED[4] */
49591   #define IPCT_INTEN4_ACKED4_Pos (20UL)              /*!< Position of ACKED4 field.                                            */
49592   #define IPCT_INTEN4_ACKED4_Msk (0x1UL << IPCT_INTEN4_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                              */
49593   #define IPCT_INTEN4_ACKED4_Min (0x0UL)             /*!< Min enumerator value of ACKED4 field.                                */
49594   #define IPCT_INTEN4_ACKED4_Max (0x1UL)             /*!< Max enumerator value of ACKED4 field.                                */
49595   #define IPCT_INTEN4_ACKED4_Disabled (0x0UL)        /*!< Disable                                                              */
49596   #define IPCT_INTEN4_ACKED4_Enabled (0x1UL)         /*!< Enable                                                               */
49597 
49598 /* ACKED5 @Bit 21 : Enable or disable interrupt for event ACKED[5] */
49599   #define IPCT_INTEN4_ACKED5_Pos (21UL)              /*!< Position of ACKED5 field.                                            */
49600   #define IPCT_INTEN4_ACKED5_Msk (0x1UL << IPCT_INTEN4_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                              */
49601   #define IPCT_INTEN4_ACKED5_Min (0x0UL)             /*!< Min enumerator value of ACKED5 field.                                */
49602   #define IPCT_INTEN4_ACKED5_Max (0x1UL)             /*!< Max enumerator value of ACKED5 field.                                */
49603   #define IPCT_INTEN4_ACKED5_Disabled (0x0UL)        /*!< Disable                                                              */
49604   #define IPCT_INTEN4_ACKED5_Enabled (0x1UL)         /*!< Enable                                                               */
49605 
49606 /* ACKED6 @Bit 22 : Enable or disable interrupt for event ACKED[6] */
49607   #define IPCT_INTEN4_ACKED6_Pos (22UL)              /*!< Position of ACKED6 field.                                            */
49608   #define IPCT_INTEN4_ACKED6_Msk (0x1UL << IPCT_INTEN4_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                              */
49609   #define IPCT_INTEN4_ACKED6_Min (0x0UL)             /*!< Min enumerator value of ACKED6 field.                                */
49610   #define IPCT_INTEN4_ACKED6_Max (0x1UL)             /*!< Max enumerator value of ACKED6 field.                                */
49611   #define IPCT_INTEN4_ACKED6_Disabled (0x0UL)        /*!< Disable                                                              */
49612   #define IPCT_INTEN4_ACKED6_Enabled (0x1UL)         /*!< Enable                                                               */
49613 
49614 /* ACKED7 @Bit 23 : Enable or disable interrupt for event ACKED[7] */
49615   #define IPCT_INTEN4_ACKED7_Pos (23UL)              /*!< Position of ACKED7 field.                                            */
49616   #define IPCT_INTEN4_ACKED7_Msk (0x1UL << IPCT_INTEN4_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                              */
49617   #define IPCT_INTEN4_ACKED7_Min (0x0UL)             /*!< Min enumerator value of ACKED7 field.                                */
49618   #define IPCT_INTEN4_ACKED7_Max (0x1UL)             /*!< Max enumerator value of ACKED7 field.                                */
49619   #define IPCT_INTEN4_ACKED7_Disabled (0x0UL)        /*!< Disable                                                              */
49620   #define IPCT_INTEN4_ACKED7_Enabled (0x1UL)         /*!< Enable                                                               */
49621 
49622 /* ACKED8 @Bit 24 : Enable or disable interrupt for event ACKED[8] */
49623   #define IPCT_INTEN4_ACKED8_Pos (24UL)              /*!< Position of ACKED8 field.                                            */
49624   #define IPCT_INTEN4_ACKED8_Msk (0x1UL << IPCT_INTEN4_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                              */
49625   #define IPCT_INTEN4_ACKED8_Min (0x0UL)             /*!< Min enumerator value of ACKED8 field.                                */
49626   #define IPCT_INTEN4_ACKED8_Max (0x1UL)             /*!< Max enumerator value of ACKED8 field.                                */
49627   #define IPCT_INTEN4_ACKED8_Disabled (0x0UL)        /*!< Disable                                                              */
49628   #define IPCT_INTEN4_ACKED8_Enabled (0x1UL)         /*!< Enable                                                               */
49629 
49630 /* ACKED9 @Bit 25 : Enable or disable interrupt for event ACKED[9] */
49631   #define IPCT_INTEN4_ACKED9_Pos (25UL)              /*!< Position of ACKED9 field.                                            */
49632   #define IPCT_INTEN4_ACKED9_Msk (0x1UL << IPCT_INTEN4_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                              */
49633   #define IPCT_INTEN4_ACKED9_Min (0x0UL)             /*!< Min enumerator value of ACKED9 field.                                */
49634   #define IPCT_INTEN4_ACKED9_Max (0x1UL)             /*!< Max enumerator value of ACKED9 field.                                */
49635   #define IPCT_INTEN4_ACKED9_Disabled (0x0UL)        /*!< Disable                                                              */
49636   #define IPCT_INTEN4_ACKED9_Enabled (0x1UL)         /*!< Enable                                                               */
49637 
49638 /* ACKED10 @Bit 26 : Enable or disable interrupt for event ACKED[10] */
49639   #define IPCT_INTEN4_ACKED10_Pos (26UL)             /*!< Position of ACKED10 field.                                           */
49640   #define IPCT_INTEN4_ACKED10_Msk (0x1UL << IPCT_INTEN4_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                           */
49641   #define IPCT_INTEN4_ACKED10_Min (0x0UL)            /*!< Min enumerator value of ACKED10 field.                               */
49642   #define IPCT_INTEN4_ACKED10_Max (0x1UL)            /*!< Max enumerator value of ACKED10 field.                               */
49643   #define IPCT_INTEN4_ACKED10_Disabled (0x0UL)       /*!< Disable                                                              */
49644   #define IPCT_INTEN4_ACKED10_Enabled (0x1UL)        /*!< Enable                                                               */
49645 
49646 /* ACKED11 @Bit 27 : Enable or disable interrupt for event ACKED[11] */
49647   #define IPCT_INTEN4_ACKED11_Pos (27UL)             /*!< Position of ACKED11 field.                                           */
49648   #define IPCT_INTEN4_ACKED11_Msk (0x1UL << IPCT_INTEN4_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                           */
49649   #define IPCT_INTEN4_ACKED11_Min (0x0UL)            /*!< Min enumerator value of ACKED11 field.                               */
49650   #define IPCT_INTEN4_ACKED11_Max (0x1UL)            /*!< Max enumerator value of ACKED11 field.                               */
49651   #define IPCT_INTEN4_ACKED11_Disabled (0x0UL)       /*!< Disable                                                              */
49652   #define IPCT_INTEN4_ACKED11_Enabled (0x1UL)        /*!< Enable                                                               */
49653 
49654 /* ACKED12 @Bit 28 : Enable or disable interrupt for event ACKED[12] */
49655   #define IPCT_INTEN4_ACKED12_Pos (28UL)             /*!< Position of ACKED12 field.                                           */
49656   #define IPCT_INTEN4_ACKED12_Msk (0x1UL << IPCT_INTEN4_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                           */
49657   #define IPCT_INTEN4_ACKED12_Min (0x0UL)            /*!< Min enumerator value of ACKED12 field.                               */
49658   #define IPCT_INTEN4_ACKED12_Max (0x1UL)            /*!< Max enumerator value of ACKED12 field.                               */
49659   #define IPCT_INTEN4_ACKED12_Disabled (0x0UL)       /*!< Disable                                                              */
49660   #define IPCT_INTEN4_ACKED12_Enabled (0x1UL)        /*!< Enable                                                               */
49661 
49662 /* ACKED13 @Bit 29 : Enable or disable interrupt for event ACKED[13] */
49663   #define IPCT_INTEN4_ACKED13_Pos (29UL)             /*!< Position of ACKED13 field.                                           */
49664   #define IPCT_INTEN4_ACKED13_Msk (0x1UL << IPCT_INTEN4_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                           */
49665   #define IPCT_INTEN4_ACKED13_Min (0x0UL)            /*!< Min enumerator value of ACKED13 field.                               */
49666   #define IPCT_INTEN4_ACKED13_Max (0x1UL)            /*!< Max enumerator value of ACKED13 field.                               */
49667   #define IPCT_INTEN4_ACKED13_Disabled (0x0UL)       /*!< Disable                                                              */
49668   #define IPCT_INTEN4_ACKED13_Enabled (0x1UL)        /*!< Enable                                                               */
49669 
49670 /* ACKED14 @Bit 30 : Enable or disable interrupt for event ACKED[14] */
49671   #define IPCT_INTEN4_ACKED14_Pos (30UL)             /*!< Position of ACKED14 field.                                           */
49672   #define IPCT_INTEN4_ACKED14_Msk (0x1UL << IPCT_INTEN4_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                           */
49673   #define IPCT_INTEN4_ACKED14_Min (0x0UL)            /*!< Min enumerator value of ACKED14 field.                               */
49674   #define IPCT_INTEN4_ACKED14_Max (0x1UL)            /*!< Max enumerator value of ACKED14 field.                               */
49675   #define IPCT_INTEN4_ACKED14_Disabled (0x0UL)       /*!< Disable                                                              */
49676   #define IPCT_INTEN4_ACKED14_Enabled (0x1UL)        /*!< Enable                                                               */
49677 
49678 /* ACKED15 @Bit 31 : Enable or disable interrupt for event ACKED[15] */
49679   #define IPCT_INTEN4_ACKED15_Pos (31UL)             /*!< Position of ACKED15 field.                                           */
49680   #define IPCT_INTEN4_ACKED15_Msk (0x1UL << IPCT_INTEN4_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                           */
49681   #define IPCT_INTEN4_ACKED15_Min (0x0UL)            /*!< Min enumerator value of ACKED15 field.                               */
49682   #define IPCT_INTEN4_ACKED15_Max (0x1UL)            /*!< Max enumerator value of ACKED15 field.                               */
49683   #define IPCT_INTEN4_ACKED15_Disabled (0x0UL)       /*!< Disable                                                              */
49684   #define IPCT_INTEN4_ACKED15_Enabled (0x1UL)        /*!< Enable                                                               */
49685 
49686 
49687 /* IPCT_INTENSET4: Enable interrupt */
49688   #define IPCT_INTENSET4_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET4 register.                                   */
49689 
49690 /* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
49691   #define IPCT_INTENSET4_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
49692   #define IPCT_INTENSET4_RECEIVE0_Msk (0x1UL << IPCT_INTENSET4_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
49693   #define IPCT_INTENSET4_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
49694   #define IPCT_INTENSET4_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
49695   #define IPCT_INTENSET4_RECEIVE0_Set (0x1UL)        /*!< Enable                                                               */
49696   #define IPCT_INTENSET4_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49697   #define IPCT_INTENSET4_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49698 
49699 /* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
49700   #define IPCT_INTENSET4_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
49701   #define IPCT_INTENSET4_RECEIVE1_Msk (0x1UL << IPCT_INTENSET4_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
49702   #define IPCT_INTENSET4_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
49703   #define IPCT_INTENSET4_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
49704   #define IPCT_INTENSET4_RECEIVE1_Set (0x1UL)        /*!< Enable                                                               */
49705   #define IPCT_INTENSET4_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49706   #define IPCT_INTENSET4_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49707 
49708 /* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
49709   #define IPCT_INTENSET4_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
49710   #define IPCT_INTENSET4_RECEIVE2_Msk (0x1UL << IPCT_INTENSET4_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
49711   #define IPCT_INTENSET4_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
49712   #define IPCT_INTENSET4_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
49713   #define IPCT_INTENSET4_RECEIVE2_Set (0x1UL)        /*!< Enable                                                               */
49714   #define IPCT_INTENSET4_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49715   #define IPCT_INTENSET4_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49716 
49717 /* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
49718   #define IPCT_INTENSET4_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
49719   #define IPCT_INTENSET4_RECEIVE3_Msk (0x1UL << IPCT_INTENSET4_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
49720   #define IPCT_INTENSET4_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
49721   #define IPCT_INTENSET4_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
49722   #define IPCT_INTENSET4_RECEIVE3_Set (0x1UL)        /*!< Enable                                                               */
49723   #define IPCT_INTENSET4_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49724   #define IPCT_INTENSET4_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49725 
49726 /* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
49727   #define IPCT_INTENSET4_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
49728   #define IPCT_INTENSET4_RECEIVE4_Msk (0x1UL << IPCT_INTENSET4_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
49729   #define IPCT_INTENSET4_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
49730   #define IPCT_INTENSET4_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
49731   #define IPCT_INTENSET4_RECEIVE4_Set (0x1UL)        /*!< Enable                                                               */
49732   #define IPCT_INTENSET4_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49733   #define IPCT_INTENSET4_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49734 
49735 /* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
49736   #define IPCT_INTENSET4_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
49737   #define IPCT_INTENSET4_RECEIVE5_Msk (0x1UL << IPCT_INTENSET4_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
49738   #define IPCT_INTENSET4_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
49739   #define IPCT_INTENSET4_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
49740   #define IPCT_INTENSET4_RECEIVE5_Set (0x1UL)        /*!< Enable                                                               */
49741   #define IPCT_INTENSET4_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49742   #define IPCT_INTENSET4_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49743 
49744 /* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
49745   #define IPCT_INTENSET4_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
49746   #define IPCT_INTENSET4_RECEIVE6_Msk (0x1UL << IPCT_INTENSET4_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
49747   #define IPCT_INTENSET4_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
49748   #define IPCT_INTENSET4_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
49749   #define IPCT_INTENSET4_RECEIVE6_Set (0x1UL)        /*!< Enable                                                               */
49750   #define IPCT_INTENSET4_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49751   #define IPCT_INTENSET4_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49752 
49753 /* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
49754   #define IPCT_INTENSET4_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
49755   #define IPCT_INTENSET4_RECEIVE7_Msk (0x1UL << IPCT_INTENSET4_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
49756   #define IPCT_INTENSET4_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
49757   #define IPCT_INTENSET4_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
49758   #define IPCT_INTENSET4_RECEIVE7_Set (0x1UL)        /*!< Enable                                                               */
49759   #define IPCT_INTENSET4_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49760   #define IPCT_INTENSET4_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49761 
49762 /* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
49763   #define IPCT_INTENSET4_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
49764   #define IPCT_INTENSET4_RECEIVE8_Msk (0x1UL << IPCT_INTENSET4_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
49765   #define IPCT_INTENSET4_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
49766   #define IPCT_INTENSET4_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
49767   #define IPCT_INTENSET4_RECEIVE8_Set (0x1UL)        /*!< Enable                                                               */
49768   #define IPCT_INTENSET4_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49769   #define IPCT_INTENSET4_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49770 
49771 /* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
49772   #define IPCT_INTENSET4_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
49773   #define IPCT_INTENSET4_RECEIVE9_Msk (0x1UL << IPCT_INTENSET4_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
49774   #define IPCT_INTENSET4_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
49775   #define IPCT_INTENSET4_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
49776   #define IPCT_INTENSET4_RECEIVE9_Set (0x1UL)        /*!< Enable                                                               */
49777   #define IPCT_INTENSET4_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49778   #define IPCT_INTENSET4_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49779 
49780 /* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
49781   #define IPCT_INTENSET4_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
49782   #define IPCT_INTENSET4_RECEIVE10_Msk (0x1UL << IPCT_INTENSET4_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
49783   #define IPCT_INTENSET4_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
49784   #define IPCT_INTENSET4_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
49785   #define IPCT_INTENSET4_RECEIVE10_Set (0x1UL)       /*!< Enable                                                               */
49786   #define IPCT_INTENSET4_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49787   #define IPCT_INTENSET4_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49788 
49789 /* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
49790   #define IPCT_INTENSET4_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
49791   #define IPCT_INTENSET4_RECEIVE11_Msk (0x1UL << IPCT_INTENSET4_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
49792   #define IPCT_INTENSET4_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
49793   #define IPCT_INTENSET4_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
49794   #define IPCT_INTENSET4_RECEIVE11_Set (0x1UL)       /*!< Enable                                                               */
49795   #define IPCT_INTENSET4_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49796   #define IPCT_INTENSET4_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49797 
49798 /* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
49799   #define IPCT_INTENSET4_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
49800   #define IPCT_INTENSET4_RECEIVE12_Msk (0x1UL << IPCT_INTENSET4_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
49801   #define IPCT_INTENSET4_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
49802   #define IPCT_INTENSET4_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
49803   #define IPCT_INTENSET4_RECEIVE12_Set (0x1UL)       /*!< Enable                                                               */
49804   #define IPCT_INTENSET4_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49805   #define IPCT_INTENSET4_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49806 
49807 /* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
49808   #define IPCT_INTENSET4_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
49809   #define IPCT_INTENSET4_RECEIVE13_Msk (0x1UL << IPCT_INTENSET4_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
49810   #define IPCT_INTENSET4_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
49811   #define IPCT_INTENSET4_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
49812   #define IPCT_INTENSET4_RECEIVE13_Set (0x1UL)       /*!< Enable                                                               */
49813   #define IPCT_INTENSET4_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49814   #define IPCT_INTENSET4_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49815 
49816 /* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
49817   #define IPCT_INTENSET4_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
49818   #define IPCT_INTENSET4_RECEIVE14_Msk (0x1UL << IPCT_INTENSET4_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
49819   #define IPCT_INTENSET4_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
49820   #define IPCT_INTENSET4_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
49821   #define IPCT_INTENSET4_RECEIVE14_Set (0x1UL)       /*!< Enable                                                               */
49822   #define IPCT_INTENSET4_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49823   #define IPCT_INTENSET4_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49824 
49825 /* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
49826   #define IPCT_INTENSET4_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
49827   #define IPCT_INTENSET4_RECEIVE15_Msk (0x1UL << IPCT_INTENSET4_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
49828   #define IPCT_INTENSET4_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
49829   #define IPCT_INTENSET4_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
49830   #define IPCT_INTENSET4_RECEIVE15_Set (0x1UL)       /*!< Enable                                                               */
49831   #define IPCT_INTENSET4_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
49832   #define IPCT_INTENSET4_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
49833 
49834 /* ACKED0 @Bit 16 : Write '1' to enable interrupt for event ACKED[0] */
49835   #define IPCT_INTENSET4_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
49836   #define IPCT_INTENSET4_ACKED0_Msk (0x1UL << IPCT_INTENSET4_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
49837   #define IPCT_INTENSET4_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
49838   #define IPCT_INTENSET4_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
49839   #define IPCT_INTENSET4_ACKED0_Set (0x1UL)          /*!< Enable                                                               */
49840   #define IPCT_INTENSET4_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49841   #define IPCT_INTENSET4_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49842 
49843 /* ACKED1 @Bit 17 : Write '1' to enable interrupt for event ACKED[1] */
49844   #define IPCT_INTENSET4_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
49845   #define IPCT_INTENSET4_ACKED1_Msk (0x1UL << IPCT_INTENSET4_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
49846   #define IPCT_INTENSET4_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
49847   #define IPCT_INTENSET4_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
49848   #define IPCT_INTENSET4_ACKED1_Set (0x1UL)          /*!< Enable                                                               */
49849   #define IPCT_INTENSET4_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49850   #define IPCT_INTENSET4_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49851 
49852 /* ACKED2 @Bit 18 : Write '1' to enable interrupt for event ACKED[2] */
49853   #define IPCT_INTENSET4_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
49854   #define IPCT_INTENSET4_ACKED2_Msk (0x1UL << IPCT_INTENSET4_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
49855   #define IPCT_INTENSET4_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
49856   #define IPCT_INTENSET4_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
49857   #define IPCT_INTENSET4_ACKED2_Set (0x1UL)          /*!< Enable                                                               */
49858   #define IPCT_INTENSET4_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49859   #define IPCT_INTENSET4_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49860 
49861 /* ACKED3 @Bit 19 : Write '1' to enable interrupt for event ACKED[3] */
49862   #define IPCT_INTENSET4_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
49863   #define IPCT_INTENSET4_ACKED3_Msk (0x1UL << IPCT_INTENSET4_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
49864   #define IPCT_INTENSET4_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
49865   #define IPCT_INTENSET4_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
49866   #define IPCT_INTENSET4_ACKED3_Set (0x1UL)          /*!< Enable                                                               */
49867   #define IPCT_INTENSET4_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49868   #define IPCT_INTENSET4_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49869 
49870 /* ACKED4 @Bit 20 : Write '1' to enable interrupt for event ACKED[4] */
49871   #define IPCT_INTENSET4_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
49872   #define IPCT_INTENSET4_ACKED4_Msk (0x1UL << IPCT_INTENSET4_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
49873   #define IPCT_INTENSET4_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
49874   #define IPCT_INTENSET4_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
49875   #define IPCT_INTENSET4_ACKED4_Set (0x1UL)          /*!< Enable                                                               */
49876   #define IPCT_INTENSET4_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49877   #define IPCT_INTENSET4_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49878 
49879 /* ACKED5 @Bit 21 : Write '1' to enable interrupt for event ACKED[5] */
49880   #define IPCT_INTENSET4_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
49881   #define IPCT_INTENSET4_ACKED5_Msk (0x1UL << IPCT_INTENSET4_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
49882   #define IPCT_INTENSET4_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
49883   #define IPCT_INTENSET4_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
49884   #define IPCT_INTENSET4_ACKED5_Set (0x1UL)          /*!< Enable                                                               */
49885   #define IPCT_INTENSET4_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49886   #define IPCT_INTENSET4_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49887 
49888 /* ACKED6 @Bit 22 : Write '1' to enable interrupt for event ACKED[6] */
49889   #define IPCT_INTENSET4_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
49890   #define IPCT_INTENSET4_ACKED6_Msk (0x1UL << IPCT_INTENSET4_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
49891   #define IPCT_INTENSET4_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
49892   #define IPCT_INTENSET4_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
49893   #define IPCT_INTENSET4_ACKED6_Set (0x1UL)          /*!< Enable                                                               */
49894   #define IPCT_INTENSET4_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49895   #define IPCT_INTENSET4_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49896 
49897 /* ACKED7 @Bit 23 : Write '1' to enable interrupt for event ACKED[7] */
49898   #define IPCT_INTENSET4_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
49899   #define IPCT_INTENSET4_ACKED7_Msk (0x1UL << IPCT_INTENSET4_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
49900   #define IPCT_INTENSET4_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
49901   #define IPCT_INTENSET4_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
49902   #define IPCT_INTENSET4_ACKED7_Set (0x1UL)          /*!< Enable                                                               */
49903   #define IPCT_INTENSET4_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49904   #define IPCT_INTENSET4_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49905 
49906 /* ACKED8 @Bit 24 : Write '1' to enable interrupt for event ACKED[8] */
49907   #define IPCT_INTENSET4_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
49908   #define IPCT_INTENSET4_ACKED8_Msk (0x1UL << IPCT_INTENSET4_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
49909   #define IPCT_INTENSET4_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
49910   #define IPCT_INTENSET4_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
49911   #define IPCT_INTENSET4_ACKED8_Set (0x1UL)          /*!< Enable                                                               */
49912   #define IPCT_INTENSET4_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49913   #define IPCT_INTENSET4_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49914 
49915 /* ACKED9 @Bit 25 : Write '1' to enable interrupt for event ACKED[9] */
49916   #define IPCT_INTENSET4_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
49917   #define IPCT_INTENSET4_ACKED9_Msk (0x1UL << IPCT_INTENSET4_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
49918   #define IPCT_INTENSET4_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
49919   #define IPCT_INTENSET4_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
49920   #define IPCT_INTENSET4_ACKED9_Set (0x1UL)          /*!< Enable                                                               */
49921   #define IPCT_INTENSET4_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
49922   #define IPCT_INTENSET4_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
49923 
49924 /* ACKED10 @Bit 26 : Write '1' to enable interrupt for event ACKED[10] */
49925   #define IPCT_INTENSET4_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
49926   #define IPCT_INTENSET4_ACKED10_Msk (0x1UL << IPCT_INTENSET4_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
49927   #define IPCT_INTENSET4_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
49928   #define IPCT_INTENSET4_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
49929   #define IPCT_INTENSET4_ACKED10_Set (0x1UL)         /*!< Enable                                                               */
49930   #define IPCT_INTENSET4_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49931   #define IPCT_INTENSET4_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49932 
49933 /* ACKED11 @Bit 27 : Write '1' to enable interrupt for event ACKED[11] */
49934   #define IPCT_INTENSET4_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
49935   #define IPCT_INTENSET4_ACKED11_Msk (0x1UL << IPCT_INTENSET4_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
49936   #define IPCT_INTENSET4_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
49937   #define IPCT_INTENSET4_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
49938   #define IPCT_INTENSET4_ACKED11_Set (0x1UL)         /*!< Enable                                                               */
49939   #define IPCT_INTENSET4_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49940   #define IPCT_INTENSET4_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49941 
49942 /* ACKED12 @Bit 28 : Write '1' to enable interrupt for event ACKED[12] */
49943   #define IPCT_INTENSET4_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
49944   #define IPCT_INTENSET4_ACKED12_Msk (0x1UL << IPCT_INTENSET4_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
49945   #define IPCT_INTENSET4_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
49946   #define IPCT_INTENSET4_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
49947   #define IPCT_INTENSET4_ACKED12_Set (0x1UL)         /*!< Enable                                                               */
49948   #define IPCT_INTENSET4_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49949   #define IPCT_INTENSET4_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49950 
49951 /* ACKED13 @Bit 29 : Write '1' to enable interrupt for event ACKED[13] */
49952   #define IPCT_INTENSET4_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
49953   #define IPCT_INTENSET4_ACKED13_Msk (0x1UL << IPCT_INTENSET4_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
49954   #define IPCT_INTENSET4_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
49955   #define IPCT_INTENSET4_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
49956   #define IPCT_INTENSET4_ACKED13_Set (0x1UL)         /*!< Enable                                                               */
49957   #define IPCT_INTENSET4_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49958   #define IPCT_INTENSET4_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49959 
49960 /* ACKED14 @Bit 30 : Write '1' to enable interrupt for event ACKED[14] */
49961   #define IPCT_INTENSET4_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
49962   #define IPCT_INTENSET4_ACKED14_Msk (0x1UL << IPCT_INTENSET4_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
49963   #define IPCT_INTENSET4_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
49964   #define IPCT_INTENSET4_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
49965   #define IPCT_INTENSET4_ACKED14_Set (0x1UL)         /*!< Enable                                                               */
49966   #define IPCT_INTENSET4_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49967   #define IPCT_INTENSET4_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49968 
49969 /* ACKED15 @Bit 31 : Write '1' to enable interrupt for event ACKED[15] */
49970   #define IPCT_INTENSET4_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
49971   #define IPCT_INTENSET4_ACKED15_Msk (0x1UL << IPCT_INTENSET4_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
49972   #define IPCT_INTENSET4_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
49973   #define IPCT_INTENSET4_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
49974   #define IPCT_INTENSET4_ACKED15_Set (0x1UL)         /*!< Enable                                                               */
49975   #define IPCT_INTENSET4_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
49976   #define IPCT_INTENSET4_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
49977 
49978 
49979 /* IPCT_INTENCLR4: Disable interrupt */
49980   #define IPCT_INTENCLR4_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR4 register.                                   */
49981 
49982 /* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
49983   #define IPCT_INTENCLR4_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
49984   #define IPCT_INTENCLR4_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
49985   #define IPCT_INTENCLR4_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
49986   #define IPCT_INTENCLR4_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
49987   #define IPCT_INTENCLR4_RECEIVE0_Clear (0x1UL)      /*!< Disable                                                              */
49988   #define IPCT_INTENCLR4_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49989   #define IPCT_INTENCLR4_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49990 
49991 /* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
49992   #define IPCT_INTENCLR4_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
49993   #define IPCT_INTENCLR4_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
49994   #define IPCT_INTENCLR4_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
49995   #define IPCT_INTENCLR4_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
49996   #define IPCT_INTENCLR4_RECEIVE1_Clear (0x1UL)      /*!< Disable                                                              */
49997   #define IPCT_INTENCLR4_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
49998   #define IPCT_INTENCLR4_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
49999 
50000 /* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
50001   #define IPCT_INTENCLR4_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
50002   #define IPCT_INTENCLR4_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
50003   #define IPCT_INTENCLR4_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
50004   #define IPCT_INTENCLR4_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
50005   #define IPCT_INTENCLR4_RECEIVE2_Clear (0x1UL)      /*!< Disable                                                              */
50006   #define IPCT_INTENCLR4_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50007   #define IPCT_INTENCLR4_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50008 
50009 /* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
50010   #define IPCT_INTENCLR4_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
50011   #define IPCT_INTENCLR4_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
50012   #define IPCT_INTENCLR4_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
50013   #define IPCT_INTENCLR4_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
50014   #define IPCT_INTENCLR4_RECEIVE3_Clear (0x1UL)      /*!< Disable                                                              */
50015   #define IPCT_INTENCLR4_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50016   #define IPCT_INTENCLR4_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50017 
50018 /* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
50019   #define IPCT_INTENCLR4_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
50020   #define IPCT_INTENCLR4_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
50021   #define IPCT_INTENCLR4_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
50022   #define IPCT_INTENCLR4_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
50023   #define IPCT_INTENCLR4_RECEIVE4_Clear (0x1UL)      /*!< Disable                                                              */
50024   #define IPCT_INTENCLR4_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50025   #define IPCT_INTENCLR4_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50026 
50027 /* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
50028   #define IPCT_INTENCLR4_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
50029   #define IPCT_INTENCLR4_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
50030   #define IPCT_INTENCLR4_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
50031   #define IPCT_INTENCLR4_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
50032   #define IPCT_INTENCLR4_RECEIVE5_Clear (0x1UL)      /*!< Disable                                                              */
50033   #define IPCT_INTENCLR4_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50034   #define IPCT_INTENCLR4_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50035 
50036 /* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
50037   #define IPCT_INTENCLR4_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
50038   #define IPCT_INTENCLR4_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
50039   #define IPCT_INTENCLR4_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
50040   #define IPCT_INTENCLR4_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
50041   #define IPCT_INTENCLR4_RECEIVE6_Clear (0x1UL)      /*!< Disable                                                              */
50042   #define IPCT_INTENCLR4_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50043   #define IPCT_INTENCLR4_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50044 
50045 /* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
50046   #define IPCT_INTENCLR4_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
50047   #define IPCT_INTENCLR4_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
50048   #define IPCT_INTENCLR4_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
50049   #define IPCT_INTENCLR4_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
50050   #define IPCT_INTENCLR4_RECEIVE7_Clear (0x1UL)      /*!< Disable                                                              */
50051   #define IPCT_INTENCLR4_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50052   #define IPCT_INTENCLR4_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50053 
50054 /* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
50055   #define IPCT_INTENCLR4_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
50056   #define IPCT_INTENCLR4_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
50057   #define IPCT_INTENCLR4_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
50058   #define IPCT_INTENCLR4_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
50059   #define IPCT_INTENCLR4_RECEIVE8_Clear (0x1UL)      /*!< Disable                                                              */
50060   #define IPCT_INTENCLR4_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50061   #define IPCT_INTENCLR4_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50062 
50063 /* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
50064   #define IPCT_INTENCLR4_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
50065   #define IPCT_INTENCLR4_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
50066   #define IPCT_INTENCLR4_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
50067   #define IPCT_INTENCLR4_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
50068   #define IPCT_INTENCLR4_RECEIVE9_Clear (0x1UL)      /*!< Disable                                                              */
50069   #define IPCT_INTENCLR4_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50070   #define IPCT_INTENCLR4_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50071 
50072 /* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
50073   #define IPCT_INTENCLR4_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
50074   #define IPCT_INTENCLR4_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
50075   #define IPCT_INTENCLR4_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
50076   #define IPCT_INTENCLR4_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
50077   #define IPCT_INTENCLR4_RECEIVE10_Clear (0x1UL)     /*!< Disable                                                              */
50078   #define IPCT_INTENCLR4_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50079   #define IPCT_INTENCLR4_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50080 
50081 /* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
50082   #define IPCT_INTENCLR4_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
50083   #define IPCT_INTENCLR4_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
50084   #define IPCT_INTENCLR4_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
50085   #define IPCT_INTENCLR4_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
50086   #define IPCT_INTENCLR4_RECEIVE11_Clear (0x1UL)     /*!< Disable                                                              */
50087   #define IPCT_INTENCLR4_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50088   #define IPCT_INTENCLR4_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50089 
50090 /* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
50091   #define IPCT_INTENCLR4_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
50092   #define IPCT_INTENCLR4_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
50093   #define IPCT_INTENCLR4_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
50094   #define IPCT_INTENCLR4_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
50095   #define IPCT_INTENCLR4_RECEIVE12_Clear (0x1UL)     /*!< Disable                                                              */
50096   #define IPCT_INTENCLR4_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50097   #define IPCT_INTENCLR4_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50098 
50099 /* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
50100   #define IPCT_INTENCLR4_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
50101   #define IPCT_INTENCLR4_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
50102   #define IPCT_INTENCLR4_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
50103   #define IPCT_INTENCLR4_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
50104   #define IPCT_INTENCLR4_RECEIVE13_Clear (0x1UL)     /*!< Disable                                                              */
50105   #define IPCT_INTENCLR4_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50106   #define IPCT_INTENCLR4_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50107 
50108 /* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
50109   #define IPCT_INTENCLR4_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
50110   #define IPCT_INTENCLR4_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
50111   #define IPCT_INTENCLR4_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
50112   #define IPCT_INTENCLR4_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
50113   #define IPCT_INTENCLR4_RECEIVE14_Clear (0x1UL)     /*!< Disable                                                              */
50114   #define IPCT_INTENCLR4_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50115   #define IPCT_INTENCLR4_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50116 
50117 /* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
50118   #define IPCT_INTENCLR4_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
50119   #define IPCT_INTENCLR4_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR4_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
50120   #define IPCT_INTENCLR4_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
50121   #define IPCT_INTENCLR4_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
50122   #define IPCT_INTENCLR4_RECEIVE15_Clear (0x1UL)     /*!< Disable                                                              */
50123   #define IPCT_INTENCLR4_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50124   #define IPCT_INTENCLR4_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50125 
50126 /* ACKED0 @Bit 16 : Write '1' to disable interrupt for event ACKED[0] */
50127   #define IPCT_INTENCLR4_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
50128   #define IPCT_INTENCLR4_ACKED0_Msk (0x1UL << IPCT_INTENCLR4_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
50129   #define IPCT_INTENCLR4_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
50130   #define IPCT_INTENCLR4_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
50131   #define IPCT_INTENCLR4_ACKED0_Clear (0x1UL)        /*!< Disable                                                              */
50132   #define IPCT_INTENCLR4_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50133   #define IPCT_INTENCLR4_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50134 
50135 /* ACKED1 @Bit 17 : Write '1' to disable interrupt for event ACKED[1] */
50136   #define IPCT_INTENCLR4_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
50137   #define IPCT_INTENCLR4_ACKED1_Msk (0x1UL << IPCT_INTENCLR4_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
50138   #define IPCT_INTENCLR4_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
50139   #define IPCT_INTENCLR4_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
50140   #define IPCT_INTENCLR4_ACKED1_Clear (0x1UL)        /*!< Disable                                                              */
50141   #define IPCT_INTENCLR4_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50142   #define IPCT_INTENCLR4_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50143 
50144 /* ACKED2 @Bit 18 : Write '1' to disable interrupt for event ACKED[2] */
50145   #define IPCT_INTENCLR4_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
50146   #define IPCT_INTENCLR4_ACKED2_Msk (0x1UL << IPCT_INTENCLR4_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
50147   #define IPCT_INTENCLR4_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
50148   #define IPCT_INTENCLR4_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
50149   #define IPCT_INTENCLR4_ACKED2_Clear (0x1UL)        /*!< Disable                                                              */
50150   #define IPCT_INTENCLR4_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50151   #define IPCT_INTENCLR4_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50152 
50153 /* ACKED3 @Bit 19 : Write '1' to disable interrupt for event ACKED[3] */
50154   #define IPCT_INTENCLR4_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
50155   #define IPCT_INTENCLR4_ACKED3_Msk (0x1UL << IPCT_INTENCLR4_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
50156   #define IPCT_INTENCLR4_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
50157   #define IPCT_INTENCLR4_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
50158   #define IPCT_INTENCLR4_ACKED3_Clear (0x1UL)        /*!< Disable                                                              */
50159   #define IPCT_INTENCLR4_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50160   #define IPCT_INTENCLR4_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50161 
50162 /* ACKED4 @Bit 20 : Write '1' to disable interrupt for event ACKED[4] */
50163   #define IPCT_INTENCLR4_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
50164   #define IPCT_INTENCLR4_ACKED4_Msk (0x1UL << IPCT_INTENCLR4_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
50165   #define IPCT_INTENCLR4_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
50166   #define IPCT_INTENCLR4_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
50167   #define IPCT_INTENCLR4_ACKED4_Clear (0x1UL)        /*!< Disable                                                              */
50168   #define IPCT_INTENCLR4_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50169   #define IPCT_INTENCLR4_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50170 
50171 /* ACKED5 @Bit 21 : Write '1' to disable interrupt for event ACKED[5] */
50172   #define IPCT_INTENCLR4_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
50173   #define IPCT_INTENCLR4_ACKED5_Msk (0x1UL << IPCT_INTENCLR4_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
50174   #define IPCT_INTENCLR4_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
50175   #define IPCT_INTENCLR4_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
50176   #define IPCT_INTENCLR4_ACKED5_Clear (0x1UL)        /*!< Disable                                                              */
50177   #define IPCT_INTENCLR4_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50178   #define IPCT_INTENCLR4_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50179 
50180 /* ACKED6 @Bit 22 : Write '1' to disable interrupt for event ACKED[6] */
50181   #define IPCT_INTENCLR4_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
50182   #define IPCT_INTENCLR4_ACKED6_Msk (0x1UL << IPCT_INTENCLR4_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
50183   #define IPCT_INTENCLR4_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
50184   #define IPCT_INTENCLR4_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
50185   #define IPCT_INTENCLR4_ACKED6_Clear (0x1UL)        /*!< Disable                                                              */
50186   #define IPCT_INTENCLR4_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50187   #define IPCT_INTENCLR4_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50188 
50189 /* ACKED7 @Bit 23 : Write '1' to disable interrupt for event ACKED[7] */
50190   #define IPCT_INTENCLR4_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
50191   #define IPCT_INTENCLR4_ACKED7_Msk (0x1UL << IPCT_INTENCLR4_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
50192   #define IPCT_INTENCLR4_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
50193   #define IPCT_INTENCLR4_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
50194   #define IPCT_INTENCLR4_ACKED7_Clear (0x1UL)        /*!< Disable                                                              */
50195   #define IPCT_INTENCLR4_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50196   #define IPCT_INTENCLR4_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50197 
50198 /* ACKED8 @Bit 24 : Write '1' to disable interrupt for event ACKED[8] */
50199   #define IPCT_INTENCLR4_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
50200   #define IPCT_INTENCLR4_ACKED8_Msk (0x1UL << IPCT_INTENCLR4_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
50201   #define IPCT_INTENCLR4_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
50202   #define IPCT_INTENCLR4_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
50203   #define IPCT_INTENCLR4_ACKED8_Clear (0x1UL)        /*!< Disable                                                              */
50204   #define IPCT_INTENCLR4_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50205   #define IPCT_INTENCLR4_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50206 
50207 /* ACKED9 @Bit 25 : Write '1' to disable interrupt for event ACKED[9] */
50208   #define IPCT_INTENCLR4_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
50209   #define IPCT_INTENCLR4_ACKED9_Msk (0x1UL << IPCT_INTENCLR4_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
50210   #define IPCT_INTENCLR4_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
50211   #define IPCT_INTENCLR4_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
50212   #define IPCT_INTENCLR4_ACKED9_Clear (0x1UL)        /*!< Disable                                                              */
50213   #define IPCT_INTENCLR4_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50214   #define IPCT_INTENCLR4_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50215 
50216 /* ACKED10 @Bit 26 : Write '1' to disable interrupt for event ACKED[10] */
50217   #define IPCT_INTENCLR4_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
50218   #define IPCT_INTENCLR4_ACKED10_Msk (0x1UL << IPCT_INTENCLR4_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
50219   #define IPCT_INTENCLR4_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
50220   #define IPCT_INTENCLR4_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
50221   #define IPCT_INTENCLR4_ACKED10_Clear (0x1UL)       /*!< Disable                                                              */
50222   #define IPCT_INTENCLR4_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
50223   #define IPCT_INTENCLR4_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
50224 
50225 /* ACKED11 @Bit 27 : Write '1' to disable interrupt for event ACKED[11] */
50226   #define IPCT_INTENCLR4_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
50227   #define IPCT_INTENCLR4_ACKED11_Msk (0x1UL << IPCT_INTENCLR4_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
50228   #define IPCT_INTENCLR4_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
50229   #define IPCT_INTENCLR4_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
50230   #define IPCT_INTENCLR4_ACKED11_Clear (0x1UL)       /*!< Disable                                                              */
50231   #define IPCT_INTENCLR4_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
50232   #define IPCT_INTENCLR4_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
50233 
50234 /* ACKED12 @Bit 28 : Write '1' to disable interrupt for event ACKED[12] */
50235   #define IPCT_INTENCLR4_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
50236   #define IPCT_INTENCLR4_ACKED12_Msk (0x1UL << IPCT_INTENCLR4_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
50237   #define IPCT_INTENCLR4_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
50238   #define IPCT_INTENCLR4_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
50239   #define IPCT_INTENCLR4_ACKED12_Clear (0x1UL)       /*!< Disable                                                              */
50240   #define IPCT_INTENCLR4_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
50241   #define IPCT_INTENCLR4_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
50242 
50243 /* ACKED13 @Bit 29 : Write '1' to disable interrupt for event ACKED[13] */
50244   #define IPCT_INTENCLR4_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
50245   #define IPCT_INTENCLR4_ACKED13_Msk (0x1UL << IPCT_INTENCLR4_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
50246   #define IPCT_INTENCLR4_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
50247   #define IPCT_INTENCLR4_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
50248   #define IPCT_INTENCLR4_ACKED13_Clear (0x1UL)       /*!< Disable                                                              */
50249   #define IPCT_INTENCLR4_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
50250   #define IPCT_INTENCLR4_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
50251 
50252 /* ACKED14 @Bit 30 : Write '1' to disable interrupt for event ACKED[14] */
50253   #define IPCT_INTENCLR4_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
50254   #define IPCT_INTENCLR4_ACKED14_Msk (0x1UL << IPCT_INTENCLR4_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
50255   #define IPCT_INTENCLR4_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
50256   #define IPCT_INTENCLR4_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
50257   #define IPCT_INTENCLR4_ACKED14_Clear (0x1UL)       /*!< Disable                                                              */
50258   #define IPCT_INTENCLR4_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
50259   #define IPCT_INTENCLR4_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
50260 
50261 /* ACKED15 @Bit 31 : Write '1' to disable interrupt for event ACKED[15] */
50262   #define IPCT_INTENCLR4_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
50263   #define IPCT_INTENCLR4_ACKED15_Msk (0x1UL << IPCT_INTENCLR4_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
50264   #define IPCT_INTENCLR4_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
50265   #define IPCT_INTENCLR4_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
50266   #define IPCT_INTENCLR4_ACKED15_Clear (0x1UL)       /*!< Disable                                                              */
50267   #define IPCT_INTENCLR4_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
50268   #define IPCT_INTENCLR4_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
50269 
50270 
50271 /* IPCT_INTPEND4: Pending interrupts */
50272   #define IPCT_INTPEND4_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND4 register.                                    */
50273 
50274 /* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
50275   #define IPCT_INTPEND4_RECEIVE0_Pos (0UL)           /*!< Position of RECEIVE0 field.                                          */
50276   #define IPCT_INTPEND4_RECEIVE0_Msk (0x1UL << IPCT_INTPEND4_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                    */
50277   #define IPCT_INTPEND4_RECEIVE0_Min (0x0UL)         /*!< Min enumerator value of RECEIVE0 field.                              */
50278   #define IPCT_INTPEND4_RECEIVE0_Max (0x1UL)         /*!< Max enumerator value of RECEIVE0 field.                              */
50279   #define IPCT_INTPEND4_RECEIVE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50280   #define IPCT_INTPEND4_RECEIVE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
50281 
50282 /* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
50283   #define IPCT_INTPEND4_RECEIVE1_Pos (1UL)           /*!< Position of RECEIVE1 field.                                          */
50284   #define IPCT_INTPEND4_RECEIVE1_Msk (0x1UL << IPCT_INTPEND4_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                    */
50285   #define IPCT_INTPEND4_RECEIVE1_Min (0x0UL)         /*!< Min enumerator value of RECEIVE1 field.                              */
50286   #define IPCT_INTPEND4_RECEIVE1_Max (0x1UL)         /*!< Max enumerator value of RECEIVE1 field.                              */
50287   #define IPCT_INTPEND4_RECEIVE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50288   #define IPCT_INTPEND4_RECEIVE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
50289 
50290 /* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
50291   #define IPCT_INTPEND4_RECEIVE2_Pos (2UL)           /*!< Position of RECEIVE2 field.                                          */
50292   #define IPCT_INTPEND4_RECEIVE2_Msk (0x1UL << IPCT_INTPEND4_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                    */
50293   #define IPCT_INTPEND4_RECEIVE2_Min (0x0UL)         /*!< Min enumerator value of RECEIVE2 field.                              */
50294   #define IPCT_INTPEND4_RECEIVE2_Max (0x1UL)         /*!< Max enumerator value of RECEIVE2 field.                              */
50295   #define IPCT_INTPEND4_RECEIVE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50296   #define IPCT_INTPEND4_RECEIVE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
50297 
50298 /* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
50299   #define IPCT_INTPEND4_RECEIVE3_Pos (3UL)           /*!< Position of RECEIVE3 field.                                          */
50300   #define IPCT_INTPEND4_RECEIVE3_Msk (0x1UL << IPCT_INTPEND4_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                    */
50301   #define IPCT_INTPEND4_RECEIVE3_Min (0x0UL)         /*!< Min enumerator value of RECEIVE3 field.                              */
50302   #define IPCT_INTPEND4_RECEIVE3_Max (0x1UL)         /*!< Max enumerator value of RECEIVE3 field.                              */
50303   #define IPCT_INTPEND4_RECEIVE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50304   #define IPCT_INTPEND4_RECEIVE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
50305 
50306 /* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
50307   #define IPCT_INTPEND4_RECEIVE4_Pos (4UL)           /*!< Position of RECEIVE4 field.                                          */
50308   #define IPCT_INTPEND4_RECEIVE4_Msk (0x1UL << IPCT_INTPEND4_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                    */
50309   #define IPCT_INTPEND4_RECEIVE4_Min (0x0UL)         /*!< Min enumerator value of RECEIVE4 field.                              */
50310   #define IPCT_INTPEND4_RECEIVE4_Max (0x1UL)         /*!< Max enumerator value of RECEIVE4 field.                              */
50311   #define IPCT_INTPEND4_RECEIVE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50312   #define IPCT_INTPEND4_RECEIVE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
50313 
50314 /* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
50315   #define IPCT_INTPEND4_RECEIVE5_Pos (5UL)           /*!< Position of RECEIVE5 field.                                          */
50316   #define IPCT_INTPEND4_RECEIVE5_Msk (0x1UL << IPCT_INTPEND4_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                    */
50317   #define IPCT_INTPEND4_RECEIVE5_Min (0x0UL)         /*!< Min enumerator value of RECEIVE5 field.                              */
50318   #define IPCT_INTPEND4_RECEIVE5_Max (0x1UL)         /*!< Max enumerator value of RECEIVE5 field.                              */
50319   #define IPCT_INTPEND4_RECEIVE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50320   #define IPCT_INTPEND4_RECEIVE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
50321 
50322 /* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
50323   #define IPCT_INTPEND4_RECEIVE6_Pos (6UL)           /*!< Position of RECEIVE6 field.                                          */
50324   #define IPCT_INTPEND4_RECEIVE6_Msk (0x1UL << IPCT_INTPEND4_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                    */
50325   #define IPCT_INTPEND4_RECEIVE6_Min (0x0UL)         /*!< Min enumerator value of RECEIVE6 field.                              */
50326   #define IPCT_INTPEND4_RECEIVE6_Max (0x1UL)         /*!< Max enumerator value of RECEIVE6 field.                              */
50327   #define IPCT_INTPEND4_RECEIVE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50328   #define IPCT_INTPEND4_RECEIVE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
50329 
50330 /* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
50331   #define IPCT_INTPEND4_RECEIVE7_Pos (7UL)           /*!< Position of RECEIVE7 field.                                          */
50332   #define IPCT_INTPEND4_RECEIVE7_Msk (0x1UL << IPCT_INTPEND4_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                    */
50333   #define IPCT_INTPEND4_RECEIVE7_Min (0x0UL)         /*!< Min enumerator value of RECEIVE7 field.                              */
50334   #define IPCT_INTPEND4_RECEIVE7_Max (0x1UL)         /*!< Max enumerator value of RECEIVE7 field.                              */
50335   #define IPCT_INTPEND4_RECEIVE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50336   #define IPCT_INTPEND4_RECEIVE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
50337 
50338 /* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
50339   #define IPCT_INTPEND4_RECEIVE8_Pos (8UL)           /*!< Position of RECEIVE8 field.                                          */
50340   #define IPCT_INTPEND4_RECEIVE8_Msk (0x1UL << IPCT_INTPEND4_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                    */
50341   #define IPCT_INTPEND4_RECEIVE8_Min (0x0UL)         /*!< Min enumerator value of RECEIVE8 field.                              */
50342   #define IPCT_INTPEND4_RECEIVE8_Max (0x1UL)         /*!< Max enumerator value of RECEIVE8 field.                              */
50343   #define IPCT_INTPEND4_RECEIVE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50344   #define IPCT_INTPEND4_RECEIVE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
50345 
50346 /* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
50347   #define IPCT_INTPEND4_RECEIVE9_Pos (9UL)           /*!< Position of RECEIVE9 field.                                          */
50348   #define IPCT_INTPEND4_RECEIVE9_Msk (0x1UL << IPCT_INTPEND4_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                    */
50349   #define IPCT_INTPEND4_RECEIVE9_Min (0x0UL)         /*!< Min enumerator value of RECEIVE9 field.                              */
50350   #define IPCT_INTPEND4_RECEIVE9_Max (0x1UL)         /*!< Max enumerator value of RECEIVE9 field.                              */
50351   #define IPCT_INTPEND4_RECEIVE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
50352   #define IPCT_INTPEND4_RECEIVE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
50353 
50354 /* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
50355   #define IPCT_INTPEND4_RECEIVE10_Pos (10UL)         /*!< Position of RECEIVE10 field.                                         */
50356   #define IPCT_INTPEND4_RECEIVE10_Msk (0x1UL << IPCT_INTPEND4_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                 */
50357   #define IPCT_INTPEND4_RECEIVE10_Min (0x0UL)        /*!< Min enumerator value of RECEIVE10 field.                             */
50358   #define IPCT_INTPEND4_RECEIVE10_Max (0x1UL)        /*!< Max enumerator value of RECEIVE10 field.                             */
50359   #define IPCT_INTPEND4_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
50360   #define IPCT_INTPEND4_RECEIVE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
50361 
50362 /* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
50363   #define IPCT_INTPEND4_RECEIVE11_Pos (11UL)         /*!< Position of RECEIVE11 field.                                         */
50364   #define IPCT_INTPEND4_RECEIVE11_Msk (0x1UL << IPCT_INTPEND4_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                 */
50365   #define IPCT_INTPEND4_RECEIVE11_Min (0x0UL)        /*!< Min enumerator value of RECEIVE11 field.                             */
50366   #define IPCT_INTPEND4_RECEIVE11_Max (0x1UL)        /*!< Max enumerator value of RECEIVE11 field.                             */
50367   #define IPCT_INTPEND4_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
50368   #define IPCT_INTPEND4_RECEIVE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
50369 
50370 /* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
50371   #define IPCT_INTPEND4_RECEIVE12_Pos (12UL)         /*!< Position of RECEIVE12 field.                                         */
50372   #define IPCT_INTPEND4_RECEIVE12_Msk (0x1UL << IPCT_INTPEND4_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                 */
50373   #define IPCT_INTPEND4_RECEIVE12_Min (0x0UL)        /*!< Min enumerator value of RECEIVE12 field.                             */
50374   #define IPCT_INTPEND4_RECEIVE12_Max (0x1UL)        /*!< Max enumerator value of RECEIVE12 field.                             */
50375   #define IPCT_INTPEND4_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
50376   #define IPCT_INTPEND4_RECEIVE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
50377 
50378 /* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
50379   #define IPCT_INTPEND4_RECEIVE13_Pos (13UL)         /*!< Position of RECEIVE13 field.                                         */
50380   #define IPCT_INTPEND4_RECEIVE13_Msk (0x1UL << IPCT_INTPEND4_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                 */
50381   #define IPCT_INTPEND4_RECEIVE13_Min (0x0UL)        /*!< Min enumerator value of RECEIVE13 field.                             */
50382   #define IPCT_INTPEND4_RECEIVE13_Max (0x1UL)        /*!< Max enumerator value of RECEIVE13 field.                             */
50383   #define IPCT_INTPEND4_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
50384   #define IPCT_INTPEND4_RECEIVE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
50385 
50386 /* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
50387   #define IPCT_INTPEND4_RECEIVE14_Pos (14UL)         /*!< Position of RECEIVE14 field.                                         */
50388   #define IPCT_INTPEND4_RECEIVE14_Msk (0x1UL << IPCT_INTPEND4_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                 */
50389   #define IPCT_INTPEND4_RECEIVE14_Min (0x0UL)        /*!< Min enumerator value of RECEIVE14 field.                             */
50390   #define IPCT_INTPEND4_RECEIVE14_Max (0x1UL)        /*!< Max enumerator value of RECEIVE14 field.                             */
50391   #define IPCT_INTPEND4_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
50392   #define IPCT_INTPEND4_RECEIVE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
50393 
50394 /* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
50395   #define IPCT_INTPEND4_RECEIVE15_Pos (15UL)         /*!< Position of RECEIVE15 field.                                         */
50396   #define IPCT_INTPEND4_RECEIVE15_Msk (0x1UL << IPCT_INTPEND4_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                 */
50397   #define IPCT_INTPEND4_RECEIVE15_Min (0x0UL)        /*!< Min enumerator value of RECEIVE15 field.                             */
50398   #define IPCT_INTPEND4_RECEIVE15_Max (0x1UL)        /*!< Max enumerator value of RECEIVE15 field.                             */
50399   #define IPCT_INTPEND4_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
50400   #define IPCT_INTPEND4_RECEIVE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
50401 
50402 /* ACKED0 @Bit 16 : Read pending status of interrupt for event ACKED[0] */
50403   #define IPCT_INTPEND4_ACKED0_Pos (16UL)            /*!< Position of ACKED0 field.                                            */
50404   #define IPCT_INTPEND4_ACKED0_Msk (0x1UL << IPCT_INTPEND4_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                          */
50405   #define IPCT_INTPEND4_ACKED0_Min (0x0UL)           /*!< Min enumerator value of ACKED0 field.                                */
50406   #define IPCT_INTPEND4_ACKED0_Max (0x1UL)           /*!< Max enumerator value of ACKED0 field.                                */
50407   #define IPCT_INTPEND4_ACKED0_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50408   #define IPCT_INTPEND4_ACKED0_Pending (0x1UL)       /*!< Read: Pending                                                        */
50409 
50410 /* ACKED1 @Bit 17 : Read pending status of interrupt for event ACKED[1] */
50411   #define IPCT_INTPEND4_ACKED1_Pos (17UL)            /*!< Position of ACKED1 field.                                            */
50412   #define IPCT_INTPEND4_ACKED1_Msk (0x1UL << IPCT_INTPEND4_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                          */
50413   #define IPCT_INTPEND4_ACKED1_Min (0x0UL)           /*!< Min enumerator value of ACKED1 field.                                */
50414   #define IPCT_INTPEND4_ACKED1_Max (0x1UL)           /*!< Max enumerator value of ACKED1 field.                                */
50415   #define IPCT_INTPEND4_ACKED1_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50416   #define IPCT_INTPEND4_ACKED1_Pending (0x1UL)       /*!< Read: Pending                                                        */
50417 
50418 /* ACKED2 @Bit 18 : Read pending status of interrupt for event ACKED[2] */
50419   #define IPCT_INTPEND4_ACKED2_Pos (18UL)            /*!< Position of ACKED2 field.                                            */
50420   #define IPCT_INTPEND4_ACKED2_Msk (0x1UL << IPCT_INTPEND4_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                          */
50421   #define IPCT_INTPEND4_ACKED2_Min (0x0UL)           /*!< Min enumerator value of ACKED2 field.                                */
50422   #define IPCT_INTPEND4_ACKED2_Max (0x1UL)           /*!< Max enumerator value of ACKED2 field.                                */
50423   #define IPCT_INTPEND4_ACKED2_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50424   #define IPCT_INTPEND4_ACKED2_Pending (0x1UL)       /*!< Read: Pending                                                        */
50425 
50426 /* ACKED3 @Bit 19 : Read pending status of interrupt for event ACKED[3] */
50427   #define IPCT_INTPEND4_ACKED3_Pos (19UL)            /*!< Position of ACKED3 field.                                            */
50428   #define IPCT_INTPEND4_ACKED3_Msk (0x1UL << IPCT_INTPEND4_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                          */
50429   #define IPCT_INTPEND4_ACKED3_Min (0x0UL)           /*!< Min enumerator value of ACKED3 field.                                */
50430   #define IPCT_INTPEND4_ACKED3_Max (0x1UL)           /*!< Max enumerator value of ACKED3 field.                                */
50431   #define IPCT_INTPEND4_ACKED3_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50432   #define IPCT_INTPEND4_ACKED3_Pending (0x1UL)       /*!< Read: Pending                                                        */
50433 
50434 /* ACKED4 @Bit 20 : Read pending status of interrupt for event ACKED[4] */
50435   #define IPCT_INTPEND4_ACKED4_Pos (20UL)            /*!< Position of ACKED4 field.                                            */
50436   #define IPCT_INTPEND4_ACKED4_Msk (0x1UL << IPCT_INTPEND4_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                          */
50437   #define IPCT_INTPEND4_ACKED4_Min (0x0UL)           /*!< Min enumerator value of ACKED4 field.                                */
50438   #define IPCT_INTPEND4_ACKED4_Max (0x1UL)           /*!< Max enumerator value of ACKED4 field.                                */
50439   #define IPCT_INTPEND4_ACKED4_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50440   #define IPCT_INTPEND4_ACKED4_Pending (0x1UL)       /*!< Read: Pending                                                        */
50441 
50442 /* ACKED5 @Bit 21 : Read pending status of interrupt for event ACKED[5] */
50443   #define IPCT_INTPEND4_ACKED5_Pos (21UL)            /*!< Position of ACKED5 field.                                            */
50444   #define IPCT_INTPEND4_ACKED5_Msk (0x1UL << IPCT_INTPEND4_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                          */
50445   #define IPCT_INTPEND4_ACKED5_Min (0x0UL)           /*!< Min enumerator value of ACKED5 field.                                */
50446   #define IPCT_INTPEND4_ACKED5_Max (0x1UL)           /*!< Max enumerator value of ACKED5 field.                                */
50447   #define IPCT_INTPEND4_ACKED5_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50448   #define IPCT_INTPEND4_ACKED5_Pending (0x1UL)       /*!< Read: Pending                                                        */
50449 
50450 /* ACKED6 @Bit 22 : Read pending status of interrupt for event ACKED[6] */
50451   #define IPCT_INTPEND4_ACKED6_Pos (22UL)            /*!< Position of ACKED6 field.                                            */
50452   #define IPCT_INTPEND4_ACKED6_Msk (0x1UL << IPCT_INTPEND4_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                          */
50453   #define IPCT_INTPEND4_ACKED6_Min (0x0UL)           /*!< Min enumerator value of ACKED6 field.                                */
50454   #define IPCT_INTPEND4_ACKED6_Max (0x1UL)           /*!< Max enumerator value of ACKED6 field.                                */
50455   #define IPCT_INTPEND4_ACKED6_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50456   #define IPCT_INTPEND4_ACKED6_Pending (0x1UL)       /*!< Read: Pending                                                        */
50457 
50458 /* ACKED7 @Bit 23 : Read pending status of interrupt for event ACKED[7] */
50459   #define IPCT_INTPEND4_ACKED7_Pos (23UL)            /*!< Position of ACKED7 field.                                            */
50460   #define IPCT_INTPEND4_ACKED7_Msk (0x1UL << IPCT_INTPEND4_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                          */
50461   #define IPCT_INTPEND4_ACKED7_Min (0x0UL)           /*!< Min enumerator value of ACKED7 field.                                */
50462   #define IPCT_INTPEND4_ACKED7_Max (0x1UL)           /*!< Max enumerator value of ACKED7 field.                                */
50463   #define IPCT_INTPEND4_ACKED7_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50464   #define IPCT_INTPEND4_ACKED7_Pending (0x1UL)       /*!< Read: Pending                                                        */
50465 
50466 /* ACKED8 @Bit 24 : Read pending status of interrupt for event ACKED[8] */
50467   #define IPCT_INTPEND4_ACKED8_Pos (24UL)            /*!< Position of ACKED8 field.                                            */
50468   #define IPCT_INTPEND4_ACKED8_Msk (0x1UL << IPCT_INTPEND4_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                          */
50469   #define IPCT_INTPEND4_ACKED8_Min (0x0UL)           /*!< Min enumerator value of ACKED8 field.                                */
50470   #define IPCT_INTPEND4_ACKED8_Max (0x1UL)           /*!< Max enumerator value of ACKED8 field.                                */
50471   #define IPCT_INTPEND4_ACKED8_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50472   #define IPCT_INTPEND4_ACKED8_Pending (0x1UL)       /*!< Read: Pending                                                        */
50473 
50474 /* ACKED9 @Bit 25 : Read pending status of interrupt for event ACKED[9] */
50475   #define IPCT_INTPEND4_ACKED9_Pos (25UL)            /*!< Position of ACKED9 field.                                            */
50476   #define IPCT_INTPEND4_ACKED9_Msk (0x1UL << IPCT_INTPEND4_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                          */
50477   #define IPCT_INTPEND4_ACKED9_Min (0x0UL)           /*!< Min enumerator value of ACKED9 field.                                */
50478   #define IPCT_INTPEND4_ACKED9_Max (0x1UL)           /*!< Max enumerator value of ACKED9 field.                                */
50479   #define IPCT_INTPEND4_ACKED9_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
50480   #define IPCT_INTPEND4_ACKED9_Pending (0x1UL)       /*!< Read: Pending                                                        */
50481 
50482 /* ACKED10 @Bit 26 : Read pending status of interrupt for event ACKED[10] */
50483   #define IPCT_INTPEND4_ACKED10_Pos (26UL)           /*!< Position of ACKED10 field.                                           */
50484   #define IPCT_INTPEND4_ACKED10_Msk (0x1UL << IPCT_INTPEND4_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                       */
50485   #define IPCT_INTPEND4_ACKED10_Min (0x0UL)          /*!< Min enumerator value of ACKED10 field.                               */
50486   #define IPCT_INTPEND4_ACKED10_Max (0x1UL)          /*!< Max enumerator value of ACKED10 field.                               */
50487   #define IPCT_INTPEND4_ACKED10_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
50488   #define IPCT_INTPEND4_ACKED10_Pending (0x1UL)      /*!< Read: Pending                                                        */
50489 
50490 /* ACKED11 @Bit 27 : Read pending status of interrupt for event ACKED[11] */
50491   #define IPCT_INTPEND4_ACKED11_Pos (27UL)           /*!< Position of ACKED11 field.                                           */
50492   #define IPCT_INTPEND4_ACKED11_Msk (0x1UL << IPCT_INTPEND4_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                       */
50493   #define IPCT_INTPEND4_ACKED11_Min (0x0UL)          /*!< Min enumerator value of ACKED11 field.                               */
50494   #define IPCT_INTPEND4_ACKED11_Max (0x1UL)          /*!< Max enumerator value of ACKED11 field.                               */
50495   #define IPCT_INTPEND4_ACKED11_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
50496   #define IPCT_INTPEND4_ACKED11_Pending (0x1UL)      /*!< Read: Pending                                                        */
50497 
50498 /* ACKED12 @Bit 28 : Read pending status of interrupt for event ACKED[12] */
50499   #define IPCT_INTPEND4_ACKED12_Pos (28UL)           /*!< Position of ACKED12 field.                                           */
50500   #define IPCT_INTPEND4_ACKED12_Msk (0x1UL << IPCT_INTPEND4_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                       */
50501   #define IPCT_INTPEND4_ACKED12_Min (0x0UL)          /*!< Min enumerator value of ACKED12 field.                               */
50502   #define IPCT_INTPEND4_ACKED12_Max (0x1UL)          /*!< Max enumerator value of ACKED12 field.                               */
50503   #define IPCT_INTPEND4_ACKED12_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
50504   #define IPCT_INTPEND4_ACKED12_Pending (0x1UL)      /*!< Read: Pending                                                        */
50505 
50506 /* ACKED13 @Bit 29 : Read pending status of interrupt for event ACKED[13] */
50507   #define IPCT_INTPEND4_ACKED13_Pos (29UL)           /*!< Position of ACKED13 field.                                           */
50508   #define IPCT_INTPEND4_ACKED13_Msk (0x1UL << IPCT_INTPEND4_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                       */
50509   #define IPCT_INTPEND4_ACKED13_Min (0x0UL)          /*!< Min enumerator value of ACKED13 field.                               */
50510   #define IPCT_INTPEND4_ACKED13_Max (0x1UL)          /*!< Max enumerator value of ACKED13 field.                               */
50511   #define IPCT_INTPEND4_ACKED13_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
50512   #define IPCT_INTPEND4_ACKED13_Pending (0x1UL)      /*!< Read: Pending                                                        */
50513 
50514 /* ACKED14 @Bit 30 : Read pending status of interrupt for event ACKED[14] */
50515   #define IPCT_INTPEND4_ACKED14_Pos (30UL)           /*!< Position of ACKED14 field.                                           */
50516   #define IPCT_INTPEND4_ACKED14_Msk (0x1UL << IPCT_INTPEND4_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                       */
50517   #define IPCT_INTPEND4_ACKED14_Min (0x0UL)          /*!< Min enumerator value of ACKED14 field.                               */
50518   #define IPCT_INTPEND4_ACKED14_Max (0x1UL)          /*!< Max enumerator value of ACKED14 field.                               */
50519   #define IPCT_INTPEND4_ACKED14_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
50520   #define IPCT_INTPEND4_ACKED14_Pending (0x1UL)      /*!< Read: Pending                                                        */
50521 
50522 /* ACKED15 @Bit 31 : Read pending status of interrupt for event ACKED[15] */
50523   #define IPCT_INTPEND4_ACKED15_Pos (31UL)           /*!< Position of ACKED15 field.                                           */
50524   #define IPCT_INTPEND4_ACKED15_Msk (0x1UL << IPCT_INTPEND4_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                       */
50525   #define IPCT_INTPEND4_ACKED15_Min (0x0UL)          /*!< Min enumerator value of ACKED15 field.                               */
50526   #define IPCT_INTPEND4_ACKED15_Max (0x1UL)          /*!< Max enumerator value of ACKED15 field.                               */
50527   #define IPCT_INTPEND4_ACKED15_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
50528   #define IPCT_INTPEND4_ACKED15_Pending (0x1UL)      /*!< Read: Pending                                                        */
50529 
50530 
50531 /* IPCT_INTEN5: Enable or disable interrupt */
50532   #define IPCT_INTEN5_ResetValue (0x00000000UL)      /*!< Reset value of INTEN5 register.                                      */
50533 
50534 /* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
50535   #define IPCT_INTEN5_RECEIVE0_Pos (0UL)             /*!< Position of RECEIVE0 field.                                          */
50536   #define IPCT_INTEN5_RECEIVE0_Msk (0x1UL << IPCT_INTEN5_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                        */
50537   #define IPCT_INTEN5_RECEIVE0_Min (0x0UL)           /*!< Min enumerator value of RECEIVE0 field.                              */
50538   #define IPCT_INTEN5_RECEIVE0_Max (0x1UL)           /*!< Max enumerator value of RECEIVE0 field.                              */
50539   #define IPCT_INTEN5_RECEIVE0_Disabled (0x0UL)      /*!< Disable                                                              */
50540   #define IPCT_INTEN5_RECEIVE0_Enabled (0x1UL)       /*!< Enable                                                               */
50541 
50542 /* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
50543   #define IPCT_INTEN5_RECEIVE1_Pos (1UL)             /*!< Position of RECEIVE1 field.                                          */
50544   #define IPCT_INTEN5_RECEIVE1_Msk (0x1UL << IPCT_INTEN5_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                        */
50545   #define IPCT_INTEN5_RECEIVE1_Min (0x0UL)           /*!< Min enumerator value of RECEIVE1 field.                              */
50546   #define IPCT_INTEN5_RECEIVE1_Max (0x1UL)           /*!< Max enumerator value of RECEIVE1 field.                              */
50547   #define IPCT_INTEN5_RECEIVE1_Disabled (0x0UL)      /*!< Disable                                                              */
50548   #define IPCT_INTEN5_RECEIVE1_Enabled (0x1UL)       /*!< Enable                                                               */
50549 
50550 /* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
50551   #define IPCT_INTEN5_RECEIVE2_Pos (2UL)             /*!< Position of RECEIVE2 field.                                          */
50552   #define IPCT_INTEN5_RECEIVE2_Msk (0x1UL << IPCT_INTEN5_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                        */
50553   #define IPCT_INTEN5_RECEIVE2_Min (0x0UL)           /*!< Min enumerator value of RECEIVE2 field.                              */
50554   #define IPCT_INTEN5_RECEIVE2_Max (0x1UL)           /*!< Max enumerator value of RECEIVE2 field.                              */
50555   #define IPCT_INTEN5_RECEIVE2_Disabled (0x0UL)      /*!< Disable                                                              */
50556   #define IPCT_INTEN5_RECEIVE2_Enabled (0x1UL)       /*!< Enable                                                               */
50557 
50558 /* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
50559   #define IPCT_INTEN5_RECEIVE3_Pos (3UL)             /*!< Position of RECEIVE3 field.                                          */
50560   #define IPCT_INTEN5_RECEIVE3_Msk (0x1UL << IPCT_INTEN5_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                        */
50561   #define IPCT_INTEN5_RECEIVE3_Min (0x0UL)           /*!< Min enumerator value of RECEIVE3 field.                              */
50562   #define IPCT_INTEN5_RECEIVE3_Max (0x1UL)           /*!< Max enumerator value of RECEIVE3 field.                              */
50563   #define IPCT_INTEN5_RECEIVE3_Disabled (0x0UL)      /*!< Disable                                                              */
50564   #define IPCT_INTEN5_RECEIVE3_Enabled (0x1UL)       /*!< Enable                                                               */
50565 
50566 /* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
50567   #define IPCT_INTEN5_RECEIVE4_Pos (4UL)             /*!< Position of RECEIVE4 field.                                          */
50568   #define IPCT_INTEN5_RECEIVE4_Msk (0x1UL << IPCT_INTEN5_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                        */
50569   #define IPCT_INTEN5_RECEIVE4_Min (0x0UL)           /*!< Min enumerator value of RECEIVE4 field.                              */
50570   #define IPCT_INTEN5_RECEIVE4_Max (0x1UL)           /*!< Max enumerator value of RECEIVE4 field.                              */
50571   #define IPCT_INTEN5_RECEIVE4_Disabled (0x0UL)      /*!< Disable                                                              */
50572   #define IPCT_INTEN5_RECEIVE4_Enabled (0x1UL)       /*!< Enable                                                               */
50573 
50574 /* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
50575   #define IPCT_INTEN5_RECEIVE5_Pos (5UL)             /*!< Position of RECEIVE5 field.                                          */
50576   #define IPCT_INTEN5_RECEIVE5_Msk (0x1UL << IPCT_INTEN5_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                        */
50577   #define IPCT_INTEN5_RECEIVE5_Min (0x0UL)           /*!< Min enumerator value of RECEIVE5 field.                              */
50578   #define IPCT_INTEN5_RECEIVE5_Max (0x1UL)           /*!< Max enumerator value of RECEIVE5 field.                              */
50579   #define IPCT_INTEN5_RECEIVE5_Disabled (0x0UL)      /*!< Disable                                                              */
50580   #define IPCT_INTEN5_RECEIVE5_Enabled (0x1UL)       /*!< Enable                                                               */
50581 
50582 /* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
50583   #define IPCT_INTEN5_RECEIVE6_Pos (6UL)             /*!< Position of RECEIVE6 field.                                          */
50584   #define IPCT_INTEN5_RECEIVE6_Msk (0x1UL << IPCT_INTEN5_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                        */
50585   #define IPCT_INTEN5_RECEIVE6_Min (0x0UL)           /*!< Min enumerator value of RECEIVE6 field.                              */
50586   #define IPCT_INTEN5_RECEIVE6_Max (0x1UL)           /*!< Max enumerator value of RECEIVE6 field.                              */
50587   #define IPCT_INTEN5_RECEIVE6_Disabled (0x0UL)      /*!< Disable                                                              */
50588   #define IPCT_INTEN5_RECEIVE6_Enabled (0x1UL)       /*!< Enable                                                               */
50589 
50590 /* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
50591   #define IPCT_INTEN5_RECEIVE7_Pos (7UL)             /*!< Position of RECEIVE7 field.                                          */
50592   #define IPCT_INTEN5_RECEIVE7_Msk (0x1UL << IPCT_INTEN5_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                        */
50593   #define IPCT_INTEN5_RECEIVE7_Min (0x0UL)           /*!< Min enumerator value of RECEIVE7 field.                              */
50594   #define IPCT_INTEN5_RECEIVE7_Max (0x1UL)           /*!< Max enumerator value of RECEIVE7 field.                              */
50595   #define IPCT_INTEN5_RECEIVE7_Disabled (0x0UL)      /*!< Disable                                                              */
50596   #define IPCT_INTEN5_RECEIVE7_Enabled (0x1UL)       /*!< Enable                                                               */
50597 
50598 /* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
50599   #define IPCT_INTEN5_RECEIVE8_Pos (8UL)             /*!< Position of RECEIVE8 field.                                          */
50600   #define IPCT_INTEN5_RECEIVE8_Msk (0x1UL << IPCT_INTEN5_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                        */
50601   #define IPCT_INTEN5_RECEIVE8_Min (0x0UL)           /*!< Min enumerator value of RECEIVE8 field.                              */
50602   #define IPCT_INTEN5_RECEIVE8_Max (0x1UL)           /*!< Max enumerator value of RECEIVE8 field.                              */
50603   #define IPCT_INTEN5_RECEIVE8_Disabled (0x0UL)      /*!< Disable                                                              */
50604   #define IPCT_INTEN5_RECEIVE8_Enabled (0x1UL)       /*!< Enable                                                               */
50605 
50606 /* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
50607   #define IPCT_INTEN5_RECEIVE9_Pos (9UL)             /*!< Position of RECEIVE9 field.                                          */
50608   #define IPCT_INTEN5_RECEIVE9_Msk (0x1UL << IPCT_INTEN5_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                        */
50609   #define IPCT_INTEN5_RECEIVE9_Min (0x0UL)           /*!< Min enumerator value of RECEIVE9 field.                              */
50610   #define IPCT_INTEN5_RECEIVE9_Max (0x1UL)           /*!< Max enumerator value of RECEIVE9 field.                              */
50611   #define IPCT_INTEN5_RECEIVE9_Disabled (0x0UL)      /*!< Disable                                                              */
50612   #define IPCT_INTEN5_RECEIVE9_Enabled (0x1UL)       /*!< Enable                                                               */
50613 
50614 /* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
50615   #define IPCT_INTEN5_RECEIVE10_Pos (10UL)           /*!< Position of RECEIVE10 field.                                         */
50616   #define IPCT_INTEN5_RECEIVE10_Msk (0x1UL << IPCT_INTEN5_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                     */
50617   #define IPCT_INTEN5_RECEIVE10_Min (0x0UL)          /*!< Min enumerator value of RECEIVE10 field.                             */
50618   #define IPCT_INTEN5_RECEIVE10_Max (0x1UL)          /*!< Max enumerator value of RECEIVE10 field.                             */
50619   #define IPCT_INTEN5_RECEIVE10_Disabled (0x0UL)     /*!< Disable                                                              */
50620   #define IPCT_INTEN5_RECEIVE10_Enabled (0x1UL)      /*!< Enable                                                               */
50621 
50622 /* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
50623   #define IPCT_INTEN5_RECEIVE11_Pos (11UL)           /*!< Position of RECEIVE11 field.                                         */
50624   #define IPCT_INTEN5_RECEIVE11_Msk (0x1UL << IPCT_INTEN5_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                     */
50625   #define IPCT_INTEN5_RECEIVE11_Min (0x0UL)          /*!< Min enumerator value of RECEIVE11 field.                             */
50626   #define IPCT_INTEN5_RECEIVE11_Max (0x1UL)          /*!< Max enumerator value of RECEIVE11 field.                             */
50627   #define IPCT_INTEN5_RECEIVE11_Disabled (0x0UL)     /*!< Disable                                                              */
50628   #define IPCT_INTEN5_RECEIVE11_Enabled (0x1UL)      /*!< Enable                                                               */
50629 
50630 /* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
50631   #define IPCT_INTEN5_RECEIVE12_Pos (12UL)           /*!< Position of RECEIVE12 field.                                         */
50632   #define IPCT_INTEN5_RECEIVE12_Msk (0x1UL << IPCT_INTEN5_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                     */
50633   #define IPCT_INTEN5_RECEIVE12_Min (0x0UL)          /*!< Min enumerator value of RECEIVE12 field.                             */
50634   #define IPCT_INTEN5_RECEIVE12_Max (0x1UL)          /*!< Max enumerator value of RECEIVE12 field.                             */
50635   #define IPCT_INTEN5_RECEIVE12_Disabled (0x0UL)     /*!< Disable                                                              */
50636   #define IPCT_INTEN5_RECEIVE12_Enabled (0x1UL)      /*!< Enable                                                               */
50637 
50638 /* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
50639   #define IPCT_INTEN5_RECEIVE13_Pos (13UL)           /*!< Position of RECEIVE13 field.                                         */
50640   #define IPCT_INTEN5_RECEIVE13_Msk (0x1UL << IPCT_INTEN5_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                     */
50641   #define IPCT_INTEN5_RECEIVE13_Min (0x0UL)          /*!< Min enumerator value of RECEIVE13 field.                             */
50642   #define IPCT_INTEN5_RECEIVE13_Max (0x1UL)          /*!< Max enumerator value of RECEIVE13 field.                             */
50643   #define IPCT_INTEN5_RECEIVE13_Disabled (0x0UL)     /*!< Disable                                                              */
50644   #define IPCT_INTEN5_RECEIVE13_Enabled (0x1UL)      /*!< Enable                                                               */
50645 
50646 /* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
50647   #define IPCT_INTEN5_RECEIVE14_Pos (14UL)           /*!< Position of RECEIVE14 field.                                         */
50648   #define IPCT_INTEN5_RECEIVE14_Msk (0x1UL << IPCT_INTEN5_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                     */
50649   #define IPCT_INTEN5_RECEIVE14_Min (0x0UL)          /*!< Min enumerator value of RECEIVE14 field.                             */
50650   #define IPCT_INTEN5_RECEIVE14_Max (0x1UL)          /*!< Max enumerator value of RECEIVE14 field.                             */
50651   #define IPCT_INTEN5_RECEIVE14_Disabled (0x0UL)     /*!< Disable                                                              */
50652   #define IPCT_INTEN5_RECEIVE14_Enabled (0x1UL)      /*!< Enable                                                               */
50653 
50654 /* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
50655   #define IPCT_INTEN5_RECEIVE15_Pos (15UL)           /*!< Position of RECEIVE15 field.                                         */
50656   #define IPCT_INTEN5_RECEIVE15_Msk (0x1UL << IPCT_INTEN5_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                     */
50657   #define IPCT_INTEN5_RECEIVE15_Min (0x0UL)          /*!< Min enumerator value of RECEIVE15 field.                             */
50658   #define IPCT_INTEN5_RECEIVE15_Max (0x1UL)          /*!< Max enumerator value of RECEIVE15 field.                             */
50659   #define IPCT_INTEN5_RECEIVE15_Disabled (0x0UL)     /*!< Disable                                                              */
50660   #define IPCT_INTEN5_RECEIVE15_Enabled (0x1UL)      /*!< Enable                                                               */
50661 
50662 /* ACKED0 @Bit 16 : Enable or disable interrupt for event ACKED[0] */
50663   #define IPCT_INTEN5_ACKED0_Pos (16UL)              /*!< Position of ACKED0 field.                                            */
50664   #define IPCT_INTEN5_ACKED0_Msk (0x1UL << IPCT_INTEN5_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                              */
50665   #define IPCT_INTEN5_ACKED0_Min (0x0UL)             /*!< Min enumerator value of ACKED0 field.                                */
50666   #define IPCT_INTEN5_ACKED0_Max (0x1UL)             /*!< Max enumerator value of ACKED0 field.                                */
50667   #define IPCT_INTEN5_ACKED0_Disabled (0x0UL)        /*!< Disable                                                              */
50668   #define IPCT_INTEN5_ACKED0_Enabled (0x1UL)         /*!< Enable                                                               */
50669 
50670 /* ACKED1 @Bit 17 : Enable or disable interrupt for event ACKED[1] */
50671   #define IPCT_INTEN5_ACKED1_Pos (17UL)              /*!< Position of ACKED1 field.                                            */
50672   #define IPCT_INTEN5_ACKED1_Msk (0x1UL << IPCT_INTEN5_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                              */
50673   #define IPCT_INTEN5_ACKED1_Min (0x0UL)             /*!< Min enumerator value of ACKED1 field.                                */
50674   #define IPCT_INTEN5_ACKED1_Max (0x1UL)             /*!< Max enumerator value of ACKED1 field.                                */
50675   #define IPCT_INTEN5_ACKED1_Disabled (0x0UL)        /*!< Disable                                                              */
50676   #define IPCT_INTEN5_ACKED1_Enabled (0x1UL)         /*!< Enable                                                               */
50677 
50678 /* ACKED2 @Bit 18 : Enable or disable interrupt for event ACKED[2] */
50679   #define IPCT_INTEN5_ACKED2_Pos (18UL)              /*!< Position of ACKED2 field.                                            */
50680   #define IPCT_INTEN5_ACKED2_Msk (0x1UL << IPCT_INTEN5_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                              */
50681   #define IPCT_INTEN5_ACKED2_Min (0x0UL)             /*!< Min enumerator value of ACKED2 field.                                */
50682   #define IPCT_INTEN5_ACKED2_Max (0x1UL)             /*!< Max enumerator value of ACKED2 field.                                */
50683   #define IPCT_INTEN5_ACKED2_Disabled (0x0UL)        /*!< Disable                                                              */
50684   #define IPCT_INTEN5_ACKED2_Enabled (0x1UL)         /*!< Enable                                                               */
50685 
50686 /* ACKED3 @Bit 19 : Enable or disable interrupt for event ACKED[3] */
50687   #define IPCT_INTEN5_ACKED3_Pos (19UL)              /*!< Position of ACKED3 field.                                            */
50688   #define IPCT_INTEN5_ACKED3_Msk (0x1UL << IPCT_INTEN5_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                              */
50689   #define IPCT_INTEN5_ACKED3_Min (0x0UL)             /*!< Min enumerator value of ACKED3 field.                                */
50690   #define IPCT_INTEN5_ACKED3_Max (0x1UL)             /*!< Max enumerator value of ACKED3 field.                                */
50691   #define IPCT_INTEN5_ACKED3_Disabled (0x0UL)        /*!< Disable                                                              */
50692   #define IPCT_INTEN5_ACKED3_Enabled (0x1UL)         /*!< Enable                                                               */
50693 
50694 /* ACKED4 @Bit 20 : Enable or disable interrupt for event ACKED[4] */
50695   #define IPCT_INTEN5_ACKED4_Pos (20UL)              /*!< Position of ACKED4 field.                                            */
50696   #define IPCT_INTEN5_ACKED4_Msk (0x1UL << IPCT_INTEN5_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                              */
50697   #define IPCT_INTEN5_ACKED4_Min (0x0UL)             /*!< Min enumerator value of ACKED4 field.                                */
50698   #define IPCT_INTEN5_ACKED4_Max (0x1UL)             /*!< Max enumerator value of ACKED4 field.                                */
50699   #define IPCT_INTEN5_ACKED4_Disabled (0x0UL)        /*!< Disable                                                              */
50700   #define IPCT_INTEN5_ACKED4_Enabled (0x1UL)         /*!< Enable                                                               */
50701 
50702 /* ACKED5 @Bit 21 : Enable or disable interrupt for event ACKED[5] */
50703   #define IPCT_INTEN5_ACKED5_Pos (21UL)              /*!< Position of ACKED5 field.                                            */
50704   #define IPCT_INTEN5_ACKED5_Msk (0x1UL << IPCT_INTEN5_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                              */
50705   #define IPCT_INTEN5_ACKED5_Min (0x0UL)             /*!< Min enumerator value of ACKED5 field.                                */
50706   #define IPCT_INTEN5_ACKED5_Max (0x1UL)             /*!< Max enumerator value of ACKED5 field.                                */
50707   #define IPCT_INTEN5_ACKED5_Disabled (0x0UL)        /*!< Disable                                                              */
50708   #define IPCT_INTEN5_ACKED5_Enabled (0x1UL)         /*!< Enable                                                               */
50709 
50710 /* ACKED6 @Bit 22 : Enable or disable interrupt for event ACKED[6] */
50711   #define IPCT_INTEN5_ACKED6_Pos (22UL)              /*!< Position of ACKED6 field.                                            */
50712   #define IPCT_INTEN5_ACKED6_Msk (0x1UL << IPCT_INTEN5_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                              */
50713   #define IPCT_INTEN5_ACKED6_Min (0x0UL)             /*!< Min enumerator value of ACKED6 field.                                */
50714   #define IPCT_INTEN5_ACKED6_Max (0x1UL)             /*!< Max enumerator value of ACKED6 field.                                */
50715   #define IPCT_INTEN5_ACKED6_Disabled (0x0UL)        /*!< Disable                                                              */
50716   #define IPCT_INTEN5_ACKED6_Enabled (0x1UL)         /*!< Enable                                                               */
50717 
50718 /* ACKED7 @Bit 23 : Enable or disable interrupt for event ACKED[7] */
50719   #define IPCT_INTEN5_ACKED7_Pos (23UL)              /*!< Position of ACKED7 field.                                            */
50720   #define IPCT_INTEN5_ACKED7_Msk (0x1UL << IPCT_INTEN5_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                              */
50721   #define IPCT_INTEN5_ACKED7_Min (0x0UL)             /*!< Min enumerator value of ACKED7 field.                                */
50722   #define IPCT_INTEN5_ACKED7_Max (0x1UL)             /*!< Max enumerator value of ACKED7 field.                                */
50723   #define IPCT_INTEN5_ACKED7_Disabled (0x0UL)        /*!< Disable                                                              */
50724   #define IPCT_INTEN5_ACKED7_Enabled (0x1UL)         /*!< Enable                                                               */
50725 
50726 /* ACKED8 @Bit 24 : Enable or disable interrupt for event ACKED[8] */
50727   #define IPCT_INTEN5_ACKED8_Pos (24UL)              /*!< Position of ACKED8 field.                                            */
50728   #define IPCT_INTEN5_ACKED8_Msk (0x1UL << IPCT_INTEN5_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                              */
50729   #define IPCT_INTEN5_ACKED8_Min (0x0UL)             /*!< Min enumerator value of ACKED8 field.                                */
50730   #define IPCT_INTEN5_ACKED8_Max (0x1UL)             /*!< Max enumerator value of ACKED8 field.                                */
50731   #define IPCT_INTEN5_ACKED8_Disabled (0x0UL)        /*!< Disable                                                              */
50732   #define IPCT_INTEN5_ACKED8_Enabled (0x1UL)         /*!< Enable                                                               */
50733 
50734 /* ACKED9 @Bit 25 : Enable or disable interrupt for event ACKED[9] */
50735   #define IPCT_INTEN5_ACKED9_Pos (25UL)              /*!< Position of ACKED9 field.                                            */
50736   #define IPCT_INTEN5_ACKED9_Msk (0x1UL << IPCT_INTEN5_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                              */
50737   #define IPCT_INTEN5_ACKED9_Min (0x0UL)             /*!< Min enumerator value of ACKED9 field.                                */
50738   #define IPCT_INTEN5_ACKED9_Max (0x1UL)             /*!< Max enumerator value of ACKED9 field.                                */
50739   #define IPCT_INTEN5_ACKED9_Disabled (0x0UL)        /*!< Disable                                                              */
50740   #define IPCT_INTEN5_ACKED9_Enabled (0x1UL)         /*!< Enable                                                               */
50741 
50742 /* ACKED10 @Bit 26 : Enable or disable interrupt for event ACKED[10] */
50743   #define IPCT_INTEN5_ACKED10_Pos (26UL)             /*!< Position of ACKED10 field.                                           */
50744   #define IPCT_INTEN5_ACKED10_Msk (0x1UL << IPCT_INTEN5_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                           */
50745   #define IPCT_INTEN5_ACKED10_Min (0x0UL)            /*!< Min enumerator value of ACKED10 field.                               */
50746   #define IPCT_INTEN5_ACKED10_Max (0x1UL)            /*!< Max enumerator value of ACKED10 field.                               */
50747   #define IPCT_INTEN5_ACKED10_Disabled (0x0UL)       /*!< Disable                                                              */
50748   #define IPCT_INTEN5_ACKED10_Enabled (0x1UL)        /*!< Enable                                                               */
50749 
50750 /* ACKED11 @Bit 27 : Enable or disable interrupt for event ACKED[11] */
50751   #define IPCT_INTEN5_ACKED11_Pos (27UL)             /*!< Position of ACKED11 field.                                           */
50752   #define IPCT_INTEN5_ACKED11_Msk (0x1UL << IPCT_INTEN5_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                           */
50753   #define IPCT_INTEN5_ACKED11_Min (0x0UL)            /*!< Min enumerator value of ACKED11 field.                               */
50754   #define IPCT_INTEN5_ACKED11_Max (0x1UL)            /*!< Max enumerator value of ACKED11 field.                               */
50755   #define IPCT_INTEN5_ACKED11_Disabled (0x0UL)       /*!< Disable                                                              */
50756   #define IPCT_INTEN5_ACKED11_Enabled (0x1UL)        /*!< Enable                                                               */
50757 
50758 /* ACKED12 @Bit 28 : Enable or disable interrupt for event ACKED[12] */
50759   #define IPCT_INTEN5_ACKED12_Pos (28UL)             /*!< Position of ACKED12 field.                                           */
50760   #define IPCT_INTEN5_ACKED12_Msk (0x1UL << IPCT_INTEN5_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                           */
50761   #define IPCT_INTEN5_ACKED12_Min (0x0UL)            /*!< Min enumerator value of ACKED12 field.                               */
50762   #define IPCT_INTEN5_ACKED12_Max (0x1UL)            /*!< Max enumerator value of ACKED12 field.                               */
50763   #define IPCT_INTEN5_ACKED12_Disabled (0x0UL)       /*!< Disable                                                              */
50764   #define IPCT_INTEN5_ACKED12_Enabled (0x1UL)        /*!< Enable                                                               */
50765 
50766 /* ACKED13 @Bit 29 : Enable or disable interrupt for event ACKED[13] */
50767   #define IPCT_INTEN5_ACKED13_Pos (29UL)             /*!< Position of ACKED13 field.                                           */
50768   #define IPCT_INTEN5_ACKED13_Msk (0x1UL << IPCT_INTEN5_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                           */
50769   #define IPCT_INTEN5_ACKED13_Min (0x0UL)            /*!< Min enumerator value of ACKED13 field.                               */
50770   #define IPCT_INTEN5_ACKED13_Max (0x1UL)            /*!< Max enumerator value of ACKED13 field.                               */
50771   #define IPCT_INTEN5_ACKED13_Disabled (0x0UL)       /*!< Disable                                                              */
50772   #define IPCT_INTEN5_ACKED13_Enabled (0x1UL)        /*!< Enable                                                               */
50773 
50774 /* ACKED14 @Bit 30 : Enable or disable interrupt for event ACKED[14] */
50775   #define IPCT_INTEN5_ACKED14_Pos (30UL)             /*!< Position of ACKED14 field.                                           */
50776   #define IPCT_INTEN5_ACKED14_Msk (0x1UL << IPCT_INTEN5_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                           */
50777   #define IPCT_INTEN5_ACKED14_Min (0x0UL)            /*!< Min enumerator value of ACKED14 field.                               */
50778   #define IPCT_INTEN5_ACKED14_Max (0x1UL)            /*!< Max enumerator value of ACKED14 field.                               */
50779   #define IPCT_INTEN5_ACKED14_Disabled (0x0UL)       /*!< Disable                                                              */
50780   #define IPCT_INTEN5_ACKED14_Enabled (0x1UL)        /*!< Enable                                                               */
50781 
50782 /* ACKED15 @Bit 31 : Enable or disable interrupt for event ACKED[15] */
50783   #define IPCT_INTEN5_ACKED15_Pos (31UL)             /*!< Position of ACKED15 field.                                           */
50784   #define IPCT_INTEN5_ACKED15_Msk (0x1UL << IPCT_INTEN5_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                           */
50785   #define IPCT_INTEN5_ACKED15_Min (0x0UL)            /*!< Min enumerator value of ACKED15 field.                               */
50786   #define IPCT_INTEN5_ACKED15_Max (0x1UL)            /*!< Max enumerator value of ACKED15 field.                               */
50787   #define IPCT_INTEN5_ACKED15_Disabled (0x0UL)       /*!< Disable                                                              */
50788   #define IPCT_INTEN5_ACKED15_Enabled (0x1UL)        /*!< Enable                                                               */
50789 
50790 
50791 /* IPCT_INTENSET5: Enable interrupt */
50792   #define IPCT_INTENSET5_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET5 register.                                   */
50793 
50794 /* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
50795   #define IPCT_INTENSET5_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
50796   #define IPCT_INTENSET5_RECEIVE0_Msk (0x1UL << IPCT_INTENSET5_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
50797   #define IPCT_INTENSET5_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
50798   #define IPCT_INTENSET5_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
50799   #define IPCT_INTENSET5_RECEIVE0_Set (0x1UL)        /*!< Enable                                                               */
50800   #define IPCT_INTENSET5_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50801   #define IPCT_INTENSET5_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50802 
50803 /* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
50804   #define IPCT_INTENSET5_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
50805   #define IPCT_INTENSET5_RECEIVE1_Msk (0x1UL << IPCT_INTENSET5_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
50806   #define IPCT_INTENSET5_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
50807   #define IPCT_INTENSET5_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
50808   #define IPCT_INTENSET5_RECEIVE1_Set (0x1UL)        /*!< Enable                                                               */
50809   #define IPCT_INTENSET5_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50810   #define IPCT_INTENSET5_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50811 
50812 /* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
50813   #define IPCT_INTENSET5_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
50814   #define IPCT_INTENSET5_RECEIVE2_Msk (0x1UL << IPCT_INTENSET5_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
50815   #define IPCT_INTENSET5_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
50816   #define IPCT_INTENSET5_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
50817   #define IPCT_INTENSET5_RECEIVE2_Set (0x1UL)        /*!< Enable                                                               */
50818   #define IPCT_INTENSET5_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50819   #define IPCT_INTENSET5_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50820 
50821 /* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
50822   #define IPCT_INTENSET5_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
50823   #define IPCT_INTENSET5_RECEIVE3_Msk (0x1UL << IPCT_INTENSET5_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
50824   #define IPCT_INTENSET5_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
50825   #define IPCT_INTENSET5_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
50826   #define IPCT_INTENSET5_RECEIVE3_Set (0x1UL)        /*!< Enable                                                               */
50827   #define IPCT_INTENSET5_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50828   #define IPCT_INTENSET5_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50829 
50830 /* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
50831   #define IPCT_INTENSET5_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
50832   #define IPCT_INTENSET5_RECEIVE4_Msk (0x1UL << IPCT_INTENSET5_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
50833   #define IPCT_INTENSET5_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
50834   #define IPCT_INTENSET5_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
50835   #define IPCT_INTENSET5_RECEIVE4_Set (0x1UL)        /*!< Enable                                                               */
50836   #define IPCT_INTENSET5_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50837   #define IPCT_INTENSET5_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50838 
50839 /* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
50840   #define IPCT_INTENSET5_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
50841   #define IPCT_INTENSET5_RECEIVE5_Msk (0x1UL << IPCT_INTENSET5_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
50842   #define IPCT_INTENSET5_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
50843   #define IPCT_INTENSET5_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
50844   #define IPCT_INTENSET5_RECEIVE5_Set (0x1UL)        /*!< Enable                                                               */
50845   #define IPCT_INTENSET5_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50846   #define IPCT_INTENSET5_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50847 
50848 /* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
50849   #define IPCT_INTENSET5_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
50850   #define IPCT_INTENSET5_RECEIVE6_Msk (0x1UL << IPCT_INTENSET5_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
50851   #define IPCT_INTENSET5_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
50852   #define IPCT_INTENSET5_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
50853   #define IPCT_INTENSET5_RECEIVE6_Set (0x1UL)        /*!< Enable                                                               */
50854   #define IPCT_INTENSET5_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50855   #define IPCT_INTENSET5_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50856 
50857 /* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
50858   #define IPCT_INTENSET5_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
50859   #define IPCT_INTENSET5_RECEIVE7_Msk (0x1UL << IPCT_INTENSET5_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
50860   #define IPCT_INTENSET5_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
50861   #define IPCT_INTENSET5_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
50862   #define IPCT_INTENSET5_RECEIVE7_Set (0x1UL)        /*!< Enable                                                               */
50863   #define IPCT_INTENSET5_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50864   #define IPCT_INTENSET5_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50865 
50866 /* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
50867   #define IPCT_INTENSET5_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
50868   #define IPCT_INTENSET5_RECEIVE8_Msk (0x1UL << IPCT_INTENSET5_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
50869   #define IPCT_INTENSET5_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
50870   #define IPCT_INTENSET5_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
50871   #define IPCT_INTENSET5_RECEIVE8_Set (0x1UL)        /*!< Enable                                                               */
50872   #define IPCT_INTENSET5_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50873   #define IPCT_INTENSET5_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50874 
50875 /* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
50876   #define IPCT_INTENSET5_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
50877   #define IPCT_INTENSET5_RECEIVE9_Msk (0x1UL << IPCT_INTENSET5_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
50878   #define IPCT_INTENSET5_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
50879   #define IPCT_INTENSET5_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
50880   #define IPCT_INTENSET5_RECEIVE9_Set (0x1UL)        /*!< Enable                                                               */
50881   #define IPCT_INTENSET5_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
50882   #define IPCT_INTENSET5_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
50883 
50884 /* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
50885   #define IPCT_INTENSET5_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
50886   #define IPCT_INTENSET5_RECEIVE10_Msk (0x1UL << IPCT_INTENSET5_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
50887   #define IPCT_INTENSET5_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
50888   #define IPCT_INTENSET5_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
50889   #define IPCT_INTENSET5_RECEIVE10_Set (0x1UL)       /*!< Enable                                                               */
50890   #define IPCT_INTENSET5_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50891   #define IPCT_INTENSET5_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50892 
50893 /* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
50894   #define IPCT_INTENSET5_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
50895   #define IPCT_INTENSET5_RECEIVE11_Msk (0x1UL << IPCT_INTENSET5_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
50896   #define IPCT_INTENSET5_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
50897   #define IPCT_INTENSET5_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
50898   #define IPCT_INTENSET5_RECEIVE11_Set (0x1UL)       /*!< Enable                                                               */
50899   #define IPCT_INTENSET5_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50900   #define IPCT_INTENSET5_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50901 
50902 /* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
50903   #define IPCT_INTENSET5_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
50904   #define IPCT_INTENSET5_RECEIVE12_Msk (0x1UL << IPCT_INTENSET5_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
50905   #define IPCT_INTENSET5_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
50906   #define IPCT_INTENSET5_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
50907   #define IPCT_INTENSET5_RECEIVE12_Set (0x1UL)       /*!< Enable                                                               */
50908   #define IPCT_INTENSET5_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50909   #define IPCT_INTENSET5_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50910 
50911 /* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
50912   #define IPCT_INTENSET5_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
50913   #define IPCT_INTENSET5_RECEIVE13_Msk (0x1UL << IPCT_INTENSET5_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
50914   #define IPCT_INTENSET5_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
50915   #define IPCT_INTENSET5_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
50916   #define IPCT_INTENSET5_RECEIVE13_Set (0x1UL)       /*!< Enable                                                               */
50917   #define IPCT_INTENSET5_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50918   #define IPCT_INTENSET5_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50919 
50920 /* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
50921   #define IPCT_INTENSET5_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
50922   #define IPCT_INTENSET5_RECEIVE14_Msk (0x1UL << IPCT_INTENSET5_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
50923   #define IPCT_INTENSET5_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
50924   #define IPCT_INTENSET5_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
50925   #define IPCT_INTENSET5_RECEIVE14_Set (0x1UL)       /*!< Enable                                                               */
50926   #define IPCT_INTENSET5_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50927   #define IPCT_INTENSET5_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50928 
50929 /* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
50930   #define IPCT_INTENSET5_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
50931   #define IPCT_INTENSET5_RECEIVE15_Msk (0x1UL << IPCT_INTENSET5_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
50932   #define IPCT_INTENSET5_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
50933   #define IPCT_INTENSET5_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
50934   #define IPCT_INTENSET5_RECEIVE15_Set (0x1UL)       /*!< Enable                                                               */
50935   #define IPCT_INTENSET5_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
50936   #define IPCT_INTENSET5_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
50937 
50938 /* ACKED0 @Bit 16 : Write '1' to enable interrupt for event ACKED[0] */
50939   #define IPCT_INTENSET5_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
50940   #define IPCT_INTENSET5_ACKED0_Msk (0x1UL << IPCT_INTENSET5_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
50941   #define IPCT_INTENSET5_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
50942   #define IPCT_INTENSET5_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
50943   #define IPCT_INTENSET5_ACKED0_Set (0x1UL)          /*!< Enable                                                               */
50944   #define IPCT_INTENSET5_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50945   #define IPCT_INTENSET5_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50946 
50947 /* ACKED1 @Bit 17 : Write '1' to enable interrupt for event ACKED[1] */
50948   #define IPCT_INTENSET5_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
50949   #define IPCT_INTENSET5_ACKED1_Msk (0x1UL << IPCT_INTENSET5_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
50950   #define IPCT_INTENSET5_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
50951   #define IPCT_INTENSET5_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
50952   #define IPCT_INTENSET5_ACKED1_Set (0x1UL)          /*!< Enable                                                               */
50953   #define IPCT_INTENSET5_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50954   #define IPCT_INTENSET5_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50955 
50956 /* ACKED2 @Bit 18 : Write '1' to enable interrupt for event ACKED[2] */
50957   #define IPCT_INTENSET5_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
50958   #define IPCT_INTENSET5_ACKED2_Msk (0x1UL << IPCT_INTENSET5_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
50959   #define IPCT_INTENSET5_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
50960   #define IPCT_INTENSET5_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
50961   #define IPCT_INTENSET5_ACKED2_Set (0x1UL)          /*!< Enable                                                               */
50962   #define IPCT_INTENSET5_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50963   #define IPCT_INTENSET5_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50964 
50965 /* ACKED3 @Bit 19 : Write '1' to enable interrupt for event ACKED[3] */
50966   #define IPCT_INTENSET5_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
50967   #define IPCT_INTENSET5_ACKED3_Msk (0x1UL << IPCT_INTENSET5_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
50968   #define IPCT_INTENSET5_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
50969   #define IPCT_INTENSET5_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
50970   #define IPCT_INTENSET5_ACKED3_Set (0x1UL)          /*!< Enable                                                               */
50971   #define IPCT_INTENSET5_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50972   #define IPCT_INTENSET5_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50973 
50974 /* ACKED4 @Bit 20 : Write '1' to enable interrupt for event ACKED[4] */
50975   #define IPCT_INTENSET5_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
50976   #define IPCT_INTENSET5_ACKED4_Msk (0x1UL << IPCT_INTENSET5_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
50977   #define IPCT_INTENSET5_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
50978   #define IPCT_INTENSET5_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
50979   #define IPCT_INTENSET5_ACKED4_Set (0x1UL)          /*!< Enable                                                               */
50980   #define IPCT_INTENSET5_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50981   #define IPCT_INTENSET5_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50982 
50983 /* ACKED5 @Bit 21 : Write '1' to enable interrupt for event ACKED[5] */
50984   #define IPCT_INTENSET5_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
50985   #define IPCT_INTENSET5_ACKED5_Msk (0x1UL << IPCT_INTENSET5_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
50986   #define IPCT_INTENSET5_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
50987   #define IPCT_INTENSET5_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
50988   #define IPCT_INTENSET5_ACKED5_Set (0x1UL)          /*!< Enable                                                               */
50989   #define IPCT_INTENSET5_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50990   #define IPCT_INTENSET5_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
50991 
50992 /* ACKED6 @Bit 22 : Write '1' to enable interrupt for event ACKED[6] */
50993   #define IPCT_INTENSET5_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
50994   #define IPCT_INTENSET5_ACKED6_Msk (0x1UL << IPCT_INTENSET5_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
50995   #define IPCT_INTENSET5_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
50996   #define IPCT_INTENSET5_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
50997   #define IPCT_INTENSET5_ACKED6_Set (0x1UL)          /*!< Enable                                                               */
50998   #define IPCT_INTENSET5_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
50999   #define IPCT_INTENSET5_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51000 
51001 /* ACKED7 @Bit 23 : Write '1' to enable interrupt for event ACKED[7] */
51002   #define IPCT_INTENSET5_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
51003   #define IPCT_INTENSET5_ACKED7_Msk (0x1UL << IPCT_INTENSET5_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
51004   #define IPCT_INTENSET5_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
51005   #define IPCT_INTENSET5_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
51006   #define IPCT_INTENSET5_ACKED7_Set (0x1UL)          /*!< Enable                                                               */
51007   #define IPCT_INTENSET5_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51008   #define IPCT_INTENSET5_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51009 
51010 /* ACKED8 @Bit 24 : Write '1' to enable interrupt for event ACKED[8] */
51011   #define IPCT_INTENSET5_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
51012   #define IPCT_INTENSET5_ACKED8_Msk (0x1UL << IPCT_INTENSET5_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
51013   #define IPCT_INTENSET5_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
51014   #define IPCT_INTENSET5_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
51015   #define IPCT_INTENSET5_ACKED8_Set (0x1UL)          /*!< Enable                                                               */
51016   #define IPCT_INTENSET5_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51017   #define IPCT_INTENSET5_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51018 
51019 /* ACKED9 @Bit 25 : Write '1' to enable interrupt for event ACKED[9] */
51020   #define IPCT_INTENSET5_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
51021   #define IPCT_INTENSET5_ACKED9_Msk (0x1UL << IPCT_INTENSET5_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
51022   #define IPCT_INTENSET5_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
51023   #define IPCT_INTENSET5_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
51024   #define IPCT_INTENSET5_ACKED9_Set (0x1UL)          /*!< Enable                                                               */
51025   #define IPCT_INTENSET5_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51026   #define IPCT_INTENSET5_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51027 
51028 /* ACKED10 @Bit 26 : Write '1' to enable interrupt for event ACKED[10] */
51029   #define IPCT_INTENSET5_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
51030   #define IPCT_INTENSET5_ACKED10_Msk (0x1UL << IPCT_INTENSET5_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
51031   #define IPCT_INTENSET5_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
51032   #define IPCT_INTENSET5_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
51033   #define IPCT_INTENSET5_ACKED10_Set (0x1UL)         /*!< Enable                                                               */
51034   #define IPCT_INTENSET5_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51035   #define IPCT_INTENSET5_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51036 
51037 /* ACKED11 @Bit 27 : Write '1' to enable interrupt for event ACKED[11] */
51038   #define IPCT_INTENSET5_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
51039   #define IPCT_INTENSET5_ACKED11_Msk (0x1UL << IPCT_INTENSET5_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
51040   #define IPCT_INTENSET5_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
51041   #define IPCT_INTENSET5_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
51042   #define IPCT_INTENSET5_ACKED11_Set (0x1UL)         /*!< Enable                                                               */
51043   #define IPCT_INTENSET5_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51044   #define IPCT_INTENSET5_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51045 
51046 /* ACKED12 @Bit 28 : Write '1' to enable interrupt for event ACKED[12] */
51047   #define IPCT_INTENSET5_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
51048   #define IPCT_INTENSET5_ACKED12_Msk (0x1UL << IPCT_INTENSET5_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
51049   #define IPCT_INTENSET5_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
51050   #define IPCT_INTENSET5_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
51051   #define IPCT_INTENSET5_ACKED12_Set (0x1UL)         /*!< Enable                                                               */
51052   #define IPCT_INTENSET5_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51053   #define IPCT_INTENSET5_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51054 
51055 /* ACKED13 @Bit 29 : Write '1' to enable interrupt for event ACKED[13] */
51056   #define IPCT_INTENSET5_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
51057   #define IPCT_INTENSET5_ACKED13_Msk (0x1UL << IPCT_INTENSET5_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
51058   #define IPCT_INTENSET5_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
51059   #define IPCT_INTENSET5_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
51060   #define IPCT_INTENSET5_ACKED13_Set (0x1UL)         /*!< Enable                                                               */
51061   #define IPCT_INTENSET5_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51062   #define IPCT_INTENSET5_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51063 
51064 /* ACKED14 @Bit 30 : Write '1' to enable interrupt for event ACKED[14] */
51065   #define IPCT_INTENSET5_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
51066   #define IPCT_INTENSET5_ACKED14_Msk (0x1UL << IPCT_INTENSET5_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
51067   #define IPCT_INTENSET5_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
51068   #define IPCT_INTENSET5_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
51069   #define IPCT_INTENSET5_ACKED14_Set (0x1UL)         /*!< Enable                                                               */
51070   #define IPCT_INTENSET5_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51071   #define IPCT_INTENSET5_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51072 
51073 /* ACKED15 @Bit 31 : Write '1' to enable interrupt for event ACKED[15] */
51074   #define IPCT_INTENSET5_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
51075   #define IPCT_INTENSET5_ACKED15_Msk (0x1UL << IPCT_INTENSET5_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
51076   #define IPCT_INTENSET5_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
51077   #define IPCT_INTENSET5_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
51078   #define IPCT_INTENSET5_ACKED15_Set (0x1UL)         /*!< Enable                                                               */
51079   #define IPCT_INTENSET5_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51080   #define IPCT_INTENSET5_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51081 
51082 
51083 /* IPCT_INTENCLR5: Disable interrupt */
51084   #define IPCT_INTENCLR5_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR5 register.                                   */
51085 
51086 /* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
51087   #define IPCT_INTENCLR5_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
51088   #define IPCT_INTENCLR5_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
51089   #define IPCT_INTENCLR5_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
51090   #define IPCT_INTENCLR5_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
51091   #define IPCT_INTENCLR5_RECEIVE0_Clear (0x1UL)      /*!< Disable                                                              */
51092   #define IPCT_INTENCLR5_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51093   #define IPCT_INTENCLR5_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51094 
51095 /* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
51096   #define IPCT_INTENCLR5_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
51097   #define IPCT_INTENCLR5_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
51098   #define IPCT_INTENCLR5_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
51099   #define IPCT_INTENCLR5_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
51100   #define IPCT_INTENCLR5_RECEIVE1_Clear (0x1UL)      /*!< Disable                                                              */
51101   #define IPCT_INTENCLR5_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51102   #define IPCT_INTENCLR5_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51103 
51104 /* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
51105   #define IPCT_INTENCLR5_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
51106   #define IPCT_INTENCLR5_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
51107   #define IPCT_INTENCLR5_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
51108   #define IPCT_INTENCLR5_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
51109   #define IPCT_INTENCLR5_RECEIVE2_Clear (0x1UL)      /*!< Disable                                                              */
51110   #define IPCT_INTENCLR5_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51111   #define IPCT_INTENCLR5_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51112 
51113 /* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
51114   #define IPCT_INTENCLR5_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
51115   #define IPCT_INTENCLR5_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
51116   #define IPCT_INTENCLR5_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
51117   #define IPCT_INTENCLR5_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
51118   #define IPCT_INTENCLR5_RECEIVE3_Clear (0x1UL)      /*!< Disable                                                              */
51119   #define IPCT_INTENCLR5_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51120   #define IPCT_INTENCLR5_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51121 
51122 /* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
51123   #define IPCT_INTENCLR5_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
51124   #define IPCT_INTENCLR5_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
51125   #define IPCT_INTENCLR5_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
51126   #define IPCT_INTENCLR5_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
51127   #define IPCT_INTENCLR5_RECEIVE4_Clear (0x1UL)      /*!< Disable                                                              */
51128   #define IPCT_INTENCLR5_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51129   #define IPCT_INTENCLR5_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51130 
51131 /* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
51132   #define IPCT_INTENCLR5_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
51133   #define IPCT_INTENCLR5_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
51134   #define IPCT_INTENCLR5_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
51135   #define IPCT_INTENCLR5_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
51136   #define IPCT_INTENCLR5_RECEIVE5_Clear (0x1UL)      /*!< Disable                                                              */
51137   #define IPCT_INTENCLR5_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51138   #define IPCT_INTENCLR5_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51139 
51140 /* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
51141   #define IPCT_INTENCLR5_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
51142   #define IPCT_INTENCLR5_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
51143   #define IPCT_INTENCLR5_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
51144   #define IPCT_INTENCLR5_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
51145   #define IPCT_INTENCLR5_RECEIVE6_Clear (0x1UL)      /*!< Disable                                                              */
51146   #define IPCT_INTENCLR5_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51147   #define IPCT_INTENCLR5_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51148 
51149 /* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
51150   #define IPCT_INTENCLR5_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
51151   #define IPCT_INTENCLR5_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
51152   #define IPCT_INTENCLR5_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
51153   #define IPCT_INTENCLR5_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
51154   #define IPCT_INTENCLR5_RECEIVE7_Clear (0x1UL)      /*!< Disable                                                              */
51155   #define IPCT_INTENCLR5_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51156   #define IPCT_INTENCLR5_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51157 
51158 /* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
51159   #define IPCT_INTENCLR5_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
51160   #define IPCT_INTENCLR5_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
51161   #define IPCT_INTENCLR5_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
51162   #define IPCT_INTENCLR5_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
51163   #define IPCT_INTENCLR5_RECEIVE8_Clear (0x1UL)      /*!< Disable                                                              */
51164   #define IPCT_INTENCLR5_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51165   #define IPCT_INTENCLR5_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51166 
51167 /* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
51168   #define IPCT_INTENCLR5_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
51169   #define IPCT_INTENCLR5_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
51170   #define IPCT_INTENCLR5_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
51171   #define IPCT_INTENCLR5_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
51172   #define IPCT_INTENCLR5_RECEIVE9_Clear (0x1UL)      /*!< Disable                                                              */
51173   #define IPCT_INTENCLR5_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51174   #define IPCT_INTENCLR5_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51175 
51176 /* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
51177   #define IPCT_INTENCLR5_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
51178   #define IPCT_INTENCLR5_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
51179   #define IPCT_INTENCLR5_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
51180   #define IPCT_INTENCLR5_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
51181   #define IPCT_INTENCLR5_RECEIVE10_Clear (0x1UL)     /*!< Disable                                                              */
51182   #define IPCT_INTENCLR5_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
51183   #define IPCT_INTENCLR5_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
51184 
51185 /* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
51186   #define IPCT_INTENCLR5_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
51187   #define IPCT_INTENCLR5_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
51188   #define IPCT_INTENCLR5_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
51189   #define IPCT_INTENCLR5_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
51190   #define IPCT_INTENCLR5_RECEIVE11_Clear (0x1UL)     /*!< Disable                                                              */
51191   #define IPCT_INTENCLR5_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
51192   #define IPCT_INTENCLR5_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
51193 
51194 /* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
51195   #define IPCT_INTENCLR5_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
51196   #define IPCT_INTENCLR5_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
51197   #define IPCT_INTENCLR5_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
51198   #define IPCT_INTENCLR5_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
51199   #define IPCT_INTENCLR5_RECEIVE12_Clear (0x1UL)     /*!< Disable                                                              */
51200   #define IPCT_INTENCLR5_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
51201   #define IPCT_INTENCLR5_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
51202 
51203 /* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
51204   #define IPCT_INTENCLR5_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
51205   #define IPCT_INTENCLR5_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
51206   #define IPCT_INTENCLR5_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
51207   #define IPCT_INTENCLR5_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
51208   #define IPCT_INTENCLR5_RECEIVE13_Clear (0x1UL)     /*!< Disable                                                              */
51209   #define IPCT_INTENCLR5_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
51210   #define IPCT_INTENCLR5_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
51211 
51212 /* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
51213   #define IPCT_INTENCLR5_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
51214   #define IPCT_INTENCLR5_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
51215   #define IPCT_INTENCLR5_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
51216   #define IPCT_INTENCLR5_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
51217   #define IPCT_INTENCLR5_RECEIVE14_Clear (0x1UL)     /*!< Disable                                                              */
51218   #define IPCT_INTENCLR5_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
51219   #define IPCT_INTENCLR5_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
51220 
51221 /* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
51222   #define IPCT_INTENCLR5_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
51223   #define IPCT_INTENCLR5_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR5_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
51224   #define IPCT_INTENCLR5_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
51225   #define IPCT_INTENCLR5_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
51226   #define IPCT_INTENCLR5_RECEIVE15_Clear (0x1UL)     /*!< Disable                                                              */
51227   #define IPCT_INTENCLR5_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
51228   #define IPCT_INTENCLR5_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
51229 
51230 /* ACKED0 @Bit 16 : Write '1' to disable interrupt for event ACKED[0] */
51231   #define IPCT_INTENCLR5_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
51232   #define IPCT_INTENCLR5_ACKED0_Msk (0x1UL << IPCT_INTENCLR5_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
51233   #define IPCT_INTENCLR5_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
51234   #define IPCT_INTENCLR5_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
51235   #define IPCT_INTENCLR5_ACKED0_Clear (0x1UL)        /*!< Disable                                                              */
51236   #define IPCT_INTENCLR5_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51237   #define IPCT_INTENCLR5_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51238 
51239 /* ACKED1 @Bit 17 : Write '1' to disable interrupt for event ACKED[1] */
51240   #define IPCT_INTENCLR5_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
51241   #define IPCT_INTENCLR5_ACKED1_Msk (0x1UL << IPCT_INTENCLR5_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
51242   #define IPCT_INTENCLR5_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
51243   #define IPCT_INTENCLR5_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
51244   #define IPCT_INTENCLR5_ACKED1_Clear (0x1UL)        /*!< Disable                                                              */
51245   #define IPCT_INTENCLR5_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51246   #define IPCT_INTENCLR5_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51247 
51248 /* ACKED2 @Bit 18 : Write '1' to disable interrupt for event ACKED[2] */
51249   #define IPCT_INTENCLR5_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
51250   #define IPCT_INTENCLR5_ACKED2_Msk (0x1UL << IPCT_INTENCLR5_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
51251   #define IPCT_INTENCLR5_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
51252   #define IPCT_INTENCLR5_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
51253   #define IPCT_INTENCLR5_ACKED2_Clear (0x1UL)        /*!< Disable                                                              */
51254   #define IPCT_INTENCLR5_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51255   #define IPCT_INTENCLR5_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51256 
51257 /* ACKED3 @Bit 19 : Write '1' to disable interrupt for event ACKED[3] */
51258   #define IPCT_INTENCLR5_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
51259   #define IPCT_INTENCLR5_ACKED3_Msk (0x1UL << IPCT_INTENCLR5_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
51260   #define IPCT_INTENCLR5_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
51261   #define IPCT_INTENCLR5_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
51262   #define IPCT_INTENCLR5_ACKED3_Clear (0x1UL)        /*!< Disable                                                              */
51263   #define IPCT_INTENCLR5_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51264   #define IPCT_INTENCLR5_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51265 
51266 /* ACKED4 @Bit 20 : Write '1' to disable interrupt for event ACKED[4] */
51267   #define IPCT_INTENCLR5_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
51268   #define IPCT_INTENCLR5_ACKED4_Msk (0x1UL << IPCT_INTENCLR5_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
51269   #define IPCT_INTENCLR5_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
51270   #define IPCT_INTENCLR5_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
51271   #define IPCT_INTENCLR5_ACKED4_Clear (0x1UL)        /*!< Disable                                                              */
51272   #define IPCT_INTENCLR5_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51273   #define IPCT_INTENCLR5_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51274 
51275 /* ACKED5 @Bit 21 : Write '1' to disable interrupt for event ACKED[5] */
51276   #define IPCT_INTENCLR5_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
51277   #define IPCT_INTENCLR5_ACKED5_Msk (0x1UL << IPCT_INTENCLR5_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
51278   #define IPCT_INTENCLR5_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
51279   #define IPCT_INTENCLR5_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
51280   #define IPCT_INTENCLR5_ACKED5_Clear (0x1UL)        /*!< Disable                                                              */
51281   #define IPCT_INTENCLR5_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51282   #define IPCT_INTENCLR5_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51283 
51284 /* ACKED6 @Bit 22 : Write '1' to disable interrupt for event ACKED[6] */
51285   #define IPCT_INTENCLR5_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
51286   #define IPCT_INTENCLR5_ACKED6_Msk (0x1UL << IPCT_INTENCLR5_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
51287   #define IPCT_INTENCLR5_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
51288   #define IPCT_INTENCLR5_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
51289   #define IPCT_INTENCLR5_ACKED6_Clear (0x1UL)        /*!< Disable                                                              */
51290   #define IPCT_INTENCLR5_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51291   #define IPCT_INTENCLR5_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51292 
51293 /* ACKED7 @Bit 23 : Write '1' to disable interrupt for event ACKED[7] */
51294   #define IPCT_INTENCLR5_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
51295   #define IPCT_INTENCLR5_ACKED7_Msk (0x1UL << IPCT_INTENCLR5_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
51296   #define IPCT_INTENCLR5_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
51297   #define IPCT_INTENCLR5_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
51298   #define IPCT_INTENCLR5_ACKED7_Clear (0x1UL)        /*!< Disable                                                              */
51299   #define IPCT_INTENCLR5_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51300   #define IPCT_INTENCLR5_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51301 
51302 /* ACKED8 @Bit 24 : Write '1' to disable interrupt for event ACKED[8] */
51303   #define IPCT_INTENCLR5_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
51304   #define IPCT_INTENCLR5_ACKED8_Msk (0x1UL << IPCT_INTENCLR5_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
51305   #define IPCT_INTENCLR5_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
51306   #define IPCT_INTENCLR5_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
51307   #define IPCT_INTENCLR5_ACKED8_Clear (0x1UL)        /*!< Disable                                                              */
51308   #define IPCT_INTENCLR5_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51309   #define IPCT_INTENCLR5_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51310 
51311 /* ACKED9 @Bit 25 : Write '1' to disable interrupt for event ACKED[9] */
51312   #define IPCT_INTENCLR5_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
51313   #define IPCT_INTENCLR5_ACKED9_Msk (0x1UL << IPCT_INTENCLR5_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
51314   #define IPCT_INTENCLR5_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
51315   #define IPCT_INTENCLR5_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
51316   #define IPCT_INTENCLR5_ACKED9_Clear (0x1UL)        /*!< Disable                                                              */
51317   #define IPCT_INTENCLR5_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
51318   #define IPCT_INTENCLR5_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
51319 
51320 /* ACKED10 @Bit 26 : Write '1' to disable interrupt for event ACKED[10] */
51321   #define IPCT_INTENCLR5_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
51322   #define IPCT_INTENCLR5_ACKED10_Msk (0x1UL << IPCT_INTENCLR5_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
51323   #define IPCT_INTENCLR5_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
51324   #define IPCT_INTENCLR5_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
51325   #define IPCT_INTENCLR5_ACKED10_Clear (0x1UL)       /*!< Disable                                                              */
51326   #define IPCT_INTENCLR5_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51327   #define IPCT_INTENCLR5_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51328 
51329 /* ACKED11 @Bit 27 : Write '1' to disable interrupt for event ACKED[11] */
51330   #define IPCT_INTENCLR5_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
51331   #define IPCT_INTENCLR5_ACKED11_Msk (0x1UL << IPCT_INTENCLR5_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
51332   #define IPCT_INTENCLR5_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
51333   #define IPCT_INTENCLR5_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
51334   #define IPCT_INTENCLR5_ACKED11_Clear (0x1UL)       /*!< Disable                                                              */
51335   #define IPCT_INTENCLR5_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51336   #define IPCT_INTENCLR5_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51337 
51338 /* ACKED12 @Bit 28 : Write '1' to disable interrupt for event ACKED[12] */
51339   #define IPCT_INTENCLR5_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
51340   #define IPCT_INTENCLR5_ACKED12_Msk (0x1UL << IPCT_INTENCLR5_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
51341   #define IPCT_INTENCLR5_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
51342   #define IPCT_INTENCLR5_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
51343   #define IPCT_INTENCLR5_ACKED12_Clear (0x1UL)       /*!< Disable                                                              */
51344   #define IPCT_INTENCLR5_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51345   #define IPCT_INTENCLR5_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51346 
51347 /* ACKED13 @Bit 29 : Write '1' to disable interrupt for event ACKED[13] */
51348   #define IPCT_INTENCLR5_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
51349   #define IPCT_INTENCLR5_ACKED13_Msk (0x1UL << IPCT_INTENCLR5_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
51350   #define IPCT_INTENCLR5_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
51351   #define IPCT_INTENCLR5_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
51352   #define IPCT_INTENCLR5_ACKED13_Clear (0x1UL)       /*!< Disable                                                              */
51353   #define IPCT_INTENCLR5_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51354   #define IPCT_INTENCLR5_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51355 
51356 /* ACKED14 @Bit 30 : Write '1' to disable interrupt for event ACKED[14] */
51357   #define IPCT_INTENCLR5_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
51358   #define IPCT_INTENCLR5_ACKED14_Msk (0x1UL << IPCT_INTENCLR5_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
51359   #define IPCT_INTENCLR5_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
51360   #define IPCT_INTENCLR5_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
51361   #define IPCT_INTENCLR5_ACKED14_Clear (0x1UL)       /*!< Disable                                                              */
51362   #define IPCT_INTENCLR5_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51363   #define IPCT_INTENCLR5_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51364 
51365 /* ACKED15 @Bit 31 : Write '1' to disable interrupt for event ACKED[15] */
51366   #define IPCT_INTENCLR5_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
51367   #define IPCT_INTENCLR5_ACKED15_Msk (0x1UL << IPCT_INTENCLR5_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
51368   #define IPCT_INTENCLR5_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
51369   #define IPCT_INTENCLR5_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
51370   #define IPCT_INTENCLR5_ACKED15_Clear (0x1UL)       /*!< Disable                                                              */
51371   #define IPCT_INTENCLR5_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
51372   #define IPCT_INTENCLR5_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
51373 
51374 
51375 /* IPCT_INTPEND5: Pending interrupts */
51376   #define IPCT_INTPEND5_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND5 register.                                    */
51377 
51378 /* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
51379   #define IPCT_INTPEND5_RECEIVE0_Pos (0UL)           /*!< Position of RECEIVE0 field.                                          */
51380   #define IPCT_INTPEND5_RECEIVE0_Msk (0x1UL << IPCT_INTPEND5_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                    */
51381   #define IPCT_INTPEND5_RECEIVE0_Min (0x0UL)         /*!< Min enumerator value of RECEIVE0 field.                              */
51382   #define IPCT_INTPEND5_RECEIVE0_Max (0x1UL)         /*!< Max enumerator value of RECEIVE0 field.                              */
51383   #define IPCT_INTPEND5_RECEIVE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51384   #define IPCT_INTPEND5_RECEIVE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
51385 
51386 /* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
51387   #define IPCT_INTPEND5_RECEIVE1_Pos (1UL)           /*!< Position of RECEIVE1 field.                                          */
51388   #define IPCT_INTPEND5_RECEIVE1_Msk (0x1UL << IPCT_INTPEND5_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                    */
51389   #define IPCT_INTPEND5_RECEIVE1_Min (0x0UL)         /*!< Min enumerator value of RECEIVE1 field.                              */
51390   #define IPCT_INTPEND5_RECEIVE1_Max (0x1UL)         /*!< Max enumerator value of RECEIVE1 field.                              */
51391   #define IPCT_INTPEND5_RECEIVE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51392   #define IPCT_INTPEND5_RECEIVE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
51393 
51394 /* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
51395   #define IPCT_INTPEND5_RECEIVE2_Pos (2UL)           /*!< Position of RECEIVE2 field.                                          */
51396   #define IPCT_INTPEND5_RECEIVE2_Msk (0x1UL << IPCT_INTPEND5_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                    */
51397   #define IPCT_INTPEND5_RECEIVE2_Min (0x0UL)         /*!< Min enumerator value of RECEIVE2 field.                              */
51398   #define IPCT_INTPEND5_RECEIVE2_Max (0x1UL)         /*!< Max enumerator value of RECEIVE2 field.                              */
51399   #define IPCT_INTPEND5_RECEIVE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51400   #define IPCT_INTPEND5_RECEIVE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
51401 
51402 /* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
51403   #define IPCT_INTPEND5_RECEIVE3_Pos (3UL)           /*!< Position of RECEIVE3 field.                                          */
51404   #define IPCT_INTPEND5_RECEIVE3_Msk (0x1UL << IPCT_INTPEND5_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                    */
51405   #define IPCT_INTPEND5_RECEIVE3_Min (0x0UL)         /*!< Min enumerator value of RECEIVE3 field.                              */
51406   #define IPCT_INTPEND5_RECEIVE3_Max (0x1UL)         /*!< Max enumerator value of RECEIVE3 field.                              */
51407   #define IPCT_INTPEND5_RECEIVE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51408   #define IPCT_INTPEND5_RECEIVE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
51409 
51410 /* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
51411   #define IPCT_INTPEND5_RECEIVE4_Pos (4UL)           /*!< Position of RECEIVE4 field.                                          */
51412   #define IPCT_INTPEND5_RECEIVE4_Msk (0x1UL << IPCT_INTPEND5_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                    */
51413   #define IPCT_INTPEND5_RECEIVE4_Min (0x0UL)         /*!< Min enumerator value of RECEIVE4 field.                              */
51414   #define IPCT_INTPEND5_RECEIVE4_Max (0x1UL)         /*!< Max enumerator value of RECEIVE4 field.                              */
51415   #define IPCT_INTPEND5_RECEIVE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51416   #define IPCT_INTPEND5_RECEIVE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
51417 
51418 /* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
51419   #define IPCT_INTPEND5_RECEIVE5_Pos (5UL)           /*!< Position of RECEIVE5 field.                                          */
51420   #define IPCT_INTPEND5_RECEIVE5_Msk (0x1UL << IPCT_INTPEND5_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                    */
51421   #define IPCT_INTPEND5_RECEIVE5_Min (0x0UL)         /*!< Min enumerator value of RECEIVE5 field.                              */
51422   #define IPCT_INTPEND5_RECEIVE5_Max (0x1UL)         /*!< Max enumerator value of RECEIVE5 field.                              */
51423   #define IPCT_INTPEND5_RECEIVE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51424   #define IPCT_INTPEND5_RECEIVE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
51425 
51426 /* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
51427   #define IPCT_INTPEND5_RECEIVE6_Pos (6UL)           /*!< Position of RECEIVE6 field.                                          */
51428   #define IPCT_INTPEND5_RECEIVE6_Msk (0x1UL << IPCT_INTPEND5_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                    */
51429   #define IPCT_INTPEND5_RECEIVE6_Min (0x0UL)         /*!< Min enumerator value of RECEIVE6 field.                              */
51430   #define IPCT_INTPEND5_RECEIVE6_Max (0x1UL)         /*!< Max enumerator value of RECEIVE6 field.                              */
51431   #define IPCT_INTPEND5_RECEIVE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51432   #define IPCT_INTPEND5_RECEIVE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
51433 
51434 /* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
51435   #define IPCT_INTPEND5_RECEIVE7_Pos (7UL)           /*!< Position of RECEIVE7 field.                                          */
51436   #define IPCT_INTPEND5_RECEIVE7_Msk (0x1UL << IPCT_INTPEND5_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                    */
51437   #define IPCT_INTPEND5_RECEIVE7_Min (0x0UL)         /*!< Min enumerator value of RECEIVE7 field.                              */
51438   #define IPCT_INTPEND5_RECEIVE7_Max (0x1UL)         /*!< Max enumerator value of RECEIVE7 field.                              */
51439   #define IPCT_INTPEND5_RECEIVE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51440   #define IPCT_INTPEND5_RECEIVE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
51441 
51442 /* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
51443   #define IPCT_INTPEND5_RECEIVE8_Pos (8UL)           /*!< Position of RECEIVE8 field.                                          */
51444   #define IPCT_INTPEND5_RECEIVE8_Msk (0x1UL << IPCT_INTPEND5_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                    */
51445   #define IPCT_INTPEND5_RECEIVE8_Min (0x0UL)         /*!< Min enumerator value of RECEIVE8 field.                              */
51446   #define IPCT_INTPEND5_RECEIVE8_Max (0x1UL)         /*!< Max enumerator value of RECEIVE8 field.                              */
51447   #define IPCT_INTPEND5_RECEIVE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51448   #define IPCT_INTPEND5_RECEIVE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
51449 
51450 /* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
51451   #define IPCT_INTPEND5_RECEIVE9_Pos (9UL)           /*!< Position of RECEIVE9 field.                                          */
51452   #define IPCT_INTPEND5_RECEIVE9_Msk (0x1UL << IPCT_INTPEND5_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                    */
51453   #define IPCT_INTPEND5_RECEIVE9_Min (0x0UL)         /*!< Min enumerator value of RECEIVE9 field.                              */
51454   #define IPCT_INTPEND5_RECEIVE9_Max (0x1UL)         /*!< Max enumerator value of RECEIVE9 field.                              */
51455   #define IPCT_INTPEND5_RECEIVE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
51456   #define IPCT_INTPEND5_RECEIVE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
51457 
51458 /* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
51459   #define IPCT_INTPEND5_RECEIVE10_Pos (10UL)         /*!< Position of RECEIVE10 field.                                         */
51460   #define IPCT_INTPEND5_RECEIVE10_Msk (0x1UL << IPCT_INTPEND5_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                 */
51461   #define IPCT_INTPEND5_RECEIVE10_Min (0x0UL)        /*!< Min enumerator value of RECEIVE10 field.                             */
51462   #define IPCT_INTPEND5_RECEIVE10_Max (0x1UL)        /*!< Max enumerator value of RECEIVE10 field.                             */
51463   #define IPCT_INTPEND5_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
51464   #define IPCT_INTPEND5_RECEIVE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
51465 
51466 /* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
51467   #define IPCT_INTPEND5_RECEIVE11_Pos (11UL)         /*!< Position of RECEIVE11 field.                                         */
51468   #define IPCT_INTPEND5_RECEIVE11_Msk (0x1UL << IPCT_INTPEND5_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                 */
51469   #define IPCT_INTPEND5_RECEIVE11_Min (0x0UL)        /*!< Min enumerator value of RECEIVE11 field.                             */
51470   #define IPCT_INTPEND5_RECEIVE11_Max (0x1UL)        /*!< Max enumerator value of RECEIVE11 field.                             */
51471   #define IPCT_INTPEND5_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
51472   #define IPCT_INTPEND5_RECEIVE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
51473 
51474 /* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
51475   #define IPCT_INTPEND5_RECEIVE12_Pos (12UL)         /*!< Position of RECEIVE12 field.                                         */
51476   #define IPCT_INTPEND5_RECEIVE12_Msk (0x1UL << IPCT_INTPEND5_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                 */
51477   #define IPCT_INTPEND5_RECEIVE12_Min (0x0UL)        /*!< Min enumerator value of RECEIVE12 field.                             */
51478   #define IPCT_INTPEND5_RECEIVE12_Max (0x1UL)        /*!< Max enumerator value of RECEIVE12 field.                             */
51479   #define IPCT_INTPEND5_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
51480   #define IPCT_INTPEND5_RECEIVE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
51481 
51482 /* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
51483   #define IPCT_INTPEND5_RECEIVE13_Pos (13UL)         /*!< Position of RECEIVE13 field.                                         */
51484   #define IPCT_INTPEND5_RECEIVE13_Msk (0x1UL << IPCT_INTPEND5_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                 */
51485   #define IPCT_INTPEND5_RECEIVE13_Min (0x0UL)        /*!< Min enumerator value of RECEIVE13 field.                             */
51486   #define IPCT_INTPEND5_RECEIVE13_Max (0x1UL)        /*!< Max enumerator value of RECEIVE13 field.                             */
51487   #define IPCT_INTPEND5_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
51488   #define IPCT_INTPEND5_RECEIVE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
51489 
51490 /* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
51491   #define IPCT_INTPEND5_RECEIVE14_Pos (14UL)         /*!< Position of RECEIVE14 field.                                         */
51492   #define IPCT_INTPEND5_RECEIVE14_Msk (0x1UL << IPCT_INTPEND5_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                 */
51493   #define IPCT_INTPEND5_RECEIVE14_Min (0x0UL)        /*!< Min enumerator value of RECEIVE14 field.                             */
51494   #define IPCT_INTPEND5_RECEIVE14_Max (0x1UL)        /*!< Max enumerator value of RECEIVE14 field.                             */
51495   #define IPCT_INTPEND5_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
51496   #define IPCT_INTPEND5_RECEIVE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
51497 
51498 /* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
51499   #define IPCT_INTPEND5_RECEIVE15_Pos (15UL)         /*!< Position of RECEIVE15 field.                                         */
51500   #define IPCT_INTPEND5_RECEIVE15_Msk (0x1UL << IPCT_INTPEND5_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                 */
51501   #define IPCT_INTPEND5_RECEIVE15_Min (0x0UL)        /*!< Min enumerator value of RECEIVE15 field.                             */
51502   #define IPCT_INTPEND5_RECEIVE15_Max (0x1UL)        /*!< Max enumerator value of RECEIVE15 field.                             */
51503   #define IPCT_INTPEND5_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
51504   #define IPCT_INTPEND5_RECEIVE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
51505 
51506 /* ACKED0 @Bit 16 : Read pending status of interrupt for event ACKED[0] */
51507   #define IPCT_INTPEND5_ACKED0_Pos (16UL)            /*!< Position of ACKED0 field.                                            */
51508   #define IPCT_INTPEND5_ACKED0_Msk (0x1UL << IPCT_INTPEND5_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                          */
51509   #define IPCT_INTPEND5_ACKED0_Min (0x0UL)           /*!< Min enumerator value of ACKED0 field.                                */
51510   #define IPCT_INTPEND5_ACKED0_Max (0x1UL)           /*!< Max enumerator value of ACKED0 field.                                */
51511   #define IPCT_INTPEND5_ACKED0_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51512   #define IPCT_INTPEND5_ACKED0_Pending (0x1UL)       /*!< Read: Pending                                                        */
51513 
51514 /* ACKED1 @Bit 17 : Read pending status of interrupt for event ACKED[1] */
51515   #define IPCT_INTPEND5_ACKED1_Pos (17UL)            /*!< Position of ACKED1 field.                                            */
51516   #define IPCT_INTPEND5_ACKED1_Msk (0x1UL << IPCT_INTPEND5_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                          */
51517   #define IPCT_INTPEND5_ACKED1_Min (0x0UL)           /*!< Min enumerator value of ACKED1 field.                                */
51518   #define IPCT_INTPEND5_ACKED1_Max (0x1UL)           /*!< Max enumerator value of ACKED1 field.                                */
51519   #define IPCT_INTPEND5_ACKED1_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51520   #define IPCT_INTPEND5_ACKED1_Pending (0x1UL)       /*!< Read: Pending                                                        */
51521 
51522 /* ACKED2 @Bit 18 : Read pending status of interrupt for event ACKED[2] */
51523   #define IPCT_INTPEND5_ACKED2_Pos (18UL)            /*!< Position of ACKED2 field.                                            */
51524   #define IPCT_INTPEND5_ACKED2_Msk (0x1UL << IPCT_INTPEND5_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                          */
51525   #define IPCT_INTPEND5_ACKED2_Min (0x0UL)           /*!< Min enumerator value of ACKED2 field.                                */
51526   #define IPCT_INTPEND5_ACKED2_Max (0x1UL)           /*!< Max enumerator value of ACKED2 field.                                */
51527   #define IPCT_INTPEND5_ACKED2_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51528   #define IPCT_INTPEND5_ACKED2_Pending (0x1UL)       /*!< Read: Pending                                                        */
51529 
51530 /* ACKED3 @Bit 19 : Read pending status of interrupt for event ACKED[3] */
51531   #define IPCT_INTPEND5_ACKED3_Pos (19UL)            /*!< Position of ACKED3 field.                                            */
51532   #define IPCT_INTPEND5_ACKED3_Msk (0x1UL << IPCT_INTPEND5_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                          */
51533   #define IPCT_INTPEND5_ACKED3_Min (0x0UL)           /*!< Min enumerator value of ACKED3 field.                                */
51534   #define IPCT_INTPEND5_ACKED3_Max (0x1UL)           /*!< Max enumerator value of ACKED3 field.                                */
51535   #define IPCT_INTPEND5_ACKED3_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51536   #define IPCT_INTPEND5_ACKED3_Pending (0x1UL)       /*!< Read: Pending                                                        */
51537 
51538 /* ACKED4 @Bit 20 : Read pending status of interrupt for event ACKED[4] */
51539   #define IPCT_INTPEND5_ACKED4_Pos (20UL)            /*!< Position of ACKED4 field.                                            */
51540   #define IPCT_INTPEND5_ACKED4_Msk (0x1UL << IPCT_INTPEND5_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                          */
51541   #define IPCT_INTPEND5_ACKED4_Min (0x0UL)           /*!< Min enumerator value of ACKED4 field.                                */
51542   #define IPCT_INTPEND5_ACKED4_Max (0x1UL)           /*!< Max enumerator value of ACKED4 field.                                */
51543   #define IPCT_INTPEND5_ACKED4_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51544   #define IPCT_INTPEND5_ACKED4_Pending (0x1UL)       /*!< Read: Pending                                                        */
51545 
51546 /* ACKED5 @Bit 21 : Read pending status of interrupt for event ACKED[5] */
51547   #define IPCT_INTPEND5_ACKED5_Pos (21UL)            /*!< Position of ACKED5 field.                                            */
51548   #define IPCT_INTPEND5_ACKED5_Msk (0x1UL << IPCT_INTPEND5_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                          */
51549   #define IPCT_INTPEND5_ACKED5_Min (0x0UL)           /*!< Min enumerator value of ACKED5 field.                                */
51550   #define IPCT_INTPEND5_ACKED5_Max (0x1UL)           /*!< Max enumerator value of ACKED5 field.                                */
51551   #define IPCT_INTPEND5_ACKED5_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51552   #define IPCT_INTPEND5_ACKED5_Pending (0x1UL)       /*!< Read: Pending                                                        */
51553 
51554 /* ACKED6 @Bit 22 : Read pending status of interrupt for event ACKED[6] */
51555   #define IPCT_INTPEND5_ACKED6_Pos (22UL)            /*!< Position of ACKED6 field.                                            */
51556   #define IPCT_INTPEND5_ACKED6_Msk (0x1UL << IPCT_INTPEND5_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                          */
51557   #define IPCT_INTPEND5_ACKED6_Min (0x0UL)           /*!< Min enumerator value of ACKED6 field.                                */
51558   #define IPCT_INTPEND5_ACKED6_Max (0x1UL)           /*!< Max enumerator value of ACKED6 field.                                */
51559   #define IPCT_INTPEND5_ACKED6_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51560   #define IPCT_INTPEND5_ACKED6_Pending (0x1UL)       /*!< Read: Pending                                                        */
51561 
51562 /* ACKED7 @Bit 23 : Read pending status of interrupt for event ACKED[7] */
51563   #define IPCT_INTPEND5_ACKED7_Pos (23UL)            /*!< Position of ACKED7 field.                                            */
51564   #define IPCT_INTPEND5_ACKED7_Msk (0x1UL << IPCT_INTPEND5_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                          */
51565   #define IPCT_INTPEND5_ACKED7_Min (0x0UL)           /*!< Min enumerator value of ACKED7 field.                                */
51566   #define IPCT_INTPEND5_ACKED7_Max (0x1UL)           /*!< Max enumerator value of ACKED7 field.                                */
51567   #define IPCT_INTPEND5_ACKED7_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51568   #define IPCT_INTPEND5_ACKED7_Pending (0x1UL)       /*!< Read: Pending                                                        */
51569 
51570 /* ACKED8 @Bit 24 : Read pending status of interrupt for event ACKED[8] */
51571   #define IPCT_INTPEND5_ACKED8_Pos (24UL)            /*!< Position of ACKED8 field.                                            */
51572   #define IPCT_INTPEND5_ACKED8_Msk (0x1UL << IPCT_INTPEND5_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                          */
51573   #define IPCT_INTPEND5_ACKED8_Min (0x0UL)           /*!< Min enumerator value of ACKED8 field.                                */
51574   #define IPCT_INTPEND5_ACKED8_Max (0x1UL)           /*!< Max enumerator value of ACKED8 field.                                */
51575   #define IPCT_INTPEND5_ACKED8_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51576   #define IPCT_INTPEND5_ACKED8_Pending (0x1UL)       /*!< Read: Pending                                                        */
51577 
51578 /* ACKED9 @Bit 25 : Read pending status of interrupt for event ACKED[9] */
51579   #define IPCT_INTPEND5_ACKED9_Pos (25UL)            /*!< Position of ACKED9 field.                                            */
51580   #define IPCT_INTPEND5_ACKED9_Msk (0x1UL << IPCT_INTPEND5_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                          */
51581   #define IPCT_INTPEND5_ACKED9_Min (0x0UL)           /*!< Min enumerator value of ACKED9 field.                                */
51582   #define IPCT_INTPEND5_ACKED9_Max (0x1UL)           /*!< Max enumerator value of ACKED9 field.                                */
51583   #define IPCT_INTPEND5_ACKED9_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
51584   #define IPCT_INTPEND5_ACKED9_Pending (0x1UL)       /*!< Read: Pending                                                        */
51585 
51586 /* ACKED10 @Bit 26 : Read pending status of interrupt for event ACKED[10] */
51587   #define IPCT_INTPEND5_ACKED10_Pos (26UL)           /*!< Position of ACKED10 field.                                           */
51588   #define IPCT_INTPEND5_ACKED10_Msk (0x1UL << IPCT_INTPEND5_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                       */
51589   #define IPCT_INTPEND5_ACKED10_Min (0x0UL)          /*!< Min enumerator value of ACKED10 field.                               */
51590   #define IPCT_INTPEND5_ACKED10_Max (0x1UL)          /*!< Max enumerator value of ACKED10 field.                               */
51591   #define IPCT_INTPEND5_ACKED10_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
51592   #define IPCT_INTPEND5_ACKED10_Pending (0x1UL)      /*!< Read: Pending                                                        */
51593 
51594 /* ACKED11 @Bit 27 : Read pending status of interrupt for event ACKED[11] */
51595   #define IPCT_INTPEND5_ACKED11_Pos (27UL)           /*!< Position of ACKED11 field.                                           */
51596   #define IPCT_INTPEND5_ACKED11_Msk (0x1UL << IPCT_INTPEND5_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                       */
51597   #define IPCT_INTPEND5_ACKED11_Min (0x0UL)          /*!< Min enumerator value of ACKED11 field.                               */
51598   #define IPCT_INTPEND5_ACKED11_Max (0x1UL)          /*!< Max enumerator value of ACKED11 field.                               */
51599   #define IPCT_INTPEND5_ACKED11_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
51600   #define IPCT_INTPEND5_ACKED11_Pending (0x1UL)      /*!< Read: Pending                                                        */
51601 
51602 /* ACKED12 @Bit 28 : Read pending status of interrupt for event ACKED[12] */
51603   #define IPCT_INTPEND5_ACKED12_Pos (28UL)           /*!< Position of ACKED12 field.                                           */
51604   #define IPCT_INTPEND5_ACKED12_Msk (0x1UL << IPCT_INTPEND5_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                       */
51605   #define IPCT_INTPEND5_ACKED12_Min (0x0UL)          /*!< Min enumerator value of ACKED12 field.                               */
51606   #define IPCT_INTPEND5_ACKED12_Max (0x1UL)          /*!< Max enumerator value of ACKED12 field.                               */
51607   #define IPCT_INTPEND5_ACKED12_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
51608   #define IPCT_INTPEND5_ACKED12_Pending (0x1UL)      /*!< Read: Pending                                                        */
51609 
51610 /* ACKED13 @Bit 29 : Read pending status of interrupt for event ACKED[13] */
51611   #define IPCT_INTPEND5_ACKED13_Pos (29UL)           /*!< Position of ACKED13 field.                                           */
51612   #define IPCT_INTPEND5_ACKED13_Msk (0x1UL << IPCT_INTPEND5_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                       */
51613   #define IPCT_INTPEND5_ACKED13_Min (0x0UL)          /*!< Min enumerator value of ACKED13 field.                               */
51614   #define IPCT_INTPEND5_ACKED13_Max (0x1UL)          /*!< Max enumerator value of ACKED13 field.                               */
51615   #define IPCT_INTPEND5_ACKED13_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
51616   #define IPCT_INTPEND5_ACKED13_Pending (0x1UL)      /*!< Read: Pending                                                        */
51617 
51618 /* ACKED14 @Bit 30 : Read pending status of interrupt for event ACKED[14] */
51619   #define IPCT_INTPEND5_ACKED14_Pos (30UL)           /*!< Position of ACKED14 field.                                           */
51620   #define IPCT_INTPEND5_ACKED14_Msk (0x1UL << IPCT_INTPEND5_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                       */
51621   #define IPCT_INTPEND5_ACKED14_Min (0x0UL)          /*!< Min enumerator value of ACKED14 field.                               */
51622   #define IPCT_INTPEND5_ACKED14_Max (0x1UL)          /*!< Max enumerator value of ACKED14 field.                               */
51623   #define IPCT_INTPEND5_ACKED14_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
51624   #define IPCT_INTPEND5_ACKED14_Pending (0x1UL)      /*!< Read: Pending                                                        */
51625 
51626 /* ACKED15 @Bit 31 : Read pending status of interrupt for event ACKED[15] */
51627   #define IPCT_INTPEND5_ACKED15_Pos (31UL)           /*!< Position of ACKED15 field.                                           */
51628   #define IPCT_INTPEND5_ACKED15_Msk (0x1UL << IPCT_INTPEND5_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                       */
51629   #define IPCT_INTPEND5_ACKED15_Min (0x0UL)          /*!< Min enumerator value of ACKED15 field.                               */
51630   #define IPCT_INTPEND5_ACKED15_Max (0x1UL)          /*!< Max enumerator value of ACKED15 field.                               */
51631   #define IPCT_INTPEND5_ACKED15_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
51632   #define IPCT_INTPEND5_ACKED15_Pending (0x1UL)      /*!< Read: Pending                                                        */
51633 
51634 
51635 /* IPCT_INTEN6: Enable or disable interrupt */
51636   #define IPCT_INTEN6_ResetValue (0x00000000UL)      /*!< Reset value of INTEN6 register.                                      */
51637 
51638 /* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
51639   #define IPCT_INTEN6_RECEIVE0_Pos (0UL)             /*!< Position of RECEIVE0 field.                                          */
51640   #define IPCT_INTEN6_RECEIVE0_Msk (0x1UL << IPCT_INTEN6_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                        */
51641   #define IPCT_INTEN6_RECEIVE0_Min (0x0UL)           /*!< Min enumerator value of RECEIVE0 field.                              */
51642   #define IPCT_INTEN6_RECEIVE0_Max (0x1UL)           /*!< Max enumerator value of RECEIVE0 field.                              */
51643   #define IPCT_INTEN6_RECEIVE0_Disabled (0x0UL)      /*!< Disable                                                              */
51644   #define IPCT_INTEN6_RECEIVE0_Enabled (0x1UL)       /*!< Enable                                                               */
51645 
51646 /* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
51647   #define IPCT_INTEN6_RECEIVE1_Pos (1UL)             /*!< Position of RECEIVE1 field.                                          */
51648   #define IPCT_INTEN6_RECEIVE1_Msk (0x1UL << IPCT_INTEN6_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                        */
51649   #define IPCT_INTEN6_RECEIVE1_Min (0x0UL)           /*!< Min enumerator value of RECEIVE1 field.                              */
51650   #define IPCT_INTEN6_RECEIVE1_Max (0x1UL)           /*!< Max enumerator value of RECEIVE1 field.                              */
51651   #define IPCT_INTEN6_RECEIVE1_Disabled (0x0UL)      /*!< Disable                                                              */
51652   #define IPCT_INTEN6_RECEIVE1_Enabled (0x1UL)       /*!< Enable                                                               */
51653 
51654 /* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
51655   #define IPCT_INTEN6_RECEIVE2_Pos (2UL)             /*!< Position of RECEIVE2 field.                                          */
51656   #define IPCT_INTEN6_RECEIVE2_Msk (0x1UL << IPCT_INTEN6_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                        */
51657   #define IPCT_INTEN6_RECEIVE2_Min (0x0UL)           /*!< Min enumerator value of RECEIVE2 field.                              */
51658   #define IPCT_INTEN6_RECEIVE2_Max (0x1UL)           /*!< Max enumerator value of RECEIVE2 field.                              */
51659   #define IPCT_INTEN6_RECEIVE2_Disabled (0x0UL)      /*!< Disable                                                              */
51660   #define IPCT_INTEN6_RECEIVE2_Enabled (0x1UL)       /*!< Enable                                                               */
51661 
51662 /* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
51663   #define IPCT_INTEN6_RECEIVE3_Pos (3UL)             /*!< Position of RECEIVE3 field.                                          */
51664   #define IPCT_INTEN6_RECEIVE3_Msk (0x1UL << IPCT_INTEN6_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                        */
51665   #define IPCT_INTEN6_RECEIVE3_Min (0x0UL)           /*!< Min enumerator value of RECEIVE3 field.                              */
51666   #define IPCT_INTEN6_RECEIVE3_Max (0x1UL)           /*!< Max enumerator value of RECEIVE3 field.                              */
51667   #define IPCT_INTEN6_RECEIVE3_Disabled (0x0UL)      /*!< Disable                                                              */
51668   #define IPCT_INTEN6_RECEIVE3_Enabled (0x1UL)       /*!< Enable                                                               */
51669 
51670 /* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
51671   #define IPCT_INTEN6_RECEIVE4_Pos (4UL)             /*!< Position of RECEIVE4 field.                                          */
51672   #define IPCT_INTEN6_RECEIVE4_Msk (0x1UL << IPCT_INTEN6_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                        */
51673   #define IPCT_INTEN6_RECEIVE4_Min (0x0UL)           /*!< Min enumerator value of RECEIVE4 field.                              */
51674   #define IPCT_INTEN6_RECEIVE4_Max (0x1UL)           /*!< Max enumerator value of RECEIVE4 field.                              */
51675   #define IPCT_INTEN6_RECEIVE4_Disabled (0x0UL)      /*!< Disable                                                              */
51676   #define IPCT_INTEN6_RECEIVE4_Enabled (0x1UL)       /*!< Enable                                                               */
51677 
51678 /* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
51679   #define IPCT_INTEN6_RECEIVE5_Pos (5UL)             /*!< Position of RECEIVE5 field.                                          */
51680   #define IPCT_INTEN6_RECEIVE5_Msk (0x1UL << IPCT_INTEN6_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                        */
51681   #define IPCT_INTEN6_RECEIVE5_Min (0x0UL)           /*!< Min enumerator value of RECEIVE5 field.                              */
51682   #define IPCT_INTEN6_RECEIVE5_Max (0x1UL)           /*!< Max enumerator value of RECEIVE5 field.                              */
51683   #define IPCT_INTEN6_RECEIVE5_Disabled (0x0UL)      /*!< Disable                                                              */
51684   #define IPCT_INTEN6_RECEIVE5_Enabled (0x1UL)       /*!< Enable                                                               */
51685 
51686 /* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
51687   #define IPCT_INTEN6_RECEIVE6_Pos (6UL)             /*!< Position of RECEIVE6 field.                                          */
51688   #define IPCT_INTEN6_RECEIVE6_Msk (0x1UL << IPCT_INTEN6_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                        */
51689   #define IPCT_INTEN6_RECEIVE6_Min (0x0UL)           /*!< Min enumerator value of RECEIVE6 field.                              */
51690   #define IPCT_INTEN6_RECEIVE6_Max (0x1UL)           /*!< Max enumerator value of RECEIVE6 field.                              */
51691   #define IPCT_INTEN6_RECEIVE6_Disabled (0x0UL)      /*!< Disable                                                              */
51692   #define IPCT_INTEN6_RECEIVE6_Enabled (0x1UL)       /*!< Enable                                                               */
51693 
51694 /* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
51695   #define IPCT_INTEN6_RECEIVE7_Pos (7UL)             /*!< Position of RECEIVE7 field.                                          */
51696   #define IPCT_INTEN6_RECEIVE7_Msk (0x1UL << IPCT_INTEN6_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                        */
51697   #define IPCT_INTEN6_RECEIVE7_Min (0x0UL)           /*!< Min enumerator value of RECEIVE7 field.                              */
51698   #define IPCT_INTEN6_RECEIVE7_Max (0x1UL)           /*!< Max enumerator value of RECEIVE7 field.                              */
51699   #define IPCT_INTEN6_RECEIVE7_Disabled (0x0UL)      /*!< Disable                                                              */
51700   #define IPCT_INTEN6_RECEIVE7_Enabled (0x1UL)       /*!< Enable                                                               */
51701 
51702 /* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
51703   #define IPCT_INTEN6_RECEIVE8_Pos (8UL)             /*!< Position of RECEIVE8 field.                                          */
51704   #define IPCT_INTEN6_RECEIVE8_Msk (0x1UL << IPCT_INTEN6_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                        */
51705   #define IPCT_INTEN6_RECEIVE8_Min (0x0UL)           /*!< Min enumerator value of RECEIVE8 field.                              */
51706   #define IPCT_INTEN6_RECEIVE8_Max (0x1UL)           /*!< Max enumerator value of RECEIVE8 field.                              */
51707   #define IPCT_INTEN6_RECEIVE8_Disabled (0x0UL)      /*!< Disable                                                              */
51708   #define IPCT_INTEN6_RECEIVE8_Enabled (0x1UL)       /*!< Enable                                                               */
51709 
51710 /* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
51711   #define IPCT_INTEN6_RECEIVE9_Pos (9UL)             /*!< Position of RECEIVE9 field.                                          */
51712   #define IPCT_INTEN6_RECEIVE9_Msk (0x1UL << IPCT_INTEN6_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                        */
51713   #define IPCT_INTEN6_RECEIVE9_Min (0x0UL)           /*!< Min enumerator value of RECEIVE9 field.                              */
51714   #define IPCT_INTEN6_RECEIVE9_Max (0x1UL)           /*!< Max enumerator value of RECEIVE9 field.                              */
51715   #define IPCT_INTEN6_RECEIVE9_Disabled (0x0UL)      /*!< Disable                                                              */
51716   #define IPCT_INTEN6_RECEIVE9_Enabled (0x1UL)       /*!< Enable                                                               */
51717 
51718 /* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
51719   #define IPCT_INTEN6_RECEIVE10_Pos (10UL)           /*!< Position of RECEIVE10 field.                                         */
51720   #define IPCT_INTEN6_RECEIVE10_Msk (0x1UL << IPCT_INTEN6_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                     */
51721   #define IPCT_INTEN6_RECEIVE10_Min (0x0UL)          /*!< Min enumerator value of RECEIVE10 field.                             */
51722   #define IPCT_INTEN6_RECEIVE10_Max (0x1UL)          /*!< Max enumerator value of RECEIVE10 field.                             */
51723   #define IPCT_INTEN6_RECEIVE10_Disabled (0x0UL)     /*!< Disable                                                              */
51724   #define IPCT_INTEN6_RECEIVE10_Enabled (0x1UL)      /*!< Enable                                                               */
51725 
51726 /* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
51727   #define IPCT_INTEN6_RECEIVE11_Pos (11UL)           /*!< Position of RECEIVE11 field.                                         */
51728   #define IPCT_INTEN6_RECEIVE11_Msk (0x1UL << IPCT_INTEN6_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                     */
51729   #define IPCT_INTEN6_RECEIVE11_Min (0x0UL)          /*!< Min enumerator value of RECEIVE11 field.                             */
51730   #define IPCT_INTEN6_RECEIVE11_Max (0x1UL)          /*!< Max enumerator value of RECEIVE11 field.                             */
51731   #define IPCT_INTEN6_RECEIVE11_Disabled (0x0UL)     /*!< Disable                                                              */
51732   #define IPCT_INTEN6_RECEIVE11_Enabled (0x1UL)      /*!< Enable                                                               */
51733 
51734 /* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
51735   #define IPCT_INTEN6_RECEIVE12_Pos (12UL)           /*!< Position of RECEIVE12 field.                                         */
51736   #define IPCT_INTEN6_RECEIVE12_Msk (0x1UL << IPCT_INTEN6_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                     */
51737   #define IPCT_INTEN6_RECEIVE12_Min (0x0UL)          /*!< Min enumerator value of RECEIVE12 field.                             */
51738   #define IPCT_INTEN6_RECEIVE12_Max (0x1UL)          /*!< Max enumerator value of RECEIVE12 field.                             */
51739   #define IPCT_INTEN6_RECEIVE12_Disabled (0x0UL)     /*!< Disable                                                              */
51740   #define IPCT_INTEN6_RECEIVE12_Enabled (0x1UL)      /*!< Enable                                                               */
51741 
51742 /* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
51743   #define IPCT_INTEN6_RECEIVE13_Pos (13UL)           /*!< Position of RECEIVE13 field.                                         */
51744   #define IPCT_INTEN6_RECEIVE13_Msk (0x1UL << IPCT_INTEN6_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                     */
51745   #define IPCT_INTEN6_RECEIVE13_Min (0x0UL)          /*!< Min enumerator value of RECEIVE13 field.                             */
51746   #define IPCT_INTEN6_RECEIVE13_Max (0x1UL)          /*!< Max enumerator value of RECEIVE13 field.                             */
51747   #define IPCT_INTEN6_RECEIVE13_Disabled (0x0UL)     /*!< Disable                                                              */
51748   #define IPCT_INTEN6_RECEIVE13_Enabled (0x1UL)      /*!< Enable                                                               */
51749 
51750 /* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
51751   #define IPCT_INTEN6_RECEIVE14_Pos (14UL)           /*!< Position of RECEIVE14 field.                                         */
51752   #define IPCT_INTEN6_RECEIVE14_Msk (0x1UL << IPCT_INTEN6_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                     */
51753   #define IPCT_INTEN6_RECEIVE14_Min (0x0UL)          /*!< Min enumerator value of RECEIVE14 field.                             */
51754   #define IPCT_INTEN6_RECEIVE14_Max (0x1UL)          /*!< Max enumerator value of RECEIVE14 field.                             */
51755   #define IPCT_INTEN6_RECEIVE14_Disabled (0x0UL)     /*!< Disable                                                              */
51756   #define IPCT_INTEN6_RECEIVE14_Enabled (0x1UL)      /*!< Enable                                                               */
51757 
51758 /* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
51759   #define IPCT_INTEN6_RECEIVE15_Pos (15UL)           /*!< Position of RECEIVE15 field.                                         */
51760   #define IPCT_INTEN6_RECEIVE15_Msk (0x1UL << IPCT_INTEN6_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                     */
51761   #define IPCT_INTEN6_RECEIVE15_Min (0x0UL)          /*!< Min enumerator value of RECEIVE15 field.                             */
51762   #define IPCT_INTEN6_RECEIVE15_Max (0x1UL)          /*!< Max enumerator value of RECEIVE15 field.                             */
51763   #define IPCT_INTEN6_RECEIVE15_Disabled (0x0UL)     /*!< Disable                                                              */
51764   #define IPCT_INTEN6_RECEIVE15_Enabled (0x1UL)      /*!< Enable                                                               */
51765 
51766 /* ACKED0 @Bit 16 : Enable or disable interrupt for event ACKED[0] */
51767   #define IPCT_INTEN6_ACKED0_Pos (16UL)              /*!< Position of ACKED0 field.                                            */
51768   #define IPCT_INTEN6_ACKED0_Msk (0x1UL << IPCT_INTEN6_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                              */
51769   #define IPCT_INTEN6_ACKED0_Min (0x0UL)             /*!< Min enumerator value of ACKED0 field.                                */
51770   #define IPCT_INTEN6_ACKED0_Max (0x1UL)             /*!< Max enumerator value of ACKED0 field.                                */
51771   #define IPCT_INTEN6_ACKED0_Disabled (0x0UL)        /*!< Disable                                                              */
51772   #define IPCT_INTEN6_ACKED0_Enabled (0x1UL)         /*!< Enable                                                               */
51773 
51774 /* ACKED1 @Bit 17 : Enable or disable interrupt for event ACKED[1] */
51775   #define IPCT_INTEN6_ACKED1_Pos (17UL)              /*!< Position of ACKED1 field.                                            */
51776   #define IPCT_INTEN6_ACKED1_Msk (0x1UL << IPCT_INTEN6_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                              */
51777   #define IPCT_INTEN6_ACKED1_Min (0x0UL)             /*!< Min enumerator value of ACKED1 field.                                */
51778   #define IPCT_INTEN6_ACKED1_Max (0x1UL)             /*!< Max enumerator value of ACKED1 field.                                */
51779   #define IPCT_INTEN6_ACKED1_Disabled (0x0UL)        /*!< Disable                                                              */
51780   #define IPCT_INTEN6_ACKED1_Enabled (0x1UL)         /*!< Enable                                                               */
51781 
51782 /* ACKED2 @Bit 18 : Enable or disable interrupt for event ACKED[2] */
51783   #define IPCT_INTEN6_ACKED2_Pos (18UL)              /*!< Position of ACKED2 field.                                            */
51784   #define IPCT_INTEN6_ACKED2_Msk (0x1UL << IPCT_INTEN6_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                              */
51785   #define IPCT_INTEN6_ACKED2_Min (0x0UL)             /*!< Min enumerator value of ACKED2 field.                                */
51786   #define IPCT_INTEN6_ACKED2_Max (0x1UL)             /*!< Max enumerator value of ACKED2 field.                                */
51787   #define IPCT_INTEN6_ACKED2_Disabled (0x0UL)        /*!< Disable                                                              */
51788   #define IPCT_INTEN6_ACKED2_Enabled (0x1UL)         /*!< Enable                                                               */
51789 
51790 /* ACKED3 @Bit 19 : Enable or disable interrupt for event ACKED[3] */
51791   #define IPCT_INTEN6_ACKED3_Pos (19UL)              /*!< Position of ACKED3 field.                                            */
51792   #define IPCT_INTEN6_ACKED3_Msk (0x1UL << IPCT_INTEN6_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                              */
51793   #define IPCT_INTEN6_ACKED3_Min (0x0UL)             /*!< Min enumerator value of ACKED3 field.                                */
51794   #define IPCT_INTEN6_ACKED3_Max (0x1UL)             /*!< Max enumerator value of ACKED3 field.                                */
51795   #define IPCT_INTEN6_ACKED3_Disabled (0x0UL)        /*!< Disable                                                              */
51796   #define IPCT_INTEN6_ACKED3_Enabled (0x1UL)         /*!< Enable                                                               */
51797 
51798 /* ACKED4 @Bit 20 : Enable or disable interrupt for event ACKED[4] */
51799   #define IPCT_INTEN6_ACKED4_Pos (20UL)              /*!< Position of ACKED4 field.                                            */
51800   #define IPCT_INTEN6_ACKED4_Msk (0x1UL << IPCT_INTEN6_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                              */
51801   #define IPCT_INTEN6_ACKED4_Min (0x0UL)             /*!< Min enumerator value of ACKED4 field.                                */
51802   #define IPCT_INTEN6_ACKED4_Max (0x1UL)             /*!< Max enumerator value of ACKED4 field.                                */
51803   #define IPCT_INTEN6_ACKED4_Disabled (0x0UL)        /*!< Disable                                                              */
51804   #define IPCT_INTEN6_ACKED4_Enabled (0x1UL)         /*!< Enable                                                               */
51805 
51806 /* ACKED5 @Bit 21 : Enable or disable interrupt for event ACKED[5] */
51807   #define IPCT_INTEN6_ACKED5_Pos (21UL)              /*!< Position of ACKED5 field.                                            */
51808   #define IPCT_INTEN6_ACKED5_Msk (0x1UL << IPCT_INTEN6_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                              */
51809   #define IPCT_INTEN6_ACKED5_Min (0x0UL)             /*!< Min enumerator value of ACKED5 field.                                */
51810   #define IPCT_INTEN6_ACKED5_Max (0x1UL)             /*!< Max enumerator value of ACKED5 field.                                */
51811   #define IPCT_INTEN6_ACKED5_Disabled (0x0UL)        /*!< Disable                                                              */
51812   #define IPCT_INTEN6_ACKED5_Enabled (0x1UL)         /*!< Enable                                                               */
51813 
51814 /* ACKED6 @Bit 22 : Enable or disable interrupt for event ACKED[6] */
51815   #define IPCT_INTEN6_ACKED6_Pos (22UL)              /*!< Position of ACKED6 field.                                            */
51816   #define IPCT_INTEN6_ACKED6_Msk (0x1UL << IPCT_INTEN6_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                              */
51817   #define IPCT_INTEN6_ACKED6_Min (0x0UL)             /*!< Min enumerator value of ACKED6 field.                                */
51818   #define IPCT_INTEN6_ACKED6_Max (0x1UL)             /*!< Max enumerator value of ACKED6 field.                                */
51819   #define IPCT_INTEN6_ACKED6_Disabled (0x0UL)        /*!< Disable                                                              */
51820   #define IPCT_INTEN6_ACKED6_Enabled (0x1UL)         /*!< Enable                                                               */
51821 
51822 /* ACKED7 @Bit 23 : Enable or disable interrupt for event ACKED[7] */
51823   #define IPCT_INTEN6_ACKED7_Pos (23UL)              /*!< Position of ACKED7 field.                                            */
51824   #define IPCT_INTEN6_ACKED7_Msk (0x1UL << IPCT_INTEN6_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                              */
51825   #define IPCT_INTEN6_ACKED7_Min (0x0UL)             /*!< Min enumerator value of ACKED7 field.                                */
51826   #define IPCT_INTEN6_ACKED7_Max (0x1UL)             /*!< Max enumerator value of ACKED7 field.                                */
51827   #define IPCT_INTEN6_ACKED7_Disabled (0x0UL)        /*!< Disable                                                              */
51828   #define IPCT_INTEN6_ACKED7_Enabled (0x1UL)         /*!< Enable                                                               */
51829 
51830 /* ACKED8 @Bit 24 : Enable or disable interrupt for event ACKED[8] */
51831   #define IPCT_INTEN6_ACKED8_Pos (24UL)              /*!< Position of ACKED8 field.                                            */
51832   #define IPCT_INTEN6_ACKED8_Msk (0x1UL << IPCT_INTEN6_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                              */
51833   #define IPCT_INTEN6_ACKED8_Min (0x0UL)             /*!< Min enumerator value of ACKED8 field.                                */
51834   #define IPCT_INTEN6_ACKED8_Max (0x1UL)             /*!< Max enumerator value of ACKED8 field.                                */
51835   #define IPCT_INTEN6_ACKED8_Disabled (0x0UL)        /*!< Disable                                                              */
51836   #define IPCT_INTEN6_ACKED8_Enabled (0x1UL)         /*!< Enable                                                               */
51837 
51838 /* ACKED9 @Bit 25 : Enable or disable interrupt for event ACKED[9] */
51839   #define IPCT_INTEN6_ACKED9_Pos (25UL)              /*!< Position of ACKED9 field.                                            */
51840   #define IPCT_INTEN6_ACKED9_Msk (0x1UL << IPCT_INTEN6_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                              */
51841   #define IPCT_INTEN6_ACKED9_Min (0x0UL)             /*!< Min enumerator value of ACKED9 field.                                */
51842   #define IPCT_INTEN6_ACKED9_Max (0x1UL)             /*!< Max enumerator value of ACKED9 field.                                */
51843   #define IPCT_INTEN6_ACKED9_Disabled (0x0UL)        /*!< Disable                                                              */
51844   #define IPCT_INTEN6_ACKED9_Enabled (0x1UL)         /*!< Enable                                                               */
51845 
51846 /* ACKED10 @Bit 26 : Enable or disable interrupt for event ACKED[10] */
51847   #define IPCT_INTEN6_ACKED10_Pos (26UL)             /*!< Position of ACKED10 field.                                           */
51848   #define IPCT_INTEN6_ACKED10_Msk (0x1UL << IPCT_INTEN6_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                           */
51849   #define IPCT_INTEN6_ACKED10_Min (0x0UL)            /*!< Min enumerator value of ACKED10 field.                               */
51850   #define IPCT_INTEN6_ACKED10_Max (0x1UL)            /*!< Max enumerator value of ACKED10 field.                               */
51851   #define IPCT_INTEN6_ACKED10_Disabled (0x0UL)       /*!< Disable                                                              */
51852   #define IPCT_INTEN6_ACKED10_Enabled (0x1UL)        /*!< Enable                                                               */
51853 
51854 /* ACKED11 @Bit 27 : Enable or disable interrupt for event ACKED[11] */
51855   #define IPCT_INTEN6_ACKED11_Pos (27UL)             /*!< Position of ACKED11 field.                                           */
51856   #define IPCT_INTEN6_ACKED11_Msk (0x1UL << IPCT_INTEN6_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                           */
51857   #define IPCT_INTEN6_ACKED11_Min (0x0UL)            /*!< Min enumerator value of ACKED11 field.                               */
51858   #define IPCT_INTEN6_ACKED11_Max (0x1UL)            /*!< Max enumerator value of ACKED11 field.                               */
51859   #define IPCT_INTEN6_ACKED11_Disabled (0x0UL)       /*!< Disable                                                              */
51860   #define IPCT_INTEN6_ACKED11_Enabled (0x1UL)        /*!< Enable                                                               */
51861 
51862 /* ACKED12 @Bit 28 : Enable or disable interrupt for event ACKED[12] */
51863   #define IPCT_INTEN6_ACKED12_Pos (28UL)             /*!< Position of ACKED12 field.                                           */
51864   #define IPCT_INTEN6_ACKED12_Msk (0x1UL << IPCT_INTEN6_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                           */
51865   #define IPCT_INTEN6_ACKED12_Min (0x0UL)            /*!< Min enumerator value of ACKED12 field.                               */
51866   #define IPCT_INTEN6_ACKED12_Max (0x1UL)            /*!< Max enumerator value of ACKED12 field.                               */
51867   #define IPCT_INTEN6_ACKED12_Disabled (0x0UL)       /*!< Disable                                                              */
51868   #define IPCT_INTEN6_ACKED12_Enabled (0x1UL)        /*!< Enable                                                               */
51869 
51870 /* ACKED13 @Bit 29 : Enable or disable interrupt for event ACKED[13] */
51871   #define IPCT_INTEN6_ACKED13_Pos (29UL)             /*!< Position of ACKED13 field.                                           */
51872   #define IPCT_INTEN6_ACKED13_Msk (0x1UL << IPCT_INTEN6_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                           */
51873   #define IPCT_INTEN6_ACKED13_Min (0x0UL)            /*!< Min enumerator value of ACKED13 field.                               */
51874   #define IPCT_INTEN6_ACKED13_Max (0x1UL)            /*!< Max enumerator value of ACKED13 field.                               */
51875   #define IPCT_INTEN6_ACKED13_Disabled (0x0UL)       /*!< Disable                                                              */
51876   #define IPCT_INTEN6_ACKED13_Enabled (0x1UL)        /*!< Enable                                                               */
51877 
51878 /* ACKED14 @Bit 30 : Enable or disable interrupt for event ACKED[14] */
51879   #define IPCT_INTEN6_ACKED14_Pos (30UL)             /*!< Position of ACKED14 field.                                           */
51880   #define IPCT_INTEN6_ACKED14_Msk (0x1UL << IPCT_INTEN6_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                           */
51881   #define IPCT_INTEN6_ACKED14_Min (0x0UL)            /*!< Min enumerator value of ACKED14 field.                               */
51882   #define IPCT_INTEN6_ACKED14_Max (0x1UL)            /*!< Max enumerator value of ACKED14 field.                               */
51883   #define IPCT_INTEN6_ACKED14_Disabled (0x0UL)       /*!< Disable                                                              */
51884   #define IPCT_INTEN6_ACKED14_Enabled (0x1UL)        /*!< Enable                                                               */
51885 
51886 /* ACKED15 @Bit 31 : Enable or disable interrupt for event ACKED[15] */
51887   #define IPCT_INTEN6_ACKED15_Pos (31UL)             /*!< Position of ACKED15 field.                                           */
51888   #define IPCT_INTEN6_ACKED15_Msk (0x1UL << IPCT_INTEN6_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                           */
51889   #define IPCT_INTEN6_ACKED15_Min (0x0UL)            /*!< Min enumerator value of ACKED15 field.                               */
51890   #define IPCT_INTEN6_ACKED15_Max (0x1UL)            /*!< Max enumerator value of ACKED15 field.                               */
51891   #define IPCT_INTEN6_ACKED15_Disabled (0x0UL)       /*!< Disable                                                              */
51892   #define IPCT_INTEN6_ACKED15_Enabled (0x1UL)        /*!< Enable                                                               */
51893 
51894 
51895 /* IPCT_INTENSET6: Enable interrupt */
51896   #define IPCT_INTENSET6_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET6 register.                                   */
51897 
51898 /* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
51899   #define IPCT_INTENSET6_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
51900   #define IPCT_INTENSET6_RECEIVE0_Msk (0x1UL << IPCT_INTENSET6_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
51901   #define IPCT_INTENSET6_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
51902   #define IPCT_INTENSET6_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
51903   #define IPCT_INTENSET6_RECEIVE0_Set (0x1UL)        /*!< Enable                                                               */
51904   #define IPCT_INTENSET6_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51905   #define IPCT_INTENSET6_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51906 
51907 /* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
51908   #define IPCT_INTENSET6_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
51909   #define IPCT_INTENSET6_RECEIVE1_Msk (0x1UL << IPCT_INTENSET6_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
51910   #define IPCT_INTENSET6_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
51911   #define IPCT_INTENSET6_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
51912   #define IPCT_INTENSET6_RECEIVE1_Set (0x1UL)        /*!< Enable                                                               */
51913   #define IPCT_INTENSET6_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51914   #define IPCT_INTENSET6_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51915 
51916 /* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
51917   #define IPCT_INTENSET6_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
51918   #define IPCT_INTENSET6_RECEIVE2_Msk (0x1UL << IPCT_INTENSET6_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
51919   #define IPCT_INTENSET6_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
51920   #define IPCT_INTENSET6_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
51921   #define IPCT_INTENSET6_RECEIVE2_Set (0x1UL)        /*!< Enable                                                               */
51922   #define IPCT_INTENSET6_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51923   #define IPCT_INTENSET6_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51924 
51925 /* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
51926   #define IPCT_INTENSET6_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
51927   #define IPCT_INTENSET6_RECEIVE3_Msk (0x1UL << IPCT_INTENSET6_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
51928   #define IPCT_INTENSET6_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
51929   #define IPCT_INTENSET6_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
51930   #define IPCT_INTENSET6_RECEIVE3_Set (0x1UL)        /*!< Enable                                                               */
51931   #define IPCT_INTENSET6_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51932   #define IPCT_INTENSET6_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51933 
51934 /* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
51935   #define IPCT_INTENSET6_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
51936   #define IPCT_INTENSET6_RECEIVE4_Msk (0x1UL << IPCT_INTENSET6_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
51937   #define IPCT_INTENSET6_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
51938   #define IPCT_INTENSET6_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
51939   #define IPCT_INTENSET6_RECEIVE4_Set (0x1UL)        /*!< Enable                                                               */
51940   #define IPCT_INTENSET6_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51941   #define IPCT_INTENSET6_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51942 
51943 /* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
51944   #define IPCT_INTENSET6_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
51945   #define IPCT_INTENSET6_RECEIVE5_Msk (0x1UL << IPCT_INTENSET6_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
51946   #define IPCT_INTENSET6_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
51947   #define IPCT_INTENSET6_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
51948   #define IPCT_INTENSET6_RECEIVE5_Set (0x1UL)        /*!< Enable                                                               */
51949   #define IPCT_INTENSET6_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51950   #define IPCT_INTENSET6_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51951 
51952 /* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
51953   #define IPCT_INTENSET6_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
51954   #define IPCT_INTENSET6_RECEIVE6_Msk (0x1UL << IPCT_INTENSET6_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
51955   #define IPCT_INTENSET6_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
51956   #define IPCT_INTENSET6_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
51957   #define IPCT_INTENSET6_RECEIVE6_Set (0x1UL)        /*!< Enable                                                               */
51958   #define IPCT_INTENSET6_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51959   #define IPCT_INTENSET6_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51960 
51961 /* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
51962   #define IPCT_INTENSET6_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
51963   #define IPCT_INTENSET6_RECEIVE7_Msk (0x1UL << IPCT_INTENSET6_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
51964   #define IPCT_INTENSET6_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
51965   #define IPCT_INTENSET6_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
51966   #define IPCT_INTENSET6_RECEIVE7_Set (0x1UL)        /*!< Enable                                                               */
51967   #define IPCT_INTENSET6_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51968   #define IPCT_INTENSET6_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51969 
51970 /* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
51971   #define IPCT_INTENSET6_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
51972   #define IPCT_INTENSET6_RECEIVE8_Msk (0x1UL << IPCT_INTENSET6_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
51973   #define IPCT_INTENSET6_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
51974   #define IPCT_INTENSET6_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
51975   #define IPCT_INTENSET6_RECEIVE8_Set (0x1UL)        /*!< Enable                                                               */
51976   #define IPCT_INTENSET6_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51977   #define IPCT_INTENSET6_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51978 
51979 /* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
51980   #define IPCT_INTENSET6_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
51981   #define IPCT_INTENSET6_RECEIVE9_Msk (0x1UL << IPCT_INTENSET6_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
51982   #define IPCT_INTENSET6_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
51983   #define IPCT_INTENSET6_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
51984   #define IPCT_INTENSET6_RECEIVE9_Set (0x1UL)        /*!< Enable                                                               */
51985   #define IPCT_INTENSET6_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
51986   #define IPCT_INTENSET6_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
51987 
51988 /* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
51989   #define IPCT_INTENSET6_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
51990   #define IPCT_INTENSET6_RECEIVE10_Msk (0x1UL << IPCT_INTENSET6_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
51991   #define IPCT_INTENSET6_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
51992   #define IPCT_INTENSET6_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
51993   #define IPCT_INTENSET6_RECEIVE10_Set (0x1UL)       /*!< Enable                                                               */
51994   #define IPCT_INTENSET6_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
51995   #define IPCT_INTENSET6_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
51996 
51997 /* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
51998   #define IPCT_INTENSET6_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
51999   #define IPCT_INTENSET6_RECEIVE11_Msk (0x1UL << IPCT_INTENSET6_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
52000   #define IPCT_INTENSET6_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
52001   #define IPCT_INTENSET6_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
52002   #define IPCT_INTENSET6_RECEIVE11_Set (0x1UL)       /*!< Enable                                                               */
52003   #define IPCT_INTENSET6_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52004   #define IPCT_INTENSET6_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52005 
52006 /* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
52007   #define IPCT_INTENSET6_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
52008   #define IPCT_INTENSET6_RECEIVE12_Msk (0x1UL << IPCT_INTENSET6_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
52009   #define IPCT_INTENSET6_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
52010   #define IPCT_INTENSET6_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
52011   #define IPCT_INTENSET6_RECEIVE12_Set (0x1UL)       /*!< Enable                                                               */
52012   #define IPCT_INTENSET6_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52013   #define IPCT_INTENSET6_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52014 
52015 /* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
52016   #define IPCT_INTENSET6_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
52017   #define IPCT_INTENSET6_RECEIVE13_Msk (0x1UL << IPCT_INTENSET6_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
52018   #define IPCT_INTENSET6_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
52019   #define IPCT_INTENSET6_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
52020   #define IPCT_INTENSET6_RECEIVE13_Set (0x1UL)       /*!< Enable                                                               */
52021   #define IPCT_INTENSET6_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52022   #define IPCT_INTENSET6_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52023 
52024 /* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
52025   #define IPCT_INTENSET6_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
52026   #define IPCT_INTENSET6_RECEIVE14_Msk (0x1UL << IPCT_INTENSET6_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
52027   #define IPCT_INTENSET6_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
52028   #define IPCT_INTENSET6_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
52029   #define IPCT_INTENSET6_RECEIVE14_Set (0x1UL)       /*!< Enable                                                               */
52030   #define IPCT_INTENSET6_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52031   #define IPCT_INTENSET6_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52032 
52033 /* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
52034   #define IPCT_INTENSET6_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
52035   #define IPCT_INTENSET6_RECEIVE15_Msk (0x1UL << IPCT_INTENSET6_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
52036   #define IPCT_INTENSET6_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
52037   #define IPCT_INTENSET6_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
52038   #define IPCT_INTENSET6_RECEIVE15_Set (0x1UL)       /*!< Enable                                                               */
52039   #define IPCT_INTENSET6_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52040   #define IPCT_INTENSET6_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52041 
52042 /* ACKED0 @Bit 16 : Write '1' to enable interrupt for event ACKED[0] */
52043   #define IPCT_INTENSET6_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
52044   #define IPCT_INTENSET6_ACKED0_Msk (0x1UL << IPCT_INTENSET6_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
52045   #define IPCT_INTENSET6_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
52046   #define IPCT_INTENSET6_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
52047   #define IPCT_INTENSET6_ACKED0_Set (0x1UL)          /*!< Enable                                                               */
52048   #define IPCT_INTENSET6_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52049   #define IPCT_INTENSET6_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52050 
52051 /* ACKED1 @Bit 17 : Write '1' to enable interrupt for event ACKED[1] */
52052   #define IPCT_INTENSET6_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
52053   #define IPCT_INTENSET6_ACKED1_Msk (0x1UL << IPCT_INTENSET6_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
52054   #define IPCT_INTENSET6_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
52055   #define IPCT_INTENSET6_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
52056   #define IPCT_INTENSET6_ACKED1_Set (0x1UL)          /*!< Enable                                                               */
52057   #define IPCT_INTENSET6_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52058   #define IPCT_INTENSET6_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52059 
52060 /* ACKED2 @Bit 18 : Write '1' to enable interrupt for event ACKED[2] */
52061   #define IPCT_INTENSET6_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
52062   #define IPCT_INTENSET6_ACKED2_Msk (0x1UL << IPCT_INTENSET6_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
52063   #define IPCT_INTENSET6_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
52064   #define IPCT_INTENSET6_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
52065   #define IPCT_INTENSET6_ACKED2_Set (0x1UL)          /*!< Enable                                                               */
52066   #define IPCT_INTENSET6_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52067   #define IPCT_INTENSET6_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52068 
52069 /* ACKED3 @Bit 19 : Write '1' to enable interrupt for event ACKED[3] */
52070   #define IPCT_INTENSET6_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
52071   #define IPCT_INTENSET6_ACKED3_Msk (0x1UL << IPCT_INTENSET6_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
52072   #define IPCT_INTENSET6_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
52073   #define IPCT_INTENSET6_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
52074   #define IPCT_INTENSET6_ACKED3_Set (0x1UL)          /*!< Enable                                                               */
52075   #define IPCT_INTENSET6_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52076   #define IPCT_INTENSET6_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52077 
52078 /* ACKED4 @Bit 20 : Write '1' to enable interrupt for event ACKED[4] */
52079   #define IPCT_INTENSET6_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
52080   #define IPCT_INTENSET6_ACKED4_Msk (0x1UL << IPCT_INTENSET6_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
52081   #define IPCT_INTENSET6_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
52082   #define IPCT_INTENSET6_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
52083   #define IPCT_INTENSET6_ACKED4_Set (0x1UL)          /*!< Enable                                                               */
52084   #define IPCT_INTENSET6_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52085   #define IPCT_INTENSET6_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52086 
52087 /* ACKED5 @Bit 21 : Write '1' to enable interrupt for event ACKED[5] */
52088   #define IPCT_INTENSET6_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
52089   #define IPCT_INTENSET6_ACKED5_Msk (0x1UL << IPCT_INTENSET6_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
52090   #define IPCT_INTENSET6_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
52091   #define IPCT_INTENSET6_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
52092   #define IPCT_INTENSET6_ACKED5_Set (0x1UL)          /*!< Enable                                                               */
52093   #define IPCT_INTENSET6_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52094   #define IPCT_INTENSET6_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52095 
52096 /* ACKED6 @Bit 22 : Write '1' to enable interrupt for event ACKED[6] */
52097   #define IPCT_INTENSET6_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
52098   #define IPCT_INTENSET6_ACKED6_Msk (0x1UL << IPCT_INTENSET6_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
52099   #define IPCT_INTENSET6_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
52100   #define IPCT_INTENSET6_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
52101   #define IPCT_INTENSET6_ACKED6_Set (0x1UL)          /*!< Enable                                                               */
52102   #define IPCT_INTENSET6_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52103   #define IPCT_INTENSET6_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52104 
52105 /* ACKED7 @Bit 23 : Write '1' to enable interrupt for event ACKED[7] */
52106   #define IPCT_INTENSET6_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
52107   #define IPCT_INTENSET6_ACKED7_Msk (0x1UL << IPCT_INTENSET6_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
52108   #define IPCT_INTENSET6_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
52109   #define IPCT_INTENSET6_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
52110   #define IPCT_INTENSET6_ACKED7_Set (0x1UL)          /*!< Enable                                                               */
52111   #define IPCT_INTENSET6_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52112   #define IPCT_INTENSET6_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52113 
52114 /* ACKED8 @Bit 24 : Write '1' to enable interrupt for event ACKED[8] */
52115   #define IPCT_INTENSET6_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
52116   #define IPCT_INTENSET6_ACKED8_Msk (0x1UL << IPCT_INTENSET6_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
52117   #define IPCT_INTENSET6_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
52118   #define IPCT_INTENSET6_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
52119   #define IPCT_INTENSET6_ACKED8_Set (0x1UL)          /*!< Enable                                                               */
52120   #define IPCT_INTENSET6_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52121   #define IPCT_INTENSET6_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52122 
52123 /* ACKED9 @Bit 25 : Write '1' to enable interrupt for event ACKED[9] */
52124   #define IPCT_INTENSET6_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
52125   #define IPCT_INTENSET6_ACKED9_Msk (0x1UL << IPCT_INTENSET6_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
52126   #define IPCT_INTENSET6_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
52127   #define IPCT_INTENSET6_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
52128   #define IPCT_INTENSET6_ACKED9_Set (0x1UL)          /*!< Enable                                                               */
52129   #define IPCT_INTENSET6_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52130   #define IPCT_INTENSET6_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52131 
52132 /* ACKED10 @Bit 26 : Write '1' to enable interrupt for event ACKED[10] */
52133   #define IPCT_INTENSET6_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
52134   #define IPCT_INTENSET6_ACKED10_Msk (0x1UL << IPCT_INTENSET6_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
52135   #define IPCT_INTENSET6_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
52136   #define IPCT_INTENSET6_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
52137   #define IPCT_INTENSET6_ACKED10_Set (0x1UL)         /*!< Enable                                                               */
52138   #define IPCT_INTENSET6_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52139   #define IPCT_INTENSET6_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52140 
52141 /* ACKED11 @Bit 27 : Write '1' to enable interrupt for event ACKED[11] */
52142   #define IPCT_INTENSET6_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
52143   #define IPCT_INTENSET6_ACKED11_Msk (0x1UL << IPCT_INTENSET6_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
52144   #define IPCT_INTENSET6_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
52145   #define IPCT_INTENSET6_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
52146   #define IPCT_INTENSET6_ACKED11_Set (0x1UL)         /*!< Enable                                                               */
52147   #define IPCT_INTENSET6_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52148   #define IPCT_INTENSET6_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52149 
52150 /* ACKED12 @Bit 28 : Write '1' to enable interrupt for event ACKED[12] */
52151   #define IPCT_INTENSET6_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
52152   #define IPCT_INTENSET6_ACKED12_Msk (0x1UL << IPCT_INTENSET6_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
52153   #define IPCT_INTENSET6_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
52154   #define IPCT_INTENSET6_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
52155   #define IPCT_INTENSET6_ACKED12_Set (0x1UL)         /*!< Enable                                                               */
52156   #define IPCT_INTENSET6_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52157   #define IPCT_INTENSET6_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52158 
52159 /* ACKED13 @Bit 29 : Write '1' to enable interrupt for event ACKED[13] */
52160   #define IPCT_INTENSET6_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
52161   #define IPCT_INTENSET6_ACKED13_Msk (0x1UL << IPCT_INTENSET6_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
52162   #define IPCT_INTENSET6_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
52163   #define IPCT_INTENSET6_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
52164   #define IPCT_INTENSET6_ACKED13_Set (0x1UL)         /*!< Enable                                                               */
52165   #define IPCT_INTENSET6_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52166   #define IPCT_INTENSET6_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52167 
52168 /* ACKED14 @Bit 30 : Write '1' to enable interrupt for event ACKED[14] */
52169   #define IPCT_INTENSET6_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
52170   #define IPCT_INTENSET6_ACKED14_Msk (0x1UL << IPCT_INTENSET6_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
52171   #define IPCT_INTENSET6_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
52172   #define IPCT_INTENSET6_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
52173   #define IPCT_INTENSET6_ACKED14_Set (0x1UL)         /*!< Enable                                                               */
52174   #define IPCT_INTENSET6_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52175   #define IPCT_INTENSET6_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52176 
52177 /* ACKED15 @Bit 31 : Write '1' to enable interrupt for event ACKED[15] */
52178   #define IPCT_INTENSET6_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
52179   #define IPCT_INTENSET6_ACKED15_Msk (0x1UL << IPCT_INTENSET6_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
52180   #define IPCT_INTENSET6_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
52181   #define IPCT_INTENSET6_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
52182   #define IPCT_INTENSET6_ACKED15_Set (0x1UL)         /*!< Enable                                                               */
52183   #define IPCT_INTENSET6_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52184   #define IPCT_INTENSET6_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52185 
52186 
52187 /* IPCT_INTENCLR6: Disable interrupt */
52188   #define IPCT_INTENCLR6_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR6 register.                                   */
52189 
52190 /* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
52191   #define IPCT_INTENCLR6_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
52192   #define IPCT_INTENCLR6_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
52193   #define IPCT_INTENCLR6_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
52194   #define IPCT_INTENCLR6_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
52195   #define IPCT_INTENCLR6_RECEIVE0_Clear (0x1UL)      /*!< Disable                                                              */
52196   #define IPCT_INTENCLR6_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52197   #define IPCT_INTENCLR6_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52198 
52199 /* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
52200   #define IPCT_INTENCLR6_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
52201   #define IPCT_INTENCLR6_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
52202   #define IPCT_INTENCLR6_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
52203   #define IPCT_INTENCLR6_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
52204   #define IPCT_INTENCLR6_RECEIVE1_Clear (0x1UL)      /*!< Disable                                                              */
52205   #define IPCT_INTENCLR6_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52206   #define IPCT_INTENCLR6_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52207 
52208 /* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
52209   #define IPCT_INTENCLR6_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
52210   #define IPCT_INTENCLR6_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
52211   #define IPCT_INTENCLR6_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
52212   #define IPCT_INTENCLR6_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
52213   #define IPCT_INTENCLR6_RECEIVE2_Clear (0x1UL)      /*!< Disable                                                              */
52214   #define IPCT_INTENCLR6_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52215   #define IPCT_INTENCLR6_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52216 
52217 /* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
52218   #define IPCT_INTENCLR6_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
52219   #define IPCT_INTENCLR6_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
52220   #define IPCT_INTENCLR6_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
52221   #define IPCT_INTENCLR6_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
52222   #define IPCT_INTENCLR6_RECEIVE3_Clear (0x1UL)      /*!< Disable                                                              */
52223   #define IPCT_INTENCLR6_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52224   #define IPCT_INTENCLR6_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52225 
52226 /* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
52227   #define IPCT_INTENCLR6_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
52228   #define IPCT_INTENCLR6_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
52229   #define IPCT_INTENCLR6_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
52230   #define IPCT_INTENCLR6_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
52231   #define IPCT_INTENCLR6_RECEIVE4_Clear (0x1UL)      /*!< Disable                                                              */
52232   #define IPCT_INTENCLR6_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52233   #define IPCT_INTENCLR6_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52234 
52235 /* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
52236   #define IPCT_INTENCLR6_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
52237   #define IPCT_INTENCLR6_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
52238   #define IPCT_INTENCLR6_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
52239   #define IPCT_INTENCLR6_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
52240   #define IPCT_INTENCLR6_RECEIVE5_Clear (0x1UL)      /*!< Disable                                                              */
52241   #define IPCT_INTENCLR6_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52242   #define IPCT_INTENCLR6_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52243 
52244 /* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
52245   #define IPCT_INTENCLR6_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
52246   #define IPCT_INTENCLR6_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
52247   #define IPCT_INTENCLR6_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
52248   #define IPCT_INTENCLR6_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
52249   #define IPCT_INTENCLR6_RECEIVE6_Clear (0x1UL)      /*!< Disable                                                              */
52250   #define IPCT_INTENCLR6_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52251   #define IPCT_INTENCLR6_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52252 
52253 /* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
52254   #define IPCT_INTENCLR6_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
52255   #define IPCT_INTENCLR6_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
52256   #define IPCT_INTENCLR6_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
52257   #define IPCT_INTENCLR6_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
52258   #define IPCT_INTENCLR6_RECEIVE7_Clear (0x1UL)      /*!< Disable                                                              */
52259   #define IPCT_INTENCLR6_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52260   #define IPCT_INTENCLR6_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52261 
52262 /* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
52263   #define IPCT_INTENCLR6_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
52264   #define IPCT_INTENCLR6_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
52265   #define IPCT_INTENCLR6_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
52266   #define IPCT_INTENCLR6_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
52267   #define IPCT_INTENCLR6_RECEIVE8_Clear (0x1UL)      /*!< Disable                                                              */
52268   #define IPCT_INTENCLR6_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52269   #define IPCT_INTENCLR6_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52270 
52271 /* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
52272   #define IPCT_INTENCLR6_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
52273   #define IPCT_INTENCLR6_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
52274   #define IPCT_INTENCLR6_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
52275   #define IPCT_INTENCLR6_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
52276   #define IPCT_INTENCLR6_RECEIVE9_Clear (0x1UL)      /*!< Disable                                                              */
52277   #define IPCT_INTENCLR6_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
52278   #define IPCT_INTENCLR6_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
52279 
52280 /* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
52281   #define IPCT_INTENCLR6_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
52282   #define IPCT_INTENCLR6_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
52283   #define IPCT_INTENCLR6_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
52284   #define IPCT_INTENCLR6_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
52285   #define IPCT_INTENCLR6_RECEIVE10_Clear (0x1UL)     /*!< Disable                                                              */
52286   #define IPCT_INTENCLR6_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52287   #define IPCT_INTENCLR6_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52288 
52289 /* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
52290   #define IPCT_INTENCLR6_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
52291   #define IPCT_INTENCLR6_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
52292   #define IPCT_INTENCLR6_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
52293   #define IPCT_INTENCLR6_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
52294   #define IPCT_INTENCLR6_RECEIVE11_Clear (0x1UL)     /*!< Disable                                                              */
52295   #define IPCT_INTENCLR6_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52296   #define IPCT_INTENCLR6_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52297 
52298 /* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
52299   #define IPCT_INTENCLR6_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
52300   #define IPCT_INTENCLR6_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
52301   #define IPCT_INTENCLR6_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
52302   #define IPCT_INTENCLR6_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
52303   #define IPCT_INTENCLR6_RECEIVE12_Clear (0x1UL)     /*!< Disable                                                              */
52304   #define IPCT_INTENCLR6_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52305   #define IPCT_INTENCLR6_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52306 
52307 /* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
52308   #define IPCT_INTENCLR6_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
52309   #define IPCT_INTENCLR6_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
52310   #define IPCT_INTENCLR6_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
52311   #define IPCT_INTENCLR6_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
52312   #define IPCT_INTENCLR6_RECEIVE13_Clear (0x1UL)     /*!< Disable                                                              */
52313   #define IPCT_INTENCLR6_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52314   #define IPCT_INTENCLR6_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52315 
52316 /* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
52317   #define IPCT_INTENCLR6_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
52318   #define IPCT_INTENCLR6_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
52319   #define IPCT_INTENCLR6_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
52320   #define IPCT_INTENCLR6_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
52321   #define IPCT_INTENCLR6_RECEIVE14_Clear (0x1UL)     /*!< Disable                                                              */
52322   #define IPCT_INTENCLR6_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52323   #define IPCT_INTENCLR6_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52324 
52325 /* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
52326   #define IPCT_INTENCLR6_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
52327   #define IPCT_INTENCLR6_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR6_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
52328   #define IPCT_INTENCLR6_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
52329   #define IPCT_INTENCLR6_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
52330   #define IPCT_INTENCLR6_RECEIVE15_Clear (0x1UL)     /*!< Disable                                                              */
52331   #define IPCT_INTENCLR6_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
52332   #define IPCT_INTENCLR6_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
52333 
52334 /* ACKED0 @Bit 16 : Write '1' to disable interrupt for event ACKED[0] */
52335   #define IPCT_INTENCLR6_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
52336   #define IPCT_INTENCLR6_ACKED0_Msk (0x1UL << IPCT_INTENCLR6_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
52337   #define IPCT_INTENCLR6_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
52338   #define IPCT_INTENCLR6_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
52339   #define IPCT_INTENCLR6_ACKED0_Clear (0x1UL)        /*!< Disable                                                              */
52340   #define IPCT_INTENCLR6_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52341   #define IPCT_INTENCLR6_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52342 
52343 /* ACKED1 @Bit 17 : Write '1' to disable interrupt for event ACKED[1] */
52344   #define IPCT_INTENCLR6_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
52345   #define IPCT_INTENCLR6_ACKED1_Msk (0x1UL << IPCT_INTENCLR6_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
52346   #define IPCT_INTENCLR6_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
52347   #define IPCT_INTENCLR6_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
52348   #define IPCT_INTENCLR6_ACKED1_Clear (0x1UL)        /*!< Disable                                                              */
52349   #define IPCT_INTENCLR6_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52350   #define IPCT_INTENCLR6_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52351 
52352 /* ACKED2 @Bit 18 : Write '1' to disable interrupt for event ACKED[2] */
52353   #define IPCT_INTENCLR6_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
52354   #define IPCT_INTENCLR6_ACKED2_Msk (0x1UL << IPCT_INTENCLR6_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
52355   #define IPCT_INTENCLR6_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
52356   #define IPCT_INTENCLR6_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
52357   #define IPCT_INTENCLR6_ACKED2_Clear (0x1UL)        /*!< Disable                                                              */
52358   #define IPCT_INTENCLR6_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52359   #define IPCT_INTENCLR6_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52360 
52361 /* ACKED3 @Bit 19 : Write '1' to disable interrupt for event ACKED[3] */
52362   #define IPCT_INTENCLR6_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
52363   #define IPCT_INTENCLR6_ACKED3_Msk (0x1UL << IPCT_INTENCLR6_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
52364   #define IPCT_INTENCLR6_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
52365   #define IPCT_INTENCLR6_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
52366   #define IPCT_INTENCLR6_ACKED3_Clear (0x1UL)        /*!< Disable                                                              */
52367   #define IPCT_INTENCLR6_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52368   #define IPCT_INTENCLR6_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52369 
52370 /* ACKED4 @Bit 20 : Write '1' to disable interrupt for event ACKED[4] */
52371   #define IPCT_INTENCLR6_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
52372   #define IPCT_INTENCLR6_ACKED4_Msk (0x1UL << IPCT_INTENCLR6_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
52373   #define IPCT_INTENCLR6_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
52374   #define IPCT_INTENCLR6_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
52375   #define IPCT_INTENCLR6_ACKED4_Clear (0x1UL)        /*!< Disable                                                              */
52376   #define IPCT_INTENCLR6_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52377   #define IPCT_INTENCLR6_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52378 
52379 /* ACKED5 @Bit 21 : Write '1' to disable interrupt for event ACKED[5] */
52380   #define IPCT_INTENCLR6_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
52381   #define IPCT_INTENCLR6_ACKED5_Msk (0x1UL << IPCT_INTENCLR6_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
52382   #define IPCT_INTENCLR6_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
52383   #define IPCT_INTENCLR6_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
52384   #define IPCT_INTENCLR6_ACKED5_Clear (0x1UL)        /*!< Disable                                                              */
52385   #define IPCT_INTENCLR6_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52386   #define IPCT_INTENCLR6_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52387 
52388 /* ACKED6 @Bit 22 : Write '1' to disable interrupt for event ACKED[6] */
52389   #define IPCT_INTENCLR6_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
52390   #define IPCT_INTENCLR6_ACKED6_Msk (0x1UL << IPCT_INTENCLR6_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
52391   #define IPCT_INTENCLR6_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
52392   #define IPCT_INTENCLR6_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
52393   #define IPCT_INTENCLR6_ACKED6_Clear (0x1UL)        /*!< Disable                                                              */
52394   #define IPCT_INTENCLR6_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52395   #define IPCT_INTENCLR6_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52396 
52397 /* ACKED7 @Bit 23 : Write '1' to disable interrupt for event ACKED[7] */
52398   #define IPCT_INTENCLR6_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
52399   #define IPCT_INTENCLR6_ACKED7_Msk (0x1UL << IPCT_INTENCLR6_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
52400   #define IPCT_INTENCLR6_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
52401   #define IPCT_INTENCLR6_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
52402   #define IPCT_INTENCLR6_ACKED7_Clear (0x1UL)        /*!< Disable                                                              */
52403   #define IPCT_INTENCLR6_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52404   #define IPCT_INTENCLR6_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52405 
52406 /* ACKED8 @Bit 24 : Write '1' to disable interrupt for event ACKED[8] */
52407   #define IPCT_INTENCLR6_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
52408   #define IPCT_INTENCLR6_ACKED8_Msk (0x1UL << IPCT_INTENCLR6_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
52409   #define IPCT_INTENCLR6_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
52410   #define IPCT_INTENCLR6_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
52411   #define IPCT_INTENCLR6_ACKED8_Clear (0x1UL)        /*!< Disable                                                              */
52412   #define IPCT_INTENCLR6_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52413   #define IPCT_INTENCLR6_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52414 
52415 /* ACKED9 @Bit 25 : Write '1' to disable interrupt for event ACKED[9] */
52416   #define IPCT_INTENCLR6_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
52417   #define IPCT_INTENCLR6_ACKED9_Msk (0x1UL << IPCT_INTENCLR6_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
52418   #define IPCT_INTENCLR6_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
52419   #define IPCT_INTENCLR6_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
52420   #define IPCT_INTENCLR6_ACKED9_Clear (0x1UL)        /*!< Disable                                                              */
52421   #define IPCT_INTENCLR6_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
52422   #define IPCT_INTENCLR6_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
52423 
52424 /* ACKED10 @Bit 26 : Write '1' to disable interrupt for event ACKED[10] */
52425   #define IPCT_INTENCLR6_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
52426   #define IPCT_INTENCLR6_ACKED10_Msk (0x1UL << IPCT_INTENCLR6_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
52427   #define IPCT_INTENCLR6_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
52428   #define IPCT_INTENCLR6_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
52429   #define IPCT_INTENCLR6_ACKED10_Clear (0x1UL)       /*!< Disable                                                              */
52430   #define IPCT_INTENCLR6_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52431   #define IPCT_INTENCLR6_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52432 
52433 /* ACKED11 @Bit 27 : Write '1' to disable interrupt for event ACKED[11] */
52434   #define IPCT_INTENCLR6_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
52435   #define IPCT_INTENCLR6_ACKED11_Msk (0x1UL << IPCT_INTENCLR6_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
52436   #define IPCT_INTENCLR6_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
52437   #define IPCT_INTENCLR6_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
52438   #define IPCT_INTENCLR6_ACKED11_Clear (0x1UL)       /*!< Disable                                                              */
52439   #define IPCT_INTENCLR6_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52440   #define IPCT_INTENCLR6_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52441 
52442 /* ACKED12 @Bit 28 : Write '1' to disable interrupt for event ACKED[12] */
52443   #define IPCT_INTENCLR6_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
52444   #define IPCT_INTENCLR6_ACKED12_Msk (0x1UL << IPCT_INTENCLR6_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
52445   #define IPCT_INTENCLR6_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
52446   #define IPCT_INTENCLR6_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
52447   #define IPCT_INTENCLR6_ACKED12_Clear (0x1UL)       /*!< Disable                                                              */
52448   #define IPCT_INTENCLR6_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52449   #define IPCT_INTENCLR6_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52450 
52451 /* ACKED13 @Bit 29 : Write '1' to disable interrupt for event ACKED[13] */
52452   #define IPCT_INTENCLR6_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
52453   #define IPCT_INTENCLR6_ACKED13_Msk (0x1UL << IPCT_INTENCLR6_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
52454   #define IPCT_INTENCLR6_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
52455   #define IPCT_INTENCLR6_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
52456   #define IPCT_INTENCLR6_ACKED13_Clear (0x1UL)       /*!< Disable                                                              */
52457   #define IPCT_INTENCLR6_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52458   #define IPCT_INTENCLR6_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52459 
52460 /* ACKED14 @Bit 30 : Write '1' to disable interrupt for event ACKED[14] */
52461   #define IPCT_INTENCLR6_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
52462   #define IPCT_INTENCLR6_ACKED14_Msk (0x1UL << IPCT_INTENCLR6_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
52463   #define IPCT_INTENCLR6_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
52464   #define IPCT_INTENCLR6_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
52465   #define IPCT_INTENCLR6_ACKED14_Clear (0x1UL)       /*!< Disable                                                              */
52466   #define IPCT_INTENCLR6_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52467   #define IPCT_INTENCLR6_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52468 
52469 /* ACKED15 @Bit 31 : Write '1' to disable interrupt for event ACKED[15] */
52470   #define IPCT_INTENCLR6_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
52471   #define IPCT_INTENCLR6_ACKED15_Msk (0x1UL << IPCT_INTENCLR6_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
52472   #define IPCT_INTENCLR6_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
52473   #define IPCT_INTENCLR6_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
52474   #define IPCT_INTENCLR6_ACKED15_Clear (0x1UL)       /*!< Disable                                                              */
52475   #define IPCT_INTENCLR6_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
52476   #define IPCT_INTENCLR6_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
52477 
52478 
52479 /* IPCT_INTPEND6: Pending interrupts */
52480   #define IPCT_INTPEND6_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND6 register.                                    */
52481 
52482 /* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
52483   #define IPCT_INTPEND6_RECEIVE0_Pos (0UL)           /*!< Position of RECEIVE0 field.                                          */
52484   #define IPCT_INTPEND6_RECEIVE0_Msk (0x1UL << IPCT_INTPEND6_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                    */
52485   #define IPCT_INTPEND6_RECEIVE0_Min (0x0UL)         /*!< Min enumerator value of RECEIVE0 field.                              */
52486   #define IPCT_INTPEND6_RECEIVE0_Max (0x1UL)         /*!< Max enumerator value of RECEIVE0 field.                              */
52487   #define IPCT_INTPEND6_RECEIVE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52488   #define IPCT_INTPEND6_RECEIVE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
52489 
52490 /* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
52491   #define IPCT_INTPEND6_RECEIVE1_Pos (1UL)           /*!< Position of RECEIVE1 field.                                          */
52492   #define IPCT_INTPEND6_RECEIVE1_Msk (0x1UL << IPCT_INTPEND6_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                    */
52493   #define IPCT_INTPEND6_RECEIVE1_Min (0x0UL)         /*!< Min enumerator value of RECEIVE1 field.                              */
52494   #define IPCT_INTPEND6_RECEIVE1_Max (0x1UL)         /*!< Max enumerator value of RECEIVE1 field.                              */
52495   #define IPCT_INTPEND6_RECEIVE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52496   #define IPCT_INTPEND6_RECEIVE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
52497 
52498 /* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
52499   #define IPCT_INTPEND6_RECEIVE2_Pos (2UL)           /*!< Position of RECEIVE2 field.                                          */
52500   #define IPCT_INTPEND6_RECEIVE2_Msk (0x1UL << IPCT_INTPEND6_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                    */
52501   #define IPCT_INTPEND6_RECEIVE2_Min (0x0UL)         /*!< Min enumerator value of RECEIVE2 field.                              */
52502   #define IPCT_INTPEND6_RECEIVE2_Max (0x1UL)         /*!< Max enumerator value of RECEIVE2 field.                              */
52503   #define IPCT_INTPEND6_RECEIVE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52504   #define IPCT_INTPEND6_RECEIVE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
52505 
52506 /* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
52507   #define IPCT_INTPEND6_RECEIVE3_Pos (3UL)           /*!< Position of RECEIVE3 field.                                          */
52508   #define IPCT_INTPEND6_RECEIVE3_Msk (0x1UL << IPCT_INTPEND6_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                    */
52509   #define IPCT_INTPEND6_RECEIVE3_Min (0x0UL)         /*!< Min enumerator value of RECEIVE3 field.                              */
52510   #define IPCT_INTPEND6_RECEIVE3_Max (0x1UL)         /*!< Max enumerator value of RECEIVE3 field.                              */
52511   #define IPCT_INTPEND6_RECEIVE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52512   #define IPCT_INTPEND6_RECEIVE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
52513 
52514 /* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
52515   #define IPCT_INTPEND6_RECEIVE4_Pos (4UL)           /*!< Position of RECEIVE4 field.                                          */
52516   #define IPCT_INTPEND6_RECEIVE4_Msk (0x1UL << IPCT_INTPEND6_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                    */
52517   #define IPCT_INTPEND6_RECEIVE4_Min (0x0UL)         /*!< Min enumerator value of RECEIVE4 field.                              */
52518   #define IPCT_INTPEND6_RECEIVE4_Max (0x1UL)         /*!< Max enumerator value of RECEIVE4 field.                              */
52519   #define IPCT_INTPEND6_RECEIVE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52520   #define IPCT_INTPEND6_RECEIVE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
52521 
52522 /* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
52523   #define IPCT_INTPEND6_RECEIVE5_Pos (5UL)           /*!< Position of RECEIVE5 field.                                          */
52524   #define IPCT_INTPEND6_RECEIVE5_Msk (0x1UL << IPCT_INTPEND6_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                    */
52525   #define IPCT_INTPEND6_RECEIVE5_Min (0x0UL)         /*!< Min enumerator value of RECEIVE5 field.                              */
52526   #define IPCT_INTPEND6_RECEIVE5_Max (0x1UL)         /*!< Max enumerator value of RECEIVE5 field.                              */
52527   #define IPCT_INTPEND6_RECEIVE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52528   #define IPCT_INTPEND6_RECEIVE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
52529 
52530 /* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
52531   #define IPCT_INTPEND6_RECEIVE6_Pos (6UL)           /*!< Position of RECEIVE6 field.                                          */
52532   #define IPCT_INTPEND6_RECEIVE6_Msk (0x1UL << IPCT_INTPEND6_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                    */
52533   #define IPCT_INTPEND6_RECEIVE6_Min (0x0UL)         /*!< Min enumerator value of RECEIVE6 field.                              */
52534   #define IPCT_INTPEND6_RECEIVE6_Max (0x1UL)         /*!< Max enumerator value of RECEIVE6 field.                              */
52535   #define IPCT_INTPEND6_RECEIVE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52536   #define IPCT_INTPEND6_RECEIVE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
52537 
52538 /* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
52539   #define IPCT_INTPEND6_RECEIVE7_Pos (7UL)           /*!< Position of RECEIVE7 field.                                          */
52540   #define IPCT_INTPEND6_RECEIVE7_Msk (0x1UL << IPCT_INTPEND6_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                    */
52541   #define IPCT_INTPEND6_RECEIVE7_Min (0x0UL)         /*!< Min enumerator value of RECEIVE7 field.                              */
52542   #define IPCT_INTPEND6_RECEIVE7_Max (0x1UL)         /*!< Max enumerator value of RECEIVE7 field.                              */
52543   #define IPCT_INTPEND6_RECEIVE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52544   #define IPCT_INTPEND6_RECEIVE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
52545 
52546 /* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
52547   #define IPCT_INTPEND6_RECEIVE8_Pos (8UL)           /*!< Position of RECEIVE8 field.                                          */
52548   #define IPCT_INTPEND6_RECEIVE8_Msk (0x1UL << IPCT_INTPEND6_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                    */
52549   #define IPCT_INTPEND6_RECEIVE8_Min (0x0UL)         /*!< Min enumerator value of RECEIVE8 field.                              */
52550   #define IPCT_INTPEND6_RECEIVE8_Max (0x1UL)         /*!< Max enumerator value of RECEIVE8 field.                              */
52551   #define IPCT_INTPEND6_RECEIVE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52552   #define IPCT_INTPEND6_RECEIVE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
52553 
52554 /* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
52555   #define IPCT_INTPEND6_RECEIVE9_Pos (9UL)           /*!< Position of RECEIVE9 field.                                          */
52556   #define IPCT_INTPEND6_RECEIVE9_Msk (0x1UL << IPCT_INTPEND6_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                    */
52557   #define IPCT_INTPEND6_RECEIVE9_Min (0x0UL)         /*!< Min enumerator value of RECEIVE9 field.                              */
52558   #define IPCT_INTPEND6_RECEIVE9_Max (0x1UL)         /*!< Max enumerator value of RECEIVE9 field.                              */
52559   #define IPCT_INTPEND6_RECEIVE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
52560   #define IPCT_INTPEND6_RECEIVE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
52561 
52562 /* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
52563   #define IPCT_INTPEND6_RECEIVE10_Pos (10UL)         /*!< Position of RECEIVE10 field.                                         */
52564   #define IPCT_INTPEND6_RECEIVE10_Msk (0x1UL << IPCT_INTPEND6_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                 */
52565   #define IPCT_INTPEND6_RECEIVE10_Min (0x0UL)        /*!< Min enumerator value of RECEIVE10 field.                             */
52566   #define IPCT_INTPEND6_RECEIVE10_Max (0x1UL)        /*!< Max enumerator value of RECEIVE10 field.                             */
52567   #define IPCT_INTPEND6_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
52568   #define IPCT_INTPEND6_RECEIVE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
52569 
52570 /* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
52571   #define IPCT_INTPEND6_RECEIVE11_Pos (11UL)         /*!< Position of RECEIVE11 field.                                         */
52572   #define IPCT_INTPEND6_RECEIVE11_Msk (0x1UL << IPCT_INTPEND6_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                 */
52573   #define IPCT_INTPEND6_RECEIVE11_Min (0x0UL)        /*!< Min enumerator value of RECEIVE11 field.                             */
52574   #define IPCT_INTPEND6_RECEIVE11_Max (0x1UL)        /*!< Max enumerator value of RECEIVE11 field.                             */
52575   #define IPCT_INTPEND6_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
52576   #define IPCT_INTPEND6_RECEIVE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
52577 
52578 /* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
52579   #define IPCT_INTPEND6_RECEIVE12_Pos (12UL)         /*!< Position of RECEIVE12 field.                                         */
52580   #define IPCT_INTPEND6_RECEIVE12_Msk (0x1UL << IPCT_INTPEND6_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                 */
52581   #define IPCT_INTPEND6_RECEIVE12_Min (0x0UL)        /*!< Min enumerator value of RECEIVE12 field.                             */
52582   #define IPCT_INTPEND6_RECEIVE12_Max (0x1UL)        /*!< Max enumerator value of RECEIVE12 field.                             */
52583   #define IPCT_INTPEND6_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
52584   #define IPCT_INTPEND6_RECEIVE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
52585 
52586 /* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
52587   #define IPCT_INTPEND6_RECEIVE13_Pos (13UL)         /*!< Position of RECEIVE13 field.                                         */
52588   #define IPCT_INTPEND6_RECEIVE13_Msk (0x1UL << IPCT_INTPEND6_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                 */
52589   #define IPCT_INTPEND6_RECEIVE13_Min (0x0UL)        /*!< Min enumerator value of RECEIVE13 field.                             */
52590   #define IPCT_INTPEND6_RECEIVE13_Max (0x1UL)        /*!< Max enumerator value of RECEIVE13 field.                             */
52591   #define IPCT_INTPEND6_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
52592   #define IPCT_INTPEND6_RECEIVE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
52593 
52594 /* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
52595   #define IPCT_INTPEND6_RECEIVE14_Pos (14UL)         /*!< Position of RECEIVE14 field.                                         */
52596   #define IPCT_INTPEND6_RECEIVE14_Msk (0x1UL << IPCT_INTPEND6_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                 */
52597   #define IPCT_INTPEND6_RECEIVE14_Min (0x0UL)        /*!< Min enumerator value of RECEIVE14 field.                             */
52598   #define IPCT_INTPEND6_RECEIVE14_Max (0x1UL)        /*!< Max enumerator value of RECEIVE14 field.                             */
52599   #define IPCT_INTPEND6_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
52600   #define IPCT_INTPEND6_RECEIVE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
52601 
52602 /* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
52603   #define IPCT_INTPEND6_RECEIVE15_Pos (15UL)         /*!< Position of RECEIVE15 field.                                         */
52604   #define IPCT_INTPEND6_RECEIVE15_Msk (0x1UL << IPCT_INTPEND6_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                 */
52605   #define IPCT_INTPEND6_RECEIVE15_Min (0x0UL)        /*!< Min enumerator value of RECEIVE15 field.                             */
52606   #define IPCT_INTPEND6_RECEIVE15_Max (0x1UL)        /*!< Max enumerator value of RECEIVE15 field.                             */
52607   #define IPCT_INTPEND6_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
52608   #define IPCT_INTPEND6_RECEIVE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
52609 
52610 /* ACKED0 @Bit 16 : Read pending status of interrupt for event ACKED[0] */
52611   #define IPCT_INTPEND6_ACKED0_Pos (16UL)            /*!< Position of ACKED0 field.                                            */
52612   #define IPCT_INTPEND6_ACKED0_Msk (0x1UL << IPCT_INTPEND6_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                          */
52613   #define IPCT_INTPEND6_ACKED0_Min (0x0UL)           /*!< Min enumerator value of ACKED0 field.                                */
52614   #define IPCT_INTPEND6_ACKED0_Max (0x1UL)           /*!< Max enumerator value of ACKED0 field.                                */
52615   #define IPCT_INTPEND6_ACKED0_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52616   #define IPCT_INTPEND6_ACKED0_Pending (0x1UL)       /*!< Read: Pending                                                        */
52617 
52618 /* ACKED1 @Bit 17 : Read pending status of interrupt for event ACKED[1] */
52619   #define IPCT_INTPEND6_ACKED1_Pos (17UL)            /*!< Position of ACKED1 field.                                            */
52620   #define IPCT_INTPEND6_ACKED1_Msk (0x1UL << IPCT_INTPEND6_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                          */
52621   #define IPCT_INTPEND6_ACKED1_Min (0x0UL)           /*!< Min enumerator value of ACKED1 field.                                */
52622   #define IPCT_INTPEND6_ACKED1_Max (0x1UL)           /*!< Max enumerator value of ACKED1 field.                                */
52623   #define IPCT_INTPEND6_ACKED1_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52624   #define IPCT_INTPEND6_ACKED1_Pending (0x1UL)       /*!< Read: Pending                                                        */
52625 
52626 /* ACKED2 @Bit 18 : Read pending status of interrupt for event ACKED[2] */
52627   #define IPCT_INTPEND6_ACKED2_Pos (18UL)            /*!< Position of ACKED2 field.                                            */
52628   #define IPCT_INTPEND6_ACKED2_Msk (0x1UL << IPCT_INTPEND6_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                          */
52629   #define IPCT_INTPEND6_ACKED2_Min (0x0UL)           /*!< Min enumerator value of ACKED2 field.                                */
52630   #define IPCT_INTPEND6_ACKED2_Max (0x1UL)           /*!< Max enumerator value of ACKED2 field.                                */
52631   #define IPCT_INTPEND6_ACKED2_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52632   #define IPCT_INTPEND6_ACKED2_Pending (0x1UL)       /*!< Read: Pending                                                        */
52633 
52634 /* ACKED3 @Bit 19 : Read pending status of interrupt for event ACKED[3] */
52635   #define IPCT_INTPEND6_ACKED3_Pos (19UL)            /*!< Position of ACKED3 field.                                            */
52636   #define IPCT_INTPEND6_ACKED3_Msk (0x1UL << IPCT_INTPEND6_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                          */
52637   #define IPCT_INTPEND6_ACKED3_Min (0x0UL)           /*!< Min enumerator value of ACKED3 field.                                */
52638   #define IPCT_INTPEND6_ACKED3_Max (0x1UL)           /*!< Max enumerator value of ACKED3 field.                                */
52639   #define IPCT_INTPEND6_ACKED3_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52640   #define IPCT_INTPEND6_ACKED3_Pending (0x1UL)       /*!< Read: Pending                                                        */
52641 
52642 /* ACKED4 @Bit 20 : Read pending status of interrupt for event ACKED[4] */
52643   #define IPCT_INTPEND6_ACKED4_Pos (20UL)            /*!< Position of ACKED4 field.                                            */
52644   #define IPCT_INTPEND6_ACKED4_Msk (0x1UL << IPCT_INTPEND6_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                          */
52645   #define IPCT_INTPEND6_ACKED4_Min (0x0UL)           /*!< Min enumerator value of ACKED4 field.                                */
52646   #define IPCT_INTPEND6_ACKED4_Max (0x1UL)           /*!< Max enumerator value of ACKED4 field.                                */
52647   #define IPCT_INTPEND6_ACKED4_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52648   #define IPCT_INTPEND6_ACKED4_Pending (0x1UL)       /*!< Read: Pending                                                        */
52649 
52650 /* ACKED5 @Bit 21 : Read pending status of interrupt for event ACKED[5] */
52651   #define IPCT_INTPEND6_ACKED5_Pos (21UL)            /*!< Position of ACKED5 field.                                            */
52652   #define IPCT_INTPEND6_ACKED5_Msk (0x1UL << IPCT_INTPEND6_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                          */
52653   #define IPCT_INTPEND6_ACKED5_Min (0x0UL)           /*!< Min enumerator value of ACKED5 field.                                */
52654   #define IPCT_INTPEND6_ACKED5_Max (0x1UL)           /*!< Max enumerator value of ACKED5 field.                                */
52655   #define IPCT_INTPEND6_ACKED5_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52656   #define IPCT_INTPEND6_ACKED5_Pending (0x1UL)       /*!< Read: Pending                                                        */
52657 
52658 /* ACKED6 @Bit 22 : Read pending status of interrupt for event ACKED[6] */
52659   #define IPCT_INTPEND6_ACKED6_Pos (22UL)            /*!< Position of ACKED6 field.                                            */
52660   #define IPCT_INTPEND6_ACKED6_Msk (0x1UL << IPCT_INTPEND6_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                          */
52661   #define IPCT_INTPEND6_ACKED6_Min (0x0UL)           /*!< Min enumerator value of ACKED6 field.                                */
52662   #define IPCT_INTPEND6_ACKED6_Max (0x1UL)           /*!< Max enumerator value of ACKED6 field.                                */
52663   #define IPCT_INTPEND6_ACKED6_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52664   #define IPCT_INTPEND6_ACKED6_Pending (0x1UL)       /*!< Read: Pending                                                        */
52665 
52666 /* ACKED7 @Bit 23 : Read pending status of interrupt for event ACKED[7] */
52667   #define IPCT_INTPEND6_ACKED7_Pos (23UL)            /*!< Position of ACKED7 field.                                            */
52668   #define IPCT_INTPEND6_ACKED7_Msk (0x1UL << IPCT_INTPEND6_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                          */
52669   #define IPCT_INTPEND6_ACKED7_Min (0x0UL)           /*!< Min enumerator value of ACKED7 field.                                */
52670   #define IPCT_INTPEND6_ACKED7_Max (0x1UL)           /*!< Max enumerator value of ACKED7 field.                                */
52671   #define IPCT_INTPEND6_ACKED7_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52672   #define IPCT_INTPEND6_ACKED7_Pending (0x1UL)       /*!< Read: Pending                                                        */
52673 
52674 /* ACKED8 @Bit 24 : Read pending status of interrupt for event ACKED[8] */
52675   #define IPCT_INTPEND6_ACKED8_Pos (24UL)            /*!< Position of ACKED8 field.                                            */
52676   #define IPCT_INTPEND6_ACKED8_Msk (0x1UL << IPCT_INTPEND6_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                          */
52677   #define IPCT_INTPEND6_ACKED8_Min (0x0UL)           /*!< Min enumerator value of ACKED8 field.                                */
52678   #define IPCT_INTPEND6_ACKED8_Max (0x1UL)           /*!< Max enumerator value of ACKED8 field.                                */
52679   #define IPCT_INTPEND6_ACKED8_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52680   #define IPCT_INTPEND6_ACKED8_Pending (0x1UL)       /*!< Read: Pending                                                        */
52681 
52682 /* ACKED9 @Bit 25 : Read pending status of interrupt for event ACKED[9] */
52683   #define IPCT_INTPEND6_ACKED9_Pos (25UL)            /*!< Position of ACKED9 field.                                            */
52684   #define IPCT_INTPEND6_ACKED9_Msk (0x1UL << IPCT_INTPEND6_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                          */
52685   #define IPCT_INTPEND6_ACKED9_Min (0x0UL)           /*!< Min enumerator value of ACKED9 field.                                */
52686   #define IPCT_INTPEND6_ACKED9_Max (0x1UL)           /*!< Max enumerator value of ACKED9 field.                                */
52687   #define IPCT_INTPEND6_ACKED9_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
52688   #define IPCT_INTPEND6_ACKED9_Pending (0x1UL)       /*!< Read: Pending                                                        */
52689 
52690 /* ACKED10 @Bit 26 : Read pending status of interrupt for event ACKED[10] */
52691   #define IPCT_INTPEND6_ACKED10_Pos (26UL)           /*!< Position of ACKED10 field.                                           */
52692   #define IPCT_INTPEND6_ACKED10_Msk (0x1UL << IPCT_INTPEND6_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                       */
52693   #define IPCT_INTPEND6_ACKED10_Min (0x0UL)          /*!< Min enumerator value of ACKED10 field.                               */
52694   #define IPCT_INTPEND6_ACKED10_Max (0x1UL)          /*!< Max enumerator value of ACKED10 field.                               */
52695   #define IPCT_INTPEND6_ACKED10_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
52696   #define IPCT_INTPEND6_ACKED10_Pending (0x1UL)      /*!< Read: Pending                                                        */
52697 
52698 /* ACKED11 @Bit 27 : Read pending status of interrupt for event ACKED[11] */
52699   #define IPCT_INTPEND6_ACKED11_Pos (27UL)           /*!< Position of ACKED11 field.                                           */
52700   #define IPCT_INTPEND6_ACKED11_Msk (0x1UL << IPCT_INTPEND6_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                       */
52701   #define IPCT_INTPEND6_ACKED11_Min (0x0UL)          /*!< Min enumerator value of ACKED11 field.                               */
52702   #define IPCT_INTPEND6_ACKED11_Max (0x1UL)          /*!< Max enumerator value of ACKED11 field.                               */
52703   #define IPCT_INTPEND6_ACKED11_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
52704   #define IPCT_INTPEND6_ACKED11_Pending (0x1UL)      /*!< Read: Pending                                                        */
52705 
52706 /* ACKED12 @Bit 28 : Read pending status of interrupt for event ACKED[12] */
52707   #define IPCT_INTPEND6_ACKED12_Pos (28UL)           /*!< Position of ACKED12 field.                                           */
52708   #define IPCT_INTPEND6_ACKED12_Msk (0x1UL << IPCT_INTPEND6_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                       */
52709   #define IPCT_INTPEND6_ACKED12_Min (0x0UL)          /*!< Min enumerator value of ACKED12 field.                               */
52710   #define IPCT_INTPEND6_ACKED12_Max (0x1UL)          /*!< Max enumerator value of ACKED12 field.                               */
52711   #define IPCT_INTPEND6_ACKED12_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
52712   #define IPCT_INTPEND6_ACKED12_Pending (0x1UL)      /*!< Read: Pending                                                        */
52713 
52714 /* ACKED13 @Bit 29 : Read pending status of interrupt for event ACKED[13] */
52715   #define IPCT_INTPEND6_ACKED13_Pos (29UL)           /*!< Position of ACKED13 field.                                           */
52716   #define IPCT_INTPEND6_ACKED13_Msk (0x1UL << IPCT_INTPEND6_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                       */
52717   #define IPCT_INTPEND6_ACKED13_Min (0x0UL)          /*!< Min enumerator value of ACKED13 field.                               */
52718   #define IPCT_INTPEND6_ACKED13_Max (0x1UL)          /*!< Max enumerator value of ACKED13 field.                               */
52719   #define IPCT_INTPEND6_ACKED13_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
52720   #define IPCT_INTPEND6_ACKED13_Pending (0x1UL)      /*!< Read: Pending                                                        */
52721 
52722 /* ACKED14 @Bit 30 : Read pending status of interrupt for event ACKED[14] */
52723   #define IPCT_INTPEND6_ACKED14_Pos (30UL)           /*!< Position of ACKED14 field.                                           */
52724   #define IPCT_INTPEND6_ACKED14_Msk (0x1UL << IPCT_INTPEND6_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                       */
52725   #define IPCT_INTPEND6_ACKED14_Min (0x0UL)          /*!< Min enumerator value of ACKED14 field.                               */
52726   #define IPCT_INTPEND6_ACKED14_Max (0x1UL)          /*!< Max enumerator value of ACKED14 field.                               */
52727   #define IPCT_INTPEND6_ACKED14_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
52728   #define IPCT_INTPEND6_ACKED14_Pending (0x1UL)      /*!< Read: Pending                                                        */
52729 
52730 /* ACKED15 @Bit 31 : Read pending status of interrupt for event ACKED[15] */
52731   #define IPCT_INTPEND6_ACKED15_Pos (31UL)           /*!< Position of ACKED15 field.                                           */
52732   #define IPCT_INTPEND6_ACKED15_Msk (0x1UL << IPCT_INTPEND6_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                       */
52733   #define IPCT_INTPEND6_ACKED15_Min (0x0UL)          /*!< Min enumerator value of ACKED15 field.                               */
52734   #define IPCT_INTPEND6_ACKED15_Max (0x1UL)          /*!< Max enumerator value of ACKED15 field.                               */
52735   #define IPCT_INTPEND6_ACKED15_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
52736   #define IPCT_INTPEND6_ACKED15_Pending (0x1UL)      /*!< Read: Pending                                                        */
52737 
52738 
52739 /* IPCT_INTEN7: Enable or disable interrupt */
52740   #define IPCT_INTEN7_ResetValue (0x00000000UL)      /*!< Reset value of INTEN7 register.                                      */
52741 
52742 /* RECEIVE0 @Bit 0 : Enable or disable interrupt for event RECEIVE[0] */
52743   #define IPCT_INTEN7_RECEIVE0_Pos (0UL)             /*!< Position of RECEIVE0 field.                                          */
52744   #define IPCT_INTEN7_RECEIVE0_Msk (0x1UL << IPCT_INTEN7_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                        */
52745   #define IPCT_INTEN7_RECEIVE0_Min (0x0UL)           /*!< Min enumerator value of RECEIVE0 field.                              */
52746   #define IPCT_INTEN7_RECEIVE0_Max (0x1UL)           /*!< Max enumerator value of RECEIVE0 field.                              */
52747   #define IPCT_INTEN7_RECEIVE0_Disabled (0x0UL)      /*!< Disable                                                              */
52748   #define IPCT_INTEN7_RECEIVE0_Enabled (0x1UL)       /*!< Enable                                                               */
52749 
52750 /* RECEIVE1 @Bit 1 : Enable or disable interrupt for event RECEIVE[1] */
52751   #define IPCT_INTEN7_RECEIVE1_Pos (1UL)             /*!< Position of RECEIVE1 field.                                          */
52752   #define IPCT_INTEN7_RECEIVE1_Msk (0x1UL << IPCT_INTEN7_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                        */
52753   #define IPCT_INTEN7_RECEIVE1_Min (0x0UL)           /*!< Min enumerator value of RECEIVE1 field.                              */
52754   #define IPCT_INTEN7_RECEIVE1_Max (0x1UL)           /*!< Max enumerator value of RECEIVE1 field.                              */
52755   #define IPCT_INTEN7_RECEIVE1_Disabled (0x0UL)      /*!< Disable                                                              */
52756   #define IPCT_INTEN7_RECEIVE1_Enabled (0x1UL)       /*!< Enable                                                               */
52757 
52758 /* RECEIVE2 @Bit 2 : Enable or disable interrupt for event RECEIVE[2] */
52759   #define IPCT_INTEN7_RECEIVE2_Pos (2UL)             /*!< Position of RECEIVE2 field.                                          */
52760   #define IPCT_INTEN7_RECEIVE2_Msk (0x1UL << IPCT_INTEN7_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                        */
52761   #define IPCT_INTEN7_RECEIVE2_Min (0x0UL)           /*!< Min enumerator value of RECEIVE2 field.                              */
52762   #define IPCT_INTEN7_RECEIVE2_Max (0x1UL)           /*!< Max enumerator value of RECEIVE2 field.                              */
52763   #define IPCT_INTEN7_RECEIVE2_Disabled (0x0UL)      /*!< Disable                                                              */
52764   #define IPCT_INTEN7_RECEIVE2_Enabled (0x1UL)       /*!< Enable                                                               */
52765 
52766 /* RECEIVE3 @Bit 3 : Enable or disable interrupt for event RECEIVE[3] */
52767   #define IPCT_INTEN7_RECEIVE3_Pos (3UL)             /*!< Position of RECEIVE3 field.                                          */
52768   #define IPCT_INTEN7_RECEIVE3_Msk (0x1UL << IPCT_INTEN7_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                        */
52769   #define IPCT_INTEN7_RECEIVE3_Min (0x0UL)           /*!< Min enumerator value of RECEIVE3 field.                              */
52770   #define IPCT_INTEN7_RECEIVE3_Max (0x1UL)           /*!< Max enumerator value of RECEIVE3 field.                              */
52771   #define IPCT_INTEN7_RECEIVE3_Disabled (0x0UL)      /*!< Disable                                                              */
52772   #define IPCT_INTEN7_RECEIVE3_Enabled (0x1UL)       /*!< Enable                                                               */
52773 
52774 /* RECEIVE4 @Bit 4 : Enable or disable interrupt for event RECEIVE[4] */
52775   #define IPCT_INTEN7_RECEIVE4_Pos (4UL)             /*!< Position of RECEIVE4 field.                                          */
52776   #define IPCT_INTEN7_RECEIVE4_Msk (0x1UL << IPCT_INTEN7_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                        */
52777   #define IPCT_INTEN7_RECEIVE4_Min (0x0UL)           /*!< Min enumerator value of RECEIVE4 field.                              */
52778   #define IPCT_INTEN7_RECEIVE4_Max (0x1UL)           /*!< Max enumerator value of RECEIVE4 field.                              */
52779   #define IPCT_INTEN7_RECEIVE4_Disabled (0x0UL)      /*!< Disable                                                              */
52780   #define IPCT_INTEN7_RECEIVE4_Enabled (0x1UL)       /*!< Enable                                                               */
52781 
52782 /* RECEIVE5 @Bit 5 : Enable or disable interrupt for event RECEIVE[5] */
52783   #define IPCT_INTEN7_RECEIVE5_Pos (5UL)             /*!< Position of RECEIVE5 field.                                          */
52784   #define IPCT_INTEN7_RECEIVE5_Msk (0x1UL << IPCT_INTEN7_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                        */
52785   #define IPCT_INTEN7_RECEIVE5_Min (0x0UL)           /*!< Min enumerator value of RECEIVE5 field.                              */
52786   #define IPCT_INTEN7_RECEIVE5_Max (0x1UL)           /*!< Max enumerator value of RECEIVE5 field.                              */
52787   #define IPCT_INTEN7_RECEIVE5_Disabled (0x0UL)      /*!< Disable                                                              */
52788   #define IPCT_INTEN7_RECEIVE5_Enabled (0x1UL)       /*!< Enable                                                               */
52789 
52790 /* RECEIVE6 @Bit 6 : Enable or disable interrupt for event RECEIVE[6] */
52791   #define IPCT_INTEN7_RECEIVE6_Pos (6UL)             /*!< Position of RECEIVE6 field.                                          */
52792   #define IPCT_INTEN7_RECEIVE6_Msk (0x1UL << IPCT_INTEN7_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                        */
52793   #define IPCT_INTEN7_RECEIVE6_Min (0x0UL)           /*!< Min enumerator value of RECEIVE6 field.                              */
52794   #define IPCT_INTEN7_RECEIVE6_Max (0x1UL)           /*!< Max enumerator value of RECEIVE6 field.                              */
52795   #define IPCT_INTEN7_RECEIVE6_Disabled (0x0UL)      /*!< Disable                                                              */
52796   #define IPCT_INTEN7_RECEIVE6_Enabled (0x1UL)       /*!< Enable                                                               */
52797 
52798 /* RECEIVE7 @Bit 7 : Enable or disable interrupt for event RECEIVE[7] */
52799   #define IPCT_INTEN7_RECEIVE7_Pos (7UL)             /*!< Position of RECEIVE7 field.                                          */
52800   #define IPCT_INTEN7_RECEIVE7_Msk (0x1UL << IPCT_INTEN7_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                        */
52801   #define IPCT_INTEN7_RECEIVE7_Min (0x0UL)           /*!< Min enumerator value of RECEIVE7 field.                              */
52802   #define IPCT_INTEN7_RECEIVE7_Max (0x1UL)           /*!< Max enumerator value of RECEIVE7 field.                              */
52803   #define IPCT_INTEN7_RECEIVE7_Disabled (0x0UL)      /*!< Disable                                                              */
52804   #define IPCT_INTEN7_RECEIVE7_Enabled (0x1UL)       /*!< Enable                                                               */
52805 
52806 /* RECEIVE8 @Bit 8 : Enable or disable interrupt for event RECEIVE[8] */
52807   #define IPCT_INTEN7_RECEIVE8_Pos (8UL)             /*!< Position of RECEIVE8 field.                                          */
52808   #define IPCT_INTEN7_RECEIVE8_Msk (0x1UL << IPCT_INTEN7_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                        */
52809   #define IPCT_INTEN7_RECEIVE8_Min (0x0UL)           /*!< Min enumerator value of RECEIVE8 field.                              */
52810   #define IPCT_INTEN7_RECEIVE8_Max (0x1UL)           /*!< Max enumerator value of RECEIVE8 field.                              */
52811   #define IPCT_INTEN7_RECEIVE8_Disabled (0x0UL)      /*!< Disable                                                              */
52812   #define IPCT_INTEN7_RECEIVE8_Enabled (0x1UL)       /*!< Enable                                                               */
52813 
52814 /* RECEIVE9 @Bit 9 : Enable or disable interrupt for event RECEIVE[9] */
52815   #define IPCT_INTEN7_RECEIVE9_Pos (9UL)             /*!< Position of RECEIVE9 field.                                          */
52816   #define IPCT_INTEN7_RECEIVE9_Msk (0x1UL << IPCT_INTEN7_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                        */
52817   #define IPCT_INTEN7_RECEIVE9_Min (0x0UL)           /*!< Min enumerator value of RECEIVE9 field.                              */
52818   #define IPCT_INTEN7_RECEIVE9_Max (0x1UL)           /*!< Max enumerator value of RECEIVE9 field.                              */
52819   #define IPCT_INTEN7_RECEIVE9_Disabled (0x0UL)      /*!< Disable                                                              */
52820   #define IPCT_INTEN7_RECEIVE9_Enabled (0x1UL)       /*!< Enable                                                               */
52821 
52822 /* RECEIVE10 @Bit 10 : Enable or disable interrupt for event RECEIVE[10] */
52823   #define IPCT_INTEN7_RECEIVE10_Pos (10UL)           /*!< Position of RECEIVE10 field.                                         */
52824   #define IPCT_INTEN7_RECEIVE10_Msk (0x1UL << IPCT_INTEN7_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                     */
52825   #define IPCT_INTEN7_RECEIVE10_Min (0x0UL)          /*!< Min enumerator value of RECEIVE10 field.                             */
52826   #define IPCT_INTEN7_RECEIVE10_Max (0x1UL)          /*!< Max enumerator value of RECEIVE10 field.                             */
52827   #define IPCT_INTEN7_RECEIVE10_Disabled (0x0UL)     /*!< Disable                                                              */
52828   #define IPCT_INTEN7_RECEIVE10_Enabled (0x1UL)      /*!< Enable                                                               */
52829 
52830 /* RECEIVE11 @Bit 11 : Enable or disable interrupt for event RECEIVE[11] */
52831   #define IPCT_INTEN7_RECEIVE11_Pos (11UL)           /*!< Position of RECEIVE11 field.                                         */
52832   #define IPCT_INTEN7_RECEIVE11_Msk (0x1UL << IPCT_INTEN7_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                     */
52833   #define IPCT_INTEN7_RECEIVE11_Min (0x0UL)          /*!< Min enumerator value of RECEIVE11 field.                             */
52834   #define IPCT_INTEN7_RECEIVE11_Max (0x1UL)          /*!< Max enumerator value of RECEIVE11 field.                             */
52835   #define IPCT_INTEN7_RECEIVE11_Disabled (0x0UL)     /*!< Disable                                                              */
52836   #define IPCT_INTEN7_RECEIVE11_Enabled (0x1UL)      /*!< Enable                                                               */
52837 
52838 /* RECEIVE12 @Bit 12 : Enable or disable interrupt for event RECEIVE[12] */
52839   #define IPCT_INTEN7_RECEIVE12_Pos (12UL)           /*!< Position of RECEIVE12 field.                                         */
52840   #define IPCT_INTEN7_RECEIVE12_Msk (0x1UL << IPCT_INTEN7_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                     */
52841   #define IPCT_INTEN7_RECEIVE12_Min (0x0UL)          /*!< Min enumerator value of RECEIVE12 field.                             */
52842   #define IPCT_INTEN7_RECEIVE12_Max (0x1UL)          /*!< Max enumerator value of RECEIVE12 field.                             */
52843   #define IPCT_INTEN7_RECEIVE12_Disabled (0x0UL)     /*!< Disable                                                              */
52844   #define IPCT_INTEN7_RECEIVE12_Enabled (0x1UL)      /*!< Enable                                                               */
52845 
52846 /* RECEIVE13 @Bit 13 : Enable or disable interrupt for event RECEIVE[13] */
52847   #define IPCT_INTEN7_RECEIVE13_Pos (13UL)           /*!< Position of RECEIVE13 field.                                         */
52848   #define IPCT_INTEN7_RECEIVE13_Msk (0x1UL << IPCT_INTEN7_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                     */
52849   #define IPCT_INTEN7_RECEIVE13_Min (0x0UL)          /*!< Min enumerator value of RECEIVE13 field.                             */
52850   #define IPCT_INTEN7_RECEIVE13_Max (0x1UL)          /*!< Max enumerator value of RECEIVE13 field.                             */
52851   #define IPCT_INTEN7_RECEIVE13_Disabled (0x0UL)     /*!< Disable                                                              */
52852   #define IPCT_INTEN7_RECEIVE13_Enabled (0x1UL)      /*!< Enable                                                               */
52853 
52854 /* RECEIVE14 @Bit 14 : Enable or disable interrupt for event RECEIVE[14] */
52855   #define IPCT_INTEN7_RECEIVE14_Pos (14UL)           /*!< Position of RECEIVE14 field.                                         */
52856   #define IPCT_INTEN7_RECEIVE14_Msk (0x1UL << IPCT_INTEN7_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                     */
52857   #define IPCT_INTEN7_RECEIVE14_Min (0x0UL)          /*!< Min enumerator value of RECEIVE14 field.                             */
52858   #define IPCT_INTEN7_RECEIVE14_Max (0x1UL)          /*!< Max enumerator value of RECEIVE14 field.                             */
52859   #define IPCT_INTEN7_RECEIVE14_Disabled (0x0UL)     /*!< Disable                                                              */
52860   #define IPCT_INTEN7_RECEIVE14_Enabled (0x1UL)      /*!< Enable                                                               */
52861 
52862 /* RECEIVE15 @Bit 15 : Enable or disable interrupt for event RECEIVE[15] */
52863   #define IPCT_INTEN7_RECEIVE15_Pos (15UL)           /*!< Position of RECEIVE15 field.                                         */
52864   #define IPCT_INTEN7_RECEIVE15_Msk (0x1UL << IPCT_INTEN7_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                     */
52865   #define IPCT_INTEN7_RECEIVE15_Min (0x0UL)          /*!< Min enumerator value of RECEIVE15 field.                             */
52866   #define IPCT_INTEN7_RECEIVE15_Max (0x1UL)          /*!< Max enumerator value of RECEIVE15 field.                             */
52867   #define IPCT_INTEN7_RECEIVE15_Disabled (0x0UL)     /*!< Disable                                                              */
52868   #define IPCT_INTEN7_RECEIVE15_Enabled (0x1UL)      /*!< Enable                                                               */
52869 
52870 /* ACKED0 @Bit 16 : Enable or disable interrupt for event ACKED[0] */
52871   #define IPCT_INTEN7_ACKED0_Pos (16UL)              /*!< Position of ACKED0 field.                                            */
52872   #define IPCT_INTEN7_ACKED0_Msk (0x1UL << IPCT_INTEN7_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                              */
52873   #define IPCT_INTEN7_ACKED0_Min (0x0UL)             /*!< Min enumerator value of ACKED0 field.                                */
52874   #define IPCT_INTEN7_ACKED0_Max (0x1UL)             /*!< Max enumerator value of ACKED0 field.                                */
52875   #define IPCT_INTEN7_ACKED0_Disabled (0x0UL)        /*!< Disable                                                              */
52876   #define IPCT_INTEN7_ACKED0_Enabled (0x1UL)         /*!< Enable                                                               */
52877 
52878 /* ACKED1 @Bit 17 : Enable or disable interrupt for event ACKED[1] */
52879   #define IPCT_INTEN7_ACKED1_Pos (17UL)              /*!< Position of ACKED1 field.                                            */
52880   #define IPCT_INTEN7_ACKED1_Msk (0x1UL << IPCT_INTEN7_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                              */
52881   #define IPCT_INTEN7_ACKED1_Min (0x0UL)             /*!< Min enumerator value of ACKED1 field.                                */
52882   #define IPCT_INTEN7_ACKED1_Max (0x1UL)             /*!< Max enumerator value of ACKED1 field.                                */
52883   #define IPCT_INTEN7_ACKED1_Disabled (0x0UL)        /*!< Disable                                                              */
52884   #define IPCT_INTEN7_ACKED1_Enabled (0x1UL)         /*!< Enable                                                               */
52885 
52886 /* ACKED2 @Bit 18 : Enable or disable interrupt for event ACKED[2] */
52887   #define IPCT_INTEN7_ACKED2_Pos (18UL)              /*!< Position of ACKED2 field.                                            */
52888   #define IPCT_INTEN7_ACKED2_Msk (0x1UL << IPCT_INTEN7_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                              */
52889   #define IPCT_INTEN7_ACKED2_Min (0x0UL)             /*!< Min enumerator value of ACKED2 field.                                */
52890   #define IPCT_INTEN7_ACKED2_Max (0x1UL)             /*!< Max enumerator value of ACKED2 field.                                */
52891   #define IPCT_INTEN7_ACKED2_Disabled (0x0UL)        /*!< Disable                                                              */
52892   #define IPCT_INTEN7_ACKED2_Enabled (0x1UL)         /*!< Enable                                                               */
52893 
52894 /* ACKED3 @Bit 19 : Enable or disable interrupt for event ACKED[3] */
52895   #define IPCT_INTEN7_ACKED3_Pos (19UL)              /*!< Position of ACKED3 field.                                            */
52896   #define IPCT_INTEN7_ACKED3_Msk (0x1UL << IPCT_INTEN7_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                              */
52897   #define IPCT_INTEN7_ACKED3_Min (0x0UL)             /*!< Min enumerator value of ACKED3 field.                                */
52898   #define IPCT_INTEN7_ACKED3_Max (0x1UL)             /*!< Max enumerator value of ACKED3 field.                                */
52899   #define IPCT_INTEN7_ACKED3_Disabled (0x0UL)        /*!< Disable                                                              */
52900   #define IPCT_INTEN7_ACKED3_Enabled (0x1UL)         /*!< Enable                                                               */
52901 
52902 /* ACKED4 @Bit 20 : Enable or disable interrupt for event ACKED[4] */
52903   #define IPCT_INTEN7_ACKED4_Pos (20UL)              /*!< Position of ACKED4 field.                                            */
52904   #define IPCT_INTEN7_ACKED4_Msk (0x1UL << IPCT_INTEN7_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                              */
52905   #define IPCT_INTEN7_ACKED4_Min (0x0UL)             /*!< Min enumerator value of ACKED4 field.                                */
52906   #define IPCT_INTEN7_ACKED4_Max (0x1UL)             /*!< Max enumerator value of ACKED4 field.                                */
52907   #define IPCT_INTEN7_ACKED4_Disabled (0x0UL)        /*!< Disable                                                              */
52908   #define IPCT_INTEN7_ACKED4_Enabled (0x1UL)         /*!< Enable                                                               */
52909 
52910 /* ACKED5 @Bit 21 : Enable or disable interrupt for event ACKED[5] */
52911   #define IPCT_INTEN7_ACKED5_Pos (21UL)              /*!< Position of ACKED5 field.                                            */
52912   #define IPCT_INTEN7_ACKED5_Msk (0x1UL << IPCT_INTEN7_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                              */
52913   #define IPCT_INTEN7_ACKED5_Min (0x0UL)             /*!< Min enumerator value of ACKED5 field.                                */
52914   #define IPCT_INTEN7_ACKED5_Max (0x1UL)             /*!< Max enumerator value of ACKED5 field.                                */
52915   #define IPCT_INTEN7_ACKED5_Disabled (0x0UL)        /*!< Disable                                                              */
52916   #define IPCT_INTEN7_ACKED5_Enabled (0x1UL)         /*!< Enable                                                               */
52917 
52918 /* ACKED6 @Bit 22 : Enable or disable interrupt for event ACKED[6] */
52919   #define IPCT_INTEN7_ACKED6_Pos (22UL)              /*!< Position of ACKED6 field.                                            */
52920   #define IPCT_INTEN7_ACKED6_Msk (0x1UL << IPCT_INTEN7_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                              */
52921   #define IPCT_INTEN7_ACKED6_Min (0x0UL)             /*!< Min enumerator value of ACKED6 field.                                */
52922   #define IPCT_INTEN7_ACKED6_Max (0x1UL)             /*!< Max enumerator value of ACKED6 field.                                */
52923   #define IPCT_INTEN7_ACKED6_Disabled (0x0UL)        /*!< Disable                                                              */
52924   #define IPCT_INTEN7_ACKED6_Enabled (0x1UL)         /*!< Enable                                                               */
52925 
52926 /* ACKED7 @Bit 23 : Enable or disable interrupt for event ACKED[7] */
52927   #define IPCT_INTEN7_ACKED7_Pos (23UL)              /*!< Position of ACKED7 field.                                            */
52928   #define IPCT_INTEN7_ACKED7_Msk (0x1UL << IPCT_INTEN7_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                              */
52929   #define IPCT_INTEN7_ACKED7_Min (0x0UL)             /*!< Min enumerator value of ACKED7 field.                                */
52930   #define IPCT_INTEN7_ACKED7_Max (0x1UL)             /*!< Max enumerator value of ACKED7 field.                                */
52931   #define IPCT_INTEN7_ACKED7_Disabled (0x0UL)        /*!< Disable                                                              */
52932   #define IPCT_INTEN7_ACKED7_Enabled (0x1UL)         /*!< Enable                                                               */
52933 
52934 /* ACKED8 @Bit 24 : Enable or disable interrupt for event ACKED[8] */
52935   #define IPCT_INTEN7_ACKED8_Pos (24UL)              /*!< Position of ACKED8 field.                                            */
52936   #define IPCT_INTEN7_ACKED8_Msk (0x1UL << IPCT_INTEN7_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                              */
52937   #define IPCT_INTEN7_ACKED8_Min (0x0UL)             /*!< Min enumerator value of ACKED8 field.                                */
52938   #define IPCT_INTEN7_ACKED8_Max (0x1UL)             /*!< Max enumerator value of ACKED8 field.                                */
52939   #define IPCT_INTEN7_ACKED8_Disabled (0x0UL)        /*!< Disable                                                              */
52940   #define IPCT_INTEN7_ACKED8_Enabled (0x1UL)         /*!< Enable                                                               */
52941 
52942 /* ACKED9 @Bit 25 : Enable or disable interrupt for event ACKED[9] */
52943   #define IPCT_INTEN7_ACKED9_Pos (25UL)              /*!< Position of ACKED9 field.                                            */
52944   #define IPCT_INTEN7_ACKED9_Msk (0x1UL << IPCT_INTEN7_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                              */
52945   #define IPCT_INTEN7_ACKED9_Min (0x0UL)             /*!< Min enumerator value of ACKED9 field.                                */
52946   #define IPCT_INTEN7_ACKED9_Max (0x1UL)             /*!< Max enumerator value of ACKED9 field.                                */
52947   #define IPCT_INTEN7_ACKED9_Disabled (0x0UL)        /*!< Disable                                                              */
52948   #define IPCT_INTEN7_ACKED9_Enabled (0x1UL)         /*!< Enable                                                               */
52949 
52950 /* ACKED10 @Bit 26 : Enable or disable interrupt for event ACKED[10] */
52951   #define IPCT_INTEN7_ACKED10_Pos (26UL)             /*!< Position of ACKED10 field.                                           */
52952   #define IPCT_INTEN7_ACKED10_Msk (0x1UL << IPCT_INTEN7_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                           */
52953   #define IPCT_INTEN7_ACKED10_Min (0x0UL)            /*!< Min enumerator value of ACKED10 field.                               */
52954   #define IPCT_INTEN7_ACKED10_Max (0x1UL)            /*!< Max enumerator value of ACKED10 field.                               */
52955   #define IPCT_INTEN7_ACKED10_Disabled (0x0UL)       /*!< Disable                                                              */
52956   #define IPCT_INTEN7_ACKED10_Enabled (0x1UL)        /*!< Enable                                                               */
52957 
52958 /* ACKED11 @Bit 27 : Enable or disable interrupt for event ACKED[11] */
52959   #define IPCT_INTEN7_ACKED11_Pos (27UL)             /*!< Position of ACKED11 field.                                           */
52960   #define IPCT_INTEN7_ACKED11_Msk (0x1UL << IPCT_INTEN7_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                           */
52961   #define IPCT_INTEN7_ACKED11_Min (0x0UL)            /*!< Min enumerator value of ACKED11 field.                               */
52962   #define IPCT_INTEN7_ACKED11_Max (0x1UL)            /*!< Max enumerator value of ACKED11 field.                               */
52963   #define IPCT_INTEN7_ACKED11_Disabled (0x0UL)       /*!< Disable                                                              */
52964   #define IPCT_INTEN7_ACKED11_Enabled (0x1UL)        /*!< Enable                                                               */
52965 
52966 /* ACKED12 @Bit 28 : Enable or disable interrupt for event ACKED[12] */
52967   #define IPCT_INTEN7_ACKED12_Pos (28UL)             /*!< Position of ACKED12 field.                                           */
52968   #define IPCT_INTEN7_ACKED12_Msk (0x1UL << IPCT_INTEN7_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                           */
52969   #define IPCT_INTEN7_ACKED12_Min (0x0UL)            /*!< Min enumerator value of ACKED12 field.                               */
52970   #define IPCT_INTEN7_ACKED12_Max (0x1UL)            /*!< Max enumerator value of ACKED12 field.                               */
52971   #define IPCT_INTEN7_ACKED12_Disabled (0x0UL)       /*!< Disable                                                              */
52972   #define IPCT_INTEN7_ACKED12_Enabled (0x1UL)        /*!< Enable                                                               */
52973 
52974 /* ACKED13 @Bit 29 : Enable or disable interrupt for event ACKED[13] */
52975   #define IPCT_INTEN7_ACKED13_Pos (29UL)             /*!< Position of ACKED13 field.                                           */
52976   #define IPCT_INTEN7_ACKED13_Msk (0x1UL << IPCT_INTEN7_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                           */
52977   #define IPCT_INTEN7_ACKED13_Min (0x0UL)            /*!< Min enumerator value of ACKED13 field.                               */
52978   #define IPCT_INTEN7_ACKED13_Max (0x1UL)            /*!< Max enumerator value of ACKED13 field.                               */
52979   #define IPCT_INTEN7_ACKED13_Disabled (0x0UL)       /*!< Disable                                                              */
52980   #define IPCT_INTEN7_ACKED13_Enabled (0x1UL)        /*!< Enable                                                               */
52981 
52982 /* ACKED14 @Bit 30 : Enable or disable interrupt for event ACKED[14] */
52983   #define IPCT_INTEN7_ACKED14_Pos (30UL)             /*!< Position of ACKED14 field.                                           */
52984   #define IPCT_INTEN7_ACKED14_Msk (0x1UL << IPCT_INTEN7_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                           */
52985   #define IPCT_INTEN7_ACKED14_Min (0x0UL)            /*!< Min enumerator value of ACKED14 field.                               */
52986   #define IPCT_INTEN7_ACKED14_Max (0x1UL)            /*!< Max enumerator value of ACKED14 field.                               */
52987   #define IPCT_INTEN7_ACKED14_Disabled (0x0UL)       /*!< Disable                                                              */
52988   #define IPCT_INTEN7_ACKED14_Enabled (0x1UL)        /*!< Enable                                                               */
52989 
52990 /* ACKED15 @Bit 31 : Enable or disable interrupt for event ACKED[15] */
52991   #define IPCT_INTEN7_ACKED15_Pos (31UL)             /*!< Position of ACKED15 field.                                           */
52992   #define IPCT_INTEN7_ACKED15_Msk (0x1UL << IPCT_INTEN7_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                           */
52993   #define IPCT_INTEN7_ACKED15_Min (0x0UL)            /*!< Min enumerator value of ACKED15 field.                               */
52994   #define IPCT_INTEN7_ACKED15_Max (0x1UL)            /*!< Max enumerator value of ACKED15 field.                               */
52995   #define IPCT_INTEN7_ACKED15_Disabled (0x0UL)       /*!< Disable                                                              */
52996   #define IPCT_INTEN7_ACKED15_Enabled (0x1UL)        /*!< Enable                                                               */
52997 
52998 
52999 /* IPCT_INTENSET7: Enable interrupt */
53000   #define IPCT_INTENSET7_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET7 register.                                   */
53001 
53002 /* RECEIVE0 @Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */
53003   #define IPCT_INTENSET7_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
53004   #define IPCT_INTENSET7_RECEIVE0_Msk (0x1UL << IPCT_INTENSET7_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
53005   #define IPCT_INTENSET7_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
53006   #define IPCT_INTENSET7_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
53007   #define IPCT_INTENSET7_RECEIVE0_Set (0x1UL)        /*!< Enable                                                               */
53008   #define IPCT_INTENSET7_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53009   #define IPCT_INTENSET7_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53010 
53011 /* RECEIVE1 @Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */
53012   #define IPCT_INTENSET7_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
53013   #define IPCT_INTENSET7_RECEIVE1_Msk (0x1UL << IPCT_INTENSET7_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
53014   #define IPCT_INTENSET7_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
53015   #define IPCT_INTENSET7_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
53016   #define IPCT_INTENSET7_RECEIVE1_Set (0x1UL)        /*!< Enable                                                               */
53017   #define IPCT_INTENSET7_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53018   #define IPCT_INTENSET7_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53019 
53020 /* RECEIVE2 @Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */
53021   #define IPCT_INTENSET7_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
53022   #define IPCT_INTENSET7_RECEIVE2_Msk (0x1UL << IPCT_INTENSET7_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
53023   #define IPCT_INTENSET7_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
53024   #define IPCT_INTENSET7_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
53025   #define IPCT_INTENSET7_RECEIVE2_Set (0x1UL)        /*!< Enable                                                               */
53026   #define IPCT_INTENSET7_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53027   #define IPCT_INTENSET7_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53028 
53029 /* RECEIVE3 @Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */
53030   #define IPCT_INTENSET7_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
53031   #define IPCT_INTENSET7_RECEIVE3_Msk (0x1UL << IPCT_INTENSET7_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
53032   #define IPCT_INTENSET7_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
53033   #define IPCT_INTENSET7_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
53034   #define IPCT_INTENSET7_RECEIVE3_Set (0x1UL)        /*!< Enable                                                               */
53035   #define IPCT_INTENSET7_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53036   #define IPCT_INTENSET7_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53037 
53038 /* RECEIVE4 @Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */
53039   #define IPCT_INTENSET7_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
53040   #define IPCT_INTENSET7_RECEIVE4_Msk (0x1UL << IPCT_INTENSET7_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
53041   #define IPCT_INTENSET7_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
53042   #define IPCT_INTENSET7_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
53043   #define IPCT_INTENSET7_RECEIVE4_Set (0x1UL)        /*!< Enable                                                               */
53044   #define IPCT_INTENSET7_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53045   #define IPCT_INTENSET7_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53046 
53047 /* RECEIVE5 @Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */
53048   #define IPCT_INTENSET7_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
53049   #define IPCT_INTENSET7_RECEIVE5_Msk (0x1UL << IPCT_INTENSET7_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
53050   #define IPCT_INTENSET7_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
53051   #define IPCT_INTENSET7_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
53052   #define IPCT_INTENSET7_RECEIVE5_Set (0x1UL)        /*!< Enable                                                               */
53053   #define IPCT_INTENSET7_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53054   #define IPCT_INTENSET7_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53055 
53056 /* RECEIVE6 @Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */
53057   #define IPCT_INTENSET7_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
53058   #define IPCT_INTENSET7_RECEIVE6_Msk (0x1UL << IPCT_INTENSET7_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
53059   #define IPCT_INTENSET7_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
53060   #define IPCT_INTENSET7_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
53061   #define IPCT_INTENSET7_RECEIVE6_Set (0x1UL)        /*!< Enable                                                               */
53062   #define IPCT_INTENSET7_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53063   #define IPCT_INTENSET7_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53064 
53065 /* RECEIVE7 @Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */
53066   #define IPCT_INTENSET7_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
53067   #define IPCT_INTENSET7_RECEIVE7_Msk (0x1UL << IPCT_INTENSET7_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
53068   #define IPCT_INTENSET7_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
53069   #define IPCT_INTENSET7_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
53070   #define IPCT_INTENSET7_RECEIVE7_Set (0x1UL)        /*!< Enable                                                               */
53071   #define IPCT_INTENSET7_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53072   #define IPCT_INTENSET7_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53073 
53074 /* RECEIVE8 @Bit 8 : Write '1' to enable interrupt for event RECEIVE[8] */
53075   #define IPCT_INTENSET7_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
53076   #define IPCT_INTENSET7_RECEIVE8_Msk (0x1UL << IPCT_INTENSET7_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
53077   #define IPCT_INTENSET7_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
53078   #define IPCT_INTENSET7_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
53079   #define IPCT_INTENSET7_RECEIVE8_Set (0x1UL)        /*!< Enable                                                               */
53080   #define IPCT_INTENSET7_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53081   #define IPCT_INTENSET7_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53082 
53083 /* RECEIVE9 @Bit 9 : Write '1' to enable interrupt for event RECEIVE[9] */
53084   #define IPCT_INTENSET7_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
53085   #define IPCT_INTENSET7_RECEIVE9_Msk (0x1UL << IPCT_INTENSET7_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
53086   #define IPCT_INTENSET7_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
53087   #define IPCT_INTENSET7_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
53088   #define IPCT_INTENSET7_RECEIVE9_Set (0x1UL)        /*!< Enable                                                               */
53089   #define IPCT_INTENSET7_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53090   #define IPCT_INTENSET7_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53091 
53092 /* RECEIVE10 @Bit 10 : Write '1' to enable interrupt for event RECEIVE[10] */
53093   #define IPCT_INTENSET7_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
53094   #define IPCT_INTENSET7_RECEIVE10_Msk (0x1UL << IPCT_INTENSET7_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
53095   #define IPCT_INTENSET7_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
53096   #define IPCT_INTENSET7_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
53097   #define IPCT_INTENSET7_RECEIVE10_Set (0x1UL)       /*!< Enable                                                               */
53098   #define IPCT_INTENSET7_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53099   #define IPCT_INTENSET7_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53100 
53101 /* RECEIVE11 @Bit 11 : Write '1' to enable interrupt for event RECEIVE[11] */
53102   #define IPCT_INTENSET7_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
53103   #define IPCT_INTENSET7_RECEIVE11_Msk (0x1UL << IPCT_INTENSET7_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
53104   #define IPCT_INTENSET7_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
53105   #define IPCT_INTENSET7_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
53106   #define IPCT_INTENSET7_RECEIVE11_Set (0x1UL)       /*!< Enable                                                               */
53107   #define IPCT_INTENSET7_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53108   #define IPCT_INTENSET7_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53109 
53110 /* RECEIVE12 @Bit 12 : Write '1' to enable interrupt for event RECEIVE[12] */
53111   #define IPCT_INTENSET7_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
53112   #define IPCT_INTENSET7_RECEIVE12_Msk (0x1UL << IPCT_INTENSET7_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
53113   #define IPCT_INTENSET7_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
53114   #define IPCT_INTENSET7_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
53115   #define IPCT_INTENSET7_RECEIVE12_Set (0x1UL)       /*!< Enable                                                               */
53116   #define IPCT_INTENSET7_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53117   #define IPCT_INTENSET7_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53118 
53119 /* RECEIVE13 @Bit 13 : Write '1' to enable interrupt for event RECEIVE[13] */
53120   #define IPCT_INTENSET7_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
53121   #define IPCT_INTENSET7_RECEIVE13_Msk (0x1UL << IPCT_INTENSET7_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
53122   #define IPCT_INTENSET7_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
53123   #define IPCT_INTENSET7_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
53124   #define IPCT_INTENSET7_RECEIVE13_Set (0x1UL)       /*!< Enable                                                               */
53125   #define IPCT_INTENSET7_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53126   #define IPCT_INTENSET7_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53127 
53128 /* RECEIVE14 @Bit 14 : Write '1' to enable interrupt for event RECEIVE[14] */
53129   #define IPCT_INTENSET7_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
53130   #define IPCT_INTENSET7_RECEIVE14_Msk (0x1UL << IPCT_INTENSET7_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
53131   #define IPCT_INTENSET7_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
53132   #define IPCT_INTENSET7_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
53133   #define IPCT_INTENSET7_RECEIVE14_Set (0x1UL)       /*!< Enable                                                               */
53134   #define IPCT_INTENSET7_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53135   #define IPCT_INTENSET7_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53136 
53137 /* RECEIVE15 @Bit 15 : Write '1' to enable interrupt for event RECEIVE[15] */
53138   #define IPCT_INTENSET7_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
53139   #define IPCT_INTENSET7_RECEIVE15_Msk (0x1UL << IPCT_INTENSET7_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
53140   #define IPCT_INTENSET7_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
53141   #define IPCT_INTENSET7_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
53142   #define IPCT_INTENSET7_RECEIVE15_Set (0x1UL)       /*!< Enable                                                               */
53143   #define IPCT_INTENSET7_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53144   #define IPCT_INTENSET7_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53145 
53146 /* ACKED0 @Bit 16 : Write '1' to enable interrupt for event ACKED[0] */
53147   #define IPCT_INTENSET7_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
53148   #define IPCT_INTENSET7_ACKED0_Msk (0x1UL << IPCT_INTENSET7_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
53149   #define IPCT_INTENSET7_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
53150   #define IPCT_INTENSET7_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
53151   #define IPCT_INTENSET7_ACKED0_Set (0x1UL)          /*!< Enable                                                               */
53152   #define IPCT_INTENSET7_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53153   #define IPCT_INTENSET7_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53154 
53155 /* ACKED1 @Bit 17 : Write '1' to enable interrupt for event ACKED[1] */
53156   #define IPCT_INTENSET7_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
53157   #define IPCT_INTENSET7_ACKED1_Msk (0x1UL << IPCT_INTENSET7_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
53158   #define IPCT_INTENSET7_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
53159   #define IPCT_INTENSET7_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
53160   #define IPCT_INTENSET7_ACKED1_Set (0x1UL)          /*!< Enable                                                               */
53161   #define IPCT_INTENSET7_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53162   #define IPCT_INTENSET7_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53163 
53164 /* ACKED2 @Bit 18 : Write '1' to enable interrupt for event ACKED[2] */
53165   #define IPCT_INTENSET7_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
53166   #define IPCT_INTENSET7_ACKED2_Msk (0x1UL << IPCT_INTENSET7_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
53167   #define IPCT_INTENSET7_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
53168   #define IPCT_INTENSET7_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
53169   #define IPCT_INTENSET7_ACKED2_Set (0x1UL)          /*!< Enable                                                               */
53170   #define IPCT_INTENSET7_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53171   #define IPCT_INTENSET7_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53172 
53173 /* ACKED3 @Bit 19 : Write '1' to enable interrupt for event ACKED[3] */
53174   #define IPCT_INTENSET7_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
53175   #define IPCT_INTENSET7_ACKED3_Msk (0x1UL << IPCT_INTENSET7_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
53176   #define IPCT_INTENSET7_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
53177   #define IPCT_INTENSET7_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
53178   #define IPCT_INTENSET7_ACKED3_Set (0x1UL)          /*!< Enable                                                               */
53179   #define IPCT_INTENSET7_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53180   #define IPCT_INTENSET7_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53181 
53182 /* ACKED4 @Bit 20 : Write '1' to enable interrupt for event ACKED[4] */
53183   #define IPCT_INTENSET7_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
53184   #define IPCT_INTENSET7_ACKED4_Msk (0x1UL << IPCT_INTENSET7_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
53185   #define IPCT_INTENSET7_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
53186   #define IPCT_INTENSET7_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
53187   #define IPCT_INTENSET7_ACKED4_Set (0x1UL)          /*!< Enable                                                               */
53188   #define IPCT_INTENSET7_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53189   #define IPCT_INTENSET7_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53190 
53191 /* ACKED5 @Bit 21 : Write '1' to enable interrupt for event ACKED[5] */
53192   #define IPCT_INTENSET7_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
53193   #define IPCT_INTENSET7_ACKED5_Msk (0x1UL << IPCT_INTENSET7_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
53194   #define IPCT_INTENSET7_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
53195   #define IPCT_INTENSET7_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
53196   #define IPCT_INTENSET7_ACKED5_Set (0x1UL)          /*!< Enable                                                               */
53197   #define IPCT_INTENSET7_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53198   #define IPCT_INTENSET7_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53199 
53200 /* ACKED6 @Bit 22 : Write '1' to enable interrupt for event ACKED[6] */
53201   #define IPCT_INTENSET7_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
53202   #define IPCT_INTENSET7_ACKED6_Msk (0x1UL << IPCT_INTENSET7_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
53203   #define IPCT_INTENSET7_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
53204   #define IPCT_INTENSET7_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
53205   #define IPCT_INTENSET7_ACKED6_Set (0x1UL)          /*!< Enable                                                               */
53206   #define IPCT_INTENSET7_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53207   #define IPCT_INTENSET7_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53208 
53209 /* ACKED7 @Bit 23 : Write '1' to enable interrupt for event ACKED[7] */
53210   #define IPCT_INTENSET7_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
53211   #define IPCT_INTENSET7_ACKED7_Msk (0x1UL << IPCT_INTENSET7_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
53212   #define IPCT_INTENSET7_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
53213   #define IPCT_INTENSET7_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
53214   #define IPCT_INTENSET7_ACKED7_Set (0x1UL)          /*!< Enable                                                               */
53215   #define IPCT_INTENSET7_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53216   #define IPCT_INTENSET7_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53217 
53218 /* ACKED8 @Bit 24 : Write '1' to enable interrupt for event ACKED[8] */
53219   #define IPCT_INTENSET7_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
53220   #define IPCT_INTENSET7_ACKED8_Msk (0x1UL << IPCT_INTENSET7_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
53221   #define IPCT_INTENSET7_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
53222   #define IPCT_INTENSET7_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
53223   #define IPCT_INTENSET7_ACKED8_Set (0x1UL)          /*!< Enable                                                               */
53224   #define IPCT_INTENSET7_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53225   #define IPCT_INTENSET7_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53226 
53227 /* ACKED9 @Bit 25 : Write '1' to enable interrupt for event ACKED[9] */
53228   #define IPCT_INTENSET7_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
53229   #define IPCT_INTENSET7_ACKED9_Msk (0x1UL << IPCT_INTENSET7_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
53230   #define IPCT_INTENSET7_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
53231   #define IPCT_INTENSET7_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
53232   #define IPCT_INTENSET7_ACKED9_Set (0x1UL)          /*!< Enable                                                               */
53233   #define IPCT_INTENSET7_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53234   #define IPCT_INTENSET7_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53235 
53236 /* ACKED10 @Bit 26 : Write '1' to enable interrupt for event ACKED[10] */
53237   #define IPCT_INTENSET7_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
53238   #define IPCT_INTENSET7_ACKED10_Msk (0x1UL << IPCT_INTENSET7_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
53239   #define IPCT_INTENSET7_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
53240   #define IPCT_INTENSET7_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
53241   #define IPCT_INTENSET7_ACKED10_Set (0x1UL)         /*!< Enable                                                               */
53242   #define IPCT_INTENSET7_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53243   #define IPCT_INTENSET7_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53244 
53245 /* ACKED11 @Bit 27 : Write '1' to enable interrupt for event ACKED[11] */
53246   #define IPCT_INTENSET7_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
53247   #define IPCT_INTENSET7_ACKED11_Msk (0x1UL << IPCT_INTENSET7_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
53248   #define IPCT_INTENSET7_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
53249   #define IPCT_INTENSET7_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
53250   #define IPCT_INTENSET7_ACKED11_Set (0x1UL)         /*!< Enable                                                               */
53251   #define IPCT_INTENSET7_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53252   #define IPCT_INTENSET7_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53253 
53254 /* ACKED12 @Bit 28 : Write '1' to enable interrupt for event ACKED[12] */
53255   #define IPCT_INTENSET7_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
53256   #define IPCT_INTENSET7_ACKED12_Msk (0x1UL << IPCT_INTENSET7_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
53257   #define IPCT_INTENSET7_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
53258   #define IPCT_INTENSET7_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
53259   #define IPCT_INTENSET7_ACKED12_Set (0x1UL)         /*!< Enable                                                               */
53260   #define IPCT_INTENSET7_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53261   #define IPCT_INTENSET7_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53262 
53263 /* ACKED13 @Bit 29 : Write '1' to enable interrupt for event ACKED[13] */
53264   #define IPCT_INTENSET7_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
53265   #define IPCT_INTENSET7_ACKED13_Msk (0x1UL << IPCT_INTENSET7_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
53266   #define IPCT_INTENSET7_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
53267   #define IPCT_INTENSET7_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
53268   #define IPCT_INTENSET7_ACKED13_Set (0x1UL)         /*!< Enable                                                               */
53269   #define IPCT_INTENSET7_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53270   #define IPCT_INTENSET7_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53271 
53272 /* ACKED14 @Bit 30 : Write '1' to enable interrupt for event ACKED[14] */
53273   #define IPCT_INTENSET7_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
53274   #define IPCT_INTENSET7_ACKED14_Msk (0x1UL << IPCT_INTENSET7_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
53275   #define IPCT_INTENSET7_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
53276   #define IPCT_INTENSET7_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
53277   #define IPCT_INTENSET7_ACKED14_Set (0x1UL)         /*!< Enable                                                               */
53278   #define IPCT_INTENSET7_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53279   #define IPCT_INTENSET7_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53280 
53281 /* ACKED15 @Bit 31 : Write '1' to enable interrupt for event ACKED[15] */
53282   #define IPCT_INTENSET7_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
53283   #define IPCT_INTENSET7_ACKED15_Msk (0x1UL << IPCT_INTENSET7_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
53284   #define IPCT_INTENSET7_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
53285   #define IPCT_INTENSET7_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
53286   #define IPCT_INTENSET7_ACKED15_Set (0x1UL)         /*!< Enable                                                               */
53287   #define IPCT_INTENSET7_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53288   #define IPCT_INTENSET7_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53289 
53290 
53291 /* IPCT_INTENCLR7: Disable interrupt */
53292   #define IPCT_INTENCLR7_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR7 register.                                   */
53293 
53294 /* RECEIVE0 @Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */
53295   #define IPCT_INTENCLR7_RECEIVE0_Pos (0UL)          /*!< Position of RECEIVE0 field.                                          */
53296   #define IPCT_INTENCLR7_RECEIVE0_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                  */
53297   #define IPCT_INTENCLR7_RECEIVE0_Min (0x0UL)        /*!< Min enumerator value of RECEIVE0 field.                              */
53298   #define IPCT_INTENCLR7_RECEIVE0_Max (0x1UL)        /*!< Max enumerator value of RECEIVE0 field.                              */
53299   #define IPCT_INTENCLR7_RECEIVE0_Clear (0x1UL)      /*!< Disable                                                              */
53300   #define IPCT_INTENCLR7_RECEIVE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53301   #define IPCT_INTENCLR7_RECEIVE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53302 
53303 /* RECEIVE1 @Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */
53304   #define IPCT_INTENCLR7_RECEIVE1_Pos (1UL)          /*!< Position of RECEIVE1 field.                                          */
53305   #define IPCT_INTENCLR7_RECEIVE1_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                  */
53306   #define IPCT_INTENCLR7_RECEIVE1_Min (0x0UL)        /*!< Min enumerator value of RECEIVE1 field.                              */
53307   #define IPCT_INTENCLR7_RECEIVE1_Max (0x1UL)        /*!< Max enumerator value of RECEIVE1 field.                              */
53308   #define IPCT_INTENCLR7_RECEIVE1_Clear (0x1UL)      /*!< Disable                                                              */
53309   #define IPCT_INTENCLR7_RECEIVE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53310   #define IPCT_INTENCLR7_RECEIVE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53311 
53312 /* RECEIVE2 @Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */
53313   #define IPCT_INTENCLR7_RECEIVE2_Pos (2UL)          /*!< Position of RECEIVE2 field.                                          */
53314   #define IPCT_INTENCLR7_RECEIVE2_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                  */
53315   #define IPCT_INTENCLR7_RECEIVE2_Min (0x0UL)        /*!< Min enumerator value of RECEIVE2 field.                              */
53316   #define IPCT_INTENCLR7_RECEIVE2_Max (0x1UL)        /*!< Max enumerator value of RECEIVE2 field.                              */
53317   #define IPCT_INTENCLR7_RECEIVE2_Clear (0x1UL)      /*!< Disable                                                              */
53318   #define IPCT_INTENCLR7_RECEIVE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53319   #define IPCT_INTENCLR7_RECEIVE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53320 
53321 /* RECEIVE3 @Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */
53322   #define IPCT_INTENCLR7_RECEIVE3_Pos (3UL)          /*!< Position of RECEIVE3 field.                                          */
53323   #define IPCT_INTENCLR7_RECEIVE3_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                  */
53324   #define IPCT_INTENCLR7_RECEIVE3_Min (0x0UL)        /*!< Min enumerator value of RECEIVE3 field.                              */
53325   #define IPCT_INTENCLR7_RECEIVE3_Max (0x1UL)        /*!< Max enumerator value of RECEIVE3 field.                              */
53326   #define IPCT_INTENCLR7_RECEIVE3_Clear (0x1UL)      /*!< Disable                                                              */
53327   #define IPCT_INTENCLR7_RECEIVE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53328   #define IPCT_INTENCLR7_RECEIVE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53329 
53330 /* RECEIVE4 @Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */
53331   #define IPCT_INTENCLR7_RECEIVE4_Pos (4UL)          /*!< Position of RECEIVE4 field.                                          */
53332   #define IPCT_INTENCLR7_RECEIVE4_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                  */
53333   #define IPCT_INTENCLR7_RECEIVE4_Min (0x0UL)        /*!< Min enumerator value of RECEIVE4 field.                              */
53334   #define IPCT_INTENCLR7_RECEIVE4_Max (0x1UL)        /*!< Max enumerator value of RECEIVE4 field.                              */
53335   #define IPCT_INTENCLR7_RECEIVE4_Clear (0x1UL)      /*!< Disable                                                              */
53336   #define IPCT_INTENCLR7_RECEIVE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53337   #define IPCT_INTENCLR7_RECEIVE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53338 
53339 /* RECEIVE5 @Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */
53340   #define IPCT_INTENCLR7_RECEIVE5_Pos (5UL)          /*!< Position of RECEIVE5 field.                                          */
53341   #define IPCT_INTENCLR7_RECEIVE5_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                  */
53342   #define IPCT_INTENCLR7_RECEIVE5_Min (0x0UL)        /*!< Min enumerator value of RECEIVE5 field.                              */
53343   #define IPCT_INTENCLR7_RECEIVE5_Max (0x1UL)        /*!< Max enumerator value of RECEIVE5 field.                              */
53344   #define IPCT_INTENCLR7_RECEIVE5_Clear (0x1UL)      /*!< Disable                                                              */
53345   #define IPCT_INTENCLR7_RECEIVE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53346   #define IPCT_INTENCLR7_RECEIVE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53347 
53348 /* RECEIVE6 @Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */
53349   #define IPCT_INTENCLR7_RECEIVE6_Pos (6UL)          /*!< Position of RECEIVE6 field.                                          */
53350   #define IPCT_INTENCLR7_RECEIVE6_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                  */
53351   #define IPCT_INTENCLR7_RECEIVE6_Min (0x0UL)        /*!< Min enumerator value of RECEIVE6 field.                              */
53352   #define IPCT_INTENCLR7_RECEIVE6_Max (0x1UL)        /*!< Max enumerator value of RECEIVE6 field.                              */
53353   #define IPCT_INTENCLR7_RECEIVE6_Clear (0x1UL)      /*!< Disable                                                              */
53354   #define IPCT_INTENCLR7_RECEIVE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53355   #define IPCT_INTENCLR7_RECEIVE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53356 
53357 /* RECEIVE7 @Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */
53358   #define IPCT_INTENCLR7_RECEIVE7_Pos (7UL)          /*!< Position of RECEIVE7 field.                                          */
53359   #define IPCT_INTENCLR7_RECEIVE7_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                  */
53360   #define IPCT_INTENCLR7_RECEIVE7_Min (0x0UL)        /*!< Min enumerator value of RECEIVE7 field.                              */
53361   #define IPCT_INTENCLR7_RECEIVE7_Max (0x1UL)        /*!< Max enumerator value of RECEIVE7 field.                              */
53362   #define IPCT_INTENCLR7_RECEIVE7_Clear (0x1UL)      /*!< Disable                                                              */
53363   #define IPCT_INTENCLR7_RECEIVE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53364   #define IPCT_INTENCLR7_RECEIVE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53365 
53366 /* RECEIVE8 @Bit 8 : Write '1' to disable interrupt for event RECEIVE[8] */
53367   #define IPCT_INTENCLR7_RECEIVE8_Pos (8UL)          /*!< Position of RECEIVE8 field.                                          */
53368   #define IPCT_INTENCLR7_RECEIVE8_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                  */
53369   #define IPCT_INTENCLR7_RECEIVE8_Min (0x0UL)        /*!< Min enumerator value of RECEIVE8 field.                              */
53370   #define IPCT_INTENCLR7_RECEIVE8_Max (0x1UL)        /*!< Max enumerator value of RECEIVE8 field.                              */
53371   #define IPCT_INTENCLR7_RECEIVE8_Clear (0x1UL)      /*!< Disable                                                              */
53372   #define IPCT_INTENCLR7_RECEIVE8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53373   #define IPCT_INTENCLR7_RECEIVE8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53374 
53375 /* RECEIVE9 @Bit 9 : Write '1' to disable interrupt for event RECEIVE[9] */
53376   #define IPCT_INTENCLR7_RECEIVE9_Pos (9UL)          /*!< Position of RECEIVE9 field.                                          */
53377   #define IPCT_INTENCLR7_RECEIVE9_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                  */
53378   #define IPCT_INTENCLR7_RECEIVE9_Min (0x0UL)        /*!< Min enumerator value of RECEIVE9 field.                              */
53379   #define IPCT_INTENCLR7_RECEIVE9_Max (0x1UL)        /*!< Max enumerator value of RECEIVE9 field.                              */
53380   #define IPCT_INTENCLR7_RECEIVE9_Clear (0x1UL)      /*!< Disable                                                              */
53381   #define IPCT_INTENCLR7_RECEIVE9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
53382   #define IPCT_INTENCLR7_RECEIVE9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
53383 
53384 /* RECEIVE10 @Bit 10 : Write '1' to disable interrupt for event RECEIVE[10] */
53385   #define IPCT_INTENCLR7_RECEIVE10_Pos (10UL)        /*!< Position of RECEIVE10 field.                                         */
53386   #define IPCT_INTENCLR7_RECEIVE10_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.               */
53387   #define IPCT_INTENCLR7_RECEIVE10_Min (0x0UL)       /*!< Min enumerator value of RECEIVE10 field.                             */
53388   #define IPCT_INTENCLR7_RECEIVE10_Max (0x1UL)       /*!< Max enumerator value of RECEIVE10 field.                             */
53389   #define IPCT_INTENCLR7_RECEIVE10_Clear (0x1UL)     /*!< Disable                                                              */
53390   #define IPCT_INTENCLR7_RECEIVE10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53391   #define IPCT_INTENCLR7_RECEIVE10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53392 
53393 /* RECEIVE11 @Bit 11 : Write '1' to disable interrupt for event RECEIVE[11] */
53394   #define IPCT_INTENCLR7_RECEIVE11_Pos (11UL)        /*!< Position of RECEIVE11 field.                                         */
53395   #define IPCT_INTENCLR7_RECEIVE11_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.               */
53396   #define IPCT_INTENCLR7_RECEIVE11_Min (0x0UL)       /*!< Min enumerator value of RECEIVE11 field.                             */
53397   #define IPCT_INTENCLR7_RECEIVE11_Max (0x1UL)       /*!< Max enumerator value of RECEIVE11 field.                             */
53398   #define IPCT_INTENCLR7_RECEIVE11_Clear (0x1UL)     /*!< Disable                                                              */
53399   #define IPCT_INTENCLR7_RECEIVE11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53400   #define IPCT_INTENCLR7_RECEIVE11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53401 
53402 /* RECEIVE12 @Bit 12 : Write '1' to disable interrupt for event RECEIVE[12] */
53403   #define IPCT_INTENCLR7_RECEIVE12_Pos (12UL)        /*!< Position of RECEIVE12 field.                                         */
53404   #define IPCT_INTENCLR7_RECEIVE12_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.               */
53405   #define IPCT_INTENCLR7_RECEIVE12_Min (0x0UL)       /*!< Min enumerator value of RECEIVE12 field.                             */
53406   #define IPCT_INTENCLR7_RECEIVE12_Max (0x1UL)       /*!< Max enumerator value of RECEIVE12 field.                             */
53407   #define IPCT_INTENCLR7_RECEIVE12_Clear (0x1UL)     /*!< Disable                                                              */
53408   #define IPCT_INTENCLR7_RECEIVE12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53409   #define IPCT_INTENCLR7_RECEIVE12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53410 
53411 /* RECEIVE13 @Bit 13 : Write '1' to disable interrupt for event RECEIVE[13] */
53412   #define IPCT_INTENCLR7_RECEIVE13_Pos (13UL)        /*!< Position of RECEIVE13 field.                                         */
53413   #define IPCT_INTENCLR7_RECEIVE13_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.               */
53414   #define IPCT_INTENCLR7_RECEIVE13_Min (0x0UL)       /*!< Min enumerator value of RECEIVE13 field.                             */
53415   #define IPCT_INTENCLR7_RECEIVE13_Max (0x1UL)       /*!< Max enumerator value of RECEIVE13 field.                             */
53416   #define IPCT_INTENCLR7_RECEIVE13_Clear (0x1UL)     /*!< Disable                                                              */
53417   #define IPCT_INTENCLR7_RECEIVE13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53418   #define IPCT_INTENCLR7_RECEIVE13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53419 
53420 /* RECEIVE14 @Bit 14 : Write '1' to disable interrupt for event RECEIVE[14] */
53421   #define IPCT_INTENCLR7_RECEIVE14_Pos (14UL)        /*!< Position of RECEIVE14 field.                                         */
53422   #define IPCT_INTENCLR7_RECEIVE14_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.               */
53423   #define IPCT_INTENCLR7_RECEIVE14_Min (0x0UL)       /*!< Min enumerator value of RECEIVE14 field.                             */
53424   #define IPCT_INTENCLR7_RECEIVE14_Max (0x1UL)       /*!< Max enumerator value of RECEIVE14 field.                             */
53425   #define IPCT_INTENCLR7_RECEIVE14_Clear (0x1UL)     /*!< Disable                                                              */
53426   #define IPCT_INTENCLR7_RECEIVE14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53427   #define IPCT_INTENCLR7_RECEIVE14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53428 
53429 /* RECEIVE15 @Bit 15 : Write '1' to disable interrupt for event RECEIVE[15] */
53430   #define IPCT_INTENCLR7_RECEIVE15_Pos (15UL)        /*!< Position of RECEIVE15 field.                                         */
53431   #define IPCT_INTENCLR7_RECEIVE15_Msk (0x1UL << IPCT_INTENCLR7_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.               */
53432   #define IPCT_INTENCLR7_RECEIVE15_Min (0x0UL)       /*!< Min enumerator value of RECEIVE15 field.                             */
53433   #define IPCT_INTENCLR7_RECEIVE15_Max (0x1UL)       /*!< Max enumerator value of RECEIVE15 field.                             */
53434   #define IPCT_INTENCLR7_RECEIVE15_Clear (0x1UL)     /*!< Disable                                                              */
53435   #define IPCT_INTENCLR7_RECEIVE15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
53436   #define IPCT_INTENCLR7_RECEIVE15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
53437 
53438 /* ACKED0 @Bit 16 : Write '1' to disable interrupt for event ACKED[0] */
53439   #define IPCT_INTENCLR7_ACKED0_Pos (16UL)           /*!< Position of ACKED0 field.                                            */
53440   #define IPCT_INTENCLR7_ACKED0_Msk (0x1UL << IPCT_INTENCLR7_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                        */
53441   #define IPCT_INTENCLR7_ACKED0_Min (0x0UL)          /*!< Min enumerator value of ACKED0 field.                                */
53442   #define IPCT_INTENCLR7_ACKED0_Max (0x1UL)          /*!< Max enumerator value of ACKED0 field.                                */
53443   #define IPCT_INTENCLR7_ACKED0_Clear (0x1UL)        /*!< Disable                                                              */
53444   #define IPCT_INTENCLR7_ACKED0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53445   #define IPCT_INTENCLR7_ACKED0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53446 
53447 /* ACKED1 @Bit 17 : Write '1' to disable interrupt for event ACKED[1] */
53448   #define IPCT_INTENCLR7_ACKED1_Pos (17UL)           /*!< Position of ACKED1 field.                                            */
53449   #define IPCT_INTENCLR7_ACKED1_Msk (0x1UL << IPCT_INTENCLR7_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                        */
53450   #define IPCT_INTENCLR7_ACKED1_Min (0x0UL)          /*!< Min enumerator value of ACKED1 field.                                */
53451   #define IPCT_INTENCLR7_ACKED1_Max (0x1UL)          /*!< Max enumerator value of ACKED1 field.                                */
53452   #define IPCT_INTENCLR7_ACKED1_Clear (0x1UL)        /*!< Disable                                                              */
53453   #define IPCT_INTENCLR7_ACKED1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53454   #define IPCT_INTENCLR7_ACKED1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53455 
53456 /* ACKED2 @Bit 18 : Write '1' to disable interrupt for event ACKED[2] */
53457   #define IPCT_INTENCLR7_ACKED2_Pos (18UL)           /*!< Position of ACKED2 field.                                            */
53458   #define IPCT_INTENCLR7_ACKED2_Msk (0x1UL << IPCT_INTENCLR7_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                        */
53459   #define IPCT_INTENCLR7_ACKED2_Min (0x0UL)          /*!< Min enumerator value of ACKED2 field.                                */
53460   #define IPCT_INTENCLR7_ACKED2_Max (0x1UL)          /*!< Max enumerator value of ACKED2 field.                                */
53461   #define IPCT_INTENCLR7_ACKED2_Clear (0x1UL)        /*!< Disable                                                              */
53462   #define IPCT_INTENCLR7_ACKED2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53463   #define IPCT_INTENCLR7_ACKED2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53464 
53465 /* ACKED3 @Bit 19 : Write '1' to disable interrupt for event ACKED[3] */
53466   #define IPCT_INTENCLR7_ACKED3_Pos (19UL)           /*!< Position of ACKED3 field.                                            */
53467   #define IPCT_INTENCLR7_ACKED3_Msk (0x1UL << IPCT_INTENCLR7_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                        */
53468   #define IPCT_INTENCLR7_ACKED3_Min (0x0UL)          /*!< Min enumerator value of ACKED3 field.                                */
53469   #define IPCT_INTENCLR7_ACKED3_Max (0x1UL)          /*!< Max enumerator value of ACKED3 field.                                */
53470   #define IPCT_INTENCLR7_ACKED3_Clear (0x1UL)        /*!< Disable                                                              */
53471   #define IPCT_INTENCLR7_ACKED3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53472   #define IPCT_INTENCLR7_ACKED3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53473 
53474 /* ACKED4 @Bit 20 : Write '1' to disable interrupt for event ACKED[4] */
53475   #define IPCT_INTENCLR7_ACKED4_Pos (20UL)           /*!< Position of ACKED4 field.                                            */
53476   #define IPCT_INTENCLR7_ACKED4_Msk (0x1UL << IPCT_INTENCLR7_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                        */
53477   #define IPCT_INTENCLR7_ACKED4_Min (0x0UL)          /*!< Min enumerator value of ACKED4 field.                                */
53478   #define IPCT_INTENCLR7_ACKED4_Max (0x1UL)          /*!< Max enumerator value of ACKED4 field.                                */
53479   #define IPCT_INTENCLR7_ACKED4_Clear (0x1UL)        /*!< Disable                                                              */
53480   #define IPCT_INTENCLR7_ACKED4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53481   #define IPCT_INTENCLR7_ACKED4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53482 
53483 /* ACKED5 @Bit 21 : Write '1' to disable interrupt for event ACKED[5] */
53484   #define IPCT_INTENCLR7_ACKED5_Pos (21UL)           /*!< Position of ACKED5 field.                                            */
53485   #define IPCT_INTENCLR7_ACKED5_Msk (0x1UL << IPCT_INTENCLR7_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                        */
53486   #define IPCT_INTENCLR7_ACKED5_Min (0x0UL)          /*!< Min enumerator value of ACKED5 field.                                */
53487   #define IPCT_INTENCLR7_ACKED5_Max (0x1UL)          /*!< Max enumerator value of ACKED5 field.                                */
53488   #define IPCT_INTENCLR7_ACKED5_Clear (0x1UL)        /*!< Disable                                                              */
53489   #define IPCT_INTENCLR7_ACKED5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53490   #define IPCT_INTENCLR7_ACKED5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53491 
53492 /* ACKED6 @Bit 22 : Write '1' to disable interrupt for event ACKED[6] */
53493   #define IPCT_INTENCLR7_ACKED6_Pos (22UL)           /*!< Position of ACKED6 field.                                            */
53494   #define IPCT_INTENCLR7_ACKED6_Msk (0x1UL << IPCT_INTENCLR7_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                        */
53495   #define IPCT_INTENCLR7_ACKED6_Min (0x0UL)          /*!< Min enumerator value of ACKED6 field.                                */
53496   #define IPCT_INTENCLR7_ACKED6_Max (0x1UL)          /*!< Max enumerator value of ACKED6 field.                                */
53497   #define IPCT_INTENCLR7_ACKED6_Clear (0x1UL)        /*!< Disable                                                              */
53498   #define IPCT_INTENCLR7_ACKED6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53499   #define IPCT_INTENCLR7_ACKED6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53500 
53501 /* ACKED7 @Bit 23 : Write '1' to disable interrupt for event ACKED[7] */
53502   #define IPCT_INTENCLR7_ACKED7_Pos (23UL)           /*!< Position of ACKED7 field.                                            */
53503   #define IPCT_INTENCLR7_ACKED7_Msk (0x1UL << IPCT_INTENCLR7_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                        */
53504   #define IPCT_INTENCLR7_ACKED7_Min (0x0UL)          /*!< Min enumerator value of ACKED7 field.                                */
53505   #define IPCT_INTENCLR7_ACKED7_Max (0x1UL)          /*!< Max enumerator value of ACKED7 field.                                */
53506   #define IPCT_INTENCLR7_ACKED7_Clear (0x1UL)        /*!< Disable                                                              */
53507   #define IPCT_INTENCLR7_ACKED7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53508   #define IPCT_INTENCLR7_ACKED7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53509 
53510 /* ACKED8 @Bit 24 : Write '1' to disable interrupt for event ACKED[8] */
53511   #define IPCT_INTENCLR7_ACKED8_Pos (24UL)           /*!< Position of ACKED8 field.                                            */
53512   #define IPCT_INTENCLR7_ACKED8_Msk (0x1UL << IPCT_INTENCLR7_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                        */
53513   #define IPCT_INTENCLR7_ACKED8_Min (0x0UL)          /*!< Min enumerator value of ACKED8 field.                                */
53514   #define IPCT_INTENCLR7_ACKED8_Max (0x1UL)          /*!< Max enumerator value of ACKED8 field.                                */
53515   #define IPCT_INTENCLR7_ACKED8_Clear (0x1UL)        /*!< Disable                                                              */
53516   #define IPCT_INTENCLR7_ACKED8_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53517   #define IPCT_INTENCLR7_ACKED8_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53518 
53519 /* ACKED9 @Bit 25 : Write '1' to disable interrupt for event ACKED[9] */
53520   #define IPCT_INTENCLR7_ACKED9_Pos (25UL)           /*!< Position of ACKED9 field.                                            */
53521   #define IPCT_INTENCLR7_ACKED9_Msk (0x1UL << IPCT_INTENCLR7_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                        */
53522   #define IPCT_INTENCLR7_ACKED9_Min (0x0UL)          /*!< Min enumerator value of ACKED9 field.                                */
53523   #define IPCT_INTENCLR7_ACKED9_Max (0x1UL)          /*!< Max enumerator value of ACKED9 field.                                */
53524   #define IPCT_INTENCLR7_ACKED9_Clear (0x1UL)        /*!< Disable                                                              */
53525   #define IPCT_INTENCLR7_ACKED9_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
53526   #define IPCT_INTENCLR7_ACKED9_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
53527 
53528 /* ACKED10 @Bit 26 : Write '1' to disable interrupt for event ACKED[10] */
53529   #define IPCT_INTENCLR7_ACKED10_Pos (26UL)          /*!< Position of ACKED10 field.                                           */
53530   #define IPCT_INTENCLR7_ACKED10_Msk (0x1UL << IPCT_INTENCLR7_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                     */
53531   #define IPCT_INTENCLR7_ACKED10_Min (0x0UL)         /*!< Min enumerator value of ACKED10 field.                               */
53532   #define IPCT_INTENCLR7_ACKED10_Max (0x1UL)         /*!< Max enumerator value of ACKED10 field.                               */
53533   #define IPCT_INTENCLR7_ACKED10_Clear (0x1UL)       /*!< Disable                                                              */
53534   #define IPCT_INTENCLR7_ACKED10_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53535   #define IPCT_INTENCLR7_ACKED10_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53536 
53537 /* ACKED11 @Bit 27 : Write '1' to disable interrupt for event ACKED[11] */
53538   #define IPCT_INTENCLR7_ACKED11_Pos (27UL)          /*!< Position of ACKED11 field.                                           */
53539   #define IPCT_INTENCLR7_ACKED11_Msk (0x1UL << IPCT_INTENCLR7_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                     */
53540   #define IPCT_INTENCLR7_ACKED11_Min (0x0UL)         /*!< Min enumerator value of ACKED11 field.                               */
53541   #define IPCT_INTENCLR7_ACKED11_Max (0x1UL)         /*!< Max enumerator value of ACKED11 field.                               */
53542   #define IPCT_INTENCLR7_ACKED11_Clear (0x1UL)       /*!< Disable                                                              */
53543   #define IPCT_INTENCLR7_ACKED11_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53544   #define IPCT_INTENCLR7_ACKED11_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53545 
53546 /* ACKED12 @Bit 28 : Write '1' to disable interrupt for event ACKED[12] */
53547   #define IPCT_INTENCLR7_ACKED12_Pos (28UL)          /*!< Position of ACKED12 field.                                           */
53548   #define IPCT_INTENCLR7_ACKED12_Msk (0x1UL << IPCT_INTENCLR7_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                     */
53549   #define IPCT_INTENCLR7_ACKED12_Min (0x0UL)         /*!< Min enumerator value of ACKED12 field.                               */
53550   #define IPCT_INTENCLR7_ACKED12_Max (0x1UL)         /*!< Max enumerator value of ACKED12 field.                               */
53551   #define IPCT_INTENCLR7_ACKED12_Clear (0x1UL)       /*!< Disable                                                              */
53552   #define IPCT_INTENCLR7_ACKED12_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53553   #define IPCT_INTENCLR7_ACKED12_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53554 
53555 /* ACKED13 @Bit 29 : Write '1' to disable interrupt for event ACKED[13] */
53556   #define IPCT_INTENCLR7_ACKED13_Pos (29UL)          /*!< Position of ACKED13 field.                                           */
53557   #define IPCT_INTENCLR7_ACKED13_Msk (0x1UL << IPCT_INTENCLR7_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                     */
53558   #define IPCT_INTENCLR7_ACKED13_Min (0x0UL)         /*!< Min enumerator value of ACKED13 field.                               */
53559   #define IPCT_INTENCLR7_ACKED13_Max (0x1UL)         /*!< Max enumerator value of ACKED13 field.                               */
53560   #define IPCT_INTENCLR7_ACKED13_Clear (0x1UL)       /*!< Disable                                                              */
53561   #define IPCT_INTENCLR7_ACKED13_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53562   #define IPCT_INTENCLR7_ACKED13_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53563 
53564 /* ACKED14 @Bit 30 : Write '1' to disable interrupt for event ACKED[14] */
53565   #define IPCT_INTENCLR7_ACKED14_Pos (30UL)          /*!< Position of ACKED14 field.                                           */
53566   #define IPCT_INTENCLR7_ACKED14_Msk (0x1UL << IPCT_INTENCLR7_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                     */
53567   #define IPCT_INTENCLR7_ACKED14_Min (0x0UL)         /*!< Min enumerator value of ACKED14 field.                               */
53568   #define IPCT_INTENCLR7_ACKED14_Max (0x1UL)         /*!< Max enumerator value of ACKED14 field.                               */
53569   #define IPCT_INTENCLR7_ACKED14_Clear (0x1UL)       /*!< Disable                                                              */
53570   #define IPCT_INTENCLR7_ACKED14_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53571   #define IPCT_INTENCLR7_ACKED14_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53572 
53573 /* ACKED15 @Bit 31 : Write '1' to disable interrupt for event ACKED[15] */
53574   #define IPCT_INTENCLR7_ACKED15_Pos (31UL)          /*!< Position of ACKED15 field.                                           */
53575   #define IPCT_INTENCLR7_ACKED15_Msk (0x1UL << IPCT_INTENCLR7_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                     */
53576   #define IPCT_INTENCLR7_ACKED15_Min (0x0UL)         /*!< Min enumerator value of ACKED15 field.                               */
53577   #define IPCT_INTENCLR7_ACKED15_Max (0x1UL)         /*!< Max enumerator value of ACKED15 field.                               */
53578   #define IPCT_INTENCLR7_ACKED15_Clear (0x1UL)       /*!< Disable                                                              */
53579   #define IPCT_INTENCLR7_ACKED15_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
53580   #define IPCT_INTENCLR7_ACKED15_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
53581 
53582 
53583 /* IPCT_INTPEND7: Pending interrupts */
53584   #define IPCT_INTPEND7_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND7 register.                                    */
53585 
53586 /* RECEIVE0 @Bit 0 : Read pending status of interrupt for event RECEIVE[0] */
53587   #define IPCT_INTPEND7_RECEIVE0_Pos (0UL)           /*!< Position of RECEIVE0 field.                                          */
53588   #define IPCT_INTPEND7_RECEIVE0_Msk (0x1UL << IPCT_INTPEND7_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field.                    */
53589   #define IPCT_INTPEND7_RECEIVE0_Min (0x0UL)         /*!< Min enumerator value of RECEIVE0 field.                              */
53590   #define IPCT_INTPEND7_RECEIVE0_Max (0x1UL)         /*!< Max enumerator value of RECEIVE0 field.                              */
53591   #define IPCT_INTPEND7_RECEIVE0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53592   #define IPCT_INTPEND7_RECEIVE0_Pending (0x1UL)     /*!< Read: Pending                                                        */
53593 
53594 /* RECEIVE1 @Bit 1 : Read pending status of interrupt for event RECEIVE[1] */
53595   #define IPCT_INTPEND7_RECEIVE1_Pos (1UL)           /*!< Position of RECEIVE1 field.                                          */
53596   #define IPCT_INTPEND7_RECEIVE1_Msk (0x1UL << IPCT_INTPEND7_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field.                    */
53597   #define IPCT_INTPEND7_RECEIVE1_Min (0x0UL)         /*!< Min enumerator value of RECEIVE1 field.                              */
53598   #define IPCT_INTPEND7_RECEIVE1_Max (0x1UL)         /*!< Max enumerator value of RECEIVE1 field.                              */
53599   #define IPCT_INTPEND7_RECEIVE1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53600   #define IPCT_INTPEND7_RECEIVE1_Pending (0x1UL)     /*!< Read: Pending                                                        */
53601 
53602 /* RECEIVE2 @Bit 2 : Read pending status of interrupt for event RECEIVE[2] */
53603   #define IPCT_INTPEND7_RECEIVE2_Pos (2UL)           /*!< Position of RECEIVE2 field.                                          */
53604   #define IPCT_INTPEND7_RECEIVE2_Msk (0x1UL << IPCT_INTPEND7_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field.                    */
53605   #define IPCT_INTPEND7_RECEIVE2_Min (0x0UL)         /*!< Min enumerator value of RECEIVE2 field.                              */
53606   #define IPCT_INTPEND7_RECEIVE2_Max (0x1UL)         /*!< Max enumerator value of RECEIVE2 field.                              */
53607   #define IPCT_INTPEND7_RECEIVE2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53608   #define IPCT_INTPEND7_RECEIVE2_Pending (0x1UL)     /*!< Read: Pending                                                        */
53609 
53610 /* RECEIVE3 @Bit 3 : Read pending status of interrupt for event RECEIVE[3] */
53611   #define IPCT_INTPEND7_RECEIVE3_Pos (3UL)           /*!< Position of RECEIVE3 field.                                          */
53612   #define IPCT_INTPEND7_RECEIVE3_Msk (0x1UL << IPCT_INTPEND7_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field.                    */
53613   #define IPCT_INTPEND7_RECEIVE3_Min (0x0UL)         /*!< Min enumerator value of RECEIVE3 field.                              */
53614   #define IPCT_INTPEND7_RECEIVE3_Max (0x1UL)         /*!< Max enumerator value of RECEIVE3 field.                              */
53615   #define IPCT_INTPEND7_RECEIVE3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53616   #define IPCT_INTPEND7_RECEIVE3_Pending (0x1UL)     /*!< Read: Pending                                                        */
53617 
53618 /* RECEIVE4 @Bit 4 : Read pending status of interrupt for event RECEIVE[4] */
53619   #define IPCT_INTPEND7_RECEIVE4_Pos (4UL)           /*!< Position of RECEIVE4 field.                                          */
53620   #define IPCT_INTPEND7_RECEIVE4_Msk (0x1UL << IPCT_INTPEND7_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field.                    */
53621   #define IPCT_INTPEND7_RECEIVE4_Min (0x0UL)         /*!< Min enumerator value of RECEIVE4 field.                              */
53622   #define IPCT_INTPEND7_RECEIVE4_Max (0x1UL)         /*!< Max enumerator value of RECEIVE4 field.                              */
53623   #define IPCT_INTPEND7_RECEIVE4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53624   #define IPCT_INTPEND7_RECEIVE4_Pending (0x1UL)     /*!< Read: Pending                                                        */
53625 
53626 /* RECEIVE5 @Bit 5 : Read pending status of interrupt for event RECEIVE[5] */
53627   #define IPCT_INTPEND7_RECEIVE5_Pos (5UL)           /*!< Position of RECEIVE5 field.                                          */
53628   #define IPCT_INTPEND7_RECEIVE5_Msk (0x1UL << IPCT_INTPEND7_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field.                    */
53629   #define IPCT_INTPEND7_RECEIVE5_Min (0x0UL)         /*!< Min enumerator value of RECEIVE5 field.                              */
53630   #define IPCT_INTPEND7_RECEIVE5_Max (0x1UL)         /*!< Max enumerator value of RECEIVE5 field.                              */
53631   #define IPCT_INTPEND7_RECEIVE5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53632   #define IPCT_INTPEND7_RECEIVE5_Pending (0x1UL)     /*!< Read: Pending                                                        */
53633 
53634 /* RECEIVE6 @Bit 6 : Read pending status of interrupt for event RECEIVE[6] */
53635   #define IPCT_INTPEND7_RECEIVE6_Pos (6UL)           /*!< Position of RECEIVE6 field.                                          */
53636   #define IPCT_INTPEND7_RECEIVE6_Msk (0x1UL << IPCT_INTPEND7_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field.                    */
53637   #define IPCT_INTPEND7_RECEIVE6_Min (0x0UL)         /*!< Min enumerator value of RECEIVE6 field.                              */
53638   #define IPCT_INTPEND7_RECEIVE6_Max (0x1UL)         /*!< Max enumerator value of RECEIVE6 field.                              */
53639   #define IPCT_INTPEND7_RECEIVE6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53640   #define IPCT_INTPEND7_RECEIVE6_Pending (0x1UL)     /*!< Read: Pending                                                        */
53641 
53642 /* RECEIVE7 @Bit 7 : Read pending status of interrupt for event RECEIVE[7] */
53643   #define IPCT_INTPEND7_RECEIVE7_Pos (7UL)           /*!< Position of RECEIVE7 field.                                          */
53644   #define IPCT_INTPEND7_RECEIVE7_Msk (0x1UL << IPCT_INTPEND7_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field.                    */
53645   #define IPCT_INTPEND7_RECEIVE7_Min (0x0UL)         /*!< Min enumerator value of RECEIVE7 field.                              */
53646   #define IPCT_INTPEND7_RECEIVE7_Max (0x1UL)         /*!< Max enumerator value of RECEIVE7 field.                              */
53647   #define IPCT_INTPEND7_RECEIVE7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53648   #define IPCT_INTPEND7_RECEIVE7_Pending (0x1UL)     /*!< Read: Pending                                                        */
53649 
53650 /* RECEIVE8 @Bit 8 : Read pending status of interrupt for event RECEIVE[8] */
53651   #define IPCT_INTPEND7_RECEIVE8_Pos (8UL)           /*!< Position of RECEIVE8 field.                                          */
53652   #define IPCT_INTPEND7_RECEIVE8_Msk (0x1UL << IPCT_INTPEND7_RECEIVE8_Pos) /*!< Bit mask of RECEIVE8 field.                    */
53653   #define IPCT_INTPEND7_RECEIVE8_Min (0x0UL)         /*!< Min enumerator value of RECEIVE8 field.                              */
53654   #define IPCT_INTPEND7_RECEIVE8_Max (0x1UL)         /*!< Max enumerator value of RECEIVE8 field.                              */
53655   #define IPCT_INTPEND7_RECEIVE8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53656   #define IPCT_INTPEND7_RECEIVE8_Pending (0x1UL)     /*!< Read: Pending                                                        */
53657 
53658 /* RECEIVE9 @Bit 9 : Read pending status of interrupt for event RECEIVE[9] */
53659   #define IPCT_INTPEND7_RECEIVE9_Pos (9UL)           /*!< Position of RECEIVE9 field.                                          */
53660   #define IPCT_INTPEND7_RECEIVE9_Msk (0x1UL << IPCT_INTPEND7_RECEIVE9_Pos) /*!< Bit mask of RECEIVE9 field.                    */
53661   #define IPCT_INTPEND7_RECEIVE9_Min (0x0UL)         /*!< Min enumerator value of RECEIVE9 field.                              */
53662   #define IPCT_INTPEND7_RECEIVE9_Max (0x1UL)         /*!< Max enumerator value of RECEIVE9 field.                              */
53663   #define IPCT_INTPEND7_RECEIVE9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
53664   #define IPCT_INTPEND7_RECEIVE9_Pending (0x1UL)     /*!< Read: Pending                                                        */
53665 
53666 /* RECEIVE10 @Bit 10 : Read pending status of interrupt for event RECEIVE[10] */
53667   #define IPCT_INTPEND7_RECEIVE10_Pos (10UL)         /*!< Position of RECEIVE10 field.                                         */
53668   #define IPCT_INTPEND7_RECEIVE10_Msk (0x1UL << IPCT_INTPEND7_RECEIVE10_Pos) /*!< Bit mask of RECEIVE10 field.                 */
53669   #define IPCT_INTPEND7_RECEIVE10_Min (0x0UL)        /*!< Min enumerator value of RECEIVE10 field.                             */
53670   #define IPCT_INTPEND7_RECEIVE10_Max (0x1UL)        /*!< Max enumerator value of RECEIVE10 field.                             */
53671   #define IPCT_INTPEND7_RECEIVE10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
53672   #define IPCT_INTPEND7_RECEIVE10_Pending (0x1UL)    /*!< Read: Pending                                                        */
53673 
53674 /* RECEIVE11 @Bit 11 : Read pending status of interrupt for event RECEIVE[11] */
53675   #define IPCT_INTPEND7_RECEIVE11_Pos (11UL)         /*!< Position of RECEIVE11 field.                                         */
53676   #define IPCT_INTPEND7_RECEIVE11_Msk (0x1UL << IPCT_INTPEND7_RECEIVE11_Pos) /*!< Bit mask of RECEIVE11 field.                 */
53677   #define IPCT_INTPEND7_RECEIVE11_Min (0x0UL)        /*!< Min enumerator value of RECEIVE11 field.                             */
53678   #define IPCT_INTPEND7_RECEIVE11_Max (0x1UL)        /*!< Max enumerator value of RECEIVE11 field.                             */
53679   #define IPCT_INTPEND7_RECEIVE11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
53680   #define IPCT_INTPEND7_RECEIVE11_Pending (0x1UL)    /*!< Read: Pending                                                        */
53681 
53682 /* RECEIVE12 @Bit 12 : Read pending status of interrupt for event RECEIVE[12] */
53683   #define IPCT_INTPEND7_RECEIVE12_Pos (12UL)         /*!< Position of RECEIVE12 field.                                         */
53684   #define IPCT_INTPEND7_RECEIVE12_Msk (0x1UL << IPCT_INTPEND7_RECEIVE12_Pos) /*!< Bit mask of RECEIVE12 field.                 */
53685   #define IPCT_INTPEND7_RECEIVE12_Min (0x0UL)        /*!< Min enumerator value of RECEIVE12 field.                             */
53686   #define IPCT_INTPEND7_RECEIVE12_Max (0x1UL)        /*!< Max enumerator value of RECEIVE12 field.                             */
53687   #define IPCT_INTPEND7_RECEIVE12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
53688   #define IPCT_INTPEND7_RECEIVE12_Pending (0x1UL)    /*!< Read: Pending                                                        */
53689 
53690 /* RECEIVE13 @Bit 13 : Read pending status of interrupt for event RECEIVE[13] */
53691   #define IPCT_INTPEND7_RECEIVE13_Pos (13UL)         /*!< Position of RECEIVE13 field.                                         */
53692   #define IPCT_INTPEND7_RECEIVE13_Msk (0x1UL << IPCT_INTPEND7_RECEIVE13_Pos) /*!< Bit mask of RECEIVE13 field.                 */
53693   #define IPCT_INTPEND7_RECEIVE13_Min (0x0UL)        /*!< Min enumerator value of RECEIVE13 field.                             */
53694   #define IPCT_INTPEND7_RECEIVE13_Max (0x1UL)        /*!< Max enumerator value of RECEIVE13 field.                             */
53695   #define IPCT_INTPEND7_RECEIVE13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
53696   #define IPCT_INTPEND7_RECEIVE13_Pending (0x1UL)    /*!< Read: Pending                                                        */
53697 
53698 /* RECEIVE14 @Bit 14 : Read pending status of interrupt for event RECEIVE[14] */
53699   #define IPCT_INTPEND7_RECEIVE14_Pos (14UL)         /*!< Position of RECEIVE14 field.                                         */
53700   #define IPCT_INTPEND7_RECEIVE14_Msk (0x1UL << IPCT_INTPEND7_RECEIVE14_Pos) /*!< Bit mask of RECEIVE14 field.                 */
53701   #define IPCT_INTPEND7_RECEIVE14_Min (0x0UL)        /*!< Min enumerator value of RECEIVE14 field.                             */
53702   #define IPCT_INTPEND7_RECEIVE14_Max (0x1UL)        /*!< Max enumerator value of RECEIVE14 field.                             */
53703   #define IPCT_INTPEND7_RECEIVE14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
53704   #define IPCT_INTPEND7_RECEIVE14_Pending (0x1UL)    /*!< Read: Pending                                                        */
53705 
53706 /* RECEIVE15 @Bit 15 : Read pending status of interrupt for event RECEIVE[15] */
53707   #define IPCT_INTPEND7_RECEIVE15_Pos (15UL)         /*!< Position of RECEIVE15 field.                                         */
53708   #define IPCT_INTPEND7_RECEIVE15_Msk (0x1UL << IPCT_INTPEND7_RECEIVE15_Pos) /*!< Bit mask of RECEIVE15 field.                 */
53709   #define IPCT_INTPEND7_RECEIVE15_Min (0x0UL)        /*!< Min enumerator value of RECEIVE15 field.                             */
53710   #define IPCT_INTPEND7_RECEIVE15_Max (0x1UL)        /*!< Max enumerator value of RECEIVE15 field.                             */
53711   #define IPCT_INTPEND7_RECEIVE15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
53712   #define IPCT_INTPEND7_RECEIVE15_Pending (0x1UL)    /*!< Read: Pending                                                        */
53713 
53714 /* ACKED0 @Bit 16 : Read pending status of interrupt for event ACKED[0] */
53715   #define IPCT_INTPEND7_ACKED0_Pos (16UL)            /*!< Position of ACKED0 field.                                            */
53716   #define IPCT_INTPEND7_ACKED0_Msk (0x1UL << IPCT_INTPEND7_ACKED0_Pos) /*!< Bit mask of ACKED0 field.                          */
53717   #define IPCT_INTPEND7_ACKED0_Min (0x0UL)           /*!< Min enumerator value of ACKED0 field.                                */
53718   #define IPCT_INTPEND7_ACKED0_Max (0x1UL)           /*!< Max enumerator value of ACKED0 field.                                */
53719   #define IPCT_INTPEND7_ACKED0_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53720   #define IPCT_INTPEND7_ACKED0_Pending (0x1UL)       /*!< Read: Pending                                                        */
53721 
53722 /* ACKED1 @Bit 17 : Read pending status of interrupt for event ACKED[1] */
53723   #define IPCT_INTPEND7_ACKED1_Pos (17UL)            /*!< Position of ACKED1 field.                                            */
53724   #define IPCT_INTPEND7_ACKED1_Msk (0x1UL << IPCT_INTPEND7_ACKED1_Pos) /*!< Bit mask of ACKED1 field.                          */
53725   #define IPCT_INTPEND7_ACKED1_Min (0x0UL)           /*!< Min enumerator value of ACKED1 field.                                */
53726   #define IPCT_INTPEND7_ACKED1_Max (0x1UL)           /*!< Max enumerator value of ACKED1 field.                                */
53727   #define IPCT_INTPEND7_ACKED1_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53728   #define IPCT_INTPEND7_ACKED1_Pending (0x1UL)       /*!< Read: Pending                                                        */
53729 
53730 /* ACKED2 @Bit 18 : Read pending status of interrupt for event ACKED[2] */
53731   #define IPCT_INTPEND7_ACKED2_Pos (18UL)            /*!< Position of ACKED2 field.                                            */
53732   #define IPCT_INTPEND7_ACKED2_Msk (0x1UL << IPCT_INTPEND7_ACKED2_Pos) /*!< Bit mask of ACKED2 field.                          */
53733   #define IPCT_INTPEND7_ACKED2_Min (0x0UL)           /*!< Min enumerator value of ACKED2 field.                                */
53734   #define IPCT_INTPEND7_ACKED2_Max (0x1UL)           /*!< Max enumerator value of ACKED2 field.                                */
53735   #define IPCT_INTPEND7_ACKED2_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53736   #define IPCT_INTPEND7_ACKED2_Pending (0x1UL)       /*!< Read: Pending                                                        */
53737 
53738 /* ACKED3 @Bit 19 : Read pending status of interrupt for event ACKED[3] */
53739   #define IPCT_INTPEND7_ACKED3_Pos (19UL)            /*!< Position of ACKED3 field.                                            */
53740   #define IPCT_INTPEND7_ACKED3_Msk (0x1UL << IPCT_INTPEND7_ACKED3_Pos) /*!< Bit mask of ACKED3 field.                          */
53741   #define IPCT_INTPEND7_ACKED3_Min (0x0UL)           /*!< Min enumerator value of ACKED3 field.                                */
53742   #define IPCT_INTPEND7_ACKED3_Max (0x1UL)           /*!< Max enumerator value of ACKED3 field.                                */
53743   #define IPCT_INTPEND7_ACKED3_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53744   #define IPCT_INTPEND7_ACKED3_Pending (0x1UL)       /*!< Read: Pending                                                        */
53745 
53746 /* ACKED4 @Bit 20 : Read pending status of interrupt for event ACKED[4] */
53747   #define IPCT_INTPEND7_ACKED4_Pos (20UL)            /*!< Position of ACKED4 field.                                            */
53748   #define IPCT_INTPEND7_ACKED4_Msk (0x1UL << IPCT_INTPEND7_ACKED4_Pos) /*!< Bit mask of ACKED4 field.                          */
53749   #define IPCT_INTPEND7_ACKED4_Min (0x0UL)           /*!< Min enumerator value of ACKED4 field.                                */
53750   #define IPCT_INTPEND7_ACKED4_Max (0x1UL)           /*!< Max enumerator value of ACKED4 field.                                */
53751   #define IPCT_INTPEND7_ACKED4_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53752   #define IPCT_INTPEND7_ACKED4_Pending (0x1UL)       /*!< Read: Pending                                                        */
53753 
53754 /* ACKED5 @Bit 21 : Read pending status of interrupt for event ACKED[5] */
53755   #define IPCT_INTPEND7_ACKED5_Pos (21UL)            /*!< Position of ACKED5 field.                                            */
53756   #define IPCT_INTPEND7_ACKED5_Msk (0x1UL << IPCT_INTPEND7_ACKED5_Pos) /*!< Bit mask of ACKED5 field.                          */
53757   #define IPCT_INTPEND7_ACKED5_Min (0x0UL)           /*!< Min enumerator value of ACKED5 field.                                */
53758   #define IPCT_INTPEND7_ACKED5_Max (0x1UL)           /*!< Max enumerator value of ACKED5 field.                                */
53759   #define IPCT_INTPEND7_ACKED5_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53760   #define IPCT_INTPEND7_ACKED5_Pending (0x1UL)       /*!< Read: Pending                                                        */
53761 
53762 /* ACKED6 @Bit 22 : Read pending status of interrupt for event ACKED[6] */
53763   #define IPCT_INTPEND7_ACKED6_Pos (22UL)            /*!< Position of ACKED6 field.                                            */
53764   #define IPCT_INTPEND7_ACKED6_Msk (0x1UL << IPCT_INTPEND7_ACKED6_Pos) /*!< Bit mask of ACKED6 field.                          */
53765   #define IPCT_INTPEND7_ACKED6_Min (0x0UL)           /*!< Min enumerator value of ACKED6 field.                                */
53766   #define IPCT_INTPEND7_ACKED6_Max (0x1UL)           /*!< Max enumerator value of ACKED6 field.                                */
53767   #define IPCT_INTPEND7_ACKED6_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53768   #define IPCT_INTPEND7_ACKED6_Pending (0x1UL)       /*!< Read: Pending                                                        */
53769 
53770 /* ACKED7 @Bit 23 : Read pending status of interrupt for event ACKED[7] */
53771   #define IPCT_INTPEND7_ACKED7_Pos (23UL)            /*!< Position of ACKED7 field.                                            */
53772   #define IPCT_INTPEND7_ACKED7_Msk (0x1UL << IPCT_INTPEND7_ACKED7_Pos) /*!< Bit mask of ACKED7 field.                          */
53773   #define IPCT_INTPEND7_ACKED7_Min (0x0UL)           /*!< Min enumerator value of ACKED7 field.                                */
53774   #define IPCT_INTPEND7_ACKED7_Max (0x1UL)           /*!< Max enumerator value of ACKED7 field.                                */
53775   #define IPCT_INTPEND7_ACKED7_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53776   #define IPCT_INTPEND7_ACKED7_Pending (0x1UL)       /*!< Read: Pending                                                        */
53777 
53778 /* ACKED8 @Bit 24 : Read pending status of interrupt for event ACKED[8] */
53779   #define IPCT_INTPEND7_ACKED8_Pos (24UL)            /*!< Position of ACKED8 field.                                            */
53780   #define IPCT_INTPEND7_ACKED8_Msk (0x1UL << IPCT_INTPEND7_ACKED8_Pos) /*!< Bit mask of ACKED8 field.                          */
53781   #define IPCT_INTPEND7_ACKED8_Min (0x0UL)           /*!< Min enumerator value of ACKED8 field.                                */
53782   #define IPCT_INTPEND7_ACKED8_Max (0x1UL)           /*!< Max enumerator value of ACKED8 field.                                */
53783   #define IPCT_INTPEND7_ACKED8_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53784   #define IPCT_INTPEND7_ACKED8_Pending (0x1UL)       /*!< Read: Pending                                                        */
53785 
53786 /* ACKED9 @Bit 25 : Read pending status of interrupt for event ACKED[9] */
53787   #define IPCT_INTPEND7_ACKED9_Pos (25UL)            /*!< Position of ACKED9 field.                                            */
53788   #define IPCT_INTPEND7_ACKED9_Msk (0x1UL << IPCT_INTPEND7_ACKED9_Pos) /*!< Bit mask of ACKED9 field.                          */
53789   #define IPCT_INTPEND7_ACKED9_Min (0x0UL)           /*!< Min enumerator value of ACKED9 field.                                */
53790   #define IPCT_INTPEND7_ACKED9_Max (0x1UL)           /*!< Max enumerator value of ACKED9 field.                                */
53791   #define IPCT_INTPEND7_ACKED9_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
53792   #define IPCT_INTPEND7_ACKED9_Pending (0x1UL)       /*!< Read: Pending                                                        */
53793 
53794 /* ACKED10 @Bit 26 : Read pending status of interrupt for event ACKED[10] */
53795   #define IPCT_INTPEND7_ACKED10_Pos (26UL)           /*!< Position of ACKED10 field.                                           */
53796   #define IPCT_INTPEND7_ACKED10_Msk (0x1UL << IPCT_INTPEND7_ACKED10_Pos) /*!< Bit mask of ACKED10 field.                       */
53797   #define IPCT_INTPEND7_ACKED10_Min (0x0UL)          /*!< Min enumerator value of ACKED10 field.                               */
53798   #define IPCT_INTPEND7_ACKED10_Max (0x1UL)          /*!< Max enumerator value of ACKED10 field.                               */
53799   #define IPCT_INTPEND7_ACKED10_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
53800   #define IPCT_INTPEND7_ACKED10_Pending (0x1UL)      /*!< Read: Pending                                                        */
53801 
53802 /* ACKED11 @Bit 27 : Read pending status of interrupt for event ACKED[11] */
53803   #define IPCT_INTPEND7_ACKED11_Pos (27UL)           /*!< Position of ACKED11 field.                                           */
53804   #define IPCT_INTPEND7_ACKED11_Msk (0x1UL << IPCT_INTPEND7_ACKED11_Pos) /*!< Bit mask of ACKED11 field.                       */
53805   #define IPCT_INTPEND7_ACKED11_Min (0x0UL)          /*!< Min enumerator value of ACKED11 field.                               */
53806   #define IPCT_INTPEND7_ACKED11_Max (0x1UL)          /*!< Max enumerator value of ACKED11 field.                               */
53807   #define IPCT_INTPEND7_ACKED11_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
53808   #define IPCT_INTPEND7_ACKED11_Pending (0x1UL)      /*!< Read: Pending                                                        */
53809 
53810 /* ACKED12 @Bit 28 : Read pending status of interrupt for event ACKED[12] */
53811   #define IPCT_INTPEND7_ACKED12_Pos (28UL)           /*!< Position of ACKED12 field.                                           */
53812   #define IPCT_INTPEND7_ACKED12_Msk (0x1UL << IPCT_INTPEND7_ACKED12_Pos) /*!< Bit mask of ACKED12 field.                       */
53813   #define IPCT_INTPEND7_ACKED12_Min (0x0UL)          /*!< Min enumerator value of ACKED12 field.                               */
53814   #define IPCT_INTPEND7_ACKED12_Max (0x1UL)          /*!< Max enumerator value of ACKED12 field.                               */
53815   #define IPCT_INTPEND7_ACKED12_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
53816   #define IPCT_INTPEND7_ACKED12_Pending (0x1UL)      /*!< Read: Pending                                                        */
53817 
53818 /* ACKED13 @Bit 29 : Read pending status of interrupt for event ACKED[13] */
53819   #define IPCT_INTPEND7_ACKED13_Pos (29UL)           /*!< Position of ACKED13 field.                                           */
53820   #define IPCT_INTPEND7_ACKED13_Msk (0x1UL << IPCT_INTPEND7_ACKED13_Pos) /*!< Bit mask of ACKED13 field.                       */
53821   #define IPCT_INTPEND7_ACKED13_Min (0x0UL)          /*!< Min enumerator value of ACKED13 field.                               */
53822   #define IPCT_INTPEND7_ACKED13_Max (0x1UL)          /*!< Max enumerator value of ACKED13 field.                               */
53823   #define IPCT_INTPEND7_ACKED13_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
53824   #define IPCT_INTPEND7_ACKED13_Pending (0x1UL)      /*!< Read: Pending                                                        */
53825 
53826 /* ACKED14 @Bit 30 : Read pending status of interrupt for event ACKED[14] */
53827   #define IPCT_INTPEND7_ACKED14_Pos (30UL)           /*!< Position of ACKED14 field.                                           */
53828   #define IPCT_INTPEND7_ACKED14_Msk (0x1UL << IPCT_INTPEND7_ACKED14_Pos) /*!< Bit mask of ACKED14 field.                       */
53829   #define IPCT_INTPEND7_ACKED14_Min (0x0UL)          /*!< Min enumerator value of ACKED14 field.                               */
53830   #define IPCT_INTPEND7_ACKED14_Max (0x1UL)          /*!< Max enumerator value of ACKED14 field.                               */
53831   #define IPCT_INTPEND7_ACKED14_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
53832   #define IPCT_INTPEND7_ACKED14_Pending (0x1UL)      /*!< Read: Pending                                                        */
53833 
53834 /* ACKED15 @Bit 31 : Read pending status of interrupt for event ACKED[15] */
53835   #define IPCT_INTPEND7_ACKED15_Pos (31UL)           /*!< Position of ACKED15 field.                                           */
53836   #define IPCT_INTPEND7_ACKED15_Msk (0x1UL << IPCT_INTPEND7_ACKED15_Pos) /*!< Bit mask of ACKED15 field.                       */
53837   #define IPCT_INTPEND7_ACKED15_Min (0x0UL)          /*!< Min enumerator value of ACKED15 field.                               */
53838   #define IPCT_INTPEND7_ACKED15_Max (0x1UL)          /*!< Max enumerator value of ACKED15 field.                               */
53839   #define IPCT_INTPEND7_ACKED15_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
53840   #define IPCT_INTPEND7_ACKED15_Pending (0x1UL)      /*!< Read: Pending                                                        */
53841 
53842 
53843 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
53844 
53845 /* =========================================================================================================================== */
53846 /* ================                                          LPCOMP                                          ================ */
53847 /* =========================================================================================================================== */
53848 
53849 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
53850 /* ====================================================== Struct LPCOMP ====================================================== */
53851 /**
53852   * @brief Low-power comparator
53853   */
53854   typedef struct {                                   /*!< LPCOMP Structure                                                     */
53855     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start comparator                                      */
53856     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop comparator                                       */
53857     __OM uint32_t TASKS_SAMPLE;                      /*!< (@ 0x00000008) Sample comparator value                               */
53858     __IM uint32_t RESERVED[29];
53859     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
53860     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
53861     __IOM uint32_t SUBSCRIBE_SAMPLE;                 /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE               */
53862     __IM uint32_t RESERVED1[29];
53863     __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000100) LPCOMP is ready and output is valid                   */
53864     __IOM uint32_t EVENTS_DOWN;                      /*!< (@ 0x00000104) Downward crossing                                     */
53865     __IOM uint32_t EVENTS_UP;                        /*!< (@ 0x00000108) Upward crossing                                       */
53866     __IOM uint32_t EVENTS_CROSS;                     /*!< (@ 0x0000010C) Downward or upward crossing                           */
53867     __IM uint32_t RESERVED2[28];
53868     __IOM uint32_t PUBLISH_READY;                    /*!< (@ 0x00000180) Publish configuration for event READY                 */
53869     __IOM uint32_t PUBLISH_DOWN;                     /*!< (@ 0x00000184) Publish configuration for event DOWN                  */
53870     __IOM uint32_t PUBLISH_UP;                       /*!< (@ 0x00000188) Publish configuration for event UP                    */
53871     __IOM uint32_t PUBLISH_CROSS;                    /*!< (@ 0x0000018C) Publish configuration for event CROSS                 */
53872     __IM uint32_t RESERVED3[28];
53873     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
53874     __IM uint32_t RESERVED4[64];
53875     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
53876     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
53877     __IM uint32_t RESERVED5[61];
53878     __IM uint32_t RESULT;                            /*!< (@ 0x00000400) Compare result                                        */
53879     __IM uint32_t RESERVED6[63];
53880     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable LPCOMP                                         */
53881     __IOM uint32_t PSEL;                             /*!< (@ 0x00000504) Input pin select                                      */
53882     __IOM uint32_t REFSEL;                           /*!< (@ 0x00000508) Reference select                                      */
53883     __IOM uint32_t EXTREFSEL;                        /*!< (@ 0x0000050C) External reference select                             */
53884     __IM uint32_t RESERVED7[2];
53885     __IOM uint32_t CONFIGVOLTLVL;                    /*!< (@ 0x00000518) Configure voltage level for analog input              */
53886     __IM uint32_t RESERVED8;
53887     __IOM uint32_t ANADETECT;                        /*!< (@ 0x00000520) Analog detect configuration                           */
53888     __IM uint32_t RESERVED9[5];
53889     __IOM uint32_t HYST;                             /*!< (@ 0x00000538) Comparator hysteresis enable                          */
53890   } NRF_LPCOMP_Type;                                 /*!< Size = 1340 (0x53C)                                                  */
53891 
53892 /* LPCOMP_TASKS_START: Start comparator */
53893   #define LPCOMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                               */
53894 
53895 /* TASKS_START @Bit 0 : Start comparator */
53896   #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL)   /*!< Position of TASKS_START field.                                       */
53897   #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
53898   #define LPCOMP_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field.                           */
53899   #define LPCOMP_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field.                           */
53900   #define LPCOMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                     */
53901 
53902 
53903 /* LPCOMP_TASKS_STOP: Stop comparator */
53904   #define LPCOMP_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                 */
53905 
53906 /* TASKS_STOP @Bit 0 : Stop comparator */
53907   #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL)     /*!< Position of TASKS_STOP field.                                        */
53908   #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.      */
53909   #define LPCOMP_TASKS_STOP_TASKS_STOP_Min (0x1UL)   /*!< Min enumerator value of TASKS_STOP field.                            */
53910   #define LPCOMP_TASKS_STOP_TASKS_STOP_Max (0x1UL)   /*!< Max enumerator value of TASKS_STOP field.                            */
53911   #define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                       */
53912 
53913 
53914 /* LPCOMP_TASKS_SAMPLE: Sample comparator value */
53915   #define LPCOMP_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register.                             */
53916 
53917 /* TASKS_SAMPLE @Bit 0 : Sample comparator value */
53918   #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field.                                      */
53919   #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE
53920                                                                             field.*/
53921   #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field.                        */
53922   #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field.                        */
53923   #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task                                                   */
53924 
53925 
53926 /* LPCOMP_SUBSCRIBE_START: Subscribe configuration for task START */
53927   #define LPCOMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                       */
53928 
53929 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
53930   #define LPCOMP_SUBSCRIBE_START_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
53931   #define LPCOMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
53932   #define LPCOMP_SUBSCRIBE_START_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
53933   #define LPCOMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
53934 
53935 /* EN @Bit 31 : (unspecified) */
53936   #define LPCOMP_SUBSCRIBE_START_EN_Pos (31UL)       /*!< Position of EN field.                                                */
53937   #define LPCOMP_SUBSCRIBE_START_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                    */
53938   #define LPCOMP_SUBSCRIBE_START_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
53939   #define LPCOMP_SUBSCRIBE_START_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
53940   #define LPCOMP_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
53941   #define LPCOMP_SUBSCRIBE_START_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
53942 
53943 
53944 /* LPCOMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
53945   #define LPCOMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                         */
53946 
53947 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
53948   #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
53949   #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
53950   #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
53951   #define LPCOMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
53952 
53953 /* EN @Bit 31 : (unspecified) */
53954   #define LPCOMP_SUBSCRIBE_STOP_EN_Pos (31UL)        /*!< Position of EN field.                                                */
53955   #define LPCOMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                      */
53956   #define LPCOMP_SUBSCRIBE_STOP_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
53957   #define LPCOMP_SUBSCRIBE_STOP_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
53958   #define LPCOMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
53959   #define LPCOMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
53960 
53961 
53962 /* LPCOMP_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */
53963   #define LPCOMP_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register.                     */
53964 
53965 /* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */
53966   #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
53967   #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
53968   #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
53969   #define LPCOMP_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
53970 
53971 /* EN @Bit 31 : (unspecified) */
53972   #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos (31UL)      /*!< Position of EN field.                                                */
53973   #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << LPCOMP_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field.                  */
53974   #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
53975   #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
53976   #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
53977   #define LPCOMP_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
53978 
53979 
53980 /* LPCOMP_EVENTS_READY: LPCOMP is ready and output is valid */
53981   #define LPCOMP_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                             */
53982 
53983 /* EVENTS_READY @Bit 0 : LPCOMP is ready and output is valid */
53984   #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field.                                      */
53985   #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY
53986                                                                             field.*/
53987   #define LPCOMP_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                        */
53988   #define LPCOMP_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                        */
53989   #define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                       */
53990   #define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                              */
53991 
53992 
53993 /* LPCOMP_EVENTS_DOWN: Downward crossing */
53994   #define LPCOMP_EVENTS_DOWN_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DOWN register.                               */
53995 
53996 /* EVENTS_DOWN @Bit 0 : Downward crossing */
53997   #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL)   /*!< Position of EVENTS_DOWN field.                                       */
53998   #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
53999   #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Min (0x0UL) /*!< Min enumerator value of EVENTS_DOWN field.                           */
54000   #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Max (0x1UL) /*!< Max enumerator value of EVENTS_DOWN field.                           */
54001   #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0x0UL) /*!< Event not generated                                         */
54002   #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (0x1UL) /*!< Event generated                                                */
54003 
54004 
54005 /* LPCOMP_EVENTS_UP: Upward crossing */
54006   #define LPCOMP_EVENTS_UP_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_UP register.                                   */
54007 
54008 /* EVENTS_UP @Bit 0 : Upward crossing */
54009   #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL)       /*!< Position of EVENTS_UP field.                                         */
54010   #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field.           */
54011   #define LPCOMP_EVENTS_UP_EVENTS_UP_Min (0x0UL)     /*!< Min enumerator value of EVENTS_UP field.                             */
54012   #define LPCOMP_EVENTS_UP_EVENTS_UP_Max (0x1UL)     /*!< Max enumerator value of EVENTS_UP field.                             */
54013   #define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0x0UL) /*!< Event not generated                                             */
54014   #define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (0x1UL) /*!< Event generated                                                    */
54015 
54016 
54017 /* LPCOMP_EVENTS_CROSS: Downward or upward crossing */
54018   #define LPCOMP_EVENTS_CROSS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CROSS register.                             */
54019 
54020 /* EVENTS_CROSS @Bit 0 : Downward or upward crossing */
54021   #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field.                                      */
54022   #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS
54023                                                                             field.*/
54024   #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Min (0x0UL) /*!< Min enumerator value of EVENTS_CROSS field.                        */
54025   #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Max (0x1UL) /*!< Max enumerator value of EVENTS_CROSS field.                        */
54026   #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0x0UL) /*!< Event not generated                                       */
54027   #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (0x1UL) /*!< Event generated                                              */
54028 
54029 
54030 /* LPCOMP_PUBLISH_READY: Publish configuration for event READY */
54031   #define LPCOMP_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register.                           */
54032 
54033 /* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
54034   #define LPCOMP_PUBLISH_READY_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
54035   #define LPCOMP_PUBLISH_READY_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
54036   #define LPCOMP_PUBLISH_READY_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
54037   #define LPCOMP_PUBLISH_READY_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
54038 
54039 /* EN @Bit 31 : (unspecified) */
54040   #define LPCOMP_PUBLISH_READY_EN_Pos (31UL)         /*!< Position of EN field.                                                */
54041   #define LPCOMP_PUBLISH_READY_EN_Msk (0x1UL << LPCOMP_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field.                        */
54042   #define LPCOMP_PUBLISH_READY_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
54043   #define LPCOMP_PUBLISH_READY_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
54044   #define LPCOMP_PUBLISH_READY_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
54045   #define LPCOMP_PUBLISH_READY_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
54046 
54047 
54048 /* LPCOMP_PUBLISH_DOWN: Publish configuration for event DOWN */
54049   #define LPCOMP_PUBLISH_DOWN_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DOWN register.                             */
54050 
54051 /* CHIDX @Bits 0..7 : DPPI channel that event DOWN will publish to */
54052   #define LPCOMP_PUBLISH_DOWN_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
54053   #define LPCOMP_PUBLISH_DOWN_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_DOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
54054   #define LPCOMP_PUBLISH_DOWN_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
54055   #define LPCOMP_PUBLISH_DOWN_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
54056 
54057 /* EN @Bit 31 : (unspecified) */
54058   #define LPCOMP_PUBLISH_DOWN_EN_Pos (31UL)          /*!< Position of EN field.                                                */
54059   #define LPCOMP_PUBLISH_DOWN_EN_Msk (0x1UL << LPCOMP_PUBLISH_DOWN_EN_Pos) /*!< Bit mask of EN field.                          */
54060   #define LPCOMP_PUBLISH_DOWN_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
54061   #define LPCOMP_PUBLISH_DOWN_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
54062   #define LPCOMP_PUBLISH_DOWN_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
54063   #define LPCOMP_PUBLISH_DOWN_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
54064 
54065 
54066 /* LPCOMP_PUBLISH_UP: Publish configuration for event UP */
54067   #define LPCOMP_PUBLISH_UP_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_UP register.                                 */
54068 
54069 /* CHIDX @Bits 0..7 : DPPI channel that event UP will publish to */
54070   #define LPCOMP_PUBLISH_UP_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
54071   #define LPCOMP_PUBLISH_UP_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_UP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
54072   #define LPCOMP_PUBLISH_UP_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
54073   #define LPCOMP_PUBLISH_UP_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
54074 
54075 /* EN @Bit 31 : (unspecified) */
54076   #define LPCOMP_PUBLISH_UP_EN_Pos (31UL)            /*!< Position of EN field.                                                */
54077   #define LPCOMP_PUBLISH_UP_EN_Msk (0x1UL << LPCOMP_PUBLISH_UP_EN_Pos) /*!< Bit mask of EN field.                              */
54078   #define LPCOMP_PUBLISH_UP_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
54079   #define LPCOMP_PUBLISH_UP_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
54080   #define LPCOMP_PUBLISH_UP_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
54081   #define LPCOMP_PUBLISH_UP_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
54082 
54083 
54084 /* LPCOMP_PUBLISH_CROSS: Publish configuration for event CROSS */
54085   #define LPCOMP_PUBLISH_CROSS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CROSS register.                           */
54086 
54087 /* CHIDX @Bits 0..7 : DPPI channel that event CROSS will publish to */
54088   #define LPCOMP_PUBLISH_CROSS_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
54089   #define LPCOMP_PUBLISH_CROSS_CHIDX_Msk (0xFFUL << LPCOMP_PUBLISH_CROSS_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
54090   #define LPCOMP_PUBLISH_CROSS_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
54091   #define LPCOMP_PUBLISH_CROSS_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
54092 
54093 /* EN @Bit 31 : (unspecified) */
54094   #define LPCOMP_PUBLISH_CROSS_EN_Pos (31UL)         /*!< Position of EN field.                                                */
54095   #define LPCOMP_PUBLISH_CROSS_EN_Msk (0x1UL << LPCOMP_PUBLISH_CROSS_EN_Pos) /*!< Bit mask of EN field.                        */
54096   #define LPCOMP_PUBLISH_CROSS_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
54097   #define LPCOMP_PUBLISH_CROSS_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
54098   #define LPCOMP_PUBLISH_CROSS_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
54099   #define LPCOMP_PUBLISH_CROSS_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
54100 
54101 
54102 /* LPCOMP_SHORTS: Shortcuts between local events and tasks */
54103   #define LPCOMP_SHORTS_ResetValue (0x00000000UL)    /*!< Reset value of SHORTS register.                                      */
54104 
54105 /* READY_SAMPLE @Bit 0 : Shortcut between event READY and task SAMPLE */
54106   #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL)       /*!< Position of READY_SAMPLE field.                                      */
54107   #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field.        */
54108   #define LPCOMP_SHORTS_READY_SAMPLE_Min (0x0UL)     /*!< Min enumerator value of READY_SAMPLE field.                          */
54109   #define LPCOMP_SHORTS_READY_SAMPLE_Max (0x1UL)     /*!< Max enumerator value of READY_SAMPLE field.                          */
54110   #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0x0UL) /*!< Disable shortcut                                                    */
54111   #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (0x1UL) /*!< Enable shortcut                                                      */
54112 
54113 /* READY_STOP @Bit 1 : Shortcut between event READY and task STOP */
54114   #define LPCOMP_SHORTS_READY_STOP_Pos (1UL)         /*!< Position of READY_STOP field.                                        */
54115   #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field.              */
54116   #define LPCOMP_SHORTS_READY_STOP_Min (0x0UL)       /*!< Min enumerator value of READY_STOP field.                            */
54117   #define LPCOMP_SHORTS_READY_STOP_Max (0x1UL)       /*!< Max enumerator value of READY_STOP field.                            */
54118   #define LPCOMP_SHORTS_READY_STOP_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
54119   #define LPCOMP_SHORTS_READY_STOP_Enabled (0x1UL)   /*!< Enable shortcut                                                      */
54120 
54121 /* DOWN_STOP @Bit 2 : Shortcut between event DOWN and task STOP */
54122   #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL)          /*!< Position of DOWN_STOP field.                                         */
54123   #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field.                 */
54124   #define LPCOMP_SHORTS_DOWN_STOP_Min (0x0UL)        /*!< Min enumerator value of DOWN_STOP field.                             */
54125   #define LPCOMP_SHORTS_DOWN_STOP_Max (0x1UL)        /*!< Max enumerator value of DOWN_STOP field.                             */
54126   #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
54127   #define LPCOMP_SHORTS_DOWN_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */
54128 
54129 /* UP_STOP @Bit 3 : Shortcut between event UP and task STOP */
54130   #define LPCOMP_SHORTS_UP_STOP_Pos (3UL)            /*!< Position of UP_STOP field.                                           */
54131   #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field.                       */
54132   #define LPCOMP_SHORTS_UP_STOP_Min (0x0UL)          /*!< Min enumerator value of UP_STOP field.                               */
54133   #define LPCOMP_SHORTS_UP_STOP_Max (0x1UL)          /*!< Max enumerator value of UP_STOP field.                               */
54134   #define LPCOMP_SHORTS_UP_STOP_Disabled (0x0UL)     /*!< Disable shortcut                                                     */
54135   #define LPCOMP_SHORTS_UP_STOP_Enabled (0x1UL)      /*!< Enable shortcut                                                      */
54136 
54137 /* CROSS_STOP @Bit 4 : Shortcut between event CROSS and task STOP */
54138   #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL)         /*!< Position of CROSS_STOP field.                                        */
54139   #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field.              */
54140   #define LPCOMP_SHORTS_CROSS_STOP_Min (0x0UL)       /*!< Min enumerator value of CROSS_STOP field.                            */
54141   #define LPCOMP_SHORTS_CROSS_STOP_Max (0x1UL)       /*!< Max enumerator value of CROSS_STOP field.                            */
54142   #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
54143   #define LPCOMP_SHORTS_CROSS_STOP_Enabled (0x1UL)   /*!< Enable shortcut                                                      */
54144 
54145 
54146 /* LPCOMP_INTENSET: Enable interrupt */
54147   #define LPCOMP_INTENSET_ResetValue (0x00000000UL)  /*!< Reset value of INTENSET register.                                    */
54148 
54149 /* READY @Bit 0 : Write '1' to enable interrupt for event READY */
54150   #define LPCOMP_INTENSET_READY_Pos (0UL)            /*!< Position of READY field.                                             */
54151   #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field.                         */
54152   #define LPCOMP_INTENSET_READY_Min (0x0UL)          /*!< Min enumerator value of READY field.                                 */
54153   #define LPCOMP_INTENSET_READY_Max (0x1UL)          /*!< Max enumerator value of READY field.                                 */
54154   #define LPCOMP_INTENSET_READY_Set (0x1UL)          /*!< Enable                                                               */
54155   #define LPCOMP_INTENSET_READY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
54156   #define LPCOMP_INTENSET_READY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
54157 
54158 /* DOWN @Bit 1 : Write '1' to enable interrupt for event DOWN */
54159   #define LPCOMP_INTENSET_DOWN_Pos (1UL)             /*!< Position of DOWN field.                                              */
54160   #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field.                            */
54161   #define LPCOMP_INTENSET_DOWN_Min (0x0UL)           /*!< Min enumerator value of DOWN field.                                  */
54162   #define LPCOMP_INTENSET_DOWN_Max (0x1UL)           /*!< Max enumerator value of DOWN field.                                  */
54163   #define LPCOMP_INTENSET_DOWN_Set (0x1UL)           /*!< Enable                                                               */
54164   #define LPCOMP_INTENSET_DOWN_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
54165   #define LPCOMP_INTENSET_DOWN_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
54166 
54167 /* UP @Bit 2 : Write '1' to enable interrupt for event UP */
54168   #define LPCOMP_INTENSET_UP_Pos (2UL)               /*!< Position of UP field.                                                */
54169   #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field.                                  */
54170   #define LPCOMP_INTENSET_UP_Min (0x0UL)             /*!< Min enumerator value of UP field.                                    */
54171   #define LPCOMP_INTENSET_UP_Max (0x1UL)             /*!< Max enumerator value of UP field.                                    */
54172   #define LPCOMP_INTENSET_UP_Set (0x1UL)             /*!< Enable                                                               */
54173   #define LPCOMP_INTENSET_UP_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
54174   #define LPCOMP_INTENSET_UP_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
54175 
54176 /* CROSS @Bit 3 : Write '1' to enable interrupt for event CROSS */
54177   #define LPCOMP_INTENSET_CROSS_Pos (3UL)            /*!< Position of CROSS field.                                             */
54178   #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field.                         */
54179   #define LPCOMP_INTENSET_CROSS_Min (0x0UL)          /*!< Min enumerator value of CROSS field.                                 */
54180   #define LPCOMP_INTENSET_CROSS_Max (0x1UL)          /*!< Max enumerator value of CROSS field.                                 */
54181   #define LPCOMP_INTENSET_CROSS_Set (0x1UL)          /*!< Enable                                                               */
54182   #define LPCOMP_INTENSET_CROSS_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
54183   #define LPCOMP_INTENSET_CROSS_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
54184 
54185 
54186 /* LPCOMP_INTENCLR: Disable interrupt */
54187   #define LPCOMP_INTENCLR_ResetValue (0x00000000UL)  /*!< Reset value of INTENCLR register.                                    */
54188 
54189 /* READY @Bit 0 : Write '1' to disable interrupt for event READY */
54190   #define LPCOMP_INTENCLR_READY_Pos (0UL)            /*!< Position of READY field.                                             */
54191   #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field.                         */
54192   #define LPCOMP_INTENCLR_READY_Min (0x0UL)          /*!< Min enumerator value of READY field.                                 */
54193   #define LPCOMP_INTENCLR_READY_Max (0x1UL)          /*!< Max enumerator value of READY field.                                 */
54194   #define LPCOMP_INTENCLR_READY_Clear (0x1UL)        /*!< Disable                                                              */
54195   #define LPCOMP_INTENCLR_READY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
54196   #define LPCOMP_INTENCLR_READY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
54197 
54198 /* DOWN @Bit 1 : Write '1' to disable interrupt for event DOWN */
54199   #define LPCOMP_INTENCLR_DOWN_Pos (1UL)             /*!< Position of DOWN field.                                              */
54200   #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field.                            */
54201   #define LPCOMP_INTENCLR_DOWN_Min (0x0UL)           /*!< Min enumerator value of DOWN field.                                  */
54202   #define LPCOMP_INTENCLR_DOWN_Max (0x1UL)           /*!< Max enumerator value of DOWN field.                                  */
54203   #define LPCOMP_INTENCLR_DOWN_Clear (0x1UL)         /*!< Disable                                                              */
54204   #define LPCOMP_INTENCLR_DOWN_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
54205   #define LPCOMP_INTENCLR_DOWN_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
54206 
54207 /* UP @Bit 2 : Write '1' to disable interrupt for event UP */
54208   #define LPCOMP_INTENCLR_UP_Pos (2UL)               /*!< Position of UP field.                                                */
54209   #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field.                                  */
54210   #define LPCOMP_INTENCLR_UP_Min (0x0UL)             /*!< Min enumerator value of UP field.                                    */
54211   #define LPCOMP_INTENCLR_UP_Max (0x1UL)             /*!< Max enumerator value of UP field.                                    */
54212   #define LPCOMP_INTENCLR_UP_Clear (0x1UL)           /*!< Disable                                                              */
54213   #define LPCOMP_INTENCLR_UP_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
54214   #define LPCOMP_INTENCLR_UP_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
54215 
54216 /* CROSS @Bit 3 : Write '1' to disable interrupt for event CROSS */
54217   #define LPCOMP_INTENCLR_CROSS_Pos (3UL)            /*!< Position of CROSS field.                                             */
54218   #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field.                         */
54219   #define LPCOMP_INTENCLR_CROSS_Min (0x0UL)          /*!< Min enumerator value of CROSS field.                                 */
54220   #define LPCOMP_INTENCLR_CROSS_Max (0x1UL)          /*!< Max enumerator value of CROSS field.                                 */
54221   #define LPCOMP_INTENCLR_CROSS_Clear (0x1UL)        /*!< Disable                                                              */
54222   #define LPCOMP_INTENCLR_CROSS_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
54223   #define LPCOMP_INTENCLR_CROSS_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
54224 
54225 
54226 /* LPCOMP_RESULT: Compare result */
54227   #define LPCOMP_RESULT_ResetValue (0x00000000UL)    /*!< Reset value of RESULT register.                                      */
54228 
54229 /* RESULT @Bit 0 : Result of last compare. Decision point SAMPLE task. */
54230   #define LPCOMP_RESULT_RESULT_Pos (0UL)             /*!< Position of RESULT field.                                            */
54231   #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field.                          */
54232   #define LPCOMP_RESULT_RESULT_Min (0x0UL)           /*!< Min enumerator value of RESULT field.                                */
54233   #define LPCOMP_RESULT_RESULT_Max (0x1UL)           /*!< Max enumerator value of RESULT field.                                */
54234   #define LPCOMP_RESULT_RESULT_Below (0x0UL)         /*!< Input voltage is below the reference threshold (VIN+ < VIN-)         */
54235   #define LPCOMP_RESULT_RESULT_Above (0x1UL)         /*!< Input voltage is above the reference threshold (VIN+ > VIN-)         */
54236 
54237 
54238 /* LPCOMP_ENABLE: Enable LPCOMP */
54239   #define LPCOMP_ENABLE_ResetValue (0x00000000UL)    /*!< Reset value of ENABLE register.                                      */
54240 
54241 /* ENABLE @Bits 0..1 : Enable or disable LPCOMP */
54242   #define LPCOMP_ENABLE_ENABLE_Pos (0UL)             /*!< Position of ENABLE field.                                            */
54243   #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                          */
54244   #define LPCOMP_ENABLE_ENABLE_Min (0x0UL)           /*!< Min enumerator value of ENABLE field.                                */
54245   #define LPCOMP_ENABLE_ENABLE_Max (0x1UL)           /*!< Max enumerator value of ENABLE field.                                */
54246   #define LPCOMP_ENABLE_ENABLE_Disabled (0x0UL)      /*!< Disable                                                              */
54247   #define LPCOMP_ENABLE_ENABLE_Enabled (0x1UL)       /*!< Enable                                                               */
54248 
54249 
54250 /* LPCOMP_PSEL: Input pin select */
54251   #define LPCOMP_PSEL_ResetValue (0x00000000UL)      /*!< Reset value of PSEL register.                                        */
54252 
54253 /* PSEL @Bits 0..3 : Analog pin select */
54254   #define LPCOMP_PSEL_PSEL_Pos (0UL)                 /*!< Position of PSEL field.                                              */
54255   #define LPCOMP_PSEL_PSEL_Msk (0xFUL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field.                                    */
54256   #define LPCOMP_PSEL_PSEL_Min (0x0UL)               /*!< Min enumerator value of PSEL field.                                  */
54257   #define LPCOMP_PSEL_PSEL_Max (0x9UL)               /*!< Max enumerator value of PSEL field.                                  */
54258   #define LPCOMP_PSEL_PSEL_AnalogInput0 (0x0UL)      /*!< AIN0 selected as analog input                                        */
54259   #define LPCOMP_PSEL_PSEL_AnalogInput1 (0x1UL)      /*!< AIN1 selected as analog input                                        */
54260   #define LPCOMP_PSEL_PSEL_AnalogInput2 (0x2UL)      /*!< AIN2 selected as analog input                                        */
54261   #define LPCOMP_PSEL_PSEL_AnalogInput3 (0x3UL)      /*!< AIN3 selected as analog input                                        */
54262   #define LPCOMP_PSEL_PSEL_AnalogInput4 (0x4UL)      /*!< AIN4 selected as analog input                                        */
54263   #define LPCOMP_PSEL_PSEL_AnalogInput5 (0x5UL)      /*!< AIN5 selected as analog input                                        */
54264   #define LPCOMP_PSEL_PSEL_AnalogInput6 (0x6UL)      /*!< AIN6 selected as analog input                                        */
54265   #define LPCOMP_PSEL_PSEL_AnalogInput7 (0x7UL)      /*!< AIN7 selected as analog input                                        */
54266   #define LPCOMP_PSEL_PSEL_AnalogInput8 (0x8UL)      /*!< AIN8 selected as analog input                                        */
54267   #define LPCOMP_PSEL_PSEL_AnalogInput9 (0x9UL)      /*!< AIN9 selected as analog input                                        */
54268 
54269 
54270 /* LPCOMP_REFSEL: Reference select */
54271   #define LPCOMP_REFSEL_ResetValue (0x00000004UL)    /*!< Reset value of REFSEL register.                                      */
54272 
54273 /* REFSEL @Bits 0..3 : Reference select */
54274   #define LPCOMP_REFSEL_REFSEL_Pos (0UL)             /*!< Position of REFSEL field.                                            */
54275   #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field.                          */
54276   #define LPCOMP_REFSEL_REFSEL_Min (0x0UL)           /*!< Min enumerator value of REFSEL field.                                */
54277   #define LPCOMP_REFSEL_REFSEL_Max (0xFUL)           /*!< Max enumerator value of REFSEL field.                                */
54278   #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0x0UL)     /*!< VDD * 1/8 selected as reference                                      */
54279   #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (0x1UL)     /*!< VDD * 2/8 selected as reference                                      */
54280   #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (0x2UL)     /*!< VDD * 3/8 selected as reference                                      */
54281   #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (0x3UL)     /*!< VDD * 4/8 selected as reference                                      */
54282   #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (0x4UL)     /*!< VDD * 5/8 selected as reference                                      */
54283   #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (0x5UL)     /*!< VDD * 6/8 selected as reference                                      */
54284   #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (0x6UL)     /*!< VDD * 7/8 selected as reference                                      */
54285   #define LPCOMP_REFSEL_REFSEL_ARef (0x7UL)          /*!< External analog reference selected                                   */
54286   #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (0x8UL)    /*!< VDD * 1/16 selected as reference                                     */
54287   #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (0x9UL)    /*!< VDD * 3/16 selected as reference                                     */
54288   #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (0xAUL)    /*!< VDD * 5/16 selected as reference                                     */
54289   #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (0xBUL)    /*!< VDD * 7/16 selected as reference                                     */
54290   #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (0xCUL)    /*!< VDD * 9/16 selected as reference                                     */
54291   #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (0xDUL)   /*!< VDD * 11/16 selected as reference                                    */
54292   #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (0xEUL)   /*!< VDD * 13/16 selected as reference                                    */
54293   #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (0xFUL)   /*!< VDD * 15/16 selected as reference                                    */
54294 
54295 
54296 /* LPCOMP_EXTREFSEL: External reference select */
54297   #define LPCOMP_EXTREFSEL_ResetValue (0x00000000UL) /*!< Reset value of EXTREFSEL register.                                   */
54298 
54299 /* EXTREFSEL @Bit 0 : External analog reference select */
54300   #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL)       /*!< Position of EXTREFSEL field.                                         */
54301   #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field.           */
54302   #define LPCOMP_EXTREFSEL_EXTREFSEL_Min (0x0UL)     /*!< Min enumerator value of EXTREFSEL field.                             */
54303   #define LPCOMP_EXTREFSEL_EXTREFSEL_Max (0x1UL)     /*!< Max enumerator value of EXTREFSEL field.                             */
54304   #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0x0UL) /*!< Use AIN0 as external analog reference                       */
54305   #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (0x1UL) /*!< Use AIN1 as external analog reference                       */
54306 
54307 
54308 /* LPCOMP_CONFIGVOLTLVL: Configure voltage level for analog input */
54309   #define LPCOMP_CONFIGVOLTLVL_ResetValue (0x00000000UL) /*!< Reset value of CONFIGVOLTLVL register.                           */
54310 
54311 /* EN @Bit 0 : Enable 3.3V on analog input */
54312   #define LPCOMP_CONFIGVOLTLVL_EN_Pos (0UL)          /*!< Position of EN field.                                                */
54313   #define LPCOMP_CONFIGVOLTLVL_EN_Msk (0x1UL << LPCOMP_CONFIGVOLTLVL_EN_Pos) /*!< Bit mask of EN field.                        */
54314   #define LPCOMP_CONFIGVOLTLVL_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
54315   #define LPCOMP_CONFIGVOLTLVL_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
54316   #define LPCOMP_CONFIGVOLTLVL_EN_Disable (0x0UL)    /*!< Disable                                                              */
54317   #define LPCOMP_CONFIGVOLTLVL_EN_Enable (0x1UL)     /*!< Enable                                                               */
54318 
54319 
54320 /* LPCOMP_ANADETECT: Analog detect configuration */
54321   #define LPCOMP_ANADETECT_ResetValue (0x00000000UL) /*!< Reset value of ANADETECT register.                                   */
54322 
54323 /* ANADETECT @Bits 0..1 : Analog detect configuration */
54324   #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL)       /*!< Position of ANADETECT field.                                         */
54325   #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field.           */
54326   #define LPCOMP_ANADETECT_ANADETECT_Min (0x0UL)     /*!< Min enumerator value of ANADETECT field.                             */
54327   #define LPCOMP_ANADETECT_ANADETECT_Max (0x2UL)     /*!< Max enumerator value of ANADETECT field.                             */
54328   #define LPCOMP_ANADETECT_ANADETECT_Cross (0x0UL)   /*!< Generate ANADETECT on crossing, both upward crossing and downward
54329                                                           crossing*/
54330   #define LPCOMP_ANADETECT_ANADETECT_Up (0x1UL)      /*!< Generate ANADETECT on upward crossing only                           */
54331   #define LPCOMP_ANADETECT_ANADETECT_Down (0x2UL)    /*!< Generate ANADETECT on downward crossing only                         */
54332 
54333 
54334 /* LPCOMP_HYST: Comparator hysteresis enable */
54335   #define LPCOMP_HYST_ResetValue (0x00000000UL)      /*!< Reset value of HYST register.                                        */
54336 
54337 /* HYST @Bit 0 : Comparator hysteresis enable */
54338   #define LPCOMP_HYST_HYST_Pos (0UL)                 /*!< Position of HYST field.                                              */
54339   #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field.                                    */
54340   #define LPCOMP_HYST_HYST_Min (0x0UL)               /*!< Min enumerator value of HYST field.                                  */
54341   #define LPCOMP_HYST_HYST_Max (0x1UL)               /*!< Max enumerator value of HYST field.                                  */
54342   #define LPCOMP_HYST_HYST_Disabled (0x0UL)          /*!< Comparator hysteresis disabled                                       */
54343   #define LPCOMP_HYST_HYST_Enabled (0x1UL)           /*!< Comparator hysteresis enabled                                        */
54344 
54345 
54346 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
54347 
54348 /* =========================================================================================================================== */
54349 /* ================                                          LRCCONF                                          ================ */
54350 /* =========================================================================================================================== */
54351 
54352 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
54353 
54354 /* ============================================== Struct LRCCONF_TASKS_CONSTLAT ============================================== */
54355 /**
54356   * @brief TASKS_CONSTLAT [LRCCONF_TASKS_CONSTLAT] Peripheral tasks.
54357   */
54358 typedef struct {
54359   __OM  uint32_t  ENABLE;                            /*!< (@ 0x00000000) Enable constant latency mode                          */
54360   __OM  uint32_t  DISABLE;                           /*!< (@ 0x00000004) Disable constant latency mode                         */
54361 } NRF_LRCCONF_TASKS_CONSTLAT_Type;                   /*!< Size = 8 (0x008)                                                     */
54362 
54363 /* LRCCONF_TASKS_CONSTLAT_ENABLE: Enable constant latency mode */
54364   #define LRCCONF_TASKS_CONSTLAT_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register.                         */
54365 
54366 /* ENABLE @Bit 0 : Enable constant latency mode */
54367   #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                        */
54368   #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Msk (0x1UL << LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE
54369                                                                             field.*/
54370   #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Min (0x1UL) /*!< Min enumerator value of ENABLE field.                          */
54371   #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                          */
54372   #define LRCCONF_TASKS_CONSTLAT_ENABLE_ENABLE_Trigger (0x1UL) /*!< Trigger task                                               */
54373 
54374 
54375 /* LRCCONF_TASKS_CONSTLAT_DISABLE: Disable constant latency mode */
54376   #define LRCCONF_TASKS_CONSTLAT_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of DISABLE register.                       */
54377 
54378 /* DISABLE @Bit 0 : Disable constant latency mode */
54379   #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field.                                     */
54380   #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Msk (0x1UL << LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Pos) /*!< Bit mask of
54381                                                                             DISABLE field.*/
54382   #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Min (0x1UL) /*!< Min enumerator value of DISABLE field.                       */
54383   #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Max (0x1UL) /*!< Max enumerator value of DISABLE field.                       */
54384   #define LRCCONF_TASKS_CONSTLAT_DISABLE_DISABLE_Trigger (0x1UL) /*!< Trigger task                                             */
54385 
54386 
54387 
54388 /* ============================================= Struct LRCCONF_TASKS_SYSTEMOFF ============================================== */
54389 /**
54390   * @brief TASKS_SYSTEMOFF [LRCCONF_TASKS_SYSTEMOFF] Peripheral tasks.
54391   */
54392 typedef struct {
54393   __OM  uint32_t  NOTREADY;                          /*!< (@ 0x00000000) Not ready to go to System OFF                         */
54394   __OM  uint32_t  READY;                             /*!< (@ 0x00000004) Ready to go to System OFF                             */
54395 } NRF_LRCCONF_TASKS_SYSTEMOFF_Type;                  /*!< Size = 8 (0x008)                                                     */
54396 
54397 /* LRCCONF_TASKS_SYSTEMOFF_NOTREADY: Not ready to go to System OFF */
54398   #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_ResetValue (0x00000000UL) /*!< Reset value of NOTREADY register.                    */
54399 
54400 /* NOTREADY @Bit 0 : Not ready to go to System OFF */
54401   #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Pos (0UL) /*!< Position of NOTREADY field.                                 */
54402   #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Msk (0x1UL << LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Pos) /*!< Bit mask
54403                                                                             of NOTREADY field.*/
54404   #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Min (0x1UL) /*!< Min enumerator value of NOTREADY field.                   */
54405   #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Max (0x1UL) /*!< Max enumerator value of NOTREADY field.                   */
54406   #define LRCCONF_TASKS_SYSTEMOFF_NOTREADY_NOTREADY_Trigger (0x1UL) /*!< Trigger task                                          */
54407 
54408 
54409 /* LRCCONF_TASKS_SYSTEMOFF_READY: Ready to go to System OFF */
54410   #define LRCCONF_TASKS_SYSTEMOFF_READY_ResetValue (0x00000000UL) /*!< Reset value of READY register.                          */
54411 
54412 /* READY @Bit 0 : Ready to go to System OFF */
54413   #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Pos (0UL) /*!< Position of READY field.                                          */
54414   #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Msk (0x1UL << LRCCONF_TASKS_SYSTEMOFF_READY_READY_Pos) /*!< Bit mask of READY
54415                                                                             field.*/
54416   #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Min (0x1UL) /*!< Min enumerator value of READY field.                            */
54417   #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Max (0x1UL) /*!< Max enumerator value of READY field.                            */
54418   #define LRCCONF_TASKS_SYSTEMOFF_READY_READY_Trigger (0x1UL) /*!< Trigger task                                                */
54419 
54420 
54421 
54422 /* ================================================= Struct LRCCONF_CLKSTAT ================================================== */
54423 /**
54424   * @brief CLKSTAT [LRCCONF_CLKSTAT] (unspecified)
54425   */
54426 typedef struct {
54427   __IOM uint32_t  RUN;                               /*!< (@ 0x00000000) Status indicating that TASKS_REQCLKSRC task has been
54428                                                                          triggered for clock [n].*/
54429   __IOM uint32_t  SRC;                               /*!< (@ 0x00000004) Status indicating clock source for clock [n]          */
54430 } NRF_LRCCONF_CLKSTAT_Type;                          /*!< Size = 8 (0x008)                                                     */
54431   #define LRCCONF_CLKSTAT_MaxCount (8UL)             /*!< Size of CLKSTAT[8] array.                                            */
54432   #define LRCCONF_CLKSTAT_MaxIndex (7UL)             /*!< Max index of CLKSTAT[8] array.                                       */
54433   #define LRCCONF_CLKSTAT_MinIndex (0UL)             /*!< Min index of CLKSTAT[8] array.                                       */
54434 
54435 /* LRCCONF_CLKSTAT_RUN: Status indicating that TASKS_REQCLKSRC task has been triggered for clock [n]. */
54436   #define LRCCONF_CLKSTAT_RUN_ResetValue (0x00000000UL) /*!< Reset value of RUN register.                                      */
54437 
54438 /* STATUS @Bit 0 : Clock start task triggered or not */
54439   #define LRCCONF_CLKSTAT_RUN_STATUS_Pos (0UL)       /*!< Position of STATUS field.                                            */
54440   #define LRCCONF_CLKSTAT_RUN_STATUS_Msk (0x1UL << LRCCONF_CLKSTAT_RUN_STATUS_Pos) /*!< Bit mask of STATUS field.              */
54441   #define LRCCONF_CLKSTAT_RUN_STATUS_Min (0x0UL)     /*!< Min enumerator value of STATUS field.                                */
54442   #define LRCCONF_CLKSTAT_RUN_STATUS_Max (0x1UL)     /*!< Max enumerator value of STATUS field.                                */
54443   #define LRCCONF_CLKSTAT_RUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered                                              */
54444   #define LRCCONF_CLKSTAT_RUN_STATUS_Triggered (0x1UL) /*!< Task triggered                                                     */
54445 
54446 
54447 /* LRCCONF_CLKSTAT_SRC: Status indicating clock source for clock [n] */
54448   #define LRCCONF_CLKSTAT_SRC_ResetValue (0x00000000UL) /*!< Reset value of SRC register.                                      */
54449 
54450 /* SRC @Bit 0 : Clock source status */
54451   #define LRCCONF_CLKSTAT_SRC_SRC_Pos (0UL)          /*!< Position of SRC field.                                               */
54452   #define LRCCONF_CLKSTAT_SRC_SRC_Msk (0x1UL << LRCCONF_CLKSTAT_SRC_SRC_Pos) /*!< Bit mask of SRC field.                       */
54453   #define LRCCONF_CLKSTAT_SRC_SRC_Min (0x0UL)        /*!< Min enumerator value of SRC field.                                   */
54454   #define LRCCONF_CLKSTAT_SRC_SRC_Max (0x1UL)        /*!< Max enumerator value of SRC field.                                   */
54455   #define LRCCONF_CLKSTAT_SRC_SRC_OpenLoop (0x0UL)   /*!< Open loop.                                                           */
54456   #define LRCCONF_CLKSTAT_SRC_SRC_ClosedLoop (0x1UL) /*!< Closed loop.                                                         */
54457 
54458 
54459 
54460 /* ================================================= Struct LRCCONF_CLKCTRL ================================================== */
54461 /**
54462   * @brief CLKCTRL [LRCCONF_CLKCTRL] (unspecified)
54463   */
54464 typedef struct {
54465   __IOM uint32_t  ALWAYSRUN;                         /*!< (@ 0x00000000) Force the clock [n] and tree running always           */
54466   __IOM uint32_t  SRC;                               /*!< (@ 0x00000004) Select the clock source for clock [n]                 */
54467 } NRF_LRCCONF_CLKCTRL_Type;                          /*!< Size = 8 (0x008)                                                     */
54468   #define LRCCONF_CLKCTRL_MaxCount (8UL)             /*!< Size of CLKCTRL[8] array.                                            */
54469   #define LRCCONF_CLKCTRL_MaxIndex (7UL)             /*!< Max index of CLKCTRL[8] array.                                       */
54470   #define LRCCONF_CLKCTRL_MinIndex (0UL)             /*!< Min index of CLKCTRL[8] array.                                       */
54471 
54472 /* LRCCONF_CLKCTRL_ALWAYSRUN: Force the clock [n] and tree running always */
54473   #define LRCCONF_CLKCTRL_ALWAYSRUN_ResetValue (0x00000000UL) /*!< Reset value of ALWAYSRUN register.                          */
54474 
54475 /* FORCE @Bit 0 : Force the clock always running */
54476   #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Pos (0UL)  /*!< Position of FORCE field.                                             */
54477   #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Msk (0x1UL << LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Pos) /*!< Bit mask of FORCE field.     */
54478   #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Min (0x0UL) /*!< Min enumerator value of FORCE field.                                */
54479   #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Max (0x1UL) /*!< Max enumerator value of FORCE field.                                */
54480   #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_Automatic (0x0UL) /*!< Automatic clock control enabled                               */
54481   #define LRCCONF_CLKCTRL_ALWAYSRUN_FORCE_AlwaysRun (0x1UL) /*!< Clock always running                                          */
54482 
54483 
54484 /* LRCCONF_CLKCTRL_SRC: Select the clock source for clock [n] */
54485   #define LRCCONF_CLKCTRL_SRC_ResetValue (0x00000000UL) /*!< Reset value of SRC register.                                      */
54486 
54487 /* SRC @Bit 0 : Clock source */
54488   #define LRCCONF_CLKCTRL_SRC_SRC_Pos (0UL)          /*!< Position of SRC field.                                               */
54489   #define LRCCONF_CLKCTRL_SRC_SRC_Msk (0x1UL << LRCCONF_CLKCTRL_SRC_SRC_Pos) /*!< Bit mask of SRC field.                       */
54490   #define LRCCONF_CLKCTRL_SRC_SRC_Min (0x0UL)        /*!< Min enumerator value of SRC field.                                   */
54491   #define LRCCONF_CLKCTRL_SRC_SRC_Max (0x1UL)        /*!< Max enumerator value of SRC field.                                   */
54492   #define LRCCONF_CLKCTRL_SRC_SRC_OpenLoop (0x0UL)   /*!< Open loop.                                                           */
54493   #define LRCCONF_CLKCTRL_SRC_SRC_ClosedLoop (0x1UL) /*!< Closed loop.                                                         */
54494 
54495 
54496 /* ===================================================== Struct LRCCONF ====================================================== */
54497 /**
54498   * @brief LRCCONF
54499   */
54500   typedef struct {                                   /*!< LRCCONF Structure                                                    */
54501     __OM uint32_t TASKS_REQCLKSRC[8];                /*!< (@ 0x00000000) Request the clock source for clock [n]                */
54502     __OM uint32_t TASKS_STOPREQCLKSRC[8];            /*!< (@ 0x00000020) Stop requesting the clock source for clock [n]        */
54503     __OM NRF_LRCCONF_TASKS_CONSTLAT_Type TASKS_CONSTLAT; /*!< (@ 0x00000040) Peripheral tasks.                                 */
54504     __OM NRF_LRCCONF_TASKS_SYSTEMOFF_Type TASKS_SYSTEMOFF; /*!< (@ 0x00000048) Peripheral tasks.                               */
54505     __IM uint32_t RESERVED[44];
54506     __IOM uint32_t EVENTS_CLKSRCSTARTED[8];          /*!< (@ 0x00000100) Clock source is started for clock [n]                 */
54507     __IM uint32_t RESERVED1[184];
54508     __IOM NRF_LRCCONF_CLKSTAT_Type CLKSTAT[8];       /*!< (@ 0x00000400) (unspecified)                                         */
54509     __IOM NRF_LRCCONF_CLKCTRL_Type CLKCTRL[8];       /*!< (@ 0x00000440) (unspecified)                                         */
54510     __IM uint32_t CONSTLATSTAT;                      /*!< (@ 0x00000480) Status of constant latency                            */
54511     __IM uint32_t RESERVED2[3];
54512     __IOM uint32_t POWERON;                          /*!< (@ 0x00000490) Force power domain ON                                 */
54513     __IOM uint32_t RETAIN;                           /*!< (@ 0x00000494) Retain power domain                                   */
54514     __IM uint32_t RESERVED3[26];
54515     __IOM uint32_t AX2XWAITSTATES[16];               /*!< (@ 0x00000500) AX2X bridge waitstates for the domain [n], where n is
54516                                                                          the Domain ID.*/
54517   } NRF_LRCCONF_Type;                                /*!< Size = 1344 (0x540)                                                  */
54518 
54519 /* LRCCONF_TASKS_REQCLKSRC: Request the clock source for clock [n] */
54520   #define LRCCONF_TASKS_REQCLKSRC_MaxCount (8UL)     /*!< Max size of TASKS_REQCLKSRC[8] array.                                */
54521   #define LRCCONF_TASKS_REQCLKSRC_MaxIndex (7UL)     /*!< Max index of TASKS_REQCLKSRC[8] array.                               */
54522   #define LRCCONF_TASKS_REQCLKSRC_MinIndex (0UL)     /*!< Min index of TASKS_REQCLKSRC[8] array.                               */
54523   #define LRCCONF_TASKS_REQCLKSRC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_REQCLKSRC[8] register.                   */
54524 
54525 /* TASKS_REQCLKSRC @Bit 0 : Request the clock source for clock [n] */
54526   #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Pos (0UL) /*!< Position of TASKS_REQCLKSRC field.                            */
54527   #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Msk (0x1UL << LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Pos) /*!< Bit mask of
54528                                                                             TASKS_REQCLKSRC field.*/
54529   #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Min (0x1UL) /*!< Min enumerator value of TASKS_REQCLKSRC field.              */
54530   #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Max (0x1UL) /*!< Max enumerator value of TASKS_REQCLKSRC field.              */
54531   #define LRCCONF_TASKS_REQCLKSRC_TASKS_REQCLKSRC_Trigger (0x1UL) /*!< Trigger task                                            */
54532 
54533 
54534 /* LRCCONF_TASKS_STOPREQCLKSRC: Stop requesting the clock source for clock [n] */
54535   #define LRCCONF_TASKS_STOPREQCLKSRC_MaxCount (8UL) /*!< Max size of TASKS_STOPREQCLKSRC[8] array.                            */
54536   #define LRCCONF_TASKS_STOPREQCLKSRC_MaxIndex (7UL) /*!< Max index of TASKS_STOPREQCLKSRC[8] array.                           */
54537   #define LRCCONF_TASKS_STOPREQCLKSRC_MinIndex (0UL) /*!< Min index of TASKS_STOPREQCLKSRC[8] array.                           */
54538   #define LRCCONF_TASKS_STOPREQCLKSRC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPREQCLKSRC[8] register.           */
54539 
54540 /* TASKS_STOPREQCLKSRC @Bit 0 : Stop requesting the clock source for clock [n] */
54541   #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Pos (0UL) /*!< Position of TASKS_STOPREQCLKSRC field.                */
54542   #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Msk (0x1UL << LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Pos)
54543                                                                             /*!< Bit mask of TASKS_STOPREQCLKSRC field.*/
54544   #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPREQCLKSRC field.  */
54545   #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPREQCLKSRC field.  */
54546   #define LRCCONF_TASKS_STOPREQCLKSRC_TASKS_STOPREQCLKSRC_Trigger (0x1UL) /*!< Trigger task                                    */
54547 
54548 
54549 /* LRCCONF_EVENTS_CLKSRCSTARTED: Clock source is started for clock [n] */
54550   #define LRCCONF_EVENTS_CLKSRCSTARTED_MaxCount (8UL) /*!< Max size of EVENTS_CLKSRCSTARTED[8] array.                          */
54551   #define LRCCONF_EVENTS_CLKSRCSTARTED_MaxIndex (7UL) /*!< Max index of EVENTS_CLKSRCSTARTED[8] array.                         */
54552   #define LRCCONF_EVENTS_CLKSRCSTARTED_MinIndex (0UL) /*!< Min index of EVENTS_CLKSRCSTARTED[8] array.                         */
54553   #define LRCCONF_EVENTS_CLKSRCSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CLKSRCSTARTED[8] register.         */
54554 
54555 /* EVENTS_CLKSRCSTARTED @Bit 0 : Clock source is started for clock [n] */
54556   #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Pos (0UL) /*!< Position of EVENTS_CLKSRCSTARTED field.             */
54557   #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Msk (0x1UL << LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Pos)
54558                                                                             /*!< Bit mask of EVENTS_CLKSRCSTARTED field.*/
54559   #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_CLKSRCSTARTED
54560                                                                             field.*/
54561   #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_CLKSRCSTARTED
54562                                                                             field.*/
54563   #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_NotGenerated (0x0UL) /*!< Event not generated                      */
54564   #define LRCCONF_EVENTS_CLKSRCSTARTED_EVENTS_CLKSRCSTARTED_Generated (0x1UL) /*!< Event generated                             */
54565 
54566 
54567 /* LRCCONF_CONSTLATSTAT: Status of constant latency */
54568   #define LRCCONF_CONSTLATSTAT_ResetValue (0x00000000UL) /*!< Reset value of CONSTLATSTAT register.                            */
54569 
54570 /* STATUS @Bit 0 : Status */
54571   #define LRCCONF_CONSTLATSTAT_STATUS_Pos (0UL)      /*!< Position of STATUS field.                                            */
54572   #define LRCCONF_CONSTLATSTAT_STATUS_Msk (0x1UL << LRCCONF_CONSTLATSTAT_STATUS_Pos) /*!< Bit mask of STATUS field.            */
54573   #define LRCCONF_CONSTLATSTAT_STATUS_Min (0x0UL)    /*!< Min enumerator value of STATUS field.                                */
54574   #define LRCCONF_CONSTLATSTAT_STATUS_Max (0x1UL)    /*!< Max enumerator value of STATUS field.                                */
54575   #define LRCCONF_CONSTLATSTAT_STATUS_Disable (0x0UL) /*!< Constant latency disabled.                                          */
54576   #define LRCCONF_CONSTLATSTAT_STATUS_Enable (0x1UL) /*!< Constant latency enabled.                                            */
54577 
54578 
54579 /* LRCCONF_POWERON: Force power domain ON */
54580   #define LRCCONF_POWERON_ResetValue (0x00000000UL)  /*!< Reset value of POWERON register.                                     */
54581 
54582 /* MAIN @Bit 0 : Force the main power domain ON */
54583   #define LRCCONF_POWERON_MAIN_Pos (0UL)             /*!< Position of MAIN field.                                              */
54584   #define LRCCONF_POWERON_MAIN_Msk (0x1UL << LRCCONF_POWERON_MAIN_Pos) /*!< Bit mask of MAIN field.                            */
54585   #define LRCCONF_POWERON_MAIN_Min (0x0UL)           /*!< Min enumerator value of MAIN field.                                  */
54586   #define LRCCONF_POWERON_MAIN_Max (0x1UL)           /*!< Max enumerator value of MAIN field.                                  */
54587   #define LRCCONF_POWERON_MAIN_Automatic (0x0UL)     /*!< Automatic power control enabled                                      */
54588   #define LRCCONF_POWERON_MAIN_AlwaysOn (0x1UL)      /*!< Keep the power domain ON even though there is no request             */
54589 
54590 /* ACTIVE0 @Bit 4 : Force the active power domain[0] ON */
54591   #define LRCCONF_POWERON_ACTIVE0_Pos (4UL)          /*!< Position of ACTIVE0 field.                                           */
54592   #define LRCCONF_POWERON_ACTIVE0_Msk (0x1UL << LRCCONF_POWERON_ACTIVE0_Pos) /*!< Bit mask of ACTIVE0 field.                   */
54593   #define LRCCONF_POWERON_ACTIVE0_Min (0x0UL)        /*!< Min enumerator value of ACTIVE0 field.                               */
54594   #define LRCCONF_POWERON_ACTIVE0_Max (0x1UL)        /*!< Max enumerator value of ACTIVE0 field.                               */
54595   #define LRCCONF_POWERON_ACTIVE0_Automatic (0x0UL)  /*!< Automatic power control enabled                                      */
54596   #define LRCCONF_POWERON_ACTIVE0_AlwaysOn (0x1UL)   /*!< Keep the power domain ON even though there is no request             */
54597 
54598 /* ACTIVE1 @Bit 5 : Force the active power domain[1] ON */
54599   #define LRCCONF_POWERON_ACTIVE1_Pos (5UL)          /*!< Position of ACTIVE1 field.                                           */
54600   #define LRCCONF_POWERON_ACTIVE1_Msk (0x1UL << LRCCONF_POWERON_ACTIVE1_Pos) /*!< Bit mask of ACTIVE1 field.                   */
54601   #define LRCCONF_POWERON_ACTIVE1_Min (0x0UL)        /*!< Min enumerator value of ACTIVE1 field.                               */
54602   #define LRCCONF_POWERON_ACTIVE1_Max (0x1UL)        /*!< Max enumerator value of ACTIVE1 field.                               */
54603   #define LRCCONF_POWERON_ACTIVE1_Automatic (0x0UL)  /*!< Automatic power control enabled                                      */
54604   #define LRCCONF_POWERON_ACTIVE1_AlwaysOn (0x1UL)   /*!< Keep the power domain ON even though there is no request             */
54605 
54606 /* ACTIVE2 @Bit 6 : Force the active power domain[2] ON */
54607   #define LRCCONF_POWERON_ACTIVE2_Pos (6UL)          /*!< Position of ACTIVE2 field.                                           */
54608   #define LRCCONF_POWERON_ACTIVE2_Msk (0x1UL << LRCCONF_POWERON_ACTIVE2_Pos) /*!< Bit mask of ACTIVE2 field.                   */
54609   #define LRCCONF_POWERON_ACTIVE2_Min (0x0UL)        /*!< Min enumerator value of ACTIVE2 field.                               */
54610   #define LRCCONF_POWERON_ACTIVE2_Max (0x1UL)        /*!< Max enumerator value of ACTIVE2 field.                               */
54611   #define LRCCONF_POWERON_ACTIVE2_Automatic (0x0UL)  /*!< Automatic power control enabled                                      */
54612   #define LRCCONF_POWERON_ACTIVE2_AlwaysOn (0x1UL)   /*!< Keep the power domain ON even though there is no request             */
54613 
54614 /* ACTIVE3 @Bit 7 : Force the active power domain[3] ON */
54615   #define LRCCONF_POWERON_ACTIVE3_Pos (7UL)          /*!< Position of ACTIVE3 field.                                           */
54616   #define LRCCONF_POWERON_ACTIVE3_Msk (0x1UL << LRCCONF_POWERON_ACTIVE3_Pos) /*!< Bit mask of ACTIVE3 field.                   */
54617   #define LRCCONF_POWERON_ACTIVE3_Min (0x0UL)        /*!< Min enumerator value of ACTIVE3 field.                               */
54618   #define LRCCONF_POWERON_ACTIVE3_Max (0x1UL)        /*!< Max enumerator value of ACTIVE3 field.                               */
54619   #define LRCCONF_POWERON_ACTIVE3_Automatic (0x0UL)  /*!< Automatic power control enabled                                      */
54620   #define LRCCONF_POWERON_ACTIVE3_AlwaysOn (0x1UL)   /*!< Keep the power domain ON even though there is no request             */
54621 
54622 /* ACTIVE4 @Bit 8 : Force the active power domain[4] ON */
54623   #define LRCCONF_POWERON_ACTIVE4_Pos (8UL)          /*!< Position of ACTIVE4 field.                                           */
54624   #define LRCCONF_POWERON_ACTIVE4_Msk (0x1UL << LRCCONF_POWERON_ACTIVE4_Pos) /*!< Bit mask of ACTIVE4 field.                   */
54625   #define LRCCONF_POWERON_ACTIVE4_Min (0x0UL)        /*!< Min enumerator value of ACTIVE4 field.                               */
54626   #define LRCCONF_POWERON_ACTIVE4_Max (0x1UL)        /*!< Max enumerator value of ACTIVE4 field.                               */
54627   #define LRCCONF_POWERON_ACTIVE4_Automatic (0x0UL)  /*!< Automatic power control enabled                                      */
54628   #define LRCCONF_POWERON_ACTIVE4_AlwaysOn (0x1UL)   /*!< Keep the power domain ON even though there is no request             */
54629 
54630 /* ACTIVE5 @Bit 9 : Force the active power domain[5] ON */
54631   #define LRCCONF_POWERON_ACTIVE5_Pos (9UL)          /*!< Position of ACTIVE5 field.                                           */
54632   #define LRCCONF_POWERON_ACTIVE5_Msk (0x1UL << LRCCONF_POWERON_ACTIVE5_Pos) /*!< Bit mask of ACTIVE5 field.                   */
54633   #define LRCCONF_POWERON_ACTIVE5_Min (0x0UL)        /*!< Min enumerator value of ACTIVE5 field.                               */
54634   #define LRCCONF_POWERON_ACTIVE5_Max (0x1UL)        /*!< Max enumerator value of ACTIVE5 field.                               */
54635   #define LRCCONF_POWERON_ACTIVE5_Automatic (0x0UL)  /*!< Automatic power control enabled                                      */
54636   #define LRCCONF_POWERON_ACTIVE5_AlwaysOn (0x1UL)   /*!< Keep the power domain ON even though there is no request             */
54637 
54638 /* ACTIVE6 @Bit 10 : Force the active power domain[6] ON */
54639   #define LRCCONF_POWERON_ACTIVE6_Pos (10UL)         /*!< Position of ACTIVE6 field.                                           */
54640   #define LRCCONF_POWERON_ACTIVE6_Msk (0x1UL << LRCCONF_POWERON_ACTIVE6_Pos) /*!< Bit mask of ACTIVE6 field.                   */
54641   #define LRCCONF_POWERON_ACTIVE6_Min (0x0UL)        /*!< Min enumerator value of ACTIVE6 field.                               */
54642   #define LRCCONF_POWERON_ACTIVE6_Max (0x1UL)        /*!< Max enumerator value of ACTIVE6 field.                               */
54643   #define LRCCONF_POWERON_ACTIVE6_Automatic (0x0UL)  /*!< Automatic power control enabled                                      */
54644   #define LRCCONF_POWERON_ACTIVE6_AlwaysOn (0x1UL)   /*!< Keep the power domain ON even though there is no request             */
54645 
54646 /* ACTIVE7 @Bit 11 : Force the active power domain[7] ON */
54647   #define LRCCONF_POWERON_ACTIVE7_Pos (11UL)         /*!< Position of ACTIVE7 field.                                           */
54648   #define LRCCONF_POWERON_ACTIVE7_Msk (0x1UL << LRCCONF_POWERON_ACTIVE7_Pos) /*!< Bit mask of ACTIVE7 field.                   */
54649   #define LRCCONF_POWERON_ACTIVE7_Min (0x0UL)        /*!< Min enumerator value of ACTIVE7 field.                               */
54650   #define LRCCONF_POWERON_ACTIVE7_Max (0x1UL)        /*!< Max enumerator value of ACTIVE7 field.                               */
54651   #define LRCCONF_POWERON_ACTIVE7_Automatic (0x0UL)  /*!< Automatic power control enabled                                      */
54652   #define LRCCONF_POWERON_ACTIVE7_AlwaysOn (0x1UL)   /*!< Keep the power domain ON even though there is no request             */
54653 
54654 
54655 /* LRCCONF_RETAIN: Retain power domain */
54656   #define LRCCONF_RETAIN_ResetValue (0x00000FF1UL)   /*!< Reset value of RETAIN register.                                      */
54657 
54658 /* MAIN @Bit 0 : Retain the main power domain */
54659   #define LRCCONF_RETAIN_MAIN_Pos (0UL)              /*!< Position of MAIN field.                                              */
54660   #define LRCCONF_RETAIN_MAIN_Msk (0x1UL << LRCCONF_RETAIN_MAIN_Pos) /*!< Bit mask of MAIN field.                              */
54661   #define LRCCONF_RETAIN_MAIN_Min (0x0UL)            /*!< Min enumerator value of MAIN field.                                  */
54662   #define LRCCONF_RETAIN_MAIN_Max (0x1UL)            /*!< Max enumerator value of MAIN field.                                  */
54663   #define LRCCONF_RETAIN_MAIN_Disable (0x0UL)        /*!< Retain disabled                                                      */
54664   #define LRCCONF_RETAIN_MAIN_Enable (0x1UL)         /*!< Retain enabled                                                       */
54665 
54666 /* ACTIVE0 @Bit 4 : Retain the active power domain[0] */
54667   #define LRCCONF_RETAIN_ACTIVE0_Pos (4UL)           /*!< Position of ACTIVE0 field.                                           */
54668   #define LRCCONF_RETAIN_ACTIVE0_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE0_Pos) /*!< Bit mask of ACTIVE0 field.                     */
54669   #define LRCCONF_RETAIN_ACTIVE0_Min (0x0UL)         /*!< Min enumerator value of ACTIVE0 field.                               */
54670   #define LRCCONF_RETAIN_ACTIVE0_Max (0x1UL)         /*!< Max enumerator value of ACTIVE0 field.                               */
54671   #define LRCCONF_RETAIN_ACTIVE0_Disable (0x0UL)     /*!< Retain disabled                                                      */
54672   #define LRCCONF_RETAIN_ACTIVE0_Enable (0x1UL)      /*!< Retain enabled                                                       */
54673 
54674 /* ACTIVE1 @Bit 5 : Retain the active power domain[1] */
54675   #define LRCCONF_RETAIN_ACTIVE1_Pos (5UL)           /*!< Position of ACTIVE1 field.                                           */
54676   #define LRCCONF_RETAIN_ACTIVE1_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE1_Pos) /*!< Bit mask of ACTIVE1 field.                     */
54677   #define LRCCONF_RETAIN_ACTIVE1_Min (0x0UL)         /*!< Min enumerator value of ACTIVE1 field.                               */
54678   #define LRCCONF_RETAIN_ACTIVE1_Max (0x1UL)         /*!< Max enumerator value of ACTIVE1 field.                               */
54679   #define LRCCONF_RETAIN_ACTIVE1_Disable (0x0UL)     /*!< Retain disabled                                                      */
54680   #define LRCCONF_RETAIN_ACTIVE1_Enable (0x1UL)      /*!< Retain enabled                                                       */
54681 
54682 /* ACTIVE2 @Bit 6 : Retain the active power domain[2] */
54683   #define LRCCONF_RETAIN_ACTIVE2_Pos (6UL)           /*!< Position of ACTIVE2 field.                                           */
54684   #define LRCCONF_RETAIN_ACTIVE2_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE2_Pos) /*!< Bit mask of ACTIVE2 field.                     */
54685   #define LRCCONF_RETAIN_ACTIVE2_Min (0x0UL)         /*!< Min enumerator value of ACTIVE2 field.                               */
54686   #define LRCCONF_RETAIN_ACTIVE2_Max (0x1UL)         /*!< Max enumerator value of ACTIVE2 field.                               */
54687   #define LRCCONF_RETAIN_ACTIVE2_Disable (0x0UL)     /*!< Retain disabled                                                      */
54688   #define LRCCONF_RETAIN_ACTIVE2_Enable (0x1UL)      /*!< Retain enabled                                                       */
54689 
54690 /* ACTIVE3 @Bit 7 : Retain the active power domain[3] */
54691   #define LRCCONF_RETAIN_ACTIVE3_Pos (7UL)           /*!< Position of ACTIVE3 field.                                           */
54692   #define LRCCONF_RETAIN_ACTIVE3_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE3_Pos) /*!< Bit mask of ACTIVE3 field.                     */
54693   #define LRCCONF_RETAIN_ACTIVE3_Min (0x0UL)         /*!< Min enumerator value of ACTIVE3 field.                               */
54694   #define LRCCONF_RETAIN_ACTIVE3_Max (0x1UL)         /*!< Max enumerator value of ACTIVE3 field.                               */
54695   #define LRCCONF_RETAIN_ACTIVE3_Disable (0x0UL)     /*!< Retain disabled                                                      */
54696   #define LRCCONF_RETAIN_ACTIVE3_Enable (0x1UL)      /*!< Retain enabled                                                       */
54697 
54698 /* ACTIVE4 @Bit 8 : Retain the active power domain[4] */
54699   #define LRCCONF_RETAIN_ACTIVE4_Pos (8UL)           /*!< Position of ACTIVE4 field.                                           */
54700   #define LRCCONF_RETAIN_ACTIVE4_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE4_Pos) /*!< Bit mask of ACTIVE4 field.                     */
54701   #define LRCCONF_RETAIN_ACTIVE4_Min (0x0UL)         /*!< Min enumerator value of ACTIVE4 field.                               */
54702   #define LRCCONF_RETAIN_ACTIVE4_Max (0x1UL)         /*!< Max enumerator value of ACTIVE4 field.                               */
54703   #define LRCCONF_RETAIN_ACTIVE4_Disable (0x0UL)     /*!< Retain disabled                                                      */
54704   #define LRCCONF_RETAIN_ACTIVE4_Enable (0x1UL)      /*!< Retain enabled                                                       */
54705 
54706 /* ACTIVE5 @Bit 9 : Retain the active power domain[5] */
54707   #define LRCCONF_RETAIN_ACTIVE5_Pos (9UL)           /*!< Position of ACTIVE5 field.                                           */
54708   #define LRCCONF_RETAIN_ACTIVE5_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE5_Pos) /*!< Bit mask of ACTIVE5 field.                     */
54709   #define LRCCONF_RETAIN_ACTIVE5_Min (0x0UL)         /*!< Min enumerator value of ACTIVE5 field.                               */
54710   #define LRCCONF_RETAIN_ACTIVE5_Max (0x1UL)         /*!< Max enumerator value of ACTIVE5 field.                               */
54711   #define LRCCONF_RETAIN_ACTIVE5_Disable (0x0UL)     /*!< Retain disabled                                                      */
54712   #define LRCCONF_RETAIN_ACTIVE5_Enable (0x1UL)      /*!< Retain enabled                                                       */
54713 
54714 /* ACTIVE6 @Bit 10 : Retain the active power domain[6] */
54715   #define LRCCONF_RETAIN_ACTIVE6_Pos (10UL)          /*!< Position of ACTIVE6 field.                                           */
54716   #define LRCCONF_RETAIN_ACTIVE6_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE6_Pos) /*!< Bit mask of ACTIVE6 field.                     */
54717   #define LRCCONF_RETAIN_ACTIVE6_Min (0x0UL)         /*!< Min enumerator value of ACTIVE6 field.                               */
54718   #define LRCCONF_RETAIN_ACTIVE6_Max (0x1UL)         /*!< Max enumerator value of ACTIVE6 field.                               */
54719   #define LRCCONF_RETAIN_ACTIVE6_Disable (0x0UL)     /*!< Retain disabled                                                      */
54720   #define LRCCONF_RETAIN_ACTIVE6_Enable (0x1UL)      /*!< Retain enabled                                                       */
54721 
54722 /* ACTIVE7 @Bit 11 : Retain the active power domain[7] */
54723   #define LRCCONF_RETAIN_ACTIVE7_Pos (11UL)          /*!< Position of ACTIVE7 field.                                           */
54724   #define LRCCONF_RETAIN_ACTIVE7_Msk (0x1UL << LRCCONF_RETAIN_ACTIVE7_Pos) /*!< Bit mask of ACTIVE7 field.                     */
54725   #define LRCCONF_RETAIN_ACTIVE7_Min (0x0UL)         /*!< Min enumerator value of ACTIVE7 field.                               */
54726   #define LRCCONF_RETAIN_ACTIVE7_Max (0x1UL)         /*!< Max enumerator value of ACTIVE7 field.                               */
54727   #define LRCCONF_RETAIN_ACTIVE7_Disable (0x0UL)     /*!< Retain disabled                                                      */
54728   #define LRCCONF_RETAIN_ACTIVE7_Enable (0x1UL)      /*!< Retain enabled                                                       */
54729 
54730 
54731 /* LRCCONF_AX2XWAITSTATES: AX2X bridge waitstates for the domain [n], where n is the Domain ID. */
54732   #define LRCCONF_AX2XWAITSTATES_MaxCount (16UL)     /*!< Max size of AX2XWAITSTATES[16] array.                                */
54733   #define LRCCONF_AX2XWAITSTATES_MaxIndex (15UL)     /*!< Max index of AX2XWAITSTATES[16] array.                               */
54734   #define LRCCONF_AX2XWAITSTATES_MinIndex (0UL)      /*!< Min index of AX2XWAITSTATES[16] array.                               */
54735   #define LRCCONF_AX2XWAITSTATES_ResetValue (0x00000007UL) /*!< Reset value of AX2XWAITSTATES[16] register.                    */
54736 
54737 /* WAITSTATES @Bits 0..2 : Number of waitstates */
54738   #define LRCCONF_AX2XWAITSTATES_WAITSTATES_Pos (0UL) /*!< Position of WAITSTATES field.                                       */
54739   #define LRCCONF_AX2XWAITSTATES_WAITSTATES_Msk (0x7UL << LRCCONF_AX2XWAITSTATES_WAITSTATES_Pos) /*!< Bit mask of WAITSTATES
54740                                                                             field.*/
54741 
54742 
54743 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
54744 
54745 /* =========================================================================================================================== */
54746 /* ================                                           MCAN                                           ================ */
54747 /* =========================================================================================================================== */
54748 
54749 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
54750 /* ======================================================= Struct MCAN ======================================================= */
54751 /**
54752   * @brief MCAN
54753   */
54754   typedef struct {                                   /*!< MCAN Structure                                                       */
54755     __IM uint32_t RESERVED;
54756     __IM uint32_t ENDN;                              /*!< (@ 0x00000004) Endian Register                                       */
54757     __IM uint32_t RESERVED1;
54758     __IOM uint32_t DBTP;                             /*!< (@ 0x0000000C) Data Bit Timing and Prescaler Register                */
54759     __IOM uint32_t TEST;                             /*!< (@ 0x00000010) Test Register                                         */
54760     __IOM uint32_t RWD;                              /*!< (@ 0x00000014) RAM Watchdog                                          */
54761     __IOM uint32_t CCCR;                             /*!< (@ 0x00000018) CC Control Register                                   */
54762     __IOM uint32_t NBTP;                             /*!< (@ 0x0000001C) Nominal Bit Timing and Prescaler Register             */
54763     __IOM uint32_t TSCC;                             /*!< (@ 0x00000020) Timestamp Counter Configuration                       */
54764     __IOM uint32_t TSCV;                             /*!< (@ 0x00000024) Timestamp Counter Value                               */
54765     __IOM uint32_t TOCC;                             /*!< (@ 0x00000028) Timeout Counter Configuration                         */
54766     __IOM uint32_t TOCV;                             /*!< (@ 0x0000002C) Timeout Counter Value                                 */
54767     __IM uint32_t RESERVED2[4];
54768     __IOM uint32_t ECR;                              /*!< (@ 0x00000040) Error Counter Register                                */
54769     __IOM uint32_t PSR;                              /*!< (@ 0x00000044) Protocol Status Register                              */
54770     __IOM uint32_t TDCR;                             /*!< (@ 0x00000048) Transmitter Delay Compensation Register               */
54771     __IM uint32_t RESERVED3;
54772     __IOM uint32_t IR;                               /*!< (@ 0x00000050) Interrupt Register                                    */
54773     __IOM uint32_t IE;                               /*!< (@ 0x00000054) Interrupt Enable                                      */
54774     __IOM uint32_t ILS;                              /*!< (@ 0x00000058) Interrupt Line Select                                 */
54775     __IOM uint32_t ILE;                              /*!< (@ 0x0000005C) Interrupt Line Enable                                 */
54776     __IM uint32_t RESERVED4[8];
54777     __IOM uint32_t GFC;                              /*!< (@ 0x00000080) Global Filter Configuration                           */
54778     __IOM uint32_t SIDFC;                            /*!< (@ 0x00000084) Standard ID Filter Configuration                      */
54779     __IOM uint32_t XIDFC;                            /*!< (@ 0x00000088) Extended ID Filter Configuration                      */
54780     __IM uint32_t RESERVED5;
54781     __IOM uint32_t XIDAM;                            /*!< (@ 0x00000090) Extended ID AND Mask                                  */
54782     __IM uint32_t HPMS;                              /*!< (@ 0x00000094) High Priority Message Status                          */
54783     __IOM uint32_t NDAT1;                            /*!< (@ 0x00000098) New Data 1                                            */
54784     __IOM uint32_t NDAT2;                            /*!< (@ 0x0000009C) New Data 2                                            */
54785     __IOM uint32_t RXF0C;                            /*!< (@ 0x000000A0) Rx FIFO 0 Configuration                               */
54786     __IM uint32_t RXF0S;                             /*!< (@ 0x000000A4) Rx FIFO 0 Status                                      */
54787     __IOM uint32_t RXF0A;                            /*!< (@ 0x000000A8) Rx FIFO 0 Acknowledge                                 */
54788     __IOM uint32_t RXBC;                             /*!< (@ 0x000000AC) Rx Buffer Configuration                               */
54789     __IOM uint32_t RXF1C;                            /*!< (@ 0x000000B0) Rx FIFO 1 Configuration                               */
54790     __IM uint32_t RXF1S;                             /*!< (@ 0x000000B4) Rx FIFO 1 Status                                      */
54791     __IOM uint32_t RXF1A;                            /*!< (@ 0x000000B8) Rx FIFO 1 Acknowledge                                 */
54792     __IOM uint32_t RXESC;                            /*!< (@ 0x000000BC) Rx Buffer / FIFO Element Size Configuration           */
54793     __IOM uint32_t TXBC;                             /*!< (@ 0x000000C0) Tx Buffer Configuration                               */
54794     __IM uint32_t TXFQS;                             /*!< (@ 0x000000C4) Tx FIFO/Queue Status                                  */
54795     __IOM uint32_t TXESC;                            /*!< (@ 0x000000C8) Tx Buffer Element Size Configuration                  */
54796     __IM uint32_t TXBRP;                             /*!< (@ 0x000000CC) Tx Buffer Request Pending                             */
54797     __IOM uint32_t TXBAR;                            /*!< (@ 0x000000D0) Tx Buffer Add Request                                 */
54798     __IOM uint32_t TXBCR;                            /*!< (@ 0x000000D4) Tx Buffer Cancellation Request                        */
54799     __IM uint32_t TXBTO;                             /*!< (@ 0x000000D8) Tx Buffer Transmission Occurred                       */
54800     __IM uint32_t TXBCF;                             /*!< (@ 0x000000DC) Tx Buffer Cancellation Finished                       */
54801     __IOM uint32_t TXBTIE;                           /*!< (@ 0x000000E0) Tx Buffer Transmission Interrupt Enable               */
54802     __IOM uint32_t TXBCIE;                           /*!< (@ 0x000000E4) Tx Buffer Cancellation Finished Interrupt Enable      */
54803     __IM uint32_t RESERVED6[2];
54804     __IOM uint32_t TXEFC;                            /*!< (@ 0x000000F0) Tx Event FIFO Configuration                           */
54805     __IM uint32_t TXEFS;                             /*!< (@ 0x000000F4) Tx Event FIFO Status                                  */
54806     __IOM uint32_t TXEFA;                            /*!< (@ 0x000000F8) Tx Event FIFO Acknowledge                             */
54807   } NRF_MCAN_Type;                                   /*!< Size = 252 (0x0FC)                                                   */
54808 
54809 /* MCAN_ENDN: Endian Register */
54810   #define MCAN_ENDN_ResetValue (0x00000000UL)        /*!< Reset value of ENDN register.                                        */
54811 
54812 /* ETV @Bits 0..31 : Endianness Test Value */
54813   #define MCAN_ENDN_ETV_Pos (0UL)                    /*!< Position of ETV field.                                               */
54814   #define MCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << MCAN_ENDN_ETV_Pos) /*!< Bit mask of ETV field.                                    */
54815 
54816 
54817 /* MCAN_DBTP: Data Bit Timing and Prescaler Register */
54818   #define MCAN_DBTP_ResetValue (0x00000000UL)        /*!< Reset value of DBTP register.                                        */
54819 
54820 /* DSJW @Bits 0..3 : Data (Re)Synchronization Jump Width */
54821   #define MCAN_DBTP_DSJW_Pos (0UL)                   /*!< Position of DSJW field.                                              */
54822   #define MCAN_DBTP_DSJW_Msk (0xFUL << MCAN_DBTP_DSJW_Pos) /*!< Bit mask of DSJW field.                                        */
54823 
54824 /* DTSEG2 @Bits 4..7 : Data time segment after sample point */
54825   #define MCAN_DBTP_DTSEG2_Pos (4UL)                 /*!< Position of DTSEG2 field.                                            */
54826   #define MCAN_DBTP_DTSEG2_Msk (0xFUL << MCAN_DBTP_DTSEG2_Pos) /*!< Bit mask of DTSEG2 field.                                  */
54827 
54828 /* DTSEG1 @Bits 8..12 : Data time segment before sample point */
54829   #define MCAN_DBTP_DTSEG1_Pos (8UL)                 /*!< Position of DTSEG1 field.                                            */
54830   #define MCAN_DBTP_DTSEG1_Msk (0x1FUL << MCAN_DBTP_DTSEG1_Pos) /*!< Bit mask of DTSEG1 field.                                 */
54831 
54832 /* DBRP @Bits 16..20 : Data Bit Rate Prescaler */
54833   #define MCAN_DBTP_DBRP_Pos (16UL)                  /*!< Position of DBRP field.                                              */
54834   #define MCAN_DBTP_DBRP_Msk (0x1FUL << MCAN_DBTP_DBRP_Pos) /*!< Bit mask of DBRP field.                                       */
54835 
54836 /* TDC @Bit 23 : Transmitter Delay Compensation */
54837   #define MCAN_DBTP_TDC_Pos (23UL)                   /*!< Position of TDC field.                                               */
54838   #define MCAN_DBTP_TDC_Msk (0x1UL << MCAN_DBTP_TDC_Pos) /*!< Bit mask of TDC field.                                           */
54839   #define MCAN_DBTP_TDC_Min (0x0UL)                  /*!< Min enumerator value of TDC field.                                   */
54840   #define MCAN_DBTP_TDC_Max (0x1UL)                  /*!< Max enumerator value of TDC field.                                   */
54841   #define MCAN_DBTP_TDC_Disabled (0x0UL)             /*!< (unspecified)                                                        */
54842   #define MCAN_DBTP_TDC_Enabled (0x1UL)              /*!< (unspecified)                                                        */
54843 
54844 
54845 /* MCAN_TEST: Test Register */
54846   #define MCAN_TEST_ResetValue (0x00000000UL)        /*!< Reset value of TEST register.                                        */
54847 
54848 /* LBCK @Bit 4 : Loop Back Mode */
54849   #define MCAN_TEST_LBCK_Pos (4UL)                   /*!< Position of LBCK field.                                              */
54850   #define MCAN_TEST_LBCK_Msk (0x1UL << MCAN_TEST_LBCK_Pos) /*!< Bit mask of LBCK field.                                        */
54851   #define MCAN_TEST_LBCK_Min (0x0UL)                 /*!< Min enumerator value of LBCK field.                                  */
54852   #define MCAN_TEST_LBCK_Max (0x1UL)                 /*!< Max enumerator value of LBCK field.                                  */
54853   #define MCAN_TEST_LBCK_Disabled (0x0UL)            /*!< Loop Back Mode is disabled                                           */
54854   #define MCAN_TEST_LBCK_Enabled (0x1UL)             /*!< Loop Back Mode is enabled                                            */
54855 
54856 /* TX @Bits 5..6 : Control of Transmit Pin */
54857   #define MCAN_TEST_TX_Pos (5UL)                     /*!< Position of TX field.                                                */
54858   #define MCAN_TEST_TX_Msk (0x3UL << MCAN_TEST_TX_Pos) /*!< Bit mask of TX field.                                              */
54859   #define MCAN_TEST_TX_Min (0x0UL)                   /*!< Min enumerator value of TX field.                                    */
54860   #define MCAN_TEST_TX_Max (0x3UL)                   /*!< Max enumerator value of TX field.                                    */
54861   #define MCAN_TEST_TX_CanCore (0x0UL)               /*!< controlled by the CAN Core, updated at the end of the CAN bit time   */
54862   #define MCAN_TEST_TX_Monitored (0x1UL)             /*!< Sample Point can be monitored at pin m_can_tx                        */
54863   #define MCAN_TEST_TX_Dominant (0x2UL)              /*!< Dominant (0) level at pin m_can_tx                                   */
54864   #define MCAN_TEST_TX_Recessive (0x3UL)             /*!< Recessive (1) at pin m_can_tx                                        */
54865 
54866 /* RX @Bit 7 : Receive Pin */
54867   #define MCAN_TEST_RX_Pos (7UL)                     /*!< Position of RX field.                                                */
54868   #define MCAN_TEST_RX_Msk (0x1UL << MCAN_TEST_RX_Pos) /*!< Bit mask of RX field.                                              */
54869   #define MCAN_TEST_RX_Min (0x0UL)                   /*!< Min enumerator value of RX field.                                    */
54870   #define MCAN_TEST_RX_Max (0x1UL)                   /*!< Max enumerator value of RX field.                                    */
54871   #define MCAN_TEST_RX_Dominant (0x0UL)              /*!< The CAN bus is dominant (m_can_rx = 0)                               */
54872   #define MCAN_TEST_RX_Recessive (0x1UL)             /*!< The CAN bus is recessive (m_can_rx = '1')                            */
54873 
54874 /* TXBNP @Bits 8..12 : Tx Buffer Number Prepared */
54875   #define MCAN_TEST_TXBNP_Pos (8UL)                  /*!< Position of TXBNP field.                                             */
54876   #define MCAN_TEST_TXBNP_Msk (0x1FUL << MCAN_TEST_TXBNP_Pos) /*!< Bit mask of TXBNP field.                                    */
54877 
54878 /* PVAL @Bit 13 : Prepared Valid */
54879   #define MCAN_TEST_PVAL_Pos (13UL)                  /*!< Position of PVAL field.                                              */
54880   #define MCAN_TEST_PVAL_Msk (0x1UL << MCAN_TEST_PVAL_Pos) /*!< Bit mask of PVAL field.                                        */
54881   #define MCAN_TEST_PVAL_Min (0x0UL)                 /*!< Min enumerator value of PVAL field.                                  */
54882   #define MCAN_TEST_PVAL_Max (0x1UL)                 /*!< Max enumerator value of PVAL field.                                  */
54883   #define MCAN_TEST_PVAL_NotValid (0x0UL)            /*!< Value of TXBNP not valid                                             */
54884   #define MCAN_TEST_PVAL_Valid (0x1UL)               /*!< Value of TXBNP valid                                                 */
54885 
54886 /* TXBNS @Bits 16..20 : Tx Buffer Number Started */
54887   #define MCAN_TEST_TXBNS_Pos (16UL)                 /*!< Position of TXBNS field.                                             */
54888   #define MCAN_TEST_TXBNS_Msk (0x1FUL << MCAN_TEST_TXBNS_Pos) /*!< Bit mask of TXBNS field.                                    */
54889 
54890 /* SVAL @Bit 21 : Started Valid */
54891   #define MCAN_TEST_SVAL_Pos (21UL)                  /*!< Position of SVAL field.                                              */
54892   #define MCAN_TEST_SVAL_Msk (0x1UL << MCAN_TEST_SVAL_Pos) /*!< Bit mask of SVAL field.                                        */
54893   #define MCAN_TEST_SVAL_Min (0x0UL)                 /*!< Min enumerator value of SVAL field.                                  */
54894   #define MCAN_TEST_SVAL_Max (0x1UL)                 /*!< Max enumerator value of SVAL field.                                  */
54895   #define MCAN_TEST_SVAL_NotValid (0x0UL)            /*!< Value of TXBNP not valid                                             */
54896   #define MCAN_TEST_SVAL_Valid (0x1UL)               /*!< Value of TXBNP valid                                                 */
54897 
54898 
54899 /* MCAN_RWD: RAM Watchdog */
54900   #define MCAN_RWD_ResetValue (0x00000000UL)         /*!< Reset value of RWD register.                                         */
54901 
54902 /* WDC @Bits 0..7 : Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is disabled. */
54903   #define MCAN_RWD_WDC_Pos (0UL)                     /*!< Position of WDC field.                                               */
54904   #define MCAN_RWD_WDC_Msk (0xFFUL << MCAN_RWD_WDC_Pos) /*!< Bit mask of WDC field.                                            */
54905 
54906 /* WDV @Bits 8..15 : Actual Message RAM Watchdog Counter Value. */
54907   #define MCAN_RWD_WDV_Pos (8UL)                     /*!< Position of WDV field.                                               */
54908   #define MCAN_RWD_WDV_Msk (0xFFUL << MCAN_RWD_WDV_Pos) /*!< Bit mask of WDV field.                                            */
54909 
54910 
54911 /* MCAN_CCCR: CC Control Register */
54912   #define MCAN_CCCR_ResetValue (0x00000000UL)        /*!< Reset value of CCCR register.                                        */
54913 
54914 /* INIT @Bit 0 : Initialization */
54915   #define MCAN_CCCR_INIT_Pos (0UL)                   /*!< Position of INIT field.                                              */
54916   #define MCAN_CCCR_INIT_Msk (0x1UL << MCAN_CCCR_INIT_Pos) /*!< Bit mask of INIT field.                                        */
54917   #define MCAN_CCCR_INIT_Min (0x0UL)                 /*!< Min enumerator value of INIT field.                                  */
54918   #define MCAN_CCCR_INIT_Max (0x1UL)                 /*!< Max enumerator value of INIT field.                                  */
54919   #define MCAN_CCCR_INIT_Normal (0x0UL)              /*!< Normal Operation                                                     */
54920   #define MCAN_CCCR_INIT_Initialization (0x1UL)      /*!< Initialization is started                                            */
54921 
54922 /* CCE @Bit 1 : Configuration Change Enable */
54923   #define MCAN_CCCR_CCE_Pos (1UL)                    /*!< Position of CCE field.                                               */
54924   #define MCAN_CCCR_CCE_Msk (0x1UL << MCAN_CCCR_CCE_Pos) /*!< Bit mask of CCE field.                                           */
54925   #define MCAN_CCCR_CCE_Min (0x0UL)                  /*!< Min enumerator value of CCE field.                                   */
54926   #define MCAN_CCCR_CCE_Max (0x1UL)                  /*!< Max enumerator value of CCE field.                                   */
54927   #define MCAN_CCCR_CCE_Disabled (0x0UL)             /*!< The CPU has no write access to the protected configuration registers */
54928   #define MCAN_CCCR_CCE_Enabled (0x1UL)              /*!< The CPU has write access to the protected configuration registers
54929                                                           (while CCCR.INIT = '1')*/
54930 
54931 /* ASM @Bit 2 : Restricted Operation Mode */
54932   #define MCAN_CCCR_ASM_Pos (2UL)                    /*!< Position of ASM field.                                               */
54933   #define MCAN_CCCR_ASM_Msk (0x1UL << MCAN_CCCR_ASM_Pos) /*!< Bit mask of ASM field.                                           */
54934   #define MCAN_CCCR_ASM_Min (0x0UL)                  /*!< Min enumerator value of ASM field.                                   */
54935   #define MCAN_CCCR_ASM_Max (0x1UL)                  /*!< Max enumerator value of ASM field.                                   */
54936   #define MCAN_CCCR_ASM_Disabled (0x0UL)             /*!< Normal CAN operation                                                 */
54937   #define MCAN_CCCR_ASM_Enabled (0x1UL)              /*!< Restricted Operation Mode active                                     */
54938 
54939 /* CSA @Bit 3 : Clock Stop Acknowledge */
54940   #define MCAN_CCCR_CSA_Pos (3UL)                    /*!< Position of CSA field.                                               */
54941   #define MCAN_CCCR_CSA_Msk (0x1UL << MCAN_CCCR_CSA_Pos) /*!< Bit mask of CSA field.                                           */
54942   #define MCAN_CCCR_CSA_Min (0x0UL)                  /*!< Min enumerator value of CSA field.                                   */
54943   #define MCAN_CCCR_CSA_Max (0x1UL)                  /*!< Max enumerator value of CSA field.                                   */
54944   #define MCAN_CCCR_CSA_Disabled (0x0UL)             /*!< No clock stop acknowledged                                           */
54945   #define MCAN_CCCR_CSA_Enabled (0x1UL)              /*!< MCAN may be set in power down by stopping m_can_hclk and m_can_cclk  */
54946 
54947 /* CSR @Bit 4 : Clock Stop Request */
54948   #define MCAN_CCCR_CSR_Pos (4UL)                    /*!< Position of CSR field.                                               */
54949   #define MCAN_CCCR_CSR_Msk (0x1UL << MCAN_CCCR_CSR_Pos) /*!< Bit mask of CSR field.                                           */
54950   #define MCAN_CCCR_CSR_Min (0x0UL)                  /*!< Min enumerator value of CSR field.                                   */
54951   #define MCAN_CCCR_CSR_Max (0x1UL)                  /*!< Max enumerator value of CSR field.                                   */
54952   #define MCAN_CCCR_CSR_Disabled (0x0UL)             /*!< No clock stop is requested                                           */
54953   #define MCAN_CCCR_CSR_Enabled (0x1UL)              /*!< Clock stop requested.                                                */
54954 
54955 /* MON @Bit 5 : Bus Monitoring Mode */
54956   #define MCAN_CCCR_MON_Pos (5UL)                    /*!< Position of MON field.                                               */
54957   #define MCAN_CCCR_MON_Msk (0x1UL << MCAN_CCCR_MON_Pos) /*!< Bit mask of MON field.                                           */
54958   #define MCAN_CCCR_MON_Min (0x0UL)                  /*!< Min enumerator value of MON field.                                   */
54959   #define MCAN_CCCR_MON_Max (0x1UL)                  /*!< Max enumerator value of MON field.                                   */
54960   #define MCAN_CCCR_MON_Disabled (0x0UL)             /*!< Bus Monitoring Mode is disabled                                      */
54961   #define MCAN_CCCR_MON_Enabled (0x1UL)              /*!< Bus Monitoring Mode is enabled                                       */
54962 
54963 /* DAR @Bit 6 : Disable Automatic Retransmission */
54964   #define MCAN_CCCR_DAR_Pos (6UL)                    /*!< Position of DAR field.                                               */
54965   #define MCAN_CCCR_DAR_Msk (0x1UL << MCAN_CCCR_DAR_Pos) /*!< Bit mask of DAR field.                                           */
54966   #define MCAN_CCCR_DAR_Min (0x0UL)                  /*!< Min enumerator value of DAR field.                                   */
54967   #define MCAN_CCCR_DAR_Max (0x1UL)                  /*!< Max enumerator value of DAR field.                                   */
54968   #define MCAN_CCCR_DAR_Enabled (0x0UL)              /*!< Automatic retransmission of messages not transmitted successfully
54969                                                           enabled*/
54970   #define MCAN_CCCR_DAR_Disabled (0x1UL)             /*!< Automatic retransmission disabled                                    */
54971 
54972 /* TEST @Bit 7 : Test Mode Enable */
54973   #define MCAN_CCCR_TEST_Pos (7UL)                   /*!< Position of TEST field.                                              */
54974   #define MCAN_CCCR_TEST_Msk (0x1UL << MCAN_CCCR_TEST_Pos) /*!< Bit mask of TEST field.                                        */
54975   #define MCAN_CCCR_TEST_Min (0x0UL)                 /*!< Min enumerator value of TEST field.                                  */
54976   #define MCAN_CCCR_TEST_Max (0x1UL)                 /*!< Max enumerator value of TEST field.                                  */
54977   #define MCAN_CCCR_TEST_Disabled (0x0UL)            /*!< Normal operation, register TEST holds reset values                   */
54978   #define MCAN_CCCR_TEST_Enabled (0x1UL)             /*!< Test Mode, write access to register TEST enabled                     */
54979 
54980 /* FDOE @Bit 8 : FD Operation Enable */
54981   #define MCAN_CCCR_FDOE_Pos (8UL)                   /*!< Position of FDOE field.                                              */
54982   #define MCAN_CCCR_FDOE_Msk (0x1UL << MCAN_CCCR_FDOE_Pos) /*!< Bit mask of FDOE field.                                        */
54983   #define MCAN_CCCR_FDOE_Min (0x0UL)                 /*!< Min enumerator value of FDOE field.                                  */
54984   #define MCAN_CCCR_FDOE_Max (0x1UL)                 /*!< Max enumerator value of FDOE field.                                  */
54985   #define MCAN_CCCR_FDOE_Disabled (0x0UL)            /*!< FD operation disabled                                                */
54986   #define MCAN_CCCR_FDOE_Enabled (0x1UL)             /*!< FD operation enabled                                                 */
54987 
54988 /* BRSE @Bit 9 : Bit Rate Switch Enable */
54989   #define MCAN_CCCR_BRSE_Pos (9UL)                   /*!< Position of BRSE field.                                              */
54990   #define MCAN_CCCR_BRSE_Msk (0x1UL << MCAN_CCCR_BRSE_Pos) /*!< Bit mask of BRSE field.                                        */
54991   #define MCAN_CCCR_BRSE_Min (0x0UL)                 /*!< Min enumerator value of BRSE field.                                  */
54992   #define MCAN_CCCR_BRSE_Max (0x1UL)                 /*!< Max enumerator value of BRSE field.                                  */
54993   #define MCAN_CCCR_BRSE_Disabled (0x0UL)            /*!< Bit rate switching for transmissions disabled                        */
54994   #define MCAN_CCCR_BRSE_Enabled (0x1UL)             /*!< Bit rate switching for transmissions enabled                         */
54995 
54996 /* WMM @Bit 11 : Wide Message Marker */
54997   #define MCAN_CCCR_WMM_Pos (11UL)                   /*!< Position of WMM field.                                               */
54998   #define MCAN_CCCR_WMM_Msk (0x1UL << MCAN_CCCR_WMM_Pos) /*!< Bit mask of WMM field.                                           */
54999   #define MCAN_CCCR_WMM_Min (0x0UL)                  /*!< Min enumerator value of WMM field.                                   */
55000   #define MCAN_CCCR_WMM_Max (0x1UL)                  /*!< Max enumerator value of WMM field.                                   */
55001   #define MCAN_CCCR_WMM_Disabled (0x0UL)             /*!< 8-bit Message Marker used                                            */
55002   #define MCAN_CCCR_WMM_Enabled (0x1UL)              /*!< 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event
55003                                                           FIFO*/
55004 
55005 /* PXHD @Bit 12 : Protocol Exception Handling Disable */
55006   #define MCAN_CCCR_PXHD_Pos (12UL)                  /*!< Position of PXHD field.                                              */
55007   #define MCAN_CCCR_PXHD_Msk (0x1UL << MCAN_CCCR_PXHD_Pos) /*!< Bit mask of PXHD field.                                        */
55008   #define MCAN_CCCR_PXHD_Min (0x0UL)                 /*!< Min enumerator value of PXHD field.                                  */
55009   #define MCAN_CCCR_PXHD_Max (0x1UL)                 /*!< Max enumerator value of PXHD field.                                  */
55010   #define MCAN_CCCR_PXHD_Enabled (0x0UL)             /*!< Protocol exception handling enabled                                  */
55011   #define MCAN_CCCR_PXHD_Disabled (0x1UL)            /*!< Protocol exception handling disabled                                 */
55012 
55013 /* EFBI @Bit 13 : Edge Filtering during Bus Integration */
55014   #define MCAN_CCCR_EFBI_Pos (13UL)                  /*!< Position of EFBI field.                                              */
55015   #define MCAN_CCCR_EFBI_Msk (0x1UL << MCAN_CCCR_EFBI_Pos) /*!< Bit mask of EFBI field.                                        */
55016   #define MCAN_CCCR_EFBI_Min (0x0UL)                 /*!< Min enumerator value of EFBI field.                                  */
55017   #define MCAN_CCCR_EFBI_Max (0x1UL)                 /*!< Max enumerator value of EFBI field.                                  */
55018   #define MCAN_CCCR_EFBI_Disabled (0x0UL)            /*!< Edge filtering disabled                                              */
55019   #define MCAN_CCCR_EFBI_Enabled (0x1UL)             /*!< Two consecutive dominant tq required to detect an edge for hard
55020                                                           synchronization*/
55021 
55022 /* TXP @Bit 14 : Transmit Pause */
55023   #define MCAN_CCCR_TXP_Pos (14UL)                   /*!< Position of TXP field.                                               */
55024   #define MCAN_CCCR_TXP_Msk (0x1UL << MCAN_CCCR_TXP_Pos) /*!< Bit mask of TXP field.                                           */
55025   #define MCAN_CCCR_TXP_Min (0x0UL)                  /*!< Min enumerator value of TXP field.                                   */
55026   #define MCAN_CCCR_TXP_Max (0x1UL)                  /*!< Max enumerator value of TXP field.                                   */
55027   #define MCAN_CCCR_TXP_Disabled (0x0UL)             /*!< Transmit pause disabled                                              */
55028   #define MCAN_CCCR_TXP_Enabled (0x1UL)              /*!< Transmit pause enabled                                               */
55029 
55030 /* NISO @Bit 15 : Non ISO Operation */
55031   #define MCAN_CCCR_NISO_Pos (15UL)                  /*!< Position of NISO field.                                              */
55032   #define MCAN_CCCR_NISO_Msk (0x1UL << MCAN_CCCR_NISO_Pos) /*!< Bit mask of NISO field.                                        */
55033   #define MCAN_CCCR_NISO_Min (0x0UL)                 /*!< Min enumerator value of NISO field.                                  */
55034   #define MCAN_CCCR_NISO_Max (0x1UL)                 /*!< Max enumerator value of NISO field.                                  */
55035   #define MCAN_CCCR_NISO_Disabled (0x0UL)            /*!< CAN FD frame format according to ISO 11898-1:2015                    */
55036   #define MCAN_CCCR_NISO_Enabled (0x1UL)             /*!< CAN FD frame format according to Bosch CAN FD Specification V1.0     */
55037 
55038 
55039 /* MCAN_NBTP: Nominal Bit Timing and Prescaler Register */
55040   #define MCAN_NBTP_ResetValue (0x00000000UL)        /*!< Reset value of NBTP register.                                        */
55041 
55042 /* NTSEG2 @Bits 0..6 : Nominal Time segment after sample point */
55043   #define MCAN_NBTP_NTSEG2_Pos (0UL)                 /*!< Position of NTSEG2 field.                                            */
55044   #define MCAN_NBTP_NTSEG2_Msk (0x7FUL << MCAN_NBTP_NTSEG2_Pos) /*!< Bit mask of NTSEG2 field.                                 */
55045 
55046 /* NTSEG1 @Bits 8..15 : Nominal Time segment before sample point */
55047   #define MCAN_NBTP_NTSEG1_Pos (8UL)                 /*!< Position of NTSEG1 field.                                            */
55048   #define MCAN_NBTP_NTSEG1_Msk (0xFFUL << MCAN_NBTP_NTSEG1_Pos) /*!< Bit mask of NTSEG1 field.                                 */
55049 
55050 /* NBRP @Bits 16..24 : Nominal Bit Rate Prescaler */
55051   #define MCAN_NBTP_NBRP_Pos (16UL)                  /*!< Position of NBRP field.                                              */
55052   #define MCAN_NBTP_NBRP_Msk (0x1FFUL << MCAN_NBTP_NBRP_Pos) /*!< Bit mask of NBRP field.                                      */
55053 
55054 /* NSJW @Bits 25..31 : Nominal (Re)Synchronization Jump Width */
55055   #define MCAN_NBTP_NSJW_Pos (25UL)                  /*!< Position of NSJW field.                                              */
55056   #define MCAN_NBTP_NSJW_Msk (0x7FUL << MCAN_NBTP_NSJW_Pos) /*!< Bit mask of NSJW field.                                       */
55057 
55058 
55059 /* MCAN_TSCC: Timestamp Counter Configuration */
55060   #define MCAN_TSCC_ResetValue (0x00000000UL)        /*!< Reset value of TSCC register.                                        */
55061 
55062 /* TSS @Bits 0..1 : Timestamp Select */
55063   #define MCAN_TSCC_TSS_Pos (0UL)                    /*!< Position of TSS field.                                               */
55064   #define MCAN_TSCC_TSS_Msk (0x3UL << MCAN_TSCC_TSS_Pos) /*!< Bit mask of TSS field.                                           */
55065   #define MCAN_TSCC_TSS_Min (0x0UL)                  /*!< Min enumerator value of TSS field.                                   */
55066   #define MCAN_TSCC_TSS_Max (0x3UL)                  /*!< Max enumerator value of TSS field.                                   */
55067   #define MCAN_TSCC_TSS_Zero (0x0UL)                 /*!< Timestamp counter value always 0x0000                                */
55068   #define MCAN_TSCC_TSS_Increment (0x1UL)            /*!< Timestamp counter value incremented according to TCP                 */
55069   #define MCAN_TSCC_TSS_External (0x2UL)             /*!< External timestamp counter value used                                */
55070   #define MCAN_TSCC_TSS_Zero0 (0x3UL)                /*!< Same as Zero                                                         */
55071 
55072 /* TCP @Bits 16..19 : Timestamp Counter Prescaler */
55073   #define MCAN_TSCC_TCP_Pos (16UL)                   /*!< Position of TCP field.                                               */
55074   #define MCAN_TSCC_TCP_Msk (0xFUL << MCAN_TSCC_TCP_Pos) /*!< Bit mask of TCP field.                                           */
55075 
55076 
55077 /* MCAN_TSCV: Timestamp Counter Value */
55078   #define MCAN_TSCV_ResetValue (0x00000000UL)        /*!< Reset value of TSCV register.                                        */
55079 
55080 /* TSC @Bits 0..15 : Timestamp Counter */
55081   #define MCAN_TSCV_TSC_Pos (0UL)                    /*!< Position of TSC field.                                               */
55082   #define MCAN_TSCV_TSC_Msk (0xFFFFUL << MCAN_TSCV_TSC_Pos) /*!< Bit mask of TSC field.                                        */
55083 
55084 
55085 /* MCAN_TOCC: Timeout Counter Configuration */
55086   #define MCAN_TOCC_ResetValue (0x00000000UL)        /*!< Reset value of TOCC register.                                        */
55087 
55088 /* ETOC @Bit 0 : Enable Timeout Counter */
55089   #define MCAN_TOCC_ETOC_Pos (0UL)                   /*!< Position of ETOC field.                                              */
55090   #define MCAN_TOCC_ETOC_Msk (0x1UL << MCAN_TOCC_ETOC_Pos) /*!< Bit mask of ETOC field.                                        */
55091   #define MCAN_TOCC_ETOC_Min (0x0UL)                 /*!< Min enumerator value of ETOC field.                                  */
55092   #define MCAN_TOCC_ETOC_Max (0x1UL)                 /*!< Max enumerator value of ETOC field.                                  */
55093   #define MCAN_TOCC_ETOC_Disabled (0x0UL)            /*!< Timeout Counter disabled                                             */
55094   #define MCAN_TOCC_ETOC_Enabled (0x1UL)             /*!< Timeout Counter enabled                                              */
55095 
55096 /* TOS @Bits 1..2 : Timeout Select */
55097   #define MCAN_TOCC_TOS_Pos (1UL)                    /*!< Position of TOS field.                                               */
55098   #define MCAN_TOCC_TOS_Msk (0x3UL << MCAN_TOCC_TOS_Pos) /*!< Bit mask of TOS field.                                           */
55099   #define MCAN_TOCC_TOS_Min (0x0UL)                  /*!< Min enumerator value of TOS field.                                   */
55100   #define MCAN_TOCC_TOS_Max (0x3UL)                  /*!< Max enumerator value of TOS field.                                   */
55101   #define MCAN_TOCC_TOS_Continuous (0x0UL)           /*!< Continuous operation                                                 */
55102   #define MCAN_TOCC_TOS_TxEvent (0x1UL)              /*!< Timeout controlled by Tx Event FIFO                                  */
55103   #define MCAN_TOCC_TOS_RxFifo0 (0x2UL)              /*!< Timeout controlled by Rx FIFO 0                                      */
55104   #define MCAN_TOCC_TOS_RxFifo1 (0x3UL)              /*!< Timeout controlled by Rx FIFO 1                                      */
55105 
55106 /* TOP @Bits 16..31 : Timeout Period */
55107   #define MCAN_TOCC_TOP_Pos (16UL)                   /*!< Position of TOP field.                                               */
55108   #define MCAN_TOCC_TOP_Msk (0xFFFFUL << MCAN_TOCC_TOP_Pos) /*!< Bit mask of TOP field.                                        */
55109 
55110 
55111 /* MCAN_TOCV: Timeout Counter Value */
55112   #define MCAN_TOCV_ResetValue (0x00000000UL)        /*!< Reset value of TOCV register.                                        */
55113 
55114 /* TOC @Bits 0..15 : Timeout Counter */
55115   #define MCAN_TOCV_TOC_Pos (0UL)                    /*!< Position of TOC field.                                               */
55116   #define MCAN_TOCV_TOC_Msk (0xFFFFUL << MCAN_TOCV_TOC_Pos) /*!< Bit mask of TOC field.                                        */
55117 
55118 
55119 /* MCAN_ECR: Error Counter Register */
55120   #define MCAN_ECR_ResetValue (0x00000000UL)         /*!< Reset value of ECR register.                                         */
55121 
55122 /* TEC @Bits 0..7 : Transmit Error Counter */
55123   #define MCAN_ECR_TEC_Pos (0UL)                     /*!< Position of TEC field.                                               */
55124   #define MCAN_ECR_TEC_Msk (0xFFUL << MCAN_ECR_TEC_Pos) /*!< Bit mask of TEC field.                                            */
55125 
55126 /* REC @Bits 8..14 : Receive Error Counter */
55127   #define MCAN_ECR_REC_Pos (8UL)                     /*!< Position of REC field.                                               */
55128   #define MCAN_ECR_REC_Msk (0x7FUL << MCAN_ECR_REC_Pos) /*!< Bit mask of REC field.                                            */
55129 
55130 /* RP @Bit 15 : Receive Error Passive */
55131   #define MCAN_ECR_RP_Pos (15UL)                     /*!< Position of RP field.                                                */
55132   #define MCAN_ECR_RP_Msk (0x1UL << MCAN_ECR_RP_Pos) /*!< Bit mask of RP field.                                                */
55133   #define MCAN_ECR_RP_Min (0x0UL)                    /*!< Min enumerator value of RP field.                                    */
55134   #define MCAN_ECR_RP_Max (0x1UL)                    /*!< Max enumerator value of RP field.                                    */
55135   #define MCAN_ECR_RP_Below (0x0UL)                  /*!< The Receive Error Counter is below the error passive level of 128    */
55136   #define MCAN_ECR_RP_Reached (0x1UL)                /*!< The Receive Error Counter has reached the error passive level of 128 */
55137 
55138 /* CEL @Bits 16..23 : CAN Error Logging */
55139   #define MCAN_ECR_CEL_Pos (16UL)                    /*!< Position of CEL field.                                               */
55140   #define MCAN_ECR_CEL_Msk (0xFFUL << MCAN_ECR_CEL_Pos) /*!< Bit mask of CEL field.                                            */
55141 
55142 
55143 /* MCAN_PSR: Protocol Status Register */
55144   #define MCAN_PSR_ResetValue (0x00000000UL)         /*!< Reset value of PSR register.                                         */
55145 
55146 /* LEC @Bits 0..2 : Last Error Code */
55147   #define MCAN_PSR_LEC_Pos (0UL)                     /*!< Position of LEC field.                                               */
55148   #define MCAN_PSR_LEC_Msk (0x7UL << MCAN_PSR_LEC_Pos) /*!< Bit mask of LEC field.                                             */
55149   #define MCAN_PSR_LEC_Min (0x0UL)                   /*!< Min enumerator value of LEC field.                                   */
55150   #define MCAN_PSR_LEC_Max (0x7UL)                   /*!< Max enumerator value of LEC field.                                   */
55151   #define MCAN_PSR_LEC_NoError (0x0UL)               /*!< No error occurred since LEC has been reset by successful reception or
55152                                                           transmission.*/
55153   #define MCAN_PSR_LEC_StuffError (0x1UL)            /*!< More than 5 equal bits in a sequence have occurred in a part of a
55154                                                           received message where this is not allowed.*/
55155   #define MCAN_PSR_LEC_FormError (0x2UL)             /*!< A fixed format part of a received frame has the wrong format.        */
55156   #define MCAN_PSR_LEC_AckError (0x3UL)              /*!< The message transmitted by the MCAN was not acknowledged by another
55157                                                           node.*/
55158   #define MCAN_PSR_LEC_Bit1Error (0x4UL)             /*!< During the transmission of a message (with the exception of the
55159                                                           arbitration field), the device wanted to send a recessive level (bit
55160                                                           of logical value 1), but the monitored bus value was dominant.*/
55161   #define MCAN_PSR_LEC_Bit0Error (0x5UL)             /*!< During the transmission of a message (or acknowledge bit, or active
55162                                                           error flag, or overload flag), the device wanted to send a dominant
55163                                                           level (data or identifier bit logical value '0'), but the monitored
55164                                                           bus value was recessive. During Bus_Off recovery this status is set
55165                                                           each time a sequence of 11 recessive bits has been monitored. This
55166                                                           enables the CPU to monitor the proceeding of the Bus_Off recovery
55167                                                           sequence (indicating the bus is not stuck at dominant or continuously
55168                                                           disturbed).*/
55169   #define MCAN_PSR_LEC_CRCError (0x6UL)              /*!< The CRC check sum of a received message was incorrect. The CRC of an
55170                                                           incoming message does not match with the CRC calculated from the
55171                                                           received data.*/
55172   #define MCAN_PSR_LEC_NoChange (0x7UL)              /*!< Any read access to the Protocol Status Register re-initializes the LEC
55173                                                           to '7'. When the LEC shows the value '7', no CAN bus event was
55174                                                           detected since the last CPU read access to the Protocol Status
55175                                                           Register.*/
55176 
55177 /* ACT @Bits 3..4 : Activity */
55178   #define MCAN_PSR_ACT_Pos (3UL)                     /*!< Position of ACT field.                                               */
55179   #define MCAN_PSR_ACT_Msk (0x3UL << MCAN_PSR_ACT_Pos) /*!< Bit mask of ACT field.                                             */
55180   #define MCAN_PSR_ACT_Min (0x0UL)                   /*!< Min enumerator value of ACT field.                                   */
55181   #define MCAN_PSR_ACT_Max (0x3UL)                   /*!< Max enumerator value of ACT field.                                   */
55182   #define MCAN_PSR_ACT_Synchronizing (0x0UL)         /*!< Node is synchronizing on CAN communication                           */
55183   #define MCAN_PSR_ACT_Idle (0x1UL)                  /*!< Node is neither receiver nor tr ansmitter                            */
55184   #define MCAN_PSR_ACT_Receiver (0x2UL)              /*!< Node is operating as receiver                                        */
55185   #define MCAN_PSR_ACT_Transmitter (0x3UL)           /*!< Node is operating as transmitter                                     */
55186 
55187 /* EP @Bit 5 : Error Passive */
55188   #define MCAN_PSR_EP_Pos (5UL)                      /*!< Position of EP field.                                                */
55189   #define MCAN_PSR_EP_Msk (0x1UL << MCAN_PSR_EP_Pos) /*!< Bit mask of EP field.                                                */
55190   #define MCAN_PSR_EP_Min (0x0UL)                    /*!< Min enumerator value of EP field.                                    */
55191   #define MCAN_PSR_EP_Max (0x1UL)                    /*!< Max enumerator value of EP field.                                    */
55192   #define MCAN_PSR_EP_Active (0x0UL)                 /*!< The MCAN is in the Error_Active state. It normally takes part in bus
55193                                                           communication and sends an active error flag when an error has been
55194                                                           detected*/
55195   #define MCAN_PSR_EP_Passive (0x1UL)                /*!< The MCAN is in the Error_Passive state                               */
55196 
55197 /* EW @Bit 6 : Warning Status */
55198   #define MCAN_PSR_EW_Pos (6UL)                      /*!< Position of EW field.                                                */
55199   #define MCAN_PSR_EW_Msk (0x1UL << MCAN_PSR_EW_Pos) /*!< Bit mask of EW field.                                                */
55200   #define MCAN_PSR_EW_Min (0x0UL)                    /*!< Min enumerator value of EW field.                                    */
55201   #define MCAN_PSR_EW_Max (0x1UL)                    /*!< Max enumerator value of EW field.                                    */
55202   #define MCAN_PSR_EW_Below (0x0UL)                  /*!< Both error counters are below the Error_Warning limit of 96          */
55203   #define MCAN_PSR_EW_Reached (0x1UL)                /*!< At least one of error counter has reached the Error_Warning limit of
55204                                                           96*/
55205 
55206 /* BO @Bit 7 : Bus_Off Status */
55207   #define MCAN_PSR_BO_Pos (7UL)                      /*!< Position of BO field.                                                */
55208   #define MCAN_PSR_BO_Msk (0x1UL << MCAN_PSR_BO_Pos) /*!< Bit mask of BO field.                                                */
55209   #define MCAN_PSR_BO_Min (0x0UL)                    /*!< Min enumerator value of BO field.                                    */
55210   #define MCAN_PSR_BO_Max (0x1UL)                    /*!< Max enumerator value of BO field.                                    */
55211   #define MCAN_PSR_BO_On (0x0UL)                     /*!< The MCAN is not Bus_Off                                              */
55212   #define MCAN_PSR_BO_Off (0x1UL)                    /*!< The MCAN is in Bus_Off state                                         */
55213 
55214 /* DLEC @Bits 8..10 : Data Phase Last Error Code */
55215   #define MCAN_PSR_DLEC_Pos (8UL)                    /*!< Position of DLEC field.                                              */
55216   #define MCAN_PSR_DLEC_Msk (0x7UL << MCAN_PSR_DLEC_Pos) /*!< Bit mask of DLEC field.                                          */
55217 
55218 /* RESI @Bit 11 : ESI flag of last received CAN FD Message */
55219   #define MCAN_PSR_RESI_Pos (11UL)                   /*!< Position of RESI field.                                              */
55220   #define MCAN_PSR_RESI_Msk (0x1UL << MCAN_PSR_RESI_Pos) /*!< Bit mask of RESI field.                                          */
55221   #define MCAN_PSR_RESI_Min (0x0UL)                  /*!< Min enumerator value of RESI field.                                  */
55222   #define MCAN_PSR_RESI_Max (0x1UL)                  /*!< Max enumerator value of RESI field.                                  */
55223   #define MCAN_PSR_RESI_NotReceived (0x0UL)          /*!< Last received CAN FD message did not ha ve its ESI flag set          */
55224   #define MCAN_PSR_RESI_Received (0x1UL)             /*!< Last received CAN FD message had its ESI flag set                    */
55225 
55226 /* RBRS @Bit 12 : BRS flag of last received CAN FD Message */
55227   #define MCAN_PSR_RBRS_Pos (12UL)                   /*!< Position of RBRS field.                                              */
55228   #define MCAN_PSR_RBRS_Msk (0x1UL << MCAN_PSR_RBRS_Pos) /*!< Bit mask of RBRS field.                                          */
55229   #define MCAN_PSR_RBRS_Min (0x0UL)                  /*!< Min enumerator value of RBRS field.                                  */
55230   #define MCAN_PSR_RBRS_Max (0x1UL)                  /*!< Max enumerator value of RBRS field.                                  */
55231   #define MCAN_PSR_RBRS_NotReceived (0x0UL)          /*!< Last received CAN FD message did not ha ve its BRS flag set          */
55232   #define MCAN_PSR_RBRS_Received (0x1UL)             /*!< Last received CAN FD message had its BRS flag set                    */
55233 
55234 /* RFDF @Bit 13 : Received a CAN FD Message */
55235   #define MCAN_PSR_RFDF_Pos (13UL)                   /*!< Position of RFDF field.                                              */
55236   #define MCAN_PSR_RFDF_Msk (0x1UL << MCAN_PSR_RFDF_Pos) /*!< Bit mask of RFDF field.                                          */
55237   #define MCAN_PSR_RFDF_Min (0x0UL)                  /*!< Min enumerator value of RFDF field.                                  */
55238   #define MCAN_PSR_RFDF_Max (0x1UL)                  /*!< Max enumerator value of RFDF field.                                  */
55239   #define MCAN_PSR_RFDF_NotReceived (0x0UL)          /*!< Since this bit was reset by the CPU, no CAN FD message has been
55240                                                           received*/
55241   #define MCAN_PSR_RFDF_Received (0x1UL)             /*!< Message in CAN FD format with FDF flag set has been received         */
55242 
55243 /* PXE @Bit 14 : Protocol Exception Event */
55244   #define MCAN_PSR_PXE_Pos (14UL)                    /*!< Position of PXE field.                                               */
55245   #define MCAN_PSR_PXE_Msk (0x1UL << MCAN_PSR_PXE_Pos) /*!< Bit mask of PXE field.                                             */
55246   #define MCAN_PSR_PXE_Min (0x0UL)                   /*!< Min enumerator value of PXE field.                                   */
55247   #define MCAN_PSR_PXE_Max (0x1UL)                   /*!< Max enumerator value of PXE field.                                   */
55248   #define MCAN_PSR_PXE_NotTriggered (0x0UL)          /*!< No protocol exception event occurred since last read access          */
55249   #define MCAN_PSR_PXE_Triggered (0x1UL)             /*!< Protocol exception event occurred                                    */
55250 
55251 /* TDCV @Bits 16..22 : Transmitter Delay Compensation Value */
55252   #define MCAN_PSR_TDCV_Pos (16UL)                   /*!< Position of TDCV field.                                              */
55253   #define MCAN_PSR_TDCV_Msk (0x7FUL << MCAN_PSR_TDCV_Pos) /*!< Bit mask of TDCV field.                                         */
55254 
55255 
55256 /* MCAN_TDCR: Transmitter Delay Compensation Register */
55257   #define MCAN_TDCR_ResetValue (0x00000000UL)        /*!< Reset value of TDCR register.                                        */
55258 
55259 /* TDCF @Bits 0..6 : Transmitter Delay Compensation Filter Window Length */
55260   #define MCAN_TDCR_TDCF_Pos (0UL)                   /*!< Position of TDCF field.                                              */
55261   #define MCAN_TDCR_TDCF_Msk (0x7FUL << MCAN_TDCR_TDCF_Pos) /*!< Bit mask of TDCF field.                                       */
55262 
55263 /* TDCO @Bits 8..14 : Transmitter Delay Compensation SSP Offset */
55264   #define MCAN_TDCR_TDCO_Pos (8UL)                   /*!< Position of TDCO field.                                              */
55265   #define MCAN_TDCR_TDCO_Msk (0x7FUL << MCAN_TDCR_TDCO_Pos) /*!< Bit mask of TDCO field.                                       */
55266 
55267 
55268 /* MCAN_IR: Interrupt Register */
55269   #define MCAN_IR_ResetValue (0x00000000UL)          /*!< Reset value of IR register.                                          */
55270 
55271 /* RF0N @Bit 0 : Rx FIFO 0 New Message */
55272   #define MCAN_IR_RF0N_Pos (0UL)                     /*!< Position of RF0N field.                                              */
55273   #define MCAN_IR_RF0N_Msk (0x1UL << MCAN_IR_RF0N_Pos) /*!< Bit mask of RF0N field.                                            */
55274   #define MCAN_IR_RF0N_Min (0x0UL)                   /*!< Min enumerator value of RF0N field.                                  */
55275   #define MCAN_IR_RF0N_Max (0x1UL)                   /*!< Max enumerator value of RF0N field.                                  */
55276   #define MCAN_IR_RF0N_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55277   #define MCAN_IR_RF0N_NotGenerated (0x0UL)          /*!< No new message written to Rx FIFO 0                                  */
55278   #define MCAN_IR_RF0N_Generated (0x1UL)             /*!< New message written to Rx FIFO 0                                     */
55279 
55280 /* RF0W @Bit 1 : Rx FIFO 0 Watermark Reached */
55281   #define MCAN_IR_RF0W_Pos (1UL)                     /*!< Position of RF0W field.                                              */
55282   #define MCAN_IR_RF0W_Msk (0x1UL << MCAN_IR_RF0W_Pos) /*!< Bit mask of RF0W field.                                            */
55283   #define MCAN_IR_RF0W_Min (0x0UL)                   /*!< Min enumerator value of RF0W field.                                  */
55284   #define MCAN_IR_RF0W_Max (0x1UL)                   /*!< Max enumerator value of RF0W field.                                  */
55285   #define MCAN_IR_RF0W_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55286   #define MCAN_IR_RF0W_NotGenerated (0x0UL)          /*!< Rx FIFO 0 fill level below watermark                                 */
55287   #define MCAN_IR_RF0W_Generated (0x1UL)             /*!< Rx FIFO 0 fill level reached watermark                               */
55288 
55289 /* RF0F @Bit 2 : Rx FIFO 0 Full */
55290   #define MCAN_IR_RF0F_Pos (2UL)                     /*!< Position of RF0F field.                                              */
55291   #define MCAN_IR_RF0F_Msk (0x1UL << MCAN_IR_RF0F_Pos) /*!< Bit mask of RF0F field.                                            */
55292   #define MCAN_IR_RF0F_Min (0x0UL)                   /*!< Min enumerator value of RF0F field.                                  */
55293   #define MCAN_IR_RF0F_Max (0x1UL)                   /*!< Max enumerator value of RF0F field.                                  */
55294   #define MCAN_IR_RF0F_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55295   #define MCAN_IR_RF0F_NotGenerated (0x0UL)          /*!< Rx FIFO 0 not full                                                   */
55296   #define MCAN_IR_RF0F_Generated (0x1UL)             /*!< Rx FIFO 0 full                                                       */
55297 
55298 /* RF0L @Bit 3 : Rx FIFO 0 Message Lost */
55299   #define MCAN_IR_RF0L_Pos (3UL)                     /*!< Position of RF0L field.                                              */
55300   #define MCAN_IR_RF0L_Msk (0x1UL << MCAN_IR_RF0L_Pos) /*!< Bit mask of RF0L field.                                            */
55301   #define MCAN_IR_RF0L_Min (0x0UL)                   /*!< Min enumerator value of RF0L field.                                  */
55302   #define MCAN_IR_RF0L_Max (0x1UL)                   /*!< Max enumerator value of RF0L field.                                  */
55303   #define MCAN_IR_RF0L_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55304   #define MCAN_IR_RF0L_NotGenerated (0x0UL)          /*!< No Rx FIFO 0 message lost                                            */
55305   #define MCAN_IR_RF0L_Generated (0x1UL)             /*!< Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of
55306                                                           size zero*/
55307 
55308 /* RF1N @Bit 4 : Rx FIFO 1 New Message */
55309   #define MCAN_IR_RF1N_Pos (4UL)                     /*!< Position of RF1N field.                                              */
55310   #define MCAN_IR_RF1N_Msk (0x1UL << MCAN_IR_RF1N_Pos) /*!< Bit mask of RF1N field.                                            */
55311   #define MCAN_IR_RF1N_Min (0x0UL)                   /*!< Min enumerator value of RF1N field.                                  */
55312   #define MCAN_IR_RF1N_Max (0x1UL)                   /*!< Max enumerator value of RF1N field.                                  */
55313   #define MCAN_IR_RF1N_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55314   #define MCAN_IR_RF1N_NotGenerated (0x0UL)          /*!< No new message written to Rx FIFO 1                                  */
55315   #define MCAN_IR_RF1N_Generated (0x1UL)             /*!< New message written to Rx FIFO 1                                     */
55316 
55317 /* RF1W @Bit 5 : Rx FIFO 1 Watermark Reached */
55318   #define MCAN_IR_RF1W_Pos (5UL)                     /*!< Position of RF1W field.                                              */
55319   #define MCAN_IR_RF1W_Msk (0x1UL << MCAN_IR_RF1W_Pos) /*!< Bit mask of RF1W field.                                            */
55320   #define MCAN_IR_RF1W_Min (0x0UL)                   /*!< Min enumerator value of RF1W field.                                  */
55321   #define MCAN_IR_RF1W_Max (0x1UL)                   /*!< Max enumerator value of RF1W field.                                  */
55322   #define MCAN_IR_RF1W_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55323   #define MCAN_IR_RF1W_NotGenerated (0x0UL)          /*!< Rx FIFO 1 fill level below watermark                                 */
55324   #define MCAN_IR_RF1W_Generated (0x1UL)             /*!< Rx FIFO 1 fill level reached watermark                               */
55325 
55326 /* RF1F @Bit 6 : Rx FIFO 1 Full */
55327   #define MCAN_IR_RF1F_Pos (6UL)                     /*!< Position of RF1F field.                                              */
55328   #define MCAN_IR_RF1F_Msk (0x1UL << MCAN_IR_RF1F_Pos) /*!< Bit mask of RF1F field.                                            */
55329   #define MCAN_IR_RF1F_Min (0x0UL)                   /*!< Min enumerator value of RF1F field.                                  */
55330   #define MCAN_IR_RF1F_Max (0x1UL)                   /*!< Max enumerator value of RF1F field.                                  */
55331   #define MCAN_IR_RF1F_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55332   #define MCAN_IR_RF1F_NotGenerated (0x0UL)          /*!< Rx FIFO 1 not full                                                   */
55333   #define MCAN_IR_RF1F_Generated (0x1UL)             /*!< Rx FIFO 1 full                                                       */
55334 
55335 /* RF1L @Bit 7 : Rx FIFO 1 Message Lost */
55336   #define MCAN_IR_RF1L_Pos (7UL)                     /*!< Position of RF1L field.                                              */
55337   #define MCAN_IR_RF1L_Msk (0x1UL << MCAN_IR_RF1L_Pos) /*!< Bit mask of RF1L field.                                            */
55338   #define MCAN_IR_RF1L_Min (0x0UL)                   /*!< Min enumerator value of RF1L field.                                  */
55339   #define MCAN_IR_RF1L_Max (0x1UL)                   /*!< Max enumerator value of RF1L field.                                  */
55340   #define MCAN_IR_RF1L_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55341   #define MCAN_IR_RF1L_NotGenerated (0x0UL)          /*!< No Rx FIFO 1 message lost                                            */
55342   #define MCAN_IR_RF1L_Generated (0x1UL)             /*!< Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of
55343                                                           size zero*/
55344 
55345 /* HPM @Bit 8 : High Priority Message */
55346   #define MCAN_IR_HPM_Pos (8UL)                      /*!< Position of HPM field.                                               */
55347   #define MCAN_IR_HPM_Msk (0x1UL << MCAN_IR_HPM_Pos) /*!< Bit mask of HPM field.                                               */
55348   #define MCAN_IR_HPM_Min (0x0UL)                    /*!< Min enumerator value of HPM field.                                   */
55349   #define MCAN_IR_HPM_Max (0x1UL)                    /*!< Max enumerator value of HPM field.                                   */
55350   #define MCAN_IR_HPM_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55351   #define MCAN_IR_HPM_NotGenerated (0x0UL)           /*!< No high priority message received                                    */
55352   #define MCAN_IR_HPM_Generated (0x1UL)              /*!< High priority message received                                       */
55353 
55354 /* TC @Bit 9 : Transmission Completed */
55355   #define MCAN_IR_TC_Pos (9UL)                       /*!< Position of TC field.                                                */
55356   #define MCAN_IR_TC_Msk (0x1UL << MCAN_IR_TC_Pos)   /*!< Bit mask of TC field.                                                */
55357   #define MCAN_IR_TC_Min (0x0UL)                     /*!< Min enumerator value of TC field.                                    */
55358   #define MCAN_IR_TC_Max (0x1UL)                     /*!< Max enumerator value of TC field.                                    */
55359   #define MCAN_IR_TC_Clear (0x1UL)                   /*!< Write '1' to clear interrupt flag                                    */
55360   #define MCAN_IR_TC_NotGenerated (0x0UL)            /*!< No transmission completed                                            */
55361   #define MCAN_IR_TC_Generated (0x1UL)               /*!< Transmission completed                                               */
55362 
55363 /* TCF @Bit 10 : Transmission Cancellation Finished */
55364   #define MCAN_IR_TCF_Pos (10UL)                     /*!< Position of TCF field.                                               */
55365   #define MCAN_IR_TCF_Msk (0x1UL << MCAN_IR_TCF_Pos) /*!< Bit mask of TCF field.                                               */
55366   #define MCAN_IR_TCF_Min (0x0UL)                    /*!< Min enumerator value of TCF field.                                   */
55367   #define MCAN_IR_TCF_Max (0x1UL)                    /*!< Max enumerator value of TCF field.                                   */
55368   #define MCAN_IR_TCF_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55369   #define MCAN_IR_TCF_NotGenerated (0x0UL)           /*!< No transmission cancellation finished                                */
55370   #define MCAN_IR_TCF_Generated (0x1UL)              /*!< Transmission cancellation finished                                   */
55371 
55372 /* TFE @Bit 11 : Tx FIFO Empty */
55373   #define MCAN_IR_TFE_Pos (11UL)                     /*!< Position of TFE field.                                               */
55374   #define MCAN_IR_TFE_Msk (0x1UL << MCAN_IR_TFE_Pos) /*!< Bit mask of TFE field.                                               */
55375   #define MCAN_IR_TFE_Min (0x0UL)                    /*!< Min enumerator value of TFE field.                                   */
55376   #define MCAN_IR_TFE_Max (0x1UL)                    /*!< Max enumerator value of TFE field.                                   */
55377   #define MCAN_IR_TFE_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55378   #define MCAN_IR_TFE_NotGenerated (0x0UL)           /*!< Tx FIFO non-empty                                                    */
55379   #define MCAN_IR_TFE_Generated (0x1UL)              /*!< Tx FIFO empty                                                        */
55380 
55381 /* TEFN @Bit 12 : Tx Event FIFO New Entry */
55382   #define MCAN_IR_TEFN_Pos (12UL)                    /*!< Position of TEFN field.                                              */
55383   #define MCAN_IR_TEFN_Msk (0x1UL << MCAN_IR_TEFN_Pos) /*!< Bit mask of TEFN field.                                            */
55384   #define MCAN_IR_TEFN_Min (0x0UL)                   /*!< Min enumerator value of TEFN field.                                  */
55385   #define MCAN_IR_TEFN_Max (0x1UL)                   /*!< Max enumerator value of TEFN field.                                  */
55386   #define MCAN_IR_TEFN_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55387   #define MCAN_IR_TEFN_NotGenerated (0x0UL)          /*!< Tx Event FIFO unchanged                                              */
55388   #define MCAN_IR_TEFN_Generated (0x1UL)             /*!< Tx Handler wrote Tx Event FIFO element                               */
55389 
55390 /* TEFW @Bit 13 : Tx Event FIFO Watermark Reached */
55391   #define MCAN_IR_TEFW_Pos (13UL)                    /*!< Position of TEFW field.                                              */
55392   #define MCAN_IR_TEFW_Msk (0x1UL << MCAN_IR_TEFW_Pos) /*!< Bit mask of TEFW field.                                            */
55393   #define MCAN_IR_TEFW_Min (0x0UL)                   /*!< Min enumerator value of TEFW field.                                  */
55394   #define MCAN_IR_TEFW_Max (0x1UL)                   /*!< Max enumerator value of TEFW field.                                  */
55395   #define MCAN_IR_TEFW_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55396   #define MCAN_IR_TEFW_NotGenerated (0x0UL)          /*!< Tx Event FIFO fill level below watermark                             */
55397   #define MCAN_IR_TEFW_Generated (0x1UL)             /*!< Tx Event FIFO fill level reached watermark                           */
55398 
55399 /* TEFF @Bit 14 : Tx Event FIFO Full */
55400   #define MCAN_IR_TEFF_Pos (14UL)                    /*!< Position of TEFF field.                                              */
55401   #define MCAN_IR_TEFF_Msk (0x1UL << MCAN_IR_TEFF_Pos) /*!< Bit mask of TEFF field.                                            */
55402   #define MCAN_IR_TEFF_Min (0x0UL)                   /*!< Min enumerator value of TEFF field.                                  */
55403   #define MCAN_IR_TEFF_Max (0x1UL)                   /*!< Max enumerator value of TEFF field.                                  */
55404   #define MCAN_IR_TEFF_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55405   #define MCAN_IR_TEFF_NotGenerated (0x0UL)          /*!< Tx Event FIFO not full                                               */
55406   #define MCAN_IR_TEFF_Generated (0x1UL)             /*!< Tx Event FIFO full                                                   */
55407 
55408 /* TEFL @Bit 15 : Tx Event FIFO Element Lost */
55409   #define MCAN_IR_TEFL_Pos (15UL)                    /*!< Position of TEFL field.                                              */
55410   #define MCAN_IR_TEFL_Msk (0x1UL << MCAN_IR_TEFL_Pos) /*!< Bit mask of TEFL field.                                            */
55411   #define MCAN_IR_TEFL_Min (0x0UL)                   /*!< Min enumerator value of TEFL field.                                  */
55412   #define MCAN_IR_TEFL_Max (0x1UL)                   /*!< Max enumerator value of TEFL field.                                  */
55413   #define MCAN_IR_TEFL_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55414   #define MCAN_IR_TEFL_NotGenerated (0x0UL)          /*!< No Tx Event FIFO element lost                                        */
55415   #define MCAN_IR_TEFL_Generated (0x1UL)             /*!< Tx Event FIFO element lost, also set after wr ite attempt to Tx Event
55416                                                           FIFO of siz e zero*/
55417 
55418 /* TSW @Bit 16 : Timestamp Wraparound */
55419   #define MCAN_IR_TSW_Pos (16UL)                     /*!< Position of TSW field.                                               */
55420   #define MCAN_IR_TSW_Msk (0x1UL << MCAN_IR_TSW_Pos) /*!< Bit mask of TSW field.                                               */
55421   #define MCAN_IR_TSW_Min (0x0UL)                    /*!< Min enumerator value of TSW field.                                   */
55422   #define MCAN_IR_TSW_Max (0x1UL)                    /*!< Max enumerator value of TSW field.                                   */
55423   #define MCAN_IR_TSW_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55424   #define MCAN_IR_TSW_NotGenerated (0x0UL)           /*!< No timestamp counter wrap-around                                     */
55425   #define MCAN_IR_TSW_Generated (0x1UL)              /*!< Timestamp counter wrapped around                                     */
55426 
55427 /* MRAF @Bit 17 : Message RAM Access Failure */
55428   #define MCAN_IR_MRAF_Pos (17UL)                    /*!< Position of MRAF field.                                              */
55429   #define MCAN_IR_MRAF_Msk (0x1UL << MCAN_IR_MRAF_Pos) /*!< Bit mask of MRAF field.                                            */
55430   #define MCAN_IR_MRAF_Min (0x0UL)                   /*!< Min enumerator value of MRAF field.                                  */
55431   #define MCAN_IR_MRAF_Max (0x1UL)                   /*!< Max enumerator value of MRAF field.                                  */
55432   #define MCAN_IR_MRAF_Clear (0x1UL)                 /*!< Write '1' to clear interrupt flag                                    */
55433   #define MCAN_IR_MRAF_NotGenerated (0x0UL)          /*!< No Message RAM access failure occurred                               */
55434   #define MCAN_IR_MRAF_Generated (0x1UL)             /*!< Message RAM access failure occurred                                  */
55435 
55436 /* TOO @Bit 18 : Timeout Occurred */
55437   #define MCAN_IR_TOO_Pos (18UL)                     /*!< Position of TOO field.                                               */
55438   #define MCAN_IR_TOO_Msk (0x1UL << MCAN_IR_TOO_Pos) /*!< Bit mask of TOO field.                                               */
55439   #define MCAN_IR_TOO_Min (0x0UL)                    /*!< Min enumerator value of TOO field.                                   */
55440   #define MCAN_IR_TOO_Max (0x1UL)                    /*!< Max enumerator value of TOO field.                                   */
55441   #define MCAN_IR_TOO_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55442   #define MCAN_IR_TOO_NotGenerated (0x0UL)           /*!< No timeout                                                           */
55443   #define MCAN_IR_TOO_Generated (0x1UL)              /*!< Timeout reached                                                      */
55444 
55445 /* DRX @Bit 19 : Message stored to Dedicated Rx Buffer */
55446   #define MCAN_IR_DRX_Pos (19UL)                     /*!< Position of DRX field.                                               */
55447   #define MCAN_IR_DRX_Msk (0x1UL << MCAN_IR_DRX_Pos) /*!< Bit mask of DRX field.                                               */
55448   #define MCAN_IR_DRX_Min (0x0UL)                    /*!< Min enumerator value of DRX field.                                   */
55449   #define MCAN_IR_DRX_Max (0x1UL)                    /*!< Max enumerator value of DRX field.                                   */
55450   #define MCAN_IR_DRX_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55451   #define MCAN_IR_DRX_NotGenerated (0x0UL)           /*!< No Rx Buffer updated                                                 */
55452   #define MCAN_IR_DRX_Generated (0x1UL)              /*!< At least one received message stored into an Rx Buff er              */
55453 
55454 /* BEU @Bit 21 : Bus Error Uncorrected */
55455   #define MCAN_IR_BEU_Pos (21UL)                     /*!< Position of BEU field.                                               */
55456   #define MCAN_IR_BEU_Msk (0x1UL << MCAN_IR_BEU_Pos) /*!< Bit mask of BEU field.                                               */
55457   #define MCAN_IR_BEU_Min (0x0UL)                    /*!< Min enumerator value of BEU field.                                   */
55458   #define MCAN_IR_BEU_Max (0x1UL)                    /*!< Max enumerator value of BEU field.                                   */
55459   #define MCAN_IR_BEU_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55460   #define MCAN_IR_BEU_NotGenerated (0x0UL)           /*!< No read slave error detected when reading from Message RAM           */
55461   #define MCAN_IR_BEU_Generated (0x1UL)              /*!< Read slave error detected                                            */
55462 
55463 /* ELO @Bit 22 : Error Logging Overflow */
55464   #define MCAN_IR_ELO_Pos (22UL)                     /*!< Position of ELO field.                                               */
55465   #define MCAN_IR_ELO_Msk (0x1UL << MCAN_IR_ELO_Pos) /*!< Bit mask of ELO field.                                               */
55466   #define MCAN_IR_ELO_Min (0x0UL)                    /*!< Min enumerator value of ELO field.                                   */
55467   #define MCAN_IR_ELO_Max (0x1UL)                    /*!< Max enumerator value of ELO field.                                   */
55468   #define MCAN_IR_ELO_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55469   #define MCAN_IR_ELO_NotGenerated (0x0UL)           /*!< CAN Error Logging Counter did not overflow                           */
55470   #define MCAN_IR_ELO_Generated (0x1UL)              /*!< Overflow of CAN Error Logging Counter occurred                       */
55471 
55472 /* EP @Bit 23 : Error Passive */
55473   #define MCAN_IR_EP_Pos (23UL)                      /*!< Position of EP field.                                                */
55474   #define MCAN_IR_EP_Msk (0x1UL << MCAN_IR_EP_Pos)   /*!< Bit mask of EP field.                                                */
55475   #define MCAN_IR_EP_Min (0x0UL)                     /*!< Min enumerator value of EP field.                                    */
55476   #define MCAN_IR_EP_Max (0x1UL)                     /*!< Max enumerator value of EP field.                                    */
55477   #define MCAN_IR_EP_Clear (0x1UL)                   /*!< Write '1' to clear interrupt flag                                    */
55478   #define MCAN_IR_EP_NotGenerated (0x0UL)            /*!< Error_Passive status unchanged                                       */
55479   #define MCAN_IR_EP_Generated (0x1UL)               /*!< Error_Passive status changed                                         */
55480 
55481 /* EW @Bit 24 : Warning Status */
55482   #define MCAN_IR_EW_Pos (24UL)                      /*!< Position of EW field.                                                */
55483   #define MCAN_IR_EW_Msk (0x1UL << MCAN_IR_EW_Pos)   /*!< Bit mask of EW field.                                                */
55484   #define MCAN_IR_EW_Min (0x0UL)                     /*!< Min enumerator value of EW field.                                    */
55485   #define MCAN_IR_EW_Max (0x1UL)                     /*!< Max enumerator value of EW field.                                    */
55486   #define MCAN_IR_EW_Clear (0x1UL)                   /*!< Write '1' to clear interrupt flag                                    */
55487   #define MCAN_IR_EW_NotGenerated (0x0UL)            /*!< Error_Warning status unchanged                                       */
55488   #define MCAN_IR_EW_Generated (0x1UL)               /*!< Error_Warning status changed                                         */
55489 
55490 /* BO @Bit 25 : Bus_Off Status */
55491   #define MCAN_IR_BO_Pos (25UL)                      /*!< Position of BO field.                                                */
55492   #define MCAN_IR_BO_Msk (0x1UL << MCAN_IR_BO_Pos)   /*!< Bit mask of BO field.                                                */
55493   #define MCAN_IR_BO_Min (0x0UL)                     /*!< Min enumerator value of BO field.                                    */
55494   #define MCAN_IR_BO_Max (0x1UL)                     /*!< Max enumerator value of BO field.                                    */
55495   #define MCAN_IR_BO_Clear (0x1UL)                   /*!< Write '1' to clear interrupt flag                                    */
55496   #define MCAN_IR_BO_NotGenerated (0x0UL)            /*!< Bus_Off status unchanged                                             */
55497   #define MCAN_IR_BO_Generated (0x1UL)               /*!< Bus_Off status changed                                               */
55498 
55499 /* WDI @Bit 26 : Watchdog Interrupt */
55500   #define MCAN_IR_WDI_Pos (26UL)                     /*!< Position of WDI field.                                               */
55501   #define MCAN_IR_WDI_Msk (0x1UL << MCAN_IR_WDI_Pos) /*!< Bit mask of WDI field.                                               */
55502   #define MCAN_IR_WDI_Min (0x0UL)                    /*!< Min enumerator value of WDI field.                                   */
55503   #define MCAN_IR_WDI_Max (0x1UL)                    /*!< Max enumerator value of WDI field.                                   */
55504   #define MCAN_IR_WDI_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55505   #define MCAN_IR_WDI_NotGenerated (0x0UL)           /*!< No Message RAM Watchdog event occurred                               */
55506   #define MCAN_IR_WDI_Generated (0x1UL)              /*!< Message RAM Watchdog event due to missing READY                      */
55507 
55508 /* PEA @Bit 27 : Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
55509   #define MCAN_IR_PEA_Pos (27UL)                     /*!< Position of PEA field.                                               */
55510   #define MCAN_IR_PEA_Msk (0x1UL << MCAN_IR_PEA_Pos) /*!< Bit mask of PEA field.                                               */
55511   #define MCAN_IR_PEA_Min (0x0UL)                    /*!< Min enumerator value of PEA field.                                   */
55512   #define MCAN_IR_PEA_Max (0x1UL)                    /*!< Max enumerator value of PEA field.                                   */
55513   #define MCAN_IR_PEA_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55514   #define MCAN_IR_PEA_NotGenerated (0x0UL)           /*!< No protocol error in arbitration phase                               */
55515   #define MCAN_IR_PEA_Generated (0x1UL)              /*!< Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)         */
55516 
55517 /* PED @Bit 28 : Protocol Error in Data Phase (Data Bit Time is used) */
55518   #define MCAN_IR_PED_Pos (28UL)                     /*!< Position of PED field.                                               */
55519   #define MCAN_IR_PED_Msk (0x1UL << MCAN_IR_PED_Pos) /*!< Bit mask of PED field.                                               */
55520   #define MCAN_IR_PED_Min (0x0UL)                    /*!< Min enumerator value of PED field.                                   */
55521   #define MCAN_IR_PED_Max (0x1UL)                    /*!< Max enumerator value of PED field.                                   */
55522   #define MCAN_IR_PED_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55523   #define MCAN_IR_PED_NotGenerated (0x0UL)           /*!< No protocol error in data phase                                      */
55524   #define MCAN_IR_PED_Generated (0x1UL)              /*!< Protocol error in data phase detected (PSR.DLEC ≠ 0,7)               */
55525 
55526 /* ARA @Bit 29 : Access to Reserved Address */
55527   #define MCAN_IR_ARA_Pos (29UL)                     /*!< Position of ARA field.                                               */
55528   #define MCAN_IR_ARA_Msk (0x1UL << MCAN_IR_ARA_Pos) /*!< Bit mask of ARA field.                                               */
55529   #define MCAN_IR_ARA_Min (0x0UL)                    /*!< Min enumerator value of ARA field.                                   */
55530   #define MCAN_IR_ARA_Max (0x1UL)                    /*!< Max enumerator value of ARA field.                                   */
55531   #define MCAN_IR_ARA_Clear (0x1UL)                  /*!< Write '1' to clear interrupt flag                                    */
55532   #define MCAN_IR_ARA_NotGenerated (0x0UL)           /*!< No access to reserved address occurred                               */
55533   #define MCAN_IR_ARA_Generated (0x1UL)              /*!< Access to reserved address occurred                                  */
55534 
55535 
55536 /* MCAN_IE: Interrupt Enable */
55537   #define MCAN_IE_ResetValue (0x00000000UL)          /*!< Reset value of IE register.                                          */
55538 
55539 /* RF0NE @Bit 0 : Rx FIFO 0 New Message Interrupt Enable */
55540   #define MCAN_IE_RF0NE_Pos (0UL)                    /*!< Position of RF0NE field.                                             */
55541   #define MCAN_IE_RF0NE_Msk (0x1UL << MCAN_IE_RF0NE_Pos) /*!< Bit mask of RF0NE field.                                         */
55542   #define MCAN_IE_RF0NE_Min (0x0UL)                  /*!< Min enumerator value of RF0NE field.                                 */
55543   #define MCAN_IE_RF0NE_Max (0x1UL)                  /*!< Max enumerator value of RF0NE field.                                 */
55544   #define MCAN_IE_RF0NE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55545   #define MCAN_IE_RF0NE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55546 
55547 /* RF0WE @Bit 1 : Rx FIFO 0 Watermark Reached Interrupt Enable */
55548   #define MCAN_IE_RF0WE_Pos (1UL)                    /*!< Position of RF0WE field.                                             */
55549   #define MCAN_IE_RF0WE_Msk (0x1UL << MCAN_IE_RF0WE_Pos) /*!< Bit mask of RF0WE field.                                         */
55550   #define MCAN_IE_RF0WE_Min (0x0UL)                  /*!< Min enumerator value of RF0WE field.                                 */
55551   #define MCAN_IE_RF0WE_Max (0x1UL)                  /*!< Max enumerator value of RF0WE field.                                 */
55552   #define MCAN_IE_RF0WE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55553   #define MCAN_IE_RF0WE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55554 
55555 /* RF0FE @Bit 2 : Rx FIFO 0 Full Interrupt Enable */
55556   #define MCAN_IE_RF0FE_Pos (2UL)                    /*!< Position of RF0FE field.                                             */
55557   #define MCAN_IE_RF0FE_Msk (0x1UL << MCAN_IE_RF0FE_Pos) /*!< Bit mask of RF0FE field.                                         */
55558   #define MCAN_IE_RF0FE_Min (0x0UL)                  /*!< Min enumerator value of RF0FE field.                                 */
55559   #define MCAN_IE_RF0FE_Max (0x1UL)                  /*!< Max enumerator value of RF0FE field.                                 */
55560   #define MCAN_IE_RF0FE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55561   #define MCAN_IE_RF0FE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55562 
55563 /* RF0LE @Bit 3 : Rx FIFO 0 Message Lost Interrupt Enable */
55564   #define MCAN_IE_RF0LE_Pos (3UL)                    /*!< Position of RF0LE field.                                             */
55565   #define MCAN_IE_RF0LE_Msk (0x1UL << MCAN_IE_RF0LE_Pos) /*!< Bit mask of RF0LE field.                                         */
55566   #define MCAN_IE_RF0LE_Min (0x0UL)                  /*!< Min enumerator value of RF0LE field.                                 */
55567   #define MCAN_IE_RF0LE_Max (0x1UL)                  /*!< Max enumerator value of RF0LE field.                                 */
55568   #define MCAN_IE_RF0LE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55569   #define MCAN_IE_RF0LE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55570 
55571 /* RF1NE @Bit 4 : Rx FIFO 1 New Message Interrupt Enable */
55572   #define MCAN_IE_RF1NE_Pos (4UL)                    /*!< Position of RF1NE field.                                             */
55573   #define MCAN_IE_RF1NE_Msk (0x1UL << MCAN_IE_RF1NE_Pos) /*!< Bit mask of RF1NE field.                                         */
55574   #define MCAN_IE_RF1NE_Min (0x0UL)                  /*!< Min enumerator value of RF1NE field.                                 */
55575   #define MCAN_IE_RF1NE_Max (0x1UL)                  /*!< Max enumerator value of RF1NE field.                                 */
55576   #define MCAN_IE_RF1NE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55577   #define MCAN_IE_RF1NE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55578 
55579 /* RF1WE @Bit 5 : Rx FIFO 1 Watermark Reached Interrupt Enable */
55580   #define MCAN_IE_RF1WE_Pos (5UL)                    /*!< Position of RF1WE field.                                             */
55581   #define MCAN_IE_RF1WE_Msk (0x1UL << MCAN_IE_RF1WE_Pos) /*!< Bit mask of RF1WE field.                                         */
55582   #define MCAN_IE_RF1WE_Min (0x0UL)                  /*!< Min enumerator value of RF1WE field.                                 */
55583   #define MCAN_IE_RF1WE_Max (0x1UL)                  /*!< Max enumerator value of RF1WE field.                                 */
55584   #define MCAN_IE_RF1WE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55585   #define MCAN_IE_RF1WE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55586 
55587 /* RF1FE @Bit 6 : Rx FIFO 1 Full Interrupt Enable */
55588   #define MCAN_IE_RF1FE_Pos (6UL)                    /*!< Position of RF1FE field.                                             */
55589   #define MCAN_IE_RF1FE_Msk (0x1UL << MCAN_IE_RF1FE_Pos) /*!< Bit mask of RF1FE field.                                         */
55590   #define MCAN_IE_RF1FE_Min (0x0UL)                  /*!< Min enumerator value of RF1FE field.                                 */
55591   #define MCAN_IE_RF1FE_Max (0x1UL)                  /*!< Max enumerator value of RF1FE field.                                 */
55592   #define MCAN_IE_RF1FE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55593   #define MCAN_IE_RF1FE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55594 
55595 /* RF1LE @Bit 7 : Rx FIFO 1 Message Lost Interrupt Enable */
55596   #define MCAN_IE_RF1LE_Pos (7UL)                    /*!< Position of RF1LE field.                                             */
55597   #define MCAN_IE_RF1LE_Msk (0x1UL << MCAN_IE_RF1LE_Pos) /*!< Bit mask of RF1LE field.                                         */
55598   #define MCAN_IE_RF1LE_Min (0x0UL)                  /*!< Min enumerator value of RF1LE field.                                 */
55599   #define MCAN_IE_RF1LE_Max (0x1UL)                  /*!< Max enumerator value of RF1LE field.                                 */
55600   #define MCAN_IE_RF1LE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55601   #define MCAN_IE_RF1LE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55602 
55603 /* HPME @Bit 8 : High Priority Message Interrupt Enable */
55604   #define MCAN_IE_HPME_Pos (8UL)                     /*!< Position of HPME field.                                              */
55605   #define MCAN_IE_HPME_Msk (0x1UL << MCAN_IE_HPME_Pos) /*!< Bit mask of HPME field.                                            */
55606   #define MCAN_IE_HPME_Min (0x0UL)                   /*!< Min enumerator value of HPME field.                                  */
55607   #define MCAN_IE_HPME_Max (0x1UL)                   /*!< Max enumerator value of HPME field.                                  */
55608   #define MCAN_IE_HPME_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55609   #define MCAN_IE_HPME_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55610 
55611 /* TCE @Bit 9 : Transmission Completed Interrupt Enable */
55612   #define MCAN_IE_TCE_Pos (9UL)                      /*!< Position of TCE field.                                               */
55613   #define MCAN_IE_TCE_Msk (0x1UL << MCAN_IE_TCE_Pos) /*!< Bit mask of TCE field.                                               */
55614   #define MCAN_IE_TCE_Min (0x0UL)                    /*!< Min enumerator value of TCE field.                                   */
55615   #define MCAN_IE_TCE_Max (0x1UL)                    /*!< Max enumerator value of TCE field.                                   */
55616   #define MCAN_IE_TCE_Disable (0x0UL)                /*!< Interrupt disabled.                                                  */
55617   #define MCAN_IE_TCE_Enable (0x1UL)                 /*!< Interrupt enabled.                                                   */
55618 
55619 /* TCFE @Bit 10 : Transmission Cancellation Finished Interrupt Enable */
55620   #define MCAN_IE_TCFE_Pos (10UL)                    /*!< Position of TCFE field.                                              */
55621   #define MCAN_IE_TCFE_Msk (0x1UL << MCAN_IE_TCFE_Pos) /*!< Bit mask of TCFE field.                                            */
55622   #define MCAN_IE_TCFE_Min (0x0UL)                   /*!< Min enumerator value of TCFE field.                                  */
55623   #define MCAN_IE_TCFE_Max (0x1UL)                   /*!< Max enumerator value of TCFE field.                                  */
55624   #define MCAN_IE_TCFE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55625   #define MCAN_IE_TCFE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55626 
55627 /* TFEE @Bit 11 : Tx FIFO Empty Interrupt Enable */
55628   #define MCAN_IE_TFEE_Pos (11UL)                    /*!< Position of TFEE field.                                              */
55629   #define MCAN_IE_TFEE_Msk (0x1UL << MCAN_IE_TFEE_Pos) /*!< Bit mask of TFEE field.                                            */
55630   #define MCAN_IE_TFEE_Min (0x0UL)                   /*!< Min enumerator value of TFEE field.                                  */
55631   #define MCAN_IE_TFEE_Max (0x1UL)                   /*!< Max enumerator value of TFEE field.                                  */
55632   #define MCAN_IE_TFEE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55633   #define MCAN_IE_TFEE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55634 
55635 /* TEFNE @Bit 12 : Tx Event FIFO New Entry Interrupt Enable */
55636   #define MCAN_IE_TEFNE_Pos (12UL)                   /*!< Position of TEFNE field.                                             */
55637   #define MCAN_IE_TEFNE_Msk (0x1UL << MCAN_IE_TEFNE_Pos) /*!< Bit mask of TEFNE field.                                         */
55638   #define MCAN_IE_TEFNE_Min (0x0UL)                  /*!< Min enumerator value of TEFNE field.                                 */
55639   #define MCAN_IE_TEFNE_Max (0x1UL)                  /*!< Max enumerator value of TEFNE field.                                 */
55640   #define MCAN_IE_TEFNE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55641   #define MCAN_IE_TEFNE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55642 
55643 /* TEFWE @Bit 13 : Tx Event FIFO Watermark Reached Interrupt Enable */
55644   #define MCAN_IE_TEFWE_Pos (13UL)                   /*!< Position of TEFWE field.                                             */
55645   #define MCAN_IE_TEFWE_Msk (0x1UL << MCAN_IE_TEFWE_Pos) /*!< Bit mask of TEFWE field.                                         */
55646   #define MCAN_IE_TEFWE_Min (0x0UL)                  /*!< Min enumerator value of TEFWE field.                                 */
55647   #define MCAN_IE_TEFWE_Max (0x1UL)                  /*!< Max enumerator value of TEFWE field.                                 */
55648   #define MCAN_IE_TEFWE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55649   #define MCAN_IE_TEFWE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55650 
55651 /* TEFFE @Bit 14 : Tx Event FIFO Full Interrupt Enable */
55652   #define MCAN_IE_TEFFE_Pos (14UL)                   /*!< Position of TEFFE field.                                             */
55653   #define MCAN_IE_TEFFE_Msk (0x1UL << MCAN_IE_TEFFE_Pos) /*!< Bit mask of TEFFE field.                                         */
55654   #define MCAN_IE_TEFFE_Min (0x0UL)                  /*!< Min enumerator value of TEFFE field.                                 */
55655   #define MCAN_IE_TEFFE_Max (0x1UL)                  /*!< Max enumerator value of TEFFE field.                                 */
55656   #define MCAN_IE_TEFFE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55657   #define MCAN_IE_TEFFE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55658 
55659 /* TEFLE @Bit 15 : Tx Event FIFO Event Lost Interrupt Enable */
55660   #define MCAN_IE_TEFLE_Pos (15UL)                   /*!< Position of TEFLE field.                                             */
55661   #define MCAN_IE_TEFLE_Msk (0x1UL << MCAN_IE_TEFLE_Pos) /*!< Bit mask of TEFLE field.                                         */
55662   #define MCAN_IE_TEFLE_Min (0x0UL)                  /*!< Min enumerator value of TEFLE field.                                 */
55663   #define MCAN_IE_TEFLE_Max (0x1UL)                  /*!< Max enumerator value of TEFLE field.                                 */
55664   #define MCAN_IE_TEFLE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55665   #define MCAN_IE_TEFLE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55666 
55667 /* TSWE @Bit 16 : Timestamp Wraparound Interrupt Enable */
55668   #define MCAN_IE_TSWE_Pos (16UL)                    /*!< Position of TSWE field.                                              */
55669   #define MCAN_IE_TSWE_Msk (0x1UL << MCAN_IE_TSWE_Pos) /*!< Bit mask of TSWE field.                                            */
55670   #define MCAN_IE_TSWE_Min (0x0UL)                   /*!< Min enumerator value of TSWE field.                                  */
55671   #define MCAN_IE_TSWE_Max (0x1UL)                   /*!< Max enumerator value of TSWE field.                                  */
55672   #define MCAN_IE_TSWE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55673   #define MCAN_IE_TSWE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55674 
55675 /* MRAFE @Bit 17 : Message RAM Access Failure Interrupt Enable */
55676   #define MCAN_IE_MRAFE_Pos (17UL)                   /*!< Position of MRAFE field.                                             */
55677   #define MCAN_IE_MRAFE_Msk (0x1UL << MCAN_IE_MRAFE_Pos) /*!< Bit mask of MRAFE field.                                         */
55678   #define MCAN_IE_MRAFE_Min (0x0UL)                  /*!< Min enumerator value of MRAFE field.                                 */
55679   #define MCAN_IE_MRAFE_Max (0x1UL)                  /*!< Max enumerator value of MRAFE field.                                 */
55680   #define MCAN_IE_MRAFE_Disable (0x0UL)              /*!< Interrupt disabled.                                                  */
55681   #define MCAN_IE_MRAFE_Enable (0x1UL)               /*!< Interrupt enabled.                                                   */
55682 
55683 /* TOOE @Bit 18 : Timeout Occurred Interrupt Enable */
55684   #define MCAN_IE_TOOE_Pos (18UL)                    /*!< Position of TOOE field.                                              */
55685   #define MCAN_IE_TOOE_Msk (0x1UL << MCAN_IE_TOOE_Pos) /*!< Bit mask of TOOE field.                                            */
55686   #define MCAN_IE_TOOE_Min (0x0UL)                   /*!< Min enumerator value of TOOE field.                                  */
55687   #define MCAN_IE_TOOE_Max (0x1UL)                   /*!< Max enumerator value of TOOE field.                                  */
55688   #define MCAN_IE_TOOE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55689   #define MCAN_IE_TOOE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55690 
55691 /* DRXE @Bit 19 : Message stored to Dedicated Rx Buffer Interrupt Enable */
55692   #define MCAN_IE_DRXE_Pos (19UL)                    /*!< Position of DRXE field.                                              */
55693   #define MCAN_IE_DRXE_Msk (0x1UL << MCAN_IE_DRXE_Pos) /*!< Bit mask of DRXE field.                                            */
55694   #define MCAN_IE_DRXE_Min (0x0UL)                   /*!< Min enumerator value of DRXE field.                                  */
55695   #define MCAN_IE_DRXE_Max (0x1UL)                   /*!< Max enumerator value of DRXE field.                                  */
55696   #define MCAN_IE_DRXE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55697   #define MCAN_IE_DRXE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55698 
55699 /* BEUE @Bit 21 : Bus Error Uncorrected Interrupt Enable */
55700   #define MCAN_IE_BEUE_Pos (21UL)                    /*!< Position of BEUE field.                                              */
55701   #define MCAN_IE_BEUE_Msk (0x1UL << MCAN_IE_BEUE_Pos) /*!< Bit mask of BEUE field.                                            */
55702   #define MCAN_IE_BEUE_Min (0x0UL)                   /*!< Min enumerator value of BEUE field.                                  */
55703   #define MCAN_IE_BEUE_Max (0x1UL)                   /*!< Max enumerator value of BEUE field.                                  */
55704   #define MCAN_IE_BEUE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55705   #define MCAN_IE_BEUE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55706 
55707 /* ELOE @Bit 22 : Error Logging Overflow Interrupt Enable */
55708   #define MCAN_IE_ELOE_Pos (22UL)                    /*!< Position of ELOE field.                                              */
55709   #define MCAN_IE_ELOE_Msk (0x1UL << MCAN_IE_ELOE_Pos) /*!< Bit mask of ELOE field.                                            */
55710   #define MCAN_IE_ELOE_Min (0x0UL)                   /*!< Min enumerator value of ELOE field.                                  */
55711   #define MCAN_IE_ELOE_Max (0x1UL)                   /*!< Max enumerator value of ELOE field.                                  */
55712   #define MCAN_IE_ELOE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55713   #define MCAN_IE_ELOE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55714 
55715 /* EPE @Bit 23 : Error Passive Interrupt Enable */
55716   #define MCAN_IE_EPE_Pos (23UL)                     /*!< Position of EPE field.                                               */
55717   #define MCAN_IE_EPE_Msk (0x1UL << MCAN_IE_EPE_Pos) /*!< Bit mask of EPE field.                                               */
55718   #define MCAN_IE_EPE_Min (0x0UL)                    /*!< Min enumerator value of EPE field.                                   */
55719   #define MCAN_IE_EPE_Max (0x1UL)                    /*!< Max enumerator value of EPE field.                                   */
55720   #define MCAN_IE_EPE_Disable (0x0UL)                /*!< Interrupt disabled.                                                  */
55721   #define MCAN_IE_EPE_Enable (0x1UL)                 /*!< Interrupt enabled.                                                   */
55722 
55723 /* EWE @Bit 24 : Warning Status Interrupt Enable */
55724   #define MCAN_IE_EWE_Pos (24UL)                     /*!< Position of EWE field.                                               */
55725   #define MCAN_IE_EWE_Msk (0x1UL << MCAN_IE_EWE_Pos) /*!< Bit mask of EWE field.                                               */
55726   #define MCAN_IE_EWE_Min (0x0UL)                    /*!< Min enumerator value of EWE field.                                   */
55727   #define MCAN_IE_EWE_Max (0x1UL)                    /*!< Max enumerator value of EWE field.                                   */
55728   #define MCAN_IE_EWE_Disable (0x0UL)                /*!< Interrupt disabled.                                                  */
55729   #define MCAN_IE_EWE_Enable (0x1UL)                 /*!< Interrupt enabled.                                                   */
55730 
55731 /* BOE @Bit 25 : Bus_Off Status Interrupt Enable */
55732   #define MCAN_IE_BOE_Pos (25UL)                     /*!< Position of BOE field.                                               */
55733   #define MCAN_IE_BOE_Msk (0x1UL << MCAN_IE_BOE_Pos) /*!< Bit mask of BOE field.                                               */
55734   #define MCAN_IE_BOE_Min (0x0UL)                    /*!< Min enumerator value of BOE field.                                   */
55735   #define MCAN_IE_BOE_Max (0x1UL)                    /*!< Max enumerator value of BOE field.                                   */
55736   #define MCAN_IE_BOE_Disable (0x0UL)                /*!< Interrupt disabled.                                                  */
55737   #define MCAN_IE_BOE_Enable (0x1UL)                 /*!< Interrupt enabled.                                                   */
55738 
55739 /* WDIE @Bit 26 : Watchdog Interrupt Enable */
55740   #define MCAN_IE_WDIE_Pos (26UL)                    /*!< Position of WDIE field.                                              */
55741   #define MCAN_IE_WDIE_Msk (0x1UL << MCAN_IE_WDIE_Pos) /*!< Bit mask of WDIE field.                                            */
55742   #define MCAN_IE_WDIE_Min (0x0UL)                   /*!< Min enumerator value of WDIE field.                                  */
55743   #define MCAN_IE_WDIE_Max (0x1UL)                   /*!< Max enumerator value of WDIE field.                                  */
55744   #define MCAN_IE_WDIE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55745   #define MCAN_IE_WDIE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55746 
55747 /* PEAE @Bit 27 : Protocol Error in Arbitration Phase Enable */
55748   #define MCAN_IE_PEAE_Pos (27UL)                    /*!< Position of PEAE field.                                              */
55749   #define MCAN_IE_PEAE_Msk (0x1UL << MCAN_IE_PEAE_Pos) /*!< Bit mask of PEAE field.                                            */
55750   #define MCAN_IE_PEAE_Min (0x0UL)                   /*!< Min enumerator value of PEAE field.                                  */
55751   #define MCAN_IE_PEAE_Max (0x1UL)                   /*!< Max enumerator value of PEAE field.                                  */
55752   #define MCAN_IE_PEAE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55753   #define MCAN_IE_PEAE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55754 
55755 /* PEDE @Bit 28 : Protocol Error in Data Phase Enable */
55756   #define MCAN_IE_PEDE_Pos (28UL)                    /*!< Position of PEDE field.                                              */
55757   #define MCAN_IE_PEDE_Msk (0x1UL << MCAN_IE_PEDE_Pos) /*!< Bit mask of PEDE field.                                            */
55758   #define MCAN_IE_PEDE_Min (0x0UL)                   /*!< Min enumerator value of PEDE field.                                  */
55759   #define MCAN_IE_PEDE_Max (0x1UL)                   /*!< Max enumerator value of PEDE field.                                  */
55760   #define MCAN_IE_PEDE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55761   #define MCAN_IE_PEDE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55762 
55763 /* ARAE @Bit 29 : Access to Reserved Address Enable */
55764   #define MCAN_IE_ARAE_Pos (29UL)                    /*!< Position of ARAE field.                                              */
55765   #define MCAN_IE_ARAE_Msk (0x1UL << MCAN_IE_ARAE_Pos) /*!< Bit mask of ARAE field.                                            */
55766   #define MCAN_IE_ARAE_Min (0x0UL)                   /*!< Min enumerator value of ARAE field.                                  */
55767   #define MCAN_IE_ARAE_Max (0x1UL)                   /*!< Max enumerator value of ARAE field.                                  */
55768   #define MCAN_IE_ARAE_Disable (0x0UL)               /*!< Interrupt disabled.                                                  */
55769   #define MCAN_IE_ARAE_Enable (0x1UL)                /*!< Interrupt enabled.                                                   */
55770 
55771 
55772 /* MCAN_ILS: Interrupt Line Select */
55773   #define MCAN_ILS_ResetValue (0x00000000UL)         /*!< Reset value of ILS register.                                         */
55774 
55775 /* RF0NL @Bit 0 : Rx FIFO 0 New Message Interrupt Line */
55776   #define MCAN_ILS_RF0NL_Pos (0UL)                   /*!< Position of RF0NL field.                                             */
55777   #define MCAN_ILS_RF0NL_Msk (0x1UL << MCAN_ILS_RF0NL_Pos) /*!< Bit mask of RF0NL field.                                       */
55778   #define MCAN_ILS_RF0NL_Min (0x0UL)                 /*!< Min enumerator value of RF0NL field.                                 */
55779   #define MCAN_ILS_RF0NL_Max (0x1UL)                 /*!< Max enumerator value of RF0NL field.                                 */
55780   #define MCAN_ILS_RF0NL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55781   #define MCAN_ILS_RF0NL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55782 
55783 /* RF0WL @Bit 1 : Rx FIFO 0 Watermark Reached Interrupt Line */
55784   #define MCAN_ILS_RF0WL_Pos (1UL)                   /*!< Position of RF0WL field.                                             */
55785   #define MCAN_ILS_RF0WL_Msk (0x1UL << MCAN_ILS_RF0WL_Pos) /*!< Bit mask of RF0WL field.                                       */
55786   #define MCAN_ILS_RF0WL_Min (0x0UL)                 /*!< Min enumerator value of RF0WL field.                                 */
55787   #define MCAN_ILS_RF0WL_Max (0x1UL)                 /*!< Max enumerator value of RF0WL field.                                 */
55788   #define MCAN_ILS_RF0WL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55789   #define MCAN_ILS_RF0WL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55790 
55791 /* RF0FL @Bit 2 : Rx FIFO 0 Full Interrupt Line */
55792   #define MCAN_ILS_RF0FL_Pos (2UL)                   /*!< Position of RF0FL field.                                             */
55793   #define MCAN_ILS_RF0FL_Msk (0x1UL << MCAN_ILS_RF0FL_Pos) /*!< Bit mask of RF0FL field.                                       */
55794   #define MCAN_ILS_RF0FL_Min (0x0UL)                 /*!< Min enumerator value of RF0FL field.                                 */
55795   #define MCAN_ILS_RF0FL_Max (0x1UL)                 /*!< Max enumerator value of RF0FL field.                                 */
55796   #define MCAN_ILS_RF0FL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55797   #define MCAN_ILS_RF0FL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55798 
55799 /* RF0LL @Bit 3 : Rx FIFO 0 Message Lost Interrupt Line */
55800   #define MCAN_ILS_RF0LL_Pos (3UL)                   /*!< Position of RF0LL field.                                             */
55801   #define MCAN_ILS_RF0LL_Msk (0x1UL << MCAN_ILS_RF0LL_Pos) /*!< Bit mask of RF0LL field.                                       */
55802   #define MCAN_ILS_RF0LL_Min (0x0UL)                 /*!< Min enumerator value of RF0LL field.                                 */
55803   #define MCAN_ILS_RF0LL_Max (0x1UL)                 /*!< Max enumerator value of RF0LL field.                                 */
55804   #define MCAN_ILS_RF0LL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55805   #define MCAN_ILS_RF0LL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55806 
55807 /* RF1NL @Bit 4 : Rx FIFO 1 New Message Interrupt Line */
55808   #define MCAN_ILS_RF1NL_Pos (4UL)                   /*!< Position of RF1NL field.                                             */
55809   #define MCAN_ILS_RF1NL_Msk (0x1UL << MCAN_ILS_RF1NL_Pos) /*!< Bit mask of RF1NL field.                                       */
55810   #define MCAN_ILS_RF1NL_Min (0x0UL)                 /*!< Min enumerator value of RF1NL field.                                 */
55811   #define MCAN_ILS_RF1NL_Max (0x1UL)                 /*!< Max enumerator value of RF1NL field.                                 */
55812   #define MCAN_ILS_RF1NL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55813   #define MCAN_ILS_RF1NL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55814 
55815 /* RF1WL @Bit 5 : Rx FIFO 1 Watermark Reached Interrupt Line */
55816   #define MCAN_ILS_RF1WL_Pos (5UL)                   /*!< Position of RF1WL field.                                             */
55817   #define MCAN_ILS_RF1WL_Msk (0x1UL << MCAN_ILS_RF1WL_Pos) /*!< Bit mask of RF1WL field.                                       */
55818   #define MCAN_ILS_RF1WL_Min (0x0UL)                 /*!< Min enumerator value of RF1WL field.                                 */
55819   #define MCAN_ILS_RF1WL_Max (0x1UL)                 /*!< Max enumerator value of RF1WL field.                                 */
55820   #define MCAN_ILS_RF1WL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55821   #define MCAN_ILS_RF1WL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55822 
55823 /* RF1FL @Bit 6 : Rx FIFO 1 Full Interrupt Line */
55824   #define MCAN_ILS_RF1FL_Pos (6UL)                   /*!< Position of RF1FL field.                                             */
55825   #define MCAN_ILS_RF1FL_Msk (0x1UL << MCAN_ILS_RF1FL_Pos) /*!< Bit mask of RF1FL field.                                       */
55826   #define MCAN_ILS_RF1FL_Min (0x0UL)                 /*!< Min enumerator value of RF1FL field.                                 */
55827   #define MCAN_ILS_RF1FL_Max (0x1UL)                 /*!< Max enumerator value of RF1FL field.                                 */
55828   #define MCAN_ILS_RF1FL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55829   #define MCAN_ILS_RF1FL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55830 
55831 /* RF1LL @Bit 7 : Rx FIFO 1 Message Lost Interrupt Line */
55832   #define MCAN_ILS_RF1LL_Pos (7UL)                   /*!< Position of RF1LL field.                                             */
55833   #define MCAN_ILS_RF1LL_Msk (0x1UL << MCAN_ILS_RF1LL_Pos) /*!< Bit mask of RF1LL field.                                       */
55834   #define MCAN_ILS_RF1LL_Min (0x0UL)                 /*!< Min enumerator value of RF1LL field.                                 */
55835   #define MCAN_ILS_RF1LL_Max (0x1UL)                 /*!< Max enumerator value of RF1LL field.                                 */
55836   #define MCAN_ILS_RF1LL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55837   #define MCAN_ILS_RF1LL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55838 
55839 /* HPML @Bit 8 : High Priority Message Interrupt Line */
55840   #define MCAN_ILS_HPML_Pos (8UL)                    /*!< Position of HPML field.                                              */
55841   #define MCAN_ILS_HPML_Msk (0x1UL << MCAN_ILS_HPML_Pos) /*!< Bit mask of HPML field.                                          */
55842   #define MCAN_ILS_HPML_Min (0x0UL)                  /*!< Min enumerator value of HPML field.                                  */
55843   #define MCAN_ILS_HPML_Max (0x1UL)                  /*!< Max enumerator value of HPML field.                                  */
55844   #define MCAN_ILS_HPML_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55845   #define MCAN_ILS_HPML_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55846 
55847 /* TCL @Bit 9 : Transmission Completed Interrupt Line */
55848   #define MCAN_ILS_TCL_Pos (9UL)                     /*!< Position of TCL field.                                               */
55849   #define MCAN_ILS_TCL_Msk (0x1UL << MCAN_ILS_TCL_Pos) /*!< Bit mask of TCL field.                                             */
55850   #define MCAN_ILS_TCL_Min (0x0UL)                   /*!< Min enumerator value of TCL field.                                   */
55851   #define MCAN_ILS_TCL_Max (0x1UL)                   /*!< Max enumerator value of TCL field.                                   */
55852   #define MCAN_ILS_TCL_Assigned0 (0x0UL)             /*!< Interrupt assigned to interrupt line CORE0.                          */
55853   #define MCAN_ILS_TCL_Assigned1 (0x1UL)             /*!< Interrupt assigned to interrupt line CORE1.                          */
55854 
55855 /* TCFL @Bit 10 : Transmission Cancellation Finished Interrupt Line */
55856   #define MCAN_ILS_TCFL_Pos (10UL)                   /*!< Position of TCFL field.                                              */
55857   #define MCAN_ILS_TCFL_Msk (0x1UL << MCAN_ILS_TCFL_Pos) /*!< Bit mask of TCFL field.                                          */
55858   #define MCAN_ILS_TCFL_Min (0x0UL)                  /*!< Min enumerator value of TCFL field.                                  */
55859   #define MCAN_ILS_TCFL_Max (0x1UL)                  /*!< Max enumerator value of TCFL field.                                  */
55860   #define MCAN_ILS_TCFL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55861   #define MCAN_ILS_TCFL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55862 
55863 /* TFEL @Bit 11 : Tx FIFO Empty Interrupt Line */
55864   #define MCAN_ILS_TFEL_Pos (11UL)                   /*!< Position of TFEL field.                                              */
55865   #define MCAN_ILS_TFEL_Msk (0x1UL << MCAN_ILS_TFEL_Pos) /*!< Bit mask of TFEL field.                                          */
55866   #define MCAN_ILS_TFEL_Min (0x0UL)                  /*!< Min enumerator value of TFEL field.                                  */
55867   #define MCAN_ILS_TFEL_Max (0x1UL)                  /*!< Max enumerator value of TFEL field.                                  */
55868   #define MCAN_ILS_TFEL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55869   #define MCAN_ILS_TFEL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55870 
55871 /* TEFNL @Bit 12 : Tx Event FIFO New Entry Interrupt Line */
55872   #define MCAN_ILS_TEFNL_Pos (12UL)                  /*!< Position of TEFNL field.                                             */
55873   #define MCAN_ILS_TEFNL_Msk (0x1UL << MCAN_ILS_TEFNL_Pos) /*!< Bit mask of TEFNL field.                                       */
55874   #define MCAN_ILS_TEFNL_Min (0x0UL)                 /*!< Min enumerator value of TEFNL field.                                 */
55875   #define MCAN_ILS_TEFNL_Max (0x1UL)                 /*!< Max enumerator value of TEFNL field.                                 */
55876   #define MCAN_ILS_TEFNL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55877   #define MCAN_ILS_TEFNL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55878 
55879 /* TEFWL @Bit 13 : Tx Event FIFO Watermark Reached Interrupt Line */
55880   #define MCAN_ILS_TEFWL_Pos (13UL)                  /*!< Position of TEFWL field.                                             */
55881   #define MCAN_ILS_TEFWL_Msk (0x1UL << MCAN_ILS_TEFWL_Pos) /*!< Bit mask of TEFWL field.                                       */
55882   #define MCAN_ILS_TEFWL_Min (0x0UL)                 /*!< Min enumerator value of TEFWL field.                                 */
55883   #define MCAN_ILS_TEFWL_Max (0x1UL)                 /*!< Max enumerator value of TEFWL field.                                 */
55884   #define MCAN_ILS_TEFWL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55885   #define MCAN_ILS_TEFWL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55886 
55887 /* TEFFL @Bit 14 : Tx Event FIFO Full Interrupt Line */
55888   #define MCAN_ILS_TEFFL_Pos (14UL)                  /*!< Position of TEFFL field.                                             */
55889   #define MCAN_ILS_TEFFL_Msk (0x1UL << MCAN_ILS_TEFFL_Pos) /*!< Bit mask of TEFFL field.                                       */
55890   #define MCAN_ILS_TEFFL_Min (0x0UL)                 /*!< Min enumerator value of TEFFL field.                                 */
55891   #define MCAN_ILS_TEFFL_Max (0x1UL)                 /*!< Max enumerator value of TEFFL field.                                 */
55892   #define MCAN_ILS_TEFFL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55893   #define MCAN_ILS_TEFFL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55894 
55895 /* TEFLL @Bit 15 : Tx Event FIFO Event Lost Interrupt Line */
55896   #define MCAN_ILS_TEFLL_Pos (15UL)                  /*!< Position of TEFLL field.                                             */
55897   #define MCAN_ILS_TEFLL_Msk (0x1UL << MCAN_ILS_TEFLL_Pos) /*!< Bit mask of TEFLL field.                                       */
55898   #define MCAN_ILS_TEFLL_Min (0x0UL)                 /*!< Min enumerator value of TEFLL field.                                 */
55899   #define MCAN_ILS_TEFLL_Max (0x1UL)                 /*!< Max enumerator value of TEFLL field.                                 */
55900   #define MCAN_ILS_TEFLL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55901   #define MCAN_ILS_TEFLL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55902 
55903 /* TSWL @Bit 16 : Timestamp Wraparound Interrupt Line */
55904   #define MCAN_ILS_TSWL_Pos (16UL)                   /*!< Position of TSWL field.                                              */
55905   #define MCAN_ILS_TSWL_Msk (0x1UL << MCAN_ILS_TSWL_Pos) /*!< Bit mask of TSWL field.                                          */
55906   #define MCAN_ILS_TSWL_Min (0x0UL)                  /*!< Min enumerator value of TSWL field.                                  */
55907   #define MCAN_ILS_TSWL_Max (0x1UL)                  /*!< Max enumerator value of TSWL field.                                  */
55908   #define MCAN_ILS_TSWL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55909   #define MCAN_ILS_TSWL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55910 
55911 /* MRAFL @Bit 17 : Message RAM Access Failure Interrupt Line */
55912   #define MCAN_ILS_MRAFL_Pos (17UL)                  /*!< Position of MRAFL field.                                             */
55913   #define MCAN_ILS_MRAFL_Msk (0x1UL << MCAN_ILS_MRAFL_Pos) /*!< Bit mask of MRAFL field.                                       */
55914   #define MCAN_ILS_MRAFL_Min (0x0UL)                 /*!< Min enumerator value of MRAFL field.                                 */
55915   #define MCAN_ILS_MRAFL_Max (0x1UL)                 /*!< Max enumerator value of MRAFL field.                                 */
55916   #define MCAN_ILS_MRAFL_Assigned0 (0x0UL)           /*!< Interrupt assigned to interrupt line CORE0.                          */
55917   #define MCAN_ILS_MRAFL_Assigned1 (0x1UL)           /*!< Interrupt assigned to interrupt line CORE1.                          */
55918 
55919 /* TOOL @Bit 18 : Timeout Occurred Interrupt Line */
55920   #define MCAN_ILS_TOOL_Pos (18UL)                   /*!< Position of TOOL field.                                              */
55921   #define MCAN_ILS_TOOL_Msk (0x1UL << MCAN_ILS_TOOL_Pos) /*!< Bit mask of TOOL field.                                          */
55922   #define MCAN_ILS_TOOL_Min (0x0UL)                  /*!< Min enumerator value of TOOL field.                                  */
55923   #define MCAN_ILS_TOOL_Max (0x1UL)                  /*!< Max enumerator value of TOOL field.                                  */
55924   #define MCAN_ILS_TOOL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55925   #define MCAN_ILS_TOOL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55926 
55927 /* DRXL @Bit 19 : Message stored to Dedicated Rx Buffer Interrupt Line */
55928   #define MCAN_ILS_DRXL_Pos (19UL)                   /*!< Position of DRXL field.                                              */
55929   #define MCAN_ILS_DRXL_Msk (0x1UL << MCAN_ILS_DRXL_Pos) /*!< Bit mask of DRXL field.                                          */
55930   #define MCAN_ILS_DRXL_Min (0x0UL)                  /*!< Min enumerator value of DRXL field.                                  */
55931   #define MCAN_ILS_DRXL_Max (0x1UL)                  /*!< Max enumerator value of DRXL field.                                  */
55932   #define MCAN_ILS_DRXL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55933   #define MCAN_ILS_DRXL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55934 
55935 /* BEUL @Bit 21 : Bus Error Uncorrected Interrupt Line */
55936   #define MCAN_ILS_BEUL_Pos (21UL)                   /*!< Position of BEUL field.                                              */
55937   #define MCAN_ILS_BEUL_Msk (0x1UL << MCAN_ILS_BEUL_Pos) /*!< Bit mask of BEUL field.                                          */
55938   #define MCAN_ILS_BEUL_Min (0x0UL)                  /*!< Min enumerator value of BEUL field.                                  */
55939   #define MCAN_ILS_BEUL_Max (0x1UL)                  /*!< Max enumerator value of BEUL field.                                  */
55940   #define MCAN_ILS_BEUL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55941   #define MCAN_ILS_BEUL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55942 
55943 /* ELOL @Bit 22 : Error Logging Overflow Interrupt Line */
55944   #define MCAN_ILS_ELOL_Pos (22UL)                   /*!< Position of ELOL field.                                              */
55945   #define MCAN_ILS_ELOL_Msk (0x1UL << MCAN_ILS_ELOL_Pos) /*!< Bit mask of ELOL field.                                          */
55946   #define MCAN_ILS_ELOL_Min (0x0UL)                  /*!< Min enumerator value of ELOL field.                                  */
55947   #define MCAN_ILS_ELOL_Max (0x1UL)                  /*!< Max enumerator value of ELOL field.                                  */
55948   #define MCAN_ILS_ELOL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55949   #define MCAN_ILS_ELOL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55950 
55951 /* EPL @Bit 23 : Error Passive Interrupt Line */
55952   #define MCAN_ILS_EPL_Pos (23UL)                    /*!< Position of EPL field.                                               */
55953   #define MCAN_ILS_EPL_Msk (0x1UL << MCAN_ILS_EPL_Pos) /*!< Bit mask of EPL field.                                             */
55954   #define MCAN_ILS_EPL_Min (0x0UL)                   /*!< Min enumerator value of EPL field.                                   */
55955   #define MCAN_ILS_EPL_Max (0x1UL)                   /*!< Max enumerator value of EPL field.                                   */
55956   #define MCAN_ILS_EPL_Assigned0 (0x0UL)             /*!< Interrupt assigned to interrupt line CORE0.                          */
55957   #define MCAN_ILS_EPL_Assigned1 (0x1UL)             /*!< Interrupt assigned to interrupt line CORE1.                          */
55958 
55959 /* EWL @Bit 24 : Warning Status Interrupt Line */
55960   #define MCAN_ILS_EWL_Pos (24UL)                    /*!< Position of EWL field.                                               */
55961   #define MCAN_ILS_EWL_Msk (0x1UL << MCAN_ILS_EWL_Pos) /*!< Bit mask of EWL field.                                             */
55962   #define MCAN_ILS_EWL_Min (0x0UL)                   /*!< Min enumerator value of EWL field.                                   */
55963   #define MCAN_ILS_EWL_Max (0x1UL)                   /*!< Max enumerator value of EWL field.                                   */
55964   #define MCAN_ILS_EWL_Assigned0 (0x0UL)             /*!< Interrupt assigned to interrupt line CORE0.                          */
55965   #define MCAN_ILS_EWL_Assigned1 (0x1UL)             /*!< Interrupt assigned to interrupt line CORE1.                          */
55966 
55967 /* BOL @Bit 25 : Bus_Off Status Interrupt Line */
55968   #define MCAN_ILS_BOL_Pos (25UL)                    /*!< Position of BOL field.                                               */
55969   #define MCAN_ILS_BOL_Msk (0x1UL << MCAN_ILS_BOL_Pos) /*!< Bit mask of BOL field.                                             */
55970   #define MCAN_ILS_BOL_Min (0x0UL)                   /*!< Min enumerator value of BOL field.                                   */
55971   #define MCAN_ILS_BOL_Max (0x1UL)                   /*!< Max enumerator value of BOL field.                                   */
55972   #define MCAN_ILS_BOL_Assigned0 (0x0UL)             /*!< Interrupt assigned to interrupt line CORE0.                          */
55973   #define MCAN_ILS_BOL_Assigned1 (0x1UL)             /*!< Interrupt assigned to interrupt line CORE1.                          */
55974 
55975 /* WDIL @Bit 26 : Watchdog Interrupt Line */
55976   #define MCAN_ILS_WDIL_Pos (26UL)                   /*!< Position of WDIL field.                                              */
55977   #define MCAN_ILS_WDIL_Msk (0x1UL << MCAN_ILS_WDIL_Pos) /*!< Bit mask of WDIL field.                                          */
55978   #define MCAN_ILS_WDIL_Min (0x0UL)                  /*!< Min enumerator value of WDIL field.                                  */
55979   #define MCAN_ILS_WDIL_Max (0x1UL)                  /*!< Max enumerator value of WDIL field.                                  */
55980   #define MCAN_ILS_WDIL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55981   #define MCAN_ILS_WDIL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55982 
55983 /* PEAL @Bit 27 : Protocol Error in Arbitration Phase Line */
55984   #define MCAN_ILS_PEAL_Pos (27UL)                   /*!< Position of PEAL field.                                              */
55985   #define MCAN_ILS_PEAL_Msk (0x1UL << MCAN_ILS_PEAL_Pos) /*!< Bit mask of PEAL field.                                          */
55986   #define MCAN_ILS_PEAL_Min (0x0UL)                  /*!< Min enumerator value of PEAL field.                                  */
55987   #define MCAN_ILS_PEAL_Max (0x1UL)                  /*!< Max enumerator value of PEAL field.                                  */
55988   #define MCAN_ILS_PEAL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55989   #define MCAN_ILS_PEAL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55990 
55991 /* PEDL @Bit 28 : Protocol Error in Data Phase Line */
55992   #define MCAN_ILS_PEDL_Pos (28UL)                   /*!< Position of PEDL field.                                              */
55993   #define MCAN_ILS_PEDL_Msk (0x1UL << MCAN_ILS_PEDL_Pos) /*!< Bit mask of PEDL field.                                          */
55994   #define MCAN_ILS_PEDL_Min (0x0UL)                  /*!< Min enumerator value of PEDL field.                                  */
55995   #define MCAN_ILS_PEDL_Max (0x1UL)                  /*!< Max enumerator value of PEDL field.                                  */
55996   #define MCAN_ILS_PEDL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
55997   #define MCAN_ILS_PEDL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
55998 
55999 /* ARAL @Bit 29 : Access to Reserved Address Line */
56000   #define MCAN_ILS_ARAL_Pos (29UL)                   /*!< Position of ARAL field.                                              */
56001   #define MCAN_ILS_ARAL_Msk (0x1UL << MCAN_ILS_ARAL_Pos) /*!< Bit mask of ARAL field.                                          */
56002   #define MCAN_ILS_ARAL_Min (0x0UL)                  /*!< Min enumerator value of ARAL field.                                  */
56003   #define MCAN_ILS_ARAL_Max (0x1UL)                  /*!< Max enumerator value of ARAL field.                                  */
56004   #define MCAN_ILS_ARAL_Assigned0 (0x0UL)            /*!< Interrupt assigned to interrupt line CORE0.                          */
56005   #define MCAN_ILS_ARAL_Assigned1 (0x1UL)            /*!< Interrupt assigned to interrupt line CORE1.                          */
56006 
56007 
56008 /* MCAN_ILE: Interrupt Line Enable */
56009   #define MCAN_ILE_ResetValue (0x00000000UL)         /*!< Reset value of ILE register.                                         */
56010 
56011 /* EINT0 @Bit 0 : Enable Interrupt Line 0 */
56012   #define MCAN_ILE_EINT0_Pos (0UL)                   /*!< Position of EINT0 field.                                             */
56013   #define MCAN_ILE_EINT0_Msk (0x1UL << MCAN_ILE_EINT0_Pos) /*!< Bit mask of EINT0 field.                                       */
56014   #define MCAN_ILE_EINT0_Min (0x0UL)                 /*!< Min enumerator value of EINT0 field.                                 */
56015   #define MCAN_ILE_EINT0_Max (0x1UL)                 /*!< Max enumerator value of EINT0 field.                                 */
56016   #define MCAN_ILE_EINT0_Disable (0x0UL)             /*!< Interrupt line CORE0 disabled.                                       */
56017   #define MCAN_ILE_EINT0_Enable (0x1UL)              /*!< Interrupt line CORE0 enabled.                                        */
56018 
56019 /* EINT1 @Bit 1 : Enable Interrupt Line 1 */
56020   #define MCAN_ILE_EINT1_Pos (1UL)                   /*!< Position of EINT1 field.                                             */
56021   #define MCAN_ILE_EINT1_Msk (0x1UL << MCAN_ILE_EINT1_Pos) /*!< Bit mask of EINT1 field.                                       */
56022   #define MCAN_ILE_EINT1_Min (0x0UL)                 /*!< Min enumerator value of EINT1 field.                                 */
56023   #define MCAN_ILE_EINT1_Max (0x1UL)                 /*!< Max enumerator value of EINT1 field.                                 */
56024   #define MCAN_ILE_EINT1_Disable (0x0UL)             /*!< Interrupt line CORE1 disabled.                                       */
56025   #define MCAN_ILE_EINT1_Enable (0x1UL)              /*!< Interrupt line CORE1 enabled.                                        */
56026 
56027 
56028 /* MCAN_GFC: Global Filter Configuration */
56029   #define MCAN_GFC_ResetValue (0x00000000UL)         /*!< Reset value of GFC register.                                         */
56030 
56031 /* RRFE @Bit 0 : Reject Remote Frames Extended */
56032   #define MCAN_GFC_RRFE_Pos (0UL)                    /*!< Position of RRFE field.                                              */
56033   #define MCAN_GFC_RRFE_Msk (0x1UL << MCAN_GFC_RRFE_Pos) /*!< Bit mask of RRFE field.                                          */
56034   #define MCAN_GFC_RRFE_Min (0x0UL)                  /*!< Min enumerator value of RRFE field.                                  */
56035   #define MCAN_GFC_RRFE_Max (0x1UL)                  /*!< Max enumerator value of RRFE field.                                  */
56036   #define MCAN_GFC_RRFE_Filter (0x0UL)               /*!< Filter remote frames with 29-bit extended IDs.                       */
56037   #define MCAN_GFC_RRFE_Reject (0x1UL)               /*!< Reject all remote frames with 29-bit extended IDs.                   */
56038 
56039 /* RRFS @Bit 1 : Reject Remote Frames Standard */
56040   #define MCAN_GFC_RRFS_Pos (1UL)                    /*!< Position of RRFS field.                                              */
56041   #define MCAN_GFC_RRFS_Msk (0x1UL << MCAN_GFC_RRFS_Pos) /*!< Bit mask of RRFS field.                                          */
56042   #define MCAN_GFC_RRFS_Min (0x0UL)                  /*!< Min enumerator value of RRFS field.                                  */
56043   #define MCAN_GFC_RRFS_Max (0x1UL)                  /*!< Max enumerator value of RRFS field.                                  */
56044   #define MCAN_GFC_RRFS_Filter (0x0UL)               /*!< Filter remote frames with 11-bit standard IDs.                       */
56045   #define MCAN_GFC_RRFS_Reject (0x1UL)               /*!< Reject all remote frames with 11-bit standard IDs.                   */
56046 
56047 /* ANFE @Bits 2..3 : Accept Non-matching Frames Extended */
56048   #define MCAN_GFC_ANFE_Pos (2UL)                    /*!< Position of ANFE field.                                              */
56049   #define MCAN_GFC_ANFE_Msk (0x3UL << MCAN_GFC_ANFE_Pos) /*!< Bit mask of ANFE field.                                          */
56050   #define MCAN_GFC_ANFE_Min (0x0UL)                  /*!< Min enumerator value of ANFE field.                                  */
56051   #define MCAN_GFC_ANFE_Max (0x3UL)                  /*!< Max enumerator value of ANFE field.                                  */
56052   #define MCAN_GFC_ANFE_Accept0 (0x0UL)              /*!< Accept in Rx FIFO 0.                                                 */
56053   #define MCAN_GFC_ANFE_Accept1 (0x1UL)              /*!< Accept in Rx FIFO 1.                                                 */
56054   #define MCAN_GFC_ANFE_Reject0 (0x2UL)              /*!< Reject in both Rx FIFOs.                                             */
56055   #define MCAN_GFC_ANFE_Reject1 (0x3UL)              /*!< Reject in both Rx FIFOs.                                             */
56056 
56057 /* ANFS @Bits 4..5 : (unspecified) */
56058   #define MCAN_GFC_ANFS_Pos (4UL)                    /*!< Position of ANFS field.                                              */
56059   #define MCAN_GFC_ANFS_Msk (0x3UL << MCAN_GFC_ANFS_Pos) /*!< Bit mask of ANFS field.                                          */
56060   #define MCAN_GFC_ANFS_Min (0x0UL)                  /*!< Min enumerator value of ANFS field.                                  */
56061   #define MCAN_GFC_ANFS_Max (0x3UL)                  /*!< Max enumerator value of ANFS field.                                  */
56062   #define MCAN_GFC_ANFS_Accept0 (0x0UL)              /*!< Accept in Rx FIFO 0.                                                 */
56063   #define MCAN_GFC_ANFS_Accept1 (0x1UL)              /*!< Accept in Rx FIFO 1.                                                 */
56064   #define MCAN_GFC_ANFS_Reject0 (0x2UL)              /*!< Reject in both Rx FIFOs.                                             */
56065   #define MCAN_GFC_ANFS_Reject1 (0x3UL)              /*!< Reject in both Rx FIFOs.                                             */
56066 
56067 
56068 /* MCAN_SIDFC: Standard ID Filter Configuration */
56069   #define MCAN_SIDFC_ResetValue (0x00000000UL)       /*!< Reset value of SIDFC register.                                       */
56070 
56071 /* FLSSA @Bits 2..15 : Filter List Standard Start Address */
56072   #define MCAN_SIDFC_FLSSA_Pos (2UL)                 /*!< Position of FLSSA field.                                             */
56073   #define MCAN_SIDFC_FLSSA_Msk (0x3FFFUL << MCAN_SIDFC_FLSSA_Pos) /*!< Bit mask of FLSSA field.                                */
56074 
56075 /* LSS @Bits 16..23 : List Size Standard */
56076   #define MCAN_SIDFC_LSS_Pos (16UL)                  /*!< Position of LSS field.                                               */
56077   #define MCAN_SIDFC_LSS_Msk (0xFFUL << MCAN_SIDFC_LSS_Pos) /*!< Bit mask of LSS field.                                        */
56078 
56079 
56080 /* MCAN_XIDFC: Extended ID Filter Configuration */
56081   #define MCAN_XIDFC_ResetValue (0x00000000UL)       /*!< Reset value of XIDFC register.                                       */
56082 
56083 /* FLESA @Bits 2..15 : Filter List Extended Start Address */
56084   #define MCAN_XIDFC_FLESA_Pos (2UL)                 /*!< Position of FLESA field.                                             */
56085   #define MCAN_XIDFC_FLESA_Msk (0x3FFFUL << MCAN_XIDFC_FLESA_Pos) /*!< Bit mask of FLESA field.                                */
56086 
56087 /* LSE @Bits 16..22 : List Size Extended */
56088   #define MCAN_XIDFC_LSE_Pos (16UL)                  /*!< Position of LSE field.                                               */
56089   #define MCAN_XIDFC_LSE_Msk (0x7FUL << MCAN_XIDFC_LSE_Pos) /*!< Bit mask of LSE field.                                        */
56090 
56091 
56092 /* MCAN_XIDAM: Extended ID AND Mask */
56093   #define MCAN_XIDAM_ResetValue (0x00000000UL)       /*!< Reset value of XIDAM register.                                       */
56094 
56095 /* EIDM @Bits 0..28 : Extended ID Mask */
56096   #define MCAN_XIDAM_EIDM_Pos (0UL)                  /*!< Position of EIDM field.                                              */
56097   #define MCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << MCAN_XIDAM_EIDM_Pos) /*!< Bit mask of EIDM field.                               */
56098 
56099 
56100 /* MCAN_HPMS: High Priority Message Status */
56101   #define MCAN_HPMS_ResetValue (0x00000000UL)        /*!< Reset value of HPMS register.                                        */
56102 
56103 /* BIDX @Bits 0..5 : Buffer Index */
56104   #define MCAN_HPMS_BIDX_Pos (0UL)                   /*!< Position of BIDX field.                                              */
56105   #define MCAN_HPMS_BIDX_Msk (0x3FUL << MCAN_HPMS_BIDX_Pos) /*!< Bit mask of BIDX field.                                       */
56106 
56107 /* MSI @Bits 6..7 : Message Storage Indicator */
56108   #define MCAN_HPMS_MSI_Pos (6UL)                    /*!< Position of MSI field.                                               */
56109   #define MCAN_HPMS_MSI_Msk (0x3UL << MCAN_HPMS_MSI_Pos) /*!< Bit mask of MSI field.                                           */
56110   #define MCAN_HPMS_MSI_Min (0x0UL)                  /*!< Min enumerator value of MSI field.                                   */
56111   #define MCAN_HPMS_MSI_Max (0x3UL)                  /*!< Max enumerator value of MSI field.                                   */
56112   #define MCAN_HPMS_MSI_NotSelected (0x0UL)          /*!< No FIFO selected.                                                    */
56113   #define MCAN_HPMS_MSI_Lost (0x1UL)                 /*!< FIFO message lost.                                                   */
56114   #define MCAN_HPMS_MSI_Stored0 (0x2UL)              /*!< Message stored in FIFO 0.                                            */
56115   #define MCAN_HPMS_MSI_Stored1 (0x3UL)              /*!< Message stored in FIFO 1.                                            */
56116 
56117 /* FIDX @Bits 8..14 : Filter Index */
56118   #define MCAN_HPMS_FIDX_Pos (8UL)                   /*!< Position of FIDX field.                                              */
56119   #define MCAN_HPMS_FIDX_Msk (0x7FUL << MCAN_HPMS_FIDX_Pos) /*!< Bit mask of FIDX field.                                       */
56120 
56121 /* FLST @Bit 15 : Filter List */
56122   #define MCAN_HPMS_FLST_Pos (15UL)                  /*!< Position of FLST field.                                              */
56123   #define MCAN_HPMS_FLST_Msk (0x1UL << MCAN_HPMS_FLST_Pos) /*!< Bit mask of FLST field.                                        */
56124   #define MCAN_HPMS_FLST_Min (0x0UL)                 /*!< Min enumerator value of FLST field.                                  */
56125   #define MCAN_HPMS_FLST_Max (0x1UL)                 /*!< Max enumerator value of FLST field.                                  */
56126   #define MCAN_HPMS_FLST_Standard (0x0UL)            /*!< Standard Filter List.                                                */
56127   #define MCAN_HPMS_FLST_Extended (0x1UL)            /*!< Extended Filter List.                                                */
56128 
56129 
56130 /* MCAN_NDAT1: New Data 1 */
56131   #define MCAN_NDAT1_ResetValue (0x00000000UL)       /*!< Reset value of NDAT1 register.                                       */
56132 
56133 /* ND @Bits 0..31 : New Data */
56134   #define MCAN_NDAT1_ND_Pos (0UL)                    /*!< Position of ND field.                                                */
56135   #define MCAN_NDAT1_ND_Msk (0xFFFFFFFFUL << MCAN_NDAT1_ND_Pos) /*!< Bit mask of ND field.                                     */
56136   #define MCAN_NDAT1_ND_Min (0x0UL)                  /*!< Min enumerator value of ND field.                                    */
56137   #define MCAN_NDAT1_ND_Max (0x1UL)                  /*!< Max enumerator value of ND field.                                    */
56138   #define MCAN_NDAT1_ND_NotUpdated (0x00000000UL)    /*!< Rx Buffer not updated.                                               */
56139   #define MCAN_NDAT1_ND_Updated (0x00000001UL)       /*!< Rx Buffer updated from new message.                                  */
56140 
56141 
56142 /* MCAN_NDAT2: New Data 2 */
56143   #define MCAN_NDAT2_ResetValue (0x00000000UL)       /*!< Reset value of NDAT2 register.                                       */
56144 
56145 /* ND @Bits 0..31 : New Data */
56146   #define MCAN_NDAT2_ND_Pos (0UL)                    /*!< Position of ND field.                                                */
56147   #define MCAN_NDAT2_ND_Msk (0xFFFFFFFFUL << MCAN_NDAT2_ND_Pos) /*!< Bit mask of ND field.                                     */
56148   #define MCAN_NDAT2_ND_Min (0x0UL)                  /*!< Min enumerator value of ND field.                                    */
56149   #define MCAN_NDAT2_ND_Max (0x1UL)                  /*!< Max enumerator value of ND field.                                    */
56150   #define MCAN_NDAT2_ND_NotUpdated (0x00000000UL)    /*!< Rx Buffer not updated.                                               */
56151   #define MCAN_NDAT2_ND_Updated (0x00000001UL)       /*!< Rx Buffer updated from new message.                                  */
56152 
56153 
56154 /* MCAN_RXF0C: Rx FIFO 0 Configuration */
56155   #define MCAN_RXF0C_ResetValue (0x00000000UL)       /*!< Reset value of RXF0C register.                                       */
56156 
56157 /* F0SA @Bits 2..15 : Rx FIFO 0 Start Address */
56158   #define MCAN_RXF0C_F0SA_Pos (2UL)                  /*!< Position of F0SA field.                                              */
56159   #define MCAN_RXF0C_F0SA_Msk (0x3FFFUL << MCAN_RXF0C_F0SA_Pos) /*!< Bit mask of F0SA field.                                   */
56160 
56161 /* F0S @Bits 16..22 : Rx FIFO 0 Size */
56162   #define MCAN_RXF0C_F0S_Pos (16UL)                  /*!< Position of F0S field.                                               */
56163   #define MCAN_RXF0C_F0S_Msk (0x7FUL << MCAN_RXF0C_F0S_Pos) /*!< Bit mask of F0S field.                                        */
56164 
56165 /* F0WM @Bits 24..30 : Rx FIFO 0 Watermark */
56166   #define MCAN_RXF0C_F0WM_Pos (24UL)                 /*!< Position of F0WM field.                                              */
56167   #define MCAN_RXF0C_F0WM_Msk (0x7FUL << MCAN_RXF0C_F0WM_Pos) /*!< Bit mask of F0WM field.                                     */
56168 
56169 /* F0OM @Bit 31 : FIFO 0 Operation Mode */
56170   #define MCAN_RXF0C_F0OM_Pos (31UL)                 /*!< Position of F0OM field.                                              */
56171   #define MCAN_RXF0C_F0OM_Msk (0x1UL << MCAN_RXF0C_F0OM_Pos) /*!< Bit mask of F0OM field.                                      */
56172   #define MCAN_RXF0C_F0OM_Min (0x0UL)                /*!< Min enumerator value of F0OM field.                                  */
56173   #define MCAN_RXF0C_F0OM_Max (0x1UL)                /*!< Max enumerator value of F0OM field.                                  */
56174   #define MCAN_RXF0C_F0OM_Blocking (0x0UL)           /*!< FIFO 0 blocking mode.                                                */
56175   #define MCAN_RXF0C_F0OM_Overwrite (0x1UL)          /*!< FIFO 0 overwrite mode.                                               */
56176 
56177 
56178 /* MCAN_RXF0S: Rx FIFO 0 Status */
56179   #define MCAN_RXF0S_ResetValue (0x00000000UL)       /*!< Reset value of RXF0S register.                                       */
56180 
56181 /* F0FL @Bits 0..6 : Rx FIFO 0 Fill Leve */
56182   #define MCAN_RXF0S_F0FL_Pos (0UL)                  /*!< Position of F0FL field.                                              */
56183   #define MCAN_RXF0S_F0FL_Msk (0x7FUL << MCAN_RXF0S_F0FL_Pos) /*!< Bit mask of F0FL field.                                     */
56184 
56185 /* F0GI @Bits 8..13 : Rx FIFO 0 Get Index */
56186   #define MCAN_RXF0S_F0GI_Pos (8UL)                  /*!< Position of F0GI field.                                              */
56187   #define MCAN_RXF0S_F0GI_Msk (0x3FUL << MCAN_RXF0S_F0GI_Pos) /*!< Bit mask of F0GI field.                                     */
56188 
56189 /* F0PI @Bits 16..21 : Rx FIFO 0 Put Index */
56190   #define MCAN_RXF0S_F0PI_Pos (16UL)                 /*!< Position of F0PI field.                                              */
56191   #define MCAN_RXF0S_F0PI_Msk (0x3FUL << MCAN_RXF0S_F0PI_Pos) /*!< Bit mask of F0PI field.                                     */
56192 
56193 /* F0F @Bit 24 : Rx FIFO 0 Full */
56194   #define MCAN_RXF0S_F0F_Pos (24UL)                  /*!< Position of F0F field.                                               */
56195   #define MCAN_RXF0S_F0F_Msk (0x1UL << MCAN_RXF0S_F0F_Pos) /*!< Bit mask of F0F field.                                         */
56196   #define MCAN_RXF0S_F0F_Min (0x0UL)                 /*!< Min enumerator value of F0F field.                                   */
56197   #define MCAN_RXF0S_F0F_Max (0x1UL)                 /*!< Max enumerator value of F0F field.                                   */
56198   #define MCAN_RXF0S_F0F_NotFull (0x0UL)             /*!< Rx FIFO 0 not full.                                                  */
56199   #define MCAN_RXF0S_F0F_Full (0x1UL)                /*!< Rx FIFO 0 full.                                                      */
56200 
56201 /* RF0L @Bit 25 : Rx FIFO 0 Message Lost */
56202   #define MCAN_RXF0S_RF0L_Pos (25UL)                 /*!< Position of RF0L field.                                              */
56203   #define MCAN_RXF0S_RF0L_Msk (0x1UL << MCAN_RXF0S_RF0L_Pos) /*!< Bit mask of RF0L field.                                      */
56204   #define MCAN_RXF0S_RF0L_Min (0x0UL)                /*!< Min enumerator value of RF0L field.                                  */
56205   #define MCAN_RXF0S_RF0L_Max (0x1UL)                /*!< Max enumerator value of RF0L field.                                  */
56206   #define MCAN_RXF0S_RF0L_NotLost (0x0UL)            /*!< No Rx FIFO 0 message lost.                                           */
56207   #define MCAN_RXF0S_RF0L_Lost (0x1UL)               /*!< Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of
56208                                                           size zero.*/
56209 
56210 
56211 /* MCAN_RXF0A: Rx FIFO 0 Acknowledge */
56212   #define MCAN_RXF0A_ResetValue (0x00000000UL)       /*!< Reset value of RXF0A register.                                       */
56213 
56214 /* F0AI @Bits 0..5 : Rx FIFO 0 Acknowledge Index */
56215   #define MCAN_RXF0A_F0AI_Pos (0UL)                  /*!< Position of F0AI field.                                              */
56216   #define MCAN_RXF0A_F0AI_Msk (0x3FUL << MCAN_RXF0A_F0AI_Pos) /*!< Bit mask of F0AI field.                                     */
56217 
56218 
56219 /* MCAN_RXBC: Rx Buffer Configuration */
56220   #define MCAN_RXBC_ResetValue (0x00000000UL)        /*!< Reset value of RXBC register.                                        */
56221 
56222 /* RBSA @Bits 2..15 : Rx Buffer Start Address */
56223   #define MCAN_RXBC_RBSA_Pos (2UL)                   /*!< Position of RBSA field.                                              */
56224   #define MCAN_RXBC_RBSA_Msk (0x3FFFUL << MCAN_RXBC_RBSA_Pos) /*!< Bit mask of RBSA field.                                     */
56225 
56226 
56227 /* MCAN_RXF1C: Rx FIFO 1 Configuration */
56228   #define MCAN_RXF1C_ResetValue (0x00000000UL)       /*!< Reset value of RXF1C register.                                       */
56229 
56230 /* F1SA @Bits 2..15 : Rx FIFO 1 Start Address */
56231   #define MCAN_RXF1C_F1SA_Pos (2UL)                  /*!< Position of F1SA field.                                              */
56232   #define MCAN_RXF1C_F1SA_Msk (0x3FFFUL << MCAN_RXF1C_F1SA_Pos) /*!< Bit mask of F1SA field.                                   */
56233 
56234 /* F1S @Bits 16..22 : Rx FIFO 1 Size */
56235   #define MCAN_RXF1C_F1S_Pos (16UL)                  /*!< Position of F1S field.                                               */
56236   #define MCAN_RXF1C_F1S_Msk (0x7FUL << MCAN_RXF1C_F1S_Pos) /*!< Bit mask of F1S field.                                        */
56237 
56238 /* F1WM @Bits 24..30 : Rx FIFO 1 Watermark */
56239   #define MCAN_RXF1C_F1WM_Pos (24UL)                 /*!< Position of F1WM field.                                              */
56240   #define MCAN_RXF1C_F1WM_Msk (0x7FUL << MCAN_RXF1C_F1WM_Pos) /*!< Bit mask of F1WM field.                                     */
56241 
56242 /* F1OM @Bit 31 : FIFO 1 Operation Mode */
56243   #define MCAN_RXF1C_F1OM_Pos (31UL)                 /*!< Position of F1OM field.                                              */
56244   #define MCAN_RXF1C_F1OM_Msk (0x1UL << MCAN_RXF1C_F1OM_Pos) /*!< Bit mask of F1OM field.                                      */
56245   #define MCAN_RXF1C_F1OM_Min (0x0UL)                /*!< Min enumerator value of F1OM field.                                  */
56246   #define MCAN_RXF1C_F1OM_Max (0x1UL)                /*!< Max enumerator value of F1OM field.                                  */
56247   #define MCAN_RXF1C_F1OM_BlockingMode (0x0UL)       /*!< FIFO 1 blocking mode                                                 */
56248   #define MCAN_RXF1C_F1OM_OwerwriteMode (0x1UL)      /*!< FIFO 1 overwrite mode                                                */
56249 
56250 
56251 /* MCAN_RXF1S: Rx FIFO 1 Status */
56252   #define MCAN_RXF1S_ResetValue (0x00000000UL)       /*!< Reset value of RXF1S register.                                       */
56253 
56254 /* F1FL @Bits 0..6 : Rx FIFO 1 Fill Level */
56255   #define MCAN_RXF1S_F1FL_Pos (0UL)                  /*!< Position of F1FL field.                                              */
56256   #define MCAN_RXF1S_F1FL_Msk (0x7FUL << MCAN_RXF1S_F1FL_Pos) /*!< Bit mask of F1FL field.                                     */
56257 
56258 /* F1GI @Bits 8..13 : Rx FIFO 1 Get Index */
56259   #define MCAN_RXF1S_F1GI_Pos (8UL)                  /*!< Position of F1GI field.                                              */
56260   #define MCAN_RXF1S_F1GI_Msk (0x3FUL << MCAN_RXF1S_F1GI_Pos) /*!< Bit mask of F1GI field.                                     */
56261 
56262 /* F1PI @Bits 16..21 : Rx FIFO 1 Put Index */
56263   #define MCAN_RXF1S_F1PI_Pos (16UL)                 /*!< Position of F1PI field.                                              */
56264   #define MCAN_RXF1S_F1PI_Msk (0x3FUL << MCAN_RXF1S_F1PI_Pos) /*!< Bit mask of F1PI field.                                     */
56265 
56266 /* F1F @Bit 24 : Rx FIFO 1 Full */
56267   #define MCAN_RXF1S_F1F_Pos (24UL)                  /*!< Position of F1F field.                                               */
56268   #define MCAN_RXF1S_F1F_Msk (0x1UL << MCAN_RXF1S_F1F_Pos) /*!< Bit mask of F1F field.                                         */
56269   #define MCAN_RXF1S_F1F_Min (0x0UL)                 /*!< Min enumerator value of F1F field.                                   */
56270   #define MCAN_RXF1S_F1F_Max (0x1UL)                 /*!< Max enumerator value of F1F field.                                   */
56271   #define MCAN_RXF1S_F1F_NotFull (0x0UL)             /*!< Rx FIFO 1 not full                                                   */
56272   #define MCAN_RXF1S_F1F_Full (0x1UL)                /*!< Rx FIFO 1 full                                                       */
56273 
56274 /* RF1L @Bit 25 : Rx FIFO 1 Message Lost */
56275   #define MCAN_RXF1S_RF1L_Pos (25UL)                 /*!< Position of RF1L field.                                              */
56276   #define MCAN_RXF1S_RF1L_Msk (0x1UL << MCAN_RXF1S_RF1L_Pos) /*!< Bit mask of RF1L field.                                      */
56277   #define MCAN_RXF1S_RF1L_Min (0x0UL)                /*!< Min enumerator value of RF1L field.                                  */
56278   #define MCAN_RXF1S_RF1L_Max (0x1UL)                /*!< Max enumerator value of RF1L field.                                  */
56279   #define MCAN_RXF1S_RF1L_NoMessageLost (0x0UL)      /*!< No Rx FIFO 1 message lost                                            */
56280   #define MCAN_RXF1S_RF1L_MessageLost (0x1UL)        /*!< Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of
56281                                                           size zero*/
56282 
56283 /* DMS @Bits 30..31 : Debug Message Status */
56284   #define MCAN_RXF1S_DMS_Pos (30UL)                  /*!< Position of DMS field.                                               */
56285   #define MCAN_RXF1S_DMS_Msk (0x3UL << MCAN_RXF1S_DMS_Pos) /*!< Bit mask of DMS field.                                         */
56286   #define MCAN_RXF1S_DMS_Min (0x0UL)                 /*!< Min enumerator value of DMS field.                                   */
56287   #define MCAN_RXF1S_DMS_Max (0x3UL)                 /*!< Max enumerator value of DMS field.                                   */
56288   #define MCAN_RXF1S_DMS_Idle (0x0UL)                /*!< Idle state, wait for reception of debug messages, DMA request is
56289                                                           cleared*/
56290   #define MCAN_RXF1S_DMS_ReceivedMesA (0x1UL)        /*!< Debug message A received                                             */
56291   #define MCAN_RXF1S_DMS_ReceivedMesAB (0x2UL)       /*!< Debug messages A, B received                                         */
56292   #define MCAN_RXF1S_DMS_ReceivedMesABC (0x3UL)      /*!< Debug messages A, B, C received, DMA request is set                  */
56293 
56294 
56295 /* MCAN_RXF1A: Rx FIFO 1 Acknowledge */
56296   #define MCAN_RXF1A_ResetValue (0x00000000UL)       /*!< Reset value of RXF1A register.                                       */
56297 
56298 /* F1AI @Bits 0..5 : Rx FIFO 1 Acknowledge Index */
56299   #define MCAN_RXF1A_F1AI_Pos (0UL)                  /*!< Position of F1AI field.                                              */
56300   #define MCAN_RXF1A_F1AI_Msk (0x3FUL << MCAN_RXF1A_F1AI_Pos) /*!< Bit mask of F1AI field.                                     */
56301 
56302 
56303 /* MCAN_RXESC: Rx Buffer / FIFO Element Size Configuration */
56304   #define MCAN_RXESC_ResetValue (0x00000000UL)       /*!< Reset value of RXESC register.                                       */
56305 
56306 /* F0DS @Bits 0..2 : Rx FIFO 0 Data Field Size */
56307   #define MCAN_RXESC_F0DS_Pos (0UL)                  /*!< Position of F0DS field.                                              */
56308   #define MCAN_RXESC_F0DS_Msk (0x7UL << MCAN_RXESC_F0DS_Pos) /*!< Bit mask of F0DS field.                                      */
56309   #define MCAN_RXESC_F0DS_Min (0x0UL)                /*!< Min enumerator value of F0DS field.                                  */
56310   #define MCAN_RXESC_F0DS_Max (0x7UL)                /*!< Max enumerator value of F0DS field.                                  */
56311   #define MCAN_RXESC_F0DS_DataField8B (0x0UL)        /*!< 8 byte data field                                                    */
56312   #define MCAN_RXESC_F0DS_DataField12B (0x1UL)       /*!< 12 byte data field                                                   */
56313   #define MCAN_RXESC_F0DS_DataField16B (0x2UL)       /*!< 16 byte data field                                                   */
56314   #define MCAN_RXESC_F0DS_DataField20B (0x3UL)       /*!< 20 byte data field                                                   */
56315   #define MCAN_RXESC_F0DS_DataField24B (0x4UL)       /*!< 24 byte data field                                                   */
56316   #define MCAN_RXESC_F0DS_DataField32B (0x5UL)       /*!< 32 byte data field                                                   */
56317   #define MCAN_RXESC_F0DS_DataField48B (0x6UL)       /*!< 48 byte data field                                                   */
56318   #define MCAN_RXESC_F0DS_DataField64B (0x7UL)       /*!< 64 byte data field                                                   */
56319 
56320 /* F1DS @Bits 4..6 : Rx FIFO 1 Data Field Size */
56321   #define MCAN_RXESC_F1DS_Pos (4UL)                  /*!< Position of F1DS field.                                              */
56322   #define MCAN_RXESC_F1DS_Msk (0x7UL << MCAN_RXESC_F1DS_Pos) /*!< Bit mask of F1DS field.                                      */
56323   #define MCAN_RXESC_F1DS_Min (0x0UL)                /*!< Min enumerator value of F1DS field.                                  */
56324   #define MCAN_RXESC_F1DS_Max (0x7UL)                /*!< Max enumerator value of F1DS field.                                  */
56325   #define MCAN_RXESC_F1DS_DataField8B (0x0UL)        /*!< 8 byte data field                                                    */
56326   #define MCAN_RXESC_F1DS_DataField12B (0x1UL)       /*!< 12 byte data field                                                   */
56327   #define MCAN_RXESC_F1DS_DataField16B (0x2UL)       /*!< 16 byte data field                                                   */
56328   #define MCAN_RXESC_F1DS_DataField20B (0x3UL)       /*!< 20 byte data field                                                   */
56329   #define MCAN_RXESC_F1DS_DataField24B (0x4UL)       /*!< 24 byte data field                                                   */
56330   #define MCAN_RXESC_F1DS_DataField32B (0x5UL)       /*!< 32 byte data field                                                   */
56331   #define MCAN_RXESC_F1DS_DataField48B (0x6UL)       /*!< 48 byte data field                                                   */
56332   #define MCAN_RXESC_F1DS_DataField64B (0x7UL)       /*!< 64 byte data field                                                   */
56333 
56334 /* RBDS @Bits 8..10 : Rx Buffer Data Field Size */
56335   #define MCAN_RXESC_RBDS_Pos (8UL)                  /*!< Position of RBDS field.                                              */
56336   #define MCAN_RXESC_RBDS_Msk (0x7UL << MCAN_RXESC_RBDS_Pos) /*!< Bit mask of RBDS field.                                      */
56337   #define MCAN_RXESC_RBDS_Min (0x0UL)                /*!< Min enumerator value of RBDS field.                                  */
56338   #define MCAN_RXESC_RBDS_Max (0x7UL)                /*!< Max enumerator value of RBDS field.                                  */
56339   #define MCAN_RXESC_RBDS_DataField8B (0x0UL)        /*!< 8 byte data field                                                    */
56340   #define MCAN_RXESC_RBDS_DataField12B (0x1UL)       /*!< 12 byte data field                                                   */
56341   #define MCAN_RXESC_RBDS_DataField16B (0x2UL)       /*!< 16 byte data field                                                   */
56342   #define MCAN_RXESC_RBDS_DataField20B (0x3UL)       /*!< 20 byte data field                                                   */
56343   #define MCAN_RXESC_RBDS_DataField24B (0x4UL)       /*!< 24 byte data field                                                   */
56344   #define MCAN_RXESC_RBDS_DataField32B (0x5UL)       /*!< 32 byte data field                                                   */
56345   #define MCAN_RXESC_RBDS_DataField48B (0x6UL)       /*!< 48 byte data field                                                   */
56346   #define MCAN_RXESC_RBDS_DataField64B (0x7UL)       /*!< 64 byte data field                                                   */
56347 
56348 
56349 /* MCAN_TXBC: Tx Buffer Configuration */
56350   #define MCAN_TXBC_ResetValue (0x00000000UL)        /*!< Reset value of TXBC register.                                        */
56351 
56352 /* TBSA @Bits 2..15 : Tx Buffers Start Address */
56353   #define MCAN_TXBC_TBSA_Pos (2UL)                   /*!< Position of TBSA field.                                              */
56354   #define MCAN_TXBC_TBSA_Msk (0x3FFFUL << MCAN_TXBC_TBSA_Pos) /*!< Bit mask of TBSA field.                                     */
56355 
56356 /* NDTB @Bits 16..21 : Number of Dedicated Transmit Buffers */
56357   #define MCAN_TXBC_NDTB_Pos (16UL)                  /*!< Position of NDTB field.                                              */
56358   #define MCAN_TXBC_NDTB_Msk (0x3FUL << MCAN_TXBC_NDTB_Pos) /*!< Bit mask of NDTB field.                                       */
56359 
56360 /* TFQS @Bits 24..29 : Transmit FIFO/Queue Size */
56361   #define MCAN_TXBC_TFQS_Pos (24UL)                  /*!< Position of TFQS field.                                              */
56362   #define MCAN_TXBC_TFQS_Msk (0x3FUL << MCAN_TXBC_TFQS_Pos) /*!< Bit mask of TFQS field.                                       */
56363 
56364 /* TFQM @Bit 30 : Tx FIFO/Queue Mode */
56365   #define MCAN_TXBC_TFQM_Pos (30UL)                  /*!< Position of TFQM field.                                              */
56366   #define MCAN_TXBC_TFQM_Msk (0x1UL << MCAN_TXBC_TFQM_Pos) /*!< Bit mask of TFQM field.                                        */
56367   #define MCAN_TXBC_TFQM_Min (0x0UL)                 /*!< Min enumerator value of TFQM field.                                  */
56368   #define MCAN_TXBC_TFQM_Max (0x1UL)                 /*!< Max enumerator value of TFQM field.                                  */
56369   #define MCAN_TXBC_TFQM_TxFIFO (0x0UL)              /*!< Tx FIFO operation                                                    */
56370   #define MCAN_TXBC_TFQM_TxQueue (0x1UL)             /*!< Tx Queue operation                                                   */
56371 
56372 
56373 /* MCAN_TXFQS: Tx FIFO/Queue Status */
56374   #define MCAN_TXFQS_ResetValue (0x00000000UL)       /*!< Reset value of TXFQS register.                                       */
56375 
56376 /* TFFL @Bits 0..5 : Tx FIFO Free Level */
56377   #define MCAN_TXFQS_TFFL_Pos (0UL)                  /*!< Position of TFFL field.                                              */
56378   #define MCAN_TXFQS_TFFL_Msk (0x3FUL << MCAN_TXFQS_TFFL_Pos) /*!< Bit mask of TFFL field.                                     */
56379 
56380 /* TFGI @Bits 8..12 : Tx FIFO Get Index */
56381   #define MCAN_TXFQS_TFGI_Pos (8UL)                  /*!< Position of TFGI field.                                              */
56382   #define MCAN_TXFQS_TFGI_Msk (0x1FUL << MCAN_TXFQS_TFGI_Pos) /*!< Bit mask of TFGI field.                                     */
56383 
56384 /* TFQPI @Bits 16..20 : Tx FIFO/Queue Put Index */
56385   #define MCAN_TXFQS_TFQPI_Pos (16UL)                /*!< Position of TFQPI field.                                             */
56386   #define MCAN_TXFQS_TFQPI_Msk (0x1FUL << MCAN_TXFQS_TFQPI_Pos) /*!< Bit mask of TFQPI field.                                  */
56387 
56388 /* TFQF @Bit 21 : Tx FIFO/Queue Full */
56389   #define MCAN_TXFQS_TFQF_Pos (21UL)                 /*!< Position of TFQF field.                                              */
56390   #define MCAN_TXFQS_TFQF_Msk (0x1UL << MCAN_TXFQS_TFQF_Pos) /*!< Bit mask of TFQF field.                                      */
56391   #define MCAN_TXFQS_TFQF_Min (0x0UL)                /*!< Min enumerator value of TFQF field.                                  */
56392   #define MCAN_TXFQS_TFQF_Max (0x1UL)                /*!< Max enumerator value of TFQF field.                                  */
56393   #define MCAN_TXFQS_TFQF_NotFull (0x0UL)            /*!< Tx FIFO/Queue not full                                               */
56394   #define MCAN_TXFQS_TFQF_Full (0x1UL)               /*!< Tx FIFO/Queue full                                                   */
56395 
56396 
56397 /* MCAN_TXESC: Tx Buffer Element Size Configuration */
56398   #define MCAN_TXESC_ResetValue (0x00000000UL)       /*!< Reset value of TXESC register.                                       */
56399 
56400 /* TBDS @Bits 0..2 : Tx Buffer Data Field Size */
56401   #define MCAN_TXESC_TBDS_Pos (0UL)                  /*!< Position of TBDS field.                                              */
56402   #define MCAN_TXESC_TBDS_Msk (0x7UL << MCAN_TXESC_TBDS_Pos) /*!< Bit mask of TBDS field.                                      */
56403   #define MCAN_TXESC_TBDS_Min (0x0UL)                /*!< Min enumerator value of TBDS field.                                  */
56404   #define MCAN_TXESC_TBDS_Max (0x7UL)                /*!< Max enumerator value of TBDS field.                                  */
56405   #define MCAN_TXESC_TBDS_DataField8B (0x0UL)        /*!< 8 byte data field                                                    */
56406   #define MCAN_TXESC_TBDS_DataField12B (0x1UL)       /*!< 12 byte data field                                                   */
56407   #define MCAN_TXESC_TBDS_DataField16B (0x2UL)       /*!< 16 byte data field                                                   */
56408   #define MCAN_TXESC_TBDS_DataField20B (0x3UL)       /*!< 20 byte data field                                                   */
56409   #define MCAN_TXESC_TBDS_DataField24B (0x4UL)       /*!< 24 byte data field                                                   */
56410   #define MCAN_TXESC_TBDS_DataField32B (0x5UL)       /*!< 32 byte data field                                                   */
56411   #define MCAN_TXESC_TBDS_DataField48B (0x6UL)       /*!< 48 byte data field                                                   */
56412   #define MCAN_TXESC_TBDS_DataField64B (0x7UL)       /*!< 64 byte data field                                                   */
56413 
56414 
56415 /* MCAN_TXBRP: Tx Buffer Request Pending */
56416   #define MCAN_TXBRP_ResetValue (0x00000000UL)       /*!< Reset value of TXBRP register.                                       */
56417 
56418 /* TRP @Bits 0..31 : Transmission Request Pending */
56419   #define MCAN_TXBRP_TRP_Pos (0UL)                   /*!< Position of TRP field.                                               */
56420   #define MCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << MCAN_TXBRP_TRP_Pos) /*!< Bit mask of TRP field.                                  */
56421   #define MCAN_TXBRP_TRP_Min (0x0UL)                 /*!< Min enumerator value of TRP field.                                   */
56422   #define MCAN_TXBRP_TRP_Max (0x1UL)                 /*!< Max enumerator value of TRP field.                                   */
56423   #define MCAN_TXBRP_TRP_NoRequest (0x00000000UL)    /*!< No transmission request pending                                      */
56424   #define MCAN_TXBRP_TRP_Request (0x00000001UL)      /*!< Transmission request pending                                         */
56425 
56426 
56427 /* MCAN_TXBAR: Tx Buffer Add Request */
56428   #define MCAN_TXBAR_ResetValue (0x00000000UL)       /*!< Reset value of TXBAR register.                                       */
56429 
56430 /* AR @Bits 0..31 : Add Request */
56431   #define MCAN_TXBAR_AR_Pos (0UL)                    /*!< Position of AR field.                                                */
56432   #define MCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << MCAN_TXBAR_AR_Pos) /*!< Bit mask of AR field.                                     */
56433   #define MCAN_TXBAR_AR_Min (0x0UL)                  /*!< Min enumerator value of AR field.                                    */
56434   #define MCAN_TXBAR_AR_Max (0x1UL)                  /*!< Max enumerator value of AR field.                                    */
56435   #define MCAN_TXBAR_AR_NoRequest (0x00000000UL)     /*!< No transmission request added                                        */
56436   #define MCAN_TXBAR_AR_Request (0x00000001UL)       /*!< Transmission requested added                                         */
56437 
56438 
56439 /* MCAN_TXBCR: Tx Buffer Cancellation Request */
56440   #define MCAN_TXBCR_ResetValue (0x00000000UL)       /*!< Reset value of TXBCR register.                                       */
56441 
56442 /* CR @Bits 0..31 : Cancellation Request */
56443   #define MCAN_TXBCR_CR_Pos (0UL)                    /*!< Position of CR field.                                                */
56444   #define MCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << MCAN_TXBCR_CR_Pos) /*!< Bit mask of CR field.                                     */
56445   #define MCAN_TXBCR_CR_Min (0x0UL)                  /*!< Min enumerator value of CR field.                                    */
56446   #define MCAN_TXBCR_CR_Max (0x1UL)                  /*!< Max enumerator value of CR field.                                    */
56447   #define MCAN_TXBCR_CR_NoCancellation (0x00000000UL) /*!< No cancellation pending                                             */
56448   #define MCAN_TXBCR_CR_Cancellation (0x00000001UL)  /*!< Cancellation pending                                                 */
56449 
56450 
56451 /* MCAN_TXBTO: Tx Buffer Transmission Occurred */
56452   #define MCAN_TXBTO_ResetValue (0x00000000UL)       /*!< Reset value of TXBTO register.                                       */
56453 
56454 /* TO @Bits 0..31 : Transmission Occurred */
56455   #define MCAN_TXBTO_TO_Pos (0UL)                    /*!< Position of TO field.                                                */
56456   #define MCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << MCAN_TXBTO_TO_Pos) /*!< Bit mask of TO field.                                     */
56457   #define MCAN_TXBTO_TO_Min (0x0UL)                  /*!< Min enumerator value of TO field.                                    */
56458   #define MCAN_TXBTO_TO_Max (0x1UL)                  /*!< Max enumerator value of TO field.                                    */
56459   #define MCAN_TXBTO_TO_NoTransmittion (0x00000000UL) /*!< No transmission occurred                                            */
56460   #define MCAN_TXBTO_TO_Transmittion (0x00000001UL)  /*!< Transmission occurred                                                */
56461 
56462 
56463 /* MCAN_TXBCF: Tx Buffer Cancellation Finished */
56464   #define MCAN_TXBCF_ResetValue (0x00000000UL)       /*!< Reset value of TXBCF register.                                       */
56465 
56466 /* CF @Bits 0..31 : Cancellation Finished */
56467   #define MCAN_TXBCF_CF_Pos (0UL)                    /*!< Position of CF field.                                                */
56468   #define MCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << MCAN_TXBCF_CF_Pos) /*!< Bit mask of CF field.                                     */
56469   #define MCAN_TXBCF_CF_Min (0x0UL)                  /*!< Min enumerator value of CF field.                                    */
56470   #define MCAN_TXBCF_CF_Max (0x1UL)                  /*!< Max enumerator value of CF field.                                    */
56471   #define MCAN_TXBCF_CF_NoCancellation (0x00000000UL) /*!< No transmit buffer cancellation                                     */
56472   #define MCAN_TXBCF_CF_CancellationFinished (0x00000001UL) /*!< Transmit buffer cancellation finished                         */
56473 
56474 
56475 /* MCAN_TXBTIE: Tx Buffer Transmission Interrupt Enable */
56476   #define MCAN_TXBTIE_ResetValue (0x00000000UL)      /*!< Reset value of TXBTIE register.                                      */
56477 
56478 /* TIE @Bits 0..31 : Transmission Interrupt Enable */
56479   #define MCAN_TXBTIE_TIE_Pos (0UL)                  /*!< Position of TIE field.                                               */
56480   #define MCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << MCAN_TXBTIE_TIE_Pos) /*!< Bit mask of TIE field.                                */
56481   #define MCAN_TXBTIE_TIE_Min (0x0UL)                /*!< Min enumerator value of TIE field.                                   */
56482   #define MCAN_TXBTIE_TIE_Max (0x1UL)                /*!< Max enumerator value of TIE field.                                   */
56483   #define MCAN_TXBTIE_TIE_Disable (0x00000000UL)     /*!< Transmission interrupt disabled                                      */
56484   #define MCAN_TXBTIE_TIE_Enable (0x00000001UL)      /*!< Transmission interrupt enable                                        */
56485 
56486 
56487 /* MCAN_TXBCIE: Tx Buffer Cancellation Finished Interrupt Enable */
56488   #define MCAN_TXBCIE_ResetValue (0x00000000UL)      /*!< Reset value of TXBCIE register.                                      */
56489 
56490 /* CFIE @Bits 0..31 : Cancellation Finished Interrupt Enable */
56491   #define MCAN_TXBCIE_CFIE_Pos (0UL)                 /*!< Position of CFIE field.                                              */
56492   #define MCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << MCAN_TXBCIE_CFIE_Pos) /*!< Bit mask of CFIE field.                             */
56493   #define MCAN_TXBCIE_CFIE_Min (0x0UL)               /*!< Min enumerator value of CFIE field.                                  */
56494   #define MCAN_TXBCIE_CFIE_Max (0x1UL)               /*!< Max enumerator value of CFIE field.                                  */
56495   #define MCAN_TXBCIE_CFIE_Disable (0x00000000UL)    /*!< Cancellation finished interrupt disabled                             */
56496   #define MCAN_TXBCIE_CFIE_Enable (0x00000001UL)     /*!< Cancellation finished interrupt enabled                              */
56497 
56498 
56499 /* MCAN_TXEFC: Tx Event FIFO Configuration */
56500   #define MCAN_TXEFC_ResetValue (0x00000000UL)       /*!< Reset value of TXEFC register.                                       */
56501 
56502 /* EFSA @Bits 2..15 : Event FIFO Start Address */
56503   #define MCAN_TXEFC_EFSA_Pos (2UL)                  /*!< Position of EFSA field.                                              */
56504   #define MCAN_TXEFC_EFSA_Msk (0x3FFFUL << MCAN_TXEFC_EFSA_Pos) /*!< Bit mask of EFSA field.                                   */
56505 
56506 /* EFS @Bits 16..21 : Event FIFO Size */
56507   #define MCAN_TXEFC_EFS_Pos (16UL)                  /*!< Position of EFS field.                                               */
56508   #define MCAN_TXEFC_EFS_Msk (0x3FUL << MCAN_TXEFC_EFS_Pos) /*!< Bit mask of EFS field.                                        */
56509 
56510 /* EFWM @Bits 24..29 : Event FIFO Watermark */
56511   #define MCAN_TXEFC_EFWM_Pos (24UL)                 /*!< Position of EFWM field.                                              */
56512   #define MCAN_TXEFC_EFWM_Msk (0x3FUL << MCAN_TXEFC_EFWM_Pos) /*!< Bit mask of EFWM field.                                     */
56513 
56514 
56515 /* MCAN_TXEFS: Tx Event FIFO Status */
56516   #define MCAN_TXEFS_ResetValue (0x00000000UL)       /*!< Reset value of TXEFS register.                                       */
56517 
56518 /* EFFL @Bits 0..5 : Event FIFO Fill Level */
56519   #define MCAN_TXEFS_EFFL_Pos (0UL)                  /*!< Position of EFFL field.                                              */
56520   #define MCAN_TXEFS_EFFL_Msk (0x3FUL << MCAN_TXEFS_EFFL_Pos) /*!< Bit mask of EFFL field.                                     */
56521 
56522 /* EFGI @Bits 8..12 : Event FIFO Get Index */
56523   #define MCAN_TXEFS_EFGI_Pos (8UL)                  /*!< Position of EFGI field.                                              */
56524   #define MCAN_TXEFS_EFGI_Msk (0x1FUL << MCAN_TXEFS_EFGI_Pos) /*!< Bit mask of EFGI field.                                     */
56525 
56526 /* EFPI @Bits 16..20 : Event FIFO Put Index */
56527   #define MCAN_TXEFS_EFPI_Pos (16UL)                 /*!< Position of EFPI field.                                              */
56528   #define MCAN_TXEFS_EFPI_Msk (0x1FUL << MCAN_TXEFS_EFPI_Pos) /*!< Bit mask of EFPI field.                                     */
56529 
56530 /* EFF @Bit 24 : Event FIFO Full */
56531   #define MCAN_TXEFS_EFF_Pos (24UL)                  /*!< Position of EFF field.                                               */
56532   #define MCAN_TXEFS_EFF_Msk (0x1UL << MCAN_TXEFS_EFF_Pos) /*!< Bit mask of EFF field.                                         */
56533   #define MCAN_TXEFS_EFF_Min (0x0UL)                 /*!< Min enumerator value of EFF field.                                   */
56534   #define MCAN_TXEFS_EFF_Max (0x1UL)                 /*!< Max enumerator value of EFF field.                                   */
56535   #define MCAN_TXEFS_EFF_NotFull (0x0UL)             /*!< Tx Event FIFO not full                                               */
56536   #define MCAN_TXEFS_EFF_Full (0x1UL)                /*!< Tx Event FIFO full                                                   */
56537 
56538 /* TEFL @Bit 25 : Tx Event FIFO Element Lost */
56539   #define MCAN_TXEFS_TEFL_Pos (25UL)                 /*!< Position of TEFL field.                                              */
56540   #define MCAN_TXEFS_TEFL_Msk (0x1UL << MCAN_TXEFS_TEFL_Pos) /*!< Bit mask of TEFL field.                                      */
56541   #define MCAN_TXEFS_TEFL_Min (0x0UL)                /*!< Min enumerator value of TEFL field.                                  */
56542   #define MCAN_TXEFS_TEFL_Max (0x1UL)                /*!< Max enumerator value of TEFL field.                                  */
56543   #define MCAN_TXEFS_TEFL_NotLost (0x0UL)            /*!< No Tx Event FIFO element lost                                        */
56544   #define MCAN_TXEFS_TEFL_Lost (0x1UL)               /*!< Tx Event FIFO element lost, also set after wr ite attempt to Tx Event
56545                                                           FIFO of siz e zero.*/
56546 
56547 
56548 /* MCAN_TXEFA: Tx Event FIFO Acknowledge */
56549   #define MCAN_TXEFA_ResetValue (0x00000000UL)       /*!< Reset value of TXEFA register.                                       */
56550 
56551 /* EFAI @Bits 0..4 : Event FIFO Acknowledge Index */
56552   #define MCAN_TXEFA_EFAI_Pos (0UL)                  /*!< Position of EFAI field.                                              */
56553   #define MCAN_TXEFA_EFAI_Msk (0x1FUL << MCAN_TXEFA_EFAI_Pos) /*!< Bit mask of EFAI field.                                     */
56554 
56555 
56556 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
56557 
56558 /* =========================================================================================================================== */
56559 /* ================                                          MEMCONF                                          ================ */
56560 /* =========================================================================================================================== */
56561 
56562 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
56563 
56564 /* ================================================== Struct MEMCONF_POWER =================================================== */
56565 /**
56566   * @brief POWER [MEMCONF_POWER] (unspecified)
56567   */
56568 typedef struct {
56569   __IOM uint32_t  CONTROL;                           /*!< (@ 0x00000000) Control memory block power.                           */
56570   __IM  uint32_t  RESERVED;
56571   __IOM uint32_t  RET;                               /*!< (@ 0x00000008) RAM retention for RAM [n].                            */
56572   __IOM uint32_t  RET2;                              /*!< (@ 0x0000000C) RAM retention for the second bank in the RAM block    */
56573 } NRF_MEMCONF_POWER_Type;                            /*!< Size = 16 (0x010)                                                    */
56574   #define MEMCONF_POWER_MaxCount (2UL)               /*!< Size of POWER[2] array.                                              */
56575   #define MEMCONF_POWER_MaxIndex (1UL)               /*!< Max index of POWER[2] array.                                         */
56576   #define MEMCONF_POWER_MinIndex (0UL)               /*!< Min index of POWER[2] array.                                         */
56577 
56578 /* MEMCONF_POWER_CONTROL: Control memory block power. */
56579   #define MEMCONF_POWER_CONTROL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONTROL register.                                */
56580 
56581 /* MEM0 @Bit 0 : Keep the memory block MEM[0] on or off when in System ON mode. */
56582   #define MEMCONF_POWER_CONTROL_MEM0_Pos (0UL)       /*!< Position of MEM0 field.                                              */
56583   #define MEMCONF_POWER_CONTROL_MEM0_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM0_Pos) /*!< Bit mask of MEM0 field.                */
56584   #define MEMCONF_POWER_CONTROL_MEM0_Min (0x0UL)     /*!< Min enumerator value of MEM0 field.                                  */
56585   #define MEMCONF_POWER_CONTROL_MEM0_Max (0x1UL)     /*!< Max enumerator value of MEM0 field.                                  */
56586   #define MEMCONF_POWER_CONTROL_MEM0_Off (0x0UL)     /*!< Power down                                                           */
56587   #define MEMCONF_POWER_CONTROL_MEM0_On (0x1UL)      /*!< Power up                                                             */
56588 
56589 /* MEM1 @Bit 1 : Keep the memory block MEM[1] on or off when in System ON mode. */
56590   #define MEMCONF_POWER_CONTROL_MEM1_Pos (1UL)       /*!< Position of MEM1 field.                                              */
56591   #define MEMCONF_POWER_CONTROL_MEM1_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM1_Pos) /*!< Bit mask of MEM1 field.                */
56592   #define MEMCONF_POWER_CONTROL_MEM1_Min (0x0UL)     /*!< Min enumerator value of MEM1 field.                                  */
56593   #define MEMCONF_POWER_CONTROL_MEM1_Max (0x1UL)     /*!< Max enumerator value of MEM1 field.                                  */
56594   #define MEMCONF_POWER_CONTROL_MEM1_Off (0x0UL)     /*!< Power down                                                           */
56595   #define MEMCONF_POWER_CONTROL_MEM1_On (0x1UL)      /*!< Power up                                                             */
56596 
56597 /* MEM2 @Bit 2 : Keep the memory block MEM[2] on or off when in System ON mode. */
56598   #define MEMCONF_POWER_CONTROL_MEM2_Pos (2UL)       /*!< Position of MEM2 field.                                              */
56599   #define MEMCONF_POWER_CONTROL_MEM2_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM2_Pos) /*!< Bit mask of MEM2 field.                */
56600   #define MEMCONF_POWER_CONTROL_MEM2_Min (0x0UL)     /*!< Min enumerator value of MEM2 field.                                  */
56601   #define MEMCONF_POWER_CONTROL_MEM2_Max (0x1UL)     /*!< Max enumerator value of MEM2 field.                                  */
56602   #define MEMCONF_POWER_CONTROL_MEM2_Off (0x0UL)     /*!< Power down                                                           */
56603   #define MEMCONF_POWER_CONTROL_MEM2_On (0x1UL)      /*!< Power up                                                             */
56604 
56605 /* MEM3 @Bit 3 : Keep the memory block MEM[3] on or off when in System ON mode. */
56606   #define MEMCONF_POWER_CONTROL_MEM3_Pos (3UL)       /*!< Position of MEM3 field.                                              */
56607   #define MEMCONF_POWER_CONTROL_MEM3_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM3_Pos) /*!< Bit mask of MEM3 field.                */
56608   #define MEMCONF_POWER_CONTROL_MEM3_Min (0x0UL)     /*!< Min enumerator value of MEM3 field.                                  */
56609   #define MEMCONF_POWER_CONTROL_MEM3_Max (0x1UL)     /*!< Max enumerator value of MEM3 field.                                  */
56610   #define MEMCONF_POWER_CONTROL_MEM3_Off (0x0UL)     /*!< Power down                                                           */
56611   #define MEMCONF_POWER_CONTROL_MEM3_On (0x1UL)      /*!< Power up                                                             */
56612 
56613 /* MEM4 @Bit 4 : Keep the memory block MEM[4] on or off when in System ON mode. */
56614   #define MEMCONF_POWER_CONTROL_MEM4_Pos (4UL)       /*!< Position of MEM4 field.                                              */
56615   #define MEMCONF_POWER_CONTROL_MEM4_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM4_Pos) /*!< Bit mask of MEM4 field.                */
56616   #define MEMCONF_POWER_CONTROL_MEM4_Min (0x0UL)     /*!< Min enumerator value of MEM4 field.                                  */
56617   #define MEMCONF_POWER_CONTROL_MEM4_Max (0x1UL)     /*!< Max enumerator value of MEM4 field.                                  */
56618   #define MEMCONF_POWER_CONTROL_MEM4_Off (0x0UL)     /*!< Power down                                                           */
56619   #define MEMCONF_POWER_CONTROL_MEM4_On (0x1UL)      /*!< Power up                                                             */
56620 
56621 /* MEM5 @Bit 5 : Keep the memory block MEM[5] on or off when in System ON mode. */
56622   #define MEMCONF_POWER_CONTROL_MEM5_Pos (5UL)       /*!< Position of MEM5 field.                                              */
56623   #define MEMCONF_POWER_CONTROL_MEM5_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM5_Pos) /*!< Bit mask of MEM5 field.                */
56624   #define MEMCONF_POWER_CONTROL_MEM5_Min (0x0UL)     /*!< Min enumerator value of MEM5 field.                                  */
56625   #define MEMCONF_POWER_CONTROL_MEM5_Max (0x1UL)     /*!< Max enumerator value of MEM5 field.                                  */
56626   #define MEMCONF_POWER_CONTROL_MEM5_Off (0x0UL)     /*!< Power down                                                           */
56627   #define MEMCONF_POWER_CONTROL_MEM5_On (0x1UL)      /*!< Power up                                                             */
56628 
56629 /* MEM6 @Bit 6 : Keep the memory block MEM[6] on or off when in System ON mode. */
56630   #define MEMCONF_POWER_CONTROL_MEM6_Pos (6UL)       /*!< Position of MEM6 field.                                              */
56631   #define MEMCONF_POWER_CONTROL_MEM6_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM6_Pos) /*!< Bit mask of MEM6 field.                */
56632   #define MEMCONF_POWER_CONTROL_MEM6_Min (0x0UL)     /*!< Min enumerator value of MEM6 field.                                  */
56633   #define MEMCONF_POWER_CONTROL_MEM6_Max (0x1UL)     /*!< Max enumerator value of MEM6 field.                                  */
56634   #define MEMCONF_POWER_CONTROL_MEM6_Off (0x0UL)     /*!< Power down                                                           */
56635   #define MEMCONF_POWER_CONTROL_MEM6_On (0x1UL)      /*!< Power up                                                             */
56636 
56637 /* MEM7 @Bit 7 : Keep the memory block MEM[7] on or off when in System ON mode. */
56638   #define MEMCONF_POWER_CONTROL_MEM7_Pos (7UL)       /*!< Position of MEM7 field.                                              */
56639   #define MEMCONF_POWER_CONTROL_MEM7_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM7_Pos) /*!< Bit mask of MEM7 field.                */
56640   #define MEMCONF_POWER_CONTROL_MEM7_Min (0x0UL)     /*!< Min enumerator value of MEM7 field.                                  */
56641   #define MEMCONF_POWER_CONTROL_MEM7_Max (0x1UL)     /*!< Max enumerator value of MEM7 field.                                  */
56642   #define MEMCONF_POWER_CONTROL_MEM7_Off (0x0UL)     /*!< Power down                                                           */
56643   #define MEMCONF_POWER_CONTROL_MEM7_On (0x1UL)      /*!< Power up                                                             */
56644 
56645 /* MEM8 @Bit 8 : Keep the memory block MEM[8] on or off when in System ON mode. */
56646   #define MEMCONF_POWER_CONTROL_MEM8_Pos (8UL)       /*!< Position of MEM8 field.                                              */
56647   #define MEMCONF_POWER_CONTROL_MEM8_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM8_Pos) /*!< Bit mask of MEM8 field.                */
56648   #define MEMCONF_POWER_CONTROL_MEM8_Min (0x0UL)     /*!< Min enumerator value of MEM8 field.                                  */
56649   #define MEMCONF_POWER_CONTROL_MEM8_Max (0x1UL)     /*!< Max enumerator value of MEM8 field.                                  */
56650   #define MEMCONF_POWER_CONTROL_MEM8_Off (0x0UL)     /*!< Power down                                                           */
56651   #define MEMCONF_POWER_CONTROL_MEM8_On (0x1UL)      /*!< Power up                                                             */
56652 
56653 /* MEM9 @Bit 9 : Keep the memory block MEM[9] on or off when in System ON mode. */
56654   #define MEMCONF_POWER_CONTROL_MEM9_Pos (9UL)       /*!< Position of MEM9 field.                                              */
56655   #define MEMCONF_POWER_CONTROL_MEM9_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM9_Pos) /*!< Bit mask of MEM9 field.                */
56656   #define MEMCONF_POWER_CONTROL_MEM9_Min (0x0UL)     /*!< Min enumerator value of MEM9 field.                                  */
56657   #define MEMCONF_POWER_CONTROL_MEM9_Max (0x1UL)     /*!< Max enumerator value of MEM9 field.                                  */
56658   #define MEMCONF_POWER_CONTROL_MEM9_Off (0x0UL)     /*!< Power down                                                           */
56659   #define MEMCONF_POWER_CONTROL_MEM9_On (0x1UL)      /*!< Power up                                                             */
56660 
56661 /* MEM10 @Bit 10 : Keep the memory block MEM[10] on or off when in System ON mode. */
56662   #define MEMCONF_POWER_CONTROL_MEM10_Pos (10UL)     /*!< Position of MEM10 field.                                             */
56663   #define MEMCONF_POWER_CONTROL_MEM10_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM10_Pos) /*!< Bit mask of MEM10 field.             */
56664   #define MEMCONF_POWER_CONTROL_MEM10_Min (0x0UL)    /*!< Min enumerator value of MEM10 field.                                 */
56665   #define MEMCONF_POWER_CONTROL_MEM10_Max (0x1UL)    /*!< Max enumerator value of MEM10 field.                                 */
56666   #define MEMCONF_POWER_CONTROL_MEM10_Off (0x0UL)    /*!< Power down                                                           */
56667   #define MEMCONF_POWER_CONTROL_MEM10_On (0x1UL)     /*!< Power up                                                             */
56668 
56669 /* MEM11 @Bit 11 : Keep the memory block MEM[11] on or off when in System ON mode. */
56670   #define MEMCONF_POWER_CONTROL_MEM11_Pos (11UL)     /*!< Position of MEM11 field.                                             */
56671   #define MEMCONF_POWER_CONTROL_MEM11_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM11_Pos) /*!< Bit mask of MEM11 field.             */
56672   #define MEMCONF_POWER_CONTROL_MEM11_Min (0x0UL)    /*!< Min enumerator value of MEM11 field.                                 */
56673   #define MEMCONF_POWER_CONTROL_MEM11_Max (0x1UL)    /*!< Max enumerator value of MEM11 field.                                 */
56674   #define MEMCONF_POWER_CONTROL_MEM11_Off (0x0UL)    /*!< Power down                                                           */
56675   #define MEMCONF_POWER_CONTROL_MEM11_On (0x1UL)     /*!< Power up                                                             */
56676 
56677 /* MEM12 @Bit 12 : Keep the memory block MEM[12] on or off when in System ON mode. */
56678   #define MEMCONF_POWER_CONTROL_MEM12_Pos (12UL)     /*!< Position of MEM12 field.                                             */
56679   #define MEMCONF_POWER_CONTROL_MEM12_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM12_Pos) /*!< Bit mask of MEM12 field.             */
56680   #define MEMCONF_POWER_CONTROL_MEM12_Min (0x0UL)    /*!< Min enumerator value of MEM12 field.                                 */
56681   #define MEMCONF_POWER_CONTROL_MEM12_Max (0x1UL)    /*!< Max enumerator value of MEM12 field.                                 */
56682   #define MEMCONF_POWER_CONTROL_MEM12_Off (0x0UL)    /*!< Power down                                                           */
56683   #define MEMCONF_POWER_CONTROL_MEM12_On (0x1UL)     /*!< Power up                                                             */
56684 
56685 /* MEM13 @Bit 13 : Keep the memory block MEM[13] on or off when in System ON mode. */
56686   #define MEMCONF_POWER_CONTROL_MEM13_Pos (13UL)     /*!< Position of MEM13 field.                                             */
56687   #define MEMCONF_POWER_CONTROL_MEM13_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM13_Pos) /*!< Bit mask of MEM13 field.             */
56688   #define MEMCONF_POWER_CONTROL_MEM13_Min (0x0UL)    /*!< Min enumerator value of MEM13 field.                                 */
56689   #define MEMCONF_POWER_CONTROL_MEM13_Max (0x1UL)    /*!< Max enumerator value of MEM13 field.                                 */
56690   #define MEMCONF_POWER_CONTROL_MEM13_Off (0x0UL)    /*!< Power down                                                           */
56691   #define MEMCONF_POWER_CONTROL_MEM13_On (0x1UL)     /*!< Power up                                                             */
56692 
56693 /* MEM14 @Bit 14 : Keep the memory block MEM[14] on or off when in System ON mode. */
56694   #define MEMCONF_POWER_CONTROL_MEM14_Pos (14UL)     /*!< Position of MEM14 field.                                             */
56695   #define MEMCONF_POWER_CONTROL_MEM14_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM14_Pos) /*!< Bit mask of MEM14 field.             */
56696   #define MEMCONF_POWER_CONTROL_MEM14_Min (0x0UL)    /*!< Min enumerator value of MEM14 field.                                 */
56697   #define MEMCONF_POWER_CONTROL_MEM14_Max (0x1UL)    /*!< Max enumerator value of MEM14 field.                                 */
56698   #define MEMCONF_POWER_CONTROL_MEM14_Off (0x0UL)    /*!< Power down                                                           */
56699   #define MEMCONF_POWER_CONTROL_MEM14_On (0x1UL)     /*!< Power up                                                             */
56700 
56701 /* MEM15 @Bit 15 : Keep the memory block MEM[15] on or off when in System ON mode. */
56702   #define MEMCONF_POWER_CONTROL_MEM15_Pos (15UL)     /*!< Position of MEM15 field.                                             */
56703   #define MEMCONF_POWER_CONTROL_MEM15_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM15_Pos) /*!< Bit mask of MEM15 field.             */
56704   #define MEMCONF_POWER_CONTROL_MEM15_Min (0x0UL)    /*!< Min enumerator value of MEM15 field.                                 */
56705   #define MEMCONF_POWER_CONTROL_MEM15_Max (0x1UL)    /*!< Max enumerator value of MEM15 field.                                 */
56706   #define MEMCONF_POWER_CONTROL_MEM15_Off (0x0UL)    /*!< Power down                                                           */
56707   #define MEMCONF_POWER_CONTROL_MEM15_On (0x1UL)     /*!< Power up                                                             */
56708 
56709 /* MEM16 @Bit 16 : Keep the memory block MEM[16] on or off when in System ON mode. */
56710   #define MEMCONF_POWER_CONTROL_MEM16_Pos (16UL)     /*!< Position of MEM16 field.                                             */
56711   #define MEMCONF_POWER_CONTROL_MEM16_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM16_Pos) /*!< Bit mask of MEM16 field.             */
56712   #define MEMCONF_POWER_CONTROL_MEM16_Min (0x0UL)    /*!< Min enumerator value of MEM16 field.                                 */
56713   #define MEMCONF_POWER_CONTROL_MEM16_Max (0x1UL)    /*!< Max enumerator value of MEM16 field.                                 */
56714   #define MEMCONF_POWER_CONTROL_MEM16_Off (0x0UL)    /*!< Power down                                                           */
56715   #define MEMCONF_POWER_CONTROL_MEM16_On (0x1UL)     /*!< Power up                                                             */
56716 
56717 /* MEM17 @Bit 17 : Keep the memory block MEM[17] on or off when in System ON mode. */
56718   #define MEMCONF_POWER_CONTROL_MEM17_Pos (17UL)     /*!< Position of MEM17 field.                                             */
56719   #define MEMCONF_POWER_CONTROL_MEM17_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM17_Pos) /*!< Bit mask of MEM17 field.             */
56720   #define MEMCONF_POWER_CONTROL_MEM17_Min (0x0UL)    /*!< Min enumerator value of MEM17 field.                                 */
56721   #define MEMCONF_POWER_CONTROL_MEM17_Max (0x1UL)    /*!< Max enumerator value of MEM17 field.                                 */
56722   #define MEMCONF_POWER_CONTROL_MEM17_Off (0x0UL)    /*!< Power down                                                           */
56723   #define MEMCONF_POWER_CONTROL_MEM17_On (0x1UL)     /*!< Power up                                                             */
56724 
56725 /* MEM18 @Bit 18 : Keep the memory block MEM[18] on or off when in System ON mode. */
56726   #define MEMCONF_POWER_CONTROL_MEM18_Pos (18UL)     /*!< Position of MEM18 field.                                             */
56727   #define MEMCONF_POWER_CONTROL_MEM18_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM18_Pos) /*!< Bit mask of MEM18 field.             */
56728   #define MEMCONF_POWER_CONTROL_MEM18_Min (0x0UL)    /*!< Min enumerator value of MEM18 field.                                 */
56729   #define MEMCONF_POWER_CONTROL_MEM18_Max (0x1UL)    /*!< Max enumerator value of MEM18 field.                                 */
56730   #define MEMCONF_POWER_CONTROL_MEM18_Off (0x0UL)    /*!< Power down                                                           */
56731   #define MEMCONF_POWER_CONTROL_MEM18_On (0x1UL)     /*!< Power up                                                             */
56732 
56733 /* MEM19 @Bit 19 : Keep the memory block MEM[19] on or off when in System ON mode. */
56734   #define MEMCONF_POWER_CONTROL_MEM19_Pos (19UL)     /*!< Position of MEM19 field.                                             */
56735   #define MEMCONF_POWER_CONTROL_MEM19_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM19_Pos) /*!< Bit mask of MEM19 field.             */
56736   #define MEMCONF_POWER_CONTROL_MEM19_Min (0x0UL)    /*!< Min enumerator value of MEM19 field.                                 */
56737   #define MEMCONF_POWER_CONTROL_MEM19_Max (0x1UL)    /*!< Max enumerator value of MEM19 field.                                 */
56738   #define MEMCONF_POWER_CONTROL_MEM19_Off (0x0UL)    /*!< Power down                                                           */
56739   #define MEMCONF_POWER_CONTROL_MEM19_On (0x1UL)     /*!< Power up                                                             */
56740 
56741 /* MEM20 @Bit 20 : Keep the memory block MEM[20] on or off when in System ON mode. */
56742   #define MEMCONF_POWER_CONTROL_MEM20_Pos (20UL)     /*!< Position of MEM20 field.                                             */
56743   #define MEMCONF_POWER_CONTROL_MEM20_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM20_Pos) /*!< Bit mask of MEM20 field.             */
56744   #define MEMCONF_POWER_CONTROL_MEM20_Min (0x0UL)    /*!< Min enumerator value of MEM20 field.                                 */
56745   #define MEMCONF_POWER_CONTROL_MEM20_Max (0x1UL)    /*!< Max enumerator value of MEM20 field.                                 */
56746   #define MEMCONF_POWER_CONTROL_MEM20_Off (0x0UL)    /*!< Power down                                                           */
56747   #define MEMCONF_POWER_CONTROL_MEM20_On (0x1UL)     /*!< Power up                                                             */
56748 
56749 /* MEM21 @Bit 21 : Keep the memory block MEM[21] on or off when in System ON mode. */
56750   #define MEMCONF_POWER_CONTROL_MEM21_Pos (21UL)     /*!< Position of MEM21 field.                                             */
56751   #define MEMCONF_POWER_CONTROL_MEM21_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM21_Pos) /*!< Bit mask of MEM21 field.             */
56752   #define MEMCONF_POWER_CONTROL_MEM21_Min (0x0UL)    /*!< Min enumerator value of MEM21 field.                                 */
56753   #define MEMCONF_POWER_CONTROL_MEM21_Max (0x1UL)    /*!< Max enumerator value of MEM21 field.                                 */
56754   #define MEMCONF_POWER_CONTROL_MEM21_Off (0x0UL)    /*!< Power down                                                           */
56755   #define MEMCONF_POWER_CONTROL_MEM21_On (0x1UL)     /*!< Power up                                                             */
56756 
56757 /* MEM22 @Bit 22 : Keep the memory block MEM[22] on or off when in System ON mode. */
56758   #define MEMCONF_POWER_CONTROL_MEM22_Pos (22UL)     /*!< Position of MEM22 field.                                             */
56759   #define MEMCONF_POWER_CONTROL_MEM22_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM22_Pos) /*!< Bit mask of MEM22 field.             */
56760   #define MEMCONF_POWER_CONTROL_MEM22_Min (0x0UL)    /*!< Min enumerator value of MEM22 field.                                 */
56761   #define MEMCONF_POWER_CONTROL_MEM22_Max (0x1UL)    /*!< Max enumerator value of MEM22 field.                                 */
56762   #define MEMCONF_POWER_CONTROL_MEM22_Off (0x0UL)    /*!< Power down                                                           */
56763   #define MEMCONF_POWER_CONTROL_MEM22_On (0x1UL)     /*!< Power up                                                             */
56764 
56765 /* MEM23 @Bit 23 : Keep the memory block MEM[23] on or off when in System ON mode. */
56766   #define MEMCONF_POWER_CONTROL_MEM23_Pos (23UL)     /*!< Position of MEM23 field.                                             */
56767   #define MEMCONF_POWER_CONTROL_MEM23_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM23_Pos) /*!< Bit mask of MEM23 field.             */
56768   #define MEMCONF_POWER_CONTROL_MEM23_Min (0x0UL)    /*!< Min enumerator value of MEM23 field.                                 */
56769   #define MEMCONF_POWER_CONTROL_MEM23_Max (0x1UL)    /*!< Max enumerator value of MEM23 field.                                 */
56770   #define MEMCONF_POWER_CONTROL_MEM23_Off (0x0UL)    /*!< Power down                                                           */
56771   #define MEMCONF_POWER_CONTROL_MEM23_On (0x1UL)     /*!< Power up                                                             */
56772 
56773 /* MEM24 @Bit 24 : Keep the memory block MEM[24] on or off when in System ON mode. */
56774   #define MEMCONF_POWER_CONTROL_MEM24_Pos (24UL)     /*!< Position of MEM24 field.                                             */
56775   #define MEMCONF_POWER_CONTROL_MEM24_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM24_Pos) /*!< Bit mask of MEM24 field.             */
56776   #define MEMCONF_POWER_CONTROL_MEM24_Min (0x0UL)    /*!< Min enumerator value of MEM24 field.                                 */
56777   #define MEMCONF_POWER_CONTROL_MEM24_Max (0x1UL)    /*!< Max enumerator value of MEM24 field.                                 */
56778   #define MEMCONF_POWER_CONTROL_MEM24_Off (0x0UL)    /*!< Power down                                                           */
56779   #define MEMCONF_POWER_CONTROL_MEM24_On (0x1UL)     /*!< Power up                                                             */
56780 
56781 /* MEM25 @Bit 25 : Keep the memory block MEM[25] on or off when in System ON mode. */
56782   #define MEMCONF_POWER_CONTROL_MEM25_Pos (25UL)     /*!< Position of MEM25 field.                                             */
56783   #define MEMCONF_POWER_CONTROL_MEM25_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM25_Pos) /*!< Bit mask of MEM25 field.             */
56784   #define MEMCONF_POWER_CONTROL_MEM25_Min (0x0UL)    /*!< Min enumerator value of MEM25 field.                                 */
56785   #define MEMCONF_POWER_CONTROL_MEM25_Max (0x1UL)    /*!< Max enumerator value of MEM25 field.                                 */
56786   #define MEMCONF_POWER_CONTROL_MEM25_Off (0x0UL)    /*!< Power down                                                           */
56787   #define MEMCONF_POWER_CONTROL_MEM25_On (0x1UL)     /*!< Power up                                                             */
56788 
56789 /* MEM26 @Bit 26 : Keep the memory block MEM[26] on or off when in System ON mode. */
56790   #define MEMCONF_POWER_CONTROL_MEM26_Pos (26UL)     /*!< Position of MEM26 field.                                             */
56791   #define MEMCONF_POWER_CONTROL_MEM26_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM26_Pos) /*!< Bit mask of MEM26 field.             */
56792   #define MEMCONF_POWER_CONTROL_MEM26_Min (0x0UL)    /*!< Min enumerator value of MEM26 field.                                 */
56793   #define MEMCONF_POWER_CONTROL_MEM26_Max (0x1UL)    /*!< Max enumerator value of MEM26 field.                                 */
56794   #define MEMCONF_POWER_CONTROL_MEM26_Off (0x0UL)    /*!< Power down                                                           */
56795   #define MEMCONF_POWER_CONTROL_MEM26_On (0x1UL)     /*!< Power up                                                             */
56796 
56797 /* MEM27 @Bit 27 : Keep the memory block MEM[27] on or off when in System ON mode. */
56798   #define MEMCONF_POWER_CONTROL_MEM27_Pos (27UL)     /*!< Position of MEM27 field.                                             */
56799   #define MEMCONF_POWER_CONTROL_MEM27_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM27_Pos) /*!< Bit mask of MEM27 field.             */
56800   #define MEMCONF_POWER_CONTROL_MEM27_Min (0x0UL)    /*!< Min enumerator value of MEM27 field.                                 */
56801   #define MEMCONF_POWER_CONTROL_MEM27_Max (0x1UL)    /*!< Max enumerator value of MEM27 field.                                 */
56802   #define MEMCONF_POWER_CONTROL_MEM27_Off (0x0UL)    /*!< Power down                                                           */
56803   #define MEMCONF_POWER_CONTROL_MEM27_On (0x1UL)     /*!< Power up                                                             */
56804 
56805 /* MEM28 @Bit 28 : Keep the memory block MEM[28] on or off when in System ON mode. */
56806   #define MEMCONF_POWER_CONTROL_MEM28_Pos (28UL)     /*!< Position of MEM28 field.                                             */
56807   #define MEMCONF_POWER_CONTROL_MEM28_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM28_Pos) /*!< Bit mask of MEM28 field.             */
56808   #define MEMCONF_POWER_CONTROL_MEM28_Min (0x0UL)    /*!< Min enumerator value of MEM28 field.                                 */
56809   #define MEMCONF_POWER_CONTROL_MEM28_Max (0x1UL)    /*!< Max enumerator value of MEM28 field.                                 */
56810   #define MEMCONF_POWER_CONTROL_MEM28_Off (0x0UL)    /*!< Power down                                                           */
56811   #define MEMCONF_POWER_CONTROL_MEM28_On (0x1UL)     /*!< Power up                                                             */
56812 
56813 /* MEM29 @Bit 29 : Keep the memory block MEM[29] on or off when in System ON mode. */
56814   #define MEMCONF_POWER_CONTROL_MEM29_Pos (29UL)     /*!< Position of MEM29 field.                                             */
56815   #define MEMCONF_POWER_CONTROL_MEM29_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM29_Pos) /*!< Bit mask of MEM29 field.             */
56816   #define MEMCONF_POWER_CONTROL_MEM29_Min (0x0UL)    /*!< Min enumerator value of MEM29 field.                                 */
56817   #define MEMCONF_POWER_CONTROL_MEM29_Max (0x1UL)    /*!< Max enumerator value of MEM29 field.                                 */
56818   #define MEMCONF_POWER_CONTROL_MEM29_Off (0x0UL)    /*!< Power down                                                           */
56819   #define MEMCONF_POWER_CONTROL_MEM29_On (0x1UL)     /*!< Power up                                                             */
56820 
56821 /* MEM30 @Bit 30 : Keep the memory block MEM[30] on or off when in System ON mode. */
56822   #define MEMCONF_POWER_CONTROL_MEM30_Pos (30UL)     /*!< Position of MEM30 field.                                             */
56823   #define MEMCONF_POWER_CONTROL_MEM30_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM30_Pos) /*!< Bit mask of MEM30 field.             */
56824   #define MEMCONF_POWER_CONTROL_MEM30_Min (0x0UL)    /*!< Min enumerator value of MEM30 field.                                 */
56825   #define MEMCONF_POWER_CONTROL_MEM30_Max (0x1UL)    /*!< Max enumerator value of MEM30 field.                                 */
56826   #define MEMCONF_POWER_CONTROL_MEM30_Off (0x0UL)    /*!< Power down                                                           */
56827   #define MEMCONF_POWER_CONTROL_MEM30_On (0x1UL)     /*!< Power up                                                             */
56828 
56829 /* MEM31 @Bit 31 : Keep the memory block MEM[31] on or off when in System ON mode. */
56830   #define MEMCONF_POWER_CONTROL_MEM31_Pos (31UL)     /*!< Position of MEM31 field.                                             */
56831   #define MEMCONF_POWER_CONTROL_MEM31_Msk (0x1UL << MEMCONF_POWER_CONTROL_MEM31_Pos) /*!< Bit mask of MEM31 field.             */
56832   #define MEMCONF_POWER_CONTROL_MEM31_Min (0x0UL)    /*!< Min enumerator value of MEM31 field.                                 */
56833   #define MEMCONF_POWER_CONTROL_MEM31_Max (0x1UL)    /*!< Max enumerator value of MEM31 field.                                 */
56834   #define MEMCONF_POWER_CONTROL_MEM31_Off (0x0UL)    /*!< Power down                                                           */
56835   #define MEMCONF_POWER_CONTROL_MEM31_On (0x1UL)     /*!< Power up                                                             */
56836 
56837 
56838 /* MEMCONF_POWER_RET: RAM retention for RAM [n]. */
56839   #define MEMCONF_POWER_RET_ResetValue (0x00000000UL) /*!< Reset value of RET register.                                        */
56840 
56841 /* MEM0 @Bit 0 : Keep the RAM block MEM[0] retained when the parent power domain of the RAM is off. */
56842   #define MEMCONF_POWER_RET_MEM0_Pos (0UL)           /*!< Position of MEM0 field.                                              */
56843   #define MEMCONF_POWER_RET_MEM0_Msk (0x1UL << MEMCONF_POWER_RET_MEM0_Pos) /*!< Bit mask of MEM0 field.                        */
56844   #define MEMCONF_POWER_RET_MEM0_Min (0x0UL)         /*!< Min enumerator value of MEM0 field.                                  */
56845   #define MEMCONF_POWER_RET_MEM0_Max (0x1UL)         /*!< Max enumerator value of MEM0 field.                                  */
56846   #define MEMCONF_POWER_RET_MEM0_Off (0x0UL)         /*!< Retention off                                                        */
56847   #define MEMCONF_POWER_RET_MEM0_On (0x1UL)          /*!< Retention on                                                         */
56848 
56849 /* MEM1 @Bit 1 : Keep the RAM block MEM[1] retained when the parent power domain of the RAM is off. */
56850   #define MEMCONF_POWER_RET_MEM1_Pos (1UL)           /*!< Position of MEM1 field.                                              */
56851   #define MEMCONF_POWER_RET_MEM1_Msk (0x1UL << MEMCONF_POWER_RET_MEM1_Pos) /*!< Bit mask of MEM1 field.                        */
56852   #define MEMCONF_POWER_RET_MEM1_Min (0x0UL)         /*!< Min enumerator value of MEM1 field.                                  */
56853   #define MEMCONF_POWER_RET_MEM1_Max (0x1UL)         /*!< Max enumerator value of MEM1 field.                                  */
56854   #define MEMCONF_POWER_RET_MEM1_Off (0x0UL)         /*!< Retention off                                                        */
56855   #define MEMCONF_POWER_RET_MEM1_On (0x1UL)          /*!< Retention on                                                         */
56856 
56857 /* MEM2 @Bit 2 : Keep the RAM block MEM[2] retained when the parent power domain of the RAM is off. */
56858   #define MEMCONF_POWER_RET_MEM2_Pos (2UL)           /*!< Position of MEM2 field.                                              */
56859   #define MEMCONF_POWER_RET_MEM2_Msk (0x1UL << MEMCONF_POWER_RET_MEM2_Pos) /*!< Bit mask of MEM2 field.                        */
56860   #define MEMCONF_POWER_RET_MEM2_Min (0x0UL)         /*!< Min enumerator value of MEM2 field.                                  */
56861   #define MEMCONF_POWER_RET_MEM2_Max (0x1UL)         /*!< Max enumerator value of MEM2 field.                                  */
56862   #define MEMCONF_POWER_RET_MEM2_Off (0x0UL)         /*!< Retention off                                                        */
56863   #define MEMCONF_POWER_RET_MEM2_On (0x1UL)          /*!< Retention on                                                         */
56864 
56865 /* MEM3 @Bit 3 : Keep the RAM block MEM[3] retained when the parent power domain of the RAM is off. */
56866   #define MEMCONF_POWER_RET_MEM3_Pos (3UL)           /*!< Position of MEM3 field.                                              */
56867   #define MEMCONF_POWER_RET_MEM3_Msk (0x1UL << MEMCONF_POWER_RET_MEM3_Pos) /*!< Bit mask of MEM3 field.                        */
56868   #define MEMCONF_POWER_RET_MEM3_Min (0x0UL)         /*!< Min enumerator value of MEM3 field.                                  */
56869   #define MEMCONF_POWER_RET_MEM3_Max (0x1UL)         /*!< Max enumerator value of MEM3 field.                                  */
56870   #define MEMCONF_POWER_RET_MEM3_Off (0x0UL)         /*!< Retention off                                                        */
56871   #define MEMCONF_POWER_RET_MEM3_On (0x1UL)          /*!< Retention on                                                         */
56872 
56873 /* MEM4 @Bit 4 : Keep the RAM block MEM[4] retained when the parent power domain of the RAM is off. */
56874   #define MEMCONF_POWER_RET_MEM4_Pos (4UL)           /*!< Position of MEM4 field.                                              */
56875   #define MEMCONF_POWER_RET_MEM4_Msk (0x1UL << MEMCONF_POWER_RET_MEM4_Pos) /*!< Bit mask of MEM4 field.                        */
56876   #define MEMCONF_POWER_RET_MEM4_Min (0x0UL)         /*!< Min enumerator value of MEM4 field.                                  */
56877   #define MEMCONF_POWER_RET_MEM4_Max (0x1UL)         /*!< Max enumerator value of MEM4 field.                                  */
56878   #define MEMCONF_POWER_RET_MEM4_Off (0x0UL)         /*!< Retention off                                                        */
56879   #define MEMCONF_POWER_RET_MEM4_On (0x1UL)          /*!< Retention on                                                         */
56880 
56881 /* MEM5 @Bit 5 : Keep the RAM block MEM[5] retained when the parent power domain of the RAM is off. */
56882   #define MEMCONF_POWER_RET_MEM5_Pos (5UL)           /*!< Position of MEM5 field.                                              */
56883   #define MEMCONF_POWER_RET_MEM5_Msk (0x1UL << MEMCONF_POWER_RET_MEM5_Pos) /*!< Bit mask of MEM5 field.                        */
56884   #define MEMCONF_POWER_RET_MEM5_Min (0x0UL)         /*!< Min enumerator value of MEM5 field.                                  */
56885   #define MEMCONF_POWER_RET_MEM5_Max (0x1UL)         /*!< Max enumerator value of MEM5 field.                                  */
56886   #define MEMCONF_POWER_RET_MEM5_Off (0x0UL)         /*!< Retention off                                                        */
56887   #define MEMCONF_POWER_RET_MEM5_On (0x1UL)          /*!< Retention on                                                         */
56888 
56889 /* MEM6 @Bit 6 : Keep the RAM block MEM[6] retained when the parent power domain of the RAM is off. */
56890   #define MEMCONF_POWER_RET_MEM6_Pos (6UL)           /*!< Position of MEM6 field.                                              */
56891   #define MEMCONF_POWER_RET_MEM6_Msk (0x1UL << MEMCONF_POWER_RET_MEM6_Pos) /*!< Bit mask of MEM6 field.                        */
56892   #define MEMCONF_POWER_RET_MEM6_Min (0x0UL)         /*!< Min enumerator value of MEM6 field.                                  */
56893   #define MEMCONF_POWER_RET_MEM6_Max (0x1UL)         /*!< Max enumerator value of MEM6 field.                                  */
56894   #define MEMCONF_POWER_RET_MEM6_Off (0x0UL)         /*!< Retention off                                                        */
56895   #define MEMCONF_POWER_RET_MEM6_On (0x1UL)          /*!< Retention on                                                         */
56896 
56897 /* MEM7 @Bit 7 : Keep the RAM block MEM[7] retained when the parent power domain of the RAM is off. */
56898   #define MEMCONF_POWER_RET_MEM7_Pos (7UL)           /*!< Position of MEM7 field.                                              */
56899   #define MEMCONF_POWER_RET_MEM7_Msk (0x1UL << MEMCONF_POWER_RET_MEM7_Pos) /*!< Bit mask of MEM7 field.                        */
56900   #define MEMCONF_POWER_RET_MEM7_Min (0x0UL)         /*!< Min enumerator value of MEM7 field.                                  */
56901   #define MEMCONF_POWER_RET_MEM7_Max (0x1UL)         /*!< Max enumerator value of MEM7 field.                                  */
56902   #define MEMCONF_POWER_RET_MEM7_Off (0x0UL)         /*!< Retention off                                                        */
56903   #define MEMCONF_POWER_RET_MEM7_On (0x1UL)          /*!< Retention on                                                         */
56904 
56905 /* MEM8 @Bit 8 : Keep the RAM block MEM[8] retained when the parent power domain of the RAM is off. */
56906   #define MEMCONF_POWER_RET_MEM8_Pos (8UL)           /*!< Position of MEM8 field.                                              */
56907   #define MEMCONF_POWER_RET_MEM8_Msk (0x1UL << MEMCONF_POWER_RET_MEM8_Pos) /*!< Bit mask of MEM8 field.                        */
56908   #define MEMCONF_POWER_RET_MEM8_Min (0x0UL)         /*!< Min enumerator value of MEM8 field.                                  */
56909   #define MEMCONF_POWER_RET_MEM8_Max (0x1UL)         /*!< Max enumerator value of MEM8 field.                                  */
56910   #define MEMCONF_POWER_RET_MEM8_Off (0x0UL)         /*!< Retention off                                                        */
56911   #define MEMCONF_POWER_RET_MEM8_On (0x1UL)          /*!< Retention on                                                         */
56912 
56913 /* MEM9 @Bit 9 : Keep the RAM block MEM[9] retained when the parent power domain of the RAM is off. */
56914   #define MEMCONF_POWER_RET_MEM9_Pos (9UL)           /*!< Position of MEM9 field.                                              */
56915   #define MEMCONF_POWER_RET_MEM9_Msk (0x1UL << MEMCONF_POWER_RET_MEM9_Pos) /*!< Bit mask of MEM9 field.                        */
56916   #define MEMCONF_POWER_RET_MEM9_Min (0x0UL)         /*!< Min enumerator value of MEM9 field.                                  */
56917   #define MEMCONF_POWER_RET_MEM9_Max (0x1UL)         /*!< Max enumerator value of MEM9 field.                                  */
56918   #define MEMCONF_POWER_RET_MEM9_Off (0x0UL)         /*!< Retention off                                                        */
56919   #define MEMCONF_POWER_RET_MEM9_On (0x1UL)          /*!< Retention on                                                         */
56920 
56921 /* MEM10 @Bit 10 : Keep the RAM block MEM[10] retained when the parent power domain of the RAM is off. */
56922   #define MEMCONF_POWER_RET_MEM10_Pos (10UL)         /*!< Position of MEM10 field.                                             */
56923   #define MEMCONF_POWER_RET_MEM10_Msk (0x1UL << MEMCONF_POWER_RET_MEM10_Pos) /*!< Bit mask of MEM10 field.                     */
56924   #define MEMCONF_POWER_RET_MEM10_Min (0x0UL)        /*!< Min enumerator value of MEM10 field.                                 */
56925   #define MEMCONF_POWER_RET_MEM10_Max (0x1UL)        /*!< Max enumerator value of MEM10 field.                                 */
56926   #define MEMCONF_POWER_RET_MEM10_Off (0x0UL)        /*!< Retention off                                                        */
56927   #define MEMCONF_POWER_RET_MEM10_On (0x1UL)         /*!< Retention on                                                         */
56928 
56929 /* MEM11 @Bit 11 : Keep the RAM block MEM[11] retained when the parent power domain of the RAM is off. */
56930   #define MEMCONF_POWER_RET_MEM11_Pos (11UL)         /*!< Position of MEM11 field.                                             */
56931   #define MEMCONF_POWER_RET_MEM11_Msk (0x1UL << MEMCONF_POWER_RET_MEM11_Pos) /*!< Bit mask of MEM11 field.                     */
56932   #define MEMCONF_POWER_RET_MEM11_Min (0x0UL)        /*!< Min enumerator value of MEM11 field.                                 */
56933   #define MEMCONF_POWER_RET_MEM11_Max (0x1UL)        /*!< Max enumerator value of MEM11 field.                                 */
56934   #define MEMCONF_POWER_RET_MEM11_Off (0x0UL)        /*!< Retention off                                                        */
56935   #define MEMCONF_POWER_RET_MEM11_On (0x1UL)         /*!< Retention on                                                         */
56936 
56937 /* MEM12 @Bit 12 : Keep the RAM block MEM[12] retained when the parent power domain of the RAM is off. */
56938   #define MEMCONF_POWER_RET_MEM12_Pos (12UL)         /*!< Position of MEM12 field.                                             */
56939   #define MEMCONF_POWER_RET_MEM12_Msk (0x1UL << MEMCONF_POWER_RET_MEM12_Pos) /*!< Bit mask of MEM12 field.                     */
56940   #define MEMCONF_POWER_RET_MEM12_Min (0x0UL)        /*!< Min enumerator value of MEM12 field.                                 */
56941   #define MEMCONF_POWER_RET_MEM12_Max (0x1UL)        /*!< Max enumerator value of MEM12 field.                                 */
56942   #define MEMCONF_POWER_RET_MEM12_Off (0x0UL)        /*!< Retention off                                                        */
56943   #define MEMCONF_POWER_RET_MEM12_On (0x1UL)         /*!< Retention on                                                         */
56944 
56945 /* MEM13 @Bit 13 : Keep the RAM block MEM[13] retained when the parent power domain of the RAM is off. */
56946   #define MEMCONF_POWER_RET_MEM13_Pos (13UL)         /*!< Position of MEM13 field.                                             */
56947   #define MEMCONF_POWER_RET_MEM13_Msk (0x1UL << MEMCONF_POWER_RET_MEM13_Pos) /*!< Bit mask of MEM13 field.                     */
56948   #define MEMCONF_POWER_RET_MEM13_Min (0x0UL)        /*!< Min enumerator value of MEM13 field.                                 */
56949   #define MEMCONF_POWER_RET_MEM13_Max (0x1UL)        /*!< Max enumerator value of MEM13 field.                                 */
56950   #define MEMCONF_POWER_RET_MEM13_Off (0x0UL)        /*!< Retention off                                                        */
56951   #define MEMCONF_POWER_RET_MEM13_On (0x1UL)         /*!< Retention on                                                         */
56952 
56953 /* MEM14 @Bit 14 : Keep the RAM block MEM[14] retained when the parent power domain of the RAM is off. */
56954   #define MEMCONF_POWER_RET_MEM14_Pos (14UL)         /*!< Position of MEM14 field.                                             */
56955   #define MEMCONF_POWER_RET_MEM14_Msk (0x1UL << MEMCONF_POWER_RET_MEM14_Pos) /*!< Bit mask of MEM14 field.                     */
56956   #define MEMCONF_POWER_RET_MEM14_Min (0x0UL)        /*!< Min enumerator value of MEM14 field.                                 */
56957   #define MEMCONF_POWER_RET_MEM14_Max (0x1UL)        /*!< Max enumerator value of MEM14 field.                                 */
56958   #define MEMCONF_POWER_RET_MEM14_Off (0x0UL)        /*!< Retention off                                                        */
56959   #define MEMCONF_POWER_RET_MEM14_On (0x1UL)         /*!< Retention on                                                         */
56960 
56961 /* MEM15 @Bit 15 : Keep the RAM block MEM[15] retained when the parent power domain of the RAM is off. */
56962   #define MEMCONF_POWER_RET_MEM15_Pos (15UL)         /*!< Position of MEM15 field.                                             */
56963   #define MEMCONF_POWER_RET_MEM15_Msk (0x1UL << MEMCONF_POWER_RET_MEM15_Pos) /*!< Bit mask of MEM15 field.                     */
56964   #define MEMCONF_POWER_RET_MEM15_Min (0x0UL)        /*!< Min enumerator value of MEM15 field.                                 */
56965   #define MEMCONF_POWER_RET_MEM15_Max (0x1UL)        /*!< Max enumerator value of MEM15 field.                                 */
56966   #define MEMCONF_POWER_RET_MEM15_Off (0x0UL)        /*!< Retention off                                                        */
56967   #define MEMCONF_POWER_RET_MEM15_On (0x1UL)         /*!< Retention on                                                         */
56968 
56969 /* MEM16 @Bit 16 : Keep the RAM block MEM[16] retained when the parent power domain of the RAM is off. */
56970   #define MEMCONF_POWER_RET_MEM16_Pos (16UL)         /*!< Position of MEM16 field.                                             */
56971   #define MEMCONF_POWER_RET_MEM16_Msk (0x1UL << MEMCONF_POWER_RET_MEM16_Pos) /*!< Bit mask of MEM16 field.                     */
56972   #define MEMCONF_POWER_RET_MEM16_Min (0x0UL)        /*!< Min enumerator value of MEM16 field.                                 */
56973   #define MEMCONF_POWER_RET_MEM16_Max (0x1UL)        /*!< Max enumerator value of MEM16 field.                                 */
56974   #define MEMCONF_POWER_RET_MEM16_Off (0x0UL)        /*!< Retention off                                                        */
56975   #define MEMCONF_POWER_RET_MEM16_On (0x1UL)         /*!< Retention on                                                         */
56976 
56977 /* MEM17 @Bit 17 : Keep the RAM block MEM[17] retained when the parent power domain of the RAM is off. */
56978   #define MEMCONF_POWER_RET_MEM17_Pos (17UL)         /*!< Position of MEM17 field.                                             */
56979   #define MEMCONF_POWER_RET_MEM17_Msk (0x1UL << MEMCONF_POWER_RET_MEM17_Pos) /*!< Bit mask of MEM17 field.                     */
56980   #define MEMCONF_POWER_RET_MEM17_Min (0x0UL)        /*!< Min enumerator value of MEM17 field.                                 */
56981   #define MEMCONF_POWER_RET_MEM17_Max (0x1UL)        /*!< Max enumerator value of MEM17 field.                                 */
56982   #define MEMCONF_POWER_RET_MEM17_Off (0x0UL)        /*!< Retention off                                                        */
56983   #define MEMCONF_POWER_RET_MEM17_On (0x1UL)         /*!< Retention on                                                         */
56984 
56985 /* MEM18 @Bit 18 : Keep the RAM block MEM[18] retained when the parent power domain of the RAM is off. */
56986   #define MEMCONF_POWER_RET_MEM18_Pos (18UL)         /*!< Position of MEM18 field.                                             */
56987   #define MEMCONF_POWER_RET_MEM18_Msk (0x1UL << MEMCONF_POWER_RET_MEM18_Pos) /*!< Bit mask of MEM18 field.                     */
56988   #define MEMCONF_POWER_RET_MEM18_Min (0x0UL)        /*!< Min enumerator value of MEM18 field.                                 */
56989   #define MEMCONF_POWER_RET_MEM18_Max (0x1UL)        /*!< Max enumerator value of MEM18 field.                                 */
56990   #define MEMCONF_POWER_RET_MEM18_Off (0x0UL)        /*!< Retention off                                                        */
56991   #define MEMCONF_POWER_RET_MEM18_On (0x1UL)         /*!< Retention on                                                         */
56992 
56993 /* MEM19 @Bit 19 : Keep the RAM block MEM[19] retained when the parent power domain of the RAM is off. */
56994   #define MEMCONF_POWER_RET_MEM19_Pos (19UL)         /*!< Position of MEM19 field.                                             */
56995   #define MEMCONF_POWER_RET_MEM19_Msk (0x1UL << MEMCONF_POWER_RET_MEM19_Pos) /*!< Bit mask of MEM19 field.                     */
56996   #define MEMCONF_POWER_RET_MEM19_Min (0x0UL)        /*!< Min enumerator value of MEM19 field.                                 */
56997   #define MEMCONF_POWER_RET_MEM19_Max (0x1UL)        /*!< Max enumerator value of MEM19 field.                                 */
56998   #define MEMCONF_POWER_RET_MEM19_Off (0x0UL)        /*!< Retention off                                                        */
56999   #define MEMCONF_POWER_RET_MEM19_On (0x1UL)         /*!< Retention on                                                         */
57000 
57001 /* MEM20 @Bit 20 : Keep the RAM block MEM[20] retained when the parent power domain of the RAM is off. */
57002   #define MEMCONF_POWER_RET_MEM20_Pos (20UL)         /*!< Position of MEM20 field.                                             */
57003   #define MEMCONF_POWER_RET_MEM20_Msk (0x1UL << MEMCONF_POWER_RET_MEM20_Pos) /*!< Bit mask of MEM20 field.                     */
57004   #define MEMCONF_POWER_RET_MEM20_Min (0x0UL)        /*!< Min enumerator value of MEM20 field.                                 */
57005   #define MEMCONF_POWER_RET_MEM20_Max (0x1UL)        /*!< Max enumerator value of MEM20 field.                                 */
57006   #define MEMCONF_POWER_RET_MEM20_Off (0x0UL)        /*!< Retention off                                                        */
57007   #define MEMCONF_POWER_RET_MEM20_On (0x1UL)         /*!< Retention on                                                         */
57008 
57009 /* MEM21 @Bit 21 : Keep the RAM block MEM[21] retained when the parent power domain of the RAM is off. */
57010   #define MEMCONF_POWER_RET_MEM21_Pos (21UL)         /*!< Position of MEM21 field.                                             */
57011   #define MEMCONF_POWER_RET_MEM21_Msk (0x1UL << MEMCONF_POWER_RET_MEM21_Pos) /*!< Bit mask of MEM21 field.                     */
57012   #define MEMCONF_POWER_RET_MEM21_Min (0x0UL)        /*!< Min enumerator value of MEM21 field.                                 */
57013   #define MEMCONF_POWER_RET_MEM21_Max (0x1UL)        /*!< Max enumerator value of MEM21 field.                                 */
57014   #define MEMCONF_POWER_RET_MEM21_Off (0x0UL)        /*!< Retention off                                                        */
57015   #define MEMCONF_POWER_RET_MEM21_On (0x1UL)         /*!< Retention on                                                         */
57016 
57017 /* MEM22 @Bit 22 : Keep the RAM block MEM[22] retained when the parent power domain of the RAM is off. */
57018   #define MEMCONF_POWER_RET_MEM22_Pos (22UL)         /*!< Position of MEM22 field.                                             */
57019   #define MEMCONF_POWER_RET_MEM22_Msk (0x1UL << MEMCONF_POWER_RET_MEM22_Pos) /*!< Bit mask of MEM22 field.                     */
57020   #define MEMCONF_POWER_RET_MEM22_Min (0x0UL)        /*!< Min enumerator value of MEM22 field.                                 */
57021   #define MEMCONF_POWER_RET_MEM22_Max (0x1UL)        /*!< Max enumerator value of MEM22 field.                                 */
57022   #define MEMCONF_POWER_RET_MEM22_Off (0x0UL)        /*!< Retention off                                                        */
57023   #define MEMCONF_POWER_RET_MEM22_On (0x1UL)         /*!< Retention on                                                         */
57024 
57025 /* MEM23 @Bit 23 : Keep the RAM block MEM[23] retained when the parent power domain of the RAM is off. */
57026   #define MEMCONF_POWER_RET_MEM23_Pos (23UL)         /*!< Position of MEM23 field.                                             */
57027   #define MEMCONF_POWER_RET_MEM23_Msk (0x1UL << MEMCONF_POWER_RET_MEM23_Pos) /*!< Bit mask of MEM23 field.                     */
57028   #define MEMCONF_POWER_RET_MEM23_Min (0x0UL)        /*!< Min enumerator value of MEM23 field.                                 */
57029   #define MEMCONF_POWER_RET_MEM23_Max (0x1UL)        /*!< Max enumerator value of MEM23 field.                                 */
57030   #define MEMCONF_POWER_RET_MEM23_Off (0x0UL)        /*!< Retention off                                                        */
57031   #define MEMCONF_POWER_RET_MEM23_On (0x1UL)         /*!< Retention on                                                         */
57032 
57033 /* MEM24 @Bit 24 : Keep the RAM block MEM[24] retained when the parent power domain of the RAM is off. */
57034   #define MEMCONF_POWER_RET_MEM24_Pos (24UL)         /*!< Position of MEM24 field.                                             */
57035   #define MEMCONF_POWER_RET_MEM24_Msk (0x1UL << MEMCONF_POWER_RET_MEM24_Pos) /*!< Bit mask of MEM24 field.                     */
57036   #define MEMCONF_POWER_RET_MEM24_Min (0x0UL)        /*!< Min enumerator value of MEM24 field.                                 */
57037   #define MEMCONF_POWER_RET_MEM24_Max (0x1UL)        /*!< Max enumerator value of MEM24 field.                                 */
57038   #define MEMCONF_POWER_RET_MEM24_Off (0x0UL)        /*!< Retention off                                                        */
57039   #define MEMCONF_POWER_RET_MEM24_On (0x1UL)         /*!< Retention on                                                         */
57040 
57041 /* MEM25 @Bit 25 : Keep the RAM block MEM[25] retained when the parent power domain of the RAM is off. */
57042   #define MEMCONF_POWER_RET_MEM25_Pos (25UL)         /*!< Position of MEM25 field.                                             */
57043   #define MEMCONF_POWER_RET_MEM25_Msk (0x1UL << MEMCONF_POWER_RET_MEM25_Pos) /*!< Bit mask of MEM25 field.                     */
57044   #define MEMCONF_POWER_RET_MEM25_Min (0x0UL)        /*!< Min enumerator value of MEM25 field.                                 */
57045   #define MEMCONF_POWER_RET_MEM25_Max (0x1UL)        /*!< Max enumerator value of MEM25 field.                                 */
57046   #define MEMCONF_POWER_RET_MEM25_Off (0x0UL)        /*!< Retention off                                                        */
57047   #define MEMCONF_POWER_RET_MEM25_On (0x1UL)         /*!< Retention on                                                         */
57048 
57049 /* MEM26 @Bit 26 : Keep the RAM block MEM[26] retained when the parent power domain of the RAM is off. */
57050   #define MEMCONF_POWER_RET_MEM26_Pos (26UL)         /*!< Position of MEM26 field.                                             */
57051   #define MEMCONF_POWER_RET_MEM26_Msk (0x1UL << MEMCONF_POWER_RET_MEM26_Pos) /*!< Bit mask of MEM26 field.                     */
57052   #define MEMCONF_POWER_RET_MEM26_Min (0x0UL)        /*!< Min enumerator value of MEM26 field.                                 */
57053   #define MEMCONF_POWER_RET_MEM26_Max (0x1UL)        /*!< Max enumerator value of MEM26 field.                                 */
57054   #define MEMCONF_POWER_RET_MEM26_Off (0x0UL)        /*!< Retention off                                                        */
57055   #define MEMCONF_POWER_RET_MEM26_On (0x1UL)         /*!< Retention on                                                         */
57056 
57057 /* MEM27 @Bit 27 : Keep the RAM block MEM[27] retained when the parent power domain of the RAM is off. */
57058   #define MEMCONF_POWER_RET_MEM27_Pos (27UL)         /*!< Position of MEM27 field.                                             */
57059   #define MEMCONF_POWER_RET_MEM27_Msk (0x1UL << MEMCONF_POWER_RET_MEM27_Pos) /*!< Bit mask of MEM27 field.                     */
57060   #define MEMCONF_POWER_RET_MEM27_Min (0x0UL)        /*!< Min enumerator value of MEM27 field.                                 */
57061   #define MEMCONF_POWER_RET_MEM27_Max (0x1UL)        /*!< Max enumerator value of MEM27 field.                                 */
57062   #define MEMCONF_POWER_RET_MEM27_Off (0x0UL)        /*!< Retention off                                                        */
57063   #define MEMCONF_POWER_RET_MEM27_On (0x1UL)         /*!< Retention on                                                         */
57064 
57065 /* MEM28 @Bit 28 : Keep the RAM block MEM[28] retained when the parent power domain of the RAM is off. */
57066   #define MEMCONF_POWER_RET_MEM28_Pos (28UL)         /*!< Position of MEM28 field.                                             */
57067   #define MEMCONF_POWER_RET_MEM28_Msk (0x1UL << MEMCONF_POWER_RET_MEM28_Pos) /*!< Bit mask of MEM28 field.                     */
57068   #define MEMCONF_POWER_RET_MEM28_Min (0x0UL)        /*!< Min enumerator value of MEM28 field.                                 */
57069   #define MEMCONF_POWER_RET_MEM28_Max (0x1UL)        /*!< Max enumerator value of MEM28 field.                                 */
57070   #define MEMCONF_POWER_RET_MEM28_Off (0x0UL)        /*!< Retention off                                                        */
57071   #define MEMCONF_POWER_RET_MEM28_On (0x1UL)         /*!< Retention on                                                         */
57072 
57073 /* MEM29 @Bit 29 : Keep the RAM block MEM[29] retained when the parent power domain of the RAM is off. */
57074   #define MEMCONF_POWER_RET_MEM29_Pos (29UL)         /*!< Position of MEM29 field.                                             */
57075   #define MEMCONF_POWER_RET_MEM29_Msk (0x1UL << MEMCONF_POWER_RET_MEM29_Pos) /*!< Bit mask of MEM29 field.                     */
57076   #define MEMCONF_POWER_RET_MEM29_Min (0x0UL)        /*!< Min enumerator value of MEM29 field.                                 */
57077   #define MEMCONF_POWER_RET_MEM29_Max (0x1UL)        /*!< Max enumerator value of MEM29 field.                                 */
57078   #define MEMCONF_POWER_RET_MEM29_Off (0x0UL)        /*!< Retention off                                                        */
57079   #define MEMCONF_POWER_RET_MEM29_On (0x1UL)         /*!< Retention on                                                         */
57080 
57081 /* MEM30 @Bit 30 : Keep the RAM block MEM[30] retained when the parent power domain of the RAM is off. */
57082   #define MEMCONF_POWER_RET_MEM30_Pos (30UL)         /*!< Position of MEM30 field.                                             */
57083   #define MEMCONF_POWER_RET_MEM30_Msk (0x1UL << MEMCONF_POWER_RET_MEM30_Pos) /*!< Bit mask of MEM30 field.                     */
57084   #define MEMCONF_POWER_RET_MEM30_Min (0x0UL)        /*!< Min enumerator value of MEM30 field.                                 */
57085   #define MEMCONF_POWER_RET_MEM30_Max (0x1UL)        /*!< Max enumerator value of MEM30 field.                                 */
57086   #define MEMCONF_POWER_RET_MEM30_Off (0x0UL)        /*!< Retention off                                                        */
57087   #define MEMCONF_POWER_RET_MEM30_On (0x1UL)         /*!< Retention on                                                         */
57088 
57089 /* MEM31 @Bit 31 : Keep the RAM block MEM[31] retained when the parent power domain of the RAM is off. */
57090   #define MEMCONF_POWER_RET_MEM31_Pos (31UL)         /*!< Position of MEM31 field.                                             */
57091   #define MEMCONF_POWER_RET_MEM31_Msk (0x1UL << MEMCONF_POWER_RET_MEM31_Pos) /*!< Bit mask of MEM31 field.                     */
57092   #define MEMCONF_POWER_RET_MEM31_Min (0x0UL)        /*!< Min enumerator value of MEM31 field.                                 */
57093   #define MEMCONF_POWER_RET_MEM31_Max (0x1UL)        /*!< Max enumerator value of MEM31 field.                                 */
57094   #define MEMCONF_POWER_RET_MEM31_Off (0x0UL)        /*!< Retention off                                                        */
57095   #define MEMCONF_POWER_RET_MEM31_On (0x1UL)         /*!< Retention on                                                         */
57096 
57097 
57098 /* MEMCONF_POWER_RET2: RAM retention for the second bank in the RAM block */
57099   #define MEMCONF_POWER_RET2_ResetValue (0x00000000UL) /*!< Reset value of RET2 register.                                      */
57100 
57101 /* MEM0 @Bit 0 : Keep the second bank in RAM block MEM[0] retained when parent power domain of the RAM is off. */
57102   #define MEMCONF_POWER_RET2_MEM0_Pos (0UL)          /*!< Position of MEM0 field.                                              */
57103   #define MEMCONF_POWER_RET2_MEM0_Msk (0x1UL << MEMCONF_POWER_RET2_MEM0_Pos) /*!< Bit mask of MEM0 field.                      */
57104   #define MEMCONF_POWER_RET2_MEM0_Min (0x0UL)        /*!< Min enumerator value of MEM0 field.                                  */
57105   #define MEMCONF_POWER_RET2_MEM0_Max (0x1UL)        /*!< Max enumerator value of MEM0 field.                                  */
57106   #define MEMCONF_POWER_RET2_MEM0_Off (0x0UL)        /*!< Retention off                                                        */
57107   #define MEMCONF_POWER_RET2_MEM0_On (0x1UL)         /*!< Retention on                                                         */
57108 
57109 /* MEM1 @Bit 1 : Keep the second bank in RAM block MEM[1] retained when parent power domain of the RAM is off. */
57110   #define MEMCONF_POWER_RET2_MEM1_Pos (1UL)          /*!< Position of MEM1 field.                                              */
57111   #define MEMCONF_POWER_RET2_MEM1_Msk (0x1UL << MEMCONF_POWER_RET2_MEM1_Pos) /*!< Bit mask of MEM1 field.                      */
57112   #define MEMCONF_POWER_RET2_MEM1_Min (0x0UL)        /*!< Min enumerator value of MEM1 field.                                  */
57113   #define MEMCONF_POWER_RET2_MEM1_Max (0x1UL)        /*!< Max enumerator value of MEM1 field.                                  */
57114   #define MEMCONF_POWER_RET2_MEM1_Off (0x0UL)        /*!< Retention off                                                        */
57115   #define MEMCONF_POWER_RET2_MEM1_On (0x1UL)         /*!< Retention on                                                         */
57116 
57117 /* MEM2 @Bit 2 : Keep the second bank in RAM block MEM[2] retained when parent power domain of the RAM is off. */
57118   #define MEMCONF_POWER_RET2_MEM2_Pos (2UL)          /*!< Position of MEM2 field.                                              */
57119   #define MEMCONF_POWER_RET2_MEM2_Msk (0x1UL << MEMCONF_POWER_RET2_MEM2_Pos) /*!< Bit mask of MEM2 field.                      */
57120   #define MEMCONF_POWER_RET2_MEM2_Min (0x0UL)        /*!< Min enumerator value of MEM2 field.                                  */
57121   #define MEMCONF_POWER_RET2_MEM2_Max (0x1UL)        /*!< Max enumerator value of MEM2 field.                                  */
57122   #define MEMCONF_POWER_RET2_MEM2_Off (0x0UL)        /*!< Retention off                                                        */
57123   #define MEMCONF_POWER_RET2_MEM2_On (0x1UL)         /*!< Retention on                                                         */
57124 
57125 /* MEM3 @Bit 3 : Keep the second bank in RAM block MEM[3] retained when parent power domain of the RAM is off. */
57126   #define MEMCONF_POWER_RET2_MEM3_Pos (3UL)          /*!< Position of MEM3 field.                                              */
57127   #define MEMCONF_POWER_RET2_MEM3_Msk (0x1UL << MEMCONF_POWER_RET2_MEM3_Pos) /*!< Bit mask of MEM3 field.                      */
57128   #define MEMCONF_POWER_RET2_MEM3_Min (0x0UL)        /*!< Min enumerator value of MEM3 field.                                  */
57129   #define MEMCONF_POWER_RET2_MEM3_Max (0x1UL)        /*!< Max enumerator value of MEM3 field.                                  */
57130   #define MEMCONF_POWER_RET2_MEM3_Off (0x0UL)        /*!< Retention off                                                        */
57131   #define MEMCONF_POWER_RET2_MEM3_On (0x1UL)         /*!< Retention on                                                         */
57132 
57133 /* MEM4 @Bit 4 : Keep the second bank in RAM block MEM[4] retained when parent power domain of the RAM is off. */
57134   #define MEMCONF_POWER_RET2_MEM4_Pos (4UL)          /*!< Position of MEM4 field.                                              */
57135   #define MEMCONF_POWER_RET2_MEM4_Msk (0x1UL << MEMCONF_POWER_RET2_MEM4_Pos) /*!< Bit mask of MEM4 field.                      */
57136   #define MEMCONF_POWER_RET2_MEM4_Min (0x0UL)        /*!< Min enumerator value of MEM4 field.                                  */
57137   #define MEMCONF_POWER_RET2_MEM4_Max (0x1UL)        /*!< Max enumerator value of MEM4 field.                                  */
57138   #define MEMCONF_POWER_RET2_MEM4_Off (0x0UL)        /*!< Retention off                                                        */
57139   #define MEMCONF_POWER_RET2_MEM4_On (0x1UL)         /*!< Retention on                                                         */
57140 
57141 /* MEM5 @Bit 5 : Keep the second bank in RAM block MEM[5] retained when parent power domain of the RAM is off. */
57142   #define MEMCONF_POWER_RET2_MEM5_Pos (5UL)          /*!< Position of MEM5 field.                                              */
57143   #define MEMCONF_POWER_RET2_MEM5_Msk (0x1UL << MEMCONF_POWER_RET2_MEM5_Pos) /*!< Bit mask of MEM5 field.                      */
57144   #define MEMCONF_POWER_RET2_MEM5_Min (0x0UL)        /*!< Min enumerator value of MEM5 field.                                  */
57145   #define MEMCONF_POWER_RET2_MEM5_Max (0x1UL)        /*!< Max enumerator value of MEM5 field.                                  */
57146   #define MEMCONF_POWER_RET2_MEM5_Off (0x0UL)        /*!< Retention off                                                        */
57147   #define MEMCONF_POWER_RET2_MEM5_On (0x1UL)         /*!< Retention on                                                         */
57148 
57149 /* MEM6 @Bit 6 : Keep the second bank in RAM block MEM[6] retained when parent power domain of the RAM is off. */
57150   #define MEMCONF_POWER_RET2_MEM6_Pos (6UL)          /*!< Position of MEM6 field.                                              */
57151   #define MEMCONF_POWER_RET2_MEM6_Msk (0x1UL << MEMCONF_POWER_RET2_MEM6_Pos) /*!< Bit mask of MEM6 field.                      */
57152   #define MEMCONF_POWER_RET2_MEM6_Min (0x0UL)        /*!< Min enumerator value of MEM6 field.                                  */
57153   #define MEMCONF_POWER_RET2_MEM6_Max (0x1UL)        /*!< Max enumerator value of MEM6 field.                                  */
57154   #define MEMCONF_POWER_RET2_MEM6_Off (0x0UL)        /*!< Retention off                                                        */
57155   #define MEMCONF_POWER_RET2_MEM6_On (0x1UL)         /*!< Retention on                                                         */
57156 
57157 /* MEM7 @Bit 7 : Keep the second bank in RAM block MEM[7] retained when parent power domain of the RAM is off. */
57158   #define MEMCONF_POWER_RET2_MEM7_Pos (7UL)          /*!< Position of MEM7 field.                                              */
57159   #define MEMCONF_POWER_RET2_MEM7_Msk (0x1UL << MEMCONF_POWER_RET2_MEM7_Pos) /*!< Bit mask of MEM7 field.                      */
57160   #define MEMCONF_POWER_RET2_MEM7_Min (0x0UL)        /*!< Min enumerator value of MEM7 field.                                  */
57161   #define MEMCONF_POWER_RET2_MEM7_Max (0x1UL)        /*!< Max enumerator value of MEM7 field.                                  */
57162   #define MEMCONF_POWER_RET2_MEM7_Off (0x0UL)        /*!< Retention off                                                        */
57163   #define MEMCONF_POWER_RET2_MEM7_On (0x1UL)         /*!< Retention on                                                         */
57164 
57165 /* MEM8 @Bit 8 : Keep the second bank in RAM block MEM[8] retained when parent power domain of the RAM is off. */
57166   #define MEMCONF_POWER_RET2_MEM8_Pos (8UL)          /*!< Position of MEM8 field.                                              */
57167   #define MEMCONF_POWER_RET2_MEM8_Msk (0x1UL << MEMCONF_POWER_RET2_MEM8_Pos) /*!< Bit mask of MEM8 field.                      */
57168   #define MEMCONF_POWER_RET2_MEM8_Min (0x0UL)        /*!< Min enumerator value of MEM8 field.                                  */
57169   #define MEMCONF_POWER_RET2_MEM8_Max (0x1UL)        /*!< Max enumerator value of MEM8 field.                                  */
57170   #define MEMCONF_POWER_RET2_MEM8_Off (0x0UL)        /*!< Retention off                                                        */
57171   #define MEMCONF_POWER_RET2_MEM8_On (0x1UL)         /*!< Retention on                                                         */
57172 
57173 /* MEM9 @Bit 9 : Keep the second bank in RAM block MEM[9] retained when parent power domain of the RAM is off. */
57174   #define MEMCONF_POWER_RET2_MEM9_Pos (9UL)          /*!< Position of MEM9 field.                                              */
57175   #define MEMCONF_POWER_RET2_MEM9_Msk (0x1UL << MEMCONF_POWER_RET2_MEM9_Pos) /*!< Bit mask of MEM9 field.                      */
57176   #define MEMCONF_POWER_RET2_MEM9_Min (0x0UL)        /*!< Min enumerator value of MEM9 field.                                  */
57177   #define MEMCONF_POWER_RET2_MEM9_Max (0x1UL)        /*!< Max enumerator value of MEM9 field.                                  */
57178   #define MEMCONF_POWER_RET2_MEM9_Off (0x0UL)        /*!< Retention off                                                        */
57179   #define MEMCONF_POWER_RET2_MEM9_On (0x1UL)         /*!< Retention on                                                         */
57180 
57181 /* MEM10 @Bit 10 : Keep the second bank in RAM block MEM[10] retained when parent power domain of the RAM is off. */
57182   #define MEMCONF_POWER_RET2_MEM10_Pos (10UL)        /*!< Position of MEM10 field.                                             */
57183   #define MEMCONF_POWER_RET2_MEM10_Msk (0x1UL << MEMCONF_POWER_RET2_MEM10_Pos) /*!< Bit mask of MEM10 field.                   */
57184   #define MEMCONF_POWER_RET2_MEM10_Min (0x0UL)       /*!< Min enumerator value of MEM10 field.                                 */
57185   #define MEMCONF_POWER_RET2_MEM10_Max (0x1UL)       /*!< Max enumerator value of MEM10 field.                                 */
57186   #define MEMCONF_POWER_RET2_MEM10_Off (0x0UL)       /*!< Retention off                                                        */
57187   #define MEMCONF_POWER_RET2_MEM10_On (0x1UL)        /*!< Retention on                                                         */
57188 
57189 /* MEM11 @Bit 11 : Keep the second bank in RAM block MEM[11] retained when parent power domain of the RAM is off. */
57190   #define MEMCONF_POWER_RET2_MEM11_Pos (11UL)        /*!< Position of MEM11 field.                                             */
57191   #define MEMCONF_POWER_RET2_MEM11_Msk (0x1UL << MEMCONF_POWER_RET2_MEM11_Pos) /*!< Bit mask of MEM11 field.                   */
57192   #define MEMCONF_POWER_RET2_MEM11_Min (0x0UL)       /*!< Min enumerator value of MEM11 field.                                 */
57193   #define MEMCONF_POWER_RET2_MEM11_Max (0x1UL)       /*!< Max enumerator value of MEM11 field.                                 */
57194   #define MEMCONF_POWER_RET2_MEM11_Off (0x0UL)       /*!< Retention off                                                        */
57195   #define MEMCONF_POWER_RET2_MEM11_On (0x1UL)        /*!< Retention on                                                         */
57196 
57197 /* MEM12 @Bit 12 : Keep the second bank in RAM block MEM[12] retained when parent power domain of the RAM is off. */
57198   #define MEMCONF_POWER_RET2_MEM12_Pos (12UL)        /*!< Position of MEM12 field.                                             */
57199   #define MEMCONF_POWER_RET2_MEM12_Msk (0x1UL << MEMCONF_POWER_RET2_MEM12_Pos) /*!< Bit mask of MEM12 field.                   */
57200   #define MEMCONF_POWER_RET2_MEM12_Min (0x0UL)       /*!< Min enumerator value of MEM12 field.                                 */
57201   #define MEMCONF_POWER_RET2_MEM12_Max (0x1UL)       /*!< Max enumerator value of MEM12 field.                                 */
57202   #define MEMCONF_POWER_RET2_MEM12_Off (0x0UL)       /*!< Retention off                                                        */
57203   #define MEMCONF_POWER_RET2_MEM12_On (0x1UL)        /*!< Retention on                                                         */
57204 
57205 /* MEM13 @Bit 13 : Keep the second bank in RAM block MEM[13] retained when parent power domain of the RAM is off. */
57206   #define MEMCONF_POWER_RET2_MEM13_Pos (13UL)        /*!< Position of MEM13 field.                                             */
57207   #define MEMCONF_POWER_RET2_MEM13_Msk (0x1UL << MEMCONF_POWER_RET2_MEM13_Pos) /*!< Bit mask of MEM13 field.                   */
57208   #define MEMCONF_POWER_RET2_MEM13_Min (0x0UL)       /*!< Min enumerator value of MEM13 field.                                 */
57209   #define MEMCONF_POWER_RET2_MEM13_Max (0x1UL)       /*!< Max enumerator value of MEM13 field.                                 */
57210   #define MEMCONF_POWER_RET2_MEM13_Off (0x0UL)       /*!< Retention off                                                        */
57211   #define MEMCONF_POWER_RET2_MEM13_On (0x1UL)        /*!< Retention on                                                         */
57212 
57213 /* MEM14 @Bit 14 : Keep the second bank in RAM block MEM[14] retained when parent power domain of the RAM is off. */
57214   #define MEMCONF_POWER_RET2_MEM14_Pos (14UL)        /*!< Position of MEM14 field.                                             */
57215   #define MEMCONF_POWER_RET2_MEM14_Msk (0x1UL << MEMCONF_POWER_RET2_MEM14_Pos) /*!< Bit mask of MEM14 field.                   */
57216   #define MEMCONF_POWER_RET2_MEM14_Min (0x0UL)       /*!< Min enumerator value of MEM14 field.                                 */
57217   #define MEMCONF_POWER_RET2_MEM14_Max (0x1UL)       /*!< Max enumerator value of MEM14 field.                                 */
57218   #define MEMCONF_POWER_RET2_MEM14_Off (0x0UL)       /*!< Retention off                                                        */
57219   #define MEMCONF_POWER_RET2_MEM14_On (0x1UL)        /*!< Retention on                                                         */
57220 
57221 /* MEM15 @Bit 15 : Keep the second bank in RAM block MEM[15] retained when parent power domain of the RAM is off. */
57222   #define MEMCONF_POWER_RET2_MEM15_Pos (15UL)        /*!< Position of MEM15 field.                                             */
57223   #define MEMCONF_POWER_RET2_MEM15_Msk (0x1UL << MEMCONF_POWER_RET2_MEM15_Pos) /*!< Bit mask of MEM15 field.                   */
57224   #define MEMCONF_POWER_RET2_MEM15_Min (0x0UL)       /*!< Min enumerator value of MEM15 field.                                 */
57225   #define MEMCONF_POWER_RET2_MEM15_Max (0x1UL)       /*!< Max enumerator value of MEM15 field.                                 */
57226   #define MEMCONF_POWER_RET2_MEM15_Off (0x0UL)       /*!< Retention off                                                        */
57227   #define MEMCONF_POWER_RET2_MEM15_On (0x1UL)        /*!< Retention on                                                         */
57228 
57229 /* MEM16 @Bit 16 : Keep the second bank in RAM block MEM[16] retained when parent power domain of the RAM is off. */
57230   #define MEMCONF_POWER_RET2_MEM16_Pos (16UL)        /*!< Position of MEM16 field.                                             */
57231   #define MEMCONF_POWER_RET2_MEM16_Msk (0x1UL << MEMCONF_POWER_RET2_MEM16_Pos) /*!< Bit mask of MEM16 field.                   */
57232   #define MEMCONF_POWER_RET2_MEM16_Min (0x0UL)       /*!< Min enumerator value of MEM16 field.                                 */
57233   #define MEMCONF_POWER_RET2_MEM16_Max (0x1UL)       /*!< Max enumerator value of MEM16 field.                                 */
57234   #define MEMCONF_POWER_RET2_MEM16_Off (0x0UL)       /*!< Retention off                                                        */
57235   #define MEMCONF_POWER_RET2_MEM16_On (0x1UL)        /*!< Retention on                                                         */
57236 
57237 /* MEM17 @Bit 17 : Keep the second bank in RAM block MEM[17] retained when parent power domain of the RAM is off. */
57238   #define MEMCONF_POWER_RET2_MEM17_Pos (17UL)        /*!< Position of MEM17 field.                                             */
57239   #define MEMCONF_POWER_RET2_MEM17_Msk (0x1UL << MEMCONF_POWER_RET2_MEM17_Pos) /*!< Bit mask of MEM17 field.                   */
57240   #define MEMCONF_POWER_RET2_MEM17_Min (0x0UL)       /*!< Min enumerator value of MEM17 field.                                 */
57241   #define MEMCONF_POWER_RET2_MEM17_Max (0x1UL)       /*!< Max enumerator value of MEM17 field.                                 */
57242   #define MEMCONF_POWER_RET2_MEM17_Off (0x0UL)       /*!< Retention off                                                        */
57243   #define MEMCONF_POWER_RET2_MEM17_On (0x1UL)        /*!< Retention on                                                         */
57244 
57245 /* MEM18 @Bit 18 : Keep the second bank in RAM block MEM[18] retained when parent power domain of the RAM is off. */
57246   #define MEMCONF_POWER_RET2_MEM18_Pos (18UL)        /*!< Position of MEM18 field.                                             */
57247   #define MEMCONF_POWER_RET2_MEM18_Msk (0x1UL << MEMCONF_POWER_RET2_MEM18_Pos) /*!< Bit mask of MEM18 field.                   */
57248   #define MEMCONF_POWER_RET2_MEM18_Min (0x0UL)       /*!< Min enumerator value of MEM18 field.                                 */
57249   #define MEMCONF_POWER_RET2_MEM18_Max (0x1UL)       /*!< Max enumerator value of MEM18 field.                                 */
57250   #define MEMCONF_POWER_RET2_MEM18_Off (0x0UL)       /*!< Retention off                                                        */
57251   #define MEMCONF_POWER_RET2_MEM18_On (0x1UL)        /*!< Retention on                                                         */
57252 
57253 /* MEM19 @Bit 19 : Keep the second bank in RAM block MEM[19] retained when parent power domain of the RAM is off. */
57254   #define MEMCONF_POWER_RET2_MEM19_Pos (19UL)        /*!< Position of MEM19 field.                                             */
57255   #define MEMCONF_POWER_RET2_MEM19_Msk (0x1UL << MEMCONF_POWER_RET2_MEM19_Pos) /*!< Bit mask of MEM19 field.                   */
57256   #define MEMCONF_POWER_RET2_MEM19_Min (0x0UL)       /*!< Min enumerator value of MEM19 field.                                 */
57257   #define MEMCONF_POWER_RET2_MEM19_Max (0x1UL)       /*!< Max enumerator value of MEM19 field.                                 */
57258   #define MEMCONF_POWER_RET2_MEM19_Off (0x0UL)       /*!< Retention off                                                        */
57259   #define MEMCONF_POWER_RET2_MEM19_On (0x1UL)        /*!< Retention on                                                         */
57260 
57261 /* MEM20 @Bit 20 : Keep the second bank in RAM block MEM[20] retained when parent power domain of the RAM is off. */
57262   #define MEMCONF_POWER_RET2_MEM20_Pos (20UL)        /*!< Position of MEM20 field.                                             */
57263   #define MEMCONF_POWER_RET2_MEM20_Msk (0x1UL << MEMCONF_POWER_RET2_MEM20_Pos) /*!< Bit mask of MEM20 field.                   */
57264   #define MEMCONF_POWER_RET2_MEM20_Min (0x0UL)       /*!< Min enumerator value of MEM20 field.                                 */
57265   #define MEMCONF_POWER_RET2_MEM20_Max (0x1UL)       /*!< Max enumerator value of MEM20 field.                                 */
57266   #define MEMCONF_POWER_RET2_MEM20_Off (0x0UL)       /*!< Retention off                                                        */
57267   #define MEMCONF_POWER_RET2_MEM20_On (0x1UL)        /*!< Retention on                                                         */
57268 
57269 /* MEM21 @Bit 21 : Keep the second bank in RAM block MEM[21] retained when parent power domain of the RAM is off. */
57270   #define MEMCONF_POWER_RET2_MEM21_Pos (21UL)        /*!< Position of MEM21 field.                                             */
57271   #define MEMCONF_POWER_RET2_MEM21_Msk (0x1UL << MEMCONF_POWER_RET2_MEM21_Pos) /*!< Bit mask of MEM21 field.                   */
57272   #define MEMCONF_POWER_RET2_MEM21_Min (0x0UL)       /*!< Min enumerator value of MEM21 field.                                 */
57273   #define MEMCONF_POWER_RET2_MEM21_Max (0x1UL)       /*!< Max enumerator value of MEM21 field.                                 */
57274   #define MEMCONF_POWER_RET2_MEM21_Off (0x0UL)       /*!< Retention off                                                        */
57275   #define MEMCONF_POWER_RET2_MEM21_On (0x1UL)        /*!< Retention on                                                         */
57276 
57277 /* MEM22 @Bit 22 : Keep the second bank in RAM block MEM[22] retained when parent power domain of the RAM is off. */
57278   #define MEMCONF_POWER_RET2_MEM22_Pos (22UL)        /*!< Position of MEM22 field.                                             */
57279   #define MEMCONF_POWER_RET2_MEM22_Msk (0x1UL << MEMCONF_POWER_RET2_MEM22_Pos) /*!< Bit mask of MEM22 field.                   */
57280   #define MEMCONF_POWER_RET2_MEM22_Min (0x0UL)       /*!< Min enumerator value of MEM22 field.                                 */
57281   #define MEMCONF_POWER_RET2_MEM22_Max (0x1UL)       /*!< Max enumerator value of MEM22 field.                                 */
57282   #define MEMCONF_POWER_RET2_MEM22_Off (0x0UL)       /*!< Retention off                                                        */
57283   #define MEMCONF_POWER_RET2_MEM22_On (0x1UL)        /*!< Retention on                                                         */
57284 
57285 /* MEM23 @Bit 23 : Keep the second bank in RAM block MEM[23] retained when parent power domain of the RAM is off. */
57286   #define MEMCONF_POWER_RET2_MEM23_Pos (23UL)        /*!< Position of MEM23 field.                                             */
57287   #define MEMCONF_POWER_RET2_MEM23_Msk (0x1UL << MEMCONF_POWER_RET2_MEM23_Pos) /*!< Bit mask of MEM23 field.                   */
57288   #define MEMCONF_POWER_RET2_MEM23_Min (0x0UL)       /*!< Min enumerator value of MEM23 field.                                 */
57289   #define MEMCONF_POWER_RET2_MEM23_Max (0x1UL)       /*!< Max enumerator value of MEM23 field.                                 */
57290   #define MEMCONF_POWER_RET2_MEM23_Off (0x0UL)       /*!< Retention off                                                        */
57291   #define MEMCONF_POWER_RET2_MEM23_On (0x1UL)        /*!< Retention on                                                         */
57292 
57293 /* MEM24 @Bit 24 : Keep the second bank in RAM block MEM[24] retained when parent power domain of the RAM is off. */
57294   #define MEMCONF_POWER_RET2_MEM24_Pos (24UL)        /*!< Position of MEM24 field.                                             */
57295   #define MEMCONF_POWER_RET2_MEM24_Msk (0x1UL << MEMCONF_POWER_RET2_MEM24_Pos) /*!< Bit mask of MEM24 field.                   */
57296   #define MEMCONF_POWER_RET2_MEM24_Min (0x0UL)       /*!< Min enumerator value of MEM24 field.                                 */
57297   #define MEMCONF_POWER_RET2_MEM24_Max (0x1UL)       /*!< Max enumerator value of MEM24 field.                                 */
57298   #define MEMCONF_POWER_RET2_MEM24_Off (0x0UL)       /*!< Retention off                                                        */
57299   #define MEMCONF_POWER_RET2_MEM24_On (0x1UL)        /*!< Retention on                                                         */
57300 
57301 /* MEM25 @Bit 25 : Keep the second bank in RAM block MEM[25] retained when parent power domain of the RAM is off. */
57302   #define MEMCONF_POWER_RET2_MEM25_Pos (25UL)        /*!< Position of MEM25 field.                                             */
57303   #define MEMCONF_POWER_RET2_MEM25_Msk (0x1UL << MEMCONF_POWER_RET2_MEM25_Pos) /*!< Bit mask of MEM25 field.                   */
57304   #define MEMCONF_POWER_RET2_MEM25_Min (0x0UL)       /*!< Min enumerator value of MEM25 field.                                 */
57305   #define MEMCONF_POWER_RET2_MEM25_Max (0x1UL)       /*!< Max enumerator value of MEM25 field.                                 */
57306   #define MEMCONF_POWER_RET2_MEM25_Off (0x0UL)       /*!< Retention off                                                        */
57307   #define MEMCONF_POWER_RET2_MEM25_On (0x1UL)        /*!< Retention on                                                         */
57308 
57309 /* MEM26 @Bit 26 : Keep the second bank in RAM block MEM[26] retained when parent power domain of the RAM is off. */
57310   #define MEMCONF_POWER_RET2_MEM26_Pos (26UL)        /*!< Position of MEM26 field.                                             */
57311   #define MEMCONF_POWER_RET2_MEM26_Msk (0x1UL << MEMCONF_POWER_RET2_MEM26_Pos) /*!< Bit mask of MEM26 field.                   */
57312   #define MEMCONF_POWER_RET2_MEM26_Min (0x0UL)       /*!< Min enumerator value of MEM26 field.                                 */
57313   #define MEMCONF_POWER_RET2_MEM26_Max (0x1UL)       /*!< Max enumerator value of MEM26 field.                                 */
57314   #define MEMCONF_POWER_RET2_MEM26_Off (0x0UL)       /*!< Retention off                                                        */
57315   #define MEMCONF_POWER_RET2_MEM26_On (0x1UL)        /*!< Retention on                                                         */
57316 
57317 /* MEM27 @Bit 27 : Keep the second bank in RAM block MEM[27] retained when parent power domain of the RAM is off. */
57318   #define MEMCONF_POWER_RET2_MEM27_Pos (27UL)        /*!< Position of MEM27 field.                                             */
57319   #define MEMCONF_POWER_RET2_MEM27_Msk (0x1UL << MEMCONF_POWER_RET2_MEM27_Pos) /*!< Bit mask of MEM27 field.                   */
57320   #define MEMCONF_POWER_RET2_MEM27_Min (0x0UL)       /*!< Min enumerator value of MEM27 field.                                 */
57321   #define MEMCONF_POWER_RET2_MEM27_Max (0x1UL)       /*!< Max enumerator value of MEM27 field.                                 */
57322   #define MEMCONF_POWER_RET2_MEM27_Off (0x0UL)       /*!< Retention off                                                        */
57323   #define MEMCONF_POWER_RET2_MEM27_On (0x1UL)        /*!< Retention on                                                         */
57324 
57325 /* MEM28 @Bit 28 : Keep the second bank in RAM block MEM[28] retained when parent power domain of the RAM is off. */
57326   #define MEMCONF_POWER_RET2_MEM28_Pos (28UL)        /*!< Position of MEM28 field.                                             */
57327   #define MEMCONF_POWER_RET2_MEM28_Msk (0x1UL << MEMCONF_POWER_RET2_MEM28_Pos) /*!< Bit mask of MEM28 field.                   */
57328   #define MEMCONF_POWER_RET2_MEM28_Min (0x0UL)       /*!< Min enumerator value of MEM28 field.                                 */
57329   #define MEMCONF_POWER_RET2_MEM28_Max (0x1UL)       /*!< Max enumerator value of MEM28 field.                                 */
57330   #define MEMCONF_POWER_RET2_MEM28_Off (0x0UL)       /*!< Retention off                                                        */
57331   #define MEMCONF_POWER_RET2_MEM28_On (0x1UL)        /*!< Retention on                                                         */
57332 
57333 /* MEM29 @Bit 29 : Keep the second bank in RAM block MEM[29] retained when parent power domain of the RAM is off. */
57334   #define MEMCONF_POWER_RET2_MEM29_Pos (29UL)        /*!< Position of MEM29 field.                                             */
57335   #define MEMCONF_POWER_RET2_MEM29_Msk (0x1UL << MEMCONF_POWER_RET2_MEM29_Pos) /*!< Bit mask of MEM29 field.                   */
57336   #define MEMCONF_POWER_RET2_MEM29_Min (0x0UL)       /*!< Min enumerator value of MEM29 field.                                 */
57337   #define MEMCONF_POWER_RET2_MEM29_Max (0x1UL)       /*!< Max enumerator value of MEM29 field.                                 */
57338   #define MEMCONF_POWER_RET2_MEM29_Off (0x0UL)       /*!< Retention off                                                        */
57339   #define MEMCONF_POWER_RET2_MEM29_On (0x1UL)        /*!< Retention on                                                         */
57340 
57341 /* MEM30 @Bit 30 : Keep the second bank in RAM block MEM[30] retained when parent power domain of the RAM is off. */
57342   #define MEMCONF_POWER_RET2_MEM30_Pos (30UL)        /*!< Position of MEM30 field.                                             */
57343   #define MEMCONF_POWER_RET2_MEM30_Msk (0x1UL << MEMCONF_POWER_RET2_MEM30_Pos) /*!< Bit mask of MEM30 field.                   */
57344   #define MEMCONF_POWER_RET2_MEM30_Min (0x0UL)       /*!< Min enumerator value of MEM30 field.                                 */
57345   #define MEMCONF_POWER_RET2_MEM30_Max (0x1UL)       /*!< Max enumerator value of MEM30 field.                                 */
57346   #define MEMCONF_POWER_RET2_MEM30_Off (0x0UL)       /*!< Retention off                                                        */
57347   #define MEMCONF_POWER_RET2_MEM30_On (0x1UL)        /*!< Retention on                                                         */
57348 
57349 /* MEM31 @Bit 31 : Keep the second bank in RAM block MEM[31] retained when parent power domain of the RAM is off. */
57350   #define MEMCONF_POWER_RET2_MEM31_Pos (31UL)        /*!< Position of MEM31 field.                                             */
57351   #define MEMCONF_POWER_RET2_MEM31_Msk (0x1UL << MEMCONF_POWER_RET2_MEM31_Pos) /*!< Bit mask of MEM31 field.                   */
57352   #define MEMCONF_POWER_RET2_MEM31_Min (0x0UL)       /*!< Min enumerator value of MEM31 field.                                 */
57353   #define MEMCONF_POWER_RET2_MEM31_Max (0x1UL)       /*!< Max enumerator value of MEM31 field.                                 */
57354   #define MEMCONF_POWER_RET2_MEM31_Off (0x0UL)       /*!< Retention off                                                        */
57355   #define MEMCONF_POWER_RET2_MEM31_On (0x1UL)        /*!< Retention on                                                         */
57356 
57357 
57358 
57359 /* ================================================== Struct MEMCONF_REPAIR ================================================== */
57360 /**
57361   * @brief REPAIR [MEMCONF_REPAIR] (unspecified)
57362   */
57363 typedef struct {
57364   __IOM uint32_t  BITLINE;                           /*!< (@ 0x00000000) Repair configuration for RAM blocks.                  */
57365 } NRF_MEMCONF_REPAIR_Type;                           /*!< Size = 4 (0x004)                                                     */
57366   #define MEMCONF_REPAIR_MaxCount (192UL)            /*!< Size of REPAIR[192] array.                                           */
57367   #define MEMCONF_REPAIR_MaxIndex (191UL)            /*!< Max index of REPAIR[192] array.                                      */
57368   #define MEMCONF_REPAIR_MinIndex (0UL)              /*!< Min index of REPAIR[192] array.                                      */
57369 
57370 /* MEMCONF_REPAIR_BITLINE: Repair configuration for RAM blocks. */
57371   #define MEMCONF_REPAIR_BITLINE_ResetValue (0x00000000UL) /*!< Reset value of BITLINE register.                               */
57372 
57373 /* ADDR @Bits 0..6 : Repair address of the bitline */
57374   #define MEMCONF_REPAIR_BITLINE_ADDR_Pos (0UL)      /*!< Position of ADDR field.                                              */
57375   #define MEMCONF_REPAIR_BITLINE_ADDR_Msk (0x7FUL << MEMCONF_REPAIR_BITLINE_ADDR_Pos) /*!< Bit mask of ADDR field.             */
57376 
57377 /* EN @Bit 31 : Enable bitline repair */
57378   #define MEMCONF_REPAIR_BITLINE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
57379   #define MEMCONF_REPAIR_BITLINE_EN_Msk (0x1UL << MEMCONF_REPAIR_BITLINE_EN_Pos) /*!< Bit mask of EN field.                    */
57380   #define MEMCONF_REPAIR_BITLINE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
57381   #define MEMCONF_REPAIR_BITLINE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
57382   #define MEMCONF_REPAIR_BITLINE_EN_Disabled (0x0UL) /*!< Repair disabled.                                                     */
57383   #define MEMCONF_REPAIR_BITLINE_EN_Enabled (0x1UL)  /*!< Repair enabled.                                                      */
57384 
57385 
57386 
57387 /* ================================================ Struct MEMCONF_BLOCKTYPE ================================================= */
57388 /**
57389   * @brief BLOCKTYPE [MEMCONF_BLOCKTYPE] (unspecified)
57390   */
57391 typedef struct {
57392   __IOM uint32_t  TRIM;                              /*!< (@ 0x00000000) Trim configuration for the memory block types.        */
57393 } NRF_MEMCONF_BLOCKTYPE_Type;                        /*!< Size = 4 (0x004)                                                     */
57394   #define MEMCONF_BLOCKTYPE_MaxCount (64UL)          /*!< Size of BLOCKTYPE[64] array.                                         */
57395   #define MEMCONF_BLOCKTYPE_MaxIndex (63UL)          /*!< Max index of BLOCKTYPE[64] array.                                    */
57396   #define MEMCONF_BLOCKTYPE_MinIndex (0UL)           /*!< Min index of BLOCKTYPE[64] array.                                    */
57397 
57398 /* MEMCONF_BLOCKTYPE_TRIM: Trim configuration for the memory block types. */
57399   #define MEMCONF_BLOCKTYPE_TRIM_ResetValue (0x00000000UL) /*!< Reset value of TRIM register.                                  */
57400 
57401 /* MEMTRIM0 @Bit 0 : Read/write margin trim. */
57402   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Pos (0UL)  /*!< Position of MEMTRIM0 field.                                          */
57403   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM0_Pos) /*!< Bit mask of MEMTRIM0 field.  */
57404 
57405 /* MEMTRIM1 @Bit 1 : Read/write margin trim. */
57406   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM1_Pos (1UL)  /*!< Position of MEMTRIM1 field.                                          */
57407   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM1_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM1_Pos) /*!< Bit mask of MEMTRIM1 field.  */
57408 
57409 /* MEMTRIM2 @Bit 2 : Read/write margin trim. */
57410   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM2_Pos (2UL)  /*!< Position of MEMTRIM2 field.                                          */
57411   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM2_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM2_Pos) /*!< Bit mask of MEMTRIM2 field.  */
57412 
57413 /* MEMTRIM3 @Bit 3 : Read/write margin trim. */
57414   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM3_Pos (3UL)  /*!< Position of MEMTRIM3 field.                                          */
57415   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM3_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM3_Pos) /*!< Bit mask of MEMTRIM3 field.  */
57416 
57417 /* MEMTRIM4 @Bit 4 : Read/write margin trim. */
57418   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM4_Pos (4UL)  /*!< Position of MEMTRIM4 field.                                          */
57419   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM4_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM4_Pos) /*!< Bit mask of MEMTRIM4 field.  */
57420 
57421 /* MEMTRIM5 @Bit 5 : Read/write margin trim. */
57422   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM5_Pos (5UL)  /*!< Position of MEMTRIM5 field.                                          */
57423   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM5_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM5_Pos) /*!< Bit mask of MEMTRIM5 field.  */
57424 
57425 /* MEMTRIM6 @Bit 6 : Read/write margin trim. */
57426   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM6_Pos (6UL)  /*!< Position of MEMTRIM6 field.                                          */
57427   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM6_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM6_Pos) /*!< Bit mask of MEMTRIM6 field.  */
57428 
57429 /* MEMTRIM7 @Bit 7 : Read/write margin trim. */
57430   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM7_Pos (7UL)  /*!< Position of MEMTRIM7 field.                                          */
57431   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM7_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM7_Pos) /*!< Bit mask of MEMTRIM7 field.  */
57432 
57433 /* MEMTRIM8 @Bit 8 : Read/write margin trim. */
57434   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM8_Pos (8UL)  /*!< Position of MEMTRIM8 field.                                          */
57435   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM8_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM8_Pos) /*!< Bit mask of MEMTRIM8 field.  */
57436 
57437 /* MEMTRIM9 @Bit 9 : Read/write margin trim. */
57438   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM9_Pos (9UL)  /*!< Position of MEMTRIM9 field.                                          */
57439   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM9_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM9_Pos) /*!< Bit mask of MEMTRIM9 field.  */
57440 
57441 /* MEMTRIM10 @Bit 10 : Read/write margin trim. */
57442   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM10_Pos (10UL) /*!< Position of MEMTRIM10 field.                                        */
57443   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM10_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM10_Pos) /*!< Bit mask of MEMTRIM10
57444                                                                             field.*/
57445 
57446 /* MEMTRIM11 @Bit 11 : Read/write margin trim. */
57447   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM11_Pos (11UL) /*!< Position of MEMTRIM11 field.                                        */
57448   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM11_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM11_Pos) /*!< Bit mask of MEMTRIM11
57449                                                                             field.*/
57450 
57451 /* MEMTRIM12 @Bit 12 : Read/write margin trim. */
57452   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM12_Pos (12UL) /*!< Position of MEMTRIM12 field.                                        */
57453   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM12_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM12_Pos) /*!< Bit mask of MEMTRIM12
57454                                                                             field.*/
57455 
57456 /* MEMTRIM13 @Bit 13 : Read/write margin trim. */
57457   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM13_Pos (13UL) /*!< Position of MEMTRIM13 field.                                        */
57458   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM13_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM13_Pos) /*!< Bit mask of MEMTRIM13
57459                                                                             field.*/
57460 
57461 /* MEMTRIM14 @Bit 14 : Read/write margin trim. */
57462   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM14_Pos (14UL) /*!< Position of MEMTRIM14 field.                                        */
57463   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM14_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM14_Pos) /*!< Bit mask of MEMTRIM14
57464                                                                             field.*/
57465 
57466 /* MEMTRIM15 @Bit 15 : Read/write margin trim. */
57467   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM15_Pos (15UL) /*!< Position of MEMTRIM15 field.                                        */
57468   #define MEMCONF_BLOCKTYPE_TRIM_MEMTRIM15_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMTRIM15_Pos) /*!< Bit mask of MEMTRIM15
57469                                                                             field.*/
57470 
57471 /* MEMRETTRIM0 @Bit 16 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57472   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Pos (16UL) /*!< Position of MEMRETTRIM0 field.                                    */
57473   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM0_Pos) /*!< Bit mask of MEMRETTRIM0
57474                                                                             field.*/
57475 
57476 /* MEMRETTRIM1 @Bit 17 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57477   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM1_Pos (17UL) /*!< Position of MEMRETTRIM1 field.                                    */
57478   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM1_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM1_Pos) /*!< Bit mask of MEMRETTRIM1
57479                                                                             field.*/
57480 
57481 /* MEMRETTRIM2 @Bit 18 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57482   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM2_Pos (18UL) /*!< Position of MEMRETTRIM2 field.                                    */
57483   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM2_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM2_Pos) /*!< Bit mask of MEMRETTRIM2
57484                                                                             field.*/
57485 
57486 /* MEMRETTRIM3 @Bit 19 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57487   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM3_Pos (19UL) /*!< Position of MEMRETTRIM3 field.                                    */
57488   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM3_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM3_Pos) /*!< Bit mask of MEMRETTRIM3
57489                                                                             field.*/
57490 
57491 /* MEMRETTRIM4 @Bit 20 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57492   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM4_Pos (20UL) /*!< Position of MEMRETTRIM4 field.                                    */
57493   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM4_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM4_Pos) /*!< Bit mask of MEMRETTRIM4
57494                                                                             field.*/
57495 
57496 /* MEMRETTRIM5 @Bit 21 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57497   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM5_Pos (21UL) /*!< Position of MEMRETTRIM5 field.                                    */
57498   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM5_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM5_Pos) /*!< Bit mask of MEMRETTRIM5
57499                                                                             field.*/
57500 
57501 /* MEMRETTRIM6 @Bit 22 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57502   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM6_Pos (22UL) /*!< Position of MEMRETTRIM6 field.                                    */
57503   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM6_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM6_Pos) /*!< Bit mask of MEMRETTRIM6
57504                                                                             field.*/
57505 
57506 /* MEMRETTRIM7 @Bit 23 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57507   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM7_Pos (23UL) /*!< Position of MEMRETTRIM7 field.                                    */
57508   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM7_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM7_Pos) /*!< Bit mask of MEMRETTRIM7
57509                                                                             field.*/
57510 
57511 /* MEMRETTRIM8 @Bit 24 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57512   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM8_Pos (24UL) /*!< Position of MEMRETTRIM8 field.                                    */
57513   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM8_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM8_Pos) /*!< Bit mask of MEMRETTRIM8
57514                                                                             field.*/
57515 
57516 /* MEMRETTRIM9 @Bit 25 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57517   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM9_Pos (25UL) /*!< Position of MEMRETTRIM9 field.                                    */
57518   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM9_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM9_Pos) /*!< Bit mask of MEMRETTRIM9
57519                                                                             field.*/
57520 
57521 /* MEMRETTRIM10 @Bit 26 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57522   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM10_Pos (26UL) /*!< Position of MEMRETTRIM10 field.                                  */
57523   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM10_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM10_Pos) /*!< Bit mask of
57524                                                                             MEMRETTRIM10 field.*/
57525 
57526 /* MEMRETTRIM11 @Bit 27 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57527   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM11_Pos (27UL) /*!< Position of MEMRETTRIM11 field.                                  */
57528   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM11_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM11_Pos) /*!< Bit mask of
57529                                                                             MEMRETTRIM11 field.*/
57530 
57531 /* MEMRETTRIM12 @Bit 28 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57532   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM12_Pos (28UL) /*!< Position of MEMRETTRIM12 field.                                  */
57533   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM12_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM12_Pos) /*!< Bit mask of
57534                                                                             MEMRETTRIM12 field.*/
57535 
57536 /* MEMRETTRIM13 @Bit 29 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57537   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM13_Pos (29UL) /*!< Position of MEMRETTRIM13 field.                                  */
57538   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM13_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM13_Pos) /*!< Bit mask of
57539                                                                             MEMRETTRIM13 field.*/
57540 
57541 /* MEMRETTRIM14 @Bit 30 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57542   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM14_Pos (30UL) /*!< Position of MEMRETTRIM14 field.                                  */
57543   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM14_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM14_Pos) /*!< Bit mask of
57544                                                                             MEMRETTRIM14 field.*/
57545 
57546 /* MEMRETTRIM15 @Bit 31 : Trimming for retention mode for decreased leakage. Must be kept active in RAM retention mode. */
57547   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM15_Pos (31UL) /*!< Position of MEMRETTRIM15 field.                                  */
57548   #define MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM15_Msk (0x1UL << MEMCONF_BLOCKTYPE_TRIM_MEMRETTRIM15_Pos) /*!< Bit mask of
57549                                                                             MEMRETTRIM15 field.*/
57550 
57551 
57552 /* ===================================================== Struct MEMCONF ====================================================== */
57553 /**
57554   * @brief Memory configuration
57555   */
57556   typedef struct {                                   /*!< MEMCONF Structure                                                    */
57557     __IM uint32_t RESERVED[320];
57558     __IOM NRF_MEMCONF_POWER_Type POWER[2];           /*!< (@ 0x00000500) (unspecified)                                         */
57559     __IM uint32_t RESERVED1[56];
57560     __IOM NRF_MEMCONF_REPAIR_Type REPAIR[192];       /*!< (@ 0x00000600) (unspecified)                                         */
57561     __IOM NRF_MEMCONF_BLOCKTYPE_Type BLOCKTYPE[64];  /*!< (@ 0x00000900) (unspecified)                                         */
57562   } NRF_MEMCONF_Type;                                /*!< Size = 2560 (0xA00)                                                  */
57563 
57564 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
57565 
57566 /* =========================================================================================================================== */
57567 /* ================                                            MPC                                            ================ */
57568 /* =========================================================================================================================== */
57569 
57570 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
57571 
57572 /* ================================================== Struct MPC_MEMACCERR =================================================== */
57573 /**
57574   * @brief MEMACCERR [MPC_MEMACCERR] Memory Access Error status registers
57575   */
57576 typedef struct {
57577   __IM  uint32_t  ADDRESS;                           /*!< (@ 0x00000000) Target Address of Memory Access Error. Register content
57578                                                                          won't be changed as long as MEMACCERR event is active.*/
57579   __IM  uint32_t  INFO;                              /*!< (@ 0x00000004) Access information for the transaction that triggered a
57580                                                                          memory access error. Register content won't be changed
57581                                                                          as long as MEMACCERR event is active.*/
57582 } NRF_MPC_MEMACCERR_Type;                            /*!< Size = 8 (0x008)                                                     */
57583 
57584 /* MPC_MEMACCERR_ADDRESS: Target Address of Memory Access Error. Register content won't be changed as long as MEMACCERR event is
57585                            active. */
57586 
57587   #define MPC_MEMACCERR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register.                                */
57588 
57589 /* ADDRESS @Bits 0..31 : Target address for erroneous access */
57590   #define MPC_MEMACCERR_ADDRESS_ADDRESS_Pos (0UL)    /*!< Position of ADDRESS field.                                           */
57591   #define MPC_MEMACCERR_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << MPC_MEMACCERR_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.*/
57592 
57593 
57594 /* MPC_MEMACCERR_INFO: Access information for the transaction that triggered a memory access error. Register content won't be
57595                         changed as long as MEMACCERR event is active. */
57596 
57597   #define MPC_MEMACCERR_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register.                                      */
57598 
57599 /* OWNERID @Bits 0..3 : Owner identifier of the erroneous access */
57600   #define MPC_MEMACCERR_INFO_OWNERID_Pos (0UL)       /*!< Position of OWNERID field.                                           */
57601   #define MPC_MEMACCERR_INFO_OWNERID_Msk (0xFUL << MPC_MEMACCERR_INFO_OWNERID_Pos) /*!< Bit mask of OWNERID field.             */
57602   #define MPC_MEMACCERR_INFO_OWNERID_Min (0x0UL)     /*!< Min value of OWNERID field.                                          */
57603   #define MPC_MEMACCERR_INFO_OWNERID_Max (0xFUL)     /*!< Max size of OWNERID field.                                           */
57604 
57605 /* MASTERPORT @Bits 4..8 : Master port where erroneous access is detected */
57606   #define MPC_MEMACCERR_INFO_MASTERPORT_Pos (4UL)    /*!< Position of MASTERPORT field.                                        */
57607   #define MPC_MEMACCERR_INFO_MASTERPORT_Msk (0x1FUL << MPC_MEMACCERR_INFO_MASTERPORT_Pos) /*!< Bit mask of MASTERPORT field.   */
57608   #define MPC_MEMACCERR_INFO_MASTERPORT_Min (0x0UL)  /*!< Min value of MASTERPORT field.                                       */
57609   #define MPC_MEMACCERR_INFO_MASTERPORT_Max (0x1FUL) /*!< Max size of MASTERPORT field.                                        */
57610 
57611 /* READ @Bit 12 : Read bit of bus access */
57612   #define MPC_MEMACCERR_INFO_READ_Pos (12UL)         /*!< Position of READ field.                                              */
57613   #define MPC_MEMACCERR_INFO_READ_Msk (0x1UL << MPC_MEMACCERR_INFO_READ_Pos) /*!< Bit mask of READ field.                      */
57614   #define MPC_MEMACCERR_INFO_READ_Min (0x0UL)        /*!< Min enumerator value of READ field.                                  */
57615   #define MPC_MEMACCERR_INFO_READ_Max (0x1UL)        /*!< Max enumerator value of READ field.                                  */
57616   #define MPC_MEMACCERR_INFO_READ_Set (0x1UL)        /*!< Read access bit was set                                              */
57617   #define MPC_MEMACCERR_INFO_READ_NotSet (0x0UL)     /*!< Read access bit was not set                                          */
57618 
57619 /* WRITE @Bit 13 : Write bit of bus access */
57620   #define MPC_MEMACCERR_INFO_WRITE_Pos (13UL)        /*!< Position of WRITE field.                                             */
57621   #define MPC_MEMACCERR_INFO_WRITE_Msk (0x1UL << MPC_MEMACCERR_INFO_WRITE_Pos) /*!< Bit mask of WRITE field.                   */
57622   #define MPC_MEMACCERR_INFO_WRITE_Min (0x0UL)       /*!< Min enumerator value of WRITE field.                                 */
57623   #define MPC_MEMACCERR_INFO_WRITE_Max (0x1UL)       /*!< Max enumerator value of WRITE field.                                 */
57624   #define MPC_MEMACCERR_INFO_WRITE_Set (0x1UL)       /*!< Write access bit was set                                             */
57625   #define MPC_MEMACCERR_INFO_WRITE_NotSet (0x0UL)    /*!< Write access bit was not set                                         */
57626 
57627 /* EXECUTE @Bit 14 : Execute bit of bus access */
57628   #define MPC_MEMACCERR_INFO_EXECUTE_Pos (14UL)      /*!< Position of EXECUTE field.                                           */
57629   #define MPC_MEMACCERR_INFO_EXECUTE_Msk (0x1UL << MPC_MEMACCERR_INFO_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.             */
57630   #define MPC_MEMACCERR_INFO_EXECUTE_Min (0x0UL)     /*!< Min enumerator value of EXECUTE field.                               */
57631   #define MPC_MEMACCERR_INFO_EXECUTE_Max (0x1UL)     /*!< Max enumerator value of EXECUTE field.                               */
57632   #define MPC_MEMACCERR_INFO_EXECUTE_Set (0x1UL)     /*!< Execute access bit was set                                           */
57633   #define MPC_MEMACCERR_INFO_EXECUTE_NotSet (0x0UL)  /*!< Execute access bit was not set                                       */
57634 
57635 /* SECURE @Bit 15 : Secure bit of bus access */
57636   #define MPC_MEMACCERR_INFO_SECURE_Pos (15UL)       /*!< Position of SECURE field.                                            */
57637   #define MPC_MEMACCERR_INFO_SECURE_Msk (0x1UL << MPC_MEMACCERR_INFO_SECURE_Pos) /*!< Bit mask of SECURE field.                */
57638   #define MPC_MEMACCERR_INFO_SECURE_Min (0x0UL)      /*!< Min enumerator value of SECURE field.                                */
57639   #define MPC_MEMACCERR_INFO_SECURE_Max (0x1UL)      /*!< Max enumerator value of SECURE field.                                */
57640   #define MPC_MEMACCERR_INFO_SECURE_Set (0x1UL)      /*!< Secure access bit was set                                            */
57641   #define MPC_MEMACCERR_INFO_SECURE_NotSet (0x0UL)   /*!< Secure access bit was not set                                        */
57642 
57643 /* ERRORSOURCE @Bit 16 : Source of memory access error */
57644   #define MPC_MEMACCERR_INFO_ERRORSOURCE_Pos (16UL)  /*!< Position of ERRORSOURCE field.                                       */
57645   #define MPC_MEMACCERR_INFO_ERRORSOURCE_Msk (0x1UL << MPC_MEMACCERR_INFO_ERRORSOURCE_Pos) /*!< Bit mask of ERRORSOURCE field. */
57646   #define MPC_MEMACCERR_INFO_ERRORSOURCE_Min (0x0UL) /*!< Min enumerator value of ERRORSOURCE field.                           */
57647   #define MPC_MEMACCERR_INFO_ERRORSOURCE_Max (0x1UL) /*!< Max enumerator value of ERRORSOURCE field.                           */
57648   #define MPC_MEMACCERR_INFO_ERRORSOURCE_MPC (0x1UL) /*!< Error was triggered by MPC module                                    */
57649   #define MPC_MEMACCERR_INFO_ERRORSOURCE_Slave (0x0UL) /*!< Error was triggered by an AXI slave                                */
57650 
57651 
57652 
57653 /* ================================================= Struct MPC_GLOBALSLAVE ================================================== */
57654 /**
57655   * @brief GLOBALSLAVE [MPC_GLOBALSLAVE] Global slave master port connection information
57656   */
57657 typedef struct {
57658   __IOM uint32_t  MASTERPORT;                        /*!< (@ 0x00000000) Global slave connection information for master port   */
57659   __IOM uint32_t  LOCK;                              /*!< (@ 0x00000004) Lock global slave registers                           */
57660 } NRF_MPC_GLOBALSLAVE_Type;                          /*!< Size = 8 (0x008)                                                     */
57661 
57662 /* MPC_GLOBALSLAVE_MASTERPORT: Global slave connection information for master port */
57663   #define MPC_GLOBALSLAVE_MASTERPORT_ResetValue (0x00000000UL) /*!< Reset value of MASTERPORT register.                        */
57664 
57665 /* CONNECTION0 @Bit 0 : Global slave connection information for master port */
57666   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Pos (0UL) /*!< Position of CONNECTION0 field.                                 */
57667   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Pos) /*!< Bit mask of
57668                                                                             CONNECTION0 field.*/
57669   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Min (0x0UL) /*!< Min enumerator value of CONNECTION0 field.                   */
57670   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Max (0x1UL) /*!< Max enumerator value of CONNECTION0 field.                   */
57671   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Disabled (0x0UL) /*!< Master port 0 connection to global slave is disabled    */
57672   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION0_Enabled (0x1UL) /*!< Master port 0 connection to global slave is enabled      */
57673 
57674 /* CONNECTION1 @Bit 1 : Global slave connection information for master port */
57675   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Pos (1UL) /*!< Position of CONNECTION1 field.                                 */
57676   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Pos) /*!< Bit mask of
57677                                                                             CONNECTION1 field.*/
57678   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Min (0x0UL) /*!< Min enumerator value of CONNECTION1 field.                   */
57679   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Max (0x1UL) /*!< Max enumerator value of CONNECTION1 field.                   */
57680   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Disabled (0x0UL) /*!< Master port 1 connection to global slave is disabled    */
57681   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION1_Enabled (0x1UL) /*!< Master port 1 connection to global slave is enabled      */
57682 
57683 /* CONNECTION2 @Bit 2 : Global slave connection information for master port */
57684   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Pos (2UL) /*!< Position of CONNECTION2 field.                                 */
57685   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Pos) /*!< Bit mask of
57686                                                                             CONNECTION2 field.*/
57687   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Min (0x0UL) /*!< Min enumerator value of CONNECTION2 field.                   */
57688   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Max (0x1UL) /*!< Max enumerator value of CONNECTION2 field.                   */
57689   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Disabled (0x0UL) /*!< Master port 2 connection to global slave is disabled    */
57690   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION2_Enabled (0x1UL) /*!< Master port 2 connection to global slave is enabled      */
57691 
57692 /* CONNECTION3 @Bit 3 : Global slave connection information for master port */
57693   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Pos (3UL) /*!< Position of CONNECTION3 field.                                 */
57694   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Pos) /*!< Bit mask of
57695                                                                             CONNECTION3 field.*/
57696   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Min (0x0UL) /*!< Min enumerator value of CONNECTION3 field.                   */
57697   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Max (0x1UL) /*!< Max enumerator value of CONNECTION3 field.                   */
57698   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Disabled (0x0UL) /*!< Master port 3 connection to global slave is disabled    */
57699   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION3_Enabled (0x1UL) /*!< Master port 3 connection to global slave is enabled      */
57700 
57701 /* CONNECTION4 @Bit 4 : Global slave connection information for master port */
57702   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Pos (4UL) /*!< Position of CONNECTION4 field.                                 */
57703   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Pos) /*!< Bit mask of
57704                                                                             CONNECTION4 field.*/
57705   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Min (0x0UL) /*!< Min enumerator value of CONNECTION4 field.                   */
57706   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Max (0x1UL) /*!< Max enumerator value of CONNECTION4 field.                   */
57707   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Disabled (0x0UL) /*!< Master port 4 connection to global slave is disabled    */
57708   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION4_Enabled (0x1UL) /*!< Master port 4 connection to global slave is enabled      */
57709 
57710 /* CONNECTION5 @Bit 5 : Global slave connection information for master port */
57711   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Pos (5UL) /*!< Position of CONNECTION5 field.                                 */
57712   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Pos) /*!< Bit mask of
57713                                                                             CONNECTION5 field.*/
57714   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Min (0x0UL) /*!< Min enumerator value of CONNECTION5 field.                   */
57715   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Max (0x1UL) /*!< Max enumerator value of CONNECTION5 field.                   */
57716   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Disabled (0x0UL) /*!< Master port 5 connection to global slave is disabled    */
57717   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION5_Enabled (0x1UL) /*!< Master port 5 connection to global slave is enabled      */
57718 
57719 /* CONNECTION6 @Bit 6 : Global slave connection information for master port */
57720   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Pos (6UL) /*!< Position of CONNECTION6 field.                                 */
57721   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Pos) /*!< Bit mask of
57722                                                                             CONNECTION6 field.*/
57723   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Min (0x0UL) /*!< Min enumerator value of CONNECTION6 field.                   */
57724   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Max (0x1UL) /*!< Max enumerator value of CONNECTION6 field.                   */
57725   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Disabled (0x0UL) /*!< Master port 6 connection to global slave is disabled    */
57726   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION6_Enabled (0x1UL) /*!< Master port 6 connection to global slave is enabled      */
57727 
57728 /* CONNECTION7 @Bit 7 : Global slave connection information for master port */
57729   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Pos (7UL) /*!< Position of CONNECTION7 field.                                 */
57730   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Pos) /*!< Bit mask of
57731                                                                             CONNECTION7 field.*/
57732   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Min (0x0UL) /*!< Min enumerator value of CONNECTION7 field.                   */
57733   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Max (0x1UL) /*!< Max enumerator value of CONNECTION7 field.                   */
57734   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Disabled (0x0UL) /*!< Master port 7 connection to global slave is disabled    */
57735   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION7_Enabled (0x1UL) /*!< Master port 7 connection to global slave is enabled      */
57736 
57737 /* CONNECTION8 @Bit 8 : Global slave connection information for master port */
57738   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Pos (8UL) /*!< Position of CONNECTION8 field.                                 */
57739   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Pos) /*!< Bit mask of
57740                                                                             CONNECTION8 field.*/
57741   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Min (0x0UL) /*!< Min enumerator value of CONNECTION8 field.                   */
57742   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Max (0x1UL) /*!< Max enumerator value of CONNECTION8 field.                   */
57743   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Disabled (0x0UL) /*!< Master port 8 connection to global slave is disabled    */
57744   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION8_Enabled (0x1UL) /*!< Master port 8 connection to global slave is enabled      */
57745 
57746 /* CONNECTION9 @Bit 9 : Global slave connection information for master port */
57747   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Pos (9UL) /*!< Position of CONNECTION9 field.                                 */
57748   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Pos) /*!< Bit mask of
57749                                                                             CONNECTION9 field.*/
57750   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Min (0x0UL) /*!< Min enumerator value of CONNECTION9 field.                   */
57751   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Max (0x1UL) /*!< Max enumerator value of CONNECTION9 field.                   */
57752   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Disabled (0x0UL) /*!< Master port 9 connection to global slave is disabled    */
57753   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION9_Enabled (0x1UL) /*!< Master port 9 connection to global slave is enabled      */
57754 
57755 /* CONNECTION10 @Bit 10 : Global slave connection information for master port */
57756   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Pos (10UL) /*!< Position of CONNECTION10 field.                              */
57757   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Pos) /*!< Bit mask of
57758                                                                             CONNECTION10 field.*/
57759   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Min (0x0UL) /*!< Min enumerator value of CONNECTION10 field.                 */
57760   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Max (0x1UL) /*!< Max enumerator value of CONNECTION10 field.                 */
57761   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Disabled (0x0UL) /*!< Master port 10 connection to global slave is disabled  */
57762   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION10_Enabled (0x1UL) /*!< Master port 10 connection to global slave is enabled    */
57763 
57764 /* CONNECTION11 @Bit 11 : Global slave connection information for master port */
57765   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Pos (11UL) /*!< Position of CONNECTION11 field.                              */
57766   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Pos) /*!< Bit mask of
57767                                                                             CONNECTION11 field.*/
57768   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Min (0x0UL) /*!< Min enumerator value of CONNECTION11 field.                 */
57769   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Max (0x1UL) /*!< Max enumerator value of CONNECTION11 field.                 */
57770   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Disabled (0x0UL) /*!< Master port 11 connection to global slave is disabled  */
57771   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION11_Enabled (0x1UL) /*!< Master port 11 connection to global slave is enabled    */
57772 
57773 /* CONNECTION12 @Bit 12 : Global slave connection information for master port */
57774   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Pos (12UL) /*!< Position of CONNECTION12 field.                              */
57775   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Pos) /*!< Bit mask of
57776                                                                             CONNECTION12 field.*/
57777   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Min (0x0UL) /*!< Min enumerator value of CONNECTION12 field.                 */
57778   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Max (0x1UL) /*!< Max enumerator value of CONNECTION12 field.                 */
57779   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Disabled (0x0UL) /*!< Master port 12 connection to global slave is disabled  */
57780   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION12_Enabled (0x1UL) /*!< Master port 12 connection to global slave is enabled    */
57781 
57782 /* CONNECTION13 @Bit 13 : Global slave connection information for master port */
57783   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Pos (13UL) /*!< Position of CONNECTION13 field.                              */
57784   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Pos) /*!< Bit mask of
57785                                                                             CONNECTION13 field.*/
57786   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Min (0x0UL) /*!< Min enumerator value of CONNECTION13 field.                 */
57787   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Max (0x1UL) /*!< Max enumerator value of CONNECTION13 field.                 */
57788   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Disabled (0x0UL) /*!< Master port 13 connection to global slave is disabled  */
57789   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION13_Enabled (0x1UL) /*!< Master port 13 connection to global slave is enabled    */
57790 
57791 /* CONNECTION14 @Bit 14 : Global slave connection information for master port */
57792   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Pos (14UL) /*!< Position of CONNECTION14 field.                              */
57793   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Pos) /*!< Bit mask of
57794                                                                             CONNECTION14 field.*/
57795   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Min (0x0UL) /*!< Min enumerator value of CONNECTION14 field.                 */
57796   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Max (0x1UL) /*!< Max enumerator value of CONNECTION14 field.                 */
57797   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Disabled (0x0UL) /*!< Master port 14 connection to global slave is disabled  */
57798   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION14_Enabled (0x1UL) /*!< Master port 14 connection to global slave is enabled    */
57799 
57800 /* CONNECTION15 @Bit 15 : Global slave connection information for master port */
57801   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Pos (15UL) /*!< Position of CONNECTION15 field.                              */
57802   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Pos) /*!< Bit mask of
57803                                                                             CONNECTION15 field.*/
57804   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Min (0x0UL) /*!< Min enumerator value of CONNECTION15 field.                 */
57805   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Max (0x1UL) /*!< Max enumerator value of CONNECTION15 field.                 */
57806   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Disabled (0x0UL) /*!< Master port 15 connection to global slave is disabled  */
57807   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION15_Enabled (0x1UL) /*!< Master port 15 connection to global slave is enabled    */
57808 
57809 /* CONNECTION16 @Bit 16 : Global slave connection information for master port */
57810   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Pos (16UL) /*!< Position of CONNECTION16 field.                              */
57811   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Pos) /*!< Bit mask of
57812                                                                             CONNECTION16 field.*/
57813   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Min (0x0UL) /*!< Min enumerator value of CONNECTION16 field.                 */
57814   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Max (0x1UL) /*!< Max enumerator value of CONNECTION16 field.                 */
57815   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Disabled (0x0UL) /*!< Master port 16 connection to global slave is disabled  */
57816   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION16_Enabled (0x1UL) /*!< Master port 16 connection to global slave is enabled    */
57817 
57818 /* CONNECTION17 @Bit 17 : Global slave connection information for master port */
57819   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Pos (17UL) /*!< Position of CONNECTION17 field.                              */
57820   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Pos) /*!< Bit mask of
57821                                                                             CONNECTION17 field.*/
57822   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Min (0x0UL) /*!< Min enumerator value of CONNECTION17 field.                 */
57823   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Max (0x1UL) /*!< Max enumerator value of CONNECTION17 field.                 */
57824   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Disabled (0x0UL) /*!< Master port 17 connection to global slave is disabled  */
57825   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION17_Enabled (0x1UL) /*!< Master port 17 connection to global slave is enabled    */
57826 
57827 /* CONNECTION18 @Bit 18 : Global slave connection information for master port */
57828   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Pos (18UL) /*!< Position of CONNECTION18 field.                              */
57829   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Pos) /*!< Bit mask of
57830                                                                             CONNECTION18 field.*/
57831   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Min (0x0UL) /*!< Min enumerator value of CONNECTION18 field.                 */
57832   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Max (0x1UL) /*!< Max enumerator value of CONNECTION18 field.                 */
57833   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Disabled (0x0UL) /*!< Master port 18 connection to global slave is disabled  */
57834   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION18_Enabled (0x1UL) /*!< Master port 18 connection to global slave is enabled    */
57835 
57836 /* CONNECTION19 @Bit 19 : Global slave connection information for master port */
57837   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Pos (19UL) /*!< Position of CONNECTION19 field.                              */
57838   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Pos) /*!< Bit mask of
57839                                                                             CONNECTION19 field.*/
57840   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Min (0x0UL) /*!< Min enumerator value of CONNECTION19 field.                 */
57841   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Max (0x1UL) /*!< Max enumerator value of CONNECTION19 field.                 */
57842   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Disabled (0x0UL) /*!< Master port 19 connection to global slave is disabled  */
57843   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION19_Enabled (0x1UL) /*!< Master port 19 connection to global slave is enabled    */
57844 
57845 /* CONNECTION20 @Bit 20 : Global slave connection information for master port */
57846   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Pos (20UL) /*!< Position of CONNECTION20 field.                              */
57847   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Pos) /*!< Bit mask of
57848                                                                             CONNECTION20 field.*/
57849   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Min (0x0UL) /*!< Min enumerator value of CONNECTION20 field.                 */
57850   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Max (0x1UL) /*!< Max enumerator value of CONNECTION20 field.                 */
57851   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Disabled (0x0UL) /*!< Master port 20 connection to global slave is disabled  */
57852   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION20_Enabled (0x1UL) /*!< Master port 20 connection to global slave is enabled    */
57853 
57854 /* CONNECTION21 @Bit 21 : Global slave connection information for master port */
57855   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Pos (21UL) /*!< Position of CONNECTION21 field.                              */
57856   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Pos) /*!< Bit mask of
57857                                                                             CONNECTION21 field.*/
57858   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Min (0x0UL) /*!< Min enumerator value of CONNECTION21 field.                 */
57859   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Max (0x1UL) /*!< Max enumerator value of CONNECTION21 field.                 */
57860   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Disabled (0x0UL) /*!< Master port 21 connection to global slave is disabled  */
57861   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION21_Enabled (0x1UL) /*!< Master port 21 connection to global slave is enabled    */
57862 
57863 /* CONNECTION22 @Bit 22 : Global slave connection information for master port */
57864   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Pos (22UL) /*!< Position of CONNECTION22 field.                              */
57865   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Pos) /*!< Bit mask of
57866                                                                             CONNECTION22 field.*/
57867   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Min (0x0UL) /*!< Min enumerator value of CONNECTION22 field.                 */
57868   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Max (0x1UL) /*!< Max enumerator value of CONNECTION22 field.                 */
57869   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Disabled (0x0UL) /*!< Master port 22 connection to global slave is disabled  */
57870   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION22_Enabled (0x1UL) /*!< Master port 22 connection to global slave is enabled    */
57871 
57872 /* CONNECTION23 @Bit 23 : Global slave connection information for master port */
57873   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Pos (23UL) /*!< Position of CONNECTION23 field.                              */
57874   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Pos) /*!< Bit mask of
57875                                                                             CONNECTION23 field.*/
57876   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Min (0x0UL) /*!< Min enumerator value of CONNECTION23 field.                 */
57877   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Max (0x1UL) /*!< Max enumerator value of CONNECTION23 field.                 */
57878   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Disabled (0x0UL) /*!< Master port 23 connection to global slave is disabled  */
57879   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION23_Enabled (0x1UL) /*!< Master port 23 connection to global slave is enabled    */
57880 
57881 /* CONNECTION24 @Bit 24 : Global slave connection information for master port */
57882   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Pos (24UL) /*!< Position of CONNECTION24 field.                              */
57883   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Pos) /*!< Bit mask of
57884                                                                             CONNECTION24 field.*/
57885   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Min (0x0UL) /*!< Min enumerator value of CONNECTION24 field.                 */
57886   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Max (0x1UL) /*!< Max enumerator value of CONNECTION24 field.                 */
57887   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Disabled (0x0UL) /*!< Master port 24 connection to global slave is disabled  */
57888   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION24_Enabled (0x1UL) /*!< Master port 24 connection to global slave is enabled    */
57889 
57890 /* CONNECTION25 @Bit 25 : Global slave connection information for master port */
57891   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Pos (25UL) /*!< Position of CONNECTION25 field.                              */
57892   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Pos) /*!< Bit mask of
57893                                                                             CONNECTION25 field.*/
57894   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Min (0x0UL) /*!< Min enumerator value of CONNECTION25 field.                 */
57895   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Max (0x1UL) /*!< Max enumerator value of CONNECTION25 field.                 */
57896   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Disabled (0x0UL) /*!< Master port 25 connection to global slave is disabled  */
57897   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION25_Enabled (0x1UL) /*!< Master port 25 connection to global slave is enabled    */
57898 
57899 /* CONNECTION26 @Bit 26 : Global slave connection information for master port */
57900   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Pos (26UL) /*!< Position of CONNECTION26 field.                              */
57901   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Pos) /*!< Bit mask of
57902                                                                             CONNECTION26 field.*/
57903   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Min (0x0UL) /*!< Min enumerator value of CONNECTION26 field.                 */
57904   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Max (0x1UL) /*!< Max enumerator value of CONNECTION26 field.                 */
57905   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Disabled (0x0UL) /*!< Master port 26 connection to global slave is disabled  */
57906   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION26_Enabled (0x1UL) /*!< Master port 26 connection to global slave is enabled    */
57907 
57908 /* CONNECTION27 @Bit 27 : Global slave connection information for master port */
57909   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Pos (27UL) /*!< Position of CONNECTION27 field.                              */
57910   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Pos) /*!< Bit mask of
57911                                                                             CONNECTION27 field.*/
57912   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Min (0x0UL) /*!< Min enumerator value of CONNECTION27 field.                 */
57913   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Max (0x1UL) /*!< Max enumerator value of CONNECTION27 field.                 */
57914   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Disabled (0x0UL) /*!< Master port 27 connection to global slave is disabled  */
57915   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION27_Enabled (0x1UL) /*!< Master port 27 connection to global slave is enabled    */
57916 
57917 /* CONNECTION28 @Bit 28 : Global slave connection information for master port */
57918   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Pos (28UL) /*!< Position of CONNECTION28 field.                              */
57919   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Pos) /*!< Bit mask of
57920                                                                             CONNECTION28 field.*/
57921   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Min (0x0UL) /*!< Min enumerator value of CONNECTION28 field.                 */
57922   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Max (0x1UL) /*!< Max enumerator value of CONNECTION28 field.                 */
57923   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Disabled (0x0UL) /*!< Master port 28 connection to global slave is disabled  */
57924   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION28_Enabled (0x1UL) /*!< Master port 28 connection to global slave is enabled    */
57925 
57926 /* CONNECTION29 @Bit 29 : Global slave connection information for master port */
57927   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Pos (29UL) /*!< Position of CONNECTION29 field.                              */
57928   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Pos) /*!< Bit mask of
57929                                                                             CONNECTION29 field.*/
57930   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Min (0x0UL) /*!< Min enumerator value of CONNECTION29 field.                 */
57931   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Max (0x1UL) /*!< Max enumerator value of CONNECTION29 field.                 */
57932   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Disabled (0x0UL) /*!< Master port 29 connection to global slave is disabled  */
57933   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION29_Enabled (0x1UL) /*!< Master port 29 connection to global slave is enabled    */
57934 
57935 /* CONNECTION30 @Bit 30 : Global slave connection information for master port */
57936   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Pos (30UL) /*!< Position of CONNECTION30 field.                              */
57937   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Pos) /*!< Bit mask of
57938                                                                             CONNECTION30 field.*/
57939   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Min (0x0UL) /*!< Min enumerator value of CONNECTION30 field.                 */
57940   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Max (0x1UL) /*!< Max enumerator value of CONNECTION30 field.                 */
57941   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Disabled (0x0UL) /*!< Master port 30 connection to global slave is disabled  */
57942   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION30_Enabled (0x1UL) /*!< Master port 30 connection to global slave is enabled    */
57943 
57944 /* CONNECTION31 @Bit 31 : Global slave connection information for master port */
57945   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Pos (31UL) /*!< Position of CONNECTION31 field.                              */
57946   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Msk (0x1UL << MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Pos) /*!< Bit mask of
57947                                                                             CONNECTION31 field.*/
57948   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Min (0x0UL) /*!< Min enumerator value of CONNECTION31 field.                 */
57949   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Max (0x1UL) /*!< Max enumerator value of CONNECTION31 field.                 */
57950   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Disabled (0x0UL) /*!< Master port 31 connection to global slave is disabled  */
57951   #define MPC_GLOBALSLAVE_MASTERPORT_CONNECTION31_Enabled (0x1UL) /*!< Master port 31 connection to global slave is enabled    */
57952 
57953 
57954 /* MPC_GLOBALSLAVE_LOCK: Lock global slave registers */
57955   #define MPC_GLOBALSLAVE_LOCK_ResetValue (0x00000000UL) /*!< Reset value of LOCK register.                                    */
57956 
57957 /* LOCK @Bit 0 : Enable lock */
57958   #define MPC_GLOBALSLAVE_LOCK_LOCK_Pos (0UL)        /*!< Position of LOCK field.                                              */
57959   #define MPC_GLOBALSLAVE_LOCK_LOCK_Msk (0x1UL << MPC_GLOBALSLAVE_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field.                  */
57960   #define MPC_GLOBALSLAVE_LOCK_LOCK_Min (0x0UL)      /*!< Min enumerator value of LOCK field.                                  */
57961   #define MPC_GLOBALSLAVE_LOCK_LOCK_Max (0x1UL)      /*!< Max enumerator value of LOCK field.                                  */
57962   #define MPC_GLOBALSLAVE_LOCK_LOCK_Disabled (0x0UL) /*!< Lock disabled.                                                       */
57963   #define MPC_GLOBALSLAVE_LOCK_LOCK_Enabled (0x1UL)  /*!< Lock enabled.                                                        */
57964 
57965 
57966 
57967 /* =================================================== Struct MPC_RTCHOKE ==================================================== */
57968 /**
57969   * @brief RTCHOKE [MPC_RTCHOKE] Real time choke configuration for AXI master port
57970   */
57971 typedef struct {
57972   __IOM uint32_t  WRITEACCESS;                       /*!< (@ 0x00000000) Enable AXI Write Address Channel Real Time Choke for
57973                                                                          master port*/
57974   __IOM uint32_t  READACCESS;                        /*!< (@ 0x00000004) Enable AXI Read Address Channel Real Time Choke for
57975                                                                          master port*/
57976   __IM  uint32_t  RESERVED[22];
57977   __IOM uint32_t  DELAY[32];                         /*!< (@ 0x00000060) Real Time Choke delay value for slave number n        */
57978 } NRF_MPC_RTCHOKE_Type;                              /*!< Size = 224 (0x0E0)                                                   */
57979 
57980 /* MPC_RTCHOKE_WRITEACCESS: Enable AXI Write Address Channel Real Time Choke for master port */
57981   #define MPC_RTCHOKE_WRITEACCESS_ResetValue (0x00000000UL) /*!< Reset value of WRITEACCESS register.                          */
57982 
57983 /* ENABLE0 @Bit 0 : Enable Real Time Choke for Write Address Channel */
57984   #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Pos (0UL)  /*!< Position of ENABLE0 field.                                           */
57985   #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field.   */
57986   #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field.                              */
57987   #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field.                              */
57988   #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 0 Write Address
57989                                                                Channel*/
57990   #define MPC_RTCHOKE_WRITEACCESS_ENABLE0_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 0 Write Address
57991                                                               Channel*/
57992 
57993 /* ENABLE1 @Bit 1 : Enable Real Time Choke for Write Address Channel */
57994   #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Pos (1UL)  /*!< Position of ENABLE1 field.                                           */
57995   #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field.   */
57996   #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field.                              */
57997   #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field.                              */
57998   #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 1 Write Address
57999                                                                Channel*/
58000   #define MPC_RTCHOKE_WRITEACCESS_ENABLE1_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 1 Write Address
58001                                                               Channel*/
58002 
58003 /* ENABLE2 @Bit 2 : Enable Real Time Choke for Write Address Channel */
58004   #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Pos (2UL)  /*!< Position of ENABLE2 field.                                           */
58005   #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field.   */
58006   #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field.                              */
58007   #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field.                              */
58008   #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 2 Write Address
58009                                                                Channel*/
58010   #define MPC_RTCHOKE_WRITEACCESS_ENABLE2_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 2 Write Address
58011                                                               Channel*/
58012 
58013 /* ENABLE3 @Bit 3 : Enable Real Time Choke for Write Address Channel */
58014   #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Pos (3UL)  /*!< Position of ENABLE3 field.                                           */
58015   #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field.   */
58016   #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field.                              */
58017   #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field.                              */
58018   #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 3 Write Address
58019                                                                Channel*/
58020   #define MPC_RTCHOKE_WRITEACCESS_ENABLE3_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 3 Write Address
58021                                                               Channel*/
58022 
58023 /* ENABLE4 @Bit 4 : Enable Real Time Choke for Write Address Channel */
58024   #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Pos (4UL)  /*!< Position of ENABLE4 field.                                           */
58025   #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE4_Pos) /*!< Bit mask of ENABLE4 field.   */
58026   #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Min (0x0UL) /*!< Min enumerator value of ENABLE4 field.                              */
58027   #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Max (0x1UL) /*!< Max enumerator value of ENABLE4 field.                              */
58028   #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 4 Write Address
58029                                                                Channel*/
58030   #define MPC_RTCHOKE_WRITEACCESS_ENABLE4_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 4 Write Address
58031                                                               Channel*/
58032 
58033 /* ENABLE5 @Bit 5 : Enable Real Time Choke for Write Address Channel */
58034   #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Pos (5UL)  /*!< Position of ENABLE5 field.                                           */
58035   #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE5_Pos) /*!< Bit mask of ENABLE5 field.   */
58036   #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Min (0x0UL) /*!< Min enumerator value of ENABLE5 field.                              */
58037   #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Max (0x1UL) /*!< Max enumerator value of ENABLE5 field.                              */
58038   #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 5 Write Address
58039                                                                Channel*/
58040   #define MPC_RTCHOKE_WRITEACCESS_ENABLE5_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 5 Write Address
58041                                                               Channel*/
58042 
58043 /* ENABLE6 @Bit 6 : Enable Real Time Choke for Write Address Channel */
58044   #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Pos (6UL)  /*!< Position of ENABLE6 field.                                           */
58045   #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE6_Pos) /*!< Bit mask of ENABLE6 field.   */
58046   #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Min (0x0UL) /*!< Min enumerator value of ENABLE6 field.                              */
58047   #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Max (0x1UL) /*!< Max enumerator value of ENABLE6 field.                              */
58048   #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 6 Write Address
58049                                                                Channel*/
58050   #define MPC_RTCHOKE_WRITEACCESS_ENABLE6_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 6 Write Address
58051                                                               Channel*/
58052 
58053 /* ENABLE7 @Bit 7 : Enable Real Time Choke for Write Address Channel */
58054   #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Pos (7UL)  /*!< Position of ENABLE7 field.                                           */
58055   #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE7_Pos) /*!< Bit mask of ENABLE7 field.   */
58056   #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Min (0x0UL) /*!< Min enumerator value of ENABLE7 field.                              */
58057   #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Max (0x1UL) /*!< Max enumerator value of ENABLE7 field.                              */
58058   #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 7 Write Address
58059                                                                Channel*/
58060   #define MPC_RTCHOKE_WRITEACCESS_ENABLE7_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 7 Write Address
58061                                                               Channel*/
58062 
58063 /* ENABLE8 @Bit 8 : Enable Real Time Choke for Write Address Channel */
58064   #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Pos (8UL)  /*!< Position of ENABLE8 field.                                           */
58065   #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE8_Pos) /*!< Bit mask of ENABLE8 field.   */
58066   #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Min (0x0UL) /*!< Min enumerator value of ENABLE8 field.                              */
58067   #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Max (0x1UL) /*!< Max enumerator value of ENABLE8 field.                              */
58068   #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 8 Write Address
58069                                                                Channel*/
58070   #define MPC_RTCHOKE_WRITEACCESS_ENABLE8_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 8 Write Address
58071                                                               Channel*/
58072 
58073 /* ENABLE9 @Bit 9 : Enable Real Time Choke for Write Address Channel */
58074   #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Pos (9UL)  /*!< Position of ENABLE9 field.                                           */
58075   #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE9_Pos) /*!< Bit mask of ENABLE9 field.   */
58076   #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Min (0x0UL) /*!< Min enumerator value of ENABLE9 field.                              */
58077   #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Max (0x1UL) /*!< Max enumerator value of ENABLE9 field.                              */
58078   #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 9 Write Address
58079                                                                Channel*/
58080   #define MPC_RTCHOKE_WRITEACCESS_ENABLE9_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 9 Write Address
58081                                                               Channel*/
58082 
58083 /* ENABLE10 @Bit 10 : Enable Real Time Choke for Write Address Channel */
58084   #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Pos (10UL) /*!< Position of ENABLE10 field.                                         */
58085   #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE10_Pos) /*!< Bit mask of ENABLE10 field.*/
58086   #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Min (0x0UL) /*!< Min enumerator value of ENABLE10 field.                            */
58087   #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Max (0x1UL) /*!< Max enumerator value of ENABLE10 field.                            */
58088   #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 10 Write Address
58089                                                                 Channel*/
58090   #define MPC_RTCHOKE_WRITEACCESS_ENABLE10_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 10 Write Address
58091                                                                Channel*/
58092 
58093 /* ENABLE11 @Bit 11 : Enable Real Time Choke for Write Address Channel */
58094   #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Pos (11UL) /*!< Position of ENABLE11 field.                                         */
58095   #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE11_Pos) /*!< Bit mask of ENABLE11 field.*/
58096   #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Min (0x0UL) /*!< Min enumerator value of ENABLE11 field.                            */
58097   #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Max (0x1UL) /*!< Max enumerator value of ENABLE11 field.                            */
58098   #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 11 Write Address
58099                                                                 Channel*/
58100   #define MPC_RTCHOKE_WRITEACCESS_ENABLE11_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 11 Write Address
58101                                                                Channel*/
58102 
58103 /* ENABLE12 @Bit 12 : Enable Real Time Choke for Write Address Channel */
58104   #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Pos (12UL) /*!< Position of ENABLE12 field.                                         */
58105   #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE12_Pos) /*!< Bit mask of ENABLE12 field.*/
58106   #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Min (0x0UL) /*!< Min enumerator value of ENABLE12 field.                            */
58107   #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Max (0x1UL) /*!< Max enumerator value of ENABLE12 field.                            */
58108   #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 12 Write Address
58109                                                                 Channel*/
58110   #define MPC_RTCHOKE_WRITEACCESS_ENABLE12_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 12 Write Address
58111                                                                Channel*/
58112 
58113 /* ENABLE13 @Bit 13 : Enable Real Time Choke for Write Address Channel */
58114   #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Pos (13UL) /*!< Position of ENABLE13 field.                                         */
58115   #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE13_Pos) /*!< Bit mask of ENABLE13 field.*/
58116   #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Min (0x0UL) /*!< Min enumerator value of ENABLE13 field.                            */
58117   #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Max (0x1UL) /*!< Max enumerator value of ENABLE13 field.                            */
58118   #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 13 Write Address
58119                                                                 Channel*/
58120   #define MPC_RTCHOKE_WRITEACCESS_ENABLE13_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 13 Write Address
58121                                                                Channel*/
58122 
58123 /* ENABLE14 @Bit 14 : Enable Real Time Choke for Write Address Channel */
58124   #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Pos (14UL) /*!< Position of ENABLE14 field.                                         */
58125   #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE14_Pos) /*!< Bit mask of ENABLE14 field.*/
58126   #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Min (0x0UL) /*!< Min enumerator value of ENABLE14 field.                            */
58127   #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Max (0x1UL) /*!< Max enumerator value of ENABLE14 field.                            */
58128   #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 14 Write Address
58129                                                                 Channel*/
58130   #define MPC_RTCHOKE_WRITEACCESS_ENABLE14_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 14 Write Address
58131                                                                Channel*/
58132 
58133 /* ENABLE15 @Bit 15 : Enable Real Time Choke for Write Address Channel */
58134   #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Pos (15UL) /*!< Position of ENABLE15 field.                                         */
58135   #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE15_Pos) /*!< Bit mask of ENABLE15 field.*/
58136   #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Min (0x0UL) /*!< Min enumerator value of ENABLE15 field.                            */
58137   #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Max (0x1UL) /*!< Max enumerator value of ENABLE15 field.                            */
58138   #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 15 Write Address
58139                                                                 Channel*/
58140   #define MPC_RTCHOKE_WRITEACCESS_ENABLE15_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 15 Write Address
58141                                                                Channel*/
58142 
58143 /* ENABLE16 @Bit 16 : Enable Real Time Choke for Write Address Channel */
58144   #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Pos (16UL) /*!< Position of ENABLE16 field.                                         */
58145   #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE16_Pos) /*!< Bit mask of ENABLE16 field.*/
58146   #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Min (0x0UL) /*!< Min enumerator value of ENABLE16 field.                            */
58147   #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Max (0x1UL) /*!< Max enumerator value of ENABLE16 field.                            */
58148   #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 16 Write Address
58149                                                                 Channel*/
58150   #define MPC_RTCHOKE_WRITEACCESS_ENABLE16_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 16 Write Address
58151                                                                Channel*/
58152 
58153 /* ENABLE17 @Bit 17 : Enable Real Time Choke for Write Address Channel */
58154   #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Pos (17UL) /*!< Position of ENABLE17 field.                                         */
58155   #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE17_Pos) /*!< Bit mask of ENABLE17 field.*/
58156   #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Min (0x0UL) /*!< Min enumerator value of ENABLE17 field.                            */
58157   #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Max (0x1UL) /*!< Max enumerator value of ENABLE17 field.                            */
58158   #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 17 Write Address
58159                                                                 Channel*/
58160   #define MPC_RTCHOKE_WRITEACCESS_ENABLE17_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 17 Write Address
58161                                                                Channel*/
58162 
58163 /* ENABLE18 @Bit 18 : Enable Real Time Choke for Write Address Channel */
58164   #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Pos (18UL) /*!< Position of ENABLE18 field.                                         */
58165   #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE18_Pos) /*!< Bit mask of ENABLE18 field.*/
58166   #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Min (0x0UL) /*!< Min enumerator value of ENABLE18 field.                            */
58167   #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Max (0x1UL) /*!< Max enumerator value of ENABLE18 field.                            */
58168   #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 18 Write Address
58169                                                                 Channel*/
58170   #define MPC_RTCHOKE_WRITEACCESS_ENABLE18_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 18 Write Address
58171                                                                Channel*/
58172 
58173 /* ENABLE19 @Bit 19 : Enable Real Time Choke for Write Address Channel */
58174   #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Pos (19UL) /*!< Position of ENABLE19 field.                                         */
58175   #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE19_Pos) /*!< Bit mask of ENABLE19 field.*/
58176   #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Min (0x0UL) /*!< Min enumerator value of ENABLE19 field.                            */
58177   #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Max (0x1UL) /*!< Max enumerator value of ENABLE19 field.                            */
58178   #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 19 Write Address
58179                                                                 Channel*/
58180   #define MPC_RTCHOKE_WRITEACCESS_ENABLE19_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 19 Write Address
58181                                                                Channel*/
58182 
58183 /* ENABLE20 @Bit 20 : Enable Real Time Choke for Write Address Channel */
58184   #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Pos (20UL) /*!< Position of ENABLE20 field.                                         */
58185   #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE20_Pos) /*!< Bit mask of ENABLE20 field.*/
58186   #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Min (0x0UL) /*!< Min enumerator value of ENABLE20 field.                            */
58187   #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Max (0x1UL) /*!< Max enumerator value of ENABLE20 field.                            */
58188   #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 20 Write Address
58189                                                                 Channel*/
58190   #define MPC_RTCHOKE_WRITEACCESS_ENABLE20_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 20 Write Address
58191                                                                Channel*/
58192 
58193 /* ENABLE21 @Bit 21 : Enable Real Time Choke for Write Address Channel */
58194   #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Pos (21UL) /*!< Position of ENABLE21 field.                                         */
58195   #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE21_Pos) /*!< Bit mask of ENABLE21 field.*/
58196   #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Min (0x0UL) /*!< Min enumerator value of ENABLE21 field.                            */
58197   #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Max (0x1UL) /*!< Max enumerator value of ENABLE21 field.                            */
58198   #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 21 Write Address
58199                                                                 Channel*/
58200   #define MPC_RTCHOKE_WRITEACCESS_ENABLE21_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 21 Write Address
58201                                                                Channel*/
58202 
58203 /* ENABLE22 @Bit 22 : Enable Real Time Choke for Write Address Channel */
58204   #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Pos (22UL) /*!< Position of ENABLE22 field.                                         */
58205   #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE22_Pos) /*!< Bit mask of ENABLE22 field.*/
58206   #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Min (0x0UL) /*!< Min enumerator value of ENABLE22 field.                            */
58207   #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Max (0x1UL) /*!< Max enumerator value of ENABLE22 field.                            */
58208   #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 22 Write Address
58209                                                                 Channel*/
58210   #define MPC_RTCHOKE_WRITEACCESS_ENABLE22_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 22 Write Address
58211                                                                Channel*/
58212 
58213 /* ENABLE23 @Bit 23 : Enable Real Time Choke for Write Address Channel */
58214   #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Pos (23UL) /*!< Position of ENABLE23 field.                                         */
58215   #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE23_Pos) /*!< Bit mask of ENABLE23 field.*/
58216   #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Min (0x0UL) /*!< Min enumerator value of ENABLE23 field.                            */
58217   #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Max (0x1UL) /*!< Max enumerator value of ENABLE23 field.                            */
58218   #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 23 Write Address
58219                                                                 Channel*/
58220   #define MPC_RTCHOKE_WRITEACCESS_ENABLE23_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 23 Write Address
58221                                                                Channel*/
58222 
58223 /* ENABLE24 @Bit 24 : Enable Real Time Choke for Write Address Channel */
58224   #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Pos (24UL) /*!< Position of ENABLE24 field.                                         */
58225   #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE24_Pos) /*!< Bit mask of ENABLE24 field.*/
58226   #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Min (0x0UL) /*!< Min enumerator value of ENABLE24 field.                            */
58227   #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Max (0x1UL) /*!< Max enumerator value of ENABLE24 field.                            */
58228   #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 24 Write Address
58229                                                                 Channel*/
58230   #define MPC_RTCHOKE_WRITEACCESS_ENABLE24_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 24 Write Address
58231                                                                Channel*/
58232 
58233 /* ENABLE25 @Bit 25 : Enable Real Time Choke for Write Address Channel */
58234   #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Pos (25UL) /*!< Position of ENABLE25 field.                                         */
58235   #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE25_Pos) /*!< Bit mask of ENABLE25 field.*/
58236   #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Min (0x0UL) /*!< Min enumerator value of ENABLE25 field.                            */
58237   #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Max (0x1UL) /*!< Max enumerator value of ENABLE25 field.                            */
58238   #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 25 Write Address
58239                                                                 Channel*/
58240   #define MPC_RTCHOKE_WRITEACCESS_ENABLE25_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 25 Write Address
58241                                                                Channel*/
58242 
58243 /* ENABLE26 @Bit 26 : Enable Real Time Choke for Write Address Channel */
58244   #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Pos (26UL) /*!< Position of ENABLE26 field.                                         */
58245   #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE26_Pos) /*!< Bit mask of ENABLE26 field.*/
58246   #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Min (0x0UL) /*!< Min enumerator value of ENABLE26 field.                            */
58247   #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Max (0x1UL) /*!< Max enumerator value of ENABLE26 field.                            */
58248   #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 26 Write Address
58249                                                                 Channel*/
58250   #define MPC_RTCHOKE_WRITEACCESS_ENABLE26_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 26 Write Address
58251                                                                Channel*/
58252 
58253 /* ENABLE27 @Bit 27 : Enable Real Time Choke for Write Address Channel */
58254   #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Pos (27UL) /*!< Position of ENABLE27 field.                                         */
58255   #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE27_Pos) /*!< Bit mask of ENABLE27 field.*/
58256   #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Min (0x0UL) /*!< Min enumerator value of ENABLE27 field.                            */
58257   #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Max (0x1UL) /*!< Max enumerator value of ENABLE27 field.                            */
58258   #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 27 Write Address
58259                                                                 Channel*/
58260   #define MPC_RTCHOKE_WRITEACCESS_ENABLE27_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 27 Write Address
58261                                                                Channel*/
58262 
58263 /* ENABLE28 @Bit 28 : Enable Real Time Choke for Write Address Channel */
58264   #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Pos (28UL) /*!< Position of ENABLE28 field.                                         */
58265   #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE28_Pos) /*!< Bit mask of ENABLE28 field.*/
58266   #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Min (0x0UL) /*!< Min enumerator value of ENABLE28 field.                            */
58267   #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Max (0x1UL) /*!< Max enumerator value of ENABLE28 field.                            */
58268   #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 28 Write Address
58269                                                                 Channel*/
58270   #define MPC_RTCHOKE_WRITEACCESS_ENABLE28_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 28 Write Address
58271                                                                Channel*/
58272 
58273 /* ENABLE29 @Bit 29 : Enable Real Time Choke for Write Address Channel */
58274   #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Pos (29UL) /*!< Position of ENABLE29 field.                                         */
58275   #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE29_Pos) /*!< Bit mask of ENABLE29 field.*/
58276   #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Min (0x0UL) /*!< Min enumerator value of ENABLE29 field.                            */
58277   #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Max (0x1UL) /*!< Max enumerator value of ENABLE29 field.                            */
58278   #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 29 Write Address
58279                                                                 Channel*/
58280   #define MPC_RTCHOKE_WRITEACCESS_ENABLE29_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 29 Write Address
58281                                                                Channel*/
58282 
58283 /* ENABLE30 @Bit 30 : Enable Real Time Choke for Write Address Channel */
58284   #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Pos (30UL) /*!< Position of ENABLE30 field.                                         */
58285   #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE30_Pos) /*!< Bit mask of ENABLE30 field.*/
58286   #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Min (0x0UL) /*!< Min enumerator value of ENABLE30 field.                            */
58287   #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Max (0x1UL) /*!< Max enumerator value of ENABLE30 field.                            */
58288   #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 30 Write Address
58289                                                                 Channel*/
58290   #define MPC_RTCHOKE_WRITEACCESS_ENABLE30_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 30 Write Address
58291                                                                Channel*/
58292 
58293 /* ENABLE31 @Bit 31 : Enable Real Time Choke for Write Address Channel */
58294   #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Pos (31UL) /*!< Position of ENABLE31 field.                                         */
58295   #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Msk (0x1UL << MPC_RTCHOKE_WRITEACCESS_ENABLE31_Pos) /*!< Bit mask of ENABLE31 field.*/
58296   #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Min (0x0UL) /*!< Min enumerator value of ENABLE31 field.                            */
58297   #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Max (0x1UL) /*!< Max enumerator value of ENABLE31 field.                            */
58298   #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 31 Write Address
58299                                                                 Channel*/
58300   #define MPC_RTCHOKE_WRITEACCESS_ENABLE31_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 31 Write Address
58301                                                                Channel*/
58302 
58303 
58304 /* MPC_RTCHOKE_READACCESS: Enable AXI Read Address Channel Real Time Choke for master port */
58305   #define MPC_RTCHOKE_READACCESS_ResetValue (0x00000000UL) /*!< Reset value of READACCESS register.                            */
58306 
58307 /* ENABLE0 @Bit 0 : Enable Real Time Choke for Read Address Channel */
58308   #define MPC_RTCHOKE_READACCESS_ENABLE0_Pos (0UL)   /*!< Position of ENABLE0 field.                                           */
58309   #define MPC_RTCHOKE_READACCESS_ENABLE0_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field.     */
58310   #define MPC_RTCHOKE_READACCESS_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field.                               */
58311   #define MPC_RTCHOKE_READACCESS_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field.                               */
58312   #define MPC_RTCHOKE_READACCESS_ENABLE0_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 0 Read Address
58313                                                               Channel*/
58314   #define MPC_RTCHOKE_READACCESS_ENABLE0_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 0 Read Address Channel */
58315 
58316 /* ENABLE1 @Bit 1 : Enable Real Time Choke for Read Address Channel */
58317   #define MPC_RTCHOKE_READACCESS_ENABLE1_Pos (1UL)   /*!< Position of ENABLE1 field.                                           */
58318   #define MPC_RTCHOKE_READACCESS_ENABLE1_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field.     */
58319   #define MPC_RTCHOKE_READACCESS_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field.                               */
58320   #define MPC_RTCHOKE_READACCESS_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field.                               */
58321   #define MPC_RTCHOKE_READACCESS_ENABLE1_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 1 Read Address
58322                                                               Channel*/
58323   #define MPC_RTCHOKE_READACCESS_ENABLE1_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 1 Read Address Channel */
58324 
58325 /* ENABLE2 @Bit 2 : Enable Real Time Choke for Read Address Channel */
58326   #define MPC_RTCHOKE_READACCESS_ENABLE2_Pos (2UL)   /*!< Position of ENABLE2 field.                                           */
58327   #define MPC_RTCHOKE_READACCESS_ENABLE2_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field.     */
58328   #define MPC_RTCHOKE_READACCESS_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field.                               */
58329   #define MPC_RTCHOKE_READACCESS_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field.                               */
58330   #define MPC_RTCHOKE_READACCESS_ENABLE2_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 2 Read Address
58331                                                               Channel*/
58332   #define MPC_RTCHOKE_READACCESS_ENABLE2_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 2 Read Address Channel */
58333 
58334 /* ENABLE3 @Bit 3 : Enable Real Time Choke for Read Address Channel */
58335   #define MPC_RTCHOKE_READACCESS_ENABLE3_Pos (3UL)   /*!< Position of ENABLE3 field.                                           */
58336   #define MPC_RTCHOKE_READACCESS_ENABLE3_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field.     */
58337   #define MPC_RTCHOKE_READACCESS_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field.                               */
58338   #define MPC_RTCHOKE_READACCESS_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field.                               */
58339   #define MPC_RTCHOKE_READACCESS_ENABLE3_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 3 Read Address
58340                                                               Channel*/
58341   #define MPC_RTCHOKE_READACCESS_ENABLE3_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 3 Read Address Channel */
58342 
58343 /* ENABLE4 @Bit 4 : Enable Real Time Choke for Read Address Channel */
58344   #define MPC_RTCHOKE_READACCESS_ENABLE4_Pos (4UL)   /*!< Position of ENABLE4 field.                                           */
58345   #define MPC_RTCHOKE_READACCESS_ENABLE4_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE4_Pos) /*!< Bit mask of ENABLE4 field.     */
58346   #define MPC_RTCHOKE_READACCESS_ENABLE4_Min (0x0UL) /*!< Min enumerator value of ENABLE4 field.                               */
58347   #define MPC_RTCHOKE_READACCESS_ENABLE4_Max (0x1UL) /*!< Max enumerator value of ENABLE4 field.                               */
58348   #define MPC_RTCHOKE_READACCESS_ENABLE4_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 4 Read Address
58349                                                               Channel*/
58350   #define MPC_RTCHOKE_READACCESS_ENABLE4_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 4 Read Address Channel */
58351 
58352 /* ENABLE5 @Bit 5 : Enable Real Time Choke for Read Address Channel */
58353   #define MPC_RTCHOKE_READACCESS_ENABLE5_Pos (5UL)   /*!< Position of ENABLE5 field.                                           */
58354   #define MPC_RTCHOKE_READACCESS_ENABLE5_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE5_Pos) /*!< Bit mask of ENABLE5 field.     */
58355   #define MPC_RTCHOKE_READACCESS_ENABLE5_Min (0x0UL) /*!< Min enumerator value of ENABLE5 field.                               */
58356   #define MPC_RTCHOKE_READACCESS_ENABLE5_Max (0x1UL) /*!< Max enumerator value of ENABLE5 field.                               */
58357   #define MPC_RTCHOKE_READACCESS_ENABLE5_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 5 Read Address
58358                                                               Channel*/
58359   #define MPC_RTCHOKE_READACCESS_ENABLE5_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 5 Read Address Channel */
58360 
58361 /* ENABLE6 @Bit 6 : Enable Real Time Choke for Read Address Channel */
58362   #define MPC_RTCHOKE_READACCESS_ENABLE6_Pos (6UL)   /*!< Position of ENABLE6 field.                                           */
58363   #define MPC_RTCHOKE_READACCESS_ENABLE6_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE6_Pos) /*!< Bit mask of ENABLE6 field.     */
58364   #define MPC_RTCHOKE_READACCESS_ENABLE6_Min (0x0UL) /*!< Min enumerator value of ENABLE6 field.                               */
58365   #define MPC_RTCHOKE_READACCESS_ENABLE6_Max (0x1UL) /*!< Max enumerator value of ENABLE6 field.                               */
58366   #define MPC_RTCHOKE_READACCESS_ENABLE6_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 6 Read Address
58367                                                               Channel*/
58368   #define MPC_RTCHOKE_READACCESS_ENABLE6_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 6 Read Address Channel */
58369 
58370 /* ENABLE7 @Bit 7 : Enable Real Time Choke for Read Address Channel */
58371   #define MPC_RTCHOKE_READACCESS_ENABLE7_Pos (7UL)   /*!< Position of ENABLE7 field.                                           */
58372   #define MPC_RTCHOKE_READACCESS_ENABLE7_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE7_Pos) /*!< Bit mask of ENABLE7 field.     */
58373   #define MPC_RTCHOKE_READACCESS_ENABLE7_Min (0x0UL) /*!< Min enumerator value of ENABLE7 field.                               */
58374   #define MPC_RTCHOKE_READACCESS_ENABLE7_Max (0x1UL) /*!< Max enumerator value of ENABLE7 field.                               */
58375   #define MPC_RTCHOKE_READACCESS_ENABLE7_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 7 Read Address
58376                                                               Channel*/
58377   #define MPC_RTCHOKE_READACCESS_ENABLE7_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 7 Read Address Channel */
58378 
58379 /* ENABLE8 @Bit 8 : Enable Real Time Choke for Read Address Channel */
58380   #define MPC_RTCHOKE_READACCESS_ENABLE8_Pos (8UL)   /*!< Position of ENABLE8 field.                                           */
58381   #define MPC_RTCHOKE_READACCESS_ENABLE8_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE8_Pos) /*!< Bit mask of ENABLE8 field.     */
58382   #define MPC_RTCHOKE_READACCESS_ENABLE8_Min (0x0UL) /*!< Min enumerator value of ENABLE8 field.                               */
58383   #define MPC_RTCHOKE_READACCESS_ENABLE8_Max (0x1UL) /*!< Max enumerator value of ENABLE8 field.                               */
58384   #define MPC_RTCHOKE_READACCESS_ENABLE8_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 8 Read Address
58385                                                               Channel*/
58386   #define MPC_RTCHOKE_READACCESS_ENABLE8_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 8 Read Address Channel */
58387 
58388 /* ENABLE9 @Bit 9 : Enable Real Time Choke for Read Address Channel */
58389   #define MPC_RTCHOKE_READACCESS_ENABLE9_Pos (9UL)   /*!< Position of ENABLE9 field.                                           */
58390   #define MPC_RTCHOKE_READACCESS_ENABLE9_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE9_Pos) /*!< Bit mask of ENABLE9 field.     */
58391   #define MPC_RTCHOKE_READACCESS_ENABLE9_Min (0x0UL) /*!< Min enumerator value of ENABLE9 field.                               */
58392   #define MPC_RTCHOKE_READACCESS_ENABLE9_Max (0x1UL) /*!< Max enumerator value of ENABLE9 field.                               */
58393   #define MPC_RTCHOKE_READACCESS_ENABLE9_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 9 Read Address
58394                                                               Channel*/
58395   #define MPC_RTCHOKE_READACCESS_ENABLE9_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 9 Read Address Channel */
58396 
58397 /* ENABLE10 @Bit 10 : Enable Real Time Choke for Read Address Channel */
58398   #define MPC_RTCHOKE_READACCESS_ENABLE10_Pos (10UL) /*!< Position of ENABLE10 field.                                          */
58399   #define MPC_RTCHOKE_READACCESS_ENABLE10_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE10_Pos) /*!< Bit mask of ENABLE10 field.  */
58400   #define MPC_RTCHOKE_READACCESS_ENABLE10_Min (0x0UL) /*!< Min enumerator value of ENABLE10 field.                             */
58401   #define MPC_RTCHOKE_READACCESS_ENABLE10_Max (0x1UL) /*!< Max enumerator value of ENABLE10 field.                             */
58402   #define MPC_RTCHOKE_READACCESS_ENABLE10_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 10 Read Address
58403                                                                Channel*/
58404   #define MPC_RTCHOKE_READACCESS_ENABLE10_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 10 Read Address
58405                                                               Channel*/
58406 
58407 /* ENABLE11 @Bit 11 : Enable Real Time Choke for Read Address Channel */
58408   #define MPC_RTCHOKE_READACCESS_ENABLE11_Pos (11UL) /*!< Position of ENABLE11 field.                                          */
58409   #define MPC_RTCHOKE_READACCESS_ENABLE11_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE11_Pos) /*!< Bit mask of ENABLE11 field.  */
58410   #define MPC_RTCHOKE_READACCESS_ENABLE11_Min (0x0UL) /*!< Min enumerator value of ENABLE11 field.                             */
58411   #define MPC_RTCHOKE_READACCESS_ENABLE11_Max (0x1UL) /*!< Max enumerator value of ENABLE11 field.                             */
58412   #define MPC_RTCHOKE_READACCESS_ENABLE11_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 11 Read Address
58413                                                                Channel*/
58414   #define MPC_RTCHOKE_READACCESS_ENABLE11_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 11 Read Address
58415                                                               Channel*/
58416 
58417 /* ENABLE12 @Bit 12 : Enable Real Time Choke for Read Address Channel */
58418   #define MPC_RTCHOKE_READACCESS_ENABLE12_Pos (12UL) /*!< Position of ENABLE12 field.                                          */
58419   #define MPC_RTCHOKE_READACCESS_ENABLE12_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE12_Pos) /*!< Bit mask of ENABLE12 field.  */
58420   #define MPC_RTCHOKE_READACCESS_ENABLE12_Min (0x0UL) /*!< Min enumerator value of ENABLE12 field.                             */
58421   #define MPC_RTCHOKE_READACCESS_ENABLE12_Max (0x1UL) /*!< Max enumerator value of ENABLE12 field.                             */
58422   #define MPC_RTCHOKE_READACCESS_ENABLE12_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 12 Read Address
58423                                                                Channel*/
58424   #define MPC_RTCHOKE_READACCESS_ENABLE12_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 12 Read Address
58425                                                               Channel*/
58426 
58427 /* ENABLE13 @Bit 13 : Enable Real Time Choke for Read Address Channel */
58428   #define MPC_RTCHOKE_READACCESS_ENABLE13_Pos (13UL) /*!< Position of ENABLE13 field.                                          */
58429   #define MPC_RTCHOKE_READACCESS_ENABLE13_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE13_Pos) /*!< Bit mask of ENABLE13 field.  */
58430   #define MPC_RTCHOKE_READACCESS_ENABLE13_Min (0x0UL) /*!< Min enumerator value of ENABLE13 field.                             */
58431   #define MPC_RTCHOKE_READACCESS_ENABLE13_Max (0x1UL) /*!< Max enumerator value of ENABLE13 field.                             */
58432   #define MPC_RTCHOKE_READACCESS_ENABLE13_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 13 Read Address
58433                                                                Channel*/
58434   #define MPC_RTCHOKE_READACCESS_ENABLE13_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 13 Read Address
58435                                                               Channel*/
58436 
58437 /* ENABLE14 @Bit 14 : Enable Real Time Choke for Read Address Channel */
58438   #define MPC_RTCHOKE_READACCESS_ENABLE14_Pos (14UL) /*!< Position of ENABLE14 field.                                          */
58439   #define MPC_RTCHOKE_READACCESS_ENABLE14_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE14_Pos) /*!< Bit mask of ENABLE14 field.  */
58440   #define MPC_RTCHOKE_READACCESS_ENABLE14_Min (0x0UL) /*!< Min enumerator value of ENABLE14 field.                             */
58441   #define MPC_RTCHOKE_READACCESS_ENABLE14_Max (0x1UL) /*!< Max enumerator value of ENABLE14 field.                             */
58442   #define MPC_RTCHOKE_READACCESS_ENABLE14_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 14 Read Address
58443                                                                Channel*/
58444   #define MPC_RTCHOKE_READACCESS_ENABLE14_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 14 Read Address
58445                                                               Channel*/
58446 
58447 /* ENABLE15 @Bit 15 : Enable Real Time Choke for Read Address Channel */
58448   #define MPC_RTCHOKE_READACCESS_ENABLE15_Pos (15UL) /*!< Position of ENABLE15 field.                                          */
58449   #define MPC_RTCHOKE_READACCESS_ENABLE15_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE15_Pos) /*!< Bit mask of ENABLE15 field.  */
58450   #define MPC_RTCHOKE_READACCESS_ENABLE15_Min (0x0UL) /*!< Min enumerator value of ENABLE15 field.                             */
58451   #define MPC_RTCHOKE_READACCESS_ENABLE15_Max (0x1UL) /*!< Max enumerator value of ENABLE15 field.                             */
58452   #define MPC_RTCHOKE_READACCESS_ENABLE15_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 15 Read Address
58453                                                                Channel*/
58454   #define MPC_RTCHOKE_READACCESS_ENABLE15_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 15 Read Address
58455                                                               Channel*/
58456 
58457 /* ENABLE16 @Bit 16 : Enable Real Time Choke for Read Address Channel */
58458   #define MPC_RTCHOKE_READACCESS_ENABLE16_Pos (16UL) /*!< Position of ENABLE16 field.                                          */
58459   #define MPC_RTCHOKE_READACCESS_ENABLE16_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE16_Pos) /*!< Bit mask of ENABLE16 field.  */
58460   #define MPC_RTCHOKE_READACCESS_ENABLE16_Min (0x0UL) /*!< Min enumerator value of ENABLE16 field.                             */
58461   #define MPC_RTCHOKE_READACCESS_ENABLE16_Max (0x1UL) /*!< Max enumerator value of ENABLE16 field.                             */
58462   #define MPC_RTCHOKE_READACCESS_ENABLE16_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 16 Read Address
58463                                                                Channel*/
58464   #define MPC_RTCHOKE_READACCESS_ENABLE16_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 16 Read Address
58465                                                               Channel*/
58466 
58467 /* ENABLE17 @Bit 17 : Enable Real Time Choke for Read Address Channel */
58468   #define MPC_RTCHOKE_READACCESS_ENABLE17_Pos (17UL) /*!< Position of ENABLE17 field.                                          */
58469   #define MPC_RTCHOKE_READACCESS_ENABLE17_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE17_Pos) /*!< Bit mask of ENABLE17 field.  */
58470   #define MPC_RTCHOKE_READACCESS_ENABLE17_Min (0x0UL) /*!< Min enumerator value of ENABLE17 field.                             */
58471   #define MPC_RTCHOKE_READACCESS_ENABLE17_Max (0x1UL) /*!< Max enumerator value of ENABLE17 field.                             */
58472   #define MPC_RTCHOKE_READACCESS_ENABLE17_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 17 Read Address
58473                                                                Channel*/
58474   #define MPC_RTCHOKE_READACCESS_ENABLE17_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 17 Read Address
58475                                                               Channel*/
58476 
58477 /* ENABLE18 @Bit 18 : Enable Real Time Choke for Read Address Channel */
58478   #define MPC_RTCHOKE_READACCESS_ENABLE18_Pos (18UL) /*!< Position of ENABLE18 field.                                          */
58479   #define MPC_RTCHOKE_READACCESS_ENABLE18_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE18_Pos) /*!< Bit mask of ENABLE18 field.  */
58480   #define MPC_RTCHOKE_READACCESS_ENABLE18_Min (0x0UL) /*!< Min enumerator value of ENABLE18 field.                             */
58481   #define MPC_RTCHOKE_READACCESS_ENABLE18_Max (0x1UL) /*!< Max enumerator value of ENABLE18 field.                             */
58482   #define MPC_RTCHOKE_READACCESS_ENABLE18_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 18 Read Address
58483                                                                Channel*/
58484   #define MPC_RTCHOKE_READACCESS_ENABLE18_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 18 Read Address
58485                                                               Channel*/
58486 
58487 /* ENABLE19 @Bit 19 : Enable Real Time Choke for Read Address Channel */
58488   #define MPC_RTCHOKE_READACCESS_ENABLE19_Pos (19UL) /*!< Position of ENABLE19 field.                                          */
58489   #define MPC_RTCHOKE_READACCESS_ENABLE19_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE19_Pos) /*!< Bit mask of ENABLE19 field.  */
58490   #define MPC_RTCHOKE_READACCESS_ENABLE19_Min (0x0UL) /*!< Min enumerator value of ENABLE19 field.                             */
58491   #define MPC_RTCHOKE_READACCESS_ENABLE19_Max (0x1UL) /*!< Max enumerator value of ENABLE19 field.                             */
58492   #define MPC_RTCHOKE_READACCESS_ENABLE19_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 19 Read Address
58493                                                                Channel*/
58494   #define MPC_RTCHOKE_READACCESS_ENABLE19_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 19 Read Address
58495                                                               Channel*/
58496 
58497 /* ENABLE20 @Bit 20 : Enable Real Time Choke for Read Address Channel */
58498   #define MPC_RTCHOKE_READACCESS_ENABLE20_Pos (20UL) /*!< Position of ENABLE20 field.                                          */
58499   #define MPC_RTCHOKE_READACCESS_ENABLE20_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE20_Pos) /*!< Bit mask of ENABLE20 field.  */
58500   #define MPC_RTCHOKE_READACCESS_ENABLE20_Min (0x0UL) /*!< Min enumerator value of ENABLE20 field.                             */
58501   #define MPC_RTCHOKE_READACCESS_ENABLE20_Max (0x1UL) /*!< Max enumerator value of ENABLE20 field.                             */
58502   #define MPC_RTCHOKE_READACCESS_ENABLE20_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 20 Read Address
58503                                                                Channel*/
58504   #define MPC_RTCHOKE_READACCESS_ENABLE20_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 20 Read Address
58505                                                               Channel*/
58506 
58507 /* ENABLE21 @Bit 21 : Enable Real Time Choke for Read Address Channel */
58508   #define MPC_RTCHOKE_READACCESS_ENABLE21_Pos (21UL) /*!< Position of ENABLE21 field.                                          */
58509   #define MPC_RTCHOKE_READACCESS_ENABLE21_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE21_Pos) /*!< Bit mask of ENABLE21 field.  */
58510   #define MPC_RTCHOKE_READACCESS_ENABLE21_Min (0x0UL) /*!< Min enumerator value of ENABLE21 field.                             */
58511   #define MPC_RTCHOKE_READACCESS_ENABLE21_Max (0x1UL) /*!< Max enumerator value of ENABLE21 field.                             */
58512   #define MPC_RTCHOKE_READACCESS_ENABLE21_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 21 Read Address
58513                                                                Channel*/
58514   #define MPC_RTCHOKE_READACCESS_ENABLE21_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 21 Read Address
58515                                                               Channel*/
58516 
58517 /* ENABLE22 @Bit 22 : Enable Real Time Choke for Read Address Channel */
58518   #define MPC_RTCHOKE_READACCESS_ENABLE22_Pos (22UL) /*!< Position of ENABLE22 field.                                          */
58519   #define MPC_RTCHOKE_READACCESS_ENABLE22_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE22_Pos) /*!< Bit mask of ENABLE22 field.  */
58520   #define MPC_RTCHOKE_READACCESS_ENABLE22_Min (0x0UL) /*!< Min enumerator value of ENABLE22 field.                             */
58521   #define MPC_RTCHOKE_READACCESS_ENABLE22_Max (0x1UL) /*!< Max enumerator value of ENABLE22 field.                             */
58522   #define MPC_RTCHOKE_READACCESS_ENABLE22_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 22 Read Address
58523                                                                Channel*/
58524   #define MPC_RTCHOKE_READACCESS_ENABLE22_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 22 Read Address
58525                                                               Channel*/
58526 
58527 /* ENABLE23 @Bit 23 : Enable Real Time Choke for Read Address Channel */
58528   #define MPC_RTCHOKE_READACCESS_ENABLE23_Pos (23UL) /*!< Position of ENABLE23 field.                                          */
58529   #define MPC_RTCHOKE_READACCESS_ENABLE23_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE23_Pos) /*!< Bit mask of ENABLE23 field.  */
58530   #define MPC_RTCHOKE_READACCESS_ENABLE23_Min (0x0UL) /*!< Min enumerator value of ENABLE23 field.                             */
58531   #define MPC_RTCHOKE_READACCESS_ENABLE23_Max (0x1UL) /*!< Max enumerator value of ENABLE23 field.                             */
58532   #define MPC_RTCHOKE_READACCESS_ENABLE23_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 23 Read Address
58533                                                                Channel*/
58534   #define MPC_RTCHOKE_READACCESS_ENABLE23_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 23 Read Address
58535                                                               Channel*/
58536 
58537 /* ENABLE24 @Bit 24 : Enable Real Time Choke for Read Address Channel */
58538   #define MPC_RTCHOKE_READACCESS_ENABLE24_Pos (24UL) /*!< Position of ENABLE24 field.                                          */
58539   #define MPC_RTCHOKE_READACCESS_ENABLE24_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE24_Pos) /*!< Bit mask of ENABLE24 field.  */
58540   #define MPC_RTCHOKE_READACCESS_ENABLE24_Min (0x0UL) /*!< Min enumerator value of ENABLE24 field.                             */
58541   #define MPC_RTCHOKE_READACCESS_ENABLE24_Max (0x1UL) /*!< Max enumerator value of ENABLE24 field.                             */
58542   #define MPC_RTCHOKE_READACCESS_ENABLE24_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 24 Read Address
58543                                                                Channel*/
58544   #define MPC_RTCHOKE_READACCESS_ENABLE24_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 24 Read Address
58545                                                               Channel*/
58546 
58547 /* ENABLE25 @Bit 25 : Enable Real Time Choke for Read Address Channel */
58548   #define MPC_RTCHOKE_READACCESS_ENABLE25_Pos (25UL) /*!< Position of ENABLE25 field.                                          */
58549   #define MPC_RTCHOKE_READACCESS_ENABLE25_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE25_Pos) /*!< Bit mask of ENABLE25 field.  */
58550   #define MPC_RTCHOKE_READACCESS_ENABLE25_Min (0x0UL) /*!< Min enumerator value of ENABLE25 field.                             */
58551   #define MPC_RTCHOKE_READACCESS_ENABLE25_Max (0x1UL) /*!< Max enumerator value of ENABLE25 field.                             */
58552   #define MPC_RTCHOKE_READACCESS_ENABLE25_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 25 Read Address
58553                                                                Channel*/
58554   #define MPC_RTCHOKE_READACCESS_ENABLE25_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 25 Read Address
58555                                                               Channel*/
58556 
58557 /* ENABLE26 @Bit 26 : Enable Real Time Choke for Read Address Channel */
58558   #define MPC_RTCHOKE_READACCESS_ENABLE26_Pos (26UL) /*!< Position of ENABLE26 field.                                          */
58559   #define MPC_RTCHOKE_READACCESS_ENABLE26_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE26_Pos) /*!< Bit mask of ENABLE26 field.  */
58560   #define MPC_RTCHOKE_READACCESS_ENABLE26_Min (0x0UL) /*!< Min enumerator value of ENABLE26 field.                             */
58561   #define MPC_RTCHOKE_READACCESS_ENABLE26_Max (0x1UL) /*!< Max enumerator value of ENABLE26 field.                             */
58562   #define MPC_RTCHOKE_READACCESS_ENABLE26_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 26 Read Address
58563                                                                Channel*/
58564   #define MPC_RTCHOKE_READACCESS_ENABLE26_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 26 Read Address
58565                                                               Channel*/
58566 
58567 /* ENABLE27 @Bit 27 : Enable Real Time Choke for Read Address Channel */
58568   #define MPC_RTCHOKE_READACCESS_ENABLE27_Pos (27UL) /*!< Position of ENABLE27 field.                                          */
58569   #define MPC_RTCHOKE_READACCESS_ENABLE27_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE27_Pos) /*!< Bit mask of ENABLE27 field.  */
58570   #define MPC_RTCHOKE_READACCESS_ENABLE27_Min (0x0UL) /*!< Min enumerator value of ENABLE27 field.                             */
58571   #define MPC_RTCHOKE_READACCESS_ENABLE27_Max (0x1UL) /*!< Max enumerator value of ENABLE27 field.                             */
58572   #define MPC_RTCHOKE_READACCESS_ENABLE27_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 27 Read Address
58573                                                                Channel*/
58574   #define MPC_RTCHOKE_READACCESS_ENABLE27_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 27 Read Address
58575                                                               Channel*/
58576 
58577 /* ENABLE28 @Bit 28 : Enable Real Time Choke for Read Address Channel */
58578   #define MPC_RTCHOKE_READACCESS_ENABLE28_Pos (28UL) /*!< Position of ENABLE28 field.                                          */
58579   #define MPC_RTCHOKE_READACCESS_ENABLE28_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE28_Pos) /*!< Bit mask of ENABLE28 field.  */
58580   #define MPC_RTCHOKE_READACCESS_ENABLE28_Min (0x0UL) /*!< Min enumerator value of ENABLE28 field.                             */
58581   #define MPC_RTCHOKE_READACCESS_ENABLE28_Max (0x1UL) /*!< Max enumerator value of ENABLE28 field.                             */
58582   #define MPC_RTCHOKE_READACCESS_ENABLE28_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 28 Read Address
58583                                                                Channel*/
58584   #define MPC_RTCHOKE_READACCESS_ENABLE28_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 28 Read Address
58585                                                               Channel*/
58586 
58587 /* ENABLE29 @Bit 29 : Enable Real Time Choke for Read Address Channel */
58588   #define MPC_RTCHOKE_READACCESS_ENABLE29_Pos (29UL) /*!< Position of ENABLE29 field.                                          */
58589   #define MPC_RTCHOKE_READACCESS_ENABLE29_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE29_Pos) /*!< Bit mask of ENABLE29 field.  */
58590   #define MPC_RTCHOKE_READACCESS_ENABLE29_Min (0x0UL) /*!< Min enumerator value of ENABLE29 field.                             */
58591   #define MPC_RTCHOKE_READACCESS_ENABLE29_Max (0x1UL) /*!< Max enumerator value of ENABLE29 field.                             */
58592   #define MPC_RTCHOKE_READACCESS_ENABLE29_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 29 Read Address
58593                                                                Channel*/
58594   #define MPC_RTCHOKE_READACCESS_ENABLE29_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 29 Read Address
58595                                                               Channel*/
58596 
58597 /* ENABLE30 @Bit 30 : Enable Real Time Choke for Read Address Channel */
58598   #define MPC_RTCHOKE_READACCESS_ENABLE30_Pos (30UL) /*!< Position of ENABLE30 field.                                          */
58599   #define MPC_RTCHOKE_READACCESS_ENABLE30_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE30_Pos) /*!< Bit mask of ENABLE30 field.  */
58600   #define MPC_RTCHOKE_READACCESS_ENABLE30_Min (0x0UL) /*!< Min enumerator value of ENABLE30 field.                             */
58601   #define MPC_RTCHOKE_READACCESS_ENABLE30_Max (0x1UL) /*!< Max enumerator value of ENABLE30 field.                             */
58602   #define MPC_RTCHOKE_READACCESS_ENABLE30_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 30 Read Address
58603                                                                Channel*/
58604   #define MPC_RTCHOKE_READACCESS_ENABLE30_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 30 Read Address
58605                                                               Channel*/
58606 
58607 /* ENABLE31 @Bit 31 : Enable Real Time Choke for Read Address Channel */
58608   #define MPC_RTCHOKE_READACCESS_ENABLE31_Pos (31UL) /*!< Position of ENABLE31 field.                                          */
58609   #define MPC_RTCHOKE_READACCESS_ENABLE31_Msk (0x1UL << MPC_RTCHOKE_READACCESS_ENABLE31_Pos) /*!< Bit mask of ENABLE31 field.  */
58610   #define MPC_RTCHOKE_READACCESS_ENABLE31_Min (0x0UL) /*!< Min enumerator value of ENABLE31 field.                             */
58611   #define MPC_RTCHOKE_READACCESS_ENABLE31_Max (0x1UL) /*!< Max enumerator value of ENABLE31 field.                             */
58612   #define MPC_RTCHOKE_READACCESS_ENABLE31_Disable (0x0UL) /*!< Real Time Choke is disabled for master port 31 Read Address
58613                                                                Channel*/
58614   #define MPC_RTCHOKE_READACCESS_ENABLE31_Enable (0x1UL) /*!< Real Time Choke is enabled for master port 31 Read Address
58615                                                               Channel*/
58616 
58617 
58618 /* MPC_RTCHOKE_DELAY: Real Time Choke delay value for slave number n */
58619   #define MPC_RTCHOKE_DELAY_MaxCount (32UL)          /*!< Max size of DELAY[32] array.                                         */
58620   #define MPC_RTCHOKE_DELAY_MaxIndex (31UL)          /*!< Max index of DELAY[32] array.                                        */
58621   #define MPC_RTCHOKE_DELAY_MinIndex (0UL)           /*!< Min index of DELAY[32] array.                                        */
58622   #define MPC_RTCHOKE_DELAY_ResetValue (0x00000000UL) /*!< Reset value of DELAY[32] register.                                  */
58623 
58624 /* DELAY @Bits 0..7 : Real Time Choke delay in bus clock cycles. */
58625   #define MPC_RTCHOKE_DELAY_DELAY_Pos (0UL)          /*!< Position of DELAY field.                                             */
58626   #define MPC_RTCHOKE_DELAY_DELAY_Msk (0xFFUL << MPC_RTCHOKE_DELAY_DELAY_Pos) /*!< Bit mask of DELAY field.                    */
58627   #define MPC_RTCHOKE_DELAY_DELAY_Min (0x0UL)        /*!< Min value of DELAY field.                                            */
58628   #define MPC_RTCHOKE_DELAY_DELAY_Max (0xFFUL)       /*!< Max size of DELAY field.                                             */
58629 
58630 
58631 
58632 /* ==================================================== Struct MPC_REGION ==================================================== */
58633 /**
58634   * @brief REGION [MPC_REGION] Memory region to slave decoding table
58635   */
58636 typedef struct {
58637   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Slave region n Configuration register                 */
58638   __IOM uint32_t  STARTADDR;                         /*!< (@ 0x00000004) Region n start address                                */
58639   __IOM uint32_t  ADDRMASK;                          /*!< (@ 0x00000008) Select which bits of the incoming address are compared
58640                                                                          against the STARTADDR*/
58641   __IOM uint32_t  MASTERPORT;                        /*!< (@ 0x0000000C) Region n local master enable                          */
58642 } NRF_MPC_REGION_Type;                               /*!< Size = 16 (0x010)                                                    */
58643   #define MPC_REGION_MaxCount (32UL)                 /*!< Size of REGION[32] array.                                            */
58644   #define MPC_REGION_MaxIndex (31UL)                 /*!< Max index of REGION[32] array.                                       */
58645   #define MPC_REGION_MinIndex (0UL)                  /*!< Min index of REGION[32] array.                                       */
58646 
58647 /* MPC_REGION_CONFIG: Slave region n Configuration register */
58648   #define MPC_REGION_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                                     */
58649 
58650 /* SLAVENUMBER @Bits 0..4 : Target slave number for region n accesses. Slave number 0 is reserved for default slave */
58651   #define MPC_REGION_CONFIG_SLAVENUMBER_Pos (0UL)    /*!< Position of SLAVENUMBER field.                                       */
58652   #define MPC_REGION_CONFIG_SLAVENUMBER_Msk (0x1FUL << MPC_REGION_CONFIG_SLAVENUMBER_Pos) /*!< Bit mask of SLAVENUMBER field.  */
58653   #define MPC_REGION_CONFIG_SLAVENUMBER_Min (0x0UL)  /*!< Min value of SLAVENUMBER field.                                      */
58654   #define MPC_REGION_CONFIG_SLAVENUMBER_Max (0x1FUL) /*!< Max size of SLAVENUMBER field.                                       */
58655 
58656 /* LOCK @Bit 8 : Locks the region n setting */
58657   #define MPC_REGION_CONFIG_LOCK_Pos (8UL)           /*!< Position of LOCK field.                                              */
58658   #define MPC_REGION_CONFIG_LOCK_Msk (0x1UL << MPC_REGION_CONFIG_LOCK_Pos) /*!< Bit mask of LOCK field.                        */
58659   #define MPC_REGION_CONFIG_LOCK_Min (0x0UL)         /*!< Min enumerator value of LOCK field.                                  */
58660   #define MPC_REGION_CONFIG_LOCK_Max (0x1UL)         /*!< Max enumerator value of LOCK field.                                  */
58661   #define MPC_REGION_CONFIG_LOCK_Unlocked (0x0UL)    /*!< Region n settings can be updated                                     */
58662   #define MPC_REGION_CONFIG_LOCK_Locked (0x1UL)      /*!< Region n settings can't be updated until next reset                  */
58663 
58664 /* ENABLE @Bit 9 : Region n enable */
58665   #define MPC_REGION_CONFIG_ENABLE_Pos (9UL)         /*!< Position of ENABLE field.                                            */
58666   #define MPC_REGION_CONFIG_ENABLE_Msk (0x1UL << MPC_REGION_CONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field.                  */
58667   #define MPC_REGION_CONFIG_ENABLE_Min (0x0UL)       /*!< Min enumerator value of ENABLE field.                                */
58668   #define MPC_REGION_CONFIG_ENABLE_Max (0x1UL)       /*!< Max enumerator value of ENABLE field.                                */
58669   #define MPC_REGION_CONFIG_ENABLE_Disabled (0x0UL)  /*!< Region n is not used                                                 */
58670   #define MPC_REGION_CONFIG_ENABLE_Enabled (0x1UL)   /*!< Region n is used                                                     */
58671 
58672 /* READ @Bit 12 : Read access */
58673   #define MPC_REGION_CONFIG_READ_Pos (12UL)          /*!< Position of READ field.                                              */
58674   #define MPC_REGION_CONFIG_READ_Msk (0x1UL << MPC_REGION_CONFIG_READ_Pos) /*!< Bit mask of READ field.                        */
58675   #define MPC_REGION_CONFIG_READ_Min (0x0UL)         /*!< Min enumerator value of READ field.                                  */
58676   #define MPC_REGION_CONFIG_READ_Max (0x1UL)         /*!< Max enumerator value of READ field.                                  */
58677   #define MPC_REGION_CONFIG_READ_NotAllowed (0x0UL)  /*!< Read access to region n is not allowed                               */
58678   #define MPC_REGION_CONFIG_READ_Allowed (0x1UL)     /*!< Read access to region n is allowed                                   */
58679 
58680 /* WRITE @Bit 13 : Write access */
58681   #define MPC_REGION_CONFIG_WRITE_Pos (13UL)         /*!< Position of WRITE field.                                             */
58682   #define MPC_REGION_CONFIG_WRITE_Msk (0x1UL << MPC_REGION_CONFIG_WRITE_Pos) /*!< Bit mask of WRITE field.                     */
58683   #define MPC_REGION_CONFIG_WRITE_Min (0x0UL)        /*!< Min enumerator value of WRITE field.                                 */
58684   #define MPC_REGION_CONFIG_WRITE_Max (0x1UL)        /*!< Max enumerator value of WRITE field.                                 */
58685   #define MPC_REGION_CONFIG_WRITE_NotAllowed (0x0UL) /*!< Write access to region n is not allowed                              */
58686   #define MPC_REGION_CONFIG_WRITE_Allowed (0x1UL)    /*!< Write access to region n is allowed                                  */
58687 
58688 /* EXECUTE @Bit 14 : Software execute */
58689   #define MPC_REGION_CONFIG_EXECUTE_Pos (14UL)       /*!< Position of EXECUTE field.                                           */
58690   #define MPC_REGION_CONFIG_EXECUTE_Msk (0x1UL << MPC_REGION_CONFIG_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.               */
58691   #define MPC_REGION_CONFIG_EXECUTE_Min (0x0UL)      /*!< Min enumerator value of EXECUTE field.                               */
58692   #define MPC_REGION_CONFIG_EXECUTE_Max (0x1UL)      /*!< Max enumerator value of EXECUTE field.                               */
58693   #define MPC_REGION_CONFIG_EXECUTE_NotAllowed (0x0UL) /*!< Software execution from region n is not allowed                    */
58694   #define MPC_REGION_CONFIG_EXECUTE_Allowed (0x1UL)  /*!< Software execution from region n is allowed                          */
58695 
58696 /* SECATTR @Bit 15 : Memory security mapping */
58697   #define MPC_REGION_CONFIG_SECATTR_Pos (15UL)       /*!< Position of SECATTR field.                                           */
58698   #define MPC_REGION_CONFIG_SECATTR_Msk (0x1UL << MPC_REGION_CONFIG_SECATTR_Pos) /*!< Bit mask of SECATTR field.               */
58699   #define MPC_REGION_CONFIG_SECATTR_Min (0x0UL)      /*!< Min enumerator value of SECATTR field.                               */
58700   #define MPC_REGION_CONFIG_SECATTR_Max (0x1UL)      /*!< Max enumerator value of SECATTR field.                               */
58701   #define MPC_REGION_CONFIG_SECATTR_Secure (0x1UL)   /*!< Memory is mapped in secure memory address space                      */
58702   #define MPC_REGION_CONFIG_SECATTR_NonSecure (0x0UL) /*!< Memory is mapped in non-secure memory address space                 */
58703 
58704 /* OWNERID @Bits 16..19 : Region owner identifier. */
58705   #define MPC_REGION_CONFIG_OWNERID_Pos (16UL)       /*!< Position of OWNERID field.                                           */
58706   #define MPC_REGION_CONFIG_OWNERID_Msk (0xFUL << MPC_REGION_CONFIG_OWNERID_Pos) /*!< Bit mask of OWNERID field.               */
58707 
58708 
58709 /* MPC_REGION_STARTADDR: Region n start address */
58710   #define MPC_REGION_STARTADDR_ResetValue (0x00000000UL) /*!< Reset value of STARTADDR register.                               */
58711 
58712 /* STARTADDR @Bits 0..31 : Start address for memory region n */
58713   #define MPC_REGION_STARTADDR_STARTADDR_Pos (0UL)   /*!< Position of STARTADDR field.                                         */
58714   #define MPC_REGION_STARTADDR_STARTADDR_Msk (0xFFFFFFFFUL << MPC_REGION_STARTADDR_STARTADDR_Pos) /*!< Bit mask of STARTADDR
58715                                                                             field.*/
58716 
58717 
58718 /* MPC_REGION_ADDRMASK: Select which bits of the incoming address are compared against the STARTADDR */
58719   #define MPC_REGION_ADDRMASK_ResetValue (0x00000000UL) /*!< Reset value of ADDRMASK register.                                 */
58720 
58721 /* ADDRMASK @Bits 0..31 : Address mask for memory region n */
58722   #define MPC_REGION_ADDRMASK_ADDRMASK_Pos (0UL)     /*!< Position of ADDRMASK field.                                          */
58723   #define MPC_REGION_ADDRMASK_ADDRMASK_Msk (0xFFFFFFFFUL << MPC_REGION_ADDRMASK_ADDRMASK_Pos) /*!< Bit mask of ADDRMASK field. */
58724 
58725 
58726 /* MPC_REGION_MASTERPORT: Region n local master enable */
58727   #define MPC_REGION_MASTERPORT_ResetValue (0x00000000UL) /*!< Reset value of MASTERPORT register.                             */
58728 
58729 /* ENABLE0 @Bit 0 : Enable region n for master port 0 */
58730   #define MPC_REGION_MASTERPORT_ENABLE0_Pos (0UL)    /*!< Position of ENABLE0 field.                                           */
58731   #define MPC_REGION_MASTERPORT_ENABLE0_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field.       */
58732   #define MPC_REGION_MASTERPORT_ENABLE0_Min (0x0UL)  /*!< Min enumerator value of ENABLE0 field.                               */
58733   #define MPC_REGION_MASTERPORT_ENABLE0_Max (0x1UL)  /*!< Max enumerator value of ENABLE0 field.                               */
58734   #define MPC_REGION_MASTERPORT_ENABLE0_Disable (0x0UL) /*!< Region n is disabled for master port 0                            */
58735   #define MPC_REGION_MASTERPORT_ENABLE0_Enable (0x1UL) /*!< Region n is enabled for master port 0                              */
58736 
58737 /* ENABLE1 @Bit 1 : Enable region n for master port 1 */
58738   #define MPC_REGION_MASTERPORT_ENABLE1_Pos (1UL)    /*!< Position of ENABLE1 field.                                           */
58739   #define MPC_REGION_MASTERPORT_ENABLE1_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field.       */
58740   #define MPC_REGION_MASTERPORT_ENABLE1_Min (0x0UL)  /*!< Min enumerator value of ENABLE1 field.                               */
58741   #define MPC_REGION_MASTERPORT_ENABLE1_Max (0x1UL)  /*!< Max enumerator value of ENABLE1 field.                               */
58742   #define MPC_REGION_MASTERPORT_ENABLE1_Disable (0x0UL) /*!< Region n is disabled for master port 1                            */
58743   #define MPC_REGION_MASTERPORT_ENABLE1_Enable (0x1UL) /*!< Region n is enabled for master port 1                              */
58744 
58745 /* ENABLE2 @Bit 2 : Enable region n for master port 2 */
58746   #define MPC_REGION_MASTERPORT_ENABLE2_Pos (2UL)    /*!< Position of ENABLE2 field.                                           */
58747   #define MPC_REGION_MASTERPORT_ENABLE2_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field.       */
58748   #define MPC_REGION_MASTERPORT_ENABLE2_Min (0x0UL)  /*!< Min enumerator value of ENABLE2 field.                               */
58749   #define MPC_REGION_MASTERPORT_ENABLE2_Max (0x1UL)  /*!< Max enumerator value of ENABLE2 field.                               */
58750   #define MPC_REGION_MASTERPORT_ENABLE2_Disable (0x0UL) /*!< Region n is disabled for master port 2                            */
58751   #define MPC_REGION_MASTERPORT_ENABLE2_Enable (0x1UL) /*!< Region n is enabled for master port 2                              */
58752 
58753 /* ENABLE3 @Bit 3 : Enable region n for master port 3 */
58754   #define MPC_REGION_MASTERPORT_ENABLE3_Pos (3UL)    /*!< Position of ENABLE3 field.                                           */
58755   #define MPC_REGION_MASTERPORT_ENABLE3_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field.       */
58756   #define MPC_REGION_MASTERPORT_ENABLE3_Min (0x0UL)  /*!< Min enumerator value of ENABLE3 field.                               */
58757   #define MPC_REGION_MASTERPORT_ENABLE3_Max (0x1UL)  /*!< Max enumerator value of ENABLE3 field.                               */
58758   #define MPC_REGION_MASTERPORT_ENABLE3_Disable (0x0UL) /*!< Region n is disabled for master port 3                            */
58759   #define MPC_REGION_MASTERPORT_ENABLE3_Enable (0x1UL) /*!< Region n is enabled for master port 3                              */
58760 
58761 /* ENABLE4 @Bit 4 : Enable region n for master port 4 */
58762   #define MPC_REGION_MASTERPORT_ENABLE4_Pos (4UL)    /*!< Position of ENABLE4 field.                                           */
58763   #define MPC_REGION_MASTERPORT_ENABLE4_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE4_Pos) /*!< Bit mask of ENABLE4 field.       */
58764   #define MPC_REGION_MASTERPORT_ENABLE4_Min (0x0UL)  /*!< Min enumerator value of ENABLE4 field.                               */
58765   #define MPC_REGION_MASTERPORT_ENABLE4_Max (0x1UL)  /*!< Max enumerator value of ENABLE4 field.                               */
58766   #define MPC_REGION_MASTERPORT_ENABLE4_Disable (0x0UL) /*!< Region n is disabled for master port 4                            */
58767   #define MPC_REGION_MASTERPORT_ENABLE4_Enable (0x1UL) /*!< Region n is enabled for master port 4                              */
58768 
58769 /* ENABLE5 @Bit 5 : Enable region n for master port 5 */
58770   #define MPC_REGION_MASTERPORT_ENABLE5_Pos (5UL)    /*!< Position of ENABLE5 field.                                           */
58771   #define MPC_REGION_MASTERPORT_ENABLE5_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE5_Pos) /*!< Bit mask of ENABLE5 field.       */
58772   #define MPC_REGION_MASTERPORT_ENABLE5_Min (0x0UL)  /*!< Min enumerator value of ENABLE5 field.                               */
58773   #define MPC_REGION_MASTERPORT_ENABLE5_Max (0x1UL)  /*!< Max enumerator value of ENABLE5 field.                               */
58774   #define MPC_REGION_MASTERPORT_ENABLE5_Disable (0x0UL) /*!< Region n is disabled for master port 5                            */
58775   #define MPC_REGION_MASTERPORT_ENABLE5_Enable (0x1UL) /*!< Region n is enabled for master port 5                              */
58776 
58777 /* ENABLE6 @Bit 6 : Enable region n for master port 6 */
58778   #define MPC_REGION_MASTERPORT_ENABLE6_Pos (6UL)    /*!< Position of ENABLE6 field.                                           */
58779   #define MPC_REGION_MASTERPORT_ENABLE6_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE6_Pos) /*!< Bit mask of ENABLE6 field.       */
58780   #define MPC_REGION_MASTERPORT_ENABLE6_Min (0x0UL)  /*!< Min enumerator value of ENABLE6 field.                               */
58781   #define MPC_REGION_MASTERPORT_ENABLE6_Max (0x1UL)  /*!< Max enumerator value of ENABLE6 field.                               */
58782   #define MPC_REGION_MASTERPORT_ENABLE6_Disable (0x0UL) /*!< Region n is disabled for master port 6                            */
58783   #define MPC_REGION_MASTERPORT_ENABLE6_Enable (0x1UL) /*!< Region n is enabled for master port 6                              */
58784 
58785 /* ENABLE7 @Bit 7 : Enable region n for master port 7 */
58786   #define MPC_REGION_MASTERPORT_ENABLE7_Pos (7UL)    /*!< Position of ENABLE7 field.                                           */
58787   #define MPC_REGION_MASTERPORT_ENABLE7_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE7_Pos) /*!< Bit mask of ENABLE7 field.       */
58788   #define MPC_REGION_MASTERPORT_ENABLE7_Min (0x0UL)  /*!< Min enumerator value of ENABLE7 field.                               */
58789   #define MPC_REGION_MASTERPORT_ENABLE7_Max (0x1UL)  /*!< Max enumerator value of ENABLE7 field.                               */
58790   #define MPC_REGION_MASTERPORT_ENABLE7_Disable (0x0UL) /*!< Region n is disabled for master port 7                            */
58791   #define MPC_REGION_MASTERPORT_ENABLE7_Enable (0x1UL) /*!< Region n is enabled for master port 7                              */
58792 
58793 /* ENABLE8 @Bit 8 : Enable region n for master port 8 */
58794   #define MPC_REGION_MASTERPORT_ENABLE8_Pos (8UL)    /*!< Position of ENABLE8 field.                                           */
58795   #define MPC_REGION_MASTERPORT_ENABLE8_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE8_Pos) /*!< Bit mask of ENABLE8 field.       */
58796   #define MPC_REGION_MASTERPORT_ENABLE8_Min (0x0UL)  /*!< Min enumerator value of ENABLE8 field.                               */
58797   #define MPC_REGION_MASTERPORT_ENABLE8_Max (0x1UL)  /*!< Max enumerator value of ENABLE8 field.                               */
58798   #define MPC_REGION_MASTERPORT_ENABLE8_Disable (0x0UL) /*!< Region n is disabled for master port 8                            */
58799   #define MPC_REGION_MASTERPORT_ENABLE8_Enable (0x1UL) /*!< Region n is enabled for master port 8                              */
58800 
58801 /* ENABLE9 @Bit 9 : Enable region n for master port 9 */
58802   #define MPC_REGION_MASTERPORT_ENABLE9_Pos (9UL)    /*!< Position of ENABLE9 field.                                           */
58803   #define MPC_REGION_MASTERPORT_ENABLE9_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE9_Pos) /*!< Bit mask of ENABLE9 field.       */
58804   #define MPC_REGION_MASTERPORT_ENABLE9_Min (0x0UL)  /*!< Min enumerator value of ENABLE9 field.                               */
58805   #define MPC_REGION_MASTERPORT_ENABLE9_Max (0x1UL)  /*!< Max enumerator value of ENABLE9 field.                               */
58806   #define MPC_REGION_MASTERPORT_ENABLE9_Disable (0x0UL) /*!< Region n is disabled for master port 9                            */
58807   #define MPC_REGION_MASTERPORT_ENABLE9_Enable (0x1UL) /*!< Region n is enabled for master port 9                              */
58808 
58809 /* ENABLE10 @Bit 10 : Enable region n for master port 10 */
58810   #define MPC_REGION_MASTERPORT_ENABLE10_Pos (10UL)  /*!< Position of ENABLE10 field.                                          */
58811   #define MPC_REGION_MASTERPORT_ENABLE10_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE10_Pos) /*!< Bit mask of ENABLE10 field.    */
58812   #define MPC_REGION_MASTERPORT_ENABLE10_Min (0x0UL) /*!< Min enumerator value of ENABLE10 field.                              */
58813   #define MPC_REGION_MASTERPORT_ENABLE10_Max (0x1UL) /*!< Max enumerator value of ENABLE10 field.                              */
58814   #define MPC_REGION_MASTERPORT_ENABLE10_Disable (0x0UL) /*!< Region n is disabled for master port 10                          */
58815   #define MPC_REGION_MASTERPORT_ENABLE10_Enable (0x1UL) /*!< Region n is enabled for master port 10                            */
58816 
58817 /* ENABLE11 @Bit 11 : Enable region n for master port 11 */
58818   #define MPC_REGION_MASTERPORT_ENABLE11_Pos (11UL)  /*!< Position of ENABLE11 field.                                          */
58819   #define MPC_REGION_MASTERPORT_ENABLE11_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE11_Pos) /*!< Bit mask of ENABLE11 field.    */
58820   #define MPC_REGION_MASTERPORT_ENABLE11_Min (0x0UL) /*!< Min enumerator value of ENABLE11 field.                              */
58821   #define MPC_REGION_MASTERPORT_ENABLE11_Max (0x1UL) /*!< Max enumerator value of ENABLE11 field.                              */
58822   #define MPC_REGION_MASTERPORT_ENABLE11_Disable (0x0UL) /*!< Region n is disabled for master port 11                          */
58823   #define MPC_REGION_MASTERPORT_ENABLE11_Enable (0x1UL) /*!< Region n is enabled for master port 11                            */
58824 
58825 /* ENABLE12 @Bit 12 : Enable region n for master port 12 */
58826   #define MPC_REGION_MASTERPORT_ENABLE12_Pos (12UL)  /*!< Position of ENABLE12 field.                                          */
58827   #define MPC_REGION_MASTERPORT_ENABLE12_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE12_Pos) /*!< Bit mask of ENABLE12 field.    */
58828   #define MPC_REGION_MASTERPORT_ENABLE12_Min (0x0UL) /*!< Min enumerator value of ENABLE12 field.                              */
58829   #define MPC_REGION_MASTERPORT_ENABLE12_Max (0x1UL) /*!< Max enumerator value of ENABLE12 field.                              */
58830   #define MPC_REGION_MASTERPORT_ENABLE12_Disable (0x0UL) /*!< Region n is disabled for master port 12                          */
58831   #define MPC_REGION_MASTERPORT_ENABLE12_Enable (0x1UL) /*!< Region n is enabled for master port 12                            */
58832 
58833 /* ENABLE13 @Bit 13 : Enable region n for master port 13 */
58834   #define MPC_REGION_MASTERPORT_ENABLE13_Pos (13UL)  /*!< Position of ENABLE13 field.                                          */
58835   #define MPC_REGION_MASTERPORT_ENABLE13_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE13_Pos) /*!< Bit mask of ENABLE13 field.    */
58836   #define MPC_REGION_MASTERPORT_ENABLE13_Min (0x0UL) /*!< Min enumerator value of ENABLE13 field.                              */
58837   #define MPC_REGION_MASTERPORT_ENABLE13_Max (0x1UL) /*!< Max enumerator value of ENABLE13 field.                              */
58838   #define MPC_REGION_MASTERPORT_ENABLE13_Disable (0x0UL) /*!< Region n is disabled for master port 13                          */
58839   #define MPC_REGION_MASTERPORT_ENABLE13_Enable (0x1UL) /*!< Region n is enabled for master port 13                            */
58840 
58841 /* ENABLE14 @Bit 14 : Enable region n for master port 14 */
58842   #define MPC_REGION_MASTERPORT_ENABLE14_Pos (14UL)  /*!< Position of ENABLE14 field.                                          */
58843   #define MPC_REGION_MASTERPORT_ENABLE14_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE14_Pos) /*!< Bit mask of ENABLE14 field.    */
58844   #define MPC_REGION_MASTERPORT_ENABLE14_Min (0x0UL) /*!< Min enumerator value of ENABLE14 field.                              */
58845   #define MPC_REGION_MASTERPORT_ENABLE14_Max (0x1UL) /*!< Max enumerator value of ENABLE14 field.                              */
58846   #define MPC_REGION_MASTERPORT_ENABLE14_Disable (0x0UL) /*!< Region n is disabled for master port 14                          */
58847   #define MPC_REGION_MASTERPORT_ENABLE14_Enable (0x1UL) /*!< Region n is enabled for master port 14                            */
58848 
58849 /* ENABLE15 @Bit 15 : Enable region n for master port 15 */
58850   #define MPC_REGION_MASTERPORT_ENABLE15_Pos (15UL)  /*!< Position of ENABLE15 field.                                          */
58851   #define MPC_REGION_MASTERPORT_ENABLE15_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE15_Pos) /*!< Bit mask of ENABLE15 field.    */
58852   #define MPC_REGION_MASTERPORT_ENABLE15_Min (0x0UL) /*!< Min enumerator value of ENABLE15 field.                              */
58853   #define MPC_REGION_MASTERPORT_ENABLE15_Max (0x1UL) /*!< Max enumerator value of ENABLE15 field.                              */
58854   #define MPC_REGION_MASTERPORT_ENABLE15_Disable (0x0UL) /*!< Region n is disabled for master port 15                          */
58855   #define MPC_REGION_MASTERPORT_ENABLE15_Enable (0x1UL) /*!< Region n is enabled for master port 15                            */
58856 
58857 /* ENABLE16 @Bit 16 : Enable region n for master port 16 */
58858   #define MPC_REGION_MASTERPORT_ENABLE16_Pos (16UL)  /*!< Position of ENABLE16 field.                                          */
58859   #define MPC_REGION_MASTERPORT_ENABLE16_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE16_Pos) /*!< Bit mask of ENABLE16 field.    */
58860   #define MPC_REGION_MASTERPORT_ENABLE16_Min (0x0UL) /*!< Min enumerator value of ENABLE16 field.                              */
58861   #define MPC_REGION_MASTERPORT_ENABLE16_Max (0x1UL) /*!< Max enumerator value of ENABLE16 field.                              */
58862   #define MPC_REGION_MASTERPORT_ENABLE16_Disable (0x0UL) /*!< Region n is disabled for master port 16                          */
58863   #define MPC_REGION_MASTERPORT_ENABLE16_Enable (0x1UL) /*!< Region n is enabled for master port 16                            */
58864 
58865 /* ENABLE17 @Bit 17 : Enable region n for master port 17 */
58866   #define MPC_REGION_MASTERPORT_ENABLE17_Pos (17UL)  /*!< Position of ENABLE17 field.                                          */
58867   #define MPC_REGION_MASTERPORT_ENABLE17_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE17_Pos) /*!< Bit mask of ENABLE17 field.    */
58868   #define MPC_REGION_MASTERPORT_ENABLE17_Min (0x0UL) /*!< Min enumerator value of ENABLE17 field.                              */
58869   #define MPC_REGION_MASTERPORT_ENABLE17_Max (0x1UL) /*!< Max enumerator value of ENABLE17 field.                              */
58870   #define MPC_REGION_MASTERPORT_ENABLE17_Disable (0x0UL) /*!< Region n is disabled for master port 17                          */
58871   #define MPC_REGION_MASTERPORT_ENABLE17_Enable (0x1UL) /*!< Region n is enabled for master port 17                            */
58872 
58873 /* ENABLE18 @Bit 18 : Enable region n for master port 18 */
58874   #define MPC_REGION_MASTERPORT_ENABLE18_Pos (18UL)  /*!< Position of ENABLE18 field.                                          */
58875   #define MPC_REGION_MASTERPORT_ENABLE18_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE18_Pos) /*!< Bit mask of ENABLE18 field.    */
58876   #define MPC_REGION_MASTERPORT_ENABLE18_Min (0x0UL) /*!< Min enumerator value of ENABLE18 field.                              */
58877   #define MPC_REGION_MASTERPORT_ENABLE18_Max (0x1UL) /*!< Max enumerator value of ENABLE18 field.                              */
58878   #define MPC_REGION_MASTERPORT_ENABLE18_Disable (0x0UL) /*!< Region n is disabled for master port 18                          */
58879   #define MPC_REGION_MASTERPORT_ENABLE18_Enable (0x1UL) /*!< Region n is enabled for master port 18                            */
58880 
58881 /* ENABLE19 @Bit 19 : Enable region n for master port 19 */
58882   #define MPC_REGION_MASTERPORT_ENABLE19_Pos (19UL)  /*!< Position of ENABLE19 field.                                          */
58883   #define MPC_REGION_MASTERPORT_ENABLE19_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE19_Pos) /*!< Bit mask of ENABLE19 field.    */
58884   #define MPC_REGION_MASTERPORT_ENABLE19_Min (0x0UL) /*!< Min enumerator value of ENABLE19 field.                              */
58885   #define MPC_REGION_MASTERPORT_ENABLE19_Max (0x1UL) /*!< Max enumerator value of ENABLE19 field.                              */
58886   #define MPC_REGION_MASTERPORT_ENABLE19_Disable (0x0UL) /*!< Region n is disabled for master port 19                          */
58887   #define MPC_REGION_MASTERPORT_ENABLE19_Enable (0x1UL) /*!< Region n is enabled for master port 19                            */
58888 
58889 /* ENABLE20 @Bit 20 : Enable region n for master port 20 */
58890   #define MPC_REGION_MASTERPORT_ENABLE20_Pos (20UL)  /*!< Position of ENABLE20 field.                                          */
58891   #define MPC_REGION_MASTERPORT_ENABLE20_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE20_Pos) /*!< Bit mask of ENABLE20 field.    */
58892   #define MPC_REGION_MASTERPORT_ENABLE20_Min (0x0UL) /*!< Min enumerator value of ENABLE20 field.                              */
58893   #define MPC_REGION_MASTERPORT_ENABLE20_Max (0x1UL) /*!< Max enumerator value of ENABLE20 field.                              */
58894   #define MPC_REGION_MASTERPORT_ENABLE20_Disable (0x0UL) /*!< Region n is disabled for master port 20                          */
58895   #define MPC_REGION_MASTERPORT_ENABLE20_Enable (0x1UL) /*!< Region n is enabled for master port 20                            */
58896 
58897 /* ENABLE21 @Bit 21 : Enable region n for master port 21 */
58898   #define MPC_REGION_MASTERPORT_ENABLE21_Pos (21UL)  /*!< Position of ENABLE21 field.                                          */
58899   #define MPC_REGION_MASTERPORT_ENABLE21_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE21_Pos) /*!< Bit mask of ENABLE21 field.    */
58900   #define MPC_REGION_MASTERPORT_ENABLE21_Min (0x0UL) /*!< Min enumerator value of ENABLE21 field.                              */
58901   #define MPC_REGION_MASTERPORT_ENABLE21_Max (0x1UL) /*!< Max enumerator value of ENABLE21 field.                              */
58902   #define MPC_REGION_MASTERPORT_ENABLE21_Disable (0x0UL) /*!< Region n is disabled for master port 21                          */
58903   #define MPC_REGION_MASTERPORT_ENABLE21_Enable (0x1UL) /*!< Region n is enabled for master port 21                            */
58904 
58905 /* ENABLE22 @Bit 22 : Enable region n for master port 22 */
58906   #define MPC_REGION_MASTERPORT_ENABLE22_Pos (22UL)  /*!< Position of ENABLE22 field.                                          */
58907   #define MPC_REGION_MASTERPORT_ENABLE22_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE22_Pos) /*!< Bit mask of ENABLE22 field.    */
58908   #define MPC_REGION_MASTERPORT_ENABLE22_Min (0x0UL) /*!< Min enumerator value of ENABLE22 field.                              */
58909   #define MPC_REGION_MASTERPORT_ENABLE22_Max (0x1UL) /*!< Max enumerator value of ENABLE22 field.                              */
58910   #define MPC_REGION_MASTERPORT_ENABLE22_Disable (0x0UL) /*!< Region n is disabled for master port 22                          */
58911   #define MPC_REGION_MASTERPORT_ENABLE22_Enable (0x1UL) /*!< Region n is enabled for master port 22                            */
58912 
58913 /* ENABLE23 @Bit 23 : Enable region n for master port 23 */
58914   #define MPC_REGION_MASTERPORT_ENABLE23_Pos (23UL)  /*!< Position of ENABLE23 field.                                          */
58915   #define MPC_REGION_MASTERPORT_ENABLE23_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE23_Pos) /*!< Bit mask of ENABLE23 field.    */
58916   #define MPC_REGION_MASTERPORT_ENABLE23_Min (0x0UL) /*!< Min enumerator value of ENABLE23 field.                              */
58917   #define MPC_REGION_MASTERPORT_ENABLE23_Max (0x1UL) /*!< Max enumerator value of ENABLE23 field.                              */
58918   #define MPC_REGION_MASTERPORT_ENABLE23_Disable (0x0UL) /*!< Region n is disabled for master port 23                          */
58919   #define MPC_REGION_MASTERPORT_ENABLE23_Enable (0x1UL) /*!< Region n is enabled for master port 23                            */
58920 
58921 /* ENABLE24 @Bit 24 : Enable region n for master port 24 */
58922   #define MPC_REGION_MASTERPORT_ENABLE24_Pos (24UL)  /*!< Position of ENABLE24 field.                                          */
58923   #define MPC_REGION_MASTERPORT_ENABLE24_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE24_Pos) /*!< Bit mask of ENABLE24 field.    */
58924   #define MPC_REGION_MASTERPORT_ENABLE24_Min (0x0UL) /*!< Min enumerator value of ENABLE24 field.                              */
58925   #define MPC_REGION_MASTERPORT_ENABLE24_Max (0x1UL) /*!< Max enumerator value of ENABLE24 field.                              */
58926   #define MPC_REGION_MASTERPORT_ENABLE24_Disable (0x0UL) /*!< Region n is disabled for master port 24                          */
58927   #define MPC_REGION_MASTERPORT_ENABLE24_Enable (0x1UL) /*!< Region n is enabled for master port 24                            */
58928 
58929 /* ENABLE25 @Bit 25 : Enable region n for master port 25 */
58930   #define MPC_REGION_MASTERPORT_ENABLE25_Pos (25UL)  /*!< Position of ENABLE25 field.                                          */
58931   #define MPC_REGION_MASTERPORT_ENABLE25_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE25_Pos) /*!< Bit mask of ENABLE25 field.    */
58932   #define MPC_REGION_MASTERPORT_ENABLE25_Min (0x0UL) /*!< Min enumerator value of ENABLE25 field.                              */
58933   #define MPC_REGION_MASTERPORT_ENABLE25_Max (0x1UL) /*!< Max enumerator value of ENABLE25 field.                              */
58934   #define MPC_REGION_MASTERPORT_ENABLE25_Disable (0x0UL) /*!< Region n is disabled for master port 25                          */
58935   #define MPC_REGION_MASTERPORT_ENABLE25_Enable (0x1UL) /*!< Region n is enabled for master port 25                            */
58936 
58937 /* ENABLE26 @Bit 26 : Enable region n for master port 26 */
58938   #define MPC_REGION_MASTERPORT_ENABLE26_Pos (26UL)  /*!< Position of ENABLE26 field.                                          */
58939   #define MPC_REGION_MASTERPORT_ENABLE26_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE26_Pos) /*!< Bit mask of ENABLE26 field.    */
58940   #define MPC_REGION_MASTERPORT_ENABLE26_Min (0x0UL) /*!< Min enumerator value of ENABLE26 field.                              */
58941   #define MPC_REGION_MASTERPORT_ENABLE26_Max (0x1UL) /*!< Max enumerator value of ENABLE26 field.                              */
58942   #define MPC_REGION_MASTERPORT_ENABLE26_Disable (0x0UL) /*!< Region n is disabled for master port 26                          */
58943   #define MPC_REGION_MASTERPORT_ENABLE26_Enable (0x1UL) /*!< Region n is enabled for master port 26                            */
58944 
58945 /* ENABLE27 @Bit 27 : Enable region n for master port 27 */
58946   #define MPC_REGION_MASTERPORT_ENABLE27_Pos (27UL)  /*!< Position of ENABLE27 field.                                          */
58947   #define MPC_REGION_MASTERPORT_ENABLE27_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE27_Pos) /*!< Bit mask of ENABLE27 field.    */
58948   #define MPC_REGION_MASTERPORT_ENABLE27_Min (0x0UL) /*!< Min enumerator value of ENABLE27 field.                              */
58949   #define MPC_REGION_MASTERPORT_ENABLE27_Max (0x1UL) /*!< Max enumerator value of ENABLE27 field.                              */
58950   #define MPC_REGION_MASTERPORT_ENABLE27_Disable (0x0UL) /*!< Region n is disabled for master port 27                          */
58951   #define MPC_REGION_MASTERPORT_ENABLE27_Enable (0x1UL) /*!< Region n is enabled for master port 27                            */
58952 
58953 /* ENABLE28 @Bit 28 : Enable region n for master port 28 */
58954   #define MPC_REGION_MASTERPORT_ENABLE28_Pos (28UL)  /*!< Position of ENABLE28 field.                                          */
58955   #define MPC_REGION_MASTERPORT_ENABLE28_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE28_Pos) /*!< Bit mask of ENABLE28 field.    */
58956   #define MPC_REGION_MASTERPORT_ENABLE28_Min (0x0UL) /*!< Min enumerator value of ENABLE28 field.                              */
58957   #define MPC_REGION_MASTERPORT_ENABLE28_Max (0x1UL) /*!< Max enumerator value of ENABLE28 field.                              */
58958   #define MPC_REGION_MASTERPORT_ENABLE28_Disable (0x0UL) /*!< Region n is disabled for master port 28                          */
58959   #define MPC_REGION_MASTERPORT_ENABLE28_Enable (0x1UL) /*!< Region n is enabled for master port 28                            */
58960 
58961 /* ENABLE29 @Bit 29 : Enable region n for master port 29 */
58962   #define MPC_REGION_MASTERPORT_ENABLE29_Pos (29UL)  /*!< Position of ENABLE29 field.                                          */
58963   #define MPC_REGION_MASTERPORT_ENABLE29_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE29_Pos) /*!< Bit mask of ENABLE29 field.    */
58964   #define MPC_REGION_MASTERPORT_ENABLE29_Min (0x0UL) /*!< Min enumerator value of ENABLE29 field.                              */
58965   #define MPC_REGION_MASTERPORT_ENABLE29_Max (0x1UL) /*!< Max enumerator value of ENABLE29 field.                              */
58966   #define MPC_REGION_MASTERPORT_ENABLE29_Disable (0x0UL) /*!< Region n is disabled for master port 29                          */
58967   #define MPC_REGION_MASTERPORT_ENABLE29_Enable (0x1UL) /*!< Region n is enabled for master port 29                            */
58968 
58969 /* ENABLE30 @Bit 30 : Enable region n for master port 30 */
58970   #define MPC_REGION_MASTERPORT_ENABLE30_Pos (30UL)  /*!< Position of ENABLE30 field.                                          */
58971   #define MPC_REGION_MASTERPORT_ENABLE30_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE30_Pos) /*!< Bit mask of ENABLE30 field.    */
58972   #define MPC_REGION_MASTERPORT_ENABLE30_Min (0x0UL) /*!< Min enumerator value of ENABLE30 field.                              */
58973   #define MPC_REGION_MASTERPORT_ENABLE30_Max (0x1UL) /*!< Max enumerator value of ENABLE30 field.                              */
58974   #define MPC_REGION_MASTERPORT_ENABLE30_Disable (0x0UL) /*!< Region n is disabled for master port 30                          */
58975   #define MPC_REGION_MASTERPORT_ENABLE30_Enable (0x1UL) /*!< Region n is enabled for master port 30                            */
58976 
58977 /* ENABLE31 @Bit 31 : Enable region n for master port 31 */
58978   #define MPC_REGION_MASTERPORT_ENABLE31_Pos (31UL)  /*!< Position of ENABLE31 field.                                          */
58979   #define MPC_REGION_MASTERPORT_ENABLE31_Msk (0x1UL << MPC_REGION_MASTERPORT_ENABLE31_Pos) /*!< Bit mask of ENABLE31 field.    */
58980   #define MPC_REGION_MASTERPORT_ENABLE31_Min (0x0UL) /*!< Min enumerator value of ENABLE31 field.                              */
58981   #define MPC_REGION_MASTERPORT_ENABLE31_Max (0x1UL) /*!< Max enumerator value of ENABLE31 field.                              */
58982   #define MPC_REGION_MASTERPORT_ENABLE31_Disable (0x0UL) /*!< Region n is disabled for master port 31                          */
58983   #define MPC_REGION_MASTERPORT_ENABLE31_Enable (0x1UL) /*!< Region n is enabled for master port 31                            */
58984 
58985 
58986 
58987 /* =================================================== Struct MPC_OVERRIDE =================================================== */
58988 /**
58989   * @brief OVERRIDE [MPC_OVERRIDE] Special privilege tables
58990   */
58991 typedef struct {
58992   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Override region n Configuration register              */
58993   __IOM uint32_t  STARTADDR;                         /*!< (@ 0x00000004) Override region n Start Address                       */
58994   __IOM uint32_t  ENDADDR;                           /*!< (@ 0x00000008) Override region n End Address                         */
58995   __IOM int32_t   OFFSET;                            /*!< (@ 0x0000000C) Address offset value divided by 2 for override region n
58996                                                                          address re-map*/
58997   __IOM uint32_t  PERM;                              /*!< (@ 0x00000010) Permission settings for override region n             */
58998   __IOM uint32_t  PERMMASK;                          /*!< (@ 0x00000014) Masks permission setting fields from register
58999                                                                          OVERRIDE.PERM*/
59000   __IOM uint32_t  OWNER;                             /*!< (@ 0x00000018) Owner for override region                             */
59001   __IOM uint32_t  MASTERPORT;                        /*!< (@ 0x0000001C) Override region n local master enable                 */
59002 } NRF_MPC_OVERRIDE_Type;                             /*!< Size = 32 (0x020)                                                    */
59003   #define MPC_OVERRIDE_MaxCount (40UL)               /*!< Size of OVERRIDE[40] array.                                          */
59004   #define MPC_OVERRIDE_MaxIndex (39UL)               /*!< Max index of OVERRIDE[40] array.                                     */
59005   #define MPC_OVERRIDE_MinIndex (0UL)                /*!< Min index of OVERRIDE[40] array.                                     */
59006 
59007 /* MPC_OVERRIDE_CONFIG: Override region n Configuration register */
59008   #define MPC_OVERRIDE_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                                   */
59009 
59010 /* SLAVENUMBER @Bits 0..4 : Target slave number for override region n accesses. Slave number 0 is reserved for default slave */
59011   #define MPC_OVERRIDE_CONFIG_SLAVENUMBER_Pos (0UL)  /*!< Position of SLAVENUMBER field.                                       */
59012   #define MPC_OVERRIDE_CONFIG_SLAVENUMBER_Msk (0x1FUL << MPC_OVERRIDE_CONFIG_SLAVENUMBER_Pos) /*!< Bit mask of SLAVENUMBER
59013                                                                             field.*/
59014   #define MPC_OVERRIDE_CONFIG_SLAVENUMBER_Min (0x0UL) /*!< Min value of SLAVENUMBER field.                                     */
59015   #define MPC_OVERRIDE_CONFIG_SLAVENUMBER_Max (0x1FUL) /*!< Max size of SLAVENUMBER field.                                     */
59016 
59017 /* LOCK @Bit 8 : Lock Override region n */
59018   #define MPC_OVERRIDE_CONFIG_LOCK_Pos (8UL)         /*!< Position of LOCK field.                                              */
59019   #define MPC_OVERRIDE_CONFIG_LOCK_Msk (0x1UL << MPC_OVERRIDE_CONFIG_LOCK_Pos) /*!< Bit mask of LOCK field.                    */
59020   #define MPC_OVERRIDE_CONFIG_LOCK_Min (0x0UL)       /*!< Min enumerator value of LOCK field.                                  */
59021   #define MPC_OVERRIDE_CONFIG_LOCK_Max (0x1UL)       /*!< Max enumerator value of LOCK field.                                  */
59022   #define MPC_OVERRIDE_CONFIG_LOCK_Unlocked (0x0UL)  /*!< Override region n settings can be updated                            */
59023   #define MPC_OVERRIDE_CONFIG_LOCK_Locked (0x1UL)    /*!< Override region n settings can't be updated until next reset         */
59024 
59025 /* ENABLE @Bit 9 : Enable Override region n */
59026   #define MPC_OVERRIDE_CONFIG_ENABLE_Pos (9UL)       /*!< Position of ENABLE field.                                            */
59027   #define MPC_OVERRIDE_CONFIG_ENABLE_Msk (0x1UL << MPC_OVERRIDE_CONFIG_ENABLE_Pos) /*!< Bit mask of ENABLE field.              */
59028   #define MPC_OVERRIDE_CONFIG_ENABLE_Min (0x0UL)     /*!< Min enumerator value of ENABLE field.                                */
59029   #define MPC_OVERRIDE_CONFIG_ENABLE_Max (0x1UL)     /*!< Max enumerator value of ENABLE field.                                */
59030   #define MPC_OVERRIDE_CONFIG_ENABLE_Disabled (0x0UL) /*!< Override region n is not used                                       */
59031   #define MPC_OVERRIDE_CONFIG_ENABLE_Enabled (0x1UL) /*!< Override region n is used                                            */
59032 
59033 /* SECDOMENABLE @Bit 10 : Secure domain access enable for Override region n */
59034   #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Pos (10UL) /*!< Position of SECDOMENABLE field.                                     */
59035   #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Msk (0x1UL << MPC_OVERRIDE_CONFIG_SECDOMENABLE_Pos) /*!< Bit mask of SECDOMENABLE
59036                                                                             field.*/
59037   #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Min (0x0UL) /*!< Min enumerator value of SECDOMENABLE field.                        */
59038   #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Max (0x1UL) /*!< Max enumerator value of SECDOMENABLE field.                        */
59039   #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Disabled (0x0UL) /*!< Overriding of secure domain permissions is disabled for
59040                                                                  override region n*/
59041   #define MPC_OVERRIDE_CONFIG_SECDOMENABLE_Enabled (0x1UL) /*!< Overriding of secure domain permissions is enabled for override
59042                                                                 region n*/
59043 
59044 /* SECUREMASK @Bit 12 : Secure mask enable for Override region n */
59045   #define MPC_OVERRIDE_CONFIG_SECUREMASK_Pos (12UL)  /*!< Position of SECUREMASK field.                                        */
59046   #define MPC_OVERRIDE_CONFIG_SECUREMASK_Msk (0x1UL << MPC_OVERRIDE_CONFIG_SECUREMASK_Pos) /*!< Bit mask of SECUREMASK field.  */
59047   #define MPC_OVERRIDE_CONFIG_SECUREMASK_Min (0x0UL) /*!< Min enumerator value of SECUREMASK field.                            */
59048   #define MPC_OVERRIDE_CONFIG_SECUREMASK_Max (0x1UL) /*!< Max enumerator value of SECUREMASK field.                            */
59049   #define MPC_OVERRIDE_CONFIG_SECUREMASK_Disabled (0x0UL) /*!< Mask is disabled for override region n                          */
59050   #define MPC_OVERRIDE_CONFIG_SECUREMASK_Enabled (0x1UL) /*!< Mask is enabled for override region n                            */
59051 
59052 
59053 /* MPC_OVERRIDE_STARTADDR: Override region n Start Address */
59054   #define MPC_OVERRIDE_STARTADDR_ResetValue (0x00000000UL) /*!< Reset value of STARTADDR register.                             */
59055 
59056 /* STARTADDR @Bits 0..31 : Start address for override region n */
59057   #define MPC_OVERRIDE_STARTADDR_STARTADDR_Pos (0UL) /*!< Position of STARTADDR field.                                         */
59058   #define MPC_OVERRIDE_STARTADDR_STARTADDR_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_STARTADDR_STARTADDR_Pos) /*!< Bit mask of STARTADDR
59059                                                                             field.*/
59060 
59061 
59062 /* MPC_OVERRIDE_ENDADDR: Override region n End Address */
59063   #define MPC_OVERRIDE_ENDADDR_ResetValue (0x00000000UL) /*!< Reset value of ENDADDR register.                                 */
59064 
59065 /* ENDADDR @Bits 0..31 : End address for override region n */
59066   #define MPC_OVERRIDE_ENDADDR_ENDADDR_Pos (0UL)     /*!< Position of ENDADDR field.                                           */
59067   #define MPC_OVERRIDE_ENDADDR_ENDADDR_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_ENDADDR_ENDADDR_Pos) /*!< Bit mask of ENDADDR field.  */
59068 
59069 
59070 /* MPC_OVERRIDE_OFFSET: Address offset value divided by 2 for override region n address re-map */
59071   #define MPC_OVERRIDE_OFFSET_ResetValue (0x00000000UL) /*!< Reset value of OFFSET register.                                   */
59072 
59073 /* OFFSET @Bits 0..31 : Offset value */
59074   #define MPC_OVERRIDE_OFFSET_OFFSET_Pos (0UL)       /*!< Position of OFFSET field.                                            */
59075   #define MPC_OVERRIDE_OFFSET_OFFSET_Msk (0xFFFFFFFFUL << MPC_OVERRIDE_OFFSET_OFFSET_Pos) /*!< Bit mask of OFFSET field.       */
59076 
59077 
59078 /* MPC_OVERRIDE_PERM: Permission settings for override region n */
59079   #define MPC_OVERRIDE_PERM_ResetValue (0x00000000UL) /*!< Reset value of PERM register.                                       */
59080 
59081 /* READ @Bit 0 : Read access */
59082   #define MPC_OVERRIDE_PERM_READ_Pos (0UL)           /*!< Position of READ field.                                              */
59083   #define MPC_OVERRIDE_PERM_READ_Msk (0x1UL << MPC_OVERRIDE_PERM_READ_Pos) /*!< Bit mask of READ field.                        */
59084   #define MPC_OVERRIDE_PERM_READ_Min (0x0UL)         /*!< Min enumerator value of READ field.                                  */
59085   #define MPC_OVERRIDE_PERM_READ_Max (0x1UL)         /*!< Max enumerator value of READ field.                                  */
59086   #define MPC_OVERRIDE_PERM_READ_NotAllowed (0x0UL)  /*!< Read access to override region n is not allowed                      */
59087   #define MPC_OVERRIDE_PERM_READ_Allowed (0x1UL)     /*!< Read access to override region n is allowed                          */
59088 
59089 /* WRITE @Bit 1 : Write access */
59090   #define MPC_OVERRIDE_PERM_WRITE_Pos (1UL)          /*!< Position of WRITE field.                                             */
59091   #define MPC_OVERRIDE_PERM_WRITE_Msk (0x1UL << MPC_OVERRIDE_PERM_WRITE_Pos) /*!< Bit mask of WRITE field.                     */
59092   #define MPC_OVERRIDE_PERM_WRITE_Min (0x0UL)        /*!< Min enumerator value of WRITE field.                                 */
59093   #define MPC_OVERRIDE_PERM_WRITE_Max (0x1UL)        /*!< Max enumerator value of WRITE field.                                 */
59094   #define MPC_OVERRIDE_PERM_WRITE_NotAllowed (0x0UL) /*!< Write access to override region n is not allowed                     */
59095   #define MPC_OVERRIDE_PERM_WRITE_Allowed (0x1UL)    /*!< Write access to override region n is allowed                         */
59096 
59097 /* EXECUTE @Bit 2 : Software execute */
59098   #define MPC_OVERRIDE_PERM_EXECUTE_Pos (2UL)        /*!< Position of EXECUTE field.                                           */
59099   #define MPC_OVERRIDE_PERM_EXECUTE_Msk (0x1UL << MPC_OVERRIDE_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.               */
59100   #define MPC_OVERRIDE_PERM_EXECUTE_Min (0x0UL)      /*!< Min enumerator value of EXECUTE field.                               */
59101   #define MPC_OVERRIDE_PERM_EXECUTE_Max (0x1UL)      /*!< Max enumerator value of EXECUTE field.                               */
59102   #define MPC_OVERRIDE_PERM_EXECUTE_NotAllowed (0x0UL) /*!< Software execution from override region n is not allowed           */
59103   #define MPC_OVERRIDE_PERM_EXECUTE_Allowed (0x1UL)  /*!< Software execution from override region n is allowed                 */
59104 
59105 /* SECATTR @Bit 3 : Security mapping */
59106   #define MPC_OVERRIDE_PERM_SECATTR_Pos (3UL)        /*!< Position of SECATTR field.                                           */
59107   #define MPC_OVERRIDE_PERM_SECATTR_Msk (0x1UL << MPC_OVERRIDE_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field.               */
59108   #define MPC_OVERRIDE_PERM_SECATTR_Min (0x0UL)      /*!< Min enumerator value of SECATTR field.                               */
59109   #define MPC_OVERRIDE_PERM_SECATTR_Max (0x1UL)      /*!< Max enumerator value of SECATTR field.                               */
59110   #define MPC_OVERRIDE_PERM_SECATTR_Secure (0x1UL)   /*!< Override region n is mapped in secure memory address space           */
59111   #define MPC_OVERRIDE_PERM_SECATTR_NonSecure (0x0UL) /*!< Override region n is mapped in non-secure memory address space      */
59112 
59113 
59114 /* MPC_OVERRIDE_PERMMASK: Masks permission setting fields from register OVERRIDE.PERM */
59115   #define MPC_OVERRIDE_PERMMASK_ResetValue (0x00000000UL) /*!< Reset value of PERMMASK register.                               */
59116 
59117 /* READ @Bit 0 : Read mask */
59118   #define MPC_OVERRIDE_PERMMASK_READ_Pos (0UL)       /*!< Position of READ field.                                              */
59119   #define MPC_OVERRIDE_PERMMASK_READ_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_READ_Pos) /*!< Bit mask of READ field.                */
59120   #define MPC_OVERRIDE_PERMMASK_READ_Min (0x0UL)     /*!< Min enumerator value of READ field.                                  */
59121   #define MPC_OVERRIDE_PERMMASK_READ_Max (0x1UL)     /*!< Max enumerator value of READ field.                                  */
59122   #define MPC_OVERRIDE_PERMMASK_READ_Masked (0x0UL)  /*!< Permission setting READ in OVERRIDE register will not be applied     */
59123   #define MPC_OVERRIDE_PERMMASK_READ_UnMasked (0x1UL) /*!< Permission setting READ in OVERRIDE register will be applied        */
59124 
59125 /* WRITE @Bit 1 : Write mask */
59126   #define MPC_OVERRIDE_PERMMASK_WRITE_Pos (1UL)      /*!< Position of WRITE field.                                             */
59127   #define MPC_OVERRIDE_PERMMASK_WRITE_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_WRITE_Pos) /*!< Bit mask of WRITE field.             */
59128   #define MPC_OVERRIDE_PERMMASK_WRITE_Min (0x0UL)    /*!< Min enumerator value of WRITE field.                                 */
59129   #define MPC_OVERRIDE_PERMMASK_WRITE_Max (0x1UL)    /*!< Max enumerator value of WRITE field.                                 */
59130   #define MPC_OVERRIDE_PERMMASK_WRITE_Masked (0x0UL) /*!< Permission setting WRITE in OVERRIDE register will not be applied    */
59131   #define MPC_OVERRIDE_PERMMASK_WRITE_UnMasked (0x1UL) /*!< Permission setting WRITE in OVERRIDE register will be applied      */
59132 
59133 /* EXECUTE @Bit 2 : Execute mask */
59134   #define MPC_OVERRIDE_PERMMASK_EXECUTE_Pos (2UL)    /*!< Position of EXECUTE field.                                           */
59135   #define MPC_OVERRIDE_PERMMASK_EXECUTE_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.       */
59136   #define MPC_OVERRIDE_PERMMASK_EXECUTE_Min (0x0UL)  /*!< Min enumerator value of EXECUTE field.                               */
59137   #define MPC_OVERRIDE_PERMMASK_EXECUTE_Max (0x1UL)  /*!< Max enumerator value of EXECUTE field.                               */
59138   #define MPC_OVERRIDE_PERMMASK_EXECUTE_Masked (0x0UL) /*!< Permission setting EXECUTE in OVERRIDE register will not be applied*/
59139   #define MPC_OVERRIDE_PERMMASK_EXECUTE_UnMasked (0x1UL) /*!< Permission setting EXECUTE in OVERRIDE register will be applied  */
59140 
59141 /* SECATTR @Bit 3 : Security mapping mask */
59142   #define MPC_OVERRIDE_PERMMASK_SECATTR_Pos (3UL)    /*!< Position of SECATTR field.                                           */
59143   #define MPC_OVERRIDE_PERMMASK_SECATTR_Msk (0x1UL << MPC_OVERRIDE_PERMMASK_SECATTR_Pos) /*!< Bit mask of SECATTR field.       */
59144   #define MPC_OVERRIDE_PERMMASK_SECATTR_Min (0x0UL)  /*!< Min enumerator value of SECATTR field.                               */
59145   #define MPC_OVERRIDE_PERMMASK_SECATTR_Max (0x1UL)  /*!< Max enumerator value of SECATTR field.                               */
59146   #define MPC_OVERRIDE_PERMMASK_SECATTR_Masked (0x0UL) /*!< Permission setting SECATTR in OVERRIDE register will not be applied*/
59147   #define MPC_OVERRIDE_PERMMASK_SECATTR_UnMasked (0x1UL) /*!< Permission setting SECATTR in OVERRIDE register will be applied  */
59148 
59149 
59150 /* MPC_OVERRIDE_OWNER: Owner for override region */
59151   #define MPC_OVERRIDE_OWNER_ResetValue (0x00000000UL) /*!< Reset value of OWNER register.                                     */
59152 
59153 /* OWNERID @Bits 0..3 : owner identifier for override region n */
59154   #define MPC_OVERRIDE_OWNER_OWNERID_Pos (0UL)       /*!< Position of OWNERID field.                                           */
59155   #define MPC_OVERRIDE_OWNER_OWNERID_Msk (0xFUL << MPC_OVERRIDE_OWNER_OWNERID_Pos) /*!< Bit mask of OWNERID field.             */
59156   #define MPC_OVERRIDE_OWNER_OWNERID_Min (0x0UL)     /*!< Min value of OWNERID field.                                          */
59157   #define MPC_OVERRIDE_OWNER_OWNERID_Max (0xFUL)     /*!< Max size of OWNERID field.                                           */
59158 
59159 
59160 /* MPC_OVERRIDE_MASTERPORT: Override region n local master enable */
59161   #define MPC_OVERRIDE_MASTERPORT_ResetValue (0x00000000UL) /*!< Reset value of MASTERPORT register.                           */
59162 
59163 /* ENABLE0 @Bit 0 : Enable override */
59164   #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Pos (0UL)  /*!< Position of ENABLE0 field.                                           */
59165   #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE0_Pos) /*!< Bit mask of ENABLE0 field.   */
59166   #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Min (0x0UL) /*!< Min enumerator value of ENABLE0 field.                              */
59167   #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Max (0x1UL) /*!< Max enumerator value of ENABLE0 field.                              */
59168   #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Disable (0x0UL) /*!< Override region n is disabled for master port 0                 */
59169   #define MPC_OVERRIDE_MASTERPORT_ENABLE0_Enable (0x1UL) /*!< Override region n is enabled for master port 0                   */
59170 
59171 /* ENABLE1 @Bit 1 : Enable override */
59172   #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Pos (1UL)  /*!< Position of ENABLE1 field.                                           */
59173   #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE1_Pos) /*!< Bit mask of ENABLE1 field.   */
59174   #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Min (0x0UL) /*!< Min enumerator value of ENABLE1 field.                              */
59175   #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Max (0x1UL) /*!< Max enumerator value of ENABLE1 field.                              */
59176   #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Disable (0x0UL) /*!< Override region n is disabled for master port 1                 */
59177   #define MPC_OVERRIDE_MASTERPORT_ENABLE1_Enable (0x1UL) /*!< Override region n is enabled for master port 1                   */
59178 
59179 /* ENABLE2 @Bit 2 : Enable override */
59180   #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Pos (2UL)  /*!< Position of ENABLE2 field.                                           */
59181   #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE2_Pos) /*!< Bit mask of ENABLE2 field.   */
59182   #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Min (0x0UL) /*!< Min enumerator value of ENABLE2 field.                              */
59183   #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Max (0x1UL) /*!< Max enumerator value of ENABLE2 field.                              */
59184   #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Disable (0x0UL) /*!< Override region n is disabled for master port 2                 */
59185   #define MPC_OVERRIDE_MASTERPORT_ENABLE2_Enable (0x1UL) /*!< Override region n is enabled for master port 2                   */
59186 
59187 /* ENABLE3 @Bit 3 : Enable override */
59188   #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Pos (3UL)  /*!< Position of ENABLE3 field.                                           */
59189   #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE3_Pos) /*!< Bit mask of ENABLE3 field.   */
59190   #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Min (0x0UL) /*!< Min enumerator value of ENABLE3 field.                              */
59191   #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Max (0x1UL) /*!< Max enumerator value of ENABLE3 field.                              */
59192   #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Disable (0x0UL) /*!< Override region n is disabled for master port 3                 */
59193   #define MPC_OVERRIDE_MASTERPORT_ENABLE3_Enable (0x1UL) /*!< Override region n is enabled for master port 3                   */
59194 
59195 /* ENABLE4 @Bit 4 : Enable override */
59196   #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Pos (4UL)  /*!< Position of ENABLE4 field.                                           */
59197   #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE4_Pos) /*!< Bit mask of ENABLE4 field.   */
59198   #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Min (0x0UL) /*!< Min enumerator value of ENABLE4 field.                              */
59199   #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Max (0x1UL) /*!< Max enumerator value of ENABLE4 field.                              */
59200   #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Disable (0x0UL) /*!< Override region n is disabled for master port 4                 */
59201   #define MPC_OVERRIDE_MASTERPORT_ENABLE4_Enable (0x1UL) /*!< Override region n is enabled for master port 4                   */
59202 
59203 /* ENABLE5 @Bit 5 : Enable override */
59204   #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Pos (5UL)  /*!< Position of ENABLE5 field.                                           */
59205   #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE5_Pos) /*!< Bit mask of ENABLE5 field.   */
59206   #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Min (0x0UL) /*!< Min enumerator value of ENABLE5 field.                              */
59207   #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Max (0x1UL) /*!< Max enumerator value of ENABLE5 field.                              */
59208   #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Disable (0x0UL) /*!< Override region n is disabled for master port 5                 */
59209   #define MPC_OVERRIDE_MASTERPORT_ENABLE5_Enable (0x1UL) /*!< Override region n is enabled for master port 5                   */
59210 
59211 /* ENABLE6 @Bit 6 : Enable override */
59212   #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Pos (6UL)  /*!< Position of ENABLE6 field.                                           */
59213   #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE6_Pos) /*!< Bit mask of ENABLE6 field.   */
59214   #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Min (0x0UL) /*!< Min enumerator value of ENABLE6 field.                              */
59215   #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Max (0x1UL) /*!< Max enumerator value of ENABLE6 field.                              */
59216   #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Disable (0x0UL) /*!< Override region n is disabled for master port 6                 */
59217   #define MPC_OVERRIDE_MASTERPORT_ENABLE6_Enable (0x1UL) /*!< Override region n is enabled for master port 6                   */
59218 
59219 /* ENABLE7 @Bit 7 : Enable override */
59220   #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Pos (7UL)  /*!< Position of ENABLE7 field.                                           */
59221   #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE7_Pos) /*!< Bit mask of ENABLE7 field.   */
59222   #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Min (0x0UL) /*!< Min enumerator value of ENABLE7 field.                              */
59223   #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Max (0x1UL) /*!< Max enumerator value of ENABLE7 field.                              */
59224   #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Disable (0x0UL) /*!< Override region n is disabled for master port 7                 */
59225   #define MPC_OVERRIDE_MASTERPORT_ENABLE7_Enable (0x1UL) /*!< Override region n is enabled for master port 7                   */
59226 
59227 /* ENABLE8 @Bit 8 : Enable override */
59228   #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Pos (8UL)  /*!< Position of ENABLE8 field.                                           */
59229   #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE8_Pos) /*!< Bit mask of ENABLE8 field.   */
59230   #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Min (0x0UL) /*!< Min enumerator value of ENABLE8 field.                              */
59231   #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Max (0x1UL) /*!< Max enumerator value of ENABLE8 field.                              */
59232   #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Disable (0x0UL) /*!< Override region n is disabled for master port 8                 */
59233   #define MPC_OVERRIDE_MASTERPORT_ENABLE8_Enable (0x1UL) /*!< Override region n is enabled for master port 8                   */
59234 
59235 /* ENABLE9 @Bit 9 : Enable override */
59236   #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Pos (9UL)  /*!< Position of ENABLE9 field.                                           */
59237   #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE9_Pos) /*!< Bit mask of ENABLE9 field.   */
59238   #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Min (0x0UL) /*!< Min enumerator value of ENABLE9 field.                              */
59239   #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Max (0x1UL) /*!< Max enumerator value of ENABLE9 field.                              */
59240   #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Disable (0x0UL) /*!< Override region n is disabled for master port 9                 */
59241   #define MPC_OVERRIDE_MASTERPORT_ENABLE9_Enable (0x1UL) /*!< Override region n is enabled for master port 9                   */
59242 
59243 /* ENABLE10 @Bit 10 : Enable override */
59244   #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Pos (10UL) /*!< Position of ENABLE10 field.                                         */
59245   #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE10_Pos) /*!< Bit mask of ENABLE10 field.*/
59246   #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Min (0x0UL) /*!< Min enumerator value of ENABLE10 field.                            */
59247   #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Max (0x1UL) /*!< Max enumerator value of ENABLE10 field.                            */
59248   #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Disable (0x0UL) /*!< Override region n is disabled for master port 10               */
59249   #define MPC_OVERRIDE_MASTERPORT_ENABLE10_Enable (0x1UL) /*!< Override region n is enabled for master port 10                 */
59250 
59251 /* ENABLE11 @Bit 11 : Enable override */
59252   #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Pos (11UL) /*!< Position of ENABLE11 field.                                         */
59253   #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE11_Pos) /*!< Bit mask of ENABLE11 field.*/
59254   #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Min (0x0UL) /*!< Min enumerator value of ENABLE11 field.                            */
59255   #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Max (0x1UL) /*!< Max enumerator value of ENABLE11 field.                            */
59256   #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Disable (0x0UL) /*!< Override region n is disabled for master port 11               */
59257   #define MPC_OVERRIDE_MASTERPORT_ENABLE11_Enable (0x1UL) /*!< Override region n is enabled for master port 11                 */
59258 
59259 /* ENABLE12 @Bit 12 : Enable override */
59260   #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Pos (12UL) /*!< Position of ENABLE12 field.                                         */
59261   #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE12_Pos) /*!< Bit mask of ENABLE12 field.*/
59262   #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Min (0x0UL) /*!< Min enumerator value of ENABLE12 field.                            */
59263   #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Max (0x1UL) /*!< Max enumerator value of ENABLE12 field.                            */
59264   #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Disable (0x0UL) /*!< Override region n is disabled for master port 12               */
59265   #define MPC_OVERRIDE_MASTERPORT_ENABLE12_Enable (0x1UL) /*!< Override region n is enabled for master port 12                 */
59266 
59267 /* ENABLE13 @Bit 13 : Enable override */
59268   #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Pos (13UL) /*!< Position of ENABLE13 field.                                         */
59269   #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE13_Pos) /*!< Bit mask of ENABLE13 field.*/
59270   #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Min (0x0UL) /*!< Min enumerator value of ENABLE13 field.                            */
59271   #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Max (0x1UL) /*!< Max enumerator value of ENABLE13 field.                            */
59272   #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Disable (0x0UL) /*!< Override region n is disabled for master port 13               */
59273   #define MPC_OVERRIDE_MASTERPORT_ENABLE13_Enable (0x1UL) /*!< Override region n is enabled for master port 13                 */
59274 
59275 /* ENABLE14 @Bit 14 : Enable override */
59276   #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Pos (14UL) /*!< Position of ENABLE14 field.                                         */
59277   #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE14_Pos) /*!< Bit mask of ENABLE14 field.*/
59278   #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Min (0x0UL) /*!< Min enumerator value of ENABLE14 field.                            */
59279   #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Max (0x1UL) /*!< Max enumerator value of ENABLE14 field.                            */
59280   #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Disable (0x0UL) /*!< Override region n is disabled for master port 14               */
59281   #define MPC_OVERRIDE_MASTERPORT_ENABLE14_Enable (0x1UL) /*!< Override region n is enabled for master port 14                 */
59282 
59283 /* ENABLE15 @Bit 15 : Enable override */
59284   #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Pos (15UL) /*!< Position of ENABLE15 field.                                         */
59285   #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE15_Pos) /*!< Bit mask of ENABLE15 field.*/
59286   #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Min (0x0UL) /*!< Min enumerator value of ENABLE15 field.                            */
59287   #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Max (0x1UL) /*!< Max enumerator value of ENABLE15 field.                            */
59288   #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Disable (0x0UL) /*!< Override region n is disabled for master port 15               */
59289   #define MPC_OVERRIDE_MASTERPORT_ENABLE15_Enable (0x1UL) /*!< Override region n is enabled for master port 15                 */
59290 
59291 /* ENABLE16 @Bit 16 : Enable override */
59292   #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Pos (16UL) /*!< Position of ENABLE16 field.                                         */
59293   #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE16_Pos) /*!< Bit mask of ENABLE16 field.*/
59294   #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Min (0x0UL) /*!< Min enumerator value of ENABLE16 field.                            */
59295   #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Max (0x1UL) /*!< Max enumerator value of ENABLE16 field.                            */
59296   #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Disable (0x0UL) /*!< Override region n is disabled for master port 16               */
59297   #define MPC_OVERRIDE_MASTERPORT_ENABLE16_Enable (0x1UL) /*!< Override region n is enabled for master port 16                 */
59298 
59299 /* ENABLE17 @Bit 17 : Enable override */
59300   #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Pos (17UL) /*!< Position of ENABLE17 field.                                         */
59301   #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE17_Pos) /*!< Bit mask of ENABLE17 field.*/
59302   #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Min (0x0UL) /*!< Min enumerator value of ENABLE17 field.                            */
59303   #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Max (0x1UL) /*!< Max enumerator value of ENABLE17 field.                            */
59304   #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Disable (0x0UL) /*!< Override region n is disabled for master port 17               */
59305   #define MPC_OVERRIDE_MASTERPORT_ENABLE17_Enable (0x1UL) /*!< Override region n is enabled for master port 17                 */
59306 
59307 /* ENABLE18 @Bit 18 : Enable override */
59308   #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Pos (18UL) /*!< Position of ENABLE18 field.                                         */
59309   #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE18_Pos) /*!< Bit mask of ENABLE18 field.*/
59310   #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Min (0x0UL) /*!< Min enumerator value of ENABLE18 field.                            */
59311   #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Max (0x1UL) /*!< Max enumerator value of ENABLE18 field.                            */
59312   #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Disable (0x0UL) /*!< Override region n is disabled for master port 18               */
59313   #define MPC_OVERRIDE_MASTERPORT_ENABLE18_Enable (0x1UL) /*!< Override region n is enabled for master port 18                 */
59314 
59315 /* ENABLE19 @Bit 19 : Enable override */
59316   #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Pos (19UL) /*!< Position of ENABLE19 field.                                         */
59317   #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE19_Pos) /*!< Bit mask of ENABLE19 field.*/
59318   #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Min (0x0UL) /*!< Min enumerator value of ENABLE19 field.                            */
59319   #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Max (0x1UL) /*!< Max enumerator value of ENABLE19 field.                            */
59320   #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Disable (0x0UL) /*!< Override region n is disabled for master port 19               */
59321   #define MPC_OVERRIDE_MASTERPORT_ENABLE19_Enable (0x1UL) /*!< Override region n is enabled for master port 19                 */
59322 
59323 /* ENABLE20 @Bit 20 : Enable override */
59324   #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Pos (20UL) /*!< Position of ENABLE20 field.                                         */
59325   #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE20_Pos) /*!< Bit mask of ENABLE20 field.*/
59326   #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Min (0x0UL) /*!< Min enumerator value of ENABLE20 field.                            */
59327   #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Max (0x1UL) /*!< Max enumerator value of ENABLE20 field.                            */
59328   #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Disable (0x0UL) /*!< Override region n is disabled for master port 20               */
59329   #define MPC_OVERRIDE_MASTERPORT_ENABLE20_Enable (0x1UL) /*!< Override region n is enabled for master port 20                 */
59330 
59331 /* ENABLE21 @Bit 21 : Enable override */
59332   #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Pos (21UL) /*!< Position of ENABLE21 field.                                         */
59333   #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE21_Pos) /*!< Bit mask of ENABLE21 field.*/
59334   #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Min (0x0UL) /*!< Min enumerator value of ENABLE21 field.                            */
59335   #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Max (0x1UL) /*!< Max enumerator value of ENABLE21 field.                            */
59336   #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Disable (0x0UL) /*!< Override region n is disabled for master port 21               */
59337   #define MPC_OVERRIDE_MASTERPORT_ENABLE21_Enable (0x1UL) /*!< Override region n is enabled for master port 21                 */
59338 
59339 /* ENABLE22 @Bit 22 : Enable override */
59340   #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Pos (22UL) /*!< Position of ENABLE22 field.                                         */
59341   #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE22_Pos) /*!< Bit mask of ENABLE22 field.*/
59342   #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Min (0x0UL) /*!< Min enumerator value of ENABLE22 field.                            */
59343   #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Max (0x1UL) /*!< Max enumerator value of ENABLE22 field.                            */
59344   #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Disable (0x0UL) /*!< Override region n is disabled for master port 22               */
59345   #define MPC_OVERRIDE_MASTERPORT_ENABLE22_Enable (0x1UL) /*!< Override region n is enabled for master port 22                 */
59346 
59347 /* ENABLE23 @Bit 23 : Enable override */
59348   #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Pos (23UL) /*!< Position of ENABLE23 field.                                         */
59349   #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE23_Pos) /*!< Bit mask of ENABLE23 field.*/
59350   #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Min (0x0UL) /*!< Min enumerator value of ENABLE23 field.                            */
59351   #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Max (0x1UL) /*!< Max enumerator value of ENABLE23 field.                            */
59352   #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Disable (0x0UL) /*!< Override region n is disabled for master port 23               */
59353   #define MPC_OVERRIDE_MASTERPORT_ENABLE23_Enable (0x1UL) /*!< Override region n is enabled for master port 23                 */
59354 
59355 /* ENABLE24 @Bit 24 : Enable override */
59356   #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Pos (24UL) /*!< Position of ENABLE24 field.                                         */
59357   #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE24_Pos) /*!< Bit mask of ENABLE24 field.*/
59358   #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Min (0x0UL) /*!< Min enumerator value of ENABLE24 field.                            */
59359   #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Max (0x1UL) /*!< Max enumerator value of ENABLE24 field.                            */
59360   #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Disable (0x0UL) /*!< Override region n is disabled for master port 24               */
59361   #define MPC_OVERRIDE_MASTERPORT_ENABLE24_Enable (0x1UL) /*!< Override region n is enabled for master port 24                 */
59362 
59363 /* ENABLE25 @Bit 25 : Enable override */
59364   #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Pos (25UL) /*!< Position of ENABLE25 field.                                         */
59365   #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE25_Pos) /*!< Bit mask of ENABLE25 field.*/
59366   #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Min (0x0UL) /*!< Min enumerator value of ENABLE25 field.                            */
59367   #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Max (0x1UL) /*!< Max enumerator value of ENABLE25 field.                            */
59368   #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Disable (0x0UL) /*!< Override region n is disabled for master port 25               */
59369   #define MPC_OVERRIDE_MASTERPORT_ENABLE25_Enable (0x1UL) /*!< Override region n is enabled for master port 25                 */
59370 
59371 /* ENABLE26 @Bit 26 : Enable override */
59372   #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Pos (26UL) /*!< Position of ENABLE26 field.                                         */
59373   #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE26_Pos) /*!< Bit mask of ENABLE26 field.*/
59374   #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Min (0x0UL) /*!< Min enumerator value of ENABLE26 field.                            */
59375   #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Max (0x1UL) /*!< Max enumerator value of ENABLE26 field.                            */
59376   #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Disable (0x0UL) /*!< Override region n is disabled for master port 26               */
59377   #define MPC_OVERRIDE_MASTERPORT_ENABLE26_Enable (0x1UL) /*!< Override region n is enabled for master port 26                 */
59378 
59379 /* ENABLE27 @Bit 27 : Enable override */
59380   #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Pos (27UL) /*!< Position of ENABLE27 field.                                         */
59381   #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE27_Pos) /*!< Bit mask of ENABLE27 field.*/
59382   #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Min (0x0UL) /*!< Min enumerator value of ENABLE27 field.                            */
59383   #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Max (0x1UL) /*!< Max enumerator value of ENABLE27 field.                            */
59384   #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Disable (0x0UL) /*!< Override region n is disabled for master port 27               */
59385   #define MPC_OVERRIDE_MASTERPORT_ENABLE27_Enable (0x1UL) /*!< Override region n is enabled for master port 27                 */
59386 
59387 /* ENABLE28 @Bit 28 : Enable override */
59388   #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Pos (28UL) /*!< Position of ENABLE28 field.                                         */
59389   #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE28_Pos) /*!< Bit mask of ENABLE28 field.*/
59390   #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Min (0x0UL) /*!< Min enumerator value of ENABLE28 field.                            */
59391   #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Max (0x1UL) /*!< Max enumerator value of ENABLE28 field.                            */
59392   #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Disable (0x0UL) /*!< Override region n is disabled for master port 28               */
59393   #define MPC_OVERRIDE_MASTERPORT_ENABLE28_Enable (0x1UL) /*!< Override region n is enabled for master port 28                 */
59394 
59395 /* ENABLE29 @Bit 29 : Enable override */
59396   #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Pos (29UL) /*!< Position of ENABLE29 field.                                         */
59397   #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE29_Pos) /*!< Bit mask of ENABLE29 field.*/
59398   #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Min (0x0UL) /*!< Min enumerator value of ENABLE29 field.                            */
59399   #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Max (0x1UL) /*!< Max enumerator value of ENABLE29 field.                            */
59400   #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Disable (0x0UL) /*!< Override region n is disabled for master port 29               */
59401   #define MPC_OVERRIDE_MASTERPORT_ENABLE29_Enable (0x1UL) /*!< Override region n is enabled for master port 29                 */
59402 
59403 /* ENABLE30 @Bit 30 : Enable override */
59404   #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Pos (30UL) /*!< Position of ENABLE30 field.                                         */
59405   #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE30_Pos) /*!< Bit mask of ENABLE30 field.*/
59406   #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Min (0x0UL) /*!< Min enumerator value of ENABLE30 field.                            */
59407   #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Max (0x1UL) /*!< Max enumerator value of ENABLE30 field.                            */
59408   #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Disable (0x0UL) /*!< Override region n is disabled for master port 30               */
59409   #define MPC_OVERRIDE_MASTERPORT_ENABLE30_Enable (0x1UL) /*!< Override region n is enabled for master port 30                 */
59410 
59411 /* ENABLE31 @Bit 31 : Enable override */
59412   #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Pos (31UL) /*!< Position of ENABLE31 field.                                         */
59413   #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Msk (0x1UL << MPC_OVERRIDE_MASTERPORT_ENABLE31_Pos) /*!< Bit mask of ENABLE31 field.*/
59414   #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Min (0x0UL) /*!< Min enumerator value of ENABLE31 field.                            */
59415   #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Max (0x1UL) /*!< Max enumerator value of ENABLE31 field.                            */
59416   #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Disable (0x0UL) /*!< Override region n is disabled for master port 31               */
59417   #define MPC_OVERRIDE_MASTERPORT_ENABLE31_Enable (0x1UL) /*!< Override region n is enabled for master port 31                 */
59418 
59419 
59420 /* ======================================================= Struct MPC ======================================================== */
59421 /**
59422   * @brief Memory Privilege Controller
59423   */
59424   typedef struct {                                   /*!< MPC Structure                                                        */
59425     __IM uint32_t RESERVED[64];
59426     __IOM uint32_t EVENTS_MEMACCERR;                 /*!< (@ 0x00000100) Memory Access Error event                             */
59427     __IM uint32_t RESERVED1[127];
59428     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
59429     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
59430     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
59431     __IM uint32_t RESERVED2[61];
59432     __IOM NRF_MPC_MEMACCERR_Type MEMACCERR;          /*!< (@ 0x00000400) Memory Access Error status registers                  */
59433     __IM uint32_t RESERVED3[2];
59434     __IOM NRF_MPC_GLOBALSLAVE_Type GLOBALSLAVE;      /*!< (@ 0x00000410) Global slave master port connection information       */
59435     __IM uint32_t RESERVED4[2];
59436     __IOM NRF_MPC_RTCHOKE_Type RTCHOKE;              /*!< (@ 0x00000420) Real time choke configuration for AXI master port     */
59437     __IM uint32_t RESERVED5[64];
59438     __IOM NRF_MPC_REGION_Type REGION[32];            /*!< (@ 0x00000600) Memory region to slave decoding table                 */
59439     __IOM NRF_MPC_OVERRIDE_Type OVERRIDE[40];        /*!< (@ 0x00000800) Special privilege tables                              */
59440   } NRF_MPC_Type;                                    /*!< Size = 3328 (0xD00)                                                  */
59441 
59442 /* MPC_EVENTS_MEMACCERR: Memory Access Error event */
59443   #define MPC_EVENTS_MEMACCERR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MEMACCERR register.                        */
59444 
59445 /* EVENTS_MEMACCERR @Bit 0 : Memory Access Error event */
59446   #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Pos (0UL) /*!< Position of EVENTS_MEMACCERR field.                             */
59447   #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Msk (0x1UL << MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Pos) /*!< Bit mask of
59448                                                                             EVENTS_MEMACCERR field.*/
59449   #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Min (0x0UL) /*!< Min enumerator value of EVENTS_MEMACCERR field.               */
59450   #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Max (0x1UL) /*!< Max enumerator value of EVENTS_MEMACCERR field.               */
59451   #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_NotGenerated (0x0UL) /*!< Event not generated                                  */
59452   #define MPC_EVENTS_MEMACCERR_EVENTS_MEMACCERR_Generated (0x1UL) /*!< Event generated                                         */
59453 
59454 
59455 /* MPC_INTEN: Enable or disable interrupt */
59456   #define MPC_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
59457 
59458 /* MEMACCERR @Bit 0 : Enable or disable interrupt for event MEMACCERR */
59459   #define MPC_INTEN_MEMACCERR_Pos (0UL)              /*!< Position of MEMACCERR field.                                         */
59460   #define MPC_INTEN_MEMACCERR_Msk (0x1UL << MPC_INTEN_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field.                         */
59461   #define MPC_INTEN_MEMACCERR_Min (0x0UL)            /*!< Min enumerator value of MEMACCERR field.                             */
59462   #define MPC_INTEN_MEMACCERR_Max (0x1UL)            /*!< Max enumerator value of MEMACCERR field.                             */
59463   #define MPC_INTEN_MEMACCERR_Disabled (0x0UL)       /*!< Disable                                                              */
59464   #define MPC_INTEN_MEMACCERR_Enabled (0x1UL)        /*!< Enable                                                               */
59465 
59466 
59467 /* MPC_INTENSET: Enable interrupt */
59468   #define MPC_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
59469 
59470 /* MEMACCERR @Bit 0 : Write '1' to enable interrupt for event MEMACCERR */
59471   #define MPC_INTENSET_MEMACCERR_Pos (0UL)           /*!< Position of MEMACCERR field.                                         */
59472   #define MPC_INTENSET_MEMACCERR_Msk (0x1UL << MPC_INTENSET_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field.                   */
59473   #define MPC_INTENSET_MEMACCERR_Min (0x0UL)         /*!< Min enumerator value of MEMACCERR field.                             */
59474   #define MPC_INTENSET_MEMACCERR_Max (0x1UL)         /*!< Max enumerator value of MEMACCERR field.                             */
59475   #define MPC_INTENSET_MEMACCERR_Set (0x1UL)         /*!< Enable                                                               */
59476   #define MPC_INTENSET_MEMACCERR_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
59477   #define MPC_INTENSET_MEMACCERR_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
59478 
59479 
59480 /* MPC_INTENCLR: Disable interrupt */
59481   #define MPC_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
59482 
59483 /* MEMACCERR @Bit 0 : Write '1' to disable interrupt for event MEMACCERR */
59484   #define MPC_INTENCLR_MEMACCERR_Pos (0UL)           /*!< Position of MEMACCERR field.                                         */
59485   #define MPC_INTENCLR_MEMACCERR_Msk (0x1UL << MPC_INTENCLR_MEMACCERR_Pos) /*!< Bit mask of MEMACCERR field.                   */
59486   #define MPC_INTENCLR_MEMACCERR_Min (0x0UL)         /*!< Min enumerator value of MEMACCERR field.                             */
59487   #define MPC_INTENCLR_MEMACCERR_Max (0x1UL)         /*!< Max enumerator value of MEMACCERR field.                             */
59488   #define MPC_INTENCLR_MEMACCERR_Clear (0x1UL)       /*!< Disable                                                              */
59489   #define MPC_INTENCLR_MEMACCERR_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
59490   #define MPC_INTENCLR_MEMACCERR_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
59491 
59492 
59493 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
59494 
59495 /* =========================================================================================================================== */
59496 /* ================                                           MUTEX                                           ================ */
59497 /* =========================================================================================================================== */
59498 
59499 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
59500 /* ====================================================== Struct MUTEX ======================================================= */
59501 /**
59502   * @brief MUTEX
59503   */
59504   typedef struct {                                   /*!< MUTEX Structure                                                      */
59505     __IM uint32_t RESERVED[256];
59506     __IOM uint32_t MUTEX[32];                        /*!< (@ 0x00000400) Mutex register                                        */
59507   } NRF_MUTEX_Type;                                  /*!< Size = 1152 (0x480)                                                  */
59508 
59509 /* MUTEX_MUTEX: Mutex register */
59510   #define MUTEX_MUTEX_MaxCount (32UL)                /*!< Max size of MUTEX[32] array.                                         */
59511   #define MUTEX_MUTEX_MaxIndex (31UL)                /*!< Max index of MUTEX[32] array.                                        */
59512   #define MUTEX_MUTEX_MinIndex (0UL)                 /*!< Min index of MUTEX[32] array.                                        */
59513   #define MUTEX_MUTEX_ResetValue (0x00000000UL)      /*!< Reset value of MUTEX[32] register.                                   */
59514 
59515 /* MUTEX @Bit 0 : Mutex register n */
59516   #define MUTEX_MUTEX_MUTEX_Pos (0UL)                /*!< Position of MUTEX field.                                             */
59517   #define MUTEX_MUTEX_MUTEX_Msk (0x1UL << MUTEX_MUTEX_MUTEX_Pos) /*!< Bit mask of MUTEX field.                                 */
59518   #define MUTEX_MUTEX_MUTEX_Min (0x0UL)              /*!< Min enumerator value of MUTEX field.                                 */
59519   #define MUTEX_MUTEX_MUTEX_Max (0x1UL)              /*!< Max enumerator value of MUTEX field.                                 */
59520   #define MUTEX_MUTEX_MUTEX_Unlocked (0x0UL)         /*!< Mutex n is in unlocked state                                         */
59521   #define MUTEX_MUTEX_MUTEX_Locked (0x1UL)           /*!< Mutex n is in locked state                                           */
59522 
59523 
59524 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
59525 
59526 /* =========================================================================================================================== */
59527 /* ================                                           MVDMA                                           ================ */
59528 /* =========================================================================================================================== */
59529 
59530 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
59531 
59532 /* =================================================== Struct MVDMA_STATUS =================================================== */
59533 /**
59534   * @brief STATUS [MVDMA_STATUS] MVDMA status registers.
59535   */
59536 typedef struct {
59537   __IM  uint32_t  CRCRESULT;                         /*!< (@ 0x00000000) CRC checksum calculation result                       */
59538   __IM  uint32_t  FIFO;                              /*!< (@ 0x00000004) Status of intermediate fifo: empty, not empty and full
59539                                                                          information available.*/
59540   __IM  uint32_t  ACTIVE;                            /*!< (@ 0x00000008) Status of DMA transfer.                               */
59541   __IM  uint32_t  SOURCEBUSERROR;                    /*!< (@ 0x0000000C) Source bus error status.                              */
59542   __IM  uint32_t  SINKBUSERROR;                      /*!< (@ 0x00000010) Sink bus error status.                                */
59543   __IM  uint32_t  SOURCEADDRESS;                     /*!< (@ 0x00000014) Latest address being accessed on the Source channel.  */
59544   __IM  uint32_t  SINKADDRESS;                       /*!< (@ 0x00000018) Latest address being accessed on the Sink channel.    */
59545   __IM  uint32_t  SOURCEJOBCOUNT;                    /*!< (@ 0x0000001C) Number of completed jobs in the current Source
59546                                                                          descriptor list.*/
59547   __IM  uint32_t  SINKJOBCOUNT;                      /*!< (@ 0x00000020) Number of completed jobs in the current Sink descriptor
59548                                                                          list.*/
59549 } NRF_MVDMA_STATUS_Type;                             /*!< Size = 36 (0x024)                                                    */
59550 
59551 /* MVDMA_STATUS_CRCRESULT: CRC checksum calculation result */
59552   #define MVDMA_STATUS_CRCRESULT_ResetValue (0x00000000UL) /*!< Reset value of CRCRESULT register.                             */
59553 
59554 /* CRC @Bits 0..31 : Result */
59555   #define MVDMA_STATUS_CRCRESULT_CRC_Pos (0UL)       /*!< Position of CRC field.                                               */
59556   #define MVDMA_STATUS_CRCRESULT_CRC_Msk (0xFFFFFFFFUL << MVDMA_STATUS_CRCRESULT_CRC_Pos) /*!< Bit mask of CRC field.          */
59557 
59558 
59559 /* MVDMA_STATUS_FIFO: Status of intermediate fifo: empty, not empty and full information available. */
59560   #define MVDMA_STATUS_FIFO_ResetValue (0x00000000UL) /*!< Reset value of FIFO register.                                       */
59561 
59562 /* FIFOSTATUS @Bits 0..1 : Result */
59563   #define MVDMA_STATUS_FIFO_FIFOSTATUS_Pos (0UL)     /*!< Position of FIFOSTATUS field.                                        */
59564   #define MVDMA_STATUS_FIFO_FIFOSTATUS_Msk (0x3UL << MVDMA_STATUS_FIFO_FIFOSTATUS_Pos) /*!< Bit mask of FIFOSTATUS field.      */
59565   #define MVDMA_STATUS_FIFO_FIFOSTATUS_Min (0x0UL)   /*!< Min enumerator value of FIFOSTATUS field.                            */
59566   #define MVDMA_STATUS_FIFO_FIFOSTATUS_Max (0x3UL)   /*!< Max enumerator value of FIFOSTATUS field.                            */
59567   #define MVDMA_STATUS_FIFO_FIFOSTATUS_Empty (0x0UL) /*!< Fifo is empty.                                                       */
59568   #define MVDMA_STATUS_FIFO_FIFOSTATUS_AlmostFull (0x2UL) /*!< Fifo contains data.                                             */
59569   #define MVDMA_STATUS_FIFO_FIFOSTATUS_Full (0x3UL)  /*!< Fifo is full.                                                        */
59570 
59571 
59572 /* MVDMA_STATUS_ACTIVE: Status of DMA transfer. */
59573   #define MVDMA_STATUS_ACTIVE_ResetValue (0x00000000UL) /*!< Reset value of ACTIVE register.                                   */
59574 
59575 /* ACTIVE @Bit 0 : DMA activity */
59576   #define MVDMA_STATUS_ACTIVE_ACTIVE_Pos (0UL)       /*!< Position of ACTIVE field.                                            */
59577   #define MVDMA_STATUS_ACTIVE_ACTIVE_Msk (0x1UL << MVDMA_STATUS_ACTIVE_ACTIVE_Pos) /*!< Bit mask of ACTIVE field.              */
59578   #define MVDMA_STATUS_ACTIVE_ACTIVE_Min (0x0UL)     /*!< Min enumerator value of ACTIVE field.                                */
59579   #define MVDMA_STATUS_ACTIVE_ACTIVE_Max (0x1UL)     /*!< Max enumerator value of ACTIVE field.                                */
59580   #define MVDMA_STATUS_ACTIVE_ACTIVE_Idle (0x0UL)    /*!< DMA is in IDLE state.                                                */
59581   #define MVDMA_STATUS_ACTIVE_ACTIVE_Active (0x1UL)  /*!< Data being transferred.                                              */
59582 
59583 
59584 /* MVDMA_STATUS_SOURCEBUSERROR: Source bus error status. */
59585   #define MVDMA_STATUS_SOURCEBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of SOURCEBUSERROR register.                   */
59586 
59587 /* BUSERROR @Bits 0..2 : Bus error type */
59588   #define MVDMA_STATUS_SOURCEBUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                      */
59589   #define MVDMA_STATUS_SOURCEBUSERROR_BUSERROR_Msk (0x7UL << MVDMA_STATUS_SOURCEBUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
59590                                                                             field.*/
59591   #define MVDMA_STATUS_SOURCEBUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                        */
59592   #define MVDMA_STATUS_SOURCEBUSERROR_BUSERROR_Max (0x2UL) /*!< Max enumerator value of BUSERROR field.                        */
59593   #define MVDMA_STATUS_SOURCEBUSERROR_BUSERROR_NoError (0x0UL) /*!< There are no errors.                                       */
59594   #define MVDMA_STATUS_SOURCEBUSERROR_BUSERROR_SlaveError (0x1UL) /*!< Error generated by slave.                               */
59595   #define MVDMA_STATUS_SOURCEBUSERROR_BUSERROR_DecodeError (0x2UL) /*!< Error generated by interconnect.                       */
59596 
59597 
59598 /* MVDMA_STATUS_SINKBUSERROR: Sink bus error status. */
59599   #define MVDMA_STATUS_SINKBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of SINKBUSERROR register.                       */
59600 
59601 /* BUSERROR @Bits 0..2 : Bus error type */
59602   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_Pos (0UL) /*!< Position of BUSERROR field.                                        */
59603   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_Msk (0x7UL << MVDMA_STATUS_SINKBUSERROR_BUSERROR_Pos) /*!< Bit mask of BUSERROR
59604                                                                             field.*/
59605   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_Min (0x0UL) /*!< Min enumerator value of BUSERROR field.                          */
59606   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_Max (0x4UL) /*!< Max enumerator value of BUSERROR field.                          */
59607   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_NoError (0x0UL) /*!< There are no errors.                                         */
59608   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_ReadSlaveError (0x1UL) /*!< Read error generated by slave.                        */
59609   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_ReadDecodeError (0x2UL) /*!< Read error generated by interconnect.                */
59610   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_WriteSlaveError (0x3UL) /*!< Write error generated by slave.                      */
59611   #define MVDMA_STATUS_SINKBUSERROR_BUSERROR_WriteDecodeError (0x4UL) /*!< Write error generated by interconnect.              */
59612 
59613 
59614 /* MVDMA_STATUS_SOURCEADDRESS: Latest address being accessed on the Source channel. */
59615   #define MVDMA_STATUS_SOURCEADDRESS_ResetValue (0x00000000UL) /*!< Reset value of SOURCEADDRESS register.                     */
59616 
59617 /* ADDRESS @Bits 0..31 : Source address */
59618   #define MVDMA_STATUS_SOURCEADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                         */
59619   #define MVDMA_STATUS_SOURCEADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << MVDMA_STATUS_SOURCEADDRESS_ADDRESS_Pos) /*!< Bit mask of
59620                                                                             ADDRESS field.*/
59621 
59622 
59623 /* MVDMA_STATUS_SINKADDRESS: Latest address being accessed on the Sink channel. */
59624   #define MVDMA_STATUS_SINKADDRESS_ResetValue (0x00000000UL) /*!< Reset value of SINKADDRESS register.                         */
59625 
59626 /* ADDRESS @Bits 0..31 : Sink address */
59627   #define MVDMA_STATUS_SINKADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                           */
59628   #define MVDMA_STATUS_SINKADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << MVDMA_STATUS_SINKADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS
59629                                                                             field.*/
59630 
59631 
59632 /* MVDMA_STATUS_SOURCEJOBCOUNT: Number of completed jobs in the current Source descriptor list. */
59633   #define MVDMA_STATUS_SOURCEJOBCOUNT_ResetValue (0x00000000UL) /*!< Reset value of SOURCEJOBCOUNT register.                   */
59634 
59635 /* COUNT @Bits 0..31 : Source job count */
59636   #define MVDMA_STATUS_SOURCEJOBCOUNT_COUNT_Pos (0UL) /*!< Position of COUNT field.                                            */
59637   #define MVDMA_STATUS_SOURCEJOBCOUNT_COUNT_Msk (0xFFFFFFFFUL << MVDMA_STATUS_SOURCEJOBCOUNT_COUNT_Pos) /*!< Bit mask of COUNT
59638                                                                             field.*/
59639 
59640 
59641 /* MVDMA_STATUS_SINKJOBCOUNT: Number of completed jobs in the current Sink descriptor list. */
59642   #define MVDMA_STATUS_SINKJOBCOUNT_ResetValue (0x00000000UL) /*!< Reset value of SINKJOBCOUNT register.                       */
59643 
59644 /* COUNT @Bits 0..31 : Sink job count */
59645   #define MVDMA_STATUS_SINKJOBCOUNT_COUNT_Pos (0UL)  /*!< Position of COUNT field.                                             */
59646   #define MVDMA_STATUS_SINKJOBCOUNT_COUNT_Msk (0xFFFFFFFFUL << MVDMA_STATUS_SINKJOBCOUNT_COUNT_Pos) /*!< Bit mask of COUNT
59647                                                                             field.*/
59648 
59649 
59650 
59651 /* =================================================== Struct MVDMA_CONFIG =================================================== */
59652 /**
59653   * @brief CONFIG [MVDMA_CONFIG] MVDMA configuration registers.
59654   */
59655 typedef struct {
59656   __IOM uint32_t  MODE;                              /*!< (@ 0x00000000) Mode that defines where the job list pointers are
59657                                                                          located.*/
59658   __IOM uint32_t  SOURCELISTPTR;                     /*!< (@ 0x00000004) Start address of Source job list or list of job list
59659                                                                          pointers, depending on value of CONFIG.MODE.*/
59660   __IOM uint32_t  SINKLISTPTR;                       /*!< (@ 0x00000008) Start address of Sink job list or list of job list
59661                                                                          pointers, depending on value of CONFIG.MODE.*/
59662   __IM  uint32_t  RESERVED;
59663 } NRF_MVDMA_CONFIG_Type;                             /*!< Size = 16 (0x010)                                                    */
59664 
59665 /* MVDMA_CONFIG_MODE: Mode that defines where the job list pointers are located. */
59666   #define MVDMA_CONFIG_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register.                                       */
59667 
59668 /* MODE @Bit 0 : (unspecified) */
59669   #define MVDMA_CONFIG_MODE_MODE_Pos (0UL)           /*!< Position of MODE field.                                              */
59670   #define MVDMA_CONFIG_MODE_MODE_Msk (0x1UL << MVDMA_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field.                        */
59671   #define MVDMA_CONFIG_MODE_MODE_Min (0x0UL)         /*!< Min enumerator value of MODE field.                                  */
59672   #define MVDMA_CONFIG_MODE_MODE_Max (0x1UL)         /*!< Max enumerator value of MODE field.                                  */
59673   #define MVDMA_CONFIG_MODE_MODE_SingleMode (0x0UL)  /*!< Registers CONFIG.SOURCELISTPTR and CONFIG.SINKLISTPTR contain start
59674                                                           address of a single job list.*/
59675   #define MVDMA_CONFIG_MODE_MODE_MultiMode (0x1UL)   /*!< Registers CONFIG.SOURCELISTPTR and CONFIG.SINKLISTPTR contain start
59676                                                           address of a list of job list pointers in memory.*/
59677 
59678 
59679 /* MVDMA_CONFIG_SOURCELISTPTR: Start address of Source job list or list of job list pointers, depending on value of CONFIG.MODE.
59680                                 */
59681 
59682   #define MVDMA_CONFIG_SOURCELISTPTR_ResetValue (0x00000000UL) /*!< Reset value of SOURCELISTPTR register.                     */
59683 
59684 /* ADDRESS @Bits 0..31 : Source job descriptor list address. */
59685   #define MVDMA_CONFIG_SOURCELISTPTR_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                         */
59686   #define MVDMA_CONFIG_SOURCELISTPTR_ADDRESS_Msk (0xFFFFFFFFUL << MVDMA_CONFIG_SOURCELISTPTR_ADDRESS_Pos) /*!< Bit mask of
59687                                                                             ADDRESS field.*/
59688 
59689 
59690 /* MVDMA_CONFIG_SINKLISTPTR: Start address of Sink job list or list of job list pointers, depending on value of CONFIG.MODE. */
59691   #define MVDMA_CONFIG_SINKLISTPTR_ResetValue (0x00000000UL) /*!< Reset value of SINKLISTPTR register.                         */
59692 
59693 /* ADDRESS @Bits 0..31 : Sink descriptor list address. */
59694   #define MVDMA_CONFIG_SINKLISTPTR_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                           */
59695   #define MVDMA_CONFIG_SINKLISTPTR_ADDRESS_Msk (0xFFFFFFFFUL << MVDMA_CONFIG_SINKLISTPTR_ADDRESS_Pos) /*!< Bit mask of ADDRESS
59696                                                                             field.*/
59697 
59698 
59699 /* ====================================================== Struct MVDMA ======================================================= */
59700 /**
59701   * @brief MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each
59702             transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and
59703             they contain data buffer information, address pointers, buffer sizes and data type attributes.
59704 
59705   */
59706   typedef struct {                                   /*!< MVDMA Structure                                                      */
59707     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000000) Stop operation.                                       */
59708     __OM uint32_t TASKS_RESET;                       /*!< (@ 0x00000004) Reset operation.                                      */
59709     __OM uint32_t TASKS_START[8];                    /*!< (@ 0x00000008) Start operation.                                      */
59710     __IM uint32_t RESERVED[22];
59711     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000080) Subscribe configuration for task STOP                 */
59712     __IOM uint32_t SUBSCRIBE_RESET;                  /*!< (@ 0x00000084) Subscribe configuration for task RESET                */
59713     __IOM uint32_t SUBSCRIBE_START[8];               /*!< (@ 0x00000088) Subscribe configuration for task START[n]             */
59714     __IM uint32_t RESERVED1[22];
59715     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000100) Event indicating that Sink data descriptor list has
59716                                                                          been completed.*/
59717     __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000104) Event indicating that the data transfer has started.  */
59718     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000108) Event indicating that the data transfer has been
59719                                                                          stopped.*/
59720     __IOM uint32_t EVENTS_RESET;                     /*!< (@ 0x0000010C) Event indicating that the peripheral has been reset.  */
59721     __IOM uint32_t EVENTS_SOURCEBUSERROR;            /*!< (@ 0x00000110) Event indicating that a bus error has been received on
59722                                                                          the Source channel.*/
59723     __IOM uint32_t EVENTS_SINKBUSERROR;              /*!< (@ 0x00000114) Event indicating that a bus error has been received on
59724                                                                          the Sink channel.*/
59725     __IOM uint32_t EVENTS_SOURCESELECTJOBDONE;       /*!< (@ 0x00000118) Event indicating that a job on the Source channel with
59726                                                                          interrupt enable attribute bit active has been
59727                                                                          processed.*/
59728     __IOM uint32_t EVENTS_SINKSELECTJOBDONE;         /*!< (@ 0x0000011C) Event indicating that a job on the Sink channel with
59729                                                                          interrupt enable attribute bit active has been
59730                                                                          processed.*/
59731     __IM uint32_t RESERVED2[24];
59732     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000180) Publish configuration for event END                   */
59733     __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x00000184) Publish configuration for event STARTED               */
59734     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000188) Publish configuration for event STOPPED               */
59735     __IOM uint32_t PUBLISH_RESET;                    /*!< (@ 0x0000018C) Publish configuration for event RESET                 */
59736     __IOM uint32_t PUBLISH_SOURCEBUSERROR;           /*!< (@ 0x00000190) Publish configuration for event SOURCEBUSERROR        */
59737     __IOM uint32_t PUBLISH_SINKBUSERROR;             /*!< (@ 0x00000194) Publish configuration for event SINKBUSERROR          */
59738     __IOM uint32_t PUBLISH_SOURCESELECTJOBDONE;      /*!< (@ 0x00000198) Publish configuration for event SOURCESELECTJOBDONE   */
59739     __IOM uint32_t PUBLISH_SINKSELECTJOBDONE;        /*!< (@ 0x0000019C) Publish configuration for event SINKSELECTJOBDONE     */
59740     __IM uint32_t RESERVED3[88];
59741     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
59742     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
59743     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
59744     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
59745     __IM uint32_t RESERVED4[60];
59746     __IOM NRF_MVDMA_STATUS_Type STATUS;              /*!< (@ 0x00000400) MVDMA status registers.                               */
59747     __IM uint32_t RESERVED5[56];
59748     __IOM NRF_MVDMA_CONFIG_Type CONFIG;              /*!< (@ 0x00000504) MVDMA configuration registers.                        */
59749   } NRF_MVDMA_Type;                                  /*!< Size = 1300 (0x514)                                                  */
59750 
59751 /* MVDMA_TASKS_STOP: Stop operation. */
59752   #define MVDMA_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */
59753 
59754 /* TASKS_STOP @Bit 0 : Stop operation. */
59755   #define MVDMA_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
59756   #define MVDMA_TASKS_STOP_TASKS_STOP_Msk (0x1UL << MVDMA_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
59757   #define MVDMA_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
59758   #define MVDMA_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
59759   #define MVDMA_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */
59760 
59761 
59762 /* MVDMA_TASKS_RESET: Reset operation. */
59763   #define MVDMA_TASKS_RESET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESET register.                                */
59764 
59765 /* TASKS_RESET @Bit 0 : Reset operation. */
59766   #define MVDMA_TASKS_RESET_TASKS_RESET_Pos (0UL)    /*!< Position of TASKS_RESET field.                                       */
59767   #define MVDMA_TASKS_RESET_TASKS_RESET_Msk (0x1UL << MVDMA_TASKS_RESET_TASKS_RESET_Pos) /*!< Bit mask of TASKS_RESET field.   */
59768   #define MVDMA_TASKS_RESET_TASKS_RESET_Min (0x1UL)  /*!< Min enumerator value of TASKS_RESET field.                           */
59769   #define MVDMA_TASKS_RESET_TASKS_RESET_Max (0x1UL)  /*!< Max enumerator value of TASKS_RESET field.                           */
59770   #define MVDMA_TASKS_RESET_TASKS_RESET_Trigger (0x1UL) /*!< Trigger task                                                      */
59771 
59772 
59773 /* MVDMA_TASKS_START: Start operation. */
59774   #define MVDMA_TASKS_START_MaxCount (8UL)           /*!< Max size of TASKS_START[8] array.                                    */
59775   #define MVDMA_TASKS_START_MaxIndex (7UL)           /*!< Max index of TASKS_START[8] array.                                   */
59776   #define MVDMA_TASKS_START_MinIndex (0UL)           /*!< Min index of TASKS_START[8] array.                                   */
59777   #define MVDMA_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START[8] register.                             */
59778 
59779 /* TASKS_START @Bit 0 : Start operation. */
59780   #define MVDMA_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
59781   #define MVDMA_TASKS_START_TASKS_START_Msk (0x1UL << MVDMA_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
59782   #define MVDMA_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
59783   #define MVDMA_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
59784   #define MVDMA_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */
59785 
59786 
59787 /* MVDMA_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
59788   #define MVDMA_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                          */
59789 
59790 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
59791   #define MVDMA_SUBSCRIBE_STOP_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
59792   #define MVDMA_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << MVDMA_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
59793   #define MVDMA_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
59794   #define MVDMA_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
59795 
59796 /* EN @Bit 31 : (unspecified) */
59797   #define MVDMA_SUBSCRIBE_STOP_EN_Pos (31UL)         /*!< Position of EN field.                                                */
59798   #define MVDMA_SUBSCRIBE_STOP_EN_Msk (0x1UL << MVDMA_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                        */
59799   #define MVDMA_SUBSCRIBE_STOP_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
59800   #define MVDMA_SUBSCRIBE_STOP_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
59801   #define MVDMA_SUBSCRIBE_STOP_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
59802   #define MVDMA_SUBSCRIBE_STOP_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
59803 
59804 
59805 /* MVDMA_SUBSCRIBE_RESET: Subscribe configuration for task RESET */
59806   #define MVDMA_SUBSCRIBE_RESET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESET register.                        */
59807 
59808 /* CHIDX @Bits 0..7 : DPPI channel that task RESET will subscribe to */
59809   #define MVDMA_SUBSCRIBE_RESET_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
59810   #define MVDMA_SUBSCRIBE_RESET_CHIDX_Msk (0xFFUL << MVDMA_SUBSCRIBE_RESET_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
59811   #define MVDMA_SUBSCRIBE_RESET_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
59812   #define MVDMA_SUBSCRIBE_RESET_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
59813 
59814 /* EN @Bit 31 : (unspecified) */
59815   #define MVDMA_SUBSCRIBE_RESET_EN_Pos (31UL)        /*!< Position of EN field.                                                */
59816   #define MVDMA_SUBSCRIBE_RESET_EN_Msk (0x1UL << MVDMA_SUBSCRIBE_RESET_EN_Pos) /*!< Bit mask of EN field.                      */
59817   #define MVDMA_SUBSCRIBE_RESET_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
59818   #define MVDMA_SUBSCRIBE_RESET_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
59819   #define MVDMA_SUBSCRIBE_RESET_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
59820   #define MVDMA_SUBSCRIBE_RESET_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
59821 
59822 
59823 /* MVDMA_SUBSCRIBE_START: Subscribe configuration for task START[n] */
59824   #define MVDMA_SUBSCRIBE_START_MaxCount (8UL)       /*!< Max size of SUBSCRIBE_START[8] array.                                */
59825   #define MVDMA_SUBSCRIBE_START_MaxIndex (7UL)       /*!< Max index of SUBSCRIBE_START[8] array.                               */
59826   #define MVDMA_SUBSCRIBE_START_MinIndex (0UL)       /*!< Min index of SUBSCRIBE_START[8] array.                               */
59827   #define MVDMA_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START[8] register.                     */
59828 
59829 /* CHIDX @Bits 0..7 : DPPI channel that task START[n] will subscribe to */
59830   #define MVDMA_SUBSCRIBE_START_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
59831   #define MVDMA_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << MVDMA_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
59832   #define MVDMA_SUBSCRIBE_START_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
59833   #define MVDMA_SUBSCRIBE_START_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
59834 
59835 /* EN @Bit 31 : (unspecified) */
59836   #define MVDMA_SUBSCRIBE_START_EN_Pos (31UL)        /*!< Position of EN field.                                                */
59837   #define MVDMA_SUBSCRIBE_START_EN_Msk (0x1UL << MVDMA_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                      */
59838   #define MVDMA_SUBSCRIBE_START_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
59839   #define MVDMA_SUBSCRIBE_START_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
59840   #define MVDMA_SUBSCRIBE_START_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
59841   #define MVDMA_SUBSCRIBE_START_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
59842 
59843 
59844 /* MVDMA_EVENTS_END: Event indicating that Sink data descriptor list has been completed. */
59845   #define MVDMA_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register.                                  */
59846 
59847 /* EVENTS_END @Bit 0 : Event indicating that Sink data descriptor list has been completed. */
59848   #define MVDMA_EVENTS_END_EVENTS_END_Pos (0UL)      /*!< Position of EVENTS_END field.                                        */
59849   #define MVDMA_EVENTS_END_EVENTS_END_Msk (0x1UL << MVDMA_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.        */
59850   #define MVDMA_EVENTS_END_EVENTS_END_Min (0x0UL)    /*!< Min enumerator value of EVENTS_END field.                            */
59851   #define MVDMA_EVENTS_END_EVENTS_END_Max (0x1UL)    /*!< Max enumerator value of EVENTS_END field.                            */
59852   #define MVDMA_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                            */
59853   #define MVDMA_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                   */
59854 
59855 
59856 /* MVDMA_EVENTS_STARTED: Event indicating that the data transfer has started. */
59857   #define MVDMA_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                          */
59858 
59859 /* EVENTS_STARTED @Bit 0 : Event indicating that the data transfer has started. */
59860   #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                 */
59861   #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << MVDMA_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of
59862                                                                             EVENTS_STARTED field.*/
59863   #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                   */
59864   #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                   */
59865   #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                    */
59866   #define MVDMA_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                           */
59867 
59868 
59869 /* MVDMA_EVENTS_STOPPED: Event indicating that the data transfer has been stopped. */
59870   #define MVDMA_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                          */
59871 
59872 /* EVENTS_STOPPED @Bit 0 : Event indicating that the data transfer has been stopped. */
59873   #define MVDMA_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                 */
59874   #define MVDMA_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << MVDMA_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
59875                                                                             EVENTS_STOPPED field.*/
59876   #define MVDMA_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                   */
59877   #define MVDMA_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                   */
59878   #define MVDMA_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                    */
59879   #define MVDMA_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                           */
59880 
59881 
59882 /* MVDMA_EVENTS_RESET: Event indicating that the peripheral has been reset. */
59883   #define MVDMA_EVENTS_RESET_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESET register.                              */
59884 
59885 /* EVENTS_RESET @Bit 0 : Event indicating that the peripheral has been reset. */
59886   #define MVDMA_EVENTS_RESET_EVENTS_RESET_Pos (0UL)  /*!< Position of EVENTS_RESET field.                                      */
59887   #define MVDMA_EVENTS_RESET_EVENTS_RESET_Msk (0x1UL << MVDMA_EVENTS_RESET_EVENTS_RESET_Pos) /*!< Bit mask of EVENTS_RESET
59888                                                                             field.*/
59889   #define MVDMA_EVENTS_RESET_EVENTS_RESET_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESET field.                         */
59890   #define MVDMA_EVENTS_RESET_EVENTS_RESET_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESET field.                         */
59891   #define MVDMA_EVENTS_RESET_EVENTS_RESET_NotGenerated (0x0UL) /*!< Event not generated                                        */
59892   #define MVDMA_EVENTS_RESET_EVENTS_RESET_Generated (0x1UL) /*!< Event generated                                               */
59893 
59894 
59895 /* MVDMA_EVENTS_SOURCEBUSERROR: Event indicating that a bus error has been received on the Source channel. */
59896   #define MVDMA_EVENTS_SOURCEBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SOURCEBUSERROR register.            */
59897 
59898 /* EVENTS_SOURCEBUSERROR @Bit 0 : Event indicating that a bus error has been received on the Source channel. */
59899   #define MVDMA_EVENTS_SOURCEBUSERROR_EVENTS_SOURCEBUSERROR_Pos (0UL) /*!< Position of EVENTS_SOURCEBUSERROR field.            */
59900   #define MVDMA_EVENTS_SOURCEBUSERROR_EVENTS_SOURCEBUSERROR_Msk (0x1UL << MVDMA_EVENTS_SOURCEBUSERROR_EVENTS_SOURCEBUSERROR_Pos)
59901                                                                             /*!< Bit mask of EVENTS_SOURCEBUSERROR field.*/
59902   #define MVDMA_EVENTS_SOURCEBUSERROR_EVENTS_SOURCEBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_SOURCEBUSERROR
59903                                                                             field.*/
59904   #define MVDMA_EVENTS_SOURCEBUSERROR_EVENTS_SOURCEBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_SOURCEBUSERROR
59905                                                                             field.*/
59906   #define MVDMA_EVENTS_SOURCEBUSERROR_EVENTS_SOURCEBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                      */
59907   #define MVDMA_EVENTS_SOURCEBUSERROR_EVENTS_SOURCEBUSERROR_Generated (0x1UL) /*!< Event generated                             */
59908 
59909 
59910 /* MVDMA_EVENTS_SINKBUSERROR: Event indicating that a bus error has been received on the Sink channel. */
59911   #define MVDMA_EVENTS_SINKBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SINKBUSERROR register.                */
59912 
59913 /* EVENTS_SINKBUSERROR @Bit 0 : Event indicating that a bus error has been received on the Sink channel. */
59914   #define MVDMA_EVENTS_SINKBUSERROR_EVENTS_SINKBUSERROR_Pos (0UL) /*!< Position of EVENTS_SINKBUSERROR field.                  */
59915   #define MVDMA_EVENTS_SINKBUSERROR_EVENTS_SINKBUSERROR_Msk (0x1UL << MVDMA_EVENTS_SINKBUSERROR_EVENTS_SINKBUSERROR_Pos) /*!<
59916                                                                             Bit mask of EVENTS_SINKBUSERROR field.*/
59917   #define MVDMA_EVENTS_SINKBUSERROR_EVENTS_SINKBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_SINKBUSERROR field.    */
59918   #define MVDMA_EVENTS_SINKBUSERROR_EVENTS_SINKBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_SINKBUSERROR field.    */
59919   #define MVDMA_EVENTS_SINKBUSERROR_EVENTS_SINKBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                          */
59920   #define MVDMA_EVENTS_SINKBUSERROR_EVENTS_SINKBUSERROR_Generated (0x1UL) /*!< Event generated                                 */
59921 
59922 
59923 /* MVDMA_EVENTS_SOURCESELECTJOBDONE: Event indicating that a job on the Source channel with interrupt enable attribute bit
59924                                       active has been processed. */
59925 
59926   #define MVDMA_EVENTS_SOURCESELECTJOBDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SOURCESELECTJOBDONE register.  */
59927 
59928 /* EVENTS_SOURCESELECTJOBDONE @Bit 0 : Event indicating that a job on the Source channel with interrupt enable attribute bit
59929                                        active has been processed. */
59930 
59931   #define MVDMA_EVENTS_SOURCESELECTJOBDONE_EVENTS_SOURCESELECTJOBDONE_Pos (0UL) /*!< Position of EVENTS_SOURCESELECTJOBDONE
59932                                                                             field.*/
59933   #define MVDMA_EVENTS_SOURCESELECTJOBDONE_EVENTS_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_EVENTS_SOURCESELECTJOBDONE_EVENTS_SOURCESELECTJOBDONE_Pos)
59934                                                                             /*!< Bit mask of EVENTS_SOURCESELECTJOBDONE field.*/
59935   #define MVDMA_EVENTS_SOURCESELECTJOBDONE_EVENTS_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of
59936                                                                             EVENTS_SOURCESELECTJOBDONE field.*/
59937   #define MVDMA_EVENTS_SOURCESELECTJOBDONE_EVENTS_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of
59938                                                                             EVENTS_SOURCESELECTJOBDONE field.*/
59939   #define MVDMA_EVENTS_SOURCESELECTJOBDONE_EVENTS_SOURCESELECTJOBDONE_NotGenerated (0x0UL) /*!< Event not generated            */
59940   #define MVDMA_EVENTS_SOURCESELECTJOBDONE_EVENTS_SOURCESELECTJOBDONE_Generated (0x1UL) /*!< Event generated                   */
59941 
59942 
59943 /* MVDMA_EVENTS_SINKSELECTJOBDONE: Event indicating that a job on the Sink channel with interrupt enable attribute bit active
59944                                     has been processed. */
59945 
59946   #define MVDMA_EVENTS_SINKSELECTJOBDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SINKSELECTJOBDONE register.      */
59947 
59948 /* EVENTS_SINKSELECTJOBDONE @Bit 0 : Event indicating that a job on the Sink channel with interrupt enable attribute bit active
59949                                      has been processed. */
59950 
59951   #define MVDMA_EVENTS_SINKSELECTJOBDONE_EVENTS_SINKSELECTJOBDONE_Pos (0UL) /*!< Position of EVENTS_SINKSELECTJOBDONE field.   */
59952   #define MVDMA_EVENTS_SINKSELECTJOBDONE_EVENTS_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_EVENTS_SINKSELECTJOBDONE_EVENTS_SINKSELECTJOBDONE_Pos)
59953                                                                             /*!< Bit mask of EVENTS_SINKSELECTJOBDONE field.*/
59954   #define MVDMA_EVENTS_SINKSELECTJOBDONE_EVENTS_SINKSELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of
59955                                                                             EVENTS_SINKSELECTJOBDONE field.*/
59956   #define MVDMA_EVENTS_SINKSELECTJOBDONE_EVENTS_SINKSELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of
59957                                                                             EVENTS_SINKSELECTJOBDONE field.*/
59958   #define MVDMA_EVENTS_SINKSELECTJOBDONE_EVENTS_SINKSELECTJOBDONE_NotGenerated (0x0UL) /*!< Event not generated                */
59959   #define MVDMA_EVENTS_SINKSELECTJOBDONE_EVENTS_SINKSELECTJOBDONE_Generated (0x1UL) /*!< Event generated                       */
59960 
59961 
59962 /* MVDMA_PUBLISH_END: Publish configuration for event END */
59963   #define MVDMA_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                */
59964 
59965 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
59966   #define MVDMA_PUBLISH_END_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
59967   #define MVDMA_PUBLISH_END_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
59968   #define MVDMA_PUBLISH_END_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
59969   #define MVDMA_PUBLISH_END_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
59970 
59971 /* EN @Bit 31 : (unspecified) */
59972   #define MVDMA_PUBLISH_END_EN_Pos (31UL)            /*!< Position of EN field.                                                */
59973   #define MVDMA_PUBLISH_END_EN_Msk (0x1UL << MVDMA_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                              */
59974   #define MVDMA_PUBLISH_END_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
59975   #define MVDMA_PUBLISH_END_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
59976   #define MVDMA_PUBLISH_END_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
59977   #define MVDMA_PUBLISH_END_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
59978 
59979 
59980 /* MVDMA_PUBLISH_STARTED: Publish configuration for event STARTED */
59981   #define MVDMA_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                        */
59982 
59983 /* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
59984   #define MVDMA_PUBLISH_STARTED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
59985   #define MVDMA_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
59986   #define MVDMA_PUBLISH_STARTED_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
59987   #define MVDMA_PUBLISH_STARTED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
59988 
59989 /* EN @Bit 31 : (unspecified) */
59990   #define MVDMA_PUBLISH_STARTED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
59991   #define MVDMA_PUBLISH_STARTED_EN_Msk (0x1UL << MVDMA_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                      */
59992   #define MVDMA_PUBLISH_STARTED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
59993   #define MVDMA_PUBLISH_STARTED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
59994   #define MVDMA_PUBLISH_STARTED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
59995   #define MVDMA_PUBLISH_STARTED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
59996 
59997 
59998 /* MVDMA_PUBLISH_STOPPED: Publish configuration for event STOPPED */
59999   #define MVDMA_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                        */
60000 
60001 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
60002   #define MVDMA_PUBLISH_STOPPED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
60003   #define MVDMA_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
60004   #define MVDMA_PUBLISH_STOPPED_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
60005   #define MVDMA_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
60006 
60007 /* EN @Bit 31 : (unspecified) */
60008   #define MVDMA_PUBLISH_STOPPED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
60009   #define MVDMA_PUBLISH_STOPPED_EN_Msk (0x1UL << MVDMA_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                      */
60010   #define MVDMA_PUBLISH_STOPPED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
60011   #define MVDMA_PUBLISH_STOPPED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
60012   #define MVDMA_PUBLISH_STOPPED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
60013   #define MVDMA_PUBLISH_STOPPED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
60014 
60015 
60016 /* MVDMA_PUBLISH_RESET: Publish configuration for event RESET */
60017   #define MVDMA_PUBLISH_RESET_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESET register.                            */
60018 
60019 /* CHIDX @Bits 0..7 : DPPI channel that event RESET will publish to */
60020   #define MVDMA_PUBLISH_RESET_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
60021   #define MVDMA_PUBLISH_RESET_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_RESET_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
60022   #define MVDMA_PUBLISH_RESET_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
60023   #define MVDMA_PUBLISH_RESET_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
60024 
60025 /* EN @Bit 31 : (unspecified) */
60026   #define MVDMA_PUBLISH_RESET_EN_Pos (31UL)          /*!< Position of EN field.                                                */
60027   #define MVDMA_PUBLISH_RESET_EN_Msk (0x1UL << MVDMA_PUBLISH_RESET_EN_Pos) /*!< Bit mask of EN field.                          */
60028   #define MVDMA_PUBLISH_RESET_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
60029   #define MVDMA_PUBLISH_RESET_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
60030   #define MVDMA_PUBLISH_RESET_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
60031   #define MVDMA_PUBLISH_RESET_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
60032 
60033 
60034 /* MVDMA_PUBLISH_SOURCEBUSERROR: Publish configuration for event SOURCEBUSERROR */
60035   #define MVDMA_PUBLISH_SOURCEBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SOURCEBUSERROR register.          */
60036 
60037 /* CHIDX @Bits 0..7 : DPPI channel that event SOURCEBUSERROR will publish to */
60038   #define MVDMA_PUBLISH_SOURCEBUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                           */
60039   #define MVDMA_PUBLISH_SOURCEBUSERROR_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_SOURCEBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX
60040                                                                             field.*/
60041   #define MVDMA_PUBLISH_SOURCEBUSERROR_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                        */
60042   #define MVDMA_PUBLISH_SOURCEBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                        */
60043 
60044 /* EN @Bit 31 : (unspecified) */
60045   #define MVDMA_PUBLISH_SOURCEBUSERROR_EN_Pos (31UL) /*!< Position of EN field.                                                */
60046   #define MVDMA_PUBLISH_SOURCEBUSERROR_EN_Msk (0x1UL << MVDMA_PUBLISH_SOURCEBUSERROR_EN_Pos) /*!< Bit mask of EN field.        */
60047   #define MVDMA_PUBLISH_SOURCEBUSERROR_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                   */
60048   #define MVDMA_PUBLISH_SOURCEBUSERROR_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                   */
60049   #define MVDMA_PUBLISH_SOURCEBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                             */
60050   #define MVDMA_PUBLISH_SOURCEBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                               */
60051 
60052 
60053 /* MVDMA_PUBLISH_SINKBUSERROR: Publish configuration for event SINKBUSERROR */
60054   #define MVDMA_PUBLISH_SINKBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SINKBUSERROR register.              */
60055 
60056 /* CHIDX @Bits 0..7 : DPPI channel that event SINKBUSERROR will publish to */
60057   #define MVDMA_PUBLISH_SINKBUSERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
60058   #define MVDMA_PUBLISH_SINKBUSERROR_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_SINKBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
60059   #define MVDMA_PUBLISH_SINKBUSERROR_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                          */
60060   #define MVDMA_PUBLISH_SINKBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */
60061 
60062 /* EN @Bit 31 : (unspecified) */
60063   #define MVDMA_PUBLISH_SINKBUSERROR_EN_Pos (31UL)   /*!< Position of EN field.                                                */
60064   #define MVDMA_PUBLISH_SINKBUSERROR_EN_Msk (0x1UL << MVDMA_PUBLISH_SINKBUSERROR_EN_Pos) /*!< Bit mask of EN field.            */
60065   #define MVDMA_PUBLISH_SINKBUSERROR_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
60066   #define MVDMA_PUBLISH_SINKBUSERROR_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
60067   #define MVDMA_PUBLISH_SINKBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
60068   #define MVDMA_PUBLISH_SINKBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */
60069 
60070 
60071 /* MVDMA_PUBLISH_SOURCESELECTJOBDONE: Publish configuration for event SOURCESELECTJOBDONE */
60072   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SOURCESELECTJOBDONE register.*/
60073 
60074 /* CHIDX @Bits 0..7 : DPPI channel that event SOURCESELECTJOBDONE will publish to */
60075   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                      */
60076   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_SOURCESELECTJOBDONE_CHIDX_Pos) /*!< Bit mask of
60077                                                                             CHIDX field.*/
60078   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                   */
60079   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                   */
60080 
60081 /* EN @Bit 31 : (unspecified) */
60082   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_EN_Pos (31UL) /*!< Position of EN field.                                           */
60083   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_EN_Msk (0x1UL << MVDMA_PUBLISH_SOURCESELECTJOBDONE_EN_Pos) /*!< Bit mask of EN
60084                                                                             field.*/
60085   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                              */
60086   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                              */
60087   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_EN_Disabled (0x0UL) /*!< Disable publishing                                        */
60088   #define MVDMA_PUBLISH_SOURCESELECTJOBDONE_EN_Enabled (0x1UL) /*!< Enable publishing                                          */
60089 
60090 
60091 /* MVDMA_PUBLISH_SINKSELECTJOBDONE: Publish configuration for event SINKSELECTJOBDONE */
60092   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SINKSELECTJOBDONE register.    */
60093 
60094 /* CHIDX @Bits 0..7 : DPPI channel that event SINKSELECTJOBDONE will publish to */
60095   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                        */
60096   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_CHIDX_Msk (0xFFUL << MVDMA_PUBLISH_SINKSELECTJOBDONE_CHIDX_Pos) /*!< Bit mask of CHIDX
60097                                                                             field.*/
60098   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                     */
60099   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                     */
60100 
60101 /* EN @Bit 31 : (unspecified) */
60102   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_EN_Pos (31UL) /*!< Position of EN field.                                             */
60103   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_EN_Msk (0x1UL << MVDMA_PUBLISH_SINKSELECTJOBDONE_EN_Pos) /*!< Bit mask of EN field.  */
60104   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                */
60105   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                */
60106   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_EN_Disabled (0x0UL) /*!< Disable publishing                                          */
60107   #define MVDMA_PUBLISH_SINKSELECTJOBDONE_EN_Enabled (0x1UL) /*!< Enable publishing                                            */
60108 
60109 
60110 /* MVDMA_INTEN: Enable or disable interrupt */
60111   #define MVDMA_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */
60112 
60113 /* END @Bit 0 : Enable or disable interrupt for event END */
60114   #define MVDMA_INTEN_END_Pos (0UL)                  /*!< Position of END field.                                               */
60115   #define MVDMA_INTEN_END_Msk (0x1UL << MVDMA_INTEN_END_Pos) /*!< Bit mask of END field.                                       */
60116   #define MVDMA_INTEN_END_Min (0x0UL)                /*!< Min enumerator value of END field.                                   */
60117   #define MVDMA_INTEN_END_Max (0x1UL)                /*!< Max enumerator value of END field.                                   */
60118   #define MVDMA_INTEN_END_Disabled (0x0UL)           /*!< Disable                                                              */
60119   #define MVDMA_INTEN_END_Enabled (0x1UL)            /*!< Enable                                                               */
60120 
60121 /* STARTED @Bit 1 : Enable or disable interrupt for event STARTED */
60122   #define MVDMA_INTEN_STARTED_Pos (1UL)              /*!< Position of STARTED field.                                           */
60123   #define MVDMA_INTEN_STARTED_Msk (0x1UL << MVDMA_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field.                           */
60124   #define MVDMA_INTEN_STARTED_Min (0x0UL)            /*!< Min enumerator value of STARTED field.                               */
60125   #define MVDMA_INTEN_STARTED_Max (0x1UL)            /*!< Max enumerator value of STARTED field.                               */
60126   #define MVDMA_INTEN_STARTED_Disabled (0x0UL)       /*!< Disable                                                              */
60127   #define MVDMA_INTEN_STARTED_Enabled (0x1UL)        /*!< Enable                                                               */
60128 
60129 /* STOPPED @Bit 2 : Enable or disable interrupt for event STOPPED */
60130   #define MVDMA_INTEN_STOPPED_Pos (2UL)              /*!< Position of STOPPED field.                                           */
60131   #define MVDMA_INTEN_STOPPED_Msk (0x1UL << MVDMA_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                           */
60132   #define MVDMA_INTEN_STOPPED_Min (0x0UL)            /*!< Min enumerator value of STOPPED field.                               */
60133   #define MVDMA_INTEN_STOPPED_Max (0x1UL)            /*!< Max enumerator value of STOPPED field.                               */
60134   #define MVDMA_INTEN_STOPPED_Disabled (0x0UL)       /*!< Disable                                                              */
60135   #define MVDMA_INTEN_STOPPED_Enabled (0x1UL)        /*!< Enable                                                               */
60136 
60137 /* RESET @Bit 3 : Enable or disable interrupt for event RESET */
60138   #define MVDMA_INTEN_RESET_Pos (3UL)                /*!< Position of RESET field.                                             */
60139   #define MVDMA_INTEN_RESET_Msk (0x1UL << MVDMA_INTEN_RESET_Pos) /*!< Bit mask of RESET field.                                 */
60140   #define MVDMA_INTEN_RESET_Min (0x0UL)              /*!< Min enumerator value of RESET field.                                 */
60141   #define MVDMA_INTEN_RESET_Max (0x1UL)              /*!< Max enumerator value of RESET field.                                 */
60142   #define MVDMA_INTEN_RESET_Disabled (0x0UL)         /*!< Disable                                                              */
60143   #define MVDMA_INTEN_RESET_Enabled (0x1UL)          /*!< Enable                                                               */
60144 
60145 /* SOURCEBUSERROR @Bit 4 : Enable or disable interrupt for event SOURCEBUSERROR */
60146   #define MVDMA_INTEN_SOURCEBUSERROR_Pos (4UL)       /*!< Position of SOURCEBUSERROR field.                                    */
60147   #define MVDMA_INTEN_SOURCEBUSERROR_Msk (0x1UL << MVDMA_INTEN_SOURCEBUSERROR_Pos) /*!< Bit mask of SOURCEBUSERROR field.      */
60148   #define MVDMA_INTEN_SOURCEBUSERROR_Min (0x0UL)     /*!< Min enumerator value of SOURCEBUSERROR field.                        */
60149   #define MVDMA_INTEN_SOURCEBUSERROR_Max (0x1UL)     /*!< Max enumerator value of SOURCEBUSERROR field.                        */
60150   #define MVDMA_INTEN_SOURCEBUSERROR_Disabled (0x0UL) /*!< Disable                                                             */
60151   #define MVDMA_INTEN_SOURCEBUSERROR_Enabled (0x1UL) /*!< Enable                                                               */
60152 
60153 /* SINKBUSERROR @Bit 5 : Enable or disable interrupt for event SINKBUSERROR */
60154   #define MVDMA_INTEN_SINKBUSERROR_Pos (5UL)         /*!< Position of SINKBUSERROR field.                                      */
60155   #define MVDMA_INTEN_SINKBUSERROR_Msk (0x1UL << MVDMA_INTEN_SINKBUSERROR_Pos) /*!< Bit mask of SINKBUSERROR field.            */
60156   #define MVDMA_INTEN_SINKBUSERROR_Min (0x0UL)       /*!< Min enumerator value of SINKBUSERROR field.                          */
60157   #define MVDMA_INTEN_SINKBUSERROR_Max (0x1UL)       /*!< Max enumerator value of SINKBUSERROR field.                          */
60158   #define MVDMA_INTEN_SINKBUSERROR_Disabled (0x0UL)  /*!< Disable                                                              */
60159   #define MVDMA_INTEN_SINKBUSERROR_Enabled (0x1UL)   /*!< Enable                                                               */
60160 
60161 /* SOURCESELECTJOBDONE @Bit 6 : Enable or disable interrupt for event SOURCESELECTJOBDONE */
60162   #define MVDMA_INTEN_SOURCESELECTJOBDONE_Pos (6UL)  /*!< Position of SOURCESELECTJOBDONE field.                               */
60163   #define MVDMA_INTEN_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_INTEN_SOURCESELECTJOBDONE_Pos) /*!< Bit mask of
60164                                                                             SOURCESELECTJOBDONE field.*/
60165   #define MVDMA_INTEN_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SOURCESELECTJOBDONE field.                  */
60166   #define MVDMA_INTEN_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SOURCESELECTJOBDONE field.                  */
60167   #define MVDMA_INTEN_SOURCESELECTJOBDONE_Disabled (0x0UL) /*!< Disable                                                        */
60168   #define MVDMA_INTEN_SOURCESELECTJOBDONE_Enabled (0x1UL) /*!< Enable                                                          */
60169 
60170 /* SINKSELECTJOBDONE @Bit 7 : Enable or disable interrupt for event SINKSELECTJOBDONE */
60171   #define MVDMA_INTEN_SINKSELECTJOBDONE_Pos (7UL)    /*!< Position of SINKSELECTJOBDONE field.                                 */
60172   #define MVDMA_INTEN_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_INTEN_SINKSELECTJOBDONE_Pos) /*!< Bit mask of SINKSELECTJOBDONE
60173                                                                             field.*/
60174   #define MVDMA_INTEN_SINKSELECTJOBDONE_Min (0x0UL)  /*!< Min enumerator value of SINKSELECTJOBDONE field.                     */
60175   #define MVDMA_INTEN_SINKSELECTJOBDONE_Max (0x1UL)  /*!< Max enumerator value of SINKSELECTJOBDONE field.                     */
60176   #define MVDMA_INTEN_SINKSELECTJOBDONE_Disabled (0x0UL) /*!< Disable                                                          */
60177   #define MVDMA_INTEN_SINKSELECTJOBDONE_Enabled (0x1UL) /*!< Enable                                                            */
60178 
60179 
60180 /* MVDMA_INTENSET: Enable interrupt */
60181   #define MVDMA_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */
60182 
60183 /* END @Bit 0 : Write '1' to enable interrupt for event END */
60184   #define MVDMA_INTENSET_END_Pos (0UL)               /*!< Position of END field.                                               */
60185   #define MVDMA_INTENSET_END_Msk (0x1UL << MVDMA_INTENSET_END_Pos) /*!< Bit mask of END field.                                 */
60186   #define MVDMA_INTENSET_END_Min (0x0UL)             /*!< Min enumerator value of END field.                                   */
60187   #define MVDMA_INTENSET_END_Max (0x1UL)             /*!< Max enumerator value of END field.                                   */
60188   #define MVDMA_INTENSET_END_Set (0x1UL)             /*!< Enable                                                               */
60189   #define MVDMA_INTENSET_END_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
60190   #define MVDMA_INTENSET_END_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
60191 
60192 /* STARTED @Bit 1 : Write '1' to enable interrupt for event STARTED */
60193   #define MVDMA_INTENSET_STARTED_Pos (1UL)           /*!< Position of STARTED field.                                           */
60194   #define MVDMA_INTENSET_STARTED_Msk (0x1UL << MVDMA_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                     */
60195   #define MVDMA_INTENSET_STARTED_Min (0x0UL)         /*!< Min enumerator value of STARTED field.                               */
60196   #define MVDMA_INTENSET_STARTED_Max (0x1UL)         /*!< Max enumerator value of STARTED field.                               */
60197   #define MVDMA_INTENSET_STARTED_Set (0x1UL)         /*!< Enable                                                               */
60198   #define MVDMA_INTENSET_STARTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
60199   #define MVDMA_INTENSET_STARTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
60200 
60201 /* STOPPED @Bit 2 : Write '1' to enable interrupt for event STOPPED */
60202   #define MVDMA_INTENSET_STOPPED_Pos (2UL)           /*!< Position of STOPPED field.                                           */
60203   #define MVDMA_INTENSET_STOPPED_Msk (0x1UL << MVDMA_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                     */
60204   #define MVDMA_INTENSET_STOPPED_Min (0x0UL)         /*!< Min enumerator value of STOPPED field.                               */
60205   #define MVDMA_INTENSET_STOPPED_Max (0x1UL)         /*!< Max enumerator value of STOPPED field.                               */
60206   #define MVDMA_INTENSET_STOPPED_Set (0x1UL)         /*!< Enable                                                               */
60207   #define MVDMA_INTENSET_STOPPED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
60208   #define MVDMA_INTENSET_STOPPED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
60209 
60210 /* RESET @Bit 3 : Write '1' to enable interrupt for event RESET */
60211   #define MVDMA_INTENSET_RESET_Pos (3UL)             /*!< Position of RESET field.                                             */
60212   #define MVDMA_INTENSET_RESET_Msk (0x1UL << MVDMA_INTENSET_RESET_Pos) /*!< Bit mask of RESET field.                           */
60213   #define MVDMA_INTENSET_RESET_Min (0x0UL)           /*!< Min enumerator value of RESET field.                                 */
60214   #define MVDMA_INTENSET_RESET_Max (0x1UL)           /*!< Max enumerator value of RESET field.                                 */
60215   #define MVDMA_INTENSET_RESET_Set (0x1UL)           /*!< Enable                                                               */
60216   #define MVDMA_INTENSET_RESET_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
60217   #define MVDMA_INTENSET_RESET_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
60218 
60219 /* SOURCEBUSERROR @Bit 4 : Write '1' to enable interrupt for event SOURCEBUSERROR */
60220   #define MVDMA_INTENSET_SOURCEBUSERROR_Pos (4UL)    /*!< Position of SOURCEBUSERROR field.                                    */
60221   #define MVDMA_INTENSET_SOURCEBUSERROR_Msk (0x1UL << MVDMA_INTENSET_SOURCEBUSERROR_Pos) /*!< Bit mask of SOURCEBUSERROR field.*/
60222   #define MVDMA_INTENSET_SOURCEBUSERROR_Min (0x0UL)  /*!< Min enumerator value of SOURCEBUSERROR field.                        */
60223   #define MVDMA_INTENSET_SOURCEBUSERROR_Max (0x1UL)  /*!< Max enumerator value of SOURCEBUSERROR field.                        */
60224   #define MVDMA_INTENSET_SOURCEBUSERROR_Set (0x1UL)  /*!< Enable                                                               */
60225   #define MVDMA_INTENSET_SOURCEBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                   */
60226   #define MVDMA_INTENSET_SOURCEBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                     */
60227 
60228 /* SINKBUSERROR @Bit 5 : Write '1' to enable interrupt for event SINKBUSERROR */
60229   #define MVDMA_INTENSET_SINKBUSERROR_Pos (5UL)      /*!< Position of SINKBUSERROR field.                                      */
60230   #define MVDMA_INTENSET_SINKBUSERROR_Msk (0x1UL << MVDMA_INTENSET_SINKBUSERROR_Pos) /*!< Bit mask of SINKBUSERROR field.      */
60231   #define MVDMA_INTENSET_SINKBUSERROR_Min (0x0UL)    /*!< Min enumerator value of SINKBUSERROR field.                          */
60232   #define MVDMA_INTENSET_SINKBUSERROR_Max (0x1UL)    /*!< Max enumerator value of SINKBUSERROR field.                          */
60233   #define MVDMA_INTENSET_SINKBUSERROR_Set (0x1UL)    /*!< Enable                                                               */
60234   #define MVDMA_INTENSET_SINKBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
60235   #define MVDMA_INTENSET_SINKBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */
60236 
60237 /* SOURCESELECTJOBDONE @Bit 6 : Write '1' to enable interrupt for event SOURCESELECTJOBDONE */
60238   #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Pos (6UL) /*!< Position of SOURCESELECTJOBDONE field.                             */
60239   #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_INTENSET_SOURCESELECTJOBDONE_Pos) /*!< Bit mask of
60240                                                                             SOURCESELECTJOBDONE field.*/
60241   #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SOURCESELECTJOBDONE field.               */
60242   #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SOURCESELECTJOBDONE field.               */
60243   #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Set (0x1UL) /*!< Enable                                                           */
60244   #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Disabled (0x0UL) /*!< Read: Disabled                                              */
60245   #define MVDMA_INTENSET_SOURCESELECTJOBDONE_Enabled (0x1UL) /*!< Read: Enabled                                                */
60246 
60247 /* SINKSELECTJOBDONE @Bit 7 : Write '1' to enable interrupt for event SINKSELECTJOBDONE */
60248   #define MVDMA_INTENSET_SINKSELECTJOBDONE_Pos (7UL) /*!< Position of SINKSELECTJOBDONE field.                                 */
60249   #define MVDMA_INTENSET_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_INTENSET_SINKSELECTJOBDONE_Pos) /*!< Bit mask of
60250                                                                             SINKSELECTJOBDONE field.*/
60251   #define MVDMA_INTENSET_SINKSELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SINKSELECTJOBDONE field.                   */
60252   #define MVDMA_INTENSET_SINKSELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SINKSELECTJOBDONE field.                   */
60253   #define MVDMA_INTENSET_SINKSELECTJOBDONE_Set (0x1UL) /*!< Enable                                                             */
60254   #define MVDMA_INTENSET_SINKSELECTJOBDONE_Disabled (0x0UL) /*!< Read: Disabled                                                */
60255   #define MVDMA_INTENSET_SINKSELECTJOBDONE_Enabled (0x1UL) /*!< Read: Enabled                                                  */
60256 
60257 
60258 /* MVDMA_INTENCLR: Disable interrupt */
60259   #define MVDMA_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */
60260 
60261 /* END @Bit 0 : Write '1' to disable interrupt for event END */
60262   #define MVDMA_INTENCLR_END_Pos (0UL)               /*!< Position of END field.                                               */
60263   #define MVDMA_INTENCLR_END_Msk (0x1UL << MVDMA_INTENCLR_END_Pos) /*!< Bit mask of END field.                                 */
60264   #define MVDMA_INTENCLR_END_Min (0x0UL)             /*!< Min enumerator value of END field.                                   */
60265   #define MVDMA_INTENCLR_END_Max (0x1UL)             /*!< Max enumerator value of END field.                                   */
60266   #define MVDMA_INTENCLR_END_Clear (0x1UL)           /*!< Disable                                                              */
60267   #define MVDMA_INTENCLR_END_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
60268   #define MVDMA_INTENCLR_END_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
60269 
60270 /* STARTED @Bit 1 : Write '1' to disable interrupt for event STARTED */
60271   #define MVDMA_INTENCLR_STARTED_Pos (1UL)           /*!< Position of STARTED field.                                           */
60272   #define MVDMA_INTENCLR_STARTED_Msk (0x1UL << MVDMA_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                     */
60273   #define MVDMA_INTENCLR_STARTED_Min (0x0UL)         /*!< Min enumerator value of STARTED field.                               */
60274   #define MVDMA_INTENCLR_STARTED_Max (0x1UL)         /*!< Max enumerator value of STARTED field.                               */
60275   #define MVDMA_INTENCLR_STARTED_Clear (0x1UL)       /*!< Disable                                                              */
60276   #define MVDMA_INTENCLR_STARTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
60277   #define MVDMA_INTENCLR_STARTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
60278 
60279 /* STOPPED @Bit 2 : Write '1' to disable interrupt for event STOPPED */
60280   #define MVDMA_INTENCLR_STOPPED_Pos (2UL)           /*!< Position of STOPPED field.                                           */
60281   #define MVDMA_INTENCLR_STOPPED_Msk (0x1UL << MVDMA_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                     */
60282   #define MVDMA_INTENCLR_STOPPED_Min (0x0UL)         /*!< Min enumerator value of STOPPED field.                               */
60283   #define MVDMA_INTENCLR_STOPPED_Max (0x1UL)         /*!< Max enumerator value of STOPPED field.                               */
60284   #define MVDMA_INTENCLR_STOPPED_Clear (0x1UL)       /*!< Disable                                                              */
60285   #define MVDMA_INTENCLR_STOPPED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
60286   #define MVDMA_INTENCLR_STOPPED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
60287 
60288 /* RESET @Bit 3 : Write '1' to disable interrupt for event RESET */
60289   #define MVDMA_INTENCLR_RESET_Pos (3UL)             /*!< Position of RESET field.                                             */
60290   #define MVDMA_INTENCLR_RESET_Msk (0x1UL << MVDMA_INTENCLR_RESET_Pos) /*!< Bit mask of RESET field.                           */
60291   #define MVDMA_INTENCLR_RESET_Min (0x0UL)           /*!< Min enumerator value of RESET field.                                 */
60292   #define MVDMA_INTENCLR_RESET_Max (0x1UL)           /*!< Max enumerator value of RESET field.                                 */
60293   #define MVDMA_INTENCLR_RESET_Clear (0x1UL)         /*!< Disable                                                              */
60294   #define MVDMA_INTENCLR_RESET_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
60295   #define MVDMA_INTENCLR_RESET_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
60296 
60297 /* SOURCEBUSERROR @Bit 4 : Write '1' to disable interrupt for event SOURCEBUSERROR */
60298   #define MVDMA_INTENCLR_SOURCEBUSERROR_Pos (4UL)    /*!< Position of SOURCEBUSERROR field.                                    */
60299   #define MVDMA_INTENCLR_SOURCEBUSERROR_Msk (0x1UL << MVDMA_INTENCLR_SOURCEBUSERROR_Pos) /*!< Bit mask of SOURCEBUSERROR field.*/
60300   #define MVDMA_INTENCLR_SOURCEBUSERROR_Min (0x0UL)  /*!< Min enumerator value of SOURCEBUSERROR field.                        */
60301   #define MVDMA_INTENCLR_SOURCEBUSERROR_Max (0x1UL)  /*!< Max enumerator value of SOURCEBUSERROR field.                        */
60302   #define MVDMA_INTENCLR_SOURCEBUSERROR_Clear (0x1UL) /*!< Disable                                                             */
60303   #define MVDMA_INTENCLR_SOURCEBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                   */
60304   #define MVDMA_INTENCLR_SOURCEBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                     */
60305 
60306 /* SINKBUSERROR @Bit 5 : Write '1' to disable interrupt for event SINKBUSERROR */
60307   #define MVDMA_INTENCLR_SINKBUSERROR_Pos (5UL)      /*!< Position of SINKBUSERROR field.                                      */
60308   #define MVDMA_INTENCLR_SINKBUSERROR_Msk (0x1UL << MVDMA_INTENCLR_SINKBUSERROR_Pos) /*!< Bit mask of SINKBUSERROR field.      */
60309   #define MVDMA_INTENCLR_SINKBUSERROR_Min (0x0UL)    /*!< Min enumerator value of SINKBUSERROR field.                          */
60310   #define MVDMA_INTENCLR_SINKBUSERROR_Max (0x1UL)    /*!< Max enumerator value of SINKBUSERROR field.                          */
60311   #define MVDMA_INTENCLR_SINKBUSERROR_Clear (0x1UL)  /*!< Disable                                                              */
60312   #define MVDMA_INTENCLR_SINKBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                     */
60313   #define MVDMA_INTENCLR_SINKBUSERROR_Enabled (0x1UL) /*!< Read: Enabled                                                       */
60314 
60315 /* SOURCESELECTJOBDONE @Bit 6 : Write '1' to disable interrupt for event SOURCESELECTJOBDONE */
60316   #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Pos (6UL) /*!< Position of SOURCESELECTJOBDONE field.                             */
60317   #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_INTENCLR_SOURCESELECTJOBDONE_Pos) /*!< Bit mask of
60318                                                                             SOURCESELECTJOBDONE field.*/
60319   #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SOURCESELECTJOBDONE field.               */
60320   #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SOURCESELECTJOBDONE field.               */
60321   #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Clear (0x1UL) /*!< Disable                                                        */
60322   #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Disabled (0x0UL) /*!< Read: Disabled                                              */
60323   #define MVDMA_INTENCLR_SOURCESELECTJOBDONE_Enabled (0x1UL) /*!< Read: Enabled                                                */
60324 
60325 /* SINKSELECTJOBDONE @Bit 7 : Write '1' to disable interrupt for event SINKSELECTJOBDONE */
60326   #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Pos (7UL) /*!< Position of SINKSELECTJOBDONE field.                                 */
60327   #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_INTENCLR_SINKSELECTJOBDONE_Pos) /*!< Bit mask of
60328                                                                             SINKSELECTJOBDONE field.*/
60329   #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SINKSELECTJOBDONE field.                   */
60330   #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SINKSELECTJOBDONE field.                   */
60331   #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Clear (0x1UL) /*!< Disable                                                          */
60332   #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Disabled (0x0UL) /*!< Read: Disabled                                                */
60333   #define MVDMA_INTENCLR_SINKSELECTJOBDONE_Enabled (0x1UL) /*!< Read: Enabled                                                  */
60334 
60335 
60336 /* MVDMA_INTPEND: Pending interrupts */
60337   #define MVDMA_INTPEND_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND register.                                     */
60338 
60339 /* END @Bit 0 : Read pending status of interrupt for event END */
60340   #define MVDMA_INTPEND_END_Pos (0UL)                /*!< Position of END field.                                               */
60341   #define MVDMA_INTPEND_END_Msk (0x1UL << MVDMA_INTPEND_END_Pos) /*!< Bit mask of END field.                                   */
60342   #define MVDMA_INTPEND_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
60343   #define MVDMA_INTPEND_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
60344   #define MVDMA_INTPEND_END_NotPending (0x0UL)       /*!< Read: Not pending                                                    */
60345   #define MVDMA_INTPEND_END_Pending (0x1UL)          /*!< Read: Pending                                                        */
60346 
60347 /* STARTED @Bit 1 : Read pending status of interrupt for event STARTED */
60348   #define MVDMA_INTPEND_STARTED_Pos (1UL)            /*!< Position of STARTED field.                                           */
60349   #define MVDMA_INTPEND_STARTED_Msk (0x1UL << MVDMA_INTPEND_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
60350   #define MVDMA_INTPEND_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
60351   #define MVDMA_INTPEND_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
60352   #define MVDMA_INTPEND_STARTED_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
60353   #define MVDMA_INTPEND_STARTED_Pending (0x1UL)      /*!< Read: Pending                                                        */
60354 
60355 /* STOPPED @Bit 2 : Read pending status of interrupt for event STOPPED */
60356   #define MVDMA_INTPEND_STOPPED_Pos (2UL)            /*!< Position of STOPPED field.                                           */
60357   #define MVDMA_INTPEND_STOPPED_Msk (0x1UL << MVDMA_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
60358   #define MVDMA_INTPEND_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
60359   #define MVDMA_INTPEND_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
60360   #define MVDMA_INTPEND_STOPPED_NotPending (0x0UL)   /*!< Read: Not pending                                                    */
60361   #define MVDMA_INTPEND_STOPPED_Pending (0x1UL)      /*!< Read: Pending                                                        */
60362 
60363 /* RESET @Bit 3 : Read pending status of interrupt for event RESET */
60364   #define MVDMA_INTPEND_RESET_Pos (3UL)              /*!< Position of RESET field.                                             */
60365   #define MVDMA_INTPEND_RESET_Msk (0x1UL << MVDMA_INTPEND_RESET_Pos) /*!< Bit mask of RESET field.                             */
60366   #define MVDMA_INTPEND_RESET_Min (0x0UL)            /*!< Min enumerator value of RESET field.                                 */
60367   #define MVDMA_INTPEND_RESET_Max (0x1UL)            /*!< Max enumerator value of RESET field.                                 */
60368   #define MVDMA_INTPEND_RESET_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
60369   #define MVDMA_INTPEND_RESET_Pending (0x1UL)        /*!< Read: Pending                                                        */
60370 
60371 /* SOURCEBUSERROR @Bit 4 : Read pending status of interrupt for event SOURCEBUSERROR */
60372   #define MVDMA_INTPEND_SOURCEBUSERROR_Pos (4UL)     /*!< Position of SOURCEBUSERROR field.                                    */
60373   #define MVDMA_INTPEND_SOURCEBUSERROR_Msk (0x1UL << MVDMA_INTPEND_SOURCEBUSERROR_Pos) /*!< Bit mask of SOURCEBUSERROR field.  */
60374   #define MVDMA_INTPEND_SOURCEBUSERROR_Min (0x0UL)   /*!< Min enumerator value of SOURCEBUSERROR field.                        */
60375   #define MVDMA_INTPEND_SOURCEBUSERROR_Max (0x1UL)   /*!< Max enumerator value of SOURCEBUSERROR field.                        */
60376   #define MVDMA_INTPEND_SOURCEBUSERROR_NotPending (0x0UL) /*!< Read: Not pending                                               */
60377   #define MVDMA_INTPEND_SOURCEBUSERROR_Pending (0x1UL) /*!< Read: Pending                                                      */
60378 
60379 /* SINKBUSERROR @Bit 5 : Read pending status of interrupt for event SINKBUSERROR */
60380   #define MVDMA_INTPEND_SINKBUSERROR_Pos (5UL)       /*!< Position of SINKBUSERROR field.                                      */
60381   #define MVDMA_INTPEND_SINKBUSERROR_Msk (0x1UL << MVDMA_INTPEND_SINKBUSERROR_Pos) /*!< Bit mask of SINKBUSERROR field.        */
60382   #define MVDMA_INTPEND_SINKBUSERROR_Min (0x0UL)     /*!< Min enumerator value of SINKBUSERROR field.                          */
60383   #define MVDMA_INTPEND_SINKBUSERROR_Max (0x1UL)     /*!< Max enumerator value of SINKBUSERROR field.                          */
60384   #define MVDMA_INTPEND_SINKBUSERROR_NotPending (0x0UL) /*!< Read: Not pending                                                 */
60385   #define MVDMA_INTPEND_SINKBUSERROR_Pending (0x1UL) /*!< Read: Pending                                                        */
60386 
60387 /* SOURCESELECTJOBDONE @Bit 6 : Read pending status of interrupt for event SOURCESELECTJOBDONE */
60388   #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Pos (6UL) /*!< Position of SOURCESELECTJOBDONE field.                              */
60389   #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Msk (0x1UL << MVDMA_INTPEND_SOURCESELECTJOBDONE_Pos) /*!< Bit mask of
60390                                                                             SOURCESELECTJOBDONE field.*/
60391   #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SOURCESELECTJOBDONE field.                */
60392   #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SOURCESELECTJOBDONE field.                */
60393   #define MVDMA_INTPEND_SOURCESELECTJOBDONE_NotPending (0x0UL) /*!< Read: Not pending                                          */
60394   #define MVDMA_INTPEND_SOURCESELECTJOBDONE_Pending (0x1UL) /*!< Read: Pending                                                 */
60395 
60396 /* SINKSELECTJOBDONE @Bit 7 : Read pending status of interrupt for event SINKSELECTJOBDONE */
60397   #define MVDMA_INTPEND_SINKSELECTJOBDONE_Pos (7UL)  /*!< Position of SINKSELECTJOBDONE field.                                 */
60398   #define MVDMA_INTPEND_SINKSELECTJOBDONE_Msk (0x1UL << MVDMA_INTPEND_SINKSELECTJOBDONE_Pos) /*!< Bit mask of SINKSELECTJOBDONE
60399                                                                             field.*/
60400   #define MVDMA_INTPEND_SINKSELECTJOBDONE_Min (0x0UL) /*!< Min enumerator value of SINKSELECTJOBDONE field.                    */
60401   #define MVDMA_INTPEND_SINKSELECTJOBDONE_Max (0x1UL) /*!< Max enumerator value of SINKSELECTJOBDONE field.                    */
60402   #define MVDMA_INTPEND_SINKSELECTJOBDONE_NotPending (0x0UL) /*!< Read: Not pending                                            */
60403   #define MVDMA_INTPEND_SINKSELECTJOBDONE_Pending (0x1UL) /*!< Read: Pending                                                   */
60404 
60405 
60406 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
60407 
60408 /* =========================================================================================================================== */
60409 /* ================                                           NFCT                                           ================ */
60410 /* =========================================================================================================================== */
60411 
60412 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
60413 
60414 /* ================================================= Struct NFCT_FRAMESTATUS ================================================= */
60415 /**
60416   * @brief FRAMESTATUS [NFCT_FRAMESTATUS] (unspecified)
60417   */
60418 typedef struct {
60419   __IOM uint32_t  RX;                                /*!< (@ 0x00000000) Result of last incoming frame                         */
60420 } NRF_NFCT_FRAMESTATUS_Type;                         /*!< Size = 4 (0x004)                                                     */
60421 
60422 /* NFCT_FRAMESTATUS_RX: Result of last incoming frame */
60423   #define NFCT_FRAMESTATUS_RX_ResetValue (0x00000000UL) /*!< Reset value of RX register.                                       */
60424 
60425 /* CRCERROR @Bit 0 : No valid end of frame (EoF) detected */
60426   #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL)     /*!< Position of CRCERROR field.                                          */
60427   #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.        */
60428   #define NFCT_FRAMESTATUS_RX_CRCERROR_Min (0x0UL)   /*!< Min enumerator value of CRCERROR field.                              */
60429   #define NFCT_FRAMESTATUS_RX_CRCERROR_Max (0x1UL)   /*!< Max enumerator value of CRCERROR field.                              */
60430   #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0x0UL) /*!< Valid CRC detected                                              */
60431   #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (0x1UL) /*!< CRC received does not match local check                           */
60432 
60433 /* PARITYSTATUS @Bit 2 : Parity status of received frame */
60434   #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field.                                      */
60435   #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS
60436                                                                             field.*/
60437   #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Min (0x0UL) /*!< Min enumerator value of PARITYSTATUS field.                        */
60438   #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Max (0x1UL) /*!< Max enumerator value of PARITYSTATUS field.                        */
60439   #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0x0UL) /*!< Frame received with parity OK                                 */
60440   #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (0x1UL) /*!< Frame received with parity error                           */
60441 
60442 /* OVERRUN @Bit 3 : Overrun detected */
60443   #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL)      /*!< Position of OVERRUN field.                                           */
60444   #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field.           */
60445   #define NFCT_FRAMESTATUS_RX_OVERRUN_Min (0x0UL)    /*!< Min enumerator value of OVERRUN field.                               */
60446   #define NFCT_FRAMESTATUS_RX_OVERRUN_Max (0x1UL)    /*!< Max enumerator value of OVERRUN field.                               */
60447   #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0x0UL) /*!< No overrun detected                                               */
60448   #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (0x1UL) /*!< Overrun error                                                       */
60449 
60450 
60451 
60452 /* ===================================================== Struct NFCT_TXD ===================================================== */
60453 /**
60454   * @brief TXD [NFCT_TXD] (unspecified)
60455   */
60456 typedef struct {
60457   __IOM uint32_t  FRAMECONFIG;                       /*!< (@ 0x00000000) Configuration of outgoing frames                      */
60458   __IOM uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Size of outgoing frame                                */
60459 } NRF_NFCT_TXD_Type;                                 /*!< Size = 8 (0x008)                                                     */
60460 
60461 /* NFCT_TXD_FRAMECONFIG: Configuration of outgoing frames */
60462   #define NFCT_TXD_FRAMECONFIG_ResetValue (0x00000017UL) /*!< Reset value of FRAMECONFIG register.                             */
60463 
60464 /* PARITY @Bit 0 : Indicates if parity is added to the frame */
60465   #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL)      /*!< Position of PARITY field.                                            */
60466   #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field.            */
60467   #define NFCT_TXD_FRAMECONFIG_PARITY_Min (0x0UL)    /*!< Min enumerator value of PARITY field.                                */
60468   #define NFCT_TXD_FRAMECONFIG_PARITY_Max (0x1UL)    /*!< Max enumerator value of PARITY field.                                */
60469   #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not added to TX frames                                   */
60470   #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is added to TX frames                                         */
60471 
60472 /* DISCARDMODE @Bit 1 : Discarding unused bits at start or end of a frame */
60473   #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field.                                       */
60474   #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE
60475                                                                             field.*/
60476   #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Min (0x0UL) /*!< Min enumerator value of DISCARDMODE field.                         */
60477   #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Max (0x1UL) /*!< Max enumerator value of DISCARDMODE field.                         */
60478   #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0x0UL) /*!< Unused bits are discarded at end of frame (EoF)             */
60479   #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (0x1UL) /*!< Unused bits are discarded at start of frame (SoF)         */
60480 
60481 /* SOF @Bit 2 : Adding SoF or not in TX frames */
60482   #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL)         /*!< Position of SOF field.                                               */
60483   #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field.                     */
60484   #define NFCT_TXD_FRAMECONFIG_SOF_Min (0x0UL)       /*!< Min enumerator value of SOF field.                                   */
60485   #define NFCT_TXD_FRAMECONFIG_SOF_Max (0x1UL)       /*!< Max enumerator value of SOF field.                                   */
60486   #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0x0UL)     /*!< SoF symbol not added                                                 */
60487   #define NFCT_TXD_FRAMECONFIG_SOF_SoF (0x1UL)       /*!< SoF symbol added                                                     */
60488 
60489 /* CRCMODETX @Bit 4 : CRC mode for outgoing frames */
60490   #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL)   /*!< Position of CRCMODETX field.                                         */
60491   #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field.   */
60492   #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Min (0x0UL) /*!< Min enumerator value of CRCMODETX field.                             */
60493   #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Max (0x1UL) /*!< Max enumerator value of CRCMODETX field.                             */
60494   #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0x0UL) /*!< CRC is not added to the frame                                    */
60495   #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (0x1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM
60496                                                               that is used in the frame*/
60497 
60498 
60499 /* NFCT_TXD_AMOUNT: Size of outgoing frame */
60500   #define NFCT_TXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
60501 
60502 /* TXDATABITS @Bits 0..2 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding
60503                            parity bit). */
60504 
60505   #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL)       /*!< Position of TXDATABITS field.                                        */
60506   #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field.          */
60507   #define NFCT_TXD_AMOUNT_TXDATABITS_Min (0x0UL)     /*!< Min value of TXDATABITS field.                                       */
60508   #define NFCT_TXD_AMOUNT_TXDATABITS_Max (0x7UL)     /*!< Max size of TXDATABITS field.                                        */
60509 
60510 /* TXDATABYTES @Bits 3..11 : Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. */
60511   #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL)      /*!< Position of TXDATABYTES field.                                       */
60512   #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field.     */
60513   #define NFCT_TXD_AMOUNT_TXDATABYTES_Min (0x0UL)    /*!< Min value of TXDATABYTES field.                                      */
60514   #define NFCT_TXD_AMOUNT_TXDATABYTES_Max (0x101UL)  /*!< Max size of TXDATABYTES field.                                       */
60515 
60516 
60517 
60518 /* ===================================================== Struct NFCT_RXD ===================================================== */
60519 /**
60520   * @brief RXD [NFCT_RXD] (unspecified)
60521   */
60522 typedef struct {
60523   __IOM uint32_t  FRAMECONFIG;                       /*!< (@ 0x00000000) Configuration of incoming frames                      */
60524   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000004) Size of last incoming frame                           */
60525 } NRF_NFCT_RXD_Type;                                 /*!< Size = 8 (0x008)                                                     */
60526 
60527 /* NFCT_RXD_FRAMECONFIG: Configuration of incoming frames */
60528   #define NFCT_RXD_FRAMECONFIG_ResetValue (0x00000015UL) /*!< Reset value of FRAMECONFIG register.                             */
60529 
60530 /* PARITY @Bit 0 : Indicates if parity expected in RX frame */
60531   #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL)      /*!< Position of PARITY field.                                            */
60532   #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field.            */
60533   #define NFCT_RXD_FRAMECONFIG_PARITY_Min (0x0UL)    /*!< Min enumerator value of PARITY field.                                */
60534   #define NFCT_RXD_FRAMECONFIG_PARITY_Max (0x1UL)    /*!< Max enumerator value of PARITY field.                                */
60535   #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0x0UL) /*!< Parity is not expected in RX frames                                */
60536   #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (0x1UL) /*!< Parity is expected in RX frames                                      */
60537 
60538 /* SOF @Bit 2 : SoF expected or not in RX frames */
60539   #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL)         /*!< Position of SOF field.                                               */
60540   #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field.                     */
60541   #define NFCT_RXD_FRAMECONFIG_SOF_Min (0x0UL)       /*!< Min enumerator value of SOF field.                                   */
60542   #define NFCT_RXD_FRAMECONFIG_SOF_Max (0x1UL)       /*!< Max enumerator value of SOF field.                                   */
60543   #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0x0UL)     /*!< SoF symbol is not expected in RX frames                              */
60544   #define NFCT_RXD_FRAMECONFIG_SOF_SoF (0x1UL)       /*!< SoF symbol is expected in RX frames                                  */
60545 
60546 /* CRCMODERX @Bit 4 : CRC mode for incoming frames */
60547   #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL)   /*!< Position of CRCMODERX field.                                         */
60548   #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field.   */
60549   #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Min (0x0UL) /*!< Min enumerator value of CRCMODERX field.                             */
60550   #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Max (0x1UL) /*!< Max enumerator value of CRCMODERX field.                             */
60551   #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0x0UL) /*!< CRC is not expected in RX frames                                 */
60552   #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (0x1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS
60553                                                               updated*/
60554 
60555 
60556 /* NFCT_RXD_AMOUNT: Size of last incoming frame */
60557   #define NFCT_RXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
60558 
60559 /* RXDATABITS @Bits 0..2 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and
60560                            SoF/EoF framing). */
60561 
60562   #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL)       /*!< Position of RXDATABITS field.                                        */
60563   #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field.          */
60564 
60565 /* RXDATABYTES @Bits 3..11 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF
60566                              framing) */
60567 
60568   #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL)      /*!< Position of RXDATABYTES field.                                       */
60569   #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field.     */
60570 
60571 
60572 /* ======================================================= Struct NFCT ======================================================= */
60573 /**
60574   * @brief NFC-A compatible radio NFC-A compatible radio
60575   */
60576   typedef struct {                                   /*!< NFCT Structure                                                       */
60577     __OM uint32_t TASKS_ACTIVATE;                    /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing
60578                                                                          frames, change state to activated*/
60579     __OM uint32_t TASKS_DISABLE;                     /*!< (@ 0x00000004) Disable NFCT peripheral                               */
60580     __OM uint32_t TASKS_SENSE;                       /*!< (@ 0x00000008) Enable NFC sense field mode, change state to sense
60581                                                                          mode*/
60582     __OM uint32_t TASKS_STARTTX;                     /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change state
60583                                                                          to transmit*/
60584     __OM uint32_t TASKS_STOPTX;                      /*!< (@ 0x00000010) Stops an issued transmission of a frame               */
60585     __IM uint32_t RESERVED[2];
60586     __OM uint32_t TASKS_ENABLERXDATA;                /*!< (@ 0x0000001C) Initializes the EasyDMA for receive.                  */
60587     __IM uint32_t RESERVED1;
60588     __OM uint32_t TASKS_GOIDLE;                      /*!< (@ 0x00000024) Force state machine to IDLE state                     */
60589     __OM uint32_t TASKS_GOSLEEP;                     /*!< (@ 0x00000028) Force state machine to SLEEP_A state                  */
60590     __IM uint32_t RESERVED2[21];
60591     __IOM uint32_t SUBSCRIBE_ACTIVATE;               /*!< (@ 0x00000080) Subscribe configuration for task ACTIVATE             */
60592     __IOM uint32_t SUBSCRIBE_DISABLE;                /*!< (@ 0x00000084) Subscribe configuration for task DISABLE              */
60593     __IOM uint32_t SUBSCRIBE_SENSE;                  /*!< (@ 0x00000088) Subscribe configuration for task SENSE                */
60594     __IOM uint32_t SUBSCRIBE_STARTTX;                /*!< (@ 0x0000008C) Subscribe configuration for task STARTTX              */
60595     __IOM uint32_t SUBSCRIBE_STOPTX;                 /*!< (@ 0x00000090) Subscribe configuration for task STOPTX               */
60596     __IM uint32_t RESERVED3[2];
60597     __IOM uint32_t SUBSCRIBE_ENABLERXDATA;           /*!< (@ 0x0000009C) Subscribe configuration for task ENABLERXDATA         */
60598     __IM uint32_t RESERVED4;
60599     __IOM uint32_t SUBSCRIBE_GOIDLE;                 /*!< (@ 0x000000A4) Subscribe configuration for task GOIDLE               */
60600     __IOM uint32_t SUBSCRIBE_GOSLEEP;                /*!< (@ 0x000000A8) Subscribe configuration for task GOSLEEP              */
60601     __IM uint32_t RESERVED5[21];
60602     __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send
60603                                                                          frames*/
60604     __IOM uint32_t EVENTS_FIELDDETECTED;             /*!< (@ 0x00000104) Remote NFC field detected                             */
60605     __IOM uint32_t EVENTS_FIELDLOST;                 /*!< (@ 0x00000108) Remote NFC field lost                                 */
60606     __IOM uint32_t EVENTS_TXFRAMESTART;              /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted
60607                                                                          frame*/
60608     __IOM uint32_t EVENTS_TXFRAMEEND;                /*!< (@ 0x00000110) Marks the end of the last transmitted on-air symbol of
60609                                                                          a frame*/
60610     __IOM uint32_t EVENTS_RXFRAMESTART;              /*!< (@ 0x00000114) Marks the end of the first symbol of a received frame */
60611     __IOM uint32_t EVENTS_RXFRAMEEND;                /*!< (@ 0x00000118) Received data has been checked (CRC, parity) and
60612                                                                          transferred to RAM, and EasyDMA has ended accessing the
60613                                                                          RX buffer*/
60614     __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register contains
60615                                                                          details on the source of the error.*/
60616     __IM uint32_t RESERVED6[2];
60617     __IOM uint32_t EVENTS_RXERROR;                   /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX
60618                                                                          register contains details on the source of the error.*/
60619     __IOM uint32_t EVENTS_ENDRX;                     /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) in Data
60620                                                                          RAM full.*/
60621     __IOM uint32_t EVENTS_ENDTX;                     /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA has
60622                                                                          ended accessing the TX buffer*/
60623     __IM uint32_t RESERVED7;
60624     __IOM uint32_t EVENTS_AUTOCOLRESSTARTED;         /*!< (@ 0x00000138) Auto collision resolution process has started         */
60625     __IM uint32_t RESERVED8[3];
60626     __IOM uint32_t EVENTS_COLLISION;                 /*!< (@ 0x00000148) NFC auto collision resolution error reported.         */
60627     __IOM uint32_t EVENTS_SELECTED;                  /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed  */
60628     __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames.           */
60629     __IM uint32_t RESERVED9[11];
60630     __IOM uint32_t PUBLISH_READY;                    /*!< (@ 0x00000180) Publish configuration for event READY                 */
60631     __IOM uint32_t PUBLISH_FIELDDETECTED;            /*!< (@ 0x00000184) Publish configuration for event FIELDDETECTED         */
60632     __IOM uint32_t PUBLISH_FIELDLOST;                /*!< (@ 0x00000188) Publish configuration for event FIELDLOST             */
60633     __IOM uint32_t PUBLISH_TXFRAMESTART;             /*!< (@ 0x0000018C) Publish configuration for event TXFRAMESTART          */
60634     __IOM uint32_t PUBLISH_TXFRAMEEND;               /*!< (@ 0x00000190) Publish configuration for event TXFRAMEEND            */
60635     __IOM uint32_t PUBLISH_RXFRAMESTART;             /*!< (@ 0x00000194) Publish configuration for event RXFRAMESTART          */
60636     __IOM uint32_t PUBLISH_RXFRAMEEND;               /*!< (@ 0x00000198) Publish configuration for event RXFRAMEEND            */
60637     __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x0000019C) Publish configuration for event ERROR                 */
60638     __IM uint32_t RESERVED10[2];
60639     __IOM uint32_t PUBLISH_RXERROR;                  /*!< (@ 0x000001A8) Publish configuration for event RXERROR               */
60640     __IOM uint32_t PUBLISH_ENDRX;                    /*!< (@ 0x000001AC) Publish configuration for event ENDRX                 */
60641     __IOM uint32_t PUBLISH_ENDTX;                    /*!< (@ 0x000001B0) Publish configuration for event ENDTX                 */
60642     __IM uint32_t RESERVED11;
60643     __IOM uint32_t PUBLISH_AUTOCOLRESSTARTED;        /*!< (@ 0x000001B8) Publish configuration for event AUTOCOLRESSTARTED     */
60644     __IM uint32_t RESERVED12[3];
60645     __IOM uint32_t PUBLISH_COLLISION;                /*!< (@ 0x000001C8) Publish configuration for event COLLISION             */
60646     __IOM uint32_t PUBLISH_SELECTED;                 /*!< (@ 0x000001CC) Publish configuration for event SELECTED              */
60647     __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x000001D0) Publish configuration for event STARTED               */
60648     __IM uint32_t RESERVED13[11];
60649     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
60650     __IM uint32_t RESERVED14[63];
60651     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
60652     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
60653     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
60654     __IM uint32_t RESERVED15[62];
60655     __IOM uint32_t ERRORSTATUS;                      /*!< (@ 0x00000404) NFC Error Status register                             */
60656     __IM uint32_t RESERVED16;
60657     __IOM NRF_NFCT_FRAMESTATUS_Type FRAMESTATUS;     /*!< (@ 0x0000040C) (unspecified)                                         */
60658     __IM uint32_t NFCTAGSTATE;                       /*!< (@ 0x00000410) Current operating state of NFC tag                    */
60659     __IM uint32_t RESERVED17[3];
60660     __IM uint32_t SLEEPSTATE;                        /*!< (@ 0x00000420) Sleep state during automatic collision resolution     */
60661     __IM uint32_t RESERVED18[6];
60662     __IM uint32_t FIELDPRESENT;                      /*!< (@ 0x0000043C) Indicates the presence or not of a valid field        */
60663     __IM uint32_t RESERVED19[49];
60664     __IOM uint32_t FRAMEDELAYMIN;                    /*!< (@ 0x00000504) Minimum frame delay                                   */
60665     __IOM uint32_t FRAMEDELAYMAX;                    /*!< (@ 0x00000508) Maximum frame delay                                   */
60666     __IOM uint32_t FRAMEDELAYMODE;                   /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer      */
60667     __IM uint32_t RESERVED20[2];
60668     __IOM NRF_NFCT_TXD_Type TXD;                     /*!< (@ 0x00000518) (unspecified)                                         */
60669     __IOM NRF_NFCT_RXD_Type RXD;                     /*!< (@ 0x00000520) (unspecified)                                         */
60670     __IM uint32_t RESERVED21;
60671     __IOM uint32_t MODULATIONCTRL;                   /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which can
60672                                                                          be connected to a second external antenna.*/
60673     __IM uint32_t RESERVED22[2];
60674     __IOM uint32_t MODULATIONPSEL;                   /*!< (@ 0x00000538) Pin select for Modulation control                     */
60675     __IM uint32_t RESERVED23[5];
60676     __IOM uint32_t MODE;                             /*!< (@ 0x00000550) Configure EasyDMA mode                                */
60677     __IM uint32_t RESERVED24[15];
60678     __IOM uint32_t NFCID1_LAST;                      /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID)                */
60679     __IOM uint32_t NFCID1_2ND_LAST;                  /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID)            */
60680     __IOM uint32_t NFCID1_3RD_LAST;                  /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID)                  */
60681     __IOM uint32_t AUTOCOLRESCONFIG;                 /*!< (@ 0x0000059C) Controls the auto collision resolution function. This
60682                                                                          setting must be done before the NFCT peripheral is
60683                                                                          activated.*/
60684     __IOM uint32_t SENSRES;                          /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings                 */
60685     __IOM uint32_t SELRES;                           /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings                  */
60686     __IM uint32_t RESERVED25[302];
60687     __IOM uint32_t PACKETPTR;                        /*!< (@ 0x00000A60) Packet pointer for TXD and RXD data storage in Data
60688                                                                          RAM*/
60689     __IOM uint32_t MAXLEN;                           /*!< (@ 0x00000A64) Size of the RAM buffer allocated to TXD and RXD data
60690                                                                          storage each*/
60691   } NRF_NFCT_Type;                                   /*!< Size = 2664 (0xA68)                                                  */
60692 
60693 /* NFCT_TASKS_ACTIVATE: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
60694   #define NFCT_TASKS_ACTIVATE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ACTIVATE register.                           */
60695 
60696 /* TASKS_ACTIVATE @Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */
60697   #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field.                                  */
60698   #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of
60699                                                                             TASKS_ACTIVATE field.*/
60700   #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Min (0x1UL) /*!< Min enumerator value of TASKS_ACTIVATE field.                    */
60701   #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Max (0x1UL) /*!< Max enumerator value of TASKS_ACTIVATE field.                    */
60702   #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (0x1UL) /*!< Trigger task                                                 */
60703 
60704 
60705 /* NFCT_TASKS_DISABLE: Disable NFCT peripheral */
60706   #define NFCT_TASKS_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_DISABLE register.                             */
60707 
60708 /* TASKS_DISABLE @Bit 0 : Disable NFCT peripheral */
60709   #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field.                                     */
60710   #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE
60711                                                                             field.*/
60712   #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Min (0x1UL) /*!< Min enumerator value of TASKS_DISABLE field.                       */
60713   #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Max (0x1UL) /*!< Max enumerator value of TASKS_DISABLE field.                       */
60714   #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task                                                   */
60715 
60716 
60717 /* NFCT_TASKS_SENSE: Enable NFC sense field mode, change state to sense mode */
60718   #define NFCT_TASKS_SENSE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SENSE register.                                 */
60719 
60720 /* TASKS_SENSE @Bit 0 : Enable NFC sense field mode, change state to sense mode */
60721   #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL)     /*!< Position of TASKS_SENSE field.                                       */
60722   #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field.     */
60723   #define NFCT_TASKS_SENSE_TASKS_SENSE_Min (0x1UL)   /*!< Min enumerator value of TASKS_SENSE field.                           */
60724   #define NFCT_TASKS_SENSE_TASKS_SENSE_Max (0x1UL)   /*!< Max enumerator value of TASKS_SENSE field.                           */
60725   #define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (0x1UL) /*!< Trigger task                                                       */
60726 
60727 
60728 /* NFCT_TASKS_STARTTX: Start transmission of an outgoing frame, change state to transmit */
60729   #define NFCT_TASKS_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STARTTX register.                             */
60730 
60731 /* TASKS_STARTTX @Bit 0 : Start transmission of an outgoing frame, change state to transmit */
60732   #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field.                                     */
60733   #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX
60734                                                                             field.*/
60735   #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STARTTX field.                       */
60736   #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STARTTX field.                       */
60737   #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task                                                   */
60738 
60739 
60740 /* NFCT_TASKS_STOPTX: Stops an issued transmission of a frame */
60741   #define NFCT_TASKS_STOPTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPTX register.                               */
60742 
60743 /* TASKS_STOPTX @Bit 0 : Stops an issued transmission of a frame */
60744   #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL)   /*!< Position of TASKS_STOPTX field.                                      */
60745   #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << NFCT_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field.*/
60746   #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPTX field.                          */
60747   #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPTX field.                          */
60748   #define NFCT_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task                                                     */
60749 
60750 
60751 /* NFCT_TASKS_ENABLERXDATA: Initializes the EasyDMA for receive. */
60752   #define NFCT_TASKS_ENABLERXDATA_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ENABLERXDATA register.                   */
60753 
60754 /* TASKS_ENABLERXDATA @Bit 0 : Initializes the EasyDMA for receive. */
60755   #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field.                      */
60756   #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask
60757                                                                             of TASKS_ENABLERXDATA field.*/
60758   #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Min (0x1UL) /*!< Min enumerator value of TASKS_ENABLERXDATA field.        */
60759   #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Max (0x1UL) /*!< Max enumerator value of TASKS_ENABLERXDATA field.        */
60760   #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (0x1UL) /*!< Trigger task                                         */
60761 
60762 
60763 /* NFCT_TASKS_GOIDLE: Force state machine to IDLE state */
60764   #define NFCT_TASKS_GOIDLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_GOIDLE register.                               */
60765 
60766 /* TASKS_GOIDLE @Bit 0 : Force state machine to IDLE state */
60767   #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL)   /*!< Position of TASKS_GOIDLE field.                                      */
60768   #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field.*/
60769   #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Min (0x1UL) /*!< Min enumerator value of TASKS_GOIDLE field.                          */
60770   #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Max (0x1UL) /*!< Max enumerator value of TASKS_GOIDLE field.                          */
60771   #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (0x1UL) /*!< Trigger task                                                     */
60772 
60773 
60774 /* NFCT_TASKS_GOSLEEP: Force state machine to SLEEP_A state */
60775   #define NFCT_TASKS_GOSLEEP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_GOSLEEP register.                             */
60776 
60777 /* TASKS_GOSLEEP @Bit 0 : Force state machine to SLEEP_A state */
60778   #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field.                                     */
60779   #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP
60780                                                                             field.*/
60781   #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Min (0x1UL) /*!< Min enumerator value of TASKS_GOSLEEP field.                       */
60782   #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Max (0x1UL) /*!< Max enumerator value of TASKS_GOSLEEP field.                       */
60783   #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (0x1UL) /*!< Trigger task                                                   */
60784 
60785 
60786 /* NFCT_SUBSCRIBE_ACTIVATE: Subscribe configuration for task ACTIVATE */
60787   #define NFCT_SUBSCRIBE_ACTIVATE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ACTIVATE register.                   */
60788 
60789 /* CHIDX @Bits 0..7 : DPPI channel that task ACTIVATE will subscribe to */
60790   #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
60791   #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
60792   #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
60793   #define NFCT_SUBSCRIBE_ACTIVATE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
60794 
60795 /* EN @Bit 31 : (unspecified) */
60796   #define NFCT_SUBSCRIBE_ACTIVATE_EN_Pos (31UL)      /*!< Position of EN field.                                                */
60797   #define NFCT_SUBSCRIBE_ACTIVATE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ACTIVATE_EN_Pos) /*!< Bit mask of EN field.                  */
60798   #define NFCT_SUBSCRIBE_ACTIVATE_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
60799   #define NFCT_SUBSCRIBE_ACTIVATE_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
60800   #define NFCT_SUBSCRIBE_ACTIVATE_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
60801   #define NFCT_SUBSCRIBE_ACTIVATE_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
60802 
60803 
60804 /* NFCT_SUBSCRIBE_DISABLE: Subscribe configuration for task DISABLE */
60805   #define NFCT_SUBSCRIBE_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_DISABLE register.                     */
60806 
60807 /* CHIDX @Bits 0..7 : DPPI channel that task DISABLE will subscribe to */
60808   #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
60809   #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
60810   #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
60811   #define NFCT_SUBSCRIBE_DISABLE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
60812 
60813 /* EN @Bit 31 : (unspecified) */
60814   #define NFCT_SUBSCRIBE_DISABLE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
60815   #define NFCT_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field.                    */
60816   #define NFCT_SUBSCRIBE_DISABLE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
60817   #define NFCT_SUBSCRIBE_DISABLE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
60818   #define NFCT_SUBSCRIBE_DISABLE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
60819   #define NFCT_SUBSCRIBE_DISABLE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
60820 
60821 
60822 /* NFCT_SUBSCRIBE_SENSE: Subscribe configuration for task SENSE */
60823   #define NFCT_SUBSCRIBE_SENSE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SENSE register.                         */
60824 
60825 /* CHIDX @Bits 0..7 : DPPI channel that task SENSE will subscribe to */
60826   #define NFCT_SUBSCRIBE_SENSE_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
60827   #define NFCT_SUBSCRIBE_SENSE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_SENSE_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
60828   #define NFCT_SUBSCRIBE_SENSE_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
60829   #define NFCT_SUBSCRIBE_SENSE_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
60830 
60831 /* EN @Bit 31 : (unspecified) */
60832   #define NFCT_SUBSCRIBE_SENSE_EN_Pos (31UL)         /*!< Position of EN field.                                                */
60833   #define NFCT_SUBSCRIBE_SENSE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_SENSE_EN_Pos) /*!< Bit mask of EN field.                        */
60834   #define NFCT_SUBSCRIBE_SENSE_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
60835   #define NFCT_SUBSCRIBE_SENSE_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
60836   #define NFCT_SUBSCRIBE_SENSE_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
60837   #define NFCT_SUBSCRIBE_SENSE_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
60838 
60839 
60840 /* NFCT_SUBSCRIBE_STARTTX: Subscribe configuration for task STARTTX */
60841   #define NFCT_SUBSCRIBE_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STARTTX register.                     */
60842 
60843 /* CHIDX @Bits 0..7 : DPPI channel that task STARTTX will subscribe to */
60844   #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
60845   #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
60846   #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
60847   #define NFCT_SUBSCRIBE_STARTTX_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
60848 
60849 /* EN @Bit 31 : (unspecified) */
60850   #define NFCT_SUBSCRIBE_STARTTX_EN_Pos (31UL)       /*!< Position of EN field.                                                */
60851   #define NFCT_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field.                    */
60852   #define NFCT_SUBSCRIBE_STARTTX_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
60853   #define NFCT_SUBSCRIBE_STARTTX_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
60854   #define NFCT_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
60855   #define NFCT_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
60856 
60857 
60858 /* NFCT_SUBSCRIBE_STOPTX: Subscribe configuration for task STOPTX */
60859   #define NFCT_SUBSCRIBE_STOPTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOPTX register.                       */
60860 
60861 /* CHIDX @Bits 0..7 : DPPI channel that task STOPTX will subscribe to */
60862   #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
60863   #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
60864   #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
60865   #define NFCT_SUBSCRIBE_STOPTX_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
60866 
60867 /* EN @Bit 31 : (unspecified) */
60868   #define NFCT_SUBSCRIBE_STOPTX_EN_Pos (31UL)        /*!< Position of EN field.                                                */
60869   #define NFCT_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << NFCT_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field.                      */
60870   #define NFCT_SUBSCRIBE_STOPTX_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
60871   #define NFCT_SUBSCRIBE_STOPTX_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
60872   #define NFCT_SUBSCRIBE_STOPTX_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
60873   #define NFCT_SUBSCRIBE_STOPTX_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
60874 
60875 
60876 /* NFCT_SUBSCRIBE_ENABLERXDATA: Subscribe configuration for task ENABLERXDATA */
60877   #define NFCT_SUBSCRIBE_ENABLERXDATA_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ENABLERXDATA register.           */
60878 
60879 /* CHIDX @Bits 0..7 : DPPI channel that task ENABLERXDATA will subscribe to */
60880   #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
60881   #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
60882   #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                         */
60883   #define NFCT_SUBSCRIBE_ENABLERXDATA_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */
60884 
60885 /* EN @Bit 31 : (unspecified) */
60886   #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos (31UL)  /*!< Position of EN field.                                                */
60887   #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Msk (0x1UL << NFCT_SUBSCRIBE_ENABLERXDATA_EN_Pos) /*!< Bit mask of EN field.          */
60888   #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
60889   #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
60890   #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Disabled (0x0UL) /*!< Disable subscription                                            */
60891   #define NFCT_SUBSCRIBE_ENABLERXDATA_EN_Enabled (0x1UL) /*!< Enable subscription                                              */
60892 
60893 
60894 /* NFCT_SUBSCRIBE_GOIDLE: Subscribe configuration for task GOIDLE */
60895   #define NFCT_SUBSCRIBE_GOIDLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_GOIDLE register.                       */
60896 
60897 /* CHIDX @Bits 0..7 : DPPI channel that task GOIDLE will subscribe to */
60898   #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
60899   #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
60900   #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
60901   #define NFCT_SUBSCRIBE_GOIDLE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
60902 
60903 /* EN @Bit 31 : (unspecified) */
60904   #define NFCT_SUBSCRIBE_GOIDLE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
60905   #define NFCT_SUBSCRIBE_GOIDLE_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOIDLE_EN_Pos) /*!< Bit mask of EN field.                      */
60906   #define NFCT_SUBSCRIBE_GOIDLE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
60907   #define NFCT_SUBSCRIBE_GOIDLE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
60908   #define NFCT_SUBSCRIBE_GOIDLE_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
60909   #define NFCT_SUBSCRIBE_GOIDLE_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
60910 
60911 
60912 /* NFCT_SUBSCRIBE_GOSLEEP: Subscribe configuration for task GOSLEEP */
60913   #define NFCT_SUBSCRIBE_GOSLEEP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_GOSLEEP register.                     */
60914 
60915 /* CHIDX @Bits 0..7 : DPPI channel that task GOSLEEP will subscribe to */
60916   #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
60917   #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Msk (0xFFUL << NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
60918   #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
60919   #define NFCT_SUBSCRIBE_GOSLEEP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
60920 
60921 /* EN @Bit 31 : (unspecified) */
60922   #define NFCT_SUBSCRIBE_GOSLEEP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
60923   #define NFCT_SUBSCRIBE_GOSLEEP_EN_Msk (0x1UL << NFCT_SUBSCRIBE_GOSLEEP_EN_Pos) /*!< Bit mask of EN field.                    */
60924   #define NFCT_SUBSCRIBE_GOSLEEP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
60925   #define NFCT_SUBSCRIBE_GOSLEEP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
60926   #define NFCT_SUBSCRIBE_GOSLEEP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
60927   #define NFCT_SUBSCRIBE_GOSLEEP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
60928 
60929 
60930 /* NFCT_EVENTS_READY: The NFCT peripheral is ready to receive and send frames */
60931   #define NFCT_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                               */
60932 
60933 /* EVENTS_READY @Bit 0 : The NFCT peripheral is ready to receive and send frames */
60934   #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL)   /*!< Position of EVENTS_READY field.                                      */
60935   #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field.*/
60936   #define NFCT_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                          */
60937   #define NFCT_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                          */
60938   #define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                         */
60939   #define NFCT_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                                */
60940 
60941 
60942 /* NFCT_EVENTS_FIELDDETECTED: Remote NFC field detected */
60943   #define NFCT_EVENTS_FIELDDETECTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FIELDDETECTED register.               */
60944 
60945 /* EVENTS_FIELDDETECTED @Bit 0 : Remote NFC field detected */
60946   #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field.                */
60947   #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!<
60948                                                                             Bit mask of EVENTS_FIELDDETECTED field.*/
60949   #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_FIELDDETECTED field.  */
60950   #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_FIELDDETECTED field.  */
60951   #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0x0UL) /*!< Event not generated                         */
60952   #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (0x1UL) /*!< Event generated                                */
60953 
60954 
60955 /* NFCT_EVENTS_FIELDLOST: Remote NFC field lost */
60956   #define NFCT_EVENTS_FIELDLOST_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FIELDLOST register.                       */
60957 
60958 /* EVENTS_FIELDLOST @Bit 0 : Remote NFC field lost */
60959   #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field.                            */
60960   #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of
60961                                                                             EVENTS_FIELDLOST field.*/
60962   #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Min (0x0UL) /*!< Min enumerator value of EVENTS_FIELDLOST field.              */
60963   #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Max (0x1UL) /*!< Max enumerator value of EVENTS_FIELDLOST field.              */
60964   #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0x0UL) /*!< Event not generated                                 */
60965   #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (0x1UL) /*!< Event generated                                        */
60966 
60967 
60968 /* NFCT_EVENTS_TXFRAMESTART: Marks the start of the first symbol of a transmitted frame */
60969   #define NFCT_EVENTS_TXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXFRAMESTART register.                 */
60970 
60971 /* EVENTS_TXFRAMESTART @Bit 0 : Marks the start of the first symbol of a transmitted frame */
60972   #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field.                   */
60973   #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit
60974                                                                             mask of EVENTS_TXFRAMESTART field.*/
60975   #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXFRAMESTART field.     */
60976   #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXFRAMESTART field.     */
60977   #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated                           */
60978   #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (0x1UL) /*!< Event generated                                  */
60979 
60980 
60981 /* NFCT_EVENTS_TXFRAMEEND: Marks the end of the last transmitted on-air symbol of a frame */
60982   #define NFCT_EVENTS_TXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXFRAMEEND register.                     */
60983 
60984 /* EVENTS_TXFRAMEEND @Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */
60985   #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field.                         */
60986   #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of
60987                                                                             EVENTS_TXFRAMEEND field.*/
60988   #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXFRAMEEND field.           */
60989   #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXFRAMEEND field.           */
60990   #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated                               */
60991   #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (0x1UL) /*!< Event generated                                      */
60992 
60993 
60994 /* NFCT_EVENTS_RXFRAMESTART: Marks the end of the first symbol of a received frame */
60995   #define NFCT_EVENTS_RXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXFRAMESTART register.                 */
60996 
60997 /* EVENTS_RXFRAMESTART @Bit 0 : Marks the end of the first symbol of a received frame */
60998   #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field.                   */
60999   #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit
61000                                                                             mask of EVENTS_RXFRAMESTART field.*/
61001   #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXFRAMESTART field.     */
61002   #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXFRAMESTART field.     */
61003   #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0x0UL) /*!< Event not generated                           */
61004   #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (0x1UL) /*!< Event generated                                  */
61005 
61006 
61007 /* NFCT_EVENTS_RXFRAMEEND: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing
61008                             the RX buffer */
61009 
61010   #define NFCT_EVENTS_RXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXFRAMEEND register.                     */
61011 
61012 /* EVENTS_RXFRAMEEND @Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended
61013                               accessing the RX buffer */
61014 
61015   #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field.                         */
61016   #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of
61017                                                                             EVENTS_RXFRAMEEND field.*/
61018   #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXFRAMEEND field.           */
61019   #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXFRAMEEND field.           */
61020   #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0x0UL) /*!< Event not generated                               */
61021   #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (0x1UL) /*!< Event generated                                      */
61022 
61023 
61024 /* NFCT_EVENTS_ERROR: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
61025   #define NFCT_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                               */
61026 
61027 /* EVENTS_ERROR @Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
61028   #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)   /*!< Position of EVENTS_ERROR field.                                      */
61029   #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/
61030   #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field.                          */
61031   #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field.                          */
61032   #define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                         */
61033   #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                */
61034 
61035 
61036 /* NFCT_EVENTS_RXERROR: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
61037   #define NFCT_EVENTS_RXERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXERROR register.                           */
61038 
61039 /* EVENTS_RXERROR @Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
61040                            */
61041 
61042   #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field.                                  */
61043   #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of
61044                                                                             EVENTS_RXERROR field.*/
61045   #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXERROR field.                    */
61046   #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXERROR field.                    */
61047   #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0x0UL) /*!< Event not generated                                     */
61048   #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (0x1UL) /*!< Event generated                                            */
61049 
61050 
61051 /* NFCT_EVENTS_ENDRX: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
61052   #define NFCT_EVENTS_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDRX register.                               */
61053 
61054 /* EVENTS_ENDRX @Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
61055   #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)   /*!< Position of EVENTS_ENDRX field.                                      */
61056   #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field.*/
61057   #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDRX field.                          */
61058   #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDRX field.                          */
61059   #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated                                         */
61060   #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated                                                */
61061 
61062 
61063 /* NFCT_EVENTS_ENDTX: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
61064   #define NFCT_EVENTS_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDTX register.                               */
61065 
61066 /* EVENTS_ENDTX @Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */
61067   #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)   /*!< Position of EVENTS_ENDTX field.                                      */
61068   #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field.*/
61069   #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDTX field.                          */
61070   #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDTX field.                          */
61071   #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated                                         */
61072   #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated                                                */
61073 
61074 
61075 /* NFCT_EVENTS_AUTOCOLRESSTARTED: Auto collision resolution process has started */
61076   #define NFCT_EVENTS_AUTOCOLRESSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_AUTOCOLRESSTARTED register.       */
61077 
61078 /* EVENTS_AUTOCOLRESSTARTED @Bit 0 : Auto collision resolution process has started */
61079   #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field.    */
61080   #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos)
61081                                                                             /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field.*/
61082   #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of
61083                                                                             EVENTS_AUTOCOLRESSTARTED field.*/
61084   #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of
61085                                                                             EVENTS_AUTOCOLRESSTARTED field.*/
61086   #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0x0UL) /*!< Event not generated                 */
61087   #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (0x1UL) /*!< Event generated                        */
61088 
61089 
61090 /* NFCT_EVENTS_COLLISION: NFC auto collision resolution error reported. */
61091   #define NFCT_EVENTS_COLLISION_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COLLISION register.                       */
61092 
61093 /* EVENTS_COLLISION @Bit 0 : NFC auto collision resolution error reported. */
61094   #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field.                            */
61095   #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of
61096                                                                             EVENTS_COLLISION field.*/
61097   #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Min (0x0UL) /*!< Min enumerator value of EVENTS_COLLISION field.              */
61098   #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Max (0x1UL) /*!< Max enumerator value of EVENTS_COLLISION field.              */
61099   #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0x0UL) /*!< Event not generated                                 */
61100   #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (0x1UL) /*!< Event generated                                        */
61101 
61102 
61103 /* NFCT_EVENTS_SELECTED: NFC auto collision resolution successfully completed */
61104   #define NFCT_EVENTS_SELECTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SELECTED register.                         */
61105 
61106 /* EVENTS_SELECTED @Bit 0 : NFC auto collision resolution successfully completed */
61107   #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field.                               */
61108   #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of
61109                                                                             EVENTS_SELECTED field.*/
61110   #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SELECTED field.                 */
61111   #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SELECTED field.                 */
61112   #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0x0UL) /*!< Event not generated                                   */
61113   #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (0x1UL) /*!< Event generated                                          */
61114 
61115 
61116 /* NFCT_EVENTS_STARTED: EasyDMA is ready to receive or send frames. */
61117   #define NFCT_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                           */
61118 
61119 /* EVENTS_STARTED @Bit 0 : EasyDMA is ready to receive or send frames. */
61120   #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                  */
61121   #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of
61122                                                                             EVENTS_STARTED field.*/
61123   #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                    */
61124   #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                    */
61125   #define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                     */
61126   #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                            */
61127 
61128 
61129 /* NFCT_PUBLISH_READY: Publish configuration for event READY */
61130   #define NFCT_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register.                             */
61131 
61132 /* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
61133   #define NFCT_PUBLISH_READY_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
61134   #define NFCT_PUBLISH_READY_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
61135   #define NFCT_PUBLISH_READY_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
61136   #define NFCT_PUBLISH_READY_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
61137 
61138 /* EN @Bit 31 : (unspecified) */
61139   #define NFCT_PUBLISH_READY_EN_Pos (31UL)           /*!< Position of EN field.                                                */
61140   #define NFCT_PUBLISH_READY_EN_Msk (0x1UL << NFCT_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field.                            */
61141   #define NFCT_PUBLISH_READY_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
61142   #define NFCT_PUBLISH_READY_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
61143   #define NFCT_PUBLISH_READY_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
61144   #define NFCT_PUBLISH_READY_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
61145 
61146 
61147 /* NFCT_PUBLISH_FIELDDETECTED: Publish configuration for event FIELDDETECTED */
61148   #define NFCT_PUBLISH_FIELDDETECTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FIELDDETECTED register.             */
61149 
61150 /* CHIDX @Bits 0..7 : DPPI channel that event FIELDDETECTED will publish to */
61151   #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                             */
61152   #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDDETECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.  */
61153   #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                          */
61154   #define NFCT_PUBLISH_FIELDDETECTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                          */
61155 
61156 /* EN @Bit 31 : (unspecified) */
61157   #define NFCT_PUBLISH_FIELDDETECTED_EN_Pos (31UL)   /*!< Position of EN field.                                                */
61158   #define NFCT_PUBLISH_FIELDDETECTED_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDDETECTED_EN_Pos) /*!< Bit mask of EN field.            */
61159   #define NFCT_PUBLISH_FIELDDETECTED_EN_Min (0x0UL)  /*!< Min enumerator value of EN field.                                    */
61160   #define NFCT_PUBLISH_FIELDDETECTED_EN_Max (0x1UL)  /*!< Max enumerator value of EN field.                                    */
61161   #define NFCT_PUBLISH_FIELDDETECTED_EN_Disabled (0x0UL) /*!< Disable publishing                                               */
61162   #define NFCT_PUBLISH_FIELDDETECTED_EN_Enabled (0x1UL) /*!< Enable publishing                                                 */
61163 
61164 
61165 /* NFCT_PUBLISH_FIELDLOST: Publish configuration for event FIELDLOST */
61166   #define NFCT_PUBLISH_FIELDLOST_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FIELDLOST register.                     */
61167 
61168 /* CHIDX @Bits 0..7 : DPPI channel that event FIELDLOST will publish to */
61169   #define NFCT_PUBLISH_FIELDLOST_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
61170   #define NFCT_PUBLISH_FIELDLOST_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_FIELDLOST_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
61171   #define NFCT_PUBLISH_FIELDLOST_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
61172   #define NFCT_PUBLISH_FIELDLOST_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
61173 
61174 /* EN @Bit 31 : (unspecified) */
61175   #define NFCT_PUBLISH_FIELDLOST_EN_Pos (31UL)       /*!< Position of EN field.                                                */
61176   #define NFCT_PUBLISH_FIELDLOST_EN_Msk (0x1UL << NFCT_PUBLISH_FIELDLOST_EN_Pos) /*!< Bit mask of EN field.                    */
61177   #define NFCT_PUBLISH_FIELDLOST_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
61178   #define NFCT_PUBLISH_FIELDLOST_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
61179   #define NFCT_PUBLISH_FIELDLOST_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
61180   #define NFCT_PUBLISH_FIELDLOST_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
61181 
61182 
61183 /* NFCT_PUBLISH_TXFRAMESTART: Publish configuration for event TXFRAMESTART */
61184   #define NFCT_PUBLISH_TXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXFRAMESTART register.               */
61185 
61186 /* CHIDX @Bits 0..7 : DPPI channel that event TXFRAMESTART will publish to */
61187   #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
61188   #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
61189   #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                           */
61190   #define NFCT_PUBLISH_TXFRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */
61191 
61192 /* EN @Bit 31 : (unspecified) */
61193   #define NFCT_PUBLISH_TXFRAMESTART_EN_Pos (31UL)    /*!< Position of EN field.                                                */
61194   #define NFCT_PUBLISH_TXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMESTART_EN_Pos) /*!< Bit mask of EN field.              */
61195   #define NFCT_PUBLISH_TXFRAMESTART_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
61196   #define NFCT_PUBLISH_TXFRAMESTART_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
61197   #define NFCT_PUBLISH_TXFRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
61198   #define NFCT_PUBLISH_TXFRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */
61199 
61200 
61201 /* NFCT_PUBLISH_TXFRAMEEND: Publish configuration for event TXFRAMEEND */
61202   #define NFCT_PUBLISH_TXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXFRAMEEND register.                   */
61203 
61204 /* CHIDX @Bits 0..7 : DPPI channel that event TXFRAMEEND will publish to */
61205   #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
61206   #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_TXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
61207   #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
61208   #define NFCT_PUBLISH_TXFRAMEEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
61209 
61210 /* EN @Bit 31 : (unspecified) */
61211   #define NFCT_PUBLISH_TXFRAMEEND_EN_Pos (31UL)      /*!< Position of EN field.                                                */
61212   #define NFCT_PUBLISH_TXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_TXFRAMEEND_EN_Pos) /*!< Bit mask of EN field.                  */
61213   #define NFCT_PUBLISH_TXFRAMEEND_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
61214   #define NFCT_PUBLISH_TXFRAMEEND_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
61215   #define NFCT_PUBLISH_TXFRAMEEND_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
61216   #define NFCT_PUBLISH_TXFRAMEEND_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
61217 
61218 
61219 /* NFCT_PUBLISH_RXFRAMESTART: Publish configuration for event RXFRAMESTART */
61220   #define NFCT_PUBLISH_RXFRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXFRAMESTART register.               */
61221 
61222 /* CHIDX @Bits 0..7 : DPPI channel that event RXFRAMESTART will publish to */
61223   #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
61224   #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
61225   #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                           */
61226   #define NFCT_PUBLISH_RXFRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */
61227 
61228 /* EN @Bit 31 : (unspecified) */
61229   #define NFCT_PUBLISH_RXFRAMESTART_EN_Pos (31UL)    /*!< Position of EN field.                                                */
61230   #define NFCT_PUBLISH_RXFRAMESTART_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMESTART_EN_Pos) /*!< Bit mask of EN field.              */
61231   #define NFCT_PUBLISH_RXFRAMESTART_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
61232   #define NFCT_PUBLISH_RXFRAMESTART_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
61233   #define NFCT_PUBLISH_RXFRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing                                                */
61234   #define NFCT_PUBLISH_RXFRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing                                                  */
61235 
61236 
61237 /* NFCT_PUBLISH_RXFRAMEEND: Publish configuration for event RXFRAMEEND */
61238   #define NFCT_PUBLISH_RXFRAMEEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXFRAMEEND register.                   */
61239 
61240 /* CHIDX @Bits 0..7 : DPPI channel that event RXFRAMEEND will publish to */
61241   #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
61242   #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXFRAMEEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
61243   #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
61244   #define NFCT_PUBLISH_RXFRAMEEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
61245 
61246 /* EN @Bit 31 : (unspecified) */
61247   #define NFCT_PUBLISH_RXFRAMEEND_EN_Pos (31UL)      /*!< Position of EN field.                                                */
61248   #define NFCT_PUBLISH_RXFRAMEEND_EN_Msk (0x1UL << NFCT_PUBLISH_RXFRAMEEND_EN_Pos) /*!< Bit mask of EN field.                  */
61249   #define NFCT_PUBLISH_RXFRAMEEND_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
61250   #define NFCT_PUBLISH_RXFRAMEEND_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
61251   #define NFCT_PUBLISH_RXFRAMEEND_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
61252   #define NFCT_PUBLISH_RXFRAMEEND_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
61253 
61254 
61255 /* NFCT_PUBLISH_ERROR: Publish configuration for event ERROR */
61256   #define NFCT_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                             */
61257 
61258 /* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
61259   #define NFCT_PUBLISH_ERROR_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
61260   #define NFCT_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
61261   #define NFCT_PUBLISH_ERROR_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
61262   #define NFCT_PUBLISH_ERROR_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
61263 
61264 /* EN @Bit 31 : (unspecified) */
61265   #define NFCT_PUBLISH_ERROR_EN_Pos (31UL)           /*!< Position of EN field.                                                */
61266   #define NFCT_PUBLISH_ERROR_EN_Msk (0x1UL << NFCT_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                            */
61267   #define NFCT_PUBLISH_ERROR_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
61268   #define NFCT_PUBLISH_ERROR_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
61269   #define NFCT_PUBLISH_ERROR_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
61270   #define NFCT_PUBLISH_ERROR_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
61271 
61272 
61273 /* NFCT_PUBLISH_RXERROR: Publish configuration for event RXERROR */
61274   #define NFCT_PUBLISH_RXERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXERROR register.                         */
61275 
61276 /* CHIDX @Bits 0..7 : DPPI channel that event RXERROR will publish to */
61277   #define NFCT_PUBLISH_RXERROR_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
61278   #define NFCT_PUBLISH_RXERROR_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_RXERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
61279   #define NFCT_PUBLISH_RXERROR_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
61280   #define NFCT_PUBLISH_RXERROR_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
61281 
61282 /* EN @Bit 31 : (unspecified) */
61283   #define NFCT_PUBLISH_RXERROR_EN_Pos (31UL)         /*!< Position of EN field.                                                */
61284   #define NFCT_PUBLISH_RXERROR_EN_Msk (0x1UL << NFCT_PUBLISH_RXERROR_EN_Pos) /*!< Bit mask of EN field.                        */
61285   #define NFCT_PUBLISH_RXERROR_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
61286   #define NFCT_PUBLISH_RXERROR_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
61287   #define NFCT_PUBLISH_RXERROR_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
61288   #define NFCT_PUBLISH_RXERROR_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
61289 
61290 
61291 /* NFCT_PUBLISH_ENDRX: Publish configuration for event ENDRX */
61292   #define NFCT_PUBLISH_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDRX register.                             */
61293 
61294 /* CHIDX @Bits 0..7 : DPPI channel that event ENDRX will publish to */
61295   #define NFCT_PUBLISH_ENDRX_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
61296   #define NFCT_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
61297   #define NFCT_PUBLISH_ENDRX_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
61298   #define NFCT_PUBLISH_ENDRX_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
61299 
61300 /* EN @Bit 31 : (unspecified) */
61301   #define NFCT_PUBLISH_ENDRX_EN_Pos (31UL)           /*!< Position of EN field.                                                */
61302   #define NFCT_PUBLISH_ENDRX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field.                            */
61303   #define NFCT_PUBLISH_ENDRX_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
61304   #define NFCT_PUBLISH_ENDRX_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
61305   #define NFCT_PUBLISH_ENDRX_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
61306   #define NFCT_PUBLISH_ENDRX_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
61307 
61308 
61309 /* NFCT_PUBLISH_ENDTX: Publish configuration for event ENDTX */
61310   #define NFCT_PUBLISH_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDTX register.                             */
61311 
61312 /* CHIDX @Bits 0..7 : DPPI channel that event ENDTX will publish to */
61313   #define NFCT_PUBLISH_ENDTX_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
61314   #define NFCT_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
61315   #define NFCT_PUBLISH_ENDTX_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
61316   #define NFCT_PUBLISH_ENDTX_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
61317 
61318 /* EN @Bit 31 : (unspecified) */
61319   #define NFCT_PUBLISH_ENDTX_EN_Pos (31UL)           /*!< Position of EN field.                                                */
61320   #define NFCT_PUBLISH_ENDTX_EN_Msk (0x1UL << NFCT_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field.                            */
61321   #define NFCT_PUBLISH_ENDTX_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
61322   #define NFCT_PUBLISH_ENDTX_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
61323   #define NFCT_PUBLISH_ENDTX_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
61324   #define NFCT_PUBLISH_ENDTX_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
61325 
61326 
61327 /* NFCT_PUBLISH_AUTOCOLRESSTARTED: Publish configuration for event AUTOCOLRESSTARTED */
61328   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_AUTOCOLRESSTARTED register.     */
61329 
61330 /* CHIDX @Bits 0..7 : DPPI channel that event AUTOCOLRESSTARTED will publish to */
61331   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                         */
61332   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX
61333                                                                             field.*/
61334   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                      */
61335   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                      */
61336 
61337 /* EN @Bit 31 : (unspecified) */
61338   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos (31UL) /*!< Position of EN field.                                              */
61339   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Msk (0x1UL << NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Pos) /*!< Bit mask of EN field.    */
61340   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                 */
61341   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                 */
61342   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                           */
61343   #define NFCT_PUBLISH_AUTOCOLRESSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing                                             */
61344 
61345 
61346 /* NFCT_PUBLISH_COLLISION: Publish configuration for event COLLISION */
61347   #define NFCT_PUBLISH_COLLISION_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COLLISION register.                     */
61348 
61349 /* CHIDX @Bits 0..7 : DPPI channel that event COLLISION will publish to */
61350   #define NFCT_PUBLISH_COLLISION_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
61351   #define NFCT_PUBLISH_COLLISION_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_COLLISION_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
61352   #define NFCT_PUBLISH_COLLISION_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
61353   #define NFCT_PUBLISH_COLLISION_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
61354 
61355 /* EN @Bit 31 : (unspecified) */
61356   #define NFCT_PUBLISH_COLLISION_EN_Pos (31UL)       /*!< Position of EN field.                                                */
61357   #define NFCT_PUBLISH_COLLISION_EN_Msk (0x1UL << NFCT_PUBLISH_COLLISION_EN_Pos) /*!< Bit mask of EN field.                    */
61358   #define NFCT_PUBLISH_COLLISION_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
61359   #define NFCT_PUBLISH_COLLISION_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
61360   #define NFCT_PUBLISH_COLLISION_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
61361   #define NFCT_PUBLISH_COLLISION_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
61362 
61363 
61364 /* NFCT_PUBLISH_SELECTED: Publish configuration for event SELECTED */
61365   #define NFCT_PUBLISH_SELECTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SELECTED register.                       */
61366 
61367 /* CHIDX @Bits 0..7 : DPPI channel that event SELECTED will publish to */
61368   #define NFCT_PUBLISH_SELECTED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
61369   #define NFCT_PUBLISH_SELECTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_SELECTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
61370   #define NFCT_PUBLISH_SELECTED_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
61371   #define NFCT_PUBLISH_SELECTED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
61372 
61373 /* EN @Bit 31 : (unspecified) */
61374   #define NFCT_PUBLISH_SELECTED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
61375   #define NFCT_PUBLISH_SELECTED_EN_Msk (0x1UL << NFCT_PUBLISH_SELECTED_EN_Pos) /*!< Bit mask of EN field.                      */
61376   #define NFCT_PUBLISH_SELECTED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
61377   #define NFCT_PUBLISH_SELECTED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
61378   #define NFCT_PUBLISH_SELECTED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
61379   #define NFCT_PUBLISH_SELECTED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
61380 
61381 
61382 /* NFCT_PUBLISH_STARTED: Publish configuration for event STARTED */
61383   #define NFCT_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                         */
61384 
61385 /* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
61386   #define NFCT_PUBLISH_STARTED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
61387   #define NFCT_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << NFCT_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
61388   #define NFCT_PUBLISH_STARTED_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
61389   #define NFCT_PUBLISH_STARTED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
61390 
61391 /* EN @Bit 31 : (unspecified) */
61392   #define NFCT_PUBLISH_STARTED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
61393   #define NFCT_PUBLISH_STARTED_EN_Msk (0x1UL << NFCT_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                        */
61394   #define NFCT_PUBLISH_STARTED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
61395   #define NFCT_PUBLISH_STARTED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
61396   #define NFCT_PUBLISH_STARTED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
61397   #define NFCT_PUBLISH_STARTED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
61398 
61399 
61400 /* NFCT_SHORTS: Shortcuts between local events and tasks */
61401   #define NFCT_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */
61402 
61403 /* FIELDDETECTED_ACTIVATE @Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */
61404   #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field.                          */
61405   #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of
61406                                                                             FIELDDETECTED_ACTIVATE field.*/
61407   #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Min (0x0UL) /*!< Min enumerator value of FIELDDETECTED_ACTIVATE field.            */
61408   #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Max (0x1UL) /*!< Max enumerator value of FIELDDETECTED_ACTIVATE field.            */
61409   #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0x0UL) /*!< Disable shortcut                                            */
61410   #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (0x1UL) /*!< Enable shortcut                                              */
61411 
61412 /* FIELDLOST_SENSE @Bit 1 : Shortcut between event FIELDLOST and task SENSE */
61413   #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL)      /*!< Position of FIELDLOST_SENSE field.                                   */
61414   #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field.   */
61415   #define NFCT_SHORTS_FIELDLOST_SENSE_Min (0x0UL)    /*!< Min enumerator value of FIELDLOST_SENSE field.                       */
61416   #define NFCT_SHORTS_FIELDLOST_SENSE_Max (0x1UL)    /*!< Max enumerator value of FIELDLOST_SENSE field.                       */
61417   #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0x0UL) /*!< Disable shortcut                                                   */
61418   #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (0x1UL) /*!< Enable shortcut                                                     */
61419 
61420 /* TXFRAMEEND_ENABLERXDATA @Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */
61421   #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field.                        */
61422   #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of
61423                                                                             TXFRAMEEND_ENABLERXDATA field.*/
61424   #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Min (0x0UL) /*!< Min enumerator value of TXFRAMEEND_ENABLERXDATA field.          */
61425   #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Max (0x1UL) /*!< Max enumerator value of TXFRAMEEND_ENABLERXDATA field.          */
61426   #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0x0UL) /*!< Disable shortcut                                           */
61427   #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (0x1UL) /*!< Enable shortcut                                             */
61428 
61429 
61430 /* NFCT_INTEN: Enable or disable interrupt */
61431   #define NFCT_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */
61432 
61433 /* READY @Bit 0 : Enable or disable interrupt for event READY */
61434   #define NFCT_INTEN_READY_Pos (0UL)                 /*!< Position of READY field.                                             */
61435   #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field.                                   */
61436   #define NFCT_INTEN_READY_Min (0x0UL)               /*!< Min enumerator value of READY field.                                 */
61437   #define NFCT_INTEN_READY_Max (0x1UL)               /*!< Max enumerator value of READY field.                                 */
61438   #define NFCT_INTEN_READY_Disabled (0x0UL)          /*!< Disable                                                              */
61439   #define NFCT_INTEN_READY_Enabled (0x1UL)           /*!< Enable                                                               */
61440 
61441 /* FIELDDETECTED @Bit 1 : Enable or disable interrupt for event FIELDDETECTED */
61442   #define NFCT_INTEN_FIELDDETECTED_Pos (1UL)         /*!< Position of FIELDDETECTED field.                                     */
61443   #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field.           */
61444   #define NFCT_INTEN_FIELDDETECTED_Min (0x0UL)       /*!< Min enumerator value of FIELDDETECTED field.                         */
61445   #define NFCT_INTEN_FIELDDETECTED_Max (0x1UL)       /*!< Max enumerator value of FIELDDETECTED field.                         */
61446   #define NFCT_INTEN_FIELDDETECTED_Disabled (0x0UL)  /*!< Disable                                                              */
61447   #define NFCT_INTEN_FIELDDETECTED_Enabled (0x1UL)   /*!< Enable                                                               */
61448 
61449 /* FIELDLOST @Bit 2 : Enable or disable interrupt for event FIELDLOST */
61450   #define NFCT_INTEN_FIELDLOST_Pos (2UL)             /*!< Position of FIELDLOST field.                                         */
61451   #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field.                       */
61452   #define NFCT_INTEN_FIELDLOST_Min (0x0UL)           /*!< Min enumerator value of FIELDLOST field.                             */
61453   #define NFCT_INTEN_FIELDLOST_Max (0x1UL)           /*!< Max enumerator value of FIELDLOST field.                             */
61454   #define NFCT_INTEN_FIELDLOST_Disabled (0x0UL)      /*!< Disable                                                              */
61455   #define NFCT_INTEN_FIELDLOST_Enabled (0x1UL)       /*!< Enable                                                               */
61456 
61457 /* TXFRAMESTART @Bit 3 : Enable or disable interrupt for event TXFRAMESTART */
61458   #define NFCT_INTEN_TXFRAMESTART_Pos (3UL)          /*!< Position of TXFRAMESTART field.                                      */
61459   #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field.              */
61460   #define NFCT_INTEN_TXFRAMESTART_Min (0x0UL)        /*!< Min enumerator value of TXFRAMESTART field.                          */
61461   #define NFCT_INTEN_TXFRAMESTART_Max (0x1UL)        /*!< Max enumerator value of TXFRAMESTART field.                          */
61462   #define NFCT_INTEN_TXFRAMESTART_Disabled (0x0UL)   /*!< Disable                                                              */
61463   #define NFCT_INTEN_TXFRAMESTART_Enabled (0x1UL)    /*!< Enable                                                               */
61464 
61465 /* TXFRAMEEND @Bit 4 : Enable or disable interrupt for event TXFRAMEEND */
61466   #define NFCT_INTEN_TXFRAMEEND_Pos (4UL)            /*!< Position of TXFRAMEEND field.                                        */
61467   #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field.                    */
61468   #define NFCT_INTEN_TXFRAMEEND_Min (0x0UL)          /*!< Min enumerator value of TXFRAMEEND field.                            */
61469   #define NFCT_INTEN_TXFRAMEEND_Max (0x1UL)          /*!< Max enumerator value of TXFRAMEEND field.                            */
61470   #define NFCT_INTEN_TXFRAMEEND_Disabled (0x0UL)     /*!< Disable                                                              */
61471   #define NFCT_INTEN_TXFRAMEEND_Enabled (0x1UL)      /*!< Enable                                                               */
61472 
61473 /* RXFRAMESTART @Bit 5 : Enable or disable interrupt for event RXFRAMESTART */
61474   #define NFCT_INTEN_RXFRAMESTART_Pos (5UL)          /*!< Position of RXFRAMESTART field.                                      */
61475   #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field.              */
61476   #define NFCT_INTEN_RXFRAMESTART_Min (0x0UL)        /*!< Min enumerator value of RXFRAMESTART field.                          */
61477   #define NFCT_INTEN_RXFRAMESTART_Max (0x1UL)        /*!< Max enumerator value of RXFRAMESTART field.                          */
61478   #define NFCT_INTEN_RXFRAMESTART_Disabled (0x0UL)   /*!< Disable                                                              */
61479   #define NFCT_INTEN_RXFRAMESTART_Enabled (0x1UL)    /*!< Enable                                                               */
61480 
61481 /* RXFRAMEEND @Bit 6 : Enable or disable interrupt for event RXFRAMEEND */
61482   #define NFCT_INTEN_RXFRAMEEND_Pos (6UL)            /*!< Position of RXFRAMEEND field.                                        */
61483   #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field.                    */
61484   #define NFCT_INTEN_RXFRAMEEND_Min (0x0UL)          /*!< Min enumerator value of RXFRAMEEND field.                            */
61485   #define NFCT_INTEN_RXFRAMEEND_Max (0x1UL)          /*!< Max enumerator value of RXFRAMEEND field.                            */
61486   #define NFCT_INTEN_RXFRAMEEND_Disabled (0x0UL)     /*!< Disable                                                              */
61487   #define NFCT_INTEN_RXFRAMEEND_Enabled (0x1UL)      /*!< Enable                                                               */
61488 
61489 /* ERROR @Bit 7 : Enable or disable interrupt for event ERROR */
61490   #define NFCT_INTEN_ERROR_Pos (7UL)                 /*!< Position of ERROR field.                                             */
61491   #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field.                                   */
61492   #define NFCT_INTEN_ERROR_Min (0x0UL)               /*!< Min enumerator value of ERROR field.                                 */
61493   #define NFCT_INTEN_ERROR_Max (0x1UL)               /*!< Max enumerator value of ERROR field.                                 */
61494   #define NFCT_INTEN_ERROR_Disabled (0x0UL)          /*!< Disable                                                              */
61495   #define NFCT_INTEN_ERROR_Enabled (0x1UL)           /*!< Enable                                                               */
61496 
61497 /* RXERROR @Bit 10 : Enable or disable interrupt for event RXERROR */
61498   #define NFCT_INTEN_RXERROR_Pos (10UL)              /*!< Position of RXERROR field.                                           */
61499   #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field.                             */
61500   #define NFCT_INTEN_RXERROR_Min (0x0UL)             /*!< Min enumerator value of RXERROR field.                               */
61501   #define NFCT_INTEN_RXERROR_Max (0x1UL)             /*!< Max enumerator value of RXERROR field.                               */
61502   #define NFCT_INTEN_RXERROR_Disabled (0x0UL)        /*!< Disable                                                              */
61503   #define NFCT_INTEN_RXERROR_Enabled (0x1UL)         /*!< Enable                                                               */
61504 
61505 /* ENDRX @Bit 11 : Enable or disable interrupt for event ENDRX */
61506   #define NFCT_INTEN_ENDRX_Pos (11UL)                /*!< Position of ENDRX field.                                             */
61507   #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field.                                   */
61508   #define NFCT_INTEN_ENDRX_Min (0x0UL)               /*!< Min enumerator value of ENDRX field.                                 */
61509   #define NFCT_INTEN_ENDRX_Max (0x1UL)               /*!< Max enumerator value of ENDRX field.                                 */
61510   #define NFCT_INTEN_ENDRX_Disabled (0x0UL)          /*!< Disable                                                              */
61511   #define NFCT_INTEN_ENDRX_Enabled (0x1UL)           /*!< Enable                                                               */
61512 
61513 /* ENDTX @Bit 12 : Enable or disable interrupt for event ENDTX */
61514   #define NFCT_INTEN_ENDTX_Pos (12UL)                /*!< Position of ENDTX field.                                             */
61515   #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field.                                   */
61516   #define NFCT_INTEN_ENDTX_Min (0x0UL)               /*!< Min enumerator value of ENDTX field.                                 */
61517   #define NFCT_INTEN_ENDTX_Max (0x1UL)               /*!< Max enumerator value of ENDTX field.                                 */
61518   #define NFCT_INTEN_ENDTX_Disabled (0x0UL)          /*!< Disable                                                              */
61519   #define NFCT_INTEN_ENDTX_Enabled (0x1UL)           /*!< Enable                                                               */
61520 
61521 /* AUTOCOLRESSTARTED @Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */
61522   #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL)    /*!< Position of AUTOCOLRESSTARTED field.                                 */
61523   #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED
61524                                                                             field.*/
61525   #define NFCT_INTEN_AUTOCOLRESSTARTED_Min (0x0UL)   /*!< Min enumerator value of AUTOCOLRESSTARTED field.                     */
61526   #define NFCT_INTEN_AUTOCOLRESSTARTED_Max (0x1UL)   /*!< Max enumerator value of AUTOCOLRESSTARTED field.                     */
61527   #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Disable                                                           */
61528   #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Enable                                                             */
61529 
61530 /* COLLISION @Bit 18 : Enable or disable interrupt for event COLLISION */
61531   #define NFCT_INTEN_COLLISION_Pos (18UL)            /*!< Position of COLLISION field.                                         */
61532   #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field.                       */
61533   #define NFCT_INTEN_COLLISION_Min (0x0UL)           /*!< Min enumerator value of COLLISION field.                             */
61534   #define NFCT_INTEN_COLLISION_Max (0x1UL)           /*!< Max enumerator value of COLLISION field.                             */
61535   #define NFCT_INTEN_COLLISION_Disabled (0x0UL)      /*!< Disable                                                              */
61536   #define NFCT_INTEN_COLLISION_Enabled (0x1UL)       /*!< Enable                                                               */
61537 
61538 /* SELECTED @Bit 19 : Enable or disable interrupt for event SELECTED */
61539   #define NFCT_INTEN_SELECTED_Pos (19UL)             /*!< Position of SELECTED field.                                          */
61540   #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field.                          */
61541   #define NFCT_INTEN_SELECTED_Min (0x0UL)            /*!< Min enumerator value of SELECTED field.                              */
61542   #define NFCT_INTEN_SELECTED_Max (0x1UL)            /*!< Max enumerator value of SELECTED field.                              */
61543   #define NFCT_INTEN_SELECTED_Disabled (0x0UL)       /*!< Disable                                                              */
61544   #define NFCT_INTEN_SELECTED_Enabled (0x1UL)        /*!< Enable                                                               */
61545 
61546 /* STARTED @Bit 20 : Enable or disable interrupt for event STARTED */
61547   #define NFCT_INTEN_STARTED_Pos (20UL)              /*!< Position of STARTED field.                                           */
61548   #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field.                             */
61549   #define NFCT_INTEN_STARTED_Min (0x0UL)             /*!< Min enumerator value of STARTED field.                               */
61550   #define NFCT_INTEN_STARTED_Max (0x1UL)             /*!< Max enumerator value of STARTED field.                               */
61551   #define NFCT_INTEN_STARTED_Disabled (0x0UL)        /*!< Disable                                                              */
61552   #define NFCT_INTEN_STARTED_Enabled (0x1UL)         /*!< Enable                                                               */
61553 
61554 
61555 /* NFCT_INTENSET: Enable interrupt */
61556   #define NFCT_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */
61557 
61558 /* READY @Bit 0 : Write '1' to enable interrupt for event READY */
61559   #define NFCT_INTENSET_READY_Pos (0UL)              /*!< Position of READY field.                                             */
61560   #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field.                             */
61561   #define NFCT_INTENSET_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
61562   #define NFCT_INTENSET_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
61563   #define NFCT_INTENSET_READY_Set (0x1UL)            /*!< Enable                                                               */
61564   #define NFCT_INTENSET_READY_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
61565   #define NFCT_INTENSET_READY_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
61566 
61567 /* FIELDDETECTED @Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */
61568   #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL)      /*!< Position of FIELDDETECTED field.                                     */
61569   #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field.     */
61570   #define NFCT_INTENSET_FIELDDETECTED_Min (0x0UL)    /*!< Min enumerator value of FIELDDETECTED field.                         */
61571   #define NFCT_INTENSET_FIELDDETECTED_Max (0x1UL)    /*!< Max enumerator value of FIELDDETECTED field.                         */
61572   #define NFCT_INTENSET_FIELDDETECTED_Set (0x1UL)    /*!< Enable                                                               */
61573   #define NFCT_INTENSET_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
61574   #define NFCT_INTENSET_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled                                                       */
61575 
61576 /* FIELDLOST @Bit 2 : Write '1' to enable interrupt for event FIELDLOST */
61577   #define NFCT_INTENSET_FIELDLOST_Pos (2UL)          /*!< Position of FIELDLOST field.                                         */
61578   #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field.                 */
61579   #define NFCT_INTENSET_FIELDLOST_Min (0x0UL)        /*!< Min enumerator value of FIELDLOST field.                             */
61580   #define NFCT_INTENSET_FIELDLOST_Max (0x1UL)        /*!< Max enumerator value of FIELDLOST field.                             */
61581   #define NFCT_INTENSET_FIELDLOST_Set (0x1UL)        /*!< Enable                                                               */
61582   #define NFCT_INTENSET_FIELDLOST_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
61583   #define NFCT_INTENSET_FIELDLOST_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
61584 
61585 /* TXFRAMESTART @Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */
61586   #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL)       /*!< Position of TXFRAMESTART field.                                      */
61587   #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field.        */
61588   #define NFCT_INTENSET_TXFRAMESTART_Min (0x0UL)     /*!< Min enumerator value of TXFRAMESTART field.                          */
61589   #define NFCT_INTENSET_TXFRAMESTART_Max (0x1UL)     /*!< Max enumerator value of TXFRAMESTART field.                          */
61590   #define NFCT_INTENSET_TXFRAMESTART_Set (0x1UL)     /*!< Enable                                                               */
61591   #define NFCT_INTENSET_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                      */
61592   #define NFCT_INTENSET_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                        */
61593 
61594 /* TXFRAMEEND @Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */
61595   #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL)         /*!< Position of TXFRAMEEND field.                                        */
61596   #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field.              */
61597   #define NFCT_INTENSET_TXFRAMEEND_Min (0x0UL)       /*!< Min enumerator value of TXFRAMEEND field.                            */
61598   #define NFCT_INTENSET_TXFRAMEEND_Max (0x1UL)       /*!< Max enumerator value of TXFRAMEEND field.                            */
61599   #define NFCT_INTENSET_TXFRAMEEND_Set (0x1UL)       /*!< Enable                                                               */
61600   #define NFCT_INTENSET_TXFRAMEEND_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
61601   #define NFCT_INTENSET_TXFRAMEEND_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
61602 
61603 /* RXFRAMESTART @Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */
61604   #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL)       /*!< Position of RXFRAMESTART field.                                      */
61605   #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field.        */
61606   #define NFCT_INTENSET_RXFRAMESTART_Min (0x0UL)     /*!< Min enumerator value of RXFRAMESTART field.                          */
61607   #define NFCT_INTENSET_RXFRAMESTART_Max (0x1UL)     /*!< Max enumerator value of RXFRAMESTART field.                          */
61608   #define NFCT_INTENSET_RXFRAMESTART_Set (0x1UL)     /*!< Enable                                                               */
61609   #define NFCT_INTENSET_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                      */
61610   #define NFCT_INTENSET_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                        */
61611 
61612 /* RXFRAMEEND @Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */
61613   #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL)         /*!< Position of RXFRAMEEND field.                                        */
61614   #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field.              */
61615   #define NFCT_INTENSET_RXFRAMEEND_Min (0x0UL)       /*!< Min enumerator value of RXFRAMEEND field.                            */
61616   #define NFCT_INTENSET_RXFRAMEEND_Max (0x1UL)       /*!< Max enumerator value of RXFRAMEEND field.                            */
61617   #define NFCT_INTENSET_RXFRAMEEND_Set (0x1UL)       /*!< Enable                                                               */
61618   #define NFCT_INTENSET_RXFRAMEEND_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
61619   #define NFCT_INTENSET_RXFRAMEEND_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
61620 
61621 /* ERROR @Bit 7 : Write '1' to enable interrupt for event ERROR */
61622   #define NFCT_INTENSET_ERROR_Pos (7UL)              /*!< Position of ERROR field.                                             */
61623   #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
61624   #define NFCT_INTENSET_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
61625   #define NFCT_INTENSET_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
61626   #define NFCT_INTENSET_ERROR_Set (0x1UL)            /*!< Enable                                                               */
61627   #define NFCT_INTENSET_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
61628   #define NFCT_INTENSET_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
61629 
61630 /* RXERROR @Bit 10 : Write '1' to enable interrupt for event RXERROR */
61631   #define NFCT_INTENSET_RXERROR_Pos (10UL)           /*!< Position of RXERROR field.                                           */
61632   #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field.                       */
61633   #define NFCT_INTENSET_RXERROR_Min (0x0UL)          /*!< Min enumerator value of RXERROR field.                               */
61634   #define NFCT_INTENSET_RXERROR_Max (0x1UL)          /*!< Max enumerator value of RXERROR field.                               */
61635   #define NFCT_INTENSET_RXERROR_Set (0x1UL)          /*!< Enable                                                               */
61636   #define NFCT_INTENSET_RXERROR_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
61637   #define NFCT_INTENSET_RXERROR_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
61638 
61639 /* ENDRX @Bit 11 : Write '1' to enable interrupt for event ENDRX */
61640   #define NFCT_INTENSET_ENDRX_Pos (11UL)             /*!< Position of ENDRX field.                                             */
61641   #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field.                             */
61642   #define NFCT_INTENSET_ENDRX_Min (0x0UL)            /*!< Min enumerator value of ENDRX field.                                 */
61643   #define NFCT_INTENSET_ENDRX_Max (0x1UL)            /*!< Max enumerator value of ENDRX field.                                 */
61644   #define NFCT_INTENSET_ENDRX_Set (0x1UL)            /*!< Enable                                                               */
61645   #define NFCT_INTENSET_ENDRX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
61646   #define NFCT_INTENSET_ENDRX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
61647 
61648 /* ENDTX @Bit 12 : Write '1' to enable interrupt for event ENDTX */
61649   #define NFCT_INTENSET_ENDTX_Pos (12UL)             /*!< Position of ENDTX field.                                             */
61650   #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field.                             */
61651   #define NFCT_INTENSET_ENDTX_Min (0x0UL)            /*!< Min enumerator value of ENDTX field.                                 */
61652   #define NFCT_INTENSET_ENDTX_Max (0x1UL)            /*!< Max enumerator value of ENDTX field.                                 */
61653   #define NFCT_INTENSET_ENDTX_Set (0x1UL)            /*!< Enable                                                               */
61654   #define NFCT_INTENSET_ENDTX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
61655   #define NFCT_INTENSET_ENDTX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
61656 
61657 /* AUTOCOLRESSTARTED @Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */
61658   #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field.                                 */
61659   #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED
61660                                                                             field.*/
61661   #define NFCT_INTENSET_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of AUTOCOLRESSTARTED field.                    */
61662   #define NFCT_INTENSET_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of AUTOCOLRESSTARTED field.                    */
61663   #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (0x1UL) /*!< Enable                                                              */
61664   #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled                                                 */
61665   #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled                                                   */
61666 
61667 /* COLLISION @Bit 18 : Write '1' to enable interrupt for event COLLISION */
61668   #define NFCT_INTENSET_COLLISION_Pos (18UL)         /*!< Position of COLLISION field.                                         */
61669   #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field.                 */
61670   #define NFCT_INTENSET_COLLISION_Min (0x0UL)        /*!< Min enumerator value of COLLISION field.                             */
61671   #define NFCT_INTENSET_COLLISION_Max (0x1UL)        /*!< Max enumerator value of COLLISION field.                             */
61672   #define NFCT_INTENSET_COLLISION_Set (0x1UL)        /*!< Enable                                                               */
61673   #define NFCT_INTENSET_COLLISION_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
61674   #define NFCT_INTENSET_COLLISION_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
61675 
61676 /* SELECTED @Bit 19 : Write '1' to enable interrupt for event SELECTED */
61677   #define NFCT_INTENSET_SELECTED_Pos (19UL)          /*!< Position of SELECTED field.                                          */
61678   #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field.                    */
61679   #define NFCT_INTENSET_SELECTED_Min (0x0UL)         /*!< Min enumerator value of SELECTED field.                              */
61680   #define NFCT_INTENSET_SELECTED_Max (0x1UL)         /*!< Max enumerator value of SELECTED field.                              */
61681   #define NFCT_INTENSET_SELECTED_Set (0x1UL)         /*!< Enable                                                               */
61682   #define NFCT_INTENSET_SELECTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
61683   #define NFCT_INTENSET_SELECTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
61684 
61685 /* STARTED @Bit 20 : Write '1' to enable interrupt for event STARTED */
61686   #define NFCT_INTENSET_STARTED_Pos (20UL)           /*!< Position of STARTED field.                                           */
61687   #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
61688   #define NFCT_INTENSET_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
61689   #define NFCT_INTENSET_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
61690   #define NFCT_INTENSET_STARTED_Set (0x1UL)          /*!< Enable                                                               */
61691   #define NFCT_INTENSET_STARTED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
61692   #define NFCT_INTENSET_STARTED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
61693 
61694 
61695 /* NFCT_INTENCLR: Disable interrupt */
61696   #define NFCT_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */
61697 
61698 /* READY @Bit 0 : Write '1' to disable interrupt for event READY */
61699   #define NFCT_INTENCLR_READY_Pos (0UL)              /*!< Position of READY field.                                             */
61700   #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field.                             */
61701   #define NFCT_INTENCLR_READY_Min (0x0UL)            /*!< Min enumerator value of READY field.                                 */
61702   #define NFCT_INTENCLR_READY_Max (0x1UL)            /*!< Max enumerator value of READY field.                                 */
61703   #define NFCT_INTENCLR_READY_Clear (0x1UL)          /*!< Disable                                                              */
61704   #define NFCT_INTENCLR_READY_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
61705   #define NFCT_INTENCLR_READY_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
61706 
61707 /* FIELDDETECTED @Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */
61708   #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL)      /*!< Position of FIELDDETECTED field.                                     */
61709   #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field.     */
61710   #define NFCT_INTENCLR_FIELDDETECTED_Min (0x0UL)    /*!< Min enumerator value of FIELDDETECTED field.                         */
61711   #define NFCT_INTENCLR_FIELDDETECTED_Max (0x1UL)    /*!< Max enumerator value of FIELDDETECTED field.                         */
61712   #define NFCT_INTENCLR_FIELDDETECTED_Clear (0x1UL)  /*!< Disable                                                              */
61713   #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
61714   #define NFCT_INTENCLR_FIELDDETECTED_Enabled (0x1UL) /*!< Read: Enabled                                                       */
61715 
61716 /* FIELDLOST @Bit 2 : Write '1' to disable interrupt for event FIELDLOST */
61717   #define NFCT_INTENCLR_FIELDLOST_Pos (2UL)          /*!< Position of FIELDLOST field.                                         */
61718   #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field.                 */
61719   #define NFCT_INTENCLR_FIELDLOST_Min (0x0UL)        /*!< Min enumerator value of FIELDLOST field.                             */
61720   #define NFCT_INTENCLR_FIELDLOST_Max (0x1UL)        /*!< Max enumerator value of FIELDLOST field.                             */
61721   #define NFCT_INTENCLR_FIELDLOST_Clear (0x1UL)      /*!< Disable                                                              */
61722   #define NFCT_INTENCLR_FIELDLOST_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
61723   #define NFCT_INTENCLR_FIELDLOST_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
61724 
61725 /* TXFRAMESTART @Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */
61726   #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL)       /*!< Position of TXFRAMESTART field.                                      */
61727   #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field.        */
61728   #define NFCT_INTENCLR_TXFRAMESTART_Min (0x0UL)     /*!< Min enumerator value of TXFRAMESTART field.                          */
61729   #define NFCT_INTENCLR_TXFRAMESTART_Max (0x1UL)     /*!< Max enumerator value of TXFRAMESTART field.                          */
61730   #define NFCT_INTENCLR_TXFRAMESTART_Clear (0x1UL)   /*!< Disable                                                              */
61731   #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                      */
61732   #define NFCT_INTENCLR_TXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                        */
61733 
61734 /* TXFRAMEEND @Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */
61735   #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL)         /*!< Position of TXFRAMEEND field.                                        */
61736   #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field.              */
61737   #define NFCT_INTENCLR_TXFRAMEEND_Min (0x0UL)       /*!< Min enumerator value of TXFRAMEEND field.                            */
61738   #define NFCT_INTENCLR_TXFRAMEEND_Max (0x1UL)       /*!< Max enumerator value of TXFRAMEEND field.                            */
61739   #define NFCT_INTENCLR_TXFRAMEEND_Clear (0x1UL)     /*!< Disable                                                              */
61740   #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
61741   #define NFCT_INTENCLR_TXFRAMEEND_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
61742 
61743 /* RXFRAMESTART @Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */
61744   #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL)       /*!< Position of RXFRAMESTART field.                                      */
61745   #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field.        */
61746   #define NFCT_INTENCLR_RXFRAMESTART_Min (0x0UL)     /*!< Min enumerator value of RXFRAMESTART field.                          */
61747   #define NFCT_INTENCLR_RXFRAMESTART_Max (0x1UL)     /*!< Max enumerator value of RXFRAMESTART field.                          */
61748   #define NFCT_INTENCLR_RXFRAMESTART_Clear (0x1UL)   /*!< Disable                                                              */
61749   #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                      */
61750   #define NFCT_INTENCLR_RXFRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                        */
61751 
61752 /* RXFRAMEEND @Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */
61753   #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL)         /*!< Position of RXFRAMEEND field.                                        */
61754   #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field.              */
61755   #define NFCT_INTENCLR_RXFRAMEEND_Min (0x0UL)       /*!< Min enumerator value of RXFRAMEEND field.                            */
61756   #define NFCT_INTENCLR_RXFRAMEEND_Max (0x1UL)       /*!< Max enumerator value of RXFRAMEEND field.                            */
61757   #define NFCT_INTENCLR_RXFRAMEEND_Clear (0x1UL)     /*!< Disable                                                              */
61758   #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
61759   #define NFCT_INTENCLR_RXFRAMEEND_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
61760 
61761 /* ERROR @Bit 7 : Write '1' to disable interrupt for event ERROR */
61762   #define NFCT_INTENCLR_ERROR_Pos (7UL)              /*!< Position of ERROR field.                                             */
61763   #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
61764   #define NFCT_INTENCLR_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
61765   #define NFCT_INTENCLR_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
61766   #define NFCT_INTENCLR_ERROR_Clear (0x1UL)          /*!< Disable                                                              */
61767   #define NFCT_INTENCLR_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
61768   #define NFCT_INTENCLR_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
61769 
61770 /* RXERROR @Bit 10 : Write '1' to disable interrupt for event RXERROR */
61771   #define NFCT_INTENCLR_RXERROR_Pos (10UL)           /*!< Position of RXERROR field.                                           */
61772   #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field.                       */
61773   #define NFCT_INTENCLR_RXERROR_Min (0x0UL)          /*!< Min enumerator value of RXERROR field.                               */
61774   #define NFCT_INTENCLR_RXERROR_Max (0x1UL)          /*!< Max enumerator value of RXERROR field.                               */
61775   #define NFCT_INTENCLR_RXERROR_Clear (0x1UL)        /*!< Disable                                                              */
61776   #define NFCT_INTENCLR_RXERROR_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
61777   #define NFCT_INTENCLR_RXERROR_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
61778 
61779 /* ENDRX @Bit 11 : Write '1' to disable interrupt for event ENDRX */
61780   #define NFCT_INTENCLR_ENDRX_Pos (11UL)             /*!< Position of ENDRX field.                                             */
61781   #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field.                             */
61782   #define NFCT_INTENCLR_ENDRX_Min (0x0UL)            /*!< Min enumerator value of ENDRX field.                                 */
61783   #define NFCT_INTENCLR_ENDRX_Max (0x1UL)            /*!< Max enumerator value of ENDRX field.                                 */
61784   #define NFCT_INTENCLR_ENDRX_Clear (0x1UL)          /*!< Disable                                                              */
61785   #define NFCT_INTENCLR_ENDRX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
61786   #define NFCT_INTENCLR_ENDRX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
61787 
61788 /* ENDTX @Bit 12 : Write '1' to disable interrupt for event ENDTX */
61789   #define NFCT_INTENCLR_ENDTX_Pos (12UL)             /*!< Position of ENDTX field.                                             */
61790   #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field.                             */
61791   #define NFCT_INTENCLR_ENDTX_Min (0x0UL)            /*!< Min enumerator value of ENDTX field.                                 */
61792   #define NFCT_INTENCLR_ENDTX_Max (0x1UL)            /*!< Max enumerator value of ENDTX field.                                 */
61793   #define NFCT_INTENCLR_ENDTX_Clear (0x1UL)          /*!< Disable                                                              */
61794   #define NFCT_INTENCLR_ENDTX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
61795   #define NFCT_INTENCLR_ENDTX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
61796 
61797 /* AUTOCOLRESSTARTED @Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */
61798   #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field.                                 */
61799   #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED
61800                                                                             field.*/
61801   #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Min (0x0UL) /*!< Min enumerator value of AUTOCOLRESSTARTED field.                    */
61802   #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Max (0x1UL) /*!< Max enumerator value of AUTOCOLRESSTARTED field.                    */
61803   #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (0x1UL) /*!< Disable                                                           */
61804   #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0x0UL) /*!< Read: Disabled                                                 */
61805   #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (0x1UL) /*!< Read: Enabled                                                   */
61806 
61807 /* COLLISION @Bit 18 : Write '1' to disable interrupt for event COLLISION */
61808   #define NFCT_INTENCLR_COLLISION_Pos (18UL)         /*!< Position of COLLISION field.                                         */
61809   #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field.                 */
61810   #define NFCT_INTENCLR_COLLISION_Min (0x0UL)        /*!< Min enumerator value of COLLISION field.                             */
61811   #define NFCT_INTENCLR_COLLISION_Max (0x1UL)        /*!< Max enumerator value of COLLISION field.                             */
61812   #define NFCT_INTENCLR_COLLISION_Clear (0x1UL)      /*!< Disable                                                              */
61813   #define NFCT_INTENCLR_COLLISION_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
61814   #define NFCT_INTENCLR_COLLISION_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
61815 
61816 /* SELECTED @Bit 19 : Write '1' to disable interrupt for event SELECTED */
61817   #define NFCT_INTENCLR_SELECTED_Pos (19UL)          /*!< Position of SELECTED field.                                          */
61818   #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field.                    */
61819   #define NFCT_INTENCLR_SELECTED_Min (0x0UL)         /*!< Min enumerator value of SELECTED field.                              */
61820   #define NFCT_INTENCLR_SELECTED_Max (0x1UL)         /*!< Max enumerator value of SELECTED field.                              */
61821   #define NFCT_INTENCLR_SELECTED_Clear (0x1UL)       /*!< Disable                                                              */
61822   #define NFCT_INTENCLR_SELECTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
61823   #define NFCT_INTENCLR_SELECTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
61824 
61825 /* STARTED @Bit 20 : Write '1' to disable interrupt for event STARTED */
61826   #define NFCT_INTENCLR_STARTED_Pos (20UL)           /*!< Position of STARTED field.                                           */
61827   #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
61828   #define NFCT_INTENCLR_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
61829   #define NFCT_INTENCLR_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
61830   #define NFCT_INTENCLR_STARTED_Clear (0x1UL)        /*!< Disable                                                              */
61831   #define NFCT_INTENCLR_STARTED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
61832   #define NFCT_INTENCLR_STARTED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
61833 
61834 
61835 /* NFCT_ERRORSTATUS: NFC Error Status register */
61836   #define NFCT_ERRORSTATUS_ResetValue (0x00000000UL) /*!< Reset value of ERRORSTATUS register.                                 */
61837 
61838 /* FRAMEDELAYTIMEOUT @Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
61839   #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field.                               */
61840   #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of
61841                                                                             FRAMEDELAYTIMEOUT field.*/
61842 
61843 
61844 /* NFCT_NFCTAGSTATE: Current operating state of NFC tag */
61845   #define NFCT_NFCTAGSTATE_ResetValue (0x00000000UL) /*!< Reset value of NFCTAGSTATE register.                                 */
61846 
61847 /* NFCTAGSTATE @Bits 0..2 : NfcTag state */
61848   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL)     /*!< Position of NFCTAGSTATE field.                                       */
61849   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field.     */
61850   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Min (0x0UL)   /*!< Min enumerator value of NFCTAGSTATE field.                           */
61851   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Max (0x6UL)   /*!< Max enumerator value of NFCTAGSTATE field.                           */
61852   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0x0UL) /*!< Disabled or sense                                                 */
61853   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (0x2UL) /*!< RampUp                                                              */
61854   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (0x3UL)  /*!< Idle                                                                 */
61855   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (0x4UL) /*!< Receive                                                            */
61856   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (0x5UL) /*!< FrameDelay                                                      */
61857   #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (0x6UL) /*!< Transmit                                                          */
61858 
61859 
61860 /* NFCT_SLEEPSTATE: Sleep state during automatic collision resolution */
61861   #define NFCT_SLEEPSTATE_ResetValue (0x00000000UL)  /*!< Reset value of SLEEPSTATE register.                                  */
61862 
61863 /* SLEEPSTATE @Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to
61864                        SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. */
61865 
61866   #define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL)       /*!< Position of SLEEPSTATE field.                                        */
61867   #define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field.          */
61868   #define NFCT_SLEEPSTATE_SLEEPSTATE_Min (0x0UL)     /*!< Min enumerator value of SLEEPSTATE field.                            */
61869   #define NFCT_SLEEPSTATE_SLEEPSTATE_Max (0x1UL)     /*!< Max enumerator value of SLEEPSTATE field.                            */
61870   #define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0x0UL)    /*!< State is IDLE.                                                       */
61871   #define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (0x1UL)  /*!< State is SLEEP_A.                                                    */
61872 
61873 
61874 /* NFCT_FIELDPRESENT: Indicates the presence or not of a valid field */
61875   #define NFCT_FIELDPRESENT_ResetValue (0x00000000UL) /*!< Reset value of FIELDPRESENT register.                               */
61876 
61877 /* FIELDPRESENT @Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
61878   #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL)   /*!< Position of FIELDPRESENT field.                                      */
61879   #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field.*/
61880   #define NFCT_FIELDPRESENT_FIELDPRESENT_Min (0x0UL) /*!< Min enumerator value of FIELDPRESENT field.                          */
61881   #define NFCT_FIELDPRESENT_FIELDPRESENT_Max (0x1UL) /*!< Max enumerator value of FIELDPRESENT field.                          */
61882   #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0x0UL) /*!< No valid field detected                                          */
61883   #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (0x1UL) /*!< Valid field detected                                        */
61884 
61885 /* LOCKDETECT @Bit 1 : Indicates if the low level has locked to the field */
61886   #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL)     /*!< Position of LOCKDETECT field.                                        */
61887   #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field.      */
61888   #define NFCT_FIELDPRESENT_LOCKDETECT_Min (0x0UL)   /*!< Min enumerator value of LOCKDETECT field.                            */
61889   #define NFCT_FIELDPRESENT_LOCKDETECT_Max (0x1UL)   /*!< Max enumerator value of LOCKDETECT field.                            */
61890   #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0x0UL) /*!< Not locked to field                                              */
61891   #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (0x1UL) /*!< Locked to field                                                     */
61892 
61893 
61894 /* NFCT_FRAMEDELAYMIN: Minimum frame delay */
61895   #define NFCT_FRAMEDELAYMIN_ResetValue (0x00000480UL) /*!< Reset value of FRAMEDELAYMIN register.                             */
61896 
61897 /* FRAMEDELAYMIN @Bits 0..15 : Minimum frame delay in number of 13.56 MHz clock cycles */
61898   #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field.                                     */
61899   #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN
61900                                                                             field.*/
61901 
61902 
61903 /* NFCT_FRAMEDELAYMAX: Maximum frame delay */
61904   #define NFCT_FRAMEDELAYMAX_ResetValue (0x00001000UL) /*!< Reset value of FRAMEDELAYMAX register.                             */
61905 
61906 /* FRAMEDELAYMAX @Bits 0..19 : Maximum frame delay in number of 13.56 MHz clock cycles */
61907   #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field.                                     */
61908   #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of
61909                                                                             FRAMEDELAYMAX field.*/
61910 
61911 
61912 /* NFCT_FRAMEDELAYMODE: Configuration register for the Frame Delay Timer */
61913   #define NFCT_FRAMEDELAYMODE_ResetValue (0x00000001UL) /*!< Reset value of FRAMEDELAYMODE register.                           */
61914 
61915 /* FRAMEDELAYMODE @Bits 0..1 : Configuration register for the Frame Delay Timer */
61916   #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field.                                  */
61917   #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of
61918                                                                             FRAMEDELAYMODE field.*/
61919   #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Min (0x0UL) /*!< Min enumerator value of FRAMEDELAYMODE field.                    */
61920   #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Max (0x3UL) /*!< Max enumerator value of FRAMEDELAYMODE field.                    */
61921   #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0x0UL) /*!< Transmission is independent of frame timer and will start when
61922                                                                   the STARTTX task is triggered. No timeout.*/
61923   #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (0x1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX  */
61924   #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (0x2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX               */
61925   #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (0x3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN
61926                                                                      and FRAMEDELAYMAX*/
61927 
61928 
61929 /* NFCT_MODULATIONCTRL: Enables the modulation output to a GPIO pin which can be connected to a second external antenna. */
61930   #define NFCT_MODULATIONCTRL_ResetValue (0x00000001UL) /*!< Reset value of MODULATIONCTRL register.                           */
61931 
61932 /* MODULATIONCTRL @Bits 0..1 : Configuration of modulation control. */
61933   #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos (0UL) /*!< Position of MODULATIONCTRL field.                                  */
61934   #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk (0x3UL << NFCT_MODULATIONCTRL_MODULATIONCTRL_Pos) /*!< Bit mask of
61935                                                                             MODULATIONCTRL field.*/
61936   #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Min (0x0UL) /*!< Min enumerator value of MODULATIONCTRL field.                    */
61937   #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Max (0x3UL) /*!< Max enumerator value of MODULATIONCTRL field.                    */
61938   #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Invalid (0x0UL) /*!< Invalid, defaults to same behaviour as for Internal          */
61939   #define NFCT_MODULATIONCTRL_MODULATIONCTRL_Internal (0x1UL) /*!< Use internal modulator only                                 */
61940   #define NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio (0x2UL) /*!< Output digital modulation signal to a GPIO pin.            */
61941   #define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL) /*!< Use internal modulator and output digital
61942                                                                             modulation signal to a GPIO pin.*/
61943 
61944 
61945 /* NFCT_MODULATIONPSEL: Pin select for Modulation control */
61946   #define NFCT_MODULATIONPSEL_ResetValue (0xFFFFFFFFUL) /*!< Reset value of MODULATIONPSEL register.                           */
61947 
61948 /* PIN @Bits 0..4 : Pin number */
61949   #define NFCT_MODULATIONPSEL_PIN_Pos (0UL)          /*!< Position of PIN field.                                               */
61950   #define NFCT_MODULATIONPSEL_PIN_Msk (0x1FUL << NFCT_MODULATIONPSEL_PIN_Pos) /*!< Bit mask of PIN field.                      */
61951   #define NFCT_MODULATIONPSEL_PIN_Min (0x0UL)        /*!< Min value of PIN field.                                              */
61952   #define NFCT_MODULATIONPSEL_PIN_Max (0x1FUL)       /*!< Max size of PIN field.                                               */
61953 
61954 /* PORT @Bits 5..8 : Port number */
61955   #define NFCT_MODULATIONPSEL_PORT_Pos (5UL)         /*!< Position of PORT field.                                              */
61956   #define NFCT_MODULATIONPSEL_PORT_Msk (0xFUL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field.                    */
61957   #define NFCT_MODULATIONPSEL_PORT_Min (0x0UL)       /*!< Min value of PORT field.                                             */
61958   #define NFCT_MODULATIONPSEL_PORT_Max (0xFUL)       /*!< Max size of PORT field.                                              */
61959 
61960 /* CONNECT @Bit 31 : Connection */
61961   #define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL)     /*!< Position of CONNECT field.                                           */
61962   #define NFCT_MODULATIONPSEL_CONNECT_Msk (0x1UL << NFCT_MODULATIONPSEL_CONNECT_Pos) /*!< Bit mask of CONNECT field.           */
61963   #define NFCT_MODULATIONPSEL_CONNECT_Min (0x0UL)    /*!< Min enumerator value of CONNECT field.                               */
61964   #define NFCT_MODULATIONPSEL_CONNECT_Max (0x1UL)    /*!< Max enumerator value of CONNECT field.                               */
61965   #define NFCT_MODULATIONPSEL_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                     */
61966   #define NFCT_MODULATIONPSEL_CONNECT_Connected (0x0UL) /*!< Connect                                                           */
61967 
61968 
61969 /* NFCT_MODE: Configure EasyDMA mode */
61970   #define NFCT_MODE_ResetValue (0x00000001UL)        /*!< Reset value of MODE register.                                        */
61971 
61972 /* LPOP @Bits 0..1 : Enable low-power operation, or use low-latency */
61973   #define NFCT_MODE_LPOP_Pos (0UL)                   /*!< Position of LPOP field.                                              */
61974   #define NFCT_MODE_LPOP_Msk (0x3UL << NFCT_MODE_LPOP_Pos) /*!< Bit mask of LPOP field.                                        */
61975   #define NFCT_MODE_LPOP_Min (0x0UL)                 /*!< Min enumerator value of LPOP field.                                  */
61976   #define NFCT_MODE_LPOP_Max (0x3UL)                 /*!< Max enumerator value of LPOP field.                                  */
61977   #define NFCT_MODE_LPOP_LowLat (0x0UL)              /*!< Low-latency operation                                                */
61978   #define NFCT_MODE_LPOP_LowPower (0x1UL)            /*!< Low-power operation                                                  */
61979   #define NFCT_MODE_LPOP_FullLowPower (0x3UL)        /*!< Full Low-power operation                                             */
61980 
61981 
61982 /* NFCT_NFCID1_LAST: Last NFCID1 part (4, 7 or 10 bytes ID) */
61983   #define NFCT_NFCID1_LAST_ResetValue (0x00006363UL) /*!< Reset value of NFCID1_LAST register.                                 */
61984 
61985 /* NFCID1_Z @Bits 0..7 : NFCID1 byte Z (very last byte sent) */
61986   #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL)        /*!< Position of NFCID1_Z field.                                          */
61987   #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field.             */
61988 
61989 /* NFCID1_Y @Bits 8..15 : NFCID1 byte Y */
61990   #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL)        /*!< Position of NFCID1_Y field.                                          */
61991   #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field.             */
61992 
61993 /* NFCID1_X @Bits 16..23 : NFCID1 byte X */
61994   #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL)       /*!< Position of NFCID1_X field.                                          */
61995   #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field.             */
61996 
61997 /* NFCID1_W @Bits 24..31 : NFCID1 byte W */
61998   #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL)       /*!< Position of NFCID1_W field.                                          */
61999   #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field.             */
62000 
62001 
62002 /* NFCT_NFCID1_2ND_LAST: Second last NFCID1 part (7 or 10 bytes ID) */
62003   #define NFCT_NFCID1_2ND_LAST_ResetValue (0x00000000UL) /*!< Reset value of NFCID1_2ND_LAST register.                         */
62004 
62005 /* NFCID1_V @Bits 0..7 : NFCID1 byte V */
62006   #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL)    /*!< Position of NFCID1_V field.                                          */
62007   #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field.     */
62008 
62009 /* NFCID1_U @Bits 8..15 : NFCID1 byte U */
62010   #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL)    /*!< Position of NFCID1_U field.                                          */
62011   #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field.     */
62012 
62013 /* NFCID1_T @Bits 16..23 : NFCID1 byte T */
62014   #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL)   /*!< Position of NFCID1_T field.                                          */
62015   #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field.     */
62016 
62017 
62018 /* NFCT_NFCID1_3RD_LAST: Third last NFCID1 part (10 bytes ID) */
62019   #define NFCT_NFCID1_3RD_LAST_ResetValue (0x00000000UL) /*!< Reset value of NFCID1_3RD_LAST register.                         */
62020 
62021 /* NFCID1_S @Bits 0..7 : NFCID1 byte S */
62022   #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL)    /*!< Position of NFCID1_S field.                                          */
62023   #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field.     */
62024 
62025 /* NFCID1_R @Bits 8..15 : NFCID1 byte R */
62026   #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL)    /*!< Position of NFCID1_R field.                                          */
62027   #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field.     */
62028 
62029 /* NFCID1_Q @Bits 16..23 : NFCID1 byte Q */
62030   #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL)   /*!< Position of NFCID1_Q field.                                          */
62031   #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field.     */
62032 
62033 
62034 /* NFCT_AUTOCOLRESCONFIG: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral
62035                            is activated. */
62036 
62037   #define NFCT_AUTOCOLRESCONFIG_ResetValue (0x00000002UL) /*!< Reset value of AUTOCOLRESCONFIG register.                       */
62038 
62039 /* MODE @Bit 0 : Enables/disables auto collision resolution */
62040   #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL)       /*!< Position of MODE field.                                              */
62041   #define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field.                */
62042   #define NFCT_AUTOCOLRESCONFIG_MODE_Min (0x0UL)     /*!< Min enumerator value of MODE field.                                  */
62043   #define NFCT_AUTOCOLRESCONFIG_MODE_Max (0x1UL)     /*!< Max enumerator value of MODE field.                                  */
62044   #define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0x0UL) /*!< Auto collision resolution enabled                                    */
62045   #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (0x1UL) /*!< Auto collision resolution disabled                                  */
62046 
62047 
62048 /* NFCT_SENSRES: NFC-A SENS_RES auto-response settings */
62049   #define NFCT_SENSRES_ResetValue (0x00000001UL)     /*!< Reset value of SENSRES register.                                     */
62050 
62051 /* BITFRAMESDD @Bits 0..4 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital
62052                             Protocol Technical Specification */
62053 
62054   #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL)         /*!< Position of BITFRAMESDD field.                                       */
62055   #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field.            */
62056   #define NFCT_SENSRES_BITFRAMESDD_Min (0x0UL)       /*!< Min enumerator value of BITFRAMESDD field.                           */
62057   #define NFCT_SENSRES_BITFRAMESDD_Max (0x10UL)      /*!< Max enumerator value of BITFRAMESDD field.                           */
62058   #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0x00UL) /*!< SDD pattern 00000                                                    */
62059   #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (0x01UL) /*!< SDD pattern 00001                                                    */
62060   #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (0x02UL) /*!< SDD pattern 00010                                                    */
62061   #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (0x04UL) /*!< SDD pattern 00100                                                    */
62062   #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (0x08UL) /*!< SDD pattern 01000                                                    */
62063   #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (0x10UL) /*!< SDD pattern 10000                                                    */
62064 
62065 /* RFU5 @Bit 5 : Reserved for future use. Shall be 0. */
62066   #define NFCT_SENSRES_RFU5_Pos (5UL)                /*!< Position of RFU5 field.                                              */
62067   #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field.                                  */
62068 
62069 /* NFCIDSIZE @Bits 6..7 : NFCID1 size. This value is used by the auto collision resolution engine. */
62070   #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL)           /*!< Position of NFCIDSIZE field.                                         */
62071   #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field.                   */
62072   #define NFCT_SENSRES_NFCIDSIZE_Min (0x0UL)         /*!< Min enumerator value of NFCIDSIZE field.                             */
62073   #define NFCT_SENSRES_NFCIDSIZE_Max (0x2UL)         /*!< Max enumerator value of NFCIDSIZE field.                             */
62074   #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0x0UL) /*!< NFCID1 size: single (4 bytes)                                       */
62075   #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (0x1UL) /*!< NFCID1 size: double (7 bytes)                                       */
62076   #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (0x2UL) /*!< NFCID1 size: triple (10 bytes)                                      */
62077 
62078 /* PLATFCONFIG @Bits 8..11 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum,
62079                              NFC Digital Protocol Technical Specification */
62080 
62081   #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL)         /*!< Position of PLATFCONFIG field.                                       */
62082   #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field.             */
62083 
62084 /* RFU74 @Bits 12..15 : Reserved for future use. Shall be 0. */
62085   #define NFCT_SENSRES_RFU74_Pos (12UL)              /*!< Position of RFU74 field.                                             */
62086   #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field.                               */
62087 
62088 
62089 /* NFCT_SELRES: NFC-A SEL_RES auto-response settings */
62090   #define NFCT_SELRES_ResetValue (0x00000000UL)      /*!< Reset value of SELRES register.                                      */
62091 
62092 /* RFU10 @Bits 0..1 : Reserved for future use. Shall be 0. */
62093   #define NFCT_SELRES_RFU10_Pos (0UL)                /*!< Position of RFU10 field.                                             */
62094   #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field.                                 */
62095 
62096 /* CASCADE @Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical
62097                     Specification (controlled by hardware, shall be 0) */
62098 
62099   #define NFCT_SELRES_CASCADE_Pos (2UL)              /*!< Position of CASCADE field.                                           */
62100   #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field.                           */
62101 
62102 /* RFU43 @Bits 3..4 : Reserved for future use. Shall be 0. */
62103   #define NFCT_SELRES_RFU43_Pos (3UL)                /*!< Position of RFU43 field.                                             */
62104   #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field.                                 */
62105 
62106 /* PROTOCOL @Bits 5..6 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical
62107                          Specification */
62108 
62109   #define NFCT_SELRES_PROTOCOL_Pos (5UL)             /*!< Position of PROTOCOL field.                                          */
62110   #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field.                        */
62111 
62112 /* RFU7 @Bit 7 : Reserved for future use. Shall be 0. */
62113   #define NFCT_SELRES_RFU7_Pos (7UL)                 /*!< Position of RFU7 field.                                              */
62114   #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field.                                    */
62115 
62116 
62117 /* NFCT_PACKETPTR: Packet pointer for TXD and RXD data storage in Data RAM */
62118   #define NFCT_PACKETPTR_ResetValue (0x00000000UL)   /*!< Reset value of PACKETPTR register.                                   */
62119 
62120 /* PTR @Bits 0..31 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
62121   #define NFCT_PACKETPTR_PTR_Pos (0UL)               /*!< Position of PTR field.                                               */
62122   #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field.                          */
62123 
62124 
62125 /* NFCT_MAXLEN: Size of the RAM buffer allocated to TXD and RXD data storage each */
62126   #define NFCT_MAXLEN_ResetValue (0x00000000UL)      /*!< Reset value of MAXLEN register.                                      */
62127 
62128 /* MAXLEN @Bits 0..8 : Size of the RAM buffer allocated to TXD and RXD data storage each */
62129   #define NFCT_MAXLEN_MAXLEN_Pos (0UL)               /*!< Position of MAXLEN field.                                            */
62130   #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field.                            */
62131   #define NFCT_MAXLEN_MAXLEN_Min (0x0UL)             /*!< Min value of MAXLEN field.                                           */
62132   #define NFCT_MAXLEN_MAXLEN_Max (0x101UL)           /*!< Max size of MAXLEN field.                                            */
62133 
62134 
62135 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
62136 
62137 /* =========================================================================================================================== */
62138 /* ================                                            PDM                                            ================ */
62139 /* =========================================================================================================================== */
62140 
62141 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
62142 
62143 /* ===================================================== Struct PDM_PSEL ===================================================== */
62144 /**
62145   * @brief PSEL [PDM_PSEL] (unspecified)
62146   */
62147 typedef struct {
62148   __IOM uint32_t  CLK;                               /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal           */
62149   __IOM uint32_t  DIN;                               /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal           */
62150 } NRF_PDM_PSEL_Type;                                 /*!< Size = 8 (0x008)                                                     */
62151 
62152 /* PDM_PSEL_CLK: Pin number configuration for PDM CLK signal */
62153   #define PDM_PSEL_CLK_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of CLK register.                                         */
62154 
62155 /* PIN @Bits 0..4 : Pin number */
62156   #define PDM_PSEL_CLK_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
62157   #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field.                                    */
62158   #define PDM_PSEL_CLK_PIN_Min (0x0UL)               /*!< Min value of PIN field.                                              */
62159   #define PDM_PSEL_CLK_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */
62160 
62161 /* PORT @Bits 5..8 : Port number */
62162   #define PDM_PSEL_CLK_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
62163   #define PDM_PSEL_CLK_PORT_Msk (0xFUL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field.                                  */
62164   #define PDM_PSEL_CLK_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
62165   #define PDM_PSEL_CLK_PORT_Max (0xFUL)              /*!< Max size of PORT field.                                              */
62166 
62167 /* CONNECT @Bit 31 : Connection */
62168   #define PDM_PSEL_CLK_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
62169   #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
62170   #define PDM_PSEL_CLK_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
62171   #define PDM_PSEL_CLK_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
62172   #define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
62173   #define PDM_PSEL_CLK_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */
62174 
62175 
62176 /* PDM_PSEL_DIN: Pin number configuration for PDM DIN signal */
62177   #define PDM_PSEL_DIN_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of DIN register.                                         */
62178 
62179 /* PIN @Bits 0..4 : Pin number */
62180   #define PDM_PSEL_DIN_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
62181   #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field.                                    */
62182   #define PDM_PSEL_DIN_PIN_Min (0x0UL)               /*!< Min value of PIN field.                                              */
62183   #define PDM_PSEL_DIN_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */
62184 
62185 /* PORT @Bits 5..8 : Port number */
62186   #define PDM_PSEL_DIN_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
62187   #define PDM_PSEL_DIN_PORT_Msk (0xFUL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field.                                  */
62188   #define PDM_PSEL_DIN_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
62189   #define PDM_PSEL_DIN_PORT_Max (0xFUL)              /*!< Max size of PORT field.                                              */
62190 
62191 /* CONNECT @Bit 31 : Connection */
62192   #define PDM_PSEL_DIN_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
62193   #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
62194   #define PDM_PSEL_DIN_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
62195   #define PDM_PSEL_DIN_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
62196   #define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
62197   #define PDM_PSEL_DIN_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */
62198 
62199 
62200 
62201 /* ==================================================== Struct PDM_SAMPLE ==================================================== */
62202 /**
62203   * @brief SAMPLE [PDM_SAMPLE] (unspecified)
62204   */
62205 typedef struct {
62206   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) RAM address pointer to write samples to with EasyDMA  */
62207   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA
62208                                                                          mode*/
62209   __IM  uint32_t  RESERVED;
62210 } NRF_PDM_SAMPLE_Type;                               /*!< Size = 12 (0x00C)                                                    */
62211 
62212 /* PDM_SAMPLE_PTR: RAM address pointer to write samples to with EasyDMA */
62213   #define PDM_SAMPLE_PTR_ResetValue (0x00000000UL)   /*!< Reset value of PTR register.                                         */
62214 
62215 /* SAMPLEPTR @Bits 0..31 : Address to write PDM samples to over DMA */
62216   #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL)         /*!< Position of SAMPLEPTR field.                                         */
62217   #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field.        */
62218 
62219 
62220 /* PDM_SAMPLE_MAXCNT: Number of samples to allocate memory for in EasyDMA mode */
62221   #define PDM_SAMPLE_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                     */
62222 
62223 /* BUFFSIZE @Bits 0..14 : Length of DMA RAM allocation in number of samples */
62224   #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL)       /*!< Position of BUFFSIZE field.                                          */
62225   #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field.         */
62226   #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Min (0x0UL)     /*!< Min value of BUFFSIZE field.                                         */
62227   #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Max (0x7FFFUL)  /*!< Max size of BUFFSIZE field.                                          */
62228 
62229 
62230 
62231 /* ===================================================== Struct PDM_DMA ====================================================== */
62232 /**
62233   * @brief DMA [PDM_DMA] (unspecified)
62234   */
62235 typedef struct {
62236   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
62237                                                                          detected.*/
62238   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
62239                                                                          event.*/
62240 } NRF_PDM_DMA_Type;                                  /*!< Size = 8 (0x008)                                                     */
62241 
62242 /* PDM_DMA_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
62243   #define PDM_DMA_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.              */
62244 
62245 /* ENABLE @Bit 0 : (unspecified) */
62246   #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                          */
62247   #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << PDM_DMA_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of ENABLE
62248                                                                             field.*/
62249   #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                            */
62250   #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                            */
62251   #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                     */
62252   #define PDM_DMA_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                       */
62253 
62254 
62255 /* PDM_DMA_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
62256   #define PDM_DMA_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                      */
62257 
62258 /* ADDRESS @Bits 0..31 : (unspecified) */
62259   #define PDM_DMA_BUSERRORADDRESS_ADDRESS_Pos (0UL)  /*!< Position of ADDRESS field.                                           */
62260   #define PDM_DMA_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << PDM_DMA_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS
62261                                                                             field.*/
62262 
62263 
62264 /* ======================================================= Struct PDM ======================================================== */
62265 /**
62266   * @brief Pulse Density Modulation (Digital Microphone) Interface
62267   */
62268   typedef struct {                                   /*!< PDM Structure                                                        */
62269     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Starts continuous PDM transfer                        */
62270     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stops PDM transfer                                    */
62271     __IM uint32_t RESERVED[30];
62272     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
62273     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
62274     __IM uint32_t RESERVED1[30];
62275     __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000100) PDM transfer has started                              */
62276     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) PDM transfer has finished                             */
62277     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000108) The PDM has written the last sample specified by
62278                                                                          SAMPLE.MAXCNT (or the last sample after a STOP task has
62279                                                                          been received) to Data RAM*/
62280     __IM uint32_t RESERVED2[29];
62281     __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x00000180) Publish configuration for event STARTED               */
62282     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
62283     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000188) Publish configuration for event END                   */
62284     __IM uint32_t RESERVED3[93];
62285     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
62286     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
62287     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
62288     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
62289     __IM uint32_t RESERVED4[124];
62290     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) PDM module enable register                            */
62291     __IOM uint32_t PDMCLKCTRL;                       /*!< (@ 0x00000504) PDM clock generator control                           */
62292     __IOM uint32_t MODE;                             /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones'
62293                                                                          signals*/
62294     __IM uint32_t RESERVED5[3];
62295     __IOM uint32_t GAINL;                            /*!< (@ 0x00000518) Left output gain adjustment                           */
62296     __IOM uint32_t GAINR;                            /*!< (@ 0x0000051C) Right output gain adjustment                          */
62297     __IOM uint32_t RATIO;                            /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output sample
62298                                                                          rate. Change PDMCLKCTRL accordingly.*/
62299     __IM uint32_t RESERVED6[7];
62300     __IOM NRF_PDM_PSEL_Type PSEL;                    /*!< (@ 0x00000540) (unspecified)                                         */
62301     __IM uint32_t RESERVED7;
62302     __IOM uint32_t MCLKCONFIG;                       /*!< (@ 0x0000054C) Master clock generator configuration                  */
62303     __IM uint32_t RESERVED8[4];
62304     __IOM NRF_PDM_SAMPLE_Type SAMPLE;                /*!< (@ 0x00000560) (unspecified)                                         */
62305     __IM uint32_t RESERVED9[101];
62306     __IOM NRF_PDM_DMA_Type DMA;                      /*!< (@ 0x00000700) (unspecified)                                         */
62307   } NRF_PDM_Type;                                    /*!< Size = 1800 (0x708)                                                  */
62308 
62309 /* PDM_TASKS_START: Starts continuous PDM transfer */
62310   #define PDM_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
62311 
62312 /* TASKS_START @Bit 0 : Starts continuous PDM transfer */
62313   #define PDM_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
62314   #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
62315   #define PDM_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
62316   #define PDM_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
62317   #define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
62318 
62319 
62320 /* PDM_TASKS_STOP: Stops PDM transfer */
62321   #define PDM_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
62322 
62323 /* TASKS_STOP @Bit 0 : Stops PDM transfer */
62324   #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
62325   #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
62326   #define PDM_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
62327   #define PDM_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
62328   #define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
62329 
62330 
62331 /* PDM_SUBSCRIBE_START: Subscribe configuration for task START */
62332   #define PDM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */
62333 
62334 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
62335   #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
62336   #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
62337   #define PDM_SUBSCRIBE_START_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
62338   #define PDM_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
62339 
62340 /* EN @Bit 31 : (unspecified) */
62341   #define PDM_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
62342   #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
62343   #define PDM_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
62344   #define PDM_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
62345   #define PDM_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
62346   #define PDM_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
62347 
62348 
62349 /* PDM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
62350   #define PDM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */
62351 
62352 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
62353   #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
62354   #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
62355   #define PDM_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
62356   #define PDM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
62357 
62358 /* EN @Bit 31 : (unspecified) */
62359   #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
62360   #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
62361   #define PDM_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
62362   #define PDM_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
62363   #define PDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
62364   #define PDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
62365 
62366 
62367 /* PDM_EVENTS_STARTED: PDM transfer has started */
62368   #define PDM_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                            */
62369 
62370 /* EVENTS_STARTED @Bit 0 : PDM transfer has started */
62371   #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                   */
62372   #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED
62373                                                                             field.*/
62374   #define PDM_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                     */
62375   #define PDM_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                     */
62376   #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                      */
62377   #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                             */
62378 
62379 
62380 /* PDM_EVENTS_STOPPED: PDM transfer has finished */
62381   #define PDM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                            */
62382 
62383 /* EVENTS_STOPPED @Bit 0 : PDM transfer has finished */
62384   #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                   */
62385   #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED
62386                                                                             field.*/
62387   #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                     */
62388   #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                     */
62389   #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                      */
62390   #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                             */
62391 
62392 
62393 /* PDM_EVENTS_END: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been
62394                     received) to Data RAM */
62395 
62396   #define PDM_EVENTS_END_ResetValue (0x00000000UL)   /*!< Reset value of EVENTS_END register.                                  */
62397 
62398 /* EVENTS_END @Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has
62399                        been received) to Data RAM */
62400 
62401   #define PDM_EVENTS_END_EVENTS_END_Pos (0UL)        /*!< Position of EVENTS_END field.                                        */
62402   #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.            */
62403   #define PDM_EVENTS_END_EVENTS_END_Min (0x0UL)      /*!< Min enumerator value of EVENTS_END field.                            */
62404   #define PDM_EVENTS_END_EVENTS_END_Max (0x1UL)      /*!< Max enumerator value of EVENTS_END field.                            */
62405   #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                              */
62406   #define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                     */
62407 
62408 
62409 /* PDM_PUBLISH_STARTED: Publish configuration for event STARTED */
62410   #define PDM_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                          */
62411 
62412 /* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
62413   #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
62414   #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
62415   #define PDM_PUBLISH_STARTED_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
62416   #define PDM_PUBLISH_STARTED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
62417 
62418 /* EN @Bit 31 : (unspecified) */
62419   #define PDM_PUBLISH_STARTED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
62420   #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                          */
62421   #define PDM_PUBLISH_STARTED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
62422   #define PDM_PUBLISH_STARTED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
62423   #define PDM_PUBLISH_STARTED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
62424   #define PDM_PUBLISH_STARTED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
62425 
62426 
62427 /* PDM_PUBLISH_STOPPED: Publish configuration for event STOPPED */
62428   #define PDM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                          */
62429 
62430 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
62431   #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
62432   #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
62433   #define PDM_PUBLISH_STOPPED_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
62434   #define PDM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
62435 
62436 /* EN @Bit 31 : (unspecified) */
62437   #define PDM_PUBLISH_STOPPED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
62438   #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                          */
62439   #define PDM_PUBLISH_STOPPED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
62440   #define PDM_PUBLISH_STOPPED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
62441   #define PDM_PUBLISH_STOPPED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
62442   #define PDM_PUBLISH_STOPPED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
62443 
62444 
62445 /* PDM_PUBLISH_END: Publish configuration for event END */
62446   #define PDM_PUBLISH_END_ResetValue (0x00000000UL)  /*!< Reset value of PUBLISH_END register.                                 */
62447 
62448 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
62449   #define PDM_PUBLISH_END_CHIDX_Pos (0UL)            /*!< Position of CHIDX field.                                             */
62450   #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                        */
62451   #define PDM_PUBLISH_END_CHIDX_Min (0x0UL)          /*!< Min value of CHIDX field.                                            */
62452   #define PDM_PUBLISH_END_CHIDX_Max (0xFFUL)         /*!< Max size of CHIDX field.                                             */
62453 
62454 /* EN @Bit 31 : (unspecified) */
62455   #define PDM_PUBLISH_END_EN_Pos (31UL)              /*!< Position of EN field.                                                */
62456   #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                  */
62457   #define PDM_PUBLISH_END_EN_Min (0x0UL)             /*!< Min enumerator value of EN field.                                    */
62458   #define PDM_PUBLISH_END_EN_Max (0x1UL)             /*!< Max enumerator value of EN field.                                    */
62459   #define PDM_PUBLISH_END_EN_Disabled (0x0UL)        /*!< Disable publishing                                                   */
62460   #define PDM_PUBLISH_END_EN_Enabled (0x1UL)         /*!< Enable publishing                                                    */
62461 
62462 
62463 /* PDM_INTEN: Enable or disable interrupt */
62464   #define PDM_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
62465 
62466 /* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */
62467   #define PDM_INTEN_STARTED_Pos (0UL)                /*!< Position of STARTED field.                                           */
62468   #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field.                               */
62469   #define PDM_INTEN_STARTED_Min (0x0UL)              /*!< Min enumerator value of STARTED field.                               */
62470   #define PDM_INTEN_STARTED_Max (0x1UL)              /*!< Max enumerator value of STARTED field.                               */
62471   #define PDM_INTEN_STARTED_Disabled (0x0UL)         /*!< Disable                                                              */
62472   #define PDM_INTEN_STARTED_Enabled (0x1UL)          /*!< Enable                                                               */
62473 
62474 /* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */
62475   #define PDM_INTEN_STOPPED_Pos (1UL)                /*!< Position of STOPPED field.                                           */
62476   #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                               */
62477   #define PDM_INTEN_STOPPED_Min (0x0UL)              /*!< Min enumerator value of STOPPED field.                               */
62478   #define PDM_INTEN_STOPPED_Max (0x1UL)              /*!< Max enumerator value of STOPPED field.                               */
62479   #define PDM_INTEN_STOPPED_Disabled (0x0UL)         /*!< Disable                                                              */
62480   #define PDM_INTEN_STOPPED_Enabled (0x1UL)          /*!< Enable                                                               */
62481 
62482 /* END @Bit 2 : Enable or disable interrupt for event END */
62483   #define PDM_INTEN_END_Pos (2UL)                    /*!< Position of END field.                                               */
62484   #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field.                                           */
62485   #define PDM_INTEN_END_Min (0x0UL)                  /*!< Min enumerator value of END field.                                   */
62486   #define PDM_INTEN_END_Max (0x1UL)                  /*!< Max enumerator value of END field.                                   */
62487   #define PDM_INTEN_END_Disabled (0x0UL)             /*!< Disable                                                              */
62488   #define PDM_INTEN_END_Enabled (0x1UL)              /*!< Enable                                                               */
62489 
62490 
62491 /* PDM_INTENSET: Enable interrupt */
62492   #define PDM_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
62493 
62494 /* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */
62495   #define PDM_INTENSET_STARTED_Pos (0UL)             /*!< Position of STARTED field.                                           */
62496   #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                         */
62497   #define PDM_INTENSET_STARTED_Min (0x0UL)           /*!< Min enumerator value of STARTED field.                               */
62498   #define PDM_INTENSET_STARTED_Max (0x1UL)           /*!< Max enumerator value of STARTED field.                               */
62499   #define PDM_INTENSET_STARTED_Set (0x1UL)           /*!< Enable                                                               */
62500   #define PDM_INTENSET_STARTED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
62501   #define PDM_INTENSET_STARTED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
62502 
62503 /* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
62504   #define PDM_INTENSET_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
62505   #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
62506   #define PDM_INTENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
62507   #define PDM_INTENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
62508   #define PDM_INTENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
62509   #define PDM_INTENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
62510   #define PDM_INTENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
62511 
62512 /* END @Bit 2 : Write '1' to enable interrupt for event END */
62513   #define PDM_INTENSET_END_Pos (2UL)                 /*!< Position of END field.                                               */
62514   #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field.                                     */
62515   #define PDM_INTENSET_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
62516   #define PDM_INTENSET_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
62517   #define PDM_INTENSET_END_Set (0x1UL)               /*!< Enable                                                               */
62518   #define PDM_INTENSET_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
62519   #define PDM_INTENSET_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
62520 
62521 
62522 /* PDM_INTENCLR: Disable interrupt */
62523   #define PDM_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
62524 
62525 /* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */
62526   #define PDM_INTENCLR_STARTED_Pos (0UL)             /*!< Position of STARTED field.                                           */
62527   #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                         */
62528   #define PDM_INTENCLR_STARTED_Min (0x0UL)           /*!< Min enumerator value of STARTED field.                               */
62529   #define PDM_INTENCLR_STARTED_Max (0x1UL)           /*!< Max enumerator value of STARTED field.                               */
62530   #define PDM_INTENCLR_STARTED_Clear (0x1UL)         /*!< Disable                                                              */
62531   #define PDM_INTENCLR_STARTED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
62532   #define PDM_INTENCLR_STARTED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
62533 
62534 /* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
62535   #define PDM_INTENCLR_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
62536   #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
62537   #define PDM_INTENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
62538   #define PDM_INTENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
62539   #define PDM_INTENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
62540   #define PDM_INTENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
62541   #define PDM_INTENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
62542 
62543 /* END @Bit 2 : Write '1' to disable interrupt for event END */
62544   #define PDM_INTENCLR_END_Pos (2UL)                 /*!< Position of END field.                                               */
62545   #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field.                                     */
62546   #define PDM_INTENCLR_END_Min (0x0UL)               /*!< Min enumerator value of END field.                                   */
62547   #define PDM_INTENCLR_END_Max (0x1UL)               /*!< Max enumerator value of END field.                                   */
62548   #define PDM_INTENCLR_END_Clear (0x1UL)             /*!< Disable                                                              */
62549   #define PDM_INTENCLR_END_Disabled (0x0UL)          /*!< Read: Disabled                                                       */
62550   #define PDM_INTENCLR_END_Enabled (0x1UL)           /*!< Read: Enabled                                                        */
62551 
62552 
62553 /* PDM_INTPEND: Pending interrupts */
62554   #define PDM_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */
62555 
62556 /* STARTED @Bit 0 : Read pending status of interrupt for event STARTED */
62557   #define PDM_INTPEND_STARTED_Pos (0UL)              /*!< Position of STARTED field.                                           */
62558   #define PDM_INTPEND_STARTED_Msk (0x1UL << PDM_INTPEND_STARTED_Pos) /*!< Bit mask of STARTED field.                           */
62559   #define PDM_INTPEND_STARTED_Min (0x0UL)            /*!< Min enumerator value of STARTED field.                               */
62560   #define PDM_INTPEND_STARTED_Max (0x1UL)            /*!< Max enumerator value of STARTED field.                               */
62561   #define PDM_INTPEND_STARTED_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
62562   #define PDM_INTPEND_STARTED_Pending (0x1UL)        /*!< Read: Pending                                                        */
62563 
62564 /* STOPPED @Bit 1 : Read pending status of interrupt for event STOPPED */
62565   #define PDM_INTPEND_STOPPED_Pos (1UL)              /*!< Position of STOPPED field.                                           */
62566   #define PDM_INTPEND_STOPPED_Msk (0x1UL << PDM_INTPEND_STOPPED_Pos) /*!< Bit mask of STOPPED field.                           */
62567   #define PDM_INTPEND_STOPPED_Min (0x0UL)            /*!< Min enumerator value of STOPPED field.                               */
62568   #define PDM_INTPEND_STOPPED_Max (0x1UL)            /*!< Max enumerator value of STOPPED field.                               */
62569   #define PDM_INTPEND_STOPPED_NotPending (0x0UL)     /*!< Read: Not pending                                                    */
62570   #define PDM_INTPEND_STOPPED_Pending (0x1UL)        /*!< Read: Pending                                                        */
62571 
62572 /* END @Bit 2 : Read pending status of interrupt for event END */
62573   #define PDM_INTPEND_END_Pos (2UL)                  /*!< Position of END field.                                               */
62574   #define PDM_INTPEND_END_Msk (0x1UL << PDM_INTPEND_END_Pos) /*!< Bit mask of END field.                                       */
62575   #define PDM_INTPEND_END_Min (0x0UL)                /*!< Min enumerator value of END field.                                   */
62576   #define PDM_INTPEND_END_Max (0x1UL)                /*!< Max enumerator value of END field.                                   */
62577   #define PDM_INTPEND_END_NotPending (0x0UL)         /*!< Read: Not pending                                                    */
62578   #define PDM_INTPEND_END_Pending (0x1UL)            /*!< Read: Pending                                                        */
62579 
62580 
62581 /* PDM_ENABLE: PDM module enable register */
62582   #define PDM_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */
62583 
62584 /* ENABLE @Bit 0 : Enable or disable PDM module */
62585   #define PDM_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
62586   #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
62587   #define PDM_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
62588   #define PDM_ENABLE_ENABLE_Max (0x1UL)              /*!< Max enumerator value of ENABLE field.                                */
62589   #define PDM_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disable                                                              */
62590   #define PDM_ENABLE_ENABLE_Enabled (0x1UL)          /*!< Enable                                                               */
62591 
62592 
62593 /* PDM_PDMCLKCTRL: PDM clock generator control */
62594   #define PDM_PDMCLKCTRL_ResetValue (0x08400000UL)   /*!< Reset value of PDMCLKCTRL register.                                  */
62595 
62596 /* FREQ @Bits 0..31 : PDM_CLK frequency configuration. Enumerations are deprecated, use PDMCLKCTRL equation to find the register
62597                       value. The 12 least significant bits of the register are ignored and shall be set to zero. */
62598 
62599   #define PDM_PDMCLKCTRL_FREQ_Pos (0UL)              /*!< Position of FREQ field.                                              */
62600   #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field.                       */
62601   #define PDM_PDMCLKCTRL_FREQ_Min (0x8000000UL)      /*!< Min enumerator value of FREQ field.                                  */
62602   #define PDM_PDMCLKCTRL_FREQ_Max (0xA800000UL)      /*!< Max enumerator value of FREQ field.                                  */
62603   #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL)   /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz                                    */
62604   #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.  */
62605   #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL)   /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz                                    */
62606   #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL)   /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz                                    */
62607   #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL)   /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.  */
62608   #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL)   /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz                                    */
62609 
62610 
62611 /* PDM_MODE: Defines the routing of the connected PDM microphones' signals */
62612   #define PDM_MODE_ResetValue (0x00000000UL)         /*!< Reset value of MODE register.                                        */
62613 
62614 /* OPERATION @Bit 0 : Mono or stereo operation */
62615   #define PDM_MODE_OPERATION_Pos (0UL)               /*!< Position of OPERATION field.                                         */
62616   #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field.                           */
62617   #define PDM_MODE_OPERATION_Min (0x0UL)             /*!< Min enumerator value of OPERATION field.                             */
62618   #define PDM_MODE_OPERATION_Max (0x1UL)             /*!< Max enumerator value of OPERATION field.                             */
62619   #define PDM_MODE_OPERATION_Stereo (0x0UL)          /*!< Sample and store one pair (left + right) of 16-bit samples per RAM
62620                                                           word R=[31:16]; L=[15:0]*/
62621   #define PDM_MODE_OPERATION_Mono (0x1UL)            /*!< Sample and store two successive left samples (16 bits each) per RAM
62622                                                           word L1=[31:16]; L0=[15:0]*/
62623 
62624 /* EDGE @Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */
62625   #define PDM_MODE_EDGE_Pos (1UL)                    /*!< Position of EDGE field.                                              */
62626   #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field.                                          */
62627   #define PDM_MODE_EDGE_Min (0x0UL)                  /*!< Min enumerator value of EDGE field.                                  */
62628   #define PDM_MODE_EDGE_Max (0x1UL)                  /*!< Max enumerator value of EDGE field.                                  */
62629   #define PDM_MODE_EDGE_LeftFalling (0x0UL)          /*!< Left (or mono) is sampled on falling edge of PDM_CLK                 */
62630   #define PDM_MODE_EDGE_LeftRising (0x1UL)           /*!< Left (or mono) is sampled on rising edge of PDM_CLK                  */
62631 
62632 
62633 /* PDM_GAINL: Left output gain adjustment */
62634   #define PDM_GAINL_ResetValue (0x00000028UL)        /*!< Reset value of GAINL register.                                       */
62635 
62636 /* GAINL @Bits 0..6 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
62637                       0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust
62638                       0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
62639 
62640   #define PDM_GAINL_GAINL_Pos (0UL)                  /*!< Position of GAINL field.                                             */
62641   #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field.                                    */
62642   #define PDM_GAINL_GAINL_Min (0x0UL)                /*!< Min enumerator value of GAINL field.                                 */
62643   #define PDM_GAINL_GAINL_Max (0x50UL)               /*!< Max enumerator value of GAINL field.                                 */
62644   #define PDM_GAINL_GAINL_MinGain (0x00UL)           /*!< -20 dB gain adjustment (minimum)                                     */
62645   #define PDM_GAINL_GAINL_DefaultGain (0x28UL)       /*!< 0 dB gain adjustment                                                 */
62646   #define PDM_GAINL_GAINL_MaxGain (0x50UL)           /*!< +20 dB gain adjustment (maximum)                                     */
62647 
62648 
62649 /* PDM_GAINR: Right output gain adjustment */
62650   #define PDM_GAINR_ResetValue (0x00000028UL)        /*!< Reset value of GAINR register.                                       */
62651 
62652 /* GAINR @Bits 0..6 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
62653                       */
62654 
62655   #define PDM_GAINR_GAINR_Pos (0UL)                  /*!< Position of GAINR field.                                             */
62656   #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field.                                    */
62657   #define PDM_GAINR_GAINR_Min (0x0UL)                /*!< Min enumerator value of GAINR field.                                 */
62658   #define PDM_GAINR_GAINR_Max (0x50UL)               /*!< Max enumerator value of GAINR field.                                 */
62659   #define PDM_GAINR_GAINR_MinGain (0x00UL)           /*!< -20 dB gain adjustment (minimum)                                     */
62660   #define PDM_GAINR_GAINR_DefaultGain (0x28UL)       /*!< 0 dB gain adjustment                                                 */
62661   #define PDM_GAINR_GAINR_MaxGain (0x50UL)           /*!< +20 dB gain adjustment (maximum)                                     */
62662 
62663 
62664 /* PDM_RATIO: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
62665   #define PDM_RATIO_ResetValue (0x00000000UL)        /*!< Reset value of RATIO register.                                       */
62666 
62667 /* RATIO @Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
62668   #define PDM_RATIO_RATIO_Pos (0UL)                  /*!< Position of RATIO field.                                             */
62669   #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field.                                     */
62670   #define PDM_RATIO_RATIO_Min (0x0UL)                /*!< Min enumerator value of RATIO field.                                 */
62671   #define PDM_RATIO_RATIO_Max (0x1UL)                /*!< Max enumerator value of RATIO field.                                 */
62672   #define PDM_RATIO_RATIO_Ratio64 (0x0UL)            /*!< Ratio of 64                                                          */
62673   #define PDM_RATIO_RATIO_Ratio80 (0x1UL)            /*!< Ratio of 80                                                          */
62674 
62675 
62676 /* PDM_MCLKCONFIG: Master clock generator configuration */
62677   #define PDM_MCLKCONFIG_ResetValue (0x00000000UL)   /*!< Reset value of MCLKCONFIG register.                                  */
62678 
62679 /* SRC @Bit 0 : Master clock source selection */
62680   #define PDM_MCLKCONFIG_SRC_Pos (0UL)               /*!< Position of SRC field.                                               */
62681   #define PDM_MCLKCONFIG_SRC_Msk (0x1UL << PDM_MCLKCONFIG_SRC_Pos) /*!< Bit mask of SRC field.                                 */
62682   #define PDM_MCLKCONFIG_SRC_Min (0x0UL)             /*!< Min enumerator value of SRC field.                                   */
62683   #define PDM_MCLKCONFIG_SRC_Max (0x1UL)             /*!< Max enumerator value of SRC field.                                   */
62684   #define PDM_MCLKCONFIG_SRC_PCLK32M (0x0UL)         /*!< 32 MHz peripheral clock                                              */
62685   #define PDM_MCLKCONFIG_SRC_ACLK (0x1UL)            /*!< Audio PLL clock                                                      */
62686 
62687 
62688 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
62689 
62690 /* =========================================================================================================================== */
62691 /* ================                                           PPIB                                           ================ */
62692 /* =========================================================================================================================== */
62693 
62694 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
62695 
62696 /* ================================================== Struct PPIB_OVERFLOW =================================================== */
62697 /**
62698   * @brief OVERFLOW [PPIB_OVERFLOW] (unspecified)
62699   */
62700 typedef struct {
62701   __IOM uint32_t  SEND;                              /*!< (@ 0x00000000) The task overflow for SEND tasks using SUBSCRIBE_SEND.
62702                                                                          Write 0 to clear.*/
62703 } NRF_PPIB_OVERFLOW_Type;                            /*!< Size = 4 (0x004)                                                     */
62704 
62705 /* PPIB_OVERFLOW_SEND: The task overflow for SEND tasks using SUBSCRIBE_SEND. Write 0 to clear. */
62706   #define PPIB_OVERFLOW_SEND_ResetValue (0x00000000UL) /*!< Reset value of SEND register.                                      */
62707 
62708 /* SEND0 @Bit 0 : The status for tasks overflow at SUBSCRIBE_SEND[0]. */
62709   #define PPIB_OVERFLOW_SEND_SEND0_Pos (0UL)         /*!< Position of SEND0 field.                                             */
62710   #define PPIB_OVERFLOW_SEND_SEND0_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND0_Pos) /*!< Bit mask of SEND0 field.                   */
62711   #define PPIB_OVERFLOW_SEND_SEND0_Min (0x0UL)       /*!< Min enumerator value of SEND0 field.                                 */
62712   #define PPIB_OVERFLOW_SEND_SEND0_Max (0x1UL)       /*!< Max enumerator value of SEND0 field.                                 */
62713   #define PPIB_OVERFLOW_SEND_SEND0_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62714   #define PPIB_OVERFLOW_SEND_SEND0_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62715 
62716 /* SEND1 @Bit 1 : The status for tasks overflow at SUBSCRIBE_SEND[1]. */
62717   #define PPIB_OVERFLOW_SEND_SEND1_Pos (1UL)         /*!< Position of SEND1 field.                                             */
62718   #define PPIB_OVERFLOW_SEND_SEND1_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND1_Pos) /*!< Bit mask of SEND1 field.                   */
62719   #define PPIB_OVERFLOW_SEND_SEND1_Min (0x0UL)       /*!< Min enumerator value of SEND1 field.                                 */
62720   #define PPIB_OVERFLOW_SEND_SEND1_Max (0x1UL)       /*!< Max enumerator value of SEND1 field.                                 */
62721   #define PPIB_OVERFLOW_SEND_SEND1_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62722   #define PPIB_OVERFLOW_SEND_SEND1_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62723 
62724 /* SEND2 @Bit 2 : The status for tasks overflow at SUBSCRIBE_SEND[2]. */
62725   #define PPIB_OVERFLOW_SEND_SEND2_Pos (2UL)         /*!< Position of SEND2 field.                                             */
62726   #define PPIB_OVERFLOW_SEND_SEND2_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND2_Pos) /*!< Bit mask of SEND2 field.                   */
62727   #define PPIB_OVERFLOW_SEND_SEND2_Min (0x0UL)       /*!< Min enumerator value of SEND2 field.                                 */
62728   #define PPIB_OVERFLOW_SEND_SEND2_Max (0x1UL)       /*!< Max enumerator value of SEND2 field.                                 */
62729   #define PPIB_OVERFLOW_SEND_SEND2_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62730   #define PPIB_OVERFLOW_SEND_SEND2_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62731 
62732 /* SEND3 @Bit 3 : The status for tasks overflow at SUBSCRIBE_SEND[3]. */
62733   #define PPIB_OVERFLOW_SEND_SEND3_Pos (3UL)         /*!< Position of SEND3 field.                                             */
62734   #define PPIB_OVERFLOW_SEND_SEND3_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND3_Pos) /*!< Bit mask of SEND3 field.                   */
62735   #define PPIB_OVERFLOW_SEND_SEND3_Min (0x0UL)       /*!< Min enumerator value of SEND3 field.                                 */
62736   #define PPIB_OVERFLOW_SEND_SEND3_Max (0x1UL)       /*!< Max enumerator value of SEND3 field.                                 */
62737   #define PPIB_OVERFLOW_SEND_SEND3_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62738   #define PPIB_OVERFLOW_SEND_SEND3_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62739 
62740 /* SEND4 @Bit 4 : The status for tasks overflow at SUBSCRIBE_SEND[4]. */
62741   #define PPIB_OVERFLOW_SEND_SEND4_Pos (4UL)         /*!< Position of SEND4 field.                                             */
62742   #define PPIB_OVERFLOW_SEND_SEND4_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND4_Pos) /*!< Bit mask of SEND4 field.                   */
62743   #define PPIB_OVERFLOW_SEND_SEND4_Min (0x0UL)       /*!< Min enumerator value of SEND4 field.                                 */
62744   #define PPIB_OVERFLOW_SEND_SEND4_Max (0x1UL)       /*!< Max enumerator value of SEND4 field.                                 */
62745   #define PPIB_OVERFLOW_SEND_SEND4_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62746   #define PPIB_OVERFLOW_SEND_SEND4_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62747 
62748 /* SEND5 @Bit 5 : The status for tasks overflow at SUBSCRIBE_SEND[5]. */
62749   #define PPIB_OVERFLOW_SEND_SEND5_Pos (5UL)         /*!< Position of SEND5 field.                                             */
62750   #define PPIB_OVERFLOW_SEND_SEND5_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND5_Pos) /*!< Bit mask of SEND5 field.                   */
62751   #define PPIB_OVERFLOW_SEND_SEND5_Min (0x0UL)       /*!< Min enumerator value of SEND5 field.                                 */
62752   #define PPIB_OVERFLOW_SEND_SEND5_Max (0x1UL)       /*!< Max enumerator value of SEND5 field.                                 */
62753   #define PPIB_OVERFLOW_SEND_SEND5_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62754   #define PPIB_OVERFLOW_SEND_SEND5_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62755 
62756 /* SEND6 @Bit 6 : The status for tasks overflow at SUBSCRIBE_SEND[6]. */
62757   #define PPIB_OVERFLOW_SEND_SEND6_Pos (6UL)         /*!< Position of SEND6 field.                                             */
62758   #define PPIB_OVERFLOW_SEND_SEND6_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND6_Pos) /*!< Bit mask of SEND6 field.                   */
62759   #define PPIB_OVERFLOW_SEND_SEND6_Min (0x0UL)       /*!< Min enumerator value of SEND6 field.                                 */
62760   #define PPIB_OVERFLOW_SEND_SEND6_Max (0x1UL)       /*!< Max enumerator value of SEND6 field.                                 */
62761   #define PPIB_OVERFLOW_SEND_SEND6_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62762   #define PPIB_OVERFLOW_SEND_SEND6_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62763 
62764 /* SEND7 @Bit 7 : The status for tasks overflow at SUBSCRIBE_SEND[7]. */
62765   #define PPIB_OVERFLOW_SEND_SEND7_Pos (7UL)         /*!< Position of SEND7 field.                                             */
62766   #define PPIB_OVERFLOW_SEND_SEND7_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND7_Pos) /*!< Bit mask of SEND7 field.                   */
62767   #define PPIB_OVERFLOW_SEND_SEND7_Min (0x0UL)       /*!< Min enumerator value of SEND7 field.                                 */
62768   #define PPIB_OVERFLOW_SEND_SEND7_Max (0x1UL)       /*!< Max enumerator value of SEND7 field.                                 */
62769   #define PPIB_OVERFLOW_SEND_SEND7_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62770   #define PPIB_OVERFLOW_SEND_SEND7_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62771 
62772 /* SEND8 @Bit 8 : The status for tasks overflow at SUBSCRIBE_SEND[8]. */
62773   #define PPIB_OVERFLOW_SEND_SEND8_Pos (8UL)         /*!< Position of SEND8 field.                                             */
62774   #define PPIB_OVERFLOW_SEND_SEND8_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND8_Pos) /*!< Bit mask of SEND8 field.                   */
62775   #define PPIB_OVERFLOW_SEND_SEND8_Min (0x0UL)       /*!< Min enumerator value of SEND8 field.                                 */
62776   #define PPIB_OVERFLOW_SEND_SEND8_Max (0x1UL)       /*!< Max enumerator value of SEND8 field.                                 */
62777   #define PPIB_OVERFLOW_SEND_SEND8_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62778   #define PPIB_OVERFLOW_SEND_SEND8_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62779 
62780 /* SEND9 @Bit 9 : The status for tasks overflow at SUBSCRIBE_SEND[9]. */
62781   #define PPIB_OVERFLOW_SEND_SEND9_Pos (9UL)         /*!< Position of SEND9 field.                                             */
62782   #define PPIB_OVERFLOW_SEND_SEND9_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND9_Pos) /*!< Bit mask of SEND9 field.                   */
62783   #define PPIB_OVERFLOW_SEND_SEND9_Min (0x0UL)       /*!< Min enumerator value of SEND9 field.                                 */
62784   #define PPIB_OVERFLOW_SEND_SEND9_Max (0x1UL)       /*!< Max enumerator value of SEND9 field.                                 */
62785   #define PPIB_OVERFLOW_SEND_SEND9_Overflow (0x1UL)  /*!< Task overflow is happened.                                           */
62786   #define PPIB_OVERFLOW_SEND_SEND9_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                      */
62787 
62788 /* SEND10 @Bit 10 : The status for tasks overflow at SUBSCRIBE_SEND[10]. */
62789   #define PPIB_OVERFLOW_SEND_SEND10_Pos (10UL)       /*!< Position of SEND10 field.                                            */
62790   #define PPIB_OVERFLOW_SEND_SEND10_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND10_Pos) /*!< Bit mask of SEND10 field.                */
62791   #define PPIB_OVERFLOW_SEND_SEND10_Min (0x0UL)      /*!< Min enumerator value of SEND10 field.                                */
62792   #define PPIB_OVERFLOW_SEND_SEND10_Max (0x1UL)      /*!< Max enumerator value of SEND10 field.                                */
62793   #define PPIB_OVERFLOW_SEND_SEND10_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62794   #define PPIB_OVERFLOW_SEND_SEND10_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62795 
62796 /* SEND11 @Bit 11 : The status for tasks overflow at SUBSCRIBE_SEND[11]. */
62797   #define PPIB_OVERFLOW_SEND_SEND11_Pos (11UL)       /*!< Position of SEND11 field.                                            */
62798   #define PPIB_OVERFLOW_SEND_SEND11_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND11_Pos) /*!< Bit mask of SEND11 field.                */
62799   #define PPIB_OVERFLOW_SEND_SEND11_Min (0x0UL)      /*!< Min enumerator value of SEND11 field.                                */
62800   #define PPIB_OVERFLOW_SEND_SEND11_Max (0x1UL)      /*!< Max enumerator value of SEND11 field.                                */
62801   #define PPIB_OVERFLOW_SEND_SEND11_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62802   #define PPIB_OVERFLOW_SEND_SEND11_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62803 
62804 /* SEND12 @Bit 12 : The status for tasks overflow at SUBSCRIBE_SEND[12]. */
62805   #define PPIB_OVERFLOW_SEND_SEND12_Pos (12UL)       /*!< Position of SEND12 field.                                            */
62806   #define PPIB_OVERFLOW_SEND_SEND12_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND12_Pos) /*!< Bit mask of SEND12 field.                */
62807   #define PPIB_OVERFLOW_SEND_SEND12_Min (0x0UL)      /*!< Min enumerator value of SEND12 field.                                */
62808   #define PPIB_OVERFLOW_SEND_SEND12_Max (0x1UL)      /*!< Max enumerator value of SEND12 field.                                */
62809   #define PPIB_OVERFLOW_SEND_SEND12_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62810   #define PPIB_OVERFLOW_SEND_SEND12_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62811 
62812 /* SEND13 @Bit 13 : The status for tasks overflow at SUBSCRIBE_SEND[13]. */
62813   #define PPIB_OVERFLOW_SEND_SEND13_Pos (13UL)       /*!< Position of SEND13 field.                                            */
62814   #define PPIB_OVERFLOW_SEND_SEND13_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND13_Pos) /*!< Bit mask of SEND13 field.                */
62815   #define PPIB_OVERFLOW_SEND_SEND13_Min (0x0UL)      /*!< Min enumerator value of SEND13 field.                                */
62816   #define PPIB_OVERFLOW_SEND_SEND13_Max (0x1UL)      /*!< Max enumerator value of SEND13 field.                                */
62817   #define PPIB_OVERFLOW_SEND_SEND13_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62818   #define PPIB_OVERFLOW_SEND_SEND13_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62819 
62820 /* SEND14 @Bit 14 : The status for tasks overflow at SUBSCRIBE_SEND[14]. */
62821   #define PPIB_OVERFLOW_SEND_SEND14_Pos (14UL)       /*!< Position of SEND14 field.                                            */
62822   #define PPIB_OVERFLOW_SEND_SEND14_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND14_Pos) /*!< Bit mask of SEND14 field.                */
62823   #define PPIB_OVERFLOW_SEND_SEND14_Min (0x0UL)      /*!< Min enumerator value of SEND14 field.                                */
62824   #define PPIB_OVERFLOW_SEND_SEND14_Max (0x1UL)      /*!< Max enumerator value of SEND14 field.                                */
62825   #define PPIB_OVERFLOW_SEND_SEND14_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62826   #define PPIB_OVERFLOW_SEND_SEND14_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62827 
62828 /* SEND15 @Bit 15 : The status for tasks overflow at SUBSCRIBE_SEND[15]. */
62829   #define PPIB_OVERFLOW_SEND_SEND15_Pos (15UL)       /*!< Position of SEND15 field.                                            */
62830   #define PPIB_OVERFLOW_SEND_SEND15_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND15_Pos) /*!< Bit mask of SEND15 field.                */
62831   #define PPIB_OVERFLOW_SEND_SEND15_Min (0x0UL)      /*!< Min enumerator value of SEND15 field.                                */
62832   #define PPIB_OVERFLOW_SEND_SEND15_Max (0x1UL)      /*!< Max enumerator value of SEND15 field.                                */
62833   #define PPIB_OVERFLOW_SEND_SEND15_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62834   #define PPIB_OVERFLOW_SEND_SEND15_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62835 
62836 /* SEND16 @Bit 16 : The status for tasks overflow at SUBSCRIBE_SEND[16]. */
62837   #define PPIB_OVERFLOW_SEND_SEND16_Pos (16UL)       /*!< Position of SEND16 field.                                            */
62838   #define PPIB_OVERFLOW_SEND_SEND16_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND16_Pos) /*!< Bit mask of SEND16 field.                */
62839   #define PPIB_OVERFLOW_SEND_SEND16_Min (0x0UL)      /*!< Min enumerator value of SEND16 field.                                */
62840   #define PPIB_OVERFLOW_SEND_SEND16_Max (0x1UL)      /*!< Max enumerator value of SEND16 field.                                */
62841   #define PPIB_OVERFLOW_SEND_SEND16_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62842   #define PPIB_OVERFLOW_SEND_SEND16_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62843 
62844 /* SEND17 @Bit 17 : The status for tasks overflow at SUBSCRIBE_SEND[17]. */
62845   #define PPIB_OVERFLOW_SEND_SEND17_Pos (17UL)       /*!< Position of SEND17 field.                                            */
62846   #define PPIB_OVERFLOW_SEND_SEND17_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND17_Pos) /*!< Bit mask of SEND17 field.                */
62847   #define PPIB_OVERFLOW_SEND_SEND17_Min (0x0UL)      /*!< Min enumerator value of SEND17 field.                                */
62848   #define PPIB_OVERFLOW_SEND_SEND17_Max (0x1UL)      /*!< Max enumerator value of SEND17 field.                                */
62849   #define PPIB_OVERFLOW_SEND_SEND17_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62850   #define PPIB_OVERFLOW_SEND_SEND17_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62851 
62852 /* SEND18 @Bit 18 : The status for tasks overflow at SUBSCRIBE_SEND[18]. */
62853   #define PPIB_OVERFLOW_SEND_SEND18_Pos (18UL)       /*!< Position of SEND18 field.                                            */
62854   #define PPIB_OVERFLOW_SEND_SEND18_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND18_Pos) /*!< Bit mask of SEND18 field.                */
62855   #define PPIB_OVERFLOW_SEND_SEND18_Min (0x0UL)      /*!< Min enumerator value of SEND18 field.                                */
62856   #define PPIB_OVERFLOW_SEND_SEND18_Max (0x1UL)      /*!< Max enumerator value of SEND18 field.                                */
62857   #define PPIB_OVERFLOW_SEND_SEND18_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62858   #define PPIB_OVERFLOW_SEND_SEND18_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62859 
62860 /* SEND19 @Bit 19 : The status for tasks overflow at SUBSCRIBE_SEND[19]. */
62861   #define PPIB_OVERFLOW_SEND_SEND19_Pos (19UL)       /*!< Position of SEND19 field.                                            */
62862   #define PPIB_OVERFLOW_SEND_SEND19_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND19_Pos) /*!< Bit mask of SEND19 field.                */
62863   #define PPIB_OVERFLOW_SEND_SEND19_Min (0x0UL)      /*!< Min enumerator value of SEND19 field.                                */
62864   #define PPIB_OVERFLOW_SEND_SEND19_Max (0x1UL)      /*!< Max enumerator value of SEND19 field.                                */
62865   #define PPIB_OVERFLOW_SEND_SEND19_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62866   #define PPIB_OVERFLOW_SEND_SEND19_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62867 
62868 /* SEND20 @Bit 20 : The status for tasks overflow at SUBSCRIBE_SEND[20]. */
62869   #define PPIB_OVERFLOW_SEND_SEND20_Pos (20UL)       /*!< Position of SEND20 field.                                            */
62870   #define PPIB_OVERFLOW_SEND_SEND20_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND20_Pos) /*!< Bit mask of SEND20 field.                */
62871   #define PPIB_OVERFLOW_SEND_SEND20_Min (0x0UL)      /*!< Min enumerator value of SEND20 field.                                */
62872   #define PPIB_OVERFLOW_SEND_SEND20_Max (0x1UL)      /*!< Max enumerator value of SEND20 field.                                */
62873   #define PPIB_OVERFLOW_SEND_SEND20_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62874   #define PPIB_OVERFLOW_SEND_SEND20_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62875 
62876 /* SEND21 @Bit 21 : The status for tasks overflow at SUBSCRIBE_SEND[21]. */
62877   #define PPIB_OVERFLOW_SEND_SEND21_Pos (21UL)       /*!< Position of SEND21 field.                                            */
62878   #define PPIB_OVERFLOW_SEND_SEND21_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND21_Pos) /*!< Bit mask of SEND21 field.                */
62879   #define PPIB_OVERFLOW_SEND_SEND21_Min (0x0UL)      /*!< Min enumerator value of SEND21 field.                                */
62880   #define PPIB_OVERFLOW_SEND_SEND21_Max (0x1UL)      /*!< Max enumerator value of SEND21 field.                                */
62881   #define PPIB_OVERFLOW_SEND_SEND21_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62882   #define PPIB_OVERFLOW_SEND_SEND21_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62883 
62884 /* SEND22 @Bit 22 : The status for tasks overflow at SUBSCRIBE_SEND[22]. */
62885   #define PPIB_OVERFLOW_SEND_SEND22_Pos (22UL)       /*!< Position of SEND22 field.                                            */
62886   #define PPIB_OVERFLOW_SEND_SEND22_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND22_Pos) /*!< Bit mask of SEND22 field.                */
62887   #define PPIB_OVERFLOW_SEND_SEND22_Min (0x0UL)      /*!< Min enumerator value of SEND22 field.                                */
62888   #define PPIB_OVERFLOW_SEND_SEND22_Max (0x1UL)      /*!< Max enumerator value of SEND22 field.                                */
62889   #define PPIB_OVERFLOW_SEND_SEND22_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62890   #define PPIB_OVERFLOW_SEND_SEND22_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62891 
62892 /* SEND23 @Bit 23 : The status for tasks overflow at SUBSCRIBE_SEND[23]. */
62893   #define PPIB_OVERFLOW_SEND_SEND23_Pos (23UL)       /*!< Position of SEND23 field.                                            */
62894   #define PPIB_OVERFLOW_SEND_SEND23_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND23_Pos) /*!< Bit mask of SEND23 field.                */
62895   #define PPIB_OVERFLOW_SEND_SEND23_Min (0x0UL)      /*!< Min enumerator value of SEND23 field.                                */
62896   #define PPIB_OVERFLOW_SEND_SEND23_Max (0x1UL)      /*!< Max enumerator value of SEND23 field.                                */
62897   #define PPIB_OVERFLOW_SEND_SEND23_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62898   #define PPIB_OVERFLOW_SEND_SEND23_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62899 
62900 /* SEND24 @Bit 24 : The status for tasks overflow at SUBSCRIBE_SEND[24]. */
62901   #define PPIB_OVERFLOW_SEND_SEND24_Pos (24UL)       /*!< Position of SEND24 field.                                            */
62902   #define PPIB_OVERFLOW_SEND_SEND24_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND24_Pos) /*!< Bit mask of SEND24 field.                */
62903   #define PPIB_OVERFLOW_SEND_SEND24_Min (0x0UL)      /*!< Min enumerator value of SEND24 field.                                */
62904   #define PPIB_OVERFLOW_SEND_SEND24_Max (0x1UL)      /*!< Max enumerator value of SEND24 field.                                */
62905   #define PPIB_OVERFLOW_SEND_SEND24_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62906   #define PPIB_OVERFLOW_SEND_SEND24_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62907 
62908 /* SEND25 @Bit 25 : The status for tasks overflow at SUBSCRIBE_SEND[25]. */
62909   #define PPIB_OVERFLOW_SEND_SEND25_Pos (25UL)       /*!< Position of SEND25 field.                                            */
62910   #define PPIB_OVERFLOW_SEND_SEND25_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND25_Pos) /*!< Bit mask of SEND25 field.                */
62911   #define PPIB_OVERFLOW_SEND_SEND25_Min (0x0UL)      /*!< Min enumerator value of SEND25 field.                                */
62912   #define PPIB_OVERFLOW_SEND_SEND25_Max (0x1UL)      /*!< Max enumerator value of SEND25 field.                                */
62913   #define PPIB_OVERFLOW_SEND_SEND25_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62914   #define PPIB_OVERFLOW_SEND_SEND25_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62915 
62916 /* SEND26 @Bit 26 : The status for tasks overflow at SUBSCRIBE_SEND[26]. */
62917   #define PPIB_OVERFLOW_SEND_SEND26_Pos (26UL)       /*!< Position of SEND26 field.                                            */
62918   #define PPIB_OVERFLOW_SEND_SEND26_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND26_Pos) /*!< Bit mask of SEND26 field.                */
62919   #define PPIB_OVERFLOW_SEND_SEND26_Min (0x0UL)      /*!< Min enumerator value of SEND26 field.                                */
62920   #define PPIB_OVERFLOW_SEND_SEND26_Max (0x1UL)      /*!< Max enumerator value of SEND26 field.                                */
62921   #define PPIB_OVERFLOW_SEND_SEND26_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62922   #define PPIB_OVERFLOW_SEND_SEND26_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62923 
62924 /* SEND27 @Bit 27 : The status for tasks overflow at SUBSCRIBE_SEND[27]. */
62925   #define PPIB_OVERFLOW_SEND_SEND27_Pos (27UL)       /*!< Position of SEND27 field.                                            */
62926   #define PPIB_OVERFLOW_SEND_SEND27_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND27_Pos) /*!< Bit mask of SEND27 field.                */
62927   #define PPIB_OVERFLOW_SEND_SEND27_Min (0x0UL)      /*!< Min enumerator value of SEND27 field.                                */
62928   #define PPIB_OVERFLOW_SEND_SEND27_Max (0x1UL)      /*!< Max enumerator value of SEND27 field.                                */
62929   #define PPIB_OVERFLOW_SEND_SEND27_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62930   #define PPIB_OVERFLOW_SEND_SEND27_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62931 
62932 /* SEND28 @Bit 28 : The status for tasks overflow at SUBSCRIBE_SEND[28]. */
62933   #define PPIB_OVERFLOW_SEND_SEND28_Pos (28UL)       /*!< Position of SEND28 field.                                            */
62934   #define PPIB_OVERFLOW_SEND_SEND28_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND28_Pos) /*!< Bit mask of SEND28 field.                */
62935   #define PPIB_OVERFLOW_SEND_SEND28_Min (0x0UL)      /*!< Min enumerator value of SEND28 field.                                */
62936   #define PPIB_OVERFLOW_SEND_SEND28_Max (0x1UL)      /*!< Max enumerator value of SEND28 field.                                */
62937   #define PPIB_OVERFLOW_SEND_SEND28_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62938   #define PPIB_OVERFLOW_SEND_SEND28_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62939 
62940 /* SEND29 @Bit 29 : The status for tasks overflow at SUBSCRIBE_SEND[29]. */
62941   #define PPIB_OVERFLOW_SEND_SEND29_Pos (29UL)       /*!< Position of SEND29 field.                                            */
62942   #define PPIB_OVERFLOW_SEND_SEND29_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND29_Pos) /*!< Bit mask of SEND29 field.                */
62943   #define PPIB_OVERFLOW_SEND_SEND29_Min (0x0UL)      /*!< Min enumerator value of SEND29 field.                                */
62944   #define PPIB_OVERFLOW_SEND_SEND29_Max (0x1UL)      /*!< Max enumerator value of SEND29 field.                                */
62945   #define PPIB_OVERFLOW_SEND_SEND29_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62946   #define PPIB_OVERFLOW_SEND_SEND29_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62947 
62948 /* SEND30 @Bit 30 : The status for tasks overflow at SUBSCRIBE_SEND[30]. */
62949   #define PPIB_OVERFLOW_SEND_SEND30_Pos (30UL)       /*!< Position of SEND30 field.                                            */
62950   #define PPIB_OVERFLOW_SEND_SEND30_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND30_Pos) /*!< Bit mask of SEND30 field.                */
62951   #define PPIB_OVERFLOW_SEND_SEND30_Min (0x0UL)      /*!< Min enumerator value of SEND30 field.                                */
62952   #define PPIB_OVERFLOW_SEND_SEND30_Max (0x1UL)      /*!< Max enumerator value of SEND30 field.                                */
62953   #define PPIB_OVERFLOW_SEND_SEND30_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62954   #define PPIB_OVERFLOW_SEND_SEND30_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62955 
62956 /* SEND31 @Bit 31 : The status for tasks overflow at SUBSCRIBE_SEND[31]. */
62957   #define PPIB_OVERFLOW_SEND_SEND31_Pos (31UL)       /*!< Position of SEND31 field.                                            */
62958   #define PPIB_OVERFLOW_SEND_SEND31_Msk (0x1UL << PPIB_OVERFLOW_SEND_SEND31_Pos) /*!< Bit mask of SEND31 field.                */
62959   #define PPIB_OVERFLOW_SEND_SEND31_Min (0x0UL)      /*!< Min enumerator value of SEND31 field.                                */
62960   #define PPIB_OVERFLOW_SEND_SEND31_Max (0x1UL)      /*!< Max enumerator value of SEND31 field.                                */
62961   #define PPIB_OVERFLOW_SEND_SEND31_Overflow (0x1UL) /*!< Task overflow is happened.                                           */
62962   #define PPIB_OVERFLOW_SEND_SEND31_NoOverflow (0x0UL) /*!< Task overflow is not happened.                                     */
62963 
62964 
62965 /* ======================================================= Struct PPIB ======================================================= */
62966 /**
62967   * @brief PPIB APB registers
62968   */
62969   typedef struct {                                   /*!< PPIB Structure                                                       */
62970     __OM uint32_t TASKS_SEND[32];                    /*!< (@ 0x00000000) This task is unused, but the PPIB provides the
62971                                                                          SUBSCRIBE task to connect SEND [n] task.*/
62972     __IOM uint32_t SUBSCRIBE_SEND[32];               /*!< (@ 0x00000080) Subscribe configuration for task SEND[n]              */
62973     __IOM uint32_t EVENTS_RECEIVE[32];               /*!< (@ 0x00000100) This event is unused, but the PPIB provides the PUBLISH
62974                                                                          event to connect RECEIVE [n] event.*/
62975     __IOM uint32_t PUBLISH_RECEIVE[32];              /*!< (@ 0x00000180) Publish configuration for event RECEIVE[n]            */
62976     __IM uint32_t RESERVED[128];
62977     __IOM NRF_PPIB_OVERFLOW_Type OVERFLOW;           /*!< (@ 0x00000400) (unspecified)                                         */
62978   } NRF_PPIB_Type;                                   /*!< Size = 1028 (0x404)                                                  */
62979 
62980 /* PPIB_TASKS_SEND: This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. */
62981   #define PPIB_TASKS_SEND_MaxCount (32UL)            /*!< Max size of TASKS_SEND[32] array.                                    */
62982   #define PPIB_TASKS_SEND_MaxIndex (31UL)            /*!< Max index of TASKS_SEND[32] array.                                   */
62983   #define PPIB_TASKS_SEND_MinIndex (0UL)             /*!< Min index of TASKS_SEND[32] array.                                   */
62984   #define PPIB_TASKS_SEND_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_SEND[32] register.                              */
62985 
62986 /* TASKS_SEND @Bit 0 : This task is unused, but the PPIB provides the SUBSCRIBE task to connect SEND [n] task. */
62987   #define PPIB_TASKS_SEND_TASKS_SEND_Pos (0UL)       /*!< Position of TASKS_SEND field.                                        */
62988   #define PPIB_TASKS_SEND_TASKS_SEND_Msk (0x1UL << PPIB_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field.          */
62989   #define PPIB_TASKS_SEND_TASKS_SEND_Min (0x1UL)     /*!< Min enumerator value of TASKS_SEND field.                            */
62990   #define PPIB_TASKS_SEND_TASKS_SEND_Max (0x1UL)     /*!< Max enumerator value of TASKS_SEND field.                            */
62991   #define PPIB_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task                                                         */
62992 
62993 
62994 /* PPIB_SUBSCRIBE_SEND: Subscribe configuration for task SEND[n] */
62995   #define PPIB_SUBSCRIBE_SEND_MaxCount (32UL)        /*!< Max size of SUBSCRIBE_SEND[32] array.                                */
62996   #define PPIB_SUBSCRIBE_SEND_MaxIndex (31UL)        /*!< Max index of SUBSCRIBE_SEND[32] array.                               */
62997   #define PPIB_SUBSCRIBE_SEND_MinIndex (0UL)         /*!< Min index of SUBSCRIBE_SEND[32] array.                               */
62998   #define PPIB_SUBSCRIBE_SEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SEND[32] register.                       */
62999 
63000 /* CHIDX @Bits 0..7 : DPPI channel that task SEND[n] will subscribe to */
63001   #define PPIB_SUBSCRIBE_SEND_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
63002   #define PPIB_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << PPIB_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
63003   #define PPIB_SUBSCRIBE_SEND_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
63004   #define PPIB_SUBSCRIBE_SEND_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
63005 
63006 /* EN @Bit 31 : (unspecified) */
63007   #define PPIB_SUBSCRIBE_SEND_EN_Pos (31UL)          /*!< Position of EN field.                                                */
63008   #define PPIB_SUBSCRIBE_SEND_EN_Msk (0x1UL << PPIB_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field.                          */
63009   #define PPIB_SUBSCRIBE_SEND_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
63010   #define PPIB_SUBSCRIBE_SEND_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
63011   #define PPIB_SUBSCRIBE_SEND_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
63012   #define PPIB_SUBSCRIBE_SEND_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
63013 
63014 
63015 /* PPIB_EVENTS_RECEIVE: This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. */
63016   #define PPIB_EVENTS_RECEIVE_MaxCount (32UL)        /*!< Max size of EVENTS_RECEIVE[32] array.                                */
63017   #define PPIB_EVENTS_RECEIVE_MaxIndex (31UL)        /*!< Max index of EVENTS_RECEIVE[32] array.                               */
63018   #define PPIB_EVENTS_RECEIVE_MinIndex (0UL)         /*!< Min index of EVENTS_RECEIVE[32] array.                               */
63019   #define PPIB_EVENTS_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RECEIVE[32] register.                       */
63020 
63021 /* EVENTS_RECEIVE @Bit 0 : This event is unused, but the PPIB provides the PUBLISH event to connect RECEIVE [n] event. */
63022   #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field.                                  */
63023   #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of
63024                                                                             EVENTS_RECEIVE field.*/
63025   #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RECEIVE field.                    */
63026   #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RECEIVE field.                    */
63027   #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated                                     */
63028   #define PPIB_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated                                            */
63029 
63030 
63031 /* PPIB_PUBLISH_RECEIVE: Publish configuration for event RECEIVE[n] */
63032   #define PPIB_PUBLISH_RECEIVE_MaxCount (32UL)       /*!< Max size of PUBLISH_RECEIVE[32] array.                               */
63033   #define PPIB_PUBLISH_RECEIVE_MaxIndex (31UL)       /*!< Max index of PUBLISH_RECEIVE[32] array.                              */
63034   #define PPIB_PUBLISH_RECEIVE_MinIndex (0UL)        /*!< Min index of PUBLISH_RECEIVE[32] array.                              */
63035   #define PPIB_PUBLISH_RECEIVE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RECEIVE[32] register.                     */
63036 
63037 /* CHIDX @Bits 0..7 : DPPI channel that event RECEIVE[n] will publish to */
63038   #define PPIB_PUBLISH_RECEIVE_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
63039   #define PPIB_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << PPIB_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
63040   #define PPIB_PUBLISH_RECEIVE_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
63041   #define PPIB_PUBLISH_RECEIVE_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
63042 
63043 /* EN @Bit 31 : (unspecified) */
63044   #define PPIB_PUBLISH_RECEIVE_EN_Pos (31UL)         /*!< Position of EN field.                                                */
63045   #define PPIB_PUBLISH_RECEIVE_EN_Msk (0x1UL << PPIB_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field.                        */
63046   #define PPIB_PUBLISH_RECEIVE_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
63047   #define PPIB_PUBLISH_RECEIVE_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
63048   #define PPIB_PUBLISH_RECEIVE_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
63049   #define PPIB_PUBLISH_RECEIVE_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
63050 
63051 
63052 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
63053 
63054 /* =========================================================================================================================== */
63055 /* ================                                            PWM                                            ================ */
63056 /* =========================================================================================================================== */
63057 
63058 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
63059 
63060 /* ===================================================== Struct PWM_SEQ ====================================================== */
63061 /**
63062   * @brief SEQ [PWM_SEQ] (unspecified)
63063   */
63064 typedef struct {
63065   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Beginning address in RAM of this sequence             */
63066   __IOM uint32_t  CNT;                               /*!< (@ 0x00000004) Number of values (duty cycles) in this sequence       */
63067   __IOM uint32_t  REFRESH;                           /*!< (@ 0x00000008) Number of additional PWM periods between samples loaded
63068                                                                          into compare register*/
63069   __IOM uint32_t  ENDDELAY;                          /*!< (@ 0x0000000C) Time added after the sequence                         */
63070   __IM  uint32_t  RESERVED[4];
63071 } NRF_PWM_SEQ_Type;                                  /*!< Size = 32 (0x020)                                                    */
63072   #define PWM_SEQ_MaxCount (2UL)                     /*!< Size of SEQ[2] array.                                                */
63073   #define PWM_SEQ_MaxIndex (1UL)                     /*!< Max index of SEQ[2] array.                                           */
63074   #define PWM_SEQ_MinIndex (0UL)                     /*!< Min index of SEQ[2] array.                                           */
63075 
63076 /* PWM_SEQ_PTR: Beginning address in RAM of this sequence */
63077   #define PWM_SEQ_PTR_ResetValue (0x00000000UL)      /*!< Reset value of PTR register.                                         */
63078 
63079 /* PTR @Bits 0..31 : Beginning address in RAM of this sequence */
63080   #define PWM_SEQ_PTR_PTR_Pos (0UL)                  /*!< Position of PTR field.                                               */
63081   #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field.                                */
63082 
63083 
63084 /* PWM_SEQ_CNT: Number of values (duty cycles) in this sequence */
63085   #define PWM_SEQ_CNT_ResetValue (0x00000000UL)      /*!< Reset value of CNT register.                                         */
63086 
63087 /* CNT @Bits 0..14 : Number of values (duty cycles) in this sequence */
63088   #define PWM_SEQ_CNT_CNT_Pos (0UL)                  /*!< Position of CNT field.                                               */
63089   #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field.                                    */
63090   #define PWM_SEQ_CNT_CNT_Min (0x0UL)                /*!< Min enumerator value of CNT field.                                   */
63091   #define PWM_SEQ_CNT_CNT_Max (0x0UL)                /*!< Max enumerator value of CNT field.                                   */
63092   #define PWM_SEQ_CNT_CNT_Disabled (0x0000UL)        /*!< Sequence is disabled, and shall not be started as it is empty        */
63093 
63094 
63095 /* PWM_SEQ_REFRESH: Number of additional PWM periods between samples loaded into compare register */
63096   #define PWM_SEQ_REFRESH_ResetValue (0x00000001UL)  /*!< Reset value of REFRESH register.                                     */
63097 
63098 /* CNT @Bits 0..23 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM
63099                      periods) */
63100 
63101   #define PWM_SEQ_REFRESH_CNT_Pos (0UL)              /*!< Position of CNT field.                                               */
63102   #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field.                          */
63103   #define PWM_SEQ_REFRESH_CNT_Min (0x0UL)            /*!< Min enumerator value of CNT field.                                   */
63104   #define PWM_SEQ_REFRESH_CNT_Max (0x0UL)            /*!< Max enumerator value of CNT field.                                   */
63105   #define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period                                             */
63106 
63107 
63108 /* PWM_SEQ_ENDDELAY: Time added after the sequence */
63109   #define PWM_SEQ_ENDDELAY_ResetValue (0x00000000UL) /*!< Reset value of ENDDELAY register.                                    */
63110 
63111 /* CNT @Bits 0..23 : Time added after the sequence in PWM periods */
63112   #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL)             /*!< Position of CNT field.                                               */
63113   #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field.                        */
63114 
63115 
63116 
63117 /* ===================================================== Struct PWM_PSEL ===================================================== */
63118 /**
63119   * @brief PSEL [PWM_PSEL] (unspecified)
63120   */
63121 typedef struct {
63122   __IOM uint32_t  OUT[4];                            /*!< (@ 0x00000000) Output pin select for PWM channel n                   */
63123 } NRF_PWM_PSEL_Type;                                 /*!< Size = 16 (0x010)                                                    */
63124 
63125 /* PWM_PSEL_OUT: Output pin select for PWM channel n */
63126   #define PWM_PSEL_OUT_MaxCount (4UL)                /*!< Max size of OUT[4] array.                                            */
63127   #define PWM_PSEL_OUT_MaxIndex (3UL)                /*!< Max index of OUT[4] array.                                           */
63128   #define PWM_PSEL_OUT_MinIndex (0UL)                /*!< Min index of OUT[4] array.                                           */
63129   #define PWM_PSEL_OUT_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of OUT[4] register.                                      */
63130 
63131 /* PIN @Bits 0..4 : Pin number */
63132   #define PWM_PSEL_OUT_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
63133   #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field.                                    */
63134   #define PWM_PSEL_OUT_PIN_Min (0x0UL)               /*!< Min value of PIN field.                                              */
63135   #define PWM_PSEL_OUT_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */
63136 
63137 /* PORT @Bits 5..8 : Port number */
63138   #define PWM_PSEL_OUT_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
63139   #define PWM_PSEL_OUT_PORT_Msk (0xFUL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field.                                  */
63140   #define PWM_PSEL_OUT_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
63141   #define PWM_PSEL_OUT_PORT_Max (0xFUL)              /*!< Max size of PORT field.                                              */
63142 
63143 /* CONNECT @Bit 31 : Connection */
63144   #define PWM_PSEL_OUT_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
63145   #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
63146   #define PWM_PSEL_OUT_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
63147   #define PWM_PSEL_OUT_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
63148   #define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
63149   #define PWM_PSEL_OUT_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */
63150 
63151 
63152 /* ======================================================= Struct PWM ======================================================== */
63153 /**
63154   * @brief Pulse width modulation unit
63155   */
63156   typedef struct {                                   /*!< PWM Structure                                                        */
63157     __IM uint32_t RESERVED;
63158     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at the end
63159                                                                          of current PWM period, and stops sequence playback*/
63160     __OM uint32_t TASKS_SEQSTART[2];                 /*!< (@ 0x00000008) Loads the first PWM value on all enabled channels from
63161                                                                          sequence n, and starts playing that sequence at the
63162                                                                          rate defined in SEQ[n]REFRESH and/or DECODER.MODE.
63163                                                                          Causes PWM generation to start if not running.*/
63164     __OM uint32_t TASKS_NEXTSTEP;                    /*!< (@ 0x00000010) Steps by one value in the current sequence on all
63165                                                                          enabled channels if DECODER.MODE=NextStep. Does not
63166                                                                          cause PWM generation to start if not running.*/
63167     __IM uint32_t RESERVED1[28];
63168     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
63169     __IOM uint32_t SUBSCRIBE_SEQSTART[2];            /*!< (@ 0x00000088) Subscribe configuration for task SEQSTART[n]          */
63170     __IOM uint32_t SUBSCRIBE_NEXTSTEP;               /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP             */
63171     __IM uint32_t RESERVED2[28];
63172     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no
63173                                                                          longer generated*/
63174     __IOM uint32_t EVENTS_SEQSTARTED[2];             /*!< (@ 0x00000108) First PWM period started on sequence n                */
63175     __IOM uint32_t EVENTS_SEQEND[2];                 /*!< (@ 0x00000110) Emitted at end of every sequence n, when last value
63176                                                                          from RAM has been applied to wave counter*/
63177     __IOM uint32_t EVENTS_PWMPERIODEND;              /*!< (@ 0x00000118) Emitted at the end of each PWM period                 */
63178     __IOM uint32_t EVENTS_LOOPSDONE;                 /*!< (@ 0x0000011C) Concatenated sequences have been played the amount of
63179                                                                          times defined in LOOP.CNT*/
63180     __IM uint32_t RESERVED3[25];
63181     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
63182     __IOM uint32_t PUBLISH_SEQSTARTED[2];            /*!< (@ 0x00000188) Publish configuration for event SEQSTARTED[n]         */
63183     __IOM uint32_t PUBLISH_SEQEND[2];                /*!< (@ 0x00000190) Publish configuration for event SEQEND[n]             */
63184     __IOM uint32_t PUBLISH_PWMPERIODEND;             /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND          */
63185     __IOM uint32_t PUBLISH_LOOPSDONE;                /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE             */
63186     __IM uint32_t RESERVED4[24];
63187     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
63188     __IM uint32_t RESERVED5[63];
63189     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
63190     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
63191     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
63192     __IM uint32_t RESERVED6[125];
63193     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) PWM module enable register                            */
63194     __IOM uint32_t MODE;                             /*!< (@ 0x00000504) Selects operating mode of the wave counter            */
63195     __IOM uint32_t COUNTERTOP;                       /*!< (@ 0x00000508) Value up to which the pulse generator counter counts  */
63196     __IOM uint32_t PRESCALER;                        /*!< (@ 0x0000050C) Configuration for PWM_CLK                             */
63197     __IOM uint32_t DECODER;                          /*!< (@ 0x00000510) Configuration of the decoder                          */
63198     __IOM uint32_t LOOP;                             /*!< (@ 0x00000514) Number of playbacks of a loop                         */
63199     __IM uint32_t RESERVED7[2];
63200     __IOM NRF_PWM_SEQ_Type SEQ[2];                   /*!< (@ 0x00000520) (unspecified)                                         */
63201     __IOM NRF_PWM_PSEL_Type PSEL;                    /*!< (@ 0x00000560) (unspecified)                                         */
63202   } NRF_PWM_Type;                                    /*!< Size = 1392 (0x570)                                                  */
63203 
63204 /* PWM_TASKS_STOP: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
63205   #define PWM_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
63206 
63207 /* TASKS_STOP @Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
63208                        */
63209 
63210   #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
63211   #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
63212   #define PWM_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
63213   #define PWM_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
63214   #define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
63215 
63216 
63217 /* PWM_TASKS_SEQSTART: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at
63218                         the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
63219 
63220   #define PWM_TASKS_SEQSTART_MaxCount (2UL)          /*!< Max size of TASKS_SEQSTART[2] array.                                 */
63221   #define PWM_TASKS_SEQSTART_MaxIndex (1UL)          /*!< Max index of TASKS_SEQSTART[2] array.                                */
63222   #define PWM_TASKS_SEQSTART_MinIndex (0UL)          /*!< Min index of TASKS_SEQSTART[2] array.                                */
63223   #define PWM_TASKS_SEQSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SEQSTART[2] register.                         */
63224 
63225 /* TASKS_SEQSTART @Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence
63226                            at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not
63227                            running. */
63228 
63229   #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field.                                   */
63230   #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART
63231                                                                             field.*/
63232   #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_SEQSTART field.                     */
63233   #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_SEQSTART field.                     */
63234   #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (0x1UL) /*!< Trigger task                                                  */
63235 
63236 
63237 /* PWM_TASKS_NEXTSTEP: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not
63238                         cause PWM generation to start if not running. */
63239 
63240   #define PWM_TASKS_NEXTSTEP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_NEXTSTEP register.                            */
63241 
63242 /* TASKS_NEXTSTEP @Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not
63243                            cause PWM generation to start if not running. */
63244 
63245   #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field.                                   */
63246   #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP
63247                                                                             field.*/
63248   #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Min (0x1UL) /*!< Min enumerator value of TASKS_NEXTSTEP field.                     */
63249   #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Max (0x1UL) /*!< Max enumerator value of TASKS_NEXTSTEP field.                     */
63250   #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task                                                  */
63251 
63252 
63253 /* PWM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
63254   #define PWM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */
63255 
63256 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
63257   #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
63258   #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
63259   #define PWM_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
63260   #define PWM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
63261 
63262 /* EN @Bit 31 : (unspecified) */
63263   #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
63264   #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
63265   #define PWM_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
63266   #define PWM_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
63267   #define PWM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
63268   #define PWM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
63269 
63270 
63271 /* PWM_SUBSCRIBE_SEQSTART: Subscribe configuration for task SEQSTART[n] */
63272   #define PWM_SUBSCRIBE_SEQSTART_MaxCount (2UL)      /*!< Max size of SUBSCRIBE_SEQSTART[2] array.                             */
63273   #define PWM_SUBSCRIBE_SEQSTART_MaxIndex (1UL)      /*!< Max index of SUBSCRIBE_SEQSTART[2] array.                            */
63274   #define PWM_SUBSCRIBE_SEQSTART_MinIndex (0UL)      /*!< Min index of SUBSCRIBE_SEQSTART[2] array.                            */
63275   #define PWM_SUBSCRIBE_SEQSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SEQSTART[2] register.                 */
63276 
63277 /* CHIDX @Bits 0..7 : DPPI channel that task SEQSTART[n] will subscribe to */
63278   #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
63279   #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
63280   #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
63281   #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
63282 
63283 /* EN @Bit 31 : (unspecified) */
63284   #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL)       /*!< Position of EN field.                                                */
63285   #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field.                    */
63286   #define PWM_SUBSCRIBE_SEQSTART_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
63287   #define PWM_SUBSCRIBE_SEQSTART_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
63288   #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
63289   #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
63290 
63291 
63292 /* PWM_SUBSCRIBE_NEXTSTEP: Subscribe configuration for task NEXTSTEP */
63293   #define PWM_SUBSCRIBE_NEXTSTEP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_NEXTSTEP register.                    */
63294 
63295 /* CHIDX @Bits 0..7 : DPPI channel that task NEXTSTEP will subscribe to */
63296   #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
63297   #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
63298   #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
63299   #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
63300 
63301 /* EN @Bit 31 : (unspecified) */
63302   #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
63303   #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field.                    */
63304   #define PWM_SUBSCRIBE_NEXTSTEP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
63305   #define PWM_SUBSCRIBE_NEXTSTEP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
63306   #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
63307   #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
63308 
63309 
63310 /* PWM_EVENTS_STOPPED: Response to STOP task, emitted when PWM pulses are no longer generated */
63311   #define PWM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                            */
63312 
63313 /* EVENTS_STOPPED @Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
63314   #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                   */
63315   #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED
63316                                                                             field.*/
63317   #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                     */
63318   #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                     */
63319   #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                      */
63320   #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                             */
63321 
63322 
63323 /* PWM_EVENTS_SEQSTARTED: First PWM period started on sequence n */
63324   #define PWM_EVENTS_SEQSTARTED_MaxCount (2UL)       /*!< Max size of EVENTS_SEQSTARTED[2] array.                              */
63325   #define PWM_EVENTS_SEQSTARTED_MaxIndex (1UL)       /*!< Max index of EVENTS_SEQSTARTED[2] array.                             */
63326   #define PWM_EVENTS_SEQSTARTED_MinIndex (0UL)       /*!< Min index of EVENTS_SEQSTARTED[2] array.                             */
63327   #define PWM_EVENTS_SEQSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SEQSTARTED[2] register.                   */
63328 
63329 /* EVENTS_SEQSTARTED @Bit 0 : First PWM period started on sequence n */
63330   #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field.                          */
63331   #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of
63332                                                                             EVENTS_SEQSTARTED field.*/
63333   #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SEQSTARTED field.            */
63334   #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SEQSTARTED field.            */
63335   #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                */
63336   #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated                                       */
63337 
63338 
63339 /* PWM_EVENTS_SEQEND: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
63340   #define PWM_EVENTS_SEQEND_MaxCount (2UL)           /*!< Max size of EVENTS_SEQEND[2] array.                                  */
63341   #define PWM_EVENTS_SEQEND_MaxIndex (1UL)           /*!< Max index of EVENTS_SEQEND[2] array.                                 */
63342   #define PWM_EVENTS_SEQEND_MinIndex (0UL)           /*!< Min index of EVENTS_SEQEND[2] array.                                 */
63343   #define PWM_EVENTS_SEQEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SEQEND[2] register.                           */
63344 
63345 /* EVENTS_SEQEND @Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
63346   #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL)  /*!< Position of EVENTS_SEQEND field.                                     */
63347   #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND
63348                                                                             field.*/
63349   #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_SEQEND field.                        */
63350   #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_SEQEND field.                        */
63351   #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated                                        */
63352   #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated                                               */
63353 
63354 
63355 /* PWM_EVENTS_PWMPERIODEND: Emitted at the end of each PWM period */
63356   #define PWM_EVENTS_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PWMPERIODEND register.                  */
63357 
63358 /* EVENTS_PWMPERIODEND @Bit 0 : Emitted at the end of each PWM period */
63359   #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field.                    */
63360   #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit
63361                                                                             mask of EVENTS_PWMPERIODEND field.*/
63362   #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PWMPERIODEND field.      */
63363   #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PWMPERIODEND field.      */
63364   #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated                            */
63365   #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated                                   */
63366 
63367 
63368 /* PWM_EVENTS_LOOPSDONE: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
63369   #define PWM_EVENTS_LOOPSDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LOOPSDONE register.                        */
63370 
63371 /* EVENTS_LOOPSDONE @Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
63372   #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field.                             */
63373   #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of
63374                                                                             EVENTS_LOOPSDONE field.*/
63375   #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_LOOPSDONE field.               */
63376   #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_LOOPSDONE field.               */
63377   #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated                                  */
63378   #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated                                         */
63379 
63380 
63381 /* PWM_PUBLISH_STOPPED: Publish configuration for event STOPPED */
63382   #define PWM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                          */
63383 
63384 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
63385   #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
63386   #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
63387   #define PWM_PUBLISH_STOPPED_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
63388   #define PWM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
63389 
63390 /* EN @Bit 31 : (unspecified) */
63391   #define PWM_PUBLISH_STOPPED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
63392   #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                          */
63393   #define PWM_PUBLISH_STOPPED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
63394   #define PWM_PUBLISH_STOPPED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
63395   #define PWM_PUBLISH_STOPPED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
63396   #define PWM_PUBLISH_STOPPED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
63397 
63398 
63399 /* PWM_PUBLISH_SEQSTARTED: Publish configuration for event SEQSTARTED[n] */
63400   #define PWM_PUBLISH_SEQSTARTED_MaxCount (2UL)      /*!< Max size of PUBLISH_SEQSTARTED[2] array.                             */
63401   #define PWM_PUBLISH_SEQSTARTED_MaxIndex (1UL)      /*!< Max index of PUBLISH_SEQSTARTED[2] array.                            */
63402   #define PWM_PUBLISH_SEQSTARTED_MinIndex (0UL)      /*!< Min index of PUBLISH_SEQSTARTED[2] array.                            */
63403   #define PWM_PUBLISH_SEQSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SEQSTARTED[2] register.                 */
63404 
63405 /* CHIDX @Bits 0..7 : DPPI channel that event SEQSTARTED[n] will publish to */
63406   #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
63407   #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
63408   #define PWM_PUBLISH_SEQSTARTED_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
63409   #define PWM_PUBLISH_SEQSTARTED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
63410 
63411 /* EN @Bit 31 : (unspecified) */
63412   #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
63413   #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field.                    */
63414   #define PWM_PUBLISH_SEQSTARTED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
63415   #define PWM_PUBLISH_SEQSTARTED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
63416   #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
63417   #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
63418 
63419 
63420 /* PWM_PUBLISH_SEQEND: Publish configuration for event SEQEND[n] */
63421   #define PWM_PUBLISH_SEQEND_MaxCount (2UL)          /*!< Max size of PUBLISH_SEQEND[2] array.                                 */
63422   #define PWM_PUBLISH_SEQEND_MaxIndex (1UL)          /*!< Max index of PUBLISH_SEQEND[2] array.                                */
63423   #define PWM_PUBLISH_SEQEND_MinIndex (0UL)          /*!< Min index of PUBLISH_SEQEND[2] array.                                */
63424   #define PWM_PUBLISH_SEQEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SEQEND[2] register.                         */
63425 
63426 /* CHIDX @Bits 0..7 : DPPI channel that event SEQEND[n] will publish to */
63427   #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
63428   #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
63429   #define PWM_PUBLISH_SEQEND_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
63430   #define PWM_PUBLISH_SEQEND_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
63431 
63432 /* EN @Bit 31 : (unspecified) */
63433   #define PWM_PUBLISH_SEQEND_EN_Pos (31UL)           /*!< Position of EN field.                                                */
63434   #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field.                            */
63435   #define PWM_PUBLISH_SEQEND_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
63436   #define PWM_PUBLISH_SEQEND_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
63437   #define PWM_PUBLISH_SEQEND_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
63438   #define PWM_PUBLISH_SEQEND_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
63439 
63440 
63441 /* PWM_PUBLISH_PWMPERIODEND: Publish configuration for event PWMPERIODEND */
63442   #define PWM_PUBLISH_PWMPERIODEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PWMPERIODEND register.                */
63443 
63444 /* CHIDX @Bits 0..7 : DPPI channel that event PWMPERIODEND will publish to */
63445   #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
63446   #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
63447   #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
63448   #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
63449 
63450 /* EN @Bit 31 : (unspecified) */
63451   #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL)     /*!< Position of EN field.                                                */
63452   #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field.                */
63453   #define PWM_PUBLISH_PWMPERIODEND_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
63454   #define PWM_PUBLISH_PWMPERIODEND_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
63455   #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
63456   #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */
63457 
63458 
63459 /* PWM_PUBLISH_LOOPSDONE: Publish configuration for event LOOPSDONE */
63460   #define PWM_PUBLISH_LOOPSDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LOOPSDONE register.                      */
63461 
63462 /* CHIDX @Bits 0..7 : DPPI channel that event LOOPSDONE will publish to */
63463   #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
63464   #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
63465   #define PWM_PUBLISH_LOOPSDONE_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
63466   #define PWM_PUBLISH_LOOPSDONE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
63467 
63468 /* EN @Bit 31 : (unspecified) */
63469   #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
63470   #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field.                      */
63471   #define PWM_PUBLISH_LOOPSDONE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
63472   #define PWM_PUBLISH_LOOPSDONE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
63473   #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
63474   #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
63475 
63476 
63477 /* PWM_SHORTS: Shortcuts between local events and tasks */
63478   #define PWM_SHORTS_ResetValue (0x00000000UL)       /*!< Reset value of SHORTS register.                                      */
63479 
63480 /* SEQEND0_STOP @Bit 0 : Shortcut between event SEQEND[n] and task STOP */
63481   #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL)          /*!< Position of SEQEND0_STOP field.                                      */
63482   #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field.              */
63483   #define PWM_SHORTS_SEQEND0_STOP_Min (0x0UL)        /*!< Min enumerator value of SEQEND0_STOP field.                          */
63484   #define PWM_SHORTS_SEQEND0_STOP_Max (0x1UL)        /*!< Max enumerator value of SEQEND0_STOP field.                          */
63485   #define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
63486   #define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */
63487 
63488 /* SEQEND1_STOP @Bit 1 : Shortcut between event SEQEND[n] and task STOP */
63489   #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL)          /*!< Position of SEQEND1_STOP field.                                      */
63490   #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field.              */
63491   #define PWM_SHORTS_SEQEND1_STOP_Min (0x0UL)        /*!< Min enumerator value of SEQEND1_STOP field.                          */
63492   #define PWM_SHORTS_SEQEND1_STOP_Max (0x1UL)        /*!< Max enumerator value of SEQEND1_STOP field.                          */
63493   #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
63494   #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */
63495 
63496 /* LOOPSDONE_SEQSTART0 @Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[n] */
63497   #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL)   /*!< Position of LOOPSDONE_SEQSTART0 field.                               */
63498   #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0
63499                                                                             field.*/
63500   #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_SEQSTART0 field.                   */
63501   #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_SEQSTART0 field.                   */
63502   #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0x0UL) /*!< Disable shortcut                                                */
63503   #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (0x1UL) /*!< Enable shortcut                                                  */
63504 
63505 /* LOOPSDONE_SEQSTART1 @Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[n] */
63506   #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL)   /*!< Position of LOOPSDONE_SEQSTART1 field.                               */
63507   #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1
63508                                                                             field.*/
63509   #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Min (0x0UL) /*!< Min enumerator value of LOOPSDONE_SEQSTART1 field.                   */
63510   #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Max (0x1UL) /*!< Max enumerator value of LOOPSDONE_SEQSTART1 field.                   */
63511   #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0x0UL) /*!< Disable shortcut                                                */
63512   #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (0x1UL) /*!< Enable shortcut                                                  */
63513 
63514 /* LOOPSDONE_STOP @Bit 4 : Shortcut between event LOOPSDONE and task STOP */
63515   #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL)        /*!< Position of LOOPSDONE_STOP field.                                    */
63516   #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field.        */
63517   #define PWM_SHORTS_LOOPSDONE_STOP_Min (0x0UL)      /*!< Min enumerator value of LOOPSDONE_STOP field.                        */
63518   #define PWM_SHORTS_LOOPSDONE_STOP_Max (0x1UL)      /*!< Max enumerator value of LOOPSDONE_STOP field.                        */
63519   #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                     */
63520   #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
63521 
63522 
63523 /* PWM_INTEN: Enable or disable interrupt */
63524   #define PWM_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
63525 
63526 /* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */
63527   #define PWM_INTEN_STOPPED_Pos (1UL)                /*!< Position of STOPPED field.                                           */
63528   #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                               */
63529   #define PWM_INTEN_STOPPED_Min (0x0UL)              /*!< Min enumerator value of STOPPED field.                               */
63530   #define PWM_INTEN_STOPPED_Max (0x1UL)              /*!< Max enumerator value of STOPPED field.                               */
63531   #define PWM_INTEN_STOPPED_Disabled (0x0UL)         /*!< Disable                                                              */
63532   #define PWM_INTEN_STOPPED_Enabled (0x1UL)          /*!< Enable                                                               */
63533 
63534 /* SEQSTARTED0 @Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
63535   #define PWM_INTEN_SEQSTARTED0_Pos (2UL)            /*!< Position of SEQSTARTED0 field.                                       */
63536   #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field.                   */
63537   #define PWM_INTEN_SEQSTARTED0_Min (0x0UL)          /*!< Min enumerator value of SEQSTARTED0 field.                           */
63538   #define PWM_INTEN_SEQSTARTED0_Max (0x1UL)          /*!< Max enumerator value of SEQSTARTED0 field.                           */
63539   #define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL)     /*!< Disable                                                              */
63540   #define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL)      /*!< Enable                                                               */
63541 
63542 /* SEQSTARTED1 @Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
63543   #define PWM_INTEN_SEQSTARTED1_Pos (3UL)            /*!< Position of SEQSTARTED1 field.                                       */
63544   #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field.                   */
63545   #define PWM_INTEN_SEQSTARTED1_Min (0x0UL)          /*!< Min enumerator value of SEQSTARTED1 field.                           */
63546   #define PWM_INTEN_SEQSTARTED1_Max (0x1UL)          /*!< Max enumerator value of SEQSTARTED1 field.                           */
63547   #define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL)     /*!< Disable                                                              */
63548   #define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL)      /*!< Enable                                                               */
63549 
63550 /* SEQEND0 @Bit 4 : Enable or disable interrupt for event SEQEND[0] */
63551   #define PWM_INTEN_SEQEND0_Pos (4UL)                /*!< Position of SEQEND0 field.                                           */
63552   #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field.                               */
63553   #define PWM_INTEN_SEQEND0_Min (0x0UL)              /*!< Min enumerator value of SEQEND0 field.                               */
63554   #define PWM_INTEN_SEQEND0_Max (0x1UL)              /*!< Max enumerator value of SEQEND0 field.                               */
63555   #define PWM_INTEN_SEQEND0_Disabled (0x0UL)         /*!< Disable                                                              */
63556   #define PWM_INTEN_SEQEND0_Enabled (0x1UL)          /*!< Enable                                                               */
63557 
63558 /* SEQEND1 @Bit 5 : Enable or disable interrupt for event SEQEND[1] */
63559   #define PWM_INTEN_SEQEND1_Pos (5UL)                /*!< Position of SEQEND1 field.                                           */
63560   #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field.                               */
63561   #define PWM_INTEN_SEQEND1_Min (0x0UL)              /*!< Min enumerator value of SEQEND1 field.                               */
63562   #define PWM_INTEN_SEQEND1_Max (0x1UL)              /*!< Max enumerator value of SEQEND1 field.                               */
63563   #define PWM_INTEN_SEQEND1_Disabled (0x0UL)         /*!< Disable                                                              */
63564   #define PWM_INTEN_SEQEND1_Enabled (0x1UL)          /*!< Enable                                                               */
63565 
63566 /* PWMPERIODEND @Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
63567   #define PWM_INTEN_PWMPERIODEND_Pos (6UL)           /*!< Position of PWMPERIODEND field.                                      */
63568   #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.                */
63569   #define PWM_INTEN_PWMPERIODEND_Min (0x0UL)         /*!< Min enumerator value of PWMPERIODEND field.                          */
63570   #define PWM_INTEN_PWMPERIODEND_Max (0x1UL)         /*!< Max enumerator value of PWMPERIODEND field.                          */
63571   #define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL)    /*!< Disable                                                              */
63572   #define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL)     /*!< Enable                                                               */
63573 
63574 /* LOOPSDONE @Bit 7 : Enable or disable interrupt for event LOOPSDONE */
63575   #define PWM_INTEN_LOOPSDONE_Pos (7UL)              /*!< Position of LOOPSDONE field.                                         */
63576   #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field.                         */
63577   #define PWM_INTEN_LOOPSDONE_Min (0x0UL)            /*!< Min enumerator value of LOOPSDONE field.                             */
63578   #define PWM_INTEN_LOOPSDONE_Max (0x1UL)            /*!< Max enumerator value of LOOPSDONE field.                             */
63579   #define PWM_INTEN_LOOPSDONE_Disabled (0x0UL)       /*!< Disable                                                              */
63580   #define PWM_INTEN_LOOPSDONE_Enabled (0x1UL)        /*!< Enable                                                               */
63581 
63582 
63583 /* PWM_INTENSET: Enable interrupt */
63584   #define PWM_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
63585 
63586 /* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
63587   #define PWM_INTENSET_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
63588   #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
63589   #define PWM_INTENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
63590   #define PWM_INTENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
63591   #define PWM_INTENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
63592   #define PWM_INTENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
63593   #define PWM_INTENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
63594 
63595 /* SEQSTARTED0 @Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
63596   #define PWM_INTENSET_SEQSTARTED0_Pos (2UL)         /*!< Position of SEQSTARTED0 field.                                       */
63597   #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field.             */
63598   #define PWM_INTENSET_SEQSTARTED0_Min (0x0UL)       /*!< Min enumerator value of SEQSTARTED0 field.                           */
63599   #define PWM_INTENSET_SEQSTARTED0_Max (0x1UL)       /*!< Max enumerator value of SEQSTARTED0 field.                           */
63600   #define PWM_INTENSET_SEQSTARTED0_Set (0x1UL)       /*!< Enable                                                               */
63601   #define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
63602   #define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
63603 
63604 /* SEQSTARTED1 @Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
63605   #define PWM_INTENSET_SEQSTARTED1_Pos (3UL)         /*!< Position of SEQSTARTED1 field.                                       */
63606   #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field.             */
63607   #define PWM_INTENSET_SEQSTARTED1_Min (0x0UL)       /*!< Min enumerator value of SEQSTARTED1 field.                           */
63608   #define PWM_INTENSET_SEQSTARTED1_Max (0x1UL)       /*!< Max enumerator value of SEQSTARTED1 field.                           */
63609   #define PWM_INTENSET_SEQSTARTED1_Set (0x1UL)       /*!< Enable                                                               */
63610   #define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
63611   #define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
63612 
63613 /* SEQEND0 @Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
63614   #define PWM_INTENSET_SEQEND0_Pos (4UL)             /*!< Position of SEQEND0 field.                                           */
63615   #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field.                         */
63616   #define PWM_INTENSET_SEQEND0_Min (0x0UL)           /*!< Min enumerator value of SEQEND0 field.                               */
63617   #define PWM_INTENSET_SEQEND0_Max (0x1UL)           /*!< Max enumerator value of SEQEND0 field.                               */
63618   #define PWM_INTENSET_SEQEND0_Set (0x1UL)           /*!< Enable                                                               */
63619   #define PWM_INTENSET_SEQEND0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
63620   #define PWM_INTENSET_SEQEND0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
63621 
63622 /* SEQEND1 @Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
63623   #define PWM_INTENSET_SEQEND1_Pos (5UL)             /*!< Position of SEQEND1 field.                                           */
63624   #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field.                         */
63625   #define PWM_INTENSET_SEQEND1_Min (0x0UL)           /*!< Min enumerator value of SEQEND1 field.                               */
63626   #define PWM_INTENSET_SEQEND1_Max (0x1UL)           /*!< Max enumerator value of SEQEND1 field.                               */
63627   #define PWM_INTENSET_SEQEND1_Set (0x1UL)           /*!< Enable                                                               */
63628   #define PWM_INTENSET_SEQEND1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
63629   #define PWM_INTENSET_SEQEND1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
63630 
63631 /* PWMPERIODEND @Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
63632   #define PWM_INTENSET_PWMPERIODEND_Pos (6UL)        /*!< Position of PWMPERIODEND field.                                      */
63633   #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.          */
63634   #define PWM_INTENSET_PWMPERIODEND_Min (0x0UL)      /*!< Min enumerator value of PWMPERIODEND field.                          */
63635   #define PWM_INTENSET_PWMPERIODEND_Max (0x1UL)      /*!< Max enumerator value of PWMPERIODEND field.                          */
63636   #define PWM_INTENSET_PWMPERIODEND_Set (0x1UL)      /*!< Enable                                                               */
63637   #define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                       */
63638   #define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
63639 
63640 /* LOOPSDONE @Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
63641   #define PWM_INTENSET_LOOPSDONE_Pos (7UL)           /*!< Position of LOOPSDONE field.                                         */
63642   #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field.                   */
63643   #define PWM_INTENSET_LOOPSDONE_Min (0x0UL)         /*!< Min enumerator value of LOOPSDONE field.                             */
63644   #define PWM_INTENSET_LOOPSDONE_Max (0x1UL)         /*!< Max enumerator value of LOOPSDONE field.                             */
63645   #define PWM_INTENSET_LOOPSDONE_Set (0x1UL)         /*!< Enable                                                               */
63646   #define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
63647   #define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
63648 
63649 
63650 /* PWM_INTENCLR: Disable interrupt */
63651   #define PWM_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
63652 
63653 /* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
63654   #define PWM_INTENCLR_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
63655   #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
63656   #define PWM_INTENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
63657   #define PWM_INTENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
63658   #define PWM_INTENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
63659   #define PWM_INTENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
63660   #define PWM_INTENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
63661 
63662 /* SEQSTARTED0 @Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
63663   #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL)         /*!< Position of SEQSTARTED0 field.                                       */
63664   #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field.             */
63665   #define PWM_INTENCLR_SEQSTARTED0_Min (0x0UL)       /*!< Min enumerator value of SEQSTARTED0 field.                           */
63666   #define PWM_INTENCLR_SEQSTARTED0_Max (0x1UL)       /*!< Max enumerator value of SEQSTARTED0 field.                           */
63667   #define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL)     /*!< Disable                                                              */
63668   #define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
63669   #define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
63670 
63671 /* SEQSTARTED1 @Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
63672   #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL)         /*!< Position of SEQSTARTED1 field.                                       */
63673   #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field.             */
63674   #define PWM_INTENCLR_SEQSTARTED1_Min (0x0UL)       /*!< Min enumerator value of SEQSTARTED1 field.                           */
63675   #define PWM_INTENCLR_SEQSTARTED1_Max (0x1UL)       /*!< Max enumerator value of SEQSTARTED1 field.                           */
63676   #define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL)     /*!< Disable                                                              */
63677   #define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
63678   #define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
63679 
63680 /* SEQEND0 @Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
63681   #define PWM_INTENCLR_SEQEND0_Pos (4UL)             /*!< Position of SEQEND0 field.                                           */
63682   #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field.                         */
63683   #define PWM_INTENCLR_SEQEND0_Min (0x0UL)           /*!< Min enumerator value of SEQEND0 field.                               */
63684   #define PWM_INTENCLR_SEQEND0_Max (0x1UL)           /*!< Max enumerator value of SEQEND0 field.                               */
63685   #define PWM_INTENCLR_SEQEND0_Clear (0x1UL)         /*!< Disable                                                              */
63686   #define PWM_INTENCLR_SEQEND0_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
63687   #define PWM_INTENCLR_SEQEND0_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
63688 
63689 /* SEQEND1 @Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
63690   #define PWM_INTENCLR_SEQEND1_Pos (5UL)             /*!< Position of SEQEND1 field.                                           */
63691   #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field.                         */
63692   #define PWM_INTENCLR_SEQEND1_Min (0x0UL)           /*!< Min enumerator value of SEQEND1 field.                               */
63693   #define PWM_INTENCLR_SEQEND1_Max (0x1UL)           /*!< Max enumerator value of SEQEND1 field.                               */
63694   #define PWM_INTENCLR_SEQEND1_Clear (0x1UL)         /*!< Disable                                                              */
63695   #define PWM_INTENCLR_SEQEND1_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
63696   #define PWM_INTENCLR_SEQEND1_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
63697 
63698 /* PWMPERIODEND @Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
63699   #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL)        /*!< Position of PWMPERIODEND field.                                      */
63700   #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field.          */
63701   #define PWM_INTENCLR_PWMPERIODEND_Min (0x0UL)      /*!< Min enumerator value of PWMPERIODEND field.                          */
63702   #define PWM_INTENCLR_PWMPERIODEND_Max (0x1UL)      /*!< Max enumerator value of PWMPERIODEND field.                          */
63703   #define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL)    /*!< Disable                                                              */
63704   #define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled                                                       */
63705   #define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
63706 
63707 /* LOOPSDONE @Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
63708   #define PWM_INTENCLR_LOOPSDONE_Pos (7UL)           /*!< Position of LOOPSDONE field.                                         */
63709   #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field.                   */
63710   #define PWM_INTENCLR_LOOPSDONE_Min (0x0UL)         /*!< Min enumerator value of LOOPSDONE field.                             */
63711   #define PWM_INTENCLR_LOOPSDONE_Max (0x1UL)         /*!< Max enumerator value of LOOPSDONE field.                             */
63712   #define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL)       /*!< Disable                                                              */
63713   #define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
63714   #define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
63715 
63716 
63717 /* PWM_ENABLE: PWM module enable register */
63718   #define PWM_ENABLE_ResetValue (0x00000000UL)       /*!< Reset value of ENABLE register.                                      */
63719 
63720 /* ENABLE @Bit 0 : Enable or disable PWM module */
63721   #define PWM_ENABLE_ENABLE_Pos (0UL)                /*!< Position of ENABLE field.                                            */
63722   #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                                */
63723   #define PWM_ENABLE_ENABLE_Min (0x0UL)              /*!< Min enumerator value of ENABLE field.                                */
63724   #define PWM_ENABLE_ENABLE_Max (0x1UL)              /*!< Max enumerator value of ENABLE field.                                */
63725   #define PWM_ENABLE_ENABLE_Disabled (0x0UL)         /*!< Disabled                                                             */
63726   #define PWM_ENABLE_ENABLE_Enabled (0x1UL)          /*!< Enable                                                               */
63727 
63728 
63729 /* PWM_MODE: Selects operating mode of the wave counter */
63730   #define PWM_MODE_ResetValue (0x00000000UL)         /*!< Reset value of MODE register.                                        */
63731 
63732 /* UPDOWN @Bit 0 : Selects up mode or up-and-down mode for the counter */
63733   #define PWM_MODE_UPDOWN_Pos (0UL)                  /*!< Position of UPDOWN field.                                            */
63734   #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field.                                    */
63735   #define PWM_MODE_UPDOWN_Min (0x0UL)                /*!< Min enumerator value of UPDOWN field.                                */
63736   #define PWM_MODE_UPDOWN_Max (0x1UL)                /*!< Max enumerator value of UPDOWN field.                                */
63737   #define PWM_MODE_UPDOWN_Up (0x0UL)                 /*!< Up counter, edge-aligned PWM duty cycle                              */
63738   #define PWM_MODE_UPDOWN_UpAndDown (0x1UL)          /*!< Up and down counter, center-aligned PWM duty cycle                   */
63739 
63740 
63741 /* PWM_COUNTERTOP: Value up to which the pulse generator counter counts */
63742   #define PWM_COUNTERTOP_ResetValue (0x000003FFUL)   /*!< Reset value of COUNTERTOP register.                                  */
63743 
63744 /* COUNTERTOP @Bits 0..14 : Value up to which the pulse generator counter counts. This register is ignored when
63745                             DECODER.MODE=WaveForm and only values from RAM are used. */
63746 
63747   #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL)        /*!< Position of COUNTERTOP field.                                        */
63748   #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field.         */
63749   #define PWM_COUNTERTOP_COUNTERTOP_Min (0x3UL)      /*!< Min value of COUNTERTOP field.                                       */
63750   #define PWM_COUNTERTOP_COUNTERTOP_Max (0x7FFFUL)   /*!< Max size of COUNTERTOP field.                                        */
63751 
63752 
63753 /* PWM_PRESCALER: Configuration for PWM_CLK */
63754   #define PWM_PRESCALER_ResetValue (0x00000000UL)    /*!< Reset value of PRESCALER register.                                   */
63755 
63756 /* PRESCALER @Bits 0..2 : Prescaler of PWM_CLK */
63757   #define PWM_PRESCALER_PRESCALER_Pos (0UL)          /*!< Position of PRESCALER field.                                         */
63758   #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field.                 */
63759   #define PWM_PRESCALER_PRESCALER_Min (0x0UL)        /*!< Min enumerator value of PRESCALER field.                             */
63760   #define PWM_PRESCALER_PRESCALER_Max (0x7UL)        /*!< Max enumerator value of PRESCALER field.                             */
63761   #define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL)      /*!< Divide by 1 (16 MHz)                                                 */
63762   #define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL)      /*!< Divide by 2 (8 MHz)                                                  */
63763   #define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL)      /*!< Divide by 4 (4 MHz)                                                  */
63764   #define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL)      /*!< Divide by 8 (2 MHz)                                                  */
63765   #define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL)     /*!< Divide by 16 (1 MHz)                                                 */
63766   #define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL)     /*!< Divide by 32 (500 kHz)                                               */
63767   #define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL)     /*!< Divide by 64 (250 kHz)                                               */
63768   #define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL)    /*!< Divide by 128 (125 kHz)                                              */
63769 
63770 
63771 /* PWM_DECODER: Configuration of the decoder */
63772   #define PWM_DECODER_ResetValue (0x00000000UL)      /*!< Reset value of DECODER register.                                     */
63773 
63774 /* LOAD @Bits 0..1 : How a sequence is read from RAM and spread to the compare register */
63775   #define PWM_DECODER_LOAD_Pos (0UL)                 /*!< Position of LOAD field.                                              */
63776   #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field.                                    */
63777   #define PWM_DECODER_LOAD_Min (0x0UL)               /*!< Min enumerator value of LOAD field.                                  */
63778   #define PWM_DECODER_LOAD_Max (0x3UL)               /*!< Max enumerator value of LOAD field.                                  */
63779   #define PWM_DECODER_LOAD_Common (0x0UL)            /*!< 1st half word (16-bit) used in all PWM channels 0..3                 */
63780   #define PWM_DECODER_LOAD_Grouped (0x1UL)           /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3*/
63781   #define PWM_DECODER_LOAD_Individual (0x2UL)        /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3        */
63782   #define PWM_DECODER_LOAD_WaveForm (0x3UL)          /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP  */
63783 
63784 /* MODE @Bit 8 : Selects source for advancing the active sequence */
63785   #define PWM_DECODER_MODE_Pos (8UL)                 /*!< Position of MODE field.                                              */
63786   #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field.                                    */
63787   #define PWM_DECODER_MODE_Min (0x0UL)               /*!< Min enumerator value of MODE field.                                  */
63788   #define PWM_DECODER_MODE_Max (0x1UL)               /*!< Max enumerator value of MODE field.                                  */
63789   #define PWM_DECODER_MODE_RefreshCount (0x0UL)      /*!< SEQ[n].REFRESH is used to determine loading internal compare
63790                                                           registers*/
63791   #define PWM_DECODER_MODE_NextStep (0x1UL)          /*!< NEXTSTEP task causes a new value to be loaded to internal compare
63792                                                           registers*/
63793 
63794 
63795 /* PWM_LOOP: Number of playbacks of a loop */
63796   #define PWM_LOOP_ResetValue (0x00000000UL)         /*!< Reset value of LOOP register.                                        */
63797 
63798 /* CNT @Bits 0..15 : Number of playbacks of pattern cycles */
63799   #define PWM_LOOP_CNT_Pos (0UL)                     /*!< Position of CNT field.                                               */
63800   #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field.                                          */
63801   #define PWM_LOOP_CNT_Min (0x0UL)                   /*!< Min enumerator value of CNT field.                                   */
63802   #define PWM_LOOP_CNT_Max (0x0UL)                   /*!< Max enumerator value of CNT field.                                   */
63803   #define PWM_LOOP_CNT_Disabled (0x0000UL)           /*!< Looping disabled (stop at the end of the sequence)                   */
63804 
63805 
63806 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
63807 
63808 /* =========================================================================================================================== */
63809 /* ================                                           QDEC                                           ================ */
63810 /* =========================================================================================================================== */
63811 
63812 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
63813 
63814 /* ==================================================== Struct QDEC_PSEL ===================================================== */
63815 /**
63816   * @brief PSEL [QDEC_PSEL] (unspecified)
63817   */
63818 typedef struct {
63819   __IOM uint32_t  LED;                               /*!< (@ 0x00000000) Pin select for LED signal                             */
63820   __IOM uint32_t  A;                                 /*!< (@ 0x00000004) Pin select for A signal                               */
63821   __IOM uint32_t  B;                                 /*!< (@ 0x00000008) Pin select for B signal                               */
63822 } NRF_QDEC_PSEL_Type;                                /*!< Size = 12 (0x00C)                                                    */
63823 
63824 /* QDEC_PSEL_LED: Pin select for LED signal */
63825   #define QDEC_PSEL_LED_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of LED register.                                         */
63826 
63827 /* PIN @Bits 0..4 : Pin number */
63828   #define QDEC_PSEL_LED_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
63829   #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field.                                  */
63830   #define QDEC_PSEL_LED_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
63831   #define QDEC_PSEL_LED_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
63832 
63833 /* PORT @Bits 5..8 : Port number */
63834   #define QDEC_PSEL_LED_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
63835   #define QDEC_PSEL_LED_PORT_Msk (0xFUL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field.                                */
63836   #define QDEC_PSEL_LED_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
63837   #define QDEC_PSEL_LED_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
63838 
63839 /* CONNECT @Bit 31 : Connection */
63840   #define QDEC_PSEL_LED_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
63841   #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
63842   #define QDEC_PSEL_LED_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
63843   #define QDEC_PSEL_LED_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
63844   #define QDEC_PSEL_LED_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
63845   #define QDEC_PSEL_LED_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
63846 
63847 
63848 /* QDEC_PSEL_A: Pin select for A signal */
63849   #define QDEC_PSEL_A_ResetValue (0xFFFFFFFFUL)      /*!< Reset value of A register.                                           */
63850 
63851 /* PIN @Bits 0..4 : Pin number */
63852   #define QDEC_PSEL_A_PIN_Pos (0UL)                  /*!< Position of PIN field.                                               */
63853   #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field.                                      */
63854   #define QDEC_PSEL_A_PIN_Min (0x0UL)                /*!< Min value of PIN field.                                              */
63855   #define QDEC_PSEL_A_PIN_Max (0x1FUL)               /*!< Max size of PIN field.                                               */
63856 
63857 /* PORT @Bits 5..8 : Port number */
63858   #define QDEC_PSEL_A_PORT_Pos (5UL)                 /*!< Position of PORT field.                                              */
63859   #define QDEC_PSEL_A_PORT_Msk (0xFUL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field.                                    */
63860   #define QDEC_PSEL_A_PORT_Min (0x0UL)               /*!< Min value of PORT field.                                             */
63861   #define QDEC_PSEL_A_PORT_Max (0xFUL)               /*!< Max size of PORT field.                                              */
63862 
63863 /* CONNECT @Bit 31 : Connection */
63864   #define QDEC_PSEL_A_CONNECT_Pos (31UL)             /*!< Position of CONNECT field.                                           */
63865   #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field.                           */
63866   #define QDEC_PSEL_A_CONNECT_Min (0x0UL)            /*!< Min enumerator value of CONNECT field.                               */
63867   #define QDEC_PSEL_A_CONNECT_Max (0x1UL)            /*!< Max enumerator value of CONNECT field.                               */
63868   #define QDEC_PSEL_A_CONNECT_Disconnected (0x1UL)   /*!< Disconnect                                                           */
63869   #define QDEC_PSEL_A_CONNECT_Connected (0x0UL)      /*!< Connect                                                              */
63870 
63871 
63872 /* QDEC_PSEL_B: Pin select for B signal */
63873   #define QDEC_PSEL_B_ResetValue (0xFFFFFFFFUL)      /*!< Reset value of B register.                                           */
63874 
63875 /* PIN @Bits 0..4 : Pin number */
63876   #define QDEC_PSEL_B_PIN_Pos (0UL)                  /*!< Position of PIN field.                                               */
63877   #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field.                                      */
63878   #define QDEC_PSEL_B_PIN_Min (0x0UL)                /*!< Min value of PIN field.                                              */
63879   #define QDEC_PSEL_B_PIN_Max (0x1FUL)               /*!< Max size of PIN field.                                               */
63880 
63881 /* PORT @Bits 5..8 : Port number */
63882   #define QDEC_PSEL_B_PORT_Pos (5UL)                 /*!< Position of PORT field.                                              */
63883   #define QDEC_PSEL_B_PORT_Msk (0xFUL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field.                                    */
63884   #define QDEC_PSEL_B_PORT_Min (0x0UL)               /*!< Min value of PORT field.                                             */
63885   #define QDEC_PSEL_B_PORT_Max (0xFUL)               /*!< Max size of PORT field.                                              */
63886 
63887 /* CONNECT @Bit 31 : Connection */
63888   #define QDEC_PSEL_B_CONNECT_Pos (31UL)             /*!< Position of CONNECT field.                                           */
63889   #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field.                           */
63890   #define QDEC_PSEL_B_CONNECT_Min (0x0UL)            /*!< Min enumerator value of CONNECT field.                               */
63891   #define QDEC_PSEL_B_CONNECT_Max (0x1UL)            /*!< Max enumerator value of CONNECT field.                               */
63892   #define QDEC_PSEL_B_CONNECT_Disconnected (0x1UL)   /*!< Disconnect                                                           */
63893   #define QDEC_PSEL_B_CONNECT_Connected (0x0UL)      /*!< Connect                                                              */
63894 
63895 
63896 /* ======================================================= Struct QDEC ======================================================= */
63897 /**
63898   * @brief Quadrature Decoder
63899   */
63900   typedef struct {                                   /*!< QDEC Structure                                                       */
63901     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Task starting the quadrature decoder                  */
63902     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Task stopping the quadrature decoder                  */
63903     __OM uint32_t TASKS_READCLRACC;                  /*!< (@ 0x00000008) Read and clear ACC and ACCDBL                         */
63904     __OM uint32_t TASKS_RDCLRACC;                    /*!< (@ 0x0000000C) Read and clear ACC                                    */
63905     __OM uint32_t TASKS_RDCLRDBL;                    /*!< (@ 0x00000010) Read and clear ACCDBL                                 */
63906     __IM uint32_t RESERVED[27];
63907     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
63908     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
63909     __IOM uint32_t SUBSCRIBE_READCLRACC;             /*!< (@ 0x00000088) Subscribe configuration for task READCLRACC           */
63910     __IOM uint32_t SUBSCRIBE_RDCLRACC;               /*!< (@ 0x0000008C) Subscribe configuration for task RDCLRACC             */
63911     __IOM uint32_t SUBSCRIBE_RDCLRDBL;               /*!< (@ 0x00000090) Subscribe configuration for task RDCLRDBL             */
63912     __IM uint32_t RESERVED1[27];
63913     __IOM uint32_t EVENTS_SAMPLERDY;                 /*!< (@ 0x00000100) Event being generated for every new sample value
63914                                                                          written to the SAMPLE register*/
63915     __IOM uint32_t EVENTS_REPORTRDY;                 /*!< (@ 0x00000104) Non-null report ready                                 */
63916     __IOM uint32_t EVENTS_ACCOF;                     /*!< (@ 0x00000108) ACC or ACCDBL register overflow                       */
63917     __IOM uint32_t EVENTS_DBLRDY;                    /*!< (@ 0x0000010C) Double displacement(s) detected                       */
63918     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000110) QDEC has been stopped                                 */
63919     __IM uint32_t RESERVED2[27];
63920     __IOM uint32_t PUBLISH_SAMPLERDY;                /*!< (@ 0x00000180) Publish configuration for event SAMPLERDY             */
63921     __IOM uint32_t PUBLISH_REPORTRDY;                /*!< (@ 0x00000184) Publish configuration for event REPORTRDY             */
63922     __IOM uint32_t PUBLISH_ACCOF;                    /*!< (@ 0x00000188) Publish configuration for event ACCOF                 */
63923     __IOM uint32_t PUBLISH_DBLRDY;                   /*!< (@ 0x0000018C) Publish configuration for event DBLRDY                */
63924     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000190) Publish configuration for event STOPPED               */
63925     __IM uint32_t RESERVED3[27];
63926     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
63927     __IM uint32_t RESERVED4[64];
63928     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
63929     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
63930     __IM uint32_t RESERVED5[125];
63931     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable the quadrature decoder                         */
63932     __IOM uint32_t LEDPOL;                           /*!< (@ 0x00000504) LED output pin polarity                               */
63933     __IOM uint32_t SAMPLEPER;                        /*!< (@ 0x00000508) Sample period                                         */
63934     __IM int32_t  SAMPLE;                            /*!< (@ 0x0000050C) Motion sample value                                   */
63935     __IOM uint32_t REPORTPER;                        /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY and
63936                                                                          DBLRDY events can be generated*/
63937     __IM int32_t  ACC;                               /*!< (@ 0x00000514) Register accumulating the valid transitions           */
63938     __IM int32_t  ACCREAD;                           /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the READCLRACC
63939                                                                          or RDCLRACC task*/
63940     __IOM NRF_QDEC_PSEL_Type PSEL;                   /*!< (@ 0x0000051C) (unspecified)                                         */
63941     __IOM uint32_t DBFEN;                            /*!< (@ 0x00000528) Enable input debounce filters                         */
63942     __IM uint32_t RESERVED6[5];
63943     __IOM uint32_t LEDPRE;                           /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling  */
63944     __IM uint32_t ACCDBL;                            /*!< (@ 0x00000544) Register accumulating the number of detected double
63945                                                                          transitions*/
63946     __IM uint32_t ACCDBLREAD;                        /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC or
63947                                                                          RDCLRDBL task*/
63948   } NRF_QDEC_Type;                                   /*!< Size = 1356 (0x54C)                                                  */
63949 
63950 /* QDEC_TASKS_START: Task starting the quadrature decoder */
63951   #define QDEC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */
63952 
63953 /* TASKS_START @Bit 0 : Task starting the quadrature decoder */
63954   #define QDEC_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
63955   #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
63956   #define QDEC_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
63957   #define QDEC_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
63958   #define QDEC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */
63959 
63960 
63961 /* QDEC_TASKS_STOP: Task stopping the quadrature decoder */
63962   #define QDEC_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */
63963 
63964 /* TASKS_STOP @Bit 0 : Task stopping the quadrature decoder */
63965   #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
63966   #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
63967   #define QDEC_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
63968   #define QDEC_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
63969   #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */
63970 
63971 
63972 /* QDEC_TASKS_READCLRACC: Read and clear ACC and ACCDBL */
63973   #define QDEC_TASKS_READCLRACC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_READCLRACC register.                       */
63974 
63975 /* TASKS_READCLRACC @Bit 0 : Read and clear ACC and ACCDBL */
63976   #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field.                            */
63977   #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of
63978                                                                             TASKS_READCLRACC field.*/
63979   #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Min (0x1UL) /*!< Min enumerator value of TASKS_READCLRACC field.              */
63980   #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Max (0x1UL) /*!< Max enumerator value of TASKS_READCLRACC field.              */
63981   #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (0x1UL) /*!< Trigger task                                             */
63982 
63983 
63984 /* QDEC_TASKS_RDCLRACC: Read and clear ACC */
63985   #define QDEC_TASKS_RDCLRACC_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RDCLRACC register.                           */
63986 
63987 /* TASKS_RDCLRACC @Bit 0 : Read and clear ACC */
63988   #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field.                                  */
63989   #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of
63990                                                                             TASKS_RDCLRACC field.*/
63991   #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Min (0x1UL) /*!< Min enumerator value of TASKS_RDCLRACC field.                    */
63992   #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Max (0x1UL) /*!< Max enumerator value of TASKS_RDCLRACC field.                    */
63993   #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (0x1UL) /*!< Trigger task                                                 */
63994 
63995 
63996 /* QDEC_TASKS_RDCLRDBL: Read and clear ACCDBL */
63997   #define QDEC_TASKS_RDCLRDBL_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RDCLRDBL register.                           */
63998 
63999 /* TASKS_RDCLRDBL @Bit 0 : Read and clear ACCDBL */
64000   #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field.                                  */
64001   #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of
64002                                                                             TASKS_RDCLRDBL field.*/
64003   #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Min (0x1UL) /*!< Min enumerator value of TASKS_RDCLRDBL field.                    */
64004   #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Max (0x1UL) /*!< Max enumerator value of TASKS_RDCLRDBL field.                    */
64005   #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (0x1UL) /*!< Trigger task                                                 */
64006 
64007 
64008 /* QDEC_SUBSCRIBE_START: Subscribe configuration for task START */
64009   #define QDEC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                         */
64010 
64011 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
64012   #define QDEC_SUBSCRIBE_START_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
64013   #define QDEC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
64014   #define QDEC_SUBSCRIBE_START_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
64015   #define QDEC_SUBSCRIBE_START_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
64016 
64017 /* EN @Bit 31 : (unspecified) */
64018   #define QDEC_SUBSCRIBE_START_EN_Pos (31UL)         /*!< Position of EN field.                                                */
64019   #define QDEC_SUBSCRIBE_START_EN_Msk (0x1UL << QDEC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                        */
64020   #define QDEC_SUBSCRIBE_START_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
64021   #define QDEC_SUBSCRIBE_START_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
64022   #define QDEC_SUBSCRIBE_START_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
64023   #define QDEC_SUBSCRIBE_START_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
64024 
64025 
64026 /* QDEC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
64027   #define QDEC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */
64028 
64029 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
64030   #define QDEC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
64031   #define QDEC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
64032   #define QDEC_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
64033   #define QDEC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
64034 
64035 /* EN @Bit 31 : (unspecified) */
64036   #define QDEC_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
64037   #define QDEC_SUBSCRIBE_STOP_EN_Msk (0x1UL << QDEC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
64038   #define QDEC_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
64039   #define QDEC_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
64040   #define QDEC_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
64041   #define QDEC_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
64042 
64043 
64044 /* QDEC_SUBSCRIBE_READCLRACC: Subscribe configuration for task READCLRACC */
64045   #define QDEC_SUBSCRIBE_READCLRACC_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_READCLRACC register.               */
64046 
64047 /* CHIDX @Bits 0..7 : DPPI channel that task READCLRACC will subscribe to */
64048   #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
64049   #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_READCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
64050   #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                           */
64051   #define QDEC_SUBSCRIBE_READCLRACC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */
64052 
64053 /* EN @Bit 31 : (unspecified) */
64054   #define QDEC_SUBSCRIBE_READCLRACC_EN_Pos (31UL)    /*!< Position of EN field.                                                */
64055   #define QDEC_SUBSCRIBE_READCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_READCLRACC_EN_Pos) /*!< Bit mask of EN field.              */
64056   #define QDEC_SUBSCRIBE_READCLRACC_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
64057   #define QDEC_SUBSCRIBE_READCLRACC_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
64058   #define QDEC_SUBSCRIBE_READCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription                                              */
64059   #define QDEC_SUBSCRIBE_READCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription                                                */
64060 
64061 
64062 /* QDEC_SUBSCRIBE_RDCLRACC: Subscribe configuration for task RDCLRACC */
64063   #define QDEC_SUBSCRIBE_RDCLRACC_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RDCLRACC register.                   */
64064 
64065 /* CHIDX @Bits 0..7 : DPPI channel that task RDCLRACC will subscribe to */
64066   #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
64067   #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
64068   #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
64069   #define QDEC_SUBSCRIBE_RDCLRACC_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
64070 
64071 /* EN @Bit 31 : (unspecified) */
64072   #define QDEC_SUBSCRIBE_RDCLRACC_EN_Pos (31UL)      /*!< Position of EN field.                                                */
64073   #define QDEC_SUBSCRIBE_RDCLRACC_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRACC_EN_Pos) /*!< Bit mask of EN field.                  */
64074   #define QDEC_SUBSCRIBE_RDCLRACC_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
64075   #define QDEC_SUBSCRIBE_RDCLRACC_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
64076   #define QDEC_SUBSCRIBE_RDCLRACC_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
64077   #define QDEC_SUBSCRIBE_RDCLRACC_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
64078 
64079 
64080 /* QDEC_SUBSCRIBE_RDCLRDBL: Subscribe configuration for task RDCLRDBL */
64081   #define QDEC_SUBSCRIBE_RDCLRDBL_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RDCLRDBL register.                   */
64082 
64083 /* CHIDX @Bits 0..7 : DPPI channel that task RDCLRDBL will subscribe to */
64084   #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
64085   #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Msk (0xFFUL << QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
64086   #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
64087   #define QDEC_SUBSCRIBE_RDCLRDBL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
64088 
64089 /* EN @Bit 31 : (unspecified) */
64090   #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos (31UL)      /*!< Position of EN field.                                                */
64091   #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Msk (0x1UL << QDEC_SUBSCRIBE_RDCLRDBL_EN_Pos) /*!< Bit mask of EN field.                  */
64092   #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
64093   #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
64094   #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
64095   #define QDEC_SUBSCRIBE_RDCLRDBL_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
64096 
64097 
64098 /* QDEC_EVENTS_SAMPLERDY: Event being generated for every new sample value written to the SAMPLE register */
64099   #define QDEC_EVENTS_SAMPLERDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SAMPLERDY register.                       */
64100 
64101 /* EVENTS_SAMPLERDY @Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
64102   #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field.                            */
64103   #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of
64104                                                                             EVENTS_SAMPLERDY field.*/
64105   #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_SAMPLERDY field.              */
64106   #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_SAMPLERDY field.              */
64107   #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0x0UL) /*!< Event not generated                                 */
64108   #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (0x1UL) /*!< Event generated                                        */
64109 
64110 
64111 /* QDEC_EVENTS_REPORTRDY: Non-null report ready */
64112   #define QDEC_EVENTS_REPORTRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_REPORTRDY register.                       */
64113 
64114 /* EVENTS_REPORTRDY @Bit 0 : Non-null report ready */
64115   #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field.                            */
64116   #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of
64117                                                                             EVENTS_REPORTRDY field.*/
64118   #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_REPORTRDY field.              */
64119   #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_REPORTRDY field.              */
64120   #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0x0UL) /*!< Event not generated                                 */
64121   #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (0x1UL) /*!< Event generated                                        */
64122 
64123 
64124 /* QDEC_EVENTS_ACCOF: ACC or ACCDBL register overflow */
64125   #define QDEC_EVENTS_ACCOF_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACCOF register.                               */
64126 
64127 /* EVENTS_ACCOF @Bit 0 : ACC or ACCDBL register overflow */
64128   #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL)   /*!< Position of EVENTS_ACCOF field.                                      */
64129   #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field.*/
64130   #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACCOF field.                          */
64131   #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACCOF field.                          */
64132   #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0x0UL) /*!< Event not generated                                         */
64133   #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (0x1UL) /*!< Event generated                                                */
64134 
64135 
64136 /* QDEC_EVENTS_DBLRDY: Double displacement(s) detected */
64137   #define QDEC_EVENTS_DBLRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DBLRDY register.                             */
64138 
64139 /* EVENTS_DBLRDY @Bit 0 : Double displacement(s) detected */
64140   #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field.                                     */
64141   #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY
64142                                                                             field.*/
64143   #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_DBLRDY field.                       */
64144   #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_DBLRDY field.                       */
64145   #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0x0UL) /*!< Event not generated                                       */
64146   #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (0x1UL) /*!< Event generated                                              */
64147 
64148 
64149 /* QDEC_EVENTS_STOPPED: QDEC has been stopped */
64150   #define QDEC_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                           */
64151 
64152 /* EVENTS_STOPPED @Bit 0 : QDEC has been stopped */
64153   #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                  */
64154   #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
64155                                                                             EVENTS_STOPPED field.*/
64156   #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                    */
64157   #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                    */
64158   #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                     */
64159   #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                            */
64160 
64161 
64162 /* QDEC_PUBLISH_SAMPLERDY: Publish configuration for event SAMPLERDY */
64163   #define QDEC_PUBLISH_SAMPLERDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SAMPLERDY register.                     */
64164 
64165 /* CHIDX @Bits 0..7 : DPPI channel that event SAMPLERDY will publish to */
64166   #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
64167   #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_SAMPLERDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
64168   #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
64169   #define QDEC_PUBLISH_SAMPLERDY_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
64170 
64171 /* EN @Bit 31 : (unspecified) */
64172   #define QDEC_PUBLISH_SAMPLERDY_EN_Pos (31UL)       /*!< Position of EN field.                                                */
64173   #define QDEC_PUBLISH_SAMPLERDY_EN_Msk (0x1UL << QDEC_PUBLISH_SAMPLERDY_EN_Pos) /*!< Bit mask of EN field.                    */
64174   #define QDEC_PUBLISH_SAMPLERDY_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
64175   #define QDEC_PUBLISH_SAMPLERDY_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
64176   #define QDEC_PUBLISH_SAMPLERDY_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
64177   #define QDEC_PUBLISH_SAMPLERDY_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
64178 
64179 
64180 /* QDEC_PUBLISH_REPORTRDY: Publish configuration for event REPORTRDY */
64181   #define QDEC_PUBLISH_REPORTRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_REPORTRDY register.                     */
64182 
64183 /* CHIDX @Bits 0..7 : DPPI channel that event REPORTRDY will publish to */
64184   #define QDEC_PUBLISH_REPORTRDY_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
64185   #define QDEC_PUBLISH_REPORTRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_REPORTRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
64186   #define QDEC_PUBLISH_REPORTRDY_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
64187   #define QDEC_PUBLISH_REPORTRDY_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
64188 
64189 /* EN @Bit 31 : (unspecified) */
64190   #define QDEC_PUBLISH_REPORTRDY_EN_Pos (31UL)       /*!< Position of EN field.                                                */
64191   #define QDEC_PUBLISH_REPORTRDY_EN_Msk (0x1UL << QDEC_PUBLISH_REPORTRDY_EN_Pos) /*!< Bit mask of EN field.                    */
64192   #define QDEC_PUBLISH_REPORTRDY_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
64193   #define QDEC_PUBLISH_REPORTRDY_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
64194   #define QDEC_PUBLISH_REPORTRDY_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
64195   #define QDEC_PUBLISH_REPORTRDY_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
64196 
64197 
64198 /* QDEC_PUBLISH_ACCOF: Publish configuration for event ACCOF */
64199   #define QDEC_PUBLISH_ACCOF_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACCOF register.                             */
64200 
64201 /* CHIDX @Bits 0..7 : DPPI channel that event ACCOF will publish to */
64202   #define QDEC_PUBLISH_ACCOF_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
64203   #define QDEC_PUBLISH_ACCOF_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_ACCOF_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
64204   #define QDEC_PUBLISH_ACCOF_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
64205   #define QDEC_PUBLISH_ACCOF_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
64206 
64207 /* EN @Bit 31 : (unspecified) */
64208   #define QDEC_PUBLISH_ACCOF_EN_Pos (31UL)           /*!< Position of EN field.                                                */
64209   #define QDEC_PUBLISH_ACCOF_EN_Msk (0x1UL << QDEC_PUBLISH_ACCOF_EN_Pos) /*!< Bit mask of EN field.                            */
64210   #define QDEC_PUBLISH_ACCOF_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
64211   #define QDEC_PUBLISH_ACCOF_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
64212   #define QDEC_PUBLISH_ACCOF_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
64213   #define QDEC_PUBLISH_ACCOF_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
64214 
64215 
64216 /* QDEC_PUBLISH_DBLRDY: Publish configuration for event DBLRDY */
64217   #define QDEC_PUBLISH_DBLRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DBLRDY register.                           */
64218 
64219 /* CHIDX @Bits 0..7 : DPPI channel that event DBLRDY will publish to */
64220   #define QDEC_PUBLISH_DBLRDY_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
64221   #define QDEC_PUBLISH_DBLRDY_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_DBLRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
64222   #define QDEC_PUBLISH_DBLRDY_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
64223   #define QDEC_PUBLISH_DBLRDY_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
64224 
64225 /* EN @Bit 31 : (unspecified) */
64226   #define QDEC_PUBLISH_DBLRDY_EN_Pos (31UL)          /*!< Position of EN field.                                                */
64227   #define QDEC_PUBLISH_DBLRDY_EN_Msk (0x1UL << QDEC_PUBLISH_DBLRDY_EN_Pos) /*!< Bit mask of EN field.                          */
64228   #define QDEC_PUBLISH_DBLRDY_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
64229   #define QDEC_PUBLISH_DBLRDY_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
64230   #define QDEC_PUBLISH_DBLRDY_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
64231   #define QDEC_PUBLISH_DBLRDY_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
64232 
64233 
64234 /* QDEC_PUBLISH_STOPPED: Publish configuration for event STOPPED */
64235   #define QDEC_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                         */
64236 
64237 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
64238   #define QDEC_PUBLISH_STOPPED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
64239   #define QDEC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << QDEC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
64240   #define QDEC_PUBLISH_STOPPED_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
64241   #define QDEC_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
64242 
64243 /* EN @Bit 31 : (unspecified) */
64244   #define QDEC_PUBLISH_STOPPED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
64245   #define QDEC_PUBLISH_STOPPED_EN_Msk (0x1UL << QDEC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                        */
64246   #define QDEC_PUBLISH_STOPPED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
64247   #define QDEC_PUBLISH_STOPPED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
64248   #define QDEC_PUBLISH_STOPPED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
64249   #define QDEC_PUBLISH_STOPPED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
64250 
64251 
64252 /* QDEC_SHORTS: Shortcuts between local events and tasks */
64253   #define QDEC_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */
64254 
64255 /* REPORTRDY_READCLRACC @Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
64256   #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field.                              */
64257   #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of
64258                                                                             REPORTRDY_READCLRACC field.*/
64259   #define QDEC_SHORTS_REPORTRDY_READCLRACC_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_READCLRACC field.                */
64260   #define QDEC_SHORTS_REPORTRDY_READCLRACC_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_READCLRACC field.                */
64261   #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut                                              */
64262   #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut                                                */
64263 
64264 /* SAMPLERDY_STOP @Bit 1 : Shortcut between event SAMPLERDY and task STOP */
64265   #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL)       /*!< Position of SAMPLERDY_STOP field.                                    */
64266   #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field.      */
64267   #define QDEC_SHORTS_SAMPLERDY_STOP_Min (0x0UL)     /*!< Min enumerator value of SAMPLERDY_STOP field.                        */
64268   #define QDEC_SHORTS_SAMPLERDY_STOP_Max (0x1UL)     /*!< Max enumerator value of SAMPLERDY_STOP field.                        */
64269   #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
64270   #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
64271 
64272 /* REPORTRDY_RDCLRACC @Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
64273   #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL)   /*!< Position of REPORTRDY_RDCLRACC field.                                */
64274   #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC
64275                                                                             field.*/
64276   #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Min (0x0UL) /*!< Min enumerator value of REPORTRDY_RDCLRACC field.                    */
64277   #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Max (0x1UL) /*!< Max enumerator value of REPORTRDY_RDCLRACC field.                    */
64278   #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0x0UL) /*!< Disable shortcut                                                */
64279   #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (0x1UL) /*!< Enable shortcut                                                  */
64280 
64281 /* REPORTRDY_STOP @Bit 3 : Shortcut between event REPORTRDY and task STOP */
64282   #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL)       /*!< Position of REPORTRDY_STOP field.                                    */
64283   #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field.      */
64284   #define QDEC_SHORTS_REPORTRDY_STOP_Min (0x0UL)     /*!< Min enumerator value of REPORTRDY_STOP field.                        */
64285   #define QDEC_SHORTS_REPORTRDY_STOP_Max (0x1UL)     /*!< Max enumerator value of REPORTRDY_STOP field.                        */
64286   #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
64287   #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
64288 
64289 /* DBLRDY_RDCLRDBL @Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
64290   #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL)      /*!< Position of DBLRDY_RDCLRDBL field.                                   */
64291   #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field.   */
64292   #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Min (0x0UL)    /*!< Min enumerator value of DBLRDY_RDCLRDBL field.                       */
64293   #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Max (0x1UL)    /*!< Max enumerator value of DBLRDY_RDCLRDBL field.                       */
64294   #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0x0UL) /*!< Disable shortcut                                                   */
64295   #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (0x1UL) /*!< Enable shortcut                                                     */
64296 
64297 /* DBLRDY_STOP @Bit 5 : Shortcut between event DBLRDY and task STOP */
64298   #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL)          /*!< Position of DBLRDY_STOP field.                                       */
64299   #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field.               */
64300   #define QDEC_SHORTS_DBLRDY_STOP_Min (0x0UL)        /*!< Min enumerator value of DBLRDY_STOP field.                           */
64301   #define QDEC_SHORTS_DBLRDY_STOP_Max (0x1UL)        /*!< Max enumerator value of DBLRDY_STOP field.                           */
64302   #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
64303   #define QDEC_SHORTS_DBLRDY_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */
64304 
64305 /* SAMPLERDY_READCLRACC @Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
64306   #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field.                              */
64307   #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of
64308                                                                             SAMPLERDY_READCLRACC field.*/
64309   #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Min (0x0UL) /*!< Min enumerator value of SAMPLERDY_READCLRACC field.                */
64310   #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Max (0x1UL) /*!< Max enumerator value of SAMPLERDY_READCLRACC field.                */
64311   #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0x0UL) /*!< Disable shortcut                                              */
64312   #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (0x1UL) /*!< Enable shortcut                                                */
64313 
64314 
64315 /* QDEC_INTENSET: Enable interrupt */
64316   #define QDEC_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */
64317 
64318 /* SAMPLERDY @Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
64319   #define QDEC_INTENSET_SAMPLERDY_Pos (0UL)          /*!< Position of SAMPLERDY field.                                         */
64320   #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field.                 */
64321   #define QDEC_INTENSET_SAMPLERDY_Min (0x0UL)        /*!< Min enumerator value of SAMPLERDY field.                             */
64322   #define QDEC_INTENSET_SAMPLERDY_Max (0x1UL)        /*!< Max enumerator value of SAMPLERDY field.                             */
64323   #define QDEC_INTENSET_SAMPLERDY_Set (0x1UL)        /*!< Enable                                                               */
64324   #define QDEC_INTENSET_SAMPLERDY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
64325   #define QDEC_INTENSET_SAMPLERDY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
64326 
64327 /* REPORTRDY @Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
64328   #define QDEC_INTENSET_REPORTRDY_Pos (1UL)          /*!< Position of REPORTRDY field.                                         */
64329   #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field.                 */
64330   #define QDEC_INTENSET_REPORTRDY_Min (0x0UL)        /*!< Min enumerator value of REPORTRDY field.                             */
64331   #define QDEC_INTENSET_REPORTRDY_Max (0x1UL)        /*!< Max enumerator value of REPORTRDY field.                             */
64332   #define QDEC_INTENSET_REPORTRDY_Set (0x1UL)        /*!< Enable                                                               */
64333   #define QDEC_INTENSET_REPORTRDY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
64334   #define QDEC_INTENSET_REPORTRDY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
64335 
64336 /* ACCOF @Bit 2 : Write '1' to enable interrupt for event ACCOF */
64337   #define QDEC_INTENSET_ACCOF_Pos (2UL)              /*!< Position of ACCOF field.                                             */
64338   #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field.                             */
64339   #define QDEC_INTENSET_ACCOF_Min (0x0UL)            /*!< Min enumerator value of ACCOF field.                                 */
64340   #define QDEC_INTENSET_ACCOF_Max (0x1UL)            /*!< Max enumerator value of ACCOF field.                                 */
64341   #define QDEC_INTENSET_ACCOF_Set (0x1UL)            /*!< Enable                                                               */
64342   #define QDEC_INTENSET_ACCOF_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
64343   #define QDEC_INTENSET_ACCOF_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
64344 
64345 /* DBLRDY @Bit 3 : Write '1' to enable interrupt for event DBLRDY */
64346   #define QDEC_INTENSET_DBLRDY_Pos (3UL)             /*!< Position of DBLRDY field.                                            */
64347   #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field.                          */
64348   #define QDEC_INTENSET_DBLRDY_Min (0x0UL)           /*!< Min enumerator value of DBLRDY field.                                */
64349   #define QDEC_INTENSET_DBLRDY_Max (0x1UL)           /*!< Max enumerator value of DBLRDY field.                                */
64350   #define QDEC_INTENSET_DBLRDY_Set (0x1UL)           /*!< Enable                                                               */
64351   #define QDEC_INTENSET_DBLRDY_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
64352   #define QDEC_INTENSET_DBLRDY_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
64353 
64354 /* STOPPED @Bit 4 : Write '1' to enable interrupt for event STOPPED */
64355   #define QDEC_INTENSET_STOPPED_Pos (4UL)            /*!< Position of STOPPED field.                                           */
64356   #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
64357   #define QDEC_INTENSET_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
64358   #define QDEC_INTENSET_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
64359   #define QDEC_INTENSET_STOPPED_Set (0x1UL)          /*!< Enable                                                               */
64360   #define QDEC_INTENSET_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
64361   #define QDEC_INTENSET_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
64362 
64363 
64364 /* QDEC_INTENCLR: Disable interrupt */
64365   #define QDEC_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */
64366 
64367 /* SAMPLERDY @Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
64368   #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL)          /*!< Position of SAMPLERDY field.                                         */
64369   #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field.                 */
64370   #define QDEC_INTENCLR_SAMPLERDY_Min (0x0UL)        /*!< Min enumerator value of SAMPLERDY field.                             */
64371   #define QDEC_INTENCLR_SAMPLERDY_Max (0x1UL)        /*!< Max enumerator value of SAMPLERDY field.                             */
64372   #define QDEC_INTENCLR_SAMPLERDY_Clear (0x1UL)      /*!< Disable                                                              */
64373   #define QDEC_INTENCLR_SAMPLERDY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
64374   #define QDEC_INTENCLR_SAMPLERDY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
64375 
64376 /* REPORTRDY @Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
64377   #define QDEC_INTENCLR_REPORTRDY_Pos (1UL)          /*!< Position of REPORTRDY field.                                         */
64378   #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field.                 */
64379   #define QDEC_INTENCLR_REPORTRDY_Min (0x0UL)        /*!< Min enumerator value of REPORTRDY field.                             */
64380   #define QDEC_INTENCLR_REPORTRDY_Max (0x1UL)        /*!< Max enumerator value of REPORTRDY field.                             */
64381   #define QDEC_INTENCLR_REPORTRDY_Clear (0x1UL)      /*!< Disable                                                              */
64382   #define QDEC_INTENCLR_REPORTRDY_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
64383   #define QDEC_INTENCLR_REPORTRDY_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
64384 
64385 /* ACCOF @Bit 2 : Write '1' to disable interrupt for event ACCOF */
64386   #define QDEC_INTENCLR_ACCOF_Pos (2UL)              /*!< Position of ACCOF field.                                             */
64387   #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field.                             */
64388   #define QDEC_INTENCLR_ACCOF_Min (0x0UL)            /*!< Min enumerator value of ACCOF field.                                 */
64389   #define QDEC_INTENCLR_ACCOF_Max (0x1UL)            /*!< Max enumerator value of ACCOF field.                                 */
64390   #define QDEC_INTENCLR_ACCOF_Clear (0x1UL)          /*!< Disable                                                              */
64391   #define QDEC_INTENCLR_ACCOF_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
64392   #define QDEC_INTENCLR_ACCOF_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
64393 
64394 /* DBLRDY @Bit 3 : Write '1' to disable interrupt for event DBLRDY */
64395   #define QDEC_INTENCLR_DBLRDY_Pos (3UL)             /*!< Position of DBLRDY field.                                            */
64396   #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field.                          */
64397   #define QDEC_INTENCLR_DBLRDY_Min (0x0UL)           /*!< Min enumerator value of DBLRDY field.                                */
64398   #define QDEC_INTENCLR_DBLRDY_Max (0x1UL)           /*!< Max enumerator value of DBLRDY field.                                */
64399   #define QDEC_INTENCLR_DBLRDY_Clear (0x1UL)         /*!< Disable                                                              */
64400   #define QDEC_INTENCLR_DBLRDY_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
64401   #define QDEC_INTENCLR_DBLRDY_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
64402 
64403 /* STOPPED @Bit 4 : Write '1' to disable interrupt for event STOPPED */
64404   #define QDEC_INTENCLR_STOPPED_Pos (4UL)            /*!< Position of STOPPED field.                                           */
64405   #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
64406   #define QDEC_INTENCLR_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
64407   #define QDEC_INTENCLR_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
64408   #define QDEC_INTENCLR_STOPPED_Clear (0x1UL)        /*!< Disable                                                              */
64409   #define QDEC_INTENCLR_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
64410   #define QDEC_INTENCLR_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
64411 
64412 
64413 /* QDEC_ENABLE: Enable the quadrature decoder */
64414   #define QDEC_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */
64415 
64416 /* ENABLE @Bit 0 : Enable or disable the quadrature decoder */
64417   #define QDEC_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
64418   #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
64419   #define QDEC_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
64420   #define QDEC_ENABLE_ENABLE_Max (0x1UL)             /*!< Max enumerator value of ENABLE field.                                */
64421   #define QDEC_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable                                                              */
64422   #define QDEC_ENABLE_ENABLE_Enabled (0x1UL)         /*!< Enable                                                               */
64423 
64424 
64425 /* QDEC_LEDPOL: LED output pin polarity */
64426   #define QDEC_LEDPOL_ResetValue (0x00000000UL)      /*!< Reset value of LEDPOL register.                                      */
64427 
64428 /* LEDPOL @Bit 0 : LED output pin polarity */
64429   #define QDEC_LEDPOL_LEDPOL_Pos (0UL)               /*!< Position of LEDPOL field.                                            */
64430   #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field.                              */
64431   #define QDEC_LEDPOL_LEDPOL_Min (0x0UL)             /*!< Min enumerator value of LEDPOL field.                                */
64432   #define QDEC_LEDPOL_LEDPOL_Max (0x1UL)             /*!< Max enumerator value of LEDPOL field.                                */
64433   #define QDEC_LEDPOL_LEDPOL_ActiveLow (0x0UL)       /*!< Led active on output pin low                                         */
64434   #define QDEC_LEDPOL_LEDPOL_ActiveHigh (0x1UL)      /*!< Led active on output pin high                                        */
64435 
64436 
64437 /* QDEC_SAMPLEPER: Sample period */
64438   #define QDEC_SAMPLEPER_ResetValue (0x00000000UL)   /*!< Reset value of SAMPLEPER register.                                   */
64439 
64440 /* SAMPLEPER @Bits 0..3 : Sample period. The SAMPLE register will be updated for every new sample */
64441   #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL)         /*!< Position of SAMPLEPER field.                                         */
64442   #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field.               */
64443   #define QDEC_SAMPLEPER_SAMPLEPER_Min (0x0UL)       /*!< Min enumerator value of SAMPLEPER field.                             */
64444   #define QDEC_SAMPLEPER_SAMPLEPER_Max (0xAUL)       /*!< Max enumerator value of SAMPLEPER field.                             */
64445   #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x0UL)     /*!< 128 us                                                               */
64446   #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x1UL)     /*!< 256 us                                                               */
64447   #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x2UL)     /*!< 512 us                                                               */
64448   #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x3UL)    /*!< 1024 us                                                              */
64449   #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x4UL)    /*!< 2048 us                                                              */
64450   #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x5UL)    /*!< 4096 us                                                              */
64451   #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x6UL)    /*!< 8192 us                                                              */
64452   #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x7UL)   /*!< 16384 us                                                             */
64453   #define QDEC_SAMPLEPER_SAMPLEPER_32ms (0x8UL)      /*!< 32768 us                                                             */
64454   #define QDEC_SAMPLEPER_SAMPLEPER_65ms (0x9UL)      /*!< 65536 us                                                             */
64455   #define QDEC_SAMPLEPER_SAMPLEPER_131ms (0xAUL)     /*!< 131072 us                                                            */
64456 
64457 
64458 /* QDEC_SAMPLE: Motion sample value */
64459   #define QDEC_SAMPLE_ResetValue (0x00000000UL)      /*!< Reset value of SAMPLE register.                                      */
64460 
64461 /* SAMPLE @Bits 0..31 : Last motion sample */
64462   #define QDEC_SAMPLE_SAMPLE_Pos (0UL)               /*!< Position of SAMPLE field.                                            */
64463   #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field.                       */
64464   #define QDEC_SAMPLE_SAMPLE_Min (0xFFFFFFFFFFFFFFFFUL) /*!< Min value of SAMPLE field.                                        */
64465   #define QDEC_SAMPLE_SAMPLE_Max (0x2UL)             /*!< Max size of SAMPLE field.                                            */
64466 
64467 
64468 /* QDEC_REPORTPER: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
64469   #define QDEC_REPORTPER_ResetValue (0x00000000UL)   /*!< Reset value of REPORTPER register.                                   */
64470 
64471 /* REPORTPER @Bits 0..3 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY
64472                           events can be generated. */
64473 
64474   #define QDEC_REPORTPER_REPORTPER_Pos (0UL)         /*!< Position of REPORTPER field.                                         */
64475   #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field.               */
64476   #define QDEC_REPORTPER_REPORTPER_Min (0x0UL)       /*!< Min enumerator value of REPORTPER field.                             */
64477   #define QDEC_REPORTPER_REPORTPER_Max (0x8UL)       /*!< Max enumerator value of REPORTPER field.                             */
64478   #define QDEC_REPORTPER_REPORTPER_10Smpl (0x0UL)    /*!< 10 samples/report                                                    */
64479   #define QDEC_REPORTPER_REPORTPER_40Smpl (0x1UL)    /*!< 40 samples/report                                                    */
64480   #define QDEC_REPORTPER_REPORTPER_80Smpl (0x2UL)    /*!< 80 samples/report                                                    */
64481   #define QDEC_REPORTPER_REPORTPER_120Smpl (0x3UL)   /*!< 120 samples/report                                                   */
64482   #define QDEC_REPORTPER_REPORTPER_160Smpl (0x4UL)   /*!< 160 samples/report                                                   */
64483   #define QDEC_REPORTPER_REPORTPER_200Smpl (0x5UL)   /*!< 200 samples/report                                                   */
64484   #define QDEC_REPORTPER_REPORTPER_240Smpl (0x6UL)   /*!< 240 samples/report                                                   */
64485   #define QDEC_REPORTPER_REPORTPER_280Smpl (0x7UL)   /*!< 280 samples/report                                                   */
64486   #define QDEC_REPORTPER_REPORTPER_1Smpl (0x8UL)     /*!< 1 sample/report                                                      */
64487 
64488 
64489 /* QDEC_ACC: Register accumulating the valid transitions */
64490   #define QDEC_ACC_ResetValue (0x00000000UL)         /*!< Reset value of ACC register.                                         */
64491 
64492 /* ACC @Bits 0..31 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */
64493   #define QDEC_ACC_ACC_Pos (0UL)                     /*!< Position of ACC field.                                               */
64494   #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field.                                      */
64495   #define QDEC_ACC_ACC_Min (0xFFFFFFFFFFFFFC00UL)    /*!< Min value of ACC field.                                              */
64496   #define QDEC_ACC_ACC_Max (0x3FFUL)                 /*!< Max size of ACC field.                                               */
64497 
64498 
64499 /* QDEC_ACCREAD: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
64500   #define QDEC_ACCREAD_ResetValue (0x00000000UL)     /*!< Reset value of ACCREAD register.                                     */
64501 
64502 /* ACCREAD @Bits 0..31 : Snapshot of the ACC register. */
64503   #define QDEC_ACCREAD_ACCREAD_Pos (0UL)             /*!< Position of ACCREAD field.                                           */
64504   #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field.                  */
64505   #define QDEC_ACCREAD_ACCREAD_Min (0xFFFFFFFFFFFFFC00UL) /*!< Min value of ACCREAD field.                                     */
64506   #define QDEC_ACCREAD_ACCREAD_Max (0x3FFUL)         /*!< Max size of ACCREAD field.                                           */
64507 
64508 
64509 /* QDEC_DBFEN: Enable input debounce filters */
64510   #define QDEC_DBFEN_ResetValue (0x00000000UL)       /*!< Reset value of DBFEN register.                                       */
64511 
64512 /* DBFEN @Bit 0 : Enable input debounce filters */
64513   #define QDEC_DBFEN_DBFEN_Pos (0UL)                 /*!< Position of DBFEN field.                                             */
64514   #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field.                                   */
64515   #define QDEC_DBFEN_DBFEN_Min (0x0UL)               /*!< Min enumerator value of DBFEN field.                                 */
64516   #define QDEC_DBFEN_DBFEN_Max (0x1UL)               /*!< Max enumerator value of DBFEN field.                                 */
64517   #define QDEC_DBFEN_DBFEN_Disabled (0x0UL)          /*!< Debounce input filters disabled                                      */
64518   #define QDEC_DBFEN_DBFEN_Enabled (0x1UL)           /*!< Debounce input filters enabled                                       */
64519 
64520 
64521 /* QDEC_LEDPRE: Time period the LED is switched ON prior to sampling */
64522   #define QDEC_LEDPRE_ResetValue (0x00000010UL)      /*!< Reset value of LEDPRE register.                                      */
64523 
64524 /* LEDPRE @Bits 0..8 : Period in us the LED is switched on prior to sampling */
64525   #define QDEC_LEDPRE_LEDPRE_Pos (0UL)               /*!< Position of LEDPRE field.                                            */
64526   #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field.                            */
64527   #define QDEC_LEDPRE_LEDPRE_Min (0x1UL)             /*!< Min value of LEDPRE field.                                           */
64528   #define QDEC_LEDPRE_LEDPRE_Max (0x1FFUL)           /*!< Max size of LEDPRE field.                                            */
64529 
64530 
64531 /* QDEC_ACCDBL: Register accumulating the number of detected double transitions */
64532   #define QDEC_ACCDBL_ResetValue (0x00000000UL)      /*!< Reset value of ACCDBL register.                                      */
64533 
64534 /* ACCDBL @Bits 0..3 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
64535   #define QDEC_ACCDBL_ACCDBL_Pos (0UL)               /*!< Position of ACCDBL field.                                            */
64536   #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field.                              */
64537   #define QDEC_ACCDBL_ACCDBL_Min (0x0UL)             /*!< Min value of ACCDBL field.                                           */
64538   #define QDEC_ACCDBL_ACCDBL_Max (0xFUL)             /*!< Max size of ACCDBL field.                                            */
64539 
64540 
64541 /* QDEC_ACCDBLREAD: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
64542   #define QDEC_ACCDBLREAD_ResetValue (0x00000000UL)  /*!< Reset value of ACCDBLREAD register.                                  */
64543 
64544 /* ACCDBLREAD @Bits 0..3 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is
64545                            triggered. */
64546 
64547   #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL)       /*!< Position of ACCDBLREAD field.                                        */
64548   #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field.          */
64549   #define QDEC_ACCDBLREAD_ACCDBLREAD_Min (0x0UL)     /*!< Min value of ACCDBLREAD field.                                       */
64550   #define QDEC_ACCDBLREAD_ACCDBLREAD_Max (0xFUL)     /*!< Max size of ACCDBLREAD field.                                        */
64551 
64552 
64553 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
64554 
64555 /* =========================================================================================================================== */
64556 /* ================                                           RADIO                                           ================ */
64557 /* =========================================================================================================================== */
64558 
64559 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
64560 
64561 /* ==================================================== Struct RADIO_PSEL ==================================================== */
64562 /**
64563   * @brief PSEL [RADIO_PSEL] (unspecified)
64564   */
64565 typedef struct {
64566   __IOM uint32_t  DFEGPIO[8];                        /*!< (@ 0x00000000) Pin select for DFE pin n                              */
64567 } NRF_RADIO_PSEL_Type;                               /*!< Size = 32 (0x020)                                                    */
64568 
64569 /* RADIO_PSEL_DFEGPIO: Pin select for DFE pin n */
64570   #define RADIO_PSEL_DFEGPIO_MaxCount (8UL)          /*!< Max size of DFEGPIO[8] array.                                        */
64571   #define RADIO_PSEL_DFEGPIO_MaxIndex (7UL)          /*!< Max index of DFEGPIO[8] array.                                       */
64572   #define RADIO_PSEL_DFEGPIO_MinIndex (0UL)          /*!< Min index of DFEGPIO[8] array.                                       */
64573   #define RADIO_PSEL_DFEGPIO_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DFEGPIO[8] register.                                */
64574 
64575 /* PIN @Bits 0..4 : Pin number */
64576   #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL)           /*!< Position of PIN field.                                               */
64577   #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field.                        */
64578   #define RADIO_PSEL_DFEGPIO_PIN_Min (0x0UL)         /*!< Min value of PIN field.                                              */
64579   #define RADIO_PSEL_DFEGPIO_PIN_Max (0x1FUL)        /*!< Max size of PIN field.                                               */
64580 
64581 /* PORT @Bits 5..8 : Port number */
64582   #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL)          /*!< Position of PORT field.                                              */
64583   #define RADIO_PSEL_DFEGPIO_PORT_Msk (0xFUL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field.                      */
64584   #define RADIO_PSEL_DFEGPIO_PORT_Min (0x0UL)        /*!< Min value of PORT field.                                             */
64585   #define RADIO_PSEL_DFEGPIO_PORT_Max (0x1UL)        /*!< Max size of PORT field.                                              */
64586 
64587 /* CONNECT @Bit 31 : Connection */
64588   #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL)      /*!< Position of CONNECT field.                                           */
64589   #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field.             */
64590   #define RADIO_PSEL_DFEGPIO_CONNECT_Min (0x0UL)     /*!< Min enumerator value of CONNECT field.                               */
64591   #define RADIO_PSEL_DFEGPIO_CONNECT_Max (0x1UL)     /*!< Max enumerator value of CONNECT field.                               */
64592   #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                      */
64593   #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0x0UL) /*!< Connect                                                            */
64594 
64595 
64596 
64597 /* ================================================= Struct RADIO_DFEPACKET ================================================== */
64598 /**
64599   * @brief DFEPACKET [RADIO_DFEPACKET] DFE packet EasyDMA channel
64600   */
64601 typedef struct {
64602   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
64603   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes to transfer                   */
64604   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last transaction   */
64605   __IOM uint32_t  ENABLE;                            /*!< (@ 0x0000000C) (unspecified)                                         */
64606 } NRF_RADIO_DFEPACKET_Type;                          /*!< Size = 16 (0x010)                                                    */
64607 
64608 /* RADIO_DFEPACKET_PTR: Data pointer */
64609   #define RADIO_DFEPACKET_PTR_ResetValue (0x01000000UL) /*!< Reset value of PTR register.                                      */
64610 
64611 /* OFFSET @Bits 0..15 : Data pointer */
64612   #define RADIO_DFEPACKET_PTR_OFFSET_Pos (0UL)       /*!< Position of OFFSET field.                                            */
64613   #define RADIO_DFEPACKET_PTR_OFFSET_Msk (0xFFFFUL << RADIO_DFEPACKET_PTR_OFFSET_Pos) /*!< Bit mask of OFFSET field.           */
64614 
64615 /* BASE @Bit 29 : (unspecified) */
64616   #define RADIO_DFEPACKET_PTR_BASE_Pos (29UL)        /*!< Position of BASE field.                                              */
64617   #define RADIO_DFEPACKET_PTR_BASE_Msk (0x1UL << RADIO_DFEPACKET_PTR_BASE_Pos) /*!< Bit mask of BASE field.                    */
64618 
64619 
64620 /* RADIO_DFEPACKET_MAXCNT: Maximum number of bytes to transfer */
64621   #define RADIO_DFEPACKET_MAXCNT_ResetValue (0x00004000UL) /*!< Reset value of MAXCNT register.                                */
64622 
64623 /* MAXCNT @Bits 0..15 : Maximum number of bytes to transfer */
64624   #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL)    /*!< Position of MAXCNT field.                                            */
64625   #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0xFFFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.     */
64626 
64627 
64628 /* RADIO_DFEPACKET_AMOUNT: Number of bytes transferred in the last transaction */
64629   #define RADIO_DFEPACKET_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                */
64630 
64631 /* AMOUNT @Bits 0..15 : Number of bytes transferred in the last transaction */
64632   #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL)    /*!< Position of AMOUNT field.                                            */
64633   #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.     */
64634 
64635 
64636 /* RADIO_DFEPACKET_ENABLE: (unspecified) */
64637   #define RADIO_DFEPACKET_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register.                                */
64638 
64639 /* ENABLE @Bit 0 : (unspecified) */
64640   #define RADIO_DFEPACKET_ENABLE_ENABLE_Pos (0UL)    /*!< Position of ENABLE field.                                            */
64641   #define RADIO_DFEPACKET_ENABLE_ENABLE_Msk (0x1UL << RADIO_DFEPACKET_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.        */
64642   #define RADIO_DFEPACKET_ENABLE_ENABLE_Min (0x0UL)  /*!< Min enumerator value of ENABLE field.                                */
64643   #define RADIO_DFEPACKET_ENABLE_ENABLE_Max (0x1UL)  /*!< Max enumerator value of ENABLE field.                                */
64644   #define RADIO_DFEPACKET_ENABLE_ENABLE_Disabled (0x1UL) /*!< Disable                                                          */
64645   #define RADIO_DFEPACKET_ENABLE_ENABLE_Enabled (0x0UL) /*!< Enable                                                            */
64646 
64647 
64648 /* ====================================================== Struct RADIO ======================================================= */
64649 /**
64650   * @brief 2.4 GHz radio
64651   */
64652   typedef struct {                                   /*!< RADIO Structure                                                      */
64653     __OM uint32_t TASKS_TXEN;                        /*!< (@ 0x00000000) Enable RADIO in TX mode                               */
64654     __OM uint32_t TASKS_RXEN;                        /*!< (@ 0x00000004) Enable RADIO in RX mode                               */
64655     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000008) Start RADIO                                           */
64656     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x0000000C) Stop RADIO                                            */
64657     __OM uint32_t TASKS_DISABLE;                     /*!< (@ 0x00000010) Disable RADIO                                         */
64658     __OM uint32_t TASKS_RSSISTART;                   /*!< (@ 0x00000014) Start the RSSI and take one single sample of the
64659                                                                          receive signal strength*/
64660     __OM uint32_t TASKS_BCSTART;                     /*!< (@ 0x00000018) Start the bit counter                                 */
64661     __OM uint32_t TASKS_BCSTOP;                      /*!< (@ 0x0000001C) Stop the bit counter                                  */
64662     __OM uint32_t TASKS_EDSTART;                     /*!< (@ 0x00000020) Start the energy detect measurement used in IEEE
64663                                                                          802.15.4 mode*/
64664     __OM uint32_t TASKS_EDSTOP;                      /*!< (@ 0x00000024) Stop the energy detect measurement                    */
64665     __OM uint32_t TASKS_CCASTART;                    /*!< (@ 0x00000028) Start the clear channel assessment used in IEEE
64666                                                                          802.15.4 mode*/
64667     __OM uint32_t TASKS_CCASTOP;                     /*!< (@ 0x0000002C) Stop the clear channel assessment                     */
64668     __IM uint32_t RESERVED[52];
64669     __IOM uint32_t SUBSCRIBE_TXEN;                   /*!< (@ 0x00000100) Subscribe configuration for task TXEN                 */
64670     __IOM uint32_t SUBSCRIBE_RXEN;                   /*!< (@ 0x00000104) Subscribe configuration for task RXEN                 */
64671     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000108) Subscribe configuration for task START                */
64672     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x0000010C) Subscribe configuration for task STOP                 */
64673     __IOM uint32_t SUBSCRIBE_DISABLE;                /*!< (@ 0x00000110) Subscribe configuration for task DISABLE              */
64674     __IOM uint32_t SUBSCRIBE_RSSISTART;              /*!< (@ 0x00000114) Subscribe configuration for task RSSISTART            */
64675     __IOM uint32_t SUBSCRIBE_BCSTART;                /*!< (@ 0x00000118) Subscribe configuration for task BCSTART              */
64676     __IOM uint32_t SUBSCRIBE_BCSTOP;                 /*!< (@ 0x0000011C) Subscribe configuration for task BCSTOP               */
64677     __IOM uint32_t SUBSCRIBE_EDSTART;                /*!< (@ 0x00000120) Subscribe configuration for task EDSTART              */
64678     __IOM uint32_t SUBSCRIBE_EDSTOP;                 /*!< (@ 0x00000124) Subscribe configuration for task EDSTOP               */
64679     __IOM uint32_t SUBSCRIBE_CCASTART;               /*!< (@ 0x00000128) Subscribe configuration for task CCASTART             */
64680     __IOM uint32_t SUBSCRIBE_CCASTOP;                /*!< (@ 0x0000012C) Subscribe configuration for task CCASTOP              */
64681     __IM uint32_t RESERVED1[52];
64682     __IOM uint32_t EVENTS_READY;                     /*!< (@ 0x00000200) RADIO has ramped up and is ready to be started        */
64683     __IOM uint32_t EVENTS_TXREADY;                   /*!< (@ 0x00000204) RADIO has ramped up and is ready to be started TX path*/
64684     __IOM uint32_t EVENTS_RXREADY;                   /*!< (@ 0x00000208) RADIO has ramped up and is ready to be started RX path*/
64685     __IOM uint32_t EVENTS_ADDRESS;                   /*!< (@ 0x0000020C) Address sent or received                              */
64686     __IOM uint32_t EVENTS_FRAMESTART;                /*!< (@ 0x00000210) IEEE 802.15.4 length field received                   */
64687     __IOM uint32_t EVENTS_PAYLOAD;                   /*!< (@ 0x00000214) Packet payload sent or received                       */
64688     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000218) Packet sent or received                               */
64689     __IOM uint32_t EVENTS_PHYEND;                    /*!< (@ 0x0000021C) The last bit is sent on air or last bit is received   */
64690     __IOM uint32_t EVENTS_DISABLED;                  /*!< (@ 0x00000220) RADIO has been disabled                               */
64691     __IOM uint32_t EVENTS_DEVMATCH;                  /*!< (@ 0x00000224) A device address match occurred on the last received
64692                                                                          packet*/
64693     __IOM uint32_t EVENTS_DEVMISS;                   /*!< (@ 0x00000228) No device address match occurred on the last received
64694                                                                          packet*/
64695     __IOM uint32_t EVENTS_CRCOK;                     /*!< (@ 0x0000022C) Packet received with CRC ok                           */
64696     __IOM uint32_t EVENTS_CRCERROR;                  /*!< (@ 0x00000230) Packet received with CRC error                        */
64697     __IM uint32_t RESERVED2;
64698     __IOM uint32_t EVENTS_BCMATCH;                   /*!< (@ 0x00000238) Bit counter reached bit count value                   */
64699     __IOM uint32_t EVENTS_EDEND;                     /*!< (@ 0x0000023C) Sampling of energy detection complete (a new ED sample
64700                                                                          is ready for readout from the RADIO.EDSAMPLE register)*/
64701     __IOM uint32_t EVENTS_EDSTOPPED;                 /*!< (@ 0x00000240) The sampling of energy detection has stopped          */
64702     __IOM uint32_t EVENTS_CCAIDLE;                   /*!< (@ 0x00000244) Wireless medium in idle - clear to send               */
64703     __IOM uint32_t EVENTS_CCABUSY;                   /*!< (@ 0x00000248) Wireless medium busy - do not send                    */
64704     __IOM uint32_t EVENTS_CCASTOPPED;                /*!< (@ 0x0000024C) The CCA has stopped                                   */
64705     __IOM uint32_t EVENTS_RATEBOOST;                 /*!< (@ 0x00000250) Ble_LR CI field received, receive mode is changed from
64706                                                                          Ble_LR125Kbit to Ble_LR500Kbit*/
64707     __IOM uint32_t EVENTS_MHRMATCH;                  /*!< (@ 0x00000254) MAC header match found                                */
64708     __IOM uint32_t EVENTS_SYNC;                      /*!< (@ 0x00000258) Initial sync detected                                 */
64709     __IOM uint32_t EVENTS_CTEPRESENT;                /*!< (@ 0x0000025C) CTEInfo byte is received                              */
64710     __IM uint32_t RESERVED3[40];
64711     __IOM uint32_t PUBLISH_READY;                    /*!< (@ 0x00000300) Publish configuration for event READY                 */
64712     __IOM uint32_t PUBLISH_TXREADY;                  /*!< (@ 0x00000304) Publish configuration for event TXREADY               */
64713     __IOM uint32_t PUBLISH_RXREADY;                  /*!< (@ 0x00000308) Publish configuration for event RXREADY               */
64714     __IOM uint32_t PUBLISH_ADDRESS;                  /*!< (@ 0x0000030C) Publish configuration for event ADDRESS               */
64715     __IOM uint32_t PUBLISH_FRAMESTART;               /*!< (@ 0x00000310) Publish configuration for event FRAMESTART            */
64716     __IOM uint32_t PUBLISH_PAYLOAD;                  /*!< (@ 0x00000314) Publish configuration for event PAYLOAD               */
64717     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000318) Publish configuration for event END                   */
64718     __IOM uint32_t PUBLISH_PHYEND;                   /*!< (@ 0x0000031C) Publish configuration for event PHYEND                */
64719     __IOM uint32_t PUBLISH_DISABLED;                 /*!< (@ 0x00000320) Publish configuration for event DISABLED              */
64720     __IOM uint32_t PUBLISH_DEVMATCH;                 /*!< (@ 0x00000324) Publish configuration for event DEVMATCH              */
64721     __IOM uint32_t PUBLISH_DEVMISS;                  /*!< (@ 0x00000328) Publish configuration for event DEVMISS               */
64722     __IOM uint32_t PUBLISH_CRCOK;                    /*!< (@ 0x0000032C) Publish configuration for event CRCOK                 */
64723     __IOM uint32_t PUBLISH_CRCERROR;                 /*!< (@ 0x00000330) Publish configuration for event CRCERROR              */
64724     __IM uint32_t RESERVED4;
64725     __IOM uint32_t PUBLISH_BCMATCH;                  /*!< (@ 0x00000338) Publish configuration for event BCMATCH               */
64726     __IOM uint32_t PUBLISH_EDEND;                    /*!< (@ 0x0000033C) Publish configuration for event EDEND                 */
64727     __IOM uint32_t PUBLISH_EDSTOPPED;                /*!< (@ 0x00000340) Publish configuration for event EDSTOPPED             */
64728     __IOM uint32_t PUBLISH_CCAIDLE;                  /*!< (@ 0x00000344) Publish configuration for event CCAIDLE               */
64729     __IOM uint32_t PUBLISH_CCABUSY;                  /*!< (@ 0x00000348) Publish configuration for event CCABUSY               */
64730     __IOM uint32_t PUBLISH_CCASTOPPED;               /*!< (@ 0x0000034C) Publish configuration for event CCASTOPPED            */
64731     __IOM uint32_t PUBLISH_RATEBOOST;                /*!< (@ 0x00000350) Publish configuration for event RATEBOOST             */
64732     __IOM uint32_t PUBLISH_MHRMATCH;                 /*!< (@ 0x00000354) Publish configuration for event MHRMATCH              */
64733     __IOM uint32_t PUBLISH_SYNC;                     /*!< (@ 0x00000358) Publish configuration for event SYNC                  */
64734     __IOM uint32_t PUBLISH_CTEPRESENT;               /*!< (@ 0x0000035C) Publish configuration for event CTEPRESENT            */
64735     __IM uint32_t RESERVED5[40];
64736     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000400) Shortcuts between local events and tasks              */
64737     __IM uint32_t RESERVED6[33];
64738     __IOM uint32_t INTENSET00;                       /*!< (@ 0x00000488) Enable interrupt                                      */
64739     __IOM uint32_t INTENSET01;                       /*!< (@ 0x0000048C) Enable interrupt                                      */
64740     __IOM uint32_t INTENCLR00;                       /*!< (@ 0x00000490) Disable interrupt                                     */
64741     __IOM uint32_t INTENCLR01;                       /*!< (@ 0x00000494) Disable interrupt                                     */
64742     __IM uint32_t RESERVED7[4];
64743     __IOM uint32_t INTENSET10;                       /*!< (@ 0x000004A8) Enable interrupt                                      */
64744     __IOM uint32_t INTENSET11;                       /*!< (@ 0x000004AC) Enable interrupt                                      */
64745     __IOM uint32_t INTENCLR10;                       /*!< (@ 0x000004B0) Disable interrupt                                     */
64746     __IOM uint32_t INTENCLR11;                       /*!< (@ 0x000004B4) Disable interrupt                                     */
64747     __IM uint32_t RESERVED8[18];
64748     __IOM uint32_t MODE;                             /*!< (@ 0x00000500) Data rate and modulation                              */
64749     __IM uint32_t RESERVED9[7];
64750     __IM uint32_t STATE;                             /*!< (@ 0x00000520) Current radio state                                   */
64751     __IM uint32_t RESERVED10[3];
64752     __IOM uint32_t EDCTRL;                           /*!< (@ 0x00000530) IEEE 802.15.4 energy detect control                   */
64753     __IM uint32_t EDSAMPLE;                          /*!< (@ 0x00000534) IEEE 802.15.4 energy detect level                     */
64754     __IOM uint32_t CCACTRL;                          /*!< (@ 0x00000538) IEEE 802.15.4 clear channel assessment control        */
64755     __IM uint32_t RESERVED11;
64756     __IOM uint32_t DATAWHITEIV;                      /*!< (@ 0x00000540) Data whitening initial value                          */
64757     __IM uint32_t RESERVED12[112];
64758     __IOM uint32_t TIMING;                           /*!< (@ 0x00000704) Timing                                                */
64759     __IOM uint32_t FREQUENCY;                        /*!< (@ 0x00000708) Frequency                                             */
64760     __IM uint32_t RESERVED13;
64761     __IOM uint32_t TXPOWER;                          /*!< (@ 0x00000710) Output power                                          */
64762     __IOM uint32_t TIFS;                             /*!< (@ 0x00000714) Interframe spacing in us                              */
64763     __IM uint32_t RSSISAMPLE;                        /*!< (@ 0x00000718) RSSI sample                                           */
64764     __IM uint32_t RESERVED14[377];
64765     __IOM uint32_t DFEMODE;                          /*!< (@ 0x00000D00) Whether to use Angle-of-Arrival (AOA) or
64766                                                                          Angle-of-Departure (AOD)*/
64767     __IM uint32_t DFESTATUS;                         /*!< (@ 0x00000D04) DFE status information                                */
64768     __IM uint32_t RESERVED15[2];
64769     __IOM uint32_t DFECTRL1;                         /*!< (@ 0x00000D10) Various configuration for Direction finding           */
64770     __IOM uint32_t DFECTRL2;                         /*!< (@ 0x00000D14) Start offset for Direction finding                    */
64771     __IM uint32_t RESERVED16[4];
64772     __IOM uint32_t SWITCHPATTERN;                    /*!< (@ 0x00000D28) GPIO patterns to be used for each antenna             */
64773     __OM uint32_t CLEARPATTERN;                      /*!< (@ 0x00000D2C) Clear the GPIO pattern array for antenna control      */
64774     __IOM NRF_RADIO_PSEL_Type PSEL;                  /*!< (@ 0x00000D30) (unspecified)                                         */
64775     __IOM NRF_RADIO_DFEPACKET_Type DFEPACKET;        /*!< (@ 0x00000D50) DFE packet EasyDMA channel                            */
64776     __IM uint32_t RESERVED17[43];
64777     __IM uint32_t CRCSTATUS;                         /*!< (@ 0x00000E0C) CRC status                                            */
64778     __IM uint32_t RXMATCH;                           /*!< (@ 0x00000E10) Received address                                      */
64779     __IM uint32_t RXCRC;                             /*!< (@ 0x00000E14) CRC field of previously received packet               */
64780     __IM uint32_t DAI;                               /*!< (@ 0x00000E18) Device address match index                            */
64781     __IM uint32_t PDUSTAT;                           /*!< (@ 0x00000E1C) Payload status                                        */
64782     __IOM uint32_t PCNF0;                            /*!< (@ 0x00000E20) Packet configuration register 0                       */
64783     __IM uint32_t RESERVED18;
64784     __IOM uint32_t PCNF1;                            /*!< (@ 0x00000E28) Packet configuration register 1                       */
64785     __IOM uint32_t BASE0;                            /*!< (@ 0x00000E2C) Base address 0                                        */
64786     __IOM uint32_t BASE1;                            /*!< (@ 0x00000E30) Base address 1                                        */
64787     __IOM uint32_t PREFIX0;                          /*!< (@ 0x00000E34) Prefixes bytes for logical addresses 0-3              */
64788     __IOM uint32_t PREFIX1;                          /*!< (@ 0x00000E38) Prefixes bytes for logical addresses 4-7              */
64789     __IOM uint32_t TXADDRESS;                        /*!< (@ 0x00000E3C) Transmit address select                               */
64790     __IOM uint32_t RXADDRESSES;                      /*!< (@ 0x00000E40) Receive address select                                */
64791     __IOM uint32_t CRCCNF;                           /*!< (@ 0x00000E44) CRC configuration                                     */
64792     __IOM uint32_t CRCPOLY;                          /*!< (@ 0x00000E48) CRC polynomial                                        */
64793     __IOM uint32_t CRCINIT;                          /*!< (@ 0x00000E4C) CRC initial value                                     */
64794     __IOM uint32_t DAB[8];                           /*!< (@ 0x00000E50) Device address base segment n                         */
64795     __IOM uint32_t DAP[8];                           /*!< (@ 0x00000E70) Device address prefix n                               */
64796     __IOM uint32_t DACNF;                            /*!< (@ 0x00000E90) Device address match configuration                    */
64797     __IOM uint32_t BCC;                              /*!< (@ 0x00000E94) Bit counter compare                                   */
64798     __IM uint32_t RESERVED19[3];
64799     __IM uint32_t CTESTATUS;                         /*!< (@ 0x00000EA4) CTEInfo parsed from received packet                   */
64800     __IM uint32_t RESERVED20[3];
64801     __IOM uint32_t MHRMATCHCONF;                     /*!< (@ 0x00000EB4) Search pattern configuration                          */
64802     __IOM uint32_t MHRMATCHMASK;                     /*!< (@ 0x00000EB8) Pattern mask                                          */
64803     __IOM uint32_t SFD;                              /*!< (@ 0x00000EBC) IEEE 802.15.4 start of frame delimiter                */
64804     __IOM uint32_t CTEINLINECONF;                    /*!< (@ 0x00000EC0) Configuration for CTE inline mode                     */
64805     __IM uint32_t RESERVED21[3];
64806     __IOM uint32_t PACKETPTR;                        /*!< (@ 0x00000ED0) (unspecified)                                         */
64807   } NRF_RADIO_Type;                                  /*!< Size = 3796 (0xED4)                                                  */
64808 
64809 /* RADIO_TASKS_TXEN: Enable RADIO in TX mode */
64810   #define RADIO_TASKS_TXEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TXEN register.                                  */
64811 
64812 /* TASKS_TXEN @Bit 0 : Enable RADIO in TX mode */
64813   #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL)      /*!< Position of TASKS_TXEN field.                                        */
64814   #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field.        */
64815   #define RADIO_TASKS_TXEN_TASKS_TXEN_Min (0x1UL)    /*!< Min enumerator value of TASKS_TXEN field.                            */
64816   #define RADIO_TASKS_TXEN_TASKS_TXEN_Max (0x1UL)    /*!< Max enumerator value of TASKS_TXEN field.                            */
64817   #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (0x1UL) /*!< Trigger task                                                        */
64818 
64819 
64820 /* RADIO_TASKS_RXEN: Enable RADIO in RX mode */
64821   #define RADIO_TASKS_RXEN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RXEN register.                                  */
64822 
64823 /* TASKS_RXEN @Bit 0 : Enable RADIO in RX mode */
64824   #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL)      /*!< Position of TASKS_RXEN field.                                        */
64825   #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field.        */
64826   #define RADIO_TASKS_RXEN_TASKS_RXEN_Min (0x1UL)    /*!< Min enumerator value of TASKS_RXEN field.                            */
64827   #define RADIO_TASKS_RXEN_TASKS_RXEN_Max (0x1UL)    /*!< Max enumerator value of TASKS_RXEN field.                            */
64828   #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (0x1UL) /*!< Trigger task                                                        */
64829 
64830 
64831 /* RADIO_TASKS_START: Start RADIO */
64832   #define RADIO_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */
64833 
64834 /* TASKS_START @Bit 0 : Start RADIO */
64835   #define RADIO_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
64836   #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
64837   #define RADIO_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
64838   #define RADIO_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
64839   #define RADIO_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */
64840 
64841 
64842 /* RADIO_TASKS_STOP: Stop RADIO */
64843   #define RADIO_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */
64844 
64845 /* TASKS_STOP @Bit 0 : Stop RADIO */
64846   #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
64847   #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
64848   #define RADIO_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
64849   #define RADIO_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
64850   #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */
64851 
64852 
64853 /* RADIO_TASKS_DISABLE: Disable RADIO */
64854   #define RADIO_TASKS_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_DISABLE register.                            */
64855 
64856 /* TASKS_DISABLE @Bit 0 : Disable RADIO */
64857   #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field.                                    */
64858   #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE
64859                                                                             field.*/
64860   #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Min (0x1UL) /*!< Min enumerator value of TASKS_DISABLE field.                      */
64861   #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Max (0x1UL) /*!< Max enumerator value of TASKS_DISABLE field.                      */
64862   #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (0x1UL) /*!< Trigger task                                                  */
64863 
64864 
64865 /* RADIO_TASKS_RSSISTART: Start the RSSI and take one single sample of the receive signal strength */
64866   #define RADIO_TASKS_RSSISTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RSSISTART register.                        */
64867 
64868 /* TASKS_RSSISTART @Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
64869   #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field.                              */
64870   #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of
64871                                                                             TASKS_RSSISTART field.*/
64872   #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Min (0x1UL) /*!< Min enumerator value of TASKS_RSSISTART field.                */
64873   #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Max (0x1UL) /*!< Max enumerator value of TASKS_RSSISTART field.                */
64874   #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (0x1UL) /*!< Trigger task                                              */
64875 
64876 
64877 /* RADIO_TASKS_BCSTART: Start the bit counter */
64878   #define RADIO_TASKS_BCSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BCSTART register.                            */
64879 
64880 /* TASKS_BCSTART @Bit 0 : Start the bit counter */
64881   #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field.                                    */
64882   #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART
64883                                                                             field.*/
64884   #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_BCSTART field.                      */
64885   #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_BCSTART field.                      */
64886   #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (0x1UL) /*!< Trigger task                                                  */
64887 
64888 
64889 /* RADIO_TASKS_BCSTOP: Stop the bit counter */
64890   #define RADIO_TASKS_BCSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_BCSTOP register.                              */
64891 
64892 /* TASKS_BCSTOP @Bit 0 : Stop the bit counter */
64893   #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL)  /*!< Position of TASKS_BCSTOP field.                                      */
64894   #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP
64895                                                                             field.*/
64896   #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_BCSTOP field.                         */
64897   #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_BCSTOP field.                         */
64898   #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (0x1UL) /*!< Trigger task                                                    */
64899 
64900 
64901 /* RADIO_TASKS_EDSTART: Start the energy detect measurement used in IEEE 802.15.4 mode */
64902   #define RADIO_TASKS_EDSTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_EDSTART register.                            */
64903 
64904 /* TASKS_EDSTART @Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
64905   #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field.                                    */
64906   #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART
64907                                                                             field.*/
64908   #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Min (0x1UL) /*!< Min enumerator value of TASKS_EDSTART field.                      */
64909   #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Max (0x1UL) /*!< Max enumerator value of TASKS_EDSTART field.                      */
64910   #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (0x1UL) /*!< Trigger task                                                  */
64911 
64912 
64913 /* RADIO_TASKS_EDSTOP: Stop the energy detect measurement */
64914   #define RADIO_TASKS_EDSTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_EDSTOP register.                              */
64915 
64916 /* TASKS_EDSTOP @Bit 0 : Stop the energy detect measurement */
64917   #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL)  /*!< Position of TASKS_EDSTOP field.                                      */
64918   #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP
64919                                                                             field.*/
64920   #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_EDSTOP field.                         */
64921   #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_EDSTOP field.                         */
64922   #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (0x1UL) /*!< Trigger task                                                    */
64923 
64924 
64925 /* RADIO_TASKS_CCASTART: Start the clear channel assessment used in IEEE 802.15.4 mode */
64926   #define RADIO_TASKS_CCASTART_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CCASTART register.                          */
64927 
64928 /* TASKS_CCASTART @Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
64929   #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field.                                 */
64930   #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of
64931                                                                             TASKS_CCASTART field.*/
64932   #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Min (0x1UL) /*!< Min enumerator value of TASKS_CCASTART field.                   */
64933   #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Max (0x1UL) /*!< Max enumerator value of TASKS_CCASTART field.                   */
64934   #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (0x1UL) /*!< Trigger task                                                */
64935 
64936 
64937 /* RADIO_TASKS_CCASTOP: Stop the clear channel assessment */
64938   #define RADIO_TASKS_CCASTOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CCASTOP register.                            */
64939 
64940 /* TASKS_CCASTOP @Bit 0 : Stop the clear channel assessment */
64941   #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field.                                    */
64942   #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP
64943                                                                             field.*/
64944   #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Min (0x1UL) /*!< Min enumerator value of TASKS_CCASTOP field.                      */
64945   #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Max (0x1UL) /*!< Max enumerator value of TASKS_CCASTOP field.                      */
64946   #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (0x1UL) /*!< Trigger task                                                  */
64947 
64948 
64949 /* RADIO_SUBSCRIBE_TXEN: Subscribe configuration for task TXEN */
64950   #define RADIO_SUBSCRIBE_TXEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TXEN register.                          */
64951 
64952 /* CHIDX @Bits 0..7 : DPPI channel that task TXEN will subscribe to */
64953   #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
64954   #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
64955   #define RADIO_SUBSCRIBE_TXEN_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
64956   #define RADIO_SUBSCRIBE_TXEN_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
64957 
64958 /* EN @Bit 31 : (unspecified) */
64959   #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL)         /*!< Position of EN field.                                                */
64960   #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos) /*!< Bit mask of EN field.                        */
64961   #define RADIO_SUBSCRIBE_TXEN_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
64962   #define RADIO_SUBSCRIBE_TXEN_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
64963   #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
64964   #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
64965 
64966 
64967 /* RADIO_SUBSCRIBE_RXEN: Subscribe configuration for task RXEN */
64968   #define RADIO_SUBSCRIBE_RXEN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RXEN register.                          */
64969 
64970 /* CHIDX @Bits 0..7 : DPPI channel that task RXEN will subscribe to */
64971   #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
64972   #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
64973   #define RADIO_SUBSCRIBE_RXEN_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
64974   #define RADIO_SUBSCRIBE_RXEN_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
64975 
64976 /* EN @Bit 31 : (unspecified) */
64977   #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL)         /*!< Position of EN field.                                                */
64978   #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos) /*!< Bit mask of EN field.                        */
64979   #define RADIO_SUBSCRIBE_RXEN_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
64980   #define RADIO_SUBSCRIBE_RXEN_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
64981   #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
64982   #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
64983 
64984 
64985 /* RADIO_SUBSCRIBE_START: Subscribe configuration for task START */
64986   #define RADIO_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                        */
64987 
64988 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
64989   #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
64990   #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
64991   #define RADIO_SUBSCRIBE_START_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
64992   #define RADIO_SUBSCRIBE_START_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
64993 
64994 /* EN @Bit 31 : (unspecified) */
64995   #define RADIO_SUBSCRIBE_START_EN_Pos (31UL)        /*!< Position of EN field.                                                */
64996   #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                      */
64997   #define RADIO_SUBSCRIBE_START_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
64998   #define RADIO_SUBSCRIBE_START_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
64999   #define RADIO_SUBSCRIBE_START_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
65000   #define RADIO_SUBSCRIBE_START_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
65001 
65002 
65003 /* RADIO_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
65004   #define RADIO_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                          */
65005 
65006 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
65007   #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
65008   #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
65009   #define RADIO_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
65010   #define RADIO_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
65011 
65012 /* EN @Bit 31 : (unspecified) */
65013   #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL)         /*!< Position of EN field.                                                */
65014   #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                        */
65015   #define RADIO_SUBSCRIBE_STOP_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
65016   #define RADIO_SUBSCRIBE_STOP_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
65017   #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
65018   #define RADIO_SUBSCRIBE_STOP_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
65019 
65020 
65021 /* RADIO_SUBSCRIBE_DISABLE: Subscribe configuration for task DISABLE */
65022   #define RADIO_SUBSCRIBE_DISABLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_DISABLE register.                    */
65023 
65024 /* CHIDX @Bits 0..7 : DPPI channel that task DISABLE will subscribe to */
65025   #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
65026   #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
65027   #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
65028   #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
65029 
65030 /* EN @Bit 31 : (unspecified) */
65031   #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL)      /*!< Position of EN field.                                                */
65032   #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field.                  */
65033   #define RADIO_SUBSCRIBE_DISABLE_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
65034   #define RADIO_SUBSCRIBE_DISABLE_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
65035   #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
65036   #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
65037 
65038 
65039 /* RADIO_SUBSCRIBE_RSSISTART: Subscribe configuration for task RSSISTART */
65040   #define RADIO_SUBSCRIBE_RSSISTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RSSISTART register.                */
65041 
65042 /* CHIDX @Bits 0..7 : DPPI channel that task RSSISTART will subscribe to */
65043   #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL)  /*!< Position of CHIDX field.                                             */
65044   #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.    */
65045   #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                           */
65046   #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                           */
65047 
65048 /* EN @Bit 31 : (unspecified) */
65049   #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL)    /*!< Position of EN field.                                                */
65050   #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos) /*!< Bit mask of EN field.              */
65051   #define RADIO_SUBSCRIBE_RSSISTART_EN_Min (0x0UL)   /*!< Min enumerator value of EN field.                                    */
65052   #define RADIO_SUBSCRIBE_RSSISTART_EN_Max (0x1UL)   /*!< Max enumerator value of EN field.                                    */
65053   #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0x0UL) /*!< Disable subscription                                              */
65054   #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                */
65055 
65056 
65057 /* RADIO_SUBSCRIBE_BCSTART: Subscribe configuration for task BCSTART */
65058   #define RADIO_SUBSCRIBE_BCSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_BCSTART register.                    */
65059 
65060 /* CHIDX @Bits 0..7 : DPPI channel that task BCSTART will subscribe to */
65061   #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
65062   #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
65063   #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
65064   #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
65065 
65066 /* EN @Bit 31 : (unspecified) */
65067   #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL)      /*!< Position of EN field.                                                */
65068   #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos) /*!< Bit mask of EN field.                  */
65069   #define RADIO_SUBSCRIBE_BCSTART_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
65070   #define RADIO_SUBSCRIBE_BCSTART_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
65071   #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
65072   #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
65073 
65074 
65075 /* RADIO_SUBSCRIBE_BCSTOP: Subscribe configuration for task BCSTOP */
65076   #define RADIO_SUBSCRIBE_BCSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_BCSTOP register.                      */
65077 
65078 /* CHIDX @Bits 0..7 : DPPI channel that task BCSTOP will subscribe to */
65079   #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
65080   #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
65081   #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
65082   #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
65083 
65084 /* EN @Bit 31 : (unspecified) */
65085   #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
65086   #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos) /*!< Bit mask of EN field.                    */
65087   #define RADIO_SUBSCRIBE_BCSTOP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
65088   #define RADIO_SUBSCRIBE_BCSTOP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
65089   #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
65090   #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
65091 
65092 
65093 /* RADIO_SUBSCRIBE_EDSTART: Subscribe configuration for task EDSTART */
65094   #define RADIO_SUBSCRIBE_EDSTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_EDSTART register.                    */
65095 
65096 /* CHIDX @Bits 0..7 : DPPI channel that task EDSTART will subscribe to */
65097   #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
65098   #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
65099   #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
65100   #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
65101 
65102 /* EN @Bit 31 : (unspecified) */
65103   #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL)      /*!< Position of EN field.                                                */
65104   #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos) /*!< Bit mask of EN field.                  */
65105   #define RADIO_SUBSCRIBE_EDSTART_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
65106   #define RADIO_SUBSCRIBE_EDSTART_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
65107   #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
65108   #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
65109 
65110 
65111 /* RADIO_SUBSCRIBE_EDSTOP: Subscribe configuration for task EDSTOP */
65112   #define RADIO_SUBSCRIBE_EDSTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_EDSTOP register.                      */
65113 
65114 /* CHIDX @Bits 0..7 : DPPI channel that task EDSTOP will subscribe to */
65115   #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
65116   #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
65117   #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
65118   #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
65119 
65120 /* EN @Bit 31 : (unspecified) */
65121   #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL)       /*!< Position of EN field.                                                */
65122   #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos) /*!< Bit mask of EN field.                    */
65123   #define RADIO_SUBSCRIBE_EDSTOP_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
65124   #define RADIO_SUBSCRIBE_EDSTOP_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
65125   #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
65126   #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
65127 
65128 
65129 /* RADIO_SUBSCRIBE_CCASTART: Subscribe configuration for task CCASTART */
65130   #define RADIO_SUBSCRIBE_CCASTART_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CCASTART register.                  */
65131 
65132 /* CHIDX @Bits 0..7 : DPPI channel that task CCASTART will subscribe to */
65133   #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
65134   #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
65135   #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
65136   #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
65137 
65138 /* EN @Bit 31 : (unspecified) */
65139   #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL)     /*!< Position of EN field.                                                */
65140   #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos) /*!< Bit mask of EN field.                */
65141   #define RADIO_SUBSCRIBE_CCASTART_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
65142   #define RADIO_SUBSCRIBE_CCASTART_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
65143   #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
65144   #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */
65145 
65146 
65147 /* RADIO_SUBSCRIBE_CCASTOP: Subscribe configuration for task CCASTOP */
65148   #define RADIO_SUBSCRIBE_CCASTOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CCASTOP register.                    */
65149 
65150 /* CHIDX @Bits 0..7 : DPPI channel that task CCASTOP will subscribe to */
65151   #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
65152   #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
65153   #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
65154   #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
65155 
65156 /* EN @Bit 31 : (unspecified) */
65157   #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL)      /*!< Position of EN field.                                                */
65158   #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos) /*!< Bit mask of EN field.                  */
65159   #define RADIO_SUBSCRIBE_CCASTOP_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
65160   #define RADIO_SUBSCRIBE_CCASTOP_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
65161   #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
65162   #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
65163 
65164 
65165 /* RADIO_EVENTS_READY: RADIO has ramped up and is ready to be started */
65166   #define RADIO_EVENTS_READY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READY register.                              */
65167 
65168 /* EVENTS_READY @Bit 0 : RADIO has ramped up and is ready to be started */
65169   #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL)  /*!< Position of EVENTS_READY field.                                      */
65170   #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY
65171                                                                             field.*/
65172   #define RADIO_EVENTS_READY_EVENTS_READY_Min (0x0UL) /*!< Min enumerator value of EVENTS_READY field.                         */
65173   #define RADIO_EVENTS_READY_EVENTS_READY_Max (0x1UL) /*!< Max enumerator value of EVENTS_READY field.                         */
65174   #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0x0UL) /*!< Event not generated                                        */
65175   #define RADIO_EVENTS_READY_EVENTS_READY_Generated (0x1UL) /*!< Event generated                                               */
65176 
65177 
65178 /* RADIO_EVENTS_TXREADY: RADIO has ramped up and is ready to be started TX path */
65179   #define RADIO_EVENTS_TXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXREADY register.                          */
65180 
65181 /* EVENTS_TXREADY @Bit 0 : RADIO has ramped up and is ready to be started TX path */
65182   #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field.                                 */
65183   #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of
65184                                                                             EVENTS_TXREADY field.*/
65185   #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXREADY field.                   */
65186   #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXREADY field.                   */
65187   #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0x0UL) /*!< Event not generated                                    */
65188   #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (0x1UL) /*!< Event generated                                           */
65189 
65190 
65191 /* RADIO_EVENTS_RXREADY: RADIO has ramped up and is ready to be started RX path */
65192   #define RADIO_EVENTS_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXREADY register.                          */
65193 
65194 /* EVENTS_RXREADY @Bit 0 : RADIO has ramped up and is ready to be started RX path */
65195   #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field.                                 */
65196   #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of
65197                                                                             EVENTS_RXREADY field.*/
65198   #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXREADY field.                   */
65199   #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXREADY field.                   */
65200   #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0x0UL) /*!< Event not generated                                    */
65201   #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (0x1UL) /*!< Event generated                                           */
65202 
65203 
65204 /* RADIO_EVENTS_ADDRESS: Address sent or received */
65205   #define RADIO_EVENTS_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ADDRESS register.                          */
65206 
65207 /* EVENTS_ADDRESS @Bit 0 : Address sent or received */
65208   #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field.                                 */
65209   #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of
65210                                                                             EVENTS_ADDRESS field.*/
65211   #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Min (0x0UL) /*!< Min enumerator value of EVENTS_ADDRESS field.                   */
65212   #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Max (0x1UL) /*!< Max enumerator value of EVENTS_ADDRESS field.                   */
65213   #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0x0UL) /*!< Event not generated                                    */
65214   #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (0x1UL) /*!< Event generated                                           */
65215 
65216 
65217 /* RADIO_EVENTS_FRAMESTART: IEEE 802.15.4 length field received */
65218   #define RADIO_EVENTS_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FRAMESTART register.                    */
65219 
65220 /* EVENTS_FRAMESTART @Bit 0 : IEEE 802.15.4 length field received */
65221   #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field.                        */
65222   #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask
65223                                                                             of EVENTS_FRAMESTART field.*/
65224   #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Min (0x0UL) /*!< Min enumerator value of EVENTS_FRAMESTART field.          */
65225   #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Max (0x1UL) /*!< Max enumerator value of EVENTS_FRAMESTART field.          */
65226   #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0x0UL) /*!< Event not generated                              */
65227   #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (0x1UL) /*!< Event generated                                     */
65228 
65229 
65230 /* RADIO_EVENTS_PAYLOAD: Packet payload sent or received */
65231   #define RADIO_EVENTS_PAYLOAD_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PAYLOAD register.                          */
65232 
65233 /* EVENTS_PAYLOAD @Bit 0 : Packet payload sent or received */
65234   #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field.                                 */
65235   #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of
65236                                                                             EVENTS_PAYLOAD field.*/
65237   #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Min (0x0UL) /*!< Min enumerator value of EVENTS_PAYLOAD field.                   */
65238   #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Max (0x1UL) /*!< Max enumerator value of EVENTS_PAYLOAD field.                   */
65239   #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0x0UL) /*!< Event not generated                                    */
65240   #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (0x1UL) /*!< Event generated                                           */
65241 
65242 
65243 /* RADIO_EVENTS_END: Packet sent or received */
65244   #define RADIO_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register.                                  */
65245 
65246 /* EVENTS_END @Bit 0 : Packet sent or received */
65247   #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL)      /*!< Position of EVENTS_END field.                                        */
65248   #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.        */
65249   #define RADIO_EVENTS_END_EVENTS_END_Min (0x0UL)    /*!< Min enumerator value of EVENTS_END field.                            */
65250   #define RADIO_EVENTS_END_EVENTS_END_Max (0x1UL)    /*!< Max enumerator value of EVENTS_END field.                            */
65251   #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                            */
65252   #define RADIO_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                   */
65253 
65254 
65255 /* RADIO_EVENTS_PHYEND: The last bit is sent on air or last bit is received */
65256   #define RADIO_EVENTS_PHYEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PHYEND register.                            */
65257 
65258 /* EVENTS_PHYEND @Bit 0 : The last bit is sent on air or last bit is received */
65259   #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field.                                    */
65260   #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND
65261                                                                             field.*/
65262   #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_PHYEND field.                      */
65263   #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_PHYEND field.                      */
65264   #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0x0UL) /*!< Event not generated                                      */
65265   #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (0x1UL) /*!< Event generated                                             */
65266 
65267 
65268 /* RADIO_EVENTS_DISABLED: RADIO has been disabled */
65269   #define RADIO_EVENTS_DISABLED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DISABLED register.                        */
65270 
65271 /* EVENTS_DISABLED @Bit 0 : RADIO has been disabled */
65272   #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field.                              */
65273   #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of
65274                                                                             EVENTS_DISABLED field.*/
65275   #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Min (0x0UL) /*!< Min enumerator value of EVENTS_DISABLED field.                */
65276   #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Max (0x1UL) /*!< Max enumerator value of EVENTS_DISABLED field.                */
65277   #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0x0UL) /*!< Event not generated                                  */
65278   #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (0x1UL) /*!< Event generated                                         */
65279 
65280 
65281 /* RADIO_EVENTS_DEVMATCH: A device address match occurred on the last received packet */
65282   #define RADIO_EVENTS_DEVMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DEVMATCH register.                        */
65283 
65284 /* EVENTS_DEVMATCH @Bit 0 : A device address match occurred on the last received packet */
65285   #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field.                              */
65286   #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of
65287                                                                             EVENTS_DEVMATCH field.*/
65288   #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_DEVMATCH field.                */
65289   #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_DEVMATCH field.                */
65290   #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0x0UL) /*!< Event not generated                                  */
65291   #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (0x1UL) /*!< Event generated                                         */
65292 
65293 
65294 /* RADIO_EVENTS_DEVMISS: No device address match occurred on the last received packet */
65295   #define RADIO_EVENTS_DEVMISS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DEVMISS register.                          */
65296 
65297 /* EVENTS_DEVMISS @Bit 0 : No device address match occurred on the last received packet */
65298   #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field.                                 */
65299   #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of
65300                                                                             EVENTS_DEVMISS field.*/
65301   #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Min (0x0UL) /*!< Min enumerator value of EVENTS_DEVMISS field.                   */
65302   #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Max (0x1UL) /*!< Max enumerator value of EVENTS_DEVMISS field.                   */
65303   #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0x0UL) /*!< Event not generated                                    */
65304   #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (0x1UL) /*!< Event generated                                           */
65305 
65306 
65307 /* RADIO_EVENTS_CRCOK: Packet received with CRC ok */
65308   #define RADIO_EVENTS_CRCOK_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRCOK register.                              */
65309 
65310 /* EVENTS_CRCOK @Bit 0 : Packet received with CRC ok */
65311   #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL)  /*!< Position of EVENTS_CRCOK field.                                      */
65312   #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK
65313                                                                             field.*/
65314   #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRCOK field.                         */
65315   #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRCOK field.                         */
65316   #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0x0UL) /*!< Event not generated                                        */
65317   #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (0x1UL) /*!< Event generated                                               */
65318 
65319 
65320 /* RADIO_EVENTS_CRCERROR: Packet received with CRC error */
65321   #define RADIO_EVENTS_CRCERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CRCERROR register.                        */
65322 
65323 /* EVENTS_CRCERROR @Bit 0 : Packet received with CRC error */
65324   #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field.                              */
65325   #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of
65326                                                                             EVENTS_CRCERROR field.*/
65327   #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_CRCERROR field.                */
65328   #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_CRCERROR field.                */
65329   #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0x0UL) /*!< Event not generated                                  */
65330   #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (0x1UL) /*!< Event generated                                         */
65331 
65332 
65333 /* RADIO_EVENTS_BCMATCH: Bit counter reached bit count value */
65334   #define RADIO_EVENTS_BCMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_BCMATCH register.                          */
65335 
65336 /* EVENTS_BCMATCH @Bit 0 : Bit counter reached bit count value */
65337   #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field.                                 */
65338   #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of
65339                                                                             EVENTS_BCMATCH field.*/
65340   #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_BCMATCH field.                   */
65341   #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_BCMATCH field.                   */
65342   #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0x0UL) /*!< Event not generated                                    */
65343   #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (0x1UL) /*!< Event generated                                           */
65344 
65345 
65346 /* RADIO_EVENTS_EDEND: Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE
65347                         register) */
65348 
65349   #define RADIO_EVENTS_EDEND_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_EDEND register.                              */
65350 
65351 /* EVENTS_EDEND @Bit 0 : Sampling of energy detection complete (a new ED sample is ready for readout from the RADIO.EDSAMPLE
65352                          register) */
65353 
65354   #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL)  /*!< Position of EVENTS_EDEND field.                                      */
65355   #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND
65356                                                                             field.*/
65357   #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Min (0x0UL) /*!< Min enumerator value of EVENTS_EDEND field.                         */
65358   #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Max (0x1UL) /*!< Max enumerator value of EVENTS_EDEND field.                         */
65359   #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0x0UL) /*!< Event not generated                                        */
65360   #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (0x1UL) /*!< Event generated                                               */
65361 
65362 
65363 /* RADIO_EVENTS_EDSTOPPED: The sampling of energy detection has stopped */
65364   #define RADIO_EVENTS_EDSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_EDSTOPPED register.                      */
65365 
65366 /* EVENTS_EDSTOPPED @Bit 0 : The sampling of energy detection has stopped */
65367   #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field.                           */
65368   #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of
65369                                                                             EVENTS_EDSTOPPED field.*/
65370   #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_EDSTOPPED field.             */
65371   #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_EDSTOPPED field.             */
65372   #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0x0UL) /*!< Event not generated                                */
65373   #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (0x1UL) /*!< Event generated                                       */
65374 
65375 
65376 /* RADIO_EVENTS_CCAIDLE: Wireless medium in idle - clear to send */
65377   #define RADIO_EVENTS_CCAIDLE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCAIDLE register.                          */
65378 
65379 /* EVENTS_CCAIDLE @Bit 0 : Wireless medium in idle - clear to send */
65380   #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field.                                 */
65381   #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of
65382                                                                             EVENTS_CCAIDLE field.*/
65383   #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCAIDLE field.                   */
65384   #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCAIDLE field.                   */
65385   #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0x0UL) /*!< Event not generated                                    */
65386   #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (0x1UL) /*!< Event generated                                           */
65387 
65388 
65389 /* RADIO_EVENTS_CCABUSY: Wireless medium busy - do not send */
65390   #define RADIO_EVENTS_CCABUSY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCABUSY register.                          */
65391 
65392 /* EVENTS_CCABUSY @Bit 0 : Wireless medium busy - do not send */
65393   #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field.                                 */
65394   #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of
65395                                                                             EVENTS_CCABUSY field.*/
65396   #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCABUSY field.                   */
65397   #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCABUSY field.                   */
65398   #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0x0UL) /*!< Event not generated                                    */
65399   #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (0x1UL) /*!< Event generated                                           */
65400 
65401 
65402 /* RADIO_EVENTS_CCASTOPPED: The CCA has stopped */
65403   #define RADIO_EVENTS_CCASTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CCASTOPPED register.                    */
65404 
65405 /* EVENTS_CCASTOPPED @Bit 0 : The CCA has stopped */
65406   #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field.                        */
65407   #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask
65408                                                                             of EVENTS_CCASTOPPED field.*/
65409   #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_CCASTOPPED field.          */
65410   #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_CCASTOPPED field.          */
65411   #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0x0UL) /*!< Event not generated                              */
65412   #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (0x1UL) /*!< Event generated                                     */
65413 
65414 
65415 /* RADIO_EVENTS_RATEBOOST: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit */
65416   #define RADIO_EVENTS_RATEBOOST_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RATEBOOST register.                      */
65417 
65418 /* EVENTS_RATEBOOST @Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit */
65419   #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field.                           */
65420   #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of
65421                                                                             EVENTS_RATEBOOST field.*/
65422   #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Min (0x0UL) /*!< Min enumerator value of EVENTS_RATEBOOST field.             */
65423   #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Max (0x1UL) /*!< Max enumerator value of EVENTS_RATEBOOST field.             */
65424   #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0x0UL) /*!< Event not generated                                */
65425   #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (0x1UL) /*!< Event generated                                       */
65426 
65427 
65428 /* RADIO_EVENTS_MHRMATCH: MAC header match found */
65429   #define RADIO_EVENTS_MHRMATCH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_MHRMATCH register.                        */
65430 
65431 /* EVENTS_MHRMATCH @Bit 0 : MAC header match found */
65432   #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field.                              */
65433   #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of
65434                                                                             EVENTS_MHRMATCH field.*/
65435   #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Min (0x0UL) /*!< Min enumerator value of EVENTS_MHRMATCH field.                */
65436   #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Max (0x1UL) /*!< Max enumerator value of EVENTS_MHRMATCH field.                */
65437   #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0x0UL) /*!< Event not generated                                  */
65438   #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (0x1UL) /*!< Event generated                                         */
65439 
65440 
65441 /* RADIO_EVENTS_SYNC: Initial sync detected */
65442   #define RADIO_EVENTS_SYNC_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SYNC register.                                */
65443 
65444 /* EVENTS_SYNC @Bit 0 : Initial sync detected */
65445   #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL)    /*!< Position of EVENTS_SYNC field.                                       */
65446   #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field.   */
65447   #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Min (0x0UL)  /*!< Min enumerator value of EVENTS_SYNC field.                           */
65448   #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Max (0x1UL)  /*!< Max enumerator value of EVENTS_SYNC field.                           */
65449   #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0x0UL) /*!< Event not generated                                          */
65450   #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (0x1UL) /*!< Event generated                                                 */
65451 
65452 
65453 /* RADIO_EVENTS_CTEPRESENT: CTEInfo byte is received */
65454   #define RADIO_EVENTS_CTEPRESENT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CTEPRESENT register.                    */
65455 
65456 /* EVENTS_CTEPRESENT @Bit 0 : CTEInfo byte is received */
65457   #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field.                        */
65458   #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask
65459                                                                             of EVENTS_CTEPRESENT field.*/
65460   #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Min (0x0UL) /*!< Min enumerator value of EVENTS_CTEPRESENT field.          */
65461   #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Max (0x1UL) /*!< Max enumerator value of EVENTS_CTEPRESENT field.          */
65462   #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0x0UL) /*!< Event not generated                              */
65463   #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (0x1UL) /*!< Event generated                                     */
65464 
65465 
65466 /* RADIO_PUBLISH_READY: Publish configuration for event READY */
65467   #define RADIO_PUBLISH_READY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READY register.                            */
65468 
65469 /* CHIDX @Bits 0..7 : DPPI channel that event READY will publish to */
65470   #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
65471   #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
65472   #define RADIO_PUBLISH_READY_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
65473   #define RADIO_PUBLISH_READY_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
65474 
65475 /* EN @Bit 31 : (unspecified) */
65476   #define RADIO_PUBLISH_READY_EN_Pos (31UL)          /*!< Position of EN field.                                                */
65477   #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field.                          */
65478   #define RADIO_PUBLISH_READY_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
65479   #define RADIO_PUBLISH_READY_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
65480   #define RADIO_PUBLISH_READY_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
65481   #define RADIO_PUBLISH_READY_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
65482 
65483 
65484 /* RADIO_PUBLISH_TXREADY: Publish configuration for event TXREADY */
65485   #define RADIO_PUBLISH_TXREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXREADY register.                        */
65486 
65487 /* CHIDX @Bits 0..7 : DPPI channel that event TXREADY will publish to */
65488   #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
65489   #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
65490   #define RADIO_PUBLISH_TXREADY_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
65491   #define RADIO_PUBLISH_TXREADY_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
65492 
65493 /* EN @Bit 31 : (unspecified) */
65494   #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL)        /*!< Position of EN field.                                                */
65495   #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos) /*!< Bit mask of EN field.                      */
65496   #define RADIO_PUBLISH_TXREADY_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
65497   #define RADIO_PUBLISH_TXREADY_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
65498   #define RADIO_PUBLISH_TXREADY_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
65499   #define RADIO_PUBLISH_TXREADY_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
65500 
65501 
65502 /* RADIO_PUBLISH_RXREADY: Publish configuration for event RXREADY */
65503   #define RADIO_PUBLISH_RXREADY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXREADY register.                        */
65504 
65505 /* CHIDX @Bits 0..7 : DPPI channel that event RXREADY will publish to */
65506   #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
65507   #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
65508   #define RADIO_PUBLISH_RXREADY_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
65509   #define RADIO_PUBLISH_RXREADY_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
65510 
65511 /* EN @Bit 31 : (unspecified) */
65512   #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL)        /*!< Position of EN field.                                                */
65513   #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos) /*!< Bit mask of EN field.                      */
65514   #define RADIO_PUBLISH_RXREADY_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
65515   #define RADIO_PUBLISH_RXREADY_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
65516   #define RADIO_PUBLISH_RXREADY_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
65517   #define RADIO_PUBLISH_RXREADY_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
65518 
65519 
65520 /* RADIO_PUBLISH_ADDRESS: Publish configuration for event ADDRESS */
65521   #define RADIO_PUBLISH_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ADDRESS register.                        */
65522 
65523 /* CHIDX @Bits 0..7 : DPPI channel that event ADDRESS will publish to */
65524   #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
65525   #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
65526   #define RADIO_PUBLISH_ADDRESS_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
65527   #define RADIO_PUBLISH_ADDRESS_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
65528 
65529 /* EN @Bit 31 : (unspecified) */
65530   #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL)        /*!< Position of EN field.                                                */
65531   #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos) /*!< Bit mask of EN field.                      */
65532   #define RADIO_PUBLISH_ADDRESS_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
65533   #define RADIO_PUBLISH_ADDRESS_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
65534   #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
65535   #define RADIO_PUBLISH_ADDRESS_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
65536 
65537 
65538 /* RADIO_PUBLISH_FRAMESTART: Publish configuration for event FRAMESTART */
65539   #define RADIO_PUBLISH_FRAMESTART_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_FRAMESTART register.                  */
65540 
65541 /* CHIDX @Bits 0..7 : DPPI channel that event FRAMESTART will publish to */
65542   #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
65543   #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
65544   #define RADIO_PUBLISH_FRAMESTART_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
65545   #define RADIO_PUBLISH_FRAMESTART_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
65546 
65547 /* EN @Bit 31 : (unspecified) */
65548   #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL)     /*!< Position of EN field.                                                */
65549   #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field.                */
65550   #define RADIO_PUBLISH_FRAMESTART_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
65551   #define RADIO_PUBLISH_FRAMESTART_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
65552   #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
65553   #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */
65554 
65555 
65556 /* RADIO_PUBLISH_PAYLOAD: Publish configuration for event PAYLOAD */
65557   #define RADIO_PUBLISH_PAYLOAD_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PAYLOAD register.                        */
65558 
65559 /* CHIDX @Bits 0..7 : DPPI channel that event PAYLOAD will publish to */
65560   #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
65561   #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
65562   #define RADIO_PUBLISH_PAYLOAD_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
65563   #define RADIO_PUBLISH_PAYLOAD_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
65564 
65565 /* EN @Bit 31 : (unspecified) */
65566   #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL)        /*!< Position of EN field.                                                */
65567   #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos) /*!< Bit mask of EN field.                      */
65568   #define RADIO_PUBLISH_PAYLOAD_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
65569   #define RADIO_PUBLISH_PAYLOAD_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
65570   #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
65571   #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
65572 
65573 
65574 /* RADIO_PUBLISH_END: Publish configuration for event END */
65575   #define RADIO_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                */
65576 
65577 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
65578   #define RADIO_PUBLISH_END_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
65579   #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
65580   #define RADIO_PUBLISH_END_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
65581   #define RADIO_PUBLISH_END_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
65582 
65583 /* EN @Bit 31 : (unspecified) */
65584   #define RADIO_PUBLISH_END_EN_Pos (31UL)            /*!< Position of EN field.                                                */
65585   #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                              */
65586   #define RADIO_PUBLISH_END_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
65587   #define RADIO_PUBLISH_END_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
65588   #define RADIO_PUBLISH_END_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
65589   #define RADIO_PUBLISH_END_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
65590 
65591 
65592 /* RADIO_PUBLISH_PHYEND: Publish configuration for event PHYEND */
65593   #define RADIO_PUBLISH_PHYEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_PHYEND register.                          */
65594 
65595 /* CHIDX @Bits 0..7 : DPPI channel that event PHYEND will publish to */
65596   #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
65597   #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
65598   #define RADIO_PUBLISH_PHYEND_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
65599   #define RADIO_PUBLISH_PHYEND_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
65600 
65601 /* EN @Bit 31 : (unspecified) */
65602   #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL)         /*!< Position of EN field.                                                */
65603   #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos) /*!< Bit mask of EN field.                        */
65604   #define RADIO_PUBLISH_PHYEND_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
65605   #define RADIO_PUBLISH_PHYEND_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
65606   #define RADIO_PUBLISH_PHYEND_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
65607   #define RADIO_PUBLISH_PHYEND_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
65608 
65609 
65610 /* RADIO_PUBLISH_DISABLED: Publish configuration for event DISABLED */
65611   #define RADIO_PUBLISH_DISABLED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DISABLED register.                      */
65612 
65613 /* CHIDX @Bits 0..7 : DPPI channel that event DISABLED will publish to */
65614   #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
65615   #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
65616   #define RADIO_PUBLISH_DISABLED_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
65617   #define RADIO_PUBLISH_DISABLED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
65618 
65619 /* EN @Bit 31 : (unspecified) */
65620   #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
65621   #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos) /*!< Bit mask of EN field.                    */
65622   #define RADIO_PUBLISH_DISABLED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
65623   #define RADIO_PUBLISH_DISABLED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
65624   #define RADIO_PUBLISH_DISABLED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
65625   #define RADIO_PUBLISH_DISABLED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
65626 
65627 
65628 /* RADIO_PUBLISH_DEVMATCH: Publish configuration for event DEVMATCH */
65629   #define RADIO_PUBLISH_DEVMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DEVMATCH register.                      */
65630 
65631 /* CHIDX @Bits 0..7 : DPPI channel that event DEVMATCH will publish to */
65632   #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
65633   #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
65634   #define RADIO_PUBLISH_DEVMATCH_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
65635   #define RADIO_PUBLISH_DEVMATCH_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
65636 
65637 /* EN @Bit 31 : (unspecified) */
65638   #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL)       /*!< Position of EN field.                                                */
65639   #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos) /*!< Bit mask of EN field.                    */
65640   #define RADIO_PUBLISH_DEVMATCH_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
65641   #define RADIO_PUBLISH_DEVMATCH_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
65642   #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
65643   #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
65644 
65645 
65646 /* RADIO_PUBLISH_DEVMISS: Publish configuration for event DEVMISS */
65647   #define RADIO_PUBLISH_DEVMISS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DEVMISS register.                        */
65648 
65649 /* CHIDX @Bits 0..7 : DPPI channel that event DEVMISS will publish to */
65650   #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
65651   #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
65652   #define RADIO_PUBLISH_DEVMISS_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
65653   #define RADIO_PUBLISH_DEVMISS_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
65654 
65655 /* EN @Bit 31 : (unspecified) */
65656   #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL)        /*!< Position of EN field.                                                */
65657   #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos) /*!< Bit mask of EN field.                      */
65658   #define RADIO_PUBLISH_DEVMISS_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
65659   #define RADIO_PUBLISH_DEVMISS_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
65660   #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
65661   #define RADIO_PUBLISH_DEVMISS_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
65662 
65663 
65664 /* RADIO_PUBLISH_CRCOK: Publish configuration for event CRCOK */
65665   #define RADIO_PUBLISH_CRCOK_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CRCOK register.                            */
65666 
65667 /* CHIDX @Bits 0..7 : DPPI channel that event CRCOK will publish to */
65668   #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
65669   #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
65670   #define RADIO_PUBLISH_CRCOK_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
65671   #define RADIO_PUBLISH_CRCOK_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
65672 
65673 /* EN @Bit 31 : (unspecified) */
65674   #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL)          /*!< Position of EN field.                                                */
65675   #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos) /*!< Bit mask of EN field.                          */
65676   #define RADIO_PUBLISH_CRCOK_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
65677   #define RADIO_PUBLISH_CRCOK_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
65678   #define RADIO_PUBLISH_CRCOK_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
65679   #define RADIO_PUBLISH_CRCOK_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
65680 
65681 
65682 /* RADIO_PUBLISH_CRCERROR: Publish configuration for event CRCERROR */
65683   #define RADIO_PUBLISH_CRCERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CRCERROR register.                      */
65684 
65685 /* CHIDX @Bits 0..7 : DPPI channel that event CRCERROR will publish to */
65686   #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
65687   #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
65688   #define RADIO_PUBLISH_CRCERROR_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
65689   #define RADIO_PUBLISH_CRCERROR_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
65690 
65691 /* EN @Bit 31 : (unspecified) */
65692   #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL)       /*!< Position of EN field.                                                */
65693   #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos) /*!< Bit mask of EN field.                    */
65694   #define RADIO_PUBLISH_CRCERROR_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
65695   #define RADIO_PUBLISH_CRCERROR_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
65696   #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
65697   #define RADIO_PUBLISH_CRCERROR_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
65698 
65699 
65700 /* RADIO_PUBLISH_BCMATCH: Publish configuration for event BCMATCH */
65701   #define RADIO_PUBLISH_BCMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_BCMATCH register.                        */
65702 
65703 /* CHIDX @Bits 0..7 : DPPI channel that event BCMATCH will publish to */
65704   #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
65705   #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
65706   #define RADIO_PUBLISH_BCMATCH_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
65707   #define RADIO_PUBLISH_BCMATCH_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
65708 
65709 /* EN @Bit 31 : (unspecified) */
65710   #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL)        /*!< Position of EN field.                                                */
65711   #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos) /*!< Bit mask of EN field.                      */
65712   #define RADIO_PUBLISH_BCMATCH_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
65713   #define RADIO_PUBLISH_BCMATCH_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
65714   #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
65715   #define RADIO_PUBLISH_BCMATCH_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
65716 
65717 
65718 /* RADIO_PUBLISH_EDEND: Publish configuration for event EDEND */
65719   #define RADIO_PUBLISH_EDEND_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_EDEND register.                            */
65720 
65721 /* CHIDX @Bits 0..7 : DPPI channel that event EDEND will publish to */
65722   #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
65723   #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
65724   #define RADIO_PUBLISH_EDEND_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
65725   #define RADIO_PUBLISH_EDEND_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
65726 
65727 /* EN @Bit 31 : (unspecified) */
65728   #define RADIO_PUBLISH_EDEND_EN_Pos (31UL)          /*!< Position of EN field.                                                */
65729   #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos) /*!< Bit mask of EN field.                          */
65730   #define RADIO_PUBLISH_EDEND_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
65731   #define RADIO_PUBLISH_EDEND_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
65732   #define RADIO_PUBLISH_EDEND_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
65733   #define RADIO_PUBLISH_EDEND_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
65734 
65735 
65736 /* RADIO_PUBLISH_EDSTOPPED: Publish configuration for event EDSTOPPED */
65737   #define RADIO_PUBLISH_EDSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_EDSTOPPED register.                    */
65738 
65739 /* CHIDX @Bits 0..7 : DPPI channel that event EDSTOPPED will publish to */
65740   #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
65741   #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
65742   #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
65743   #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
65744 
65745 /* EN @Bit 31 : (unspecified) */
65746   #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL)      /*!< Position of EN field.                                                */
65747   #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos) /*!< Bit mask of EN field.                  */
65748   #define RADIO_PUBLISH_EDSTOPPED_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
65749   #define RADIO_PUBLISH_EDSTOPPED_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
65750   #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
65751   #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
65752 
65753 
65754 /* RADIO_PUBLISH_CCAIDLE: Publish configuration for event CCAIDLE */
65755   #define RADIO_PUBLISH_CCAIDLE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCAIDLE register.                        */
65756 
65757 /* CHIDX @Bits 0..7 : DPPI channel that event CCAIDLE will publish to */
65758   #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
65759   #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
65760   #define RADIO_PUBLISH_CCAIDLE_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
65761   #define RADIO_PUBLISH_CCAIDLE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
65762 
65763 /* EN @Bit 31 : (unspecified) */
65764   #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
65765   #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos) /*!< Bit mask of EN field.                      */
65766   #define RADIO_PUBLISH_CCAIDLE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
65767   #define RADIO_PUBLISH_CCAIDLE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
65768   #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
65769   #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
65770 
65771 
65772 /* RADIO_PUBLISH_CCABUSY: Publish configuration for event CCABUSY */
65773   #define RADIO_PUBLISH_CCABUSY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCABUSY register.                        */
65774 
65775 /* CHIDX @Bits 0..7 : DPPI channel that event CCABUSY will publish to */
65776   #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
65777   #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
65778   #define RADIO_PUBLISH_CCABUSY_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
65779   #define RADIO_PUBLISH_CCABUSY_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
65780 
65781 /* EN @Bit 31 : (unspecified) */
65782   #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL)        /*!< Position of EN field.                                                */
65783   #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos) /*!< Bit mask of EN field.                      */
65784   #define RADIO_PUBLISH_CCABUSY_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
65785   #define RADIO_PUBLISH_CCABUSY_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
65786   #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
65787   #define RADIO_PUBLISH_CCABUSY_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
65788 
65789 
65790 /* RADIO_PUBLISH_CCASTOPPED: Publish configuration for event CCASTOPPED */
65791   #define RADIO_PUBLISH_CCASTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CCASTOPPED register.                  */
65792 
65793 /* CHIDX @Bits 0..7 : DPPI channel that event CCASTOPPED will publish to */
65794   #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
65795   #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
65796   #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
65797   #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
65798 
65799 /* EN @Bit 31 : (unspecified) */
65800   #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL)     /*!< Position of EN field.                                                */
65801   #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos) /*!< Bit mask of EN field.                */
65802   #define RADIO_PUBLISH_CCASTOPPED_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
65803   #define RADIO_PUBLISH_CCASTOPPED_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
65804   #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
65805   #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */
65806 
65807 
65808 /* RADIO_PUBLISH_RATEBOOST: Publish configuration for event RATEBOOST */
65809   #define RADIO_PUBLISH_RATEBOOST_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RATEBOOST register.                    */
65810 
65811 /* CHIDX @Bits 0..7 : DPPI channel that event RATEBOOST will publish to */
65812   #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
65813   #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
65814   #define RADIO_PUBLISH_RATEBOOST_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
65815   #define RADIO_PUBLISH_RATEBOOST_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
65816 
65817 /* EN @Bit 31 : (unspecified) */
65818   #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL)      /*!< Position of EN field.                                                */
65819   #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos) /*!< Bit mask of EN field.                  */
65820   #define RADIO_PUBLISH_RATEBOOST_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
65821   #define RADIO_PUBLISH_RATEBOOST_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
65822   #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
65823   #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
65824 
65825 
65826 /* RADIO_PUBLISH_MHRMATCH: Publish configuration for event MHRMATCH */
65827   #define RADIO_PUBLISH_MHRMATCH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_MHRMATCH register.                      */
65828 
65829 /* CHIDX @Bits 0..7 : DPPI channel that event MHRMATCH will publish to */
65830   #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
65831   #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
65832   #define RADIO_PUBLISH_MHRMATCH_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
65833   #define RADIO_PUBLISH_MHRMATCH_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
65834 
65835 /* EN @Bit 31 : (unspecified) */
65836   #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL)       /*!< Position of EN field.                                                */
65837   #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos) /*!< Bit mask of EN field.                    */
65838   #define RADIO_PUBLISH_MHRMATCH_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
65839   #define RADIO_PUBLISH_MHRMATCH_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
65840   #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
65841   #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
65842 
65843 
65844 /* RADIO_PUBLISH_SYNC: Publish configuration for event SYNC */
65845   #define RADIO_PUBLISH_SYNC_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SYNC register.                              */
65846 
65847 /* CHIDX @Bits 0..7 : DPPI channel that event SYNC will publish to */
65848   #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
65849   #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
65850   #define RADIO_PUBLISH_SYNC_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
65851   #define RADIO_PUBLISH_SYNC_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
65852 
65853 /* EN @Bit 31 : (unspecified) */
65854   #define RADIO_PUBLISH_SYNC_EN_Pos (31UL)           /*!< Position of EN field.                                                */
65855   #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field.                            */
65856   #define RADIO_PUBLISH_SYNC_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
65857   #define RADIO_PUBLISH_SYNC_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
65858   #define RADIO_PUBLISH_SYNC_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
65859   #define RADIO_PUBLISH_SYNC_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
65860 
65861 
65862 /* RADIO_PUBLISH_CTEPRESENT: Publish configuration for event CTEPRESENT */
65863   #define RADIO_PUBLISH_CTEPRESENT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CTEPRESENT register.                  */
65864 
65865 /* CHIDX @Bits 0..7 : DPPI channel that event CTEPRESENT will publish to */
65866   #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
65867   #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
65868   #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
65869   #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
65870 
65871 /* EN @Bit 31 : (unspecified) */
65872   #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL)     /*!< Position of EN field.                                                */
65873   #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos) /*!< Bit mask of EN field.                */
65874   #define RADIO_PUBLISH_CTEPRESENT_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
65875   #define RADIO_PUBLISH_CTEPRESENT_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
65876   #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
65877   #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */
65878 
65879 
65880 /* RADIO_SHORTS: Shortcuts between local events and tasks */
65881   #define RADIO_SHORTS_ResetValue (0x00000000UL)     /*!< Reset value of SHORTS register.                                      */
65882 
65883 /* READY_START @Bit 0 : Shortcut between event READY and task START */
65884   #define RADIO_SHORTS_READY_START_Pos (0UL)         /*!< Position of READY_START field.                                       */
65885   #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field.             */
65886   #define RADIO_SHORTS_READY_START_Min (0x0UL)       /*!< Min enumerator value of READY_START field.                           */
65887   #define RADIO_SHORTS_READY_START_Max (0x1UL)       /*!< Max enumerator value of READY_START field.                           */
65888   #define RADIO_SHORTS_READY_START_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
65889   #define RADIO_SHORTS_READY_START_Enabled (0x1UL)   /*!< Enable shortcut                                                      */
65890 
65891 /* END_DISABLE @Bit 1 : Shortcut between event END and task DISABLE */
65892   #define RADIO_SHORTS_END_DISABLE_Pos (1UL)         /*!< Position of END_DISABLE field.                                       */
65893   #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field.             */
65894   #define RADIO_SHORTS_END_DISABLE_Min (0x0UL)       /*!< Min enumerator value of END_DISABLE field.                           */
65895   #define RADIO_SHORTS_END_DISABLE_Max (0x1UL)       /*!< Max enumerator value of END_DISABLE field.                           */
65896   #define RADIO_SHORTS_END_DISABLE_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
65897   #define RADIO_SHORTS_END_DISABLE_Enabled (0x1UL)   /*!< Enable shortcut                                                      */
65898 
65899 /* DISABLED_TXEN @Bit 2 : Shortcut between event DISABLED and task TXEN */
65900   #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL)       /*!< Position of DISABLED_TXEN field.                                     */
65901   #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field.       */
65902   #define RADIO_SHORTS_DISABLED_TXEN_Min (0x0UL)     /*!< Min enumerator value of DISABLED_TXEN field.                         */
65903   #define RADIO_SHORTS_DISABLED_TXEN_Max (0x1UL)     /*!< Max enumerator value of DISABLED_TXEN field.                         */
65904   #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0x0UL) /*!< Disable shortcut                                                    */
65905   #define RADIO_SHORTS_DISABLED_TXEN_Enabled (0x1UL) /*!< Enable shortcut                                                      */
65906 
65907 /* DISABLED_RXEN @Bit 3 : Shortcut between event DISABLED and task RXEN */
65908   #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL)       /*!< Position of DISABLED_RXEN field.                                     */
65909   #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field.       */
65910   #define RADIO_SHORTS_DISABLED_RXEN_Min (0x0UL)     /*!< Min enumerator value of DISABLED_RXEN field.                         */
65911   #define RADIO_SHORTS_DISABLED_RXEN_Max (0x1UL)     /*!< Max enumerator value of DISABLED_RXEN field.                         */
65912   #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0x0UL) /*!< Disable shortcut                                                    */
65913   #define RADIO_SHORTS_DISABLED_RXEN_Enabled (0x1UL) /*!< Enable shortcut                                                      */
65914 
65915 /* ADDRESS_RSSISTART @Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
65916   #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL)   /*!< Position of ADDRESS_RSSISTART field.                                 */
65917   #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART
65918                                                                             field.*/
65919   #define RADIO_SHORTS_ADDRESS_RSSISTART_Min (0x0UL) /*!< Min enumerator value of ADDRESS_RSSISTART field.                     */
65920   #define RADIO_SHORTS_ADDRESS_RSSISTART_Max (0x1UL) /*!< Max enumerator value of ADDRESS_RSSISTART field.                     */
65921   #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0x0UL) /*!< Disable shortcut                                                */
65922   #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (0x1UL) /*!< Enable shortcut                                                  */
65923 
65924 /* END_START @Bit 5 : Shortcut between event END and task START */
65925   #define RADIO_SHORTS_END_START_Pos (5UL)           /*!< Position of END_START field.                                         */
65926   #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field.                   */
65927   #define RADIO_SHORTS_END_START_Min (0x0UL)         /*!< Min enumerator value of END_START field.                             */
65928   #define RADIO_SHORTS_END_START_Max (0x1UL)         /*!< Max enumerator value of END_START field.                             */
65929   #define RADIO_SHORTS_END_START_Disabled (0x0UL)    /*!< Disable shortcut                                                     */
65930   #define RADIO_SHORTS_END_START_Enabled (0x1UL)     /*!< Enable shortcut                                                      */
65931 
65932 /* ADDRESS_BCSTART @Bit 6 : Shortcut between event ADDRESS and task BCSTART */
65933   #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL)     /*!< Position of ADDRESS_BCSTART field.                                   */
65934   #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
65935   #define RADIO_SHORTS_ADDRESS_BCSTART_Min (0x0UL)   /*!< Min enumerator value of ADDRESS_BCSTART field.                       */
65936   #define RADIO_SHORTS_ADDRESS_BCSTART_Max (0x1UL)   /*!< Max enumerator value of ADDRESS_BCSTART field.                       */
65937   #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0x0UL) /*!< Disable shortcut                                                  */
65938   #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (0x1UL) /*!< Enable shortcut                                                    */
65939 
65940 /* RXREADY_CCASTART @Bit 10 : Shortcut between event RXREADY and task CCASTART */
65941   #define RADIO_SHORTS_RXREADY_CCASTART_Pos (10UL)   /*!< Position of RXREADY_CCASTART field.                                  */
65942   #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART
65943                                                                             field.*/
65944   #define RADIO_SHORTS_RXREADY_CCASTART_Min (0x0UL)  /*!< Min enumerator value of RXREADY_CCASTART field.                      */
65945   #define RADIO_SHORTS_RXREADY_CCASTART_Max (0x1UL)  /*!< Max enumerator value of RXREADY_CCASTART field.                      */
65946   #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0x0UL) /*!< Disable shortcut                                                 */
65947   #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (0x1UL) /*!< Enable shortcut                                                   */
65948 
65949 /* CCAIDLE_TXEN @Bit 11 : Shortcut between event CCAIDLE and task TXEN */
65950   #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (11UL)       /*!< Position of CCAIDLE_TXEN field.                                      */
65951   #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field.          */
65952   #define RADIO_SHORTS_CCAIDLE_TXEN_Min (0x0UL)      /*!< Min enumerator value of CCAIDLE_TXEN field.                          */
65953   #define RADIO_SHORTS_CCAIDLE_TXEN_Max (0x1UL)      /*!< Max enumerator value of CCAIDLE_TXEN field.                          */
65954   #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0x0UL) /*!< Disable shortcut                                                     */
65955   #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
65956 
65957 /* CCABUSY_DISABLE @Bit 12 : Shortcut between event CCABUSY and task DISABLE */
65958   #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (12UL)    /*!< Position of CCABUSY_DISABLE field.                                   */
65959   #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
65960   #define RADIO_SHORTS_CCABUSY_DISABLE_Min (0x0UL)   /*!< Min enumerator value of CCABUSY_DISABLE field.                       */
65961   #define RADIO_SHORTS_CCABUSY_DISABLE_Max (0x1UL)   /*!< Max enumerator value of CCABUSY_DISABLE field.                       */
65962   #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0x0UL) /*!< Disable shortcut                                                  */
65963   #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (0x1UL) /*!< Enable shortcut                                                    */
65964 
65965 /* FRAMESTART_BCSTART @Bit 13 : Shortcut between event FRAMESTART and task BCSTART */
65966   #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (13UL) /*!< Position of FRAMESTART_BCSTART field.                                */
65967   #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART
65968                                                                             field.*/
65969   #define RADIO_SHORTS_FRAMESTART_BCSTART_Min (0x0UL) /*!< Min enumerator value of FRAMESTART_BCSTART field.                   */
65970   #define RADIO_SHORTS_FRAMESTART_BCSTART_Max (0x1UL) /*!< Max enumerator value of FRAMESTART_BCSTART field.                   */
65971   #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0x0UL) /*!< Disable shortcut                                               */
65972   #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (0x1UL) /*!< Enable shortcut                                                 */
65973 
65974 /* READY_EDSTART @Bit 14 : Shortcut between event READY and task EDSTART */
65975   #define RADIO_SHORTS_READY_EDSTART_Pos (14UL)      /*!< Position of READY_EDSTART field.                                     */
65976   #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field.       */
65977   #define RADIO_SHORTS_READY_EDSTART_Min (0x0UL)     /*!< Min enumerator value of READY_EDSTART field.                         */
65978   #define RADIO_SHORTS_READY_EDSTART_Max (0x1UL)     /*!< Max enumerator value of READY_EDSTART field.                         */
65979   #define RADIO_SHORTS_READY_EDSTART_Disabled (0x0UL) /*!< Disable shortcut                                                    */
65980   #define RADIO_SHORTS_READY_EDSTART_Enabled (0x1UL) /*!< Enable shortcut                                                      */
65981 
65982 /* EDEND_DISABLE @Bit 15 : Shortcut between event EDEND and task DISABLE */
65983   #define RADIO_SHORTS_EDEND_DISABLE_Pos (15UL)      /*!< Position of EDEND_DISABLE field.                                     */
65984   #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field.       */
65985   #define RADIO_SHORTS_EDEND_DISABLE_Min (0x0UL)     /*!< Min enumerator value of EDEND_DISABLE field.                         */
65986   #define RADIO_SHORTS_EDEND_DISABLE_Max (0x1UL)     /*!< Max enumerator value of EDEND_DISABLE field.                         */
65987   #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut                                                    */
65988   #define RADIO_SHORTS_EDEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut                                                      */
65989 
65990 /* CCAIDLE_STOP @Bit 16 : Shortcut between event CCAIDLE and task STOP */
65991   #define RADIO_SHORTS_CCAIDLE_STOP_Pos (16UL)       /*!< Position of CCAIDLE_STOP field.                                      */
65992   #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field.          */
65993   #define RADIO_SHORTS_CCAIDLE_STOP_Min (0x0UL)      /*!< Min enumerator value of CCAIDLE_STOP field.                          */
65994   #define RADIO_SHORTS_CCAIDLE_STOP_Max (0x1UL)      /*!< Max enumerator value of CCAIDLE_STOP field.                          */
65995   #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                     */
65996   #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
65997 
65998 /* TXREADY_START @Bit 17 : Shortcut between event TXREADY and task START */
65999   #define RADIO_SHORTS_TXREADY_START_Pos (17UL)      /*!< Position of TXREADY_START field.                                     */
66000   #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field.       */
66001   #define RADIO_SHORTS_TXREADY_START_Min (0x0UL)     /*!< Min enumerator value of TXREADY_START field.                         */
66002   #define RADIO_SHORTS_TXREADY_START_Max (0x1UL)     /*!< Max enumerator value of TXREADY_START field.                         */
66003   #define RADIO_SHORTS_TXREADY_START_Disabled (0x0UL) /*!< Disable shortcut                                                    */
66004   #define RADIO_SHORTS_TXREADY_START_Enabled (0x1UL) /*!< Enable shortcut                                                      */
66005 
66006 /* RXREADY_START @Bit 18 : Shortcut between event RXREADY and task START */
66007   #define RADIO_SHORTS_RXREADY_START_Pos (18UL)      /*!< Position of RXREADY_START field.                                     */
66008   #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field.       */
66009   #define RADIO_SHORTS_RXREADY_START_Min (0x0UL)     /*!< Min enumerator value of RXREADY_START field.                         */
66010   #define RADIO_SHORTS_RXREADY_START_Max (0x1UL)     /*!< Max enumerator value of RXREADY_START field.                         */
66011   #define RADIO_SHORTS_RXREADY_START_Disabled (0x0UL) /*!< Disable shortcut                                                    */
66012   #define RADIO_SHORTS_RXREADY_START_Enabled (0x1UL) /*!< Enable shortcut                                                      */
66013 
66014 /* PHYEND_DISABLE @Bit 19 : Shortcut between event PHYEND and task DISABLE */
66015   #define RADIO_SHORTS_PHYEND_DISABLE_Pos (19UL)     /*!< Position of PHYEND_DISABLE field.                                    */
66016   #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field.    */
66017   #define RADIO_SHORTS_PHYEND_DISABLE_Min (0x0UL)    /*!< Min enumerator value of PHYEND_DISABLE field.                        */
66018   #define RADIO_SHORTS_PHYEND_DISABLE_Max (0x1UL)    /*!< Max enumerator value of PHYEND_DISABLE field.                        */
66019   #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0x0UL) /*!< Disable shortcut                                                   */
66020   #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (0x1UL) /*!< Enable shortcut                                                     */
66021 
66022 /* PHYEND_START @Bit 20 : Shortcut between event PHYEND and task START */
66023   #define RADIO_SHORTS_PHYEND_START_Pos (20UL)       /*!< Position of PHYEND_START field.                                      */
66024   #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field.          */
66025   #define RADIO_SHORTS_PHYEND_START_Min (0x0UL)      /*!< Min enumerator value of PHYEND_START field.                          */
66026   #define RADIO_SHORTS_PHYEND_START_Max (0x1UL)      /*!< Max enumerator value of PHYEND_START field.                          */
66027   #define RADIO_SHORTS_PHYEND_START_Disabled (0x0UL) /*!< Disable shortcut                                                     */
66028   #define RADIO_SHORTS_PHYEND_START_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
66029 
66030 
66031 /* RADIO_INTENSET00: Enable interrupt */
66032   #define RADIO_INTENSET00_ResetValue (0x00000000UL) /*!< Reset value of INTENSET00 register.                                  */
66033 
66034 /* READY @Bit 0 : Write '1' to enable interrupt for event READY */
66035   #define RADIO_INTENSET00_READY_Pos (0UL)           /*!< Position of READY field.                                             */
66036   #define RADIO_INTENSET00_READY_Msk (0x1UL << RADIO_INTENSET00_READY_Pos) /*!< Bit mask of READY field.                       */
66037   #define RADIO_INTENSET00_READY_Min (0x0UL)         /*!< Min enumerator value of READY field.                                 */
66038   #define RADIO_INTENSET00_READY_Max (0x1UL)         /*!< Max enumerator value of READY field.                                 */
66039   #define RADIO_INTENSET00_READY_Set (0x1UL)         /*!< Enable                                                               */
66040   #define RADIO_INTENSET00_READY_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66041   #define RADIO_INTENSET00_READY_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66042 
66043 /* TXREADY @Bit 1 : Write '1' to enable interrupt for event TXREADY */
66044   #define RADIO_INTENSET00_TXREADY_Pos (1UL)         /*!< Position of TXREADY field.                                           */
66045   #define RADIO_INTENSET00_TXREADY_Msk (0x1UL << RADIO_INTENSET00_TXREADY_Pos) /*!< Bit mask of TXREADY field.                 */
66046   #define RADIO_INTENSET00_TXREADY_Min (0x0UL)       /*!< Min enumerator value of TXREADY field.                               */
66047   #define RADIO_INTENSET00_TXREADY_Max (0x1UL)       /*!< Max enumerator value of TXREADY field.                               */
66048   #define RADIO_INTENSET00_TXREADY_Set (0x1UL)       /*!< Enable                                                               */
66049   #define RADIO_INTENSET00_TXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66050   #define RADIO_INTENSET00_TXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66051 
66052 /* RXREADY @Bit 2 : Write '1' to enable interrupt for event RXREADY */
66053   #define RADIO_INTENSET00_RXREADY_Pos (2UL)         /*!< Position of RXREADY field.                                           */
66054   #define RADIO_INTENSET00_RXREADY_Msk (0x1UL << RADIO_INTENSET00_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
66055   #define RADIO_INTENSET00_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
66056   #define RADIO_INTENSET00_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
66057   #define RADIO_INTENSET00_RXREADY_Set (0x1UL)       /*!< Enable                                                               */
66058   #define RADIO_INTENSET00_RXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66059   #define RADIO_INTENSET00_RXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66060 
66061 /* ADDRESS @Bit 3 : Write '1' to enable interrupt for event ADDRESS */
66062   #define RADIO_INTENSET00_ADDRESS_Pos (3UL)         /*!< Position of ADDRESS field.                                           */
66063   #define RADIO_INTENSET00_ADDRESS_Msk (0x1UL << RADIO_INTENSET00_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                 */
66064   #define RADIO_INTENSET00_ADDRESS_Min (0x0UL)       /*!< Min enumerator value of ADDRESS field.                               */
66065   #define RADIO_INTENSET00_ADDRESS_Max (0x1UL)       /*!< Max enumerator value of ADDRESS field.                               */
66066   #define RADIO_INTENSET00_ADDRESS_Set (0x1UL)       /*!< Enable                                                               */
66067   #define RADIO_INTENSET00_ADDRESS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66068   #define RADIO_INTENSET00_ADDRESS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66069 
66070 /* FRAMESTART @Bit 4 : Write '1' to enable interrupt for event FRAMESTART */
66071   #define RADIO_INTENSET00_FRAMESTART_Pos (4UL)      /*!< Position of FRAMESTART field.                                        */
66072   #define RADIO_INTENSET00_FRAMESTART_Msk (0x1UL << RADIO_INTENSET00_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.        */
66073   #define RADIO_INTENSET00_FRAMESTART_Min (0x0UL)    /*!< Min enumerator value of FRAMESTART field.                            */
66074   #define RADIO_INTENSET00_FRAMESTART_Max (0x1UL)    /*!< Max enumerator value of FRAMESTART field.                            */
66075   #define RADIO_INTENSET00_FRAMESTART_Set (0x1UL)    /*!< Enable                                                               */
66076   #define RADIO_INTENSET00_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66077   #define RADIO_INTENSET00_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66078 
66079 /* PAYLOAD @Bit 5 : Write '1' to enable interrupt for event PAYLOAD */
66080   #define RADIO_INTENSET00_PAYLOAD_Pos (5UL)         /*!< Position of PAYLOAD field.                                           */
66081   #define RADIO_INTENSET00_PAYLOAD_Msk (0x1UL << RADIO_INTENSET00_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field.                 */
66082   #define RADIO_INTENSET00_PAYLOAD_Min (0x0UL)       /*!< Min enumerator value of PAYLOAD field.                               */
66083   #define RADIO_INTENSET00_PAYLOAD_Max (0x1UL)       /*!< Max enumerator value of PAYLOAD field.                               */
66084   #define RADIO_INTENSET00_PAYLOAD_Set (0x1UL)       /*!< Enable                                                               */
66085   #define RADIO_INTENSET00_PAYLOAD_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66086   #define RADIO_INTENSET00_PAYLOAD_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66087 
66088 /* END @Bit 6 : Write '1' to enable interrupt for event END */
66089   #define RADIO_INTENSET00_END_Pos (6UL)             /*!< Position of END field.                                               */
66090   #define RADIO_INTENSET00_END_Msk (0x1UL << RADIO_INTENSET00_END_Pos) /*!< Bit mask of END field.                             */
66091   #define RADIO_INTENSET00_END_Min (0x0UL)           /*!< Min enumerator value of END field.                                   */
66092   #define RADIO_INTENSET00_END_Max (0x1UL)           /*!< Max enumerator value of END field.                                   */
66093   #define RADIO_INTENSET00_END_Set (0x1UL)           /*!< Enable                                                               */
66094   #define RADIO_INTENSET00_END_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
66095   #define RADIO_INTENSET00_END_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
66096 
66097 /* PHYEND @Bit 7 : Write '1' to enable interrupt for event PHYEND */
66098   #define RADIO_INTENSET00_PHYEND_Pos (7UL)          /*!< Position of PHYEND field.                                            */
66099   #define RADIO_INTENSET00_PHYEND_Msk (0x1UL << RADIO_INTENSET00_PHYEND_Pos) /*!< Bit mask of PHYEND field.                    */
66100   #define RADIO_INTENSET00_PHYEND_Min (0x0UL)        /*!< Min enumerator value of PHYEND field.                                */
66101   #define RADIO_INTENSET00_PHYEND_Max (0x1UL)        /*!< Max enumerator value of PHYEND field.                                */
66102   #define RADIO_INTENSET00_PHYEND_Set (0x1UL)        /*!< Enable                                                               */
66103   #define RADIO_INTENSET00_PHYEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
66104   #define RADIO_INTENSET00_PHYEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
66105 
66106 /* DISABLED @Bit 8 : Write '1' to enable interrupt for event DISABLED */
66107   #define RADIO_INTENSET00_DISABLED_Pos (8UL)        /*!< Position of DISABLED field.                                          */
66108   #define RADIO_INTENSET00_DISABLED_Msk (0x1UL << RADIO_INTENSET00_DISABLED_Pos) /*!< Bit mask of DISABLED field.              */
66109   #define RADIO_INTENSET00_DISABLED_Min (0x0UL)      /*!< Min enumerator value of DISABLED field.                              */
66110   #define RADIO_INTENSET00_DISABLED_Max (0x1UL)      /*!< Max enumerator value of DISABLED field.                              */
66111   #define RADIO_INTENSET00_DISABLED_Set (0x1UL)      /*!< Enable                                                               */
66112   #define RADIO_INTENSET00_DISABLED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66113   #define RADIO_INTENSET00_DISABLED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66114 
66115 /* DEVMATCH @Bit 9 : Write '1' to enable interrupt for event DEVMATCH */
66116   #define RADIO_INTENSET00_DEVMATCH_Pos (9UL)        /*!< Position of DEVMATCH field.                                          */
66117   #define RADIO_INTENSET00_DEVMATCH_Msk (0x1UL << RADIO_INTENSET00_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field.              */
66118   #define RADIO_INTENSET00_DEVMATCH_Min (0x0UL)      /*!< Min enumerator value of DEVMATCH field.                              */
66119   #define RADIO_INTENSET00_DEVMATCH_Max (0x1UL)      /*!< Max enumerator value of DEVMATCH field.                              */
66120   #define RADIO_INTENSET00_DEVMATCH_Set (0x1UL)      /*!< Enable                                                               */
66121   #define RADIO_INTENSET00_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66122   #define RADIO_INTENSET00_DEVMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66123 
66124 /* DEVMISS @Bit 10 : Write '1' to enable interrupt for event DEVMISS */
66125   #define RADIO_INTENSET00_DEVMISS_Pos (10UL)        /*!< Position of DEVMISS field.                                           */
66126   #define RADIO_INTENSET00_DEVMISS_Msk (0x1UL << RADIO_INTENSET00_DEVMISS_Pos) /*!< Bit mask of DEVMISS field.                 */
66127   #define RADIO_INTENSET00_DEVMISS_Min (0x0UL)       /*!< Min enumerator value of DEVMISS field.                               */
66128   #define RADIO_INTENSET00_DEVMISS_Max (0x1UL)       /*!< Max enumerator value of DEVMISS field.                               */
66129   #define RADIO_INTENSET00_DEVMISS_Set (0x1UL)       /*!< Enable                                                               */
66130   #define RADIO_INTENSET00_DEVMISS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66131   #define RADIO_INTENSET00_DEVMISS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66132 
66133 /* CRCOK @Bit 11 : Write '1' to enable interrupt for event CRCOK */
66134   #define RADIO_INTENSET00_CRCOK_Pos (11UL)          /*!< Position of CRCOK field.                                             */
66135   #define RADIO_INTENSET00_CRCOK_Msk (0x1UL << RADIO_INTENSET00_CRCOK_Pos) /*!< Bit mask of CRCOK field.                       */
66136   #define RADIO_INTENSET00_CRCOK_Min (0x0UL)         /*!< Min enumerator value of CRCOK field.                                 */
66137   #define RADIO_INTENSET00_CRCOK_Max (0x1UL)         /*!< Max enumerator value of CRCOK field.                                 */
66138   #define RADIO_INTENSET00_CRCOK_Set (0x1UL)         /*!< Enable                                                               */
66139   #define RADIO_INTENSET00_CRCOK_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66140   #define RADIO_INTENSET00_CRCOK_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66141 
66142 /* CRCERROR @Bit 12 : Write '1' to enable interrupt for event CRCERROR */
66143   #define RADIO_INTENSET00_CRCERROR_Pos (12UL)       /*!< Position of CRCERROR field.                                          */
66144   #define RADIO_INTENSET00_CRCERROR_Msk (0x1UL << RADIO_INTENSET00_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.              */
66145   #define RADIO_INTENSET00_CRCERROR_Min (0x0UL)      /*!< Min enumerator value of CRCERROR field.                              */
66146   #define RADIO_INTENSET00_CRCERROR_Max (0x1UL)      /*!< Max enumerator value of CRCERROR field.                              */
66147   #define RADIO_INTENSET00_CRCERROR_Set (0x1UL)      /*!< Enable                                                               */
66148   #define RADIO_INTENSET00_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66149   #define RADIO_INTENSET00_CRCERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66150 
66151 /* BCMATCH @Bit 14 : Write '1' to enable interrupt for event BCMATCH */
66152   #define RADIO_INTENSET00_BCMATCH_Pos (14UL)        /*!< Position of BCMATCH field.                                           */
66153   #define RADIO_INTENSET00_BCMATCH_Msk (0x1UL << RADIO_INTENSET00_BCMATCH_Pos) /*!< Bit mask of BCMATCH field.                 */
66154   #define RADIO_INTENSET00_BCMATCH_Min (0x0UL)       /*!< Min enumerator value of BCMATCH field.                               */
66155   #define RADIO_INTENSET00_BCMATCH_Max (0x1UL)       /*!< Max enumerator value of BCMATCH field.                               */
66156   #define RADIO_INTENSET00_BCMATCH_Set (0x1UL)       /*!< Enable                                                               */
66157   #define RADIO_INTENSET00_BCMATCH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66158   #define RADIO_INTENSET00_BCMATCH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66159 
66160 /* EDEND @Bit 15 : Write '1' to enable interrupt for event EDEND */
66161   #define RADIO_INTENSET00_EDEND_Pos (15UL)          /*!< Position of EDEND field.                                             */
66162   #define RADIO_INTENSET00_EDEND_Msk (0x1UL << RADIO_INTENSET00_EDEND_Pos) /*!< Bit mask of EDEND field.                       */
66163   #define RADIO_INTENSET00_EDEND_Min (0x0UL)         /*!< Min enumerator value of EDEND field.                                 */
66164   #define RADIO_INTENSET00_EDEND_Max (0x1UL)         /*!< Max enumerator value of EDEND field.                                 */
66165   #define RADIO_INTENSET00_EDEND_Set (0x1UL)         /*!< Enable                                                               */
66166   #define RADIO_INTENSET00_EDEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66167   #define RADIO_INTENSET00_EDEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66168 
66169 /* EDSTOPPED @Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
66170   #define RADIO_INTENSET00_EDSTOPPED_Pos (16UL)      /*!< Position of EDSTOPPED field.                                         */
66171   #define RADIO_INTENSET00_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET00_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field.           */
66172   #define RADIO_INTENSET00_EDSTOPPED_Min (0x0UL)     /*!< Min enumerator value of EDSTOPPED field.                             */
66173   #define RADIO_INTENSET00_EDSTOPPED_Max (0x1UL)     /*!< Max enumerator value of EDSTOPPED field.                             */
66174   #define RADIO_INTENSET00_EDSTOPPED_Set (0x1UL)     /*!< Enable                                                               */
66175   #define RADIO_INTENSET00_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                      */
66176   #define RADIO_INTENSET00_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                        */
66177 
66178 /* CCAIDLE @Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
66179   #define RADIO_INTENSET00_CCAIDLE_Pos (17UL)        /*!< Position of CCAIDLE field.                                           */
66180   #define RADIO_INTENSET00_CCAIDLE_Msk (0x1UL << RADIO_INTENSET00_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field.                 */
66181   #define RADIO_INTENSET00_CCAIDLE_Min (0x0UL)       /*!< Min enumerator value of CCAIDLE field.                               */
66182   #define RADIO_INTENSET00_CCAIDLE_Max (0x1UL)       /*!< Max enumerator value of CCAIDLE field.                               */
66183   #define RADIO_INTENSET00_CCAIDLE_Set (0x1UL)       /*!< Enable                                                               */
66184   #define RADIO_INTENSET00_CCAIDLE_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66185   #define RADIO_INTENSET00_CCAIDLE_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66186 
66187 /* CCABUSY @Bit 18 : Write '1' to enable interrupt for event CCABUSY */
66188   #define RADIO_INTENSET00_CCABUSY_Pos (18UL)        /*!< Position of CCABUSY field.                                           */
66189   #define RADIO_INTENSET00_CCABUSY_Msk (0x1UL << RADIO_INTENSET00_CCABUSY_Pos) /*!< Bit mask of CCABUSY field.                 */
66190   #define RADIO_INTENSET00_CCABUSY_Min (0x0UL)       /*!< Min enumerator value of CCABUSY field.                               */
66191   #define RADIO_INTENSET00_CCABUSY_Max (0x1UL)       /*!< Max enumerator value of CCABUSY field.                               */
66192   #define RADIO_INTENSET00_CCABUSY_Set (0x1UL)       /*!< Enable                                                               */
66193   #define RADIO_INTENSET00_CCABUSY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66194   #define RADIO_INTENSET00_CCABUSY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66195 
66196 /* CCASTOPPED @Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
66197   #define RADIO_INTENSET00_CCASTOPPED_Pos (19UL)     /*!< Position of CCASTOPPED field.                                        */
66198   #define RADIO_INTENSET00_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET00_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field.        */
66199   #define RADIO_INTENSET00_CCASTOPPED_Min (0x0UL)    /*!< Min enumerator value of CCASTOPPED field.                            */
66200   #define RADIO_INTENSET00_CCASTOPPED_Max (0x1UL)    /*!< Max enumerator value of CCASTOPPED field.                            */
66201   #define RADIO_INTENSET00_CCASTOPPED_Set (0x1UL)    /*!< Enable                                                               */
66202   #define RADIO_INTENSET00_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66203   #define RADIO_INTENSET00_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66204 
66205 /* RATEBOOST @Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
66206   #define RADIO_INTENSET00_RATEBOOST_Pos (20UL)      /*!< Position of RATEBOOST field.                                         */
66207   #define RADIO_INTENSET00_RATEBOOST_Msk (0x1UL << RADIO_INTENSET00_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field.           */
66208   #define RADIO_INTENSET00_RATEBOOST_Min (0x0UL)     /*!< Min enumerator value of RATEBOOST field.                             */
66209   #define RADIO_INTENSET00_RATEBOOST_Max (0x1UL)     /*!< Max enumerator value of RATEBOOST field.                             */
66210   #define RADIO_INTENSET00_RATEBOOST_Set (0x1UL)     /*!< Enable                                                               */
66211   #define RADIO_INTENSET00_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled                                                      */
66212   #define RADIO_INTENSET00_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled                                                        */
66213 
66214 /* MHRMATCH @Bit 21 : Write '1' to enable interrupt for event MHRMATCH */
66215   #define RADIO_INTENSET00_MHRMATCH_Pos (21UL)       /*!< Position of MHRMATCH field.                                          */
66216   #define RADIO_INTENSET00_MHRMATCH_Msk (0x1UL << RADIO_INTENSET00_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field.              */
66217   #define RADIO_INTENSET00_MHRMATCH_Min (0x0UL)      /*!< Min enumerator value of MHRMATCH field.                              */
66218   #define RADIO_INTENSET00_MHRMATCH_Max (0x1UL)      /*!< Max enumerator value of MHRMATCH field.                              */
66219   #define RADIO_INTENSET00_MHRMATCH_Set (0x1UL)      /*!< Enable                                                               */
66220   #define RADIO_INTENSET00_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66221   #define RADIO_INTENSET00_MHRMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66222 
66223 /* SYNC @Bit 22 : Write '1' to enable interrupt for event SYNC */
66224   #define RADIO_INTENSET00_SYNC_Pos (22UL)           /*!< Position of SYNC field.                                              */
66225   #define RADIO_INTENSET00_SYNC_Msk (0x1UL << RADIO_INTENSET00_SYNC_Pos) /*!< Bit mask of SYNC field.                          */
66226   #define RADIO_INTENSET00_SYNC_Min (0x0UL)          /*!< Min enumerator value of SYNC field.                                  */
66227   #define RADIO_INTENSET00_SYNC_Max (0x1UL)          /*!< Max enumerator value of SYNC field.                                  */
66228   #define RADIO_INTENSET00_SYNC_Set (0x1UL)          /*!< Enable                                                               */
66229   #define RADIO_INTENSET00_SYNC_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
66230   #define RADIO_INTENSET00_SYNC_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
66231 
66232 /* CTEPRESENT @Bit 23 : Write '1' to enable interrupt for event CTEPRESENT */
66233   #define RADIO_INTENSET00_CTEPRESENT_Pos (23UL)     /*!< Position of CTEPRESENT field.                                        */
66234   #define RADIO_INTENSET00_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET00_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field.        */
66235   #define RADIO_INTENSET00_CTEPRESENT_Min (0x0UL)    /*!< Min enumerator value of CTEPRESENT field.                            */
66236   #define RADIO_INTENSET00_CTEPRESENT_Max (0x1UL)    /*!< Max enumerator value of CTEPRESENT field.                            */
66237   #define RADIO_INTENSET00_CTEPRESENT_Set (0x1UL)    /*!< Enable                                                               */
66238   #define RADIO_INTENSET00_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66239   #define RADIO_INTENSET00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66240 
66241 
66242 /* RADIO_INTENCLR00: Disable interrupt */
66243   #define RADIO_INTENCLR00_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR00 register.                                  */
66244 
66245 /* READY @Bit 0 : Write '1' to disable interrupt for event READY */
66246   #define RADIO_INTENCLR00_READY_Pos (0UL)           /*!< Position of READY field.                                             */
66247   #define RADIO_INTENCLR00_READY_Msk (0x1UL << RADIO_INTENCLR00_READY_Pos) /*!< Bit mask of READY field.                       */
66248   #define RADIO_INTENCLR00_READY_Min (0x0UL)         /*!< Min enumerator value of READY field.                                 */
66249   #define RADIO_INTENCLR00_READY_Max (0x1UL)         /*!< Max enumerator value of READY field.                                 */
66250   #define RADIO_INTENCLR00_READY_Clear (0x1UL)       /*!< Disable                                                              */
66251   #define RADIO_INTENCLR00_READY_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66252   #define RADIO_INTENCLR00_READY_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66253 
66254 /* TXREADY @Bit 1 : Write '1' to disable interrupt for event TXREADY */
66255   #define RADIO_INTENCLR00_TXREADY_Pos (1UL)         /*!< Position of TXREADY field.                                           */
66256   #define RADIO_INTENCLR00_TXREADY_Msk (0x1UL << RADIO_INTENCLR00_TXREADY_Pos) /*!< Bit mask of TXREADY field.                 */
66257   #define RADIO_INTENCLR00_TXREADY_Min (0x0UL)       /*!< Min enumerator value of TXREADY field.                               */
66258   #define RADIO_INTENCLR00_TXREADY_Max (0x1UL)       /*!< Max enumerator value of TXREADY field.                               */
66259   #define RADIO_INTENCLR00_TXREADY_Clear (0x1UL)     /*!< Disable                                                              */
66260   #define RADIO_INTENCLR00_TXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66261   #define RADIO_INTENCLR00_TXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66262 
66263 /* RXREADY @Bit 2 : Write '1' to disable interrupt for event RXREADY */
66264   #define RADIO_INTENCLR00_RXREADY_Pos (2UL)         /*!< Position of RXREADY field.                                           */
66265   #define RADIO_INTENCLR00_RXREADY_Msk (0x1UL << RADIO_INTENCLR00_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
66266   #define RADIO_INTENCLR00_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
66267   #define RADIO_INTENCLR00_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
66268   #define RADIO_INTENCLR00_RXREADY_Clear (0x1UL)     /*!< Disable                                                              */
66269   #define RADIO_INTENCLR00_RXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66270   #define RADIO_INTENCLR00_RXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66271 
66272 /* ADDRESS @Bit 3 : Write '1' to disable interrupt for event ADDRESS */
66273   #define RADIO_INTENCLR00_ADDRESS_Pos (3UL)         /*!< Position of ADDRESS field.                                           */
66274   #define RADIO_INTENCLR00_ADDRESS_Msk (0x1UL << RADIO_INTENCLR00_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                 */
66275   #define RADIO_INTENCLR00_ADDRESS_Min (0x0UL)       /*!< Min enumerator value of ADDRESS field.                               */
66276   #define RADIO_INTENCLR00_ADDRESS_Max (0x1UL)       /*!< Max enumerator value of ADDRESS field.                               */
66277   #define RADIO_INTENCLR00_ADDRESS_Clear (0x1UL)     /*!< Disable                                                              */
66278   #define RADIO_INTENCLR00_ADDRESS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66279   #define RADIO_INTENCLR00_ADDRESS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66280 
66281 /* FRAMESTART @Bit 4 : Write '1' to disable interrupt for event FRAMESTART */
66282   #define RADIO_INTENCLR00_FRAMESTART_Pos (4UL)      /*!< Position of FRAMESTART field.                                        */
66283   #define RADIO_INTENCLR00_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR00_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.        */
66284   #define RADIO_INTENCLR00_FRAMESTART_Min (0x0UL)    /*!< Min enumerator value of FRAMESTART field.                            */
66285   #define RADIO_INTENCLR00_FRAMESTART_Max (0x1UL)    /*!< Max enumerator value of FRAMESTART field.                            */
66286   #define RADIO_INTENCLR00_FRAMESTART_Clear (0x1UL)  /*!< Disable                                                              */
66287   #define RADIO_INTENCLR00_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66288   #define RADIO_INTENCLR00_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66289 
66290 /* PAYLOAD @Bit 5 : Write '1' to disable interrupt for event PAYLOAD */
66291   #define RADIO_INTENCLR00_PAYLOAD_Pos (5UL)         /*!< Position of PAYLOAD field.                                           */
66292   #define RADIO_INTENCLR00_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR00_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field.                 */
66293   #define RADIO_INTENCLR00_PAYLOAD_Min (0x0UL)       /*!< Min enumerator value of PAYLOAD field.                               */
66294   #define RADIO_INTENCLR00_PAYLOAD_Max (0x1UL)       /*!< Max enumerator value of PAYLOAD field.                               */
66295   #define RADIO_INTENCLR00_PAYLOAD_Clear (0x1UL)     /*!< Disable                                                              */
66296   #define RADIO_INTENCLR00_PAYLOAD_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66297   #define RADIO_INTENCLR00_PAYLOAD_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66298 
66299 /* END @Bit 6 : Write '1' to disable interrupt for event END */
66300   #define RADIO_INTENCLR00_END_Pos (6UL)             /*!< Position of END field.                                               */
66301   #define RADIO_INTENCLR00_END_Msk (0x1UL << RADIO_INTENCLR00_END_Pos) /*!< Bit mask of END field.                             */
66302   #define RADIO_INTENCLR00_END_Min (0x0UL)           /*!< Min enumerator value of END field.                                   */
66303   #define RADIO_INTENCLR00_END_Max (0x1UL)           /*!< Max enumerator value of END field.                                   */
66304   #define RADIO_INTENCLR00_END_Clear (0x1UL)         /*!< Disable                                                              */
66305   #define RADIO_INTENCLR00_END_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
66306   #define RADIO_INTENCLR00_END_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
66307 
66308 /* PHYEND @Bit 7 : Write '1' to disable interrupt for event PHYEND */
66309   #define RADIO_INTENCLR00_PHYEND_Pos (7UL)          /*!< Position of PHYEND field.                                            */
66310   #define RADIO_INTENCLR00_PHYEND_Msk (0x1UL << RADIO_INTENCLR00_PHYEND_Pos) /*!< Bit mask of PHYEND field.                    */
66311   #define RADIO_INTENCLR00_PHYEND_Min (0x0UL)        /*!< Min enumerator value of PHYEND field.                                */
66312   #define RADIO_INTENCLR00_PHYEND_Max (0x1UL)        /*!< Max enumerator value of PHYEND field.                                */
66313   #define RADIO_INTENCLR00_PHYEND_Clear (0x1UL)      /*!< Disable                                                              */
66314   #define RADIO_INTENCLR00_PHYEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
66315   #define RADIO_INTENCLR00_PHYEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
66316 
66317 /* DISABLED @Bit 8 : Write '1' to disable interrupt for event DISABLED */
66318   #define RADIO_INTENCLR00_DISABLED_Pos (8UL)        /*!< Position of DISABLED field.                                          */
66319   #define RADIO_INTENCLR00_DISABLED_Msk (0x1UL << RADIO_INTENCLR00_DISABLED_Pos) /*!< Bit mask of DISABLED field.              */
66320   #define RADIO_INTENCLR00_DISABLED_Min (0x0UL)      /*!< Min enumerator value of DISABLED field.                              */
66321   #define RADIO_INTENCLR00_DISABLED_Max (0x1UL)      /*!< Max enumerator value of DISABLED field.                              */
66322   #define RADIO_INTENCLR00_DISABLED_Clear (0x1UL)    /*!< Disable                                                              */
66323   #define RADIO_INTENCLR00_DISABLED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66324   #define RADIO_INTENCLR00_DISABLED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66325 
66326 /* DEVMATCH @Bit 9 : Write '1' to disable interrupt for event DEVMATCH */
66327   #define RADIO_INTENCLR00_DEVMATCH_Pos (9UL)        /*!< Position of DEVMATCH field.                                          */
66328   #define RADIO_INTENCLR00_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR00_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field.              */
66329   #define RADIO_INTENCLR00_DEVMATCH_Min (0x0UL)      /*!< Min enumerator value of DEVMATCH field.                              */
66330   #define RADIO_INTENCLR00_DEVMATCH_Max (0x1UL)      /*!< Max enumerator value of DEVMATCH field.                              */
66331   #define RADIO_INTENCLR00_DEVMATCH_Clear (0x1UL)    /*!< Disable                                                              */
66332   #define RADIO_INTENCLR00_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66333   #define RADIO_INTENCLR00_DEVMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66334 
66335 /* DEVMISS @Bit 10 : Write '1' to disable interrupt for event DEVMISS */
66336   #define RADIO_INTENCLR00_DEVMISS_Pos (10UL)        /*!< Position of DEVMISS field.                                           */
66337   #define RADIO_INTENCLR00_DEVMISS_Msk (0x1UL << RADIO_INTENCLR00_DEVMISS_Pos) /*!< Bit mask of DEVMISS field.                 */
66338   #define RADIO_INTENCLR00_DEVMISS_Min (0x0UL)       /*!< Min enumerator value of DEVMISS field.                               */
66339   #define RADIO_INTENCLR00_DEVMISS_Max (0x1UL)       /*!< Max enumerator value of DEVMISS field.                               */
66340   #define RADIO_INTENCLR00_DEVMISS_Clear (0x1UL)     /*!< Disable                                                              */
66341   #define RADIO_INTENCLR00_DEVMISS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66342   #define RADIO_INTENCLR00_DEVMISS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66343 
66344 /* CRCOK @Bit 11 : Write '1' to disable interrupt for event CRCOK */
66345   #define RADIO_INTENCLR00_CRCOK_Pos (11UL)          /*!< Position of CRCOK field.                                             */
66346   #define RADIO_INTENCLR00_CRCOK_Msk (0x1UL << RADIO_INTENCLR00_CRCOK_Pos) /*!< Bit mask of CRCOK field.                       */
66347   #define RADIO_INTENCLR00_CRCOK_Min (0x0UL)         /*!< Min enumerator value of CRCOK field.                                 */
66348   #define RADIO_INTENCLR00_CRCOK_Max (0x1UL)         /*!< Max enumerator value of CRCOK field.                                 */
66349   #define RADIO_INTENCLR00_CRCOK_Clear (0x1UL)       /*!< Disable                                                              */
66350   #define RADIO_INTENCLR00_CRCOK_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66351   #define RADIO_INTENCLR00_CRCOK_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66352 
66353 /* CRCERROR @Bit 12 : Write '1' to disable interrupt for event CRCERROR */
66354   #define RADIO_INTENCLR00_CRCERROR_Pos (12UL)       /*!< Position of CRCERROR field.                                          */
66355   #define RADIO_INTENCLR00_CRCERROR_Msk (0x1UL << RADIO_INTENCLR00_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.              */
66356   #define RADIO_INTENCLR00_CRCERROR_Min (0x0UL)      /*!< Min enumerator value of CRCERROR field.                              */
66357   #define RADIO_INTENCLR00_CRCERROR_Max (0x1UL)      /*!< Max enumerator value of CRCERROR field.                              */
66358   #define RADIO_INTENCLR00_CRCERROR_Clear (0x1UL)    /*!< Disable                                                              */
66359   #define RADIO_INTENCLR00_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66360   #define RADIO_INTENCLR00_CRCERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66361 
66362 /* BCMATCH @Bit 14 : Write '1' to disable interrupt for event BCMATCH */
66363   #define RADIO_INTENCLR00_BCMATCH_Pos (14UL)        /*!< Position of BCMATCH field.                                           */
66364   #define RADIO_INTENCLR00_BCMATCH_Msk (0x1UL << RADIO_INTENCLR00_BCMATCH_Pos) /*!< Bit mask of BCMATCH field.                 */
66365   #define RADIO_INTENCLR00_BCMATCH_Min (0x0UL)       /*!< Min enumerator value of BCMATCH field.                               */
66366   #define RADIO_INTENCLR00_BCMATCH_Max (0x1UL)       /*!< Max enumerator value of BCMATCH field.                               */
66367   #define RADIO_INTENCLR00_BCMATCH_Clear (0x1UL)     /*!< Disable                                                              */
66368   #define RADIO_INTENCLR00_BCMATCH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66369   #define RADIO_INTENCLR00_BCMATCH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66370 
66371 /* EDEND @Bit 15 : Write '1' to disable interrupt for event EDEND */
66372   #define RADIO_INTENCLR00_EDEND_Pos (15UL)          /*!< Position of EDEND field.                                             */
66373   #define RADIO_INTENCLR00_EDEND_Msk (0x1UL << RADIO_INTENCLR00_EDEND_Pos) /*!< Bit mask of EDEND field.                       */
66374   #define RADIO_INTENCLR00_EDEND_Min (0x0UL)         /*!< Min enumerator value of EDEND field.                                 */
66375   #define RADIO_INTENCLR00_EDEND_Max (0x1UL)         /*!< Max enumerator value of EDEND field.                                 */
66376   #define RADIO_INTENCLR00_EDEND_Clear (0x1UL)       /*!< Disable                                                              */
66377   #define RADIO_INTENCLR00_EDEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66378   #define RADIO_INTENCLR00_EDEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66379 
66380 /* EDSTOPPED @Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
66381   #define RADIO_INTENCLR00_EDSTOPPED_Pos (16UL)      /*!< Position of EDSTOPPED field.                                         */
66382   #define RADIO_INTENCLR00_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR00_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field.           */
66383   #define RADIO_INTENCLR00_EDSTOPPED_Min (0x0UL)     /*!< Min enumerator value of EDSTOPPED field.                             */
66384   #define RADIO_INTENCLR00_EDSTOPPED_Max (0x1UL)     /*!< Max enumerator value of EDSTOPPED field.                             */
66385   #define RADIO_INTENCLR00_EDSTOPPED_Clear (0x1UL)   /*!< Disable                                                              */
66386   #define RADIO_INTENCLR00_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                      */
66387   #define RADIO_INTENCLR00_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                        */
66388 
66389 /* CCAIDLE @Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
66390   #define RADIO_INTENCLR00_CCAIDLE_Pos (17UL)        /*!< Position of CCAIDLE field.                                           */
66391   #define RADIO_INTENCLR00_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR00_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field.                 */
66392   #define RADIO_INTENCLR00_CCAIDLE_Min (0x0UL)       /*!< Min enumerator value of CCAIDLE field.                               */
66393   #define RADIO_INTENCLR00_CCAIDLE_Max (0x1UL)       /*!< Max enumerator value of CCAIDLE field.                               */
66394   #define RADIO_INTENCLR00_CCAIDLE_Clear (0x1UL)     /*!< Disable                                                              */
66395   #define RADIO_INTENCLR00_CCAIDLE_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66396   #define RADIO_INTENCLR00_CCAIDLE_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66397 
66398 /* CCABUSY @Bit 18 : Write '1' to disable interrupt for event CCABUSY */
66399   #define RADIO_INTENCLR00_CCABUSY_Pos (18UL)        /*!< Position of CCABUSY field.                                           */
66400   #define RADIO_INTENCLR00_CCABUSY_Msk (0x1UL << RADIO_INTENCLR00_CCABUSY_Pos) /*!< Bit mask of CCABUSY field.                 */
66401   #define RADIO_INTENCLR00_CCABUSY_Min (0x0UL)       /*!< Min enumerator value of CCABUSY field.                               */
66402   #define RADIO_INTENCLR00_CCABUSY_Max (0x1UL)       /*!< Max enumerator value of CCABUSY field.                               */
66403   #define RADIO_INTENCLR00_CCABUSY_Clear (0x1UL)     /*!< Disable                                                              */
66404   #define RADIO_INTENCLR00_CCABUSY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66405   #define RADIO_INTENCLR00_CCABUSY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66406 
66407 /* CCASTOPPED @Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
66408   #define RADIO_INTENCLR00_CCASTOPPED_Pos (19UL)     /*!< Position of CCASTOPPED field.                                        */
66409   #define RADIO_INTENCLR00_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR00_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field.        */
66410   #define RADIO_INTENCLR00_CCASTOPPED_Min (0x0UL)    /*!< Min enumerator value of CCASTOPPED field.                            */
66411   #define RADIO_INTENCLR00_CCASTOPPED_Max (0x1UL)    /*!< Max enumerator value of CCASTOPPED field.                            */
66412   #define RADIO_INTENCLR00_CCASTOPPED_Clear (0x1UL)  /*!< Disable                                                              */
66413   #define RADIO_INTENCLR00_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66414   #define RADIO_INTENCLR00_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66415 
66416 /* RATEBOOST @Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
66417   #define RADIO_INTENCLR00_RATEBOOST_Pos (20UL)      /*!< Position of RATEBOOST field.                                         */
66418   #define RADIO_INTENCLR00_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR00_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field.           */
66419   #define RADIO_INTENCLR00_RATEBOOST_Min (0x0UL)     /*!< Min enumerator value of RATEBOOST field.                             */
66420   #define RADIO_INTENCLR00_RATEBOOST_Max (0x1UL)     /*!< Max enumerator value of RATEBOOST field.                             */
66421   #define RADIO_INTENCLR00_RATEBOOST_Clear (0x1UL)   /*!< Disable                                                              */
66422   #define RADIO_INTENCLR00_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled                                                      */
66423   #define RADIO_INTENCLR00_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled                                                        */
66424 
66425 /* MHRMATCH @Bit 21 : Write '1' to disable interrupt for event MHRMATCH */
66426   #define RADIO_INTENCLR00_MHRMATCH_Pos (21UL)       /*!< Position of MHRMATCH field.                                          */
66427   #define RADIO_INTENCLR00_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR00_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field.              */
66428   #define RADIO_INTENCLR00_MHRMATCH_Min (0x0UL)      /*!< Min enumerator value of MHRMATCH field.                              */
66429   #define RADIO_INTENCLR00_MHRMATCH_Max (0x1UL)      /*!< Max enumerator value of MHRMATCH field.                              */
66430   #define RADIO_INTENCLR00_MHRMATCH_Clear (0x1UL)    /*!< Disable                                                              */
66431   #define RADIO_INTENCLR00_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66432   #define RADIO_INTENCLR00_MHRMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66433 
66434 /* SYNC @Bit 22 : Write '1' to disable interrupt for event SYNC */
66435   #define RADIO_INTENCLR00_SYNC_Pos (22UL)           /*!< Position of SYNC field.                                              */
66436   #define RADIO_INTENCLR00_SYNC_Msk (0x1UL << RADIO_INTENCLR00_SYNC_Pos) /*!< Bit mask of SYNC field.                          */
66437   #define RADIO_INTENCLR00_SYNC_Min (0x0UL)          /*!< Min enumerator value of SYNC field.                                  */
66438   #define RADIO_INTENCLR00_SYNC_Max (0x1UL)          /*!< Max enumerator value of SYNC field.                                  */
66439   #define RADIO_INTENCLR00_SYNC_Clear (0x1UL)        /*!< Disable                                                              */
66440   #define RADIO_INTENCLR00_SYNC_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
66441   #define RADIO_INTENCLR00_SYNC_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
66442 
66443 /* CTEPRESENT @Bit 23 : Write '1' to disable interrupt for event CTEPRESENT */
66444   #define RADIO_INTENCLR00_CTEPRESENT_Pos (23UL)     /*!< Position of CTEPRESENT field.                                        */
66445   #define RADIO_INTENCLR00_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR00_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field.        */
66446   #define RADIO_INTENCLR00_CTEPRESENT_Min (0x0UL)    /*!< Min enumerator value of CTEPRESENT field.                            */
66447   #define RADIO_INTENCLR00_CTEPRESENT_Max (0x1UL)    /*!< Max enumerator value of CTEPRESENT field.                            */
66448   #define RADIO_INTENCLR00_CTEPRESENT_Clear (0x1UL)  /*!< Disable                                                              */
66449   #define RADIO_INTENCLR00_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66450   #define RADIO_INTENCLR00_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66451 
66452 
66453 /* RADIO_INTENSET10: Enable interrupt */
66454   #define RADIO_INTENSET10_ResetValue (0x00000000UL) /*!< Reset value of INTENSET10 register.                                  */
66455 
66456 /* READY @Bit 0 : Write '1' to enable interrupt for event READY */
66457   #define RADIO_INTENSET10_READY_Pos (0UL)           /*!< Position of READY field.                                             */
66458   #define RADIO_INTENSET10_READY_Msk (0x1UL << RADIO_INTENSET10_READY_Pos) /*!< Bit mask of READY field.                       */
66459   #define RADIO_INTENSET10_READY_Min (0x0UL)         /*!< Min enumerator value of READY field.                                 */
66460   #define RADIO_INTENSET10_READY_Max (0x1UL)         /*!< Max enumerator value of READY field.                                 */
66461   #define RADIO_INTENSET10_READY_Set (0x1UL)         /*!< Enable                                                               */
66462   #define RADIO_INTENSET10_READY_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66463   #define RADIO_INTENSET10_READY_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66464 
66465 /* TXREADY @Bit 1 : Write '1' to enable interrupt for event TXREADY */
66466   #define RADIO_INTENSET10_TXREADY_Pos (1UL)         /*!< Position of TXREADY field.                                           */
66467   #define RADIO_INTENSET10_TXREADY_Msk (0x1UL << RADIO_INTENSET10_TXREADY_Pos) /*!< Bit mask of TXREADY field.                 */
66468   #define RADIO_INTENSET10_TXREADY_Min (0x0UL)       /*!< Min enumerator value of TXREADY field.                               */
66469   #define RADIO_INTENSET10_TXREADY_Max (0x1UL)       /*!< Max enumerator value of TXREADY field.                               */
66470   #define RADIO_INTENSET10_TXREADY_Set (0x1UL)       /*!< Enable                                                               */
66471   #define RADIO_INTENSET10_TXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66472   #define RADIO_INTENSET10_TXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66473 
66474 /* RXREADY @Bit 2 : Write '1' to enable interrupt for event RXREADY */
66475   #define RADIO_INTENSET10_RXREADY_Pos (2UL)         /*!< Position of RXREADY field.                                           */
66476   #define RADIO_INTENSET10_RXREADY_Msk (0x1UL << RADIO_INTENSET10_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
66477   #define RADIO_INTENSET10_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
66478   #define RADIO_INTENSET10_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
66479   #define RADIO_INTENSET10_RXREADY_Set (0x1UL)       /*!< Enable                                                               */
66480   #define RADIO_INTENSET10_RXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66481   #define RADIO_INTENSET10_RXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66482 
66483 /* ADDRESS @Bit 3 : Write '1' to enable interrupt for event ADDRESS */
66484   #define RADIO_INTENSET10_ADDRESS_Pos (3UL)         /*!< Position of ADDRESS field.                                           */
66485   #define RADIO_INTENSET10_ADDRESS_Msk (0x1UL << RADIO_INTENSET10_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                 */
66486   #define RADIO_INTENSET10_ADDRESS_Min (0x0UL)       /*!< Min enumerator value of ADDRESS field.                               */
66487   #define RADIO_INTENSET10_ADDRESS_Max (0x1UL)       /*!< Max enumerator value of ADDRESS field.                               */
66488   #define RADIO_INTENSET10_ADDRESS_Set (0x1UL)       /*!< Enable                                                               */
66489   #define RADIO_INTENSET10_ADDRESS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66490   #define RADIO_INTENSET10_ADDRESS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66491 
66492 /* FRAMESTART @Bit 4 : Write '1' to enable interrupt for event FRAMESTART */
66493   #define RADIO_INTENSET10_FRAMESTART_Pos (4UL)      /*!< Position of FRAMESTART field.                                        */
66494   #define RADIO_INTENSET10_FRAMESTART_Msk (0x1UL << RADIO_INTENSET10_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.        */
66495   #define RADIO_INTENSET10_FRAMESTART_Min (0x0UL)    /*!< Min enumerator value of FRAMESTART field.                            */
66496   #define RADIO_INTENSET10_FRAMESTART_Max (0x1UL)    /*!< Max enumerator value of FRAMESTART field.                            */
66497   #define RADIO_INTENSET10_FRAMESTART_Set (0x1UL)    /*!< Enable                                                               */
66498   #define RADIO_INTENSET10_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66499   #define RADIO_INTENSET10_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66500 
66501 /* PAYLOAD @Bit 5 : Write '1' to enable interrupt for event PAYLOAD */
66502   #define RADIO_INTENSET10_PAYLOAD_Pos (5UL)         /*!< Position of PAYLOAD field.                                           */
66503   #define RADIO_INTENSET10_PAYLOAD_Msk (0x1UL << RADIO_INTENSET10_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field.                 */
66504   #define RADIO_INTENSET10_PAYLOAD_Min (0x0UL)       /*!< Min enumerator value of PAYLOAD field.                               */
66505   #define RADIO_INTENSET10_PAYLOAD_Max (0x1UL)       /*!< Max enumerator value of PAYLOAD field.                               */
66506   #define RADIO_INTENSET10_PAYLOAD_Set (0x1UL)       /*!< Enable                                                               */
66507   #define RADIO_INTENSET10_PAYLOAD_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66508   #define RADIO_INTENSET10_PAYLOAD_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66509 
66510 /* END @Bit 6 : Write '1' to enable interrupt for event END */
66511   #define RADIO_INTENSET10_END_Pos (6UL)             /*!< Position of END field.                                               */
66512   #define RADIO_INTENSET10_END_Msk (0x1UL << RADIO_INTENSET10_END_Pos) /*!< Bit mask of END field.                             */
66513   #define RADIO_INTENSET10_END_Min (0x0UL)           /*!< Min enumerator value of END field.                                   */
66514   #define RADIO_INTENSET10_END_Max (0x1UL)           /*!< Max enumerator value of END field.                                   */
66515   #define RADIO_INTENSET10_END_Set (0x1UL)           /*!< Enable                                                               */
66516   #define RADIO_INTENSET10_END_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
66517   #define RADIO_INTENSET10_END_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
66518 
66519 /* PHYEND @Bit 7 : Write '1' to enable interrupt for event PHYEND */
66520   #define RADIO_INTENSET10_PHYEND_Pos (7UL)          /*!< Position of PHYEND field.                                            */
66521   #define RADIO_INTENSET10_PHYEND_Msk (0x1UL << RADIO_INTENSET10_PHYEND_Pos) /*!< Bit mask of PHYEND field.                    */
66522   #define RADIO_INTENSET10_PHYEND_Min (0x0UL)        /*!< Min enumerator value of PHYEND field.                                */
66523   #define RADIO_INTENSET10_PHYEND_Max (0x1UL)        /*!< Max enumerator value of PHYEND field.                                */
66524   #define RADIO_INTENSET10_PHYEND_Set (0x1UL)        /*!< Enable                                                               */
66525   #define RADIO_INTENSET10_PHYEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
66526   #define RADIO_INTENSET10_PHYEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
66527 
66528 /* DISABLED @Bit 8 : Write '1' to enable interrupt for event DISABLED */
66529   #define RADIO_INTENSET10_DISABLED_Pos (8UL)        /*!< Position of DISABLED field.                                          */
66530   #define RADIO_INTENSET10_DISABLED_Msk (0x1UL << RADIO_INTENSET10_DISABLED_Pos) /*!< Bit mask of DISABLED field.              */
66531   #define RADIO_INTENSET10_DISABLED_Min (0x0UL)      /*!< Min enumerator value of DISABLED field.                              */
66532   #define RADIO_INTENSET10_DISABLED_Max (0x1UL)      /*!< Max enumerator value of DISABLED field.                              */
66533   #define RADIO_INTENSET10_DISABLED_Set (0x1UL)      /*!< Enable                                                               */
66534   #define RADIO_INTENSET10_DISABLED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66535   #define RADIO_INTENSET10_DISABLED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66536 
66537 /* DEVMATCH @Bit 9 : Write '1' to enable interrupt for event DEVMATCH */
66538   #define RADIO_INTENSET10_DEVMATCH_Pos (9UL)        /*!< Position of DEVMATCH field.                                          */
66539   #define RADIO_INTENSET10_DEVMATCH_Msk (0x1UL << RADIO_INTENSET10_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field.              */
66540   #define RADIO_INTENSET10_DEVMATCH_Min (0x0UL)      /*!< Min enumerator value of DEVMATCH field.                              */
66541   #define RADIO_INTENSET10_DEVMATCH_Max (0x1UL)      /*!< Max enumerator value of DEVMATCH field.                              */
66542   #define RADIO_INTENSET10_DEVMATCH_Set (0x1UL)      /*!< Enable                                                               */
66543   #define RADIO_INTENSET10_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66544   #define RADIO_INTENSET10_DEVMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66545 
66546 /* DEVMISS @Bit 10 : Write '1' to enable interrupt for event DEVMISS */
66547   #define RADIO_INTENSET10_DEVMISS_Pos (10UL)        /*!< Position of DEVMISS field.                                           */
66548   #define RADIO_INTENSET10_DEVMISS_Msk (0x1UL << RADIO_INTENSET10_DEVMISS_Pos) /*!< Bit mask of DEVMISS field.                 */
66549   #define RADIO_INTENSET10_DEVMISS_Min (0x0UL)       /*!< Min enumerator value of DEVMISS field.                               */
66550   #define RADIO_INTENSET10_DEVMISS_Max (0x1UL)       /*!< Max enumerator value of DEVMISS field.                               */
66551   #define RADIO_INTENSET10_DEVMISS_Set (0x1UL)       /*!< Enable                                                               */
66552   #define RADIO_INTENSET10_DEVMISS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66553   #define RADIO_INTENSET10_DEVMISS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66554 
66555 /* CRCOK @Bit 11 : Write '1' to enable interrupt for event CRCOK */
66556   #define RADIO_INTENSET10_CRCOK_Pos (11UL)          /*!< Position of CRCOK field.                                             */
66557   #define RADIO_INTENSET10_CRCOK_Msk (0x1UL << RADIO_INTENSET10_CRCOK_Pos) /*!< Bit mask of CRCOK field.                       */
66558   #define RADIO_INTENSET10_CRCOK_Min (0x0UL)         /*!< Min enumerator value of CRCOK field.                                 */
66559   #define RADIO_INTENSET10_CRCOK_Max (0x1UL)         /*!< Max enumerator value of CRCOK field.                                 */
66560   #define RADIO_INTENSET10_CRCOK_Set (0x1UL)         /*!< Enable                                                               */
66561   #define RADIO_INTENSET10_CRCOK_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66562   #define RADIO_INTENSET10_CRCOK_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66563 
66564 /* CRCERROR @Bit 12 : Write '1' to enable interrupt for event CRCERROR */
66565   #define RADIO_INTENSET10_CRCERROR_Pos (12UL)       /*!< Position of CRCERROR field.                                          */
66566   #define RADIO_INTENSET10_CRCERROR_Msk (0x1UL << RADIO_INTENSET10_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.              */
66567   #define RADIO_INTENSET10_CRCERROR_Min (0x0UL)      /*!< Min enumerator value of CRCERROR field.                              */
66568   #define RADIO_INTENSET10_CRCERROR_Max (0x1UL)      /*!< Max enumerator value of CRCERROR field.                              */
66569   #define RADIO_INTENSET10_CRCERROR_Set (0x1UL)      /*!< Enable                                                               */
66570   #define RADIO_INTENSET10_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66571   #define RADIO_INTENSET10_CRCERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66572 
66573 /* BCMATCH @Bit 14 : Write '1' to enable interrupt for event BCMATCH */
66574   #define RADIO_INTENSET10_BCMATCH_Pos (14UL)        /*!< Position of BCMATCH field.                                           */
66575   #define RADIO_INTENSET10_BCMATCH_Msk (0x1UL << RADIO_INTENSET10_BCMATCH_Pos) /*!< Bit mask of BCMATCH field.                 */
66576   #define RADIO_INTENSET10_BCMATCH_Min (0x0UL)       /*!< Min enumerator value of BCMATCH field.                               */
66577   #define RADIO_INTENSET10_BCMATCH_Max (0x1UL)       /*!< Max enumerator value of BCMATCH field.                               */
66578   #define RADIO_INTENSET10_BCMATCH_Set (0x1UL)       /*!< Enable                                                               */
66579   #define RADIO_INTENSET10_BCMATCH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66580   #define RADIO_INTENSET10_BCMATCH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66581 
66582 /* EDEND @Bit 15 : Write '1' to enable interrupt for event EDEND */
66583   #define RADIO_INTENSET10_EDEND_Pos (15UL)          /*!< Position of EDEND field.                                             */
66584   #define RADIO_INTENSET10_EDEND_Msk (0x1UL << RADIO_INTENSET10_EDEND_Pos) /*!< Bit mask of EDEND field.                       */
66585   #define RADIO_INTENSET10_EDEND_Min (0x0UL)         /*!< Min enumerator value of EDEND field.                                 */
66586   #define RADIO_INTENSET10_EDEND_Max (0x1UL)         /*!< Max enumerator value of EDEND field.                                 */
66587   #define RADIO_INTENSET10_EDEND_Set (0x1UL)         /*!< Enable                                                               */
66588   #define RADIO_INTENSET10_EDEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66589   #define RADIO_INTENSET10_EDEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66590 
66591 /* EDSTOPPED @Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
66592   #define RADIO_INTENSET10_EDSTOPPED_Pos (16UL)      /*!< Position of EDSTOPPED field.                                         */
66593   #define RADIO_INTENSET10_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET10_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field.           */
66594   #define RADIO_INTENSET10_EDSTOPPED_Min (0x0UL)     /*!< Min enumerator value of EDSTOPPED field.                             */
66595   #define RADIO_INTENSET10_EDSTOPPED_Max (0x1UL)     /*!< Max enumerator value of EDSTOPPED field.                             */
66596   #define RADIO_INTENSET10_EDSTOPPED_Set (0x1UL)     /*!< Enable                                                               */
66597   #define RADIO_INTENSET10_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                      */
66598   #define RADIO_INTENSET10_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                        */
66599 
66600 /* CCAIDLE @Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
66601   #define RADIO_INTENSET10_CCAIDLE_Pos (17UL)        /*!< Position of CCAIDLE field.                                           */
66602   #define RADIO_INTENSET10_CCAIDLE_Msk (0x1UL << RADIO_INTENSET10_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field.                 */
66603   #define RADIO_INTENSET10_CCAIDLE_Min (0x0UL)       /*!< Min enumerator value of CCAIDLE field.                               */
66604   #define RADIO_INTENSET10_CCAIDLE_Max (0x1UL)       /*!< Max enumerator value of CCAIDLE field.                               */
66605   #define RADIO_INTENSET10_CCAIDLE_Set (0x1UL)       /*!< Enable                                                               */
66606   #define RADIO_INTENSET10_CCAIDLE_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66607   #define RADIO_INTENSET10_CCAIDLE_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66608 
66609 /* CCABUSY @Bit 18 : Write '1' to enable interrupt for event CCABUSY */
66610   #define RADIO_INTENSET10_CCABUSY_Pos (18UL)        /*!< Position of CCABUSY field.                                           */
66611   #define RADIO_INTENSET10_CCABUSY_Msk (0x1UL << RADIO_INTENSET10_CCABUSY_Pos) /*!< Bit mask of CCABUSY field.                 */
66612   #define RADIO_INTENSET10_CCABUSY_Min (0x0UL)       /*!< Min enumerator value of CCABUSY field.                               */
66613   #define RADIO_INTENSET10_CCABUSY_Max (0x1UL)       /*!< Max enumerator value of CCABUSY field.                               */
66614   #define RADIO_INTENSET10_CCABUSY_Set (0x1UL)       /*!< Enable                                                               */
66615   #define RADIO_INTENSET10_CCABUSY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66616   #define RADIO_INTENSET10_CCABUSY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66617 
66618 /* CCASTOPPED @Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
66619   #define RADIO_INTENSET10_CCASTOPPED_Pos (19UL)     /*!< Position of CCASTOPPED field.                                        */
66620   #define RADIO_INTENSET10_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET10_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field.        */
66621   #define RADIO_INTENSET10_CCASTOPPED_Min (0x0UL)    /*!< Min enumerator value of CCASTOPPED field.                            */
66622   #define RADIO_INTENSET10_CCASTOPPED_Max (0x1UL)    /*!< Max enumerator value of CCASTOPPED field.                            */
66623   #define RADIO_INTENSET10_CCASTOPPED_Set (0x1UL)    /*!< Enable                                                               */
66624   #define RADIO_INTENSET10_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66625   #define RADIO_INTENSET10_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66626 
66627 /* RATEBOOST @Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
66628   #define RADIO_INTENSET10_RATEBOOST_Pos (20UL)      /*!< Position of RATEBOOST field.                                         */
66629   #define RADIO_INTENSET10_RATEBOOST_Msk (0x1UL << RADIO_INTENSET10_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field.           */
66630   #define RADIO_INTENSET10_RATEBOOST_Min (0x0UL)     /*!< Min enumerator value of RATEBOOST field.                             */
66631   #define RADIO_INTENSET10_RATEBOOST_Max (0x1UL)     /*!< Max enumerator value of RATEBOOST field.                             */
66632   #define RADIO_INTENSET10_RATEBOOST_Set (0x1UL)     /*!< Enable                                                               */
66633   #define RADIO_INTENSET10_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled                                                      */
66634   #define RADIO_INTENSET10_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled                                                        */
66635 
66636 /* MHRMATCH @Bit 21 : Write '1' to enable interrupt for event MHRMATCH */
66637   #define RADIO_INTENSET10_MHRMATCH_Pos (21UL)       /*!< Position of MHRMATCH field.                                          */
66638   #define RADIO_INTENSET10_MHRMATCH_Msk (0x1UL << RADIO_INTENSET10_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field.              */
66639   #define RADIO_INTENSET10_MHRMATCH_Min (0x0UL)      /*!< Min enumerator value of MHRMATCH field.                              */
66640   #define RADIO_INTENSET10_MHRMATCH_Max (0x1UL)      /*!< Max enumerator value of MHRMATCH field.                              */
66641   #define RADIO_INTENSET10_MHRMATCH_Set (0x1UL)      /*!< Enable                                                               */
66642   #define RADIO_INTENSET10_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66643   #define RADIO_INTENSET10_MHRMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66644 
66645 /* SYNC @Bit 22 : Write '1' to enable interrupt for event SYNC */
66646   #define RADIO_INTENSET10_SYNC_Pos (22UL)           /*!< Position of SYNC field.                                              */
66647   #define RADIO_INTENSET10_SYNC_Msk (0x1UL << RADIO_INTENSET10_SYNC_Pos) /*!< Bit mask of SYNC field.                          */
66648   #define RADIO_INTENSET10_SYNC_Min (0x0UL)          /*!< Min enumerator value of SYNC field.                                  */
66649   #define RADIO_INTENSET10_SYNC_Max (0x1UL)          /*!< Max enumerator value of SYNC field.                                  */
66650   #define RADIO_INTENSET10_SYNC_Set (0x1UL)          /*!< Enable                                                               */
66651   #define RADIO_INTENSET10_SYNC_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
66652   #define RADIO_INTENSET10_SYNC_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
66653 
66654 /* CTEPRESENT @Bit 23 : Write '1' to enable interrupt for event CTEPRESENT */
66655   #define RADIO_INTENSET10_CTEPRESENT_Pos (23UL)     /*!< Position of CTEPRESENT field.                                        */
66656   #define RADIO_INTENSET10_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET10_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field.        */
66657   #define RADIO_INTENSET10_CTEPRESENT_Min (0x0UL)    /*!< Min enumerator value of CTEPRESENT field.                            */
66658   #define RADIO_INTENSET10_CTEPRESENT_Max (0x1UL)    /*!< Max enumerator value of CTEPRESENT field.                            */
66659   #define RADIO_INTENSET10_CTEPRESENT_Set (0x1UL)    /*!< Enable                                                               */
66660   #define RADIO_INTENSET10_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66661   #define RADIO_INTENSET10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66662 
66663 
66664 /* RADIO_INTENCLR10: Disable interrupt */
66665   #define RADIO_INTENCLR10_ResetValue (0x00000000UL) /*!< Reset value of INTENCLR10 register.                                  */
66666 
66667 /* READY @Bit 0 : Write '1' to disable interrupt for event READY */
66668   #define RADIO_INTENCLR10_READY_Pos (0UL)           /*!< Position of READY field.                                             */
66669   #define RADIO_INTENCLR10_READY_Msk (0x1UL << RADIO_INTENCLR10_READY_Pos) /*!< Bit mask of READY field.                       */
66670   #define RADIO_INTENCLR10_READY_Min (0x0UL)         /*!< Min enumerator value of READY field.                                 */
66671   #define RADIO_INTENCLR10_READY_Max (0x1UL)         /*!< Max enumerator value of READY field.                                 */
66672   #define RADIO_INTENCLR10_READY_Clear (0x1UL)       /*!< Disable                                                              */
66673   #define RADIO_INTENCLR10_READY_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66674   #define RADIO_INTENCLR10_READY_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66675 
66676 /* TXREADY @Bit 1 : Write '1' to disable interrupt for event TXREADY */
66677   #define RADIO_INTENCLR10_TXREADY_Pos (1UL)         /*!< Position of TXREADY field.                                           */
66678   #define RADIO_INTENCLR10_TXREADY_Msk (0x1UL << RADIO_INTENCLR10_TXREADY_Pos) /*!< Bit mask of TXREADY field.                 */
66679   #define RADIO_INTENCLR10_TXREADY_Min (0x0UL)       /*!< Min enumerator value of TXREADY field.                               */
66680   #define RADIO_INTENCLR10_TXREADY_Max (0x1UL)       /*!< Max enumerator value of TXREADY field.                               */
66681   #define RADIO_INTENCLR10_TXREADY_Clear (0x1UL)     /*!< Disable                                                              */
66682   #define RADIO_INTENCLR10_TXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66683   #define RADIO_INTENCLR10_TXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66684 
66685 /* RXREADY @Bit 2 : Write '1' to disable interrupt for event RXREADY */
66686   #define RADIO_INTENCLR10_RXREADY_Pos (2UL)         /*!< Position of RXREADY field.                                           */
66687   #define RADIO_INTENCLR10_RXREADY_Msk (0x1UL << RADIO_INTENCLR10_RXREADY_Pos) /*!< Bit mask of RXREADY field.                 */
66688   #define RADIO_INTENCLR10_RXREADY_Min (0x0UL)       /*!< Min enumerator value of RXREADY field.                               */
66689   #define RADIO_INTENCLR10_RXREADY_Max (0x1UL)       /*!< Max enumerator value of RXREADY field.                               */
66690   #define RADIO_INTENCLR10_RXREADY_Clear (0x1UL)     /*!< Disable                                                              */
66691   #define RADIO_INTENCLR10_RXREADY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66692   #define RADIO_INTENCLR10_RXREADY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66693 
66694 /* ADDRESS @Bit 3 : Write '1' to disable interrupt for event ADDRESS */
66695   #define RADIO_INTENCLR10_ADDRESS_Pos (3UL)         /*!< Position of ADDRESS field.                                           */
66696   #define RADIO_INTENCLR10_ADDRESS_Msk (0x1UL << RADIO_INTENCLR10_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                 */
66697   #define RADIO_INTENCLR10_ADDRESS_Min (0x0UL)       /*!< Min enumerator value of ADDRESS field.                               */
66698   #define RADIO_INTENCLR10_ADDRESS_Max (0x1UL)       /*!< Max enumerator value of ADDRESS field.                               */
66699   #define RADIO_INTENCLR10_ADDRESS_Clear (0x1UL)     /*!< Disable                                                              */
66700   #define RADIO_INTENCLR10_ADDRESS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66701   #define RADIO_INTENCLR10_ADDRESS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66702 
66703 /* FRAMESTART @Bit 4 : Write '1' to disable interrupt for event FRAMESTART */
66704   #define RADIO_INTENCLR10_FRAMESTART_Pos (4UL)      /*!< Position of FRAMESTART field.                                        */
66705   #define RADIO_INTENCLR10_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR10_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field.        */
66706   #define RADIO_INTENCLR10_FRAMESTART_Min (0x0UL)    /*!< Min enumerator value of FRAMESTART field.                            */
66707   #define RADIO_INTENCLR10_FRAMESTART_Max (0x1UL)    /*!< Max enumerator value of FRAMESTART field.                            */
66708   #define RADIO_INTENCLR10_FRAMESTART_Clear (0x1UL)  /*!< Disable                                                              */
66709   #define RADIO_INTENCLR10_FRAMESTART_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66710   #define RADIO_INTENCLR10_FRAMESTART_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66711 
66712 /* PAYLOAD @Bit 5 : Write '1' to disable interrupt for event PAYLOAD */
66713   #define RADIO_INTENCLR10_PAYLOAD_Pos (5UL)         /*!< Position of PAYLOAD field.                                           */
66714   #define RADIO_INTENCLR10_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR10_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field.                 */
66715   #define RADIO_INTENCLR10_PAYLOAD_Min (0x0UL)       /*!< Min enumerator value of PAYLOAD field.                               */
66716   #define RADIO_INTENCLR10_PAYLOAD_Max (0x1UL)       /*!< Max enumerator value of PAYLOAD field.                               */
66717   #define RADIO_INTENCLR10_PAYLOAD_Clear (0x1UL)     /*!< Disable                                                              */
66718   #define RADIO_INTENCLR10_PAYLOAD_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66719   #define RADIO_INTENCLR10_PAYLOAD_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66720 
66721 /* END @Bit 6 : Write '1' to disable interrupt for event END */
66722   #define RADIO_INTENCLR10_END_Pos (6UL)             /*!< Position of END field.                                               */
66723   #define RADIO_INTENCLR10_END_Msk (0x1UL << RADIO_INTENCLR10_END_Pos) /*!< Bit mask of END field.                             */
66724   #define RADIO_INTENCLR10_END_Min (0x0UL)           /*!< Min enumerator value of END field.                                   */
66725   #define RADIO_INTENCLR10_END_Max (0x1UL)           /*!< Max enumerator value of END field.                                   */
66726   #define RADIO_INTENCLR10_END_Clear (0x1UL)         /*!< Disable                                                              */
66727   #define RADIO_INTENCLR10_END_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
66728   #define RADIO_INTENCLR10_END_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
66729 
66730 /* PHYEND @Bit 7 : Write '1' to disable interrupt for event PHYEND */
66731   #define RADIO_INTENCLR10_PHYEND_Pos (7UL)          /*!< Position of PHYEND field.                                            */
66732   #define RADIO_INTENCLR10_PHYEND_Msk (0x1UL << RADIO_INTENCLR10_PHYEND_Pos) /*!< Bit mask of PHYEND field.                    */
66733   #define RADIO_INTENCLR10_PHYEND_Min (0x0UL)        /*!< Min enumerator value of PHYEND field.                                */
66734   #define RADIO_INTENCLR10_PHYEND_Max (0x1UL)        /*!< Max enumerator value of PHYEND field.                                */
66735   #define RADIO_INTENCLR10_PHYEND_Clear (0x1UL)      /*!< Disable                                                              */
66736   #define RADIO_INTENCLR10_PHYEND_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
66737   #define RADIO_INTENCLR10_PHYEND_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
66738 
66739 /* DISABLED @Bit 8 : Write '1' to disable interrupt for event DISABLED */
66740   #define RADIO_INTENCLR10_DISABLED_Pos (8UL)        /*!< Position of DISABLED field.                                          */
66741   #define RADIO_INTENCLR10_DISABLED_Msk (0x1UL << RADIO_INTENCLR10_DISABLED_Pos) /*!< Bit mask of DISABLED field.              */
66742   #define RADIO_INTENCLR10_DISABLED_Min (0x0UL)      /*!< Min enumerator value of DISABLED field.                              */
66743   #define RADIO_INTENCLR10_DISABLED_Max (0x1UL)      /*!< Max enumerator value of DISABLED field.                              */
66744   #define RADIO_INTENCLR10_DISABLED_Clear (0x1UL)    /*!< Disable                                                              */
66745   #define RADIO_INTENCLR10_DISABLED_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66746   #define RADIO_INTENCLR10_DISABLED_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66747 
66748 /* DEVMATCH @Bit 9 : Write '1' to disable interrupt for event DEVMATCH */
66749   #define RADIO_INTENCLR10_DEVMATCH_Pos (9UL)        /*!< Position of DEVMATCH field.                                          */
66750   #define RADIO_INTENCLR10_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR10_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field.              */
66751   #define RADIO_INTENCLR10_DEVMATCH_Min (0x0UL)      /*!< Min enumerator value of DEVMATCH field.                              */
66752   #define RADIO_INTENCLR10_DEVMATCH_Max (0x1UL)      /*!< Max enumerator value of DEVMATCH field.                              */
66753   #define RADIO_INTENCLR10_DEVMATCH_Clear (0x1UL)    /*!< Disable                                                              */
66754   #define RADIO_INTENCLR10_DEVMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66755   #define RADIO_INTENCLR10_DEVMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66756 
66757 /* DEVMISS @Bit 10 : Write '1' to disable interrupt for event DEVMISS */
66758   #define RADIO_INTENCLR10_DEVMISS_Pos (10UL)        /*!< Position of DEVMISS field.                                           */
66759   #define RADIO_INTENCLR10_DEVMISS_Msk (0x1UL << RADIO_INTENCLR10_DEVMISS_Pos) /*!< Bit mask of DEVMISS field.                 */
66760   #define RADIO_INTENCLR10_DEVMISS_Min (0x0UL)       /*!< Min enumerator value of DEVMISS field.                               */
66761   #define RADIO_INTENCLR10_DEVMISS_Max (0x1UL)       /*!< Max enumerator value of DEVMISS field.                               */
66762   #define RADIO_INTENCLR10_DEVMISS_Clear (0x1UL)     /*!< Disable                                                              */
66763   #define RADIO_INTENCLR10_DEVMISS_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66764   #define RADIO_INTENCLR10_DEVMISS_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66765 
66766 /* CRCOK @Bit 11 : Write '1' to disable interrupt for event CRCOK */
66767   #define RADIO_INTENCLR10_CRCOK_Pos (11UL)          /*!< Position of CRCOK field.                                             */
66768   #define RADIO_INTENCLR10_CRCOK_Msk (0x1UL << RADIO_INTENCLR10_CRCOK_Pos) /*!< Bit mask of CRCOK field.                       */
66769   #define RADIO_INTENCLR10_CRCOK_Min (0x0UL)         /*!< Min enumerator value of CRCOK field.                                 */
66770   #define RADIO_INTENCLR10_CRCOK_Max (0x1UL)         /*!< Max enumerator value of CRCOK field.                                 */
66771   #define RADIO_INTENCLR10_CRCOK_Clear (0x1UL)       /*!< Disable                                                              */
66772   #define RADIO_INTENCLR10_CRCOK_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66773   #define RADIO_INTENCLR10_CRCOK_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66774 
66775 /* CRCERROR @Bit 12 : Write '1' to disable interrupt for event CRCERROR */
66776   #define RADIO_INTENCLR10_CRCERROR_Pos (12UL)       /*!< Position of CRCERROR field.                                          */
66777   #define RADIO_INTENCLR10_CRCERROR_Msk (0x1UL << RADIO_INTENCLR10_CRCERROR_Pos) /*!< Bit mask of CRCERROR field.              */
66778   #define RADIO_INTENCLR10_CRCERROR_Min (0x0UL)      /*!< Min enumerator value of CRCERROR field.                              */
66779   #define RADIO_INTENCLR10_CRCERROR_Max (0x1UL)      /*!< Max enumerator value of CRCERROR field.                              */
66780   #define RADIO_INTENCLR10_CRCERROR_Clear (0x1UL)    /*!< Disable                                                              */
66781   #define RADIO_INTENCLR10_CRCERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66782   #define RADIO_INTENCLR10_CRCERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66783 
66784 /* BCMATCH @Bit 14 : Write '1' to disable interrupt for event BCMATCH */
66785   #define RADIO_INTENCLR10_BCMATCH_Pos (14UL)        /*!< Position of BCMATCH field.                                           */
66786   #define RADIO_INTENCLR10_BCMATCH_Msk (0x1UL << RADIO_INTENCLR10_BCMATCH_Pos) /*!< Bit mask of BCMATCH field.                 */
66787   #define RADIO_INTENCLR10_BCMATCH_Min (0x0UL)       /*!< Min enumerator value of BCMATCH field.                               */
66788   #define RADIO_INTENCLR10_BCMATCH_Max (0x1UL)       /*!< Max enumerator value of BCMATCH field.                               */
66789   #define RADIO_INTENCLR10_BCMATCH_Clear (0x1UL)     /*!< Disable                                                              */
66790   #define RADIO_INTENCLR10_BCMATCH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66791   #define RADIO_INTENCLR10_BCMATCH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66792 
66793 /* EDEND @Bit 15 : Write '1' to disable interrupt for event EDEND */
66794   #define RADIO_INTENCLR10_EDEND_Pos (15UL)          /*!< Position of EDEND field.                                             */
66795   #define RADIO_INTENCLR10_EDEND_Msk (0x1UL << RADIO_INTENCLR10_EDEND_Pos) /*!< Bit mask of EDEND field.                       */
66796   #define RADIO_INTENCLR10_EDEND_Min (0x0UL)         /*!< Min enumerator value of EDEND field.                                 */
66797   #define RADIO_INTENCLR10_EDEND_Max (0x1UL)         /*!< Max enumerator value of EDEND field.                                 */
66798   #define RADIO_INTENCLR10_EDEND_Clear (0x1UL)       /*!< Disable                                                              */
66799   #define RADIO_INTENCLR10_EDEND_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
66800   #define RADIO_INTENCLR10_EDEND_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
66801 
66802 /* EDSTOPPED @Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
66803   #define RADIO_INTENCLR10_EDSTOPPED_Pos (16UL)      /*!< Position of EDSTOPPED field.                                         */
66804   #define RADIO_INTENCLR10_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR10_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field.           */
66805   #define RADIO_INTENCLR10_EDSTOPPED_Min (0x0UL)     /*!< Min enumerator value of EDSTOPPED field.                             */
66806   #define RADIO_INTENCLR10_EDSTOPPED_Max (0x1UL)     /*!< Max enumerator value of EDSTOPPED field.                             */
66807   #define RADIO_INTENCLR10_EDSTOPPED_Clear (0x1UL)   /*!< Disable                                                              */
66808   #define RADIO_INTENCLR10_EDSTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                      */
66809   #define RADIO_INTENCLR10_EDSTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                        */
66810 
66811 /* CCAIDLE @Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
66812   #define RADIO_INTENCLR10_CCAIDLE_Pos (17UL)        /*!< Position of CCAIDLE field.                                           */
66813   #define RADIO_INTENCLR10_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR10_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field.                 */
66814   #define RADIO_INTENCLR10_CCAIDLE_Min (0x0UL)       /*!< Min enumerator value of CCAIDLE field.                               */
66815   #define RADIO_INTENCLR10_CCAIDLE_Max (0x1UL)       /*!< Max enumerator value of CCAIDLE field.                               */
66816   #define RADIO_INTENCLR10_CCAIDLE_Clear (0x1UL)     /*!< Disable                                                              */
66817   #define RADIO_INTENCLR10_CCAIDLE_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66818   #define RADIO_INTENCLR10_CCAIDLE_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66819 
66820 /* CCABUSY @Bit 18 : Write '1' to disable interrupt for event CCABUSY */
66821   #define RADIO_INTENCLR10_CCABUSY_Pos (18UL)        /*!< Position of CCABUSY field.                                           */
66822   #define RADIO_INTENCLR10_CCABUSY_Msk (0x1UL << RADIO_INTENCLR10_CCABUSY_Pos) /*!< Bit mask of CCABUSY field.                 */
66823   #define RADIO_INTENCLR10_CCABUSY_Min (0x0UL)       /*!< Min enumerator value of CCABUSY field.                               */
66824   #define RADIO_INTENCLR10_CCABUSY_Max (0x1UL)       /*!< Max enumerator value of CCABUSY field.                               */
66825   #define RADIO_INTENCLR10_CCABUSY_Clear (0x1UL)     /*!< Disable                                                              */
66826   #define RADIO_INTENCLR10_CCABUSY_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
66827   #define RADIO_INTENCLR10_CCABUSY_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
66828 
66829 /* CCASTOPPED @Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
66830   #define RADIO_INTENCLR10_CCASTOPPED_Pos (19UL)     /*!< Position of CCASTOPPED field.                                        */
66831   #define RADIO_INTENCLR10_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR10_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field.        */
66832   #define RADIO_INTENCLR10_CCASTOPPED_Min (0x0UL)    /*!< Min enumerator value of CCASTOPPED field.                            */
66833   #define RADIO_INTENCLR10_CCASTOPPED_Max (0x1UL)    /*!< Max enumerator value of CCASTOPPED field.                            */
66834   #define RADIO_INTENCLR10_CCASTOPPED_Clear (0x1UL)  /*!< Disable                                                              */
66835   #define RADIO_INTENCLR10_CCASTOPPED_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66836   #define RADIO_INTENCLR10_CCASTOPPED_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66837 
66838 /* RATEBOOST @Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
66839   #define RADIO_INTENCLR10_RATEBOOST_Pos (20UL)      /*!< Position of RATEBOOST field.                                         */
66840   #define RADIO_INTENCLR10_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR10_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field.           */
66841   #define RADIO_INTENCLR10_RATEBOOST_Min (0x0UL)     /*!< Min enumerator value of RATEBOOST field.                             */
66842   #define RADIO_INTENCLR10_RATEBOOST_Max (0x1UL)     /*!< Max enumerator value of RATEBOOST field.                             */
66843   #define RADIO_INTENCLR10_RATEBOOST_Clear (0x1UL)   /*!< Disable                                                              */
66844   #define RADIO_INTENCLR10_RATEBOOST_Disabled (0x0UL) /*!< Read: Disabled                                                      */
66845   #define RADIO_INTENCLR10_RATEBOOST_Enabled (0x1UL) /*!< Read: Enabled                                                        */
66846 
66847 /* MHRMATCH @Bit 21 : Write '1' to disable interrupt for event MHRMATCH */
66848   #define RADIO_INTENCLR10_MHRMATCH_Pos (21UL)       /*!< Position of MHRMATCH field.                                          */
66849   #define RADIO_INTENCLR10_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR10_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field.              */
66850   #define RADIO_INTENCLR10_MHRMATCH_Min (0x0UL)      /*!< Min enumerator value of MHRMATCH field.                              */
66851   #define RADIO_INTENCLR10_MHRMATCH_Max (0x1UL)      /*!< Max enumerator value of MHRMATCH field.                              */
66852   #define RADIO_INTENCLR10_MHRMATCH_Clear (0x1UL)    /*!< Disable                                                              */
66853   #define RADIO_INTENCLR10_MHRMATCH_Disabled (0x0UL) /*!< Read: Disabled                                                       */
66854   #define RADIO_INTENCLR10_MHRMATCH_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
66855 
66856 /* SYNC @Bit 22 : Write '1' to disable interrupt for event SYNC */
66857   #define RADIO_INTENCLR10_SYNC_Pos (22UL)           /*!< Position of SYNC field.                                              */
66858   #define RADIO_INTENCLR10_SYNC_Msk (0x1UL << RADIO_INTENCLR10_SYNC_Pos) /*!< Bit mask of SYNC field.                          */
66859   #define RADIO_INTENCLR10_SYNC_Min (0x0UL)          /*!< Min enumerator value of SYNC field.                                  */
66860   #define RADIO_INTENCLR10_SYNC_Max (0x1UL)          /*!< Max enumerator value of SYNC field.                                  */
66861   #define RADIO_INTENCLR10_SYNC_Clear (0x1UL)        /*!< Disable                                                              */
66862   #define RADIO_INTENCLR10_SYNC_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
66863   #define RADIO_INTENCLR10_SYNC_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
66864 
66865 /* CTEPRESENT @Bit 23 : Write '1' to disable interrupt for event CTEPRESENT */
66866   #define RADIO_INTENCLR10_CTEPRESENT_Pos (23UL)     /*!< Position of CTEPRESENT field.                                        */
66867   #define RADIO_INTENCLR10_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR10_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field.        */
66868   #define RADIO_INTENCLR10_CTEPRESENT_Min (0x0UL)    /*!< Min enumerator value of CTEPRESENT field.                            */
66869   #define RADIO_INTENCLR10_CTEPRESENT_Max (0x1UL)    /*!< Max enumerator value of CTEPRESENT field.                            */
66870   #define RADIO_INTENCLR10_CTEPRESENT_Clear (0x1UL)  /*!< Disable                                                              */
66871   #define RADIO_INTENCLR10_CTEPRESENT_Disabled (0x0UL) /*!< Read: Disabled                                                     */
66872   #define RADIO_INTENCLR10_CTEPRESENT_Enabled (0x1UL) /*!< Read: Enabled                                                       */
66873 
66874 
66875 /* RADIO_MODE: Data rate and modulation */
66876   #define RADIO_MODE_ResetValue (0x00000000UL)       /*!< Reset value of MODE register.                                        */
66877 
66878 /* MODE @Bits 0..3 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
66879   #define RADIO_MODE_MODE_Pos (0UL)                  /*!< Position of MODE field.                                              */
66880   #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field.                                      */
66881   #define RADIO_MODE_MODE_Min (0x0UL)                /*!< Min enumerator value of MODE field.                                  */
66882   #define RADIO_MODE_MODE_Max (0xFUL)                /*!< Max enumerator value of MODE field.                                  */
66883   #define RADIO_MODE_MODE_Nrf_1Mbit (0x0UL)          /*!< 1 Mbps Nordic proprietary radio mode                                 */
66884   #define RADIO_MODE_MODE_Nrf_2Mbit (0x1UL)          /*!< 2 Mbps Nordic proprietary radio mode                                 */
66885   #define RADIO_MODE_MODE_Ble_1Mbit (0x3UL)          /*!< 1 Mbps BLE                                                           */
66886   #define RADIO_MODE_MODE_Ble_2Mbit (0x4UL)          /*!< 2 Mbps BLE                                                           */
66887   #define RADIO_MODE_MODE_Ble_LR125Kbit (0x5UL)      /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX                     */
66888   #define RADIO_MODE_MODE_Ble_LR500Kbit (0x6UL)      /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX                     */
66889   #define RADIO_MODE_MODE_Nrf_4Mbit0_5 (0x9UL)       /*!< 4 Mbps Nordic proprietary radio mode (BT=0.5/h=0.5)                  */
66890   #define RADIO_MODE_MODE_Nrf_4Mbit0_25 (0xAUL)      /*!< 4 Mbps Nordic proprietary radio mode (BT=0.5/h=0.25)                 */
66891   #define RADIO_MODE_MODE_Ieee802154_250Kbit (0xFUL) /*!< IEEE 802.15.4-2006 250 kbps                                          */
66892 
66893 
66894 /* RADIO_STATE: Current radio state */
66895   #define RADIO_STATE_ResetValue (0x00000000UL)      /*!< Reset value of STATE register.                                       */
66896 
66897 /* STATE @Bits 0..3 : Current radio state */
66898   #define RADIO_STATE_STATE_Pos (0UL)                /*!< Position of STATE field.                                             */
66899   #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field.                                 */
66900   #define RADIO_STATE_STATE_Min (0x0UL)              /*!< Min enumerator value of STATE field.                                 */
66901   #define RADIO_STATE_STATE_Max (0xCUL)              /*!< Max enumerator value of STATE field.                                 */
66902   #define RADIO_STATE_STATE_Disabled (0x0UL)         /*!< RADIO is in the Disabled state                                       */
66903   #define RADIO_STATE_STATE_RxRu (0x1UL)             /*!< RADIO is in the RXRU state                                           */
66904   #define RADIO_STATE_STATE_RxIdle (0x2UL)           /*!< RADIO is in the RXIDLE state                                         */
66905   #define RADIO_STATE_STATE_Rx (0x3UL)               /*!< RADIO is in the RX state                                             */
66906   #define RADIO_STATE_STATE_RxDisable (0x4UL)        /*!< RADIO is in the RXDISABLED state                                     */
66907   #define RADIO_STATE_STATE_TxRu (0x9UL)             /*!< RADIO is in the TXRU state                                           */
66908   #define RADIO_STATE_STATE_TxIdle (0xAUL)           /*!< RADIO is in the TXIDLE state                                         */
66909   #define RADIO_STATE_STATE_Tx (0xBUL)               /*!< RADIO is in the TX state                                             */
66910   #define RADIO_STATE_STATE_TxDisable (0xCUL)        /*!< RADIO is in the TXDISABLED state                                     */
66911 
66912 
66913 /* RADIO_EDCTRL: IEEE 802.15.4 energy detect control */
66914   #define RADIO_EDCTRL_ResetValue (0x20000000UL)     /*!< Reset value of EDCTRL register.                                      */
66915 
66916 /* EDCNT @Bits 0..20 : IEEE 802.15.4 energy detect loop count */
66917   #define RADIO_EDCTRL_EDCNT_Pos (0UL)               /*!< Position of EDCNT field.                                             */
66918   #define RADIO_EDCTRL_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCTRL_EDCNT_Pos) /*!< Bit mask of EDCNT field.                          */
66919 
66920 /* EDPERIOD @Bits 24..29 : IEEE 802.15.4 energy detect/cca period, 4us resolution */
66921   #define RADIO_EDCTRL_EDPERIOD_Pos (24UL)           /*!< Position of EDPERIOD field.                                          */
66922   #define RADIO_EDCTRL_EDPERIOD_Msk (0x3FUL << RADIO_EDCTRL_EDPERIOD_Pos) /*!< Bit mask of EDPERIOD field.                     */
66923 
66924 
66925 /* RADIO_EDSAMPLE: IEEE 802.15.4 energy detect level */
66926   #define RADIO_EDSAMPLE_ResetValue (0x00000000UL)   /*!< Reset value of EDSAMPLE register.                                    */
66927 
66928 /* EDLVL @Bits 0..7 : IEEE 802.15.4 energy detect level */
66929   #define RADIO_EDSAMPLE_EDLVL_Pos (0UL)             /*!< Position of EDLVL field.                                             */
66930   #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field.                          */
66931   #define RADIO_EDSAMPLE_EDLVL_Min (0x0UL)           /*!< Min value of EDLVL field.                                            */
66932   #define RADIO_EDSAMPLE_EDLVL_Max (0x7FUL)          /*!< Max size of EDLVL field.                                             */
66933 
66934 
66935 /* RADIO_CCACTRL: IEEE 802.15.4 clear channel assessment control */
66936   #define RADIO_CCACTRL_ResetValue (0x052D0000UL)    /*!< Reset value of CCACTRL register.                                     */
66937 
66938 /* CCAMODE @Bits 0..2 : CCA mode of operation */
66939   #define RADIO_CCACTRL_CCAMODE_Pos (0UL)            /*!< Position of CCAMODE field.                                           */
66940   #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field.                       */
66941   #define RADIO_CCACTRL_CCAMODE_Min (0x0UL)          /*!< Min enumerator value of CCAMODE field.                               */
66942   #define RADIO_CCACTRL_CCAMODE_Max (0x4UL)          /*!< Max enumerator value of CCAMODE field.                               */
66943   #define RADIO_CCACTRL_CCAMODE_EdMode (0x0UL)       /*!< Energy above threshold                                               */
66944   #define RADIO_CCACTRL_CCAMODE_CarrierMode (0x1UL)  /*!< Carrier seen                                                         */
66945   #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (0x2UL) /*!< Energy above threshold AND carrier seen                          */
66946   #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (0x3UL) /*!< Energy above threshold OR carrier seen                            */
66947   #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (0x4UL)  /*!< Energy above threshold test mode that will abort when first ED
66948                                                           measurement over threshold is seen. No averaging.*/
66949 
66950 /* CCAEDTHRES @Bits 8..15 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
66951   #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL)         /*!< Position of CCAEDTHRES field.                                        */
66952   #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field.             */
66953 
66954 /* CCACORRTHRES @Bits 16..23 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and
66955                                CarrierOrEdMode. */
66956 
66957   #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL)      /*!< Position of CCACORRTHRES field.                                      */
66958   #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field.       */
66959 
66960 /* CCACORRCNT @Bits 24..31 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect
66961                              is enabled. */
66962 
66963   #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL)        /*!< Position of CCACORRCNT field.                                        */
66964   #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field.             */
66965 
66966 
66967 /* RADIO_DATAWHITEIV: Data whitening initial value */
66968   #define RADIO_DATAWHITEIV_ResetValue (0x00000040UL) /*!< Reset value of DATAWHITEIV register.                                */
66969 
66970 /* DATAWHITEIV @Bits 0..5 : (unspecified) */
66971   #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL)    /*!< Position of DATAWHITEIV field.                                       */
66972   #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field.  */
66973 
66974 
66975 /* RADIO_TIMING: Timing */
66976   #define RADIO_TIMING_ResetValue (0x00000000UL)     /*!< Reset value of TIMING register.                                      */
66977 
66978 /* RU @Bit 0 : 0: Default ramp-up time, compatible with 180nm radio. 1: Fast ramp-up. */
66979   #define RADIO_TIMING_RU_Pos (0UL)                  /*!< Position of RU field.                                                */
66980   #define RADIO_TIMING_RU_Msk (0x1UL << RADIO_TIMING_RU_Pos) /*!< Bit mask of RU field.                                        */
66981 
66982 
66983 /* RADIO_FREQUENCY: Frequency */
66984   #define RADIO_FREQUENCY_ResetValue (0x00000002UL)  /*!< Reset value of FREQUENCY register.                                   */
66985 
66986 /* FREQUENCY @Bits 0..6 : Radio channel frequency. Frequency = 2400 + FREQUENCY (MHz). */
66987   #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL)        /*!< Position of FREQUENCY field.                                         */
66988   #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field.            */
66989 
66990 /* MAP @Bit 8 : Channel map selection. 0: Channel map between 2400 MHZ to 2500 MHz, Frequency = 2400 + FREQUENCY (MHz). 1:
66991                 Channel map between 2360 MHZ to 2460 MHz, Frequency = 2360 + FREQUENCY (MHz). */
66992 
66993   #define RADIO_FREQUENCY_MAP_Pos (8UL)              /*!< Position of MAP field.                                               */
66994   #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field.                               */
66995 
66996 
66997 /* RADIO_TXPOWER: Output power */
66998   #define RADIO_TXPOWER_ResetValue (0x00000000UL)    /*!< Reset value of TXPOWER register.                                     */
66999 
67000 /* TXPOWER @Bits 0..7 : RADIO output power */
67001   #define RADIO_TXPOWER_TXPOWER_Pos (0UL)            /*!< Position of TXPOWER field.                                           */
67002   #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field.                      */
67003   #define RADIO_TXPOWER_TXPOWER_Min (0x0UL)          /*!< Min enumerator value of TXPOWER field.                               */
67004   #define RADIO_TXPOWER_TXPOWER_Max (0xFFUL)         /*!< Max enumerator value of TXPOWER field.                               */
67005   #define RADIO_TXPOWER_TXPOWER_Pos10dBm (0x0AUL)    /*!< +10 dBm                                                              */
67006   #define RADIO_TXPOWER_TXPOWER_Pos9dBm (0x09UL)     /*!< +9 dBm                                                               */
67007   #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x08UL)     /*!< +8 dBm                                                               */
67008   #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x07UL)     /*!< +7 dBm                                                               */
67009   #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x06UL)     /*!< +6 dBm                                                               */
67010   #define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x05UL)     /*!< +5 dBm                                                               */
67011   #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL)     /*!< +4 dBm                                                               */
67012   #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL)     /*!< +3 dBm                                                               */
67013   #define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x02UL)     /*!< +2 dBm                                                               */
67014   #define RADIO_TXPOWER_TXPOWER_Pos1dBm (0x01UL)     /*!< +1 dBm                                                               */
67015   #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL)        /*!< 0 dBm                                                                */
67016   #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0xFFUL)     /*!< -1 dBm                                                               */
67017   #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0xFEUL)     /*!< -2 dBm                                                               */
67018   #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL)     /*!< -4 dBm                                                               */
67019   #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL)     /*!< -8 dBm                                                               */
67020   #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL)    /*!< -12 dBm                                                              */
67021   #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL)    /*!< -16 dBm                                                              */
67022   #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL)    /*!< -20 dBm                                                              */
67023   #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL)    /*!< -30 dBm                                                              */
67024   #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL)    /*!< -40 dBm                                                              */
67025   #define RADIO_TXPOWER_TXPOWER_Neg70dBm (0xBAUL)    /*!< -70 dBm                                                              */
67026 
67027 
67028 /* RADIO_TIFS: Interframe spacing in us */
67029   #define RADIO_TIFS_ResetValue (0x00000000UL)       /*!< Reset value of TIFS register.                                        */
67030 
67031 /* TIFS @Bits 0..9 : Interframe spacing in us. Interframe space is the time interval between two consecutive packets. It is
67032                      defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of
67033                      the first bit of the subsequent packet. */
67034 
67035   #define RADIO_TIFS_TIFS_Pos (0UL)                  /*!< Position of TIFS field.                                              */
67036   #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field.                                    */
67037 
67038 
67039 /* RADIO_RSSISAMPLE: RSSI sample */
67040   #define RADIO_RSSISAMPLE_ResetValue (0x0000007FUL) /*!< Reset value of RSSISAMPLE register.                                  */
67041 
67042 /* RSSISAMPLE @Bits 0..6 : RSSI sample result. The value of this register is read as a positive value while the actual received
67043                            signal strength is a negative value. Actual received signal strength is therefore as follows:
67044                            received signal strength = -A dBm. */
67045 
67046   #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL)      /*!< Position of RSSISAMPLE field.                                        */
67047   #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field.       */
67048 
67049 
67050 /* RADIO_DFEMODE: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */
67051   #define RADIO_DFEMODE_ResetValue (0x00000000UL)    /*!< Reset value of DFEMODE register.                                     */
67052 
67053 /* DFEOPMODE @Bits 0..1 : Direction finding operation mode */
67054   #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL)          /*!< Position of DFEOPMODE field.                                         */
67055   #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field.                 */
67056   #define RADIO_DFEMODE_DFEOPMODE_Min (0x0UL)        /*!< Min enumerator value of DFEOPMODE field.                             */
67057   #define RADIO_DFEMODE_DFEOPMODE_Max (0x3UL)        /*!< Max enumerator value of DFEOPMODE field.                             */
67058   #define RADIO_DFEMODE_DFEOPMODE_Disabled (0x0UL)   /*!< Direction finding mode disabled                                      */
67059   #define RADIO_DFEMODE_DFEOPMODE_AoD (0x2UL)        /*!< Direction finding mode set to AoD                                    */
67060   #define RADIO_DFEMODE_DFEOPMODE_AoA (0x3UL)        /*!< Direction finding mode set to AoA                                    */
67061 
67062 
67063 /* RADIO_DFESTATUS: DFE status information */
67064   #define RADIO_DFESTATUS_ResetValue (0x00000000UL)  /*!< Reset value of DFESTATUS register.                                   */
67065 
67066 /* SWITCHINGSTATE @Bits 0..2 : Internal state of switching state machine */
67067   #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL)   /*!< Position of SWITCHINGSTATE field.                                    */
67068   #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE
67069                                                                             field.*/
67070   #define RADIO_DFESTATUS_SWITCHINGSTATE_Min (0x0UL) /*!< Min enumerator value of SWITCHINGSTATE field.                        */
67071   #define RADIO_DFESTATUS_SWITCHINGSTATE_Max (0x5UL) /*!< Max enumerator value of SWITCHINGSTATE field.                        */
67072   #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0x0UL) /*!< Switching state Idle                                                */
67073   #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (0x1UL) /*!< Switching state Offset                                            */
67074   #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (0x2UL) /*!< Switching state Guard                                              */
67075   #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (0x3UL) /*!< Switching state Ref                                                  */
67076   #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (0x4UL) /*!< Switching state Switching                                      */
67077   #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (0x5UL) /*!< Switching state Ending                                            */
67078 
67079 /* SAMPLINGSTATE @Bit 4 : Internal state of sampling state machine */
67080   #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL)    /*!< Position of SAMPLINGSTATE field.                                     */
67081   #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */
67082   #define RADIO_DFESTATUS_SAMPLINGSTATE_Min (0x0UL)  /*!< Min enumerator value of SAMPLINGSTATE field.                         */
67083   #define RADIO_DFESTATUS_SAMPLINGSTATE_Max (0x1UL)  /*!< Max enumerator value of SAMPLINGSTATE field.                         */
67084   #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0x0UL) /*!< Sampling state Idle                                                  */
67085   #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (0x1UL) /*!< Sampling state Sampling                                          */
67086 
67087 
67088 /* RADIO_DFECTRL1: Various configuration for Direction finding */
67089   #define RADIO_DFECTRL1_ResetValue (0x00023282UL)   /*!< Reset value of DFECTRL1 register.                                    */
67090 
67091 /* NUMBEROF8US @Bits 0..5 : Length of the AoA/AoD procedure in number of 8 us units */
67092   #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL)       /*!< Position of NUMBEROF8US field.                                       */
67093   #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field.        */
67094 
67095 /* DFEINEXTENSION @Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */
67096   #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL)    /*!< Position of DFEINEXTENSION field.                                    */
67097   #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field.*/
67098   #define RADIO_DFECTRL1_DFEINEXTENSION_Min (0x0UL)  /*!< Min enumerator value of DFEINEXTENSION field.                        */
67099   #define RADIO_DFECTRL1_DFEINEXTENSION_Max (0x1UL)  /*!< Max enumerator value of DFEINEXTENSION field.                        */
67100   #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (0x1UL)  /*!< AoA/AoD procedure triggered at end of CRC                            */
67101   #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0x0UL) /*!< Antenna switching/sampling is done in the packet payload          */
67102 
67103 /* TSWITCHSPACING @Bits 8..10 : Interval between every time the antenna is changed in the SWITCHING state */
67104   #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL)    /*!< Position of TSWITCHSPACING field.                                    */
67105   #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field.*/
67106   #define RADIO_DFECTRL1_TSWITCHSPACING_Min (0x1UL)  /*!< Min enumerator value of TSWITCHSPACING field.                        */
67107   #define RADIO_DFECTRL1_TSWITCHSPACING_Max (0x3UL)  /*!< Max enumerator value of TSWITCHSPACING field.                        */
67108   #define RADIO_DFECTRL1_TSWITCHSPACING_4us (0x1UL)  /*!< 4us                                                                  */
67109   #define RADIO_DFECTRL1_TSWITCHSPACING_2us (0x2UL)  /*!< 2us                                                                  */
67110   #define RADIO_DFECTRL1_TSWITCHSPACING_1us (0x3UL)  /*!< 1us                                                                  */
67111 
67112 /* TSAMPLESPACINGREF @Bits 12..14 : Interval between samples in the REFERENCE period */
67113   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field.                                */
67114   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of
67115                                                                             TSAMPLESPACINGREF field.*/
67116   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Min (0x1UL) /*!< Min enumerator value of TSAMPLESPACINGREF field.                   */
67117   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Max (0x6UL) /*!< Max enumerator value of TSAMPLESPACINGREF field.                   */
67118   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (0x1UL) /*!< 4us                                                                */
67119   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (0x2UL) /*!< 2us                                                                */
67120   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (0x3UL) /*!< 1us                                                                */
67121   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (0x4UL) /*!< 0.5us                                                            */
67122   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (0x5UL) /*!< 0.25us                                                           */
67123   #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (0x6UL) /*!< 0.125us                                                          */
67124 
67125 /* SAMPLETYPE @Bit 15 : Whether to sample I/Q or magnitude/phase */
67126   #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL)       /*!< Position of SAMPLETYPE field.                                        */
67127   #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field.            */
67128   #define RADIO_DFECTRL1_SAMPLETYPE_Min (0x0UL)      /*!< Min enumerator value of SAMPLETYPE field.                            */
67129   #define RADIO_DFECTRL1_SAMPLETYPE_Max (0x1UL)      /*!< Max enumerator value of SAMPLETYPE field.                            */
67130   #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0x0UL)       /*!< Complex samples in I and Q                                           */
67131   #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (0x1UL) /*!< Complex samples as magnitude and phase                               */
67132 
67133 /* TSAMPLESPACING @Bits 16..18 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */
67134   #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL)   /*!< Position of TSAMPLESPACING field.                                    */
67135   #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field.*/
67136   #define RADIO_DFECTRL1_TSAMPLESPACING_Min (0x1UL)  /*!< Min enumerator value of TSAMPLESPACING field.                        */
67137   #define RADIO_DFECTRL1_TSAMPLESPACING_Max (0x6UL)  /*!< Max enumerator value of TSAMPLESPACING field.                        */
67138   #define RADIO_DFECTRL1_TSAMPLESPACING_4us (0x1UL)  /*!< 4us                                                                  */
67139   #define RADIO_DFECTRL1_TSAMPLESPACING_2us (0x2UL)  /*!< 2us                                                                  */
67140   #define RADIO_DFECTRL1_TSAMPLESPACING_1us (0x3UL)  /*!< 1us                                                                  */
67141   #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (0x4UL) /*!< 0.5us                                                               */
67142   #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (0x5UL) /*!< 0.25us                                                              */
67143   #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (0x6UL) /*!< 0.125us                                                             */
67144 
67145 /* REPEATPATTERN @Bits 20..23 : Repeat every antenna pattern N times. */
67146   #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL)    /*!< Position of REPEATPATTERN field.                                     */
67147   #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field.   */
67148   #define RADIO_DFECTRL1_REPEATPATTERN_Min (0x0UL)   /*!< Min enumerator value of REPEATPATTERN field.                         */
67149   #define RADIO_DFECTRL1_REPEATPATTERN_Max (0x0UL)   /*!< Max enumerator value of REPEATPATTERN field.                         */
67150   #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0x0UL) /*!< Do not repeat (1 time in total)                                   */
67151 
67152 /* AGCBACKOFFGAIN @Bits 24..27 : Gain will be lowered by the specified number of gain steps at the start of CTE */
67153   #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL)   /*!< Position of AGCBACKOFFGAIN field.                                    */
67154   #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field.*/
67155 
67156 
67157 /* RADIO_DFECTRL2: Start offset for Direction finding */
67158   #define RADIO_DFECTRL2_ResetValue (0x00000000UL)   /*!< Reset value of DFECTRL2 register.                                    */
67159 
67160 /* TSWITCHOFFSET @Bits 0..12 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */
67161   #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL)     /*!< Position of TSWITCHOFFSET field.                                     */
67162   #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field.*/
67163 
67164 /* TSAMPLEOFFSET @Bits 16..27 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning
67165                                 of the REFERENCE state - 12 us after switching start */
67166 
67167   #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL)    /*!< Position of TSAMPLEOFFSET field.                                     */
67168   #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */
67169 
67170 
67171 /* RADIO_SWITCHPATTERN: GPIO patterns to be used for each antenna */
67172   #define RADIO_SWITCHPATTERN_ResetValue (0x00000000UL) /*!< Reset value of SWITCHPATTERN register.                            */
67173 
67174 /* SWITCHPATTERN @Bits 0..7 : Fill array of GPIO patterns for antenna control */
67175   #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field.                                    */
67176   #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN
67177                                                                             field.*/
67178 
67179 
67180 /* RADIO_CLEARPATTERN: Clear the GPIO pattern array for antenna control */
67181   #define RADIO_CLEARPATTERN_ResetValue (0x00000000UL) /*!< Reset value of CLEARPATTERN register.                              */
67182 
67183 /* CLEARPATTERN @Bit 0 : Clear the GPIO pattern array for antenna control Behaves as a task register, but does not have PPI nor
67184                          IRQ */
67185 
67186   #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL)  /*!< Position of CLEARPATTERN field.                                      */
67187   #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN
67188                                                                             field.*/
67189 
67190 
67191 /* RADIO_CRCSTATUS: CRC status */
67192   #define RADIO_CRCSTATUS_ResetValue (0x00000000UL)  /*!< Reset value of CRCSTATUS register.                                   */
67193 
67194 /* CRCSTATUS @Bit 0 : CRC status of packet received */
67195   #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL)        /*!< Position of CRCSTATUS field.                                         */
67196   #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field.             */
67197   #define RADIO_CRCSTATUS_CRCSTATUS_Min (0x0UL)      /*!< Min enumerator value of CRCSTATUS field.                             */
67198   #define RADIO_CRCSTATUS_CRCSTATUS_Max (0x1UL)      /*!< Max enumerator value of CRCSTATUS field.                             */
67199   #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0x0UL) /*!< Packet received with CRC error                                       */
67200   #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (0x1UL)    /*!< Packet received with CRC ok                                          */
67201 
67202 
67203 /* RADIO_RXMATCH: Received address */
67204   #define RADIO_RXMATCH_ResetValue (0x00000000UL)    /*!< Reset value of RXMATCH register.                                     */
67205 
67206 /* RXMATCH @Bits 0..2 : Received address */
67207   #define RADIO_RXMATCH_RXMATCH_Pos (0UL)            /*!< Position of RXMATCH field.                                           */
67208   #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field.                       */
67209 
67210 
67211 /* RADIO_RXCRC: CRC field of previously received packet */
67212   #define RADIO_RXCRC_ResetValue (0x00000000UL)      /*!< Reset value of RXCRC register.                                       */
67213 
67214 /* RXCRC @Bits 0..23 : CRC field of previously received packet */
67215   #define RADIO_RXCRC_RXCRC_Pos (0UL)                /*!< Position of RXCRC field.                                             */
67216   #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field.                            */
67217 
67218 
67219 /* RADIO_DAI: Device address match index */
67220   #define RADIO_DAI_ResetValue (0x00000000UL)        /*!< Reset value of DAI register.                                         */
67221 
67222 /* DAI @Bits 0..2 : Device address match index */
67223   #define RADIO_DAI_DAI_Pos (0UL)                    /*!< Position of DAI field.                                               */
67224   #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field.                                           */
67225 
67226 
67227 /* RADIO_PDUSTAT: Payload status */
67228   #define RADIO_PDUSTAT_ResetValue (0x00000000UL)    /*!< Reset value of PDUSTAT register.                                     */
67229 
67230 /* PDUSTAT @Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
67231   #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL)            /*!< Position of PDUSTAT field.                                           */
67232   #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field.                       */
67233   #define RADIO_PDUSTAT_PDUSTAT_Min (0x0UL)          /*!< Min enumerator value of PDUSTAT field.                               */
67234   #define RADIO_PDUSTAT_PDUSTAT_Max (0x1UL)          /*!< Max enumerator value of PDUSTAT field.                               */
67235   #define RADIO_PDUSTAT_PDUSTAT_LessThan (0x0UL)     /*!< Payload less than PCNF1.MAXLEN                                       */
67236   #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (0x1UL)  /*!< Payload greater than PCNF1.MAXLEN                                    */
67237 
67238 /* CISTAT @Bits 1..2 : Status on what rate packet is received with in Long Range */
67239   #define RADIO_PDUSTAT_CISTAT_Pos (1UL)             /*!< Position of CISTAT field.                                            */
67240   #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field.                          */
67241   #define RADIO_PDUSTAT_CISTAT_Min (0x0UL)           /*!< Min enumerator value of CISTAT field.                                */
67242   #define RADIO_PDUSTAT_CISTAT_Max (0x1UL)           /*!< Max enumerator value of CISTAT field.                                */
67243   #define RADIO_PDUSTAT_CISTAT_LR125kbit (0x0UL)     /*!< Frame is received at 125 kbps                                        */
67244   #define RADIO_PDUSTAT_CISTAT_LR500kbit (0x1UL)     /*!< Frame is received at 500 kbps                                        */
67245 
67246 
67247 /* RADIO_PCNF0: Packet configuration register 0 */
67248   #define RADIO_PCNF0_ResetValue (0x00000000UL)      /*!< Reset value of PCNF0 register.                                       */
67249 
67250 /* LFLEN @Bits 0..3 : Length on air of LENGTH field in number of bits. */
67251   #define RADIO_PCNF0_LFLEN_Pos (0UL)                /*!< Position of LFLEN field.                                             */
67252   #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field.                                 */
67253 
67254 /* S0LEN @Bit 8 : Length on air of S0 field in number of bytes. */
67255   #define RADIO_PCNF0_S0LEN_Pos (8UL)                /*!< Position of S0LEN field.                                             */
67256   #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field.                                 */
67257 
67258 /* S1LEN @Bits 16..19 : Length on air of S1 field in number of bits. */
67259   #define RADIO_PCNF0_S1LEN_Pos (16UL)               /*!< Position of S1LEN field.                                             */
67260   #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field.                                 */
67261 
67262 /* S1INCL @Bits 20..21 : Include or exclude S1 field in RAM */
67263   #define RADIO_PCNF0_S1INCL_Pos (20UL)              /*!< Position of S1INCL field.                                            */
67264   #define RADIO_PCNF0_S1INCL_Msk (0x3UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field.                              */
67265   #define RADIO_PCNF0_S1INCL_Min (0x0UL)             /*!< Min enumerator value of S1INCL field.                                */
67266   #define RADIO_PCNF0_S1INCL_Max (0x1UL)             /*!< Max enumerator value of S1INCL field.                                */
67267   #define RADIO_PCNF0_S1INCL_Automatic (0x0UL)       /*!< Include S1 field in RAM only if S1LEN > 0                            */
67268   #define RADIO_PCNF0_S1INCL_Include (0x1UL)         /*!< Always include S1 field in RAM independent of S1LEN                  */
67269 
67270 /* CILEN @Bits 22..23 : Length of code indicator - long range */
67271   #define RADIO_PCNF0_CILEN_Pos (22UL)               /*!< Position of CILEN field.                                             */
67272   #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field.                                 */
67273 
67274 /* PLEN @Bits 24..25 : Length of preamble on air. Decision point: TASKS_START task */
67275   #define RADIO_PCNF0_PLEN_Pos (24UL)                /*!< Position of PLEN field.                                              */
67276   #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field.                                    */
67277   #define RADIO_PCNF0_PLEN_Min (0x0UL)               /*!< Min enumerator value of PLEN field.                                  */
67278   #define RADIO_PCNF0_PLEN_Max (0x3UL)               /*!< Max enumerator value of PLEN field.                                  */
67279   #define RADIO_PCNF0_PLEN_8bit (0x0UL)              /*!< 8-bit preamble                                                       */
67280   #define RADIO_PCNF0_PLEN_16bit (0x1UL)             /*!< 16-bit preamble                                                      */
67281   #define RADIO_PCNF0_PLEN_32bitZero (0x2UL)         /*!< 32-bit zero preamble - used for IEEE 802.15.4                        */
67282   #define RADIO_PCNF0_PLEN_LongRange (0x3UL)         /*!< Preamble - used for BLE long range                                   */
67283 
67284 /* CRCINC @Bit 26 : Indicates if LENGTH field contains CRC or not */
67285   #define RADIO_PCNF0_CRCINC_Pos (26UL)              /*!< Position of CRCINC field.                                            */
67286   #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field.                              */
67287   #define RADIO_PCNF0_CRCINC_Min (0x0UL)             /*!< Min enumerator value of CRCINC field.                                */
67288   #define RADIO_PCNF0_CRCINC_Max (0x1UL)             /*!< Max enumerator value of CRCINC field.                                */
67289   #define RADIO_PCNF0_CRCINC_Exclude (0x0UL)         /*!< LENGTH does not contain CRC                                          */
67290   #define RADIO_PCNF0_CRCINC_Include (0x1UL)         /*!< LENGTH includes CRC                                                  */
67291 
67292 /* TERMLEN @Bits 29..30 : Length of TERM field in Long Range operation */
67293   #define RADIO_PCNF0_TERMLEN_Pos (29UL)             /*!< Position of TERMLEN field.                                           */
67294   #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field.                           */
67295 
67296 
67297 /* RADIO_PCNF1: Packet configuration register 1 */
67298   #define RADIO_PCNF1_ResetValue (0x00000000UL)      /*!< Reset value of PCNF1 register.                                       */
67299 
67300 /* MAXLEN @Bits 0..7 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate
67301                        the payload to MAXLEN. */
67302 
67303   #define RADIO_PCNF1_MAXLEN_Pos (0UL)               /*!< Position of MAXLEN field.                                            */
67304   #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field.                             */
67305   #define RADIO_PCNF1_MAXLEN_Min (0x0UL)             /*!< Min value of MAXLEN field.                                           */
67306   #define RADIO_PCNF1_MAXLEN_Max (0xFFUL)            /*!< Max size of MAXLEN field.                                            */
67307 
67308 /* STATLEN @Bits 8..15 : Static length in number of bytes */
67309   #define RADIO_PCNF1_STATLEN_Pos (8UL)              /*!< Position of STATLEN field.                                           */
67310   #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field.                          */
67311   #define RADIO_PCNF1_STATLEN_Min (0x0UL)            /*!< Min value of STATLEN field.                                          */
67312   #define RADIO_PCNF1_STATLEN_Max (0xFFUL)           /*!< Max size of STATLEN field.                                           */
67313 
67314 /* BALEN @Bits 16..18 : Base address length in number of bytes */
67315   #define RADIO_PCNF1_BALEN_Pos (16UL)               /*!< Position of BALEN field.                                             */
67316   #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field.                                 */
67317   #define RADIO_PCNF1_BALEN_Min (0x1UL)              /*!< Min value of BALEN field.                                            */
67318   #define RADIO_PCNF1_BALEN_Max (0x1UL)              /*!< Max size of BALEN field.                                             */
67319 
67320 /* ENDIAN @Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
67321   #define RADIO_PCNF1_ENDIAN_Pos (24UL)              /*!< Position of ENDIAN field.                                            */
67322   #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field.                              */
67323   #define RADIO_PCNF1_ENDIAN_Min (0x0UL)             /*!< Min enumerator value of ENDIAN field.                                */
67324   #define RADIO_PCNF1_ENDIAN_Max (0x1UL)             /*!< Max enumerator value of ENDIAN field.                                */
67325   #define RADIO_PCNF1_ENDIAN_Little (0x0UL)          /*!< Least significant bit on air first                                   */
67326   #define RADIO_PCNF1_ENDIAN_Big (0x1UL)             /*!< Most significant bit on air first                                    */
67327 
67328 /* WHITEEN @Bit 25 : Enable or disable packet whitening */
67329   #define RADIO_PCNF1_WHITEEN_Pos (25UL)             /*!< Position of WHITEEN field.                                           */
67330   #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field.                           */
67331   #define RADIO_PCNF1_WHITEEN_Min (0x0UL)            /*!< Min enumerator value of WHITEEN field.                               */
67332   #define RADIO_PCNF1_WHITEEN_Max (0x1UL)            /*!< Max enumerator value of WHITEEN field.                               */
67333   #define RADIO_PCNF1_WHITEEN_Disabled (0x0UL)       /*!< Disable                                                              */
67334   #define RADIO_PCNF1_WHITEEN_Enabled (0x1UL)        /*!< Enable                                                               */
67335 
67336 
67337 /* RADIO_BASE0: Base address 0 */
67338   #define RADIO_BASE0_ResetValue (0x00000000UL)      /*!< Reset value of BASE0 register.                                       */
67339 
67340 /* BASE0 @Bits 0..31 : Base address 0 */
67341   #define RADIO_BASE0_BASE0_Pos (0UL)                /*!< Position of BASE0 field.                                             */
67342   #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field.                          */
67343 
67344 
67345 /* RADIO_BASE1: Base address 1 */
67346   #define RADIO_BASE1_ResetValue (0x00000000UL)      /*!< Reset value of BASE1 register.                                       */
67347 
67348 /* BASE1 @Bits 0..31 : Base address 1 */
67349   #define RADIO_BASE1_BASE1_Pos (0UL)                /*!< Position of BASE1 field.                                             */
67350   #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field.                          */
67351 
67352 
67353 /* RADIO_PREFIX0: Prefixes bytes for logical addresses 0-3 */
67354   #define RADIO_PREFIX0_ResetValue (0x00000000UL)    /*!< Reset value of PREFIX0 register.                                     */
67355 
67356 /* AP0 @Bits 0..7 : Address prefix 0 */
67357   #define RADIO_PREFIX0_AP0_Pos (0UL)                /*!< Position of AP0 field.                                               */
67358   #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field.                                  */
67359 
67360 /* AP1 @Bits 8..15 : Address prefix 1 */
67361   #define RADIO_PREFIX0_AP1_Pos (8UL)                /*!< Position of AP1 field.                                               */
67362   #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field.                                  */
67363 
67364 /* AP2 @Bits 16..23 : Address prefix 2 */
67365   #define RADIO_PREFIX0_AP2_Pos (16UL)               /*!< Position of AP2 field.                                               */
67366   #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field.                                  */
67367 
67368 /* AP3 @Bits 24..31 : Address prefix 3 */
67369   #define RADIO_PREFIX0_AP3_Pos (24UL)               /*!< Position of AP3 field.                                               */
67370   #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field.                                  */
67371 
67372 
67373 /* RADIO_PREFIX1: Prefixes bytes for logical addresses 4-7 */
67374   #define RADIO_PREFIX1_ResetValue (0x00000000UL)    /*!< Reset value of PREFIX1 register.                                     */
67375 
67376 /* AP4 @Bits 0..7 : Address prefix 4 */
67377   #define RADIO_PREFIX1_AP4_Pos (0UL)                /*!< Position of AP4 field.                                               */
67378   #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field.                                  */
67379 
67380 /* AP5 @Bits 8..15 : Address prefix 5 */
67381   #define RADIO_PREFIX1_AP5_Pos (8UL)                /*!< Position of AP5 field.                                               */
67382   #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field.                                  */
67383 
67384 /* AP6 @Bits 16..23 : Address prefix 6 */
67385   #define RADIO_PREFIX1_AP6_Pos (16UL)               /*!< Position of AP6 field.                                               */
67386   #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field.                                  */
67387 
67388 /* AP7 @Bits 24..31 : Address prefix 7 */
67389   #define RADIO_PREFIX1_AP7_Pos (24UL)               /*!< Position of AP7 field.                                               */
67390   #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field.                                  */
67391 
67392 
67393 /* RADIO_TXADDRESS: Transmit address select */
67394   #define RADIO_TXADDRESS_ResetValue (0x00000000UL)  /*!< Reset value of TXADDRESS register.                                   */
67395 
67396 /* TXADDRESS @Bits 0..2 : Transmit address select */
67397   #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL)        /*!< Position of TXADDRESS field.                                         */
67398   #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field.             */
67399 
67400 
67401 /* RADIO_RXADDRESSES: Receive address select */
67402   #define RADIO_RXADDRESSES_ResetValue (0x00000000UL) /*!< Reset value of RXADDRESSES register.                                */
67403 
67404 /* ADDR0 @Bit 0 : Enable or disable reception on logical address 0 */
67405   #define RADIO_RXADDRESSES_ADDR0_Pos (0UL)          /*!< Position of ADDR0 field.                                             */
67406   #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field.                     */
67407   #define RADIO_RXADDRESSES_ADDR0_Min (0x0UL)        /*!< Min enumerator value of ADDR0 field.                                 */
67408   #define RADIO_RXADDRESSES_ADDR0_Max (0x1UL)        /*!< Max enumerator value of ADDR0 field.                                 */
67409   #define RADIO_RXADDRESSES_ADDR0_Disabled (0x0UL)   /*!< Disable                                                              */
67410   #define RADIO_RXADDRESSES_ADDR0_Enabled (0x1UL)    /*!< Enable                                                               */
67411 
67412 /* ADDR1 @Bit 1 : Enable or disable reception on logical address 1 */
67413   #define RADIO_RXADDRESSES_ADDR1_Pos (1UL)          /*!< Position of ADDR1 field.                                             */
67414   #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field.                     */
67415   #define RADIO_RXADDRESSES_ADDR1_Min (0x0UL)        /*!< Min enumerator value of ADDR1 field.                                 */
67416   #define RADIO_RXADDRESSES_ADDR1_Max (0x1UL)        /*!< Max enumerator value of ADDR1 field.                                 */
67417   #define RADIO_RXADDRESSES_ADDR1_Disabled (0x0UL)   /*!< Disable                                                              */
67418   #define RADIO_RXADDRESSES_ADDR1_Enabled (0x1UL)    /*!< Enable                                                               */
67419 
67420 /* ADDR2 @Bit 2 : Enable or disable reception on logical address 2 */
67421   #define RADIO_RXADDRESSES_ADDR2_Pos (2UL)          /*!< Position of ADDR2 field.                                             */
67422   #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field.                     */
67423   #define RADIO_RXADDRESSES_ADDR2_Min (0x0UL)        /*!< Min enumerator value of ADDR2 field.                                 */
67424   #define RADIO_RXADDRESSES_ADDR2_Max (0x1UL)        /*!< Max enumerator value of ADDR2 field.                                 */
67425   #define RADIO_RXADDRESSES_ADDR2_Disabled (0x0UL)   /*!< Disable                                                              */
67426   #define RADIO_RXADDRESSES_ADDR2_Enabled (0x1UL)    /*!< Enable                                                               */
67427 
67428 /* ADDR3 @Bit 3 : Enable or disable reception on logical address 3 */
67429   #define RADIO_RXADDRESSES_ADDR3_Pos (3UL)          /*!< Position of ADDR3 field.                                             */
67430   #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field.                     */
67431   #define RADIO_RXADDRESSES_ADDR3_Min (0x0UL)        /*!< Min enumerator value of ADDR3 field.                                 */
67432   #define RADIO_RXADDRESSES_ADDR3_Max (0x1UL)        /*!< Max enumerator value of ADDR3 field.                                 */
67433   #define RADIO_RXADDRESSES_ADDR3_Disabled (0x0UL)   /*!< Disable                                                              */
67434   #define RADIO_RXADDRESSES_ADDR3_Enabled (0x1UL)    /*!< Enable                                                               */
67435 
67436 /* ADDR4 @Bit 4 : Enable or disable reception on logical address 4 */
67437   #define RADIO_RXADDRESSES_ADDR4_Pos (4UL)          /*!< Position of ADDR4 field.                                             */
67438   #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field.                     */
67439   #define RADIO_RXADDRESSES_ADDR4_Min (0x0UL)        /*!< Min enumerator value of ADDR4 field.                                 */
67440   #define RADIO_RXADDRESSES_ADDR4_Max (0x1UL)        /*!< Max enumerator value of ADDR4 field.                                 */
67441   #define RADIO_RXADDRESSES_ADDR4_Disabled (0x0UL)   /*!< Disable                                                              */
67442   #define RADIO_RXADDRESSES_ADDR4_Enabled (0x1UL)    /*!< Enable                                                               */
67443 
67444 /* ADDR5 @Bit 5 : Enable or disable reception on logical address 5 */
67445   #define RADIO_RXADDRESSES_ADDR5_Pos (5UL)          /*!< Position of ADDR5 field.                                             */
67446   #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field.                     */
67447   #define RADIO_RXADDRESSES_ADDR5_Min (0x0UL)        /*!< Min enumerator value of ADDR5 field.                                 */
67448   #define RADIO_RXADDRESSES_ADDR5_Max (0x1UL)        /*!< Max enumerator value of ADDR5 field.                                 */
67449   #define RADIO_RXADDRESSES_ADDR5_Disabled (0x0UL)   /*!< Disable                                                              */
67450   #define RADIO_RXADDRESSES_ADDR5_Enabled (0x1UL)    /*!< Enable                                                               */
67451 
67452 /* ADDR6 @Bit 6 : Enable or disable reception on logical address 6 */
67453   #define RADIO_RXADDRESSES_ADDR6_Pos (6UL)          /*!< Position of ADDR6 field.                                             */
67454   #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field.                     */
67455   #define RADIO_RXADDRESSES_ADDR6_Min (0x0UL)        /*!< Min enumerator value of ADDR6 field.                                 */
67456   #define RADIO_RXADDRESSES_ADDR6_Max (0x1UL)        /*!< Max enumerator value of ADDR6 field.                                 */
67457   #define RADIO_RXADDRESSES_ADDR6_Disabled (0x0UL)   /*!< Disable                                                              */
67458   #define RADIO_RXADDRESSES_ADDR6_Enabled (0x1UL)    /*!< Enable                                                               */
67459 
67460 /* ADDR7 @Bit 7 : Enable or disable reception on logical address 7 */
67461   #define RADIO_RXADDRESSES_ADDR7_Pos (7UL)          /*!< Position of ADDR7 field.                                             */
67462   #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field.                     */
67463   #define RADIO_RXADDRESSES_ADDR7_Min (0x0UL)        /*!< Min enumerator value of ADDR7 field.                                 */
67464   #define RADIO_RXADDRESSES_ADDR7_Max (0x1UL)        /*!< Max enumerator value of ADDR7 field.                                 */
67465   #define RADIO_RXADDRESSES_ADDR7_Disabled (0x0UL)   /*!< Disable                                                              */
67466   #define RADIO_RXADDRESSES_ADDR7_Enabled (0x1UL)    /*!< Enable                                                               */
67467 
67468 
67469 /* RADIO_CRCCNF: CRC configuration */
67470   #define RADIO_CRCCNF_ResetValue (0x00000000UL)     /*!< Reset value of CRCCNF register.                                      */
67471 
67472 /* LEN @Bits 0..1 : CRC length in number of bytes. */
67473   #define RADIO_CRCCNF_LEN_Pos (0UL)                 /*!< Position of LEN field.                                               */
67474   #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field.                                     */
67475   #define RADIO_CRCCNF_LEN_Min (0x1UL)               /*!< Min value of LEN field.                                              */
67476   #define RADIO_CRCCNF_LEN_Max (0x3UL)               /*!< Max size of LEN field.                                               */
67477   #define RADIO_CRCCNF_LEN_Disabled (0x0UL)          /*!< CRC length is zero and CRC calculation is disabled                   */
67478   #define RADIO_CRCCNF_LEN_One (0x1UL)               /*!< CRC length is one byte and CRC calculation is enabled                */
67479   #define RADIO_CRCCNF_LEN_Two (0x2UL)               /*!< CRC length is two bytes and CRC calculation is enabled               */
67480   #define RADIO_CRCCNF_LEN_Three (0x3UL)             /*!< CRC length is three bytes and CRC calculation is enabled             */
67481 
67482 /* SKIPADDR @Bits 8..9 : Include or exclude packet address field out of CRC calculation. */
67483   #define RADIO_CRCCNF_SKIPADDR_Pos (8UL)            /*!< Position of SKIPADDR field.                                          */
67484   #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field.                      */
67485   #define RADIO_CRCCNF_SKIPADDR_Min (0x0UL)          /*!< Min enumerator value of SKIPADDR field.                              */
67486   #define RADIO_CRCCNF_SKIPADDR_Max (0x2UL)          /*!< Max enumerator value of SKIPADDR field.                              */
67487   #define RADIO_CRCCNF_SKIPADDR_Include (0x0UL)      /*!< CRC calculation includes address field                               */
67488   #define RADIO_CRCCNF_SKIPADDR_Skip (0x1UL)         /*!< CRC calculation does not include address field. The CRC calculation
67489                                                           will start at the first byte after the address.*/
67490   #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (0x2UL)   /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after
67491                                                           length field.*/
67492 
67493 
67494 /* RADIO_CRCPOLY: CRC polynomial */
67495   #define RADIO_CRCPOLY_ResetValue (0x00000000UL)    /*!< Reset value of CRCPOLY register.                                     */
67496 
67497 /* CRCPOLY @Bits 0..23 : CRC polynomial */
67498   #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL)            /*!< Position of CRCPOLY field.                                           */
67499   #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field.                  */
67500 
67501 
67502 /* RADIO_CRCINIT: CRC initial value */
67503   #define RADIO_CRCINIT_ResetValue (0x00000000UL)    /*!< Reset value of CRCINIT register.                                     */
67504 
67505 /* CRCINIT @Bits 0..23 : CRC initial value */
67506   #define RADIO_CRCINIT_CRCINIT_Pos (0UL)            /*!< Position of CRCINIT field.                                           */
67507   #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field.                  */
67508 
67509 
67510 /* RADIO_DAB: Device address base segment n */
67511   #define RADIO_DAB_MaxCount (8UL)                   /*!< Max size of DAB[8] array.                                            */
67512   #define RADIO_DAB_MaxIndex (7UL)                   /*!< Max index of DAB[8] array.                                           */
67513   #define RADIO_DAB_MinIndex (0UL)                   /*!< Min index of DAB[8] array.                                           */
67514   #define RADIO_DAB_ResetValue (0x00000000UL)        /*!< Reset value of DAB[8] register.                                      */
67515 
67516 /* DAB @Bits 0..31 : Device address base segment n */
67517   #define RADIO_DAB_DAB_Pos (0UL)                    /*!< Position of DAB field.                                               */
67518   #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field.                                    */
67519 
67520 
67521 /* RADIO_DAP: Device address prefix n */
67522   #define RADIO_DAP_MaxCount (8UL)                   /*!< Max size of DAP[8] array.                                            */
67523   #define RADIO_DAP_MaxIndex (7UL)                   /*!< Max index of DAP[8] array.                                           */
67524   #define RADIO_DAP_MinIndex (0UL)                   /*!< Min index of DAP[8] array.                                           */
67525   #define RADIO_DAP_ResetValue (0x00000000UL)        /*!< Reset value of DAP[8] register.                                      */
67526 
67527 /* DAP @Bits 0..15 : Device address prefix n */
67528   #define RADIO_DAP_DAP_Pos (0UL)                    /*!< Position of DAP field.                                               */
67529   #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field.                                        */
67530 
67531 
67532 /* RADIO_DACNF: Device address match configuration */
67533   #define RADIO_DACNF_ResetValue (0x00000000UL)      /*!< Reset value of DACNF register.                                       */
67534 
67535 /* ENA0 @Bit 0 : Enable or disable device address matching using device address 0 */
67536   #define RADIO_DACNF_ENA0_Pos (0UL)                 /*!< Position of ENA0 field.                                              */
67537   #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field.                                    */
67538   #define RADIO_DACNF_ENA0_Min (0x0UL)               /*!< Min enumerator value of ENA0 field.                                  */
67539   #define RADIO_DACNF_ENA0_Max (0x1UL)               /*!< Max enumerator value of ENA0 field.                                  */
67540   #define RADIO_DACNF_ENA0_Disabled (0x0UL)          /*!< Disabled                                                             */
67541   #define RADIO_DACNF_ENA0_Enabled (0x1UL)           /*!< Enabled                                                              */
67542 
67543 /* ENA1 @Bit 1 : Enable or disable device address matching using device address 1 */
67544   #define RADIO_DACNF_ENA1_Pos (1UL)                 /*!< Position of ENA1 field.                                              */
67545   #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field.                                    */
67546   #define RADIO_DACNF_ENA1_Min (0x0UL)               /*!< Min enumerator value of ENA1 field.                                  */
67547   #define RADIO_DACNF_ENA1_Max (0x1UL)               /*!< Max enumerator value of ENA1 field.                                  */
67548   #define RADIO_DACNF_ENA1_Disabled (0x0UL)          /*!< Disabled                                                             */
67549   #define RADIO_DACNF_ENA1_Enabled (0x1UL)           /*!< Enabled                                                              */
67550 
67551 /* ENA2 @Bit 2 : Enable or disable device address matching using device address 2 */
67552   #define RADIO_DACNF_ENA2_Pos (2UL)                 /*!< Position of ENA2 field.                                              */
67553   #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field.                                    */
67554   #define RADIO_DACNF_ENA2_Min (0x0UL)               /*!< Min enumerator value of ENA2 field.                                  */
67555   #define RADIO_DACNF_ENA2_Max (0x1UL)               /*!< Max enumerator value of ENA2 field.                                  */
67556   #define RADIO_DACNF_ENA2_Disabled (0x0UL)          /*!< Disabled                                                             */
67557   #define RADIO_DACNF_ENA2_Enabled (0x1UL)           /*!< Enabled                                                              */
67558 
67559 /* ENA3 @Bit 3 : Enable or disable device address matching using device address 3 */
67560   #define RADIO_DACNF_ENA3_Pos (3UL)                 /*!< Position of ENA3 field.                                              */
67561   #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field.                                    */
67562   #define RADIO_DACNF_ENA3_Min (0x0UL)               /*!< Min enumerator value of ENA3 field.                                  */
67563   #define RADIO_DACNF_ENA3_Max (0x1UL)               /*!< Max enumerator value of ENA3 field.                                  */
67564   #define RADIO_DACNF_ENA3_Disabled (0x0UL)          /*!< Disabled                                                             */
67565   #define RADIO_DACNF_ENA3_Enabled (0x1UL)           /*!< Enabled                                                              */
67566 
67567 /* ENA4 @Bit 4 : Enable or disable device address matching using device address 4 */
67568   #define RADIO_DACNF_ENA4_Pos (4UL)                 /*!< Position of ENA4 field.                                              */
67569   #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field.                                    */
67570   #define RADIO_DACNF_ENA4_Min (0x0UL)               /*!< Min enumerator value of ENA4 field.                                  */
67571   #define RADIO_DACNF_ENA4_Max (0x1UL)               /*!< Max enumerator value of ENA4 field.                                  */
67572   #define RADIO_DACNF_ENA4_Disabled (0x0UL)          /*!< Disabled                                                             */
67573   #define RADIO_DACNF_ENA4_Enabled (0x1UL)           /*!< Enabled                                                              */
67574 
67575 /* ENA5 @Bit 5 : Enable or disable device address matching using device address 5 */
67576   #define RADIO_DACNF_ENA5_Pos (5UL)                 /*!< Position of ENA5 field.                                              */
67577   #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field.                                    */
67578   #define RADIO_DACNF_ENA5_Min (0x0UL)               /*!< Min enumerator value of ENA5 field.                                  */
67579   #define RADIO_DACNF_ENA5_Max (0x1UL)               /*!< Max enumerator value of ENA5 field.                                  */
67580   #define RADIO_DACNF_ENA5_Disabled (0x0UL)          /*!< Disabled                                                             */
67581   #define RADIO_DACNF_ENA5_Enabled (0x1UL)           /*!< Enabled                                                              */
67582 
67583 /* ENA6 @Bit 6 : Enable or disable device address matching using device address 6 */
67584   #define RADIO_DACNF_ENA6_Pos (6UL)                 /*!< Position of ENA6 field.                                              */
67585   #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field.                                    */
67586   #define RADIO_DACNF_ENA6_Min (0x0UL)               /*!< Min enumerator value of ENA6 field.                                  */
67587   #define RADIO_DACNF_ENA6_Max (0x1UL)               /*!< Max enumerator value of ENA6 field.                                  */
67588   #define RADIO_DACNF_ENA6_Disabled (0x0UL)          /*!< Disabled                                                             */
67589   #define RADIO_DACNF_ENA6_Enabled (0x1UL)           /*!< Enabled                                                              */
67590 
67591 /* ENA7 @Bit 7 : Enable or disable device address matching using device address 7 */
67592   #define RADIO_DACNF_ENA7_Pos (7UL)                 /*!< Position of ENA7 field.                                              */
67593   #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field.                                    */
67594   #define RADIO_DACNF_ENA7_Min (0x0UL)               /*!< Min enumerator value of ENA7 field.                                  */
67595   #define RADIO_DACNF_ENA7_Max (0x1UL)               /*!< Max enumerator value of ENA7 field.                                  */
67596   #define RADIO_DACNF_ENA7_Disabled (0x0UL)          /*!< Disabled                                                             */
67597   #define RADIO_DACNF_ENA7_Enabled (0x1UL)           /*!< Enabled                                                              */
67598 
67599 /* TXADD0 @Bit 8 : TxAdd for device address 0 */
67600   #define RADIO_DACNF_TXADD0_Pos (8UL)               /*!< Position of TXADD0 field.                                            */
67601   #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field.                              */
67602 
67603 /* TXADD1 @Bit 9 : TxAdd for device address 1 */
67604   #define RADIO_DACNF_TXADD1_Pos (9UL)               /*!< Position of TXADD1 field.                                            */
67605   #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field.                              */
67606 
67607 /* TXADD2 @Bit 10 : TxAdd for device address 2 */
67608   #define RADIO_DACNF_TXADD2_Pos (10UL)              /*!< Position of TXADD2 field.                                            */
67609   #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field.                              */
67610 
67611 /* TXADD3 @Bit 11 : TxAdd for device address 3 */
67612   #define RADIO_DACNF_TXADD3_Pos (11UL)              /*!< Position of TXADD3 field.                                            */
67613   #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field.                              */
67614 
67615 /* TXADD4 @Bit 12 : TxAdd for device address 4 */
67616   #define RADIO_DACNF_TXADD4_Pos (12UL)              /*!< Position of TXADD4 field.                                            */
67617   #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field.                              */
67618 
67619 /* TXADD5 @Bit 13 : TxAdd for device address 5 */
67620   #define RADIO_DACNF_TXADD5_Pos (13UL)              /*!< Position of TXADD5 field.                                            */
67621   #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field.                              */
67622 
67623 /* TXADD6 @Bit 14 : TxAdd for device address 6 */
67624   #define RADIO_DACNF_TXADD6_Pos (14UL)              /*!< Position of TXADD6 field.                                            */
67625   #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field.                              */
67626 
67627 /* TXADD7 @Bit 15 : TxAdd for device address 7 */
67628   #define RADIO_DACNF_TXADD7_Pos (15UL)              /*!< Position of TXADD7 field.                                            */
67629   #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field.                              */
67630 
67631 
67632 /* RADIO_BCC: Bit counter compare */
67633   #define RADIO_BCC_ResetValue (0x00000000UL)        /*!< Reset value of BCC register.                                         */
67634 
67635 /* BCC @Bits 0..31 : Bit counter compare */
67636   #define RADIO_BCC_BCC_Pos (0UL)                    /*!< Position of BCC field.                                               */
67637   #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field.                                    */
67638 
67639 
67640 /* RADIO_CTESTATUS: CTEInfo parsed from received packet */
67641   #define RADIO_CTESTATUS_ResetValue (0x00000000UL)  /*!< Reset value of CTESTATUS register.                                   */
67642 
67643 /* CTETIME @Bits 0..4 : CTETime parsed from packet */
67644   #define RADIO_CTESTATUS_CTETIME_Pos (0UL)          /*!< Position of CTETIME field.                                           */
67645   #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field.                  */
67646 
67647 /* RFU @Bit 5 : RFU parsed from packet */
67648   #define RADIO_CTESTATUS_RFU_Pos (5UL)              /*!< Position of RFU field.                                               */
67649   #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field.                               */
67650 
67651 /* CTETYPE @Bits 6..7 : CTEType parsed from packet */
67652   #define RADIO_CTESTATUS_CTETYPE_Pos (6UL)          /*!< Position of CTETYPE field.                                           */
67653   #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field.                   */
67654 
67655 
67656 /* RADIO_MHRMATCHCONF: Search pattern configuration */
67657   #define RADIO_MHRMATCHCONF_ResetValue (0x00000000UL) /*!< Reset value of MHRMATCHCONF register.                              */
67658 
67659 /* MHRMATCHCONF @Bits 0..31 : Search pattern configuration */
67660   #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL)  /*!< Position of MHRMATCHCONF field.                                      */
67661   #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of
67662                                                                             MHRMATCHCONF field.*/
67663 
67664 
67665 /* RADIO_MHRMATCHMASK: Pattern mask */
67666   #define RADIO_MHRMATCHMASK_ResetValue (0x00000000UL) /*!< Reset value of MHRMATCHMASK register.                              */
67667 
67668 /* MHRMATCHMASK @Bits 0..31 : Pattern mask */
67669   #define RADIO_MHRMATCHMASK_MHRMATCHMASK_Pos (0UL)  /*!< Position of MHRMATCHMASK field.                                      */
67670   #define RADIO_MHRMATCHMASK_MHRMATCHMASK_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMASK_MHRMATCHMASK_Pos) /*!< Bit mask of
67671                                                                             MHRMATCHMASK field.*/
67672 
67673 
67674 /* RADIO_SFD: IEEE 802.15.4 start of frame delimiter */
67675   #define RADIO_SFD_ResetValue (0x000000A7UL)        /*!< Reset value of SFD register.                                         */
67676 
67677 /* SFD @Bits 0..7 : IEEE 802.15.4 start of frame delimiter */
67678   #define RADIO_SFD_SFD_Pos (0UL)                    /*!< Position of SFD field.                                               */
67679   #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field.                                          */
67680 
67681 
67682 /* RADIO_CTEINLINECONF: Configuration for CTE inline mode */
67683   #define RADIO_CTEINLINECONF_ResetValue (0x00002800UL) /*!< Reset value of CTEINLINECONF register.                            */
67684 
67685 /* CTEINLINECTRLEN @Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */
67686   #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field.                                */
67687   #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of
67688                                                                             CTEINLINECTRLEN field.*/
67689   #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Min (0x0UL) /*!< Min enumerator value of CTEINLINECTRLEN field.                  */
67690   #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Max (0x1UL) /*!< Max enumerator value of CTEINLINECTRLEN field.                  */
67691   #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (0x1UL) /*!< Parsing of CTEInfo is enabled                               */
67692   #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0x0UL) /*!< Parsing of CTEInfo is disabled                             */
67693 
67694 /* CTEINFOINS1 @Bit 3 : CTEInfo is S1 byte or not */
67695   #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL)  /*!< Position of CTEINFOINS1 field.                                       */
67696   #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1
67697                                                                             field.*/
67698   #define RADIO_CTEINLINECONF_CTEINFOINS1_Min (0x0UL) /*!< Min enumerator value of CTEINFOINS1 field.                          */
67699   #define RADIO_CTEINLINECONF_CTEINFOINS1_Max (0x1UL) /*!< Max enumerator value of CTEINFOINS1 field.                          */
67700   #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (0x1UL) /*!< CTEInfo is in S1 byte (data PDU)                                   */
67701   #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0x0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU)                     */
67702 
67703 /* CTEERRORHANDLING @Bit 4 : Sampling/switching if CRC is not OK */
67704   #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field.                              */
67705   #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of
67706                                                                             CTEERRORHANDLING field.*/
67707   #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Min (0x0UL) /*!< Min enumerator value of CTEERRORHANDLING field.                */
67708   #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Max (0x1UL) /*!< Max enumerator value of CTEERRORHANDLING field.                */
67709   #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (0x1UL) /*!< Sampling and antenna switching also when CRC is not OK         */
67710   #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0x0UL) /*!< No sampling and antenna switching when CRC is not OK            */
67711 
67712 /* CTETIMEVALIDRANGE @Bits 6..7 : Max range of CTETime */
67713   #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field.                            */
67714   #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of
67715                                                                             CTETIMEVALIDRANGE field.*/
67716   #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Min (0x0UL) /*!< Min enumerator value of CTETIMEVALIDRANGE field.              */
67717   #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Max (0x2UL) /*!< Max enumerator value of CTETIMEVALIDRANGE field.              */
67718   #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0x0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger
67719                                                                 han 20*/
67720   #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (0x1UL) /*!< 31 in 8us unit                                                 */
67721   #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (0x2UL) /*!< 63 in 8us unit                                                 */
67722 
67723 /* CTEINLINERXMODE1US @Bits 10..12 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */
67724   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field.                         */
67725   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of
67726                                                                             CTEINLINERXMODE1US field.*/
67727   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Min (0x1UL) /*!< Min enumerator value of CTEINLINERXMODE1US field.            */
67728   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Max (0x6UL) /*!< Max enumerator value of CTEINLINERXMODE1US field.            */
67729   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (0x1UL) /*!< 4us                                                          */
67730   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (0x2UL) /*!< 2us                                                          */
67731   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (0x3UL) /*!< 1us                                                          */
67732   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (0x4UL) /*!< 0.5us                                                      */
67733   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (0x5UL) /*!< 0.25us                                                     */
67734   #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (0x6UL) /*!< 0.125us                                                    */
67735 
67736 /* CTEINLINERXMODE2US @Bits 13..15 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */
67737   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field.                         */
67738   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of
67739                                                                             CTEINLINERXMODE2US field.*/
67740   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Min (0x1UL) /*!< Min enumerator value of CTEINLINERXMODE2US field.            */
67741   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Max (0x6UL) /*!< Max enumerator value of CTEINLINERXMODE2US field.            */
67742   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (0x1UL) /*!< 4us                                                          */
67743   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (0x2UL) /*!< 2us                                                          */
67744   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (0x3UL) /*!< 1us                                                          */
67745   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (0x4UL) /*!< 0.5us                                                      */
67746   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (0x5UL) /*!< 0.25us                                                     */
67747   #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (0x6UL) /*!< 0.125us                                                    */
67748 
67749 /* S0CONF @Bits 16..23 : S0 bit pattern to match */
67750   #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL)      /*!< Position of S0CONF field.                                            */
67751   #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field.             */
67752 
67753 /* S0MASK @Bits 24..31 : S0 bit mask to set which bit to match */
67754   #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL)      /*!< Position of S0MASK field.                                            */
67755   #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field.             */
67756 
67757 
67758 /* RADIO_PACKETPTR: (unspecified) */
67759   #define RADIO_PACKETPTR_ResetValue (0x00000000UL)  /*!< Reset value of PACKETPTR register.                                   */
67760 
67761 /* OFFSET @Bits 0..15 : (unspecified) */
67762   #define RADIO_PACKETPTR_OFFSET_Pos (0UL)           /*!< Position of OFFSET field.                                            */
67763   #define RADIO_PACKETPTR_OFFSET_Msk (0xFFFFUL << RADIO_PACKETPTR_OFFSET_Pos) /*!< Bit mask of OFFSET field.                   */
67764 
67765 /* BASE @Bit 29 : (unspecified) */
67766   #define RADIO_PACKETPTR_BASE_Pos (29UL)            /*!< Position of BASE field.                                              */
67767   #define RADIO_PACKETPTR_BASE_Msk (0x1UL << RADIO_PACKETPTR_BASE_Pos) /*!< Bit mask of BASE field.                            */
67768 
67769 
67770 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
67771 
67772 /* =========================================================================================================================== */
67773 /* ================                                           RAMC                                           ================ */
67774 /* =========================================================================================================================== */
67775 
67776 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
67777 /* ======================================================= Struct RAMC ======================================================= */
67778 /**
67779   * @brief RAM Controller
67780   */
67781   typedef struct {                                   /*!< RAMC Structure                                                       */
67782     __IM uint32_t RESERVED[64];
67783     __IOM uint32_t EVENTS_ERRORFIX;                  /*!< (@ 0x00000100) ECC detected fixable (one bit) error in read data from
67784                                                                          RAM.*/
67785     __IOM uint32_t EVENTS_ERRORNONFIX;               /*!< (@ 0x00000104) ECC detected non-fixable (multiple bits) error in read
67786                                                                          data from RAM.*/
67787     __IM uint32_t RESERVED1[254];
67788     __IOM uint32_t WAITSTATES;                       /*!< (@ 0x00000500) Waitstates for read operations.                       */
67789     __IM uint32_t RESERVED2[63];
67790     __IOM uint32_t SECBASE;                          /*!< (@ 0x00000600) Base address for secure access area.                  */
67791     __IOM uint32_t SECENABLE;                        /*!< (@ 0x00000604) Enable secure access restrictions.                    */
67792   } NRF_RAMC_Type;                                   /*!< Size = 1544 (0x608)                                                  */
67793 
67794 /* RAMC_EVENTS_ERRORFIX: ECC detected fixable (one bit) error in read data from RAM. */
67795   #define RAMC_EVENTS_ERRORFIX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERRORFIX register.                         */
67796 
67797 /* EVENTS_ERRORFIX @Bit 0 : ECC detected fixable (one bit) error in read data from RAM. */
67798   #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Pos (0UL) /*!< Position of EVENTS_ERRORFIX field.                               */
67799   #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Msk (0x1UL << RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Pos) /*!< Bit mask of
67800                                                                             EVENTS_ERRORFIX field.*/
67801   #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERRORFIX field.                 */
67802   #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERRORFIX field.                 */
67803   #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_NotGenerated (0x0UL) /*!< Event not generated                                   */
67804   #define RAMC_EVENTS_ERRORFIX_EVENTS_ERRORFIX_Generated (0x1UL) /*!< Event generated                                          */
67805 
67806 
67807 /* RAMC_EVENTS_ERRORNONFIX: ECC detected non-fixable (multiple bits) error in read data from RAM. */
67808   #define RAMC_EVENTS_ERRORNONFIX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERRORNONFIX register.                   */
67809 
67810 /* EVENTS_ERRORNONFIX @Bit 0 : ECC detected non-fixable (multiple bits) error in read data from RAM. */
67811   #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Pos (0UL) /*!< Position of EVENTS_ERRORNONFIX field.                      */
67812   #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Msk (0x1UL << RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Pos) /*!< Bit mask
67813                                                                             of EVENTS_ERRORNONFIX field.*/
67814   #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERRORNONFIX field.        */
67815   #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERRORNONFIX field.        */
67816   #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_NotGenerated (0x0UL) /*!< Event not generated                             */
67817   #define RAMC_EVENTS_ERRORNONFIX_EVENTS_ERRORNONFIX_Generated (0x1UL) /*!< Event generated                                    */
67818 
67819 
67820 /* RAMC_WAITSTATES: Waitstates for read operations. */
67821   #define RAMC_WAITSTATES_ResetValue (0x00000000UL)  /*!< Reset value of WAITSTATES register.                                  */
67822 
67823 /* WAITSTATES @Bit 0 : Number of waitstates for a read from the RAM. */
67824   #define RAMC_WAITSTATES_WAITSTATES_Pos (0UL)       /*!< Position of WAITSTATES field.                                        */
67825   #define RAMC_WAITSTATES_WAITSTATES_Msk (0x1UL << RAMC_WAITSTATES_WAITSTATES_Pos) /*!< Bit mask of WAITSTATES field.          */
67826   #define RAMC_WAITSTATES_WAITSTATES_Min (0x0UL)     /*!< Min value of WAITSTATES field.                                       */
67827   #define RAMC_WAITSTATES_WAITSTATES_Max (0x1UL)     /*!< Max size of WAITSTATES field.                                        */
67828 
67829 
67830 /* RAMC_SECBASE: Base address for secure access area. */
67831   #define RAMC_SECBASE_ResetValue (0x00000000UL)     /*!< Reset value of SECBASE register.                                     */
67832 
67833 /* ADDR @Bits 0..31 : Base address */
67834   #define RAMC_SECBASE_ADDR_Pos (0UL)                /*!< Position of ADDR field.                                              */
67835   #define RAMC_SECBASE_ADDR_Msk (0xFFFFFFFFUL << RAMC_SECBASE_ADDR_Pos) /*!< Bit mask of ADDR field.                           */
67836 
67837 
67838 /* RAMC_SECENABLE: Enable secure access restrictions. */
67839   #define RAMC_SECENABLE_ResetValue (0x00000000UL)   /*!< Reset value of SECENABLE register.                                   */
67840 
67841 /* ENABLE @Bit 0 : Enable secure access restrictions */
67842   #define RAMC_SECENABLE_ENABLE_Pos (0UL)            /*!< Position of ENABLE field.                                            */
67843   #define RAMC_SECENABLE_ENABLE_Msk (0x1UL << RAMC_SECENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                        */
67844   #define RAMC_SECENABLE_ENABLE_Min (0x0UL)          /*!< Min enumerator value of ENABLE field.                                */
67845   #define RAMC_SECENABLE_ENABLE_Max (0x1UL)          /*!< Max enumerator value of ENABLE field.                                */
67846   #define RAMC_SECENABLE_ENABLE_Disable (0x0UL)      /*!< Secure access restrictions disabled                                  */
67847   #define RAMC_SECENABLE_ENABLE_Enable (0x1UL)       /*!< Secure access restrictions enabled                                   */
67848 
67849 
67850 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
67851 
67852 /* =========================================================================================================================== */
67853 /* ================                                         RESETINFO                                         ================ */
67854 /* =========================================================================================================================== */
67855 
67856 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
67857 
67858 /* ============================================ Struct RESETINFO_RESETREAS_ERROR ============================================= */
67859 /**
67860   * @brief ERROR [RESETINFO_RESETREAS_ERROR] (unspecified)
67861   */
67862 typedef struct {
67863   __IOM uint32_t  STATUS;                            /*!< (@ 0x00000000) Reset error status.                                   */
67864   __IOM uint32_t  ADDRESS;                           /*!< (@ 0x00000004) Reset error address.                                  */
67865 } NRF_RESETINFO_RESETREAS_ERROR_Type;                /*!< Size = 8 (0x008)                                                     */
67866 
67867 /* RESETINFO_RESETREAS_ERROR_STATUS: Reset error status. */
67868   #define RESETINFO_RESETREAS_ERROR_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register.                      */
67869 
67870 /* ERRORSTATUS @Bits 0..3 : Error status */
67871   #define RESETINFO_RESETREAS_ERROR_STATUS_ERRORSTATUS_Pos (0UL) /*!< Position of ERRORSTATUS field.                           */
67872   #define RESETINFO_RESETREAS_ERROR_STATUS_ERRORSTATUS_Msk (0xFUL << RESETINFO_RESETREAS_ERROR_STATUS_ERRORSTATUS_Pos) /*!< Bit
67873                                                                             mask of ERRORSTATUS field.*/
67874 
67875 
67876 /* RESETINFO_RESETREAS_ERROR_ADDRESS: Reset error address. */
67877   #define RESETINFO_RESETREAS_ERROR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register.                    */
67878 
67879 /* ERRORADDRESS @Bits 0..31 : Error address */
67880   #define RESETINFO_RESETREAS_ERROR_ADDRESS_ERRORADDRESS_Pos (0UL) /*!< Position of ERRORADDRESS field.                        */
67881   #define RESETINFO_RESETREAS_ERROR_ADDRESS_ERRORADDRESS_Msk (0xFFFFFFFFUL << RESETINFO_RESETREAS_ERROR_ADDRESS_ERRORADDRESS_Pos)
67882                                                                             /*!< Bit mask of ERRORADDRESS field.*/
67883 
67884 
67885 
67886 /* =============================================== Struct RESETINFO_RESETREAS ================================================ */
67887 /**
67888   * @brief RESETREAS [RESETINFO_RESETREAS] (unspecified)
67889   */
67890 typedef struct {
67891   __IOM uint32_t  GLOBAL;                            /*!< (@ 0x00000000) Global reset reason.                                  */
67892   __IOM uint32_t  LOCAL;                             /*!< (@ 0x00000004) Local reset reason.                                   */
67893   __IOM NRF_RESETINFO_RESETREAS_ERROR_Type ERROR;    /*!< (@ 0x00000008) (unspecified)                                         */
67894 } NRF_RESETINFO_RESETREAS_Type;                      /*!< Size = 16 (0x010)                                                    */
67895 
67896 /* RESETINFO_RESETREAS_GLOBAL: Global reset reason. */
67897   #define RESETINFO_RESETREAS_GLOBAL_ResetValue (0x00000000UL) /*!< Reset value of GLOBAL register.                            */
67898 
67899 /* RESETPOR @Bit 0 : Reset from power on reset. */
67900   #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Pos (0UL) /*!< Position of RESETPOR field.                                       */
67901   #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_RESETPOR_Pos) /*!< Bit mask of RESETPOR
67902                                                                             field.*/
67903   #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Min (0x0UL) /*!< Min enumerator value of RESETPOR field.                         */
67904   #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Max (0x1UL) /*!< Max enumerator value of RESETPOR field.                         */
67905   #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_NotDetected (0x0UL) /*!< Not detected                                            */
67906   #define RESETINFO_RESETREAS_GLOBAL_RESETPOR_Detected (0x1UL) /*!< Detected                                                   */
67907 
67908 /* RESETPIN @Bit 1 : Reset from pin reset detected. */
67909   #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Pos (1UL) /*!< Position of RESETPIN field.                                       */
67910   #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_RESETPIN_Pos) /*!< Bit mask of RESETPIN
67911                                                                             field.*/
67912   #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Min (0x0UL) /*!< Min enumerator value of RESETPIN field.                         */
67913   #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Max (0x1UL) /*!< Max enumerator value of RESETPIN field.                         */
67914   #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_NotDetected (0x0UL) /*!< Not detected                                            */
67915   #define RESETINFO_RESETREAS_GLOBAL_RESETPIN_Detected (0x1UL) /*!< Detected                                                   */
67916 
67917 /* DOG @Bit 2 : Reset from the SysCtrl watchdog timer detected. */
67918   #define RESETINFO_RESETREAS_GLOBAL_DOG_Pos (2UL)   /*!< Position of DOG field.                                               */
67919   #define RESETINFO_RESETREAS_GLOBAL_DOG_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_DOG_Pos) /*!< Bit mask of DOG field.         */
67920   #define RESETINFO_RESETREAS_GLOBAL_DOG_Min (0x0UL) /*!< Min enumerator value of DOG field.                                   */
67921   #define RESETINFO_RESETREAS_GLOBAL_DOG_Max (0x1UL) /*!< Max enumerator value of DOG field.                                   */
67922   #define RESETINFO_RESETREAS_GLOBAL_DOG_NotDetected (0x0UL) /*!< Not detected                                                 */
67923   #define RESETINFO_RESETREAS_GLOBAL_DOG_Detected (0x1UL) /*!< Detected                                                        */
67924 
67925 /* CTRLAP @Bit 3 : Reset from CTRL-AP detected. */
67926   #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Pos (3UL) /*!< Position of CTRLAP field.                                           */
67927   #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_CTRLAP_Pos) /*!< Bit mask of CTRLAP field.*/
67928   #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Min (0x0UL) /*!< Min enumerator value of CTRLAP field.                             */
67929   #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Max (0x1UL) /*!< Max enumerator value of CTRLAP field.                             */
67930   #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_NotDetected (0x0UL) /*!< Not detected                                              */
67931   #define RESETINFO_RESETREAS_GLOBAL_CTRLAP_Detected (0x1UL) /*!< Detected                                                     */
67932 
67933 /* SECSREQ @Bit 4 : Reset due to secure domain system reset request. */
67934   #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Pos (4UL) /*!< Position of SECSREQ field.                                         */
67935   #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECSREQ_Pos) /*!< Bit mask of SECSREQ
67936                                                                             field.*/
67937   #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Min (0x0UL) /*!< Min enumerator value of SECSREQ field.                           */
67938   #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Max (0x1UL) /*!< Max enumerator value of SECSREQ field.                           */
67939   #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_NotDetected (0x0UL) /*!< Not detected                                             */
67940   #define RESETINFO_RESETREAS_GLOBAL_SECSREQ_Detected (0x1UL) /*!< Detected                                                    */
67941 
67942 /* SECWDT @Bit 5 : Reset due to secure domain watchdog timer detected. */
67943   #define RESETINFO_RESETREAS_GLOBAL_SECWDT_Pos (5UL) /*!< Position of SECWDT field.                                           */
67944   #define RESETINFO_RESETREAS_GLOBAL_SECWDT_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECWDT_Pos) /*!< Bit mask of SECWDT field.*/
67945   #define RESETINFO_RESETREAS_GLOBAL_SECWDT_Min (0x0UL) /*!< Min enumerator value of SECWDT field.                             */
67946   #define RESETINFO_RESETREAS_GLOBAL_SECWDT_Max (0x1UL) /*!< Max enumerator value of SECWDT field.                             */
67947   #define RESETINFO_RESETREAS_GLOBAL_SECWDT_NotDetected (0x0UL) /*!< Not detected                                              */
67948   #define RESETINFO_RESETREAS_GLOBAL_SECWDT_Detected (0x1UL) /*!< Detected                                                     */
67949 
67950 /* SECLOCKUP @Bit 6 : Reset due to secure domain lockup. */
67951   #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Pos (6UL) /*!< Position of SECLOCKUP field.                                     */
67952   #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Pos) /*!< Bit mask of
67953                                                                             SECLOCKUP field.*/
67954   #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Min (0x0UL) /*!< Min enumerator value of SECLOCKUP field.                       */
67955   #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Max (0x1UL) /*!< Max enumerator value of SECLOCKUP field.                       */
67956   #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_NotDetected (0x0UL) /*!< Not detected                                           */
67957   #define RESETINFO_RESETREAS_GLOBAL_SECLOCKUP_Detected (0x1UL) /*!< Detected                                                  */
67958 
67959 /* SECTAMPER @Bit 7 : Reset due to secure domain tamper detected */
67960   #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Pos (7UL) /*!< Position of SECTAMPER field.                                     */
67961   #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Pos) /*!< Bit mask of
67962                                                                             SECTAMPER field.*/
67963   #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Min (0x0UL) /*!< Min enumerator value of SECTAMPER field.                       */
67964   #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Max (0x1UL) /*!< Max enumerator value of SECTAMPER field.                       */
67965   #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_NotDetected (0x0UL) /*!< Not detected                                           */
67966   #define RESETINFO_RESETREAS_GLOBAL_SECTAMPER_Detected (0x1UL) /*!< Detected                                                  */
67967 
67968 /* OFF @Bit 8 : Reset due to wakeup from System OFF mode when wakeup is triggered by DETECT signal from GPIO. */
67969   #define RESETINFO_RESETREAS_GLOBAL_OFF_Pos (8UL)   /*!< Position of OFF field.                                               */
67970   #define RESETINFO_RESETREAS_GLOBAL_OFF_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_OFF_Pos) /*!< Bit mask of OFF field.         */
67971   #define RESETINFO_RESETREAS_GLOBAL_OFF_Min (0x0UL) /*!< Min enumerator value of OFF field.                                   */
67972   #define RESETINFO_RESETREAS_GLOBAL_OFF_Max (0x1UL) /*!< Max enumerator value of OFF field.                                   */
67973   #define RESETINFO_RESETREAS_GLOBAL_OFF_NotDetected (0x0UL) /*!< Not detected                                                 */
67974   #define RESETINFO_RESETREAS_GLOBAL_OFF_Detected (0x1UL) /*!< Detected                                                        */
67975 
67976 /* LPCOMP @Bit 9 : Reset due to wakeup from System OFF mode when wakeup is triggered by LPCOMP (Low Power Comparator). */
67977   #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Pos (9UL) /*!< Position of LPCOMP field.                                           */
67978   #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_LPCOMP_Pos) /*!< Bit mask of LPCOMP field.*/
67979   #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Min (0x0UL) /*!< Min enumerator value of LPCOMP field.                             */
67980   #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Max (0x1UL) /*!< Max enumerator value of LPCOMP field.                             */
67981   #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_NotDetected (0x0UL) /*!< Not detected                                              */
67982   #define RESETINFO_RESETREAS_GLOBAL_LPCOMP_Detected (0x1UL) /*!< Detected                                                     */
67983 
67984 /* DIF @Bit 10 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode. */
67985   #define RESETINFO_RESETREAS_GLOBAL_DIF_Pos (10UL)  /*!< Position of DIF field.                                               */
67986   #define RESETINFO_RESETREAS_GLOBAL_DIF_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_DIF_Pos) /*!< Bit mask of DIF field.         */
67987   #define RESETINFO_RESETREAS_GLOBAL_DIF_Min (0x0UL) /*!< Min enumerator value of DIF field.                                   */
67988   #define RESETINFO_RESETREAS_GLOBAL_DIF_Max (0x1UL) /*!< Max enumerator value of DIF field.                                   */
67989   #define RESETINFO_RESETREAS_GLOBAL_DIF_NotDetected (0x0UL) /*!< Not detected                                                 */
67990   #define RESETINFO_RESETREAS_GLOBAL_DIF_Detected (0x1UL) /*!< Detected                                                        */
67991 
67992 /* GRTC @Bit 11 : Reset due to wakeup from System OFF mode when wakeup is triggered by GRTC interrupt. */
67993   #define RESETINFO_RESETREAS_GLOBAL_GRTC_Pos (11UL) /*!< Position of GRTC field.                                              */
67994   #define RESETINFO_RESETREAS_GLOBAL_GRTC_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_GRTC_Pos) /*!< Bit mask of GRTC field.      */
67995   #define RESETINFO_RESETREAS_GLOBAL_GRTC_Min (0x0UL) /*!< Min enumerator value of GRTC field.                                 */
67996   #define RESETINFO_RESETREAS_GLOBAL_GRTC_Max (0x1UL) /*!< Max enumerator value of GRTC field.                                 */
67997   #define RESETINFO_RESETREAS_GLOBAL_GRTC_NotDetected (0x0UL) /*!< Not detected                                                */
67998   #define RESETINFO_RESETREAS_GLOBAL_GRTC_Detected (0x1UL) /*!< Detected                                                       */
67999 
68000 /* NFC @Bit 12 : Reset due to wakeup from System OFF mode when wakeup is triggered by NFC field detection in sense mode. */
68001   #define RESETINFO_RESETREAS_GLOBAL_NFC_Pos (12UL)  /*!< Position of NFC field.                                               */
68002   #define RESETINFO_RESETREAS_GLOBAL_NFC_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_NFC_Pos) /*!< Bit mask of NFC field.         */
68003   #define RESETINFO_RESETREAS_GLOBAL_NFC_Min (0x0UL) /*!< Min enumerator value of NFC field.                                   */
68004   #define RESETINFO_RESETREAS_GLOBAL_NFC_Max (0x1UL) /*!< Max enumerator value of NFC field.                                   */
68005   #define RESETINFO_RESETREAS_GLOBAL_NFC_NotDetected (0x0UL) /*!< Not detected                                                 */
68006   #define RESETINFO_RESETREAS_GLOBAL_NFC_Detected (0x1UL) /*!< Detected                                                        */
68007 
68008 /* VUSB @Bit 13 : Reset after wakeup from System OFF mode due to VBUS rising into valid range. */
68009   #define RESETINFO_RESETREAS_GLOBAL_VUSB_Pos (13UL) /*!< Position of VUSB field.                                              */
68010   #define RESETINFO_RESETREAS_GLOBAL_VUSB_Msk (0x1UL << RESETINFO_RESETREAS_GLOBAL_VUSB_Pos) /*!< Bit mask of VUSB field.      */
68011   #define RESETINFO_RESETREAS_GLOBAL_VUSB_Min (0x0UL) /*!< Min enumerator value of VUSB field.                                 */
68012   #define RESETINFO_RESETREAS_GLOBAL_VUSB_Max (0x1UL) /*!< Max enumerator value of VUSB field.                                 */
68013   #define RESETINFO_RESETREAS_GLOBAL_VUSB_NotDetected (0x0UL) /*!< Not detected                                                */
68014   #define RESETINFO_RESETREAS_GLOBAL_VUSB_Detected (0x1UL) /*!< Detected                                                       */
68015 
68016 
68017 /* RESETINFO_RESETREAS_LOCAL: Local reset reason. */
68018   #define RESETINFO_RESETREAS_LOCAL_ResetValue (0x00000000UL) /*!< Reset value of LOCAL register.                              */
68019 
68020 /* DOG @Bit 0 : Reset from the local watchdog timer detected */
68021   #define RESETINFO_RESETREAS_LOCAL_DOG_Pos (0UL)    /*!< Position of DOG field.                                               */
68022   #define RESETINFO_RESETREAS_LOCAL_DOG_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_DOG_Pos) /*!< Bit mask of DOG field.           */
68023   #define RESETINFO_RESETREAS_LOCAL_DOG_Min (0x0UL)  /*!< Min enumerator value of DOG field.                                   */
68024   #define RESETINFO_RESETREAS_LOCAL_DOG_Max (0x1UL)  /*!< Max enumerator value of DOG field.                                   */
68025   #define RESETINFO_RESETREAS_LOCAL_DOG_NotDetected (0x0UL) /*!< Not detected                                                  */
68026   #define RESETINFO_RESETREAS_LOCAL_DOG_Detected (0x1UL) /*!< Detected                                                         */
68027 
68028 /* DOGNS @Bit 1 : Reset from the local non-secure watchdog timer detected */
68029   #define RESETINFO_RESETREAS_LOCAL_DOGNS_Pos (1UL)  /*!< Position of DOGNS field.                                             */
68030   #define RESETINFO_RESETREAS_LOCAL_DOGNS_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_DOGNS_Pos) /*!< Bit mask of DOGNS field.     */
68031   #define RESETINFO_RESETREAS_LOCAL_DOGNS_Min (0x0UL) /*!< Min enumerator value of DOGNS field.                                */
68032   #define RESETINFO_RESETREAS_LOCAL_DOGNS_Max (0x1UL) /*!< Max enumerator value of DOGNS field.                                */
68033   #define RESETINFO_RESETREAS_LOCAL_DOGNS_NotDetected (0x0UL) /*!< Not detected                                                */
68034   #define RESETINFO_RESETREAS_LOCAL_DOGNS_Detected (0x1UL) /*!< Detected                                                       */
68035 
68036 /* SREQ @Bit 2 : Reset from the local soft reset request detected. */
68037   #define RESETINFO_RESETREAS_LOCAL_SREQ_Pos (2UL)   /*!< Position of SREQ field.                                              */
68038   #define RESETINFO_RESETREAS_LOCAL_SREQ_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_SREQ_Pos) /*!< Bit mask of SREQ field.        */
68039   #define RESETINFO_RESETREAS_LOCAL_SREQ_Min (0x0UL) /*!< Min enumerator value of SREQ field.                                  */
68040   #define RESETINFO_RESETREAS_LOCAL_SREQ_Max (0x1UL) /*!< Max enumerator value of SREQ field.                                  */
68041   #define RESETINFO_RESETREAS_LOCAL_SREQ_NotDetected (0x0UL) /*!< Not detected                                                 */
68042   #define RESETINFO_RESETREAS_LOCAL_SREQ_Detected (0x1UL) /*!< Detected                                                        */
68043 
68044 /* LOCKUP @Bit 3 : Reset from local CPU lockup detected */
68045   #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field.                                            */
68046   #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_LOCKUP_Pos) /*!< Bit mask of LOCKUP field.  */
68047   #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Min (0x0UL) /*!< Min enumerator value of LOCKUP field.                              */
68048   #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Max (0x1UL) /*!< Max enumerator value of LOCKUP field.                              */
68049   #define RESETINFO_RESETREAS_LOCAL_LOCKUP_NotDetected (0x0UL) /*!< Not detected                                               */
68050   #define RESETINFO_RESETREAS_LOCAL_LOCKUP_Detected (0x1UL) /*!< Detected                                                      */
68051 
68052 /* CROSSDOMAIN @Bit 4 : Reset due to cross domain reset source. */
68053   #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Pos (4UL) /*!< Position of CROSSDOMAIN field.                                  */
68054   #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Pos) /*!< Bit mask of
68055                                                                             CROSSDOMAIN field.*/
68056   #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Min (0x0UL) /*!< Min enumerator value of CROSSDOMAIN field.                    */
68057   #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Max (0x1UL) /*!< Max enumerator value of CROSSDOMAIN field.                    */
68058   #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_NotDetected (0x0UL) /*!< Not detected                                          */
68059   #define RESETINFO_RESETREAS_LOCAL_CROSSDOMAIN_Detected (0x1UL) /*!< Detected                                                 */
68060 
68061 /* UNRETAINEDWAKE @Bit 5 : Reset due to wake from unretained state. */
68062   #define RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Pos (5UL) /*!< Position of UNRETAINEDWAKE field.                            */
68063   #define RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Msk (0x1UL << RESETINFO_RESETREAS_LOCAL_UNRETAINEDWAKE_Pos) /*!< Bit mask of
68064                                                                             UNRETAINEDWAKE field.*/
68065 
68066 
68067 /* ==================================================== Struct RESETINFO ===================================================== */
68068 /**
68069   * @brief RESETINFO
68070   */
68071   typedef struct {                                   /*!< RESETINFO Structure                                                  */
68072     __IM uint32_t RESERVED[296];
68073     __IOM NRF_RESETINFO_RESETREAS_Type RESETREAS;    /*!< (@ 0x000004A0) (unspecified)                                         */
68074     __IM uint32_t RESERVED1[4];
68075     __IOM uint32_t RESTOREVALID;                     /*!< (@ 0x000004C0) Valid restore image is present in RAM.                */
68076   } NRF_RESETINFO_Type;                              /*!< Size = 1220 (0x4C4)                                                  */
68077 
68078 /* RESETINFO_RESTOREVALID: Valid restore image is present in RAM. */
68079   #define RESETINFO_RESTOREVALID_ResetValue (0x00000000UL) /*!< Reset value of RESTOREVALID register.                          */
68080 
68081 /* RESTOREVALID @Bit 0 : Valid restore image is present in RAM. */
68082   #define RESETINFO_RESTOREVALID_RESTOREVALID_Pos (0UL) /*!< Position of RESTOREVALID field.                                   */
68083   #define RESETINFO_RESTOREVALID_RESTOREVALID_Msk (0x1UL << RESETINFO_RESTOREVALID_RESTOREVALID_Pos) /*!< Bit mask of
68084                                                                             RESTOREVALID field.*/
68085   #define RESETINFO_RESTOREVALID_RESTOREVALID_Min (0x0UL) /*!< Min enumerator value of RESTOREVALID field.                     */
68086   #define RESETINFO_RESTOREVALID_RESTOREVALID_Max (0x1UL) /*!< Max enumerator value of RESTOREVALID field.                     */
68087   #define RESETINFO_RESTOREVALID_RESTOREVALID_NotPreset (0x0UL) /*!< Not present                                               */
68088   #define RESETINFO_RESTOREVALID_RESTOREVALID_Present (0x1UL) /*!< Present                                                     */
68089 
68090 
68091 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
68092 
68093 /* =========================================================================================================================== */
68094 /* ================                                            RTC                                            ================ */
68095 /* =========================================================================================================================== */
68096 
68097 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
68098 /* ======================================================= Struct RTC ======================================================== */
68099 /**
68100   * @brief Real-time counter
68101   */
68102   typedef struct {                                   /*!< RTC Structure                                                        */
68103     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start RTC counter                                     */
68104     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop RTC counter                                      */
68105     __OM uint32_t TASKS_CLEAR;                       /*!< (@ 0x00000008) Clear RTC counter                                     */
68106     __OM uint32_t TASKS_TRIGOVRFLW;                  /*!< (@ 0x0000000C) Set counter to: maximum value - 0xF                   */
68107     __IM uint32_t RESERVED[12];
68108     __OM uint32_t TASKS_CAPTURE[8];                  /*!< (@ 0x00000040) Capture RTC counter to CC[n] register                 */
68109     __IM uint32_t RESERVED1[8];
68110     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
68111     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
68112     __IOM uint32_t SUBSCRIBE_CLEAR;                  /*!< (@ 0x00000088) Subscribe configuration for task CLEAR                */
68113     __IOM uint32_t SUBSCRIBE_TRIGOVRFLW;             /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW           */
68114     __IM uint32_t RESERVED2[12];
68115     __IOM uint32_t SUBSCRIBE_CAPTURE[8];             /*!< (@ 0x000000C0) Subscribe configuration for task CAPTURE[n]           */
68116     __IM uint32_t RESERVED3[8];
68117     __IOM uint32_t EVENTS_TICK;                      /*!< (@ 0x00000100) Event on counter increment                            */
68118     __IOM uint32_t EVENTS_OVRFLW;                    /*!< (@ 0x00000104) Event on counter overflow                             */
68119     __IM uint32_t RESERVED4[14];
68120     __IOM uint32_t EVENTS_COMPARE[8];                /*!< (@ 0x00000140) Compare event on CC[n] match                          */
68121     __IM uint32_t RESERVED5[8];
68122     __IOM uint32_t PUBLISH_TICK;                     /*!< (@ 0x00000180) Publish configuration for event TICK                  */
68123     __IOM uint32_t PUBLISH_OVRFLW;                   /*!< (@ 0x00000184) Publish configuration for event OVRFLW                */
68124     __IM uint32_t RESERVED6[14];
68125     __IOM uint32_t PUBLISH_COMPARE[8];               /*!< (@ 0x000001C0) Publish configuration for event COMPARE[n]            */
68126     __IM uint32_t RESERVED7[8];
68127     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
68128     __IM uint32_t RESERVED8[64];
68129     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
68130     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
68131     __IM uint32_t RESERVED9[13];
68132     __IOM uint32_t EVTEN;                            /*!< (@ 0x00000340) Enable or disable event routing                       */
68133     __IOM uint32_t EVTENSET;                         /*!< (@ 0x00000344) Enable event routing                                  */
68134     __IOM uint32_t EVTENCLR;                         /*!< (@ 0x00000348) Disable event routing                                 */
68135     __IM uint32_t RESERVED10[110];
68136     __IM uint32_t COUNTER;                           /*!< (@ 0x00000504) Current counter value                                 */
68137     __IOM uint32_t PRESCALER;                        /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 /
68138                                                                          (PRESCALER + 1)). Must be written when RTC is stopped.*/
68139     __IM uint32_t RESERVED11[13];
68140     __IOM uint32_t CC[8];                            /*!< (@ 0x00000540) Compare register n                                    */
68141   } NRF_RTC_Type;                                    /*!< Size = 1376 (0x560)                                                  */
68142 
68143 /* RTC_TASKS_START: Start RTC counter */
68144   #define RTC_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
68145 
68146 /* TASKS_START @Bit 0 : Start RTC counter */
68147   #define RTC_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
68148   #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
68149   #define RTC_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
68150   #define RTC_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
68151   #define RTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
68152 
68153 
68154 /* RTC_TASKS_STOP: Stop RTC counter */
68155   #define RTC_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
68156 
68157 /* TASKS_STOP @Bit 0 : Stop RTC counter */
68158   #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
68159   #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
68160   #define RTC_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
68161   #define RTC_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
68162   #define RTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
68163 
68164 
68165 /* RTC_TASKS_CLEAR: Clear RTC counter */
68166   #define RTC_TASKS_CLEAR_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_CLEAR register.                                 */
68167 
68168 /* TASKS_CLEAR @Bit 0 : Clear RTC counter */
68169   #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)      /*!< Position of TASKS_CLEAR field.                                       */
68170   #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field.       */
68171   #define RTC_TASKS_CLEAR_TASKS_CLEAR_Min (0x1UL)    /*!< Min enumerator value of TASKS_CLEAR field.                           */
68172   #define RTC_TASKS_CLEAR_TASKS_CLEAR_Max (0x1UL)    /*!< Max enumerator value of TASKS_CLEAR field.                           */
68173   #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task                                                        */
68174 
68175 
68176 /* RTC_TASKS_TRIGOVRFLW: Set counter to: maximum value - 0xF */
68177   #define RTC_TASKS_TRIGOVRFLW_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGOVRFLW register.                        */
68178 
68179 /* TASKS_TRIGOVRFLW @Bit 0 : Set counter to: maximum value - 0xF */
68180   #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field.                             */
68181   #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of
68182                                                                             TASKS_TRIGOVRFLW field.*/
68183   #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGOVRFLW field.               */
68184   #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGOVRFLW field.               */
68185   #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (0x1UL) /*!< Trigger task                                              */
68186 
68187 
68188 /* RTC_TASKS_CAPTURE: Capture RTC counter to CC[n] register */
68189   #define RTC_TASKS_CAPTURE_MaxCount (8UL)           /*!< Max size of TASKS_CAPTURE[8] array.                                  */
68190   #define RTC_TASKS_CAPTURE_MaxIndex (7UL)           /*!< Max index of TASKS_CAPTURE[8] array.                                 */
68191   #define RTC_TASKS_CAPTURE_MinIndex (0UL)           /*!< Min index of TASKS_CAPTURE[8] array.                                 */
68192   #define RTC_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[8] register.                           */
68193 
68194 /* TASKS_CAPTURE @Bit 0 : Capture RTC counter to CC[n] register */
68195   #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL)  /*!< Position of TASKS_CAPTURE field.                                     */
68196   #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE
68197                                                                             field.*/
68198   #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field.                        */
68199   #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field.                        */
68200   #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task                                                    */
68201 
68202 
68203 /* RTC_SUBSCRIBE_START: Subscribe configuration for task START */
68204   #define RTC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */
68205 
68206 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
68207   #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
68208   #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
68209   #define RTC_SUBSCRIBE_START_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
68210   #define RTC_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
68211 
68212 /* EN @Bit 31 : (unspecified) */
68213   #define RTC_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
68214   #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
68215   #define RTC_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
68216   #define RTC_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
68217   #define RTC_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
68218   #define RTC_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
68219 
68220 
68221 /* RTC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
68222   #define RTC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */
68223 
68224 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
68225   #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
68226   #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
68227   #define RTC_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
68228   #define RTC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
68229 
68230 /* EN @Bit 31 : (unspecified) */
68231   #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
68232   #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
68233   #define RTC_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
68234   #define RTC_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
68235   #define RTC_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
68236   #define RTC_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
68237 
68238 
68239 /* RTC_SUBSCRIBE_CLEAR: Subscribe configuration for task CLEAR */
68240   #define RTC_SUBSCRIBE_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLEAR register.                          */
68241 
68242 /* CHIDX @Bits 0..7 : DPPI channel that task CLEAR will subscribe to */
68243   #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
68244   #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
68245   #define RTC_SUBSCRIBE_CLEAR_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
68246   #define RTC_SUBSCRIBE_CLEAR_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
68247 
68248 /* EN @Bit 31 : (unspecified) */
68249   #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL)          /*!< Position of EN field.                                                */
68250   #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field.                          */
68251   #define RTC_SUBSCRIBE_CLEAR_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
68252   #define RTC_SUBSCRIBE_CLEAR_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
68253   #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
68254   #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
68255 
68256 
68257 /* RTC_SUBSCRIBE_TRIGOVRFLW: Subscribe configuration for task TRIGOVRFLW */
68258   #define RTC_SUBSCRIBE_TRIGOVRFLW_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGOVRFLW register.                */
68259 
68260 /* CHIDX @Bits 0..7 : DPPI channel that task TRIGOVRFLW will subscribe to */
68261   #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
68262   #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
68263   #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
68264   #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
68265 
68266 /* EN @Bit 31 : (unspecified) */
68267   #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL)     /*!< Position of EN field.                                                */
68268   #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field.                */
68269   #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
68270   #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
68271   #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
68272   #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */
68273 
68274 
68275 /* RTC_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */
68276   #define RTC_SUBSCRIBE_CAPTURE_MaxCount (8UL)       /*!< Max size of SUBSCRIBE_CAPTURE[8] array.                              */
68277   #define RTC_SUBSCRIBE_CAPTURE_MaxIndex (7UL)       /*!< Max index of SUBSCRIBE_CAPTURE[8] array.                             */
68278   #define RTC_SUBSCRIBE_CAPTURE_MinIndex (0UL)       /*!< Min index of SUBSCRIBE_CAPTURE[8] array.                             */
68279   #define RTC_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[8] register.                   */
68280 
68281 /* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */
68282   #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
68283   #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
68284   #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
68285   #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
68286 
68287 /* EN @Bit 31 : (unspecified) */
68288   #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
68289   #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field.                      */
68290   #define RTC_SUBSCRIBE_CAPTURE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
68291   #define RTC_SUBSCRIBE_CAPTURE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
68292   #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
68293   #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
68294 
68295 
68296 /* RTC_EVENTS_TICK: Event on counter increment */
68297   #define RTC_EVENTS_TICK_ResetValue (0x00000000UL)  /*!< Reset value of EVENTS_TICK register.                                 */
68298 
68299 /* EVENTS_TICK @Bit 0 : Event on counter increment */
68300   #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL)      /*!< Position of EVENTS_TICK field.                                       */
68301   #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field.       */
68302   #define RTC_EVENTS_TICK_EVENTS_TICK_Min (0x0UL)    /*!< Min enumerator value of EVENTS_TICK field.                           */
68303   #define RTC_EVENTS_TICK_EVENTS_TICK_Max (0x1UL)    /*!< Max enumerator value of EVENTS_TICK field.                           */
68304   #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0x0UL) /*!< Event not generated                                            */
68305   #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (0x1UL) /*!< Event generated                                                   */
68306 
68307 
68308 /* RTC_EVENTS_OVRFLW: Event on counter overflow */
68309   #define RTC_EVENTS_OVRFLW_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_OVRFLW register.                              */
68310 
68311 /* EVENTS_OVRFLW @Bit 0 : Event on counter overflow */
68312   #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL)  /*!< Position of EVENTS_OVRFLW field.                                     */
68313   #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW
68314                                                                             field.*/
68315   #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Min (0x0UL) /*!< Min enumerator value of EVENTS_OVRFLW field.                        */
68316   #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Max (0x1UL) /*!< Max enumerator value of EVENTS_OVRFLW field.                        */
68317   #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0x0UL) /*!< Event not generated                                        */
68318   #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (0x1UL) /*!< Event generated                                               */
68319 
68320 
68321 /* RTC_EVENTS_COMPARE: Compare event on CC[n] match */
68322   #define RTC_EVENTS_COMPARE_MaxCount (8UL)          /*!< Max size of EVENTS_COMPARE[8] array.                                 */
68323   #define RTC_EVENTS_COMPARE_MaxIndex (7UL)          /*!< Max index of EVENTS_COMPARE[8] array.                                */
68324   #define RTC_EVENTS_COMPARE_MinIndex (0UL)          /*!< Min index of EVENTS_COMPARE[8] array.                                */
68325   #define RTC_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[8] register.                         */
68326 
68327 /* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */
68328   #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field.                                   */
68329   #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE
68330                                                                             field.*/
68331   #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field.                     */
68332   #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field.                     */
68333   #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated                                      */
68334   #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated                                             */
68335 
68336 
68337 /* RTC_PUBLISH_TICK: Publish configuration for event TICK */
68338   #define RTC_PUBLISH_TICK_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TICK register.                                */
68339 
68340 /* CHIDX @Bits 0..7 : DPPI channel that event TICK will publish to */
68341   #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL)           /*!< Position of CHIDX field.                                             */
68342   #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field.                      */
68343   #define RTC_PUBLISH_TICK_CHIDX_Min (0x0UL)         /*!< Min value of CHIDX field.                                            */
68344   #define RTC_PUBLISH_TICK_CHIDX_Max (0xFFUL)        /*!< Max size of CHIDX field.                                             */
68345 
68346 /* EN @Bit 31 : (unspecified) */
68347   #define RTC_PUBLISH_TICK_EN_Pos (31UL)             /*!< Position of EN field.                                                */
68348   #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field.                                */
68349   #define RTC_PUBLISH_TICK_EN_Min (0x0UL)            /*!< Min enumerator value of EN field.                                    */
68350   #define RTC_PUBLISH_TICK_EN_Max (0x1UL)            /*!< Max enumerator value of EN field.                                    */
68351   #define RTC_PUBLISH_TICK_EN_Disabled (0x0UL)       /*!< Disable publishing                                                   */
68352   #define RTC_PUBLISH_TICK_EN_Enabled (0x1UL)        /*!< Enable publishing                                                    */
68353 
68354 
68355 /* RTC_PUBLISH_OVRFLW: Publish configuration for event OVRFLW */
68356   #define RTC_PUBLISH_OVRFLW_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_OVRFLW register.                            */
68357 
68358 /* CHIDX @Bits 0..7 : DPPI channel that event OVRFLW will publish to */
68359   #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
68360   #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
68361   #define RTC_PUBLISH_OVRFLW_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
68362   #define RTC_PUBLISH_OVRFLW_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
68363 
68364 /* EN @Bit 31 : (unspecified) */
68365   #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL)           /*!< Position of EN field.                                                */
68366   #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field.                            */
68367   #define RTC_PUBLISH_OVRFLW_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
68368   #define RTC_PUBLISH_OVRFLW_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
68369   #define RTC_PUBLISH_OVRFLW_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
68370   #define RTC_PUBLISH_OVRFLW_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
68371 
68372 
68373 /* RTC_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */
68374   #define RTC_PUBLISH_COMPARE_MaxCount (8UL)         /*!< Max size of PUBLISH_COMPARE[8] array.                                */
68375   #define RTC_PUBLISH_COMPARE_MaxIndex (7UL)         /*!< Max index of PUBLISH_COMPARE[8] array.                               */
68376   #define RTC_PUBLISH_COMPARE_MinIndex (0UL)         /*!< Min index of PUBLISH_COMPARE[8] array.                               */
68377   #define RTC_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[8] register.                       */
68378 
68379 /* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */
68380   #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
68381   #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
68382   #define RTC_PUBLISH_COMPARE_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
68383   #define RTC_PUBLISH_COMPARE_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
68384 
68385 /* EN @Bit 31 : (unspecified) */
68386   #define RTC_PUBLISH_COMPARE_EN_Pos (31UL)          /*!< Position of EN field.                                                */
68387   #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field.                          */
68388   #define RTC_PUBLISH_COMPARE_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
68389   #define RTC_PUBLISH_COMPARE_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
68390   #define RTC_PUBLISH_COMPARE_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
68391   #define RTC_PUBLISH_COMPARE_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
68392 
68393 
68394 /* RTC_SHORTS: Shortcuts between local events and tasks */
68395   #define RTC_SHORTS_ResetValue (0x00000000UL)       /*!< Reset value of SHORTS register.                                      */
68396 
68397 /* COMPARE0_CLEAR @Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
68398   #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL)        /*!< Position of COMPARE0_CLEAR field.                                    */
68399   #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field.        */
68400   #define RTC_SHORTS_COMPARE0_CLEAR_Min (0x0UL)      /*!< Min enumerator value of COMPARE0_CLEAR field.                        */
68401   #define RTC_SHORTS_COMPARE0_CLEAR_Max (0x1UL)      /*!< Max enumerator value of COMPARE0_CLEAR field.                        */
68402   #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                     */
68403   #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
68404 
68405 /* COMPARE1_CLEAR @Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
68406   #define RTC_SHORTS_COMPARE1_CLEAR_Pos (1UL)        /*!< Position of COMPARE1_CLEAR field.                                    */
68407   #define RTC_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field.        */
68408   #define RTC_SHORTS_COMPARE1_CLEAR_Min (0x0UL)      /*!< Min enumerator value of COMPARE1_CLEAR field.                        */
68409   #define RTC_SHORTS_COMPARE1_CLEAR_Max (0x1UL)      /*!< Max enumerator value of COMPARE1_CLEAR field.                        */
68410   #define RTC_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                     */
68411   #define RTC_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
68412 
68413 /* COMPARE2_CLEAR @Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
68414   #define RTC_SHORTS_COMPARE2_CLEAR_Pos (2UL)        /*!< Position of COMPARE2_CLEAR field.                                    */
68415   #define RTC_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field.        */
68416   #define RTC_SHORTS_COMPARE2_CLEAR_Min (0x0UL)      /*!< Min enumerator value of COMPARE2_CLEAR field.                        */
68417   #define RTC_SHORTS_COMPARE2_CLEAR_Max (0x1UL)      /*!< Max enumerator value of COMPARE2_CLEAR field.                        */
68418   #define RTC_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                     */
68419   #define RTC_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
68420 
68421 /* COMPARE3_CLEAR @Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
68422   #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL)        /*!< Position of COMPARE3_CLEAR field.                                    */
68423   #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field.        */
68424   #define RTC_SHORTS_COMPARE3_CLEAR_Min (0x0UL)      /*!< Min enumerator value of COMPARE3_CLEAR field.                        */
68425   #define RTC_SHORTS_COMPARE3_CLEAR_Max (0x1UL)      /*!< Max enumerator value of COMPARE3_CLEAR field.                        */
68426   #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                     */
68427   #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
68428 
68429 /* COMPARE4_CLEAR @Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
68430   #define RTC_SHORTS_COMPARE4_CLEAR_Pos (4UL)        /*!< Position of COMPARE4_CLEAR field.                                    */
68431   #define RTC_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field.        */
68432   #define RTC_SHORTS_COMPARE4_CLEAR_Min (0x0UL)      /*!< Min enumerator value of COMPARE4_CLEAR field.                        */
68433   #define RTC_SHORTS_COMPARE4_CLEAR_Max (0x1UL)      /*!< Max enumerator value of COMPARE4_CLEAR field.                        */
68434   #define RTC_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                     */
68435   #define RTC_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
68436 
68437 /* COMPARE5_CLEAR @Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
68438   #define RTC_SHORTS_COMPARE5_CLEAR_Pos (5UL)        /*!< Position of COMPARE5_CLEAR field.                                    */
68439   #define RTC_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field.        */
68440   #define RTC_SHORTS_COMPARE5_CLEAR_Min (0x0UL)      /*!< Min enumerator value of COMPARE5_CLEAR field.                        */
68441   #define RTC_SHORTS_COMPARE5_CLEAR_Max (0x1UL)      /*!< Max enumerator value of COMPARE5_CLEAR field.                        */
68442   #define RTC_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                     */
68443   #define RTC_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
68444 
68445 /* COMPARE6_CLEAR @Bit 6 : Shortcut between event COMPARE[6] and task CLEAR */
68446   #define RTC_SHORTS_COMPARE6_CLEAR_Pos (6UL)        /*!< Position of COMPARE6_CLEAR field.                                    */
68447   #define RTC_SHORTS_COMPARE6_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE6_CLEAR_Pos) /*!< Bit mask of COMPARE6_CLEAR field.        */
68448   #define RTC_SHORTS_COMPARE6_CLEAR_Min (0x0UL)      /*!< Min enumerator value of COMPARE6_CLEAR field.                        */
68449   #define RTC_SHORTS_COMPARE6_CLEAR_Max (0x1UL)      /*!< Max enumerator value of COMPARE6_CLEAR field.                        */
68450   #define RTC_SHORTS_COMPARE6_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                     */
68451   #define RTC_SHORTS_COMPARE6_CLEAR_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
68452 
68453 /* COMPARE7_CLEAR @Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */
68454   #define RTC_SHORTS_COMPARE7_CLEAR_Pos (7UL)        /*!< Position of COMPARE7_CLEAR field.                                    */
68455   #define RTC_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field.        */
68456   #define RTC_SHORTS_COMPARE7_CLEAR_Min (0x0UL)      /*!< Min enumerator value of COMPARE7_CLEAR field.                        */
68457   #define RTC_SHORTS_COMPARE7_CLEAR_Max (0x1UL)      /*!< Max enumerator value of COMPARE7_CLEAR field.                        */
68458   #define RTC_SHORTS_COMPARE7_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                     */
68459   #define RTC_SHORTS_COMPARE7_CLEAR_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
68460 
68461 
68462 /* RTC_INTENSET: Enable interrupt */
68463   #define RTC_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
68464 
68465 /* TICK @Bit 0 : Write '1' to enable interrupt for event TICK */
68466   #define RTC_INTENSET_TICK_Pos (0UL)                /*!< Position of TICK field.                                              */
68467   #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field.                                  */
68468   #define RTC_INTENSET_TICK_Min (0x0UL)              /*!< Min enumerator value of TICK field.                                  */
68469   #define RTC_INTENSET_TICK_Max (0x1UL)              /*!< Max enumerator value of TICK field.                                  */
68470   #define RTC_INTENSET_TICK_Set (0x1UL)              /*!< Enable                                                               */
68471   #define RTC_INTENSET_TICK_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
68472   #define RTC_INTENSET_TICK_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
68473 
68474 /* OVRFLW @Bit 1 : Write '1' to enable interrupt for event OVRFLW */
68475   #define RTC_INTENSET_OVRFLW_Pos (1UL)              /*!< Position of OVRFLW field.                                            */
68476   #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field.                            */
68477   #define RTC_INTENSET_OVRFLW_Min (0x0UL)            /*!< Min enumerator value of OVRFLW field.                                */
68478   #define RTC_INTENSET_OVRFLW_Max (0x1UL)            /*!< Max enumerator value of OVRFLW field.                                */
68479   #define RTC_INTENSET_OVRFLW_Set (0x1UL)            /*!< Enable                                                               */
68480   #define RTC_INTENSET_OVRFLW_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
68481   #define RTC_INTENSET_OVRFLW_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
68482 
68483 /* COMPARE0 @Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
68484   #define RTC_INTENSET_COMPARE0_Pos (16UL)           /*!< Position of COMPARE0 field.                                          */
68485   #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
68486   #define RTC_INTENSET_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
68487   #define RTC_INTENSET_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
68488   #define RTC_INTENSET_COMPARE0_Set (0x1UL)          /*!< Enable                                                               */
68489   #define RTC_INTENSET_COMPARE0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68490   #define RTC_INTENSET_COMPARE0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68491 
68492 /* COMPARE1 @Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
68493   #define RTC_INTENSET_COMPARE1_Pos (17UL)           /*!< Position of COMPARE1 field.                                          */
68494   #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
68495   #define RTC_INTENSET_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
68496   #define RTC_INTENSET_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
68497   #define RTC_INTENSET_COMPARE1_Set (0x1UL)          /*!< Enable                                                               */
68498   #define RTC_INTENSET_COMPARE1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68499   #define RTC_INTENSET_COMPARE1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68500 
68501 /* COMPARE2 @Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
68502   #define RTC_INTENSET_COMPARE2_Pos (18UL)           /*!< Position of COMPARE2 field.                                          */
68503   #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
68504   #define RTC_INTENSET_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
68505   #define RTC_INTENSET_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
68506   #define RTC_INTENSET_COMPARE2_Set (0x1UL)          /*!< Enable                                                               */
68507   #define RTC_INTENSET_COMPARE2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68508   #define RTC_INTENSET_COMPARE2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68509 
68510 /* COMPARE3 @Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
68511   #define RTC_INTENSET_COMPARE3_Pos (19UL)           /*!< Position of COMPARE3 field.                                          */
68512   #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
68513   #define RTC_INTENSET_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
68514   #define RTC_INTENSET_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
68515   #define RTC_INTENSET_COMPARE3_Set (0x1UL)          /*!< Enable                                                               */
68516   #define RTC_INTENSET_COMPARE3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68517   #define RTC_INTENSET_COMPARE3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68518 
68519 /* COMPARE4 @Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
68520   #define RTC_INTENSET_COMPARE4_Pos (20UL)           /*!< Position of COMPARE4 field.                                          */
68521   #define RTC_INTENSET_COMPARE4_Msk (0x1UL << RTC_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
68522   #define RTC_INTENSET_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
68523   #define RTC_INTENSET_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
68524   #define RTC_INTENSET_COMPARE4_Set (0x1UL)          /*!< Enable                                                               */
68525   #define RTC_INTENSET_COMPARE4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68526   #define RTC_INTENSET_COMPARE4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68527 
68528 /* COMPARE5 @Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
68529   #define RTC_INTENSET_COMPARE5_Pos (21UL)           /*!< Position of COMPARE5 field.                                          */
68530   #define RTC_INTENSET_COMPARE5_Msk (0x1UL << RTC_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
68531   #define RTC_INTENSET_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
68532   #define RTC_INTENSET_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
68533   #define RTC_INTENSET_COMPARE5_Set (0x1UL)          /*!< Enable                                                               */
68534   #define RTC_INTENSET_COMPARE5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68535   #define RTC_INTENSET_COMPARE5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68536 
68537 /* COMPARE6 @Bit 22 : Write '1' to enable interrupt for event COMPARE[6] */
68538   #define RTC_INTENSET_COMPARE6_Pos (22UL)           /*!< Position of COMPARE6 field.                                          */
68539   #define RTC_INTENSET_COMPARE6_Msk (0x1UL << RTC_INTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
68540   #define RTC_INTENSET_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
68541   #define RTC_INTENSET_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
68542   #define RTC_INTENSET_COMPARE6_Set (0x1UL)          /*!< Enable                                                               */
68543   #define RTC_INTENSET_COMPARE6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68544   #define RTC_INTENSET_COMPARE6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68545 
68546 /* COMPARE7 @Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */
68547   #define RTC_INTENSET_COMPARE7_Pos (23UL)           /*!< Position of COMPARE7 field.                                          */
68548   #define RTC_INTENSET_COMPARE7_Msk (0x1UL << RTC_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
68549   #define RTC_INTENSET_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
68550   #define RTC_INTENSET_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
68551   #define RTC_INTENSET_COMPARE7_Set (0x1UL)          /*!< Enable                                                               */
68552   #define RTC_INTENSET_COMPARE7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68553   #define RTC_INTENSET_COMPARE7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68554 
68555 
68556 /* RTC_INTENCLR: Disable interrupt */
68557   #define RTC_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
68558 
68559 /* TICK @Bit 0 : Write '1' to disable interrupt for event TICK */
68560   #define RTC_INTENCLR_TICK_Pos (0UL)                /*!< Position of TICK field.                                              */
68561   #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field.                                  */
68562   #define RTC_INTENCLR_TICK_Min (0x0UL)              /*!< Min enumerator value of TICK field.                                  */
68563   #define RTC_INTENCLR_TICK_Max (0x1UL)              /*!< Max enumerator value of TICK field.                                  */
68564   #define RTC_INTENCLR_TICK_Clear (0x1UL)            /*!< Disable                                                              */
68565   #define RTC_INTENCLR_TICK_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
68566   #define RTC_INTENCLR_TICK_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
68567 
68568 /* OVRFLW @Bit 1 : Write '1' to disable interrupt for event OVRFLW */
68569   #define RTC_INTENCLR_OVRFLW_Pos (1UL)              /*!< Position of OVRFLW field.                                            */
68570   #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field.                            */
68571   #define RTC_INTENCLR_OVRFLW_Min (0x0UL)            /*!< Min enumerator value of OVRFLW field.                                */
68572   #define RTC_INTENCLR_OVRFLW_Max (0x1UL)            /*!< Max enumerator value of OVRFLW field.                                */
68573   #define RTC_INTENCLR_OVRFLW_Clear (0x1UL)          /*!< Disable                                                              */
68574   #define RTC_INTENCLR_OVRFLW_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
68575   #define RTC_INTENCLR_OVRFLW_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
68576 
68577 /* COMPARE0 @Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
68578   #define RTC_INTENCLR_COMPARE0_Pos (16UL)           /*!< Position of COMPARE0 field.                                          */
68579   #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
68580   #define RTC_INTENCLR_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
68581   #define RTC_INTENCLR_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
68582   #define RTC_INTENCLR_COMPARE0_Clear (0x1UL)        /*!< Disable                                                              */
68583   #define RTC_INTENCLR_COMPARE0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68584   #define RTC_INTENCLR_COMPARE0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68585 
68586 /* COMPARE1 @Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
68587   #define RTC_INTENCLR_COMPARE1_Pos (17UL)           /*!< Position of COMPARE1 field.                                          */
68588   #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
68589   #define RTC_INTENCLR_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
68590   #define RTC_INTENCLR_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
68591   #define RTC_INTENCLR_COMPARE1_Clear (0x1UL)        /*!< Disable                                                              */
68592   #define RTC_INTENCLR_COMPARE1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68593   #define RTC_INTENCLR_COMPARE1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68594 
68595 /* COMPARE2 @Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
68596   #define RTC_INTENCLR_COMPARE2_Pos (18UL)           /*!< Position of COMPARE2 field.                                          */
68597   #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
68598   #define RTC_INTENCLR_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
68599   #define RTC_INTENCLR_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
68600   #define RTC_INTENCLR_COMPARE2_Clear (0x1UL)        /*!< Disable                                                              */
68601   #define RTC_INTENCLR_COMPARE2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68602   #define RTC_INTENCLR_COMPARE2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68603 
68604 /* COMPARE3 @Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
68605   #define RTC_INTENCLR_COMPARE3_Pos (19UL)           /*!< Position of COMPARE3 field.                                          */
68606   #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
68607   #define RTC_INTENCLR_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
68608   #define RTC_INTENCLR_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
68609   #define RTC_INTENCLR_COMPARE3_Clear (0x1UL)        /*!< Disable                                                              */
68610   #define RTC_INTENCLR_COMPARE3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68611   #define RTC_INTENCLR_COMPARE3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68612 
68613 /* COMPARE4 @Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
68614   #define RTC_INTENCLR_COMPARE4_Pos (20UL)           /*!< Position of COMPARE4 field.                                          */
68615   #define RTC_INTENCLR_COMPARE4_Msk (0x1UL << RTC_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
68616   #define RTC_INTENCLR_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
68617   #define RTC_INTENCLR_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
68618   #define RTC_INTENCLR_COMPARE4_Clear (0x1UL)        /*!< Disable                                                              */
68619   #define RTC_INTENCLR_COMPARE4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68620   #define RTC_INTENCLR_COMPARE4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68621 
68622 /* COMPARE5 @Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
68623   #define RTC_INTENCLR_COMPARE5_Pos (21UL)           /*!< Position of COMPARE5 field.                                          */
68624   #define RTC_INTENCLR_COMPARE5_Msk (0x1UL << RTC_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
68625   #define RTC_INTENCLR_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
68626   #define RTC_INTENCLR_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
68627   #define RTC_INTENCLR_COMPARE5_Clear (0x1UL)        /*!< Disable                                                              */
68628   #define RTC_INTENCLR_COMPARE5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68629   #define RTC_INTENCLR_COMPARE5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68630 
68631 /* COMPARE6 @Bit 22 : Write '1' to disable interrupt for event COMPARE[6] */
68632   #define RTC_INTENCLR_COMPARE6_Pos (22UL)           /*!< Position of COMPARE6 field.                                          */
68633   #define RTC_INTENCLR_COMPARE6_Msk (0x1UL << RTC_INTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
68634   #define RTC_INTENCLR_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
68635   #define RTC_INTENCLR_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
68636   #define RTC_INTENCLR_COMPARE6_Clear (0x1UL)        /*!< Disable                                                              */
68637   #define RTC_INTENCLR_COMPARE6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68638   #define RTC_INTENCLR_COMPARE6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68639 
68640 /* COMPARE7 @Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */
68641   #define RTC_INTENCLR_COMPARE7_Pos (23UL)           /*!< Position of COMPARE7 field.                                          */
68642   #define RTC_INTENCLR_COMPARE7_Msk (0x1UL << RTC_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
68643   #define RTC_INTENCLR_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
68644   #define RTC_INTENCLR_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
68645   #define RTC_INTENCLR_COMPARE7_Clear (0x1UL)        /*!< Disable                                                              */
68646   #define RTC_INTENCLR_COMPARE7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68647   #define RTC_INTENCLR_COMPARE7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68648 
68649 
68650 /* RTC_EVTEN: Enable or disable event routing */
68651   #define RTC_EVTEN_ResetValue (0x00000000UL)        /*!< Reset value of EVTEN register.                                       */
68652 
68653 /* TICK @Bit 0 : Enable or disable event routing for event TICK */
68654   #define RTC_EVTEN_TICK_Pos (0UL)                   /*!< Position of TICK field.                                              */
68655   #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field.                                        */
68656   #define RTC_EVTEN_TICK_Min (0x0UL)                 /*!< Min enumerator value of TICK field.                                  */
68657   #define RTC_EVTEN_TICK_Max (0x1UL)                 /*!< Max enumerator value of TICK field.                                  */
68658   #define RTC_EVTEN_TICK_Disabled (0x0UL)            /*!< Disable                                                              */
68659   #define RTC_EVTEN_TICK_Enabled (0x1UL)             /*!< Enable                                                               */
68660 
68661 /* OVRFLW @Bit 1 : Enable or disable event routing for event OVRFLW */
68662   #define RTC_EVTEN_OVRFLW_Pos (1UL)                 /*!< Position of OVRFLW field.                                            */
68663   #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field.                                  */
68664   #define RTC_EVTEN_OVRFLW_Min (0x0UL)               /*!< Min enumerator value of OVRFLW field.                                */
68665   #define RTC_EVTEN_OVRFLW_Max (0x1UL)               /*!< Max enumerator value of OVRFLW field.                                */
68666   #define RTC_EVTEN_OVRFLW_Disabled (0x0UL)          /*!< Disable                                                              */
68667   #define RTC_EVTEN_OVRFLW_Enabled (0x1UL)           /*!< Enable                                                               */
68668 
68669 /* COMPARE0 @Bit 16 : Enable or disable event routing for event COMPARE[0] */
68670   #define RTC_EVTEN_COMPARE0_Pos (16UL)              /*!< Position of COMPARE0 field.                                          */
68671   #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                            */
68672   #define RTC_EVTEN_COMPARE0_Min (0x0UL)             /*!< Min enumerator value of COMPARE0 field.                              */
68673   #define RTC_EVTEN_COMPARE0_Max (0x1UL)             /*!< Max enumerator value of COMPARE0 field.                              */
68674   #define RTC_EVTEN_COMPARE0_Disabled (0x0UL)        /*!< Disable                                                              */
68675   #define RTC_EVTEN_COMPARE0_Enabled (0x1UL)         /*!< Enable                                                               */
68676 
68677 /* COMPARE1 @Bit 17 : Enable or disable event routing for event COMPARE[1] */
68678   #define RTC_EVTEN_COMPARE1_Pos (17UL)              /*!< Position of COMPARE1 field.                                          */
68679   #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                            */
68680   #define RTC_EVTEN_COMPARE1_Min (0x0UL)             /*!< Min enumerator value of COMPARE1 field.                              */
68681   #define RTC_EVTEN_COMPARE1_Max (0x1UL)             /*!< Max enumerator value of COMPARE1 field.                              */
68682   #define RTC_EVTEN_COMPARE1_Disabled (0x0UL)        /*!< Disable                                                              */
68683   #define RTC_EVTEN_COMPARE1_Enabled (0x1UL)         /*!< Enable                                                               */
68684 
68685 /* COMPARE2 @Bit 18 : Enable or disable event routing for event COMPARE[2] */
68686   #define RTC_EVTEN_COMPARE2_Pos (18UL)              /*!< Position of COMPARE2 field.                                          */
68687   #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                            */
68688   #define RTC_EVTEN_COMPARE2_Min (0x0UL)             /*!< Min enumerator value of COMPARE2 field.                              */
68689   #define RTC_EVTEN_COMPARE2_Max (0x1UL)             /*!< Max enumerator value of COMPARE2 field.                              */
68690   #define RTC_EVTEN_COMPARE2_Disabled (0x0UL)        /*!< Disable                                                              */
68691   #define RTC_EVTEN_COMPARE2_Enabled (0x1UL)         /*!< Enable                                                               */
68692 
68693 /* COMPARE3 @Bit 19 : Enable or disable event routing for event COMPARE[3] */
68694   #define RTC_EVTEN_COMPARE3_Pos (19UL)              /*!< Position of COMPARE3 field.                                          */
68695   #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                            */
68696   #define RTC_EVTEN_COMPARE3_Min (0x0UL)             /*!< Min enumerator value of COMPARE3 field.                              */
68697   #define RTC_EVTEN_COMPARE3_Max (0x1UL)             /*!< Max enumerator value of COMPARE3 field.                              */
68698   #define RTC_EVTEN_COMPARE3_Disabled (0x0UL)        /*!< Disable                                                              */
68699   #define RTC_EVTEN_COMPARE3_Enabled (0x1UL)         /*!< Enable                                                               */
68700 
68701 /* COMPARE4 @Bit 20 : Enable or disable event routing for event COMPARE[4] */
68702   #define RTC_EVTEN_COMPARE4_Pos (20UL)              /*!< Position of COMPARE4 field.                                          */
68703   #define RTC_EVTEN_COMPARE4_Msk (0x1UL << RTC_EVTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                            */
68704   #define RTC_EVTEN_COMPARE4_Min (0x0UL)             /*!< Min enumerator value of COMPARE4 field.                              */
68705   #define RTC_EVTEN_COMPARE4_Max (0x1UL)             /*!< Max enumerator value of COMPARE4 field.                              */
68706   #define RTC_EVTEN_COMPARE4_Disabled (0x0UL)        /*!< Disable                                                              */
68707   #define RTC_EVTEN_COMPARE4_Enabled (0x1UL)         /*!< Enable                                                               */
68708 
68709 /* COMPARE5 @Bit 21 : Enable or disable event routing for event COMPARE[5] */
68710   #define RTC_EVTEN_COMPARE5_Pos (21UL)              /*!< Position of COMPARE5 field.                                          */
68711   #define RTC_EVTEN_COMPARE5_Msk (0x1UL << RTC_EVTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                            */
68712   #define RTC_EVTEN_COMPARE5_Min (0x0UL)             /*!< Min enumerator value of COMPARE5 field.                              */
68713   #define RTC_EVTEN_COMPARE5_Max (0x1UL)             /*!< Max enumerator value of COMPARE5 field.                              */
68714   #define RTC_EVTEN_COMPARE5_Disabled (0x0UL)        /*!< Disable                                                              */
68715   #define RTC_EVTEN_COMPARE5_Enabled (0x1UL)         /*!< Enable                                                               */
68716 
68717 /* COMPARE6 @Bit 22 : Enable or disable event routing for event COMPARE[6] */
68718   #define RTC_EVTEN_COMPARE6_Pos (22UL)              /*!< Position of COMPARE6 field.                                          */
68719   #define RTC_EVTEN_COMPARE6_Msk (0x1UL << RTC_EVTEN_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                            */
68720   #define RTC_EVTEN_COMPARE6_Min (0x0UL)             /*!< Min enumerator value of COMPARE6 field.                              */
68721   #define RTC_EVTEN_COMPARE6_Max (0x1UL)             /*!< Max enumerator value of COMPARE6 field.                              */
68722   #define RTC_EVTEN_COMPARE6_Disabled (0x0UL)        /*!< Disable                                                              */
68723   #define RTC_EVTEN_COMPARE6_Enabled (0x1UL)         /*!< Enable                                                               */
68724 
68725 /* COMPARE7 @Bit 23 : Enable or disable event routing for event COMPARE[7] */
68726   #define RTC_EVTEN_COMPARE7_Pos (23UL)              /*!< Position of COMPARE7 field.                                          */
68727   #define RTC_EVTEN_COMPARE7_Msk (0x1UL << RTC_EVTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                            */
68728   #define RTC_EVTEN_COMPARE7_Min (0x0UL)             /*!< Min enumerator value of COMPARE7 field.                              */
68729   #define RTC_EVTEN_COMPARE7_Max (0x1UL)             /*!< Max enumerator value of COMPARE7 field.                              */
68730   #define RTC_EVTEN_COMPARE7_Disabled (0x0UL)        /*!< Disable                                                              */
68731   #define RTC_EVTEN_COMPARE7_Enabled (0x1UL)         /*!< Enable                                                               */
68732 
68733 
68734 /* RTC_EVTENSET: Enable event routing */
68735   #define RTC_EVTENSET_ResetValue (0x00000000UL)     /*!< Reset value of EVTENSET register.                                    */
68736 
68737 /* TICK @Bit 0 : Write '1' to enable event routing for event TICK */
68738   #define RTC_EVTENSET_TICK_Pos (0UL)                /*!< Position of TICK field.                                              */
68739   #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field.                                  */
68740   #define RTC_EVTENSET_TICK_Min (0x0UL)              /*!< Min enumerator value of TICK field.                                  */
68741   #define RTC_EVTENSET_TICK_Max (0x1UL)              /*!< Max enumerator value of TICK field.                                  */
68742   #define RTC_EVTENSET_TICK_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
68743   #define RTC_EVTENSET_TICK_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
68744   #define RTC_EVTENSET_TICK_Set (0x1UL)              /*!< Enable                                                               */
68745 
68746 /* OVRFLW @Bit 1 : Write '1' to enable event routing for event OVRFLW */
68747   #define RTC_EVTENSET_OVRFLW_Pos (1UL)              /*!< Position of OVRFLW field.                                            */
68748   #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field.                            */
68749   #define RTC_EVTENSET_OVRFLW_Min (0x0UL)            /*!< Min enumerator value of OVRFLW field.                                */
68750   #define RTC_EVTENSET_OVRFLW_Max (0x1UL)            /*!< Max enumerator value of OVRFLW field.                                */
68751   #define RTC_EVTENSET_OVRFLW_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
68752   #define RTC_EVTENSET_OVRFLW_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
68753   #define RTC_EVTENSET_OVRFLW_Set (0x1UL)            /*!< Enable                                                               */
68754 
68755 /* COMPARE0 @Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
68756   #define RTC_EVTENSET_COMPARE0_Pos (16UL)           /*!< Position of COMPARE0 field.                                          */
68757   #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
68758   #define RTC_EVTENSET_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
68759   #define RTC_EVTENSET_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
68760   #define RTC_EVTENSET_COMPARE0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68761   #define RTC_EVTENSET_COMPARE0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68762   #define RTC_EVTENSET_COMPARE0_Set (0x1UL)          /*!< Enable                                                               */
68763 
68764 /* COMPARE1 @Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
68765   #define RTC_EVTENSET_COMPARE1_Pos (17UL)           /*!< Position of COMPARE1 field.                                          */
68766   #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
68767   #define RTC_EVTENSET_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
68768   #define RTC_EVTENSET_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
68769   #define RTC_EVTENSET_COMPARE1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68770   #define RTC_EVTENSET_COMPARE1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68771   #define RTC_EVTENSET_COMPARE1_Set (0x1UL)          /*!< Enable                                                               */
68772 
68773 /* COMPARE2 @Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
68774   #define RTC_EVTENSET_COMPARE2_Pos (18UL)           /*!< Position of COMPARE2 field.                                          */
68775   #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
68776   #define RTC_EVTENSET_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
68777   #define RTC_EVTENSET_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
68778   #define RTC_EVTENSET_COMPARE2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68779   #define RTC_EVTENSET_COMPARE2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68780   #define RTC_EVTENSET_COMPARE2_Set (0x1UL)          /*!< Enable                                                               */
68781 
68782 /* COMPARE3 @Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
68783   #define RTC_EVTENSET_COMPARE3_Pos (19UL)           /*!< Position of COMPARE3 field.                                          */
68784   #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
68785   #define RTC_EVTENSET_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
68786   #define RTC_EVTENSET_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
68787   #define RTC_EVTENSET_COMPARE3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68788   #define RTC_EVTENSET_COMPARE3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68789   #define RTC_EVTENSET_COMPARE3_Set (0x1UL)          /*!< Enable                                                               */
68790 
68791 /* COMPARE4 @Bit 20 : Write '1' to enable event routing for event COMPARE[4] */
68792   #define RTC_EVTENSET_COMPARE4_Pos (20UL)           /*!< Position of COMPARE4 field.                                          */
68793   #define RTC_EVTENSET_COMPARE4_Msk (0x1UL << RTC_EVTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
68794   #define RTC_EVTENSET_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
68795   #define RTC_EVTENSET_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
68796   #define RTC_EVTENSET_COMPARE4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68797   #define RTC_EVTENSET_COMPARE4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68798   #define RTC_EVTENSET_COMPARE4_Set (0x1UL)          /*!< Enable                                                               */
68799 
68800 /* COMPARE5 @Bit 21 : Write '1' to enable event routing for event COMPARE[5] */
68801   #define RTC_EVTENSET_COMPARE5_Pos (21UL)           /*!< Position of COMPARE5 field.                                          */
68802   #define RTC_EVTENSET_COMPARE5_Msk (0x1UL << RTC_EVTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
68803   #define RTC_EVTENSET_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
68804   #define RTC_EVTENSET_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
68805   #define RTC_EVTENSET_COMPARE5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68806   #define RTC_EVTENSET_COMPARE5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68807   #define RTC_EVTENSET_COMPARE5_Set (0x1UL)          /*!< Enable                                                               */
68808 
68809 /* COMPARE6 @Bit 22 : Write '1' to enable event routing for event COMPARE[6] */
68810   #define RTC_EVTENSET_COMPARE6_Pos (22UL)           /*!< Position of COMPARE6 field.                                          */
68811   #define RTC_EVTENSET_COMPARE6_Msk (0x1UL << RTC_EVTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
68812   #define RTC_EVTENSET_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
68813   #define RTC_EVTENSET_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
68814   #define RTC_EVTENSET_COMPARE6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68815   #define RTC_EVTENSET_COMPARE6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68816   #define RTC_EVTENSET_COMPARE6_Set (0x1UL)          /*!< Enable                                                               */
68817 
68818 /* COMPARE7 @Bit 23 : Write '1' to enable event routing for event COMPARE[7] */
68819   #define RTC_EVTENSET_COMPARE7_Pos (23UL)           /*!< Position of COMPARE7 field.                                          */
68820   #define RTC_EVTENSET_COMPARE7_Msk (0x1UL << RTC_EVTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
68821   #define RTC_EVTENSET_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
68822   #define RTC_EVTENSET_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
68823   #define RTC_EVTENSET_COMPARE7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68824   #define RTC_EVTENSET_COMPARE7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68825   #define RTC_EVTENSET_COMPARE7_Set (0x1UL)          /*!< Enable                                                               */
68826 
68827 
68828 /* RTC_EVTENCLR: Disable event routing */
68829   #define RTC_EVTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of EVTENCLR register.                                    */
68830 
68831 /* TICK @Bit 0 : Write '1' to disable event routing for event TICK */
68832   #define RTC_EVTENCLR_TICK_Pos (0UL)                /*!< Position of TICK field.                                              */
68833   #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field.                                  */
68834   #define RTC_EVTENCLR_TICK_Min (0x0UL)              /*!< Min enumerator value of TICK field.                                  */
68835   #define RTC_EVTENCLR_TICK_Max (0x1UL)              /*!< Max enumerator value of TICK field.                                  */
68836   #define RTC_EVTENCLR_TICK_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
68837   #define RTC_EVTENCLR_TICK_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
68838   #define RTC_EVTENCLR_TICK_Clear (0x1UL)            /*!< Disable                                                              */
68839 
68840 /* OVRFLW @Bit 1 : Write '1' to disable event routing for event OVRFLW */
68841   #define RTC_EVTENCLR_OVRFLW_Pos (1UL)              /*!< Position of OVRFLW field.                                            */
68842   #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field.                            */
68843   #define RTC_EVTENCLR_OVRFLW_Min (0x0UL)            /*!< Min enumerator value of OVRFLW field.                                */
68844   #define RTC_EVTENCLR_OVRFLW_Max (0x1UL)            /*!< Max enumerator value of OVRFLW field.                                */
68845   #define RTC_EVTENCLR_OVRFLW_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
68846   #define RTC_EVTENCLR_OVRFLW_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
68847   #define RTC_EVTENCLR_OVRFLW_Clear (0x1UL)          /*!< Disable                                                              */
68848 
68849 /* COMPARE0 @Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
68850   #define RTC_EVTENCLR_COMPARE0_Pos (16UL)           /*!< Position of COMPARE0 field.                                          */
68851   #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                      */
68852   #define RTC_EVTENCLR_COMPARE0_Min (0x0UL)          /*!< Min enumerator value of COMPARE0 field.                              */
68853   #define RTC_EVTENCLR_COMPARE0_Max (0x1UL)          /*!< Max enumerator value of COMPARE0 field.                              */
68854   #define RTC_EVTENCLR_COMPARE0_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68855   #define RTC_EVTENCLR_COMPARE0_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68856   #define RTC_EVTENCLR_COMPARE0_Clear (0x1UL)        /*!< Disable                                                              */
68857 
68858 /* COMPARE1 @Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
68859   #define RTC_EVTENCLR_COMPARE1_Pos (17UL)           /*!< Position of COMPARE1 field.                                          */
68860   #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                      */
68861   #define RTC_EVTENCLR_COMPARE1_Min (0x0UL)          /*!< Min enumerator value of COMPARE1 field.                              */
68862   #define RTC_EVTENCLR_COMPARE1_Max (0x1UL)          /*!< Max enumerator value of COMPARE1 field.                              */
68863   #define RTC_EVTENCLR_COMPARE1_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68864   #define RTC_EVTENCLR_COMPARE1_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68865   #define RTC_EVTENCLR_COMPARE1_Clear (0x1UL)        /*!< Disable                                                              */
68866 
68867 /* COMPARE2 @Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
68868   #define RTC_EVTENCLR_COMPARE2_Pos (18UL)           /*!< Position of COMPARE2 field.                                          */
68869   #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                      */
68870   #define RTC_EVTENCLR_COMPARE2_Min (0x0UL)          /*!< Min enumerator value of COMPARE2 field.                              */
68871   #define RTC_EVTENCLR_COMPARE2_Max (0x1UL)          /*!< Max enumerator value of COMPARE2 field.                              */
68872   #define RTC_EVTENCLR_COMPARE2_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68873   #define RTC_EVTENCLR_COMPARE2_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68874   #define RTC_EVTENCLR_COMPARE2_Clear (0x1UL)        /*!< Disable                                                              */
68875 
68876 /* COMPARE3 @Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
68877   #define RTC_EVTENCLR_COMPARE3_Pos (19UL)           /*!< Position of COMPARE3 field.                                          */
68878   #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                      */
68879   #define RTC_EVTENCLR_COMPARE3_Min (0x0UL)          /*!< Min enumerator value of COMPARE3 field.                              */
68880   #define RTC_EVTENCLR_COMPARE3_Max (0x1UL)          /*!< Max enumerator value of COMPARE3 field.                              */
68881   #define RTC_EVTENCLR_COMPARE3_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68882   #define RTC_EVTENCLR_COMPARE3_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68883   #define RTC_EVTENCLR_COMPARE3_Clear (0x1UL)        /*!< Disable                                                              */
68884 
68885 /* COMPARE4 @Bit 20 : Write '1' to disable event routing for event COMPARE[4] */
68886   #define RTC_EVTENCLR_COMPARE4_Pos (20UL)           /*!< Position of COMPARE4 field.                                          */
68887   #define RTC_EVTENCLR_COMPARE4_Msk (0x1UL << RTC_EVTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                      */
68888   #define RTC_EVTENCLR_COMPARE4_Min (0x0UL)          /*!< Min enumerator value of COMPARE4 field.                              */
68889   #define RTC_EVTENCLR_COMPARE4_Max (0x1UL)          /*!< Max enumerator value of COMPARE4 field.                              */
68890   #define RTC_EVTENCLR_COMPARE4_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68891   #define RTC_EVTENCLR_COMPARE4_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68892   #define RTC_EVTENCLR_COMPARE4_Clear (0x1UL)        /*!< Disable                                                              */
68893 
68894 /* COMPARE5 @Bit 21 : Write '1' to disable event routing for event COMPARE[5] */
68895   #define RTC_EVTENCLR_COMPARE5_Pos (21UL)           /*!< Position of COMPARE5 field.                                          */
68896   #define RTC_EVTENCLR_COMPARE5_Msk (0x1UL << RTC_EVTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                      */
68897   #define RTC_EVTENCLR_COMPARE5_Min (0x0UL)          /*!< Min enumerator value of COMPARE5 field.                              */
68898   #define RTC_EVTENCLR_COMPARE5_Max (0x1UL)          /*!< Max enumerator value of COMPARE5 field.                              */
68899   #define RTC_EVTENCLR_COMPARE5_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68900   #define RTC_EVTENCLR_COMPARE5_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68901   #define RTC_EVTENCLR_COMPARE5_Clear (0x1UL)        /*!< Disable                                                              */
68902 
68903 /* COMPARE6 @Bit 22 : Write '1' to disable event routing for event COMPARE[6] */
68904   #define RTC_EVTENCLR_COMPARE6_Pos (22UL)           /*!< Position of COMPARE6 field.                                          */
68905   #define RTC_EVTENCLR_COMPARE6_Msk (0x1UL << RTC_EVTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                      */
68906   #define RTC_EVTENCLR_COMPARE6_Min (0x0UL)          /*!< Min enumerator value of COMPARE6 field.                              */
68907   #define RTC_EVTENCLR_COMPARE6_Max (0x1UL)          /*!< Max enumerator value of COMPARE6 field.                              */
68908   #define RTC_EVTENCLR_COMPARE6_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68909   #define RTC_EVTENCLR_COMPARE6_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68910   #define RTC_EVTENCLR_COMPARE6_Clear (0x1UL)        /*!< Disable                                                              */
68911 
68912 /* COMPARE7 @Bit 23 : Write '1' to disable event routing for event COMPARE[7] */
68913   #define RTC_EVTENCLR_COMPARE7_Pos (23UL)           /*!< Position of COMPARE7 field.                                          */
68914   #define RTC_EVTENCLR_COMPARE7_Msk (0x1UL << RTC_EVTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                      */
68915   #define RTC_EVTENCLR_COMPARE7_Min (0x0UL)          /*!< Min enumerator value of COMPARE7 field.                              */
68916   #define RTC_EVTENCLR_COMPARE7_Max (0x1UL)          /*!< Max enumerator value of COMPARE7 field.                              */
68917   #define RTC_EVTENCLR_COMPARE7_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
68918   #define RTC_EVTENCLR_COMPARE7_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
68919   #define RTC_EVTENCLR_COMPARE7_Clear (0x1UL)        /*!< Disable                                                              */
68920 
68921 
68922 /* RTC_COUNTER: Current counter value */
68923   #define RTC_COUNTER_ResetValue (0x00000000UL)      /*!< Reset value of COUNTER register.                                     */
68924 
68925 /* COUNTER @Bits 0..23 : Counter value */
68926   #define RTC_COUNTER_COUNTER_Pos (0UL)              /*!< Position of COUNTER field.                                           */
68927   #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field.                      */
68928 
68929 
68930 /* RTC_PRESCALER: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */
68931   #define RTC_PRESCALER_ResetValue (0x00000000UL)    /*!< Reset value of PRESCALER register.                                   */
68932 
68933 /* PRESCALER @Bits 0..11 : Prescaler value */
68934   #define RTC_PRESCALER_PRESCALER_Pos (0UL)          /*!< Position of PRESCALER field.                                         */
68935   #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field.               */
68936 
68937 
68938 /* RTC_CC: Compare register n */
68939   #define RTC_CC_MaxCount (8UL)                      /*!< Max size of CC[8] array.                                             */
68940   #define RTC_CC_MaxIndex (7UL)                      /*!< Max index of CC[8] array.                                            */
68941   #define RTC_CC_MinIndex (0UL)                      /*!< Min index of CC[8] array.                                            */
68942   #define RTC_CC_ResetValue (0x00000000UL)           /*!< Reset value of CC[8] register.                                       */
68943 
68944 /* COMPARE @Bits 0..23 : Compare value */
68945   #define RTC_CC_COMPARE_Pos (0UL)                   /*!< Position of COMPARE field.                                           */
68946   #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field.                                */
68947 
68948 
68949 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
68950 
68951 /* =========================================================================================================================== */
68952 /* ================                                           SAADC                                           ================ */
68953 /* =========================================================================================================================== */
68954 
68955 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
68956 
68957 /* ================================================= Struct SAADC_EVENTS_CH ================================================== */
68958 /**
68959   * @brief EVENTS_CH [SAADC_EVENTS_CH] Peripheral events.
68960   */
68961 typedef struct {
68962   __IOM uint32_t  LIMITH;                            /*!< (@ 0x00000000) Last results is equal or above CH[n].LIMIT.HIGH       */
68963   __IOM uint32_t  LIMITL;                            /*!< (@ 0x00000004) Last results is equal or below CH[n].LIMIT.LOW        */
68964 } NRF_SAADC_EVENTS_CH_Type;                          /*!< Size = 8 (0x008)                                                     */
68965   #define SAADC_EVENTS_CH_MaxCount (8UL)             /*!< Size of EVENTS_CH[8] array.                                          */
68966   #define SAADC_EVENTS_CH_MaxIndex (7UL)             /*!< Max index of EVENTS_CH[8] array.                                     */
68967   #define SAADC_EVENTS_CH_MinIndex (0UL)             /*!< Min index of EVENTS_CH[8] array.                                     */
68968 
68969 /* SAADC_EVENTS_CH_LIMITH: Last results is equal or above CH[n].LIMIT.HIGH */
68970   #define SAADC_EVENTS_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register.                                */
68971 
68972 /* LIMITH @Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
68973   #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL)    /*!< Position of LIMITH field.                                            */
68974   #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field.        */
68975   #define SAADC_EVENTS_CH_LIMITH_LIMITH_Min (0x0UL)  /*!< Min enumerator value of LIMITH field.                                */
68976   #define SAADC_EVENTS_CH_LIMITH_LIMITH_Max (0x1UL)  /*!< Max enumerator value of LIMITH field.                                */
68977   #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated                                          */
68978   #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated                                                 */
68979 
68980 
68981 /* SAADC_EVENTS_CH_LIMITL: Last results is equal or below CH[n].LIMIT.LOW */
68982   #define SAADC_EVENTS_CH_LIMITL_ResetValue (0x00000000UL) /*!< Reset value of LIMITL register.                                */
68983 
68984 /* LIMITL @Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
68985   #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL)    /*!< Position of LIMITL field.                                            */
68986   #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field.        */
68987   #define SAADC_EVENTS_CH_LIMITL_LIMITL_Min (0x0UL)  /*!< Min enumerator value of LIMITL field.                                */
68988   #define SAADC_EVENTS_CH_LIMITL_LIMITL_Max (0x1UL)  /*!< Max enumerator value of LIMITL field.                                */
68989   #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated                                          */
68990   #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated                                                 */
68991 
68992 
68993 
68994 /* ================================================= Struct SAADC_PUBLISH_CH ================================================= */
68995 /**
68996   * @brief PUBLISH_CH [SAADC_PUBLISH_CH] Publish configuration for events
68997   */
68998 typedef struct {
68999   __IOM uint32_t  LIMITH;                            /*!< (@ 0x00000000) Publish configuration for event CH[n].LIMITH          */
69000   __IOM uint32_t  LIMITL;                            /*!< (@ 0x00000004) Publish configuration for event CH[n].LIMITL          */
69001 } NRF_SAADC_PUBLISH_CH_Type;                         /*!< Size = 8 (0x008)                                                     */
69002   #define SAADC_PUBLISH_CH_MaxCount (8UL)            /*!< Size of PUBLISH_CH[8] array.                                         */
69003   #define SAADC_PUBLISH_CH_MaxIndex (7UL)            /*!< Max index of PUBLISH_CH[8] array.                                    */
69004   #define SAADC_PUBLISH_CH_MinIndex (0UL)            /*!< Min index of PUBLISH_CH[8] array.                                    */
69005 
69006 /* SAADC_PUBLISH_CH_LIMITH: Publish configuration for event CH[n].LIMITH */
69007   #define SAADC_PUBLISH_CH_LIMITH_ResetValue (0x00000000UL) /*!< Reset value of LIMITH register.                               */
69008 
69009 /* CHIDX @Bits 0..7 : DPPI channel that event CH[n].LIMITH will publish to */
69010   #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
69011   #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
69012   #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
69013   #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
69014 
69015 /* EN @Bit 31 : (unspecified) */
69016   #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL)      /*!< Position of EN field.                                                */
69017   #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field.                  */
69018   #define SAADC_PUBLISH_CH_LIMITH_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
69019   #define SAADC_PUBLISH_CH_LIMITH_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
69020   #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
69021   #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
69022 
69023 
69024 /* SAADC_PUBLISH_CH_LIMITL: Publish configuration for event CH[n].LIMITL */
69025   #define SAADC_PUBLISH_CH_LIMITL_ResetValue (0x00000000UL) /*!< Reset value of LIMITL register.                               */
69026 
69027 /* CHIDX @Bits 0..7 : DPPI channel that event CH[n].LIMITL will publish to */
69028   #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
69029   #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
69030   #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
69031   #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
69032 
69033 /* EN @Bit 31 : (unspecified) */
69034   #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL)      /*!< Position of EN field.                                                */
69035   #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field.                  */
69036   #define SAADC_PUBLISH_CH_LIMITL_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
69037   #define SAADC_PUBLISH_CH_LIMITL_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
69038   #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
69039   #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
69040 
69041 
69042 
69043 /* ==================================================== Struct SAADC_TRIM ==================================================== */
69044 /**
69045   * @brief TRIM [SAADC_TRIM] (unspecified)
69046   */
69047 typedef struct {
69048   __IOM uint32_t  LINCALCOEFF[6];                    /*!< (@ 0x00000000) Linearity calibration coefficient                     */
69049 } NRF_SAADC_TRIM_Type;                               /*!< Size = 24 (0x018)                                                    */
69050 
69051 /* SAADC_TRIM_LINCALCOEFF: Linearity calibration coefficient */
69052   #define SAADC_TRIM_LINCALCOEFF_MaxCount (6UL)      /*!< Max size of LINCALCOEFF[6] array.                                    */
69053   #define SAADC_TRIM_LINCALCOEFF_MaxIndex (5UL)      /*!< Max index of LINCALCOEFF[6] array.                                   */
69054   #define SAADC_TRIM_LINCALCOEFF_MinIndex (0UL)      /*!< Min index of LINCALCOEFF[6] array.                                   */
69055   #define SAADC_TRIM_LINCALCOEFF_ResetValue (0x00000000UL) /*!< Reset value of LINCALCOEFF[6] register.                        */
69056 
69057 /* VAL @Bits 0..15 : value */
69058   #define SAADC_TRIM_LINCALCOEFF_VAL_Pos (0UL)       /*!< Position of VAL field.                                               */
69059   #define SAADC_TRIM_LINCALCOEFF_VAL_Msk (0xFFFFUL << SAADC_TRIM_LINCALCOEFF_VAL_Pos) /*!< Bit mask of VAL field.              */
69060   #define SAADC_TRIM_LINCALCOEFF_VAL_Min (0x0UL)     /*!< Min value of VAL field.                                              */
69061   #define SAADC_TRIM_LINCALCOEFF_VAL_Max (0xFFFFUL)  /*!< Max size of VAL field.                                               */
69062 
69063 
69064 
69065 /* ===================================================== Struct SAADC_CH ===================================================== */
69066 /**
69067   * @brief CH [SAADC_CH] (unspecified)
69068   */
69069 typedef struct {
69070   __IOM uint32_t  PSELP;                             /*!< (@ 0x00000000) Input positive pin selection for CH[n]                */
69071   __IOM uint32_t  PSELN;                             /*!< (@ 0x00000004) Input negative pin selection for CH[n]                */
69072   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000008) Input configuration for CH[n]                         */
69073   __IOM uint32_t  LIMIT;                             /*!< (@ 0x0000000C) High/low limits for event monitoring a channel        */
69074 } NRF_SAADC_CH_Type;                                 /*!< Size = 16 (0x010)                                                    */
69075   #define SAADC_CH_MaxCount (8UL)                    /*!< Size of CH[8] array.                                                 */
69076   #define SAADC_CH_MaxIndex (7UL)                    /*!< Max index of CH[8] array.                                            */
69077   #define SAADC_CH_MinIndex (0UL)                    /*!< Min index of CH[8] array.                                            */
69078 
69079 /* SAADC_CH_PSELP: Input positive pin selection for CH[n] */
69080   #define SAADC_CH_PSELP_ResetValue (0x00000000UL)   /*!< Reset value of PSELP register.                                       */
69081 
69082 /* PSELP @Bits 0..4 : Analog positive input channel */
69083   #define SAADC_CH_PSELP_PSELP_Pos (0UL)             /*!< Position of PSELP field.                                             */
69084   #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field.                          */
69085   #define SAADC_CH_PSELP_PSELP_Min (0x0UL)           /*!< Min enumerator value of PSELP field.                                 */
69086   #define SAADC_CH_PSELP_PSELP_Max (0x16UL)          /*!< Max enumerator value of PSELP field.                                 */
69087   #define SAADC_CH_PSELP_PSELP_NC (0x00UL)           /*!< Not connected                                                        */
69088   #define SAADC_CH_PSELP_PSELP_AnalogInput0 (0x01UL) /*!< AIN0                                                                 */
69089   #define SAADC_CH_PSELP_PSELP_AnalogInput1 (0x02UL) /*!< AIN1                                                                 */
69090   #define SAADC_CH_PSELP_PSELP_AnalogInput2 (0x03UL) /*!< AIN2                                                                 */
69091   #define SAADC_CH_PSELP_PSELP_AnalogInput3 (0x04UL) /*!< AIN3                                                                 */
69092   #define SAADC_CH_PSELP_PSELP_AnalogInput4 (0x05UL) /*!< AIN4                                                                 */
69093   #define SAADC_CH_PSELP_PSELP_AnalogInput5 (0x06UL) /*!< AIN5                                                                 */
69094   #define SAADC_CH_PSELP_PSELP_AnalogInput6 (0x07UL) /*!< AIN6                                                                 */
69095   #define SAADC_CH_PSELP_PSELP_AnalogInput7 (0x08UL) /*!< AIN7                                                                 */
69096   #define SAADC_CH_PSELP_PSELP_AnalogInput8 (0x11UL) /*!< AIN8                                                                 */
69097   #define SAADC_CH_PSELP_PSELP_AnalogInput9 (0x12UL) /*!< AIN9                                                                 */
69098   #define SAADC_CH_PSELP_PSELP_AnalogInput10 (0x13UL) /*!< AIN10                                                               */
69099   #define SAADC_CH_PSELP_PSELP_AnalogInput11 (0x14UL) /*!< AIN11                                                               */
69100   #define SAADC_CH_PSELP_PSELP_AnalogInput12 (0x15UL) /*!< AIN12                                                               */
69101   #define SAADC_CH_PSELP_PSELP_AnalogInput13 (0x16UL) /*!< AIN13                                                               */
69102 
69103 
69104 /* SAADC_CH_PSELN: Input negative pin selection for CH[n] */
69105   #define SAADC_CH_PSELN_ResetValue (0x00000000UL)   /*!< Reset value of PSELN register.                                       */
69106 
69107 /* PSELN @Bits 0..4 : Analog negative input, enables differential channel */
69108   #define SAADC_CH_PSELN_PSELN_Pos (0UL)             /*!< Position of PSELN field.                                             */
69109   #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field.                          */
69110   #define SAADC_CH_PSELN_PSELN_Min (0x0UL)           /*!< Min enumerator value of PSELN field.                                 */
69111   #define SAADC_CH_PSELN_PSELN_Max (0x16UL)          /*!< Max enumerator value of PSELN field.                                 */
69112   #define SAADC_CH_PSELN_PSELN_NC (0x00UL)           /*!< Not connected                                                        */
69113   #define SAADC_CH_PSELN_PSELN_AnalogInput0 (0x01UL) /*!< AIN0                                                                 */
69114   #define SAADC_CH_PSELN_PSELN_AnalogInput1 (0x02UL) /*!< AIN1                                                                 */
69115   #define SAADC_CH_PSELN_PSELN_AnalogInput2 (0x03UL) /*!< AIN2                                                                 */
69116   #define SAADC_CH_PSELN_PSELN_AnalogInput3 (0x04UL) /*!< AIN3                                                                 */
69117   #define SAADC_CH_PSELN_PSELN_AnalogInput4 (0x05UL) /*!< AIN4                                                                 */
69118   #define SAADC_CH_PSELN_PSELN_AnalogInput5 (0x06UL) /*!< AIN5                                                                 */
69119   #define SAADC_CH_PSELN_PSELN_AnalogInput6 (0x07UL) /*!< AIN6                                                                 */
69120   #define SAADC_CH_PSELN_PSELN_AnalogInput7 (0x08UL) /*!< AIN7                                                                 */
69121   #define SAADC_CH_PSELN_PSELN_AnalogInput8 (0x11UL) /*!< AIN8                                                                 */
69122   #define SAADC_CH_PSELN_PSELN_AnalogInput9 (0x12UL) /*!< AIN9                                                                 */
69123   #define SAADC_CH_PSELN_PSELN_AnalogInput10 (0x13UL) /*!< AIN10                                                               */
69124   #define SAADC_CH_PSELN_PSELN_AnalogInput11 (0x14UL) /*!< AIN11                                                               */
69125   #define SAADC_CH_PSELN_PSELN_AnalogInput12 (0x15UL) /*!< AIN12                                                               */
69126   #define SAADC_CH_PSELN_PSELN_AnalogInput13 (0x16UL) /*!< AIN13                                                               */
69127 
69128 
69129 /* SAADC_CH_CONFIG: Input configuration for CH[n] */
69130   #define SAADC_CH_CONFIG_ResetValue (0x00020000UL)  /*!< Reset value of CONFIG register.                                      */
69131 
69132 /* RESP @Bits 0..1 : Positive channel resistor control */
69133   #define SAADC_CH_CONFIG_RESP_Pos (0UL)             /*!< Position of RESP field.                                              */
69134   #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field.                            */
69135   #define SAADC_CH_CONFIG_RESP_Min (0x0UL)           /*!< Min enumerator value of RESP field.                                  */
69136   #define SAADC_CH_CONFIG_RESP_Max (0x3UL)           /*!< Max enumerator value of RESP field.                                  */
69137   #define SAADC_CH_CONFIG_RESP_Bypass (0x0UL)        /*!< Bypass resistor ladder                                               */
69138   #define SAADC_CH_CONFIG_RESP_Pulldown (0x1UL)      /*!< Pull-down to GND                                                     */
69139   #define SAADC_CH_CONFIG_RESP_Pullup (0x2UL)        /*!< Pull-up to VDD_AO_1V8                                                */
69140   #define SAADC_CH_CONFIG_RESP_VDDAO1V8div2 (0x3UL)  /*!< Set input at VDD_AO_1V8/2                                            */
69141 
69142 /* RESN @Bits 4..5 : Negative channel resistor control */
69143   #define SAADC_CH_CONFIG_RESN_Pos (4UL)             /*!< Position of RESN field.                                              */
69144   #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field.                            */
69145   #define SAADC_CH_CONFIG_RESN_Min (0x0UL)           /*!< Min enumerator value of RESN field.                                  */
69146   #define SAADC_CH_CONFIG_RESN_Max (0x3UL)           /*!< Max enumerator value of RESN field.                                  */
69147   #define SAADC_CH_CONFIG_RESN_Bypass (0x0UL)        /*!< Bypass resistor ladder                                               */
69148   #define SAADC_CH_CONFIG_RESN_Pulldown (0x1UL)      /*!< Pull-down to GND                                                     */
69149   #define SAADC_CH_CONFIG_RESN_Pullup (0x2UL)        /*!< Pull-up to VDD_AO_1V8                                                */
69150   #define SAADC_CH_CONFIG_RESN_VDDAO1V8div2 (0x3UL)  /*!< Set input at VDD_AO_1V8/2                                            */
69151 
69152 /* GAIN @Bits 8..9 : Gain control */
69153   #define SAADC_CH_CONFIG_GAIN_Pos (8UL)             /*!< Position of GAIN field.                                              */
69154   #define SAADC_CH_CONFIG_GAIN_Msk (0x3UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field.                            */
69155   #define SAADC_CH_CONFIG_GAIN_Min (0x0UL)           /*!< Min enumerator value of GAIN field.                                  */
69156   #define SAADC_CH_CONFIG_GAIN_Max (0x3UL)           /*!< Max enumerator value of GAIN field.                                  */
69157   #define SAADC_CH_CONFIG_GAIN_Gain2_3 (0x0UL)       /*!< 2/3                                                                  */
69158   #define SAADC_CH_CONFIG_GAIN_Gain1 (0x1UL)         /*!< 1                                                                    */
69159   #define SAADC_CH_CONFIG_GAIN_Gain2 (0x2UL)         /*!< 2                                                                    */
69160   #define SAADC_CH_CONFIG_GAIN_Gain4 (0x3UL)         /*!< 4                                                                    */
69161 
69162 /* BURST @Bit 11 : Enable burst mode */
69163   #define SAADC_CH_CONFIG_BURST_Pos (11UL)           /*!< Position of BURST field.                                             */
69164   #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field.                         */
69165   #define SAADC_CH_CONFIG_BURST_Min (0x0UL)          /*!< Min enumerator value of BURST field.                                 */
69166   #define SAADC_CH_CONFIG_BURST_Max (0x1UL)          /*!< Max enumerator value of BURST field.                                 */
69167   #define SAADC_CH_CONFIG_BURST_Disabled (0x0UL)     /*!< Burst mode is disabled (normal operation)                            */
69168   #define SAADC_CH_CONFIG_BURST_Enabled (0x1UL)      /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as
69169                                                           fast as it can, and sends the average to Data RAM.*/
69170 
69171 /* REFSEL @Bit 12 : Reference control */
69172   #define SAADC_CH_CONFIG_REFSEL_Pos (12UL)          /*!< Position of REFSEL field.                                            */
69173   #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field.                      */
69174   #define SAADC_CH_CONFIG_REFSEL_Min (0x0UL)         /*!< Min enumerator value of REFSEL field.                                */
69175   #define SAADC_CH_CONFIG_REFSEL_Max (0x1UL)         /*!< Max enumerator value of REFSEL field.                                */
69176   #define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL)    /*!< Internal reference (1.024 V)                                         */
69177   #define SAADC_CH_CONFIG_REFSEL_External (0x1UL)    /*!< External reference given at PADC_EXT_REF_1V2                         */
69178 
69179 /* MODE @Bit 15 : Enable differential mode */
69180   #define SAADC_CH_CONFIG_MODE_Pos (15UL)            /*!< Position of MODE field.                                              */
69181   #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field.                            */
69182   #define SAADC_CH_CONFIG_MODE_Min (0x0UL)           /*!< Min enumerator value of MODE field.                                  */
69183   #define SAADC_CH_CONFIG_MODE_Max (0x1UL)           /*!< Max enumerator value of MODE field.                                  */
69184   #define SAADC_CH_CONFIG_MODE_SE (0x0UL)            /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to
69185                                                           GND*/
69186   #define SAADC_CH_CONFIG_MODE_Diff (0x1UL)          /*!< Differential                                                         */
69187 
69188 /* TACQ @Bits 16..24 : Acquisition time, the time the ADC uses to sample the input voltage. Resulting acquistion time is
69189                        ((TACQ+1) x 125 ns) */
69190 
69191   #define SAADC_CH_CONFIG_TACQ_Pos (16UL)            /*!< Position of TACQ field.                                              */
69192   #define SAADC_CH_CONFIG_TACQ_Msk (0x1FFUL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field.                          */
69193   #define SAADC_CH_CONFIG_TACQ_Min (0x0UL)           /*!< Min value of TACQ field.                                             */
69194   #define SAADC_CH_CONFIG_TACQ_Max (0x13FUL)         /*!< Max size of TACQ field.                                              */
69195 
69196 /* TCONV @Bits 28..30 : Conversion time. Resulting conversion time is ((TCONV+1) x 250 ns) */
69197   #define SAADC_CH_CONFIG_TCONV_Pos (28UL)           /*!< Position of TCONV field.                                             */
69198   #define SAADC_CH_CONFIG_TCONV_Msk (0x7UL << SAADC_CH_CONFIG_TCONV_Pos) /*!< Bit mask of TCONV field.                         */
69199   #define SAADC_CH_CONFIG_TCONV_Min (0x0UL)          /*!< Min value of TCONV field.                                            */
69200   #define SAADC_CH_CONFIG_TCONV_Max (0x7UL)          /*!< Max size of TCONV field.                                             */
69201 
69202 
69203 /* SAADC_CH_LIMIT: High/low limits for event monitoring a channel */
69204   #define SAADC_CH_LIMIT_ResetValue (0x7FFF8000UL)   /*!< Reset value of LIMIT register.                                       */
69205 
69206 /* LOW @Bits 0..15 : Low level limit */
69207   #define SAADC_CH_LIMIT_LOW_Pos (0UL)               /*!< Position of LOW field.                                               */
69208   #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field.                              */
69209 
69210 /* HIGH @Bits 16..31 : High level limit */
69211   #define SAADC_CH_LIMIT_HIGH_Pos (16UL)             /*!< Position of HIGH field.                                              */
69212   #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field.                           */
69213 
69214 
69215 
69216 /* =================================================== Struct SAADC_RESULT =================================================== */
69217 /**
69218   * @brief RESULT [SAADC_RESULT] RESULT EasyDMA channel
69219   */
69220 typedef struct {
69221   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
69222   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of buffer bytes to transfer            */
69223   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of buffer bytes transferred since last START   */
69224   __IM  uint32_t  RESERVED;
69225 } NRF_SAADC_RESULT_Type;                             /*!< Size = 16 (0x010)                                                    */
69226 
69227 /* SAADC_RESULT_PTR: Data pointer */
69228   #define SAADC_RESULT_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register.                                         */
69229 
69230 /* PTR @Bits 0..31 : Data pointer */
69231   #define SAADC_RESULT_PTR_PTR_Pos (0UL)             /*!< Position of PTR field.                                               */
69232   #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field.                      */
69233 
69234 
69235 /* SAADC_RESULT_MAXCNT: Maximum number of buffer bytes to transfer */
69236   #define SAADC_RESULT_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                   */
69237 
69238 /* MAXCNT @Bits 0..14 : Maximum number of buffer bytes to transfer */
69239   #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL)       /*!< Position of MAXCNT field.                                            */
69240   #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.           */
69241 
69242 
69243 /* SAADC_RESULT_AMOUNT: Number of buffer bytes transferred since last START */
69244   #define SAADC_RESULT_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                   */
69245 
69246 /* AMOUNT @Bits 0..14 : Number of buffer bytes transferred since last START. This register can be read after an END or STOPPED
69247                         event. */
69248 
69249   #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL)       /*!< Position of AMOUNT field.                                            */
69250   #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.           */
69251 
69252 
69253 /* ====================================================== Struct SAADC ======================================================= */
69254 /**
69255   * @brief Analog to Digital Converter
69256   */
69257   typedef struct {                                   /*!< SAADC Structure                                                      */
69258     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in RAM    */
69259     __OM uint32_t TASKS_SAMPLE;                      /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels
69260                                                                          are sampled*/
69261     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion    */
69262     __OM uint32_t TASKS_CALIBRATEOFFSET;             /*!< (@ 0x0000000C) Starts offset auto-calibration                        */
69263     __IM uint32_t RESERVED[28];
69264     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
69265     __IOM uint32_t SUBSCRIBE_SAMPLE;                 /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE               */
69266     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000088) Subscribe configuration for task STOP                 */
69267     __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET;        /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET      */
69268     __IM uint32_t RESERVED1[28];
69269     __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x00000100) The ADC has started                                   */
69270     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000104) The ADC has filled up the Result buffer               */
69271     __IOM uint32_t EVENTS_DONE;                      /*!< (@ 0x00000108) A conversion task has been completed. Depending on the
69272                                                                          mode, multiple conversions might be needed for a result
69273                                                                          to be transferred to RAM.*/
69274     __IOM uint32_t EVENTS_RESULTDONE;                /*!< (@ 0x0000010C) A result is ready to get transferred to RAM.          */
69275     __IOM uint32_t EVENTS_CALIBRATEDONE;             /*!< (@ 0x00000110) Calibration is complete                               */
69276     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000114) The ADC has stopped                                   */
69277     __IOM NRF_SAADC_EVENTS_CH_Type EVENTS_CH[8];     /*!< (@ 0x00000118) Peripheral events.                                    */
69278     __IM uint32_t RESERVED2[10];
69279     __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x00000180) Publish configuration for event STARTED               */
69280     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000184) Publish configuration for event END                   */
69281     __IOM uint32_t PUBLISH_DONE;                     /*!< (@ 0x00000188) Publish configuration for event DONE                  */
69282     __IOM uint32_t PUBLISH_RESULTDONE;               /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE            */
69283     __IOM uint32_t PUBLISH_CALIBRATEDONE;            /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE         */
69284     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000194) Publish configuration for event STOPPED               */
69285     __IOM NRF_SAADC_PUBLISH_CH_Type PUBLISH_CH[8];   /*!< (@ 0x00000198) Publish configuration for events                      */
69286     __IM uint32_t RESERVED3[74];
69287     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
69288     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
69289     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
69290     __IM uint32_t RESERVED4[61];
69291     __IM uint32_t STATUS;                            /*!< (@ 0x00000400) Status                                                */
69292     __IM uint32_t RESERVED5[15];
69293     __IOM NRF_SAADC_TRIM_Type TRIM;                  /*!< (@ 0x00000440) (unspecified)                                         */
69294     __IM uint32_t RESERVED6[42];
69295     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable or disable ADC                                 */
69296     __IM uint32_t RESERVED7[3];
69297     __IOM NRF_SAADC_CH_Type CH[8];                   /*!< (@ 0x00000510) (unspecified)                                         */
69298     __IM uint32_t RESERVED8[24];
69299     __IOM uint32_t RESOLUTION;                       /*!< (@ 0x000005F0) Resolution configuration                              */
69300     __IOM uint32_t OVERSAMPLE;                       /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should not be
69301                                                                          combined with SCAN. The RESOLUTION is applied before
69302                                                                          averaging, thus for high OVERSAMPLE a higher RESOLUTION
69303                                                                          should be used.*/
69304     __IOM uint32_t SAMPLERATE;                       /*!< (@ 0x000005F8) Controls normal or continuous sample rate             */
69305     __IM uint32_t RESERVED9[12];
69306     __IOM NRF_SAADC_RESULT_Type RESULT;              /*!< (@ 0x0000062C) RESULT EasyDMA channel                                */
69307   } NRF_SAADC_Type;                                  /*!< Size = 1596 (0x63C)                                                  */
69308 
69309 /* SAADC_TASKS_START: Start the ADC and prepare the result buffer in RAM */
69310   #define SAADC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */
69311 
69312 /* TASKS_START @Bit 0 : Start the ADC and prepare the result buffer in RAM */
69313   #define SAADC_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
69314   #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
69315   #define SAADC_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
69316   #define SAADC_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
69317   #define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */
69318 
69319 
69320 /* SAADC_TASKS_SAMPLE: Take one ADC sample, if scan is enabled all channels are sampled */
69321   #define SAADC_TASKS_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SAMPLE register.                              */
69322 
69323 /* TASKS_SAMPLE @Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
69324   #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL)  /*!< Position of TASKS_SAMPLE field.                                      */
69325   #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE
69326                                                                             field.*/
69327   #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Min (0x1UL) /*!< Min enumerator value of TASKS_SAMPLE field.                         */
69328   #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Max (0x1UL) /*!< Max enumerator value of TASKS_SAMPLE field.                         */
69329   #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task                                                    */
69330 
69331 
69332 /* SAADC_TASKS_STOP: Stop the ADC and terminate any on-going conversion */
69333   #define SAADC_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */
69334 
69335 /* TASKS_STOP @Bit 0 : Stop the ADC and terminate any on-going conversion */
69336   #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
69337   #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
69338   #define SAADC_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
69339   #define SAADC_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
69340   #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */
69341 
69342 
69343 /* SAADC_TASKS_CALIBRATEOFFSET: Starts offset auto-calibration */
69344   #define SAADC_TASKS_CALIBRATEOFFSET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CALIBRATEOFFSET register.            */
69345 
69346 /* TASKS_CALIBRATEOFFSET @Bit 0 : Starts offset auto-calibration */
69347   #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field.            */
69348   #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos)
69349                                                                             /*!< Bit mask of TASKS_CALIBRATEOFFSET field.*/
69350   #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Min (0x1UL) /*!< Min enumerator value of TASKS_CALIBRATEOFFSET
69351                                                                             field.*/
69352   #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Max (0x1UL) /*!< Max enumerator value of TASKS_CALIBRATEOFFSET
69353                                                                             field.*/
69354   #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task                                  */
69355 
69356 
69357 /* SAADC_SUBSCRIBE_START: Subscribe configuration for task START */
69358   #define SAADC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                        */
69359 
69360 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
69361   #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
69362   #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
69363   #define SAADC_SUBSCRIBE_START_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
69364   #define SAADC_SUBSCRIBE_START_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
69365 
69366 /* EN @Bit 31 : (unspecified) */
69367   #define SAADC_SUBSCRIBE_START_EN_Pos (31UL)        /*!< Position of EN field.                                                */
69368   #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                      */
69369   #define SAADC_SUBSCRIBE_START_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
69370   #define SAADC_SUBSCRIBE_START_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
69371   #define SAADC_SUBSCRIBE_START_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
69372   #define SAADC_SUBSCRIBE_START_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
69373 
69374 
69375 /* SAADC_SUBSCRIBE_SAMPLE: Subscribe configuration for task SAMPLE */
69376   #define SAADC_SUBSCRIBE_SAMPLE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SAMPLE register.                      */
69377 
69378 /* CHIDX @Bits 0..7 : DPPI channel that task SAMPLE will subscribe to */
69379   #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
69380   #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
69381   #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
69382   #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
69383 
69384 /* EN @Bit 31 : (unspecified) */
69385   #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
69386   #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field.                    */
69387   #define SAADC_SUBSCRIBE_SAMPLE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
69388   #define SAADC_SUBSCRIBE_SAMPLE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
69389   #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
69390   #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
69391 
69392 
69393 /* SAADC_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
69394   #define SAADC_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                          */
69395 
69396 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
69397   #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
69398   #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
69399   #define SAADC_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
69400   #define SAADC_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
69401 
69402 /* EN @Bit 31 : (unspecified) */
69403   #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL)         /*!< Position of EN field.                                                */
69404   #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                        */
69405   #define SAADC_SUBSCRIBE_STOP_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
69406   #define SAADC_SUBSCRIBE_STOP_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
69407   #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
69408   #define SAADC_SUBSCRIBE_STOP_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
69409 
69410 
69411 /* SAADC_SUBSCRIBE_CALIBRATEOFFSET: Subscribe configuration for task CALIBRATEOFFSET */
69412   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CALIBRATEOFFSET register.    */
69413 
69414 /* CHIDX @Bits 0..7 : DPPI channel that task CALIBRATEOFFSET will subscribe to */
69415   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                        */
69416   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX
69417                                                                             field.*/
69418   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                     */
69419   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                     */
69420 
69421 /* EN @Bit 31 : (unspecified) */
69422   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field.                                             */
69423   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field.  */
69424   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                */
69425   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                */
69426   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0x0UL) /*!< Disable subscription                                        */
69427   #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (0x1UL) /*!< Enable subscription                                          */
69428 
69429 
69430 /* SAADC_EVENTS_STARTED: The ADC has started */
69431   #define SAADC_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                          */
69432 
69433 /* EVENTS_STARTED @Bit 0 : The ADC has started */
69434   #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                 */
69435   #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of
69436                                                                             EVENTS_STARTED field.*/
69437   #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                   */
69438   #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                   */
69439   #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                    */
69440   #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                           */
69441 
69442 
69443 /* SAADC_EVENTS_END: The ADC has filled up the Result buffer */
69444   #define SAADC_EVENTS_END_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_END register.                                  */
69445 
69446 /* EVENTS_END @Bit 0 : The ADC has filled up the Result buffer */
69447   #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL)      /*!< Position of EVENTS_END field.                                        */
69448   #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.        */
69449   #define SAADC_EVENTS_END_EVENTS_END_Min (0x0UL)    /*!< Min enumerator value of EVENTS_END field.                            */
69450   #define SAADC_EVENTS_END_EVENTS_END_Max (0x1UL)    /*!< Max enumerator value of EVENTS_END field.                            */
69451   #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                            */
69452   #define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                   */
69453 
69454 
69455 /* SAADC_EVENTS_DONE: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a
69456                        result to be transferred to RAM. */
69457 
69458   #define SAADC_EVENTS_DONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DONE register.                                */
69459 
69460 /* EVENTS_DONE @Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a
69461                         result to be transferred to RAM. */
69462 
69463   #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL)    /*!< Position of EVENTS_DONE field.                                       */
69464   #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field.   */
69465   #define SAADC_EVENTS_DONE_EVENTS_DONE_Min (0x0UL)  /*!< Min enumerator value of EVENTS_DONE field.                           */
69466   #define SAADC_EVENTS_DONE_EVENTS_DONE_Max (0x1UL)  /*!< Max enumerator value of EVENTS_DONE field.                           */
69467   #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated                                          */
69468   #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated                                                 */
69469 
69470 
69471 /* SAADC_EVENTS_RESULTDONE: A result is ready to get transferred to RAM. */
69472   #define SAADC_EVENTS_RESULTDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RESULTDONE register.                    */
69473 
69474 /* EVENTS_RESULTDONE @Bit 0 : A result is ready to get transferred to RAM. */
69475   #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field.                        */
69476   #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask
69477                                                                             of EVENTS_RESULTDONE field.*/
69478   #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RESULTDONE field.          */
69479   #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RESULTDONE field.          */
69480   #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated                              */
69481   #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated                                     */
69482 
69483 
69484 /* SAADC_EVENTS_CALIBRATEDONE: Calibration is complete */
69485   #define SAADC_EVENTS_CALIBRATEDONE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CALIBRATEDONE register.              */
69486 
69487 /* EVENTS_CALIBRATEDONE @Bit 0 : Calibration is complete */
69488   #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field.               */
69489   #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos)
69490                                                                             /*!< Bit mask of EVENTS_CALIBRATEDONE field.*/
69491   #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Min (0x0UL) /*!< Min enumerator value of EVENTS_CALIBRATEDONE field. */
69492   #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Max (0x1UL) /*!< Max enumerator value of EVENTS_CALIBRATEDONE field. */
69493   #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated                        */
69494   #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated                               */
69495 
69496 
69497 /* SAADC_EVENTS_STOPPED: The ADC has stopped */
69498   #define SAADC_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                          */
69499 
69500 /* EVENTS_STOPPED @Bit 0 : The ADC has stopped */
69501   #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                 */
69502   #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
69503                                                                             EVENTS_STOPPED field.*/
69504   #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                   */
69505   #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                   */
69506   #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                    */
69507   #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                           */
69508 
69509 
69510 /* SAADC_PUBLISH_STARTED: Publish configuration for event STARTED */
69511   #define SAADC_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                        */
69512 
69513 /* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
69514   #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
69515   #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
69516   #define SAADC_PUBLISH_STARTED_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
69517   #define SAADC_PUBLISH_STARTED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
69518 
69519 /* EN @Bit 31 : (unspecified) */
69520   #define SAADC_PUBLISH_STARTED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
69521   #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                      */
69522   #define SAADC_PUBLISH_STARTED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
69523   #define SAADC_PUBLISH_STARTED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
69524   #define SAADC_PUBLISH_STARTED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
69525   #define SAADC_PUBLISH_STARTED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
69526 
69527 
69528 /* SAADC_PUBLISH_END: Publish configuration for event END */
69529   #define SAADC_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                */
69530 
69531 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
69532   #define SAADC_PUBLISH_END_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
69533   #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
69534   #define SAADC_PUBLISH_END_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
69535   #define SAADC_PUBLISH_END_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
69536 
69537 /* EN @Bit 31 : (unspecified) */
69538   #define SAADC_PUBLISH_END_EN_Pos (31UL)            /*!< Position of EN field.                                                */
69539   #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                              */
69540   #define SAADC_PUBLISH_END_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
69541   #define SAADC_PUBLISH_END_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
69542   #define SAADC_PUBLISH_END_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
69543   #define SAADC_PUBLISH_END_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
69544 
69545 
69546 /* SAADC_PUBLISH_DONE: Publish configuration for event DONE */
69547   #define SAADC_PUBLISH_DONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DONE register.                              */
69548 
69549 /* CHIDX @Bits 0..7 : DPPI channel that event DONE will publish to */
69550   #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
69551   #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
69552   #define SAADC_PUBLISH_DONE_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
69553   #define SAADC_PUBLISH_DONE_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
69554 
69555 /* EN @Bit 31 : (unspecified) */
69556   #define SAADC_PUBLISH_DONE_EN_Pos (31UL)           /*!< Position of EN field.                                                */
69557   #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field.                            */
69558   #define SAADC_PUBLISH_DONE_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
69559   #define SAADC_PUBLISH_DONE_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
69560   #define SAADC_PUBLISH_DONE_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
69561   #define SAADC_PUBLISH_DONE_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
69562 
69563 
69564 /* SAADC_PUBLISH_RESULTDONE: Publish configuration for event RESULTDONE */
69565   #define SAADC_PUBLISH_RESULTDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RESULTDONE register.                  */
69566 
69567 /* CHIDX @Bits 0..7 : DPPI channel that event RESULTDONE will publish to */
69568   #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
69569   #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
69570   #define SAADC_PUBLISH_RESULTDONE_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
69571   #define SAADC_PUBLISH_RESULTDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
69572 
69573 /* EN @Bit 31 : (unspecified) */
69574   #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL)     /*!< Position of EN field.                                                */
69575   #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field.                */
69576   #define SAADC_PUBLISH_RESULTDONE_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
69577   #define SAADC_PUBLISH_RESULTDONE_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
69578   #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
69579   #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */
69580 
69581 
69582 /* SAADC_PUBLISH_CALIBRATEDONE: Publish configuration for event CALIBRATEDONE */
69583   #define SAADC_PUBLISH_CALIBRATEDONE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CALIBRATEDONE register.            */
69584 
69585 /* CHIDX @Bits 0..7 : DPPI channel that event CALIBRATEDONE will publish to */
69586   #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field.                                            */
69587   #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/
69588   #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                         */
69589   #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                         */
69590 
69591 /* EN @Bit 31 : (unspecified) */
69592   #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL)  /*!< Position of EN field.                                                */
69593   #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field.          */
69594   #define SAADC_PUBLISH_CALIBRATEDONE_EN_Min (0x0UL) /*!< Min enumerator value of EN field.                                    */
69595   #define SAADC_PUBLISH_CALIBRATEDONE_EN_Max (0x1UL) /*!< Max enumerator value of EN field.                                    */
69596   #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0x0UL) /*!< Disable publishing                                              */
69597   #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (0x1UL) /*!< Enable publishing                                                */
69598 
69599 
69600 /* SAADC_PUBLISH_STOPPED: Publish configuration for event STOPPED */
69601   #define SAADC_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                        */
69602 
69603 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
69604   #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
69605   #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
69606   #define SAADC_PUBLISH_STOPPED_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
69607   #define SAADC_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
69608 
69609 /* EN @Bit 31 : (unspecified) */
69610   #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
69611   #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                      */
69612   #define SAADC_PUBLISH_STOPPED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
69613   #define SAADC_PUBLISH_STOPPED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
69614   #define SAADC_PUBLISH_STOPPED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
69615   #define SAADC_PUBLISH_STOPPED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
69616 
69617 
69618 /* SAADC_INTEN: Enable or disable interrupt */
69619   #define SAADC_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */
69620 
69621 /* STARTED @Bit 0 : Enable or disable interrupt for event STARTED */
69622   #define SAADC_INTEN_STARTED_Pos (0UL)              /*!< Position of STARTED field.                                           */
69623   #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field.                           */
69624   #define SAADC_INTEN_STARTED_Min (0x0UL)            /*!< Min enumerator value of STARTED field.                               */
69625   #define SAADC_INTEN_STARTED_Max (0x1UL)            /*!< Max enumerator value of STARTED field.                               */
69626   #define SAADC_INTEN_STARTED_Disabled (0x0UL)       /*!< Disable                                                              */
69627   #define SAADC_INTEN_STARTED_Enabled (0x1UL)        /*!< Enable                                                               */
69628 
69629 /* END @Bit 1 : Enable or disable interrupt for event END */
69630   #define SAADC_INTEN_END_Pos (1UL)                  /*!< Position of END field.                                               */
69631   #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field.                                       */
69632   #define SAADC_INTEN_END_Min (0x0UL)                /*!< Min enumerator value of END field.                                   */
69633   #define SAADC_INTEN_END_Max (0x1UL)                /*!< Max enumerator value of END field.                                   */
69634   #define SAADC_INTEN_END_Disabled (0x0UL)           /*!< Disable                                                              */
69635   #define SAADC_INTEN_END_Enabled (0x1UL)            /*!< Enable                                                               */
69636 
69637 /* DONE @Bit 2 : Enable or disable interrupt for event DONE */
69638   #define SAADC_INTEN_DONE_Pos (2UL)                 /*!< Position of DONE field.                                              */
69639   #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field.                                    */
69640   #define SAADC_INTEN_DONE_Min (0x0UL)               /*!< Min enumerator value of DONE field.                                  */
69641   #define SAADC_INTEN_DONE_Max (0x1UL)               /*!< Max enumerator value of DONE field.                                  */
69642   #define SAADC_INTEN_DONE_Disabled (0x0UL)          /*!< Disable                                                              */
69643   #define SAADC_INTEN_DONE_Enabled (0x1UL)           /*!< Enable                                                               */
69644 
69645 /* RESULTDONE @Bit 3 : Enable or disable interrupt for event RESULTDONE */
69646   #define SAADC_INTEN_RESULTDONE_Pos (3UL)           /*!< Position of RESULTDONE field.                                        */
69647   #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field.                  */
69648   #define SAADC_INTEN_RESULTDONE_Min (0x0UL)         /*!< Min enumerator value of RESULTDONE field.                            */
69649   #define SAADC_INTEN_RESULTDONE_Max (0x1UL)         /*!< Max enumerator value of RESULTDONE field.                            */
69650   #define SAADC_INTEN_RESULTDONE_Disabled (0x0UL)    /*!< Disable                                                              */
69651   #define SAADC_INTEN_RESULTDONE_Enabled (0x1UL)     /*!< Enable                                                               */
69652 
69653 /* CALIBRATEDONE @Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
69654   #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL)        /*!< Position of CALIBRATEDONE field.                                     */
69655   #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field.         */
69656   #define SAADC_INTEN_CALIBRATEDONE_Min (0x0UL)      /*!< Min enumerator value of CALIBRATEDONE field.                         */
69657   #define SAADC_INTEN_CALIBRATEDONE_Max (0x1UL)      /*!< Max enumerator value of CALIBRATEDONE field.                         */
69658   #define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable                                                              */
69659   #define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL)  /*!< Enable                                                               */
69660 
69661 /* STOPPED @Bit 5 : Enable or disable interrupt for event STOPPED */
69662   #define SAADC_INTEN_STOPPED_Pos (5UL)              /*!< Position of STOPPED field.                                           */
69663   #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                           */
69664   #define SAADC_INTEN_STOPPED_Min (0x0UL)            /*!< Min enumerator value of STOPPED field.                               */
69665   #define SAADC_INTEN_STOPPED_Max (0x1UL)            /*!< Max enumerator value of STOPPED field.                               */
69666   #define SAADC_INTEN_STOPPED_Disabled (0x0UL)       /*!< Disable                                                              */
69667   #define SAADC_INTEN_STOPPED_Enabled (0x1UL)        /*!< Enable                                                               */
69668 
69669 /* CH0LIMITH @Bit 6 : Enable or disable interrupt for event CH0LIMITH */
69670   #define SAADC_INTEN_CH0LIMITH_Pos (6UL)            /*!< Position of CH0LIMITH field.                                         */
69671   #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field.                     */
69672   #define SAADC_INTEN_CH0LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH0LIMITH field.                             */
69673   #define SAADC_INTEN_CH0LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH0LIMITH field.                             */
69674   #define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
69675   #define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */
69676 
69677 /* CH0LIMITL @Bit 7 : Enable or disable interrupt for event CH0LIMITL */
69678   #define SAADC_INTEN_CH0LIMITL_Pos (7UL)            /*!< Position of CH0LIMITL field.                                         */
69679   #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field.                     */
69680   #define SAADC_INTEN_CH0LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH0LIMITL field.                             */
69681   #define SAADC_INTEN_CH0LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH0LIMITL field.                             */
69682   #define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
69683   #define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */
69684 
69685 /* CH1LIMITH @Bit 8 : Enable or disable interrupt for event CH1LIMITH */
69686   #define SAADC_INTEN_CH1LIMITH_Pos (8UL)            /*!< Position of CH1LIMITH field.                                         */
69687   #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field.                     */
69688   #define SAADC_INTEN_CH1LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH1LIMITH field.                             */
69689   #define SAADC_INTEN_CH1LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH1LIMITH field.                             */
69690   #define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
69691   #define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */
69692 
69693 /* CH1LIMITL @Bit 9 : Enable or disable interrupt for event CH1LIMITL */
69694   #define SAADC_INTEN_CH1LIMITL_Pos (9UL)            /*!< Position of CH1LIMITL field.                                         */
69695   #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field.                     */
69696   #define SAADC_INTEN_CH1LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH1LIMITL field.                             */
69697   #define SAADC_INTEN_CH1LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH1LIMITL field.                             */
69698   #define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
69699   #define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */
69700 
69701 /* CH2LIMITH @Bit 10 : Enable or disable interrupt for event CH2LIMITH */
69702   #define SAADC_INTEN_CH2LIMITH_Pos (10UL)           /*!< Position of CH2LIMITH field.                                         */
69703   #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field.                     */
69704   #define SAADC_INTEN_CH2LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH2LIMITH field.                             */
69705   #define SAADC_INTEN_CH2LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH2LIMITH field.                             */
69706   #define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
69707   #define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */
69708 
69709 /* CH2LIMITL @Bit 11 : Enable or disable interrupt for event CH2LIMITL */
69710   #define SAADC_INTEN_CH2LIMITL_Pos (11UL)           /*!< Position of CH2LIMITL field.                                         */
69711   #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field.                     */
69712   #define SAADC_INTEN_CH2LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH2LIMITL field.                             */
69713   #define SAADC_INTEN_CH2LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH2LIMITL field.                             */
69714   #define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
69715   #define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */
69716 
69717 /* CH3LIMITH @Bit 12 : Enable or disable interrupt for event CH3LIMITH */
69718   #define SAADC_INTEN_CH3LIMITH_Pos (12UL)           /*!< Position of CH3LIMITH field.                                         */
69719   #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field.                     */
69720   #define SAADC_INTEN_CH3LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH3LIMITH field.                             */
69721   #define SAADC_INTEN_CH3LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH3LIMITH field.                             */
69722   #define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
69723   #define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */
69724 
69725 /* CH3LIMITL @Bit 13 : Enable or disable interrupt for event CH3LIMITL */
69726   #define SAADC_INTEN_CH3LIMITL_Pos (13UL)           /*!< Position of CH3LIMITL field.                                         */
69727   #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field.                     */
69728   #define SAADC_INTEN_CH3LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH3LIMITL field.                             */
69729   #define SAADC_INTEN_CH3LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH3LIMITL field.                             */
69730   #define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
69731   #define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */
69732 
69733 /* CH4LIMITH @Bit 14 : Enable or disable interrupt for event CH4LIMITH */
69734   #define SAADC_INTEN_CH4LIMITH_Pos (14UL)           /*!< Position of CH4LIMITH field.                                         */
69735   #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field.                     */
69736   #define SAADC_INTEN_CH4LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH4LIMITH field.                             */
69737   #define SAADC_INTEN_CH4LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH4LIMITH field.                             */
69738   #define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
69739   #define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */
69740 
69741 /* CH4LIMITL @Bit 15 : Enable or disable interrupt for event CH4LIMITL */
69742   #define SAADC_INTEN_CH4LIMITL_Pos (15UL)           /*!< Position of CH4LIMITL field.                                         */
69743   #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field.                     */
69744   #define SAADC_INTEN_CH4LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH4LIMITL field.                             */
69745   #define SAADC_INTEN_CH4LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH4LIMITL field.                             */
69746   #define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
69747   #define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */
69748 
69749 /* CH5LIMITH @Bit 16 : Enable or disable interrupt for event CH5LIMITH */
69750   #define SAADC_INTEN_CH5LIMITH_Pos (16UL)           /*!< Position of CH5LIMITH field.                                         */
69751   #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field.                     */
69752   #define SAADC_INTEN_CH5LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH5LIMITH field.                             */
69753   #define SAADC_INTEN_CH5LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH5LIMITH field.                             */
69754   #define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
69755   #define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */
69756 
69757 /* CH5LIMITL @Bit 17 : Enable or disable interrupt for event CH5LIMITL */
69758   #define SAADC_INTEN_CH5LIMITL_Pos (17UL)           /*!< Position of CH5LIMITL field.                                         */
69759   #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field.                     */
69760   #define SAADC_INTEN_CH5LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH5LIMITL field.                             */
69761   #define SAADC_INTEN_CH5LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH5LIMITL field.                             */
69762   #define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
69763   #define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */
69764 
69765 /* CH6LIMITH @Bit 18 : Enable or disable interrupt for event CH6LIMITH */
69766   #define SAADC_INTEN_CH6LIMITH_Pos (18UL)           /*!< Position of CH6LIMITH field.                                         */
69767   #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field.                     */
69768   #define SAADC_INTEN_CH6LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH6LIMITH field.                             */
69769   #define SAADC_INTEN_CH6LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH6LIMITH field.                             */
69770   #define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
69771   #define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */
69772 
69773 /* CH6LIMITL @Bit 19 : Enable or disable interrupt for event CH6LIMITL */
69774   #define SAADC_INTEN_CH6LIMITL_Pos (19UL)           /*!< Position of CH6LIMITL field.                                         */
69775   #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field.                     */
69776   #define SAADC_INTEN_CH6LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH6LIMITL field.                             */
69777   #define SAADC_INTEN_CH6LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH6LIMITL field.                             */
69778   #define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
69779   #define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */
69780 
69781 /* CH7LIMITH @Bit 20 : Enable or disable interrupt for event CH7LIMITH */
69782   #define SAADC_INTEN_CH7LIMITH_Pos (20UL)           /*!< Position of CH7LIMITH field.                                         */
69783   #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field.                     */
69784   #define SAADC_INTEN_CH7LIMITH_Min (0x0UL)          /*!< Min enumerator value of CH7LIMITH field.                             */
69785   #define SAADC_INTEN_CH7LIMITH_Max (0x1UL)          /*!< Max enumerator value of CH7LIMITH field.                             */
69786   #define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL)     /*!< Disable                                                              */
69787   #define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL)      /*!< Enable                                                               */
69788 
69789 /* CH7LIMITL @Bit 21 : Enable or disable interrupt for event CH7LIMITL */
69790   #define SAADC_INTEN_CH7LIMITL_Pos (21UL)           /*!< Position of CH7LIMITL field.                                         */
69791   #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field.                     */
69792   #define SAADC_INTEN_CH7LIMITL_Min (0x0UL)          /*!< Min enumerator value of CH7LIMITL field.                             */
69793   #define SAADC_INTEN_CH7LIMITL_Max (0x1UL)          /*!< Max enumerator value of CH7LIMITL field.                             */
69794   #define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL)     /*!< Disable                                                              */
69795   #define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL)      /*!< Enable                                                               */
69796 
69797 
69798 /* SAADC_INTENSET: Enable interrupt */
69799   #define SAADC_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */
69800 
69801 /* STARTED @Bit 0 : Write '1' to enable interrupt for event STARTED */
69802   #define SAADC_INTENSET_STARTED_Pos (0UL)           /*!< Position of STARTED field.                                           */
69803   #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                     */
69804   #define SAADC_INTENSET_STARTED_Min (0x0UL)         /*!< Min enumerator value of STARTED field.                               */
69805   #define SAADC_INTENSET_STARTED_Max (0x1UL)         /*!< Max enumerator value of STARTED field.                               */
69806   #define SAADC_INTENSET_STARTED_Set (0x1UL)         /*!< Enable                                                               */
69807   #define SAADC_INTENSET_STARTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
69808   #define SAADC_INTENSET_STARTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
69809 
69810 /* END @Bit 1 : Write '1' to enable interrupt for event END */
69811   #define SAADC_INTENSET_END_Pos (1UL)               /*!< Position of END field.                                               */
69812   #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field.                                 */
69813   #define SAADC_INTENSET_END_Min (0x0UL)             /*!< Min enumerator value of END field.                                   */
69814   #define SAADC_INTENSET_END_Max (0x1UL)             /*!< Max enumerator value of END field.                                   */
69815   #define SAADC_INTENSET_END_Set (0x1UL)             /*!< Enable                                                               */
69816   #define SAADC_INTENSET_END_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
69817   #define SAADC_INTENSET_END_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
69818 
69819 /* DONE @Bit 2 : Write '1' to enable interrupt for event DONE */
69820   #define SAADC_INTENSET_DONE_Pos (2UL)              /*!< Position of DONE field.                                              */
69821   #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field.                              */
69822   #define SAADC_INTENSET_DONE_Min (0x0UL)            /*!< Min enumerator value of DONE field.                                  */
69823   #define SAADC_INTENSET_DONE_Max (0x1UL)            /*!< Max enumerator value of DONE field.                                  */
69824   #define SAADC_INTENSET_DONE_Set (0x1UL)            /*!< Enable                                                               */
69825   #define SAADC_INTENSET_DONE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
69826   #define SAADC_INTENSET_DONE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
69827 
69828 /* RESULTDONE @Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
69829   #define SAADC_INTENSET_RESULTDONE_Pos (3UL)        /*!< Position of RESULTDONE field.                                        */
69830   #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field.            */
69831   #define SAADC_INTENSET_RESULTDONE_Min (0x0UL)      /*!< Min enumerator value of RESULTDONE field.                            */
69832   #define SAADC_INTENSET_RESULTDONE_Max (0x1UL)      /*!< Max enumerator value of RESULTDONE field.                            */
69833   #define SAADC_INTENSET_RESULTDONE_Set (0x1UL)      /*!< Enable                                                               */
69834   #define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled                                                       */
69835   #define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
69836 
69837 /* CALIBRATEDONE @Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
69838   #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL)     /*!< Position of CALIBRATEDONE field.                                     */
69839   #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field.   */
69840   #define SAADC_INTENSET_CALIBRATEDONE_Min (0x0UL)   /*!< Min enumerator value of CALIBRATEDONE field.                         */
69841   #define SAADC_INTENSET_CALIBRATEDONE_Max (0x1UL)   /*!< Max enumerator value of CALIBRATEDONE field.                         */
69842   #define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL)   /*!< Enable                                                               */
69843   #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
69844   #define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
69845 
69846 /* STOPPED @Bit 5 : Write '1' to enable interrupt for event STOPPED */
69847   #define SAADC_INTENSET_STOPPED_Pos (5UL)           /*!< Position of STOPPED field.                                           */
69848   #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                     */
69849   #define SAADC_INTENSET_STOPPED_Min (0x0UL)         /*!< Min enumerator value of STOPPED field.                               */
69850   #define SAADC_INTENSET_STOPPED_Max (0x1UL)         /*!< Max enumerator value of STOPPED field.                               */
69851   #define SAADC_INTENSET_STOPPED_Set (0x1UL)         /*!< Enable                                                               */
69852   #define SAADC_INTENSET_STOPPED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
69853   #define SAADC_INTENSET_STOPPED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
69854 
69855 /* CH0LIMITH @Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
69856   #define SAADC_INTENSET_CH0LIMITH_Pos (6UL)         /*!< Position of CH0LIMITH field.                                         */
69857   #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field.               */
69858   #define SAADC_INTENSET_CH0LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH0LIMITH field.                             */
69859   #define SAADC_INTENSET_CH0LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH0LIMITH field.                             */
69860   #define SAADC_INTENSET_CH0LIMITH_Set (0x1UL)       /*!< Enable                                                               */
69861   #define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69862   #define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69863 
69864 /* CH0LIMITL @Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
69865   #define SAADC_INTENSET_CH0LIMITL_Pos (7UL)         /*!< Position of CH0LIMITL field.                                         */
69866   #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field.               */
69867   #define SAADC_INTENSET_CH0LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH0LIMITL field.                             */
69868   #define SAADC_INTENSET_CH0LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH0LIMITL field.                             */
69869   #define SAADC_INTENSET_CH0LIMITL_Set (0x1UL)       /*!< Enable                                                               */
69870   #define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69871   #define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69872 
69873 /* CH1LIMITH @Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
69874   #define SAADC_INTENSET_CH1LIMITH_Pos (8UL)         /*!< Position of CH1LIMITH field.                                         */
69875   #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field.               */
69876   #define SAADC_INTENSET_CH1LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH1LIMITH field.                             */
69877   #define SAADC_INTENSET_CH1LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH1LIMITH field.                             */
69878   #define SAADC_INTENSET_CH1LIMITH_Set (0x1UL)       /*!< Enable                                                               */
69879   #define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69880   #define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69881 
69882 /* CH1LIMITL @Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
69883   #define SAADC_INTENSET_CH1LIMITL_Pos (9UL)         /*!< Position of CH1LIMITL field.                                         */
69884   #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field.               */
69885   #define SAADC_INTENSET_CH1LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH1LIMITL field.                             */
69886   #define SAADC_INTENSET_CH1LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH1LIMITL field.                             */
69887   #define SAADC_INTENSET_CH1LIMITL_Set (0x1UL)       /*!< Enable                                                               */
69888   #define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69889   #define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69890 
69891 /* CH2LIMITH @Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
69892   #define SAADC_INTENSET_CH2LIMITH_Pos (10UL)        /*!< Position of CH2LIMITH field.                                         */
69893   #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field.               */
69894   #define SAADC_INTENSET_CH2LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH2LIMITH field.                             */
69895   #define SAADC_INTENSET_CH2LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH2LIMITH field.                             */
69896   #define SAADC_INTENSET_CH2LIMITH_Set (0x1UL)       /*!< Enable                                                               */
69897   #define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69898   #define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69899 
69900 /* CH2LIMITL @Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
69901   #define SAADC_INTENSET_CH2LIMITL_Pos (11UL)        /*!< Position of CH2LIMITL field.                                         */
69902   #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field.               */
69903   #define SAADC_INTENSET_CH2LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH2LIMITL field.                             */
69904   #define SAADC_INTENSET_CH2LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH2LIMITL field.                             */
69905   #define SAADC_INTENSET_CH2LIMITL_Set (0x1UL)       /*!< Enable                                                               */
69906   #define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69907   #define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69908 
69909 /* CH3LIMITH @Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
69910   #define SAADC_INTENSET_CH3LIMITH_Pos (12UL)        /*!< Position of CH3LIMITH field.                                         */
69911   #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field.               */
69912   #define SAADC_INTENSET_CH3LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH3LIMITH field.                             */
69913   #define SAADC_INTENSET_CH3LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH3LIMITH field.                             */
69914   #define SAADC_INTENSET_CH3LIMITH_Set (0x1UL)       /*!< Enable                                                               */
69915   #define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69916   #define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69917 
69918 /* CH3LIMITL @Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
69919   #define SAADC_INTENSET_CH3LIMITL_Pos (13UL)        /*!< Position of CH3LIMITL field.                                         */
69920   #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field.               */
69921   #define SAADC_INTENSET_CH3LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH3LIMITL field.                             */
69922   #define SAADC_INTENSET_CH3LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH3LIMITL field.                             */
69923   #define SAADC_INTENSET_CH3LIMITL_Set (0x1UL)       /*!< Enable                                                               */
69924   #define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69925   #define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69926 
69927 /* CH4LIMITH @Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
69928   #define SAADC_INTENSET_CH4LIMITH_Pos (14UL)        /*!< Position of CH4LIMITH field.                                         */
69929   #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field.               */
69930   #define SAADC_INTENSET_CH4LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH4LIMITH field.                             */
69931   #define SAADC_INTENSET_CH4LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH4LIMITH field.                             */
69932   #define SAADC_INTENSET_CH4LIMITH_Set (0x1UL)       /*!< Enable                                                               */
69933   #define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69934   #define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69935 
69936 /* CH4LIMITL @Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
69937   #define SAADC_INTENSET_CH4LIMITL_Pos (15UL)        /*!< Position of CH4LIMITL field.                                         */
69938   #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field.               */
69939   #define SAADC_INTENSET_CH4LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH4LIMITL field.                             */
69940   #define SAADC_INTENSET_CH4LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH4LIMITL field.                             */
69941   #define SAADC_INTENSET_CH4LIMITL_Set (0x1UL)       /*!< Enable                                                               */
69942   #define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69943   #define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69944 
69945 /* CH5LIMITH @Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
69946   #define SAADC_INTENSET_CH5LIMITH_Pos (16UL)        /*!< Position of CH5LIMITH field.                                         */
69947   #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field.               */
69948   #define SAADC_INTENSET_CH5LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH5LIMITH field.                             */
69949   #define SAADC_INTENSET_CH5LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH5LIMITH field.                             */
69950   #define SAADC_INTENSET_CH5LIMITH_Set (0x1UL)       /*!< Enable                                                               */
69951   #define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69952   #define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69953 
69954 /* CH5LIMITL @Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
69955   #define SAADC_INTENSET_CH5LIMITL_Pos (17UL)        /*!< Position of CH5LIMITL field.                                         */
69956   #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field.               */
69957   #define SAADC_INTENSET_CH5LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH5LIMITL field.                             */
69958   #define SAADC_INTENSET_CH5LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH5LIMITL field.                             */
69959   #define SAADC_INTENSET_CH5LIMITL_Set (0x1UL)       /*!< Enable                                                               */
69960   #define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69961   #define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69962 
69963 /* CH6LIMITH @Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
69964   #define SAADC_INTENSET_CH6LIMITH_Pos (18UL)        /*!< Position of CH6LIMITH field.                                         */
69965   #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field.               */
69966   #define SAADC_INTENSET_CH6LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH6LIMITH field.                             */
69967   #define SAADC_INTENSET_CH6LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH6LIMITH field.                             */
69968   #define SAADC_INTENSET_CH6LIMITH_Set (0x1UL)       /*!< Enable                                                               */
69969   #define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69970   #define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69971 
69972 /* CH6LIMITL @Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
69973   #define SAADC_INTENSET_CH6LIMITL_Pos (19UL)        /*!< Position of CH6LIMITL field.                                         */
69974   #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field.               */
69975   #define SAADC_INTENSET_CH6LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH6LIMITL field.                             */
69976   #define SAADC_INTENSET_CH6LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH6LIMITL field.                             */
69977   #define SAADC_INTENSET_CH6LIMITL_Set (0x1UL)       /*!< Enable                                                               */
69978   #define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69979   #define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69980 
69981 /* CH7LIMITH @Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
69982   #define SAADC_INTENSET_CH7LIMITH_Pos (20UL)        /*!< Position of CH7LIMITH field.                                         */
69983   #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field.               */
69984   #define SAADC_INTENSET_CH7LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH7LIMITH field.                             */
69985   #define SAADC_INTENSET_CH7LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH7LIMITH field.                             */
69986   #define SAADC_INTENSET_CH7LIMITH_Set (0x1UL)       /*!< Enable                                                               */
69987   #define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69988   #define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69989 
69990 /* CH7LIMITL @Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
69991   #define SAADC_INTENSET_CH7LIMITL_Pos (21UL)        /*!< Position of CH7LIMITL field.                                         */
69992   #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field.               */
69993   #define SAADC_INTENSET_CH7LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH7LIMITL field.                             */
69994   #define SAADC_INTENSET_CH7LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH7LIMITL field.                             */
69995   #define SAADC_INTENSET_CH7LIMITL_Set (0x1UL)       /*!< Enable                                                               */
69996   #define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
69997   #define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
69998 
69999 
70000 /* SAADC_INTENCLR: Disable interrupt */
70001   #define SAADC_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */
70002 
70003 /* STARTED @Bit 0 : Write '1' to disable interrupt for event STARTED */
70004   #define SAADC_INTENCLR_STARTED_Pos (0UL)           /*!< Position of STARTED field.                                           */
70005   #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                     */
70006   #define SAADC_INTENCLR_STARTED_Min (0x0UL)         /*!< Min enumerator value of STARTED field.                               */
70007   #define SAADC_INTENCLR_STARTED_Max (0x1UL)         /*!< Max enumerator value of STARTED field.                               */
70008   #define SAADC_INTENCLR_STARTED_Clear (0x1UL)       /*!< Disable                                                              */
70009   #define SAADC_INTENCLR_STARTED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
70010   #define SAADC_INTENCLR_STARTED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
70011 
70012 /* END @Bit 1 : Write '1' to disable interrupt for event END */
70013   #define SAADC_INTENCLR_END_Pos (1UL)               /*!< Position of END field.                                               */
70014   #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field.                                 */
70015   #define SAADC_INTENCLR_END_Min (0x0UL)             /*!< Min enumerator value of END field.                                   */
70016   #define SAADC_INTENCLR_END_Max (0x1UL)             /*!< Max enumerator value of END field.                                   */
70017   #define SAADC_INTENCLR_END_Clear (0x1UL)           /*!< Disable                                                              */
70018   #define SAADC_INTENCLR_END_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
70019   #define SAADC_INTENCLR_END_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
70020 
70021 /* DONE @Bit 2 : Write '1' to disable interrupt for event DONE */
70022   #define SAADC_INTENCLR_DONE_Pos (2UL)              /*!< Position of DONE field.                                              */
70023   #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field.                              */
70024   #define SAADC_INTENCLR_DONE_Min (0x0UL)            /*!< Min enumerator value of DONE field.                                  */
70025   #define SAADC_INTENCLR_DONE_Max (0x1UL)            /*!< Max enumerator value of DONE field.                                  */
70026   #define SAADC_INTENCLR_DONE_Clear (0x1UL)          /*!< Disable                                                              */
70027   #define SAADC_INTENCLR_DONE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
70028   #define SAADC_INTENCLR_DONE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
70029 
70030 /* RESULTDONE @Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
70031   #define SAADC_INTENCLR_RESULTDONE_Pos (3UL)        /*!< Position of RESULTDONE field.                                        */
70032   #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field.            */
70033   #define SAADC_INTENCLR_RESULTDONE_Min (0x0UL)      /*!< Min enumerator value of RESULTDONE field.                            */
70034   #define SAADC_INTENCLR_RESULTDONE_Max (0x1UL)      /*!< Max enumerator value of RESULTDONE field.                            */
70035   #define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL)    /*!< Disable                                                              */
70036   #define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled                                                       */
70037   #define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
70038 
70039 /* CALIBRATEDONE @Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
70040   #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL)     /*!< Position of CALIBRATEDONE field.                                     */
70041   #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field.   */
70042   #define SAADC_INTENCLR_CALIBRATEDONE_Min (0x0UL)   /*!< Min enumerator value of CALIBRATEDONE field.                         */
70043   #define SAADC_INTENCLR_CALIBRATEDONE_Max (0x1UL)   /*!< Max enumerator value of CALIBRATEDONE field.                         */
70044   #define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable                                                              */
70045   #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled                                                    */
70046   #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled                                                      */
70047 
70048 /* STOPPED @Bit 5 : Write '1' to disable interrupt for event STOPPED */
70049   #define SAADC_INTENCLR_STOPPED_Pos (5UL)           /*!< Position of STOPPED field.                                           */
70050   #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                     */
70051   #define SAADC_INTENCLR_STOPPED_Min (0x0UL)         /*!< Min enumerator value of STOPPED field.                               */
70052   #define SAADC_INTENCLR_STOPPED_Max (0x1UL)         /*!< Max enumerator value of STOPPED field.                               */
70053   #define SAADC_INTENCLR_STOPPED_Clear (0x1UL)       /*!< Disable                                                              */
70054   #define SAADC_INTENCLR_STOPPED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
70055   #define SAADC_INTENCLR_STOPPED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
70056 
70057 /* CH0LIMITH @Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
70058   #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL)         /*!< Position of CH0LIMITH field.                                         */
70059   #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field.               */
70060   #define SAADC_INTENCLR_CH0LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH0LIMITH field.                             */
70061   #define SAADC_INTENCLR_CH0LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH0LIMITH field.                             */
70062   #define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
70063   #define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70064   #define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70065 
70066 /* CH0LIMITL @Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
70067   #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL)         /*!< Position of CH0LIMITL field.                                         */
70068   #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field.               */
70069   #define SAADC_INTENCLR_CH0LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH0LIMITL field.                             */
70070   #define SAADC_INTENCLR_CH0LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH0LIMITL field.                             */
70071   #define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
70072   #define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70073   #define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70074 
70075 /* CH1LIMITH @Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
70076   #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL)         /*!< Position of CH1LIMITH field.                                         */
70077   #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field.               */
70078   #define SAADC_INTENCLR_CH1LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH1LIMITH field.                             */
70079   #define SAADC_INTENCLR_CH1LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH1LIMITH field.                             */
70080   #define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
70081   #define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70082   #define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70083 
70084 /* CH1LIMITL @Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
70085   #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL)         /*!< Position of CH1LIMITL field.                                         */
70086   #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field.               */
70087   #define SAADC_INTENCLR_CH1LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH1LIMITL field.                             */
70088   #define SAADC_INTENCLR_CH1LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH1LIMITL field.                             */
70089   #define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
70090   #define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70091   #define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70092 
70093 /* CH2LIMITH @Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
70094   #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL)        /*!< Position of CH2LIMITH field.                                         */
70095   #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field.               */
70096   #define SAADC_INTENCLR_CH2LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH2LIMITH field.                             */
70097   #define SAADC_INTENCLR_CH2LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH2LIMITH field.                             */
70098   #define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
70099   #define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70100   #define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70101 
70102 /* CH2LIMITL @Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
70103   #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL)        /*!< Position of CH2LIMITL field.                                         */
70104   #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field.               */
70105   #define SAADC_INTENCLR_CH2LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH2LIMITL field.                             */
70106   #define SAADC_INTENCLR_CH2LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH2LIMITL field.                             */
70107   #define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
70108   #define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70109   #define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70110 
70111 /* CH3LIMITH @Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
70112   #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL)        /*!< Position of CH3LIMITH field.                                         */
70113   #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field.               */
70114   #define SAADC_INTENCLR_CH3LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH3LIMITH field.                             */
70115   #define SAADC_INTENCLR_CH3LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH3LIMITH field.                             */
70116   #define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
70117   #define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70118   #define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70119 
70120 /* CH3LIMITL @Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
70121   #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL)        /*!< Position of CH3LIMITL field.                                         */
70122   #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field.               */
70123   #define SAADC_INTENCLR_CH3LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH3LIMITL field.                             */
70124   #define SAADC_INTENCLR_CH3LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH3LIMITL field.                             */
70125   #define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
70126   #define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70127   #define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70128 
70129 /* CH4LIMITH @Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
70130   #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL)        /*!< Position of CH4LIMITH field.                                         */
70131   #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field.               */
70132   #define SAADC_INTENCLR_CH4LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH4LIMITH field.                             */
70133   #define SAADC_INTENCLR_CH4LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH4LIMITH field.                             */
70134   #define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
70135   #define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70136   #define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70137 
70138 /* CH4LIMITL @Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
70139   #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL)        /*!< Position of CH4LIMITL field.                                         */
70140   #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field.               */
70141   #define SAADC_INTENCLR_CH4LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH4LIMITL field.                             */
70142   #define SAADC_INTENCLR_CH4LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH4LIMITL field.                             */
70143   #define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
70144   #define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70145   #define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70146 
70147 /* CH5LIMITH @Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
70148   #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL)        /*!< Position of CH5LIMITH field.                                         */
70149   #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field.               */
70150   #define SAADC_INTENCLR_CH5LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH5LIMITH field.                             */
70151   #define SAADC_INTENCLR_CH5LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH5LIMITH field.                             */
70152   #define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
70153   #define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70154   #define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70155 
70156 /* CH5LIMITL @Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
70157   #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL)        /*!< Position of CH5LIMITL field.                                         */
70158   #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field.               */
70159   #define SAADC_INTENCLR_CH5LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH5LIMITL field.                             */
70160   #define SAADC_INTENCLR_CH5LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH5LIMITL field.                             */
70161   #define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
70162   #define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70163   #define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70164 
70165 /* CH6LIMITH @Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
70166   #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL)        /*!< Position of CH6LIMITH field.                                         */
70167   #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field.               */
70168   #define SAADC_INTENCLR_CH6LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH6LIMITH field.                             */
70169   #define SAADC_INTENCLR_CH6LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH6LIMITH field.                             */
70170   #define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
70171   #define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70172   #define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70173 
70174 /* CH6LIMITL @Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
70175   #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL)        /*!< Position of CH6LIMITL field.                                         */
70176   #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field.               */
70177   #define SAADC_INTENCLR_CH6LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH6LIMITL field.                             */
70178   #define SAADC_INTENCLR_CH6LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH6LIMITL field.                             */
70179   #define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
70180   #define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70181   #define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70182 
70183 /* CH7LIMITH @Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
70184   #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL)        /*!< Position of CH7LIMITH field.                                         */
70185   #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field.               */
70186   #define SAADC_INTENCLR_CH7LIMITH_Min (0x0UL)       /*!< Min enumerator value of CH7LIMITH field.                             */
70187   #define SAADC_INTENCLR_CH7LIMITH_Max (0x1UL)       /*!< Max enumerator value of CH7LIMITH field.                             */
70188   #define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL)     /*!< Disable                                                              */
70189   #define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70190   #define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70191 
70192 /* CH7LIMITL @Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
70193   #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL)        /*!< Position of CH7LIMITL field.                                         */
70194   #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field.               */
70195   #define SAADC_INTENCLR_CH7LIMITL_Min (0x0UL)       /*!< Min enumerator value of CH7LIMITL field.                             */
70196   #define SAADC_INTENCLR_CH7LIMITL_Max (0x1UL)       /*!< Max enumerator value of CH7LIMITL field.                             */
70197   #define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL)     /*!< Disable                                                              */
70198   #define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
70199   #define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
70200 
70201 
70202 /* SAADC_STATUS: Status */
70203   #define SAADC_STATUS_ResetValue (0x00000000UL)     /*!< Reset value of STATUS register.                                      */
70204 
70205 /* STATUS @Bit 0 : Status */
70206   #define SAADC_STATUS_STATUS_Pos (0UL)              /*!< Position of STATUS field.                                            */
70207   #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field.                            */
70208   #define SAADC_STATUS_STATUS_Min (0x0UL)            /*!< Min enumerator value of STATUS field.                                */
70209   #define SAADC_STATUS_STATUS_Max (0x1UL)            /*!< Max enumerator value of STATUS field.                                */
70210   #define SAADC_STATUS_STATUS_Ready (0x0UL)          /*!< ADC is ready. No on-going conversion.                                */
70211   #define SAADC_STATUS_STATUS_Busy (0x1UL)           /*!< ADC is busy. Single conversion in progress.                          */
70212 
70213 
70214 /* SAADC_ENABLE: Enable or disable ADC */
70215   #define SAADC_ENABLE_ResetValue (0x00000000UL)     /*!< Reset value of ENABLE register.                                      */
70216 
70217 /* ENABLE @Bit 0 : Enable or disable ADC */
70218   #define SAADC_ENABLE_ENABLE_Pos (0UL)              /*!< Position of ENABLE field.                                            */
70219   #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                            */
70220   #define SAADC_ENABLE_ENABLE_Min (0x0UL)            /*!< Min enumerator value of ENABLE field.                                */
70221   #define SAADC_ENABLE_ENABLE_Max (0x1UL)            /*!< Max enumerator value of ENABLE field.                                */
70222   #define SAADC_ENABLE_ENABLE_Disabled (0x0UL)       /*!< Disable ADC                                                          */
70223   #define SAADC_ENABLE_ENABLE_Enabled (0x1UL)        /*!< Enable ADC                                                           */
70224 
70225 
70226 /* SAADC_RESOLUTION: Resolution configuration */
70227   #define SAADC_RESOLUTION_ResetValue (0x00000001UL) /*!< Reset value of RESOLUTION register.                                  */
70228 
70229 /* VAL @Bits 0..2 : Set the resolution */
70230   #define SAADC_RESOLUTION_VAL_Pos (0UL)             /*!< Position of VAL field.                                               */
70231   #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field.                             */
70232   #define SAADC_RESOLUTION_VAL_Min (0x0UL)           /*!< Min enumerator value of VAL field.                                   */
70233   #define SAADC_RESOLUTION_VAL_Max (0x3UL)           /*!< Max enumerator value of VAL field.                                   */
70234   #define SAADC_RESOLUTION_VAL_8bit (0x0UL)          /*!< 8 bit                                                                */
70235   #define SAADC_RESOLUTION_VAL_10bit (0x1UL)         /*!< 10 bit                                                               */
70236   #define SAADC_RESOLUTION_VAL_12bit (0x2UL)         /*!< 12 bit                                                               */
70237   #define SAADC_RESOLUTION_VAL_14bit (0x3UL)         /*!< 14 bit                                                               */
70238 
70239 
70240 /* SAADC_OVERSAMPLE: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before
70241                       averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
70242 
70243   #define SAADC_OVERSAMPLE_ResetValue (0x00000000UL) /*!< Reset value of OVERSAMPLE register.                                  */
70244 
70245 /* OVERSAMPLE @Bits 0..3 : Oversample control */
70246   #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL)      /*!< Position of OVERSAMPLE field.                                        */
70247   #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field.        */
70248   #define SAADC_OVERSAMPLE_OVERSAMPLE_Min (0x0UL)    /*!< Min enumerator value of OVERSAMPLE field.                            */
70249   #define SAADC_OVERSAMPLE_OVERSAMPLE_Max (0x8UL)    /*!< Max enumerator value of OVERSAMPLE field.                            */
70250   #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling                                                  */
70251   #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x                                                        */
70252   #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x                                                        */
70253   #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x                                                        */
70254   #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x                                                      */
70255   #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x                                                      */
70256   #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x                                                      */
70257   #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x                                                    */
70258   #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x                                                    */
70259 
70260 
70261 /* SAADC_SAMPLERATE: Controls normal or continuous sample rate */
70262   #define SAADC_SAMPLERATE_ResetValue (0x00000000UL) /*!< Reset value of SAMPLERATE register.                                  */
70263 
70264 /* CC @Bits 0..10 : Capture and compare value. Sample rate is 16 MHz/CC */
70265   #define SAADC_SAMPLERATE_CC_Pos (0UL)              /*!< Position of CC field.                                                */
70266   #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field.                              */
70267   #define SAADC_SAMPLERATE_CC_Min (0x4UL)            /*!< Min value of CC field.                                               */
70268   #define SAADC_SAMPLERATE_CC_Max (0x7FFUL)          /*!< Max size of CC field.                                                */
70269 
70270 /* MODE @Bit 12 : Select mode for sample rate control */
70271   #define SAADC_SAMPLERATE_MODE_Pos (12UL)           /*!< Position of MODE field.                                              */
70272   #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field.                          */
70273   #define SAADC_SAMPLERATE_MODE_Min (0x0UL)          /*!< Min enumerator value of MODE field.                                  */
70274   #define SAADC_SAMPLERATE_MODE_Max (0x1UL)          /*!< Max enumerator value of MODE field.                                  */
70275   #define SAADC_SAMPLERATE_MODE_Task (0x0UL)         /*!< Rate is controlled from SAMPLE task                                  */
70276   #define SAADC_SAMPLERATE_MODE_Timers (0x1UL)       /*!< Rate is controlled from local timer (use CC to control the rate)     */
70277 
70278 
70279 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
70280 
70281 /* =========================================================================================================================== */
70282 /* ================                                           SPIM                                           ================ */
70283 /* =========================================================================================================================== */
70284 
70285 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
70286 
70287 /* ==================================================== Struct SPIM_PSEL ===================================================== */
70288 /**
70289   * @brief PSEL [SPIM_PSEL] (unspecified)
70290   */
70291 typedef struct {
70292   __IOM uint32_t  SCK;                               /*!< (@ 0x00000000) Pin select for SCK                                    */
70293   __IOM uint32_t  MOSI;                              /*!< (@ 0x00000004) Pin select for MOSI signal                            */
70294   __IOM uint32_t  MISO;                              /*!< (@ 0x00000008) Pin select for MISO signal                            */
70295   __IOM uint32_t  CSN;                               /*!< (@ 0x0000000C) Pin select for CSN                                    */
70296 } NRF_SPIM_PSEL_Type;                                /*!< Size = 16 (0x010)                                                    */
70297 
70298 /* SPIM_PSEL_SCK: Pin select for SCK */
70299   #define SPIM_PSEL_SCK_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SCK register.                                         */
70300 
70301 /* PIN @Bits 0..4 : Pin number */
70302   #define SPIM_PSEL_SCK_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
70303   #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field.                                  */
70304   #define SPIM_PSEL_SCK_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
70305   #define SPIM_PSEL_SCK_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
70306 
70307 /* PORT @Bits 5..8 : Port number */
70308   #define SPIM_PSEL_SCK_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
70309   #define SPIM_PSEL_SCK_PORT_Msk (0xFUL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field.                                */
70310   #define SPIM_PSEL_SCK_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
70311   #define SPIM_PSEL_SCK_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
70312 
70313 /* CONNECT @Bit 31 : Connection */
70314   #define SPIM_PSEL_SCK_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
70315   #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
70316   #define SPIM_PSEL_SCK_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
70317   #define SPIM_PSEL_SCK_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
70318   #define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
70319   #define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
70320 
70321 
70322 /* SPIM_PSEL_MOSI: Pin select for MOSI signal */
70323   #define SPIM_PSEL_MOSI_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MOSI register.                                        */
70324 
70325 /* PIN @Bits 0..4 : Pin number */
70326   #define SPIM_PSEL_MOSI_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
70327   #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field.                                */
70328   #define SPIM_PSEL_MOSI_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
70329   #define SPIM_PSEL_MOSI_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
70330 
70331 /* PORT @Bits 5..8 : Port number */
70332   #define SPIM_PSEL_MOSI_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
70333   #define SPIM_PSEL_MOSI_PORT_Msk (0xFUL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field.                              */
70334   #define SPIM_PSEL_MOSI_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
70335   #define SPIM_PSEL_MOSI_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
70336 
70337 /* CONNECT @Bit 31 : Connection */
70338   #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
70339   #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
70340   #define SPIM_PSEL_MOSI_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
70341   #define SPIM_PSEL_MOSI_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
70342   #define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
70343   #define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
70344 
70345 
70346 /* SPIM_PSEL_MISO: Pin select for MISO signal */
70347   #define SPIM_PSEL_MISO_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MISO register.                                        */
70348 
70349 /* PIN @Bits 0..4 : Pin number */
70350   #define SPIM_PSEL_MISO_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
70351   #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field.                                */
70352   #define SPIM_PSEL_MISO_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
70353   #define SPIM_PSEL_MISO_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
70354 
70355 /* PORT @Bits 5..8 : Port number */
70356   #define SPIM_PSEL_MISO_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
70357   #define SPIM_PSEL_MISO_PORT_Msk (0xFUL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field.                              */
70358   #define SPIM_PSEL_MISO_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
70359   #define SPIM_PSEL_MISO_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
70360 
70361 /* CONNECT @Bit 31 : Connection */
70362   #define SPIM_PSEL_MISO_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
70363   #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
70364   #define SPIM_PSEL_MISO_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
70365   #define SPIM_PSEL_MISO_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
70366   #define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
70367   #define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
70368 
70369 
70370 /* SPIM_PSEL_CSN: Pin select for CSN */
70371   #define SPIM_PSEL_CSN_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of CSN register.                                         */
70372 
70373 /* PIN @Bits 0..4 : Pin number */
70374   #define SPIM_PSEL_CSN_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
70375   #define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field.                                  */
70376   #define SPIM_PSEL_CSN_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
70377   #define SPIM_PSEL_CSN_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
70378 
70379 /* PORT @Bits 5..8 : Port number */
70380   #define SPIM_PSEL_CSN_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
70381   #define SPIM_PSEL_CSN_PORT_Msk (0xFUL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field.                                */
70382   #define SPIM_PSEL_CSN_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
70383   #define SPIM_PSEL_CSN_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
70384 
70385 /* CONNECT @Bit 31 : Connection */
70386   #define SPIM_PSEL_CSN_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
70387   #define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
70388   #define SPIM_PSEL_CSN_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
70389   #define SPIM_PSEL_CSN_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
70390   #define SPIM_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
70391   #define SPIM_PSEL_CSN_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
70392 
70393 
70394 
70395 /* ===================================================== Struct SPIM_RXD ===================================================== */
70396 /**
70397   * @brief RXD [SPIM_RXD] RXD EasyDMA channel
70398   */
70399 typedef struct {
70400   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
70401   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in receive buffer             */
70402   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last transaction   */
70403   __IOM uint32_t  LIST;                              /*!< (@ 0x0000000C) EasyDMA list type                                     */
70404 } NRF_SPIM_RXD_Type;                                 /*!< Size = 16 (0x010)                                                    */
70405 
70406 /* SPIM_RXD_PTR: Data pointer */
70407   #define SPIM_RXD_PTR_ResetValue (0x00000000UL)     /*!< Reset value of PTR register.                                         */
70408 
70409 /* PTR @Bits 0..31 : Data pointer */
70410   #define SPIM_RXD_PTR_PTR_Pos (0UL)                 /*!< Position of PTR field.                                               */
70411   #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                              */
70412 
70413 
70414 /* SPIM_RXD_MAXCNT: Maximum number of bytes in receive buffer */
70415   #define SPIM_RXD_MAXCNT_ResetValue (0x00000000UL)  /*!< Reset value of MAXCNT register.                                      */
70416 
70417 /* MAXCNT @Bits 0..14 : Maximum number of bytes in receive buffer */
70418   #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL)           /*!< Position of MAXCNT field.                                            */
70419   #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                   */
70420   #define SPIM_RXD_MAXCNT_MAXCNT_Min (0x1UL)         /*!< Min value of MAXCNT field.                                           */
70421   #define SPIM_RXD_MAXCNT_MAXCNT_Max (0x7FFFUL)      /*!< Max size of MAXCNT field.                                            */
70422 
70423 
70424 /* SPIM_RXD_AMOUNT: Number of bytes transferred in the last transaction */
70425   #define SPIM_RXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
70426 
70427 /* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction */
70428   #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL)           /*!< Position of AMOUNT field.                                            */
70429   #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
70430   #define SPIM_RXD_AMOUNT_AMOUNT_Min (0x1UL)         /*!< Min value of AMOUNT field.                                           */
70431   #define SPIM_RXD_AMOUNT_AMOUNT_Max (0x7FFFUL)      /*!< Max size of AMOUNT field.                                            */
70432 
70433 
70434 /* SPIM_RXD_LIST: EasyDMA list type */
70435   #define SPIM_RXD_LIST_ResetValue (0x00000000UL)    /*!< Reset value of LIST register.                                        */
70436 
70437 /* LIST @Bits 0..1 : List type */
70438   #define SPIM_RXD_LIST_LIST_Pos (0UL)               /*!< Position of LIST field.                                              */
70439   #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field.                                */
70440   #define SPIM_RXD_LIST_LIST_Min (0x0UL)             /*!< Min enumerator value of LIST field.                                  */
70441   #define SPIM_RXD_LIST_LIST_Max (0x1UL)             /*!< Max enumerator value of LIST field.                                  */
70442   #define SPIM_RXD_LIST_LIST_Disabled (0x0UL)        /*!< Disable EasyDMA list                                                 */
70443   #define SPIM_RXD_LIST_LIST_ArrayList (0x1UL)       /*!< Use array list                                                       */
70444 
70445 
70446 
70447 /* ===================================================== Struct SPIM_TXD ===================================================== */
70448 /**
70449   * @brief TXD [SPIM_TXD] TXD EasyDMA channel
70450   */
70451 typedef struct {
70452   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
70453   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Number of bytes in transmit buffer                    */
70454   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last transaction   */
70455   __IOM uint32_t  LIST;                              /*!< (@ 0x0000000C) EasyDMA list type                                     */
70456 } NRF_SPIM_TXD_Type;                                 /*!< Size = 16 (0x010)                                                    */
70457 
70458 /* SPIM_TXD_PTR: Data pointer */
70459   #define SPIM_TXD_PTR_ResetValue (0x00000000UL)     /*!< Reset value of PTR register.                                         */
70460 
70461 /* PTR @Bits 0..31 : Data pointer */
70462   #define SPIM_TXD_PTR_PTR_Pos (0UL)                 /*!< Position of PTR field.                                               */
70463   #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                              */
70464 
70465 
70466 /* SPIM_TXD_MAXCNT: Number of bytes in transmit buffer */
70467   #define SPIM_TXD_MAXCNT_ResetValue (0x00000000UL)  /*!< Reset value of MAXCNT register.                                      */
70468 
70469 /* MAXCNT @Bits 0..14 : Maximum number of bytes in transmit buffer */
70470   #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL)           /*!< Position of MAXCNT field.                                            */
70471   #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                   */
70472   #define SPIM_TXD_MAXCNT_MAXCNT_Min (0x1UL)         /*!< Min value of MAXCNT field.                                           */
70473   #define SPIM_TXD_MAXCNT_MAXCNT_Max (0x7FFFUL)      /*!< Max size of MAXCNT field.                                            */
70474 
70475 
70476 /* SPIM_TXD_AMOUNT: Number of bytes transferred in the last transaction */
70477   #define SPIM_TXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
70478 
70479 /* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction */
70480   #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL)           /*!< Position of AMOUNT field.                                            */
70481   #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
70482   #define SPIM_TXD_AMOUNT_AMOUNT_Min (0x1UL)         /*!< Min value of AMOUNT field.                                           */
70483   #define SPIM_TXD_AMOUNT_AMOUNT_Max (0x7FFFUL)      /*!< Max size of AMOUNT field.                                            */
70484 
70485 
70486 /* SPIM_TXD_LIST: EasyDMA list type */
70487   #define SPIM_TXD_LIST_ResetValue (0x00000000UL)    /*!< Reset value of LIST register.                                        */
70488 
70489 /* LIST @Bits 0..1 : List type */
70490   #define SPIM_TXD_LIST_LIST_Pos (0UL)               /*!< Position of LIST field.                                              */
70491   #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field.                                */
70492   #define SPIM_TXD_LIST_LIST_Min (0x0UL)             /*!< Min enumerator value of LIST field.                                  */
70493   #define SPIM_TXD_LIST_LIST_Max (0x1UL)             /*!< Max enumerator value of LIST field.                                  */
70494   #define SPIM_TXD_LIST_LIST_Disabled (0x0UL)        /*!< Disable EasyDMA list                                                 */
70495   #define SPIM_TXD_LIST_LIST_ArrayList (0x1UL)       /*!< Use array list                                                       */
70496 
70497 
70498 
70499 /* ================================================== Struct SPIM_IFTIMING =================================================== */
70500 /**
70501   * @brief IFTIMING [SPIM_IFTIMING] (unspecified)
70502   */
70503 typedef struct {
70504   __IOM uint32_t  RXDELAY;                           /*!< (@ 0x00000000) Sample delay for input serial data on MISO            */
70505   __IOM uint32_t  CSNDUR;                            /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge of SCK.
70506                                                                          When SHORTS.END_START is used, this is also the minimum
70507                                                                          duration CSN must stay high between transactions.*/
70508 } NRF_SPIM_IFTIMING_Type;                            /*!< Size = 8 (0x008)                                                     */
70509 
70510 /* SPIM_IFTIMING_RXDELAY: Sample delay for input serial data on MISO */
70511   #define SPIM_IFTIMING_RXDELAY_ResetValue (0x00000002UL) /*!< Reset value of RXDELAY register.                                */
70512 
70513 /* RXDELAY @Bits 0..2 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles
70514                         (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for
70515                         CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA =
70516                         0, the input serial data is sampled on the rising edge of SCK. */
70517 
70518   #define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL)    /*!< Position of RXDELAY field.                                           */
70519   #define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field.       */
70520   #define SPIM_IFTIMING_RXDELAY_RXDELAY_Min (0x0UL)  /*!< Min value of RXDELAY field.                                          */
70521   #define SPIM_IFTIMING_RXDELAY_RXDELAY_Max (0x7UL)  /*!< Max size of RXDELAY field.                                           */
70522 
70523 
70524 /* SPIM_IFTIMING_CSNDUR: Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the
70525                           minimum duration CSN must stay high between transactions. */
70526 
70527   #define SPIM_IFTIMING_CSNDUR_ResetValue (0x00000002UL) /*!< Reset value of CSNDUR register.                                  */
70528 
70529 /* CSNDUR @Bits 0..7 : Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is the minimum
70530                        duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles
70531                        (15.625 ns). */
70532 
70533   #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL)      /*!< Position of CSNDUR field.                                            */
70534   #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field.           */
70535   #define SPIM_IFTIMING_CSNDUR_CSNDUR_Min (0x0UL)    /*!< Min value of CSNDUR field.                                           */
70536   #define SPIM_IFTIMING_CSNDUR_CSNDUR_Max (0xFFUL)   /*!< Max size of CSNDUR field.                                            */
70537 
70538 
70539 
70540 /* =================================================== Struct SPIM_DMA_RX ==================================================== */
70541 /**
70542   * @brief RX [SPIM_DMA_RX] (unspecified)
70543   */
70544 typedef struct {
70545   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
70546                                                                          detected.*/
70547   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
70548                                                                          event.*/
70549 } NRF_SPIM_DMA_RX_Type;                              /*!< Size = 8 (0x008)                                                     */
70550 
70551 /* SPIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
70552   #define SPIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */
70553 
70554 /* ENABLE @Bit 0 : (unspecified) */
70555   #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
70556   #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
70557                                                                             ENABLE field.*/
70558   #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
70559   #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
70560   #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
70561   #define SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */
70562 
70563 
70564 /* SPIM_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
70565   #define SPIM_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */
70566 
70567 /* ADDRESS @Bits 0..31 : (unspecified) */
70568   #define SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
70569   #define SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
70570                                                                             ADDRESS field.*/
70571 
70572 
70573 
70574 /* =================================================== Struct SPIM_DMA_TX ==================================================== */
70575 /**
70576   * @brief TX [SPIM_DMA_TX] (unspecified)
70577   */
70578 typedef struct {
70579   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
70580                                                                          detected.*/
70581   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
70582                                                                          event.*/
70583 } NRF_SPIM_DMA_TX_Type;                              /*!< Size = 8 (0x008)                                                     */
70584 
70585 /* SPIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
70586   #define SPIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */
70587 
70588 /* ENABLE @Bit 0 : (unspecified) */
70589   #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
70590   #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
70591                                                                             ENABLE field.*/
70592   #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
70593   #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
70594   #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
70595   #define SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */
70596 
70597 
70598 /* SPIM_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
70599   #define SPIM_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */
70600 
70601 /* ADDRESS @Bits 0..31 : (unspecified) */
70602   #define SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
70603   #define SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
70604                                                                             ADDRESS field.*/
70605 
70606 
70607 
70608 /* ===================================================== Struct SPIM_DMA ===================================================== */
70609 /**
70610   * @brief DMA [SPIM_DMA] (unspecified)
70611   */
70612 typedef struct {
70613   __IOM NRF_SPIM_DMA_RX_Type RX;                     /*!< (@ 0x00000000) (unspecified)                                         */
70614   __IOM NRF_SPIM_DMA_TX_Type TX;                     /*!< (@ 0x00000008) (unspecified)                                         */
70615 } NRF_SPIM_DMA_Type;                                 /*!< Size = 16 (0x010)                                                    */
70616 
70617 /* ======================================================= Struct SPIM ======================================================= */
70618 /**
70619   * @brief Serial Peripheral Interface Master with EasyDMA
70620   */
70621   typedef struct {                                   /*!< SPIM Structure                                                       */
70622     __IM uint32_t RESERVED[4];
70623     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000010) Start SPI transaction                                 */
70624     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000014) Stop SPI transaction                                  */
70625     __IM uint32_t RESERVED1;
70626     __OM uint32_t TASKS_SUSPEND;                     /*!< (@ 0x0000001C) Suspend SPI transaction                               */
70627     __OM uint32_t TASKS_RESUME;                      /*!< (@ 0x00000020) Resume SPI transaction                                */
70628     __IM uint32_t RESERVED2[27];
70629     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000090) Subscribe configuration for task START                */
70630     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000094) Subscribe configuration for task STOP                 */
70631     __IM uint32_t RESERVED3;
70632     __IOM uint32_t SUBSCRIBE_SUSPEND;                /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND              */
70633     __IOM uint32_t SUBSCRIBE_RESUME;                 /*!< (@ 0x000000A0) Subscribe configuration for task RESUME               */
70634     __IM uint32_t RESERVED4[24];
70635     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) SPI transaction has stopped                           */
70636     __IM uint32_t RESERVED5[2];
70637     __IOM uint32_t EVENTS_ENDRX;                     /*!< (@ 0x00000110) End of RXD buffer reached                             */
70638     __IM uint32_t RESERVED6;
70639     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached              */
70640     __IM uint32_t RESERVED7;
70641     __IOM uint32_t EVENTS_ENDTX;                     /*!< (@ 0x00000120) End of TXD buffer reached                             */
70642     __IM uint32_t RESERVED8[10];
70643     __IOM uint32_t EVENTS_STARTED;                   /*!< (@ 0x0000014C) Transaction started                                   */
70644     __IM uint32_t RESERVED9[9];
70645     __IOM uint32_t EVENTS_RXBUSERROR;                /*!< (@ 0x00000174) This event is generated if an error occurs during the
70646                                                                          bus transfer.*/
70647     __IOM uint32_t EVENTS_TXBUSERROR;                /*!< (@ 0x00000178) This event is generated if an error occurs during the
70648                                                                          bus transfer.*/
70649     __IM uint32_t RESERVED10[2];
70650     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
70651     __IM uint32_t RESERVED11[2];
70652     __IOM uint32_t PUBLISH_ENDRX;                    /*!< (@ 0x00000190) Publish configuration for event ENDRX                 */
70653     __IM uint32_t RESERVED12;
70654     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000198) Publish configuration for event END                   */
70655     __IM uint32_t RESERVED13;
70656     __IOM uint32_t PUBLISH_ENDTX;                    /*!< (@ 0x000001A0) Publish configuration for event ENDTX                 */
70657     __IM uint32_t RESERVED14[10];
70658     __IOM uint32_t PUBLISH_STARTED;                  /*!< (@ 0x000001CC) Publish configuration for event STARTED               */
70659     __IM uint32_t RESERVED15[9];
70660     __IOM uint32_t PUBLISH_RXBUSERROR;               /*!< (@ 0x000001F4) Publish configuration for event RXBUSERROR            */
70661     __IOM uint32_t PUBLISH_TXBUSERROR;               /*!< (@ 0x000001F8) Publish configuration for event TXBUSERROR            */
70662     __IM uint32_t RESERVED16;
70663     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
70664     __IM uint32_t RESERVED17[64];
70665     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
70666     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
70667     __IM uint32_t RESERVED18[61];
70668     __IOM uint32_t STALLSTAT;                        /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields in
70669                                                                          this register are set to STALL by hardware whenever a
70670                                                                          stall occurres and can be cleared (set to NOSTALL) by
70671                                                                          the CPU.*/
70672     __IM uint32_t RESERVED19[63];
70673     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable SPIM                                           */
70674     __IM uint32_t RESERVED20;
70675     __IOM NRF_SPIM_PSEL_Type PSEL;                   /*!< (@ 0x00000508) (unspecified)                                         */
70676     __IM uint32_t RESERVED21[3];
70677     __IOM uint32_t FREQUENCY;                        /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK source
70678                                                                          selected.*/
70679     __IM uint32_t RESERVED22[3];
70680     __IOM NRF_SPIM_RXD_Type RXD;                     /*!< (@ 0x00000534) RXD EasyDMA channel                                   */
70681     __IOM NRF_SPIM_TXD_Type TXD;                     /*!< (@ 0x00000544) TXD EasyDMA channel                                   */
70682     __IOM uint32_t CONFIG;                           /*!< (@ 0x00000554) Configuration register                                */
70683     __IM uint32_t RESERVED23[2];
70684     __IOM NRF_SPIM_IFTIMING_Type IFTIMING;           /*!< (@ 0x00000560) (unspecified)                                         */
70685     __IOM uint32_t CSNPOL;                           /*!< (@ 0x00000568) Polarity of CSN output                                */
70686     __IOM uint32_t PSELDCX;                          /*!< (@ 0x0000056C) Pin select for DCX signal                             */
70687     __IOM uint32_t DCXCNT;                           /*!< (@ 0x00000570) DCX configuration                                     */
70688     __IM uint32_t RESERVED24[15];
70689     __IOM NRF_SPIM_DMA_Type DMA;                     /*!< (@ 0x000005B0) (unspecified)                                         */
70690     __IOM uint32_t ORC;                              /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have been
70691                                                                          transmitted in the case when RXD.MAXCNT is greater than
70692                                                                          TXD.MAXCNT*/
70693   } NRF_SPIM_Type;                                   /*!< Size = 1476 (0x5C4)                                                  */
70694 
70695 /* SPIM_TASKS_START: Start SPI transaction */
70696   #define SPIM_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */
70697 
70698 /* TASKS_START @Bit 0 : Start SPI transaction */
70699   #define SPIM_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
70700   #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
70701   #define SPIM_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
70702   #define SPIM_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
70703   #define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */
70704 
70705 
70706 /* SPIM_TASKS_STOP: Stop SPI transaction */
70707   #define SPIM_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */
70708 
70709 /* TASKS_STOP @Bit 0 : Stop SPI transaction */
70710   #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
70711   #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
70712   #define SPIM_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
70713   #define SPIM_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
70714   #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */
70715 
70716 
70717 /* SPIM_TASKS_SUSPEND: Suspend SPI transaction */
70718   #define SPIM_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register.                             */
70719 
70720 /* TASKS_SUSPEND @Bit 0 : Suspend SPI transaction */
70721   #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field.                                     */
70722   #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND
70723                                                                             field.*/
70724   #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field.                       */
70725   #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field.                       */
70726   #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task                                                   */
70727 
70728 
70729 /* SPIM_TASKS_RESUME: Resume SPI transaction */
70730   #define SPIM_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register.                               */
70731 
70732 /* TASKS_RESUME @Bit 0 : Resume SPI transaction */
70733   #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)   /*!< Position of TASKS_RESUME field.                                      */
70734   #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/
70735   #define SPIM_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field.                          */
70736   #define SPIM_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field.                          */
70737   #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task                                                     */
70738 
70739 
70740 /* SPIM_SUBSCRIBE_START: Subscribe configuration for task START */
70741   #define SPIM_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                         */
70742 
70743 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
70744   #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
70745   #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
70746   #define SPIM_SUBSCRIBE_START_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
70747   #define SPIM_SUBSCRIBE_START_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
70748 
70749 /* EN @Bit 31 : (unspecified) */
70750   #define SPIM_SUBSCRIBE_START_EN_Pos (31UL)         /*!< Position of EN field.                                                */
70751   #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                        */
70752   #define SPIM_SUBSCRIBE_START_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
70753   #define SPIM_SUBSCRIBE_START_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
70754   #define SPIM_SUBSCRIBE_START_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
70755   #define SPIM_SUBSCRIBE_START_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
70756 
70757 
70758 /* SPIM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
70759   #define SPIM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */
70760 
70761 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
70762   #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
70763   #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
70764   #define SPIM_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
70765   #define SPIM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
70766 
70767 /* EN @Bit 31 : (unspecified) */
70768   #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
70769   #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
70770   #define SPIM_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
70771   #define SPIM_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
70772   #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
70773   #define SPIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
70774 
70775 
70776 /* SPIM_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */
70777   #define SPIM_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register.                     */
70778 
70779 /* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */
70780   #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
70781   #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
70782   #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
70783   #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
70784 
70785 /* EN @Bit 31 : (unspecified) */
70786   #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)       /*!< Position of EN field.                                                */
70787   #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field.                    */
70788   #define SPIM_SUBSCRIBE_SUSPEND_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
70789   #define SPIM_SUBSCRIBE_SUSPEND_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
70790   #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
70791   #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
70792 
70793 
70794 /* SPIM_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */
70795   #define SPIM_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register.                       */
70796 
70797 /* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */
70798   #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
70799   #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
70800   #define SPIM_SUBSCRIBE_RESUME_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
70801   #define SPIM_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
70802 
70803 /* EN @Bit 31 : (unspecified) */
70804   #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL)        /*!< Position of EN field.                                                */
70805   #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field.                      */
70806   #define SPIM_SUBSCRIBE_RESUME_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
70807   #define SPIM_SUBSCRIBE_RESUME_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
70808   #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
70809   #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
70810 
70811 
70812 /* SPIM_EVENTS_STOPPED: SPI transaction has stopped */
70813   #define SPIM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                           */
70814 
70815 /* EVENTS_STOPPED @Bit 0 : SPI transaction has stopped */
70816   #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                  */
70817   #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
70818                                                                             EVENTS_STOPPED field.*/
70819   #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                    */
70820   #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                    */
70821   #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                     */
70822   #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                            */
70823 
70824 
70825 /* SPIM_EVENTS_ENDRX: End of RXD buffer reached */
70826   #define SPIM_EVENTS_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDRX register.                               */
70827 
70828 /* EVENTS_ENDRX @Bit 0 : End of RXD buffer reached */
70829   #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)   /*!< Position of EVENTS_ENDRX field.                                      */
70830   #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field.*/
70831   #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDRX field.                          */
70832   #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDRX field.                          */
70833   #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated                                         */
70834   #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated                                                */
70835 
70836 
70837 /* SPIM_EVENTS_END: End of RXD buffer and TXD buffer reached */
70838   #define SPIM_EVENTS_END_ResetValue (0x00000000UL)  /*!< Reset value of EVENTS_END register.                                  */
70839 
70840 /* EVENTS_END @Bit 0 : End of RXD buffer and TXD buffer reached */
70841   #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL)       /*!< Position of EVENTS_END field.                                        */
70842   #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.          */
70843   #define SPIM_EVENTS_END_EVENTS_END_Min (0x0UL)     /*!< Min enumerator value of EVENTS_END field.                            */
70844   #define SPIM_EVENTS_END_EVENTS_END_Max (0x1UL)     /*!< Max enumerator value of EVENTS_END field.                            */
70845   #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
70846   #define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                    */
70847 
70848 
70849 /* SPIM_EVENTS_ENDTX: End of TXD buffer reached */
70850   #define SPIM_EVENTS_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDTX register.                               */
70851 
70852 /* EVENTS_ENDTX @Bit 0 : End of TXD buffer reached */
70853   #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)   /*!< Position of EVENTS_ENDTX field.                                      */
70854   #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field.*/
70855   #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDTX field.                          */
70856   #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDTX field.                          */
70857   #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated                                         */
70858   #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated                                                */
70859 
70860 
70861 /* SPIM_EVENTS_STARTED: Transaction started */
70862   #define SPIM_EVENTS_STARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STARTED register.                           */
70863 
70864 /* EVENTS_STARTED @Bit 0 : Transaction started */
70865   #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field.                                  */
70866   #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of
70867                                                                             EVENTS_STARTED field.*/
70868   #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STARTED field.                    */
70869   #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STARTED field.                    */
70870   #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated                                     */
70871   #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated                                            */
70872 
70873 
70874 /* SPIM_EVENTS_RXBUSERROR: This event is generated if an error occurs during the bus transfer. */
70875   #define SPIM_EVENTS_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXBUSERROR register.                     */
70876 
70877 /* EVENTS_RXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
70878   #define SPIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos (0UL) /*!< Position of EVENTS_RXBUSERROR field.                         */
70879   #define SPIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Msk (0x1UL << SPIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos) /*!< Bit mask of
70880                                                                             EVENTS_RXBUSERROR field.*/
70881   #define SPIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXBUSERROR field.           */
70882   #define SPIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXBUSERROR field.           */
70883   #define SPIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                               */
70884   #define SPIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Generated (0x1UL) /*!< Event generated                                      */
70885 
70886 
70887 /* SPIM_EVENTS_TXBUSERROR: This event is generated if an error occurs during the bus transfer. */
70888   #define SPIM_EVENTS_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXBUSERROR register.                     */
70889 
70890 /* EVENTS_TXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
70891   #define SPIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos (0UL) /*!< Position of EVENTS_TXBUSERROR field.                         */
70892   #define SPIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Msk (0x1UL << SPIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos) /*!< Bit mask of
70893                                                                             EVENTS_TXBUSERROR field.*/
70894   #define SPIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXBUSERROR field.           */
70895   #define SPIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXBUSERROR field.           */
70896   #define SPIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                               */
70897   #define SPIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Generated (0x1UL) /*!< Event generated                                      */
70898 
70899 
70900 /* SPIM_PUBLISH_STOPPED: Publish configuration for event STOPPED */
70901   #define SPIM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                         */
70902 
70903 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
70904   #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
70905   #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
70906   #define SPIM_PUBLISH_STOPPED_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
70907   #define SPIM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
70908 
70909 /* EN @Bit 31 : (unspecified) */
70910   #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
70911   #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                        */
70912   #define SPIM_PUBLISH_STOPPED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
70913   #define SPIM_PUBLISH_STOPPED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
70914   #define SPIM_PUBLISH_STOPPED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
70915   #define SPIM_PUBLISH_STOPPED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
70916 
70917 
70918 /* SPIM_PUBLISH_ENDRX: Publish configuration for event ENDRX */
70919   #define SPIM_PUBLISH_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDRX register.                             */
70920 
70921 /* CHIDX @Bits 0..7 : DPPI channel that event ENDRX will publish to */
70922   #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
70923   #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
70924   #define SPIM_PUBLISH_ENDRX_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
70925   #define SPIM_PUBLISH_ENDRX_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
70926 
70927 /* EN @Bit 31 : (unspecified) */
70928   #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL)           /*!< Position of EN field.                                                */
70929   #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field.                            */
70930   #define SPIM_PUBLISH_ENDRX_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
70931   #define SPIM_PUBLISH_ENDRX_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
70932   #define SPIM_PUBLISH_ENDRX_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
70933   #define SPIM_PUBLISH_ENDRX_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
70934 
70935 
70936 /* SPIM_PUBLISH_END: Publish configuration for event END */
70937   #define SPIM_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                 */
70938 
70939 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
70940   #define SPIM_PUBLISH_END_CHIDX_Pos (0UL)           /*!< Position of CHIDX field.                                             */
70941   #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                      */
70942   #define SPIM_PUBLISH_END_CHIDX_Min (0x0UL)         /*!< Min value of CHIDX field.                                            */
70943   #define SPIM_PUBLISH_END_CHIDX_Max (0xFFUL)        /*!< Max size of CHIDX field.                                             */
70944 
70945 /* EN @Bit 31 : (unspecified) */
70946   #define SPIM_PUBLISH_END_EN_Pos (31UL)             /*!< Position of EN field.                                                */
70947   #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                */
70948   #define SPIM_PUBLISH_END_EN_Min (0x0UL)            /*!< Min enumerator value of EN field.                                    */
70949   #define SPIM_PUBLISH_END_EN_Max (0x1UL)            /*!< Max enumerator value of EN field.                                    */
70950   #define SPIM_PUBLISH_END_EN_Disabled (0x0UL)       /*!< Disable publishing                                                   */
70951   #define SPIM_PUBLISH_END_EN_Enabled (0x1UL)        /*!< Enable publishing                                                    */
70952 
70953 
70954 /* SPIM_PUBLISH_ENDTX: Publish configuration for event ENDTX */
70955   #define SPIM_PUBLISH_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDTX register.                             */
70956 
70957 /* CHIDX @Bits 0..7 : DPPI channel that event ENDTX will publish to */
70958   #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
70959   #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
70960   #define SPIM_PUBLISH_ENDTX_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
70961   #define SPIM_PUBLISH_ENDTX_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
70962 
70963 /* EN @Bit 31 : (unspecified) */
70964   #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL)           /*!< Position of EN field.                                                */
70965   #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field.                            */
70966   #define SPIM_PUBLISH_ENDTX_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
70967   #define SPIM_PUBLISH_ENDTX_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
70968   #define SPIM_PUBLISH_ENDTX_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
70969   #define SPIM_PUBLISH_ENDTX_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
70970 
70971 
70972 /* SPIM_PUBLISH_STARTED: Publish configuration for event STARTED */
70973   #define SPIM_PUBLISH_STARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STARTED register.                         */
70974 
70975 /* CHIDX @Bits 0..7 : DPPI channel that event STARTED will publish to */
70976   #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
70977   #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
70978   #define SPIM_PUBLISH_STARTED_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
70979   #define SPIM_PUBLISH_STARTED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
70980 
70981 /* EN @Bit 31 : (unspecified) */
70982   #define SPIM_PUBLISH_STARTED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
70983   #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field.                        */
70984   #define SPIM_PUBLISH_STARTED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
70985   #define SPIM_PUBLISH_STARTED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
70986   #define SPIM_PUBLISH_STARTED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
70987   #define SPIM_PUBLISH_STARTED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
70988 
70989 
70990 /* SPIM_PUBLISH_RXBUSERROR: Publish configuration for event RXBUSERROR */
70991   #define SPIM_PUBLISH_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXBUSERROR register.                   */
70992 
70993 /* CHIDX @Bits 0..7 : DPPI channel that event RXBUSERROR will publish to */
70994   #define SPIM_PUBLISH_RXBUSERROR_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
70995   #define SPIM_PUBLISH_RXBUSERROR_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_RXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
70996   #define SPIM_PUBLISH_RXBUSERROR_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
70997   #define SPIM_PUBLISH_RXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
70998 
70999 /* EN @Bit 31 : (unspecified) */
71000   #define SPIM_PUBLISH_RXBUSERROR_EN_Pos (31UL)      /*!< Position of EN field.                                                */
71001   #define SPIM_PUBLISH_RXBUSERROR_EN_Msk (0x1UL << SPIM_PUBLISH_RXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                  */
71002   #define SPIM_PUBLISH_RXBUSERROR_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
71003   #define SPIM_PUBLISH_RXBUSERROR_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
71004   #define SPIM_PUBLISH_RXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
71005   #define SPIM_PUBLISH_RXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
71006 
71007 
71008 /* SPIM_PUBLISH_TXBUSERROR: Publish configuration for event TXBUSERROR */
71009   #define SPIM_PUBLISH_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXBUSERROR register.                   */
71010 
71011 /* CHIDX @Bits 0..7 : DPPI channel that event TXBUSERROR will publish to */
71012   #define SPIM_PUBLISH_TXBUSERROR_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
71013   #define SPIM_PUBLISH_TXBUSERROR_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_TXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
71014   #define SPIM_PUBLISH_TXBUSERROR_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
71015   #define SPIM_PUBLISH_TXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
71016 
71017 /* EN @Bit 31 : (unspecified) */
71018   #define SPIM_PUBLISH_TXBUSERROR_EN_Pos (31UL)      /*!< Position of EN field.                                                */
71019   #define SPIM_PUBLISH_TXBUSERROR_EN_Msk (0x1UL << SPIM_PUBLISH_TXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                  */
71020   #define SPIM_PUBLISH_TXBUSERROR_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
71021   #define SPIM_PUBLISH_TXBUSERROR_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
71022   #define SPIM_PUBLISH_TXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
71023   #define SPIM_PUBLISH_TXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
71024 
71025 
71026 /* SPIM_SHORTS: Shortcuts between local events and tasks */
71027   #define SPIM_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */
71028 
71029 /* END_START @Bit 17 : Shortcut between event END and task START */
71030   #define SPIM_SHORTS_END_START_Pos (17UL)           /*!< Position of END_START field.                                         */
71031   #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field.                     */
71032   #define SPIM_SHORTS_END_START_Min (0x0UL)          /*!< Min enumerator value of END_START field.                             */
71033   #define SPIM_SHORTS_END_START_Max (0x1UL)          /*!< Max enumerator value of END_START field.                             */
71034   #define SPIM_SHORTS_END_START_Disabled (0x0UL)     /*!< Disable shortcut                                                     */
71035   #define SPIM_SHORTS_END_START_Enabled (0x1UL)      /*!< Enable shortcut                                                      */
71036 
71037 
71038 /* SPIM_INTENSET: Enable interrupt */
71039   #define SPIM_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */
71040 
71041 /* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
71042   #define SPIM_INTENSET_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
71043   #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
71044   #define SPIM_INTENSET_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
71045   #define SPIM_INTENSET_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
71046   #define SPIM_INTENSET_STOPPED_Set (0x1UL)          /*!< Enable                                                               */
71047   #define SPIM_INTENSET_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
71048   #define SPIM_INTENSET_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
71049 
71050 /* ENDRX @Bit 4 : Write '1' to enable interrupt for event ENDRX */
71051   #define SPIM_INTENSET_ENDRX_Pos (4UL)              /*!< Position of ENDRX field.                                             */
71052   #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field.                             */
71053   #define SPIM_INTENSET_ENDRX_Min (0x0UL)            /*!< Min enumerator value of ENDRX field.                                 */
71054   #define SPIM_INTENSET_ENDRX_Max (0x1UL)            /*!< Max enumerator value of ENDRX field.                                 */
71055   #define SPIM_INTENSET_ENDRX_Set (0x1UL)            /*!< Enable                                                               */
71056   #define SPIM_INTENSET_ENDRX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
71057   #define SPIM_INTENSET_ENDRX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
71058 
71059 /* END @Bit 6 : Write '1' to enable interrupt for event END */
71060   #define SPIM_INTENSET_END_Pos (6UL)                /*!< Position of END field.                                               */
71061   #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field.                                   */
71062   #define SPIM_INTENSET_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
71063   #define SPIM_INTENSET_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
71064   #define SPIM_INTENSET_END_Set (0x1UL)              /*!< Enable                                                               */
71065   #define SPIM_INTENSET_END_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
71066   #define SPIM_INTENSET_END_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
71067 
71068 /* ENDTX @Bit 8 : Write '1' to enable interrupt for event ENDTX */
71069   #define SPIM_INTENSET_ENDTX_Pos (8UL)              /*!< Position of ENDTX field.                                             */
71070   #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field.                             */
71071   #define SPIM_INTENSET_ENDTX_Min (0x0UL)            /*!< Min enumerator value of ENDTX field.                                 */
71072   #define SPIM_INTENSET_ENDTX_Max (0x1UL)            /*!< Max enumerator value of ENDTX field.                                 */
71073   #define SPIM_INTENSET_ENDTX_Set (0x1UL)            /*!< Enable                                                               */
71074   #define SPIM_INTENSET_ENDTX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
71075   #define SPIM_INTENSET_ENDTX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
71076 
71077 /* STARTED @Bit 19 : Write '1' to enable interrupt for event STARTED */
71078   #define SPIM_INTENSET_STARTED_Pos (19UL)           /*!< Position of STARTED field.                                           */
71079   #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
71080   #define SPIM_INTENSET_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
71081   #define SPIM_INTENSET_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
71082   #define SPIM_INTENSET_STARTED_Set (0x1UL)          /*!< Enable                                                               */
71083   #define SPIM_INTENSET_STARTED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
71084   #define SPIM_INTENSET_STARTED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
71085 
71086 /* RXBUSERROR @Bit 29 : Write '1' to enable interrupt for event RXBUSERROR */
71087   #define SPIM_INTENSET_RXBUSERROR_Pos (29UL)        /*!< Position of RXBUSERROR field.                                        */
71088   #define SPIM_INTENSET_RXBUSERROR_Msk (0x1UL << SPIM_INTENSET_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.              */
71089   #define SPIM_INTENSET_RXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of RXBUSERROR field.                            */
71090   #define SPIM_INTENSET_RXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of RXBUSERROR field.                            */
71091   #define SPIM_INTENSET_RXBUSERROR_Set (0x1UL)       /*!< Enable                                                               */
71092   #define SPIM_INTENSET_RXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
71093   #define SPIM_INTENSET_RXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
71094 
71095 /* TXBUSERROR @Bit 30 : Write '1' to enable interrupt for event TXBUSERROR */
71096   #define SPIM_INTENSET_TXBUSERROR_Pos (30UL)        /*!< Position of TXBUSERROR field.                                        */
71097   #define SPIM_INTENSET_TXBUSERROR_Msk (0x1UL << SPIM_INTENSET_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.              */
71098   #define SPIM_INTENSET_TXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of TXBUSERROR field.                            */
71099   #define SPIM_INTENSET_TXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of TXBUSERROR field.                            */
71100   #define SPIM_INTENSET_TXBUSERROR_Set (0x1UL)       /*!< Enable                                                               */
71101   #define SPIM_INTENSET_TXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
71102   #define SPIM_INTENSET_TXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
71103 
71104 
71105 /* SPIM_INTENCLR: Disable interrupt */
71106   #define SPIM_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */
71107 
71108 /* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
71109   #define SPIM_INTENCLR_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
71110   #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
71111   #define SPIM_INTENCLR_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
71112   #define SPIM_INTENCLR_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
71113   #define SPIM_INTENCLR_STOPPED_Clear (0x1UL)        /*!< Disable                                                              */
71114   #define SPIM_INTENCLR_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
71115   #define SPIM_INTENCLR_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
71116 
71117 /* ENDRX @Bit 4 : Write '1' to disable interrupt for event ENDRX */
71118   #define SPIM_INTENCLR_ENDRX_Pos (4UL)              /*!< Position of ENDRX field.                                             */
71119   #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field.                             */
71120   #define SPIM_INTENCLR_ENDRX_Min (0x0UL)            /*!< Min enumerator value of ENDRX field.                                 */
71121   #define SPIM_INTENCLR_ENDRX_Max (0x1UL)            /*!< Max enumerator value of ENDRX field.                                 */
71122   #define SPIM_INTENCLR_ENDRX_Clear (0x1UL)          /*!< Disable                                                              */
71123   #define SPIM_INTENCLR_ENDRX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
71124   #define SPIM_INTENCLR_ENDRX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
71125 
71126 /* END @Bit 6 : Write '1' to disable interrupt for event END */
71127   #define SPIM_INTENCLR_END_Pos (6UL)                /*!< Position of END field.                                               */
71128   #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field.                                   */
71129   #define SPIM_INTENCLR_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
71130   #define SPIM_INTENCLR_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
71131   #define SPIM_INTENCLR_END_Clear (0x1UL)            /*!< Disable                                                              */
71132   #define SPIM_INTENCLR_END_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
71133   #define SPIM_INTENCLR_END_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
71134 
71135 /* ENDTX @Bit 8 : Write '1' to disable interrupt for event ENDTX */
71136   #define SPIM_INTENCLR_ENDTX_Pos (8UL)              /*!< Position of ENDTX field.                                             */
71137   #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field.                             */
71138   #define SPIM_INTENCLR_ENDTX_Min (0x0UL)            /*!< Min enumerator value of ENDTX field.                                 */
71139   #define SPIM_INTENCLR_ENDTX_Max (0x1UL)            /*!< Max enumerator value of ENDTX field.                                 */
71140   #define SPIM_INTENCLR_ENDTX_Clear (0x1UL)          /*!< Disable                                                              */
71141   #define SPIM_INTENCLR_ENDTX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
71142   #define SPIM_INTENCLR_ENDTX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
71143 
71144 /* STARTED @Bit 19 : Write '1' to disable interrupt for event STARTED */
71145   #define SPIM_INTENCLR_STARTED_Pos (19UL)           /*!< Position of STARTED field.                                           */
71146   #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field.                       */
71147   #define SPIM_INTENCLR_STARTED_Min (0x0UL)          /*!< Min enumerator value of STARTED field.                               */
71148   #define SPIM_INTENCLR_STARTED_Max (0x1UL)          /*!< Max enumerator value of STARTED field.                               */
71149   #define SPIM_INTENCLR_STARTED_Clear (0x1UL)        /*!< Disable                                                              */
71150   #define SPIM_INTENCLR_STARTED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
71151   #define SPIM_INTENCLR_STARTED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
71152 
71153 /* RXBUSERROR @Bit 29 : Write '1' to disable interrupt for event RXBUSERROR */
71154   #define SPIM_INTENCLR_RXBUSERROR_Pos (29UL)        /*!< Position of RXBUSERROR field.                                        */
71155   #define SPIM_INTENCLR_RXBUSERROR_Msk (0x1UL << SPIM_INTENCLR_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.              */
71156   #define SPIM_INTENCLR_RXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of RXBUSERROR field.                            */
71157   #define SPIM_INTENCLR_RXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of RXBUSERROR field.                            */
71158   #define SPIM_INTENCLR_RXBUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
71159   #define SPIM_INTENCLR_RXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
71160   #define SPIM_INTENCLR_RXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
71161 
71162 /* TXBUSERROR @Bit 30 : Write '1' to disable interrupt for event TXBUSERROR */
71163   #define SPIM_INTENCLR_TXBUSERROR_Pos (30UL)        /*!< Position of TXBUSERROR field.                                        */
71164   #define SPIM_INTENCLR_TXBUSERROR_Msk (0x1UL << SPIM_INTENCLR_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.              */
71165   #define SPIM_INTENCLR_TXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of TXBUSERROR field.                            */
71166   #define SPIM_INTENCLR_TXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of TXBUSERROR field.                            */
71167   #define SPIM_INTENCLR_TXBUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
71168   #define SPIM_INTENCLR_TXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
71169   #define SPIM_INTENCLR_TXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
71170 
71171 
71172 /* SPIM_STALLSTAT: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a
71173                     stall occurres and can be cleared (set to NOSTALL) by the CPU. */
71174 
71175   #define SPIM_STALLSTAT_ResetValue (0x00000000UL)   /*!< Reset value of STALLSTAT register.                                   */
71176 
71177 /* TX @Bit 0 : Stall status for EasyDMA RAM reads */
71178   #define SPIM_STALLSTAT_TX_Pos (0UL)                /*!< Position of TX field.                                                */
71179   #define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field.                                    */
71180   #define SPIM_STALLSTAT_TX_Min (0x0UL)              /*!< Min value of TX field.                                               */
71181   #define SPIM_STALLSTAT_TX_Max (0x1UL)              /*!< Max size of TX field.                                                */
71182   #define SPIM_STALLSTAT_TX_NOSTALL (0x0UL)          /*!< No stall                                                             */
71183   #define SPIM_STALLSTAT_TX_STALL (0x1UL)            /*!< A stall has occurred                                                 */
71184 
71185 /* RX @Bit 1 : Stall status for EasyDMA RAM writes */
71186   #define SPIM_STALLSTAT_RX_Pos (1UL)                /*!< Position of RX field.                                                */
71187   #define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field.                                    */
71188   #define SPIM_STALLSTAT_RX_Min (0x0UL)              /*!< Min value of RX field.                                               */
71189   #define SPIM_STALLSTAT_RX_Max (0x1UL)              /*!< Max size of RX field.                                                */
71190   #define SPIM_STALLSTAT_RX_NOSTALL (0x0UL)          /*!< No stall                                                             */
71191   #define SPIM_STALLSTAT_RX_STALL (0x1UL)            /*!< A stall has occurred                                                 */
71192 
71193 
71194 /* SPIM_ENABLE: Enable SPIM */
71195   #define SPIM_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */
71196 
71197 /* ENABLE @Bits 0..3 : Enable or disable SPIM */
71198   #define SPIM_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
71199   #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
71200   #define SPIM_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
71201   #define SPIM_ENABLE_ENABLE_Max (0x7UL)             /*!< Max enumerator value of ENABLE field.                                */
71202   #define SPIM_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable SPIM                                                         */
71203   #define SPIM_ENABLE_ENABLE_Enabled (0x7UL)         /*!< Enable SPIM                                                          */
71204 
71205 
71206 /* SPIM_FREQUENCY: SPI frequency. Accuracy depends on the HFCLK source selected. */
71207   #define SPIM_FREQUENCY_ResetValue (0x04000000UL)   /*!< Reset value of FREQUENCY register.                                   */
71208 
71209 /* FREQUENCY @Bits 0..31 : SPI master data rate */
71210   #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL)         /*!< Position of FREQUENCY field.                                         */
71211   #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field.        */
71212   #define SPIM_FREQUENCY_FREQUENCY_Min (0x2000000UL) /*!< Min enumerator value of FREQUENCY field.                             */
71213   #define SPIM_FREQUENCY_FREQUENCY_Max (0x80000000UL) /*!< Max enumerator value of FREQUENCY field.                            */
71214   #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps                                                           */
71215   #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps                                                           */
71216   #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps                                                           */
71217   #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps                                                               */
71218   #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps                                                               */
71219   #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps                                                               */
71220   #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps                                                               */
71221   #define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps                                                             */
71222   #define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps                                                             */
71223 
71224 
71225 /* SPIM_CONFIG: Configuration register */
71226   #define SPIM_CONFIG_ResetValue (0x00000000UL)      /*!< Reset value of CONFIG register.                                      */
71227 
71228 /* ORDER @Bit 0 : Bit order */
71229   #define SPIM_CONFIG_ORDER_Pos (0UL)                /*!< Position of ORDER field.                                             */
71230   #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field.                                 */
71231   #define SPIM_CONFIG_ORDER_Min (0x0UL)              /*!< Min enumerator value of ORDER field.                                 */
71232   #define SPIM_CONFIG_ORDER_Max (0x1UL)              /*!< Max enumerator value of ORDER field.                                 */
71233   #define SPIM_CONFIG_ORDER_MsbFirst (0x0UL)         /*!< Most significant bit shifted out first                               */
71234   #define SPIM_CONFIG_ORDER_LsbFirst (0x1UL)         /*!< Least significant bit shifted out first                              */
71235 
71236 /* CPHA @Bit 1 : Serial clock (SCK) phase */
71237   #define SPIM_CONFIG_CPHA_Pos (1UL)                 /*!< Position of CPHA field.                                              */
71238   #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field.                                    */
71239   #define SPIM_CONFIG_CPHA_Min (0x0UL)               /*!< Min enumerator value of CPHA field.                                  */
71240   #define SPIM_CONFIG_CPHA_Max (0x1UL)               /*!< Max enumerator value of CPHA field.                                  */
71241   #define SPIM_CONFIG_CPHA_Leading (0x0UL)           /*!< Sample on leading edge of clock, shift serial data on trailing edge  */
71242   #define SPIM_CONFIG_CPHA_Trailing (0x1UL)          /*!< Sample on trailing edge of clock, shift serial data on leading edge  */
71243 
71244 /* CPOL @Bit 2 : Serial clock (SCK) polarity */
71245   #define SPIM_CONFIG_CPOL_Pos (2UL)                 /*!< Position of CPOL field.                                              */
71246   #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field.                                    */
71247   #define SPIM_CONFIG_CPOL_Min (0x0UL)               /*!< Min enumerator value of CPOL field.                                  */
71248   #define SPIM_CONFIG_CPOL_Max (0x1UL)               /*!< Max enumerator value of CPOL field.                                  */
71249   #define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL)        /*!< Active high                                                          */
71250   #define SPIM_CONFIG_CPOL_ActiveLow (0x1UL)         /*!< Active low                                                           */
71251 
71252 
71253 /* SPIM_CSNPOL: Polarity of CSN output */
71254   #define SPIM_CSNPOL_ResetValue (0x00000000UL)      /*!< Reset value of CSNPOL register.                                      */
71255 
71256 /* CSNPOL @Bit 0 : Polarity of CSN output */
71257   #define SPIM_CSNPOL_CSNPOL_Pos (0UL)               /*!< Position of CSNPOL field.                                            */
71258   #define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field.                              */
71259   #define SPIM_CSNPOL_CSNPOL_Min (0x0UL)             /*!< Min enumerator value of CSNPOL field.                                */
71260   #define SPIM_CSNPOL_CSNPOL_Max (0x1UL)             /*!< Max enumerator value of CSNPOL field.                                */
71261   #define SPIM_CSNPOL_CSNPOL_LOW (0x0UL)             /*!< Active low (idle state high)                                         */
71262   #define SPIM_CSNPOL_CSNPOL_HIGH (0x1UL)            /*!< Active high (idle state low)                                         */
71263 
71264 
71265 /* SPIM_PSELDCX: Pin select for DCX signal */
71266   #define SPIM_PSELDCX_ResetValue (0xFFFFFFFFUL)     /*!< Reset value of PSELDCX register.                                     */
71267 
71268 /* PIN @Bits 0..4 : Pin number */
71269   #define SPIM_PSELDCX_PIN_Pos (0UL)                 /*!< Position of PIN field.                                               */
71270   #define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field.                                    */
71271   #define SPIM_PSELDCX_PIN_Min (0x0UL)               /*!< Min value of PIN field.                                              */
71272   #define SPIM_PSELDCX_PIN_Max (0x1FUL)              /*!< Max size of PIN field.                                               */
71273 
71274 /* PORT @Bits 5..8 : Port number */
71275   #define SPIM_PSELDCX_PORT_Pos (5UL)                /*!< Position of PORT field.                                              */
71276   #define SPIM_PSELDCX_PORT_Msk (0xFUL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field.                                  */
71277   #define SPIM_PSELDCX_PORT_Min (0x0UL)              /*!< Min value of PORT field.                                             */
71278   #define SPIM_PSELDCX_PORT_Max (0xFUL)              /*!< Max size of PORT field.                                              */
71279 
71280 /* CONNECT @Bit 31 : Connection */
71281   #define SPIM_PSELDCX_CONNECT_Pos (31UL)            /*!< Position of CONNECT field.                                           */
71282   #define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field.                         */
71283   #define SPIM_PSELDCX_CONNECT_Min (0x0UL)           /*!< Min enumerator value of CONNECT field.                               */
71284   #define SPIM_PSELDCX_CONNECT_Max (0x1UL)           /*!< Max enumerator value of CONNECT field.                               */
71285   #define SPIM_PSELDCX_CONNECT_Disconnected (0x1UL)  /*!< Disconnect                                                           */
71286   #define SPIM_PSELDCX_CONNECT_Connected (0x0UL)     /*!< Connect                                                              */
71287 
71288 
71289 /* SPIM_DCXCNT: DCX configuration */
71290   #define SPIM_DCXCNT_ResetValue (0x00000000UL)      /*!< Reset value of DCXCNT register.                                      */
71291 
71292 /* DCXCNT @Bits 0..3 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be
71293                        low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates
71294                        that all bytes are command bytes. */
71295 
71296   #define SPIM_DCXCNT_DCXCNT_Pos (0UL)               /*!< Position of DCXCNT field.                                            */
71297   #define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field.                              */
71298   #define SPIM_DCXCNT_DCXCNT_Min (0x0UL)             /*!< Min value of DCXCNT field.                                           */
71299   #define SPIM_DCXCNT_DCXCNT_Max (0xFUL)             /*!< Max size of DCXCNT field.                                            */
71300 
71301 
71302 /* SPIM_ORC: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than
71303               TXD.MAXCNT */
71304 
71305   #define SPIM_ORC_ResetValue (0x00000000UL)         /*!< Reset value of ORC register.                                         */
71306 
71307 /* ORC @Bits 0..7 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than
71308                     TXD.MAXCNT. */
71309 
71310   #define SPIM_ORC_ORC_Pos (0UL)                     /*!< Position of ORC field.                                               */
71311   #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field.                                            */
71312 
71313 
71314 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
71315 
71316 /* =========================================================================================================================== */
71317 /* ================                                           SPIS                                           ================ */
71318 /* =========================================================================================================================== */
71319 
71320 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
71321 
71322 /* ==================================================== Struct SPIS_PSEL ===================================================== */
71323 /**
71324   * @brief PSEL [SPIS_PSEL] (unspecified)
71325   */
71326 typedef struct {
71327   __IOM uint32_t  SCK;                               /*!< (@ 0x00000000) Pin select for SCK                                    */
71328   __IOM uint32_t  MISO;                              /*!< (@ 0x00000004) Pin select for MISO signal                            */
71329   __IOM uint32_t  MOSI;                              /*!< (@ 0x00000008) Pin select for MOSI signal                            */
71330   __IOM uint32_t  CSN;                               /*!< (@ 0x0000000C) Pin select for CSN signal                             */
71331 } NRF_SPIS_PSEL_Type;                                /*!< Size = 16 (0x010)                                                    */
71332 
71333 /* SPIS_PSEL_SCK: Pin select for SCK */
71334   #define SPIS_PSEL_SCK_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SCK register.                                         */
71335 
71336 /* PIN @Bits 0..4 : Pin number */
71337   #define SPIS_PSEL_SCK_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
71338   #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field.                                  */
71339   #define SPIS_PSEL_SCK_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
71340   #define SPIS_PSEL_SCK_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
71341 
71342 /* PORT @Bits 5..8 : Port number */
71343   #define SPIS_PSEL_SCK_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
71344   #define SPIS_PSEL_SCK_PORT_Msk (0xFUL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field.                                */
71345   #define SPIS_PSEL_SCK_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
71346   #define SPIS_PSEL_SCK_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
71347 
71348 /* CONNECT @Bit 31 : Connection */
71349   #define SPIS_PSEL_SCK_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
71350   #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
71351   #define SPIS_PSEL_SCK_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
71352   #define SPIS_PSEL_SCK_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
71353   #define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
71354   #define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
71355 
71356 
71357 /* SPIS_PSEL_MISO: Pin select for MISO signal */
71358   #define SPIS_PSEL_MISO_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MISO register.                                        */
71359 
71360 /* PIN @Bits 0..4 : Pin number */
71361   #define SPIS_PSEL_MISO_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
71362   #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field.                                */
71363   #define SPIS_PSEL_MISO_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
71364   #define SPIS_PSEL_MISO_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
71365 
71366 /* PORT @Bits 5..8 : Port number */
71367   #define SPIS_PSEL_MISO_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
71368   #define SPIS_PSEL_MISO_PORT_Msk (0xFUL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field.                              */
71369   #define SPIS_PSEL_MISO_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
71370   #define SPIS_PSEL_MISO_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
71371 
71372 /* CONNECT @Bit 31 : Connection */
71373   #define SPIS_PSEL_MISO_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
71374   #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
71375   #define SPIS_PSEL_MISO_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
71376   #define SPIS_PSEL_MISO_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
71377   #define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
71378   #define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
71379 
71380 
71381 /* SPIS_PSEL_MOSI: Pin select for MOSI signal */
71382   #define SPIS_PSEL_MOSI_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of MOSI register.                                        */
71383 
71384 /* PIN @Bits 0..4 : Pin number */
71385   #define SPIS_PSEL_MOSI_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
71386   #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field.                                */
71387   #define SPIS_PSEL_MOSI_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
71388   #define SPIS_PSEL_MOSI_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
71389 
71390 /* PORT @Bits 5..8 : Port number */
71391   #define SPIS_PSEL_MOSI_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
71392   #define SPIS_PSEL_MOSI_PORT_Msk (0xFUL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field.                              */
71393   #define SPIS_PSEL_MOSI_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
71394   #define SPIS_PSEL_MOSI_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
71395 
71396 /* CONNECT @Bit 31 : Connection */
71397   #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
71398   #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
71399   #define SPIS_PSEL_MOSI_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
71400   #define SPIS_PSEL_MOSI_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
71401   #define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
71402   #define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
71403 
71404 
71405 /* SPIS_PSEL_CSN: Pin select for CSN signal */
71406   #define SPIS_PSEL_CSN_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of CSN register.                                         */
71407 
71408 /* PIN @Bits 0..4 : Pin number */
71409   #define SPIS_PSEL_CSN_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
71410   #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field.                                  */
71411   #define SPIS_PSEL_CSN_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
71412   #define SPIS_PSEL_CSN_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
71413 
71414 /* PORT @Bits 5..8 : Port number */
71415   #define SPIS_PSEL_CSN_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
71416   #define SPIS_PSEL_CSN_PORT_Msk (0xFUL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field.                                */
71417   #define SPIS_PSEL_CSN_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
71418   #define SPIS_PSEL_CSN_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
71419 
71420 /* CONNECT @Bit 31 : Connection */
71421   #define SPIS_PSEL_CSN_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
71422   #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
71423   #define SPIS_PSEL_CSN_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
71424   #define SPIS_PSEL_CSN_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
71425   #define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
71426   #define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
71427 
71428 
71429 
71430 /* ===================================================== Struct SPIS_RXD ===================================================== */
71431 /**
71432   * @brief RXD [SPIS_RXD] (unspecified)
71433   */
71434 typedef struct {
71435   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) RXD data pointer                                      */
71436   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in receive buffer             */
71437   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes received in last granted transaction  */
71438   __IOM uint32_t  LIST;                              /*!< (@ 0x0000000C) EasyDMA list type                                     */
71439 } NRF_SPIS_RXD_Type;                                 /*!< Size = 16 (0x010)                                                    */
71440 
71441 /* SPIS_RXD_PTR: RXD data pointer */
71442   #define SPIS_RXD_PTR_ResetValue (0x00000000UL)     /*!< Reset value of PTR register.                                         */
71443 
71444 /* PTR @Bits 0..31 : RXD data pointer */
71445   #define SPIS_RXD_PTR_PTR_Pos (0UL)                 /*!< Position of PTR field.                                               */
71446   #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                              */
71447 
71448 
71449 /* SPIS_RXD_MAXCNT: Maximum number of bytes in receive buffer */
71450   #define SPIS_RXD_MAXCNT_ResetValue (0x00000000UL)  /*!< Reset value of MAXCNT register.                                      */
71451 
71452 /* MAXCNT @Bits 0..14 : Maximum number of bytes in receive buffer */
71453   #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL)           /*!< Position of MAXCNT field.                                            */
71454   #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                   */
71455   #define SPIS_RXD_MAXCNT_MAXCNT_Min (0x1UL)         /*!< Min value of MAXCNT field.                                           */
71456   #define SPIS_RXD_MAXCNT_MAXCNT_Max (0x7FFFUL)      /*!< Max size of MAXCNT field.                                            */
71457 
71458 
71459 /* SPIS_RXD_AMOUNT: Number of bytes received in last granted transaction */
71460   #define SPIS_RXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
71461 
71462 /* AMOUNT @Bits 0..14 : Number of bytes received in the last granted transaction */
71463   #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL)           /*!< Position of AMOUNT field.                                            */
71464   #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
71465   #define SPIS_RXD_AMOUNT_AMOUNT_Min (0x1UL)         /*!< Min value of AMOUNT field.                                           */
71466   #define SPIS_RXD_AMOUNT_AMOUNT_Max (0x7FFFUL)      /*!< Max size of AMOUNT field.                                            */
71467 
71468 
71469 /* SPIS_RXD_LIST: EasyDMA list type */
71470   #define SPIS_RXD_LIST_ResetValue (0x00000000UL)    /*!< Reset value of LIST register.                                        */
71471 
71472 /* LIST @Bits 0..1 : List type */
71473   #define SPIS_RXD_LIST_LIST_Pos (0UL)               /*!< Position of LIST field.                                              */
71474   #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field.                                */
71475   #define SPIS_RXD_LIST_LIST_Min (0x0UL)             /*!< Min enumerator value of LIST field.                                  */
71476   #define SPIS_RXD_LIST_LIST_Max (0x1UL)             /*!< Max enumerator value of LIST field.                                  */
71477   #define SPIS_RXD_LIST_LIST_Disabled (0x0UL)        /*!< Disable EasyDMA list                                                 */
71478   #define SPIS_RXD_LIST_LIST_ArrayList (0x1UL)       /*!< Use array list                                                       */
71479 
71480 
71481 
71482 /* ===================================================== Struct SPIS_TXD ===================================================== */
71483 /**
71484   * @brief TXD [SPIS_TXD] (unspecified)
71485   */
71486 typedef struct {
71487   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) TXD data pointer                                      */
71488   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer            */
71489   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transmitted in last granted
71490                                                                          transaction*/
71491   __IOM uint32_t  LIST;                              /*!< (@ 0x0000000C) EasyDMA list type                                     */
71492 } NRF_SPIS_TXD_Type;                                 /*!< Size = 16 (0x010)                                                    */
71493 
71494 /* SPIS_TXD_PTR: TXD data pointer */
71495   #define SPIS_TXD_PTR_ResetValue (0x00000000UL)     /*!< Reset value of PTR register.                                         */
71496 
71497 /* PTR @Bits 0..31 : TXD data pointer */
71498   #define SPIS_TXD_PTR_PTR_Pos (0UL)                 /*!< Position of PTR field.                                               */
71499   #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                              */
71500 
71501 
71502 /* SPIS_TXD_MAXCNT: Maximum number of bytes in transmit buffer */
71503   #define SPIS_TXD_MAXCNT_ResetValue (0x00000000UL)  /*!< Reset value of MAXCNT register.                                      */
71504 
71505 /* MAXCNT @Bits 0..14 : Maximum number of bytes in transmit buffer */
71506   #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL)           /*!< Position of MAXCNT field.                                            */
71507   #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                   */
71508   #define SPIS_TXD_MAXCNT_MAXCNT_Min (0x1UL)         /*!< Min value of MAXCNT field.                                           */
71509   #define SPIS_TXD_MAXCNT_MAXCNT_Max (0x7FFFUL)      /*!< Max size of MAXCNT field.                                            */
71510 
71511 
71512 /* SPIS_TXD_AMOUNT: Number of bytes transmitted in last granted transaction */
71513   #define SPIS_TXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
71514 
71515 /* AMOUNT @Bits 0..14 : Number of bytes transmitted in last granted transaction */
71516   #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL)           /*!< Position of AMOUNT field.                                            */
71517   #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
71518   #define SPIS_TXD_AMOUNT_AMOUNT_Min (0x1UL)         /*!< Min value of AMOUNT field.                                           */
71519   #define SPIS_TXD_AMOUNT_AMOUNT_Max (0x7FFFUL)      /*!< Max size of AMOUNT field.                                            */
71520 
71521 
71522 /* SPIS_TXD_LIST: EasyDMA list type */
71523   #define SPIS_TXD_LIST_ResetValue (0x00000000UL)    /*!< Reset value of LIST register.                                        */
71524 
71525 /* LIST @Bits 0..1 : List type */
71526   #define SPIS_TXD_LIST_LIST_Pos (0UL)               /*!< Position of LIST field.                                              */
71527   #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field.                                */
71528   #define SPIS_TXD_LIST_LIST_Min (0x0UL)             /*!< Min enumerator value of LIST field.                                  */
71529   #define SPIS_TXD_LIST_LIST_Max (0x1UL)             /*!< Max enumerator value of LIST field.                                  */
71530   #define SPIS_TXD_LIST_LIST_Disabled (0x0UL)        /*!< Disable EasyDMA list                                                 */
71531   #define SPIS_TXD_LIST_LIST_ArrayList (0x1UL)       /*!< Use array list                                                       */
71532 
71533 
71534 
71535 /* =================================================== Struct SPIS_DMA_RX ==================================================== */
71536 /**
71537   * @brief RX [SPIS_DMA_RX] (unspecified)
71538   */
71539 typedef struct {
71540   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
71541                                                                          detected.*/
71542   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
71543                                                                          event.*/
71544 } NRF_SPIS_DMA_RX_Type;                              /*!< Size = 8 (0x008)                                                     */
71545 
71546 /* SPIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
71547   #define SPIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */
71548 
71549 /* ENABLE @Bit 0 : (unspecified) */
71550   #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
71551   #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
71552                                                                             ENABLE field.*/
71553   #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
71554   #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
71555   #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
71556   #define SPIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */
71557 
71558 
71559 /* SPIS_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
71560   #define SPIS_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */
71561 
71562 /* ADDRESS @Bits 0..31 : (unspecified) */
71563   #define SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
71564   #define SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
71565                                                                             ADDRESS field.*/
71566 
71567 
71568 
71569 /* =================================================== Struct SPIS_DMA_TX ==================================================== */
71570 /**
71571   * @brief TX [SPIS_DMA_TX] (unspecified)
71572   */
71573 typedef struct {
71574   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
71575                                                                          detected.*/
71576   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
71577                                                                          event.*/
71578 } NRF_SPIS_DMA_TX_Type;                              /*!< Size = 8 (0x008)                                                     */
71579 
71580 /* SPIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
71581   #define SPIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */
71582 
71583 /* ENABLE @Bit 0 : (unspecified) */
71584   #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
71585   #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
71586                                                                             ENABLE field.*/
71587   #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
71588   #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
71589   #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
71590   #define SPIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */
71591 
71592 
71593 /* SPIS_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
71594   #define SPIS_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */
71595 
71596 /* ADDRESS @Bits 0..31 : (unspecified) */
71597   #define SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
71598   #define SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << SPIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
71599                                                                             ADDRESS field.*/
71600 
71601 
71602 
71603 /* ===================================================== Struct SPIS_DMA ===================================================== */
71604 /**
71605   * @brief DMA [SPIS_DMA] (unspecified)
71606   */
71607 typedef struct {
71608   __IOM NRF_SPIS_DMA_RX_Type RX;                     /*!< (@ 0x00000000) (unspecified)                                         */
71609   __IOM NRF_SPIS_DMA_TX_Type TX;                     /*!< (@ 0x00000008) (unspecified)                                         */
71610 } NRF_SPIS_DMA_Type;                                 /*!< Size = 16 (0x010)                                                    */
71611 
71612 /* ======================================================= Struct SPIS ======================================================= */
71613 /**
71614   * @brief SPI Slave
71615   */
71616   typedef struct {                                   /*!< SPIS Structure                                                       */
71617     __IM uint32_t RESERVED[9];
71618     __OM uint32_t TASKS_ACQUIRE;                     /*!< (@ 0x00000024) Acquire SPI semaphore                                 */
71619     __OM uint32_t TASKS_RELEASE;                     /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave to
71620                                                                          acquire it*/
71621     __IM uint32_t RESERVED1[30];
71622     __IOM uint32_t SUBSCRIBE_ACQUIRE;                /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE              */
71623     __IOM uint32_t SUBSCRIBE_RELEASE;                /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE              */
71624     __IM uint32_t RESERVED2[22];
71625     __IOM uint32_t EVENTS_END;                       /*!< (@ 0x00000104) Granted transaction completed                         */
71626     __IM uint32_t RESERVED3[2];
71627     __IOM uint32_t EVENTS_ENDRX;                     /*!< (@ 0x00000110) End of RXD buffer reached                             */
71628     __IM uint32_t RESERVED4[5];
71629     __IOM uint32_t EVENTS_ACQUIRED;                  /*!< (@ 0x00000128) Semaphore acquired                                    */
71630     __IM uint32_t RESERVED5[18];
71631     __IOM uint32_t EVENTS_RXBUSERROR;                /*!< (@ 0x00000174) This event is generated if an error occurs during the
71632                                                                          bus transfer.*/
71633     __IOM uint32_t EVENTS_TXBUSERROR;                /*!< (@ 0x00000178) This event is generated if an error occurs during the
71634                                                                          bus transfer.*/
71635     __IM uint32_t RESERVED6[2];
71636     __IOM uint32_t PUBLISH_END;                      /*!< (@ 0x00000184) Publish configuration for event END                   */
71637     __IM uint32_t RESERVED7[2];
71638     __IOM uint32_t PUBLISH_ENDRX;                    /*!< (@ 0x00000190) Publish configuration for event ENDRX                 */
71639     __IM uint32_t RESERVED8[5];
71640     __IOM uint32_t PUBLISH_ACQUIRED;                 /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED              */
71641     __IM uint32_t RESERVED9[18];
71642     __IOM uint32_t PUBLISH_RXBUSERROR;               /*!< (@ 0x000001F4) Publish configuration for event RXBUSERROR            */
71643     __IOM uint32_t PUBLISH_TXBUSERROR;               /*!< (@ 0x000001F8) Publish configuration for event TXBUSERROR            */
71644     __IM uint32_t RESERVED10;
71645     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
71646     __IM uint32_t RESERVED11[64];
71647     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
71648     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
71649     __IM uint32_t RESERVED12[61];
71650     __IM uint32_t SEMSTAT;                           /*!< (@ 0x00000400) Semaphore status register                             */
71651     __IM uint32_t RESERVED13[15];
71652     __IOM uint32_t STATUS;                           /*!< (@ 0x00000440) Status from last transaction                          */
71653     __IM uint32_t RESERVED14[47];
71654     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable SPI slave                                      */
71655     __IM uint32_t RESERVED15;
71656     __IOM NRF_SPIS_PSEL_Type PSEL;                   /*!< (@ 0x00000508) (unspecified)                                         */
71657     __IM uint32_t RESERVED16[7];
71658     __IOM NRF_SPIS_RXD_Type RXD;                     /*!< (@ 0x00000534) (unspecified)                                         */
71659     __IOM NRF_SPIS_TXD_Type TXD;                     /*!< (@ 0x00000544) (unspecified)                                         */
71660     __IOM uint32_t CONFIG;                           /*!< (@ 0x00000554) Configuration register                                */
71661     __IM uint32_t RESERVED17;
71662     __IOM uint32_t DEF;                              /*!< (@ 0x0000055C) Default character. Character clocked out in case of an
71663                                                                          ignored transaction.*/
71664     __IM uint32_t RESERVED18[20];
71665     __IOM NRF_SPIS_DMA_Type DMA;                     /*!< (@ 0x000005B0) (unspecified)                                         */
71666     __IOM uint32_t ORC;                              /*!< (@ 0x000005C0) Over-read character                                   */
71667   } NRF_SPIS_Type;                                   /*!< Size = 1476 (0x5C4)                                                  */
71668 
71669 /* SPIS_TASKS_ACQUIRE: Acquire SPI semaphore */
71670   #define SPIS_TASKS_ACQUIRE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_ACQUIRE register.                             */
71671 
71672 /* TASKS_ACQUIRE @Bit 0 : Acquire SPI semaphore */
71673   #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field.                                     */
71674   #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE
71675                                                                             field.*/
71676   #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Min (0x1UL) /*!< Min enumerator value of TASKS_ACQUIRE field.                       */
71677   #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Max (0x1UL) /*!< Max enumerator value of TASKS_ACQUIRE field.                       */
71678   #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task                                                   */
71679 
71680 
71681 /* SPIS_TASKS_RELEASE: Release SPI semaphore, enabling the SPI slave to acquire it */
71682   #define SPIS_TASKS_RELEASE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RELEASE register.                             */
71683 
71684 /* TASKS_RELEASE @Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
71685   #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field.                                     */
71686   #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE
71687                                                                             field.*/
71688   #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Min (0x1UL) /*!< Min enumerator value of TASKS_RELEASE field.                       */
71689   #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Max (0x1UL) /*!< Max enumerator value of TASKS_RELEASE field.                       */
71690   #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task                                                   */
71691 
71692 
71693 /* SPIS_SUBSCRIBE_ACQUIRE: Subscribe configuration for task ACQUIRE */
71694   #define SPIS_SUBSCRIBE_ACQUIRE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_ACQUIRE register.                     */
71695 
71696 /* CHIDX @Bits 0..7 : DPPI channel that task ACQUIRE will subscribe to */
71697   #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
71698   #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
71699   #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
71700   #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
71701 
71702 /* EN @Bit 31 : (unspecified) */
71703   #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
71704   #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field.                    */
71705   #define SPIS_SUBSCRIBE_ACQUIRE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
71706   #define SPIS_SUBSCRIBE_ACQUIRE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
71707   #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
71708   #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
71709 
71710 
71711 /* SPIS_SUBSCRIBE_RELEASE: Subscribe configuration for task RELEASE */
71712   #define SPIS_SUBSCRIBE_RELEASE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RELEASE register.                     */
71713 
71714 /* CHIDX @Bits 0..7 : DPPI channel that task RELEASE will subscribe to */
71715   #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
71716   #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
71717   #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
71718   #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
71719 
71720 /* EN @Bit 31 : (unspecified) */
71721   #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL)       /*!< Position of EN field.                                                */
71722   #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field.                    */
71723   #define SPIS_SUBSCRIBE_RELEASE_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
71724   #define SPIS_SUBSCRIBE_RELEASE_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
71725   #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
71726   #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
71727 
71728 
71729 /* SPIS_EVENTS_END: Granted transaction completed */
71730   #define SPIS_EVENTS_END_ResetValue (0x00000000UL)  /*!< Reset value of EVENTS_END register.                                  */
71731 
71732 /* EVENTS_END @Bit 0 : Granted transaction completed */
71733   #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL)       /*!< Position of EVENTS_END field.                                        */
71734   #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field.          */
71735   #define SPIS_EVENTS_END_EVENTS_END_Min (0x0UL)     /*!< Min enumerator value of EVENTS_END field.                            */
71736   #define SPIS_EVENTS_END_EVENTS_END_Max (0x1UL)     /*!< Max enumerator value of EVENTS_END field.                            */
71737   #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated                                             */
71738   #define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated                                                    */
71739 
71740 
71741 /* SPIS_EVENTS_ENDRX: End of RXD buffer reached */
71742   #define SPIS_EVENTS_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDRX register.                               */
71743 
71744 /* EVENTS_ENDRX @Bit 0 : End of RXD buffer reached */
71745   #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)   /*!< Position of EVENTS_ENDRX field.                                      */
71746   #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field.*/
71747   #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDRX field.                          */
71748   #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDRX field.                          */
71749   #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated                                         */
71750   #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated                                                */
71751 
71752 
71753 /* SPIS_EVENTS_ACQUIRED: Semaphore acquired */
71754   #define SPIS_EVENTS_ACQUIRED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ACQUIRED register.                         */
71755 
71756 /* EVENTS_ACQUIRED @Bit 0 : Semaphore acquired */
71757   #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field.                               */
71758   #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of
71759                                                                             EVENTS_ACQUIRED field.*/
71760   #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Min (0x0UL) /*!< Min enumerator value of EVENTS_ACQUIRED field.                 */
71761   #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Max (0x1UL) /*!< Max enumerator value of EVENTS_ACQUIRED field.                 */
71762   #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated                                   */
71763   #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated                                          */
71764 
71765 
71766 /* SPIS_EVENTS_RXBUSERROR: This event is generated if an error occurs during the bus transfer. */
71767   #define SPIS_EVENTS_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXBUSERROR register.                     */
71768 
71769 /* EVENTS_RXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
71770   #define SPIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos (0UL) /*!< Position of EVENTS_RXBUSERROR field.                         */
71771   #define SPIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Msk (0x1UL << SPIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos) /*!< Bit mask of
71772                                                                             EVENTS_RXBUSERROR field.*/
71773   #define SPIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXBUSERROR field.           */
71774   #define SPIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXBUSERROR field.           */
71775   #define SPIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                               */
71776   #define SPIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Generated (0x1UL) /*!< Event generated                                      */
71777 
71778 
71779 /* SPIS_EVENTS_TXBUSERROR: This event is generated if an error occurs during the bus transfer. */
71780   #define SPIS_EVENTS_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXBUSERROR register.                     */
71781 
71782 /* EVENTS_TXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
71783   #define SPIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos (0UL) /*!< Position of EVENTS_TXBUSERROR field.                         */
71784   #define SPIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Msk (0x1UL << SPIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos) /*!< Bit mask of
71785                                                                             EVENTS_TXBUSERROR field.*/
71786   #define SPIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXBUSERROR field.           */
71787   #define SPIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXBUSERROR field.           */
71788   #define SPIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                               */
71789   #define SPIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Generated (0x1UL) /*!< Event generated                                      */
71790 
71791 
71792 /* SPIS_PUBLISH_END: Publish configuration for event END */
71793   #define SPIS_PUBLISH_END_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_END register.                                 */
71794 
71795 /* CHIDX @Bits 0..7 : DPPI channel that event END will publish to */
71796   #define SPIS_PUBLISH_END_CHIDX_Pos (0UL)           /*!< Position of CHIDX field.                                             */
71797   #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field.                      */
71798   #define SPIS_PUBLISH_END_CHIDX_Min (0x0UL)         /*!< Min value of CHIDX field.                                            */
71799   #define SPIS_PUBLISH_END_CHIDX_Max (0xFFUL)        /*!< Max size of CHIDX field.                                             */
71800 
71801 /* EN @Bit 31 : (unspecified) */
71802   #define SPIS_PUBLISH_END_EN_Pos (31UL)             /*!< Position of EN field.                                                */
71803   #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field.                                */
71804   #define SPIS_PUBLISH_END_EN_Min (0x0UL)            /*!< Min enumerator value of EN field.                                    */
71805   #define SPIS_PUBLISH_END_EN_Max (0x1UL)            /*!< Max enumerator value of EN field.                                    */
71806   #define SPIS_PUBLISH_END_EN_Disabled (0x0UL)       /*!< Disable publishing                                                   */
71807   #define SPIS_PUBLISH_END_EN_Enabled (0x1UL)        /*!< Enable publishing                                                    */
71808 
71809 
71810 /* SPIS_PUBLISH_ENDRX: Publish configuration for event ENDRX */
71811   #define SPIS_PUBLISH_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDRX register.                             */
71812 
71813 /* CHIDX @Bits 0..7 : DPPI channel that event ENDRX will publish to */
71814   #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
71815   #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
71816   #define SPIS_PUBLISH_ENDRX_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
71817   #define SPIS_PUBLISH_ENDRX_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
71818 
71819 /* EN @Bit 31 : (unspecified) */
71820   #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL)           /*!< Position of EN field.                                                */
71821   #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field.                            */
71822   #define SPIS_PUBLISH_ENDRX_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
71823   #define SPIS_PUBLISH_ENDRX_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
71824   #define SPIS_PUBLISH_ENDRX_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
71825   #define SPIS_PUBLISH_ENDRX_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
71826 
71827 
71828 /* SPIS_PUBLISH_ACQUIRED: Publish configuration for event ACQUIRED */
71829   #define SPIS_PUBLISH_ACQUIRED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ACQUIRED register.                       */
71830 
71831 /* CHIDX @Bits 0..7 : DPPI channel that event ACQUIRED will publish to */
71832   #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
71833   #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
71834   #define SPIS_PUBLISH_ACQUIRED_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
71835   #define SPIS_PUBLISH_ACQUIRED_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
71836 
71837 /* EN @Bit 31 : (unspecified) */
71838   #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
71839   #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field.                      */
71840   #define SPIS_PUBLISH_ACQUIRED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
71841   #define SPIS_PUBLISH_ACQUIRED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
71842   #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
71843   #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
71844 
71845 
71846 /* SPIS_PUBLISH_RXBUSERROR: Publish configuration for event RXBUSERROR */
71847   #define SPIS_PUBLISH_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXBUSERROR register.                   */
71848 
71849 /* CHIDX @Bits 0..7 : DPPI channel that event RXBUSERROR will publish to */
71850   #define SPIS_PUBLISH_RXBUSERROR_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
71851   #define SPIS_PUBLISH_RXBUSERROR_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_RXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
71852   #define SPIS_PUBLISH_RXBUSERROR_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
71853   #define SPIS_PUBLISH_RXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
71854 
71855 /* EN @Bit 31 : (unspecified) */
71856   #define SPIS_PUBLISH_RXBUSERROR_EN_Pos (31UL)      /*!< Position of EN field.                                                */
71857   #define SPIS_PUBLISH_RXBUSERROR_EN_Msk (0x1UL << SPIS_PUBLISH_RXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                  */
71858   #define SPIS_PUBLISH_RXBUSERROR_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
71859   #define SPIS_PUBLISH_RXBUSERROR_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
71860   #define SPIS_PUBLISH_RXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
71861   #define SPIS_PUBLISH_RXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
71862 
71863 
71864 /* SPIS_PUBLISH_TXBUSERROR: Publish configuration for event TXBUSERROR */
71865   #define SPIS_PUBLISH_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXBUSERROR register.                   */
71866 
71867 /* CHIDX @Bits 0..7 : DPPI channel that event TXBUSERROR will publish to */
71868   #define SPIS_PUBLISH_TXBUSERROR_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
71869   #define SPIS_PUBLISH_TXBUSERROR_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_TXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
71870   #define SPIS_PUBLISH_TXBUSERROR_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
71871   #define SPIS_PUBLISH_TXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
71872 
71873 /* EN @Bit 31 : (unspecified) */
71874   #define SPIS_PUBLISH_TXBUSERROR_EN_Pos (31UL)      /*!< Position of EN field.                                                */
71875   #define SPIS_PUBLISH_TXBUSERROR_EN_Msk (0x1UL << SPIS_PUBLISH_TXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                  */
71876   #define SPIS_PUBLISH_TXBUSERROR_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
71877   #define SPIS_PUBLISH_TXBUSERROR_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
71878   #define SPIS_PUBLISH_TXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
71879   #define SPIS_PUBLISH_TXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
71880 
71881 
71882 /* SPIS_SHORTS: Shortcuts between local events and tasks */
71883   #define SPIS_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */
71884 
71885 /* END_ACQUIRE @Bit 2 : Shortcut between event END and task ACQUIRE */
71886   #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL)          /*!< Position of END_ACQUIRE field.                                       */
71887   #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field.               */
71888   #define SPIS_SHORTS_END_ACQUIRE_Min (0x0UL)        /*!< Min enumerator value of END_ACQUIRE field.                           */
71889   #define SPIS_SHORTS_END_ACQUIRE_Max (0x1UL)        /*!< Max enumerator value of END_ACQUIRE field.                           */
71890   #define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
71891   #define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL)    /*!< Enable shortcut                                                      */
71892 
71893 
71894 /* SPIS_INTENSET: Enable interrupt */
71895   #define SPIS_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */
71896 
71897 /* END @Bit 1 : Write '1' to enable interrupt for event END */
71898   #define SPIS_INTENSET_END_Pos (1UL)                /*!< Position of END field.                                               */
71899   #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field.                                   */
71900   #define SPIS_INTENSET_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
71901   #define SPIS_INTENSET_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
71902   #define SPIS_INTENSET_END_Set (0x1UL)              /*!< Enable                                                               */
71903   #define SPIS_INTENSET_END_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
71904   #define SPIS_INTENSET_END_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
71905 
71906 /* ENDRX @Bit 4 : Write '1' to enable interrupt for event ENDRX */
71907   #define SPIS_INTENSET_ENDRX_Pos (4UL)              /*!< Position of ENDRX field.                                             */
71908   #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field.                             */
71909   #define SPIS_INTENSET_ENDRX_Min (0x0UL)            /*!< Min enumerator value of ENDRX field.                                 */
71910   #define SPIS_INTENSET_ENDRX_Max (0x1UL)            /*!< Max enumerator value of ENDRX field.                                 */
71911   #define SPIS_INTENSET_ENDRX_Set (0x1UL)            /*!< Enable                                                               */
71912   #define SPIS_INTENSET_ENDRX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
71913   #define SPIS_INTENSET_ENDRX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
71914 
71915 /* ACQUIRED @Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
71916   #define SPIS_INTENSET_ACQUIRED_Pos (10UL)          /*!< Position of ACQUIRED field.                                          */
71917   #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field.                    */
71918   #define SPIS_INTENSET_ACQUIRED_Min (0x0UL)         /*!< Min enumerator value of ACQUIRED field.                              */
71919   #define SPIS_INTENSET_ACQUIRED_Max (0x1UL)         /*!< Max enumerator value of ACQUIRED field.                              */
71920   #define SPIS_INTENSET_ACQUIRED_Set (0x1UL)         /*!< Enable                                                               */
71921   #define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
71922   #define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
71923 
71924 /* RXBUSERROR @Bit 29 : Write '1' to enable interrupt for event RXBUSERROR */
71925   #define SPIS_INTENSET_RXBUSERROR_Pos (29UL)        /*!< Position of RXBUSERROR field.                                        */
71926   #define SPIS_INTENSET_RXBUSERROR_Msk (0x1UL << SPIS_INTENSET_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.              */
71927   #define SPIS_INTENSET_RXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of RXBUSERROR field.                            */
71928   #define SPIS_INTENSET_RXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of RXBUSERROR field.                            */
71929   #define SPIS_INTENSET_RXBUSERROR_Set (0x1UL)       /*!< Enable                                                               */
71930   #define SPIS_INTENSET_RXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
71931   #define SPIS_INTENSET_RXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
71932 
71933 /* TXBUSERROR @Bit 30 : Write '1' to enable interrupt for event TXBUSERROR */
71934   #define SPIS_INTENSET_TXBUSERROR_Pos (30UL)        /*!< Position of TXBUSERROR field.                                        */
71935   #define SPIS_INTENSET_TXBUSERROR_Msk (0x1UL << SPIS_INTENSET_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.              */
71936   #define SPIS_INTENSET_TXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of TXBUSERROR field.                            */
71937   #define SPIS_INTENSET_TXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of TXBUSERROR field.                            */
71938   #define SPIS_INTENSET_TXBUSERROR_Set (0x1UL)       /*!< Enable                                                               */
71939   #define SPIS_INTENSET_TXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
71940   #define SPIS_INTENSET_TXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
71941 
71942 
71943 /* SPIS_INTENCLR: Disable interrupt */
71944   #define SPIS_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */
71945 
71946 /* END @Bit 1 : Write '1' to disable interrupt for event END */
71947   #define SPIS_INTENCLR_END_Pos (1UL)                /*!< Position of END field.                                               */
71948   #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field.                                   */
71949   #define SPIS_INTENCLR_END_Min (0x0UL)              /*!< Min enumerator value of END field.                                   */
71950   #define SPIS_INTENCLR_END_Max (0x1UL)              /*!< Max enumerator value of END field.                                   */
71951   #define SPIS_INTENCLR_END_Clear (0x1UL)            /*!< Disable                                                              */
71952   #define SPIS_INTENCLR_END_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
71953   #define SPIS_INTENCLR_END_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
71954 
71955 /* ENDRX @Bit 4 : Write '1' to disable interrupt for event ENDRX */
71956   #define SPIS_INTENCLR_ENDRX_Pos (4UL)              /*!< Position of ENDRX field.                                             */
71957   #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field.                             */
71958   #define SPIS_INTENCLR_ENDRX_Min (0x0UL)            /*!< Min enumerator value of ENDRX field.                                 */
71959   #define SPIS_INTENCLR_ENDRX_Max (0x1UL)            /*!< Max enumerator value of ENDRX field.                                 */
71960   #define SPIS_INTENCLR_ENDRX_Clear (0x1UL)          /*!< Disable                                                              */
71961   #define SPIS_INTENCLR_ENDRX_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
71962   #define SPIS_INTENCLR_ENDRX_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
71963 
71964 /* ACQUIRED @Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
71965   #define SPIS_INTENCLR_ACQUIRED_Pos (10UL)          /*!< Position of ACQUIRED field.                                          */
71966   #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field.                    */
71967   #define SPIS_INTENCLR_ACQUIRED_Min (0x0UL)         /*!< Min enumerator value of ACQUIRED field.                              */
71968   #define SPIS_INTENCLR_ACQUIRED_Max (0x1UL)         /*!< Max enumerator value of ACQUIRED field.                              */
71969   #define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL)       /*!< Disable                                                              */
71970   #define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL)    /*!< Read: Disabled                                                       */
71971   #define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL)     /*!< Read: Enabled                                                        */
71972 
71973 /* RXBUSERROR @Bit 29 : Write '1' to disable interrupt for event RXBUSERROR */
71974   #define SPIS_INTENCLR_RXBUSERROR_Pos (29UL)        /*!< Position of RXBUSERROR field.                                        */
71975   #define SPIS_INTENCLR_RXBUSERROR_Msk (0x1UL << SPIS_INTENCLR_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.              */
71976   #define SPIS_INTENCLR_RXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of RXBUSERROR field.                            */
71977   #define SPIS_INTENCLR_RXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of RXBUSERROR field.                            */
71978   #define SPIS_INTENCLR_RXBUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
71979   #define SPIS_INTENCLR_RXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
71980   #define SPIS_INTENCLR_RXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
71981 
71982 /* TXBUSERROR @Bit 30 : Write '1' to disable interrupt for event TXBUSERROR */
71983   #define SPIS_INTENCLR_TXBUSERROR_Pos (30UL)        /*!< Position of TXBUSERROR field.                                        */
71984   #define SPIS_INTENCLR_TXBUSERROR_Msk (0x1UL << SPIS_INTENCLR_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.              */
71985   #define SPIS_INTENCLR_TXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of TXBUSERROR field.                            */
71986   #define SPIS_INTENCLR_TXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of TXBUSERROR field.                            */
71987   #define SPIS_INTENCLR_TXBUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
71988   #define SPIS_INTENCLR_TXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
71989   #define SPIS_INTENCLR_TXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
71990 
71991 
71992 /* SPIS_SEMSTAT: Semaphore status register */
71993   #define SPIS_SEMSTAT_ResetValue (0x00000001UL)     /*!< Reset value of SEMSTAT register.                                     */
71994 
71995 /* SEMSTAT @Bits 0..1 : Semaphore status */
71996   #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL)             /*!< Position of SEMSTAT field.                                           */
71997   #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field.                         */
71998   #define SPIS_SEMSTAT_SEMSTAT_Min (0x0UL)           /*!< Min enumerator value of SEMSTAT field.                               */
71999   #define SPIS_SEMSTAT_SEMSTAT_Max (0x3UL)           /*!< Max enumerator value of SEMSTAT field.                               */
72000   #define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL)          /*!< Semaphore is free                                                    */
72001   #define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL)           /*!< Semaphore is assigned to CPU                                         */
72002   #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL)          /*!< Semaphore is assigned to SPI slave                                   */
72003   #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL)    /*!< Semaphore is assigned to SPI but a handover to the CPU is pending    */
72004 
72005 
72006 /* SPIS_STATUS: Status from last transaction */
72007   #define SPIS_STATUS_ResetValue (0x00000000UL)      /*!< Reset value of STATUS register.                                      */
72008 
72009 /* OVERREAD @Bit 0 : TX buffer over-read detected, and prevented */
72010   #define SPIS_STATUS_OVERREAD_Pos (0UL)             /*!< Position of OVERREAD field.                                          */
72011   #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field.                        */
72012   #define SPIS_STATUS_OVERREAD_Min (0x0UL)           /*!< Min enumerator value of OVERREAD field.                              */
72013   #define SPIS_STATUS_OVERREAD_Max (0x1UL)           /*!< Max enumerator value of OVERREAD field.                              */
72014   #define SPIS_STATUS_OVERREAD_NotPresent (0x0UL)    /*!< Read: error not present                                              */
72015   #define SPIS_STATUS_OVERREAD_Present (0x1UL)       /*!< Read: error present                                                  */
72016   #define SPIS_STATUS_OVERREAD_Clear (0x1UL)         /*!< Write: clear error on writing '1'                                    */
72017 
72018 /* OVERFLOW @Bit 1 : RX buffer overflow detected, and prevented */
72019   #define SPIS_STATUS_OVERFLOW_Pos (1UL)             /*!< Position of OVERFLOW field.                                          */
72020   #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field.                        */
72021   #define SPIS_STATUS_OVERFLOW_Min (0x0UL)           /*!< Min enumerator value of OVERFLOW field.                              */
72022   #define SPIS_STATUS_OVERFLOW_Max (0x1UL)           /*!< Max enumerator value of OVERFLOW field.                              */
72023   #define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL)    /*!< Read: error not present                                              */
72024   #define SPIS_STATUS_OVERFLOW_Present (0x1UL)       /*!< Read: error present                                                  */
72025   #define SPIS_STATUS_OVERFLOW_Clear (0x1UL)         /*!< Write: clear error on writing '1'                                    */
72026 
72027 
72028 /* SPIS_ENABLE: Enable SPI slave */
72029   #define SPIS_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */
72030 
72031 /* ENABLE @Bits 0..3 : Enable or disable SPI slave */
72032   #define SPIS_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
72033   #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
72034   #define SPIS_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
72035   #define SPIS_ENABLE_ENABLE_Max (0x2UL)             /*!< Max enumerator value of ENABLE field.                                */
72036   #define SPIS_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable SPI slave                                                    */
72037   #define SPIS_ENABLE_ENABLE_Enabled (0x2UL)         /*!< Enable SPI slave                                                     */
72038 
72039 
72040 /* SPIS_CONFIG: Configuration register */
72041   #define SPIS_CONFIG_ResetValue (0x00000000UL)      /*!< Reset value of CONFIG register.                                      */
72042 
72043 /* ORDER @Bit 0 : Bit order */
72044   #define SPIS_CONFIG_ORDER_Pos (0UL)                /*!< Position of ORDER field.                                             */
72045   #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field.                                 */
72046   #define SPIS_CONFIG_ORDER_Min (0x0UL)              /*!< Min enumerator value of ORDER field.                                 */
72047   #define SPIS_CONFIG_ORDER_Max (0x1UL)              /*!< Max enumerator value of ORDER field.                                 */
72048   #define SPIS_CONFIG_ORDER_MsbFirst (0x0UL)         /*!< Most significant bit shifted out first                               */
72049   #define SPIS_CONFIG_ORDER_LsbFirst (0x1UL)         /*!< Least significant bit shifted out first                              */
72050 
72051 /* CPHA @Bit 1 : Serial clock (SCK) phase */
72052   #define SPIS_CONFIG_CPHA_Pos (1UL)                 /*!< Position of CPHA field.                                              */
72053   #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field.                                    */
72054   #define SPIS_CONFIG_CPHA_Min (0x0UL)               /*!< Min enumerator value of CPHA field.                                  */
72055   #define SPIS_CONFIG_CPHA_Max (0x1UL)               /*!< Max enumerator value of CPHA field.                                  */
72056   #define SPIS_CONFIG_CPHA_Leading (0x0UL)           /*!< Sample on leading edge of clock, shift serial data on trailing edge  */
72057   #define SPIS_CONFIG_CPHA_Trailing (0x1UL)          /*!< Sample on trailing edge of clock, shift serial data on leading edge  */
72058 
72059 /* CPOL @Bit 2 : Serial clock (SCK) polarity */
72060   #define SPIS_CONFIG_CPOL_Pos (2UL)                 /*!< Position of CPOL field.                                              */
72061   #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field.                                    */
72062   #define SPIS_CONFIG_CPOL_Min (0x0UL)               /*!< Min enumerator value of CPOL field.                                  */
72063   #define SPIS_CONFIG_CPOL_Max (0x1UL)               /*!< Max enumerator value of CPOL field.                                  */
72064   #define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL)        /*!< Active high                                                          */
72065   #define SPIS_CONFIG_CPOL_ActiveLow (0x1UL)         /*!< Active low                                                           */
72066 
72067 
72068 /* SPIS_DEF: Default character. Character clocked out in case of an ignored transaction. */
72069   #define SPIS_DEF_ResetValue (0x00000000UL)         /*!< Reset value of DEF register.                                         */
72070 
72071 /* DEF @Bits 0..7 : Default character. Character clocked out in case of an ignored transaction. */
72072   #define SPIS_DEF_DEF_Pos (0UL)                     /*!< Position of DEF field.                                               */
72073   #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field.                                            */
72074 
72075 
72076 /* SPIS_ORC: Over-read character */
72077   #define SPIS_ORC_ResetValue (0x00000000UL)         /*!< Reset value of ORC register.                                         */
72078 
72079 /* ORC @Bits 0..7 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
72080   #define SPIS_ORC_ORC_Pos (0UL)                     /*!< Position of ORC field.                                               */
72081   #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field.                                            */
72082 
72083 
72084 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
72085 
72086 /* =========================================================================================================================== */
72087 /* ================                                            SPU                                            ================ */
72088 /* =========================================================================================================================== */
72089 
72090 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
72091 
72092 /* ================================================= Struct SPU_PERIPHACCERR ================================================= */
72093 /**
72094   * @brief PERIPHACCERR [SPU_PERIPHACCERR] (unspecified)
72095   */
72096 typedef struct {
72097   __IM  uint32_t  ADDRESS;                           /*!< (@ 0x00000000) Address of the transaction that caused first error.   */
72098   __IM  uint32_t  INFO;                              /*!< (@ 0x00000004) Information about the transaction that caused first
72099                                                                          error.*/
72100 } NRF_SPU_PERIPHACCERR_Type;                         /*!< Size = 8 (0x008)                                                     */
72101 
72102 /* SPU_PERIPHACCERR_ADDRESS: Address of the transaction that caused first error. */
72103   #define SPU_PERIPHACCERR_ADDRESS_ResetValue (0x00000000UL) /*!< Reset value of ADDRESS register.                             */
72104 
72105 /* ADDRESS @Bits 0..15 : Address */
72106   #define SPU_PERIPHACCERR_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                           */
72107   #define SPU_PERIPHACCERR_ADDRESS_ADDRESS_Msk (0xFFFFUL << SPU_PERIPHACCERR_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS
72108                                                                             field.*/
72109 
72110 
72111 /* SPU_PERIPHACCERR_INFO: Information about the transaction that caused first error. */
72112   #define SPU_PERIPHACCERR_INFO_ResetValue (0x00000000UL) /*!< Reset value of INFO register.                                   */
72113 
72114 /* OWNERID @Bits 0..3 : OWNERID */
72115   #define SPU_PERIPHACCERR_INFO_OWNERID_Pos (0UL)    /*!< Position of OWNERID field.                                           */
72116   #define SPU_PERIPHACCERR_INFO_OWNERID_Msk (0xFUL << SPU_PERIPHACCERR_INFO_OWNERID_Pos) /*!< Bit mask of OWNERID field.       */
72117 
72118 
72119 
72120 /* ==================================================== Struct SPU_PERIPH ==================================================== */
72121 /**
72122   * @brief PERIPH [SPU_PERIPH] (unspecified)
72123   */
72124 typedef struct {
72125   __IOM uint32_t  PERM;                              /*!< (@ 0x00000000) Get and set the applicable access permissions for the
72126                                                                          peripheral slave index n*/
72127 } NRF_SPU_PERIPH_Type;                               /*!< Size = 4 (0x004)                                                     */
72128   #define SPU_PERIPH_MaxCount (32UL)                 /*!< Size of PERIPH[32] array.                                            */
72129   #define SPU_PERIPH_MaxIndex (31UL)                 /*!< Max index of PERIPH[32] array.                                       */
72130   #define SPU_PERIPH_MinIndex (0UL)                  /*!< Min index of PERIPH[32] array.                                       */
72131 
72132 /* SPU_PERIPH_PERM: Get and set the applicable access permissions for the peripheral slave index n */
72133   #define SPU_PERIPH_PERM_ResetValue (0x8000000AUL)  /*!< Reset value of PERM register.                                        */
72134 
72135 /* SECUREMAPPING @Bits 0..1 : Read capabilities for TrustZone Cortex-M secure attribute */
72136   #define SPU_PERIPH_PERM_SECUREMAPPING_Pos (0UL)    /*!< Position of SECUREMAPPING field.                                     */
72137   #define SPU_PERIPH_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPH_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */
72138   #define SPU_PERIPH_PERM_SECUREMAPPING_Min (0x0UL)  /*!< Min enumerator value of SECUREMAPPING field.                         */
72139   #define SPU_PERIPH_PERM_SECUREMAPPING_Max (0x3UL)  /*!< Max enumerator value of SECUREMAPPING field.                         */
72140   #define SPU_PERIPH_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< This peripheral is always accessible as a non-secure peripheral */
72141   #define SPU_PERIPH_PERM_SECUREMAPPING_Secure (0x1UL) /*!< This peripheral is always accessible as a secure peripheral        */
72142   #define SPU_PERIPH_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for this peripheral is
72143                                                                     defined by the PERIPH[n].PERM register*/
72144   #define SPU_PERIPH_PERM_SECUREMAPPING_Split (0x3UL) /*!< This peripheral implements the split security mechanism.            */
72145 
72146 /* DMA @Bits 2..3 : Read the peripheral DMA capabilities */
72147   #define SPU_PERIPH_PERM_DMA_Pos (2UL)              /*!< Position of DMA field.                                               */
72148   #define SPU_PERIPH_PERM_DMA_Msk (0x3UL << SPU_PERIPH_PERM_DMA_Pos) /*!< Bit mask of DMA field.                               */
72149   #define SPU_PERIPH_PERM_DMA_Min (0x0UL)            /*!< Min enumerator value of DMA field.                                   */
72150   #define SPU_PERIPH_PERM_DMA_Max (0x2UL)            /*!< Max enumerator value of DMA field.                                   */
72151   #define SPU_PERIPH_PERM_DMA_NoDMA (0x0UL)          /*!< Peripheral has no DMA capability                                     */
72152   #define SPU_PERIPH_PERM_DMA_NoSeparateAttribute (0x1UL) /*!< Peripheral has DMA and DMA transfers always have the same
72153                                                                security attribute as assigned to the peripheral*/
72154   #define SPU_PERIPH_PERM_DMA_SeparateAttribute (0x2UL) /*!< Peripheral has DMA and DMA transfers can have a different security
72155                                                              attribute than the one assigned to the peripheral*/
72156 
72157 /* SECATTR @Bit 4 : Peripheral security mapping */
72158   #define SPU_PERIPH_PERM_SECATTR_Pos (4UL)          /*!< Position of SECATTR field.                                           */
72159   #define SPU_PERIPH_PERM_SECATTR_Msk (0x1UL << SPU_PERIPH_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field.                   */
72160   #define SPU_PERIPH_PERM_SECATTR_Min (0x0UL)        /*!< Min enumerator value of SECATTR field.                               */
72161   #define SPU_PERIPH_PERM_SECATTR_Max (0x1UL)        /*!< Max enumerator value of SECATTR field.                               */
72162   #define SPU_PERIPH_PERM_SECATTR_Secure (0x1UL)     /*!< Peripheral is mapped in secure peripheral address space              */
72163   #define SPU_PERIPH_PERM_SECATTR_NonSecure (0x0UL)  /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure
72164                                                           peripheral address space. If SECUREMAPPING == Split: Peripheral is
72165                                                           mapped in non-secure and secure peripheral address space.*/
72166 
72167 /* DMASEC @Bit 5 : Security attribution for the DMA transfer */
72168   #define SPU_PERIPH_PERM_DMASEC_Pos (5UL)           /*!< Position of DMASEC field.                                            */
72169   #define SPU_PERIPH_PERM_DMASEC_Msk (0x1UL << SPU_PERIPH_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field.                      */
72170   #define SPU_PERIPH_PERM_DMASEC_Min (0x0UL)         /*!< Min enumerator value of DMASEC field.                                */
72171   #define SPU_PERIPH_PERM_DMASEC_Max (0x1UL)         /*!< Max enumerator value of DMASEC field.                                */
72172   #define SPU_PERIPH_PERM_DMASEC_Secure (0x1UL)      /*!< DMA transfers initiated by this peripheral have the secure attribute
72173                                                           set*/
72174   #define SPU_PERIPH_PERM_DMASEC_NonSecure (0x0UL)   /*!< DMA transfers initiated by this peripheral have the non-secure
72175                                                           attribute set*/
72176 
72177 /* LOCK @Bit 8 : Register lock */
72178   #define SPU_PERIPH_PERM_LOCK_Pos (8UL)             /*!< Position of LOCK field.                                              */
72179   #define SPU_PERIPH_PERM_LOCK_Msk (0x1UL << SPU_PERIPH_PERM_LOCK_Pos) /*!< Bit mask of LOCK field.                            */
72180   #define SPU_PERIPH_PERM_LOCK_Min (0x0UL)           /*!< Min enumerator value of LOCK field.                                  */
72181   #define SPU_PERIPH_PERM_LOCK_Max (0x1UL)           /*!< Max enumerator value of LOCK field.                                  */
72182   #define SPU_PERIPH_PERM_LOCK_Unlocked (0x0UL)      /*!< This register can be updated                                         */
72183   #define SPU_PERIPH_PERM_LOCK_Locked (0x1UL)        /*!< The content of this register can not be changed until the next reset */
72184 
72185 /* OWNERID @Bits 16..19 : Peripheral owner ID */
72186   #define SPU_PERIPH_PERM_OWNERID_Pos (16UL)         /*!< Position of OWNERID field.                                           */
72187   #define SPU_PERIPH_PERM_OWNERID_Msk (0xFUL << SPU_PERIPH_PERM_OWNERID_Pos) /*!< Bit mask of OWNERID field.                   */
72188   #define SPU_PERIPH_PERM_OWNERID_Min (0x0UL)        /*!< Min value of OWNERID field.                                          */
72189   #define SPU_PERIPH_PERM_OWNERID_Max (0xFUL)        /*!< Max size of OWNERID field.                                           */
72190 
72191 /* OWNERPROG @Bit 30 : Indicates if OWNERID is programmable or not */
72192   #define SPU_PERIPH_PERM_OWNERPROG_Pos (30UL)       /*!< Position of OWNERPROG field.                                         */
72193   #define SPU_PERIPH_PERM_OWNERPROG_Msk (0x1UL << SPU_PERIPH_PERM_OWNERPROG_Pos) /*!< Bit mask of OWNERPROG field.             */
72194   #define SPU_PERIPH_PERM_OWNERPROG_Min (0x0UL)      /*!< Min enumerator value of OWNERPROG field.                             */
72195   #define SPU_PERIPH_PERM_OWNERPROG_Max (0x1UL)      /*!< Max enumerator value of OWNERPROG field.                             */
72196   #define SPU_PERIPH_PERM_OWNERPROG_NotProgrammable (0x0UL) /*!< OWNERID is not programmable                                   */
72197   #define SPU_PERIPH_PERM_OWNERPROG_Programmable (0x1UL) /*!< OWNERID is programmable                                          */
72198 
72199 /* PRESENT @Bit 31 : Indicates if a peripheral is present with peripheral slave index n */
72200   #define SPU_PERIPH_PERM_PRESENT_Pos (31UL)         /*!< Position of PRESENT field.                                           */
72201   #define SPU_PERIPH_PERM_PRESENT_Msk (0x1UL << SPU_PERIPH_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field.                   */
72202   #define SPU_PERIPH_PERM_PRESENT_Min (0x0UL)        /*!< Min enumerator value of PRESENT field.                               */
72203   #define SPU_PERIPH_PERM_PRESENT_Max (0x1UL)        /*!< Max enumerator value of PRESENT field.                               */
72204   #define SPU_PERIPH_PERM_PRESENT_NotPresent (0x0UL) /*!< Peripheral is not present                                            */
72205   #define SPU_PERIPH_PERM_PRESENT_IsPresent (0x1UL)  /*!< Peripheral is present                                                */
72206 
72207 
72208 
72209 /* ================================================= Struct SPU_FEATURE_IPCT ================================================= */
72210 /**
72211   * @brief IPCT [SPU_FEATURE_IPCT] (unspecified)
72212   */
72213 typedef struct {
72214   __IOM uint32_t  CH[24];                            /*!< (@ 0x00000000) Configuration of features for channel n of IPCT       */
72215   __IOM uint32_t  INTERRUPT[8];                      /*!< (@ 0x00000060) Configuration of features for interrupt n of IPCT     */
72216 } NRF_SPU_FEATURE_IPCT_Type;                         /*!< Size = 128 (0x080)                                                   */
72217 
72218 /* SPU_FEATURE_IPCT_CH: Configuration of features for channel n of IPCT */
72219   #define SPU_FEATURE_IPCT_CH_MaxCount (24UL)        /*!< Max size of CH[24] array.                                            */
72220   #define SPU_FEATURE_IPCT_CH_MaxIndex (23UL)        /*!< Max index of CH[24] array.                                           */
72221   #define SPU_FEATURE_IPCT_CH_MinIndex (0UL)         /*!< Min index of CH[24] array.                                           */
72222   #define SPU_FEATURE_IPCT_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[24] register.                                   */
72223 
72224 /* SECATTR @Bit 4 : SECATTR feature */
72225   #define SPU_FEATURE_IPCT_CH_SECATTR_Pos (4UL)      /*!< Position of SECATTR field.                                           */
72226   #define SPU_FEATURE_IPCT_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_IPCT_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field.           */
72227   #define SPU_FEATURE_IPCT_CH_SECATTR_Min (0x0UL)    /*!< Min enumerator value of SECATTR field.                               */
72228   #define SPU_FEATURE_IPCT_CH_SECATTR_Max (0x1UL)    /*!< Max enumerator value of SECATTR field.                               */
72229   #define SPU_FEATURE_IPCT_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                         */
72230   #define SPU_FEATURE_IPCT_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                                 */
72231 
72232 /* LOCK @Bit 8 : LOCK feature */
72233   #define SPU_FEATURE_IPCT_CH_LOCK_Pos (8UL)         /*!< Position of LOCK field.                                              */
72234   #define SPU_FEATURE_IPCT_CH_LOCK_Msk (0x1UL << SPU_FEATURE_IPCT_CH_LOCK_Pos) /*!< Bit mask of LOCK field.                    */
72235   #define SPU_FEATURE_IPCT_CH_LOCK_Min (0x0UL)       /*!< Min enumerator value of LOCK field.                                  */
72236   #define SPU_FEATURE_IPCT_CH_LOCK_Max (0x1UL)       /*!< Max enumerator value of LOCK field.                                  */
72237   #define SPU_FEATURE_IPCT_CH_LOCK_Unlocked (0x0UL)  /*!< Feature permissions can be updated                                   */
72238   #define SPU_FEATURE_IPCT_CH_LOCK_Locked (0x1UL)    /*!< Feature permissions can not be changed until the next reset          */
72239 
72240 /* OWNERID @Bits 16..19 : Feature owner ID */
72241   #define SPU_FEATURE_IPCT_CH_OWNERID_Pos (16UL)     /*!< Position of OWNERID field.                                           */
72242   #define SPU_FEATURE_IPCT_CH_OWNERID_Msk (0xFUL << SPU_FEATURE_IPCT_CH_OWNERID_Pos) /*!< Bit mask of OWNERID field.           */
72243   #define SPU_FEATURE_IPCT_CH_OWNERID_Min (0x0UL)    /*!< Min value of OWNERID field.                                          */
72244   #define SPU_FEATURE_IPCT_CH_OWNERID_Max (0xFUL)    /*!< Max size of OWNERID field.                                           */
72245 
72246 
72247 /* SPU_FEATURE_IPCT_INTERRUPT: Configuration of features for interrupt n of IPCT */
72248   #define SPU_FEATURE_IPCT_INTERRUPT_MaxCount (8UL)  /*!< Max size of INTERRUPT[8] array.                                      */
72249   #define SPU_FEATURE_IPCT_INTERRUPT_MaxIndex (7UL)  /*!< Max index of INTERRUPT[8] array.                                     */
72250   #define SPU_FEATURE_IPCT_INTERRUPT_MinIndex (0UL)  /*!< Min index of INTERRUPT[8] array.                                     */
72251   #define SPU_FEATURE_IPCT_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[8] register.                      */
72252 
72253 /* SECATTR @Bit 4 : SECATTR feature */
72254   #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                         */
72255   #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR
72256                                                                             field.*/
72257   #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                           */
72258   #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                           */
72259   #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                  */
72260   #define SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                          */
72261 
72262 /* LOCK @Bit 8 : LOCK feature */
72263   #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Pos (8UL)  /*!< Position of LOCK field.                                              */
72264   #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_IPCT_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field.      */
72265   #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                                 */
72266   #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                                 */
72267   #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                             */
72268   #define SPU_FEATURE_IPCT_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset      */
72269 
72270 /* OWNERID @Bits 16..19 : Feature owner ID */
72271   #define SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Pos (16UL) /*!< Position of OWNERID field.                                        */
72272   #define SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Msk (0xFUL << SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Pos) /*!< Bit mask of OWNERID
72273                                                                             field.*/
72274   #define SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field.                                      */
72275   #define SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field.                                       */
72276 
72277 
72278 
72279 /* ================================================ Struct SPU_FEATURE_DPPIC ================================================= */
72280 /**
72281   * @brief DPPIC [SPU_FEATURE_DPPIC] (unspecified)
72282   */
72283 typedef struct {
72284   __IOM uint32_t  CH[24];                            /*!< (@ 0x00000000) Configuration of features for channel n of DPPIC      */
72285   __IOM uint32_t  CHG[8];                            /*!< (@ 0x00000060) Configuration of features for channel group n of DPPIC*/
72286 } NRF_SPU_FEATURE_DPPIC_Type;                        /*!< Size = 128 (0x080)                                                   */
72287 
72288 /* SPU_FEATURE_DPPIC_CH: Configuration of features for channel n of DPPIC */
72289   #define SPU_FEATURE_DPPIC_CH_MaxCount (24UL)       /*!< Max size of CH[24] array.                                            */
72290   #define SPU_FEATURE_DPPIC_CH_MaxIndex (23UL)       /*!< Max index of CH[24] array.                                           */
72291   #define SPU_FEATURE_DPPIC_CH_MinIndex (0UL)        /*!< Min index of CH[24] array.                                           */
72292   #define SPU_FEATURE_DPPIC_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[24] register.                                  */
72293 
72294 /* SECATTR @Bit 4 : SECATTR feature */
72295   #define SPU_FEATURE_DPPIC_CH_SECATTR_Pos (4UL)     /*!< Position of SECATTR field.                                           */
72296   #define SPU_FEATURE_DPPIC_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_DPPIC_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field.         */
72297   #define SPU_FEATURE_DPPIC_CH_SECATTR_Min (0x0UL)   /*!< Min enumerator value of SECATTR field.                               */
72298   #define SPU_FEATURE_DPPIC_CH_SECATTR_Max (0x1UL)   /*!< Max enumerator value of SECATTR field.                               */
72299   #define SPU_FEATURE_DPPIC_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                        */
72300   #define SPU_FEATURE_DPPIC_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                                */
72301 
72302 /* LOCK @Bit 8 : LOCK feature */
72303   #define SPU_FEATURE_DPPIC_CH_LOCK_Pos (8UL)        /*!< Position of LOCK field.                                              */
72304   #define SPU_FEATURE_DPPIC_CH_LOCK_Msk (0x1UL << SPU_FEATURE_DPPIC_CH_LOCK_Pos) /*!< Bit mask of LOCK field.                  */
72305   #define SPU_FEATURE_DPPIC_CH_LOCK_Min (0x0UL)      /*!< Min enumerator value of LOCK field.                                  */
72306   #define SPU_FEATURE_DPPIC_CH_LOCK_Max (0x1UL)      /*!< Max enumerator value of LOCK field.                                  */
72307   #define SPU_FEATURE_DPPIC_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                   */
72308   #define SPU_FEATURE_DPPIC_CH_LOCK_Locked (0x1UL)   /*!< Feature permissions can not be changed until the next reset          */
72309 
72310 /* OWNERID @Bits 16..19 : Feature owner ID */
72311   #define SPU_FEATURE_DPPIC_CH_OWNERID_Pos (16UL)    /*!< Position of OWNERID field.                                           */
72312   #define SPU_FEATURE_DPPIC_CH_OWNERID_Msk (0xFUL << SPU_FEATURE_DPPIC_CH_OWNERID_Pos) /*!< Bit mask of OWNERID field.         */
72313   #define SPU_FEATURE_DPPIC_CH_OWNERID_Min (0x0UL)   /*!< Min value of OWNERID field.                                          */
72314   #define SPU_FEATURE_DPPIC_CH_OWNERID_Max (0xFUL)   /*!< Max size of OWNERID field.                                           */
72315 
72316 
72317 /* SPU_FEATURE_DPPIC_CHG: Configuration of features for channel group n of DPPIC */
72318   #define SPU_FEATURE_DPPIC_CHG_MaxCount (8UL)       /*!< Max size of CHG[8] array.                                            */
72319   #define SPU_FEATURE_DPPIC_CHG_MaxIndex (7UL)       /*!< Max index of CHG[8] array.                                           */
72320   #define SPU_FEATURE_DPPIC_CHG_MinIndex (0UL)       /*!< Min index of CHG[8] array.                                           */
72321   #define SPU_FEATURE_DPPIC_CHG_ResetValue (0x00000000UL) /*!< Reset value of CHG[8] register.                                 */
72322 
72323 /* SECATTR @Bit 4 : SECATTR feature */
72324   #define SPU_FEATURE_DPPIC_CHG_SECATTR_Pos (4UL)    /*!< Position of SECATTR field.                                           */
72325   #define SPU_FEATURE_DPPIC_CHG_SECATTR_Msk (0x1UL << SPU_FEATURE_DPPIC_CHG_SECATTR_Pos) /*!< Bit mask of SECATTR field.       */
72326   #define SPU_FEATURE_DPPIC_CHG_SECATTR_Min (0x0UL)  /*!< Min enumerator value of SECATTR field.                               */
72327   #define SPU_FEATURE_DPPIC_CHG_SECATTR_Max (0x1UL)  /*!< Max enumerator value of SECATTR field.                               */
72328   #define SPU_FEATURE_DPPIC_CHG_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                       */
72329   #define SPU_FEATURE_DPPIC_CHG_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                               */
72330 
72331 /* LOCK @Bit 8 : LOCK feature */
72332   #define SPU_FEATURE_DPPIC_CHG_LOCK_Pos (8UL)       /*!< Position of LOCK field.                                              */
72333   #define SPU_FEATURE_DPPIC_CHG_LOCK_Msk (0x1UL << SPU_FEATURE_DPPIC_CHG_LOCK_Pos) /*!< Bit mask of LOCK field.                */
72334   #define SPU_FEATURE_DPPIC_CHG_LOCK_Min (0x0UL)     /*!< Min enumerator value of LOCK field.                                  */
72335   #define SPU_FEATURE_DPPIC_CHG_LOCK_Max (0x1UL)     /*!< Max enumerator value of LOCK field.                                  */
72336   #define SPU_FEATURE_DPPIC_CHG_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                  */
72337   #define SPU_FEATURE_DPPIC_CHG_LOCK_Locked (0x1UL)  /*!< Feature permissions can not be changed until the next reset          */
72338 
72339 /* OWNERID @Bits 16..19 : Feature owner ID */
72340   #define SPU_FEATURE_DPPIC_CHG_OWNERID_Pos (16UL)   /*!< Position of OWNERID field.                                           */
72341   #define SPU_FEATURE_DPPIC_CHG_OWNERID_Msk (0xFUL << SPU_FEATURE_DPPIC_CHG_OWNERID_Pos) /*!< Bit mask of OWNERID field.       */
72342   #define SPU_FEATURE_DPPIC_CHG_OWNERID_Min (0x0UL)  /*!< Min value of OWNERID field.                                          */
72343   #define SPU_FEATURE_DPPIC_CHG_OWNERID_Max (0xFUL)  /*!< Max size of OWNERID field.                                           */
72344 
72345 
72346 
72347 /* ================================================ Struct SPU_FEATURE_GPIOTE ================================================ */
72348 /**
72349   * @brief GPIOTE [SPU_FEATURE_GPIOTE] (unspecified)
72350   */
72351 typedef struct {
72352   __IOM uint32_t  CH[8];                             /*!< (@ 0x00000000) Configuration of features for channel o of GPIOTE[n]  */
72353   __IOM uint32_t  INTERRUPT[8];                      /*!< (@ 0x00000020) Configuration of features for interrupt o of GPIOTE[n]*/
72354 } NRF_SPU_FEATURE_GPIOTE_Type;                       /*!< Size = 64 (0x040)                                                    */
72355   #define SPU_FEATURE_GPIOTE_MaxCount (1UL)          /*!< Size of GPIOTE[1] array.                                             */
72356   #define SPU_FEATURE_GPIOTE_MaxIndex (0UL)          /*!< Max index of GPIOTE[1] array.                                        */
72357   #define SPU_FEATURE_GPIOTE_MinIndex (0UL)          /*!< Min index of GPIOTE[1] array.                                        */
72358 
72359 /* SPU_FEATURE_GPIOTE_CH: Configuration of features for channel o of GPIOTE[n] */
72360   #define SPU_FEATURE_GPIOTE_CH_MaxCount (8UL)       /*!< Max size of CH[8] array.                                             */
72361   #define SPU_FEATURE_GPIOTE_CH_MaxIndex (7UL)       /*!< Max index of CH[8] array.                                            */
72362   #define SPU_FEATURE_GPIOTE_CH_MinIndex (0UL)       /*!< Min index of CH[8] array.                                            */
72363   #define SPU_FEATURE_GPIOTE_CH_ResetValue (0x00000000UL) /*!< Reset value of CH[8] register.                                  */
72364 
72365 /* SECATTR @Bit 4 : SECATTR feature */
72366   #define SPU_FEATURE_GPIOTE_CH_SECATTR_Pos (4UL)    /*!< Position of SECATTR field.                                           */
72367   #define SPU_FEATURE_GPIOTE_CH_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIOTE_CH_SECATTR_Pos) /*!< Bit mask of SECATTR field.       */
72368   #define SPU_FEATURE_GPIOTE_CH_SECATTR_Min (0x0UL)  /*!< Min enumerator value of SECATTR field.                               */
72369   #define SPU_FEATURE_GPIOTE_CH_SECATTR_Max (0x1UL)  /*!< Max enumerator value of SECATTR field.                               */
72370   #define SPU_FEATURE_GPIOTE_CH_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                       */
72371   #define SPU_FEATURE_GPIOTE_CH_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                               */
72372 
72373 /* LOCK @Bit 8 : LOCK feature */
72374   #define SPU_FEATURE_GPIOTE_CH_LOCK_Pos (8UL)       /*!< Position of LOCK field.                                              */
72375   #define SPU_FEATURE_GPIOTE_CH_LOCK_Msk (0x1UL << SPU_FEATURE_GPIOTE_CH_LOCK_Pos) /*!< Bit mask of LOCK field.                */
72376   #define SPU_FEATURE_GPIOTE_CH_LOCK_Min (0x0UL)     /*!< Min enumerator value of LOCK field.                                  */
72377   #define SPU_FEATURE_GPIOTE_CH_LOCK_Max (0x1UL)     /*!< Max enumerator value of LOCK field.                                  */
72378   #define SPU_FEATURE_GPIOTE_CH_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                  */
72379   #define SPU_FEATURE_GPIOTE_CH_LOCK_Locked (0x1UL)  /*!< Feature permissions can not be changed until the next reset          */
72380 
72381 /* OWNERID @Bits 16..19 : Feature owner ID */
72382   #define SPU_FEATURE_GPIOTE_CH_OWNERID_Pos (16UL)   /*!< Position of OWNERID field.                                           */
72383   #define SPU_FEATURE_GPIOTE_CH_OWNERID_Msk (0xFUL << SPU_FEATURE_GPIOTE_CH_OWNERID_Pos) /*!< Bit mask of OWNERID field.       */
72384   #define SPU_FEATURE_GPIOTE_CH_OWNERID_Min (0x0UL)  /*!< Min value of OWNERID field.                                          */
72385   #define SPU_FEATURE_GPIOTE_CH_OWNERID_Max (0xFUL)  /*!< Max size of OWNERID field.                                           */
72386 
72387 
72388 /* SPU_FEATURE_GPIOTE_INTERRUPT: Configuration of features for interrupt o of GPIOTE[n] */
72389   #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxCount (8UL) /*!< Max size of INTERRUPT[8] array.                                     */
72390   #define SPU_FEATURE_GPIOTE_INTERRUPT_MaxIndex (7UL) /*!< Max index of INTERRUPT[8] array.                                    */
72391   #define SPU_FEATURE_GPIOTE_INTERRUPT_MinIndex (0UL) /*!< Min index of INTERRUPT[8] array.                                    */
72392   #define SPU_FEATURE_GPIOTE_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[8] register.                    */
72393 
72394 /* SECATTR @Bit 4 : SECATTR feature */
72395   #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                       */
72396   #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR
72397                                                                             field.*/
72398   #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                         */
72399   #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                         */
72400   #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                */
72401   #define SPU_FEATURE_GPIOTE_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                        */
72402 
72403 /* LOCK @Bit 8 : LOCK feature */
72404   #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos (8UL) /*!< Position of LOCK field.                                             */
72405   #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field.  */
72406   #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                               */
72407   #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                               */
72408   #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                           */
72409   #define SPU_FEATURE_GPIOTE_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset    */
72410 
72411 /* OWNERID @Bits 16..19 : Feature owner ID */
72412   #define SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Pos (16UL) /*!< Position of OWNERID field.                                      */
72413   #define SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Msk (0xFUL << SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Pos) /*!< Bit mask of OWNERID
72414                                                                             field.*/
72415   #define SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field.                                    */
72416   #define SPU_FEATURE_GPIOTE_INTERRUPT_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field.                                     */
72417 
72418 
72419 
72420 /* ================================================= Struct SPU_FEATURE_GPIO ================================================= */
72421 /**
72422   * @brief GPIO [SPU_FEATURE_GPIO] (unspecified)
72423   */
72424 typedef struct {
72425   __IOM uint32_t  PIN[32];                           /*!< (@ 0x00000000) Configuration of features for GPIO[n] PIN[o]          */
72426 } NRF_SPU_FEATURE_GPIO_Type;                         /*!< Size = 128 (0x080)                                                   */
72427   #define SPU_FEATURE_GPIO_MaxCount (10UL)           /*!< Size of GPIO[10] array.                                              */
72428   #define SPU_FEATURE_GPIO_MaxIndex (9UL)            /*!< Max index of GPIO[10] array.                                         */
72429   #define SPU_FEATURE_GPIO_MinIndex (0UL)            /*!< Min index of GPIO[10] array.                                         */
72430 
72431 /* SPU_FEATURE_GPIO_PIN: Configuration of features for GPIO[n] PIN[o] */
72432   #define SPU_FEATURE_GPIO_PIN_MaxCount (32UL)       /*!< Max size of PIN[32] array.                                           */
72433   #define SPU_FEATURE_GPIO_PIN_MaxIndex (31UL)       /*!< Max index of PIN[32] array.                                          */
72434   #define SPU_FEATURE_GPIO_PIN_MinIndex (0UL)        /*!< Min index of PIN[32] array.                                          */
72435   #define SPU_FEATURE_GPIO_PIN_ResetValue (0x00000000UL) /*!< Reset value of PIN[32] register.                                 */
72436 
72437 /* SECATTR @Bit 4 : SECATTR feature */
72438   #define SPU_FEATURE_GPIO_PIN_SECATTR_Pos (4UL)     /*!< Position of SECATTR field.                                           */
72439   #define SPU_FEATURE_GPIO_PIN_SECATTR_Msk (0x1UL << SPU_FEATURE_GPIO_PIN_SECATTR_Pos) /*!< Bit mask of SECATTR field.         */
72440   #define SPU_FEATURE_GPIO_PIN_SECATTR_Min (0x0UL)   /*!< Min enumerator value of SECATTR field.                               */
72441   #define SPU_FEATURE_GPIO_PIN_SECATTR_Max (0x1UL)   /*!< Max enumerator value of SECATTR field.                               */
72442   #define SPU_FEATURE_GPIO_PIN_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                        */
72443   #define SPU_FEATURE_GPIO_PIN_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                                */
72444 
72445 /* LOCK @Bit 8 : LOCK feature */
72446   #define SPU_FEATURE_GPIO_PIN_LOCK_Pos (8UL)        /*!< Position of LOCK field.                                              */
72447   #define SPU_FEATURE_GPIO_PIN_LOCK_Msk (0x1UL << SPU_FEATURE_GPIO_PIN_LOCK_Pos) /*!< Bit mask of LOCK field.                  */
72448   #define SPU_FEATURE_GPIO_PIN_LOCK_Min (0x0UL)      /*!< Min enumerator value of LOCK field.                                  */
72449   #define SPU_FEATURE_GPIO_PIN_LOCK_Max (0x1UL)      /*!< Max enumerator value of LOCK field.                                  */
72450   #define SPU_FEATURE_GPIO_PIN_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                                   */
72451   #define SPU_FEATURE_GPIO_PIN_LOCK_Locked (0x1UL)   /*!< Feature permissions can not be changed until the next reset          */
72452 
72453 /* OWNERID @Bits 16..19 : Feature owner ID */
72454   #define SPU_FEATURE_GPIO_PIN_OWNERID_Pos (16UL)    /*!< Position of OWNERID field.                                           */
72455   #define SPU_FEATURE_GPIO_PIN_OWNERID_Msk (0xFUL << SPU_FEATURE_GPIO_PIN_OWNERID_Pos) /*!< Bit mask of OWNERID field.         */
72456   #define SPU_FEATURE_GPIO_PIN_OWNERID_Min (0x0UL)   /*!< Min value of OWNERID field.                                          */
72457   #define SPU_FEATURE_GPIO_PIN_OWNERID_Max (0xFUL)   /*!< Max size of OWNERID field.                                           */
72458 
72459 
72460 
72461 /* ================================================= Struct SPU_FEATURE_GRTC ================================================= */
72462 /**
72463   * @brief GRTC [SPU_FEATURE_GRTC] (unspecified)
72464   */
72465 typedef struct {
72466   __IOM uint32_t  CC[16];                            /*!< (@ 0x00000000) Configuration of features for CC n of GRTC            */
72467   __IM  uint32_t  RESERVED[15];
72468   __IOM uint32_t  SYSCOUNTER;                        /*!< (@ 0x0000007C) Configuration of features for SYSCOUNTERL/SYSCOUNTERH
72469                                                                          of GRTC*/
72470   __IOM uint32_t  INTERRUPT[7];                      /*!< (@ 0x00000080) Configuration of features for interrupt n of GRTC     */
72471 } NRF_SPU_FEATURE_GRTC_Type;                         /*!< Size = 156 (0x09C)                                                   */
72472 
72473 /* SPU_FEATURE_GRTC_CC: Configuration of features for CC n of GRTC */
72474   #define SPU_FEATURE_GRTC_CC_MaxCount (16UL)        /*!< Max size of CC[16] array.                                            */
72475   #define SPU_FEATURE_GRTC_CC_MaxIndex (15UL)        /*!< Max index of CC[16] array.                                           */
72476   #define SPU_FEATURE_GRTC_CC_MinIndex (0UL)         /*!< Min index of CC[16] array.                                           */
72477   #define SPU_FEATURE_GRTC_CC_ResetValue (0x00000000UL) /*!< Reset value of CC[16] register.                                   */
72478 
72479 /* SECATTR @Bit 4 : SECATTR feature */
72480   #define SPU_FEATURE_GRTC_CC_SECATTR_Pos (4UL)      /*!< Position of SECATTR field.                                           */
72481   #define SPU_FEATURE_GRTC_CC_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_CC_SECATTR_Pos) /*!< Bit mask of SECATTR field.           */
72482   #define SPU_FEATURE_GRTC_CC_SECATTR_Min (0x0UL)    /*!< Min enumerator value of SECATTR field.                               */
72483   #define SPU_FEATURE_GRTC_CC_SECATTR_Max (0x1UL)    /*!< Max enumerator value of SECATTR field.                               */
72484   #define SPU_FEATURE_GRTC_CC_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                         */
72485   #define SPU_FEATURE_GRTC_CC_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                                 */
72486 
72487 /* LOCK @Bit 8 : LOCK feature */
72488   #define SPU_FEATURE_GRTC_CC_LOCK_Pos (8UL)         /*!< Position of LOCK field.                                              */
72489   #define SPU_FEATURE_GRTC_CC_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_CC_LOCK_Pos) /*!< Bit mask of LOCK field.                    */
72490   #define SPU_FEATURE_GRTC_CC_LOCK_Min (0x0UL)       /*!< Min enumerator value of LOCK field.                                  */
72491   #define SPU_FEATURE_GRTC_CC_LOCK_Max (0x1UL)       /*!< Max enumerator value of LOCK field.                                  */
72492   #define SPU_FEATURE_GRTC_CC_LOCK_Unlocked (0x0UL)  /*!< Feature permissions can be updated                                   */
72493   #define SPU_FEATURE_GRTC_CC_LOCK_Locked (0x1UL)    /*!< Feature permissions can not be changed until the next reset          */
72494 
72495 /* OWNERID @Bits 16..19 : Feature owner ID */
72496   #define SPU_FEATURE_GRTC_CC_OWNERID_Pos (16UL)     /*!< Position of OWNERID field.                                           */
72497   #define SPU_FEATURE_GRTC_CC_OWNERID_Msk (0xFUL << SPU_FEATURE_GRTC_CC_OWNERID_Pos) /*!< Bit mask of OWNERID field.           */
72498   #define SPU_FEATURE_GRTC_CC_OWNERID_Min (0x0UL)    /*!< Min value of OWNERID field.                                          */
72499   #define SPU_FEATURE_GRTC_CC_OWNERID_Max (0xFUL)    /*!< Max size of OWNERID field.                                           */
72500 
72501 
72502 /* SPU_FEATURE_GRTC_SYSCOUNTER: Configuration of features for SYSCOUNTERL/SYSCOUNTERH of GRTC */
72503   #define SPU_FEATURE_GRTC_SYSCOUNTER_ResetValue (0x00000000UL) /*!< Reset value of SYSCOUNTER register.                       */
72504 
72505 /* SECATTR @Bit 4 : SECATTR feature */
72506   #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                        */
72507   #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Pos) /*!< Bit mask of SECATTR
72508                                                                             field.*/
72509   #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                          */
72510   #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                          */
72511   #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                 */
72512   #define SPU_FEATURE_GRTC_SYSCOUNTER_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                         */
72513 
72514 /* LOCK @Bit 8 : LOCK feature */
72515   #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos (8UL) /*!< Position of LOCK field.                                              */
72516   #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Pos) /*!< Bit mask of LOCK field.    */
72517   #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                                */
72518   #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                                */
72519   #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                            */
72520   #define SPU_FEATURE_GRTC_SYSCOUNTER_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset     */
72521 
72522 /* OWNERID @Bits 16..19 : Feature owner ID */
72523   #define SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Pos (16UL) /*!< Position of OWNERID field.                                       */
72524   #define SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Msk (0xFUL << SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Pos) /*!< Bit mask of OWNERID
72525                                                                             field.*/
72526   #define SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field.                                     */
72527   #define SPU_FEATURE_GRTC_SYSCOUNTER_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field.                                      */
72528 
72529 
72530 /* SPU_FEATURE_GRTC_INTERRUPT: Configuration of features for interrupt n of GRTC */
72531   #define SPU_FEATURE_GRTC_INTERRUPT_MaxCount (7UL)  /*!< Max size of INTERRUPT[7] array.                                      */
72532   #define SPU_FEATURE_GRTC_INTERRUPT_MaxIndex (6UL)  /*!< Max index of INTERRUPT[7] array.                                     */
72533   #define SPU_FEATURE_GRTC_INTERRUPT_MinIndex (0UL)  /*!< Min index of INTERRUPT[7] array.                                     */
72534   #define SPU_FEATURE_GRTC_INTERRUPT_ResetValue (0x00000000UL) /*!< Reset value of INTERRUPT[7] register.                      */
72535 
72536 /* SECATTR @Bit 4 : SECATTR feature */
72537   #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                         */
72538   #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Msk (0x1UL << SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos) /*!< Bit mask of SECATTR
72539                                                                             field.*/
72540   #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                           */
72541   #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                           */
72542   #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage                  */
72543   #define SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                          */
72544 
72545 /* LOCK @Bit 8 : LOCK feature */
72546   #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos (8UL)  /*!< Position of LOCK field.                                              */
72547   #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Msk (0x1UL << SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos) /*!< Bit mask of LOCK field.      */
72548   #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                                 */
72549   #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                                 */
72550   #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                             */
72551   #define SPU_FEATURE_GRTC_INTERRUPT_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset      */
72552 
72553 /* OWNERID @Bits 16..19 : Feature owner ID */
72554   #define SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Pos (16UL) /*!< Position of OWNERID field.                                        */
72555   #define SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Msk (0xFUL << SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Pos) /*!< Bit mask of OWNERID
72556                                                                             field.*/
72557   #define SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field.                                      */
72558   #define SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field.                                       */
72559 
72560 
72561 
72562 /* ============================================= Struct SPU_FEATURE_BELLS_DOMAIN ============================================= */
72563 /**
72564   * @brief DOMAIN [SPU_FEATURE_BELLS_DOMAIN] (unspecified)
72565   */
72566 typedef struct {
72567   __IOM uint32_t  BELL[16];                          /*!< (@ 0x00000000) Configuration of features for bell pair [(o * 2) + 1:o
72568                                                                          * 2] of domain n*/
72569 } NRF_SPU_FEATURE_BELLS_DOMAIN_Type;                 /*!< Size = 64 (0x040)                                                    */
72570   #define SPU_FEATURE_BELLS_DOMAIN_MaxCount (16UL)   /*!< Size of DOMAIN[16] array.                                            */
72571   #define SPU_FEATURE_BELLS_DOMAIN_MaxIndex (15UL)   /*!< Max index of DOMAIN[16] array.                                       */
72572   #define SPU_FEATURE_BELLS_DOMAIN_MinIndex (0UL)    /*!< Min index of DOMAIN[16] array.                                       */
72573 
72574 /* SPU_FEATURE_BELLS_DOMAIN_BELL: Configuration of features for bell pair [(o * 2) + 1:o * 2] of domain n */
72575   #define SPU_FEATURE_BELLS_DOMAIN_BELL_MaxCount (16UL) /*!< Max size of BELL[16] array.                                       */
72576   #define SPU_FEATURE_BELLS_DOMAIN_BELL_MaxIndex (15UL) /*!< Max index of BELL[16] array.                                      */
72577   #define SPU_FEATURE_BELLS_DOMAIN_BELL_MinIndex (0UL) /*!< Min index of BELL[16] array.                                       */
72578   #define SPU_FEATURE_BELLS_DOMAIN_BELL_ResetValue (0x00000000UL) /*!< Reset value of BELL[16] register.                       */
72579 
72580 /* SECATTR @Bit 4 : SECATTR feature */
72581   #define SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Pos (4UL) /*!< Position of SECATTR field.                                      */
72582   #define SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Msk (0x1UL << SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Pos) /*!< Bit mask of
72583                                                                             SECATTR field.*/
72584   #define SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Min (0x0UL) /*!< Min enumerator value of SECATTR field.                        */
72585   #define SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Max (0x1UL) /*!< Max enumerator value of SECATTR field.                        */
72586   #define SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_NonSecure (0x0UL) /*!< Feature is available for non-secure usage               */
72587   #define SPU_FEATURE_BELLS_DOMAIN_BELL_SECATTR_Secure (0x1UL) /*!< Feature is reserved for secure usage                       */
72588 
72589 /* LOCK @Bit 8 : LOCK feature */
72590   #define SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Pos (8UL) /*!< Position of LOCK field.                                            */
72591   #define SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Msk (0x1UL << SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Pos) /*!< Bit mask of LOCK field.*/
72592   #define SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Min (0x0UL) /*!< Min enumerator value of LOCK field.                              */
72593   #define SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Max (0x1UL) /*!< Max enumerator value of LOCK field.                              */
72594   #define SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Unlocked (0x0UL) /*!< Feature permissions can be updated                          */
72595   #define SPU_FEATURE_BELLS_DOMAIN_BELL_LOCK_Locked (0x1UL) /*!< Feature permissions can not be changed until the next reset   */
72596 
72597 /* OWNERID @Bits 16..19 : Feature owner ID */
72598   #define SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Pos (16UL) /*!< Position of OWNERID field.                                     */
72599   #define SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Msk (0xFUL << SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Pos) /*!< Bit mask of
72600                                                                             OWNERID field.*/
72601   #define SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Min (0x0UL) /*!< Min value of OWNERID field.                                   */
72602   #define SPU_FEATURE_BELLS_DOMAIN_BELL_OWNERID_Max (0xFUL) /*!< Max size of OWNERID field.                                    */
72603 
72604 
72605 
72606 /* ================================================ Struct SPU_FEATURE_BELLS ================================================= */
72607 /**
72608   * @brief BELLS [SPU_FEATURE_BELLS] (unspecified)
72609   */
72610 typedef struct {
72611   __IOM NRF_SPU_FEATURE_BELLS_DOMAIN_Type DOMAIN[16]; /*!< (@ 0x00000000) (unspecified)                                        */
72612 } NRF_SPU_FEATURE_BELLS_Type;                        /*!< Size = 1024 (0x400)                                                  */
72613 
72614 
72615 /* =================================================== Struct SPU_FEATURE ==================================================== */
72616 /**
72617   * @brief FEATURE [SPU_FEATURE] (unspecified)
72618   */
72619 typedef union {
72620   struct {
72621     __IOM NRF_SPU_FEATURE_IPCT_Type IPCT;            /*!< (@ 0x00000000) (unspecified)                                         */
72622     __IOM NRF_SPU_FEATURE_DPPIC_Type DPPIC;          /*!< (@ 0x00000080) (unspecified)                                         */
72623     __IOM NRF_SPU_FEATURE_GPIOTE_Type GPIOTE[1];     /*!< (@ 0x00000100) (unspecified)                                         */
72624     __IM uint32_t RESERVED[48];
72625     #if defined(_GNUC_)
72626       #pragma GCC diagnostic push
72627       #pragma GCC diagnostic ignored "-Wpedantic"
72628     #endif
72629     union {
72630       __IOM NRF_SPU_FEATURE_GPIO_Type GPIO[10];      /*!< (@ 0x00000200) (unspecified)                                         */
72631       __IOM NRF_SPU_FEATURE_GRTC_Type GRTC;          /*!< (@ 0x00000200) (unspecified)                                         */
72632       __IM uint32_t RESERVED1[320];
72633     };
72634     #if defined(_GNUC_)
72635       #pragma GCC diagnostic pop
72636     #endif
72637   };
72638   __IOM NRF_SPU_FEATURE_BELLS_Type BELLS;            /*!< (@ 0x00000000) (unspecified)                                         */
72639   __IM  uint32_t  RESERVED2[448];
72640 } NRF_SPU_FEATURE_Type;                              /*!< Size = 1792 (0x700)                                                  */
72641 
72642 /* ======================================================= Struct SPU ======================================================== */
72643 /**
72644   * @brief System protection unit
72645   */
72646   typedef struct {                                   /*!< SPU Structure                                                        */
72647     __IM uint32_t RESERVED[64];
72648     __IOM uint32_t EVENTS_PERIPHACCERR;              /*!< (@ 0x00000100) A security violation has been detected on one or
72649                                                                          several peripherals*/
72650     __IM uint32_t RESERVED1[127];
72651     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
72652     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
72653     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
72654     __IM uint32_t RESERVED2[62];
72655     __IOM NRF_SPU_PERIPHACCERR_Type PERIPHACCERR;    /*!< (@ 0x00000404) (unspecified)                                         */
72656     __IM uint32_t RESERVED3[61];
72657     __IOM NRF_SPU_PERIPH_Type PERIPH[32];            /*!< (@ 0x00000500) (unspecified)                                         */
72658     __IM uint32_t RESERVED4[32];
72659     __IOM NRF_SPU_FEATURE_Type FEATURE;              /*!< (@ 0x00000600) (unspecified)                                         */
72660   } NRF_SPU_Type;                                    /*!< Size = 3328 (0xD00)                                                  */
72661 
72662 /* SPU_EVENTS_PERIPHACCERR: A security violation has been detected on one or several peripherals */
72663   #define SPU_EVENTS_PERIPHACCERR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_PERIPHACCERR register.                  */
72664 
72665 /* EVENTS_PERIPHACCERR @Bit 0 : A security violation has been detected on one or several peripherals */
72666   #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field.                    */
72667   #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit
72668                                                                             mask of EVENTS_PERIPHACCERR field.*/
72669   #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Min (0x0UL) /*!< Min enumerator value of EVENTS_PERIPHACCERR field.      */
72670   #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Max (0x1UL) /*!< Max enumerator value of EVENTS_PERIPHACCERR field.      */
72671   #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0x0UL) /*!< Event not generated                            */
72672   #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (0x1UL) /*!< Event generated                                   */
72673 
72674 
72675 /* SPU_INTEN: Enable or disable interrupt */
72676   #define SPU_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
72677 
72678 /* PERIPHACCERR @Bit 0 : Enable or disable interrupt for event PERIPHACCERR */
72679   #define SPU_INTEN_PERIPHACCERR_Pos (0UL)           /*!< Position of PERIPHACCERR field.                                      */
72680   #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field.                */
72681   #define SPU_INTEN_PERIPHACCERR_Min (0x0UL)         /*!< Min enumerator value of PERIPHACCERR field.                          */
72682   #define SPU_INTEN_PERIPHACCERR_Max (0x1UL)         /*!< Max enumerator value of PERIPHACCERR field.                          */
72683   #define SPU_INTEN_PERIPHACCERR_Disabled (0x0UL)    /*!< Disable                                                              */
72684   #define SPU_INTEN_PERIPHACCERR_Enabled (0x1UL)     /*!< Enable                                                               */
72685 
72686 
72687 /* SPU_INTENSET: Enable interrupt */
72688   #define SPU_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
72689 
72690 /* PERIPHACCERR @Bit 0 : Write '1' to enable interrupt for event PERIPHACCERR */
72691   #define SPU_INTENSET_PERIPHACCERR_Pos (0UL)        /*!< Position of PERIPHACCERR field.                                      */
72692   #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field.          */
72693   #define SPU_INTENSET_PERIPHACCERR_Min (0x0UL)      /*!< Min enumerator value of PERIPHACCERR field.                          */
72694   #define SPU_INTENSET_PERIPHACCERR_Max (0x1UL)      /*!< Max enumerator value of PERIPHACCERR field.                          */
72695   #define SPU_INTENSET_PERIPHACCERR_Set (0x1UL)      /*!< Enable                                                               */
72696   #define SPU_INTENSET_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
72697   #define SPU_INTENSET_PERIPHACCERR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
72698 
72699 
72700 /* SPU_INTENCLR: Disable interrupt */
72701   #define SPU_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
72702 
72703 /* PERIPHACCERR @Bit 0 : Write '1' to disable interrupt for event PERIPHACCERR */
72704   #define SPU_INTENCLR_PERIPHACCERR_Pos (0UL)        /*!< Position of PERIPHACCERR field.                                      */
72705   #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field.          */
72706   #define SPU_INTENCLR_PERIPHACCERR_Min (0x0UL)      /*!< Min enumerator value of PERIPHACCERR field.                          */
72707   #define SPU_INTENCLR_PERIPHACCERR_Max (0x1UL)      /*!< Max enumerator value of PERIPHACCERR field.                          */
72708   #define SPU_INTENCLR_PERIPHACCERR_Clear (0x1UL)    /*!< Disable                                                              */
72709   #define SPU_INTENCLR_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
72710   #define SPU_INTENCLR_PERIPHACCERR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
72711 
72712 
72713 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
72714 
72715 /* =========================================================================================================================== */
72716 /* ================                                            STM                                            ================ */
72717 /* =========================================================================================================================== */
72718 
72719 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
72720 /* ======================================================= Struct STM ======================================================== */
72721 /**
72722   * @brief System Trace Macrocell
72723   */
72724   typedef struct {                                   /*!< STM Structure                                                        */
72725     __IM uint32_t RESERVED[772];
72726     __IOM uint32_t DMACTLR;                          /*!< (@ 0x00000C10) Controls the DMA transfer request mechanism.          */
72727     __IM uint32_t RESERVED1[120];
72728     __IM uint32_t HEMASTR;                           /*!< (@ 0x00000DF4) Indicates the STPv2 master number of hardware event
72729                                                                          trace. This number is the master number presented in
72730                                                                          STPv2.*/
72731     __IM uint32_t HEFEAT1R;                          /*!< (@ 0x00000DF8) Indicates the features of the STM.                    */
72732     __IM uint32_t HEIDR;                             /*!< (@ 0x00000DFC) Indicates the features of hardware event tracing in the
72733                                                                          STM.*/
72734     __IM uint32_t RESERVED2[32];
72735     __IOM uint32_t TCSR;                             /*!< (@ 0x00000E80) Controls the STM settings.                            */
72736     __IM uint32_t RESERVED3[4];
72737     __IOM uint32_t AUXCR;                            /*!< (@ 0x00000E94) Used for implementation defined STM controls.         */
72738     __IM uint32_t RESERVED4[2];
72739     __IOM uint32_t SPFEAT1R;                         /*!< (@ 0x00000EA0) Indicates the features of the STM.                    */
72740     __IOM uint32_t SPFEAT2R;                         /*!< (@ 0x00000EA4) Indicates the features of the STM.                    */
72741     __IOM uint32_t SPFEAT3R;                         /*!< (@ 0x00000EA8) Indicates the features of the STM.                    */
72742     __IM uint32_t RESERVED5[15];
72743     __OM uint32_t ITTRIGGER;                         /*!< (@ 0x00000EE8) Integration Test for Cross-Trigger Outputs Register.  */
72744     __OM uint32_t ITATBDATA0;                        /*!< (@ 0x00000EEC) Controls the value of the ATDATAM output in integration
72745                                                                          mode.*/
72746     __OM uint32_t ITATBCTR2;                         /*!< (@ 0x00000EF0) Controls the value of the ATDATAM output in integration
72747                                                                          mode.*/
72748     __OM uint32_t ITATBID;                           /*!< (@ 0x00000EF4) Controls the value of the ATIDM output in integration
72749                                                                          mode.*/
72750     __OM uint32_t ITATBCTR0;                         /*!< (@ 0x00000EF8) Controls the value of the ATVALIDM, AFREADYM, and
72751                                                                          ATBYTESM outputs in integration mode.*/
72752     __IM uint32_t RESERVED6;
72753     __IOM uint32_t ITCTRL;                           /*!< (@ 0x00000F00) Used to enable topology detection. This register
72754                                                                          enables the component to switch from a functional mode,
72755                                                                          the default behavior, to integration mode where the
72756                                                                          inputs and outputs of the component can be directly
72757                                                                          controlled for integration testing and topology
72758                                                                          solving.*/
72759     __IM uint32_t RESERVED7[43];
72760     __IOM uint32_t LAR;                              /*!< (@ 0x00000FB0) This is used to enable write access to device
72761                                                                          registers.*/
72762     __IOM uint32_t LSR;                              /*!< (@ 0x00000FB4) This indicates the status of the lock control
72763                                                                          mechanism. This lock prevents accidental writes by code
72764                                                                          under debug. Accesses to the extended stimulus port
72765                                                                          registers are not affected by the lock mechanism. This
72766                                                                          register must always be present although there might
72767                                                                          not be any lock access control mechanism. The lock
72768                                                                          mechanism, where present and locked, must block write
72769                                                                          accesses to any control register, except the Lock
72770                                                                          Access Register. For most components this covers all
72771                                                                          registers except for the Lock Access Register.*/
72772     __IOM uint32_t AUTHSTATUS;                       /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the
72773                                                                          system*/
72774     __IM uint32_t RESERVED8[3];
72775     __IM uint32_t DEVID;                             /*!< (@ 0x00000FC8) Indicates the capabilities of the STM.                */
72776     __IM uint32_t DEVTYPE;                           /*!< (@ 0x00000FCC) Controls the single-shot comparator.                  */
72777     __IOM uint32_t PIDR4;                            /*!< (@ 0x00000FD0) Coresight peripheral identification registers.        */
72778     __IM uint32_t RESERVED9[3];
72779     __IOM uint32_t PIDR0;                            /*!< (@ 0x00000FE0) Coresight peripheral identification registers.        */
72780     __IOM uint32_t PIDR1;                            /*!< (@ 0x00000FE4) Coresight peripheral identification registers.        */
72781     __IOM uint32_t PIDR2;                            /*!< (@ 0x00000FE8) Coresight peripheral identification registers.        */
72782     __IOM uint32_t PIDR3;                            /*!< (@ 0x00000FEC) Coresight peripheral identification registers.        */
72783     __IOM uint32_t CIDR0;                            /*!< (@ 0x00000FF0) Coresight component identification registers.         */
72784     __IOM uint32_t CIDR1;                            /*!< (@ 0x00000FF4) Coresight component identification registers.         */
72785     __IOM uint32_t CIDR2;                            /*!< (@ 0x00000FF8) Coresight component identification registers.         */
72786     __IOM uint32_t CIDR3;                            /*!< (@ 0x00000FFC) Coresight component identification registers.         */
72787   } NRF_STM_Type;                                    /*!< Size = 4096 (0x1000)                                                 */
72788 
72789 /* STM_DMACTLR: Controls the DMA transfer request mechanism. */
72790   #define STM_DMACTLR_ResetValue (0x00000000UL)      /*!< Reset value of DMACTLR register.                                     */
72791 
72792 /* SENS @Bits 2..3 : Determines the sensitivity of the DMA request to the current buffer level in the STM */
72793   #define STM_DMACTLR_SENS_Pos (2UL)                 /*!< Position of SENS field.                                              */
72794   #define STM_DMACTLR_SENS_Msk (0x3UL << STM_DMACTLR_SENS_Pos) /*!< Bit mask of SENS field.                                    */
72795   #define STM_DMACTLR_SENS_Min (0x0UL)               /*!< Min enumerator value of SENS field.                                  */
72796   #define STM_DMACTLR_SENS_Max (0x3UL)               /*!< Max enumerator value of SENS field.                                  */
72797   #define STM_DMACTLR_SENS_LT25 (0x0UL)              /*!< Buffer is <25 percent full.                                          */
72798   #define STM_DMACTLR_SENS_LT50 (0x1UL)              /*!< Buffer is <50 percent full.                                          */
72799   #define STM_DMACTLR_SENS_LT75 (0x2UL)              /*!< Buffer is <75 percent full.                                          */
72800   #define STM_DMACTLR_SENS_LT100 (0x3UL)             /*!< Buffer is <100 percent full.                                         */
72801 
72802 
72803 /* STM_HEMASTR: Indicates the STPv2 master number of hardware event trace. This number is the master number presented in STPv2.
72804                  */
72805 
72806   #define STM_HEMASTR_ResetValue (0x00000000UL)      /*!< Reset value of HEMASTR register.                                     */
72807 
72808 /* MASTER @Bits 0..16 : The STPv2 master number that hardware event traces should be associated with. */
72809   #define STM_HEMASTR_MASTER_Pos (0UL)               /*!< Position of MASTER field.                                            */
72810   #define STM_HEMASTR_MASTER_Msk (0x1FFFFUL << STM_HEMASTR_MASTER_Pos) /*!< Bit mask of MASTER field.                          */
72811   #define STM_HEMASTR_MASTER_Min (0x0UL)             /*!< Min value of MASTER field.                                           */
72812   #define STM_HEMASTR_MASTER_Max (0xFFFFUL)          /*!< Max size of MASTER field.                                            */
72813 
72814 
72815 /* STM_HEFEAT1R: Indicates the features of the STM. */
72816   #define STM_HEFEAT1R_ResetValue (0x00000000UL)     /*!< Reset value of HEFEAT1R register.                                    */
72817 
72818 /* HETER @Bit 0 : STMHETER support */
72819   #define STM_HEFEAT1R_HETER_Pos (0UL)               /*!< Position of HETER field.                                             */
72820   #define STM_HEFEAT1R_HETER_Msk (0x1UL << STM_HEFEAT1R_HETER_Pos) /*!< Bit mask of HETER field.                               */
72821   #define STM_HEFEAT1R_HETER_Min (0x0UL)             /*!< Min enumerator value of HETER field.                                 */
72822   #define STM_HEFEAT1R_HETER_Max (0x1UL)             /*!< Max enumerator value of HETER field.                                 */
72823   #define STM_HEFEAT1R_HETER_NotImplemented (0x0UL)  /*!< The feature is not implemented.                                      */
72824   #define STM_HEFEAT1R_HETER_Implemented (0x1UL)     /*!< The feature is implemented.                                          */
72825 
72826 /* HEERR @Bit 2 : Hardware event error detection support */
72827   #define STM_HEFEAT1R_HEERR_Pos (2UL)               /*!< Position of HEERR field.                                             */
72828   #define STM_HEFEAT1R_HEERR_Msk (0x1UL << STM_HEFEAT1R_HEERR_Pos) /*!< Bit mask of HEERR field.                               */
72829   #define STM_HEFEAT1R_HEERR_Min (0x0UL)             /*!< Min enumerator value of HEERR field.                                 */
72830   #define STM_HEFEAT1R_HEERR_Max (0x1UL)             /*!< Max enumerator value of HEERR field.                                 */
72831   #define STM_HEFEAT1R_HEERR_NotImplemented (0x0UL)  /*!< The feature is not implemented.                                      */
72832   #define STM_HEFEAT1R_HEERR_Implemented (0x1UL)     /*!< The feature is implemented.                                          */
72833 
72834 /* HEMASTR @Bit 3 : STMHEMASTR support */
72835   #define STM_HEFEAT1R_HEMASTR_Pos (3UL)             /*!< Position of HEMASTR field.                                           */
72836   #define STM_HEFEAT1R_HEMASTR_Msk (0x1UL << STM_HEFEAT1R_HEMASTR_Pos) /*!< Bit mask of HEMASTR field.                         */
72837   #define STM_HEFEAT1R_HEMASTR_Min (0x0UL)           /*!< Min enumerator value of HEMASTR field.                               */
72838   #define STM_HEFEAT1R_HEMASTR_Max (0x1UL)           /*!< Max enumerator value of HEMASTR field.                               */
72839   #define STM_HEFEAT1R_HEMASTR_NotImplemented (0x0UL) /*!< The feature is not implemented.                                     */
72840   #define STM_HEFEAT1R_HEMASTR_Implemented (0x1UL)   /*!< The feature is implemented.                                          */
72841 
72842 /* NUMHE @Bits 15..23 : The number of hardware events supported by the STM */
72843   #define STM_HEFEAT1R_NUMHE_Pos (15UL)              /*!< Position of NUMHE field.                                             */
72844   #define STM_HEFEAT1R_NUMHE_Msk (0x1FFUL << STM_HEFEAT1R_NUMHE_Pos) /*!< Bit mask of NUMHE field.                             */
72845   #define STM_HEFEAT1R_NUMHE_Min (0x0UL)             /*!< Min value of NUMHE field.                                            */
72846   #define STM_HEFEAT1R_NUMHE_Max (0xFFUL)            /*!< Max size of NUMHE field.                                             */
72847 
72848 
72849 /* STM_HEIDR: Indicates the features of hardware event tracing in the STM. */
72850   #define STM_HEIDR_ResetValue (0x00000000UL)        /*!< Reset value of HEIDR register.                                       */
72851 
72852 /* CLASS @Bits 0..3 : The CLASS field identifies the programmers model */
72853   #define STM_HEIDR_CLASS_Pos (0UL)                  /*!< Position of CLASS field.                                             */
72854   #define STM_HEIDR_CLASS_Msk (0xFUL << STM_HEIDR_CLASS_Pos) /*!< Bit mask of CLASS field.                                     */
72855   #define STM_HEIDR_CLASS_Min (0x1UL)                /*!< Min enumerator value of CLASS field.                                 */
72856   #define STM_HEIDR_CLASS_Max (0x1UL)                /*!< Max enumerator value of CLASS field.                                 */
72857   #define STM_HEIDR_CLASS_HardwareEventControl (0x1UL) /*!< Hardware Event Control programmers model                           */
72858 
72859 /* CLASSREV @Bits 4..7 : The CLASSREV field identifies the revision of the programmers model */
72860   #define STM_HEIDR_CLASSREV_Pos (4UL)               /*!< Position of CLASSREV field.                                          */
72861   #define STM_HEIDR_CLASSREV_Msk (0xFUL << STM_HEIDR_CLASSREV_Pos) /*!< Bit mask of CLASSREV field.                            */
72862 
72863 /* VENDSPEC @Bits 8..11 : The VENDSPEC field identifies any vendor specific modifications or mappings */
72864   #define STM_HEIDR_VENDSPEC_Pos (8UL)               /*!< Position of VENDSPEC field.                                          */
72865   #define STM_HEIDR_VENDSPEC_Msk (0xFUL << STM_HEIDR_VENDSPEC_Pos) /*!< Bit mask of VENDSPEC field.                            */
72866 
72867 
72868 /* STM_TCSR: Controls the STM settings. */
72869   #define STM_TCSR_ResetValue (0x00000000UL)         /*!< Reset value of TCSR register.                                        */
72870 
72871 /* EN @Bit 0 : Global STM enable */
72872   #define STM_TCSR_EN_Pos (0UL)                      /*!< Position of EN field.                                                */
72873   #define STM_TCSR_EN_Msk (0x1UL << STM_TCSR_EN_Pos) /*!< Bit mask of EN field.                                                */
72874   #define STM_TCSR_EN_Min (0x0UL)                    /*!< Min enumerator value of EN field.                                    */
72875   #define STM_TCSR_EN_Max (0x1UL)                    /*!< Max enumerator value of EN field.                                    */
72876   #define STM_TCSR_EN_Disabled (0x0UL)               /*!< The STM is disabled.                                                 */
72877   #define STM_TCSR_EN_Enabled (0x1UL)                /*!< The STM is enabled.                                                  */
72878 
72879 /* TSEN @Bit 1 : Enable or disable timestamp bundling. */
72880   #define STM_TCSR_TSEN_Pos (1UL)                    /*!< Position of TSEN field.                                              */
72881   #define STM_TCSR_TSEN_Msk (0x1UL << STM_TCSR_TSEN_Pos) /*!< Bit mask of TSEN field.                                          */
72882   #define STM_TCSR_TSEN_Min (0x0UL)                  /*!< Min enumerator value of TSEN field.                                  */
72883   #define STM_TCSR_TSEN_Max (0x1UL)                  /*!< Max enumerator value of TSEN field.                                  */
72884   #define STM_TCSR_TSEN_Disabled (0x0UL)             /*!< Time stamps are disabled. Requests for timestamp generation are
72885                                                           ignored, and stimulus port writes selecting timestamping are treated
72886                                                           as if it were not selected.*/
72887   #define STM_TCSR_TSEN_Enabled (0x1UL)              /*!< Time stamps are enabled. If stimulus writes select timestamping, a
72888                                                           timestamp is output according to STPv2.*/
72889 
72890 /* SYNCEN @Bit 2 : STMSYNCR is implemented so this value is Read As One. */
72891   #define STM_TCSR_SYNCEN_Pos (2UL)                  /*!< Position of SYNCEN field.                                            */
72892   #define STM_TCSR_SYNCEN_Msk (0x1UL << STM_TCSR_SYNCEN_Pos) /*!< Bit mask of SYNCEN field.                                    */
72893   #define STM_TCSR_SYNCEN_Min (0x0UL)                /*!< Min enumerator value of SYNCEN field.                                */
72894   #define STM_TCSR_SYNCEN_Max (0x1UL)                /*!< Max enumerator value of SYNCEN field.                                */
72895   #define STM_TCSR_SYNCEN_Disabled (0x0UL)           /*!< The STM Sync feature is disabled.                                    */
72896   #define STM_TCSR_SYNCEN_Enabled (0x1UL)            /*!< The STM Sync feature is enabled.                                     */
72897 
72898 /* COMPEN @Bit 5 : Compression Enable for Stimulus Ports. */
72899   #define STM_TCSR_COMPEN_Pos (5UL)                  /*!< Position of COMPEN field.                                            */
72900   #define STM_TCSR_COMPEN_Msk (0x1UL << STM_TCSR_COMPEN_Pos) /*!< Bit mask of COMPEN field.                                    */
72901   #define STM_TCSR_COMPEN_Min (0x0UL)                /*!< Min enumerator value of COMPEN field.                                */
72902   #define STM_TCSR_COMPEN_Max (0x1UL)                /*!< Max enumerator value of COMPEN field.                                */
72903   #define STM_TCSR_COMPEN_Disabled (0x0UL)           /*!< Compression disabled, data transfers are transmitted at the size of
72904                                                           the transaction.*/
72905   #define STM_TCSR_COMPEN_Enabled (0x1UL)            /*!< Compression enabled, data transfers are compressed to save bandwidth.*/
72906 
72907 /* TRACEID @Bits 16..22 : ATB Trace ID. Setting this value to all zeroes might result in Unpredictable tracing. */
72908   #define STM_TCSR_TRACEID_Pos (16UL)                /*!< Position of TRACEID field.                                           */
72909   #define STM_TCSR_TRACEID_Msk (0x7FUL << STM_TCSR_TRACEID_Pos) /*!< Bit mask of TRACEID field.                                */
72910   #define STM_TCSR_TRACEID_Min (0x7FUL)              /*!< Min value of TRACEID field.                                          */
72911   #define STM_TCSR_TRACEID_Max (0x7FUL)              /*!< Max size of TRACEID field.                                           */
72912 
72913 /* BUSY @Bit 23 : STM is busy, for example the STM trace FIFO is not empty. */
72914   #define STM_TCSR_BUSY_Pos (23UL)                   /*!< Position of BUSY field.                                              */
72915   #define STM_TCSR_BUSY_Msk (0x1UL << STM_TCSR_BUSY_Pos) /*!< Bit mask of BUSY field.                                          */
72916   #define STM_TCSR_BUSY_Min (0x0UL)                  /*!< Min enumerator value of BUSY field.                                  */
72917   #define STM_TCSR_BUSY_Max (0x1UL)                  /*!< Max enumerator value of BUSY field.                                  */
72918   #define STM_TCSR_BUSY_Ready (0x0UL)                /*!< STM is not busy.                                                     */
72919   #define STM_TCSR_BUSY_Busy (0x1UL)                 /*!< STM is busy.                                                         */
72920 
72921 
72922 /* STM_AUXCR: Used for implementation defined STM controls. */
72923   #define STM_AUXCR_ResetValue (0x00000000UL)        /*!< Reset value of AUXCR register.                                       */
72924 
72925 /* FIFOAF @Bit 0 : FIFO Auto-flush. */
72926   #define STM_AUXCR_FIFOAF_Pos (0UL)                 /*!< Position of FIFOAF field.                                            */
72927   #define STM_AUXCR_FIFOAF_Msk (0x1UL << STM_AUXCR_FIFOAF_Pos) /*!< Bit mask of FIFOAF field.                                  */
72928   #define STM_AUXCR_FIFOAF_Min (0x0UL)               /*!< Min enumerator value of FIFOAF field.                                */
72929   #define STM_AUXCR_FIFOAF_Max (0x1UL)               /*!< Max enumerator value of FIFOAF field.                                */
72930   #define STM_AUXCR_FIFOAF_Disabled (0x0UL)          /*!< Auto-flush is disabled.                                              */
72931   #define STM_AUXCR_FIFOAF_Enabled (0x1UL)           /*!< Auto-flush is enabled. The STM automatically drains all data it has
72932                                                           even if the ATB interface is not fully utilized.*/
72933 
72934 /* ASYNCPE @Bit 1 : Is ASYNC priority higher than trace? */
72935   #define STM_AUXCR_ASYNCPE_Pos (1UL)                /*!< Position of ASYNCPE field.                                           */
72936   #define STM_AUXCR_ASYNCPE_Msk (0x1UL << STM_AUXCR_ASYNCPE_Pos) /*!< Bit mask of ASYNCPE field.                               */
72937   #define STM_AUXCR_ASYNCPE_Min (0x0UL)              /*!< Min enumerator value of ASYNCPE field.                               */
72938   #define STM_AUXCR_ASYNCPE_Max (0x1UL)              /*!< Max enumerator value of ASYNCPE field.                               */
72939   #define STM_AUXCR_ASYNCPE_Lower (0x0UL)            /*!< ASYNC priority is always lower than trace.                           */
72940   #define STM_AUXCR_ASYNCPE_Escalate (0x1UL)         /*!< ASYNC priority escalates on second synchronization request.          */
72941 
72942 /* PRIORINVDIS @Bit 2 : Controls arbitration between AXI and HW during flush. */
72943   #define STM_AUXCR_PRIORINVDIS_Pos (2UL)            /*!< Position of PRIORINVDIS field.                                       */
72944   #define STM_AUXCR_PRIORINVDIS_Msk (0x1UL << STM_AUXCR_PRIORINVDIS_Pos) /*!< Bit mask of PRIORINVDIS field.                   */
72945   #define STM_AUXCR_PRIORINVDIS_Min (0x0UL)          /*!< Min enumerator value of PRIORINVDIS field.                           */
72946   #define STM_AUXCR_PRIORINVDIS_Max (0x1UL)          /*!< Max enumerator value of PRIORINVDIS field.                           */
72947   #define STM_AUXCR_PRIORINVDIS_Enabled (0x0UL)      /*!< Priority inversion, when AXI flush is finished, HW gets priority until
72948                                                           HW flush is done.*/
72949   #define STM_AUXCR_PRIORINVDIS_Disabled (0x1UL)     /*!< Priority inversion disabled, AXI always has priority over HW.        */
72950 
72951 /* CLKON @Bit 3 : Provides override control for architectural clock gate enable. */
72952   #define STM_AUXCR_CLKON_Pos (3UL)                  /*!< Position of CLKON field.                                             */
72953   #define STM_AUXCR_CLKON_Msk (0x1UL << STM_AUXCR_CLKON_Pos) /*!< Bit mask of CLKON field.                                     */
72954   #define STM_AUXCR_CLKON_Min (0x0UL)                /*!< Min enumerator value of CLKON field.                                 */
72955   #define STM_AUXCR_CLKON_Max (0x1UL)                /*!< Max enumerator value of CLKON field.                                 */
72956   #define STM_AUXCR_CLKON_Disabled (0x0UL)           /*!< No override, clock gate is controlled by the state of STM.           */
72957   #define STM_AUXCR_CLKON_Enabled (0x1UL)            /*!< Override, clock is enabled.                                          */
72958 
72959 /* AFREADYHIGH @Bit 4 : Provides override control for the AFREADY output */
72960   #define STM_AUXCR_AFREADYHIGH_Pos (4UL)            /*!< Position of AFREADYHIGH field.                                       */
72961   #define STM_AUXCR_AFREADYHIGH_Msk (0x1UL << STM_AUXCR_AFREADYHIGH_Pos) /*!< Bit mask of AFREADYHIGH field.                   */
72962   #define STM_AUXCR_AFREADYHIGH_Min (0x0UL)          /*!< Min enumerator value of AFREADYHIGH field.                           */
72963   #define STM_AUXCR_AFREADYHIGH_Max (0x1UL)          /*!< Max enumerator value of AFREADYHIGH field.                           */
72964   #define STM_AUXCR_AFREADYHIGH_Disabled (0x0UL)     /*!< No override, AFREADY is controlled by the state of STM.              */
72965   #define STM_AUXCR_AFREADYHIGH_Enabled (0x1UL)      /*!< Override, AFREADY is driven HIGH.                                    */
72966 
72967 
72968 /* STM_SPFEAT1R: Indicates the features of the STM. */
72969   #define STM_SPFEAT1R_ResetValue (0x00000000UL)     /*!< Reset value of SPFEAT1R register.                                    */
72970 
72971 /* PROT @Bits 0..3 : Indicates the implemented STM protocol. */
72972   #define STM_SPFEAT1R_PROT_Pos (0UL)                /*!< Position of PROT field.                                              */
72973   #define STM_SPFEAT1R_PROT_Msk (0xFUL << STM_SPFEAT1R_PROT_Pos) /*!< Bit mask of PROT field.                                  */
72974   #define STM_SPFEAT1R_PROT_Min (0x1UL)              /*!< Min enumerator value of PROT field.                                  */
72975   #define STM_SPFEAT1R_PROT_Max (0x1UL)              /*!< Max enumerator value of PROT field.                                  */
72976   #define STM_SPFEAT1R_PROT_STPV2 (0x1UL)            /*!< STM implements the STPV2 protocol.                                   */
72977 
72978 /* TS @Bits 4..5 : Timestamp support. */
72979   #define STM_SPFEAT1R_TS_Pos (4UL)                  /*!< Position of TS field.                                                */
72980   #define STM_SPFEAT1R_TS_Msk (0x3UL << STM_SPFEAT1R_TS_Pos) /*!< Bit mask of TS field.                                        */
72981   #define STM_SPFEAT1R_TS_Min (0x1UL)                /*!< Min enumerator value of TS field.                                    */
72982   #define STM_SPFEAT1R_TS_Max (0x1UL)                /*!< Max enumerator value of TS field.                                    */
72983   #define STM_SPFEAT1R_TS_Absolute (0x1UL)           /*!< Absolute timestamps implemented.                                     */
72984 
72985 /* TSFREQ @Bit 6 : Timestamp frequency indication configuration. */
72986   #define STM_SPFEAT1R_TSFREQ_Pos (6UL)              /*!< Position of TSFREQ field.                                            */
72987   #define STM_SPFEAT1R_TSFREQ_Msk (0x1UL << STM_SPFEAT1R_TSFREQ_Pos) /*!< Bit mask of TSFREQ field.                            */
72988   #define STM_SPFEAT1R_TSFREQ_Min (0x0UL)            /*!< Min enumerator value of TSFREQ field.                                */
72989   #define STM_SPFEAT1R_TSFREQ_Max (0x1UL)            /*!< Max enumerator value of TSFREQ field.                                */
72990   #define STM_SPFEAT1R_TSFREQ_NotImplemented (0x0UL) /*!< STMTSFREQR is read-only.                                             */
72991   #define STM_SPFEAT1R_TSFREQ_Implemented (0x1UL)    /*!< STMTSFREQR is read-write.                                            */
72992 
72993 /* FORCETS @Bit 7 : Timestamp force configuration. */
72994   #define STM_SPFEAT1R_FORCETS_Pos (7UL)             /*!< Position of FORCETS field.                                           */
72995   #define STM_SPFEAT1R_FORCETS_Msk (0x1UL << STM_SPFEAT1R_FORCETS_Pos) /*!< Bit mask of FORCETS field.                         */
72996   #define STM_SPFEAT1R_FORCETS_Min (0x0UL)           /*!< Min enumerator value of FORCETS field.                               */
72997   #define STM_SPFEAT1R_FORCETS_Max (0x1UL)           /*!< Max enumerator value of FORCETS field.                               */
72998   #define STM_SPFEAT1R_FORCETS_NotImplemented (0x0UL) /*!< STMTSSTIMR bit 0 is read-only.                                      */
72999   #define STM_SPFEAT1R_FORCETS_Implemented (0x1UL)   /*!< STMTSSTIMR bit 0 is read-write.                                      */
73000 
73001 /* TRACEBUS @Bits 10..13 : Trace bus support. */
73002   #define STM_SPFEAT1R_TRACEBUS_Pos (10UL)           /*!< Position of TRACEBUS field.                                          */
73003   #define STM_SPFEAT1R_TRACEBUS_Msk (0xFUL << STM_SPFEAT1R_TRACEBUS_Pos) /*!< Bit mask of TRACEBUS field.                      */
73004 
73005 /* TRIGCTL @Bits 14..15 : Trigger control support. */
73006   #define STM_SPFEAT1R_TRIGCTL_Pos (14UL)            /*!< Position of TRIGCTL field.                                           */
73007   #define STM_SPFEAT1R_TRIGCTL_Msk (0x3UL << STM_SPFEAT1R_TRIGCTL_Pos) /*!< Bit mask of TRIGCTL field.                         */
73008 
73009 /* TSPRESCALE @Bits 16..17 : Timestamp prescale support */
73010   #define STM_SPFEAT1R_TSPRESCALE_Pos (16UL)         /*!< Position of TSPRESCALE field.                                        */
73011   #define STM_SPFEAT1R_TSPRESCALE_Msk (0x3UL << STM_SPFEAT1R_TSPRESCALE_Pos) /*!< Bit mask of TSPRESCALE field.                */
73012   #define STM_SPFEAT1R_TSPRESCALE_Min (0x0UL)        /*!< Min enumerator value of TSPRESCALE field.                            */
73013   #define STM_SPFEAT1R_TSPRESCALE_Max (0x1UL)        /*!< Max enumerator value of TSPRESCALE field.                            */
73014   #define STM_SPFEAT1R_TSPRESCALE_NotImplemented (0x0UL) /*!< Timestamp prescale is not implemented.                           */
73015   #define STM_SPFEAT1R_TSPRESCALE_Implemented (0x1UL) /*!< Timestamp prescale is implemented.                                  */
73016 
73017 /* HWTEN @Bits 18..19 : STMTCSR.HWTEN support */
73018   #define STM_SPFEAT1R_HWTEN_Pos (18UL)              /*!< Position of HWTEN field.                                             */
73019   #define STM_SPFEAT1R_HWTEN_Msk (0x3UL << STM_SPFEAT1R_HWTEN_Pos) /*!< Bit mask of HWTEN field.                               */
73020   #define STM_SPFEAT1R_HWTEN_Min (0x1UL)             /*!< Min enumerator value of HWTEN field.                                 */
73021   #define STM_SPFEAT1R_HWTEN_Max (0x1UL)             /*!< Max enumerator value of HWTEN field.                                 */
73022   #define STM_SPFEAT1R_HWTEN_NotImplemented (0x1UL)  /*!< STMTCSR.HWTEN is not implemented                                     */
73023 
73024 /* SYNCEN @Bits 20..21 : STMTCSR.SYNCEN support */
73025   #define STM_SPFEAT1R_SYNCEN_Pos (20UL)             /*!< Position of SYNCEN field.                                            */
73026   #define STM_SPFEAT1R_SYNCEN_Msk (0x3UL << STM_SPFEAT1R_SYNCEN_Pos) /*!< Bit mask of SYNCEN field.                            */
73027   #define STM_SPFEAT1R_SYNCEN_Min (0x2UL)            /*!< Min enumerator value of SYNCEN field.                                */
73028   #define STM_SPFEAT1R_SYNCEN_Max (0x2UL)            /*!< Max enumerator value of SYNCEN field.                                */
73029   #define STM_SPFEAT1R_SYNCEN_ReadAsOne (0x2UL)      /*!< STMTCSR.SYNCEN implemented but always reads as b1                    */
73030 
73031 /* SWOEN @Bits 22..23 : STMTCSR.SWOEN support */
73032   #define STM_SPFEAT1R_SWOEN_Pos (22UL)              /*!< Position of SWOEN field.                                             */
73033   #define STM_SPFEAT1R_SWOEN_Msk (0x3UL << STM_SPFEAT1R_SWOEN_Pos) /*!< Bit mask of SWOEN field.                               */
73034   #define STM_SPFEAT1R_SWOEN_Min (0x1UL)             /*!< Min enumerator value of SWOEN field.                                 */
73035   #define STM_SPFEAT1R_SWOEN_Max (0x1UL)             /*!< Max enumerator value of SWOEN field.                                 */
73036   #define STM_SPFEAT1R_SWOEN_NotImplemented (0x1UL)  /*!< STMTCSR.SWOEN not implemented                                        */
73037 
73038 
73039 /* STM_SPFEAT2R: Indicates the features of the STM. */
73040   #define STM_SPFEAT2R_ResetValue (0x00000000UL)     /*!< Reset value of SPFEAT2R register.                                    */
73041 
73042 /* SPTER @Bits 0..1 : STMSPTER support. */
73043   #define STM_SPFEAT2R_SPTER_Pos (0UL)               /*!< Position of SPTER field.                                             */
73044   #define STM_SPFEAT2R_SPTER_Msk (0x3UL << STM_SPFEAT2R_SPTER_Pos) /*!< Bit mask of SPTER field.                               */
73045   #define STM_SPFEAT2R_SPTER_Min (0x2UL)             /*!< Min enumerator value of SPTER field.                                 */
73046   #define STM_SPFEAT2R_SPTER_Max (0x2UL)             /*!< Max enumerator value of SPTER field.                                 */
73047   #define STM_SPFEAT2R_SPTER_Implemented (0x2UL)     /*!< STMSPTER is implemented.                                             */
73048 
73049 /* SPER @Bit 2 : STMSPER presence. */
73050   #define STM_SPFEAT2R_SPER_Pos (2UL)                /*!< Position of SPER field.                                              */
73051   #define STM_SPFEAT2R_SPER_Msk (0x1UL << STM_SPFEAT2R_SPER_Pos) /*!< Bit mask of SPER field.                                  */
73052   #define STM_SPFEAT2R_SPER_Min (0x0UL)              /*!< Min enumerator value of SPER field.                                  */
73053   #define STM_SPFEAT2R_SPER_Max (0x1UL)              /*!< Max enumerator value of SPER field.                                  */
73054   #define STM_SPFEAT2R_SPER_Implemented (0x0UL)      /*!< STMSPER is implemented.                                              */
73055   #define STM_SPFEAT2R_SPER_NotImplemented (0x1UL)   /*!< STMSPER is not implemented.                                          */
73056 
73057 /* SPCOMP @Bits 4..5 : Data compression on stimulus ports support. */
73058   #define STM_SPFEAT2R_SPCOMP_Pos (4UL)              /*!< Position of SPCOMP field.                                            */
73059   #define STM_SPFEAT2R_SPCOMP_Msk (0x3UL << STM_SPFEAT2R_SPCOMP_Pos) /*!< Bit mask of SPCOMP field.                            */
73060   #define STM_SPFEAT2R_SPCOMP_Min (0x3UL)            /*!< Min enumerator value of SPCOMP field.                                */
73061   #define STM_SPFEAT2R_SPCOMP_Max (0x3UL)            /*!< Max enumerator value of SPCOMP field.                                */
73062   #define STM_SPFEAT2R_SPCOMP_Programmable (0x3UL)   /*!< Data compression support is programmable. STMTCSR.COMPEN is
73063                                                           implemented.*/
73064 
73065 /* SPOVERRIDE @Bit 6 : Timestamp force configuration. */
73066   #define STM_SPFEAT2R_SPOVERRIDE_Pos (6UL)          /*!< Position of SPOVERRIDE field.                                        */
73067   #define STM_SPFEAT2R_SPOVERRIDE_Msk (0x1UL << STM_SPFEAT2R_SPOVERRIDE_Pos) /*!< Bit mask of SPOVERRIDE field.                */
73068   #define STM_SPFEAT2R_SPOVERRIDE_Min (0x0UL)        /*!< Min enumerator value of SPOVERRIDE field.                            */
73069   #define STM_SPFEAT2R_SPOVERRIDE_Max (0x1UL)        /*!< Max enumerator value of SPOVERRIDE field.                            */
73070   #define STM_SPFEAT2R_SPOVERRIDE_NotImplemented (0x0UL) /*!< STMSPOVERRIDER and STMSPMOVERRIDER is not implemented.           */
73071   #define STM_SPFEAT2R_SPOVERRIDE_Implemented (0x1UL) /*!< STMSPOVERRIDER and STMSPMOVERRIDER is implemented.                  */
73072 
73073 /* PRIVMASK @Bits 7..8 : STMPRIVMASKR support. */
73074   #define STM_SPFEAT2R_PRIVMASK_Pos (7UL)            /*!< Position of PRIVMASK field.                                          */
73075   #define STM_SPFEAT2R_PRIVMASK_Msk (0x3UL << STM_SPFEAT2R_PRIVMASK_Pos) /*!< Bit mask of PRIVMASK field.                      */
73076   #define STM_SPFEAT2R_PRIVMASK_Min (0x1UL)          /*!< Min enumerator value of PRIVMASK field.                              */
73077   #define STM_SPFEAT2R_PRIVMASK_Max (0x1UL)          /*!< Max enumerator value of PRIVMASK field.                              */
73078   #define STM_SPFEAT2R_PRIVMASK_NotImplemented (0x1UL) /*!< STMPRIVMASKR is not implemented.                                   */
73079 
73080 /* SPTRTYPE @Bits 9..10 : Stimulus port transaction type support. */
73081   #define STM_SPFEAT2R_SPTRTYPE_Pos (9UL)            /*!< Position of SPTRTYPE field.                                          */
73082   #define STM_SPFEAT2R_SPTRTYPE_Msk (0x3UL << STM_SPFEAT2R_SPTRTYPE_Pos) /*!< Bit mask of SPTRTYPE field.                      */
73083   #define STM_SPFEAT2R_SPTRTYPE_Min (0x2UL)          /*!< Min enumerator value of SPTRTYPE field.                              */
73084   #define STM_SPFEAT2R_SPTRTYPE_Max (0x2UL)          /*!< Max enumerator value of SPTRTYPE field.                              */
73085   #define STM_SPFEAT2R_SPTRTYPE_InvariantAndGuaranteed (0x2UL) /*!< Both invariant timing and guaranteed transactions are
73086                                                                     supported.*/
73087 
73088 /* DSIZE @Bits 12..15 : Fundamental data size. */
73089   #define STM_SPFEAT2R_DSIZE_Pos (12UL)              /*!< Position of DSIZE field.                                             */
73090   #define STM_SPFEAT2R_DSIZE_Msk (0xFUL << STM_SPFEAT2R_DSIZE_Pos) /*!< Bit mask of DSIZE field.                               */
73091   #define STM_SPFEAT2R_DSIZE_Min (0x0UL)             /*!< Min enumerator value of DSIZE field.                                 */
73092   #define STM_SPFEAT2R_DSIZE_Max (0x0UL)             /*!< Max enumerator value of DSIZE field.                                 */
73093   #define STM_SPFEAT2R_DSIZE_Bits32 (0x0UL)          /*!< 32-bit data.                                                         */
73094 
73095 /* SPTYPE @Bits 18..19 : Stimulus port type support */
73096   #define STM_SPFEAT2R_SPTYPE_Pos (18UL)             /*!< Position of SPTYPE field.                                            */
73097   #define STM_SPFEAT2R_SPTYPE_Msk (0x3UL << STM_SPFEAT2R_SPTYPE_Pos) /*!< Bit mask of SPTYPE field.                            */
73098   #define STM_SPFEAT2R_SPTYPE_Min (0x1UL)            /*!< Min enumerator value of SPTYPE field.                                */
73099   #define STM_SPFEAT2R_SPTYPE_Max (0x1UL)            /*!< Max enumerator value of SPTYPE field.                                */
73100   #define STM_SPFEAT2R_SPTYPE_OnlyExtended (0x1UL)   /*!< Only extended stimulus ports are implemented.                        */
73101 
73102 
73103 /* STM_SPFEAT3R: Indicates the features of the STM. */
73104   #define STM_SPFEAT3R_ResetValue (0x00000000UL)     /*!< Reset value of SPFEAT3R register.                                    */
73105 
73106 /* NUMMAST @Bits 0..6 : The number of stimulus ports masters implemented, minus 1. */
73107   #define STM_SPFEAT3R_NUMMAST_Pos (0UL)             /*!< Position of NUMMAST field.                                           */
73108   #define STM_SPFEAT3R_NUMMAST_Msk (0x7FUL << STM_SPFEAT3R_NUMMAST_Pos) /*!< Bit mask of NUMMAST field.                        */
73109   #define STM_SPFEAT3R_NUMMAST_Min (0x3FUL)          /*!< Min enumerator value of NUMMAST field.                               */
73110   #define STM_SPFEAT3R_NUMMAST_Max (0x3FUL)          /*!< Max enumerator value of NUMMAST field.                               */
73111   #define STM_SPFEAT3R_NUMMAST_Masters128 (0x3FUL)   /*!< Example: 128 masters implemented.                                    */
73112 
73113 
73114 /* STM_ITTRIGGER: Integration Test for Cross-Trigger Outputs Register. */
73115   #define STM_ITTRIGGER_ResetValue (0x00000000UL)    /*!< Reset value of ITTRIGGER register.                                   */
73116 
73117 /* TRIGOUTSPTE_W @Bit 0 : Sets the value of the TRIGOUTSPTE output in integration mode. */
73118   #define STM_ITTRIGGER_TRIGOUTSPTE_W_Pos (0UL)      /*!< Position of TRIGOUTSPTE_W field.                                     */
73119   #define STM_ITTRIGGER_TRIGOUTSPTE_W_Msk (0x1UL << STM_ITTRIGGER_TRIGOUTSPTE_W_Pos) /*!< Bit mask of TRIGOUTSPTE_W field.     */
73120   #define STM_ITTRIGGER_TRIGOUTSPTE_W_Min (0x0UL)    /*!< Min enumerator value of TRIGOUTSPTE_W field.                         */
73121   #define STM_ITTRIGGER_TRIGOUTSPTE_W_Max (0x1UL)    /*!< Max enumerator value of TRIGOUTSPTE_W field.                         */
73122   #define STM_ITTRIGGER_TRIGOUTSPTE_W_Low (0x0UL)    /*!< Drive logic 0 on output.                                             */
73123   #define STM_ITTRIGGER_TRIGOUTSPTE_W_High (0x1UL)   /*!< Drive logic 1 on output.                                             */
73124 
73125 /* TRIGOUTSW_W @Bit 1 : Sets the value of the TRIGOUTSW output in integration mode. */
73126   #define STM_ITTRIGGER_TRIGOUTSW_W_Pos (1UL)        /*!< Position of TRIGOUTSW_W field.                                       */
73127   #define STM_ITTRIGGER_TRIGOUTSW_W_Msk (0x1UL << STM_ITTRIGGER_TRIGOUTSW_W_Pos) /*!< Bit mask of TRIGOUTSW_W field.           */
73128   #define STM_ITTRIGGER_TRIGOUTSW_W_Min (0x0UL)      /*!< Min enumerator value of TRIGOUTSW_W field.                           */
73129   #define STM_ITTRIGGER_TRIGOUTSW_W_Max (0x1UL)      /*!< Max enumerator value of TRIGOUTSW_W field.                           */
73130   #define STM_ITTRIGGER_TRIGOUTSW_W_Low (0x0UL)      /*!< Drive logic 0 on output.                                             */
73131   #define STM_ITTRIGGER_TRIGOUTSW_W_High (0x1UL)     /*!< Drive logic 1 on output.                                             */
73132 
73133 /* TRIGOUTHETE_W @Bit 2 : Sets the value of the TRIGOUTHETE output in integration mode. */
73134   #define STM_ITTRIGGER_TRIGOUTHETE_W_Pos (2UL)      /*!< Position of TRIGOUTHETE_W field.                                     */
73135   #define STM_ITTRIGGER_TRIGOUTHETE_W_Msk (0x1UL << STM_ITTRIGGER_TRIGOUTHETE_W_Pos) /*!< Bit mask of TRIGOUTHETE_W field.     */
73136   #define STM_ITTRIGGER_TRIGOUTHETE_W_Min (0x0UL)    /*!< Min enumerator value of TRIGOUTHETE_W field.                         */
73137   #define STM_ITTRIGGER_TRIGOUTHETE_W_Max (0x1UL)    /*!< Max enumerator value of TRIGOUTHETE_W field.                         */
73138   #define STM_ITTRIGGER_TRIGOUTHETE_W_Low (0x0UL)    /*!< Drive logic 0 on output.                                             */
73139   #define STM_ITTRIGGER_TRIGOUTHETE_W_High (0x1UL)   /*!< Drive logic 1 on output.                                             */
73140 
73141 /* ASYNCOUT_W @Bit 3 : Sets the value of the ASYNCOUT output in integration mode. */
73142   #define STM_ITTRIGGER_ASYNCOUT_W_Pos (3UL)         /*!< Position of ASYNCOUT_W field.                                        */
73143   #define STM_ITTRIGGER_ASYNCOUT_W_Msk (0x1UL << STM_ITTRIGGER_ASYNCOUT_W_Pos) /*!< Bit mask of ASYNCOUT_W field.              */
73144   #define STM_ITTRIGGER_ASYNCOUT_W_Min (0x0UL)       /*!< Min enumerator value of ASYNCOUT_W field.                            */
73145   #define STM_ITTRIGGER_ASYNCOUT_W_Max (0x1UL)       /*!< Max enumerator value of ASYNCOUT_W field.                            */
73146   #define STM_ITTRIGGER_ASYNCOUT_W_Low (0x0UL)       /*!< Drive logic 0 on output.                                             */
73147   #define STM_ITTRIGGER_ASYNCOUT_W_High (0x1UL)      /*!< Drive logic 1 on output.                                             */
73148 
73149 
73150 /* STM_ITATBDATA0: Controls the value of the ATDATAM output in integration mode. */
73151   #define STM_ITATBDATA0_ResetValue (0x00000000UL)   /*!< Reset value of ITATBDATA0 register.                                  */
73152 
73153 /* ATDATAM0_W @Bit 0 : Sets the value of the ATDATAM[0]. */
73154   #define STM_ITATBDATA0_ATDATAM0_W_Pos (0UL)        /*!< Position of ATDATAM0_W field.                                        */
73155   #define STM_ITATBDATA0_ATDATAM0_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM0_W_Pos) /*!< Bit mask of ATDATAM0_W field.            */
73156   #define STM_ITATBDATA0_ATDATAM0_W_Min (0x0UL)      /*!< Min enumerator value of ATDATAM0_W field.                            */
73157   #define STM_ITATBDATA0_ATDATAM0_W_Max (0x1UL)      /*!< Max enumerator value of ATDATAM0_W field.                            */
73158   #define STM_ITATBDATA0_ATDATAM0_W_Low (0x0UL)      /*!< Drive logic 0 on output.                                             */
73159   #define STM_ITATBDATA0_ATDATAM0_W_High (0x1UL)     /*!< Drive logic 1 on output.                                             */
73160 
73161 /* ATDATAM7_W @Bit 1 : Sets the value of the ATDATAM[7] output. */
73162   #define STM_ITATBDATA0_ATDATAM7_W_Pos (1UL)        /*!< Position of ATDATAM7_W field.                                        */
73163   #define STM_ITATBDATA0_ATDATAM7_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM7_W_Pos) /*!< Bit mask of ATDATAM7_W field.            */
73164   #define STM_ITATBDATA0_ATDATAM7_W_Min (0x0UL)      /*!< Min enumerator value of ATDATAM7_W field.                            */
73165   #define STM_ITATBDATA0_ATDATAM7_W_Max (0x1UL)      /*!< Max enumerator value of ATDATAM7_W field.                            */
73166   #define STM_ITATBDATA0_ATDATAM7_W_Low (0x0UL)      /*!< Drive logic 0 on output.                                             */
73167   #define STM_ITATBDATA0_ATDATAM7_W_High (0x1UL)     /*!< Drive logic 1 on output.                                             */
73168 
73169 /* ATDATAM15_W @Bit 2 : Sets the value of the ATDATAM[15]. */
73170   #define STM_ITATBDATA0_ATDATAM15_W_Pos (2UL)       /*!< Position of ATDATAM15_W field.                                       */
73171   #define STM_ITATBDATA0_ATDATAM15_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM15_W_Pos) /*!< Bit mask of ATDATAM15_W field.         */
73172   #define STM_ITATBDATA0_ATDATAM15_W_Min (0x0UL)     /*!< Min enumerator value of ATDATAM15_W field.                           */
73173   #define STM_ITATBDATA0_ATDATAM15_W_Max (0x1UL)     /*!< Max enumerator value of ATDATAM15_W field.                           */
73174   #define STM_ITATBDATA0_ATDATAM15_W_Low (0x0UL)     /*!< Drive logic 0 on output.                                             */
73175   #define STM_ITATBDATA0_ATDATAM15_W_High (0x1UL)    /*!< Drive logic 1 on output.                                             */
73176 
73177 /* ATDATAM23_W @Bit 3 : Sets the value of the ATDATAM[23]. */
73178   #define STM_ITATBDATA0_ATDATAM23_W_Pos (3UL)       /*!< Position of ATDATAM23_W field.                                       */
73179   #define STM_ITATBDATA0_ATDATAM23_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM23_W_Pos) /*!< Bit mask of ATDATAM23_W field.         */
73180   #define STM_ITATBDATA0_ATDATAM23_W_Min (0x0UL)     /*!< Min enumerator value of ATDATAM23_W field.                           */
73181   #define STM_ITATBDATA0_ATDATAM23_W_Max (0x1UL)     /*!< Max enumerator value of ATDATAM23_W field.                           */
73182   #define STM_ITATBDATA0_ATDATAM23_W_Low (0x0UL)     /*!< Drive logic 0 on output.                                             */
73183   #define STM_ITATBDATA0_ATDATAM23_W_High (0x1UL)    /*!< Drive logic 1 on output.                                             */
73184 
73185 /* ATDATAM31_W @Bit 4 : Sets the value of the ATDATAM[31]. */
73186   #define STM_ITATBDATA0_ATDATAM31_W_Pos (4UL)       /*!< Position of ATDATAM31_W field.                                       */
73187   #define STM_ITATBDATA0_ATDATAM31_W_Msk (0x1UL << STM_ITATBDATA0_ATDATAM31_W_Pos) /*!< Bit mask of ATDATAM31_W field.         */
73188   #define STM_ITATBDATA0_ATDATAM31_W_Min (0x0UL)     /*!< Min enumerator value of ATDATAM31_W field.                           */
73189   #define STM_ITATBDATA0_ATDATAM31_W_Max (0x1UL)     /*!< Max enumerator value of ATDATAM31_W field.                           */
73190   #define STM_ITATBDATA0_ATDATAM31_W_Low (0x0UL)     /*!< Drive logic 0 on output.                                             */
73191   #define STM_ITATBDATA0_ATDATAM31_W_High (0x1UL)    /*!< Drive logic 1 on output.                                             */
73192 
73193 
73194 /* STM_ITATBCTR2: Controls the value of the ATDATAM output in integration mode. */
73195   #define STM_ITATBCTR2_ResetValue (0x00000000UL)    /*!< Reset value of ITATBCTR2 register.                                   */
73196 
73197 /* ATREADYM_R @Bit 0 : Reads the value of the ATREADYM input. */
73198   #define STM_ITATBCTR2_ATREADYM_R_Pos (0UL)         /*!< Position of ATREADYM_R field.                                        */
73199   #define STM_ITATBCTR2_ATREADYM_R_Msk (0x1UL << STM_ITATBCTR2_ATREADYM_R_Pos) /*!< Bit mask of ATREADYM_R field.              */
73200   #define STM_ITATBCTR2_ATREADYM_R_Min (0x0UL)       /*!< Min enumerator value of ATREADYM_R field.                            */
73201   #define STM_ITATBCTR2_ATREADYM_R_Max (0x1UL)       /*!< Max enumerator value of ATREADYM_R field.                            */
73202   #define STM_ITATBCTR2_ATREADYM_R_Low (0x0UL)       /*!< Pin is at logic 0.                                                   */
73203   #define STM_ITATBCTR2_ATREADYM_R_High (0x1UL)      /*!< Pin is at logic 1.                                                   */
73204 
73205 /* AFVALIDM_R @Bit 1 : Reads the value of the AFVALIDM input. */
73206   #define STM_ITATBCTR2_AFVALIDM_R_Pos (1UL)         /*!< Position of AFVALIDM_R field.                                        */
73207   #define STM_ITATBCTR2_AFVALIDM_R_Msk (0x1UL << STM_ITATBCTR2_AFVALIDM_R_Pos) /*!< Bit mask of AFVALIDM_R field.              */
73208   #define STM_ITATBCTR2_AFVALIDM_R_Min (0x0UL)       /*!< Min enumerator value of AFVALIDM_R field.                            */
73209   #define STM_ITATBCTR2_AFVALIDM_R_Max (0x1UL)       /*!< Max enumerator value of AFVALIDM_R field.                            */
73210   #define STM_ITATBCTR2_AFVALIDM_R_Low (0x0UL)       /*!< Pin is at logic 0.                                                   */
73211   #define STM_ITATBCTR2_AFVALIDM_R_High (0x1UL)      /*!< Pin is at logic 1.                                                   */
73212 
73213 
73214 /* STM_ITATBID: Controls the value of the ATIDM output in integration mode. */
73215   #define STM_ITATBID_ResetValue (0x00000000UL)      /*!< Reset value of ITATBID register.                                     */
73216 
73217 /* ATIDM_W0 @Bit 0 : Sets the value of pin 0 of the ATIDM output. */
73218   #define STM_ITATBID_ATIDM_W0_Pos (0UL)             /*!< Position of ATIDM_W0 field.                                          */
73219   #define STM_ITATBID_ATIDM_W0_Msk (0x1UL << STM_ITATBID_ATIDM_W0_Pos) /*!< Bit mask of ATIDM_W0 field.                        */
73220   #define STM_ITATBID_ATIDM_W0_Min (0x0UL)           /*!< Min enumerator value of ATIDM_W0 field.                              */
73221   #define STM_ITATBID_ATIDM_W0_Max (0x1UL)           /*!< Max enumerator value of ATIDM_W0 field.                              */
73222   #define STM_ITATBID_ATIDM_W0_Low (0x0UL)           /*!< Pin is at logic 0.                                                   */
73223   #define STM_ITATBID_ATIDM_W0_High (0x1UL)          /*!< Pin is at logic 1.                                                   */
73224 
73225 /* ATIDM_W1 @Bit 1 : Sets the value of pin 1 of the ATIDM output. */
73226   #define STM_ITATBID_ATIDM_W1_Pos (1UL)             /*!< Position of ATIDM_W1 field.                                          */
73227   #define STM_ITATBID_ATIDM_W1_Msk (0x1UL << STM_ITATBID_ATIDM_W1_Pos) /*!< Bit mask of ATIDM_W1 field.                        */
73228   #define STM_ITATBID_ATIDM_W1_Min (0x0UL)           /*!< Min enumerator value of ATIDM_W1 field.                              */
73229   #define STM_ITATBID_ATIDM_W1_Max (0x1UL)           /*!< Max enumerator value of ATIDM_W1 field.                              */
73230   #define STM_ITATBID_ATIDM_W1_Low (0x0UL)           /*!< Pin is at logic 0.                                                   */
73231   #define STM_ITATBID_ATIDM_W1_High (0x1UL)          /*!< Pin is at logic 1.                                                   */
73232 
73233 /* ATIDM_W2 @Bit 2 : Sets the value of pin 2 of the ATIDM output. */
73234   #define STM_ITATBID_ATIDM_W2_Pos (2UL)             /*!< Position of ATIDM_W2 field.                                          */
73235   #define STM_ITATBID_ATIDM_W2_Msk (0x1UL << STM_ITATBID_ATIDM_W2_Pos) /*!< Bit mask of ATIDM_W2 field.                        */
73236   #define STM_ITATBID_ATIDM_W2_Min (0x0UL)           /*!< Min enumerator value of ATIDM_W2 field.                              */
73237   #define STM_ITATBID_ATIDM_W2_Max (0x1UL)           /*!< Max enumerator value of ATIDM_W2 field.                              */
73238   #define STM_ITATBID_ATIDM_W2_Low (0x0UL)           /*!< Pin is at logic 0.                                                   */
73239   #define STM_ITATBID_ATIDM_W2_High (0x1UL)          /*!< Pin is at logic 1.                                                   */
73240 
73241 /* ATIDM_W3 @Bit 3 : Sets the value of pin 3 of the ATIDM output. */
73242   #define STM_ITATBID_ATIDM_W3_Pos (3UL)             /*!< Position of ATIDM_W3 field.                                          */
73243   #define STM_ITATBID_ATIDM_W3_Msk (0x1UL << STM_ITATBID_ATIDM_W3_Pos) /*!< Bit mask of ATIDM_W3 field.                        */
73244   #define STM_ITATBID_ATIDM_W3_Min (0x0UL)           /*!< Min enumerator value of ATIDM_W3 field.                              */
73245   #define STM_ITATBID_ATIDM_W3_Max (0x1UL)           /*!< Max enumerator value of ATIDM_W3 field.                              */
73246   #define STM_ITATBID_ATIDM_W3_Low (0x0UL)           /*!< Pin is at logic 0.                                                   */
73247   #define STM_ITATBID_ATIDM_W3_High (0x1UL)          /*!< Pin is at logic 1.                                                   */
73248 
73249 /* ATIDM_W4 @Bit 4 : Sets the value of pin 4 of the ATIDM output. */
73250   #define STM_ITATBID_ATIDM_W4_Pos (4UL)             /*!< Position of ATIDM_W4 field.                                          */
73251   #define STM_ITATBID_ATIDM_W4_Msk (0x1UL << STM_ITATBID_ATIDM_W4_Pos) /*!< Bit mask of ATIDM_W4 field.                        */
73252   #define STM_ITATBID_ATIDM_W4_Min (0x0UL)           /*!< Min enumerator value of ATIDM_W4 field.                              */
73253   #define STM_ITATBID_ATIDM_W4_Max (0x1UL)           /*!< Max enumerator value of ATIDM_W4 field.                              */
73254   #define STM_ITATBID_ATIDM_W4_Low (0x0UL)           /*!< Pin is at logic 0.                                                   */
73255   #define STM_ITATBID_ATIDM_W4_High (0x1UL)          /*!< Pin is at logic 1.                                                   */
73256 
73257 /* ATIDM_W5 @Bit 5 : Sets the value of pin 5 of the ATIDM output. */
73258   #define STM_ITATBID_ATIDM_W5_Pos (5UL)             /*!< Position of ATIDM_W5 field.                                          */
73259   #define STM_ITATBID_ATIDM_W5_Msk (0x1UL << STM_ITATBID_ATIDM_W5_Pos) /*!< Bit mask of ATIDM_W5 field.                        */
73260   #define STM_ITATBID_ATIDM_W5_Min (0x0UL)           /*!< Min enumerator value of ATIDM_W5 field.                              */
73261   #define STM_ITATBID_ATIDM_W5_Max (0x1UL)           /*!< Max enumerator value of ATIDM_W5 field.                              */
73262   #define STM_ITATBID_ATIDM_W5_Low (0x0UL)           /*!< Pin is at logic 0.                                                   */
73263   #define STM_ITATBID_ATIDM_W5_High (0x1UL)          /*!< Pin is at logic 1.                                                   */
73264 
73265 /* ATIDM_W6 @Bit 6 : Sets the value of pin 6 of the ATIDM output. */
73266   #define STM_ITATBID_ATIDM_W6_Pos (6UL)             /*!< Position of ATIDM_W6 field.                                          */
73267   #define STM_ITATBID_ATIDM_W6_Msk (0x1UL << STM_ITATBID_ATIDM_W6_Pos) /*!< Bit mask of ATIDM_W6 field.                        */
73268   #define STM_ITATBID_ATIDM_W6_Min (0x0UL)           /*!< Min enumerator value of ATIDM_W6 field.                              */
73269   #define STM_ITATBID_ATIDM_W6_Max (0x1UL)           /*!< Max enumerator value of ATIDM_W6 field.                              */
73270   #define STM_ITATBID_ATIDM_W6_Low (0x0UL)           /*!< Pin is at logic 0.                                                   */
73271   #define STM_ITATBID_ATIDM_W6_High (0x1UL)          /*!< Pin is at logic 1.                                                   */
73272 
73273 
73274 /* STM_ITATBCTR0: Controls the value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mode. */
73275   #define STM_ITATBCTR0_ResetValue (0x00000000UL)    /*!< Reset value of ITATBCTR0 register.                                   */
73276 
73277 /* ATVALIDM_W @Bit 0 : Sets the value of the ATVALIDM output. */
73278   #define STM_ITATBCTR0_ATVALIDM_W_Pos (0UL)         /*!< Position of ATVALIDM_W field.                                        */
73279   #define STM_ITATBCTR0_ATVALIDM_W_Msk (0x1UL << STM_ITATBCTR0_ATVALIDM_W_Pos) /*!< Bit mask of ATVALIDM_W field.              */
73280   #define STM_ITATBCTR0_ATVALIDM_W_Min (0x0UL)       /*!< Min enumerator value of ATVALIDM_W field.                            */
73281   #define STM_ITATBCTR0_ATVALIDM_W_Max (0x1UL)       /*!< Max enumerator value of ATVALIDM_W field.                            */
73282   #define STM_ITATBCTR0_ATVALIDM_W_Low (0x0UL)       /*!< Pin is at logic 0.                                                   */
73283   #define STM_ITATBCTR0_ATVALIDM_W_High (0x1UL)      /*!< Pin is at logic 1.                                                   */
73284 
73285 /* AFREADYM_W @Bit 1 : Sets the value of the AFREADYM_W output. */
73286   #define STM_ITATBCTR0_AFREADYM_W_Pos (1UL)         /*!< Position of AFREADYM_W field.                                        */
73287   #define STM_ITATBCTR0_AFREADYM_W_Msk (0x1UL << STM_ITATBCTR0_AFREADYM_W_Pos) /*!< Bit mask of AFREADYM_W field.              */
73288   #define STM_ITATBCTR0_AFREADYM_W_Min (0x0UL)       /*!< Min enumerator value of AFREADYM_W field.                            */
73289   #define STM_ITATBCTR0_AFREADYM_W_Max (0x1UL)       /*!< Max enumerator value of AFREADYM_W field.                            */
73290   #define STM_ITATBCTR0_AFREADYM_W_Low (0x0UL)       /*!< Pin is at logic 0.                                                   */
73291   #define STM_ITATBCTR0_AFREADYM_W_High (0x1UL)      /*!< Pin is at logic 1.                                                   */
73292 
73293 /* ATBYTESM_W0 @Bit 8 : Sets the value of pin 0 of the ATBYTESM output. */
73294   #define STM_ITATBCTR0_ATBYTESM_W0_Pos (8UL)        /*!< Position of ATBYTESM_W0 field.                                       */
73295   #define STM_ITATBCTR0_ATBYTESM_W0_Msk (0x1UL << STM_ITATBCTR0_ATBYTESM_W0_Pos) /*!< Bit mask of ATBYTESM_W0 field.           */
73296   #define STM_ITATBCTR0_ATBYTESM_W0_Min (0x0UL)      /*!< Min enumerator value of ATBYTESM_W0 field.                           */
73297   #define STM_ITATBCTR0_ATBYTESM_W0_Max (0x1UL)      /*!< Max enumerator value of ATBYTESM_W0 field.                           */
73298   #define STM_ITATBCTR0_ATBYTESM_W0_Low (0x0UL)      /*!< Pin is at logic 0.                                                   */
73299   #define STM_ITATBCTR0_ATBYTESM_W0_High (0x1UL)     /*!< Pin is at logic 1.                                                   */
73300 
73301 /* ATBYTESM_W1 @Bit 9 : Sets the value of pin 1 of the ATBYTESM output. */
73302   #define STM_ITATBCTR0_ATBYTESM_W1_Pos (9UL)        /*!< Position of ATBYTESM_W1 field.                                       */
73303   #define STM_ITATBCTR0_ATBYTESM_W1_Msk (0x1UL << STM_ITATBCTR0_ATBYTESM_W1_Pos) /*!< Bit mask of ATBYTESM_W1 field.           */
73304   #define STM_ITATBCTR0_ATBYTESM_W1_Min (0x0UL)      /*!< Min enumerator value of ATBYTESM_W1 field.                           */
73305   #define STM_ITATBCTR0_ATBYTESM_W1_Max (0x1UL)      /*!< Max enumerator value of ATBYTESM_W1 field.                           */
73306   #define STM_ITATBCTR0_ATBYTESM_W1_Low (0x0UL)      /*!< Pin is at logic 0.                                                   */
73307   #define STM_ITATBCTR0_ATBYTESM_W1_High (0x1UL)     /*!< Pin is at logic 1.                                                   */
73308 
73309 
73310 /* STM_ITCTRL: Used to enable topology detection. This register enables the component to switch from a functional mode, the
73311                 default behavior, to integration mode where the inputs and outputs of the component can be directly controlled
73312                 for integration testing and topology solving. */
73313 
73314   #define STM_ITCTRL_ResetValue (0x00000000UL)       /*!< Reset value of ITCTRL register.                                      */
73315 
73316 /* INTEGRATIONMODE @Bit 0 : Enables the component to switch from functional mode to integration mode and back. If no integration
73317                             functionality is implemented, this register must read as zero. */
73318 
73319   #define STM_ITCTRL_INTEGRATIONMODE_Pos (0UL)       /*!< Position of INTEGRATIONMODE field.                                   */
73320   #define STM_ITCTRL_INTEGRATIONMODE_Msk (0x1UL << STM_ITCTRL_INTEGRATIONMODE_Pos) /*!< Bit mask of INTEGRATIONMODE field.     */
73321   #define STM_ITCTRL_INTEGRATIONMODE_Min (0x0UL)     /*!< Min enumerator value of INTEGRATIONMODE field.                       */
73322   #define STM_ITCTRL_INTEGRATIONMODE_Max (0x1UL)     /*!< Max enumerator value of INTEGRATIONMODE field.                       */
73323   #define STM_ITCTRL_INTEGRATIONMODE_Disabled (0x0UL) /*!< Integration mode is disabled.                                       */
73324   #define STM_ITCTRL_INTEGRATIONMODE_Enabled (0x1UL) /*!< Integration mode is Enabled.                                         */
73325 
73326 
73327 /* STM_LAR: This is used to enable write access to device registers. */
73328   #define STM_LAR_ResetValue (0x00000000UL)          /*!< Reset value of LAR register.                                         */
73329 
73330 /* ACCESS @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access.
73331                         */
73332 
73333   #define STM_LAR_ACCESS_Pos (0UL)                   /*!< Position of ACCESS field.                                            */
73334   #define STM_LAR_ACCESS_Msk (0xFFFFFFFFUL << STM_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field.                               */
73335   #define STM_LAR_ACCESS_Min (0xC5ACCE55UL)          /*!< Min enumerator value of ACCESS field.                                */
73336   #define STM_LAR_ACCESS_Max (0xC5ACCE55UL)          /*!< Max enumerator value of ACCESS field.                                */
73337   #define STM_LAR_ACCESS_UnLock (0xC5ACCE55UL)       /*!< Unlock register interface.                                           */
73338 
73339 
73340 /* STM_LSR: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug.
73341              Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always
73342              be present although there might not be any lock access control mechanism. The lock mechanism, where present and
73343              locked, must block write accesses to any control register, except the Lock Access Register. For most components
73344              this covers all registers except for the Lock Access Register. */
73345 
73346   #define STM_LSR_ResetValue (0x00000000UL)          /*!< Reset value of LSR register.                                         */
73347 
73348 /* PRESENT @Bit 0 : Indicates that a lock control mechanism exists for this device. */
73349   #define STM_LSR_PRESENT_Pos (0UL)                  /*!< Position of PRESENT field.                                           */
73350   #define STM_LSR_PRESENT_Msk (0x1UL << STM_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field.                                   */
73351   #define STM_LSR_PRESENT_Min (0x0UL)                /*!< Min enumerator value of PRESENT field.                               */
73352   #define STM_LSR_PRESENT_Max (0x1UL)                /*!< Max enumerator value of PRESENT field.                               */
73353   #define STM_LSR_PRESENT_NotImplemented (0x0UL)     /*!< No lock control mechanism exists, writes to the Lock Access Register
73354                                                           are ignored.*/
73355   #define STM_LSR_PRESENT_Implemented (0x1UL)        /*!< Lock control mechanism is present.                                   */
73356 
73357 /* LOCKED @Bit 1 : Returns the current status of the Lock. */
73358   #define STM_LSR_LOCKED_Pos (1UL)                   /*!< Position of LOCKED field.                                            */
73359   #define STM_LSR_LOCKED_Msk (0x1UL << STM_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field.                                      */
73360   #define STM_LSR_LOCKED_Min (0x0UL)                 /*!< Min enumerator value of LOCKED field.                                */
73361   #define STM_LSR_LOCKED_Max (0x1UL)                 /*!< Max enumerator value of LOCKED field.                                */
73362   #define STM_LSR_LOCKED_UnLocked (0x0UL)            /*!< Write access is allowed to this device.                              */
73363   #define STM_LSR_LOCKED_Locked (0x1UL)              /*!< Write access to the component is blocked. All writes to control
73364                                                           registers are ignored. Reads are permitted.*/
73365 
73366 /* TYPE @Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */
73367   #define STM_LSR_TYPE_Pos (2UL)                     /*!< Position of TYPE field.                                              */
73368   #define STM_LSR_TYPE_Msk (0x1UL << STM_LSR_TYPE_Pos) /*!< Bit mask of TYPE field.                                            */
73369   #define STM_LSR_TYPE_Min (0x0UL)                   /*!< Min enumerator value of TYPE field.                                  */
73370   #define STM_LSR_TYPE_Max (0x1UL)                   /*!< Max enumerator value of TYPE field.                                  */
73371   #define STM_LSR_TYPE_Bits32 (0x0UL)                /*!< This component implements a 32-bit Lock Access Register.             */
73372   #define STM_LSR_TYPE_Bits8 (0x1UL)                 /*!< This component implements an 8-bit Lock Access Register.             */
73373 
73374 
73375 /* STM_AUTHSTATUS: Indicates the current level of tracing permitted by the system */
73376   #define STM_AUTHSTATUS_ResetValue (0x00000000UL)   /*!< Reset value of AUTHSTATUS register.                                  */
73377 
73378 /* NSID @Bits 0..1 : Non-secure Invasive Debug */
73379   #define STM_AUTHSTATUS_NSID_Pos (0UL)              /*!< Position of NSID field.                                              */
73380   #define STM_AUTHSTATUS_NSID_Msk (0x3UL << STM_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field.                              */
73381   #define STM_AUTHSTATUS_NSID_Min (0x0UL)            /*!< Min enumerator value of NSID field.                                  */
73382   #define STM_AUTHSTATUS_NSID_Max (0x1UL)            /*!< Max enumerator value of NSID field.                                  */
73383   #define STM_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                      */
73384   #define STM_AUTHSTATUS_NSID_Implemented (0x1UL)    /*!< The feature is implemented.                                          */
73385 
73386 /* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */
73387   #define STM_AUTHSTATUS_NSNID_Pos (2UL)             /*!< Position of NSNID field.                                             */
73388   #define STM_AUTHSTATUS_NSNID_Msk (0x3UL << STM_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field.                           */
73389   #define STM_AUTHSTATUS_NSNID_Min (0x0UL)           /*!< Min enumerator value of NSNID field.                                 */
73390   #define STM_AUTHSTATUS_NSNID_Max (0x1UL)           /*!< Max enumerator value of NSNID field.                                 */
73391   #define STM_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                     */
73392   #define STM_AUTHSTATUS_NSNID_Implemented (0x1UL)   /*!< The feature is implemented.                                          */
73393 
73394 /* SID @Bits 4..5 : Secure Invasive Debug */
73395   #define STM_AUTHSTATUS_SID_Pos (4UL)               /*!< Position of SID field.                                               */
73396   #define STM_AUTHSTATUS_SID_Msk (0x3UL << STM_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field.                                 */
73397   #define STM_AUTHSTATUS_SID_Min (0x0UL)             /*!< Min enumerator value of SID field.                                   */
73398   #define STM_AUTHSTATUS_SID_Max (0x1UL)             /*!< Max enumerator value of SID field.                                   */
73399   #define STM_AUTHSTATUS_SID_NotImplemented (0x0UL)  /*!< The feature is not implemented.                                      */
73400   #define STM_AUTHSTATUS_SID_Implemented (0x1UL)     /*!< The feature is implemented.                                          */
73401 
73402 /* SNID @Bits 6..7 : Secure Non-Invasive Debug */
73403   #define STM_AUTHSTATUS_SNID_Pos (6UL)              /*!< Position of SNID field.                                              */
73404   #define STM_AUTHSTATUS_SNID_Msk (0x3UL << STM_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field.                              */
73405   #define STM_AUTHSTATUS_SNID_Min (0x0UL)            /*!< Min enumerator value of SNID field.                                  */
73406   #define STM_AUTHSTATUS_SNID_Max (0x1UL)            /*!< Max enumerator value of SNID field.                                  */
73407   #define STM_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                      */
73408   #define STM_AUTHSTATUS_SNID_Implemented (0x1UL)    /*!< The feature is implemented.                                          */
73409 
73410 
73411 /* STM_DEVID: Indicates the capabilities of the STM. */
73412   #define STM_DEVID_ResetValue (0x00000000UL)        /*!< Reset value of DEVID register.                                       */
73413 
73414 /* NUMSP @Bits 0..16 : This value indicates the number of stimulus ports implemented. */
73415   #define STM_DEVID_NUMSP_Pos (0UL)                  /*!< Position of NUMSP field.                                             */
73416   #define STM_DEVID_NUMSP_Msk (0x1FFFFUL << STM_DEVID_NUMSP_Pos) /*!< Bit mask of NUMSP field.                                 */
73417   #define STM_DEVID_NUMSP_Max (0x10000UL)            /*!< Maximum 65,536 stimulus ports can be implemented.                    */
73418 
73419 
73420 /* STM_DEVTYPE: Controls the single-shot comparator. */
73421   #define STM_DEVTYPE_ResetValue (0x00000000UL)      /*!< Reset value of DEVTYPE register.                                     */
73422 
73423 /* MAJOR @Bits 0..3 : The main type of the component */
73424   #define STM_DEVTYPE_MAJOR_Pos (0UL)                /*!< Position of MAJOR field.                                             */
73425   #define STM_DEVTYPE_MAJOR_Msk (0xFUL << STM_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field.                                 */
73426   #define STM_DEVTYPE_MAJOR_Min (0x3UL)              /*!< Min enumerator value of MAJOR field.                                 */
73427   #define STM_DEVTYPE_MAJOR_Max (0x3UL)              /*!< Max enumerator value of MAJOR field.                                 */
73428   #define STM_DEVTYPE_MAJOR_TraceSource (0x3UL)      /*!< Peripheral is a trace source.                                        */
73429 
73430 /* SUB @Bits 4..7 : The sub-type of the component */
73431   #define STM_DEVTYPE_SUB_Pos (4UL)                  /*!< Position of SUB field.                                               */
73432   #define STM_DEVTYPE_SUB_Msk (0xFUL << STM_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field.                                       */
73433   #define STM_DEVTYPE_SUB_Min (0x6UL)                /*!< Min enumerator value of SUB field.                                   */
73434   #define STM_DEVTYPE_SUB_Max (0x6UL)                /*!< Max enumerator value of SUB field.                                   */
73435   #define STM_DEVTYPE_SUB_StimulusTrace (0x6UL)      /*!< Peripheral is a stimulus trace source.                               */
73436 
73437 
73438 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
73439 
73440 /* =========================================================================================================================== */
73441 /* ================                                          STMDATA                                          ================ */
73442 /* =========================================================================================================================== */
73443 
73444 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
73445 
73446 /* ================================================== Struct STMDATA_DOMAIN ================================================== */
73447 /**
73448   * @brief DOMAIN [STMDATA_DOMAIN] (unspecified)
73449   */
73450 typedef struct {
73451   __IOM uint8_t   NSDATA[16777216];                  /*!< (@ 0x00000000) NonSecure STM output data buffer for domain n. Writes
73452                                                                          to this region generates trace packets with id n+96.*/
73453   __IOM uint8_t   SDATA[16777216];                   /*!< (@ 0x01000000) Secure STM output data buffer for domain n. Writes to
73454                                                                          this region generates trace packets with id n+32.*/
73455 } NRF_STMDATA_DOMAIN_Type;                           /*!< Size = 33554432 (0x2000000)                                          */
73456   #define STMDATA_DOMAIN_MaxCount (16UL)             /*!< Size of DOMAIN[16] array.                                            */
73457   #define STMDATA_DOMAIN_MaxIndex (15UL)             /*!< Max index of DOMAIN[16] array.                                       */
73458   #define STMDATA_DOMAIN_MinIndex (0UL)              /*!< Min index of DOMAIN[16] array.                                       */
73459 
73460 /* ===================================================== Struct STMDATA ====================================================== */
73461 /**
73462   * @brief System Trace Macrocell data buffer
73463   */
73464   typedef struct {                                   /*!< STMDATA Structure                                                    */
73465     #if defined(_GNUC_)
73466       #pragma GCC diagnostic push
73467       #pragma GCC diagnostic ignored "-Wpedantic"
73468     #endif
73469     union {
73470       __IOM NRF_STMDATA_DOMAIN_Type DOMAIN[16];      /*!< (@ 0x00000000) (unspecified)                                         */
73471     };
73472     #if defined(_GNUC_)
73473       #pragma GCC diagnostic pop
73474     #endif
73475   } NRF_STMDATA_Type;                                /*!< Size = 536870912 (0x20000000)                                        */
73476 
73477 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
73478 
73479 /* =========================================================================================================================== */
73480 /* ================                                            TBM                                            ================ */
73481 /* =========================================================================================================================== */
73482 
73483 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
73484 /* ======================================================= Struct TBM ======================================================== */
73485 /**
73486   * @brief Trace buffer monitor
73487   */
73488   typedef struct {                                   /*!< TBM Structure                                                        */
73489     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start counter                                         */
73490     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop counter, clear counter value                     */
73491     __OM uint32_t TASKS_FLUSH;                       /*!< (@ 0x00000008) Stop counter, keep current counter value              */
73492     __IM uint32_t RESERVED[61];
73493     __IOM uint32_t EVENTS_HALFFULL;                  /*!< (@ 0x00000100) Counter value equals half-full                        */
73494     __IOM uint32_t EVENTS_FULL;                      /*!< (@ 0x00000104) Counter value equals full                             */
73495     __IOM uint32_t EVENTS_FLUSH;                     /*!< (@ 0x00000108) Counter stopped due to flush                          */
73496     __IM uint32_t RESERVED1[61];
73497     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
73498     __IM uint32_t RESERVED2[63];
73499     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
73500     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
73501     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
73502     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
73503     __IM uint32_t RESERVED3[60];
73504     __IOM uint32_t BUFFERSIZE;                       /*!< (@ 0x00000400) System RAM trace buffer total size in bytes           */
73505     __IM uint32_t COUNT;                             /*!< (@ 0x00000404) Counter current value                                 */
73506   } NRF_TBM_Type;                                    /*!< Size = 1032 (0x408)                                                  */
73507 
73508 /* TBM_TASKS_START: Start counter */
73509   #define TBM_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
73510 
73511 /* TASKS_START @Bit 0 : Start counter */
73512   #define TBM_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
73513   #define TBM_TASKS_START_TASKS_START_Msk (0x1UL << TBM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
73514   #define TBM_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
73515   #define TBM_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
73516   #define TBM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
73517 
73518 
73519 /* TBM_TASKS_STOP: Stop counter, clear counter value */
73520   #define TBM_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
73521 
73522 /* TASKS_STOP @Bit 0 : Stop counter, clear counter value */
73523   #define TBM_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
73524   #define TBM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TBM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
73525   #define TBM_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
73526   #define TBM_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
73527   #define TBM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
73528 
73529 
73530 /* TBM_TASKS_FLUSH: Stop counter, keep current counter value */
73531   #define TBM_TASKS_FLUSH_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_FLUSH register.                                 */
73532 
73533 /* TASKS_FLUSH @Bit 0 : Stop counter, keep current counter value */
73534   #define TBM_TASKS_FLUSH_TASKS_FLUSH_Pos (0UL)      /*!< Position of TASKS_FLUSH field.                                       */
73535   #define TBM_TASKS_FLUSH_TASKS_FLUSH_Msk (0x1UL << TBM_TASKS_FLUSH_TASKS_FLUSH_Pos) /*!< Bit mask of TASKS_FLUSH field.       */
73536   #define TBM_TASKS_FLUSH_TASKS_FLUSH_Min (0x1UL)    /*!< Min enumerator value of TASKS_FLUSH field.                           */
73537   #define TBM_TASKS_FLUSH_TASKS_FLUSH_Max (0x1UL)    /*!< Max enumerator value of TASKS_FLUSH field.                           */
73538   #define TBM_TASKS_FLUSH_TASKS_FLUSH_Trigger (0x1UL) /*!< Trigger task                                                        */
73539 
73540 
73541 /* TBM_EVENTS_HALFFULL: Counter value equals half-full */
73542   #define TBM_EVENTS_HALFFULL_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_HALFFULL register.                          */
73543 
73544 /* EVENTS_HALFFULL @Bit 0 : Counter value equals half-full */
73545   #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Pos (0UL) /*!< Position of EVENTS_HALFFULL field.                                */
73546   #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Msk (0x1UL << TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Pos) /*!< Bit mask of
73547                                                                             EVENTS_HALFFULL field.*/
73548   #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Min (0x0UL) /*!< Min enumerator value of EVENTS_HALFFULL field.                  */
73549   #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Max (0x1UL) /*!< Max enumerator value of EVENTS_HALFFULL field.                  */
73550   #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_NotGenerated (0x0UL) /*!< Event not generated                                    */
73551   #define TBM_EVENTS_HALFFULL_EVENTS_HALFFULL_Generated (0x1UL) /*!< Event generated                                           */
73552 
73553 
73554 /* TBM_EVENTS_FULL: Counter value equals full */
73555   #define TBM_EVENTS_FULL_ResetValue (0x00000000UL)  /*!< Reset value of EVENTS_FULL register.                                 */
73556 
73557 /* EVENTS_FULL @Bit 0 : Counter value equals full */
73558   #define TBM_EVENTS_FULL_EVENTS_FULL_Pos (0UL)      /*!< Position of EVENTS_FULL field.                                       */
73559   #define TBM_EVENTS_FULL_EVENTS_FULL_Msk (0x1UL << TBM_EVENTS_FULL_EVENTS_FULL_Pos) /*!< Bit mask of EVENTS_FULL field.       */
73560   #define TBM_EVENTS_FULL_EVENTS_FULL_Min (0x0UL)    /*!< Min enumerator value of EVENTS_FULL field.                           */
73561   #define TBM_EVENTS_FULL_EVENTS_FULL_Max (0x1UL)    /*!< Max enumerator value of EVENTS_FULL field.                           */
73562   #define TBM_EVENTS_FULL_EVENTS_FULL_NotGenerated (0x0UL) /*!< Event not generated                                            */
73563   #define TBM_EVENTS_FULL_EVENTS_FULL_Generated (0x1UL) /*!< Event generated                                                   */
73564 
73565 
73566 /* TBM_EVENTS_FLUSH: Counter stopped due to flush */
73567   #define TBM_EVENTS_FLUSH_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_FLUSH register.                                */
73568 
73569 /* EVENTS_FLUSH @Bit 0 : Counter stopped due to flush */
73570   #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Pos (0UL)    /*!< Position of EVENTS_FLUSH field.                                      */
73571   #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Msk (0x1UL << TBM_EVENTS_FLUSH_EVENTS_FLUSH_Pos) /*!< Bit mask of EVENTS_FLUSH field.  */
73572   #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Min (0x0UL)  /*!< Min enumerator value of EVENTS_FLUSH field.                          */
73573   #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Max (0x1UL)  /*!< Max enumerator value of EVENTS_FLUSH field.                          */
73574   #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_NotGenerated (0x0UL) /*!< Event not generated                                          */
73575   #define TBM_EVENTS_FLUSH_EVENTS_FLUSH_Generated (0x1UL) /*!< Event generated                                                 */
73576 
73577 
73578 /* TBM_INTEN: Enable or disable interrupt */
73579   #define TBM_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
73580 
73581 /* HALFFULL @Bit 0 : Enable or disable interrupt for event HALFFULL */
73582   #define TBM_INTEN_HALFFULL_Pos (0UL)               /*!< Position of HALFFULL field.                                          */
73583   #define TBM_INTEN_HALFFULL_Msk (0x1UL << TBM_INTEN_HALFFULL_Pos) /*!< Bit mask of HALFFULL field.                            */
73584   #define TBM_INTEN_HALFFULL_Min (0x0UL)             /*!< Min enumerator value of HALFFULL field.                              */
73585   #define TBM_INTEN_HALFFULL_Max (0x1UL)             /*!< Max enumerator value of HALFFULL field.                              */
73586   #define TBM_INTEN_HALFFULL_Disabled (0x0UL)        /*!< Disable                                                              */
73587   #define TBM_INTEN_HALFFULL_Enabled (0x1UL)         /*!< Enable                                                               */
73588 
73589 /* FULL @Bit 1 : Enable or disable interrupt for event FULL */
73590   #define TBM_INTEN_FULL_Pos (1UL)                   /*!< Position of FULL field.                                              */
73591   #define TBM_INTEN_FULL_Msk (0x1UL << TBM_INTEN_FULL_Pos) /*!< Bit mask of FULL field.                                        */
73592   #define TBM_INTEN_FULL_Min (0x0UL)                 /*!< Min enumerator value of FULL field.                                  */
73593   #define TBM_INTEN_FULL_Max (0x1UL)                 /*!< Max enumerator value of FULL field.                                  */
73594   #define TBM_INTEN_FULL_Disabled (0x0UL)            /*!< Disable                                                              */
73595   #define TBM_INTEN_FULL_Enabled (0x1UL)             /*!< Enable                                                               */
73596 
73597 /* FLUSH @Bit 2 : Enable or disable interrupt for event FLUSH */
73598   #define TBM_INTEN_FLUSH_Pos (2UL)                  /*!< Position of FLUSH field.                                             */
73599   #define TBM_INTEN_FLUSH_Msk (0x1UL << TBM_INTEN_FLUSH_Pos) /*!< Bit mask of FLUSH field.                                     */
73600   #define TBM_INTEN_FLUSH_Min (0x0UL)                /*!< Min enumerator value of FLUSH field.                                 */
73601   #define TBM_INTEN_FLUSH_Max (0x1UL)                /*!< Max enumerator value of FLUSH field.                                 */
73602   #define TBM_INTEN_FLUSH_Disabled (0x0UL)           /*!< Disable                                                              */
73603   #define TBM_INTEN_FLUSH_Enabled (0x1UL)            /*!< Enable                                                               */
73604 
73605 
73606 /* TBM_INTENSET: Enable interrupt */
73607   #define TBM_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
73608 
73609 /* HALFFULL @Bit 0 : Write '1' to enable interrupt for event HALFFULL */
73610   #define TBM_INTENSET_HALFFULL_Pos (0UL)            /*!< Position of HALFFULL field.                                          */
73611   #define TBM_INTENSET_HALFFULL_Msk (0x1UL << TBM_INTENSET_HALFFULL_Pos) /*!< Bit mask of HALFFULL field.                      */
73612   #define TBM_INTENSET_HALFFULL_Min (0x0UL)          /*!< Min enumerator value of HALFFULL field.                              */
73613   #define TBM_INTENSET_HALFFULL_Max (0x1UL)          /*!< Max enumerator value of HALFFULL field.                              */
73614   #define TBM_INTENSET_HALFFULL_Set (0x1UL)          /*!< Enable                                                               */
73615   #define TBM_INTENSET_HALFFULL_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
73616   #define TBM_INTENSET_HALFFULL_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
73617 
73618 /* FULL @Bit 1 : Write '1' to enable interrupt for event FULL */
73619   #define TBM_INTENSET_FULL_Pos (1UL)                /*!< Position of FULL field.                                              */
73620   #define TBM_INTENSET_FULL_Msk (0x1UL << TBM_INTENSET_FULL_Pos) /*!< Bit mask of FULL field.                                  */
73621   #define TBM_INTENSET_FULL_Min (0x0UL)              /*!< Min enumerator value of FULL field.                                  */
73622   #define TBM_INTENSET_FULL_Max (0x1UL)              /*!< Max enumerator value of FULL field.                                  */
73623   #define TBM_INTENSET_FULL_Set (0x1UL)              /*!< Enable                                                               */
73624   #define TBM_INTENSET_FULL_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
73625   #define TBM_INTENSET_FULL_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
73626 
73627 /* FLUSH @Bit 2 : Write '1' to enable interrupt for event FLUSH */
73628   #define TBM_INTENSET_FLUSH_Pos (2UL)               /*!< Position of FLUSH field.                                             */
73629   #define TBM_INTENSET_FLUSH_Msk (0x1UL << TBM_INTENSET_FLUSH_Pos) /*!< Bit mask of FLUSH field.                               */
73630   #define TBM_INTENSET_FLUSH_Min (0x0UL)             /*!< Min enumerator value of FLUSH field.                                 */
73631   #define TBM_INTENSET_FLUSH_Max (0x1UL)             /*!< Max enumerator value of FLUSH field.                                 */
73632   #define TBM_INTENSET_FLUSH_Set (0x1UL)             /*!< Enable                                                               */
73633   #define TBM_INTENSET_FLUSH_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
73634   #define TBM_INTENSET_FLUSH_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
73635 
73636 
73637 /* TBM_INTENCLR: Disable interrupt */
73638   #define TBM_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
73639 
73640 /* HALFFULL @Bit 0 : Write '1' to disable interrupt for event HALFFULL */
73641   #define TBM_INTENCLR_HALFFULL_Pos (0UL)            /*!< Position of HALFFULL field.                                          */
73642   #define TBM_INTENCLR_HALFFULL_Msk (0x1UL << TBM_INTENCLR_HALFFULL_Pos) /*!< Bit mask of HALFFULL field.                      */
73643   #define TBM_INTENCLR_HALFFULL_Min (0x0UL)          /*!< Min enumerator value of HALFFULL field.                              */
73644   #define TBM_INTENCLR_HALFFULL_Max (0x1UL)          /*!< Max enumerator value of HALFFULL field.                              */
73645   #define TBM_INTENCLR_HALFFULL_Clear (0x1UL)        /*!< Disable                                                              */
73646   #define TBM_INTENCLR_HALFFULL_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
73647   #define TBM_INTENCLR_HALFFULL_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
73648 
73649 /* FULL @Bit 1 : Write '1' to disable interrupt for event FULL */
73650   #define TBM_INTENCLR_FULL_Pos (1UL)                /*!< Position of FULL field.                                              */
73651   #define TBM_INTENCLR_FULL_Msk (0x1UL << TBM_INTENCLR_FULL_Pos) /*!< Bit mask of FULL field.                                  */
73652   #define TBM_INTENCLR_FULL_Min (0x0UL)              /*!< Min enumerator value of FULL field.                                  */
73653   #define TBM_INTENCLR_FULL_Max (0x1UL)              /*!< Max enumerator value of FULL field.                                  */
73654   #define TBM_INTENCLR_FULL_Clear (0x1UL)            /*!< Disable                                                              */
73655   #define TBM_INTENCLR_FULL_Disabled (0x0UL)         /*!< Read: Disabled                                                       */
73656   #define TBM_INTENCLR_FULL_Enabled (0x1UL)          /*!< Read: Enabled                                                        */
73657 
73658 /* FLUSH @Bit 2 : Write '1' to disable interrupt for event FLUSH */
73659   #define TBM_INTENCLR_FLUSH_Pos (2UL)               /*!< Position of FLUSH field.                                             */
73660   #define TBM_INTENCLR_FLUSH_Msk (0x1UL << TBM_INTENCLR_FLUSH_Pos) /*!< Bit mask of FLUSH field.                               */
73661   #define TBM_INTENCLR_FLUSH_Min (0x0UL)             /*!< Min enumerator value of FLUSH field.                                 */
73662   #define TBM_INTENCLR_FLUSH_Max (0x1UL)             /*!< Max enumerator value of FLUSH field.                                 */
73663   #define TBM_INTENCLR_FLUSH_Clear (0x1UL)           /*!< Disable                                                              */
73664   #define TBM_INTENCLR_FLUSH_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
73665   #define TBM_INTENCLR_FLUSH_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
73666 
73667 
73668 /* TBM_INTPEND: Pending interrupts */
73669   #define TBM_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */
73670 
73671 /* HALFFULL @Bit 0 : Read pending status of interrupt for event HALFFULL */
73672   #define TBM_INTPEND_HALFFULL_Pos (0UL)             /*!< Position of HALFFULL field.                                          */
73673   #define TBM_INTPEND_HALFFULL_Msk (0x1UL << TBM_INTPEND_HALFFULL_Pos) /*!< Bit mask of HALFFULL field.                        */
73674   #define TBM_INTPEND_HALFFULL_Min (0x0UL)           /*!< Min enumerator value of HALFFULL field.                              */
73675   #define TBM_INTPEND_HALFFULL_Max (0x1UL)           /*!< Max enumerator value of HALFFULL field.                              */
73676   #define TBM_INTPEND_HALFFULL_NotPending (0x0UL)    /*!< Read: Not pending                                                    */
73677   #define TBM_INTPEND_HALFFULL_Pending (0x1UL)       /*!< Read: Pending                                                        */
73678 
73679 /* FULL @Bit 1 : Read pending status of interrupt for event FULL */
73680   #define TBM_INTPEND_FULL_Pos (1UL)                 /*!< Position of FULL field.                                              */
73681   #define TBM_INTPEND_FULL_Msk (0x1UL << TBM_INTPEND_FULL_Pos) /*!< Bit mask of FULL field.                                    */
73682   #define TBM_INTPEND_FULL_Min (0x0UL)               /*!< Min enumerator value of FULL field.                                  */
73683   #define TBM_INTPEND_FULL_Max (0x1UL)               /*!< Max enumerator value of FULL field.                                  */
73684   #define TBM_INTPEND_FULL_NotPending (0x0UL)        /*!< Read: Not pending                                                    */
73685   #define TBM_INTPEND_FULL_Pending (0x1UL)           /*!< Read: Pending                                                        */
73686 
73687 /* FLUSH @Bit 2 : Read pending status of interrupt for event FLUSH */
73688   #define TBM_INTPEND_FLUSH_Pos (2UL)                /*!< Position of FLUSH field.                                             */
73689   #define TBM_INTPEND_FLUSH_Msk (0x1UL << TBM_INTPEND_FLUSH_Pos) /*!< Bit mask of FLUSH field.                                 */
73690   #define TBM_INTPEND_FLUSH_Min (0x0UL)              /*!< Min enumerator value of FLUSH field.                                 */
73691   #define TBM_INTPEND_FLUSH_Max (0x1UL)              /*!< Max enumerator value of FLUSH field.                                 */
73692   #define TBM_INTPEND_FLUSH_NotPending (0x0UL)       /*!< Read: Not pending                                                    */
73693   #define TBM_INTPEND_FLUSH_Pending (0x1UL)          /*!< Read: Pending                                                        */
73694 
73695 
73696 /* TBM_BUFFERSIZE: System RAM trace buffer total size in bytes */
73697   #define TBM_BUFFERSIZE_ResetValue (0x000001FFUL)   /*!< Reset value of BUFFERSIZE register.                                  */
73698 
73699 /* BUFFERSIZE @Bits 0..11 : Must only be configured in STOP mode. Must be multiple of 16 bytes to make half-buffer size always
73700                             64 bit word aligned. BUFFERSIZE LSB byte always fixed as 0xF to 16 bytes boundary. Minimum
73701                             BUFFERSIZE value 0x00F i.e. 16 bytes, maximum value 0xFFF i.e. 4096 bytes. */
73702 
73703   #define TBM_BUFFERSIZE_BUFFERSIZE_Pos (0UL)        /*!< Position of BUFFERSIZE field.                                        */
73704   #define TBM_BUFFERSIZE_BUFFERSIZE_Msk (0xFFFUL << TBM_BUFFERSIZE_BUFFERSIZE_Pos) /*!< Bit mask of BUFFERSIZE field.          */
73705   #define TBM_BUFFERSIZE_BUFFERSIZE_Min (0x00FUL)    /*!< 16 bytes                                                             */
73706   #define TBM_BUFFERSIZE_BUFFERSIZE_Max (0xFFFUL)    /*!< 4096 bytes                                                           */
73707 
73708 
73709 /* TBM_COUNT: Counter current value */
73710   #define TBM_COUNT_ResetValue (0x00000000UL)        /*!< Reset value of COUNT register.                                       */
73711 
73712 /* COUNT @Bits 0..11 : Counter current value */
73713   #define TBM_COUNT_COUNT_Pos (0UL)                  /*!< Position of COUNT field.                                             */
73714   #define TBM_COUNT_COUNT_Msk (0xFFFUL << TBM_COUNT_COUNT_Pos) /*!< Bit mask of COUNT field.                                   */
73715 
73716 
73717 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
73718 
73719 /* =========================================================================================================================== */
73720 /* ================                                          TDDCONF                                          ================ */
73721 /* =========================================================================================================================== */
73722 
73723 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
73724 /* ===================================================== Struct TDDCONF ====================================================== */
73725 /**
73726   * @brief TDDCONF
73727   */
73728   typedef struct {                                   /*!< TDDCONF Structure                                                    */
73729     __IM uint32_t RESERVED[256];
73730     __IOM uint32_t SYSPWRUPREQ;                      /*!< (@ 0x00000400) System power-up request                               */
73731     __IOM uint32_t DBGPWRUPREQ;                      /*!< (@ 0x00000404) Debug power-up request                                */
73732     __IOM uint32_t TRACEPORTSPEED;                   /*!< (@ 0x00000408) Trace port trace clock speed                          */
73733     __IM uint32_t DEBUGPOWERREQSTATUS;               /*!< (@ 0x0000040C) Combined effective system status of both SWJ-DP and
73734                                                                          TDDCONF registers originated power requests*/
73735   } NRF_TDDCONF_Type;                                /*!< Size = 1040 (0x410)                                                  */
73736 
73737 /* TDDCONF_SYSPWRUPREQ: System power-up request */
73738   #define TDDCONF_SYSPWRUPREQ_ResetValue (0x00000000UL) /*!< Reset value of SYSPWRUPREQ register.                              */
73739 
73740 /* ACTIVE @Bit 0 : Activate power-up request */
73741   #define TDDCONF_SYSPWRUPREQ_ACTIVE_Pos (0UL)       /*!< Position of ACTIVE field.                                            */
73742   #define TDDCONF_SYSPWRUPREQ_ACTIVE_Msk (0x1UL << TDDCONF_SYSPWRUPREQ_ACTIVE_Pos) /*!< Bit mask of ACTIVE field.              */
73743   #define TDDCONF_SYSPWRUPREQ_ACTIVE_Min (0x0UL)     /*!< Min enumerator value of ACTIVE field.                                */
73744   #define TDDCONF_SYSPWRUPREQ_ACTIVE_Max (0x1UL)     /*!< Max enumerator value of ACTIVE field.                                */
73745   #define TDDCONF_SYSPWRUPREQ_ACTIVE_NotActive (0x0UL) /*!< Power-up request not active                                        */
73746   #define TDDCONF_SYSPWRUPREQ_ACTIVE_Active (0x1UL)  /*!< Power-up request active                                              */
73747 
73748 
73749 /* TDDCONF_DBGPWRUPREQ: Debug power-up request */
73750   #define TDDCONF_DBGPWRUPREQ_ResetValue (0x00000000UL) /*!< Reset value of DBGPWRUPREQ register.                              */
73751 
73752 /* ACTIVE @Bit 0 : Activate power-up request */
73753   #define TDDCONF_DBGPWRUPREQ_ACTIVE_Pos (0UL)       /*!< Position of ACTIVE field.                                            */
73754   #define TDDCONF_DBGPWRUPREQ_ACTIVE_Msk (0x1UL << TDDCONF_DBGPWRUPREQ_ACTIVE_Pos) /*!< Bit mask of ACTIVE field.              */
73755   #define TDDCONF_DBGPWRUPREQ_ACTIVE_Min (0x0UL)     /*!< Min enumerator value of ACTIVE field.                                */
73756   #define TDDCONF_DBGPWRUPREQ_ACTIVE_Max (0x1UL)     /*!< Max enumerator value of ACTIVE field.                                */
73757   #define TDDCONF_DBGPWRUPREQ_ACTIVE_NotActive (0x0UL) /*!< Power-up request not active                                        */
73758   #define TDDCONF_DBGPWRUPREQ_ACTIVE_Active (0x1UL)  /*!< Power-up request active                                              */
73759 
73760 
73761 /* TDDCONF_TRACEPORTSPEED: Trace port trace clock speed */
73762   #define TDDCONF_TRACEPORTSPEED_ResetValue (0x00000000UL) /*!< Reset value of TRACEPORTSPEED register.                        */
73763 
73764 /* SPEED @Bits 0..1 : Trace clock speed */
73765   #define TDDCONF_TRACEPORTSPEED_SPEED_Pos (0UL)     /*!< Position of SPEED field.                                             */
73766   #define TDDCONF_TRACEPORTSPEED_SPEED_Msk (0x3UL << TDDCONF_TRACEPORTSPEED_SPEED_Pos) /*!< Bit mask of SPEED field.           */
73767 
73768 
73769 /* TDDCONF_DEBUGPOWERREQSTATUS: Combined effective system status of both SWJ-DP and TDDCONF registers originated power requests
73770                                  */
73771 
73772   #define TDDCONF_DEBUGPOWERREQSTATUS_ResetValue (0x00000000UL) /*!< Reset value of DEBUGPOWERREQSTATUS register.              */
73773 
73774 /* SYSPWRUPREQUESTED @Bit 0 : System powerup request status */
73775   #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Pos (0UL) /*!< Position of SYSPWRUPREQUESTED field.                    */
73776   #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Msk (0x1UL << TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Pos) /*!<
73777                                                                             Bit mask of SYSPWRUPREQUESTED field.*/
73778   #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Min (0x0UL) /*!< Min enumerator value of SYSPWRUPREQUESTED field.      */
73779   #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_Max (0x1UL) /*!< Max enumerator value of SYSPWRUPREQUESTED field.      */
73780   #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_NoPowerReq (0x0UL) /*!< Power not requested                            */
73781   #define TDDCONF_DEBUGPOWERREQSTATUS_SYSPWRUPREQUESTED_PowerReq (0x1UL) /*!< Power requested                                  */
73782 
73783 /* DBGPWRUPREQUESTED @Bit 1 : Debug domain powerup request status */
73784   #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Pos (1UL) /*!< Position of DBGPWRUPREQUESTED field.                    */
73785   #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Msk (0x1UL << TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Pos) /*!<
73786                                                                             Bit mask of DBGPWRUPREQUESTED field.*/
73787   #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Min (0x0UL) /*!< Min enumerator value of DBGPWRUPREQUESTED field.      */
73788   #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_Max (0x1UL) /*!< Max enumerator value of DBGPWRUPREQUESTED field.      */
73789   #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_NoPowerReq (0x0UL) /*!< Power not requested                            */
73790   #define TDDCONF_DEBUGPOWERREQSTATUS_DBGPWRUPREQUESTED_PowerReq (0x1UL) /*!< Power requested                                  */
73791 
73792 
73793 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
73794 
73795 /* =========================================================================================================================== */
73796 /* ================                                           TEMP                                           ================ */
73797 /* =========================================================================================================================== */
73798 
73799 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
73800 /* ======================================================= Struct TEMP ======================================================= */
73801 /**
73802   * @brief Temperature Sensor
73803   */
73804   typedef struct {                                   /*!< TEMP Structure                                                       */
73805     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start temperature measurement                         */
73806     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop temperature measurement                          */
73807     __IM uint32_t RESERVED[30];
73808     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
73809     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
73810     __IM uint32_t RESERVED1[30];
73811     __IOM uint32_t EVENTS_DATARDY;                   /*!< (@ 0x00000100) Temperature measurement complete, data ready          */
73812     __IM uint32_t RESERVED2[31];
73813     __IOM uint32_t PUBLISH_DATARDY;                  /*!< (@ 0x00000180) Publish configuration for event DATARDY               */
73814     __IM uint32_t RESERVED3[96];
73815     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
73816     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
73817     __IM uint32_t RESERVED4[127];
73818     __IM int32_t  TEMP;                              /*!< (@ 0x00000508) Temperature in degC (0.25deg steps)                   */
73819     __IM uint32_t RESERVED5[5];
73820     __IOM uint32_t A0;                               /*!< (@ 0x00000520) Slope of 1st piece wise linear function               */
73821     __IOM uint32_t A1;                               /*!< (@ 0x00000524) Slope of 2nd piece wise linear function               */
73822     __IOM uint32_t A2;                               /*!< (@ 0x00000528) Slope of 3rd piece wise linear function               */
73823     __IOM uint32_t A3;                               /*!< (@ 0x0000052C) Slope of 4th piece wise linear function               */
73824     __IOM uint32_t A4;                               /*!< (@ 0x00000530) Slope of 5th piece wise linear function               */
73825     __IOM uint32_t A5;                               /*!< (@ 0x00000534) Slope of 6th piece wise linear function               */
73826     __IOM uint32_t A6;                               /*!< (@ 0x00000538) Slope of 7th piece wise linear function               */
73827     __IM uint32_t RESERVED6;
73828     __IOM uint32_t B0;                               /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function         */
73829     __IOM uint32_t B1;                               /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function         */
73830     __IOM uint32_t B2;                               /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function         */
73831     __IOM uint32_t B3;                               /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function         */
73832     __IOM uint32_t B4;                               /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function         */
73833     __IOM uint32_t B5;                               /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function         */
73834     __IOM uint32_t B6;                               /*!< (@ 0x00000558) y-intercept of 7th piece wise linear function         */
73835     __IM uint32_t RESERVED7;
73836     __IOM uint32_t T0;                               /*!< (@ 0x00000560) End point of 1st piece wise linear function           */
73837     __IOM uint32_t T1;                               /*!< (@ 0x00000564) End point of 2nd piece wise linear function           */
73838     __IOM uint32_t T2;                               /*!< (@ 0x00000568) End point of 3rd piece wise linear function           */
73839     __IOM uint32_t T3;                               /*!< (@ 0x0000056C) End point of 4th piece wise linear function           */
73840     __IOM uint32_t T4;                               /*!< (@ 0x00000570) End point of 5th piece wise linear function           */
73841     __IOM uint32_t T5;                               /*!< (@ 0x00000574) End point of 6th piece wise linear function           */
73842   } NRF_TEMP_Type;                                   /*!< Size = 1400 (0x578)                                                  */
73843 
73844 /* TEMP_TASKS_START: Start temperature measurement */
73845   #define TEMP_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                 */
73846 
73847 /* TASKS_START @Bit 0 : Start temperature measurement */
73848   #define TEMP_TASKS_START_TASKS_START_Pos (0UL)     /*!< Position of TASKS_START field.                                       */
73849   #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.     */
73850   #define TEMP_TASKS_START_TASKS_START_Min (0x1UL)   /*!< Min enumerator value of TASKS_START field.                           */
73851   #define TEMP_TASKS_START_TASKS_START_Max (0x1UL)   /*!< Max enumerator value of TASKS_START field.                           */
73852   #define TEMP_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                       */
73853 
73854 
73855 /* TEMP_TASKS_STOP: Stop temperature measurement */
73856   #define TEMP_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */
73857 
73858 /* TASKS_STOP @Bit 0 : Stop temperature measurement */
73859   #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
73860   #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
73861   #define TEMP_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
73862   #define TEMP_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
73863   #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */
73864 
73865 
73866 /* TEMP_SUBSCRIBE_START: Subscribe configuration for task START */
73867   #define TEMP_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                         */
73868 
73869 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
73870   #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
73871   #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
73872   #define TEMP_SUBSCRIBE_START_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
73873   #define TEMP_SUBSCRIBE_START_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
73874 
73875 /* EN @Bit 31 : (unspecified) */
73876   #define TEMP_SUBSCRIBE_START_EN_Pos (31UL)         /*!< Position of EN field.                                                */
73877   #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                        */
73878   #define TEMP_SUBSCRIBE_START_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
73879   #define TEMP_SUBSCRIBE_START_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
73880   #define TEMP_SUBSCRIBE_START_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
73881   #define TEMP_SUBSCRIBE_START_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
73882 
73883 
73884 /* TEMP_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
73885   #define TEMP_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */
73886 
73887 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
73888   #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
73889   #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
73890   #define TEMP_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
73891   #define TEMP_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
73892 
73893 /* EN @Bit 31 : (unspecified) */
73894   #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
73895   #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
73896   #define TEMP_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
73897   #define TEMP_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
73898   #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
73899   #define TEMP_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
73900 
73901 
73902 /* TEMP_EVENTS_DATARDY: Temperature measurement complete, data ready */
73903   #define TEMP_EVENTS_DATARDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_DATARDY register.                           */
73904 
73905 /* EVENTS_DATARDY @Bit 0 : Temperature measurement complete, data ready */
73906   #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field.                                  */
73907   #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of
73908                                                                             EVENTS_DATARDY field.*/
73909   #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_DATARDY field.                    */
73910   #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_DATARDY field.                    */
73911   #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0x0UL) /*!< Event not generated                                     */
73912   #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (0x1UL) /*!< Event generated                                            */
73913 
73914 
73915 /* TEMP_PUBLISH_DATARDY: Publish configuration for event DATARDY */
73916   #define TEMP_PUBLISH_DATARDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_DATARDY register.                         */
73917 
73918 /* CHIDX @Bits 0..7 : DPPI channel that event DATARDY will publish to */
73919   #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
73920   #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
73921   #define TEMP_PUBLISH_DATARDY_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
73922   #define TEMP_PUBLISH_DATARDY_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
73923 
73924 /* EN @Bit 31 : (unspecified) */
73925   #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL)         /*!< Position of EN field.                                                */
73926   #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field.                        */
73927   #define TEMP_PUBLISH_DATARDY_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
73928   #define TEMP_PUBLISH_DATARDY_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
73929   #define TEMP_PUBLISH_DATARDY_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
73930   #define TEMP_PUBLISH_DATARDY_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
73931 
73932 
73933 /* TEMP_INTENSET: Enable interrupt */
73934   #define TEMP_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */
73935 
73936 /* DATARDY @Bit 0 : Write '1' to enable interrupt for event DATARDY */
73937   #define TEMP_INTENSET_DATARDY_Pos (0UL)            /*!< Position of DATARDY field.                                           */
73938   #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field.                       */
73939   #define TEMP_INTENSET_DATARDY_Min (0x0UL)          /*!< Min enumerator value of DATARDY field.                               */
73940   #define TEMP_INTENSET_DATARDY_Max (0x1UL)          /*!< Max enumerator value of DATARDY field.                               */
73941   #define TEMP_INTENSET_DATARDY_Set (0x1UL)          /*!< Enable                                                               */
73942   #define TEMP_INTENSET_DATARDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
73943   #define TEMP_INTENSET_DATARDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
73944 
73945 
73946 /* TEMP_INTENCLR: Disable interrupt */
73947   #define TEMP_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */
73948 
73949 /* DATARDY @Bit 0 : Write '1' to disable interrupt for event DATARDY */
73950   #define TEMP_INTENCLR_DATARDY_Pos (0UL)            /*!< Position of DATARDY field.                                           */
73951   #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field.                       */
73952   #define TEMP_INTENCLR_DATARDY_Min (0x0UL)          /*!< Min enumerator value of DATARDY field.                               */
73953   #define TEMP_INTENCLR_DATARDY_Max (0x1UL)          /*!< Max enumerator value of DATARDY field.                               */
73954   #define TEMP_INTENCLR_DATARDY_Clear (0x1UL)        /*!< Disable                                                              */
73955   #define TEMP_INTENCLR_DATARDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
73956   #define TEMP_INTENCLR_DATARDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
73957 
73958 
73959 /* TEMP_TEMP: Temperature in degC (0.25deg steps) */
73960   #define TEMP_TEMP_ResetValue (0x00000000UL)        /*!< Reset value of TEMP register.                                        */
73961 
73962 /* TEMP @Bits 0..31 : Temperature in degC (0.25deg steps) */
73963   #define TEMP_TEMP_TEMP_Pos (0UL)                   /*!< Position of TEMP field.                                              */
73964   #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field.                                 */
73965 
73966 
73967 /* TEMP_A0: Slope of 1st piece wise linear function */
73968   #define TEMP_A0_ResetValue (0x000002D9UL)          /*!< Reset value of A0 register.                                          */
73969 
73970 /* A0 @Bits 0..11 : Slope of 1st piece wise linear function */
73971   #define TEMP_A0_A0_Pos (0UL)                       /*!< Position of A0 field.                                                */
73972   #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field.                                                */
73973 
73974 
73975 /* TEMP_A1: Slope of 2nd piece wise linear function */
73976   #define TEMP_A1_ResetValue (0x00000322UL)          /*!< Reset value of A1 register.                                          */
73977 
73978 /* A1 @Bits 0..11 : Slope of 2nd piece wise linear function */
73979   #define TEMP_A1_A1_Pos (0UL)                       /*!< Position of A1 field.                                                */
73980   #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field.                                                */
73981 
73982 
73983 /* TEMP_A2: Slope of 3rd piece wise linear function */
73984   #define TEMP_A2_ResetValue (0x00000355UL)          /*!< Reset value of A2 register.                                          */
73985 
73986 /* A2 @Bits 0..11 : Slope of 3rd piece wise linear function */
73987   #define TEMP_A2_A2_Pos (0UL)                       /*!< Position of A2 field.                                                */
73988   #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field.                                                */
73989 
73990 
73991 /* TEMP_A3: Slope of 4th piece wise linear function */
73992   #define TEMP_A3_ResetValue (0x000003DFUL)          /*!< Reset value of A3 register.                                          */
73993 
73994 /* A3 @Bits 0..11 : Slope of 4th piece wise linear function */
73995   #define TEMP_A3_A3_Pos (0UL)                       /*!< Position of A3 field.                                                */
73996   #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field.                                                */
73997 
73998 
73999 /* TEMP_A4: Slope of 5th piece wise linear function */
74000   #define TEMP_A4_ResetValue (0x0000044EUL)          /*!< Reset value of A4 register.                                          */
74001 
74002 /* A4 @Bits 0..11 : Slope of 5th piece wise linear function */
74003   #define TEMP_A4_A4_Pos (0UL)                       /*!< Position of A4 field.                                                */
74004   #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field.                                                */
74005 
74006 
74007 /* TEMP_A5: Slope of 6th piece wise linear function */
74008   #define TEMP_A5_ResetValue (0x000004B7UL)          /*!< Reset value of A5 register.                                          */
74009 
74010 /* A5 @Bits 0..11 : Slope of 6th piece wise linear function */
74011   #define TEMP_A5_A5_Pos (0UL)                       /*!< Position of A5 field.                                                */
74012   #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field.                                                */
74013 
74014 
74015 /* TEMP_A6: Slope of 7th piece wise linear function */
74016   #define TEMP_A6_ResetValue (0x000004B7UL)          /*!< Reset value of A6 register.                                          */
74017 
74018 /* A6 @Bits 0..11 : Slope of 7th piece wise linear function */
74019   #define TEMP_A6_A6_Pos (0UL)                       /*!< Position of A6 field.                                                */
74020   #define TEMP_A6_A6_Msk (0xFFFUL << TEMP_A6_A6_Pos) /*!< Bit mask of A6 field.                                                */
74021 
74022 
74023 /* TEMP_B0: y-intercept of 1st piece wise linear function */
74024   #define TEMP_B0_ResetValue (0x00000FC7UL)          /*!< Reset value of B0 register.                                          */
74025 
74026 /* B0 @Bits 0..11 : y-intercept of 1st piece wise linear function */
74027   #define TEMP_B0_B0_Pos (0UL)                       /*!< Position of B0 field.                                                */
74028   #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field.                                                */
74029 
74030 
74031 /* TEMP_B1: y-intercept of 2nd piece wise linear function */
74032   #define TEMP_B1_ResetValue (0x00000F71UL)          /*!< Reset value of B1 register.                                          */
74033 
74034 /* B1 @Bits 0..11 : y-intercept of 2nd piece wise linear function */
74035   #define TEMP_B1_B1_Pos (0UL)                       /*!< Position of B1 field.                                                */
74036   #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field.                                                */
74037 
74038 
74039 /* TEMP_B2: y-intercept of 3rd piece wise linear function */
74040   #define TEMP_B2_ResetValue (0x00000F6CUL)          /*!< Reset value of B2 register.                                          */
74041 
74042 /* B2 @Bits 0..11 : y-intercept of 3rd piece wise linear function */
74043   #define TEMP_B2_B2_Pos (0UL)                       /*!< Position of B2 field.                                                */
74044   #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field.                                                */
74045 
74046 
74047 /* TEMP_B3: y-intercept of 4th piece wise linear function */
74048   #define TEMP_B3_ResetValue (0x00000FCBUL)          /*!< Reset value of B3 register.                                          */
74049 
74050 /* B3 @Bits 0..11 : y-intercept of 4th piece wise linear function */
74051   #define TEMP_B3_B3_Pos (0UL)                       /*!< Position of B3 field.                                                */
74052   #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field.                                                */
74053 
74054 
74055 /* TEMP_B4: y-intercept of 5th piece wise linear function */
74056   #define TEMP_B4_ResetValue (0x0000004BUL)          /*!< Reset value of B4 register.                                          */
74057 
74058 /* B4 @Bits 0..11 : y-intercept of 5th piece wise linear function */
74059   #define TEMP_B4_B4_Pos (0UL)                       /*!< Position of B4 field.                                                */
74060   #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field.                                                */
74061 
74062 
74063 /* TEMP_B5: y-intercept of 6th piece wise linear function */
74064   #define TEMP_B5_ResetValue (0x000000F6UL)          /*!< Reset value of B5 register.                                          */
74065 
74066 /* B5 @Bits 0..11 : y-intercept of 6th piece wise linear function */
74067   #define TEMP_B5_B5_Pos (0UL)                       /*!< Position of B5 field.                                                */
74068   #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field.                                                */
74069 
74070 
74071 /* TEMP_B6: y-intercept of 7th piece wise linear function */
74072   #define TEMP_B6_ResetValue (0x000000F6UL)          /*!< Reset value of B6 register.                                          */
74073 
74074 /* B6 @Bits 0..11 : y-intercept of 7th piece wise linear function */
74075   #define TEMP_B6_B6_Pos (0UL)                       /*!< Position of B6 field.                                                */
74076   #define TEMP_B6_B6_Msk (0xFFFUL << TEMP_B6_B6_Pos) /*!< Bit mask of B6 field.                                                */
74077 
74078 
74079 /* TEMP_T0: End point of 1st piece wise linear function */
74080   #define TEMP_T0_ResetValue (0x000000E1UL)          /*!< Reset value of T0 register.                                          */
74081 
74082 /* T0 @Bits 0..7 : End point of 1st piece wise linear function */
74083   #define TEMP_T0_T0_Pos (0UL)                       /*!< Position of T0 field.                                                */
74084   #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos)  /*!< Bit mask of T0 field.                                                */
74085 
74086 
74087 /* TEMP_T1: End point of 2nd piece wise linear function */
74088   #define TEMP_T1_ResetValue (0x000000F9UL)          /*!< Reset value of T1 register.                                          */
74089 
74090 /* T1 @Bits 0..7 : End point of 2nd piece wise linear function */
74091   #define TEMP_T1_T1_Pos (0UL)                       /*!< Position of T1 field.                                                */
74092   #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos)  /*!< Bit mask of T1 field.                                                */
74093 
74094 
74095 /* TEMP_T2: End point of 3rd piece wise linear function */
74096   #define TEMP_T2_ResetValue (0x00000010UL)          /*!< Reset value of T2 register.                                          */
74097 
74098 /* T2 @Bits 0..7 : End point of 3rd piece wise linear function */
74099   #define TEMP_T2_T2_Pos (0UL)                       /*!< Position of T2 field.                                                */
74100   #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos)  /*!< Bit mask of T2 field.                                                */
74101 
74102 
74103 /* TEMP_T3: End point of 4th piece wise linear function */
74104   #define TEMP_T3_ResetValue (0x00000026UL)          /*!< Reset value of T3 register.                                          */
74105 
74106 /* T3 @Bits 0..7 : End point of 4th piece wise linear function */
74107   #define TEMP_T3_T3_Pos (0UL)                       /*!< Position of T3 field.                                                */
74108   #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos)  /*!< Bit mask of T3 field.                                                */
74109 
74110 
74111 /* TEMP_T4: End point of 5th piece wise linear function */
74112   #define TEMP_T4_ResetValue (0x0000003FUL)          /*!< Reset value of T4 register.                                          */
74113 
74114 /* T4 @Bits 0..7 : End point of 5th piece wise linear function */
74115   #define TEMP_T4_T4_Pos (0UL)                       /*!< Position of T4 field.                                                */
74116   #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos)  /*!< Bit mask of T4 field.                                                */
74117 
74118 
74119 /* TEMP_T5: End point of 6th piece wise linear function */
74120   #define TEMP_T5_ResetValue (0x00000078UL)          /*!< Reset value of T5 register.                                          */
74121 
74122 /* T5 @Bits 0..7 : End point of 6th piece wise linear function */
74123   #define TEMP_T5_T5_Pos (0UL)                       /*!< Position of T5 field.                                                */
74124   #define TEMP_T5_T5_Msk (0xFFUL << TEMP_T5_T5_Pos)  /*!< Bit mask of T5 field.                                                */
74125 
74126 
74127 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
74128 
74129 /* =========================================================================================================================== */
74130 /* ================                                           TIMER                                           ================ */
74131 /* =========================================================================================================================== */
74132 
74133 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
74134 /* ====================================================== Struct TIMER ======================================================= */
74135 /**
74136   * @brief Timer/Counter
74137   */
74138   typedef struct {                                   /*!< TIMER Structure                                                      */
74139     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start Timer                                           */
74140     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop Timer                                            */
74141     __OM uint32_t TASKS_COUNT;                       /*!< (@ 0x00000008) Increment Timer (Counter mode only)                   */
74142     __OM uint32_t TASKS_CLEAR;                       /*!< (@ 0x0000000C) Clear time                                            */
74143     __OM uint32_t TASKS_SHUTDOWN;                    /*!< (@ 0x00000010) Shut down timer                                       */
74144     __IM uint32_t RESERVED[11];
74145     __OM uint32_t TASKS_CAPTURE[8];                  /*!< (@ 0x00000040) Capture Timer value to CC[n] register                 */
74146     __IM uint32_t RESERVED1[8];
74147     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
74148     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
74149     __IOM uint32_t SUBSCRIBE_COUNT;                  /*!< (@ 0x00000088) Subscribe configuration for task COUNT                */
74150     __IOM uint32_t SUBSCRIBE_CLEAR;                  /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR                */
74151     __IOM uint32_t SUBSCRIBE_SHUTDOWN;               /*!< (@ 0x00000090) Subscribe configuration for task SHUTDOWN             */
74152     __IM uint32_t RESERVED2[11];
74153     __IOM uint32_t SUBSCRIBE_CAPTURE[8];             /*!< (@ 0x000000C0) Subscribe configuration for task CAPTURE[n]           */
74154     __IM uint32_t RESERVED3[24];
74155     __IOM uint32_t EVENTS_COMPARE[8];                /*!< (@ 0x00000140) Compare event on CC[n] match                          */
74156     __IM uint32_t RESERVED4[24];
74157     __IOM uint32_t PUBLISH_COMPARE[8];               /*!< (@ 0x000001C0) Publish configuration for event COMPARE[n]            */
74158     __IM uint32_t RESERVED5[8];
74159     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
74160     __IM uint32_t RESERVED6[63];
74161     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
74162     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
74163     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
74164     __IM uint32_t RESERVED7[126];
74165     __IOM uint32_t MODE;                             /*!< (@ 0x00000504) Timer mode selection                                  */
74166     __IOM uint32_t BITMODE;                          /*!< (@ 0x00000508) Configure the number of bits used by the TIMER        */
74167     __IM uint32_t RESERVED8;
74168     __IOM uint32_t PRESCALER;                        /*!< (@ 0x00000510) Timer prescaler register                              */
74169     __IM uint32_t RESERVED9[11];
74170     __IOM uint32_t CC[8];                            /*!< (@ 0x00000540) Capture/Compare register n                            */
74171     __IM uint32_t RESERVED10[8];
74172     __IOM uint32_t ONESHOTEN[8];                     /*!< (@ 0x00000580) Enable one-shot operation for Capture/Compare channel
74173                                                                          n*/
74174   } NRF_TIMER_Type;                                  /*!< Size = 1440 (0x5A0)                                                  */
74175 
74176 /* TIMER_TASKS_START: Start Timer */
74177   #define TIMER_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */
74178 
74179 /* TASKS_START @Bit 0 : Start Timer */
74180   #define TIMER_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
74181   #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
74182   #define TIMER_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
74183   #define TIMER_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
74184   #define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */
74185 
74186 
74187 /* TIMER_TASKS_STOP: Stop Timer */
74188   #define TIMER_TASKS_STOP_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOP register.                                  */
74189 
74190 /* TASKS_STOP @Bit 0 : Stop Timer */
74191   #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL)      /*!< Position of TASKS_STOP field.                                        */
74192   #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.        */
74193   #define TIMER_TASKS_STOP_TASKS_STOP_Min (0x1UL)    /*!< Min enumerator value of TASKS_STOP field.                            */
74194   #define TIMER_TASKS_STOP_TASKS_STOP_Max (0x1UL)    /*!< Max enumerator value of TASKS_STOP field.                            */
74195   #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                        */
74196 
74197 
74198 /* TIMER_TASKS_COUNT: Increment Timer (Counter mode only) */
74199   #define TIMER_TASKS_COUNT_ResetValue (0x00000000UL) /*!< Reset value of TASKS_COUNT register.                                */
74200 
74201 /* TASKS_COUNT @Bit 0 : Increment Timer (Counter mode only) */
74202   #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL)    /*!< Position of TASKS_COUNT field.                                       */
74203   #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field.   */
74204   #define TIMER_TASKS_COUNT_TASKS_COUNT_Min (0x1UL)  /*!< Min enumerator value of TASKS_COUNT field.                           */
74205   #define TIMER_TASKS_COUNT_TASKS_COUNT_Max (0x1UL)  /*!< Max enumerator value of TASKS_COUNT field.                           */
74206   #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task                                                      */
74207 
74208 
74209 /* TIMER_TASKS_CLEAR: Clear time */
74210   #define TIMER_TASKS_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CLEAR register.                                */
74211 
74212 /* TASKS_CLEAR @Bit 0 : Clear time */
74213   #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL)    /*!< Position of TASKS_CLEAR field.                                       */
74214   #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field.   */
74215   #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Min (0x1UL)  /*!< Min enumerator value of TASKS_CLEAR field.                           */
74216   #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Max (0x1UL)  /*!< Max enumerator value of TASKS_CLEAR field.                           */
74217   #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task                                                      */
74218 
74219 
74220 /* TIMER_TASKS_SHUTDOWN: Shut down timer */
74221   #define TIMER_TASKS_SHUTDOWN_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SHUTDOWN register.                          */
74222 
74223 /* TASKS_SHUTDOWN @Bit 0 : Shut down timer */
74224   #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field.                                 */
74225   #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of
74226                                                                             TASKS_SHUTDOWN field.*/
74227   #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Min (0x1UL) /*!< Min enumerator value of TASKS_SHUTDOWN field.                   */
74228   #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Max (0x1UL) /*!< Max enumerator value of TASKS_SHUTDOWN field.                   */
74229   #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (0x1UL) /*!< Trigger task                                                */
74230 
74231 
74232 /* TIMER_TASKS_CAPTURE: Capture Timer value to CC[n] register */
74233   #define TIMER_TASKS_CAPTURE_MaxCount (8UL)         /*!< Max size of TASKS_CAPTURE[8] array.                                  */
74234   #define TIMER_TASKS_CAPTURE_MaxIndex (7UL)         /*!< Max index of TASKS_CAPTURE[8] array.                                 */
74235   #define TIMER_TASKS_CAPTURE_MinIndex (0UL)         /*!< Min index of TASKS_CAPTURE[8] array.                                 */
74236   #define TIMER_TASKS_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of TASKS_CAPTURE[8] register.                         */
74237 
74238 /* TASKS_CAPTURE @Bit 0 : Capture Timer value to CC[n] register */
74239   #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field.                                    */
74240   #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE
74241                                                                             field.*/
74242   #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Min (0x1UL) /*!< Min enumerator value of TASKS_CAPTURE field.                      */
74243   #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Max (0x1UL) /*!< Max enumerator value of TASKS_CAPTURE field.                      */
74244   #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task                                                  */
74245 
74246 
74247 /* TIMER_SUBSCRIBE_START: Subscribe configuration for task START */
74248   #define TIMER_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                        */
74249 
74250 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
74251   #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
74252   #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
74253   #define TIMER_SUBSCRIBE_START_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
74254   #define TIMER_SUBSCRIBE_START_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
74255 
74256 /* EN @Bit 31 : (unspecified) */
74257   #define TIMER_SUBSCRIBE_START_EN_Pos (31UL)        /*!< Position of EN field.                                                */
74258   #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                      */
74259   #define TIMER_SUBSCRIBE_START_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
74260   #define TIMER_SUBSCRIBE_START_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
74261   #define TIMER_SUBSCRIBE_START_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
74262   #define TIMER_SUBSCRIBE_START_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
74263 
74264 
74265 /* TIMER_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
74266   #define TIMER_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                          */
74267 
74268 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
74269   #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
74270   #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
74271   #define TIMER_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
74272   #define TIMER_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
74273 
74274 /* EN @Bit 31 : (unspecified) */
74275   #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL)         /*!< Position of EN field.                                                */
74276   #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                        */
74277   #define TIMER_SUBSCRIBE_STOP_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
74278   #define TIMER_SUBSCRIBE_STOP_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
74279   #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0x0UL)   /*!< Disable subscription                                                 */
74280   #define TIMER_SUBSCRIBE_STOP_EN_Enabled (0x1UL)    /*!< Enable subscription                                                  */
74281 
74282 
74283 /* TIMER_SUBSCRIBE_COUNT: Subscribe configuration for task COUNT */
74284   #define TIMER_SUBSCRIBE_COUNT_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_COUNT register.                        */
74285 
74286 /* CHIDX @Bits 0..7 : DPPI channel that task COUNT will subscribe to */
74287   #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
74288   #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
74289   #define TIMER_SUBSCRIBE_COUNT_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
74290   #define TIMER_SUBSCRIBE_COUNT_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
74291 
74292 /* EN @Bit 31 : (unspecified) */
74293   #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL)        /*!< Position of EN field.                                                */
74294   #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field.                      */
74295   #define TIMER_SUBSCRIBE_COUNT_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
74296   #define TIMER_SUBSCRIBE_COUNT_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
74297   #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
74298   #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
74299 
74300 
74301 /* TIMER_SUBSCRIBE_CLEAR: Subscribe configuration for task CLEAR */
74302   #define TIMER_SUBSCRIBE_CLEAR_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CLEAR register.                        */
74303 
74304 /* CHIDX @Bits 0..7 : DPPI channel that task CLEAR will subscribe to */
74305   #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
74306   #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
74307   #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
74308   #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
74309 
74310 /* EN @Bit 31 : (unspecified) */
74311   #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL)        /*!< Position of EN field.                                                */
74312   #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field.                      */
74313   #define TIMER_SUBSCRIBE_CLEAR_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
74314   #define TIMER_SUBSCRIBE_CLEAR_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
74315   #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
74316   #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
74317 
74318 
74319 /* TIMER_SUBSCRIBE_SHUTDOWN: Subscribe configuration for task SHUTDOWN */
74320   #define TIMER_SUBSCRIBE_SHUTDOWN_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SHUTDOWN register.                  */
74321 
74322 /* CHIDX @Bits 0..7 : DPPI channel that task SHUTDOWN will subscribe to */
74323   #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
74324   #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
74325   #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
74326   #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
74327 
74328 /* EN @Bit 31 : (unspecified) */
74329   #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL)     /*!< Position of EN field.                                                */
74330   #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field.                */
74331   #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
74332   #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
74333   #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
74334   #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */
74335 
74336 
74337 /* TIMER_SUBSCRIBE_CAPTURE: Subscribe configuration for task CAPTURE[n] */
74338   #define TIMER_SUBSCRIBE_CAPTURE_MaxCount (8UL)     /*!< Max size of SUBSCRIBE_CAPTURE[8] array.                              */
74339   #define TIMER_SUBSCRIBE_CAPTURE_MaxIndex (7UL)     /*!< Max index of SUBSCRIBE_CAPTURE[8] array.                             */
74340   #define TIMER_SUBSCRIBE_CAPTURE_MinIndex (0UL)     /*!< Min index of SUBSCRIBE_CAPTURE[8] array.                             */
74341   #define TIMER_SUBSCRIBE_CAPTURE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_CAPTURE[8] register.                 */
74342 
74343 /* CHIDX @Bits 0..7 : DPPI channel that task CAPTURE[n] will subscribe to */
74344   #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
74345   #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
74346   #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
74347   #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
74348 
74349 /* EN @Bit 31 : (unspecified) */
74350   #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL)      /*!< Position of EN field.                                                */
74351   #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field.                  */
74352   #define TIMER_SUBSCRIBE_CAPTURE_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
74353   #define TIMER_SUBSCRIBE_CAPTURE_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
74354   #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
74355   #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
74356 
74357 
74358 /* TIMER_EVENTS_COMPARE: Compare event on CC[n] match */
74359   #define TIMER_EVENTS_COMPARE_MaxCount (8UL)        /*!< Max size of EVENTS_COMPARE[8] array.                                 */
74360   #define TIMER_EVENTS_COMPARE_MaxIndex (7UL)        /*!< Max index of EVENTS_COMPARE[8] array.                                */
74361   #define TIMER_EVENTS_COMPARE_MinIndex (0UL)        /*!< Min index of EVENTS_COMPARE[8] array.                                */
74362   #define TIMER_EVENTS_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_COMPARE[8] register.                       */
74363 
74364 /* EVENTS_COMPARE @Bit 0 : Compare event on CC[n] match */
74365   #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field.                                 */
74366   #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of
74367                                                                             EVENTS_COMPARE field.*/
74368   #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Min (0x0UL) /*!< Min enumerator value of EVENTS_COMPARE field.                   */
74369   #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Max (0x1UL) /*!< Max enumerator value of EVENTS_COMPARE field.                   */
74370   #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated                                    */
74371   #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated                                           */
74372 
74373 
74374 /* TIMER_PUBLISH_COMPARE: Publish configuration for event COMPARE[n] */
74375   #define TIMER_PUBLISH_COMPARE_MaxCount (8UL)       /*!< Max size of PUBLISH_COMPARE[8] array.                                */
74376   #define TIMER_PUBLISH_COMPARE_MaxIndex (7UL)       /*!< Max index of PUBLISH_COMPARE[8] array.                               */
74377   #define TIMER_PUBLISH_COMPARE_MinIndex (0UL)       /*!< Min index of PUBLISH_COMPARE[8] array.                               */
74378   #define TIMER_PUBLISH_COMPARE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_COMPARE[8] register.                     */
74379 
74380 /* CHIDX @Bits 0..7 : DPPI channel that event COMPARE[n] will publish to */
74381   #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
74382   #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
74383   #define TIMER_PUBLISH_COMPARE_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
74384   #define TIMER_PUBLISH_COMPARE_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
74385 
74386 /* EN @Bit 31 : (unspecified) */
74387   #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL)        /*!< Position of EN field.                                                */
74388   #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field.                      */
74389   #define TIMER_PUBLISH_COMPARE_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
74390   #define TIMER_PUBLISH_COMPARE_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
74391   #define TIMER_PUBLISH_COMPARE_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
74392   #define TIMER_PUBLISH_COMPARE_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
74393 
74394 
74395 /* TIMER_SHORTS: Shortcuts between local events and tasks */
74396   #define TIMER_SHORTS_ResetValue (0x00000000UL)     /*!< Reset value of SHORTS register.                                      */
74397 
74398 /* COMPARE0_CLEAR @Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
74399   #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL)      /*!< Position of COMPARE0_CLEAR field.                                    */
74400   #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field.    */
74401   #define TIMER_SHORTS_COMPARE0_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE0_CLEAR field.                        */
74402   #define TIMER_SHORTS_COMPARE0_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE0_CLEAR field.                        */
74403   #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
74404   #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */
74405 
74406 /* COMPARE1_CLEAR @Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
74407   #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL)      /*!< Position of COMPARE1_CLEAR field.                                    */
74408   #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field.    */
74409   #define TIMER_SHORTS_COMPARE1_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE1_CLEAR field.                        */
74410   #define TIMER_SHORTS_COMPARE1_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE1_CLEAR field.                        */
74411   #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
74412   #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */
74413 
74414 /* COMPARE2_CLEAR @Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
74415   #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL)      /*!< Position of COMPARE2_CLEAR field.                                    */
74416   #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field.    */
74417   #define TIMER_SHORTS_COMPARE2_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE2_CLEAR field.                        */
74418   #define TIMER_SHORTS_COMPARE2_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE2_CLEAR field.                        */
74419   #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
74420   #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */
74421 
74422 /* COMPARE3_CLEAR @Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
74423   #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL)      /*!< Position of COMPARE3_CLEAR field.                                    */
74424   #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field.    */
74425   #define TIMER_SHORTS_COMPARE3_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE3_CLEAR field.                        */
74426   #define TIMER_SHORTS_COMPARE3_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE3_CLEAR field.                        */
74427   #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
74428   #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */
74429 
74430 /* COMPARE4_CLEAR @Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
74431   #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL)      /*!< Position of COMPARE4_CLEAR field.                                    */
74432   #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field.    */
74433   #define TIMER_SHORTS_COMPARE4_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE4_CLEAR field.                        */
74434   #define TIMER_SHORTS_COMPARE4_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE4_CLEAR field.                        */
74435   #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
74436   #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */
74437 
74438 /* COMPARE5_CLEAR @Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
74439   #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL)      /*!< Position of COMPARE5_CLEAR field.                                    */
74440   #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field.    */
74441   #define TIMER_SHORTS_COMPARE5_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE5_CLEAR field.                        */
74442   #define TIMER_SHORTS_COMPARE5_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE5_CLEAR field.                        */
74443   #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
74444   #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */
74445 
74446 /* COMPARE6_CLEAR @Bit 6 : Shortcut between event COMPARE[6] and task CLEAR */
74447   #define TIMER_SHORTS_COMPARE6_CLEAR_Pos (6UL)      /*!< Position of COMPARE6_CLEAR field.                                    */
74448   #define TIMER_SHORTS_COMPARE6_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE6_CLEAR_Pos) /*!< Bit mask of COMPARE6_CLEAR field.    */
74449   #define TIMER_SHORTS_COMPARE6_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE6_CLEAR field.                        */
74450   #define TIMER_SHORTS_COMPARE6_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE6_CLEAR field.                        */
74451   #define TIMER_SHORTS_COMPARE6_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
74452   #define TIMER_SHORTS_COMPARE6_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */
74453 
74454 /* COMPARE7_CLEAR @Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */
74455   #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL)      /*!< Position of COMPARE7_CLEAR field.                                    */
74456   #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field.    */
74457   #define TIMER_SHORTS_COMPARE7_CLEAR_Min (0x0UL)    /*!< Min enumerator value of COMPARE7_CLEAR field.                        */
74458   #define TIMER_SHORTS_COMPARE7_CLEAR_Max (0x1UL)    /*!< Max enumerator value of COMPARE7_CLEAR field.                        */
74459   #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0x0UL) /*!< Disable shortcut                                                   */
74460   #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (0x1UL) /*!< Enable shortcut                                                     */
74461 
74462 /* COMPARE0_STOP @Bit 16 : Shortcut between event COMPARE[0] and task STOP */
74463   #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL)      /*!< Position of COMPARE0_STOP field.                                     */
74464   #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field.       */
74465   #define TIMER_SHORTS_COMPARE0_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE0_STOP field.                         */
74466   #define TIMER_SHORTS_COMPARE0_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE0_STOP field.                         */
74467   #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
74468   #define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
74469 
74470 /* COMPARE1_STOP @Bit 17 : Shortcut between event COMPARE[1] and task STOP */
74471   #define TIMER_SHORTS_COMPARE1_STOP_Pos (17UL)      /*!< Position of COMPARE1_STOP field.                                     */
74472   #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field.       */
74473   #define TIMER_SHORTS_COMPARE1_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE1_STOP field.                         */
74474   #define TIMER_SHORTS_COMPARE1_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE1_STOP field.                         */
74475   #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
74476   #define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
74477 
74478 /* COMPARE2_STOP @Bit 18 : Shortcut between event COMPARE[2] and task STOP */
74479   #define TIMER_SHORTS_COMPARE2_STOP_Pos (18UL)      /*!< Position of COMPARE2_STOP field.                                     */
74480   #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field.       */
74481   #define TIMER_SHORTS_COMPARE2_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE2_STOP field.                         */
74482   #define TIMER_SHORTS_COMPARE2_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE2_STOP field.                         */
74483   #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
74484   #define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
74485 
74486 /* COMPARE3_STOP @Bit 19 : Shortcut between event COMPARE[3] and task STOP */
74487   #define TIMER_SHORTS_COMPARE3_STOP_Pos (19UL)      /*!< Position of COMPARE3_STOP field.                                     */
74488   #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field.       */
74489   #define TIMER_SHORTS_COMPARE3_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE3_STOP field.                         */
74490   #define TIMER_SHORTS_COMPARE3_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE3_STOP field.                         */
74491   #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
74492   #define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
74493 
74494 /* COMPARE4_STOP @Bit 20 : Shortcut between event COMPARE[4] and task STOP */
74495   #define TIMER_SHORTS_COMPARE4_STOP_Pos (20UL)      /*!< Position of COMPARE4_STOP field.                                     */
74496   #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field.       */
74497   #define TIMER_SHORTS_COMPARE4_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE4_STOP field.                         */
74498   #define TIMER_SHORTS_COMPARE4_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE4_STOP field.                         */
74499   #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
74500   #define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
74501 
74502 /* COMPARE5_STOP @Bit 21 : Shortcut between event COMPARE[5] and task STOP */
74503   #define TIMER_SHORTS_COMPARE5_STOP_Pos (21UL)      /*!< Position of COMPARE5_STOP field.                                     */
74504   #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field.       */
74505   #define TIMER_SHORTS_COMPARE5_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE5_STOP field.                         */
74506   #define TIMER_SHORTS_COMPARE5_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE5_STOP field.                         */
74507   #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
74508   #define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
74509 
74510 /* COMPARE6_STOP @Bit 22 : Shortcut between event COMPARE[6] and task STOP */
74511   #define TIMER_SHORTS_COMPARE6_STOP_Pos (22UL)      /*!< Position of COMPARE6_STOP field.                                     */
74512   #define TIMER_SHORTS_COMPARE6_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE6_STOP_Pos) /*!< Bit mask of COMPARE6_STOP field.       */
74513   #define TIMER_SHORTS_COMPARE6_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE6_STOP field.                         */
74514   #define TIMER_SHORTS_COMPARE6_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE6_STOP field.                         */
74515   #define TIMER_SHORTS_COMPARE6_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
74516   #define TIMER_SHORTS_COMPARE6_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
74517 
74518 /* COMPARE7_STOP @Bit 23 : Shortcut between event COMPARE[7] and task STOP */
74519   #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL)      /*!< Position of COMPARE7_STOP field.                                     */
74520   #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos) /*!< Bit mask of COMPARE7_STOP field.       */
74521   #define TIMER_SHORTS_COMPARE7_STOP_Min (0x0UL)     /*!< Min enumerator value of COMPARE7_STOP field.                         */
74522   #define TIMER_SHORTS_COMPARE7_STOP_Max (0x1UL)     /*!< Max enumerator value of COMPARE7_STOP field.                         */
74523   #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0x0UL) /*!< Disable shortcut                                                    */
74524   #define TIMER_SHORTS_COMPARE7_STOP_Enabled (0x1UL) /*!< Enable shortcut                                                      */
74525 
74526 
74527 /* TIMER_INTEN: Enable or disable interrupt */
74528   #define TIMER_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */
74529 
74530 /* COMPARE0 @Bit 16 : Enable or disable interrupt for event COMPARE[0] */
74531   #define TIMER_INTEN_COMPARE0_Pos (16UL)            /*!< Position of COMPARE0 field.                                          */
74532   #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                        */
74533   #define TIMER_INTEN_COMPARE0_Min (0x0UL)           /*!< Min enumerator value of COMPARE0 field.                              */
74534   #define TIMER_INTEN_COMPARE0_Max (0x1UL)           /*!< Max enumerator value of COMPARE0 field.                              */
74535   #define TIMER_INTEN_COMPARE0_Disabled (0x0UL)      /*!< Disable                                                              */
74536   #define TIMER_INTEN_COMPARE0_Enabled (0x1UL)       /*!< Enable                                                               */
74537 
74538 /* COMPARE1 @Bit 17 : Enable or disable interrupt for event COMPARE[1] */
74539   #define TIMER_INTEN_COMPARE1_Pos (17UL)            /*!< Position of COMPARE1 field.                                          */
74540   #define TIMER_INTEN_COMPARE1_Msk (0x1UL << TIMER_INTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                        */
74541   #define TIMER_INTEN_COMPARE1_Min (0x0UL)           /*!< Min enumerator value of COMPARE1 field.                              */
74542   #define TIMER_INTEN_COMPARE1_Max (0x1UL)           /*!< Max enumerator value of COMPARE1 field.                              */
74543   #define TIMER_INTEN_COMPARE1_Disabled (0x0UL)      /*!< Disable                                                              */
74544   #define TIMER_INTEN_COMPARE1_Enabled (0x1UL)       /*!< Enable                                                               */
74545 
74546 /* COMPARE2 @Bit 18 : Enable or disable interrupt for event COMPARE[2] */
74547   #define TIMER_INTEN_COMPARE2_Pos (18UL)            /*!< Position of COMPARE2 field.                                          */
74548   #define TIMER_INTEN_COMPARE2_Msk (0x1UL << TIMER_INTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                        */
74549   #define TIMER_INTEN_COMPARE2_Min (0x0UL)           /*!< Min enumerator value of COMPARE2 field.                              */
74550   #define TIMER_INTEN_COMPARE2_Max (0x1UL)           /*!< Max enumerator value of COMPARE2 field.                              */
74551   #define TIMER_INTEN_COMPARE2_Disabled (0x0UL)      /*!< Disable                                                              */
74552   #define TIMER_INTEN_COMPARE2_Enabled (0x1UL)       /*!< Enable                                                               */
74553 
74554 /* COMPARE3 @Bit 19 : Enable or disable interrupt for event COMPARE[3] */
74555   #define TIMER_INTEN_COMPARE3_Pos (19UL)            /*!< Position of COMPARE3 field.                                          */
74556   #define TIMER_INTEN_COMPARE3_Msk (0x1UL << TIMER_INTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                        */
74557   #define TIMER_INTEN_COMPARE3_Min (0x0UL)           /*!< Min enumerator value of COMPARE3 field.                              */
74558   #define TIMER_INTEN_COMPARE3_Max (0x1UL)           /*!< Max enumerator value of COMPARE3 field.                              */
74559   #define TIMER_INTEN_COMPARE3_Disabled (0x0UL)      /*!< Disable                                                              */
74560   #define TIMER_INTEN_COMPARE3_Enabled (0x1UL)       /*!< Enable                                                               */
74561 
74562 /* COMPARE4 @Bit 20 : Enable or disable interrupt for event COMPARE[4] */
74563   #define TIMER_INTEN_COMPARE4_Pos (20UL)            /*!< Position of COMPARE4 field.                                          */
74564   #define TIMER_INTEN_COMPARE4_Msk (0x1UL << TIMER_INTEN_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                        */
74565   #define TIMER_INTEN_COMPARE4_Min (0x0UL)           /*!< Min enumerator value of COMPARE4 field.                              */
74566   #define TIMER_INTEN_COMPARE4_Max (0x1UL)           /*!< Max enumerator value of COMPARE4 field.                              */
74567   #define TIMER_INTEN_COMPARE4_Disabled (0x0UL)      /*!< Disable                                                              */
74568   #define TIMER_INTEN_COMPARE4_Enabled (0x1UL)       /*!< Enable                                                               */
74569 
74570 /* COMPARE5 @Bit 21 : Enable or disable interrupt for event COMPARE[5] */
74571   #define TIMER_INTEN_COMPARE5_Pos (21UL)            /*!< Position of COMPARE5 field.                                          */
74572   #define TIMER_INTEN_COMPARE5_Msk (0x1UL << TIMER_INTEN_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                        */
74573   #define TIMER_INTEN_COMPARE5_Min (0x0UL)           /*!< Min enumerator value of COMPARE5 field.                              */
74574   #define TIMER_INTEN_COMPARE5_Max (0x1UL)           /*!< Max enumerator value of COMPARE5 field.                              */
74575   #define TIMER_INTEN_COMPARE5_Disabled (0x0UL)      /*!< Disable                                                              */
74576   #define TIMER_INTEN_COMPARE5_Enabled (0x1UL)       /*!< Enable                                                               */
74577 
74578 /* COMPARE6 @Bit 22 : Enable or disable interrupt for event COMPARE[6] */
74579   #define TIMER_INTEN_COMPARE6_Pos (22UL)            /*!< Position of COMPARE6 field.                                          */
74580   #define TIMER_INTEN_COMPARE6_Msk (0x1UL << TIMER_INTEN_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                        */
74581   #define TIMER_INTEN_COMPARE6_Min (0x0UL)           /*!< Min enumerator value of COMPARE6 field.                              */
74582   #define TIMER_INTEN_COMPARE6_Max (0x1UL)           /*!< Max enumerator value of COMPARE6 field.                              */
74583   #define TIMER_INTEN_COMPARE6_Disabled (0x0UL)      /*!< Disable                                                              */
74584   #define TIMER_INTEN_COMPARE6_Enabled (0x1UL)       /*!< Enable                                                               */
74585 
74586 /* COMPARE7 @Bit 23 : Enable or disable interrupt for event COMPARE[7] */
74587   #define TIMER_INTEN_COMPARE7_Pos (23UL)            /*!< Position of COMPARE7 field.                                          */
74588   #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                        */
74589   #define TIMER_INTEN_COMPARE7_Min (0x0UL)           /*!< Min enumerator value of COMPARE7 field.                              */
74590   #define TIMER_INTEN_COMPARE7_Max (0x1UL)           /*!< Max enumerator value of COMPARE7 field.                              */
74591   #define TIMER_INTEN_COMPARE7_Disabled (0x0UL)      /*!< Disable                                                              */
74592   #define TIMER_INTEN_COMPARE7_Enabled (0x1UL)       /*!< Enable                                                               */
74593 
74594 
74595 /* TIMER_INTENSET: Enable interrupt */
74596   #define TIMER_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */
74597 
74598 /* COMPARE0 @Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
74599   #define TIMER_INTENSET_COMPARE0_Pos (16UL)         /*!< Position of COMPARE0 field.                                          */
74600   #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
74601   #define TIMER_INTENSET_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
74602   #define TIMER_INTENSET_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
74603   #define TIMER_INTENSET_COMPARE0_Set (0x1UL)        /*!< Enable                                                               */
74604   #define TIMER_INTENSET_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74605   #define TIMER_INTENSET_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74606 
74607 /* COMPARE1 @Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
74608   #define TIMER_INTENSET_COMPARE1_Pos (17UL)         /*!< Position of COMPARE1 field.                                          */
74609   #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
74610   #define TIMER_INTENSET_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
74611   #define TIMER_INTENSET_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
74612   #define TIMER_INTENSET_COMPARE1_Set (0x1UL)        /*!< Enable                                                               */
74613   #define TIMER_INTENSET_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74614   #define TIMER_INTENSET_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74615 
74616 /* COMPARE2 @Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
74617   #define TIMER_INTENSET_COMPARE2_Pos (18UL)         /*!< Position of COMPARE2 field.                                          */
74618   #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
74619   #define TIMER_INTENSET_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
74620   #define TIMER_INTENSET_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
74621   #define TIMER_INTENSET_COMPARE2_Set (0x1UL)        /*!< Enable                                                               */
74622   #define TIMER_INTENSET_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74623   #define TIMER_INTENSET_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74624 
74625 /* COMPARE3 @Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
74626   #define TIMER_INTENSET_COMPARE3_Pos (19UL)         /*!< Position of COMPARE3 field.                                          */
74627   #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
74628   #define TIMER_INTENSET_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
74629   #define TIMER_INTENSET_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
74630   #define TIMER_INTENSET_COMPARE3_Set (0x1UL)        /*!< Enable                                                               */
74631   #define TIMER_INTENSET_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74632   #define TIMER_INTENSET_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74633 
74634 /* COMPARE4 @Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
74635   #define TIMER_INTENSET_COMPARE4_Pos (20UL)         /*!< Position of COMPARE4 field.                                          */
74636   #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
74637   #define TIMER_INTENSET_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
74638   #define TIMER_INTENSET_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
74639   #define TIMER_INTENSET_COMPARE4_Set (0x1UL)        /*!< Enable                                                               */
74640   #define TIMER_INTENSET_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74641   #define TIMER_INTENSET_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74642 
74643 /* COMPARE5 @Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
74644   #define TIMER_INTENSET_COMPARE5_Pos (21UL)         /*!< Position of COMPARE5 field.                                          */
74645   #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
74646   #define TIMER_INTENSET_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
74647   #define TIMER_INTENSET_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
74648   #define TIMER_INTENSET_COMPARE5_Set (0x1UL)        /*!< Enable                                                               */
74649   #define TIMER_INTENSET_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74650   #define TIMER_INTENSET_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74651 
74652 /* COMPARE6 @Bit 22 : Write '1' to enable interrupt for event COMPARE[6] */
74653   #define TIMER_INTENSET_COMPARE6_Pos (22UL)         /*!< Position of COMPARE6 field.                                          */
74654   #define TIMER_INTENSET_COMPARE6_Msk (0x1UL << TIMER_INTENSET_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
74655   #define TIMER_INTENSET_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
74656   #define TIMER_INTENSET_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
74657   #define TIMER_INTENSET_COMPARE6_Set (0x1UL)        /*!< Enable                                                               */
74658   #define TIMER_INTENSET_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74659   #define TIMER_INTENSET_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74660 
74661 /* COMPARE7 @Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */
74662   #define TIMER_INTENSET_COMPARE7_Pos (23UL)         /*!< Position of COMPARE7 field.                                          */
74663   #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
74664   #define TIMER_INTENSET_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
74665   #define TIMER_INTENSET_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
74666   #define TIMER_INTENSET_COMPARE7_Set (0x1UL)        /*!< Enable                                                               */
74667   #define TIMER_INTENSET_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74668   #define TIMER_INTENSET_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74669 
74670 
74671 /* TIMER_INTENCLR: Disable interrupt */
74672   #define TIMER_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */
74673 
74674 /* COMPARE0 @Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
74675   #define TIMER_INTENCLR_COMPARE0_Pos (16UL)         /*!< Position of COMPARE0 field.                                          */
74676   #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field.                  */
74677   #define TIMER_INTENCLR_COMPARE0_Min (0x0UL)        /*!< Min enumerator value of COMPARE0 field.                              */
74678   #define TIMER_INTENCLR_COMPARE0_Max (0x1UL)        /*!< Max enumerator value of COMPARE0 field.                              */
74679   #define TIMER_INTENCLR_COMPARE0_Clear (0x1UL)      /*!< Disable                                                              */
74680   #define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74681   #define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74682 
74683 /* COMPARE1 @Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
74684   #define TIMER_INTENCLR_COMPARE1_Pos (17UL)         /*!< Position of COMPARE1 field.                                          */
74685   #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field.                  */
74686   #define TIMER_INTENCLR_COMPARE1_Min (0x0UL)        /*!< Min enumerator value of COMPARE1 field.                              */
74687   #define TIMER_INTENCLR_COMPARE1_Max (0x1UL)        /*!< Max enumerator value of COMPARE1 field.                              */
74688   #define TIMER_INTENCLR_COMPARE1_Clear (0x1UL)      /*!< Disable                                                              */
74689   #define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74690   #define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74691 
74692 /* COMPARE2 @Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
74693   #define TIMER_INTENCLR_COMPARE2_Pos (18UL)         /*!< Position of COMPARE2 field.                                          */
74694   #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field.                  */
74695   #define TIMER_INTENCLR_COMPARE2_Min (0x0UL)        /*!< Min enumerator value of COMPARE2 field.                              */
74696   #define TIMER_INTENCLR_COMPARE2_Max (0x1UL)        /*!< Max enumerator value of COMPARE2 field.                              */
74697   #define TIMER_INTENCLR_COMPARE2_Clear (0x1UL)      /*!< Disable                                                              */
74698   #define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74699   #define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74700 
74701 /* COMPARE3 @Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
74702   #define TIMER_INTENCLR_COMPARE3_Pos (19UL)         /*!< Position of COMPARE3 field.                                          */
74703   #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field.                  */
74704   #define TIMER_INTENCLR_COMPARE3_Min (0x0UL)        /*!< Min enumerator value of COMPARE3 field.                              */
74705   #define TIMER_INTENCLR_COMPARE3_Max (0x1UL)        /*!< Max enumerator value of COMPARE3 field.                              */
74706   #define TIMER_INTENCLR_COMPARE3_Clear (0x1UL)      /*!< Disable                                                              */
74707   #define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74708   #define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74709 
74710 /* COMPARE4 @Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
74711   #define TIMER_INTENCLR_COMPARE4_Pos (20UL)         /*!< Position of COMPARE4 field.                                          */
74712   #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field.                  */
74713   #define TIMER_INTENCLR_COMPARE4_Min (0x0UL)        /*!< Min enumerator value of COMPARE4 field.                              */
74714   #define TIMER_INTENCLR_COMPARE4_Max (0x1UL)        /*!< Max enumerator value of COMPARE4 field.                              */
74715   #define TIMER_INTENCLR_COMPARE4_Clear (0x1UL)      /*!< Disable                                                              */
74716   #define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74717   #define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74718 
74719 /* COMPARE5 @Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
74720   #define TIMER_INTENCLR_COMPARE5_Pos (21UL)         /*!< Position of COMPARE5 field.                                          */
74721   #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field.                  */
74722   #define TIMER_INTENCLR_COMPARE5_Min (0x0UL)        /*!< Min enumerator value of COMPARE5 field.                              */
74723   #define TIMER_INTENCLR_COMPARE5_Max (0x1UL)        /*!< Max enumerator value of COMPARE5 field.                              */
74724   #define TIMER_INTENCLR_COMPARE5_Clear (0x1UL)      /*!< Disable                                                              */
74725   #define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74726   #define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74727 
74728 /* COMPARE6 @Bit 22 : Write '1' to disable interrupt for event COMPARE[6] */
74729   #define TIMER_INTENCLR_COMPARE6_Pos (22UL)         /*!< Position of COMPARE6 field.                                          */
74730   #define TIMER_INTENCLR_COMPARE6_Msk (0x1UL << TIMER_INTENCLR_COMPARE6_Pos) /*!< Bit mask of COMPARE6 field.                  */
74731   #define TIMER_INTENCLR_COMPARE6_Min (0x0UL)        /*!< Min enumerator value of COMPARE6 field.                              */
74732   #define TIMER_INTENCLR_COMPARE6_Max (0x1UL)        /*!< Max enumerator value of COMPARE6 field.                              */
74733   #define TIMER_INTENCLR_COMPARE6_Clear (0x1UL)      /*!< Disable                                                              */
74734   #define TIMER_INTENCLR_COMPARE6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74735   #define TIMER_INTENCLR_COMPARE6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74736 
74737 /* COMPARE7 @Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */
74738   #define TIMER_INTENCLR_COMPARE7_Pos (23UL)         /*!< Position of COMPARE7 field.                                          */
74739   #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field.                  */
74740   #define TIMER_INTENCLR_COMPARE7_Min (0x0UL)        /*!< Min enumerator value of COMPARE7 field.                              */
74741   #define TIMER_INTENCLR_COMPARE7_Max (0x1UL)        /*!< Max enumerator value of COMPARE7 field.                              */
74742   #define TIMER_INTENCLR_COMPARE7_Clear (0x1UL)      /*!< Disable                                                              */
74743   #define TIMER_INTENCLR_COMPARE7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
74744   #define TIMER_INTENCLR_COMPARE7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
74745 
74746 
74747 /* TIMER_MODE: Timer mode selection */
74748   #define TIMER_MODE_ResetValue (0x00000000UL)       /*!< Reset value of MODE register.                                        */
74749 
74750 /* MODE @Bits 0..1 : Timer mode */
74751   #define TIMER_MODE_MODE_Pos (0UL)                  /*!< Position of MODE field.                                              */
74752   #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field.                                      */
74753   #define TIMER_MODE_MODE_Min (0x0UL)                /*!< Min enumerator value of MODE field.                                  */
74754   #define TIMER_MODE_MODE_Max (0x2UL)                /*!< Max enumerator value of MODE field.                                  */
74755   #define TIMER_MODE_MODE_Timer (0x0UL)              /*!< Select Timer mode                                                    */
74756   #define TIMER_MODE_MODE_Counter (0x1UL)            /*!< Select Counter mode                                                  */
74757   #define TIMER_MODE_MODE_LowPowerCounter (0x2UL)    /*!< Select Low Power Counter mode                                        */
74758 
74759 
74760 /* TIMER_BITMODE: Configure the number of bits used by the TIMER */
74761   #define TIMER_BITMODE_ResetValue (0x00000000UL)    /*!< Reset value of BITMODE register.                                     */
74762 
74763 /* BITMODE @Bits 0..1 : Timer bit width */
74764   #define TIMER_BITMODE_BITMODE_Pos (0UL)            /*!< Position of BITMODE field.                                           */
74765   #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field.                       */
74766   #define TIMER_BITMODE_BITMODE_Min (0x0UL)          /*!< Min enumerator value of BITMODE field.                               */
74767   #define TIMER_BITMODE_BITMODE_Max (0x3UL)          /*!< Max enumerator value of BITMODE field.                               */
74768   #define TIMER_BITMODE_BITMODE_16Bit (0x0UL)        /*!< 16 bit timer bit width                                               */
74769   #define TIMER_BITMODE_BITMODE_08Bit (0x1UL)        /*!< 8 bit timer bit width                                                */
74770   #define TIMER_BITMODE_BITMODE_24Bit (0x2UL)        /*!< 24 bit timer bit width                                               */
74771   #define TIMER_BITMODE_BITMODE_32Bit (0x3UL)        /*!< 32 bit timer bit width                                               */
74772 
74773 
74774 /* TIMER_PRESCALER: Timer prescaler register */
74775   #define TIMER_PRESCALER_ResetValue (0x00000004UL)  /*!< Reset value of PRESCALER register.                                   */
74776 
74777 /* PRESCALER @Bits 0..3 : Prescaler value */
74778   #define TIMER_PRESCALER_PRESCALER_Pos (0UL)        /*!< Position of PRESCALER field.                                         */
74779   #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field.             */
74780   #define TIMER_PRESCALER_PRESCALER_Min (0x0UL)      /*!< Min value of PRESCALER field.                                        */
74781   #define TIMER_PRESCALER_PRESCALER_Max (0x9UL)      /*!< Max size of PRESCALER field.                                         */
74782 
74783 
74784 /* TIMER_CC: Capture/Compare register n */
74785   #define TIMER_CC_MaxCount (8UL)                    /*!< Max size of CC[8] array.                                             */
74786   #define TIMER_CC_MaxIndex (7UL)                    /*!< Max index of CC[8] array.                                            */
74787   #define TIMER_CC_MinIndex (0UL)                    /*!< Min index of CC[8] array.                                            */
74788   #define TIMER_CC_ResetValue (0x00000000UL)         /*!< Reset value of CC[8] register.                                       */
74789 
74790 /* CC @Bits 0..31 : Capture/Compare value */
74791   #define TIMER_CC_CC_Pos (0UL)                      /*!< Position of CC field.                                                */
74792   #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field.                                         */
74793 
74794 
74795 /* TIMER_ONESHOTEN: Enable one-shot operation for Capture/Compare channel n */
74796   #define TIMER_ONESHOTEN_MaxCount (8UL)             /*!< Max size of ONESHOTEN[8] array.                                      */
74797   #define TIMER_ONESHOTEN_MaxIndex (7UL)             /*!< Max index of ONESHOTEN[8] array.                                     */
74798   #define TIMER_ONESHOTEN_MinIndex (0UL)             /*!< Min index of ONESHOTEN[8] array.                                     */
74799   #define TIMER_ONESHOTEN_ResetValue (0x00000000UL)  /*!< Reset value of ONESHOTEN[8] register.                                */
74800 
74801 /* ONESHOTEN @Bit 0 : Enable one-shot operation */
74802   #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL)        /*!< Position of ONESHOTEN field.                                         */
74803   #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field.             */
74804   #define TIMER_ONESHOTEN_ONESHOTEN_Min (0x0UL)      /*!< Min enumerator value of ONESHOTEN field.                             */
74805   #define TIMER_ONESHOTEN_ONESHOTEN_Max (0x1UL)      /*!< Max enumerator value of ONESHOTEN field.                             */
74806   #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0x0UL)  /*!< Disable one-shot operation                                           */
74807   #define TIMER_ONESHOTEN_ONESHOTEN_Enable (0x1UL)   /*!< Enable one-shot operation                                            */
74808 
74809 
74810 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
74811 
74812 /* =========================================================================================================================== */
74813 /* ================                                           TPIU                                           ================ */
74814 /* =========================================================================================================================== */
74815 
74816 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
74817 /* ======================================================= Struct TPIU ======================================================= */
74818 /**
74819   * @brief Trace Port Interface Unit
74820   */
74821   typedef struct {                                   /*!< TPIU Structure                                                       */
74822     __IOM uint32_t SUPPORTEDPORTSIZES;               /*!< (@ 0x00000000) Each bit location is a single port size that is
74823                                                                          supported on the device.*/
74824     __IOM uint32_t CURRENTPORTSIZE;                  /*!< (@ 0x00000004) Each bit location is a single port size. One bit can be
74825                                                                          set, and indicates the current port size.*/
74826     __IM uint32_t RESERVED[62];
74827     __IOM uint32_t SUPPORTEDTRIGGERMODES;            /*!< (@ 0x00000100) The Supported_trigger_modes register indicates the
74828                                                                          implemented trigger counter multipliers and other
74829                                                                          supported features of the trigger system.*/
74830     __IOM uint32_t TRIGGERCOUNTERVALUE;              /*!< (@ 0x00000104) The Trigger_counter_value register enables delaying the
74831                                                                          indication of triggers to any external connected trace
74832                                                                          capture or storage devices.*/
74833     __IOM uint32_t TRIGGERMULTIPLIER;                /*!< (@ 0x00000108) The Trigger_multiplier register contains the selectors
74834                                                                          for the trigger counter multiplier.*/
74835     __IM uint32_t RESERVED1[61];
74836     __IOM uint32_t SUPPPORTEDTESTPATTERNMODES;       /*!< (@ 0x00000200) The Supported_test_pattern_modes register provides a
74837                                                                          set of known bit sequences or patterns that can be
74838                                                                          output over the trace port and can be detected by the
74839                                                                          TPA or other associated trace capture device.*/
74840     __IOM uint32_t CURRENTTESTPATTERNMODES;          /*!< (@ 0x00000204) Current_test_pattern_mode indicates the current test
74841                                                                          pattern or mode selected.*/
74842     __IOM uint32_t TPRCR;                            /*!< (@ 0x00000208) The TPRCR register is an 8-bit counter start value that
74843                                                                          is decremented. A write sets the initial counter value
74844                                                                          and a read returns the programmed value.*/
74845     __IM uint32_t RESERVED2[61];
74846     __IOM uint32_t FFSR;                             /*!< (@ 0x00000300) The FFSR register indicates the current status of the
74847                                                                          formatter and flush features available in the TPIU.*/
74848     __IOM uint32_t FFCR;                             /*!< (@ 0x00000304) The FFCR register controls the generation of stop,
74849                                                                          trigger, and flush events.*/
74850     __IOM uint32_t FSCR;                             /*!< (@ 0x00000308) The FSCR register enables the frequency of
74851                                                                          synchronization information to be optimized to suit the
74852                                                                          Trace Port Analyzer (TPA) capture buffer size.*/
74853     __IM uint32_t RESERVED3[61];
74854     __IOM uint32_t EXTCTLINPORT;                     /*!< (@ 0x00000400) Two ports can be used as a control and feedback
74855                                                                          mechanism for any serializers, pin sharing
74856                                                                          multiplexers, or other solutions that might be added to
74857                                                                          the trace output pins either for pin control or a
74858                                                                          high-speed trace port solution.*/
74859     __IOM uint32_t EXTCTLOUTPORT;                    /*!< (@ 0x00000404) Two ports can be used as a control and feedback
74860                                                                          mechanism for any serializers, pin sharing
74861                                                                          multiplexers, or other solutions that might be added to
74862                                                                          the trace output pins either for pin control or a high
74863                                                                          speed trace port solution. These ports are raw register
74864                                                                          banks that sample or export the corresponding external
74865                                                                          pins.*/
74866     __IM uint32_t RESERVED4[695];
74867     __IOM uint32_t ITTRFLINACK;                      /*!< (@ 0x00000EE4) The ITTRFLINACK register enables control of the
74868                                                                          triginack and flushinack outputs from the TPIU.*/
74869     __IOM uint32_t ITTRFLIN;                         /*!< (@ 0x00000EE8) The ITTRFLIN register contains the values of the
74870                                                                          flushin and trigin inputs to the TPIU.*/
74871     __IOM uint32_t ITATBDATA0;                       /*!< (@ 0x00000EEC) The ITATBDATA0 register contains the value of the
74872                                                                          atdatas inputs to the TPIU. The values are valid only
74873                                                                          when atvalids is HIGH.*/
74874     __IOM uint32_t ITATBCTR2;                        /*!< (@ 0x00000EF0) Enables control of the atreadys and afvalids outputs of
74875                                                                          the TPIU.*/
74876     __IOM uint32_t ITATBCTR1;                        /*!< (@ 0x00000EF4) The ITATBCTR1 register contains the value of the atids
74877                                                                          input to the TPIU. This is only valid when atvalids is
74878                                                                          HIGH.*/
74879     __IOM uint32_t ITATBCTR0;                        /*!< (@ 0x00000EF8) The ITATBCTR0 register captures the values of the
74880                                                                          atvalids, afreadys, and atbytess inputs to the TPIU. To
74881                                                                          ensure the integration registers work correctly in a
74882                                                                          system, the value of atbytess is only valid when
74883                                                                          atvalids, bit[0], is HIGH.*/
74884     __IM uint32_t RESERVED5;
74885     __IOM uint32_t ITCTRL;                           /*!< (@ 0x00000F00) Used to enable topology detection. This register
74886                                                                          enables the component to switch from a functional mode,
74887                                                                          the default behavior, to integration mode where the
74888                                                                          inputs and outputs of the component can be directly
74889                                                                          controlled for integration testing and topology
74890                                                                          solving.*/
74891     __IM uint32_t RESERVED6[39];
74892     __IOM uint32_t CLAIMSET;                         /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate
74893                                                                          application and debugger access to trace unit
74894                                                                          functionality. The claim tags have no effect on the
74895                                                                          operation of the component. The CLAIMSET register sets
74896                                                                          bits in the claim tag, and determines the number of
74897                                                                          claim bits implemented.*/
74898     __IOM uint32_t CLAIMCLR;                         /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate
74899                                                                          application and debugger access to trace unit
74900                                                                          functionality. The claim tags have no effect on the
74901                                                                          operation of the component. The CLAIMCLR register sets
74902                                                                          the bits in the claim tag to 0 and determines the
74903                                                                          current value of the claim tag.*/
74904     __IM uint32_t RESERVED7[2];
74905     __IOM uint32_t LAR;                              /*!< (@ 0x00000FB0) This is used to enable write access to device
74906                                                                          registers.*/
74907     __IOM uint32_t LSR;                              /*!< (@ 0x00000FB4) This indicates the status of the lock control
74908                                                                          mechanism. This lock prevents accidental writes by code
74909                                                                          under debug. Accesses to the extended stimulus port
74910                                                                          registers are not affected by the lock mechanism. This
74911                                                                          register must always be present although there might
74912                                                                          not be any lock access control mechanism. The lock
74913                                                                          mechanism, where present and locked, must block write
74914                                                                          accesses to any control register, except the Lock
74915                                                                          Access Register. For most components this covers all
74916                                                                          registers except for the Lock Access Register.*/
74917     __IOM uint32_t AUTHSTATUS;                       /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted by the
74918                                                                          system*/
74919     __IM uint32_t RESERVED8[3];
74920     __IM uint32_t DEVID;                             /*!< (@ 0x00000FC8) Indicates the capabilities of the component.          */
74921     __IM uint32_t DEVTYPE;                           /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with
74922                                                                          information about the component when the Part Number
74923                                                                          field is not recognized. The debugger can then report
74924                                                                          this information.*/
74925     __IOM uint32_t PIDR4;                            /*!< (@ 0x00000FD0) Coresight peripheral identification registers.        */
74926     __IM uint32_t RESERVED9[3];
74927     __IOM uint32_t PIDR0;                            /*!< (@ 0x00000FE0) Coresight peripheral identification registers.        */
74928     __IOM uint32_t PIDR1;                            /*!< (@ 0x00000FE4) Coresight peripheral identification registers.        */
74929     __IOM uint32_t PIDR2;                            /*!< (@ 0x00000FE8) Coresight peripheral identification registers.        */
74930     __IOM uint32_t PIDR3;                            /*!< (@ 0x00000FEC) Coresight peripheral identification registers.        */
74931     __IOM uint32_t CIDR0;                            /*!< (@ 0x00000FF0) Coresight component identification registers.         */
74932     __IOM uint32_t CIDR1;                            /*!< (@ 0x00000FF4) Coresight component identification registers.         */
74933     __IOM uint32_t CIDR2;                            /*!< (@ 0x00000FF8) Coresight component identification registers.         */
74934     __IOM uint32_t CIDR3;                            /*!< (@ 0x00000FFC) Coresight component identification registers.         */
74935   } NRF_TPIU_Type;                                   /*!< Size = 4096 (0x1000)                                                 */
74936 
74937 /* TPIU_SUPPORTEDPORTSIZES: Each bit location is a single port size that is supported on the device. */
74938   #define TPIU_SUPPORTEDPORTSIZES_ResetValue (0x00000000UL) /*!< Reset value of SUPPORTEDPORTSIZES register.                   */
74939 
74940 /* PORT_SIZE_1 @Bit 0 : Indicates whether the TPIU supports port size of 1-bit. */
74941   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Pos (0UL) /*!< Position of PORT_SIZE_1 field.                                    */
74942   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Pos) /*!< Bit mask of
74943                                                                             PORT_SIZE_1 field.*/
74944   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_1 field.                      */
74945   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_1 field.                      */
74946   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_NotSupported (0x0UL) /*!< Port size 1 is not supported.                          */
74947   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Supported (0x1UL) /*!< Port size 1 is supported.                                 */
74948 
74949 /* PORT_SIZE_2 @Bit 1 : Indicates whether the TPIU supports port size of 2-bit. */
74950   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Pos (1UL) /*!< Position of PORT_SIZE_2 field.                                    */
74951   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Pos) /*!< Bit mask of
74952                                                                             PORT_SIZE_2 field.*/
74953   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_2 field.                      */
74954   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_2 field.                      */
74955   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_NotSupported (0x0UL) /*!< Port size 2 is not supported.                          */
74956   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Supported (0x1UL) /*!< Port size 2 is supported.                                 */
74957 
74958 /* PORT_SIZE_3 @Bit 2 : Indicates whether the TPIU supports port size of 3-bit. */
74959   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Pos (2UL) /*!< Position of PORT_SIZE_3 field.                                    */
74960   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Pos) /*!< Bit mask of
74961                                                                             PORT_SIZE_3 field.*/
74962   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_3 field.                      */
74963   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_3 field.                      */
74964   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_NotSupported (0x0UL) /*!< Port size 3 is not supported.                          */
74965   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Supported (0x1UL) /*!< Port size 3 is supported.                                 */
74966 
74967 /* PORT_SIZE_4 @Bit 3 : Indicates whether the TPIU supports port size of 4-bit. */
74968   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Pos (3UL) /*!< Position of PORT_SIZE_4 field.                                    */
74969   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Pos) /*!< Bit mask of
74970                                                                             PORT_SIZE_4 field.*/
74971   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_4 field.                      */
74972   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_4 field.                      */
74973   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_NotSupported (0x0UL) /*!< Port size 4 is not supported.                          */
74974   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Supported (0x1UL) /*!< Port size 4 is supported.                                 */
74975 
74976 /* PORT_SIZE_5 @Bit 4 : Indicates whether the TPIU supports port size of 5-bit. */
74977   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Pos (4UL) /*!< Position of PORT_SIZE_5 field.                                    */
74978   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Pos) /*!< Bit mask of
74979                                                                             PORT_SIZE_5 field.*/
74980   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_5 field.                      */
74981   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_5 field.                      */
74982   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_NotSupported (0x0UL) /*!< Port size 5 is not supported.                          */
74983   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Supported (0x1UL) /*!< Port size 5 is supported.                                 */
74984 
74985 /* PORT_SIZE_6 @Bit 5 : Indicates whether the TPIU supports port size of 6-bit. */
74986   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Pos (5UL) /*!< Position of PORT_SIZE_6 field.                                    */
74987   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Pos) /*!< Bit mask of
74988                                                                             PORT_SIZE_6 field.*/
74989   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_6 field.                      */
74990   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_6 field.                      */
74991   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_NotSupported (0x0UL) /*!< Port size 6 is not supported.                          */
74992   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Supported (0x1UL) /*!< Port size 6 is supported.                                 */
74993 
74994 /* PORT_SIZE_7 @Bit 6 : Indicates whether the TPIU supports port size of 7-bit. */
74995   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Pos (6UL) /*!< Position of PORT_SIZE_7 field.                                    */
74996   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Pos) /*!< Bit mask of
74997                                                                             PORT_SIZE_7 field.*/
74998   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_7 field.                      */
74999   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_7 field.                      */
75000   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_NotSupported (0x0UL) /*!< Port size 7 is not supported.                          */
75001   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Supported (0x1UL) /*!< Port size 7 is supported.                                 */
75002 
75003 /* PORT_SIZE_8 @Bit 7 : Indicates whether the TPIU supports port size of 8-bit. */
75004   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Pos (7UL) /*!< Position of PORT_SIZE_8 field.                                    */
75005   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Pos) /*!< Bit mask of
75006                                                                             PORT_SIZE_8 field.*/
75007   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_8 field.                      */
75008   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_8 field.                      */
75009   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_NotSupported (0x0UL) /*!< Port size 8 is not supported.                          */
75010   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Supported (0x1UL) /*!< Port size 8 is supported.                                 */
75011 
75012 /* PORT_SIZE_9 @Bit 8 : Indicates whether the TPIU supports port size of 9-bit. */
75013   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Pos (8UL) /*!< Position of PORT_SIZE_9 field.                                    */
75014   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Pos) /*!< Bit mask of
75015                                                                             PORT_SIZE_9 field.*/
75016   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_9 field.                      */
75017   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_9 field.                      */
75018   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_NotSupported (0x0UL) /*!< Port size 9 is not supported.                          */
75019   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Supported (0x1UL) /*!< Port size 9 is supported.                                 */
75020 
75021 /* PORT_SIZE_10 @Bit 9 : Indicates whether the TPIU supports port size of 10-bit. */
75022   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Pos (9UL) /*!< Position of PORT_SIZE_10 field.                                  */
75023   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Pos) /*!< Bit mask of
75024                                                                             PORT_SIZE_10 field.*/
75025   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_10 field.                    */
75026   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_10 field.                    */
75027   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_NotSupported (0x0UL) /*!< Port size 10 is not supported.                        */
75028   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Supported (0x1UL) /*!< Port size 10 is supported.                               */
75029 
75030 /* PORT_SIZE_11 @Bit 10 : Indicates whether the TPIU supports port size of 11-bit. */
75031   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Pos (10UL) /*!< Position of PORT_SIZE_11 field.                                 */
75032   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Pos) /*!< Bit mask of
75033                                                                             PORT_SIZE_11 field.*/
75034   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_11 field.                    */
75035   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_11 field.                    */
75036   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_NotSupported (0x0UL) /*!< Port size 11 is not supported.                        */
75037   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Supported (0x1UL) /*!< Port size 11 is supported.                               */
75038 
75039 /* PORT_SIZE_12 @Bit 11 : Indicates whether the TPIU supports port size of 12-bit. */
75040   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Pos (11UL) /*!< Position of PORT_SIZE_12 field.                                 */
75041   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Pos) /*!< Bit mask of
75042                                                                             PORT_SIZE_12 field.*/
75043   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_12 field.                    */
75044   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_12 field.                    */
75045   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_NotSupported (0x0UL) /*!< Port size 12 is not supported.                        */
75046   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Supported (0x1UL) /*!< Port size 12 is supported.                               */
75047 
75048 /* PORT_SIZE_13 @Bit 12 : Indicates whether the TPIU supports port size of 13-bit. */
75049   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Pos (12UL) /*!< Position of PORT_SIZE_13 field.                                 */
75050   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Pos) /*!< Bit mask of
75051                                                                             PORT_SIZE_13 field.*/
75052   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_13 field.                    */
75053   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_13 field.                    */
75054   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_NotSupported (0x0UL) /*!< Port size 13 is not supported.                        */
75055   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Supported (0x1UL) /*!< Port size 13 is supported.                               */
75056 
75057 /* PORT_SIZE_14 @Bit 13 : Indicates whether the TPIU supports port size of 14-bit. */
75058   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Pos (13UL) /*!< Position of PORT_SIZE_14 field.                                 */
75059   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Pos) /*!< Bit mask of
75060                                                                             PORT_SIZE_14 field.*/
75061   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_14 field.                    */
75062   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_14 field.                    */
75063   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_NotSupported (0x0UL) /*!< Port size 14 is not supported.                        */
75064   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Supported (0x1UL) /*!< Port size 14 is supported.                               */
75065 
75066 /* PORT_SIZE_15 @Bit 14 : Indicates whether the TPIU supports port size of 15-bit. */
75067   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Pos (14UL) /*!< Position of PORT_SIZE_15 field.                                 */
75068   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Pos) /*!< Bit mask of
75069                                                                             PORT_SIZE_15 field.*/
75070   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_15 field.                    */
75071   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_15 field.                    */
75072   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_NotSupported (0x0UL) /*!< Port size 15 is not supported.                        */
75073   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Supported (0x1UL) /*!< Port size 15 is supported.                               */
75074 
75075 /* PORT_SIZE_16 @Bit 15 : Indicates whether the TPIU supports port size of 16-bit. */
75076   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Pos (15UL) /*!< Position of PORT_SIZE_16 field.                                 */
75077   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Pos) /*!< Bit mask of
75078                                                                             PORT_SIZE_16 field.*/
75079   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_16 field.                    */
75080   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_16 field.                    */
75081   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_NotSupported (0x0UL) /*!< Port size 16 is not supported.                        */
75082   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Supported (0x1UL) /*!< Port size 16 is supported.                               */
75083 
75084 /* PORT_SIZE_17 @Bit 16 : Indicates whether the TPIU supports port size of 17-bit. */
75085   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Pos (16UL) /*!< Position of PORT_SIZE_17 field.                                 */
75086   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Pos) /*!< Bit mask of
75087                                                                             PORT_SIZE_17 field.*/
75088   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_17 field.                    */
75089   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_17 field.                    */
75090   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_NotSupported (0x0UL) /*!< Port size 17 is not supported.                        */
75091   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Supported (0x1UL) /*!< Port size 17 is supported.                               */
75092 
75093 /* PORT_SIZE_18 @Bit 17 : Indicates whether the TPIU supports port size of 18-bit. */
75094   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Pos (17UL) /*!< Position of PORT_SIZE_18 field.                                 */
75095   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Pos) /*!< Bit mask of
75096                                                                             PORT_SIZE_18 field.*/
75097   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_18 field.                    */
75098   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_18 field.                    */
75099   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_NotSupported (0x0UL) /*!< Port size 18 is not supported.                        */
75100   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Supported (0x1UL) /*!< Port size 18 is supported.                               */
75101 
75102 /* PORT_SIZE_19 @Bit 18 : Indicates whether the TPIU supports port size of 19-bit. */
75103   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Pos (18UL) /*!< Position of PORT_SIZE_19 field.                                 */
75104   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Pos) /*!< Bit mask of
75105                                                                             PORT_SIZE_19 field.*/
75106   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_19 field.                    */
75107   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_19 field.                    */
75108   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_NotSupported (0x0UL) /*!< Port size 19 is not supported.                        */
75109   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Supported (0x1UL) /*!< Port size 19 is supported.                               */
75110 
75111 /* PORT_SIZE_20 @Bit 19 : Indicates whether the TPIU supports port size of 20-bit. */
75112   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Pos (19UL) /*!< Position of PORT_SIZE_20 field.                                 */
75113   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Pos) /*!< Bit mask of
75114                                                                             PORT_SIZE_20 field.*/
75115   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_20 field.                    */
75116   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_20 field.                    */
75117   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_NotSupported (0x0UL) /*!< Port size 20 is not supported.                        */
75118   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Supported (0x1UL) /*!< Port size 20 is supported.                               */
75119 
75120 /* PORT_SIZE_21 @Bit 20 : Indicates whether the TPIU supports port size of 21-bit. */
75121   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Pos (20UL) /*!< Position of PORT_SIZE_21 field.                                 */
75122   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Pos) /*!< Bit mask of
75123                                                                             PORT_SIZE_21 field.*/
75124   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_21 field.                    */
75125   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_21 field.                    */
75126   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_NotSupported (0x0UL) /*!< Port size 21 is not supported.                        */
75127   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Supported (0x1UL) /*!< Port size 21 is supported.                               */
75128 
75129 /* PORT_SIZE_22 @Bit 21 : Indicates whether the TPIU supports port size of 22-bit. */
75130   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Pos (21UL) /*!< Position of PORT_SIZE_22 field.                                 */
75131   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Pos) /*!< Bit mask of
75132                                                                             PORT_SIZE_22 field.*/
75133   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_22 field.                    */
75134   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_22 field.                    */
75135   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_NotSupported (0x0UL) /*!< Port size 22 is not supported.                        */
75136   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Supported (0x1UL) /*!< Port size 22 is supported.                               */
75137 
75138 /* PORT_SIZE_23 @Bit 22 : Indicates whether the TPIU supports port size of 23-bit. */
75139   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Pos (22UL) /*!< Position of PORT_SIZE_23 field.                                 */
75140   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Pos) /*!< Bit mask of
75141                                                                             PORT_SIZE_23 field.*/
75142   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_23 field.                    */
75143   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_23 field.                    */
75144   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_NotSupported (0x0UL) /*!< Port size 23 is not supported.                        */
75145   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Supported (0x1UL) /*!< Port size 23 is supported.                               */
75146 
75147 /* PORT_SIZE_24 @Bit 23 : Indicates whether the TPIU supports port size of 24-bit. */
75148   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Pos (23UL) /*!< Position of PORT_SIZE_24 field.                                 */
75149   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Pos) /*!< Bit mask of
75150                                                                             PORT_SIZE_24 field.*/
75151   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_24 field.                    */
75152   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_24 field.                    */
75153   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_NotSupported (0x0UL) /*!< Port size 24 is not supported.                        */
75154   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Supported (0x1UL) /*!< Port size 24 is supported.                               */
75155 
75156 /* PORT_SIZE_25 @Bit 24 : Indicates whether the TPIU supports port size of 25-bit. */
75157   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Pos (24UL) /*!< Position of PORT_SIZE_25 field.                                 */
75158   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Pos) /*!< Bit mask of
75159                                                                             PORT_SIZE_25 field.*/
75160   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_25 field.                    */
75161   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_25 field.                    */
75162   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_NotSupported (0x0UL) /*!< Port size 25 is not supported.                        */
75163   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Supported (0x1UL) /*!< Port size 25 is supported.                               */
75164 
75165 /* PORT_SIZE_26 @Bit 25 : Indicates whether the TPIU supports port size of 26-bit. */
75166   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Pos (25UL) /*!< Position of PORT_SIZE_26 field.                                 */
75167   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Pos) /*!< Bit mask of
75168                                                                             PORT_SIZE_26 field.*/
75169   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_26 field.                    */
75170   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_26 field.                    */
75171   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_NotSupported (0x0UL) /*!< Port size 26 is not supported.                        */
75172   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Supported (0x1UL) /*!< Port size 26 is supported.                               */
75173 
75174 /* PORT_SIZE_27 @Bit 26 : Indicates whether the TPIU supports port size of 27-bit. */
75175   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Pos (26UL) /*!< Position of PORT_SIZE_27 field.                                 */
75176   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Pos) /*!< Bit mask of
75177                                                                             PORT_SIZE_27 field.*/
75178   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_27 field.                    */
75179   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_27 field.                    */
75180   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_NotSupported (0x0UL) /*!< Port size 27 is not supported.                        */
75181   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Supported (0x1UL) /*!< Port size 27 is supported.                               */
75182 
75183 /* PORT_SIZE_28 @Bit 27 : Indicates whether the TPIU supports port size of 28-bit. */
75184   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Pos (27UL) /*!< Position of PORT_SIZE_28 field.                                 */
75185   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Pos) /*!< Bit mask of
75186                                                                             PORT_SIZE_28 field.*/
75187   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_28 field.                    */
75188   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_28 field.                    */
75189   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_NotSupported (0x0UL) /*!< Port size 28 is not supported.                        */
75190   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Supported (0x1UL) /*!< Port size 28 is supported.                               */
75191 
75192 /* PORT_SIZE_29 @Bit 28 : Indicates whether the TPIU supports port size of 29-bit. */
75193   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Pos (28UL) /*!< Position of PORT_SIZE_29 field.                                 */
75194   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Pos) /*!< Bit mask of
75195                                                                             PORT_SIZE_29 field.*/
75196   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_29 field.                    */
75197   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_29 field.                    */
75198   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_NotSupported (0x0UL) /*!< Port size 29 is not supported.                        */
75199   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Supported (0x1UL) /*!< Port size 29 is supported.                               */
75200 
75201 /* PORT_SIZE_30 @Bit 29 : Indicates whether the TPIU supports port size of 30-bit. */
75202   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Pos (29UL) /*!< Position of PORT_SIZE_30 field.                                 */
75203   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Pos) /*!< Bit mask of
75204                                                                             PORT_SIZE_30 field.*/
75205   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_30 field.                    */
75206   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_30 field.                    */
75207   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_NotSupported (0x0UL) /*!< Port size 30 is not supported.                        */
75208   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Supported (0x1UL) /*!< Port size 30 is supported.                               */
75209 
75210 /* PORT_SIZE_31 @Bit 30 : Indicates whether the TPIU supports port size of 31-bit. */
75211   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Pos (30UL) /*!< Position of PORT_SIZE_31 field.                                 */
75212   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Pos) /*!< Bit mask of
75213                                                                             PORT_SIZE_31 field.*/
75214   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_31 field.                    */
75215   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_31 field.                    */
75216   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_NotSupported (0x0UL) /*!< Port size 31 is not supported.                        */
75217   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Supported (0x1UL) /*!< Port size 31 is supported.                               */
75218 
75219 /* PORT_SIZE_32 @Bit 31 : Indicates whether the TPIU supports port size of 32-bit. */
75220   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Pos (31UL) /*!< Position of PORT_SIZE_32 field.                                 */
75221   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Pos) /*!< Bit mask of
75222                                                                             PORT_SIZE_32 field.*/
75223   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_32 field.                    */
75224   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_32 field.                    */
75225   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_NotSupported (0x0UL) /*!< Port size 32 is not supported.                        */
75226   #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Supported (0x1UL) /*!< Port size 32 is supported.                               */
75227 
75228 
75229 /* TPIU_CURRENTPORTSIZE: Each bit location is a single port size. One bit can be set, and indicates the current port size. */
75230   #define TPIU_CURRENTPORTSIZE_ResetValue (0x00000000UL) /*!< Reset value of CURRENTPORTSIZE register.                         */
75231 
75232 /* PORT_SIZE_1 @Bit 0 : Indicates which port size is currently selected. */
75233   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Pos (0UL) /*!< Position of PORT_SIZE_1 field.                                       */
75234   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Pos) /*!< Bit mask of PORT_SIZE_1
75235                                                                             field.*/
75236   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_1 field.                         */
75237   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_1 field.                         */
75238   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_NotSelected (0x0UL) /*!< Port size 1 is not selected.                               */
75239   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Selected (0x1UL) /*!< Port size 1 is selected.                                      */
75240 
75241 /* PORT_SIZE_2 @Bit 1 : Indicates which port size is currently selected. */
75242   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Pos (1UL) /*!< Position of PORT_SIZE_2 field.                                       */
75243   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Pos) /*!< Bit mask of PORT_SIZE_2
75244                                                                             field.*/
75245   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_2 field.                         */
75246   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_2 field.                         */
75247   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_NotSelected (0x0UL) /*!< Port size 2 is not selected.                               */
75248   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Selected (0x1UL) /*!< Port size 2 is selected.                                      */
75249 
75250 /* PORT_SIZE_3 @Bit 2 : Indicates which port size is currently selected. */
75251   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Pos (2UL) /*!< Position of PORT_SIZE_3 field.                                       */
75252   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Pos) /*!< Bit mask of PORT_SIZE_3
75253                                                                             field.*/
75254   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_3 field.                         */
75255   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_3 field.                         */
75256   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_NotSelected (0x0UL) /*!< Port size 3 is not selected.                               */
75257   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Selected (0x1UL) /*!< Port size 3 is selected.                                      */
75258 
75259 /* PORT_SIZE_4 @Bit 3 : Indicates which port size is currently selected. */
75260   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Pos (3UL) /*!< Position of PORT_SIZE_4 field.                                       */
75261   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Pos) /*!< Bit mask of PORT_SIZE_4
75262                                                                             field.*/
75263   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_4 field.                         */
75264   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_4 field.                         */
75265   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_NotSelected (0x0UL) /*!< Port size 4 is not selected.                               */
75266   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Selected (0x1UL) /*!< Port size 4 is selected.                                      */
75267 
75268 /* PORT_SIZE_5 @Bit 4 : Indicates which port size is currently selected. */
75269   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Pos (4UL) /*!< Position of PORT_SIZE_5 field.                                       */
75270   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Pos) /*!< Bit mask of PORT_SIZE_5
75271                                                                             field.*/
75272   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_5 field.                         */
75273   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_5 field.                         */
75274   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_NotSelected (0x0UL) /*!< Port size 5 is not selected.                               */
75275   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Selected (0x1UL) /*!< Port size 5 is selected.                                      */
75276 
75277 /* PORT_SIZE_6 @Bit 5 : Indicates which port size is currently selected. */
75278   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Pos (5UL) /*!< Position of PORT_SIZE_6 field.                                       */
75279   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Pos) /*!< Bit mask of PORT_SIZE_6
75280                                                                             field.*/
75281   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_6 field.                         */
75282   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_6 field.                         */
75283   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_NotSelected (0x0UL) /*!< Port size 6 is not selected.                               */
75284   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Selected (0x1UL) /*!< Port size 6 is selected.                                      */
75285 
75286 /* PORT_SIZE_7 @Bit 6 : Indicates which port size is currently selected. */
75287   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Pos (6UL) /*!< Position of PORT_SIZE_7 field.                                       */
75288   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Pos) /*!< Bit mask of PORT_SIZE_7
75289                                                                             field.*/
75290   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_7 field.                         */
75291   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_7 field.                         */
75292   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_NotSelected (0x0UL) /*!< Port size 7 is not selected.                               */
75293   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Selected (0x1UL) /*!< Port size 7 is selected.                                      */
75294 
75295 /* PORT_SIZE_8 @Bit 7 : Indicates which port size is currently selected. */
75296   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Pos (7UL) /*!< Position of PORT_SIZE_8 field.                                       */
75297   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Pos) /*!< Bit mask of PORT_SIZE_8
75298                                                                             field.*/
75299   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_8 field.                         */
75300   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_8 field.                         */
75301   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_NotSelected (0x0UL) /*!< Port size 8 is not selected.                               */
75302   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Selected (0x1UL) /*!< Port size 8 is selected.                                      */
75303 
75304 /* PORT_SIZE_9 @Bit 8 : Indicates which port size is currently selected. */
75305   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Pos (8UL) /*!< Position of PORT_SIZE_9 field.                                       */
75306   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Pos) /*!< Bit mask of PORT_SIZE_9
75307                                                                             field.*/
75308   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_9 field.                         */
75309   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_9 field.                         */
75310   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_NotSelected (0x0UL) /*!< Port size 9 is not selected.                               */
75311   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Selected (0x1UL) /*!< Port size 9 is selected.                                      */
75312 
75313 /* PORT_SIZE_10 @Bit 9 : Indicates which port size is currently selected. */
75314   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Pos (9UL) /*!< Position of PORT_SIZE_10 field.                                     */
75315   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Pos) /*!< Bit mask of PORT_SIZE_10
75316                                                                             field.*/
75317   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_10 field.                       */
75318   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_10 field.                       */
75319   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_NotSelected (0x0UL) /*!< Port size 10 is not selected.                             */
75320   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Selected (0x1UL) /*!< Port size 10 is selected.                                    */
75321 
75322 /* PORT_SIZE_11 @Bit 10 : Indicates which port size is currently selected. */
75323   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Pos (10UL) /*!< Position of PORT_SIZE_11 field.                                    */
75324   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Pos) /*!< Bit mask of PORT_SIZE_11
75325                                                                             field.*/
75326   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_11 field.                       */
75327   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_11 field.                       */
75328   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_NotSelected (0x0UL) /*!< Port size 11 is not selected.                             */
75329   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Selected (0x1UL) /*!< Port size 11 is selected.                                    */
75330 
75331 /* PORT_SIZE_12 @Bit 11 : Indicates which port size is currently selected. */
75332   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Pos (11UL) /*!< Position of PORT_SIZE_12 field.                                    */
75333   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Pos) /*!< Bit mask of PORT_SIZE_12
75334                                                                             field.*/
75335   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_12 field.                       */
75336   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_12 field.                       */
75337   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_NotSelected (0x0UL) /*!< Port size 12 is not selected.                             */
75338   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Selected (0x1UL) /*!< Port size 12 is selected.                                    */
75339 
75340 /* PORT_SIZE_13 @Bit 12 : Indicates which port size is currently selected. */
75341   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Pos (12UL) /*!< Position of PORT_SIZE_13 field.                                    */
75342   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Pos) /*!< Bit mask of PORT_SIZE_13
75343                                                                             field.*/
75344   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_13 field.                       */
75345   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_13 field.                       */
75346   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_NotSelected (0x0UL) /*!< Port size 13 is not selected.                             */
75347   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Selected (0x1UL) /*!< Port size 13 is selected.                                    */
75348 
75349 /* PORT_SIZE_14 @Bit 13 : Indicates which port size is currently selected. */
75350   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Pos (13UL) /*!< Position of PORT_SIZE_14 field.                                    */
75351   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Pos) /*!< Bit mask of PORT_SIZE_14
75352                                                                             field.*/
75353   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_14 field.                       */
75354   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_14 field.                       */
75355   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_NotSelected (0x0UL) /*!< Port size 14 is not selected.                             */
75356   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Selected (0x1UL) /*!< Port size 14 is selected.                                    */
75357 
75358 /* PORT_SIZE_15 @Bit 14 : Indicates which port size is currently selected. */
75359   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Pos (14UL) /*!< Position of PORT_SIZE_15 field.                                    */
75360   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Pos) /*!< Bit mask of PORT_SIZE_15
75361                                                                             field.*/
75362   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_15 field.                       */
75363   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_15 field.                       */
75364   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_NotSelected (0x0UL) /*!< Port size 15 is not selected.                             */
75365   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Selected (0x1UL) /*!< Port size 15 is selected.                                    */
75366 
75367 /* PORT_SIZE_16 @Bit 15 : Indicates which port size is currently selected. */
75368   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Pos (15UL) /*!< Position of PORT_SIZE_16 field.                                    */
75369   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Pos) /*!< Bit mask of PORT_SIZE_16
75370                                                                             field.*/
75371   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_16 field.                       */
75372   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_16 field.                       */
75373   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_NotSelected (0x0UL) /*!< Port size 16 is not selected.                             */
75374   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Selected (0x1UL) /*!< Port size 16 is selected.                                    */
75375 
75376 /* PORT_SIZE_17 @Bit 16 : Indicates which port size is currently selected. */
75377   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Pos (16UL) /*!< Position of PORT_SIZE_17 field.                                    */
75378   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Pos) /*!< Bit mask of PORT_SIZE_17
75379                                                                             field.*/
75380   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_17 field.                       */
75381   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_17 field.                       */
75382   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_NotSelected (0x0UL) /*!< Port size 17 is not selected.                             */
75383   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Selected (0x1UL) /*!< Port size 17 is selected.                                    */
75384 
75385 /* PORT_SIZE_18 @Bit 17 : Indicates which port size is currently selected. */
75386   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Pos (17UL) /*!< Position of PORT_SIZE_18 field.                                    */
75387   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Pos) /*!< Bit mask of PORT_SIZE_18
75388                                                                             field.*/
75389   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_18 field.                       */
75390   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_18 field.                       */
75391   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_NotSelected (0x0UL) /*!< Port size 18 is not selected.                             */
75392   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Selected (0x1UL) /*!< Port size 18 is selected.                                    */
75393 
75394 /* PORT_SIZE_19 @Bit 18 : Indicates which port size is currently selected. */
75395   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Pos (18UL) /*!< Position of PORT_SIZE_19 field.                                    */
75396   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Pos) /*!< Bit mask of PORT_SIZE_19
75397                                                                             field.*/
75398   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_19 field.                       */
75399   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_19 field.                       */
75400   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_NotSelected (0x0UL) /*!< Port size 19 is not selected.                             */
75401   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Selected (0x1UL) /*!< Port size 19 is selected.                                    */
75402 
75403 /* PORT_SIZE_20 @Bit 19 : Indicates which port size is currently selected. */
75404   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Pos (19UL) /*!< Position of PORT_SIZE_20 field.                                    */
75405   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Pos) /*!< Bit mask of PORT_SIZE_20
75406                                                                             field.*/
75407   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_20 field.                       */
75408   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_20 field.                       */
75409   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_NotSelected (0x0UL) /*!< Port size 20 is not selected.                             */
75410   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Selected (0x1UL) /*!< Port size 20 is selected.                                    */
75411 
75412 /* PORT_SIZE_21 @Bit 20 : Indicates which port size is currently selected. */
75413   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Pos (20UL) /*!< Position of PORT_SIZE_21 field.                                    */
75414   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Pos) /*!< Bit mask of PORT_SIZE_21
75415                                                                             field.*/
75416   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_21 field.                       */
75417   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_21 field.                       */
75418   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_NotSelected (0x0UL) /*!< Port size 21 is not selected.                             */
75419   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Selected (0x1UL) /*!< Port size 21 is selected.                                    */
75420 
75421 /* PORT_SIZE_22 @Bit 21 : Indicates which port size is currently selected. */
75422   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Pos (21UL) /*!< Position of PORT_SIZE_22 field.                                    */
75423   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Pos) /*!< Bit mask of PORT_SIZE_22
75424                                                                             field.*/
75425   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_22 field.                       */
75426   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_22 field.                       */
75427   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_NotSelected (0x0UL) /*!< Port size 22 is not selected.                             */
75428   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Selected (0x1UL) /*!< Port size 22 is selected.                                    */
75429 
75430 /* PORT_SIZE_23 @Bit 22 : Indicates which port size is currently selected. */
75431   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Pos (22UL) /*!< Position of PORT_SIZE_23 field.                                    */
75432   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Pos) /*!< Bit mask of PORT_SIZE_23
75433                                                                             field.*/
75434   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_23 field.                       */
75435   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_23 field.                       */
75436   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_NotSelected (0x0UL) /*!< Port size 23 is not selected.                             */
75437   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Selected (0x1UL) /*!< Port size 23 is selected.                                    */
75438 
75439 /* PORT_SIZE_24 @Bit 23 : Indicates which port size is currently selected. */
75440   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Pos (23UL) /*!< Position of PORT_SIZE_24 field.                                    */
75441   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Pos) /*!< Bit mask of PORT_SIZE_24
75442                                                                             field.*/
75443   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_24 field.                       */
75444   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_24 field.                       */
75445   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_NotSelected (0x0UL) /*!< Port size 24 is not selected.                             */
75446   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Selected (0x1UL) /*!< Port size 24 is selected.                                    */
75447 
75448 /* PORT_SIZE_25 @Bit 24 : Indicates which port size is currently selected. */
75449   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Pos (24UL) /*!< Position of PORT_SIZE_25 field.                                    */
75450   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Pos) /*!< Bit mask of PORT_SIZE_25
75451                                                                             field.*/
75452   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_25 field.                       */
75453   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_25 field.                       */
75454   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_NotSelected (0x0UL) /*!< Port size 25 is not selected.                             */
75455   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Selected (0x1UL) /*!< Port size 25 is selected.                                    */
75456 
75457 /* PORT_SIZE_26 @Bit 25 : Indicates which port size is currently selected. */
75458   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Pos (25UL) /*!< Position of PORT_SIZE_26 field.                                    */
75459   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Pos) /*!< Bit mask of PORT_SIZE_26
75460                                                                             field.*/
75461   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_26 field.                       */
75462   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_26 field.                       */
75463   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_NotSelected (0x0UL) /*!< Port size 26 is not selected.                             */
75464   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Selected (0x1UL) /*!< Port size 26 is selected.                                    */
75465 
75466 /* PORT_SIZE_27 @Bit 26 : Indicates which port size is currently selected. */
75467   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Pos (26UL) /*!< Position of PORT_SIZE_27 field.                                    */
75468   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Pos) /*!< Bit mask of PORT_SIZE_27
75469                                                                             field.*/
75470   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_27 field.                       */
75471   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_27 field.                       */
75472   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_NotSelected (0x0UL) /*!< Port size 27 is not selected.                             */
75473   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Selected (0x1UL) /*!< Port size 27 is selected.                                    */
75474 
75475 /* PORT_SIZE_28 @Bit 27 : Indicates which port size is currently selected. */
75476   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Pos (27UL) /*!< Position of PORT_SIZE_28 field.                                    */
75477   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Pos) /*!< Bit mask of PORT_SIZE_28
75478                                                                             field.*/
75479   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_28 field.                       */
75480   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_28 field.                       */
75481   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_NotSelected (0x0UL) /*!< Port size 28 is not selected.                             */
75482   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Selected (0x1UL) /*!< Port size 28 is selected.                                    */
75483 
75484 /* PORT_SIZE_29 @Bit 28 : Indicates which port size is currently selected. */
75485   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Pos (28UL) /*!< Position of PORT_SIZE_29 field.                                    */
75486   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Pos) /*!< Bit mask of PORT_SIZE_29
75487                                                                             field.*/
75488   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_29 field.                       */
75489   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_29 field.                       */
75490   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_NotSelected (0x0UL) /*!< Port size 29 is not selected.                             */
75491   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Selected (0x1UL) /*!< Port size 29 is selected.                                    */
75492 
75493 /* PORT_SIZE_30 @Bit 29 : Indicates which port size is currently selected. */
75494   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Pos (29UL) /*!< Position of PORT_SIZE_30 field.                                    */
75495   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Pos) /*!< Bit mask of PORT_SIZE_30
75496                                                                             field.*/
75497   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_30 field.                       */
75498   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_30 field.                       */
75499   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_NotSelected (0x0UL) /*!< Port size 30 is not selected.                             */
75500   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Selected (0x1UL) /*!< Port size 30 is selected.                                    */
75501 
75502 /* PORT_SIZE_31 @Bit 30 : Indicates which port size is currently selected. */
75503   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Pos (30UL) /*!< Position of PORT_SIZE_31 field.                                    */
75504   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Pos) /*!< Bit mask of PORT_SIZE_31
75505                                                                             field.*/
75506   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_31 field.                       */
75507   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_31 field.                       */
75508   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_NotSelected (0x0UL) /*!< Port size 31 is not selected.                             */
75509   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Selected (0x1UL) /*!< Port size 31 is selected.                                    */
75510 
75511 /* PORT_SIZE_32 @Bit 31 : Indicates which port size is currently selected. */
75512   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Pos (31UL) /*!< Position of PORT_SIZE_32 field.                                    */
75513   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Pos) /*!< Bit mask of PORT_SIZE_32
75514                                                                             field.*/
75515   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Min (0x0UL) /*!< Min enumerator value of PORT_SIZE_32 field.                       */
75516   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Max (0x1UL) /*!< Max enumerator value of PORT_SIZE_32 field.                       */
75517   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_NotSelected (0x0UL) /*!< Port size 32 is not selected.                             */
75518   #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Selected (0x1UL) /*!< Port size 32 is selected.                                    */
75519 
75520 
75521 /* TPIU_SUPPORTEDTRIGGERMODES: The Supported_trigger_modes register indicates the implemented trigger counter multipliers and
75522                                 other supported features of the trigger system. */
75523 
75524   #define TPIU_SUPPORTEDTRIGGERMODES_ResetValue (0x00000000UL) /*!< Reset value of SUPPORTEDTRIGGERMODES register.             */
75525 
75526 /* MULT0 @Bit 0 : Indicates whether multiplying the trigger counter by 2^(0+1) is supported. */
75527   #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Pos (0UL) /*!< Position of MULT0 field.                                             */
75528   #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT0_Pos) /*!< Bit mask of MULT0 field.   */
75529   #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Min (0x0UL) /*!< Min enumerator value of MULT0 field.                               */
75530   #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Max (0x1UL) /*!< Max enumerator value of MULT0 field.                               */
75531   #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(0+1) is supported.   */
75532   #define TPIU_SUPPORTEDTRIGGERMODES_MULT0_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(0+1) is supported.      */
75533 
75534 /* MULT1 @Bit 1 : Indicates whether multiplying the trigger counter by 2^(1+1) is supported. */
75535   #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Pos (1UL) /*!< Position of MULT1 field.                                             */
75536   #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT1_Pos) /*!< Bit mask of MULT1 field.   */
75537   #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Min (0x0UL) /*!< Min enumerator value of MULT1 field.                               */
75538   #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Max (0x1UL) /*!< Max enumerator value of MULT1 field.                               */
75539   #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(1+1) is supported.   */
75540   #define TPIU_SUPPORTEDTRIGGERMODES_MULT1_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(1+1) is supported.      */
75541 
75542 /* MULT2 @Bit 2 : Indicates whether multiplying the trigger counter by 2^(2+1) is supported. */
75543   #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Pos (2UL) /*!< Position of MULT2 field.                                             */
75544   #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT2_Pos) /*!< Bit mask of MULT2 field.   */
75545   #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Min (0x0UL) /*!< Min enumerator value of MULT2 field.                               */
75546   #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Max (0x1UL) /*!< Max enumerator value of MULT2 field.                               */
75547   #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(2+1) is supported.   */
75548   #define TPIU_SUPPORTEDTRIGGERMODES_MULT2_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(2+1) is supported.      */
75549 
75550 /* MULT3 @Bit 3 : Indicates whether multiplying the trigger counter by 2^(3+1) is supported. */
75551   #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Pos (3UL) /*!< Position of MULT3 field.                                             */
75552   #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT3_Pos) /*!< Bit mask of MULT3 field.   */
75553   #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Min (0x0UL) /*!< Min enumerator value of MULT3 field.                               */
75554   #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Max (0x1UL) /*!< Max enumerator value of MULT3 field.                               */
75555   #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(3+1) is supported.   */
75556   #define TPIU_SUPPORTEDTRIGGERMODES_MULT3_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(3+1) is supported.      */
75557 
75558 /* MULT4 @Bit 4 : Indicates whether multiplying the trigger counter by 2^(4+1) is supported. */
75559   #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Pos (4UL) /*!< Position of MULT4 field.                                             */
75560   #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT4_Pos) /*!< Bit mask of MULT4 field.   */
75561   #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Min (0x0UL) /*!< Min enumerator value of MULT4 field.                               */
75562   #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Max (0x1UL) /*!< Max enumerator value of MULT4 field.                               */
75563   #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(4+1) is supported.   */
75564   #define TPIU_SUPPORTEDTRIGGERMODES_MULT4_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(4+1) is supported.      */
75565 
75566 /* TCOUNT8 @Bit 8 : Indicates whether an 8-bit wide counter register is implemented. */
75567   #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Pos (8UL) /*!< Position of TCOUNT8 field.                                         */
75568   #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Pos) /*!< Bit mask of TCOUNT8
75569                                                                             field.*/
75570   #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Min (0x0UL) /*!< Min enumerator value of TCOUNT8 field.                           */
75571   #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Max (0x1UL) /*!< Max enumerator value of TCOUNT8 field.                           */
75572   #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_NotImplemented (0x0UL) /*!< An 8-bit wide counter register is implemented.        */
75573   #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Implemented (0x1UL) /*!< An 8-bit wide counter register is implemented.           */
75574 
75575 /* TRIGGERED @Bit 16 : A trigger has occurred and the counter has reached 0. */
75576   #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Pos (16UL) /*!< Position of TRIGGERED field.                                    */
75577   #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Pos) /*!< Bit mask of
75578                                                                             TRIGGERED field.*/
75579   #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of TRIGGERED field.                       */
75580   #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of TRIGGERED field.                       */
75581   #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_NotOccured (0x0UL) /*!< Trigger has not occurred.                               */
75582   #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Occured (0x1UL) /*!< Trigger has occurred.                                      */
75583 
75584 /* TRGRUN @Bit 17 : A trigger has occurred but the counter is not at 0. */
75585   #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Pos (17UL) /*!< Position of TRGRUN field.                                          */
75586   #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Pos) /*!< Bit mask of TRGRUN field.*/
75587   #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Min (0x0UL) /*!< Min enumerator value of TRGRUN field.                             */
75588   #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Max (0x1UL) /*!< Max enumerator value of TRGRUN field.                             */
75589   #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_NotOccured (0x0UL) /*!< Either a trigger has not occurred or the counter is at 0.  */
75590   #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Occured (0x1UL) /*!< A trigger has occurred but the counter is not at 0.           */
75591 
75592 
75593 /* TPIU_TRIGGERCOUNTERVALUE: The Trigger_counter_value register enables delaying the indication of triggers to any external
75594                               connected trace capture or storage devices. */
75595 
75596   #define TPIU_TRIGGERCOUNTERVALUE_ResetValue (0x00000000UL) /*!< Reset value of TRIGGERCOUNTERVALUE register.                 */
75597 
75598 /* TrigCount @Bits 0..7 : 8-bit counter value for the number of words to be output from the formatter before a trigger is
75599                           inserted. */
75600 
75601   #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Pos (0UL) /*!< Position of TrigCount field.                                       */
75602   #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Msk (0xFFUL << TPIU_TRIGGERCOUNTERVALUE_TrigCount_Pos) /*!< Bit mask of TrigCount
75603                                                                             field.*/
75604   #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Min (0x0UL) /*!< Min value of TrigCount field.                                    */
75605   #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Max (0xFFUL) /*!< Max size of TrigCount field.                                    */
75606 
75607 
75608 /* TPIU_TRIGGERMULTIPLIER: The Trigger_multiplier register contains the selectors for the trigger counter multiplier. */
75609   #define TPIU_TRIGGERMULTIPLIER_ResetValue (0x00000000UL) /*!< Reset value of TRIGGERMULTIPLIER register.                     */
75610 
75611 /* MULT0 @Bit 0 : Multiply the Trigger Counter by 2^n. */
75612   #define TPIU_TRIGGERMULTIPLIER_MULT0_Pos (0UL)     /*!< Position of MULT0 field.                                             */
75613   #define TPIU_TRIGGERMULTIPLIER_MULT0_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT0_Pos) /*!< Bit mask of MULT0 field.           */
75614   #define TPIU_TRIGGERMULTIPLIER_MULT0_Min (0x0UL)   /*!< Min enumerator value of MULT0 field.                                 */
75615   #define TPIU_TRIGGERMULTIPLIER_MULT0_Max (0x1UL)   /*!< Max enumerator value of MULT0 field.                                 */
75616   #define TPIU_TRIGGERMULTIPLIER_MULT0_Disabled (0x0UL) /*!< Multiplier disabled.                                              */
75617   #define TPIU_TRIGGERMULTIPLIER_MULT0_Enabled (0x1UL) /*!< Multiplier enabled.                                                */
75618 
75619 /* MULT1 @Bit 1 : Multiply the Trigger Counter by 2^n. */
75620   #define TPIU_TRIGGERMULTIPLIER_MULT1_Pos (1UL)     /*!< Position of MULT1 field.                                             */
75621   #define TPIU_TRIGGERMULTIPLIER_MULT1_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT1_Pos) /*!< Bit mask of MULT1 field.           */
75622   #define TPIU_TRIGGERMULTIPLIER_MULT1_Min (0x0UL)   /*!< Min enumerator value of MULT1 field.                                 */
75623   #define TPIU_TRIGGERMULTIPLIER_MULT1_Max (0x1UL)   /*!< Max enumerator value of MULT1 field.                                 */
75624   #define TPIU_TRIGGERMULTIPLIER_MULT1_Disabled (0x0UL) /*!< Multiplier disabled.                                              */
75625   #define TPIU_TRIGGERMULTIPLIER_MULT1_Enabled (0x1UL) /*!< Multiplier enabled.                                                */
75626 
75627 /* MULT2 @Bit 2 : Multiply the Trigger Counter by 2^n. */
75628   #define TPIU_TRIGGERMULTIPLIER_MULT2_Pos (2UL)     /*!< Position of MULT2 field.                                             */
75629   #define TPIU_TRIGGERMULTIPLIER_MULT2_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT2_Pos) /*!< Bit mask of MULT2 field.           */
75630   #define TPIU_TRIGGERMULTIPLIER_MULT2_Min (0x0UL)   /*!< Min enumerator value of MULT2 field.                                 */
75631   #define TPIU_TRIGGERMULTIPLIER_MULT2_Max (0x1UL)   /*!< Max enumerator value of MULT2 field.                                 */
75632   #define TPIU_TRIGGERMULTIPLIER_MULT2_Disabled (0x0UL) /*!< Multiplier disabled.                                              */
75633   #define TPIU_TRIGGERMULTIPLIER_MULT2_Enabled (0x1UL) /*!< Multiplier enabled.                                                */
75634 
75635 /* MULT3 @Bit 3 : Multiply the Trigger Counter by 2^n. */
75636   #define TPIU_TRIGGERMULTIPLIER_MULT3_Pos (3UL)     /*!< Position of MULT3 field.                                             */
75637   #define TPIU_TRIGGERMULTIPLIER_MULT3_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT3_Pos) /*!< Bit mask of MULT3 field.           */
75638   #define TPIU_TRIGGERMULTIPLIER_MULT3_Min (0x0UL)   /*!< Min enumerator value of MULT3 field.                                 */
75639   #define TPIU_TRIGGERMULTIPLIER_MULT3_Max (0x1UL)   /*!< Max enumerator value of MULT3 field.                                 */
75640   #define TPIU_TRIGGERMULTIPLIER_MULT3_Disabled (0x0UL) /*!< Multiplier disabled.                                              */
75641   #define TPIU_TRIGGERMULTIPLIER_MULT3_Enabled (0x1UL) /*!< Multiplier enabled.                                                */
75642 
75643 /* MULT4 @Bit 4 : Multiply the Trigger Counter by 2^n. */
75644   #define TPIU_TRIGGERMULTIPLIER_MULT4_Pos (4UL)     /*!< Position of MULT4 field.                                             */
75645   #define TPIU_TRIGGERMULTIPLIER_MULT4_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT4_Pos) /*!< Bit mask of MULT4 field.           */
75646   #define TPIU_TRIGGERMULTIPLIER_MULT4_Min (0x0UL)   /*!< Min enumerator value of MULT4 field.                                 */
75647   #define TPIU_TRIGGERMULTIPLIER_MULT4_Max (0x1UL)   /*!< Max enumerator value of MULT4 field.                                 */
75648   #define TPIU_TRIGGERMULTIPLIER_MULT4_Disabled (0x0UL) /*!< Multiplier disabled.                                              */
75649   #define TPIU_TRIGGERMULTIPLIER_MULT4_Enabled (0x1UL) /*!< Multiplier enabled.                                                */
75650 
75651 
75652 /* TPIU_SUPPPORTEDTESTPATTERNMODES: The Supported_test_pattern_modes register provides a set of known bit sequences or patterns
75653                                      that can be output over the trace port and can be detected by the TPA or other associated
75654                                      trace capture device. */
75655 
75656   #define TPIU_SUPPPORTEDTESTPATTERNMODES_ResetValue (0x00000000UL) /*!< Reset value of SUPPPORTEDTESTPATTERNMODES register.   */
75657 
75658 /* PATW1 @Bit 0 : Indicates whether the walking 1s pattern is supported as output over the trace port. */
75659   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Pos (0UL) /*!< Position of PATW1 field.                                        */
75660   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Pos) /*!< Bit mask of PATW1
75661                                                                             field.*/
75662   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Min (0x0UL) /*!< Min enumerator value of PATW1 field.                          */
75663   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Max (0x1UL) /*!< Max enumerator value of PATW1 field.                          */
75664   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_NotSupported (0x0UL) /*!< Test pattern is not supported.                       */
75665   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Supported (0x1UL) /*!< Test pattern is supported.                              */
75666 
75667 /* PATW0 @Bit 1 : Indicates whether the walking 0s pattern is supported as output over the trace port. */
75668   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Pos (1UL) /*!< Position of PATW0 field.                                        */
75669   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Pos) /*!< Bit mask of PATW0
75670                                                                             field.*/
75671   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Min (0x0UL) /*!< Min enumerator value of PATW0 field.                          */
75672   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Max (0x1UL) /*!< Max enumerator value of PATW0 field.                          */
75673   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_NotSupported (0x0UL) /*!< Test pattern is not supported.                       */
75674   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Supported (0x1UL) /*!< Test pattern is supported.                              */
75675 
75676 /* PATA5 @Bit 2 : Indicates whether the AA/55 pattern is supported as output over the trace port. */
75677   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Pos (2UL) /*!< Position of PATA5 field.                                        */
75678   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Pos) /*!< Bit mask of PATA5
75679                                                                             field.*/
75680   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Min (0x0UL) /*!< Min enumerator value of PATA5 field.                          */
75681   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Max (0x1UL) /*!< Max enumerator value of PATA5 field.                          */
75682   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_NotSupported (0x0UL) /*!< Test pattern is not supported.                       */
75683   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Supported (0x1UL) /*!< Test pattern is supported.                              */
75684 
75685 /* PATF0 @Bit 3 : Indicates whether the FF/00 pattern is supported as output over the trace port. */
75686   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Pos (3UL) /*!< Position of PATF0 field.                                        */
75687   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Pos) /*!< Bit mask of PATF0
75688                                                                             field.*/
75689   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Min (0x0UL) /*!< Min enumerator value of PATF0 field.                          */
75690   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Max (0x1UL) /*!< Max enumerator value of PATF0 field.                          */
75691   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_NotSupported (0x0UL) /*!< Test pattern is not supported.                       */
75692   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Supported (0x1UL) /*!< Test pattern is supported.                              */
75693 
75694 /* PTIMEEN @Bit 16 : Indicates whether timed mode is supported. */
75695   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Pos (16UL) /*!< Position of PTIMEEN field.                                   */
75696   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Pos) /*!< Bit mask of
75697                                                                             PTIMEEN field.*/
75698   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Min (0x0UL) /*!< Min enumerator value of PTIMEEN field.                      */
75699   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Max (0x1UL) /*!< Max enumerator value of PTIMEEN field.                      */
75700   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_NotSupported (0x0UL) /*!< Mode is not supported.                             */
75701   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Supported (0x1UL) /*!< Mode is supported.                                    */
75702 
75703 /* PCONTEN @Bit 17 : Indicates whether continuous mode is supported. */
75704   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Pos (17UL) /*!< Position of PCONTEN field.                                   */
75705   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Pos) /*!< Bit mask of
75706                                                                             PCONTEN field.*/
75707   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Min (0x0UL) /*!< Min enumerator value of PCONTEN field.                      */
75708   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Max (0x1UL) /*!< Max enumerator value of PCONTEN field.                      */
75709   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_NotSupported (0x0UL) /*!< Mode is not supported.                             */
75710   #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Supported (0x1UL) /*!< Mode is supported.                                    */
75711 
75712 
75713 /* TPIU_CURRENTTESTPATTERNMODES: Current_test_pattern_mode indicates the current test pattern or mode selected. */
75714   #define TPIU_CURRENTTESTPATTERNMODES_ResetValue (0x00000000UL) /*!< Reset value of CURRENTTESTPATTERNMODES register.         */
75715 
75716 /* PATW1 @Bit 0 : Indicates whether the walking 1s pattern is supported as output over the trace port. */
75717   #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Pos (0UL) /*!< Position of PATW1 field.                                           */
75718   #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATW1_Pos) /*!< Bit mask of PATW1
75719                                                                             field.*/
75720   #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Min (0x0UL) /*!< Min enumerator value of PATW1 field.                             */
75721   #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Max (0x1UL) /*!< Max enumerator value of PATW1 field.                             */
75722   #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Disabled (0x0UL) /*!< Test pattern is disabled.                                   */
75723   #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Enabled (0x1UL) /*!< Test pattern is enabled.                                     */
75724 
75725 /* PATW0 @Bit 1 : Indicates whether the walking 0s pattern is supported as output over the trace port. */
75726   #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Pos (1UL) /*!< Position of PATW0 field.                                           */
75727   #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATW0_Pos) /*!< Bit mask of PATW0
75728                                                                             field.*/
75729   #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Min (0x0UL) /*!< Min enumerator value of PATW0 field.                             */
75730   #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Max (0x1UL) /*!< Max enumerator value of PATW0 field.                             */
75731   #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Disabled (0x0UL) /*!< Test pattern is disabled.                                   */
75732   #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Enabled (0x1UL) /*!< Test pattern is enabled.                                     */
75733 
75734 /* PATA5 @Bit 2 : Indicates whether the AA/55 pattern is supported as output over the trace port. */
75735   #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Pos (2UL) /*!< Position of PATA5 field.                                           */
75736   #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATA5_Pos) /*!< Bit mask of PATA5
75737                                                                             field.*/
75738   #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Min (0x0UL) /*!< Min enumerator value of PATA5 field.                             */
75739   #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Max (0x1UL) /*!< Max enumerator value of PATA5 field.                             */
75740   #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Disabled (0x0UL) /*!< Test pattern is disabled.                                   */
75741   #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Enabled (0x1UL) /*!< Test pattern is enabled.                                     */
75742 
75743 /* PATF0 @Bit 3 : Indicates whether the FF/00 pattern is supported as output over the trace port. */
75744   #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Pos (3UL) /*!< Position of PATF0 field.                                           */
75745   #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATF0_Pos) /*!< Bit mask of PATF0
75746                                                                             field.*/
75747   #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Min (0x0UL) /*!< Min enumerator value of PATF0 field.                             */
75748   #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Max (0x1UL) /*!< Max enumerator value of PATF0 field.                             */
75749   #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Disabled (0x0UL) /*!< Test pattern is disabled.                                   */
75750   #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Enabled (0x1UL) /*!< Test pattern is enabled.                                     */
75751 
75752 /* PTIMEEN @Bit 16 : Indicates whether timed mode is supported. */
75753   #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Pos (16UL) /*!< Position of PTIMEEN field.                                      */
75754   #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Pos) /*!< Bit mask of PTIMEEN
75755                                                                             field.*/
75756   #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Min (0x0UL) /*!< Min enumerator value of PTIMEEN field.                         */
75757   #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Max (0x1UL) /*!< Max enumerator value of PTIMEEN field.                         */
75758   #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Disabled (0x0UL) /*!< Mode is disabled.                                         */
75759   #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Enabled (0x1UL) /*!< Mode is enabled.                                           */
75760 
75761 /* PCONTEN @Bit 17 : Indicates whether continuous mode is supported. */
75762   #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Pos (17UL) /*!< Position of PCONTEN field.                                      */
75763   #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Pos) /*!< Bit mask of PCONTEN
75764                                                                             field.*/
75765   #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Min (0x0UL) /*!< Min enumerator value of PCONTEN field.                         */
75766   #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Max (0x1UL) /*!< Max enumerator value of PCONTEN field.                         */
75767   #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Disabled (0x0UL) /*!< Mode is disabled.                                         */
75768   #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Enabled (0x1UL) /*!< Mode is enabled.                                           */
75769 
75770 
75771 /* TPIU_TPRCR: The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value
75772                 and a read returns the programmed value. */
75773 
75774   #define TPIU_TPRCR_ResetValue (0x00000000UL)       /*!< Reset value of TPRCR register.                                       */
75775 
75776 /* PATTCOUNT @Bits 0..7 : 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it
75777                           switches to the next pattern. */
75778 
75779   #define TPIU_TPRCR_PATTCOUNT_Pos (0UL)             /*!< Position of PATTCOUNT field.                                         */
75780   #define TPIU_TPRCR_PATTCOUNT_Msk (0xFFUL << TPIU_TPRCR_PATTCOUNT_Pos) /*!< Bit mask of PATTCOUNT field.                      */
75781   #define TPIU_TPRCR_PATTCOUNT_Min (0x0UL)           /*!< Min value of PATTCOUNT field.                                        */
75782   #define TPIU_TPRCR_PATTCOUNT_Max (0xFFUL)          /*!< Max size of PATTCOUNT field.                                         */
75783 
75784 
75785 /* TPIU_FFSR: The FFSR register indicates the current status of the formatter and flush features available in the TPIU. */
75786   #define TPIU_FFSR_ResetValue (0x00000000UL)        /*!< Reset value of FFSR register.                                        */
75787 
75788 /* FLINPROG @Bit 0 : Flush in progress. */
75789   #define TPIU_FFSR_FLINPROG_Pos (0UL)               /*!< Position of FLINPROG field.                                          */
75790   #define TPIU_FFSR_FLINPROG_Msk (0x1UL << TPIU_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field.                            */
75791   #define TPIU_FFSR_FLINPROG_Min (0x0UL)             /*!< Min enumerator value of FLINPROG field.                              */
75792   #define TPIU_FFSR_FLINPROG_Max (0x1UL)             /*!< Max enumerator value of FLINPROG field.                              */
75793   #define TPIU_FFSR_FLINPROG_NotInProgress (0x0UL)   /*!< A flush is not in progress.                                          */
75794   #define TPIU_FFSR_FLINPROG_InProgress (0x1UL)      /*!< A flush is in progress.                                              */
75795 
75796 /* FTSTOPPED @Bit 1 : The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional
75797                       trace data on the ATB interface is ignored and atreadys goes HIGH. */
75798 
75799   #define TPIU_FFSR_FTSTOPPED_Pos (1UL)              /*!< Position of FTSTOPPED field.                                         */
75800   #define TPIU_FFSR_FTSTOPPED_Msk (0x1UL << TPIU_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field.                         */
75801   #define TPIU_FFSR_FTSTOPPED_Min (0x0UL)            /*!< Min enumerator value of FTSTOPPED field.                             */
75802   #define TPIU_FFSR_FTSTOPPED_Max (0x1UL)            /*!< Max enumerator value of FTSTOPPED field.                             */
75803   #define TPIU_FFSR_FTSTOPPED_Running (0x0UL)        /*!< Formatter has not stopped.                                           */
75804   #define TPIU_FFSR_FTSTOPPED_Stopped (0x1UL)        /*!< Formatter has stopped.                                               */
75805 
75806 /* TCPRESENT @Bit 2 : Indicates whether the TRACECTL pin is available for use. */
75807   #define TPIU_FFSR_TCPRESENT_Pos (2UL)              /*!< Position of TCPRESENT field.                                         */
75808   #define TPIU_FFSR_TCPRESENT_Msk (0x1UL << TPIU_FFSR_TCPRESENT_Pos) /*!< Bit mask of TCPRESENT field.                         */
75809   #define TPIU_FFSR_TCPRESENT_Min (0x0UL)            /*!< Min enumerator value of TCPRESENT field.                             */
75810   #define TPIU_FFSR_TCPRESENT_Max (0x1UL)            /*!< Max enumerator value of TCPRESENT field.                             */
75811   #define TPIU_FFSR_TCPRESENT_NotPresent (0x0UL)     /*!< TRACECTL pin is not present.                                         */
75812   #define TPIU_FFSR_TCPRESENT_Present (0x1UL)        /*!< TRACECTL pin is present.                                             */
75813 
75814 
75815 /* TPIU_FFCR: The FFCR register controls the generation of stop, trigger, and flush events. */
75816   #define TPIU_FFCR_ResetValue (0x00000000UL)        /*!< Reset value of FFCR register.                                        */
75817 
75818 /* ENFTC @Bit 0 : Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl,
75819                   where present. */
75820 
75821   #define TPIU_FFCR_ENFTC_Pos (0UL)                  /*!< Position of ENFTC field.                                             */
75822   #define TPIU_FFCR_ENFTC_Msk (0x1UL << TPIU_FFCR_ENFTC_Pos) /*!< Bit mask of ENFTC field.                                     */
75823   #define TPIU_FFCR_ENFTC_Min (0x0UL)                /*!< Min enumerator value of ENFTC field.                                 */
75824   #define TPIU_FFCR_ENFTC_Max (0x1UL)                /*!< Max enumerator value of ENFTC field.                                 */
75825   #define TPIU_FFCR_ENFTC_Disabled (0x0UL)           /*!< The formatting feature is disabled.                                  */
75826   #define TPIU_FFCR_ENFTC_Enabled (0x1UL)            /*!< The formatting feature is enabled.                                   */
75827 
75828 /* ENFCONT @Bit 1 : Is embedded in trigger packets and indicates that no cycle is using sync packets. */
75829   #define TPIU_FFCR_ENFCONT_Pos (1UL)                /*!< Position of ENFCONT field.                                           */
75830   #define TPIU_FFCR_ENFCONT_Msk (0x1UL << TPIU_FFCR_ENFCONT_Pos) /*!< Bit mask of ENFCONT field.                               */
75831   #define TPIU_FFCR_ENFCONT_Min (0x0UL)              /*!< Min enumerator value of ENFCONT field.                               */
75832   #define TPIU_FFCR_ENFCONT_Max (0x1UL)              /*!< Max enumerator value of ENFCONT field.                               */
75833   #define TPIU_FFCR_ENFCONT_Disabled (0x0UL)         /*!< The formatting feature is disabled.                                  */
75834   #define TPIU_FFCR_ENFCONT_Enabled (0x1UL)          /*!< The formatting feature is enabled.                                   */
75835 
75836 /* FONFLIN @Bit 4 : Enables the use of the flushin connection. */
75837   #define TPIU_FFCR_FONFLIN_Pos (4UL)                /*!< Position of FONFLIN field.                                           */
75838   #define TPIU_FFCR_FONFLIN_Msk (0x1UL << TPIU_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field.                               */
75839   #define TPIU_FFCR_FONFLIN_Min (0x0UL)              /*!< Min enumerator value of FONFLIN field.                               */
75840   #define TPIU_FFCR_FONFLIN_Max (0x1UL)              /*!< Max enumerator value of FONFLIN field.                               */
75841   #define TPIU_FFCR_FONFLIN_Disabled (0x0UL)         /*!< The formatting feature is disabled.                                  */
75842   #define TPIU_FFCR_FONFLIN_Enabled (0x1UL)          /*!< The formatting feature is enabled.                                   */
75843 
75844 /* FONTRIG @Bit 5 : Initiates a manual flush of data in the system when a trigger event occurs. */
75845   #define TPIU_FFCR_FONTRIG_Pos (5UL)                /*!< Position of FONTRIG field.                                           */
75846   #define TPIU_FFCR_FONTRIG_Msk (0x1UL << TPIU_FFCR_FONTRIG_Pos) /*!< Bit mask of FONTRIG field.                               */
75847   #define TPIU_FFCR_FONTRIG_Min (0x0UL)              /*!< Min enumerator value of FONTRIG field.                               */
75848   #define TPIU_FFCR_FONTRIG_Max (0x1UL)              /*!< Max enumerator value of FONTRIG field.                               */
75849   #define TPIU_FFCR_FONTRIG_Disabled (0x0UL)         /*!< The formatting feature is disabled.                                  */
75850   #define TPIU_FFCR_FONTRIG_Enabled (0x1UL)          /*!< The formatting feature is enabled.                                   */
75851 
75852 /* FONMANR @Bit 6 : Generates a flush. This bit is set to 0 when this flush is serviced. */
75853   #define TPIU_FFCR_FONMANR_Pos (6UL)                /*!< Position of FONMANR field.                                           */
75854   #define TPIU_FFCR_FONMANR_Msk (0x1UL << TPIU_FFCR_FONMANR_Pos) /*!< Bit mask of FONMANR field.                               */
75855   #define TPIU_FFCR_FONMANR_Min (0x0UL)              /*!< Min enumerator value of FONMANR field.                               */
75856   #define TPIU_FFCR_FONMANR_Max (0x1UL)              /*!< Max enumerator value of FONMANR field.                               */
75857   #define TPIU_FFCR_FONMANR_Disabled (0x0UL)         /*!< The formatting feature is disabled.                                  */
75858   #define TPIU_FFCR_FONMANR_Enabled (0x1UL)          /*!< The formatting feature is enabled.                                   */
75859 
75860 /* FONMANW @Bit 7 : Generates a flush. This bit is set to 1 when this flush is serviced. */
75861   #define TPIU_FFCR_FONMANW_Pos (7UL)                /*!< Position of FONMANW field.                                           */
75862   #define TPIU_FFCR_FONMANW_Msk (0x1UL << TPIU_FFCR_FONMANW_Pos) /*!< Bit mask of FONMANW field.                               */
75863   #define TPIU_FFCR_FONMANW_Min (0x0UL)              /*!< Min enumerator value of FONMANW field.                               */
75864   #define TPIU_FFCR_FONMANW_Max (0x1UL)              /*!< Max enumerator value of FONMANW field.                               */
75865   #define TPIU_FFCR_FONMANW_Disabled (0x0UL)         /*!< The formatting feature is disabled.                                  */
75866   #define TPIU_FFCR_FONMANW_Enabled (0x1UL)          /*!< The formatting feature is enabled.                                   */
75867 
75868 /* TRIGIN @Bit 8 : Indicates a trigger when trigin is asserted. */
75869   #define TPIU_FFCR_TRIGIN_Pos (8UL)                 /*!< Position of TRIGIN field.                                            */
75870   #define TPIU_FFCR_TRIGIN_Msk (0x1UL << TPIU_FFCR_TRIGIN_Pos) /*!< Bit mask of TRIGIN field.                                  */
75871   #define TPIU_FFCR_TRIGIN_Min (0x0UL)               /*!< Min enumerator value of TRIGIN field.                                */
75872   #define TPIU_FFCR_TRIGIN_Max (0x1UL)               /*!< Max enumerator value of TRIGIN field.                                */
75873   #define TPIU_FFCR_TRIGIN_Disabled (0x0UL)          /*!< The formatting feature is disabled.                                  */
75874   #define TPIU_FFCR_TRIGIN_Enabled (0x1UL)           /*!< The formatting feature is enabled.                                   */
75875 
75876 /* TRIGEVT @Bit 9 : Indicates a trigger on a trigger event. */
75877   #define TPIU_FFCR_TRIGEVT_Pos (9UL)                /*!< Position of TRIGEVT field.                                           */
75878   #define TPIU_FFCR_TRIGEVT_Msk (0x1UL << TPIU_FFCR_TRIGEVT_Pos) /*!< Bit mask of TRIGEVT field.                               */
75879   #define TPIU_FFCR_TRIGEVT_Min (0x0UL)              /*!< Min enumerator value of TRIGEVT field.                               */
75880   #define TPIU_FFCR_TRIGEVT_Max (0x1UL)              /*!< Max enumerator value of TRIGEVT field.                               */
75881   #define TPIU_FFCR_TRIGEVT_Disabled (0x0UL)         /*!< The formatting feature is disabled.                                  */
75882   #define TPIU_FFCR_TRIGEVT_Enabled (0x1UL)          /*!< The formatting feature is enabled.                                   */
75883 
75884 /* TRIGFL @Bit 10 : Indicates a trigger when flush completion on afreadys is returned. */
75885   #define TPIU_FFCR_TRIGFL_Pos (10UL)                /*!< Position of TRIGFL field.                                            */
75886   #define TPIU_FFCR_TRIGFL_Msk (0x1UL << TPIU_FFCR_TRIGFL_Pos) /*!< Bit mask of TRIGFL field.                                  */
75887   #define TPIU_FFCR_TRIGFL_Min (0x0UL)               /*!< Min enumerator value of TRIGFL field.                                */
75888   #define TPIU_FFCR_TRIGFL_Max (0x1UL)               /*!< Max enumerator value of TRIGFL field.                                */
75889   #define TPIU_FFCR_TRIGFL_Disabled (0x0UL)          /*!< The formatting feature is disabled.                                  */
75890   #define TPIU_FFCR_TRIGFL_Enabled (0x1UL)           /*!< The formatting feature is enabled.                                   */
75891 
75892 /* STOPFL @Bit 12 : Forces the FIFO to drain off any part-completed packets. */
75893   #define TPIU_FFCR_STOPFL_Pos (12UL)                /*!< Position of STOPFL field.                                            */
75894   #define TPIU_FFCR_STOPFL_Msk (0x1UL << TPIU_FFCR_STOPFL_Pos) /*!< Bit mask of STOPFL field.                                  */
75895   #define TPIU_FFCR_STOPFL_Min (0x0UL)               /*!< Min enumerator value of STOPFL field.                                */
75896   #define TPIU_FFCR_STOPFL_Max (0x1UL)               /*!< Max enumerator value of STOPFL field.                                */
75897   #define TPIU_FFCR_STOPFL_Disabled (0x0UL)          /*!< The formatting feature is disabled.                                  */
75898   #define TPIU_FFCR_STOPFL_Enabled (0x1UL)           /*!< The formatting feature is enabled.                                   */
75899 
75900 /* STOPTRIG @Bit 13 : Stops the formatter after a trigger event is observed. Reset to disabled or 0. */
75901   #define TPIU_FFCR_STOPTRIG_Pos (13UL)              /*!< Position of STOPTRIG field.                                          */
75902   #define TPIU_FFCR_STOPTRIG_Msk (0x1UL << TPIU_FFCR_STOPTRIG_Pos) /*!< Bit mask of STOPTRIG field.                            */
75903   #define TPIU_FFCR_STOPTRIG_Min (0x0UL)             /*!< Min enumerator value of STOPTRIG field.                              */
75904   #define TPIU_FFCR_STOPTRIG_Max (0x1UL)             /*!< Max enumerator value of STOPTRIG field.                              */
75905   #define TPIU_FFCR_STOPTRIG_Disabled (0x0UL)        /*!< The formatting feature is disabled.                                  */
75906   #define TPIU_FFCR_STOPTRIG_Enabled (0x1UL)         /*!< The formatting feature is enabled.                                   */
75907 
75908 
75909 /* TPIU_FSCR: The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port
75910                Analyzer (TPA) capture buffer size. */
75911 
75912   #define TPIU_FSCR_ResetValue (0x00000000UL)        /*!< Reset value of FSCR register.                                        */
75913 
75914 /* CYCCOUNT @Bits 0..11 : 12-bit counter reload value. Indicates the number of complete frames between full synchronization
75915                           packets. */
75916 
75917   #define TPIU_FSCR_CYCCOUNT_Pos (0UL)               /*!< Position of CYCCOUNT field.                                          */
75918   #define TPIU_FSCR_CYCCOUNT_Msk (0xFFFUL << TPIU_FSCR_CYCCOUNT_Pos) /*!< Bit mask of CYCCOUNT field.                          */
75919   #define TPIU_FSCR_CYCCOUNT_Min (0x0UL)             /*!< Min value of CYCCOUNT field.                                         */
75920   #define TPIU_FSCR_CYCCOUNT_Max (0x400UL)           /*!< Max size of CYCCOUNT field.                                          */
75921 
75922 
75923 /* TPIU_EXTCTLINPORT: Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers,
75924                        or other solutions that might be added to the trace output pins either for pin control or a high-speed
75925                        trace port solution. */
75926 
75927   #define TPIU_EXTCTLINPORT_ResetValue (0x00000000UL) /*!< Reset value of EXTCTLINPORT register.                               */
75928 
75929 /* EXTCTLIN0 @Bit 0 : EXTCTL inputs. */
75930   #define TPIU_EXTCTLINPORT_EXTCTLIN0_Pos (0UL)      /*!< Position of EXTCTLIN0 field.                                         */
75931   #define TPIU_EXTCTLINPORT_EXTCTLIN0_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN0_Pos) /*!< Bit mask of EXTCTLIN0 field.         */
75932   #define TPIU_EXTCTLINPORT_EXTCTLIN0_Min (0x0UL)    /*!< Min enumerator value of EXTCTLIN0 field.                             */
75933   #define TPIU_EXTCTLINPORT_EXTCTLIN0_Max (0x1UL)    /*!< Max enumerator value of EXTCTLIN0 field.                             */
75934   #define TPIU_EXTCTLINPORT_EXTCTLIN0_Low (0x0UL)    /*!< Input EXTCTL0 is low.                                                */
75935   #define TPIU_EXTCTLINPORT_EXTCTLIN0_High (0x1UL)   /*!< Input EXTCTL0 is high.                                               */
75936 
75937 /* EXTCTLIN1 @Bit 1 : EXTCTL inputs. */
75938   #define TPIU_EXTCTLINPORT_EXTCTLIN1_Pos (1UL)      /*!< Position of EXTCTLIN1 field.                                         */
75939   #define TPIU_EXTCTLINPORT_EXTCTLIN1_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN1_Pos) /*!< Bit mask of EXTCTLIN1 field.         */
75940   #define TPIU_EXTCTLINPORT_EXTCTLIN1_Min (0x0UL)    /*!< Min enumerator value of EXTCTLIN1 field.                             */
75941   #define TPIU_EXTCTLINPORT_EXTCTLIN1_Max (0x1UL)    /*!< Max enumerator value of EXTCTLIN1 field.                             */
75942   #define TPIU_EXTCTLINPORT_EXTCTLIN1_Low (0x0UL)    /*!< Input EXTCTL1 is low.                                                */
75943   #define TPIU_EXTCTLINPORT_EXTCTLIN1_High (0x1UL)   /*!< Input EXTCTL1 is high.                                               */
75944 
75945 /* EXTCTLIN2 @Bit 2 : EXTCTL inputs. */
75946   #define TPIU_EXTCTLINPORT_EXTCTLIN2_Pos (2UL)      /*!< Position of EXTCTLIN2 field.                                         */
75947   #define TPIU_EXTCTLINPORT_EXTCTLIN2_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN2_Pos) /*!< Bit mask of EXTCTLIN2 field.         */
75948   #define TPIU_EXTCTLINPORT_EXTCTLIN2_Min (0x0UL)    /*!< Min enumerator value of EXTCTLIN2 field.                             */
75949   #define TPIU_EXTCTLINPORT_EXTCTLIN2_Max (0x1UL)    /*!< Max enumerator value of EXTCTLIN2 field.                             */
75950   #define TPIU_EXTCTLINPORT_EXTCTLIN2_Low (0x0UL)    /*!< Input EXTCTL2 is low.                                                */
75951   #define TPIU_EXTCTLINPORT_EXTCTLIN2_High (0x1UL)   /*!< Input EXTCTL2 is high.                                               */
75952 
75953 /* EXTCTLIN3 @Bit 3 : EXTCTL inputs. */
75954   #define TPIU_EXTCTLINPORT_EXTCTLIN3_Pos (3UL)      /*!< Position of EXTCTLIN3 field.                                         */
75955   #define TPIU_EXTCTLINPORT_EXTCTLIN3_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN3_Pos) /*!< Bit mask of EXTCTLIN3 field.         */
75956   #define TPIU_EXTCTLINPORT_EXTCTLIN3_Min (0x0UL)    /*!< Min enumerator value of EXTCTLIN3 field.                             */
75957   #define TPIU_EXTCTLINPORT_EXTCTLIN3_Max (0x1UL)    /*!< Max enumerator value of EXTCTLIN3 field.                             */
75958   #define TPIU_EXTCTLINPORT_EXTCTLIN3_Low (0x0UL)    /*!< Input EXTCTL3 is low.                                                */
75959   #define TPIU_EXTCTLINPORT_EXTCTLIN3_High (0x1UL)   /*!< Input EXTCTL3 is high.                                               */
75960 
75961 /* EXTCTLIN4 @Bit 4 : EXTCTL inputs. */
75962   #define TPIU_EXTCTLINPORT_EXTCTLIN4_Pos (4UL)      /*!< Position of EXTCTLIN4 field.                                         */
75963   #define TPIU_EXTCTLINPORT_EXTCTLIN4_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN4_Pos) /*!< Bit mask of EXTCTLIN4 field.         */
75964   #define TPIU_EXTCTLINPORT_EXTCTLIN4_Min (0x0UL)    /*!< Min enumerator value of EXTCTLIN4 field.                             */
75965   #define TPIU_EXTCTLINPORT_EXTCTLIN4_Max (0x1UL)    /*!< Max enumerator value of EXTCTLIN4 field.                             */
75966   #define TPIU_EXTCTLINPORT_EXTCTLIN4_Low (0x0UL)    /*!< Input EXTCTL4 is low.                                                */
75967   #define TPIU_EXTCTLINPORT_EXTCTLIN4_High (0x1UL)   /*!< Input EXTCTL4 is high.                                               */
75968 
75969 /* EXTCTLIN5 @Bit 5 : EXTCTL inputs. */
75970   #define TPIU_EXTCTLINPORT_EXTCTLIN5_Pos (5UL)      /*!< Position of EXTCTLIN5 field.                                         */
75971   #define TPIU_EXTCTLINPORT_EXTCTLIN5_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN5_Pos) /*!< Bit mask of EXTCTLIN5 field.         */
75972   #define TPIU_EXTCTLINPORT_EXTCTLIN5_Min (0x0UL)    /*!< Min enumerator value of EXTCTLIN5 field.                             */
75973   #define TPIU_EXTCTLINPORT_EXTCTLIN5_Max (0x1UL)    /*!< Max enumerator value of EXTCTLIN5 field.                             */
75974   #define TPIU_EXTCTLINPORT_EXTCTLIN5_Low (0x0UL)    /*!< Input EXTCTL5 is low.                                                */
75975   #define TPIU_EXTCTLINPORT_EXTCTLIN5_High (0x1UL)   /*!< Input EXTCTL5 is high.                                               */
75976 
75977 /* EXTCTLIN6 @Bit 6 : EXTCTL inputs. */
75978   #define TPIU_EXTCTLINPORT_EXTCTLIN6_Pos (6UL)      /*!< Position of EXTCTLIN6 field.                                         */
75979   #define TPIU_EXTCTLINPORT_EXTCTLIN6_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN6_Pos) /*!< Bit mask of EXTCTLIN6 field.         */
75980   #define TPIU_EXTCTLINPORT_EXTCTLIN6_Min (0x0UL)    /*!< Min enumerator value of EXTCTLIN6 field.                             */
75981   #define TPIU_EXTCTLINPORT_EXTCTLIN6_Max (0x1UL)    /*!< Max enumerator value of EXTCTLIN6 field.                             */
75982   #define TPIU_EXTCTLINPORT_EXTCTLIN6_Low (0x0UL)    /*!< Input EXTCTL6 is low.                                                */
75983   #define TPIU_EXTCTLINPORT_EXTCTLIN6_High (0x1UL)   /*!< Input EXTCTL6 is high.                                               */
75984 
75985 /* EXTCTLIN7 @Bit 7 : EXTCTL inputs. */
75986   #define TPIU_EXTCTLINPORT_EXTCTLIN7_Pos (7UL)      /*!< Position of EXTCTLIN7 field.                                         */
75987   #define TPIU_EXTCTLINPORT_EXTCTLIN7_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN7_Pos) /*!< Bit mask of EXTCTLIN7 field.         */
75988   #define TPIU_EXTCTLINPORT_EXTCTLIN7_Min (0x0UL)    /*!< Min enumerator value of EXTCTLIN7 field.                             */
75989   #define TPIU_EXTCTLINPORT_EXTCTLIN7_Max (0x1UL)    /*!< Max enumerator value of EXTCTLIN7 field.                             */
75990   #define TPIU_EXTCTLINPORT_EXTCTLIN7_Low (0x0UL)    /*!< Input EXTCTL7 is low.                                                */
75991   #define TPIU_EXTCTLINPORT_EXTCTLIN7_High (0x1UL)   /*!< Input EXTCTL7 is high.                                               */
75992 
75993 
75994 /* TPIU_EXTCTLOUTPORT: Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers,
75995                         or other solutions that might be added to the trace output pins either for pin control or a high speed
75996                         trace port solution. These ports are raw register banks that sample or export the corresponding external
75997                         pins. */
75998 
75999   #define TPIU_EXTCTLOUTPORT_ResetValue (0x00000000UL) /*!< Reset value of EXTCTLOUTPORT register.                             */
76000 
76001 /* EXTCTLOUT0 @Bit 0 : EXTCTL outputs. */
76002   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Pos (0UL)    /*!< Position of EXTCTLOUT0 field.                                        */
76003   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Pos) /*!< Bit mask of EXTCTLOUT0 field.    */
76004   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Min (0x0UL)  /*!< Min enumerator value of EXTCTLOUT0 field.                            */
76005   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Max (0x1UL)  /*!< Max enumerator value of EXTCTLOUT0 field.                            */
76006   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_Low (0x0UL)  /*!< Output EXTCTL0 is low.                                               */
76007   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT0_High (0x1UL) /*!< Output EXTCTL0 is high.                                              */
76008 
76009 /* EXTCTLOUT1 @Bit 1 : EXTCTL outputs. */
76010   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Pos (1UL)    /*!< Position of EXTCTLOUT1 field.                                        */
76011   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Pos) /*!< Bit mask of EXTCTLOUT1 field.    */
76012   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Min (0x0UL)  /*!< Min enumerator value of EXTCTLOUT1 field.                            */
76013   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Max (0x1UL)  /*!< Max enumerator value of EXTCTLOUT1 field.                            */
76014   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_Low (0x0UL)  /*!< Output EXTCTL1 is low.                                               */
76015   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT1_High (0x1UL) /*!< Output EXTCTL1 is high.                                              */
76016 
76017 /* EXTCTLOUT2 @Bit 2 : EXTCTL outputs. */
76018   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Pos (2UL)    /*!< Position of EXTCTLOUT2 field.                                        */
76019   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Pos) /*!< Bit mask of EXTCTLOUT2 field.    */
76020   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Min (0x0UL)  /*!< Min enumerator value of EXTCTLOUT2 field.                            */
76021   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Max (0x1UL)  /*!< Max enumerator value of EXTCTLOUT2 field.                            */
76022   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_Low (0x0UL)  /*!< Output EXTCTL2 is low.                                               */
76023   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT2_High (0x1UL) /*!< Output EXTCTL2 is high.                                              */
76024 
76025 /* EXTCTLOUT3 @Bit 3 : EXTCTL outputs. */
76026   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Pos (3UL)    /*!< Position of EXTCTLOUT3 field.                                        */
76027   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Pos) /*!< Bit mask of EXTCTLOUT3 field.    */
76028   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Min (0x0UL)  /*!< Min enumerator value of EXTCTLOUT3 field.                            */
76029   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Max (0x1UL)  /*!< Max enumerator value of EXTCTLOUT3 field.                            */
76030   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_Low (0x0UL)  /*!< Output EXTCTL3 is low.                                               */
76031   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT3_High (0x1UL) /*!< Output EXTCTL3 is high.                                              */
76032 
76033 /* EXTCTLOUT4 @Bit 4 : EXTCTL outputs. */
76034   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Pos (4UL)    /*!< Position of EXTCTLOUT4 field.                                        */
76035   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Pos) /*!< Bit mask of EXTCTLOUT4 field.    */
76036   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Min (0x0UL)  /*!< Min enumerator value of EXTCTLOUT4 field.                            */
76037   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Max (0x1UL)  /*!< Max enumerator value of EXTCTLOUT4 field.                            */
76038   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_Low (0x0UL)  /*!< Output EXTCTL4 is low.                                               */
76039   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT4_High (0x1UL) /*!< Output EXTCTL4 is high.                                              */
76040 
76041 /* EXTCTLOUT5 @Bit 5 : EXTCTL outputs. */
76042   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Pos (5UL)    /*!< Position of EXTCTLOUT5 field.                                        */
76043   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Pos) /*!< Bit mask of EXTCTLOUT5 field.    */
76044   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Min (0x0UL)  /*!< Min enumerator value of EXTCTLOUT5 field.                            */
76045   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Max (0x1UL)  /*!< Max enumerator value of EXTCTLOUT5 field.                            */
76046   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_Low (0x0UL)  /*!< Output EXTCTL5 is low.                                               */
76047   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT5_High (0x1UL) /*!< Output EXTCTL5 is high.                                              */
76048 
76049 /* EXTCTLOUT6 @Bit 6 : EXTCTL outputs. */
76050   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Pos (6UL)    /*!< Position of EXTCTLOUT6 field.                                        */
76051   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Pos) /*!< Bit mask of EXTCTLOUT6 field.    */
76052   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Min (0x0UL)  /*!< Min enumerator value of EXTCTLOUT6 field.                            */
76053   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Max (0x1UL)  /*!< Max enumerator value of EXTCTLOUT6 field.                            */
76054   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_Low (0x0UL)  /*!< Output EXTCTL6 is low.                                               */
76055   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT6_High (0x1UL) /*!< Output EXTCTL6 is high.                                              */
76056 
76057 /* EXTCTLOUT7 @Bit 7 : EXTCTL outputs. */
76058   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Pos (7UL)    /*!< Position of EXTCTLOUT7 field.                                        */
76059   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Pos) /*!< Bit mask of EXTCTLOUT7 field.    */
76060   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Min (0x0UL)  /*!< Min enumerator value of EXTCTLOUT7 field.                            */
76061   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Max (0x1UL)  /*!< Max enumerator value of EXTCTLOUT7 field.                            */
76062   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_Low (0x0UL)  /*!< Output EXTCTL7 is low.                                               */
76063   #define TPIU_EXTCTLOUTPORT_EXTCTLOUT7_High (0x1UL) /*!< Output EXTCTL7 is high.                                              */
76064 
76065 
76066 /* TPIU_ITTRFLINACK: The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. */
76067   #define TPIU_ITTRFLINACK_ResetValue (0x00000000UL) /*!< Reset value of ITTRFLINACK register.                                 */
76068 
76069 /* TRIGINACK @Bit 0 : Sets the value of triginack. */
76070   #define TPIU_ITTRFLINACK_TRIGINACK_Pos (0UL)       /*!< Position of TRIGINACK field.                                         */
76071   #define TPIU_ITTRFLINACK_TRIGINACK_Msk (0x1UL << TPIU_ITTRFLINACK_TRIGINACK_Pos) /*!< Bit mask of TRIGINACK field.           */
76072   #define TPIU_ITTRFLINACK_TRIGINACK_Min (0x0UL)     /*!< Min enumerator value of TRIGINACK field.                             */
76073   #define TPIU_ITTRFLINACK_TRIGINACK_Max (0x1UL)     /*!< Max enumerator value of TRIGINACK field.                             */
76074   #define TPIU_ITTRFLINACK_TRIGINACK_Low (0x0UL)     /*!< Pin is logic 0.                                                      */
76075   #define TPIU_ITTRFLINACK_TRIGINACK_High (0x1UL)    /*!< Pin is logic 1.                                                      */
76076 
76077 /* FLUSHINACK @Bit 1 : Sets the value of flushinack. */
76078   #define TPIU_ITTRFLINACK_FLUSHINACK_Pos (1UL)      /*!< Position of FLUSHINACK field.                                        */
76079   #define TPIU_ITTRFLINACK_FLUSHINACK_Msk (0x1UL << TPIU_ITTRFLINACK_FLUSHINACK_Pos) /*!< Bit mask of FLUSHINACK field.        */
76080   #define TPIU_ITTRFLINACK_FLUSHINACK_Min (0x0UL)    /*!< Min enumerator value of FLUSHINACK field.                            */
76081   #define TPIU_ITTRFLINACK_FLUSHINACK_Max (0x1UL)    /*!< Max enumerator value of FLUSHINACK field.                            */
76082   #define TPIU_ITTRFLINACK_FLUSHINACK_Low (0x0UL)    /*!< Pin is logic 0.                                                      */
76083   #define TPIU_ITTRFLINACK_FLUSHINACK_High (0x1UL)   /*!< Pin is logic 1.                                                      */
76084 
76085 
76086 /* TPIU_ITTRFLIN: The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. */
76087   #define TPIU_ITTRFLIN_ResetValue (0x00000000UL)    /*!< Reset value of ITTRFLIN register.                                    */
76088 
76089 /* TRIGIN @Bit 0 : Reads the value of trigin. */
76090   #define TPIU_ITTRFLIN_TRIGIN_Pos (0UL)             /*!< Position of TRIGIN field.                                            */
76091   #define TPIU_ITTRFLIN_TRIGIN_Msk (0x1UL << TPIU_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field.                          */
76092   #define TPIU_ITTRFLIN_TRIGIN_Min (0x0UL)           /*!< Min enumerator value of TRIGIN field.                                */
76093   #define TPIU_ITTRFLIN_TRIGIN_Max (0x1UL)           /*!< Max enumerator value of TRIGIN field.                                */
76094   #define TPIU_ITTRFLIN_TRIGIN_Low (0x0UL)           /*!< Pin is logic 0.                                                      */
76095   #define TPIU_ITTRFLIN_TRIGIN_High (0x1UL)          /*!< Pin is logic 1.                                                      */
76096 
76097 /* FLUSHIN @Bit 1 : Reads the value of flushin. */
76098   #define TPIU_ITTRFLIN_FLUSHIN_Pos (1UL)            /*!< Position of FLUSHIN field.                                           */
76099   #define TPIU_ITTRFLIN_FLUSHIN_Msk (0x1UL << TPIU_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field.                       */
76100   #define TPIU_ITTRFLIN_FLUSHIN_Min (0x0UL)          /*!< Min enumerator value of FLUSHIN field.                               */
76101   #define TPIU_ITTRFLIN_FLUSHIN_Max (0x1UL)          /*!< Max enumerator value of FLUSHIN field.                               */
76102   #define TPIU_ITTRFLIN_FLUSHIN_Low (0x0UL)          /*!< Pin is logic 0.                                                      */
76103   #define TPIU_ITTRFLIN_FLUSHIN_High (0x1UL)         /*!< Pin is logic 1.                                                      */
76104 
76105 
76106 /* TPIU_ITATBDATA0: The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when
76107                      atvalids is HIGH. */
76108 
76109   #define TPIU_ITATBDATA0_ResetValue (0x00000000UL)  /*!< Reset value of ITATBDATA0 register.                                  */
76110 
76111 /* ATDATA0 @Bit 0 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
76112                     corresponding atdatam pin of the enabled port. */
76113 
76114   #define TPIU_ITATBDATA0_ATDATA0_Pos (0UL)          /*!< Position of ATDATA0 field.                                           */
76115   #define TPIU_ITATBDATA0_ATDATA0_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA0_Pos) /*!< Bit mask of ATDATA0 field.                   */
76116   #define TPIU_ITATBDATA0_ATDATA0_Min (0x0UL)        /*!< Min enumerator value of ATDATA0 field.                               */
76117   #define TPIU_ITATBDATA0_ATDATA0_Max (0x1UL)        /*!< Max enumerator value of ATDATA0 field.                               */
76118   #define TPIU_ITATBDATA0_ATDATA0_Low (0x0UL)        /*!< Pin is logic 0.                                                      */
76119   #define TPIU_ITATBDATA0_ATDATA0_High (0x1UL)       /*!< Pin is logic 1.                                                      */
76120 
76121 /* ATDATA1 @Bit 1 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
76122                     corresponding atdatam pin of the enabled port. */
76123 
76124   #define TPIU_ITATBDATA0_ATDATA1_Pos (1UL)          /*!< Position of ATDATA1 field.                                           */
76125   #define TPIU_ITATBDATA0_ATDATA1_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA1_Pos) /*!< Bit mask of ATDATA1 field.                   */
76126   #define TPIU_ITATBDATA0_ATDATA1_Min (0x0UL)        /*!< Min enumerator value of ATDATA1 field.                               */
76127   #define TPIU_ITATBDATA0_ATDATA1_Max (0x1UL)        /*!< Max enumerator value of ATDATA1 field.                               */
76128   #define TPIU_ITATBDATA0_ATDATA1_Low (0x0UL)        /*!< Pin is logic 0.                                                      */
76129   #define TPIU_ITATBDATA0_ATDATA1_High (0x1UL)       /*!< Pin is logic 1.                                                      */
76130 
76131 /* ATDATA2 @Bit 2 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
76132                     corresponding atdatam pin of the enabled port. */
76133 
76134   #define TPIU_ITATBDATA0_ATDATA2_Pos (2UL)          /*!< Position of ATDATA2 field.                                           */
76135   #define TPIU_ITATBDATA0_ATDATA2_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA2_Pos) /*!< Bit mask of ATDATA2 field.                   */
76136   #define TPIU_ITATBDATA0_ATDATA2_Min (0x0UL)        /*!< Min enumerator value of ATDATA2 field.                               */
76137   #define TPIU_ITATBDATA0_ATDATA2_Max (0x1UL)        /*!< Max enumerator value of ATDATA2 field.                               */
76138   #define TPIU_ITATBDATA0_ATDATA2_Low (0x0UL)        /*!< Pin is logic 0.                                                      */
76139   #define TPIU_ITATBDATA0_ATDATA2_High (0x1UL)       /*!< Pin is logic 1.                                                      */
76140 
76141 /* ATDATA3 @Bit 3 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
76142                     corresponding atdatam pin of the enabled port. */
76143 
76144   #define TPIU_ITATBDATA0_ATDATA3_Pos (3UL)          /*!< Position of ATDATA3 field.                                           */
76145   #define TPIU_ITATBDATA0_ATDATA3_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA3_Pos) /*!< Bit mask of ATDATA3 field.                   */
76146   #define TPIU_ITATBDATA0_ATDATA3_Min (0x0UL)        /*!< Min enumerator value of ATDATA3 field.                               */
76147   #define TPIU_ITATBDATA0_ATDATA3_Max (0x1UL)        /*!< Max enumerator value of ATDATA3 field.                               */
76148   #define TPIU_ITATBDATA0_ATDATA3_Low (0x0UL)        /*!< Pin is logic 0.                                                      */
76149   #define TPIU_ITATBDATA0_ATDATA3_High (0x1UL)       /*!< Pin is logic 1.                                                      */
76150 
76151 /* ATDATA4 @Bit 4 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the
76152                     corresponding atdatam pin of the enabled port. */
76153 
76154   #define TPIU_ITATBDATA0_ATDATA4_Pos (4UL)          /*!< Position of ATDATA4 field.                                           */
76155   #define TPIU_ITATBDATA0_ATDATA4_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA4_Pos) /*!< Bit mask of ATDATA4 field.                   */
76156   #define TPIU_ITATBDATA0_ATDATA4_Min (0x0UL)        /*!< Min enumerator value of ATDATA4 field.                               */
76157   #define TPIU_ITATBDATA0_ATDATA4_Max (0x1UL)        /*!< Max enumerator value of ATDATA4 field.                               */
76158   #define TPIU_ITATBDATA0_ATDATA4_Low (0x0UL)        /*!< Pin is logic 0.                                                      */
76159   #define TPIU_ITATBDATA0_ATDATA4_High (0x1UL)       /*!< Pin is logic 1.                                                      */
76160 
76161 
76162 /* TPIU_ITATBCTR2: Enables control of the atreadys and afvalids outputs of the TPIU. */
76163   #define TPIU_ITATBCTR2_ResetValue (0x00000000UL)   /*!< Reset value of ITATBCTR2 register.                                   */
76164 
76165 /* ATREADY @Bit 0 : Sets the value of afvalid. */
76166   #define TPIU_ITATBCTR2_ATREADY_Pos (0UL)           /*!< Position of ATREADY field.                                           */
76167   #define TPIU_ITATBCTR2_ATREADY_Msk (0x1UL << TPIU_ITATBCTR2_ATREADY_Pos) /*!< Bit mask of ATREADY field.                     */
76168   #define TPIU_ITATBCTR2_ATREADY_Min (0x0UL)         /*!< Min enumerator value of ATREADY field.                               */
76169   #define TPIU_ITATBCTR2_ATREADY_Max (0x1UL)         /*!< Max enumerator value of ATREADY field.                               */
76170   #define TPIU_ITATBCTR2_ATREADY_Low (0x0UL)         /*!< Pin is logic 0.                                                      */
76171   #define TPIU_ITATBCTR2_ATREADY_High (0x1UL)        /*!< Pin is logic 1.                                                      */
76172 
76173 /* AFVALID @Bit 1 : Sets the value of atready. */
76174   #define TPIU_ITATBCTR2_AFVALID_Pos (1UL)           /*!< Position of AFVALID field.                                           */
76175   #define TPIU_ITATBCTR2_AFVALID_Msk (0x1UL << TPIU_ITATBCTR2_AFVALID_Pos) /*!< Bit mask of AFVALID field.                     */
76176   #define TPIU_ITATBCTR2_AFVALID_Min (0x0UL)         /*!< Min enumerator value of AFVALID field.                               */
76177   #define TPIU_ITATBCTR2_AFVALID_Max (0x1UL)         /*!< Max enumerator value of AFVALID field.                               */
76178   #define TPIU_ITATBCTR2_AFVALID_Low (0x0UL)         /*!< Pin is logic 0.                                                      */
76179   #define TPIU_ITATBCTR2_AFVALID_High (0x1UL)        /*!< Pin is logic 1.                                                      */
76180 
76181 
76182 /* TPIU_ITATBCTR1: The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is
76183                     HIGH. */
76184 
76185   #define TPIU_ITATBCTR1_ResetValue (0x00000000UL)   /*!< Reset value of ITATBCTR1 register.                                   */
76186 
76187 /* ATID @Bits 0..6 : Reads the value of atids. */
76188   #define TPIU_ITATBCTR1_ATID_Pos (0UL)              /*!< Position of ATID field.                                              */
76189   #define TPIU_ITATBCTR1_ATID_Msk (0x7FUL << TPIU_ITATBCTR1_ATID_Pos) /*!< Bit mask of ATID field.                             */
76190   #define TPIU_ITATBCTR1_ATID_Min (0x0UL)            /*!< Min enumerator value of ATID field.                                  */
76191   #define TPIU_ITATBCTR1_ATID_Max (0x1UL)            /*!< Max enumerator value of ATID field.                                  */
76192   #define TPIU_ITATBCTR1_ATID_Low (0x00UL)           /*!< Pin is logic 0.                                                      */
76193   #define TPIU_ITATBCTR1_ATID_High (0x01UL)          /*!< Pin is logic 1.                                                      */
76194 
76195 
76196 /* TPIU_ITATBCTR0: The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. To
76197                     ensure the integration registers work correctly in a system, the value of atbytess is only valid when
76198                     atvalids, bit[0], is HIGH. */
76199 
76200   #define TPIU_ITATBCTR0_ResetValue (0x00000000UL)   /*!< Reset value of ITATBCTR0 register.                                   */
76201 
76202 /* ATVALID @Bit 0 : Reads the value of atvalids. */
76203   #define TPIU_ITATBCTR0_ATVALID_Pos (0UL)           /*!< Position of ATVALID field.                                           */
76204   #define TPIU_ITATBCTR0_ATVALID_Msk (0x1UL << TPIU_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field.                     */
76205   #define TPIU_ITATBCTR0_ATVALID_Min (0x0UL)         /*!< Min enumerator value of ATVALID field.                               */
76206   #define TPIU_ITATBCTR0_ATVALID_Max (0x1UL)         /*!< Max enumerator value of ATVALID field.                               */
76207   #define TPIU_ITATBCTR0_ATVALID_Low (0x0UL)         /*!< Pin is logic 0.                                                      */
76208   #define TPIU_ITATBCTR0_ATVALID_High (0x1UL)        /*!< Pin is logic 1.                                                      */
76209 
76210 /* AFREADY @Bit 2 : Reads the value of afreadys. */
76211   #define TPIU_ITATBCTR0_AFREADY_Pos (2UL)           /*!< Position of AFREADY field.                                           */
76212   #define TPIU_ITATBCTR0_AFREADY_Msk (0x1UL << TPIU_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field.                     */
76213   #define TPIU_ITATBCTR0_AFREADY_Min (0x0UL)         /*!< Min enumerator value of AFREADY field.                               */
76214   #define TPIU_ITATBCTR0_AFREADY_Max (0x1UL)         /*!< Max enumerator value of AFREADY field.                               */
76215   #define TPIU_ITATBCTR0_AFREADY_Low (0x0UL)         /*!< Pin is logic 0.                                                      */
76216   #define TPIU_ITATBCTR0_AFREADY_High (0x1UL)        /*!< Pin is logic 1.                                                      */
76217 
76218 /* ATBYTES @Bits 8..9 : Reads the value of atbytess. */
76219   #define TPIU_ITATBCTR0_ATBYTES_Pos (8UL)           /*!< Position of ATBYTES field.                                           */
76220   #define TPIU_ITATBCTR0_ATBYTES_Msk (0x3UL << TPIU_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field.                     */
76221   #define TPIU_ITATBCTR0_ATBYTES_Min (0x0UL)         /*!< Min enumerator value of ATBYTES field.                               */
76222   #define TPIU_ITATBCTR0_ATBYTES_Max (0x1UL)         /*!< Max enumerator value of ATBYTES field.                               */
76223   #define TPIU_ITATBCTR0_ATBYTES_Low (0x0UL)         /*!< Pin is logic 0.                                                      */
76224   #define TPIU_ITATBCTR0_ATBYTES_High (0x1UL)        /*!< Pin is logic 1.                                                      */
76225 
76226 
76227 /* TPIU_ITCTRL: Used to enable topology detection. This register enables the component to switch from a functional mode, the
76228                  default behavior, to integration mode where the inputs and outputs of the component can be directly controlled
76229                  for integration testing and topology solving. */
76230 
76231   #define TPIU_ITCTRL_ResetValue (0x00000000UL)      /*!< Reset value of ITCTRL register.                                      */
76232 
76233 /* INTEGRATIONMODE @Bit 0 : Enables the component to switch from functional mode to integration mode and back. If no integration
76234                             functionality is implemented, this register must read as zero. */
76235 
76236   #define TPIU_ITCTRL_INTEGRATIONMODE_Pos (0UL)      /*!< Position of INTEGRATIONMODE field.                                   */
76237   #define TPIU_ITCTRL_INTEGRATIONMODE_Msk (0x1UL << TPIU_ITCTRL_INTEGRATIONMODE_Pos) /*!< Bit mask of INTEGRATIONMODE field.   */
76238   #define TPIU_ITCTRL_INTEGRATIONMODE_Min (0x0UL)    /*!< Min enumerator value of INTEGRATIONMODE field.                       */
76239   #define TPIU_ITCTRL_INTEGRATIONMODE_Max (0x1UL)    /*!< Max enumerator value of INTEGRATIONMODE field.                       */
76240   #define TPIU_ITCTRL_INTEGRATIONMODE_Disabled (0x0UL) /*!< Integration mode is disabled.                                      */
76241   #define TPIU_ITCTRL_INTEGRATIONMODE_Enabled (0x1UL) /*!< Integration mode is Enabled.                                        */
76242 
76243 
76244 /* TPIU_CLAIMSET: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The
76245                    claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim
76246                    tag, and determines the number of claim bits implemented. */
76247 
76248   #define TPIU_CLAIMSET_ResetValue (0x00000000UL)    /*!< Reset value of CLAIMSET register.                                    */
76249 
76250 /* BIT0 @Bit 0 : Set claim bit 0 and check if bit is implemented or not. */
76251   #define TPIU_CLAIMSET_BIT0_Pos (0UL)               /*!< Position of BIT0 field.                                              */
76252   #define TPIU_CLAIMSET_BIT0_Msk (0x1UL << TPIU_CLAIMSET_BIT0_Pos) /*!< Bit mask of BIT0 field.                                */
76253   #define TPIU_CLAIMSET_BIT0_Min (0x0UL)             /*!< Min enumerator value of BIT0 field.                                  */
76254   #define TPIU_CLAIMSET_BIT0_Max (0x1UL)             /*!< Max enumerator value of BIT0 field.                                  */
76255   #define TPIU_CLAIMSET_BIT0_NotImplemented (0x0UL)  /*!< Claim bit 0 is not implemented.                                      */
76256   #define TPIU_CLAIMSET_BIT0_Implemented (0x1UL)     /*!< Claim bit 0 is implemented.                                          */
76257   #define TPIU_CLAIMSET_BIT0_Set (0x1UL)             /*!< Set claim bit 0.                                                     */
76258 
76259 /* BIT1 @Bit 1 : Set claim bit 1 and check if bit is implemented or not. */
76260   #define TPIU_CLAIMSET_BIT1_Pos (1UL)               /*!< Position of BIT1 field.                                              */
76261   #define TPIU_CLAIMSET_BIT1_Msk (0x1UL << TPIU_CLAIMSET_BIT1_Pos) /*!< Bit mask of BIT1 field.                                */
76262   #define TPIU_CLAIMSET_BIT1_Min (0x0UL)             /*!< Min enumerator value of BIT1 field.                                  */
76263   #define TPIU_CLAIMSET_BIT1_Max (0x1UL)             /*!< Max enumerator value of BIT1 field.                                  */
76264   #define TPIU_CLAIMSET_BIT1_NotImplemented (0x0UL)  /*!< Claim bit 1 is not implemented.                                      */
76265   #define TPIU_CLAIMSET_BIT1_Implemented (0x1UL)     /*!< Claim bit 1 is implemented.                                          */
76266   #define TPIU_CLAIMSET_BIT1_Set (0x1UL)             /*!< Set claim bit 1.                                                     */
76267 
76268 /* BIT2 @Bit 2 : Set claim bit 2 and check if bit is implemented or not. */
76269   #define TPIU_CLAIMSET_BIT2_Pos (2UL)               /*!< Position of BIT2 field.                                              */
76270   #define TPIU_CLAIMSET_BIT2_Msk (0x1UL << TPIU_CLAIMSET_BIT2_Pos) /*!< Bit mask of BIT2 field.                                */
76271   #define TPIU_CLAIMSET_BIT2_Min (0x0UL)             /*!< Min enumerator value of BIT2 field.                                  */
76272   #define TPIU_CLAIMSET_BIT2_Max (0x1UL)             /*!< Max enumerator value of BIT2 field.                                  */
76273   #define TPIU_CLAIMSET_BIT2_NotImplemented (0x0UL)  /*!< Claim bit 2 is not implemented.                                      */
76274   #define TPIU_CLAIMSET_BIT2_Implemented (0x1UL)     /*!< Claim bit 2 is implemented.                                          */
76275   #define TPIU_CLAIMSET_BIT2_Set (0x1UL)             /*!< Set claim bit 2.                                                     */
76276 
76277 /* BIT3 @Bit 3 : Set claim bit 3 and check if bit is implemented or not. */
76278   #define TPIU_CLAIMSET_BIT3_Pos (3UL)               /*!< Position of BIT3 field.                                              */
76279   #define TPIU_CLAIMSET_BIT3_Msk (0x1UL << TPIU_CLAIMSET_BIT3_Pos) /*!< Bit mask of BIT3 field.                                */
76280   #define TPIU_CLAIMSET_BIT3_Min (0x0UL)             /*!< Min enumerator value of BIT3 field.                                  */
76281   #define TPIU_CLAIMSET_BIT3_Max (0x1UL)             /*!< Max enumerator value of BIT3 field.                                  */
76282   #define TPIU_CLAIMSET_BIT3_NotImplemented (0x0UL)  /*!< Claim bit 3 is not implemented.                                      */
76283   #define TPIU_CLAIMSET_BIT3_Implemented (0x1UL)     /*!< Claim bit 3 is implemented.                                          */
76284   #define TPIU_CLAIMSET_BIT3_Set (0x1UL)             /*!< Set claim bit 3.                                                     */
76285 
76286 
76287 /* TPIU_CLAIMCLR: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The
76288                    claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim
76289                    tag to 0 and determines the current value of the claim tag. */
76290 
76291   #define TPIU_CLAIMCLR_ResetValue (0x00000000UL)    /*!< Reset value of CLAIMCLR register.                                    */
76292 
76293 /* BIT0 @Bit 0 : Read or clear claim bit 0. */
76294   #define TPIU_CLAIMCLR_BIT0_Pos (0UL)               /*!< Position of BIT0 field.                                              */
76295   #define TPIU_CLAIMCLR_BIT0_Msk (0x1UL << TPIU_CLAIMCLR_BIT0_Pos) /*!< Bit mask of BIT0 field.                                */
76296   #define TPIU_CLAIMCLR_BIT0_Min (0x0UL)             /*!< Min enumerator value of BIT0 field.                                  */
76297   #define TPIU_CLAIMCLR_BIT0_Max (0x1UL)             /*!< Max enumerator value of BIT0 field.                                  */
76298   #define TPIU_CLAIMCLR_BIT0_Cleared (0x0UL)         /*!< Claim bit 0 is not set.                                              */
76299   #define TPIU_CLAIMCLR_BIT0_Set (0x1UL)             /*!< Claim bit 0 is set.                                                  */
76300   #define TPIU_CLAIMCLR_BIT0_Clear (0x1UL)           /*!< Clear claim bit 0.                                                   */
76301 
76302 /* BIT1 @Bit 1 : Read or clear claim bit 1. */
76303   #define TPIU_CLAIMCLR_BIT1_Pos (1UL)               /*!< Position of BIT1 field.                                              */
76304   #define TPIU_CLAIMCLR_BIT1_Msk (0x1UL << TPIU_CLAIMCLR_BIT1_Pos) /*!< Bit mask of BIT1 field.                                */
76305   #define TPIU_CLAIMCLR_BIT1_Min (0x0UL)             /*!< Min enumerator value of BIT1 field.                                  */
76306   #define TPIU_CLAIMCLR_BIT1_Max (0x1UL)             /*!< Max enumerator value of BIT1 field.                                  */
76307   #define TPIU_CLAIMCLR_BIT1_Cleared (0x0UL)         /*!< Claim bit 1 is not set.                                              */
76308   #define TPIU_CLAIMCLR_BIT1_Set (0x1UL)             /*!< Claim bit 1 is set.                                                  */
76309   #define TPIU_CLAIMCLR_BIT1_Clear (0x1UL)           /*!< Clear claim bit 1.                                                   */
76310 
76311 /* BIT2 @Bit 2 : Read or clear claim bit 2. */
76312   #define TPIU_CLAIMCLR_BIT2_Pos (2UL)               /*!< Position of BIT2 field.                                              */
76313   #define TPIU_CLAIMCLR_BIT2_Msk (0x1UL << TPIU_CLAIMCLR_BIT2_Pos) /*!< Bit mask of BIT2 field.                                */
76314   #define TPIU_CLAIMCLR_BIT2_Min (0x0UL)             /*!< Min enumerator value of BIT2 field.                                  */
76315   #define TPIU_CLAIMCLR_BIT2_Max (0x1UL)             /*!< Max enumerator value of BIT2 field.                                  */
76316   #define TPIU_CLAIMCLR_BIT2_Cleared (0x0UL)         /*!< Claim bit 2 is not set.                                              */
76317   #define TPIU_CLAIMCLR_BIT2_Set (0x1UL)             /*!< Claim bit 2 is set.                                                  */
76318   #define TPIU_CLAIMCLR_BIT2_Clear (0x1UL)           /*!< Clear claim bit 2.                                                   */
76319 
76320 /* BIT3 @Bit 3 : Read or clear claim bit 3. */
76321   #define TPIU_CLAIMCLR_BIT3_Pos (3UL)               /*!< Position of BIT3 field.                                              */
76322   #define TPIU_CLAIMCLR_BIT3_Msk (0x1UL << TPIU_CLAIMCLR_BIT3_Pos) /*!< Bit mask of BIT3 field.                                */
76323   #define TPIU_CLAIMCLR_BIT3_Min (0x0UL)             /*!< Min enumerator value of BIT3 field.                                  */
76324   #define TPIU_CLAIMCLR_BIT3_Max (0x1UL)             /*!< Max enumerator value of BIT3 field.                                  */
76325   #define TPIU_CLAIMCLR_BIT3_Cleared (0x0UL)         /*!< Claim bit 3 is not set.                                              */
76326   #define TPIU_CLAIMCLR_BIT3_Set (0x1UL)             /*!< Claim bit 3 is set.                                                  */
76327   #define TPIU_CLAIMCLR_BIT3_Clear (0x1UL)           /*!< Clear claim bit 3.                                                   */
76328 
76329 
76330 /* TPIU_LAR: This is used to enable write access to device registers. */
76331   #define TPIU_LAR_ResetValue (0x00000000UL)         /*!< Reset value of LAR register.                                         */
76332 
76333 /* ACCESS @Bits 0..31 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access.
76334                         */
76335 
76336   #define TPIU_LAR_ACCESS_Pos (0UL)                  /*!< Position of ACCESS field.                                            */
76337   #define TPIU_LAR_ACCESS_Msk (0xFFFFFFFFUL << TPIU_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field.                             */
76338   #define TPIU_LAR_ACCESS_Min (0xC5ACCE55UL)         /*!< Min enumerator value of ACCESS field.                                */
76339   #define TPIU_LAR_ACCESS_Max (0xC5ACCE55UL)         /*!< Max enumerator value of ACCESS field.                                */
76340   #define TPIU_LAR_ACCESS_UnLock (0xC5ACCE55UL)      /*!< Unlock register interface.                                           */
76341 
76342 
76343 /* TPIU_LSR: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug.
76344               Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always
76345               be present although there might not be any lock access control mechanism. The lock mechanism, where present and
76346               locked, must block write accesses to any control register, except the Lock Access Register. For most components
76347               this covers all registers except for the Lock Access Register. */
76348 
76349   #define TPIU_LSR_ResetValue (0x00000000UL)         /*!< Reset value of LSR register.                                         */
76350 
76351 /* PRESENT @Bit 0 : Indicates that a lock control mechanism exists for this device. */
76352   #define TPIU_LSR_PRESENT_Pos (0UL)                 /*!< Position of PRESENT field.                                           */
76353   #define TPIU_LSR_PRESENT_Msk (0x1UL << TPIU_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field.                                 */
76354   #define TPIU_LSR_PRESENT_Min (0x0UL)               /*!< Min enumerator value of PRESENT field.                               */
76355   #define TPIU_LSR_PRESENT_Max (0x1UL)               /*!< Max enumerator value of PRESENT field.                               */
76356   #define TPIU_LSR_PRESENT_NotImplemented (0x0UL)    /*!< No lock control mechanism exists, writes to the Lock Access Register
76357                                                           are ignored.*/
76358   #define TPIU_LSR_PRESENT_Implemented (0x1UL)       /*!< Lock control mechanism is present.                                   */
76359 
76360 /* LOCKED @Bit 1 : Returns the current status of the Lock. */
76361   #define TPIU_LSR_LOCKED_Pos (1UL)                  /*!< Position of LOCKED field.                                            */
76362   #define TPIU_LSR_LOCKED_Msk (0x1UL << TPIU_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field.                                    */
76363   #define TPIU_LSR_LOCKED_Min (0x0UL)                /*!< Min enumerator value of LOCKED field.                                */
76364   #define TPIU_LSR_LOCKED_Max (0x1UL)                /*!< Max enumerator value of LOCKED field.                                */
76365   #define TPIU_LSR_LOCKED_UnLocked (0x0UL)           /*!< Write access is allowed to this device.                              */
76366   #define TPIU_LSR_LOCKED_Locked (0x1UL)             /*!< Write access to the component is blocked. All writes to control
76367                                                           registers are ignored. Reads are permitted.*/
76368 
76369 /* TYPE @Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */
76370   #define TPIU_LSR_TYPE_Pos (2UL)                    /*!< Position of TYPE field.                                              */
76371   #define TPIU_LSR_TYPE_Msk (0x1UL << TPIU_LSR_TYPE_Pos) /*!< Bit mask of TYPE field.                                          */
76372   #define TPIU_LSR_TYPE_Min (0x0UL)                  /*!< Min enumerator value of TYPE field.                                  */
76373   #define TPIU_LSR_TYPE_Max (0x1UL)                  /*!< Max enumerator value of TYPE field.                                  */
76374   #define TPIU_LSR_TYPE_Bits32 (0x0UL)               /*!< This component implements a 32-bit Lock Access Register.             */
76375   #define TPIU_LSR_TYPE_Bits8 (0x1UL)                /*!< This component implements an 8-bit Lock Access Register.             */
76376 
76377 
76378 /* TPIU_AUTHSTATUS: Indicates the current level of tracing permitted by the system */
76379   #define TPIU_AUTHSTATUS_ResetValue (0x00000000UL)  /*!< Reset value of AUTHSTATUS register.                                  */
76380 
76381 /* NSID @Bits 0..1 : Non-secure Invasive Debug */
76382   #define TPIU_AUTHSTATUS_NSID_Pos (0UL)             /*!< Position of NSID field.                                              */
76383   #define TPIU_AUTHSTATUS_NSID_Msk (0x3UL << TPIU_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field.                            */
76384   #define TPIU_AUTHSTATUS_NSID_Min (0x0UL)           /*!< Min enumerator value of NSID field.                                  */
76385   #define TPIU_AUTHSTATUS_NSID_Max (0x1UL)           /*!< Max enumerator value of NSID field.                                  */
76386   #define TPIU_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                     */
76387   #define TPIU_AUTHSTATUS_NSID_Implemented (0x1UL)   /*!< The feature is implemented.                                          */
76388 
76389 /* NSNID @Bits 2..3 : Non-secure Non-Invasive Debug */
76390   #define TPIU_AUTHSTATUS_NSNID_Pos (2UL)            /*!< Position of NSNID field.                                             */
76391   #define TPIU_AUTHSTATUS_NSNID_Msk (0x3UL << TPIU_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field.                         */
76392   #define TPIU_AUTHSTATUS_NSNID_Min (0x0UL)          /*!< Min enumerator value of NSNID field.                                 */
76393   #define TPIU_AUTHSTATUS_NSNID_Max (0x1UL)          /*!< Max enumerator value of NSNID field.                                 */
76394   #define TPIU_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                    */
76395   #define TPIU_AUTHSTATUS_NSNID_Implemented (0x1UL)  /*!< The feature is implemented.                                          */
76396 
76397 /* SID @Bits 4..5 : Secure Invasive Debug */
76398   #define TPIU_AUTHSTATUS_SID_Pos (4UL)              /*!< Position of SID field.                                               */
76399   #define TPIU_AUTHSTATUS_SID_Msk (0x3UL << TPIU_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field.                               */
76400   #define TPIU_AUTHSTATUS_SID_Min (0x0UL)            /*!< Min enumerator value of SID field.                                   */
76401   #define TPIU_AUTHSTATUS_SID_Max (0x1UL)            /*!< Max enumerator value of SID field.                                   */
76402   #define TPIU_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                      */
76403   #define TPIU_AUTHSTATUS_SID_Implemented (0x1UL)    /*!< The feature is implemented.                                          */
76404 
76405 /* SNID @Bits 6..7 : Secure Non-Invasive Debug */
76406   #define TPIU_AUTHSTATUS_SNID_Pos (6UL)             /*!< Position of SNID field.                                              */
76407   #define TPIU_AUTHSTATUS_SNID_Msk (0x3UL << TPIU_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field.                            */
76408   #define TPIU_AUTHSTATUS_SNID_Min (0x0UL)           /*!< Min enumerator value of SNID field.                                  */
76409   #define TPIU_AUTHSTATUS_SNID_Max (0x1UL)           /*!< Max enumerator value of SNID field.                                  */
76410   #define TPIU_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented.                                     */
76411   #define TPIU_AUTHSTATUS_SNID_Implemented (0x1UL)   /*!< The feature is implemented.                                          */
76412 
76413 
76414 /* TPIU_DEVID: Indicates the capabilities of the component. */
76415   #define TPIU_DEVID_ResetValue (0x00000000UL)       /*!< Reset value of DEVID register.                                       */
76416 
76417 /* MUXNUM @Bits 0..4 : Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of
76418                        multiplexing on the input to the ATB. Currently only 0x00 is supported, that is, no multiplexing is
76419                        present. This value helps detect the ATB structure. */
76420 
76421   #define TPIU_DEVID_MUXNUM_Pos (0UL)                /*!< Position of MUXNUM field.                                            */
76422   #define TPIU_DEVID_MUXNUM_Msk (0x1FUL << TPIU_DEVID_MUXNUM_Pos) /*!< Bit mask of MUXNUM field.                               */
76423 
76424 /* CLKRELAT @Bit 5 : Indicates the relationship between atclk and traceclkin. */
76425   #define TPIU_DEVID_CLKRELAT_Pos (5UL)              /*!< Position of CLKRELAT field.                                          */
76426   #define TPIU_DEVID_CLKRELAT_Msk (0x1UL << TPIU_DEVID_CLKRELAT_Pos) /*!< Bit mask of CLKRELAT field.                          */
76427   #define TPIU_DEVID_CLKRELAT_Min (0x0UL)            /*!< Min enumerator value of CLKRELAT field.                              */
76428   #define TPIU_DEVID_CLKRELAT_Max (0x1UL)            /*!< Max enumerator value of CLKRELAT field.                              */
76429   #define TPIU_DEVID_CLKRELAT_Synchronous (0x0UL)    /*!< atclk and traceclkin are synchronous.                                */
76430   #define TPIU_DEVID_CLKRELAT_ASynchronous (0x1UL)   /*!< atclk and traceclkin are asynchronous.                               */
76431 
76432 /* FIFOSIZE @Bits 6..8 : FIFO size in powers of 2. */
76433   #define TPIU_DEVID_FIFOSIZE_Pos (6UL)              /*!< Position of FIFOSIZE field.                                          */
76434   #define TPIU_DEVID_FIFOSIZE_Msk (0x7UL << TPIU_DEVID_FIFOSIZE_Pos) /*!< Bit mask of FIFOSIZE field.                          */
76435   #define TPIU_DEVID_FIFOSIZE_Min (0x2UL)            /*!< Min enumerator value of FIFOSIZE field.                              */
76436   #define TPIU_DEVID_FIFOSIZE_Max (0x2UL)            /*!< Max enumerator value of FIFOSIZE field.                              */
76437   #define TPIU_DEVID_FIFOSIZE_Entries4 (0x2UL)       /*!< FIFO size of 4 entries, that is, 16 bytes.                           */
76438 
76439 /* TCLKDATA @Bit 9 : Indicates whether trace clock plus data is supported. */
76440   #define TPIU_DEVID_TCLKDATA_Pos (9UL)              /*!< Position of TCLKDATA field.                                          */
76441   #define TPIU_DEVID_TCLKDATA_Msk (0x1UL << TPIU_DEVID_TCLKDATA_Pos) /*!< Bit mask of TCLKDATA field.                          */
76442   #define TPIU_DEVID_TCLKDATA_Min (0x0UL)            /*!< Min enumerator value of TCLKDATA field.                              */
76443   #define TPIU_DEVID_TCLKDATA_Max (0x1UL)            /*!< Max enumerator value of TCLKDATA field.                              */
76444   #define TPIU_DEVID_TCLKDATA_Supported (0x0UL)      /*!< Trace clock and data is supported.                                   */
76445   #define TPIU_DEVID_TCLKDATA_NotSupported (0x1UL)   /*!< Trace clock and data is not supported.                               */
76446 
76447 /* SWOMAN @Bit 10 : Indicates whether Serial Wire Output, Manchester encoded format, is supported. */
76448   #define TPIU_DEVID_SWOMAN_Pos (10UL)               /*!< Position of SWOMAN field.                                            */
76449   #define TPIU_DEVID_SWOMAN_Msk (0x1UL << TPIU_DEVID_SWOMAN_Pos) /*!< Bit mask of SWOMAN field.                                */
76450   #define TPIU_DEVID_SWOMAN_Min (0x0UL)              /*!< Min enumerator value of SWOMAN field.                                */
76451   #define TPIU_DEVID_SWOMAN_Max (0x1UL)              /*!< Max enumerator value of SWOMAN field.                                */
76452   #define TPIU_DEVID_SWOMAN_NotSupported (0x0UL)     /*!< Serial Wire Output, Manchester encoded format, is not supported.     */
76453   #define TPIU_DEVID_SWOMAN_Supported (0x1UL)        /*!< Serial Wire Output, Manchester encoded format, is supported.         */
76454 
76455 /* SWOUARTNRZ @Bit 11 : Indicates whether Serial Wire Output, UART or NRZ, is supported. */
76456   #define TPIU_DEVID_SWOUARTNRZ_Pos (11UL)           /*!< Position of SWOUARTNRZ field.                                        */
76457   #define TPIU_DEVID_SWOUARTNRZ_Msk (0x1UL << TPIU_DEVID_SWOUARTNRZ_Pos) /*!< Bit mask of SWOUARTNRZ field.                    */
76458   #define TPIU_DEVID_SWOUARTNRZ_Min (0x0UL)          /*!< Min enumerator value of SWOUARTNRZ field.                            */
76459   #define TPIU_DEVID_SWOUARTNRZ_Max (0x1UL)          /*!< Max enumerator value of SWOUARTNRZ field.                            */
76460   #define TPIU_DEVID_SWOUARTNRZ_NotSupported (0x0UL) /*!< Serial Wire Output, UART or NRZ, is not supported.                   */
76461   #define TPIU_DEVID_SWOUARTNRZ_Supported (0x1UL)    /*!< Serial Wire Output, UART or NRZ, is supported.                       */
76462 
76463 
76464 /* TPIU_DEVTYPE: The DEVTYPE register provides a debugger with information about the component when the Part Number field is not
76465                   recognized. The debugger can then report this information. */
76466 
76467   #define TPIU_DEVTYPE_ResetValue (0x00000000UL)     /*!< Reset value of DEVTYPE register.                                     */
76468 
76469 /* MAJOR @Bits 0..3 : The main type of the component */
76470   #define TPIU_DEVTYPE_MAJOR_Pos (0UL)               /*!< Position of MAJOR field.                                             */
76471   #define TPIU_DEVTYPE_MAJOR_Msk (0xFUL << TPIU_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field.                               */
76472   #define TPIU_DEVTYPE_MAJOR_Min (0x1UL)             /*!< Min enumerator value of MAJOR field.                                 */
76473   #define TPIU_DEVTYPE_MAJOR_Max (0x1UL)             /*!< Max enumerator value of MAJOR field.                                 */
76474   #define TPIU_DEVTYPE_MAJOR_TraceSource (0x1UL)     /*!< Peripheral is a trace sink.                                          */
76475 
76476 /* SUB @Bits 4..7 : The sub-type of the component */
76477   #define TPIU_DEVTYPE_SUB_Pos (4UL)                 /*!< Position of SUB field.                                               */
76478   #define TPIU_DEVTYPE_SUB_Msk (0xFUL << TPIU_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field.                                     */
76479   #define TPIU_DEVTYPE_SUB_Min (0x1UL)               /*!< Min enumerator value of SUB field.                                   */
76480   #define TPIU_DEVTYPE_SUB_Max (0x1UL)               /*!< Max enumerator value of SUB field.                                   */
76481   #define TPIU_DEVTYPE_SUB_TracePort (0x1UL)         /*!< Indicates that this component is a trace port component.             */
76482 
76483 
76484 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
76485 
76486 /* =========================================================================================================================== */
76487 /* ================                                           TSGEN                                           ================ */
76488 /* =========================================================================================================================== */
76489 
76490 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
76491 /* ====================================================== Struct TSGEN ======================================================= */
76492 /**
76493   * @brief Timestamp generator
76494   */
76495   typedef struct {                                   /*!< TSGEN Structure                                                      */
76496     __IOM uint32_t CNTCR;                            /*!< (@ 0x00000000) Counter Control Register                              */
76497     __IM uint32_t CNTSR;                             /*!< (@ 0x00000004) Counter Status Register                               */
76498     __IOM uint32_t CNTCVL;                           /*!< (@ 0x00000008) Current Counter Value Lower register                  */
76499     __IOM uint32_t CNTCVU;                           /*!< (@ 0x0000000C) Current Counter Value Upper register                  */
76500     __IM uint32_t RESERVED[4];
76501     __IOM uint32_t CNTFID0;                          /*!< (@ 0x00000020) Base Frequency ID                                     */
76502     __IM uint32_t RESERVED1[1003];
76503     __IM uint32_t PIDR4;                             /*!< (@ 0x00000FD0) Peripheral ID4 Register                               */
76504     __IM uint32_t RESERVED2[3];
76505     __IM uint32_t PIDR0;                             /*!< (@ 0x00000FE0) Peripheral ID0 Register                               */
76506     __IM uint32_t PIDR1;                             /*!< (@ 0x00000FE4) Peripheral ID1 Register                               */
76507     __IM uint32_t PIDR2;                             /*!< (@ 0x00000FE8) Peripheral ID2 Register                               */
76508     __IM uint32_t PIDR3;                             /*!< (@ 0x00000FEC) Peripheral ID3 Register                               */
76509     __IM uint32_t CIDR0;                             /*!< (@ 0x00000FF0) Component ID0 Register                                */
76510     __IM uint32_t CIDR1;                             /*!< (@ 0x00000FF4) Component ID1 Register                                */
76511     __IM uint32_t CIDR2;                             /*!< (@ 0x00000FF8) Component ID2 Register                                */
76512     __IM uint32_t CIDR3;                             /*!< (@ 0x00000FFC) Component ID3 Register                                */
76513   } NRF_TSGEN_Type;                                  /*!< Size = 4096 (0x1000)                                                 */
76514 
76515 /* TSGEN_CNTCR: Counter Control Register */
76516   #define TSGEN_CNTCR_ResetValue (0x00000000UL)      /*!< Reset value of CNTCR register.                                       */
76517 
76518 /* EN @Bit 0 : Counter enable */
76519   #define TSGEN_CNTCR_EN_Pos (0UL)                   /*!< Position of EN field.                                                */
76520   #define TSGEN_CNTCR_EN_Msk (0x1UL << TSGEN_CNTCR_EN_Pos) /*!< Bit mask of EN field.                                          */
76521   #define TSGEN_CNTCR_EN_Min (0x0UL)                 /*!< Min enumerator value of EN field.                                    */
76522   #define TSGEN_CNTCR_EN_Max (0x1UL)                 /*!< Max enumerator value of EN field.                                    */
76523   #define TSGEN_CNTCR_EN_Disabled (0x0UL)            /*!< (unspecified)                                                        */
76524   #define TSGEN_CNTCR_EN_Enabled (0x1UL)             /*!< (unspecified)                                                        */
76525 
76526 /* HDBG @Bit 1 : Halt on Debug */
76527   #define TSGEN_CNTCR_HDBG_Pos (1UL)                 /*!< Position of HDBG field.                                              */
76528   #define TSGEN_CNTCR_HDBG_Msk (0x1UL << TSGEN_CNTCR_HDBG_Pos) /*!< Bit mask of HDBG field.                                    */
76529   #define TSGEN_CNTCR_HDBG_Min (0x0UL)               /*!< Min enumerator value of HDBG field.                                  */
76530   #define TSGEN_CNTCR_HDBG_Max (0x1UL)               /*!< Max enumerator value of HDBG field.                                  */
76531   #define TSGEN_CNTCR_HDBG_Disabled (0x0UL)          /*!< Do not halt on debug, HLTDBG signal into the counter has no effect.  */
76532   #define TSGEN_CNTCR_HDBG_Enabled (0x1UL)           /*!< Halt on debug, when HLTDBG is driven HIGH, the count value is held
76533                                                           static.*/
76534 
76535 
76536 /* TSGEN_CNTSR: Counter Status Register */
76537   #define TSGEN_CNTSR_ResetValue (0x00000000UL)      /*!< Reset value of CNTSR register.                                       */
76538 
76539 /* DBGH @Bit 1 : Debug halted */
76540   #define TSGEN_CNTSR_DBGH_Pos (1UL)                 /*!< Position of DBGH field.                                              */
76541   #define TSGEN_CNTSR_DBGH_Msk (0x1UL << TSGEN_CNTSR_DBGH_Pos) /*!< Bit mask of DBGH field.                                    */
76542 
76543 
76544 /* TSGEN_CNTCVL: Current Counter Value Lower register */
76545   #define TSGEN_CNTCVL_ResetValue (0x00000000UL)     /*!< Reset value of CNTCVL register.                                      */
76546 
76547 /* CNTCVL_L_32 @Bits 0..31 : Current value of Counter, lower 32 bits */
76548   #define TSGEN_CNTCVL_CNTCVL_L_32_Pos (0UL)         /*!< Position of CNTCVL_L_32 field.                                       */
76549   #define TSGEN_CNTCVL_CNTCVL_L_32_Msk (0xFFFFFFFFUL << TSGEN_CNTCVL_CNTCVL_L_32_Pos) /*!< Bit mask of CNTCVL_L_32 field.      */
76550 
76551 
76552 /* TSGEN_CNTCVU: Current Counter Value Upper register */
76553   #define TSGEN_CNTCVU_ResetValue (0x00000000UL)     /*!< Reset value of CNTCVU register.                                      */
76554 
76555 /* CNTCVU_U_32 @Bits 0..31 : Current value of Counter, upper 32 bits */
76556   #define TSGEN_CNTCVU_CNTCVU_U_32_Pos (0UL)         /*!< Position of CNTCVU_U_32 field.                                       */
76557   #define TSGEN_CNTCVU_CNTCVU_U_32_Msk (0xFFFFFFFFUL << TSGEN_CNTCVU_CNTCVU_U_32_Pos) /*!< Bit mask of CNTCVU_U_32 field.      */
76558 
76559 
76560 /* TSGEN_CNTFID0: Base Frequency ID */
76561   #define TSGEN_CNTFID0_ResetValue (0x00000000UL)    /*!< Reset value of CNTFID0 register.                                     */
76562 
76563 /* FREQ @Bits 0..31 : Frequency in number of ticks per second (up to 4 GHz) */
76564   #define TSGEN_CNTFID0_FREQ_Pos (0UL)               /*!< Position of FREQ field.                                              */
76565   #define TSGEN_CNTFID0_FREQ_Msk (0xFFFFFFFFUL << TSGEN_CNTFID0_FREQ_Pos) /*!< Bit mask of FREQ field.                         */
76566 
76567 
76568 /* TSGEN_PIDR4: Peripheral ID4 Register */
76569   #define TSGEN_PIDR4_ResetValue (0x00000004UL)      /*!< Reset value of PIDR4 register.                                       */
76570 
76571 /* DES_2 @Bits 0..3 : JEDEC continuation code indicating the designer of the component, together with the identity code. */
76572   #define TSGEN_PIDR4_DES_2_Pos (0UL)                /*!< Position of DES_2 field.                                             */
76573   #define TSGEN_PIDR4_DES_2_Msk (0xFUL << TSGEN_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field.                                 */
76574 
76575 /* SIZE @Bits 4..7 : This is a 4-bit value that indicates the total contiguous size of the memory window used by this component
76576                      in powers of 2 from the standard 4KB. If a component only requires the standard 4KB, this must read as 0x0,
76577                      4KB only. For 8KB set to 0x1, for 16KB set to 0x2, for 32KB set to 0x3, and so on. */
76578 
76579   #define TSGEN_PIDR4_SIZE_Pos (4UL)                 /*!< Position of SIZE field.                                              */
76580   #define TSGEN_PIDR4_SIZE_Msk (0xFUL << TSGEN_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field.                                    */
76581 
76582 
76583 /* TSGEN_PIDR0: Peripheral ID0 Register */
76584   #define TSGEN_PIDR0_ResetValue (0x00000001UL)      /*!< Reset value of PIDR0 register.                                       */
76585 
76586 /* PART_0 @Bits 0..7 : Bits [7:0] of the component part number. This is selected by the designer of the component. */
76587   #define TSGEN_PIDR0_PART_0_Pos (0UL)               /*!< Position of PART_0 field.                                            */
76588   #define TSGEN_PIDR0_PART_0_Msk (0xFFUL << TSGEN_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field.                             */
76589 
76590 
76591 /* TSGEN_PIDR1: Peripheral ID1 Register */
76592   #define TSGEN_PIDR1_ResetValue (0x000000B1UL)      /*!< Reset value of PIDR1 register.                                       */
76593 
76594 /* PART_1 @Bits 0..3 : Bits [11:8] of the component part number. This is selected by the designer of the component. */
76595   #define TSGEN_PIDR1_PART_1_Pos (0UL)               /*!< Position of PART_1 field.                                            */
76596   #define TSGEN_PIDR1_PART_1_Msk (0xFUL << TSGEN_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field.                              */
76597 
76598 /* DES_0 @Bits 4..7 : Bits [3:0] of the JEDEC identity code indicating the designer of the component, together with the
76599                       continuation code. */
76600 
76601   #define TSGEN_PIDR1_DES_0_Pos (4UL)                /*!< Position of DES_0 field.                                             */
76602   #define TSGEN_PIDR1_DES_0_Msk (0xFUL << TSGEN_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field.                                 */
76603 
76604 
76605 /* TSGEN_PIDR2: Peripheral ID2 Register */
76606   #define TSGEN_PIDR2_ResetValue (0x0000001BUL)      /*!< Reset value of PIDR2 register.                                       */
76607 
76608 /* DES_1 @Bits 0..2 : Bits [6:4] of the JEDEC identity code indicating the designer of the component, together with the
76609                       continuation code. */
76610 
76611   #define TSGEN_PIDR2_DES_1_Pos (0UL)                /*!< Position of DES_1 field.                                             */
76612   #define TSGEN_PIDR2_DES_1_Msk (0x7UL << TSGEN_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field.                                 */
76613 
76614 /* JEDEC @Bit 3 : Always set. Indicates that a JEDEC assigned value is used. */
76615   #define TSGEN_PIDR2_JEDEC_Pos (3UL)                /*!< Position of JEDEC field.                                             */
76616   #define TSGEN_PIDR2_JEDEC_Msk (0x1UL << TSGEN_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field.                                 */
76617 
76618 /* REVISION @Bits 4..7 : The Revision field is an incremental value starting at 0x0 for the first design of this component. This
76619                          only increases by 1 for both major and minor revisions and is used as a look-up to establish the exact
76620                          major and minor revision. */
76621 
76622   #define TSGEN_PIDR2_REVISION_Pos (4UL)             /*!< Position of REVISION field.                                          */
76623   #define TSGEN_PIDR2_REVISION_Msk (0xFUL << TSGEN_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field.                        */
76624 
76625 
76626 /* TSGEN_PIDR3: Peripheral ID3 Register */
76627   #define TSGEN_PIDR3_ResetValue (0x00000000UL)      /*!< Reset value of PIDR3 register.                                       */
76628 
76629 /* CMOD @Bits 0..3 : Where the component is reusable IP, this value indicates if the customer has modified the behavior of the
76630                      component. In most cases this field is zero. */
76631 
76632   #define TSGEN_PIDR3_CMOD_Pos (0UL)                 /*!< Position of CMOD field.                                              */
76633   #define TSGEN_PIDR3_CMOD_Msk (0xFUL << TSGEN_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field.                                    */
76634 
76635 /* REVAND @Bits 4..7 : This field indicates minor errata fixes specific to this design, for example metal fixes after
76636                        implementation. In most cases this field is zero. It is recommended that component designers ensure this
76637                        field can be changed by a metal fix if required, for example by driving it from registers that reset to
76638                        zero. */
76639 
76640   #define TSGEN_PIDR3_REVAND_Pos (4UL)               /*!< Position of REVAND field.                                            */
76641   #define TSGEN_PIDR3_REVAND_Msk (0xFUL << TSGEN_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field.                              */
76642 
76643 
76644 /* TSGEN_CIDR0: Component ID0 Register */
76645   #define TSGEN_CIDR0_ResetValue (0x0000000DUL)      /*!< Reset value of CIDR0 register.                                       */
76646 
76647 /* PRMBL_0 @Bits 0..7 : Contains bits[7:0] of the component identification code. */
76648   #define TSGEN_CIDR0_PRMBL_0_Pos (0UL)              /*!< Position of PRMBL_0 field.                                           */
76649   #define TSGEN_CIDR0_PRMBL_0_Msk (0xFFUL << TSGEN_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field.                          */
76650 
76651 
76652 /* TSGEN_CIDR1: Component ID1 Register */
76653   #define TSGEN_CIDR1_ResetValue (0x000000F0UL)      /*!< Reset value of CIDR1 register.                                       */
76654 
76655 /* PRMBL_1 @Bits 0..3 : Contains bits[11:8] of the component identification code. */
76656   #define TSGEN_CIDR1_PRMBL_1_Pos (0UL)              /*!< Position of PRMBL_1 field.                                           */
76657   #define TSGEN_CIDR1_PRMBL_1_Msk (0xFUL << TSGEN_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field.                           */
76658 
76659 /* CLASS @Bits 4..7 : Class of the component, for example, ROM table or CoreSight component. */
76660   #define TSGEN_CIDR1_CLASS_Pos (4UL)                /*!< Position of CLASS field.                                             */
76661   #define TSGEN_CIDR1_CLASS_Msk (0xFUL << TSGEN_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field.                                 */
76662 
76663 
76664 /* TSGEN_CIDR2: Component ID2 Register */
76665   #define TSGEN_CIDR2_ResetValue (0x00000005UL)      /*!< Reset value of CIDR2 register.                                       */
76666 
76667 /* PRMBL_2 @Bits 0..7 : Contains bits[23:16] of the component identification code. */
76668   #define TSGEN_CIDR2_PRMBL_2_Pos (0UL)              /*!< Position of PRMBL_2 field.                                           */
76669   #define TSGEN_CIDR2_PRMBL_2_Msk (0xFFUL << TSGEN_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field.                          */
76670 
76671 
76672 /* TSGEN_CIDR3: Component ID3 Register */
76673   #define TSGEN_CIDR3_ResetValue (0x000000B1UL)      /*!< Reset value of CIDR3 register.                                       */
76674 
76675 /* PRMBL_3 @Bits 0..7 : Contains bits[31:24] of the component identification code. */
76676   #define TSGEN_CIDR3_PRMBL_3_Pos (0UL)              /*!< Position of PRMBL_3 field.                                           */
76677   #define TSGEN_CIDR3_PRMBL_3_Msk (0xFFUL << TSGEN_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field.                          */
76678 
76679 
76680 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
76681 
76682 /* =========================================================================================================================== */
76683 /* ================                                           TWIM                                           ================ */
76684 /* =========================================================================================================================== */
76685 
76686 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
76687 
76688 /* ==================================================== Struct TWIM_PSEL ===================================================== */
76689 /**
76690   * @brief PSEL [TWIM_PSEL] (unspecified)
76691   */
76692 typedef struct {
76693   __IOM uint32_t  SCL;                               /*!< (@ 0x00000000) Pin select for SCL signal                             */
76694   __IOM uint32_t  SDA;                               /*!< (@ 0x00000004) Pin select for SDA signal                             */
76695 } NRF_TWIM_PSEL_Type;                                /*!< Size = 8 (0x008)                                                     */
76696 
76697 /* TWIM_PSEL_SCL: Pin select for SCL signal */
76698   #define TWIM_PSEL_SCL_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SCL register.                                         */
76699 
76700 /* PIN @Bits 0..4 : Pin number */
76701   #define TWIM_PSEL_SCL_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
76702   #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field.                                  */
76703   #define TWIM_PSEL_SCL_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
76704   #define TWIM_PSEL_SCL_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
76705 
76706 /* PORT @Bits 5..8 : Port number */
76707   #define TWIM_PSEL_SCL_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
76708   #define TWIM_PSEL_SCL_PORT_Msk (0xFUL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field.                                */
76709   #define TWIM_PSEL_SCL_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
76710   #define TWIM_PSEL_SCL_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
76711 
76712 /* CONNECT @Bit 31 : Connection */
76713   #define TWIM_PSEL_SCL_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
76714   #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
76715   #define TWIM_PSEL_SCL_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
76716   #define TWIM_PSEL_SCL_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
76717   #define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
76718   #define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
76719 
76720 
76721 /* TWIM_PSEL_SDA: Pin select for SDA signal */
76722   #define TWIM_PSEL_SDA_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SDA register.                                         */
76723 
76724 /* PIN @Bits 0..4 : Pin number */
76725   #define TWIM_PSEL_SDA_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
76726   #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field.                                  */
76727   #define TWIM_PSEL_SDA_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
76728   #define TWIM_PSEL_SDA_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
76729 
76730 /* PORT @Bits 5..8 : Port number */
76731   #define TWIM_PSEL_SDA_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
76732   #define TWIM_PSEL_SDA_PORT_Msk (0xFUL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field.                                */
76733   #define TWIM_PSEL_SDA_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
76734   #define TWIM_PSEL_SDA_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
76735 
76736 /* CONNECT @Bit 31 : Connection */
76737   #define TWIM_PSEL_SDA_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
76738   #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
76739   #define TWIM_PSEL_SDA_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
76740   #define TWIM_PSEL_SDA_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
76741   #define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
76742   #define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
76743 
76744 
76745 
76746 /* ===================================================== Struct TWIM_RXD ===================================================== */
76747 /**
76748   * @brief RXD [TWIM_RXD] RXD EasyDMA channel
76749   */
76750 typedef struct {
76751   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
76752   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in receive buffer             */
76753   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last transaction   */
76754   __IOM uint32_t  LIST;                              /*!< (@ 0x0000000C) EasyDMA list type                                     */
76755 } NRF_TWIM_RXD_Type;                                 /*!< Size = 16 (0x010)                                                    */
76756 
76757 /* TWIM_RXD_PTR: Data pointer */
76758   #define TWIM_RXD_PTR_ResetValue (0x00000000UL)     /*!< Reset value of PTR register.                                         */
76759 
76760 /* PTR @Bits 0..31 : Data pointer */
76761   #define TWIM_RXD_PTR_PTR_Pos (0UL)                 /*!< Position of PTR field.                                               */
76762   #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                              */
76763 
76764 
76765 /* TWIM_RXD_MAXCNT: Maximum number of bytes in receive buffer */
76766   #define TWIM_RXD_MAXCNT_ResetValue (0x00000000UL)  /*!< Reset value of MAXCNT register.                                      */
76767 
76768 /* MAXCNT @Bits 0..14 : Maximum number of bytes in receive buffer */
76769   #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL)           /*!< Position of MAXCNT field.                                            */
76770   #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                   */
76771   #define TWIM_RXD_MAXCNT_MAXCNT_Min (0x1UL)         /*!< Min value of MAXCNT field.                                           */
76772   #define TWIM_RXD_MAXCNT_MAXCNT_Max (0x7FFFUL)      /*!< Max size of MAXCNT field.                                            */
76773 
76774 
76775 /* TWIM_RXD_AMOUNT: Number of bytes transferred in the last transaction */
76776   #define TWIM_RXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
76777 
76778 /* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
76779   #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL)           /*!< Position of AMOUNT field.                                            */
76780   #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
76781   #define TWIM_RXD_AMOUNT_AMOUNT_Min (0x1UL)         /*!< Min value of AMOUNT field.                                           */
76782   #define TWIM_RXD_AMOUNT_AMOUNT_Max (0x7FFFUL)      /*!< Max size of AMOUNT field.                                            */
76783 
76784 
76785 /* TWIM_RXD_LIST: EasyDMA list type */
76786   #define TWIM_RXD_LIST_ResetValue (0x00000000UL)    /*!< Reset value of LIST register.                                        */
76787 
76788 /* LIST @Bits 0..2 : List type */
76789   #define TWIM_RXD_LIST_LIST_Pos (0UL)               /*!< Position of LIST field.                                              */
76790   #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field.                                */
76791   #define TWIM_RXD_LIST_LIST_Min (0x0UL)             /*!< Min enumerator value of LIST field.                                  */
76792   #define TWIM_RXD_LIST_LIST_Max (0x1UL)             /*!< Max enumerator value of LIST field.                                  */
76793   #define TWIM_RXD_LIST_LIST_Disabled (0x0UL)        /*!< Disable EasyDMA list                                                 */
76794   #define TWIM_RXD_LIST_LIST_ArrayList (0x1UL)       /*!< Use array list                                                       */
76795 
76796 
76797 
76798 /* ===================================================== Struct TWIM_TXD ===================================================== */
76799 /**
76800   * @brief TXD [TWIM_TXD] TXD EasyDMA channel
76801   */
76802 typedef struct {
76803   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
76804   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer            */
76805   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last transaction   */
76806   __IOM uint32_t  LIST;                              /*!< (@ 0x0000000C) EasyDMA list type                                     */
76807 } NRF_TWIM_TXD_Type;                                 /*!< Size = 16 (0x010)                                                    */
76808 
76809 /* TWIM_TXD_PTR: Data pointer */
76810   #define TWIM_TXD_PTR_ResetValue (0x00000000UL)     /*!< Reset value of PTR register.                                         */
76811 
76812 /* PTR @Bits 0..31 : Data pointer */
76813   #define TWIM_TXD_PTR_PTR_Pos (0UL)                 /*!< Position of PTR field.                                               */
76814   #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                              */
76815 
76816 
76817 /* TWIM_TXD_MAXCNT: Maximum number of bytes in transmit buffer */
76818   #define TWIM_TXD_MAXCNT_ResetValue (0x00000000UL)  /*!< Reset value of MAXCNT register.                                      */
76819 
76820 /* MAXCNT @Bits 0..14 : Maximum number of bytes in transmit buffer */
76821   #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL)           /*!< Position of MAXCNT field.                                            */
76822   #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                   */
76823   #define TWIM_TXD_MAXCNT_MAXCNT_Min (0x1UL)         /*!< Min value of MAXCNT field.                                           */
76824   #define TWIM_TXD_MAXCNT_MAXCNT_Max (0x7FFFUL)      /*!< Max size of MAXCNT field.                                            */
76825 
76826 
76827 /* TWIM_TXD_AMOUNT: Number of bytes transferred in the last transaction */
76828   #define TWIM_TXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
76829 
76830 /* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
76831   #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL)           /*!< Position of AMOUNT field.                                            */
76832   #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
76833   #define TWIM_TXD_AMOUNT_AMOUNT_Min (0x1UL)         /*!< Min value of AMOUNT field.                                           */
76834   #define TWIM_TXD_AMOUNT_AMOUNT_Max (0x7FFFUL)      /*!< Max size of AMOUNT field.                                            */
76835 
76836 
76837 /* TWIM_TXD_LIST: EasyDMA list type */
76838   #define TWIM_TXD_LIST_ResetValue (0x00000000UL)    /*!< Reset value of LIST register.                                        */
76839 
76840 /* LIST @Bits 0..2 : List type */
76841   #define TWIM_TXD_LIST_LIST_Pos (0UL)               /*!< Position of LIST field.                                              */
76842   #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field.                                */
76843   #define TWIM_TXD_LIST_LIST_Min (0x0UL)             /*!< Min enumerator value of LIST field.                                  */
76844   #define TWIM_TXD_LIST_LIST_Max (0x1UL)             /*!< Max enumerator value of LIST field.                                  */
76845   #define TWIM_TXD_LIST_LIST_Disabled (0x0UL)        /*!< Disable EasyDMA list                                                 */
76846   #define TWIM_TXD_LIST_LIST_ArrayList (0x1UL)       /*!< Use array list                                                       */
76847 
76848 
76849 
76850 /* =================================================== Struct TWIM_DMA_RX ==================================================== */
76851 /**
76852   * @brief RX [TWIM_DMA_RX] (unspecified)
76853   */
76854 typedef struct {
76855   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
76856                                                                          detected.*/
76857   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
76858                                                                          event.*/
76859 } NRF_TWIM_DMA_RX_Type;                              /*!< Size = 8 (0x008)                                                     */
76860 
76861 /* TWIM_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
76862   #define TWIM_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */
76863 
76864 /* ENABLE @Bit 0 : (unspecified) */
76865   #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
76866   #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
76867                                                                             ENABLE field.*/
76868   #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
76869   #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
76870   #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
76871   #define TWIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */
76872 
76873 
76874 /* TWIM_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
76875   #define TWIM_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */
76876 
76877 /* ADDRESS @Bits 0..31 : (unspecified) */
76878   #define TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
76879   #define TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIM_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
76880                                                                             ADDRESS field.*/
76881 
76882 
76883 
76884 /* =================================================== Struct TWIM_DMA_TX ==================================================== */
76885 /**
76886   * @brief TX [TWIM_DMA_TX] (unspecified)
76887   */
76888 typedef struct {
76889   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
76890                                                                          detected.*/
76891   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
76892                                                                          event.*/
76893 } NRF_TWIM_DMA_TX_Type;                              /*!< Size = 8 (0x008)                                                     */
76894 
76895 /* TWIM_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
76896   #define TWIM_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */
76897 
76898 /* ENABLE @Bit 0 : (unspecified) */
76899   #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
76900   #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
76901                                                                             ENABLE field.*/
76902   #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
76903   #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
76904   #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
76905   #define TWIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */
76906 
76907 
76908 /* TWIM_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
76909   #define TWIM_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */
76910 
76911 /* ADDRESS @Bits 0..31 : (unspecified) */
76912   #define TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
76913   #define TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIM_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
76914                                                                             ADDRESS field.*/
76915 
76916 
76917 
76918 /* ===================================================== Struct TWIM_DMA ===================================================== */
76919 /**
76920   * @brief DMA [TWIM_DMA] (unspecified)
76921   */
76922 typedef struct {
76923   __IOM NRF_TWIM_DMA_RX_Type RX;                     /*!< (@ 0x00000000) (unspecified)                                         */
76924   __IOM NRF_TWIM_DMA_TX_Type TX;                     /*!< (@ 0x00000008) (unspecified)                                         */
76925 } NRF_TWIM_DMA_Type;                                 /*!< Size = 16 (0x010)                                                    */
76926 
76927 /* ======================================================= Struct TWIM ======================================================= */
76928 /**
76929   * @brief I2C compatible Two-Wire Master Interface with EasyDMA
76930   */
76931   typedef struct {                                   /*!< TWIM Structure                                                       */
76932     __OM uint32_t TASKS_STARTRX;                     /*!< (@ 0x00000000) Start TWI receive sequence                            */
76933     __IM uint32_t RESERVED;
76934     __OM uint32_t TASKS_STARTTX;                     /*!< (@ 0x00000008) Start TWI transmit sequence                           */
76935     __IM uint32_t RESERVED1[2];
76936     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the TWI
76937                                                                          master is not suspended.*/
76938     __IM uint32_t RESERVED2;
76939     __OM uint32_t TASKS_SUSPEND;                     /*!< (@ 0x0000001C) Suspend TWI transaction                               */
76940     __OM uint32_t TASKS_RESUME;                      /*!< (@ 0x00000020) Resume TWI transaction                                */
76941     __IM uint32_t RESERVED3[23];
76942     __IOM uint32_t SUBSCRIBE_STARTRX;                /*!< (@ 0x00000080) Subscribe configuration for task STARTRX              */
76943     __IM uint32_t RESERVED4;
76944     __IOM uint32_t SUBSCRIBE_STARTTX;                /*!< (@ 0x00000088) Subscribe configuration for task STARTTX              */
76945     __IM uint32_t RESERVED5[2];
76946     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000094) Subscribe configuration for task STOP                 */
76947     __IM uint32_t RESERVED6;
76948     __IOM uint32_t SUBSCRIBE_SUSPEND;                /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND              */
76949     __IOM uint32_t SUBSCRIBE_RESUME;                 /*!< (@ 0x000000A0) Subscribe configuration for task RESUME               */
76950     __IM uint32_t RESERVED7[24];
76951     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) TWI stopped                                           */
76952     __IM uint32_t RESERVED8[7];
76953     __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000124) TWI error                                             */
76954     __IM uint32_t RESERVED9[8];
76955     __IOM uint32_t EVENTS_SUSPENDED;                 /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is now
76956                                                                          suspended.*/
76957     __IOM uint32_t EVENTS_RXSTARTED;                 /*!< (@ 0x0000014C) Receive sequence started                              */
76958     __IOM uint32_t EVENTS_TXSTARTED;                 /*!< (@ 0x00000150) Transmit sequence started                             */
76959     __IM uint32_t RESERVED10[2];
76960     __IOM uint32_t EVENTS_LASTRX;                    /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte      */
76961     __IOM uint32_t EVENTS_LASTTX;                    /*!< (@ 0x00000160) Byte boundary, starting to transmit the last byte     */
76962     __IM uint32_t RESERVED11[4];
76963     __IOM uint32_t EVENTS_RXBUSERROR;                /*!< (@ 0x00000174) This event is generated if an error occurs during the
76964                                                                          bus transfer.*/
76965     __IOM uint32_t EVENTS_TXBUSERROR;                /*!< (@ 0x00000178) This event is generated if an error occurs during the
76966                                                                          bus transfer.*/
76967     __IM uint32_t RESERVED12[2];
76968     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
76969     __IM uint32_t RESERVED13[7];
76970     __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x000001A4) Publish configuration for event ERROR                 */
76971     __IM uint32_t RESERVED14[8];
76972     __IOM uint32_t PUBLISH_SUSPENDED;                /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED             */
76973     __IOM uint32_t PUBLISH_RXSTARTED;                /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED             */
76974     __IOM uint32_t PUBLISH_TXSTARTED;                /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED             */
76975     __IM uint32_t RESERVED15[2];
76976     __IOM uint32_t PUBLISH_LASTRX;                   /*!< (@ 0x000001DC) Publish configuration for event LASTRX                */
76977     __IOM uint32_t PUBLISH_LASTTX;                   /*!< (@ 0x000001E0) Publish configuration for event LASTTX                */
76978     __IM uint32_t RESERVED16[4];
76979     __IOM uint32_t PUBLISH_RXBUSERROR;               /*!< (@ 0x000001F4) Publish configuration for event RXBUSERROR            */
76980     __IOM uint32_t PUBLISH_TXBUSERROR;               /*!< (@ 0x000001F8) Publish configuration for event TXBUSERROR            */
76981     __IM uint32_t RESERVED17;
76982     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
76983     __IM uint32_t RESERVED18[63];
76984     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
76985     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
76986     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
76987     __IM uint32_t RESERVED19[110];
76988     __IOM uint32_t ERRORSRC;                         /*!< (@ 0x000004C4) Error source                                          */
76989     __IM uint32_t RESERVED20[14];
76990     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable TWIM                                           */
76991     __IM uint32_t RESERVED21;
76992     __IOM NRF_TWIM_PSEL_Type PSEL;                   /*!< (@ 0x00000508) (unspecified)                                         */
76993     __IM uint32_t RESERVED22[5];
76994     __IOM uint32_t FREQUENCY;                        /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK source
76995                                                                          selected.*/
76996     __IM uint32_t RESERVED23[3];
76997     __IOM NRF_TWIM_RXD_Type RXD;                     /*!< (@ 0x00000534) RXD EasyDMA channel                                   */
76998     __IOM NRF_TWIM_TXD_Type TXD;                     /*!< (@ 0x00000544) TXD EasyDMA channel                                   */
76999     __IM uint32_t RESERVED24[13];
77000     __IOM uint32_t ADDRESS;                          /*!< (@ 0x00000588) Address used in the TWI transfer                      */
77001     __IM uint32_t RESERVED25[9];
77002     __IOM NRF_TWIM_DMA_Type DMA;                     /*!< (@ 0x000005B0) (unspecified)                                         */
77003   } NRF_TWIM_Type;                                   /*!< Size = 1472 (0x5C0)                                                  */
77004 
77005 /* TWIM_TASKS_STARTRX: Start TWI receive sequence */
77006   #define TWIM_TASKS_STARTRX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STARTRX register.                             */
77007 
77008 /* TASKS_STARTRX @Bit 0 : Start TWI receive sequence */
77009   #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field.                                     */
77010   #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX
77011                                                                             field.*/
77012   #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Min (0x1UL) /*!< Min enumerator value of TASKS_STARTRX field.                       */
77013   #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Max (0x1UL) /*!< Max enumerator value of TASKS_STARTRX field.                       */
77014   #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task                                                   */
77015 
77016 
77017 /* TWIM_TASKS_STARTTX: Start TWI transmit sequence */
77018   #define TWIM_TASKS_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STARTTX register.                             */
77019 
77020 /* TASKS_STARTTX @Bit 0 : Start TWI transmit sequence */
77021   #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field.                                     */
77022   #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX
77023                                                                             field.*/
77024   #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STARTTX field.                       */
77025   #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STARTTX field.                       */
77026   #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task                                                   */
77027 
77028 
77029 /* TWIM_TASKS_STOP: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
77030   #define TWIM_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */
77031 
77032 /* TASKS_STOP @Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
77033   #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
77034   #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
77035   #define TWIM_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
77036   #define TWIM_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
77037   #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */
77038 
77039 
77040 /* TWIM_TASKS_SUSPEND: Suspend TWI transaction */
77041   #define TWIM_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register.                             */
77042 
77043 /* TASKS_SUSPEND @Bit 0 : Suspend TWI transaction */
77044   #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field.                                     */
77045   #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND
77046                                                                             field.*/
77047   #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field.                       */
77048   #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field.                       */
77049   #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task                                                   */
77050 
77051 
77052 /* TWIM_TASKS_RESUME: Resume TWI transaction */
77053   #define TWIM_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register.                               */
77054 
77055 /* TASKS_RESUME @Bit 0 : Resume TWI transaction */
77056   #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL)   /*!< Position of TASKS_RESUME field.                                      */
77057   #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/
77058   #define TWIM_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field.                          */
77059   #define TWIM_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field.                          */
77060   #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task                                                     */
77061 
77062 
77063 /* TWIM_SUBSCRIBE_STARTRX: Subscribe configuration for task STARTRX */
77064   #define TWIM_SUBSCRIBE_STARTRX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STARTRX register.                     */
77065 
77066 /* CHIDX @Bits 0..7 : DPPI channel that task STARTRX will subscribe to */
77067   #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
77068   #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
77069   #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
77070   #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
77071 
77072 /* EN @Bit 31 : (unspecified) */
77073   #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL)       /*!< Position of EN field.                                                */
77074   #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field.                    */
77075   #define TWIM_SUBSCRIBE_STARTRX_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
77076   #define TWIM_SUBSCRIBE_STARTRX_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
77077   #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
77078   #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
77079 
77080 
77081 /* TWIM_SUBSCRIBE_STARTTX: Subscribe configuration for task STARTTX */
77082   #define TWIM_SUBSCRIBE_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STARTTX register.                     */
77083 
77084 /* CHIDX @Bits 0..7 : DPPI channel that task STARTTX will subscribe to */
77085   #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
77086   #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
77087   #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
77088   #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
77089 
77090 /* EN @Bit 31 : (unspecified) */
77091   #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL)       /*!< Position of EN field.                                                */
77092   #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field.                    */
77093   #define TWIM_SUBSCRIBE_STARTTX_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
77094   #define TWIM_SUBSCRIBE_STARTTX_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
77095   #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
77096   #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
77097 
77098 
77099 /* TWIM_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
77100   #define TWIM_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */
77101 
77102 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
77103   #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
77104   #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
77105   #define TWIM_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
77106   #define TWIM_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
77107 
77108 /* EN @Bit 31 : (unspecified) */
77109   #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
77110   #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
77111   #define TWIM_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
77112   #define TWIM_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
77113   #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
77114   #define TWIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
77115 
77116 
77117 /* TWIM_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */
77118   #define TWIM_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register.                     */
77119 
77120 /* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */
77121   #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
77122   #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
77123   #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
77124   #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
77125 
77126 /* EN @Bit 31 : (unspecified) */
77127   #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL)       /*!< Position of EN field.                                                */
77128   #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field.                    */
77129   #define TWIM_SUBSCRIBE_SUSPEND_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
77130   #define TWIM_SUBSCRIBE_SUSPEND_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
77131   #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
77132   #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
77133 
77134 
77135 /* TWIM_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */
77136   #define TWIM_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register.                       */
77137 
77138 /* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */
77139   #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
77140   #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
77141   #define TWIM_SUBSCRIBE_RESUME_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
77142   #define TWIM_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
77143 
77144 /* EN @Bit 31 : (unspecified) */
77145   #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL)        /*!< Position of EN field.                                                */
77146   #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field.                      */
77147   #define TWIM_SUBSCRIBE_RESUME_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
77148   #define TWIM_SUBSCRIBE_RESUME_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
77149   #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
77150   #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
77151 
77152 
77153 /* TWIM_EVENTS_STOPPED: TWI stopped */
77154   #define TWIM_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                           */
77155 
77156 /* EVENTS_STOPPED @Bit 0 : TWI stopped */
77157   #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                  */
77158   #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
77159                                                                             EVENTS_STOPPED field.*/
77160   #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                    */
77161   #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                    */
77162   #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                     */
77163   #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                            */
77164 
77165 
77166 /* TWIM_EVENTS_ERROR: TWI error */
77167   #define TWIM_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                               */
77168 
77169 /* EVENTS_ERROR @Bit 0 : TWI error */
77170   #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)   /*!< Position of EVENTS_ERROR field.                                      */
77171   #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/
77172   #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field.                          */
77173   #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field.                          */
77174   #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                         */
77175   #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                */
77176 
77177 
77178 /* TWIM_EVENTS_SUSPENDED: SUSPEND task has been issued, TWI traffic is now suspended. */
77179   #define TWIM_EVENTS_SUSPENDED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_SUSPENDED register.                       */
77180 
77181 /* EVENTS_SUSPENDED @Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */
77182   #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field.                            */
77183   #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of
77184                                                                             EVENTS_SUSPENDED field.*/
77185   #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Min (0x0UL) /*!< Min enumerator value of EVENTS_SUSPENDED field.              */
77186   #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Max (0x1UL) /*!< Max enumerator value of EVENTS_SUSPENDED field.              */
77187   #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated                                 */
77188   #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated                                        */
77189 
77190 
77191 /* TWIM_EVENTS_RXSTARTED: Receive sequence started */
77192   #define TWIM_EVENTS_RXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXSTARTED register.                       */
77193 
77194 /* EVENTS_RXSTARTED @Bit 0 : Receive sequence started */
77195   #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field.                            */
77196   #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of
77197                                                                             EVENTS_RXSTARTED field.*/
77198   #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXSTARTED field.              */
77199   #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXSTARTED field.              */
77200   #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                 */
77201   #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated                                        */
77202 
77203 
77204 /* TWIM_EVENTS_TXSTARTED: Transmit sequence started */
77205   #define TWIM_EVENTS_TXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXSTARTED register.                       */
77206 
77207 /* EVENTS_TXSTARTED @Bit 0 : Transmit sequence started */
77208   #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field.                            */
77209   #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of
77210                                                                             EVENTS_TXSTARTED field.*/
77211   #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXSTARTED field.              */
77212   #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXSTARTED field.              */
77213   #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                 */
77214   #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated                                        */
77215 
77216 
77217 /* TWIM_EVENTS_LASTRX: Byte boundary, starting to receive the last byte */
77218   #define TWIM_EVENTS_LASTRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LASTRX register.                             */
77219 
77220 /* EVENTS_LASTRX @Bit 0 : Byte boundary, starting to receive the last byte */
77221   #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field.                                     */
77222   #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX
77223                                                                             field.*/
77224   #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_LASTRX field.                       */
77225   #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_LASTRX field.                       */
77226   #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated                                       */
77227   #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated                                              */
77228 
77229 
77230 /* TWIM_EVENTS_LASTTX: Byte boundary, starting to transmit the last byte */
77231   #define TWIM_EVENTS_LASTTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_LASTTX register.                             */
77232 
77233 /* EVENTS_LASTTX @Bit 0 : Byte boundary, starting to transmit the last byte */
77234   #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field.                                     */
77235   #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX
77236                                                                             field.*/
77237   #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_LASTTX field.                       */
77238   #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_LASTTX field.                       */
77239   #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated                                       */
77240   #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated                                              */
77241 
77242 
77243 /* TWIM_EVENTS_RXBUSERROR: This event is generated if an error occurs during the bus transfer. */
77244   #define TWIM_EVENTS_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXBUSERROR register.                     */
77245 
77246 /* EVENTS_RXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
77247   #define TWIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos (0UL) /*!< Position of EVENTS_RXBUSERROR field.                         */
77248   #define TWIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Msk (0x1UL << TWIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos) /*!< Bit mask of
77249                                                                             EVENTS_RXBUSERROR field.*/
77250   #define TWIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXBUSERROR field.           */
77251   #define TWIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXBUSERROR field.           */
77252   #define TWIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                               */
77253   #define TWIM_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Generated (0x1UL) /*!< Event generated                                      */
77254 
77255 
77256 /* TWIM_EVENTS_TXBUSERROR: This event is generated if an error occurs during the bus transfer. */
77257   #define TWIM_EVENTS_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXBUSERROR register.                     */
77258 
77259 /* EVENTS_TXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
77260   #define TWIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos (0UL) /*!< Position of EVENTS_TXBUSERROR field.                         */
77261   #define TWIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Msk (0x1UL << TWIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos) /*!< Bit mask of
77262                                                                             EVENTS_TXBUSERROR field.*/
77263   #define TWIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXBUSERROR field.           */
77264   #define TWIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXBUSERROR field.           */
77265   #define TWIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                               */
77266   #define TWIM_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Generated (0x1UL) /*!< Event generated                                      */
77267 
77268 
77269 /* TWIM_PUBLISH_STOPPED: Publish configuration for event STOPPED */
77270   #define TWIM_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                         */
77271 
77272 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
77273   #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
77274   #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
77275   #define TWIM_PUBLISH_STOPPED_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
77276   #define TWIM_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
77277 
77278 /* EN @Bit 31 : (unspecified) */
77279   #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
77280   #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                        */
77281   #define TWIM_PUBLISH_STOPPED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
77282   #define TWIM_PUBLISH_STOPPED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
77283   #define TWIM_PUBLISH_STOPPED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
77284   #define TWIM_PUBLISH_STOPPED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
77285 
77286 
77287 /* TWIM_PUBLISH_ERROR: Publish configuration for event ERROR */
77288   #define TWIM_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                             */
77289 
77290 /* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
77291   #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
77292   #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
77293   #define TWIM_PUBLISH_ERROR_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
77294   #define TWIM_PUBLISH_ERROR_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
77295 
77296 /* EN @Bit 31 : (unspecified) */
77297   #define TWIM_PUBLISH_ERROR_EN_Pos (31UL)           /*!< Position of EN field.                                                */
77298   #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                            */
77299   #define TWIM_PUBLISH_ERROR_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
77300   #define TWIM_PUBLISH_ERROR_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
77301   #define TWIM_PUBLISH_ERROR_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
77302   #define TWIM_PUBLISH_ERROR_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
77303 
77304 
77305 /* TWIM_PUBLISH_SUSPENDED: Publish configuration for event SUSPENDED */
77306   #define TWIM_PUBLISH_SUSPENDED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_SUSPENDED register.                     */
77307 
77308 /* CHIDX @Bits 0..7 : DPPI channel that event SUSPENDED will publish to */
77309   #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
77310   #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
77311   #define TWIM_PUBLISH_SUSPENDED_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
77312   #define TWIM_PUBLISH_SUSPENDED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
77313 
77314 /* EN @Bit 31 : (unspecified) */
77315   #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
77316   #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field.                    */
77317   #define TWIM_PUBLISH_SUSPENDED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
77318   #define TWIM_PUBLISH_SUSPENDED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
77319   #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
77320   #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
77321 
77322 
77323 /* TWIM_PUBLISH_RXSTARTED: Publish configuration for event RXSTARTED */
77324   #define TWIM_PUBLISH_RXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXSTARTED register.                     */
77325 
77326 /* CHIDX @Bits 0..7 : DPPI channel that event RXSTARTED will publish to */
77327   #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
77328   #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
77329   #define TWIM_PUBLISH_RXSTARTED_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
77330   #define TWIM_PUBLISH_RXSTARTED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
77331 
77332 /* EN @Bit 31 : (unspecified) */
77333   #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
77334   #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field.                    */
77335   #define TWIM_PUBLISH_RXSTARTED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
77336   #define TWIM_PUBLISH_RXSTARTED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
77337   #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
77338   #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
77339 
77340 
77341 /* TWIM_PUBLISH_TXSTARTED: Publish configuration for event TXSTARTED */
77342   #define TWIM_PUBLISH_TXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXSTARTED register.                     */
77343 
77344 /* CHIDX @Bits 0..7 : DPPI channel that event TXSTARTED will publish to */
77345   #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
77346   #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
77347   #define TWIM_PUBLISH_TXSTARTED_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
77348   #define TWIM_PUBLISH_TXSTARTED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
77349 
77350 /* EN @Bit 31 : (unspecified) */
77351   #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
77352   #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field.                    */
77353   #define TWIM_PUBLISH_TXSTARTED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
77354   #define TWIM_PUBLISH_TXSTARTED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
77355   #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
77356   #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
77357 
77358 
77359 /* TWIM_PUBLISH_LASTRX: Publish configuration for event LASTRX */
77360   #define TWIM_PUBLISH_LASTRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LASTRX register.                           */
77361 
77362 /* CHIDX @Bits 0..7 : DPPI channel that event LASTRX will publish to */
77363   #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
77364   #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
77365   #define TWIM_PUBLISH_LASTRX_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
77366   #define TWIM_PUBLISH_LASTRX_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
77367 
77368 /* EN @Bit 31 : (unspecified) */
77369   #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL)          /*!< Position of EN field.                                                */
77370   #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field.                          */
77371   #define TWIM_PUBLISH_LASTRX_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
77372   #define TWIM_PUBLISH_LASTRX_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
77373   #define TWIM_PUBLISH_LASTRX_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
77374   #define TWIM_PUBLISH_LASTRX_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
77375 
77376 
77377 /* TWIM_PUBLISH_LASTTX: Publish configuration for event LASTTX */
77378   #define TWIM_PUBLISH_LASTTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_LASTTX register.                           */
77379 
77380 /* CHIDX @Bits 0..7 : DPPI channel that event LASTTX will publish to */
77381   #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
77382   #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
77383   #define TWIM_PUBLISH_LASTTX_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
77384   #define TWIM_PUBLISH_LASTTX_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
77385 
77386 /* EN @Bit 31 : (unspecified) */
77387   #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL)          /*!< Position of EN field.                                                */
77388   #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field.                          */
77389   #define TWIM_PUBLISH_LASTTX_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
77390   #define TWIM_PUBLISH_LASTTX_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
77391   #define TWIM_PUBLISH_LASTTX_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
77392   #define TWIM_PUBLISH_LASTTX_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
77393 
77394 
77395 /* TWIM_PUBLISH_RXBUSERROR: Publish configuration for event RXBUSERROR */
77396   #define TWIM_PUBLISH_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXBUSERROR register.                   */
77397 
77398 /* CHIDX @Bits 0..7 : DPPI channel that event RXBUSERROR will publish to */
77399   #define TWIM_PUBLISH_RXBUSERROR_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
77400   #define TWIM_PUBLISH_RXBUSERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
77401   #define TWIM_PUBLISH_RXBUSERROR_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
77402   #define TWIM_PUBLISH_RXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
77403 
77404 /* EN @Bit 31 : (unspecified) */
77405   #define TWIM_PUBLISH_RXBUSERROR_EN_Pos (31UL)      /*!< Position of EN field.                                                */
77406   #define TWIM_PUBLISH_RXBUSERROR_EN_Msk (0x1UL << TWIM_PUBLISH_RXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                  */
77407   #define TWIM_PUBLISH_RXBUSERROR_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
77408   #define TWIM_PUBLISH_RXBUSERROR_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
77409   #define TWIM_PUBLISH_RXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
77410   #define TWIM_PUBLISH_RXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
77411 
77412 
77413 /* TWIM_PUBLISH_TXBUSERROR: Publish configuration for event TXBUSERROR */
77414   #define TWIM_PUBLISH_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXBUSERROR register.                   */
77415 
77416 /* CHIDX @Bits 0..7 : DPPI channel that event TXBUSERROR will publish to */
77417   #define TWIM_PUBLISH_TXBUSERROR_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
77418   #define TWIM_PUBLISH_TXBUSERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
77419   #define TWIM_PUBLISH_TXBUSERROR_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
77420   #define TWIM_PUBLISH_TXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
77421 
77422 /* EN @Bit 31 : (unspecified) */
77423   #define TWIM_PUBLISH_TXBUSERROR_EN_Pos (31UL)      /*!< Position of EN field.                                                */
77424   #define TWIM_PUBLISH_TXBUSERROR_EN_Msk (0x1UL << TWIM_PUBLISH_TXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                  */
77425   #define TWIM_PUBLISH_TXBUSERROR_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
77426   #define TWIM_PUBLISH_TXBUSERROR_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
77427   #define TWIM_PUBLISH_TXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
77428   #define TWIM_PUBLISH_TXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
77429 
77430 
77431 /* TWIM_SHORTS: Shortcuts between local events and tasks */
77432   #define TWIM_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */
77433 
77434 /* LASTTX_STARTRX @Bit 7 : Shortcut between event LASTTX and task STARTRX */
77435   #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL)       /*!< Position of LASTTX_STARTRX field.                                    */
77436   #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field.      */
77437   #define TWIM_SHORTS_LASTTX_STARTRX_Min (0x0UL)     /*!< Min enumerator value of LASTTX_STARTRX field.                        */
77438   #define TWIM_SHORTS_LASTTX_STARTRX_Max (0x1UL)     /*!< Max enumerator value of LASTTX_STARTRX field.                        */
77439   #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut                                                    */
77440   #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut                                                      */
77441 
77442 /* LASTTX_SUSPEND @Bit 8 : Shortcut between event LASTTX and task SUSPEND */
77443   #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL)       /*!< Position of LASTTX_SUSPEND field.                                    */
77444   #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field.      */
77445   #define TWIM_SHORTS_LASTTX_SUSPEND_Min (0x0UL)     /*!< Min enumerator value of LASTTX_SUSPEND field.                        */
77446   #define TWIM_SHORTS_LASTTX_SUSPEND_Max (0x1UL)     /*!< Max enumerator value of LASTTX_SUSPEND field.                        */
77447   #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut                                                    */
77448   #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut                                                      */
77449 
77450 /* LASTTX_STOP @Bit 9 : Shortcut between event LASTTX and task STOP */
77451   #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL)          /*!< Position of LASTTX_STOP field.                                       */
77452   #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field.               */
77453   #define TWIM_SHORTS_LASTTX_STOP_Min (0x0UL)        /*!< Min enumerator value of LASTTX_STOP field.                           */
77454   #define TWIM_SHORTS_LASTTX_STOP_Max (0x1UL)        /*!< Max enumerator value of LASTTX_STOP field.                           */
77455   #define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
77456   #define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */
77457 
77458 /* LASTRX_STARTTX @Bit 10 : Shortcut between event LASTRX and task STARTTX */
77459   #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL)      /*!< Position of LASTRX_STARTTX field.                                    */
77460   #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field.      */
77461   #define TWIM_SHORTS_LASTRX_STARTTX_Min (0x0UL)     /*!< Min enumerator value of LASTRX_STARTTX field.                        */
77462   #define TWIM_SHORTS_LASTRX_STARTTX_Max (0x1UL)     /*!< Max enumerator value of LASTRX_STARTTX field.                        */
77463   #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0x0UL) /*!< Disable shortcut                                                    */
77464   #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (0x1UL) /*!< Enable shortcut                                                      */
77465 
77466 /* LASTRX_STOP @Bit 12 : Shortcut between event LASTRX and task STOP */
77467   #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL)         /*!< Position of LASTRX_STOP field.                                       */
77468   #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field.               */
77469   #define TWIM_SHORTS_LASTRX_STOP_Min (0x0UL)        /*!< Min enumerator value of LASTRX_STOP field.                           */
77470   #define TWIM_SHORTS_LASTRX_STOP_Max (0x1UL)        /*!< Max enumerator value of LASTRX_STOP field.                           */
77471   #define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL)   /*!< Disable shortcut                                                     */
77472   #define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL)    /*!< Enable shortcut                                                      */
77473 
77474 
77475 /* TWIM_INTEN: Enable or disable interrupt */
77476   #define TWIM_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */
77477 
77478 /* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */
77479   #define TWIM_INTEN_STOPPED_Pos (1UL)               /*!< Position of STOPPED field.                                           */
77480   #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                             */
77481   #define TWIM_INTEN_STOPPED_Min (0x0UL)             /*!< Min enumerator value of STOPPED field.                               */
77482   #define TWIM_INTEN_STOPPED_Max (0x1UL)             /*!< Max enumerator value of STOPPED field.                               */
77483   #define TWIM_INTEN_STOPPED_Disabled (0x0UL)        /*!< Disable                                                              */
77484   #define TWIM_INTEN_STOPPED_Enabled (0x1UL)         /*!< Enable                                                               */
77485 
77486 /* ERROR @Bit 9 : Enable or disable interrupt for event ERROR */
77487   #define TWIM_INTEN_ERROR_Pos (9UL)                 /*!< Position of ERROR field.                                             */
77488   #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field.                                   */
77489   #define TWIM_INTEN_ERROR_Min (0x0UL)               /*!< Min enumerator value of ERROR field.                                 */
77490   #define TWIM_INTEN_ERROR_Max (0x1UL)               /*!< Max enumerator value of ERROR field.                                 */
77491   #define TWIM_INTEN_ERROR_Disabled (0x0UL)          /*!< Disable                                                              */
77492   #define TWIM_INTEN_ERROR_Enabled (0x1UL)           /*!< Enable                                                               */
77493 
77494 /* SUSPENDED @Bit 18 : Enable or disable interrupt for event SUSPENDED */
77495   #define TWIM_INTEN_SUSPENDED_Pos (18UL)            /*!< Position of SUSPENDED field.                                         */
77496   #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field.                       */
77497   #define TWIM_INTEN_SUSPENDED_Min (0x0UL)           /*!< Min enumerator value of SUSPENDED field.                             */
77498   #define TWIM_INTEN_SUSPENDED_Max (0x1UL)           /*!< Max enumerator value of SUSPENDED field.                             */
77499   #define TWIM_INTEN_SUSPENDED_Disabled (0x0UL)      /*!< Disable                                                              */
77500   #define TWIM_INTEN_SUSPENDED_Enabled (0x1UL)       /*!< Enable                                                               */
77501 
77502 /* RXSTARTED @Bit 19 : Enable or disable interrupt for event RXSTARTED */
77503   #define TWIM_INTEN_RXSTARTED_Pos (19UL)            /*!< Position of RXSTARTED field.                                         */
77504   #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.                       */
77505   #define TWIM_INTEN_RXSTARTED_Min (0x0UL)           /*!< Min enumerator value of RXSTARTED field.                             */
77506   #define TWIM_INTEN_RXSTARTED_Max (0x1UL)           /*!< Max enumerator value of RXSTARTED field.                             */
77507   #define TWIM_INTEN_RXSTARTED_Disabled (0x0UL)      /*!< Disable                                                              */
77508   #define TWIM_INTEN_RXSTARTED_Enabled (0x1UL)       /*!< Enable                                                               */
77509 
77510 /* TXSTARTED @Bit 20 : Enable or disable interrupt for event TXSTARTED */
77511   #define TWIM_INTEN_TXSTARTED_Pos (20UL)            /*!< Position of TXSTARTED field.                                         */
77512   #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.                       */
77513   #define TWIM_INTEN_TXSTARTED_Min (0x0UL)           /*!< Min enumerator value of TXSTARTED field.                             */
77514   #define TWIM_INTEN_TXSTARTED_Max (0x1UL)           /*!< Max enumerator value of TXSTARTED field.                             */
77515   #define TWIM_INTEN_TXSTARTED_Disabled (0x0UL)      /*!< Disable                                                              */
77516   #define TWIM_INTEN_TXSTARTED_Enabled (0x1UL)       /*!< Enable                                                               */
77517 
77518 /* LASTRX @Bit 23 : Enable or disable interrupt for event LASTRX */
77519   #define TWIM_INTEN_LASTRX_Pos (23UL)               /*!< Position of LASTRX field.                                            */
77520   #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field.                                */
77521   #define TWIM_INTEN_LASTRX_Min (0x0UL)              /*!< Min enumerator value of LASTRX field.                                */
77522   #define TWIM_INTEN_LASTRX_Max (0x1UL)              /*!< Max enumerator value of LASTRX field.                                */
77523   #define TWIM_INTEN_LASTRX_Disabled (0x0UL)         /*!< Disable                                                              */
77524   #define TWIM_INTEN_LASTRX_Enabled (0x1UL)          /*!< Enable                                                               */
77525 
77526 /* LASTTX @Bit 24 : Enable or disable interrupt for event LASTTX */
77527   #define TWIM_INTEN_LASTTX_Pos (24UL)               /*!< Position of LASTTX field.                                            */
77528   #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field.                                */
77529   #define TWIM_INTEN_LASTTX_Min (0x0UL)              /*!< Min enumerator value of LASTTX field.                                */
77530   #define TWIM_INTEN_LASTTX_Max (0x1UL)              /*!< Max enumerator value of LASTTX field.                                */
77531   #define TWIM_INTEN_LASTTX_Disabled (0x0UL)         /*!< Disable                                                              */
77532   #define TWIM_INTEN_LASTTX_Enabled (0x1UL)          /*!< Enable                                                               */
77533 
77534 /* RXBUSERROR @Bit 29 : Enable or disable interrupt for event RXBUSERROR */
77535   #define TWIM_INTEN_RXBUSERROR_Pos (29UL)           /*!< Position of RXBUSERROR field.                                        */
77536   #define TWIM_INTEN_RXBUSERROR_Msk (0x1UL << TWIM_INTEN_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.                    */
77537   #define TWIM_INTEN_RXBUSERROR_Min (0x0UL)          /*!< Min enumerator value of RXBUSERROR field.                            */
77538   #define TWIM_INTEN_RXBUSERROR_Max (0x1UL)          /*!< Max enumerator value of RXBUSERROR field.                            */
77539   #define TWIM_INTEN_RXBUSERROR_Disabled (0x0UL)     /*!< Disable                                                              */
77540   #define TWIM_INTEN_RXBUSERROR_Enabled (0x1UL)      /*!< Enable                                                               */
77541 
77542 /* TXBUSERROR @Bit 30 : Enable or disable interrupt for event TXBUSERROR */
77543   #define TWIM_INTEN_TXBUSERROR_Pos (30UL)           /*!< Position of TXBUSERROR field.                                        */
77544   #define TWIM_INTEN_TXBUSERROR_Msk (0x1UL << TWIM_INTEN_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.                    */
77545   #define TWIM_INTEN_TXBUSERROR_Min (0x0UL)          /*!< Min enumerator value of TXBUSERROR field.                            */
77546   #define TWIM_INTEN_TXBUSERROR_Max (0x1UL)          /*!< Max enumerator value of TXBUSERROR field.                            */
77547   #define TWIM_INTEN_TXBUSERROR_Disabled (0x0UL)     /*!< Disable                                                              */
77548   #define TWIM_INTEN_TXBUSERROR_Enabled (0x1UL)      /*!< Enable                                                               */
77549 
77550 
77551 /* TWIM_INTENSET: Enable interrupt */
77552   #define TWIM_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */
77553 
77554 /* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
77555   #define TWIM_INTENSET_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
77556   #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
77557   #define TWIM_INTENSET_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
77558   #define TWIM_INTENSET_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
77559   #define TWIM_INTENSET_STOPPED_Set (0x1UL)          /*!< Enable                                                               */
77560   #define TWIM_INTENSET_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
77561   #define TWIM_INTENSET_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
77562 
77563 /* ERROR @Bit 9 : Write '1' to enable interrupt for event ERROR */
77564   #define TWIM_INTENSET_ERROR_Pos (9UL)              /*!< Position of ERROR field.                                             */
77565   #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
77566   #define TWIM_INTENSET_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
77567   #define TWIM_INTENSET_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
77568   #define TWIM_INTENSET_ERROR_Set (0x1UL)            /*!< Enable                                                               */
77569   #define TWIM_INTENSET_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
77570   #define TWIM_INTENSET_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
77571 
77572 /* SUSPENDED @Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
77573   #define TWIM_INTENSET_SUSPENDED_Pos (18UL)         /*!< Position of SUSPENDED field.                                         */
77574   #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field.                 */
77575   #define TWIM_INTENSET_SUSPENDED_Min (0x0UL)        /*!< Min enumerator value of SUSPENDED field.                             */
77576   #define TWIM_INTENSET_SUSPENDED_Max (0x1UL)        /*!< Max enumerator value of SUSPENDED field.                             */
77577   #define TWIM_INTENSET_SUSPENDED_Set (0x1UL)        /*!< Enable                                                               */
77578   #define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
77579   #define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
77580 
77581 /* RXSTARTED @Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
77582   #define TWIM_INTENSET_RXSTARTED_Pos (19UL)         /*!< Position of RXSTARTED field.                                         */
77583   #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.                 */
77584   #define TWIM_INTENSET_RXSTARTED_Min (0x0UL)        /*!< Min enumerator value of RXSTARTED field.                             */
77585   #define TWIM_INTENSET_RXSTARTED_Max (0x1UL)        /*!< Max enumerator value of RXSTARTED field.                             */
77586   #define TWIM_INTENSET_RXSTARTED_Set (0x1UL)        /*!< Enable                                                               */
77587   #define TWIM_INTENSET_RXSTARTED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
77588   #define TWIM_INTENSET_RXSTARTED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
77589 
77590 /* TXSTARTED @Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
77591   #define TWIM_INTENSET_TXSTARTED_Pos (20UL)         /*!< Position of TXSTARTED field.                                         */
77592   #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.                 */
77593   #define TWIM_INTENSET_TXSTARTED_Min (0x0UL)        /*!< Min enumerator value of TXSTARTED field.                             */
77594   #define TWIM_INTENSET_TXSTARTED_Max (0x1UL)        /*!< Max enumerator value of TXSTARTED field.                             */
77595   #define TWIM_INTENSET_TXSTARTED_Set (0x1UL)        /*!< Enable                                                               */
77596   #define TWIM_INTENSET_TXSTARTED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
77597   #define TWIM_INTENSET_TXSTARTED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
77598 
77599 /* LASTRX @Bit 23 : Write '1' to enable interrupt for event LASTRX */
77600   #define TWIM_INTENSET_LASTRX_Pos (23UL)            /*!< Position of LASTRX field.                                            */
77601   #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field.                          */
77602   #define TWIM_INTENSET_LASTRX_Min (0x0UL)           /*!< Min enumerator value of LASTRX field.                                */
77603   #define TWIM_INTENSET_LASTRX_Max (0x1UL)           /*!< Max enumerator value of LASTRX field.                                */
77604   #define TWIM_INTENSET_LASTRX_Set (0x1UL)           /*!< Enable                                                               */
77605   #define TWIM_INTENSET_LASTRX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
77606   #define TWIM_INTENSET_LASTRX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
77607 
77608 /* LASTTX @Bit 24 : Write '1' to enable interrupt for event LASTTX */
77609   #define TWIM_INTENSET_LASTTX_Pos (24UL)            /*!< Position of LASTTX field.                                            */
77610   #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field.                          */
77611   #define TWIM_INTENSET_LASTTX_Min (0x0UL)           /*!< Min enumerator value of LASTTX field.                                */
77612   #define TWIM_INTENSET_LASTTX_Max (0x1UL)           /*!< Max enumerator value of LASTTX field.                                */
77613   #define TWIM_INTENSET_LASTTX_Set (0x1UL)           /*!< Enable                                                               */
77614   #define TWIM_INTENSET_LASTTX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
77615   #define TWIM_INTENSET_LASTTX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
77616 
77617 /* RXBUSERROR @Bit 29 : Write '1' to enable interrupt for event RXBUSERROR */
77618   #define TWIM_INTENSET_RXBUSERROR_Pos (29UL)        /*!< Position of RXBUSERROR field.                                        */
77619   #define TWIM_INTENSET_RXBUSERROR_Msk (0x1UL << TWIM_INTENSET_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.              */
77620   #define TWIM_INTENSET_RXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of RXBUSERROR field.                            */
77621   #define TWIM_INTENSET_RXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of RXBUSERROR field.                            */
77622   #define TWIM_INTENSET_RXBUSERROR_Set (0x1UL)       /*!< Enable                                                               */
77623   #define TWIM_INTENSET_RXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
77624   #define TWIM_INTENSET_RXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
77625 
77626 /* TXBUSERROR @Bit 30 : Write '1' to enable interrupt for event TXBUSERROR */
77627   #define TWIM_INTENSET_TXBUSERROR_Pos (30UL)        /*!< Position of TXBUSERROR field.                                        */
77628   #define TWIM_INTENSET_TXBUSERROR_Msk (0x1UL << TWIM_INTENSET_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.              */
77629   #define TWIM_INTENSET_TXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of TXBUSERROR field.                            */
77630   #define TWIM_INTENSET_TXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of TXBUSERROR field.                            */
77631   #define TWIM_INTENSET_TXBUSERROR_Set (0x1UL)       /*!< Enable                                                               */
77632   #define TWIM_INTENSET_TXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
77633   #define TWIM_INTENSET_TXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
77634 
77635 
77636 /* TWIM_INTENCLR: Disable interrupt */
77637   #define TWIM_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */
77638 
77639 /* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
77640   #define TWIM_INTENCLR_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
77641   #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
77642   #define TWIM_INTENCLR_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
77643   #define TWIM_INTENCLR_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
77644   #define TWIM_INTENCLR_STOPPED_Clear (0x1UL)        /*!< Disable                                                              */
77645   #define TWIM_INTENCLR_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
77646   #define TWIM_INTENCLR_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
77647 
77648 /* ERROR @Bit 9 : Write '1' to disable interrupt for event ERROR */
77649   #define TWIM_INTENCLR_ERROR_Pos (9UL)              /*!< Position of ERROR field.                                             */
77650   #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
77651   #define TWIM_INTENCLR_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
77652   #define TWIM_INTENCLR_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
77653   #define TWIM_INTENCLR_ERROR_Clear (0x1UL)          /*!< Disable                                                              */
77654   #define TWIM_INTENCLR_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
77655   #define TWIM_INTENCLR_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
77656 
77657 /* SUSPENDED @Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
77658   #define TWIM_INTENCLR_SUSPENDED_Pos (18UL)         /*!< Position of SUSPENDED field.                                         */
77659   #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field.                 */
77660   #define TWIM_INTENCLR_SUSPENDED_Min (0x0UL)        /*!< Min enumerator value of SUSPENDED field.                             */
77661   #define TWIM_INTENCLR_SUSPENDED_Max (0x1UL)        /*!< Max enumerator value of SUSPENDED field.                             */
77662   #define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL)      /*!< Disable                                                              */
77663   #define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
77664   #define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
77665 
77666 /* RXSTARTED @Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
77667   #define TWIM_INTENCLR_RXSTARTED_Pos (19UL)         /*!< Position of RXSTARTED field.                                         */
77668   #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.                 */
77669   #define TWIM_INTENCLR_RXSTARTED_Min (0x0UL)        /*!< Min enumerator value of RXSTARTED field.                             */
77670   #define TWIM_INTENCLR_RXSTARTED_Max (0x1UL)        /*!< Max enumerator value of RXSTARTED field.                             */
77671   #define TWIM_INTENCLR_RXSTARTED_Clear (0x1UL)      /*!< Disable                                                              */
77672   #define TWIM_INTENCLR_RXSTARTED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
77673   #define TWIM_INTENCLR_RXSTARTED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
77674 
77675 /* TXSTARTED @Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
77676   #define TWIM_INTENCLR_TXSTARTED_Pos (20UL)         /*!< Position of TXSTARTED field.                                         */
77677   #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.                 */
77678   #define TWIM_INTENCLR_TXSTARTED_Min (0x0UL)        /*!< Min enumerator value of TXSTARTED field.                             */
77679   #define TWIM_INTENCLR_TXSTARTED_Max (0x1UL)        /*!< Max enumerator value of TXSTARTED field.                             */
77680   #define TWIM_INTENCLR_TXSTARTED_Clear (0x1UL)      /*!< Disable                                                              */
77681   #define TWIM_INTENCLR_TXSTARTED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
77682   #define TWIM_INTENCLR_TXSTARTED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
77683 
77684 /* LASTRX @Bit 23 : Write '1' to disable interrupt for event LASTRX */
77685   #define TWIM_INTENCLR_LASTRX_Pos (23UL)            /*!< Position of LASTRX field.                                            */
77686   #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field.                          */
77687   #define TWIM_INTENCLR_LASTRX_Min (0x0UL)           /*!< Min enumerator value of LASTRX field.                                */
77688   #define TWIM_INTENCLR_LASTRX_Max (0x1UL)           /*!< Max enumerator value of LASTRX field.                                */
77689   #define TWIM_INTENCLR_LASTRX_Clear (0x1UL)         /*!< Disable                                                              */
77690   #define TWIM_INTENCLR_LASTRX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
77691   #define TWIM_INTENCLR_LASTRX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
77692 
77693 /* LASTTX @Bit 24 : Write '1' to disable interrupt for event LASTTX */
77694   #define TWIM_INTENCLR_LASTTX_Pos (24UL)            /*!< Position of LASTTX field.                                            */
77695   #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field.                          */
77696   #define TWIM_INTENCLR_LASTTX_Min (0x0UL)           /*!< Min enumerator value of LASTTX field.                                */
77697   #define TWIM_INTENCLR_LASTTX_Max (0x1UL)           /*!< Max enumerator value of LASTTX field.                                */
77698   #define TWIM_INTENCLR_LASTTX_Clear (0x1UL)         /*!< Disable                                                              */
77699   #define TWIM_INTENCLR_LASTTX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
77700   #define TWIM_INTENCLR_LASTTX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
77701 
77702 /* RXBUSERROR @Bit 29 : Write '1' to disable interrupt for event RXBUSERROR */
77703   #define TWIM_INTENCLR_RXBUSERROR_Pos (29UL)        /*!< Position of RXBUSERROR field.                                        */
77704   #define TWIM_INTENCLR_RXBUSERROR_Msk (0x1UL << TWIM_INTENCLR_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.              */
77705   #define TWIM_INTENCLR_RXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of RXBUSERROR field.                            */
77706   #define TWIM_INTENCLR_RXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of RXBUSERROR field.                            */
77707   #define TWIM_INTENCLR_RXBUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
77708   #define TWIM_INTENCLR_RXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
77709   #define TWIM_INTENCLR_RXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
77710 
77711 /* TXBUSERROR @Bit 30 : Write '1' to disable interrupt for event TXBUSERROR */
77712   #define TWIM_INTENCLR_TXBUSERROR_Pos (30UL)        /*!< Position of TXBUSERROR field.                                        */
77713   #define TWIM_INTENCLR_TXBUSERROR_Msk (0x1UL << TWIM_INTENCLR_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.              */
77714   #define TWIM_INTENCLR_TXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of TXBUSERROR field.                            */
77715   #define TWIM_INTENCLR_TXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of TXBUSERROR field.                            */
77716   #define TWIM_INTENCLR_TXBUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
77717   #define TWIM_INTENCLR_TXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
77718   #define TWIM_INTENCLR_TXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
77719 
77720 
77721 /* TWIM_ERRORSRC: Error source */
77722   #define TWIM_ERRORSRC_ResetValue (0x00000000UL)    /*!< Reset value of ERRORSRC register.                                    */
77723 
77724 /* OVERRUN @Bit 0 : Overrun error */
77725   #define TWIM_ERRORSRC_OVERRUN_Pos (0UL)            /*!< Position of OVERRUN field.                                           */
77726   #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field.                       */
77727   #define TWIM_ERRORSRC_OVERRUN_Min (0x0UL)          /*!< Min enumerator value of OVERRUN field.                               */
77728   #define TWIM_ERRORSRC_OVERRUN_Max (0x1UL)          /*!< Max enumerator value of OVERRUN field.                               */
77729   #define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL)  /*!< Error did not occur                                                  */
77730   #define TWIM_ERRORSRC_OVERRUN_Received (0x1UL)     /*!< Error occurred                                                       */
77731 
77732 /* ANACK @Bit 1 : NACK received after sending the address (write '1' to clear) */
77733   #define TWIM_ERRORSRC_ANACK_Pos (1UL)              /*!< Position of ANACK field.                                             */
77734   #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field.                             */
77735   #define TWIM_ERRORSRC_ANACK_Min (0x0UL)            /*!< Min enumerator value of ANACK field.                                 */
77736   #define TWIM_ERRORSRC_ANACK_Max (0x1UL)            /*!< Max enumerator value of ANACK field.                                 */
77737   #define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL)    /*!< Error did not occur                                                  */
77738   #define TWIM_ERRORSRC_ANACK_Received (0x1UL)       /*!< Error occurred                                                       */
77739 
77740 /* DNACK @Bit 2 : NACK received after sending a data byte (write '1' to clear) */
77741   #define TWIM_ERRORSRC_DNACK_Pos (2UL)              /*!< Position of DNACK field.                                             */
77742   #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field.                             */
77743   #define TWIM_ERRORSRC_DNACK_Min (0x0UL)            /*!< Min enumerator value of DNACK field.                                 */
77744   #define TWIM_ERRORSRC_DNACK_Max (0x1UL)            /*!< Max enumerator value of DNACK field.                                 */
77745   #define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL)    /*!< Error did not occur                                                  */
77746   #define TWIM_ERRORSRC_DNACK_Received (0x1UL)       /*!< Error occurred                                                       */
77747 
77748 
77749 /* TWIM_ENABLE: Enable TWIM */
77750   #define TWIM_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */
77751 
77752 /* ENABLE @Bits 0..3 : Enable or disable TWIM */
77753   #define TWIM_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
77754   #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
77755   #define TWIM_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
77756   #define TWIM_ENABLE_ENABLE_Max (0x6UL)             /*!< Max enumerator value of ENABLE field.                                */
77757   #define TWIM_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable TWIM                                                         */
77758   #define TWIM_ENABLE_ENABLE_Enabled (0x6UL)         /*!< Enable TWIM                                                          */
77759 
77760 
77761 /* TWIM_FREQUENCY: TWI frequency. Accuracy depends on the HFCLK source selected. */
77762   #define TWIM_FREQUENCY_ResetValue (0x04000000UL)   /*!< Reset value of FREQUENCY register.                                   */
77763 
77764 /* FREQUENCY @Bits 0..31 : TWI master clock frequency */
77765   #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL)         /*!< Position of FREQUENCY field.                                         */
77766   #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field.        */
77767   #define TWIM_FREQUENCY_FREQUENCY_Min (0x1980000UL) /*!< Min enumerator value of FREQUENCY field.                             */
77768   #define TWIM_FREQUENCY_FREQUENCY_Max (0xFF00000UL) /*!< Max enumerator value of FREQUENCY field.                             */
77769   #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps                                                           */
77770   #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps                                                           */
77771   #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps                                                           */
77772   #define TWIM_FREQUENCY_FREQUENCY_K1000 (0x0FF00000UL) /*!< 1000 kbps                                                         */
77773 
77774 
77775 /* TWIM_ADDRESS: Address used in the TWI transfer */
77776   #define TWIM_ADDRESS_ResetValue (0x00000000UL)     /*!< Reset value of ADDRESS register.                                     */
77777 
77778 /* ADDRESS @Bits 0..6 : Address used in the TWI transfer */
77779   #define TWIM_ADDRESS_ADDRESS_Pos (0UL)             /*!< Position of ADDRESS field.                                           */
77780   #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                        */
77781 
77782 
77783 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
77784 
77785 /* =========================================================================================================================== */
77786 /* ================                                           TWIS                                           ================ */
77787 /* =========================================================================================================================== */
77788 
77789 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
77790 
77791 /* ==================================================== Struct TWIS_PSEL ===================================================== */
77792 /**
77793   * @brief PSEL [TWIS_PSEL] (unspecified)
77794   */
77795 typedef struct {
77796   __IOM uint32_t  SCL;                               /*!< (@ 0x00000000) Pin select for SCL signal                             */
77797   __IOM uint32_t  SDA;                               /*!< (@ 0x00000004) Pin select for SDA signal                             */
77798 } NRF_TWIS_PSEL_Type;                                /*!< Size = 8 (0x008)                                                     */
77799 
77800 /* TWIS_PSEL_SCL: Pin select for SCL signal */
77801   #define TWIS_PSEL_SCL_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SCL register.                                         */
77802 
77803 /* PIN @Bits 0..4 : Pin number */
77804   #define TWIS_PSEL_SCL_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
77805   #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field.                                  */
77806   #define TWIS_PSEL_SCL_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
77807   #define TWIS_PSEL_SCL_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
77808 
77809 /* PORT @Bits 5..8 : Port number */
77810   #define TWIS_PSEL_SCL_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
77811   #define TWIS_PSEL_SCL_PORT_Msk (0xFUL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field.                                */
77812   #define TWIS_PSEL_SCL_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
77813   #define TWIS_PSEL_SCL_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
77814 
77815 /* CONNECT @Bit 31 : Connection */
77816   #define TWIS_PSEL_SCL_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
77817   #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
77818   #define TWIS_PSEL_SCL_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
77819   #define TWIS_PSEL_SCL_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
77820   #define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
77821   #define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
77822 
77823 
77824 /* TWIS_PSEL_SDA: Pin select for SDA signal */
77825   #define TWIS_PSEL_SDA_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SDA register.                                         */
77826 
77827 /* PIN @Bits 0..4 : Pin number */
77828   #define TWIS_PSEL_SDA_PIN_Pos (0UL)                /*!< Position of PIN field.                                               */
77829   #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field.                                  */
77830   #define TWIS_PSEL_SDA_PIN_Min (0x0UL)              /*!< Min value of PIN field.                                              */
77831   #define TWIS_PSEL_SDA_PIN_Max (0x1FUL)             /*!< Max size of PIN field.                                               */
77832 
77833 /* PORT @Bits 5..8 : Port number */
77834   #define TWIS_PSEL_SDA_PORT_Pos (5UL)               /*!< Position of PORT field.                                              */
77835   #define TWIS_PSEL_SDA_PORT_Msk (0xFUL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field.                                */
77836   #define TWIS_PSEL_SDA_PORT_Min (0x0UL)             /*!< Min value of PORT field.                                             */
77837   #define TWIS_PSEL_SDA_PORT_Max (0xFUL)             /*!< Max size of PORT field.                                              */
77838 
77839 /* CONNECT @Bit 31 : Connection */
77840   #define TWIS_PSEL_SDA_CONNECT_Pos (31UL)           /*!< Position of CONNECT field.                                           */
77841   #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field.                       */
77842   #define TWIS_PSEL_SDA_CONNECT_Min (0x0UL)          /*!< Min enumerator value of CONNECT field.                               */
77843   #define TWIS_PSEL_SDA_CONNECT_Max (0x1UL)          /*!< Max enumerator value of CONNECT field.                               */
77844   #define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                           */
77845   #define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL)    /*!< Connect                                                              */
77846 
77847 
77848 
77849 /* ===================================================== Struct TWIS_RXD ===================================================== */
77850 /**
77851   * @brief RXD [TWIS_RXD] RXD EasyDMA channel
77852   */
77853 typedef struct {
77854   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) RXD Data pointer                                      */
77855   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer                 */
77856   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last RXD
77857                                                                          transaction*/
77858   __IOM uint32_t  LIST;                              /*!< (@ 0x0000000C) EasyDMA list type                                     */
77859 } NRF_TWIS_RXD_Type;                                 /*!< Size = 16 (0x010)                                                    */
77860 
77861 /* TWIS_RXD_PTR: RXD Data pointer */
77862   #define TWIS_RXD_PTR_ResetValue (0x00000000UL)     /*!< Reset value of PTR register.                                         */
77863 
77864 /* PTR @Bits 0..31 : RXD Data pointer */
77865   #define TWIS_RXD_PTR_PTR_Pos (0UL)                 /*!< Position of PTR field.                                               */
77866   #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                              */
77867 
77868 
77869 /* TWIS_RXD_MAXCNT: Maximum number of bytes in RXD buffer */
77870   #define TWIS_RXD_MAXCNT_ResetValue (0x00000000UL)  /*!< Reset value of MAXCNT register.                                      */
77871 
77872 /* MAXCNT @Bits 0..14 : Maximum number of bytes in RXD buffer */
77873   #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL)           /*!< Position of MAXCNT field.                                            */
77874   #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                   */
77875   #define TWIS_RXD_MAXCNT_MAXCNT_Min (0x1UL)         /*!< Min value of MAXCNT field.                                           */
77876   #define TWIS_RXD_MAXCNT_MAXCNT_Max (0x7FFFUL)      /*!< Max size of MAXCNT field.                                            */
77877 
77878 
77879 /* TWIS_RXD_AMOUNT: Number of bytes transferred in the last RXD transaction */
77880   #define TWIS_RXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
77881 
77882 /* AMOUNT @Bits 0..14 : Number of bytes transferred in the last RXD transaction */
77883   #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL)           /*!< Position of AMOUNT field.                                            */
77884   #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
77885   #define TWIS_RXD_AMOUNT_AMOUNT_Min (0x1UL)         /*!< Min value of AMOUNT field.                                           */
77886   #define TWIS_RXD_AMOUNT_AMOUNT_Max (0x7FFFUL)      /*!< Max size of AMOUNT field.                                            */
77887 
77888 
77889 /* TWIS_RXD_LIST: EasyDMA list type */
77890   #define TWIS_RXD_LIST_ResetValue (0x00000000UL)    /*!< Reset value of LIST register.                                        */
77891 
77892 /* LIST @Bits 0..1 : List type */
77893   #define TWIS_RXD_LIST_LIST_Pos (0UL)               /*!< Position of LIST field.                                              */
77894   #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field.                                */
77895   #define TWIS_RXD_LIST_LIST_Min (0x0UL)             /*!< Min enumerator value of LIST field.                                  */
77896   #define TWIS_RXD_LIST_LIST_Max (0x1UL)             /*!< Max enumerator value of LIST field.                                  */
77897   #define TWIS_RXD_LIST_LIST_Disabled (0x0UL)        /*!< Disable EasyDMA list                                                 */
77898   #define TWIS_RXD_LIST_LIST_ArrayList (0x1UL)       /*!< Use array list                                                       */
77899 
77900 
77901 
77902 /* ===================================================== Struct TWIS_TXD ===================================================== */
77903 /**
77904   * @brief TXD [TWIS_TXD] TXD EasyDMA channel
77905   */
77906 typedef struct {
77907   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) TXD Data pointer                                      */
77908   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer                 */
77909   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last TXD
77910                                                                          transaction*/
77911   __IOM uint32_t  LIST;                              /*!< (@ 0x0000000C) EasyDMA list type                                     */
77912 } NRF_TWIS_TXD_Type;                                 /*!< Size = 16 (0x010)                                                    */
77913 
77914 /* TWIS_TXD_PTR: TXD Data pointer */
77915   #define TWIS_TXD_PTR_ResetValue (0x00000000UL)     /*!< Reset value of PTR register.                                         */
77916 
77917 /* PTR @Bits 0..31 : TXD Data pointer */
77918   #define TWIS_TXD_PTR_PTR_Pos (0UL)                 /*!< Position of PTR field.                                               */
77919   #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                              */
77920 
77921 
77922 /* TWIS_TXD_MAXCNT: Maximum number of bytes in TXD buffer */
77923   #define TWIS_TXD_MAXCNT_ResetValue (0x00000000UL)  /*!< Reset value of MAXCNT register.                                      */
77924 
77925 /* MAXCNT @Bits 0..14 : Maximum number of bytes in TXD buffer */
77926   #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL)           /*!< Position of MAXCNT field.                                            */
77927   #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                   */
77928   #define TWIS_TXD_MAXCNT_MAXCNT_Min (0x1UL)         /*!< Min value of MAXCNT field.                                           */
77929   #define TWIS_TXD_MAXCNT_MAXCNT_Max (0x7FFFUL)      /*!< Max size of MAXCNT field.                                            */
77930 
77931 
77932 /* TWIS_TXD_AMOUNT: Number of bytes transferred in the last TXD transaction */
77933   #define TWIS_TXD_AMOUNT_ResetValue (0x00000000UL)  /*!< Reset value of AMOUNT register.                                      */
77934 
77935 /* AMOUNT @Bits 0..14 : Number of bytes transferred in the last TXD transaction */
77936   #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL)           /*!< Position of AMOUNT field.                                            */
77937   #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                   */
77938   #define TWIS_TXD_AMOUNT_AMOUNT_Min (0x1UL)         /*!< Min value of AMOUNT field.                                           */
77939   #define TWIS_TXD_AMOUNT_AMOUNT_Max (0x7FFFUL)      /*!< Max size of AMOUNT field.                                            */
77940 
77941 
77942 /* TWIS_TXD_LIST: EasyDMA list type */
77943   #define TWIS_TXD_LIST_ResetValue (0x00000000UL)    /*!< Reset value of LIST register.                                        */
77944 
77945 /* LIST @Bits 0..1 : List type */
77946   #define TWIS_TXD_LIST_LIST_Pos (0UL)               /*!< Position of LIST field.                                              */
77947   #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field.                                */
77948   #define TWIS_TXD_LIST_LIST_Min (0x0UL)             /*!< Min enumerator value of LIST field.                                  */
77949   #define TWIS_TXD_LIST_LIST_Max (0x1UL)             /*!< Max enumerator value of LIST field.                                  */
77950   #define TWIS_TXD_LIST_LIST_Disabled (0x0UL)        /*!< Disable EasyDMA list                                                 */
77951   #define TWIS_TXD_LIST_LIST_ArrayList (0x1UL)       /*!< Use array list                                                       */
77952 
77953 
77954 
77955 /* =================================================== Struct TWIS_DMA_RX ==================================================== */
77956 /**
77957   * @brief RX [TWIS_DMA_RX] (unspecified)
77958   */
77959 typedef struct {
77960   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
77961                                                                          detected.*/
77962   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
77963                                                                          event.*/
77964 } NRF_TWIS_DMA_RX_Type;                              /*!< Size = 8 (0x008)                                                     */
77965 
77966 /* TWIS_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
77967   #define TWIS_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */
77968 
77969 /* ENABLE @Bit 0 : (unspecified) */
77970   #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
77971   #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
77972                                                                             ENABLE field.*/
77973   #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
77974   #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
77975   #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
77976   #define TWIS_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */
77977 
77978 
77979 /* TWIS_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
77980   #define TWIS_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */
77981 
77982 /* ADDRESS @Bits 0..31 : (unspecified) */
77983   #define TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
77984   #define TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIS_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
77985                                                                             ADDRESS field.*/
77986 
77987 
77988 
77989 /* =================================================== Struct TWIS_DMA_TX ==================================================== */
77990 /**
77991   * @brief TX [TWIS_DMA_TX] (unspecified)
77992   */
77993 typedef struct {
77994   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
77995                                                                          detected.*/
77996   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
77997                                                                          event.*/
77998 } NRF_TWIS_DMA_TX_Type;                              /*!< Size = 8 (0x008)                                                     */
77999 
78000 /* TWIS_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
78001   #define TWIS_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.          */
78002 
78003 /* ENABLE @Bit 0 : (unspecified) */
78004   #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                      */
78005   #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
78006                                                                             ENABLE field.*/
78007   #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                        */
78008   #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                        */
78009   #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                 */
78010   #define TWIS_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                   */
78011 
78012 
78013 /* TWIS_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
78014   #define TWIS_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                  */
78015 
78016 /* ADDRESS @Bits 0..31 : (unspecified) */
78017   #define TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                        */
78018   #define TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << TWIS_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
78019                                                                             ADDRESS field.*/
78020 
78021 
78022 
78023 /* ===================================================== Struct TWIS_DMA ===================================================== */
78024 /**
78025   * @brief DMA [TWIS_DMA] (unspecified)
78026   */
78027 typedef struct {
78028   __IOM NRF_TWIS_DMA_RX_Type RX;                     /*!< (@ 0x00000000) (unspecified)                                         */
78029   __IOM NRF_TWIS_DMA_TX_Type TX;                     /*!< (@ 0x00000008) (unspecified)                                         */
78030 } NRF_TWIS_DMA_Type;                                 /*!< Size = 16 (0x010)                                                    */
78031 
78032 /* ======================================================= Struct TWIS ======================================================= */
78033 /**
78034   * @brief I2C compatible Two-Wire Slave Interface with EasyDMA
78035   */
78036   typedef struct {                                   /*!< TWIS Structure                                                       */
78037     __IM uint32_t RESERVED[5];
78038     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000014) Stop TWI transaction                                  */
78039     __IM uint32_t RESERVED1;
78040     __OM uint32_t TASKS_SUSPEND;                     /*!< (@ 0x0000001C) Suspend TWI transaction                               */
78041     __OM uint32_t TASKS_RESUME;                      /*!< (@ 0x00000020) Resume TWI transaction                                */
78042     __IM uint32_t RESERVED2[3];
78043     __OM uint32_t TASKS_PREPARERX;                   /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command   */
78044     __OM uint32_t TASKS_PREPARETX;                   /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command    */
78045     __IM uint32_t RESERVED3[23];
78046     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000094) Subscribe configuration for task STOP                 */
78047     __IM uint32_t RESERVED4;
78048     __IOM uint32_t SUBSCRIBE_SUSPEND;                /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND              */
78049     __IOM uint32_t SUBSCRIBE_RESUME;                 /*!< (@ 0x000000A0) Subscribe configuration for task RESUME               */
78050     __IM uint32_t RESERVED5[3];
78051     __IOM uint32_t SUBSCRIBE_PREPARERX;              /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX            */
78052     __IOM uint32_t SUBSCRIBE_PREPARETX;              /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX            */
78053     __IM uint32_t RESERVED6[19];
78054     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) TWI stopped                                           */
78055     __IM uint32_t RESERVED7[7];
78056     __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000124) TWI error                                             */
78057     __IM uint32_t RESERVED8[9];
78058     __IOM uint32_t EVENTS_RXSTARTED;                 /*!< (@ 0x0000014C) Receive sequence started                              */
78059     __IOM uint32_t EVENTS_TXSTARTED;                 /*!< (@ 0x00000150) Transmit sequence started                             */
78060     __IM uint32_t RESERVED9[4];
78061     __IOM uint32_t EVENTS_WRITE;                     /*!< (@ 0x00000164) Write command received                                */
78062     __IOM uint32_t EVENTS_READ;                      /*!< (@ 0x00000168) Read command received                                 */
78063     __IM uint32_t RESERVED10[2];
78064     __IOM uint32_t EVENTS_RXBUSERROR;                /*!< (@ 0x00000174) This event is generated if an error occurs during the
78065                                                                          bus transfer.*/
78066     __IOM uint32_t EVENTS_TXBUSERROR;                /*!< (@ 0x00000178) This event is generated if an error occurs during the
78067                                                                          bus transfer.*/
78068     __IM uint32_t RESERVED11[2];
78069     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
78070     __IM uint32_t RESERVED12[7];
78071     __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x000001A4) Publish configuration for event ERROR                 */
78072     __IM uint32_t RESERVED13[9];
78073     __IOM uint32_t PUBLISH_RXSTARTED;                /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED             */
78074     __IOM uint32_t PUBLISH_TXSTARTED;                /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED             */
78075     __IM uint32_t RESERVED14[4];
78076     __IOM uint32_t PUBLISH_WRITE;                    /*!< (@ 0x000001E4) Publish configuration for event WRITE                 */
78077     __IOM uint32_t PUBLISH_READ;                     /*!< (@ 0x000001E8) Publish configuration for event READ                  */
78078     __IM uint32_t RESERVED15[2];
78079     __IOM uint32_t PUBLISH_RXBUSERROR;               /*!< (@ 0x000001F4) Publish configuration for event RXBUSERROR            */
78080     __IOM uint32_t PUBLISH_TXBUSERROR;               /*!< (@ 0x000001F8) Publish configuration for event TXBUSERROR            */
78081     __IM uint32_t RESERVED16;
78082     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
78083     __IM uint32_t RESERVED17[63];
78084     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
78085     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
78086     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
78087     __IM uint32_t RESERVED18[113];
78088     __IOM uint32_t ERRORSRC;                         /*!< (@ 0x000004D0) Error source                                          */
78089     __IM uint32_t MATCH;                             /*!< (@ 0x000004D4) Status register indicating which address had a match  */
78090     __IM uint32_t RESERVED19[10];
78091     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable TWIS                                           */
78092     __IM uint32_t RESERVED20;
78093     __IOM NRF_TWIS_PSEL_Type PSEL;                   /*!< (@ 0x00000508) (unspecified)                                         */
78094     __IM uint32_t RESERVED21[9];
78095     __IOM NRF_TWIS_RXD_Type RXD;                     /*!< (@ 0x00000534) RXD EasyDMA channel                                   */
78096     __IOM NRF_TWIS_TXD_Type TXD;                     /*!< (@ 0x00000544) TXD EasyDMA channel                                   */
78097     __IM uint32_t RESERVED22[13];
78098     __IOM uint32_t ADDRESS[2];                       /*!< (@ 0x00000588) TWI slave address n                                   */
78099     __IM uint32_t RESERVED23;
78100     __IOM uint32_t CONFIG;                           /*!< (@ 0x00000594) Configuration register for the address match mechanism*/
78101     __IM uint32_t RESERVED24[6];
78102     __IOM NRF_TWIS_DMA_Type DMA;                     /*!< (@ 0x000005B0) (unspecified)                                         */
78103     __IOM uint32_t ORC;                              /*!< (@ 0x000005C0) Over-read character. Character sent out in case of an
78104                                                                          over-read of the transmit buffer.*/
78105   } NRF_TWIS_Type;                                   /*!< Size = 1476 (0x5C4)                                                  */
78106 
78107 /* TWIS_TASKS_STOP: Stop TWI transaction */
78108   #define TWIS_TASKS_STOP_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_STOP register.                                  */
78109 
78110 /* TASKS_STOP @Bit 0 : Stop TWI transaction */
78111   #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL)       /*!< Position of TASKS_STOP field.                                        */
78112   #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.          */
78113   #define TWIS_TASKS_STOP_TASKS_STOP_Min (0x1UL)     /*!< Min enumerator value of TASKS_STOP field.                            */
78114   #define TWIS_TASKS_STOP_TASKS_STOP_Max (0x1UL)     /*!< Max enumerator value of TASKS_STOP field.                            */
78115   #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task                                                         */
78116 
78117 
78118 /* TWIS_TASKS_SUSPEND: Suspend TWI transaction */
78119   #define TWIS_TASKS_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of TASKS_SUSPEND register.                             */
78120 
78121 /* TASKS_SUSPEND @Bit 0 : Suspend TWI transaction */
78122   #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field.                                     */
78123   #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND
78124                                                                             field.*/
78125   #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Min (0x1UL) /*!< Min enumerator value of TASKS_SUSPEND field.                       */
78126   #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Max (0x1UL) /*!< Max enumerator value of TASKS_SUSPEND field.                       */
78127   #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task                                                   */
78128 
78129 
78130 /* TWIS_TASKS_RESUME: Resume TWI transaction */
78131   #define TWIS_TASKS_RESUME_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESUME register.                               */
78132 
78133 /* TASKS_RESUME @Bit 0 : Resume TWI transaction */
78134   #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL)   /*!< Position of TASKS_RESUME field.                                      */
78135   #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field.*/
78136   #define TWIS_TASKS_RESUME_TASKS_RESUME_Min (0x1UL) /*!< Min enumerator value of TASKS_RESUME field.                          */
78137   #define TWIS_TASKS_RESUME_TASKS_RESUME_Max (0x1UL) /*!< Max enumerator value of TASKS_RESUME field.                          */
78138   #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task                                                     */
78139 
78140 
78141 /* TWIS_TASKS_PREPARERX: Prepare the TWI slave to respond to a write command */
78142   #define TWIS_TASKS_PREPARERX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PREPARERX register.                         */
78143 
78144 /* TASKS_PREPARERX @Bit 0 : Prepare the TWI slave to respond to a write command */
78145   #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field.                               */
78146   #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of
78147                                                                             TASKS_PREPARERX field.*/
78148   #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Min (0x1UL) /*!< Min enumerator value of TASKS_PREPARERX field.                 */
78149   #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Max (0x1UL) /*!< Max enumerator value of TASKS_PREPARERX field.                 */
78150   #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task                                               */
78151 
78152 
78153 /* TWIS_TASKS_PREPARETX: Prepare the TWI slave to respond to a read command */
78154   #define TWIS_TASKS_PREPARETX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_PREPARETX register.                         */
78155 
78156 /* TASKS_PREPARETX @Bit 0 : Prepare the TWI slave to respond to a read command */
78157   #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field.                               */
78158   #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of
78159                                                                             TASKS_PREPARETX field.*/
78160   #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Min (0x1UL) /*!< Min enumerator value of TASKS_PREPARETX field.                 */
78161   #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Max (0x1UL) /*!< Max enumerator value of TASKS_PREPARETX field.                 */
78162   #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task                                               */
78163 
78164 
78165 /* TWIS_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
78166   #define TWIS_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                           */
78167 
78168 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
78169   #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
78170   #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
78171   #define TWIS_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
78172   #define TWIS_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
78173 
78174 /* EN @Bit 31 : (unspecified) */
78175   #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL)          /*!< Position of EN field.                                                */
78176   #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                          */
78177   #define TWIS_SUBSCRIBE_STOP_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
78178   #define TWIS_SUBSCRIBE_STOP_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
78179   #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
78180   #define TWIS_SUBSCRIBE_STOP_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
78181 
78182 
78183 /* TWIS_SUBSCRIBE_SUSPEND: Subscribe configuration for task SUSPEND */
78184   #define TWIS_SUBSCRIBE_SUSPEND_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_SUSPEND register.                     */
78185 
78186 /* CHIDX @Bits 0..7 : DPPI channel that task SUSPEND will subscribe to */
78187   #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
78188   #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
78189   #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
78190   #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
78191 
78192 /* EN @Bit 31 : (unspecified) */
78193   #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL)       /*!< Position of EN field.                                                */
78194   #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field.                    */
78195   #define TWIS_SUBSCRIBE_SUSPEND_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
78196   #define TWIS_SUBSCRIBE_SUSPEND_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
78197   #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
78198   #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
78199 
78200 
78201 /* TWIS_SUBSCRIBE_RESUME: Subscribe configuration for task RESUME */
78202   #define TWIS_SUBSCRIBE_RESUME_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESUME register.                       */
78203 
78204 /* CHIDX @Bits 0..7 : DPPI channel that task RESUME will subscribe to */
78205   #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL)      /*!< Position of CHIDX field.                                             */
78206   #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field.            */
78207   #define TWIS_SUBSCRIBE_RESUME_CHIDX_Min (0x0UL)    /*!< Min value of CHIDX field.                                            */
78208   #define TWIS_SUBSCRIBE_RESUME_CHIDX_Max (0xFFUL)   /*!< Max size of CHIDX field.                                             */
78209 
78210 /* EN @Bit 31 : (unspecified) */
78211   #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL)        /*!< Position of EN field.                                                */
78212   #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field.                      */
78213   #define TWIS_SUBSCRIBE_RESUME_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
78214   #define TWIS_SUBSCRIBE_RESUME_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
78215   #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
78216   #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
78217 
78218 
78219 /* TWIS_SUBSCRIBE_PREPARERX: Subscribe configuration for task PREPARERX */
78220   #define TWIS_SUBSCRIBE_PREPARERX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PREPARERX register.                 */
78221 
78222 /* CHIDX @Bits 0..7 : DPPI channel that task PREPARERX will subscribe to */
78223   #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
78224   #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
78225   #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
78226   #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
78227 
78228 /* EN @Bit 31 : (unspecified) */
78229   #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL)     /*!< Position of EN field.                                                */
78230   #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field.                */
78231   #define TWIS_SUBSCRIBE_PREPARERX_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
78232   #define TWIS_SUBSCRIBE_PREPARERX_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
78233   #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
78234   #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */
78235 
78236 
78237 /* TWIS_SUBSCRIBE_PREPARETX: Subscribe configuration for task PREPARETX */
78238   #define TWIS_SUBSCRIBE_PREPARETX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_PREPARETX register.                 */
78239 
78240 /* CHIDX @Bits 0..7 : DPPI channel that task PREPARETX will subscribe to */
78241   #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
78242   #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
78243   #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
78244   #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
78245 
78246 /* EN @Bit 31 : (unspecified) */
78247   #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL)     /*!< Position of EN field.                                                */
78248   #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field.                */
78249   #define TWIS_SUBSCRIBE_PREPARETX_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
78250   #define TWIS_SUBSCRIBE_PREPARETX_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
78251   #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0x0UL) /*!< Disable subscription                                               */
78252   #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (0x1UL) /*!< Enable subscription                                                 */
78253 
78254 
78255 /* TWIS_EVENTS_STOPPED: TWI stopped */
78256   #define TWIS_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                           */
78257 
78258 /* EVENTS_STOPPED @Bit 0 : TWI stopped */
78259   #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                  */
78260   #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of
78261                                                                             EVENTS_STOPPED field.*/
78262   #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                    */
78263   #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                    */
78264   #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                     */
78265   #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                            */
78266 
78267 
78268 /* TWIS_EVENTS_ERROR: TWI error */
78269   #define TWIS_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                               */
78270 
78271 /* EVENTS_ERROR @Bit 0 : TWI error */
78272   #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)   /*!< Position of EVENTS_ERROR field.                                      */
78273   #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field.*/
78274   #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field.                          */
78275   #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field.                          */
78276   #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                         */
78277   #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                                */
78278 
78279 
78280 /* TWIS_EVENTS_RXSTARTED: Receive sequence started */
78281   #define TWIS_EVENTS_RXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXSTARTED register.                       */
78282 
78283 /* EVENTS_RXSTARTED @Bit 0 : Receive sequence started */
78284   #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field.                            */
78285   #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of
78286                                                                             EVENTS_RXSTARTED field.*/
78287   #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXSTARTED field.              */
78288   #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXSTARTED field.              */
78289   #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                 */
78290   #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated                                        */
78291 
78292 
78293 /* TWIS_EVENTS_TXSTARTED: Transmit sequence started */
78294   #define TWIS_EVENTS_TXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXSTARTED register.                       */
78295 
78296 /* EVENTS_TXSTARTED @Bit 0 : Transmit sequence started */
78297   #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field.                            */
78298   #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of
78299                                                                             EVENTS_TXSTARTED field.*/
78300   #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXSTARTED field.              */
78301   #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXSTARTED field.              */
78302   #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                 */
78303   #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated                                        */
78304 
78305 
78306 /* TWIS_EVENTS_WRITE: Write command received */
78307   #define TWIS_EVENTS_WRITE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_WRITE register.                               */
78308 
78309 /* EVENTS_WRITE @Bit 0 : Write command received */
78310   #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL)   /*!< Position of EVENTS_WRITE field.                                      */
78311   #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field.*/
78312   #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Min (0x0UL) /*!< Min enumerator value of EVENTS_WRITE field.                          */
78313   #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Max (0x1UL) /*!< Max enumerator value of EVENTS_WRITE field.                          */
78314   #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated                                         */
78315   #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated                                                */
78316 
78317 
78318 /* TWIS_EVENTS_READ: Read command received */
78319   #define TWIS_EVENTS_READ_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READ register.                                 */
78320 
78321 /* EVENTS_READ @Bit 0 : Read command received */
78322   #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL)     /*!< Position of EVENTS_READ field.                                       */
78323   #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field.     */
78324   #define TWIS_EVENTS_READ_EVENTS_READ_Min (0x0UL)   /*!< Min enumerator value of EVENTS_READ field.                           */
78325   #define TWIS_EVENTS_READ_EVENTS_READ_Max (0x1UL)   /*!< Max enumerator value of EVENTS_READ field.                           */
78326   #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated                                           */
78327   #define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated                                                  */
78328 
78329 
78330 /* TWIS_EVENTS_RXBUSERROR: This event is generated if an error occurs during the bus transfer. */
78331   #define TWIS_EVENTS_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXBUSERROR register.                     */
78332 
78333 /* EVENTS_RXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
78334   #define TWIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos (0UL) /*!< Position of EVENTS_RXBUSERROR field.                         */
78335   #define TWIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Msk (0x1UL << TWIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos) /*!< Bit mask of
78336                                                                             EVENTS_RXBUSERROR field.*/
78337   #define TWIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXBUSERROR field.           */
78338   #define TWIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXBUSERROR field.           */
78339   #define TWIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                               */
78340   #define TWIS_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Generated (0x1UL) /*!< Event generated                                      */
78341 
78342 
78343 /* TWIS_EVENTS_TXBUSERROR: This event is generated if an error occurs during the bus transfer. */
78344   #define TWIS_EVENTS_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXBUSERROR register.                     */
78345 
78346 /* EVENTS_TXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
78347   #define TWIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos (0UL) /*!< Position of EVENTS_TXBUSERROR field.                         */
78348   #define TWIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Msk (0x1UL << TWIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos) /*!< Bit mask of
78349                                                                             EVENTS_TXBUSERROR field.*/
78350   #define TWIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXBUSERROR field.           */
78351   #define TWIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXBUSERROR field.           */
78352   #define TWIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                               */
78353   #define TWIS_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Generated (0x1UL) /*!< Event generated                                      */
78354 
78355 
78356 /* TWIS_PUBLISH_STOPPED: Publish configuration for event STOPPED */
78357   #define TWIS_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                         */
78358 
78359 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
78360   #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
78361   #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
78362   #define TWIS_PUBLISH_STOPPED_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
78363   #define TWIS_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
78364 
78365 /* EN @Bit 31 : (unspecified) */
78366   #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL)         /*!< Position of EN field.                                                */
78367   #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                        */
78368   #define TWIS_PUBLISH_STOPPED_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
78369   #define TWIS_PUBLISH_STOPPED_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
78370   #define TWIS_PUBLISH_STOPPED_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
78371   #define TWIS_PUBLISH_STOPPED_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
78372 
78373 
78374 /* TWIS_PUBLISH_ERROR: Publish configuration for event ERROR */
78375   #define TWIS_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                             */
78376 
78377 /* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
78378   #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
78379   #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
78380   #define TWIS_PUBLISH_ERROR_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
78381   #define TWIS_PUBLISH_ERROR_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
78382 
78383 /* EN @Bit 31 : (unspecified) */
78384   #define TWIS_PUBLISH_ERROR_EN_Pos (31UL)           /*!< Position of EN field.                                                */
78385   #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                            */
78386   #define TWIS_PUBLISH_ERROR_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
78387   #define TWIS_PUBLISH_ERROR_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
78388   #define TWIS_PUBLISH_ERROR_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
78389   #define TWIS_PUBLISH_ERROR_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
78390 
78391 
78392 /* TWIS_PUBLISH_RXSTARTED: Publish configuration for event RXSTARTED */
78393   #define TWIS_PUBLISH_RXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXSTARTED register.                     */
78394 
78395 /* CHIDX @Bits 0..7 : DPPI channel that event RXSTARTED will publish to */
78396   #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
78397   #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
78398   #define TWIS_PUBLISH_RXSTARTED_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
78399   #define TWIS_PUBLISH_RXSTARTED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
78400 
78401 /* EN @Bit 31 : (unspecified) */
78402   #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
78403   #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field.                    */
78404   #define TWIS_PUBLISH_RXSTARTED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
78405   #define TWIS_PUBLISH_RXSTARTED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
78406   #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
78407   #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
78408 
78409 
78410 /* TWIS_PUBLISH_TXSTARTED: Publish configuration for event TXSTARTED */
78411   #define TWIS_PUBLISH_TXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXSTARTED register.                     */
78412 
78413 /* CHIDX @Bits 0..7 : DPPI channel that event TXSTARTED will publish to */
78414   #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
78415   #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
78416   #define TWIS_PUBLISH_TXSTARTED_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
78417   #define TWIS_PUBLISH_TXSTARTED_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
78418 
78419 /* EN @Bit 31 : (unspecified) */
78420   #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL)       /*!< Position of EN field.                                                */
78421   #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field.                    */
78422   #define TWIS_PUBLISH_TXSTARTED_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
78423   #define TWIS_PUBLISH_TXSTARTED_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
78424   #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                                   */
78425   #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (0x1UL)  /*!< Enable publishing                                                    */
78426 
78427 
78428 /* TWIS_PUBLISH_WRITE: Publish configuration for event WRITE */
78429   #define TWIS_PUBLISH_WRITE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_WRITE register.                             */
78430 
78431 /* CHIDX @Bits 0..7 : DPPI channel that event WRITE will publish to */
78432   #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
78433   #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
78434   #define TWIS_PUBLISH_WRITE_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
78435   #define TWIS_PUBLISH_WRITE_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
78436 
78437 /* EN @Bit 31 : (unspecified) */
78438   #define TWIS_PUBLISH_WRITE_EN_Pos (31UL)           /*!< Position of EN field.                                                */
78439   #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field.                            */
78440   #define TWIS_PUBLISH_WRITE_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
78441   #define TWIS_PUBLISH_WRITE_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
78442   #define TWIS_PUBLISH_WRITE_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
78443   #define TWIS_PUBLISH_WRITE_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
78444 
78445 
78446 /* TWIS_PUBLISH_READ: Publish configuration for event READ */
78447   #define TWIS_PUBLISH_READ_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_READ register.                               */
78448 
78449 /* CHIDX @Bits 0..7 : DPPI channel that event READ will publish to */
78450   #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
78451   #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
78452   #define TWIS_PUBLISH_READ_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
78453   #define TWIS_PUBLISH_READ_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
78454 
78455 /* EN @Bit 31 : (unspecified) */
78456   #define TWIS_PUBLISH_READ_EN_Pos (31UL)            /*!< Position of EN field.                                                */
78457   #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field.                              */
78458   #define TWIS_PUBLISH_READ_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
78459   #define TWIS_PUBLISH_READ_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
78460   #define TWIS_PUBLISH_READ_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
78461   #define TWIS_PUBLISH_READ_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
78462 
78463 
78464 /* TWIS_PUBLISH_RXBUSERROR: Publish configuration for event RXBUSERROR */
78465   #define TWIS_PUBLISH_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXBUSERROR register.                   */
78466 
78467 /* CHIDX @Bits 0..7 : DPPI channel that event RXBUSERROR will publish to */
78468   #define TWIS_PUBLISH_RXBUSERROR_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
78469   #define TWIS_PUBLISH_RXBUSERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
78470   #define TWIS_PUBLISH_RXBUSERROR_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
78471   #define TWIS_PUBLISH_RXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
78472 
78473 /* EN @Bit 31 : (unspecified) */
78474   #define TWIS_PUBLISH_RXBUSERROR_EN_Pos (31UL)      /*!< Position of EN field.                                                */
78475   #define TWIS_PUBLISH_RXBUSERROR_EN_Msk (0x1UL << TWIS_PUBLISH_RXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                  */
78476   #define TWIS_PUBLISH_RXBUSERROR_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
78477   #define TWIS_PUBLISH_RXBUSERROR_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
78478   #define TWIS_PUBLISH_RXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
78479   #define TWIS_PUBLISH_RXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
78480 
78481 
78482 /* TWIS_PUBLISH_TXBUSERROR: Publish configuration for event TXBUSERROR */
78483   #define TWIS_PUBLISH_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXBUSERROR register.                   */
78484 
78485 /* CHIDX @Bits 0..7 : DPPI channel that event TXBUSERROR will publish to */
78486   #define TWIS_PUBLISH_TXBUSERROR_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
78487   #define TWIS_PUBLISH_TXBUSERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
78488   #define TWIS_PUBLISH_TXBUSERROR_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
78489   #define TWIS_PUBLISH_TXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
78490 
78491 /* EN @Bit 31 : (unspecified) */
78492   #define TWIS_PUBLISH_TXBUSERROR_EN_Pos (31UL)      /*!< Position of EN field.                                                */
78493   #define TWIS_PUBLISH_TXBUSERROR_EN_Msk (0x1UL << TWIS_PUBLISH_TXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                  */
78494   #define TWIS_PUBLISH_TXBUSERROR_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
78495   #define TWIS_PUBLISH_TXBUSERROR_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
78496   #define TWIS_PUBLISH_TXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
78497   #define TWIS_PUBLISH_TXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
78498 
78499 
78500 /* TWIS_SHORTS: Shortcuts between local events and tasks */
78501   #define TWIS_SHORTS_ResetValue (0x00000000UL)      /*!< Reset value of SHORTS register.                                      */
78502 
78503 /* WRITE_SUSPEND @Bit 13 : Shortcut between event WRITE and task SUSPEND */
78504   #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL)       /*!< Position of WRITE_SUSPEND field.                                     */
78505   #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field.         */
78506   #define TWIS_SHORTS_WRITE_SUSPEND_Min (0x0UL)      /*!< Min enumerator value of WRITE_SUSPEND field.                         */
78507   #define TWIS_SHORTS_WRITE_SUSPEND_Max (0x1UL)      /*!< Max enumerator value of WRITE_SUSPEND field.                         */
78508   #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut                                                     */
78509   #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
78510 
78511 /* READ_SUSPEND @Bit 14 : Shortcut between event READ and task SUSPEND */
78512   #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL)        /*!< Position of READ_SUSPEND field.                                      */
78513   #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field.            */
78514   #define TWIS_SHORTS_READ_SUSPEND_Min (0x0UL)       /*!< Min enumerator value of READ_SUSPEND field.                          */
78515   #define TWIS_SHORTS_READ_SUSPEND_Max (0x1UL)       /*!< Max enumerator value of READ_SUSPEND field.                          */
78516   #define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL)  /*!< Disable shortcut                                                     */
78517   #define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL)   /*!< Enable shortcut                                                      */
78518 
78519 
78520 /* TWIS_INTEN: Enable or disable interrupt */
78521   #define TWIS_INTEN_ResetValue (0x00000000UL)       /*!< Reset value of INTEN register.                                       */
78522 
78523 /* STOPPED @Bit 1 : Enable or disable interrupt for event STOPPED */
78524   #define TWIS_INTEN_STOPPED_Pos (1UL)               /*!< Position of STOPPED field.                                           */
78525   #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field.                             */
78526   #define TWIS_INTEN_STOPPED_Min (0x0UL)             /*!< Min enumerator value of STOPPED field.                               */
78527   #define TWIS_INTEN_STOPPED_Max (0x1UL)             /*!< Max enumerator value of STOPPED field.                               */
78528   #define TWIS_INTEN_STOPPED_Disabled (0x0UL)        /*!< Disable                                                              */
78529   #define TWIS_INTEN_STOPPED_Enabled (0x1UL)         /*!< Enable                                                               */
78530 
78531 /* ERROR @Bit 9 : Enable or disable interrupt for event ERROR */
78532   #define TWIS_INTEN_ERROR_Pos (9UL)                 /*!< Position of ERROR field.                                             */
78533   #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field.                                   */
78534   #define TWIS_INTEN_ERROR_Min (0x0UL)               /*!< Min enumerator value of ERROR field.                                 */
78535   #define TWIS_INTEN_ERROR_Max (0x1UL)               /*!< Max enumerator value of ERROR field.                                 */
78536   #define TWIS_INTEN_ERROR_Disabled (0x0UL)          /*!< Disable                                                              */
78537   #define TWIS_INTEN_ERROR_Enabled (0x1UL)           /*!< Enable                                                               */
78538 
78539 /* RXSTARTED @Bit 19 : Enable or disable interrupt for event RXSTARTED */
78540   #define TWIS_INTEN_RXSTARTED_Pos (19UL)            /*!< Position of RXSTARTED field.                                         */
78541   #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.                       */
78542   #define TWIS_INTEN_RXSTARTED_Min (0x0UL)           /*!< Min enumerator value of RXSTARTED field.                             */
78543   #define TWIS_INTEN_RXSTARTED_Max (0x1UL)           /*!< Max enumerator value of RXSTARTED field.                             */
78544   #define TWIS_INTEN_RXSTARTED_Disabled (0x0UL)      /*!< Disable                                                              */
78545   #define TWIS_INTEN_RXSTARTED_Enabled (0x1UL)       /*!< Enable                                                               */
78546 
78547 /* TXSTARTED @Bit 20 : Enable or disable interrupt for event TXSTARTED */
78548   #define TWIS_INTEN_TXSTARTED_Pos (20UL)            /*!< Position of TXSTARTED field.                                         */
78549   #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.                       */
78550   #define TWIS_INTEN_TXSTARTED_Min (0x0UL)           /*!< Min enumerator value of TXSTARTED field.                             */
78551   #define TWIS_INTEN_TXSTARTED_Max (0x1UL)           /*!< Max enumerator value of TXSTARTED field.                             */
78552   #define TWIS_INTEN_TXSTARTED_Disabled (0x0UL)      /*!< Disable                                                              */
78553   #define TWIS_INTEN_TXSTARTED_Enabled (0x1UL)       /*!< Enable                                                               */
78554 
78555 /* WRITE @Bit 25 : Enable or disable interrupt for event WRITE */
78556   #define TWIS_INTEN_WRITE_Pos (25UL)                /*!< Position of WRITE field.                                             */
78557   #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field.                                   */
78558   #define TWIS_INTEN_WRITE_Min (0x0UL)               /*!< Min enumerator value of WRITE field.                                 */
78559   #define TWIS_INTEN_WRITE_Max (0x1UL)               /*!< Max enumerator value of WRITE field.                                 */
78560   #define TWIS_INTEN_WRITE_Disabled (0x0UL)          /*!< Disable                                                              */
78561   #define TWIS_INTEN_WRITE_Enabled (0x1UL)           /*!< Enable                                                               */
78562 
78563 /* READ @Bit 26 : Enable or disable interrupt for event READ */
78564   #define TWIS_INTEN_READ_Pos (26UL)                 /*!< Position of READ field.                                              */
78565   #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field.                                      */
78566   #define TWIS_INTEN_READ_Min (0x0UL)                /*!< Min enumerator value of READ field.                                  */
78567   #define TWIS_INTEN_READ_Max (0x1UL)                /*!< Max enumerator value of READ field.                                  */
78568   #define TWIS_INTEN_READ_Disabled (0x0UL)           /*!< Disable                                                              */
78569   #define TWIS_INTEN_READ_Enabled (0x1UL)            /*!< Enable                                                               */
78570 
78571 /* RXBUSERROR @Bit 29 : Enable or disable interrupt for event RXBUSERROR */
78572   #define TWIS_INTEN_RXBUSERROR_Pos (29UL)           /*!< Position of RXBUSERROR field.                                        */
78573   #define TWIS_INTEN_RXBUSERROR_Msk (0x1UL << TWIS_INTEN_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.                    */
78574   #define TWIS_INTEN_RXBUSERROR_Min (0x0UL)          /*!< Min enumerator value of RXBUSERROR field.                            */
78575   #define TWIS_INTEN_RXBUSERROR_Max (0x1UL)          /*!< Max enumerator value of RXBUSERROR field.                            */
78576   #define TWIS_INTEN_RXBUSERROR_Disabled (0x0UL)     /*!< Disable                                                              */
78577   #define TWIS_INTEN_RXBUSERROR_Enabled (0x1UL)      /*!< Enable                                                               */
78578 
78579 /* TXBUSERROR @Bit 30 : Enable or disable interrupt for event TXBUSERROR */
78580   #define TWIS_INTEN_TXBUSERROR_Pos (30UL)           /*!< Position of TXBUSERROR field.                                        */
78581   #define TWIS_INTEN_TXBUSERROR_Msk (0x1UL << TWIS_INTEN_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.                    */
78582   #define TWIS_INTEN_TXBUSERROR_Min (0x0UL)          /*!< Min enumerator value of TXBUSERROR field.                            */
78583   #define TWIS_INTEN_TXBUSERROR_Max (0x1UL)          /*!< Max enumerator value of TXBUSERROR field.                            */
78584   #define TWIS_INTEN_TXBUSERROR_Disabled (0x0UL)     /*!< Disable                                                              */
78585   #define TWIS_INTEN_TXBUSERROR_Enabled (0x1UL)      /*!< Enable                                                               */
78586 
78587 
78588 /* TWIS_INTENSET: Enable interrupt */
78589   #define TWIS_INTENSET_ResetValue (0x00000000UL)    /*!< Reset value of INTENSET register.                                    */
78590 
78591 /* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
78592   #define TWIS_INTENSET_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
78593   #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
78594   #define TWIS_INTENSET_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
78595   #define TWIS_INTENSET_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
78596   #define TWIS_INTENSET_STOPPED_Set (0x1UL)          /*!< Enable                                                               */
78597   #define TWIS_INTENSET_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
78598   #define TWIS_INTENSET_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
78599 
78600 /* ERROR @Bit 9 : Write '1' to enable interrupt for event ERROR */
78601   #define TWIS_INTENSET_ERROR_Pos (9UL)              /*!< Position of ERROR field.                                             */
78602   #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
78603   #define TWIS_INTENSET_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
78604   #define TWIS_INTENSET_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
78605   #define TWIS_INTENSET_ERROR_Set (0x1UL)            /*!< Enable                                                               */
78606   #define TWIS_INTENSET_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
78607   #define TWIS_INTENSET_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
78608 
78609 /* RXSTARTED @Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
78610   #define TWIS_INTENSET_RXSTARTED_Pos (19UL)         /*!< Position of RXSTARTED field.                                         */
78611   #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.                 */
78612   #define TWIS_INTENSET_RXSTARTED_Min (0x0UL)        /*!< Min enumerator value of RXSTARTED field.                             */
78613   #define TWIS_INTENSET_RXSTARTED_Max (0x1UL)        /*!< Max enumerator value of RXSTARTED field.                             */
78614   #define TWIS_INTENSET_RXSTARTED_Set (0x1UL)        /*!< Enable                                                               */
78615   #define TWIS_INTENSET_RXSTARTED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
78616   #define TWIS_INTENSET_RXSTARTED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
78617 
78618 /* TXSTARTED @Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
78619   #define TWIS_INTENSET_TXSTARTED_Pos (20UL)         /*!< Position of TXSTARTED field.                                         */
78620   #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.                 */
78621   #define TWIS_INTENSET_TXSTARTED_Min (0x0UL)        /*!< Min enumerator value of TXSTARTED field.                             */
78622   #define TWIS_INTENSET_TXSTARTED_Max (0x1UL)        /*!< Max enumerator value of TXSTARTED field.                             */
78623   #define TWIS_INTENSET_TXSTARTED_Set (0x1UL)        /*!< Enable                                                               */
78624   #define TWIS_INTENSET_TXSTARTED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
78625   #define TWIS_INTENSET_TXSTARTED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
78626 
78627 /* WRITE @Bit 25 : Write '1' to enable interrupt for event WRITE */
78628   #define TWIS_INTENSET_WRITE_Pos (25UL)             /*!< Position of WRITE field.                                             */
78629   #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field.                             */
78630   #define TWIS_INTENSET_WRITE_Min (0x0UL)            /*!< Min enumerator value of WRITE field.                                 */
78631   #define TWIS_INTENSET_WRITE_Max (0x1UL)            /*!< Max enumerator value of WRITE field.                                 */
78632   #define TWIS_INTENSET_WRITE_Set (0x1UL)            /*!< Enable                                                               */
78633   #define TWIS_INTENSET_WRITE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
78634   #define TWIS_INTENSET_WRITE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
78635 
78636 /* READ @Bit 26 : Write '1' to enable interrupt for event READ */
78637   #define TWIS_INTENSET_READ_Pos (26UL)              /*!< Position of READ field.                                              */
78638   #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field.                                */
78639   #define TWIS_INTENSET_READ_Min (0x0UL)             /*!< Min enumerator value of READ field.                                  */
78640   #define TWIS_INTENSET_READ_Max (0x1UL)             /*!< Max enumerator value of READ field.                                  */
78641   #define TWIS_INTENSET_READ_Set (0x1UL)             /*!< Enable                                                               */
78642   #define TWIS_INTENSET_READ_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
78643   #define TWIS_INTENSET_READ_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
78644 
78645 /* RXBUSERROR @Bit 29 : Write '1' to enable interrupt for event RXBUSERROR */
78646   #define TWIS_INTENSET_RXBUSERROR_Pos (29UL)        /*!< Position of RXBUSERROR field.                                        */
78647   #define TWIS_INTENSET_RXBUSERROR_Msk (0x1UL << TWIS_INTENSET_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.              */
78648   #define TWIS_INTENSET_RXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of RXBUSERROR field.                            */
78649   #define TWIS_INTENSET_RXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of RXBUSERROR field.                            */
78650   #define TWIS_INTENSET_RXBUSERROR_Set (0x1UL)       /*!< Enable                                                               */
78651   #define TWIS_INTENSET_RXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
78652   #define TWIS_INTENSET_RXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
78653 
78654 /* TXBUSERROR @Bit 30 : Write '1' to enable interrupt for event TXBUSERROR */
78655   #define TWIS_INTENSET_TXBUSERROR_Pos (30UL)        /*!< Position of TXBUSERROR field.                                        */
78656   #define TWIS_INTENSET_TXBUSERROR_Msk (0x1UL << TWIS_INTENSET_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.              */
78657   #define TWIS_INTENSET_TXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of TXBUSERROR field.                            */
78658   #define TWIS_INTENSET_TXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of TXBUSERROR field.                            */
78659   #define TWIS_INTENSET_TXBUSERROR_Set (0x1UL)       /*!< Enable                                                               */
78660   #define TWIS_INTENSET_TXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
78661   #define TWIS_INTENSET_TXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
78662 
78663 
78664 /* TWIS_INTENCLR: Disable interrupt */
78665   #define TWIS_INTENCLR_ResetValue (0x00000000UL)    /*!< Reset value of INTENCLR register.                                    */
78666 
78667 /* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
78668   #define TWIS_INTENCLR_STOPPED_Pos (1UL)            /*!< Position of STOPPED field.                                           */
78669   #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                       */
78670   #define TWIS_INTENCLR_STOPPED_Min (0x0UL)          /*!< Min enumerator value of STOPPED field.                               */
78671   #define TWIS_INTENCLR_STOPPED_Max (0x1UL)          /*!< Max enumerator value of STOPPED field.                               */
78672   #define TWIS_INTENCLR_STOPPED_Clear (0x1UL)        /*!< Disable                                                              */
78673   #define TWIS_INTENCLR_STOPPED_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
78674   #define TWIS_INTENCLR_STOPPED_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
78675 
78676 /* ERROR @Bit 9 : Write '1' to disable interrupt for event ERROR */
78677   #define TWIS_INTENCLR_ERROR_Pos (9UL)              /*!< Position of ERROR field.                                             */
78678   #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                             */
78679   #define TWIS_INTENCLR_ERROR_Min (0x0UL)            /*!< Min enumerator value of ERROR field.                                 */
78680   #define TWIS_INTENCLR_ERROR_Max (0x1UL)            /*!< Max enumerator value of ERROR field.                                 */
78681   #define TWIS_INTENCLR_ERROR_Clear (0x1UL)          /*!< Disable                                                              */
78682   #define TWIS_INTENCLR_ERROR_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
78683   #define TWIS_INTENCLR_ERROR_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
78684 
78685 /* RXSTARTED @Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
78686   #define TWIS_INTENCLR_RXSTARTED_Pos (19UL)         /*!< Position of RXSTARTED field.                                         */
78687   #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.                 */
78688   #define TWIS_INTENCLR_RXSTARTED_Min (0x0UL)        /*!< Min enumerator value of RXSTARTED field.                             */
78689   #define TWIS_INTENCLR_RXSTARTED_Max (0x1UL)        /*!< Max enumerator value of RXSTARTED field.                             */
78690   #define TWIS_INTENCLR_RXSTARTED_Clear (0x1UL)      /*!< Disable                                                              */
78691   #define TWIS_INTENCLR_RXSTARTED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
78692   #define TWIS_INTENCLR_RXSTARTED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
78693 
78694 /* TXSTARTED @Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
78695   #define TWIS_INTENCLR_TXSTARTED_Pos (20UL)         /*!< Position of TXSTARTED field.                                         */
78696   #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.                 */
78697   #define TWIS_INTENCLR_TXSTARTED_Min (0x0UL)        /*!< Min enumerator value of TXSTARTED field.                             */
78698   #define TWIS_INTENCLR_TXSTARTED_Max (0x1UL)        /*!< Max enumerator value of TXSTARTED field.                             */
78699   #define TWIS_INTENCLR_TXSTARTED_Clear (0x1UL)      /*!< Disable                                                              */
78700   #define TWIS_INTENCLR_TXSTARTED_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
78701   #define TWIS_INTENCLR_TXSTARTED_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
78702 
78703 /* WRITE @Bit 25 : Write '1' to disable interrupt for event WRITE */
78704   #define TWIS_INTENCLR_WRITE_Pos (25UL)             /*!< Position of WRITE field.                                             */
78705   #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field.                             */
78706   #define TWIS_INTENCLR_WRITE_Min (0x0UL)            /*!< Min enumerator value of WRITE field.                                 */
78707   #define TWIS_INTENCLR_WRITE_Max (0x1UL)            /*!< Max enumerator value of WRITE field.                                 */
78708   #define TWIS_INTENCLR_WRITE_Clear (0x1UL)          /*!< Disable                                                              */
78709   #define TWIS_INTENCLR_WRITE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
78710   #define TWIS_INTENCLR_WRITE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
78711 
78712 /* READ @Bit 26 : Write '1' to disable interrupt for event READ */
78713   #define TWIS_INTENCLR_READ_Pos (26UL)              /*!< Position of READ field.                                              */
78714   #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field.                                */
78715   #define TWIS_INTENCLR_READ_Min (0x0UL)             /*!< Min enumerator value of READ field.                                  */
78716   #define TWIS_INTENCLR_READ_Max (0x1UL)             /*!< Max enumerator value of READ field.                                  */
78717   #define TWIS_INTENCLR_READ_Clear (0x1UL)           /*!< Disable                                                              */
78718   #define TWIS_INTENCLR_READ_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
78719   #define TWIS_INTENCLR_READ_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
78720 
78721 /* RXBUSERROR @Bit 29 : Write '1' to disable interrupt for event RXBUSERROR */
78722   #define TWIS_INTENCLR_RXBUSERROR_Pos (29UL)        /*!< Position of RXBUSERROR field.                                        */
78723   #define TWIS_INTENCLR_RXBUSERROR_Msk (0x1UL << TWIS_INTENCLR_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.              */
78724   #define TWIS_INTENCLR_RXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of RXBUSERROR field.                            */
78725   #define TWIS_INTENCLR_RXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of RXBUSERROR field.                            */
78726   #define TWIS_INTENCLR_RXBUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
78727   #define TWIS_INTENCLR_RXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
78728   #define TWIS_INTENCLR_RXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
78729 
78730 /* TXBUSERROR @Bit 30 : Write '1' to disable interrupt for event TXBUSERROR */
78731   #define TWIS_INTENCLR_TXBUSERROR_Pos (30UL)        /*!< Position of TXBUSERROR field.                                        */
78732   #define TWIS_INTENCLR_TXBUSERROR_Msk (0x1UL << TWIS_INTENCLR_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.              */
78733   #define TWIS_INTENCLR_TXBUSERROR_Min (0x0UL)       /*!< Min enumerator value of TXBUSERROR field.                            */
78734   #define TWIS_INTENCLR_TXBUSERROR_Max (0x1UL)       /*!< Max enumerator value of TXBUSERROR field.                            */
78735   #define TWIS_INTENCLR_TXBUSERROR_Clear (0x1UL)     /*!< Disable                                                              */
78736   #define TWIS_INTENCLR_TXBUSERROR_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
78737   #define TWIS_INTENCLR_TXBUSERROR_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
78738 
78739 
78740 /* TWIS_ERRORSRC: Error source */
78741   #define TWIS_ERRORSRC_ResetValue (0x00000000UL)    /*!< Reset value of ERRORSRC register.                                    */
78742 
78743 /* OVERFLOW @Bit 0 : RX buffer overflow detected, and prevented */
78744   #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL)           /*!< Position of OVERFLOW field.                                          */
78745   #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field.                    */
78746   #define TWIS_ERRORSRC_OVERFLOW_Min (0x0UL)         /*!< Min enumerator value of OVERFLOW field.                              */
78747   #define TWIS_ERRORSRC_OVERFLOW_Max (0x1UL)         /*!< Max enumerator value of OVERFLOW field.                              */
78748   #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur                                                  */
78749   #define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL)    /*!< Error occurred                                                       */
78750 
78751 /* DNACK @Bit 2 : NACK sent after receiving a data byte */
78752   #define TWIS_ERRORSRC_DNACK_Pos (2UL)              /*!< Position of DNACK field.                                             */
78753   #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field.                             */
78754   #define TWIS_ERRORSRC_DNACK_Min (0x0UL)            /*!< Min enumerator value of DNACK field.                                 */
78755   #define TWIS_ERRORSRC_DNACK_Max (0x1UL)            /*!< Max enumerator value of DNACK field.                                 */
78756   #define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL)    /*!< Error did not occur                                                  */
78757   #define TWIS_ERRORSRC_DNACK_Received (0x1UL)       /*!< Error occurred                                                       */
78758 
78759 /* OVERREAD @Bit 3 : TX buffer over-read detected, and prevented */
78760   #define TWIS_ERRORSRC_OVERREAD_Pos (3UL)           /*!< Position of OVERREAD field.                                          */
78761   #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field.                    */
78762   #define TWIS_ERRORSRC_OVERREAD_Min (0x0UL)         /*!< Min enumerator value of OVERREAD field.                              */
78763   #define TWIS_ERRORSRC_OVERREAD_Max (0x1UL)         /*!< Max enumerator value of OVERREAD field.                              */
78764   #define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur                                                  */
78765   #define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL)    /*!< Error occurred                                                       */
78766 
78767 
78768 /* TWIS_MATCH: Status register indicating which address had a match */
78769   #define TWIS_MATCH_ResetValue (0x00000000UL)       /*!< Reset value of MATCH register.                                       */
78770 
78771 /* MATCH @Bit 0 : Indication of which address in ADDRESS that matched the incoming address */
78772   #define TWIS_MATCH_MATCH_Pos (0UL)                 /*!< Position of MATCH field.                                             */
78773   #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field.                                   */
78774   #define TWIS_MATCH_MATCH_Min (0x0UL)               /*!< Min value of MATCH field.                                            */
78775   #define TWIS_MATCH_MATCH_Max (0x1UL)               /*!< Max size of MATCH field.                                             */
78776 
78777 
78778 /* TWIS_ENABLE: Enable TWIS */
78779   #define TWIS_ENABLE_ResetValue (0x00000000UL)      /*!< Reset value of ENABLE register.                                      */
78780 
78781 /* ENABLE @Bits 0..3 : Enable or disable TWIS */
78782   #define TWIS_ENABLE_ENABLE_Pos (0UL)               /*!< Position of ENABLE field.                                            */
78783   #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                              */
78784   #define TWIS_ENABLE_ENABLE_Min (0x0UL)             /*!< Min enumerator value of ENABLE field.                                */
78785   #define TWIS_ENABLE_ENABLE_Max (0x9UL)             /*!< Max enumerator value of ENABLE field.                                */
78786   #define TWIS_ENABLE_ENABLE_Disabled (0x0UL)        /*!< Disable TWIS                                                         */
78787   #define TWIS_ENABLE_ENABLE_Enabled (0x9UL)         /*!< Enable TWIS                                                          */
78788 
78789 
78790 /* TWIS_ADDRESS: TWI slave address n */
78791   #define TWIS_ADDRESS_MaxCount (2UL)                /*!< Max size of ADDRESS[2] array.                                        */
78792   #define TWIS_ADDRESS_MaxIndex (1UL)                /*!< Max index of ADDRESS[2] array.                                       */
78793   #define TWIS_ADDRESS_MinIndex (0UL)                /*!< Min index of ADDRESS[2] array.                                       */
78794   #define TWIS_ADDRESS_ResetValue (0x00000000UL)     /*!< Reset value of ADDRESS[2] register.                                  */
78795 
78796 /* ADDRESS @Bits 0..6 : TWI slave address */
78797   #define TWIS_ADDRESS_ADDRESS_Pos (0UL)             /*!< Position of ADDRESS field.                                           */
78798   #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.                        */
78799 
78800 
78801 /* TWIS_CONFIG: Configuration register for the address match mechanism */
78802   #define TWIS_CONFIG_ResetValue (0x00000001UL)      /*!< Reset value of CONFIG register.                                      */
78803 
78804 /* ADDRESS0 @Bit 0 : Enable or disable address matching on ADDRESS[0] */
78805   #define TWIS_CONFIG_ADDRESS0_Pos (0UL)             /*!< Position of ADDRESS0 field.                                          */
78806   #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field.                        */
78807   #define TWIS_CONFIG_ADDRESS0_Min (0x0UL)           /*!< Min enumerator value of ADDRESS0 field.                              */
78808   #define TWIS_CONFIG_ADDRESS0_Max (0x1UL)           /*!< Max enumerator value of ADDRESS0 field.                              */
78809   #define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL)      /*!< Disabled                                                             */
78810   #define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL)       /*!< Enabled                                                              */
78811 
78812 /* ADDRESS1 @Bit 1 : Enable or disable address matching on ADDRESS[1] */
78813   #define TWIS_CONFIG_ADDRESS1_Pos (1UL)             /*!< Position of ADDRESS1 field.                                          */
78814   #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field.                        */
78815   #define TWIS_CONFIG_ADDRESS1_Min (0x0UL)           /*!< Min enumerator value of ADDRESS1 field.                              */
78816   #define TWIS_CONFIG_ADDRESS1_Max (0x1UL)           /*!< Max enumerator value of ADDRESS1 field.                              */
78817   #define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL)      /*!< Disabled                                                             */
78818   #define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL)       /*!< Enabled                                                              */
78819 
78820 
78821 /* TWIS_ORC: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
78822   #define TWIS_ORC_ResetValue (0x00000000UL)         /*!< Reset value of ORC register.                                         */
78823 
78824 /* ORC @Bits 0..7 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
78825   #define TWIS_ORC_ORC_Pos (0UL)                     /*!< Position of ORC field.                                               */
78826   #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field.                                            */
78827 
78828 
78829 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
78830 
78831 /* =========================================================================================================================== */
78832 /* ================                                           UARTE                                           ================ */
78833 /* =========================================================================================================================== */
78834 
78835 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
78836 
78837 /* ==================================================== Struct UARTE_PSEL ==================================================== */
78838 /**
78839   * @brief PSEL [UARTE_PSEL] (unspecified)
78840   */
78841 typedef struct {
78842   __IOM uint32_t  RTS;                               /*!< (@ 0x00000000) Pin select for RTS signal                             */
78843   __IOM uint32_t  TXD;                               /*!< (@ 0x00000004) Pin select for TXD signal                             */
78844   __IOM uint32_t  CTS;                               /*!< (@ 0x00000008) Pin select for CTS signal                             */
78845   __IOM uint32_t  RXD;                               /*!< (@ 0x0000000C) Pin select for RXD signal                             */
78846 } NRF_UARTE_PSEL_Type;                               /*!< Size = 16 (0x010)                                                    */
78847 
78848 /* UARTE_PSEL_RTS: Pin select for RTS signal */
78849   #define UARTE_PSEL_RTS_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of RTS register.                                         */
78850 
78851 /* PIN @Bits 0..4 : Pin number */
78852   #define UARTE_PSEL_RTS_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
78853   #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field.                                */
78854   #define UARTE_PSEL_RTS_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
78855   #define UARTE_PSEL_RTS_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
78856 
78857 /* PORT @Bits 5..8 : Port number */
78858   #define UARTE_PSEL_RTS_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
78859   #define UARTE_PSEL_RTS_PORT_Msk (0xFUL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field.                              */
78860   #define UARTE_PSEL_RTS_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
78861   #define UARTE_PSEL_RTS_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
78862 
78863 /* CONNECT @Bit 31 : Connection */
78864   #define UARTE_PSEL_RTS_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
78865   #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
78866   #define UARTE_PSEL_RTS_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
78867   #define UARTE_PSEL_RTS_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
78868   #define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
78869   #define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
78870 
78871 
78872 /* UARTE_PSEL_TXD: Pin select for TXD signal */
78873   #define UARTE_PSEL_TXD_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of TXD register.                                         */
78874 
78875 /* PIN @Bits 0..4 : Pin number */
78876   #define UARTE_PSEL_TXD_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
78877   #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field.                                */
78878   #define UARTE_PSEL_TXD_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
78879   #define UARTE_PSEL_TXD_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
78880 
78881 /* PORT @Bits 5..8 : Port number */
78882   #define UARTE_PSEL_TXD_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
78883   #define UARTE_PSEL_TXD_PORT_Msk (0xFUL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field.                              */
78884   #define UARTE_PSEL_TXD_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
78885   #define UARTE_PSEL_TXD_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
78886 
78887 /* CONNECT @Bit 31 : Connection */
78888   #define UARTE_PSEL_TXD_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
78889   #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
78890   #define UARTE_PSEL_TXD_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
78891   #define UARTE_PSEL_TXD_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
78892   #define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
78893   #define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
78894 
78895 
78896 /* UARTE_PSEL_CTS: Pin select for CTS signal */
78897   #define UARTE_PSEL_CTS_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of CTS register.                                         */
78898 
78899 /* PIN @Bits 0..4 : Pin number */
78900   #define UARTE_PSEL_CTS_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
78901   #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field.                                */
78902   #define UARTE_PSEL_CTS_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
78903   #define UARTE_PSEL_CTS_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
78904 
78905 /* PORT @Bits 5..8 : Port number */
78906   #define UARTE_PSEL_CTS_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
78907   #define UARTE_PSEL_CTS_PORT_Msk (0xFUL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field.                              */
78908   #define UARTE_PSEL_CTS_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
78909   #define UARTE_PSEL_CTS_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
78910 
78911 /* CONNECT @Bit 31 : Connection */
78912   #define UARTE_PSEL_CTS_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
78913   #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
78914   #define UARTE_PSEL_CTS_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
78915   #define UARTE_PSEL_CTS_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
78916   #define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
78917   #define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
78918 
78919 
78920 /* UARTE_PSEL_RXD: Pin select for RXD signal */
78921   #define UARTE_PSEL_RXD_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of RXD register.                                         */
78922 
78923 /* PIN @Bits 0..4 : Pin number */
78924   #define UARTE_PSEL_RXD_PIN_Pos (0UL)               /*!< Position of PIN field.                                               */
78925   #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field.                                */
78926   #define UARTE_PSEL_RXD_PIN_Min (0x0UL)             /*!< Min value of PIN field.                                              */
78927   #define UARTE_PSEL_RXD_PIN_Max (0x1FUL)            /*!< Max size of PIN field.                                               */
78928 
78929 /* PORT @Bits 5..8 : Port number */
78930   #define UARTE_PSEL_RXD_PORT_Pos (5UL)              /*!< Position of PORT field.                                              */
78931   #define UARTE_PSEL_RXD_PORT_Msk (0xFUL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field.                              */
78932   #define UARTE_PSEL_RXD_PORT_Min (0x0UL)            /*!< Min value of PORT field.                                             */
78933   #define UARTE_PSEL_RXD_PORT_Max (0xFUL)            /*!< Max size of PORT field.                                              */
78934 
78935 /* CONNECT @Bit 31 : Connection */
78936   #define UARTE_PSEL_RXD_CONNECT_Pos (31UL)          /*!< Position of CONNECT field.                                           */
78937   #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field.                     */
78938   #define UARTE_PSEL_RXD_CONNECT_Min (0x0UL)         /*!< Min enumerator value of CONNECT field.                               */
78939   #define UARTE_PSEL_RXD_CONNECT_Max (0x1UL)         /*!< Max enumerator value of CONNECT field.                               */
78940   #define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect                                                          */
78941   #define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL)   /*!< Connect                                                              */
78942 
78943 
78944 
78945 /* ==================================================== Struct UARTE_RXD ===================================================== */
78946 /**
78947   * @brief RXD [UARTE_RXD] RXD EasyDMA channel
78948   */
78949 typedef struct {
78950   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
78951   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in receive buffer             */
78952   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last transaction   */
78953 } NRF_UARTE_RXD_Type;                                /*!< Size = 12 (0x00C)                                                    */
78954 
78955 /* UARTE_RXD_PTR: Data pointer */
78956   #define UARTE_RXD_PTR_ResetValue (0x00000000UL)    /*!< Reset value of PTR register.                                         */
78957 
78958 /* PTR @Bits 0..31 : Data pointer */
78959   #define UARTE_RXD_PTR_PTR_Pos (0UL)                /*!< Position of PTR field.                                               */
78960   #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                            */
78961 
78962 
78963 /* UARTE_RXD_MAXCNT: Maximum number of bytes in receive buffer */
78964   #define UARTE_RXD_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                      */
78965 
78966 /* MAXCNT @Bits 0..14 : Maximum number of bytes in receive buffer */
78967   #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL)          /*!< Position of MAXCNT field.                                            */
78968   #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                 */
78969   #define UARTE_RXD_MAXCNT_MAXCNT_Min (0x1UL)        /*!< Min value of MAXCNT field.                                           */
78970   #define UARTE_RXD_MAXCNT_MAXCNT_Max (0x7FFFUL)     /*!< Max size of MAXCNT field.                                            */
78971 
78972 
78973 /* UARTE_RXD_AMOUNT: Number of bytes transferred in the last transaction */
78974   #define UARTE_RXD_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                      */
78975 
78976 /* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction */
78977   #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL)          /*!< Position of AMOUNT field.                                            */
78978   #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                 */
78979   #define UARTE_RXD_AMOUNT_AMOUNT_Min (0x1UL)        /*!< Min value of AMOUNT field.                                           */
78980   #define UARTE_RXD_AMOUNT_AMOUNT_Max (0x7FFFUL)     /*!< Max size of AMOUNT field.                                            */
78981 
78982 
78983 
78984 /* ==================================================== Struct UARTE_TXD ===================================================== */
78985 /**
78986   * @brief TXD [UARTE_TXD] TXD EasyDMA channel
78987   */
78988 typedef struct {
78989   __IOM uint32_t  PTR;                               /*!< (@ 0x00000000) Data pointer                                          */
78990   __IOM uint32_t  MAXCNT;                            /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer            */
78991   __IM  uint32_t  AMOUNT;                            /*!< (@ 0x00000008) Number of bytes transferred in the last transaction   */
78992 } NRF_UARTE_TXD_Type;                                /*!< Size = 12 (0x00C)                                                    */
78993 
78994 /* UARTE_TXD_PTR: Data pointer */
78995   #define UARTE_TXD_PTR_ResetValue (0x00000000UL)    /*!< Reset value of PTR register.                                         */
78996 
78997 /* PTR @Bits 0..31 : Data pointer */
78998   #define UARTE_TXD_PTR_PTR_Pos (0UL)                /*!< Position of PTR field.                                               */
78999   #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field.                            */
79000 
79001 
79002 /* UARTE_TXD_MAXCNT: Maximum number of bytes in transmit buffer */
79003   #define UARTE_TXD_MAXCNT_ResetValue (0x00000000UL) /*!< Reset value of MAXCNT register.                                      */
79004 
79005 /* MAXCNT @Bits 0..14 : Maximum number of bytes in transmit buffer */
79006   #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL)          /*!< Position of MAXCNT field.                                            */
79007   #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x7FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field.                 */
79008   #define UARTE_TXD_MAXCNT_MAXCNT_Min (0x1UL)        /*!< Min value of MAXCNT field.                                           */
79009   #define UARTE_TXD_MAXCNT_MAXCNT_Max (0x7FFFUL)     /*!< Max size of MAXCNT field.                                            */
79010 
79011 
79012 /* UARTE_TXD_AMOUNT: Number of bytes transferred in the last transaction */
79013   #define UARTE_TXD_AMOUNT_ResetValue (0x00000000UL) /*!< Reset value of AMOUNT register.                                      */
79014 
79015 /* AMOUNT @Bits 0..14 : Number of bytes transferred in the last transaction */
79016   #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL)          /*!< Position of AMOUNT field.                                            */
79017   #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x7FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field.                 */
79018   #define UARTE_TXD_AMOUNT_AMOUNT_Min (0x1UL)        /*!< Min value of AMOUNT field.                                           */
79019   #define UARTE_TXD_AMOUNT_AMOUNT_Max (0x7FFFUL)     /*!< Max size of AMOUNT field.                                            */
79020 
79021 
79022 
79023 /* =================================================== Struct UARTE_DMA_RX =================================================== */
79024 /**
79025   * @brief RX [UARTE_DMA_RX] (unspecified)
79026   */
79027 typedef struct {
79028   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
79029                                                                          detected.*/
79030   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
79031                                                                          event.*/
79032 } NRF_UARTE_DMA_RX_Type;                             /*!< Size = 8 (0x008)                                                     */
79033 
79034 /* UARTE_DMA_RX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
79035   #define UARTE_DMA_RX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.         */
79036 
79037 /* ENABLE @Bit 0 : (unspecified) */
79038   #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                     */
79039   #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
79040                                                                             ENABLE field.*/
79041   #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                       */
79042   #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                       */
79043   #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                */
79044   #define UARTE_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                  */
79045 
79046 
79047 /* UARTE_DMA_RX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
79048   #define UARTE_DMA_RX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                 */
79049 
79050 /* ADDRESS @Bits 0..31 : (unspecified) */
79051   #define UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                       */
79052   #define UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UARTE_DMA_RX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
79053                                                                             ADDRESS field.*/
79054 
79055 
79056 
79057 /* =================================================== Struct UARTE_DMA_TX =================================================== */
79058 /**
79059   * @brief TX [UARTE_DMA_TX] (unspecified)
79060   */
79061 typedef struct {
79062   __IOM uint32_t  TERMINATEONBUSERROR;               /*!< (@ 0x00000000) Terminate the transaction if a BUSERROR event is
79063                                                                          detected.*/
79064   __IM  uint32_t  BUSERRORADDRESS;                   /*!< (@ 0x00000004) Address of transaction that generated the last BUSERROR
79065                                                                          event.*/
79066 } NRF_UARTE_DMA_TX_Type;                             /*!< Size = 8 (0x008)                                                     */
79067 
79068 /* UARTE_DMA_TX_TERMINATEONBUSERROR: Terminate the transaction if a BUSERROR event is detected. */
79069   #define UARTE_DMA_TX_TERMINATEONBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of TERMINATEONBUSERROR register.         */
79070 
79071 /* ENABLE @Bit 0 : (unspecified) */
79072   #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos (0UL) /*!< Position of ENABLE field.                                     */
79073   #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk (0x1UL << UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) /*!< Bit mask of
79074                                                                             ENABLE field.*/
79075   #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field.                       */
79076   #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field.                       */
79077   #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Disabled (0x0UL) /*!< Disable                                                */
79078   #define UARTE_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled (0x1UL) /*!< Enable                                                  */
79079 
79080 
79081 /* UARTE_DMA_TX_BUSERRORADDRESS: Address of transaction that generated the last BUSERROR event. */
79082   #define UARTE_DMA_TX_BUSERRORADDRESS_ResetValue (0x00000000UL) /*!< Reset value of BUSERRORADDRESS register.                 */
79083 
79084 /* ADDRESS @Bits 0..31 : (unspecified) */
79085   #define UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                       */
79086   #define UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UARTE_DMA_TX_BUSERRORADDRESS_ADDRESS_Pos) /*!< Bit mask of
79087                                                                             ADDRESS field.*/
79088 
79089 
79090 
79091 /* ==================================================== Struct UARTE_DMA ===================================================== */
79092 /**
79093   * @brief DMA [UARTE_DMA] (unspecified)
79094   */
79095 typedef struct {
79096   __IOM NRF_UARTE_DMA_RX_Type RX;                    /*!< (@ 0x00000000) (unspecified)                                         */
79097   __IOM NRF_UARTE_DMA_TX_Type TX;                    /*!< (@ 0x00000008) (unspecified)                                         */
79098 } NRF_UARTE_DMA_Type;                                /*!< Size = 16 (0x010)                                                    */
79099 
79100 /* ====================================================== Struct UARTE ======================================================= */
79101 /**
79102   * @brief UART with EasyDMA
79103   */
79104   typedef struct {                                   /*!< UARTE Structure                                                      */
79105     __OM uint32_t TASKS_STARTRX;                     /*!< (@ 0x00000000) Start UART receiver                                   */
79106     __OM uint32_t TASKS_STOPRX;                      /*!< (@ 0x00000004) Stop UART receiver                                    */
79107     __OM uint32_t TASKS_STARTTX;                     /*!< (@ 0x00000008) Start UART transmitter                                */
79108     __OM uint32_t TASKS_STOPTX;                      /*!< (@ 0x0000000C) Stop UART transmitter                                 */
79109     __IM uint32_t RESERVED[7];
79110     __OM uint32_t TASKS_FLUSHRX;                     /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer                          */
79111     __IM uint32_t RESERVED1[20];
79112     __IOM uint32_t SUBSCRIBE_STARTRX;                /*!< (@ 0x00000080) Subscribe configuration for task STARTRX              */
79113     __IOM uint32_t SUBSCRIBE_STOPRX;                 /*!< (@ 0x00000084) Subscribe configuration for task STOPRX               */
79114     __IOM uint32_t SUBSCRIBE_STARTTX;                /*!< (@ 0x00000088) Subscribe configuration for task STARTTX              */
79115     __IOM uint32_t SUBSCRIBE_STOPTX;                 /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX               */
79116     __IM uint32_t RESERVED2[7];
79117     __IOM uint32_t SUBSCRIBE_FLUSHRX;                /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX              */
79118     __IM uint32_t RESERVED3[20];
79119     __IOM uint32_t EVENTS_CTS;                       /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send.            */
79120     __IOM uint32_t EVENTS_NCTS;                      /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send.     */
79121     __IOM uint32_t EVENTS_RXDRDY;                    /*!< (@ 0x00000108) Data received in RXD (but potentially not yet
79122                                                                          transferred to Data RAM)*/
79123     __IM uint32_t RESERVED4;
79124     __IOM uint32_t EVENTS_ENDRX;                     /*!< (@ 0x00000110) Receive buffer is filled up                           */
79125     __IM uint32_t RESERVED5[2];
79126     __IOM uint32_t EVENTS_TXDRDY;                    /*!< (@ 0x0000011C) Data sent from TXD                                    */
79127     __IOM uint32_t EVENTS_ENDTX;                     /*!< (@ 0x00000120) Last TX byte transmitted                              */
79128     __IOM uint32_t EVENTS_ERROR;                     /*!< (@ 0x00000124) Error detected                                        */
79129     __IM uint32_t RESERVED6[7];
79130     __IOM uint32_t EVENTS_RXTO;                      /*!< (@ 0x00000144) Receiver timeout                                      */
79131     __IM uint32_t RESERVED7;
79132     __IOM uint32_t EVENTS_RXSTARTED;                 /*!< (@ 0x0000014C) UART receiver has started                             */
79133     __IOM uint32_t EVENTS_TXSTARTED;                 /*!< (@ 0x00000150) UART transmitter has started                          */
79134     __IM uint32_t RESERVED8;
79135     __IOM uint32_t EVENTS_TXSTOPPED;                 /*!< (@ 0x00000158) Transmitter stopped                                   */
79136     __IM uint32_t RESERVED9[6];
79137     __IOM uint32_t EVENTS_RXBUSERROR;                /*!< (@ 0x00000174) This event is generated if an error occurs during the
79138                                                                          bus transfer.*/
79139     __IOM uint32_t EVENTS_TXBUSERROR;                /*!< (@ 0x00000178) This event is generated if an error occurs during the
79140                                                                          bus transfer.*/
79141     __IM uint32_t RESERVED10;
79142     __IOM uint32_t PUBLISH_CTS;                      /*!< (@ 0x00000180) Publish configuration for event CTS                   */
79143     __IOM uint32_t PUBLISH_NCTS;                     /*!< (@ 0x00000184) Publish configuration for event NCTS                  */
79144     __IOM uint32_t PUBLISH_RXDRDY;                   /*!< (@ 0x00000188) Publish configuration for event RXDRDY                */
79145     __IM uint32_t RESERVED11;
79146     __IOM uint32_t PUBLISH_ENDRX;                    /*!< (@ 0x00000190) Publish configuration for event ENDRX                 */
79147     __IM uint32_t RESERVED12[2];
79148     __IOM uint32_t PUBLISH_TXDRDY;                   /*!< (@ 0x0000019C) Publish configuration for event TXDRDY                */
79149     __IOM uint32_t PUBLISH_ENDTX;                    /*!< (@ 0x000001A0) Publish configuration for event ENDTX                 */
79150     __IOM uint32_t PUBLISH_ERROR;                    /*!< (@ 0x000001A4) Publish configuration for event ERROR                 */
79151     __IM uint32_t RESERVED13[7];
79152     __IOM uint32_t PUBLISH_RXTO;                     /*!< (@ 0x000001C4) Publish configuration for event RXTO                  */
79153     __IM uint32_t RESERVED14;
79154     __IOM uint32_t PUBLISH_RXSTARTED;                /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED             */
79155     __IOM uint32_t PUBLISH_TXSTARTED;                /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED             */
79156     __IM uint32_t RESERVED15;
79157     __IOM uint32_t PUBLISH_TXSTOPPED;                /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED             */
79158     __IM uint32_t RESERVED16[6];
79159     __IOM uint32_t PUBLISH_RXBUSERROR;               /*!< (@ 0x000001F4) Publish configuration for event RXBUSERROR            */
79160     __IOM uint32_t PUBLISH_TXBUSERROR;               /*!< (@ 0x000001F8) Publish configuration for event TXBUSERROR            */
79161     __IM uint32_t RESERVED17;
79162     __IOM uint32_t SHORTS;                           /*!< (@ 0x00000200) Shortcuts between local events and tasks              */
79163     __IM uint32_t RESERVED18[63];
79164     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
79165     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
79166     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
79167     __IM uint32_t RESERVED19[93];
79168     __IOM uint32_t ERRORSRC;                         /*!< (@ 0x00000480) Error source                                          */
79169     __IM uint32_t RESERVED20[31];
79170     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000500) Enable UART                                           */
79171     __IM uint32_t RESERVED21;
79172     __IOM NRF_UARTE_PSEL_Type PSEL;                  /*!< (@ 0x00000508) (unspecified)                                         */
79173     __IM uint32_t RESERVED22[3];
79174     __IOM uint32_t BAUDRATE;                         /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
79175                                                                          selected.*/
79176     __IM uint32_t RESERVED23[3];
79177     __IOM NRF_UARTE_RXD_Type RXD;                    /*!< (@ 0x00000534) RXD EasyDMA channel                                   */
79178     __IM uint32_t RESERVED24;
79179     __IOM NRF_UARTE_TXD_Type TXD;                    /*!< (@ 0x00000544) TXD EasyDMA channel                                   */
79180     __IM uint32_t RESERVED25[7];
79181     __IOM uint32_t CONFIG;                           /*!< (@ 0x0000056C) Configuration of parity and hardware flow control     */
79182     __IM uint32_t RESERVED26[16];
79183     __IOM NRF_UARTE_DMA_Type DMA;                    /*!< (@ 0x000005B0) (unspecified)                                         */
79184   } NRF_UARTE_Type;                                  /*!< Size = 1472 (0x5C0)                                                  */
79185 
79186 /* UARTE_TASKS_STARTRX: Start UART receiver */
79187   #define UARTE_TASKS_STARTRX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STARTRX register.                            */
79188 
79189 /* TASKS_STARTRX @Bit 0 : Start UART receiver */
79190   #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field.                                    */
79191   #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX
79192                                                                             field.*/
79193   #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Min (0x1UL) /*!< Min enumerator value of TASKS_STARTRX field.                      */
79194   #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Max (0x1UL) /*!< Max enumerator value of TASKS_STARTRX field.                      */
79195   #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task                                                  */
79196 
79197 
79198 /* UARTE_TASKS_STOPRX: Stop UART receiver */
79199   #define UARTE_TASKS_STOPRX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPRX register.                              */
79200 
79201 /* TASKS_STOPRX @Bit 0 : Stop UART receiver */
79202   #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL)  /*!< Position of TASKS_STOPRX field.                                      */
79203   #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX
79204                                                                             field.*/
79205   #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPRX field.                         */
79206   #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPRX field.                         */
79207   #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (0x1UL) /*!< Trigger task                                                    */
79208 
79209 
79210 /* UARTE_TASKS_STARTTX: Start UART transmitter */
79211   #define UARTE_TASKS_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STARTTX register.                            */
79212 
79213 /* TASKS_STARTTX @Bit 0 : Start UART transmitter */
79214   #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field.                                    */
79215   #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX
79216                                                                             field.*/
79217   #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STARTTX field.                      */
79218   #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STARTTX field.                      */
79219   #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task                                                  */
79220 
79221 
79222 /* UARTE_TASKS_STOPTX: Stop UART transmitter */
79223   #define UARTE_TASKS_STOPTX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_STOPTX register.                              */
79224 
79225 /* TASKS_STOPTX @Bit 0 : Stop UART transmitter */
79226   #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL)  /*!< Position of TASKS_STOPTX field.                                      */
79227   #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX
79228                                                                             field.*/
79229   #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Min (0x1UL) /*!< Min enumerator value of TASKS_STOPTX field.                         */
79230   #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Max (0x1UL) /*!< Max enumerator value of TASKS_STOPTX field.                         */
79231   #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task                                                    */
79232 
79233 
79234 /* UARTE_TASKS_FLUSHRX: Flush RX FIFO into RX buffer */
79235   #define UARTE_TASKS_FLUSHRX_ResetValue (0x00000000UL) /*!< Reset value of TASKS_FLUSHRX register.                            */
79236 
79237 /* TASKS_FLUSHRX @Bit 0 : Flush RX FIFO into RX buffer */
79238   #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field.                                    */
79239   #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX
79240                                                                             field.*/
79241   #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Min (0x1UL) /*!< Min enumerator value of TASKS_FLUSHRX field.                      */
79242   #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Max (0x1UL) /*!< Max enumerator value of TASKS_FLUSHRX field.                      */
79243   #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task                                                  */
79244 
79245 
79246 /* UARTE_SUBSCRIBE_STARTRX: Subscribe configuration for task STARTRX */
79247   #define UARTE_SUBSCRIBE_STARTRX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STARTRX register.                    */
79248 
79249 /* CHIDX @Bits 0..7 : DPPI channel that task STARTRX will subscribe to */
79250   #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
79251   #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
79252   #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
79253   #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
79254 
79255 /* EN @Bit 31 : (unspecified) */
79256   #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL)      /*!< Position of EN field.                                                */
79257   #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field.                  */
79258   #define UARTE_SUBSCRIBE_STARTRX_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
79259   #define UARTE_SUBSCRIBE_STARTRX_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
79260   #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
79261   #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
79262 
79263 
79264 /* UARTE_SUBSCRIBE_STOPRX: Subscribe configuration for task STOPRX */
79265   #define UARTE_SUBSCRIBE_STOPRX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOPRX register.                      */
79266 
79267 /* CHIDX @Bits 0..7 : DPPI channel that task STOPRX will subscribe to */
79268   #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
79269   #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
79270   #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
79271   #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
79272 
79273 /* EN @Bit 31 : (unspecified) */
79274   #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL)       /*!< Position of EN field.                                                */
79275   #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field.                    */
79276   #define UARTE_SUBSCRIBE_STOPRX_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
79277   #define UARTE_SUBSCRIBE_STOPRX_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
79278   #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
79279   #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
79280 
79281 
79282 /* UARTE_SUBSCRIBE_STARTTX: Subscribe configuration for task STARTTX */
79283   #define UARTE_SUBSCRIBE_STARTTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STARTTX register.                    */
79284 
79285 /* CHIDX @Bits 0..7 : DPPI channel that task STARTTX will subscribe to */
79286   #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
79287   #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
79288   #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
79289   #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
79290 
79291 /* EN @Bit 31 : (unspecified) */
79292   #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL)      /*!< Position of EN field.                                                */
79293   #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field.                  */
79294   #define UARTE_SUBSCRIBE_STARTTX_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
79295   #define UARTE_SUBSCRIBE_STARTTX_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
79296   #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
79297   #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
79298 
79299 
79300 /* UARTE_SUBSCRIBE_STOPTX: Subscribe configuration for task STOPTX */
79301   #define UARTE_SUBSCRIBE_STOPTX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOPTX register.                      */
79302 
79303 /* CHIDX @Bits 0..7 : DPPI channel that task STOPTX will subscribe to */
79304   #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL)     /*!< Position of CHIDX field.                                             */
79305   #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.          */
79306   #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Min (0x0UL)   /*!< Min value of CHIDX field.                                            */
79307   #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Max (0xFFUL)  /*!< Max size of CHIDX field.                                             */
79308 
79309 /* EN @Bit 31 : (unspecified) */
79310   #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL)       /*!< Position of EN field.                                                */
79311   #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field.                    */
79312   #define UARTE_SUBSCRIBE_STOPTX_EN_Min (0x0UL)      /*!< Min enumerator value of EN field.                                    */
79313   #define UARTE_SUBSCRIBE_STOPTX_EN_Max (0x1UL)      /*!< Max enumerator value of EN field.                                    */
79314   #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0x0UL) /*!< Disable subscription                                                 */
79315   #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (0x1UL)  /*!< Enable subscription                                                  */
79316 
79317 
79318 /* UARTE_SUBSCRIBE_FLUSHRX: Subscribe configuration for task FLUSHRX */
79319   #define UARTE_SUBSCRIBE_FLUSHRX_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_FLUSHRX register.                    */
79320 
79321 /* CHIDX @Bits 0..7 : DPPI channel that task FLUSHRX will subscribe to */
79322   #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
79323   #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
79324   #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
79325   #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
79326 
79327 /* EN @Bit 31 : (unspecified) */
79328   #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL)      /*!< Position of EN field.                                                */
79329   #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field.                  */
79330   #define UARTE_SUBSCRIBE_FLUSHRX_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
79331   #define UARTE_SUBSCRIBE_FLUSHRX_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
79332   #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0x0UL) /*!< Disable subscription                                                */
79333   #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (0x1UL) /*!< Enable subscription                                                  */
79334 
79335 
79336 /* UARTE_EVENTS_CTS: CTS is activated (set low). Clear To Send. */
79337   #define UARTE_EVENTS_CTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CTS register.                                  */
79338 
79339 /* EVENTS_CTS @Bit 0 : CTS is activated (set low). Clear To Send. */
79340   #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL)      /*!< Position of EVENTS_CTS field.                                        */
79341   #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field.        */
79342   #define UARTE_EVENTS_CTS_EVENTS_CTS_Min (0x0UL)    /*!< Min enumerator value of EVENTS_CTS field.                            */
79343   #define UARTE_EVENTS_CTS_EVENTS_CTS_Max (0x1UL)    /*!< Max enumerator value of EVENTS_CTS field.                            */
79344   #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated                                            */
79345   #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated                                                   */
79346 
79347 
79348 /* UARTE_EVENTS_NCTS: CTS is deactivated (set high). Not Clear To Send. */
79349   #define UARTE_EVENTS_NCTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_NCTS register.                                */
79350 
79351 /* EVENTS_NCTS @Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
79352   #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL)    /*!< Position of EVENTS_NCTS field.                                       */
79353   #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field.   */
79354   #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Min (0x0UL)  /*!< Min enumerator value of EVENTS_NCTS field.                           */
79355   #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Max (0x1UL)  /*!< Max enumerator value of EVENTS_NCTS field.                           */
79356   #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated                                          */
79357   #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated                                                 */
79358 
79359 
79360 /* UARTE_EVENTS_RXDRDY: Data received in RXD (but potentially not yet transferred to Data RAM) */
79361   #define UARTE_EVENTS_RXDRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXDRDY register.                            */
79362 
79363 /* EVENTS_RXDRDY @Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
79364   #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field.                                    */
79365   #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY
79366                                                                             field.*/
79367   #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXDRDY field.                      */
79368   #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXDRDY field.                      */
79369   #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated                                      */
79370   #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated                                             */
79371 
79372 
79373 /* UARTE_EVENTS_ENDRX: Receive buffer is filled up */
79374   #define UARTE_EVENTS_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDRX register.                              */
79375 
79376 /* EVENTS_ENDRX @Bit 0 : Receive buffer is filled up */
79377   #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL)  /*!< Position of EVENTS_ENDRX field.                                      */
79378   #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX
79379                                                                             field.*/
79380   #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDRX field.                         */
79381   #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDRX field.                         */
79382   #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated                                        */
79383   #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated                                               */
79384 
79385 
79386 /* UARTE_EVENTS_TXDRDY: Data sent from TXD */
79387   #define UARTE_EVENTS_TXDRDY_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXDRDY register.                            */
79388 
79389 /* EVENTS_TXDRDY @Bit 0 : Data sent from TXD */
79390   #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field.                                    */
79391   #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY
79392                                                                             field.*/
79393   #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXDRDY field.                      */
79394   #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXDRDY field.                      */
79395   #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated                                      */
79396   #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated                                             */
79397 
79398 
79399 /* UARTE_EVENTS_ENDTX: Last TX byte transmitted */
79400   #define UARTE_EVENTS_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ENDTX register.                              */
79401 
79402 /* EVENTS_ENDTX @Bit 0 : Last TX byte transmitted */
79403   #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL)  /*!< Position of EVENTS_ENDTX field.                                      */
79404   #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX
79405                                                                             field.*/
79406   #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Min (0x0UL) /*!< Min enumerator value of EVENTS_ENDTX field.                         */
79407   #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Max (0x1UL) /*!< Max enumerator value of EVENTS_ENDTX field.                         */
79408   #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated                                        */
79409   #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated                                               */
79410 
79411 
79412 /* UARTE_EVENTS_ERROR: Error detected */
79413   #define UARTE_EVENTS_ERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERROR register.                              */
79414 
79415 /* EVENTS_ERROR @Bit 0 : Error detected */
79416   #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL)  /*!< Position of EVENTS_ERROR field.                                      */
79417   #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR
79418                                                                             field.*/
79419   #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERROR field.                         */
79420   #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERROR field.                         */
79421   #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated                                        */
79422   #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated                                               */
79423 
79424 
79425 /* UARTE_EVENTS_RXTO: Receiver timeout */
79426   #define UARTE_EVENTS_RXTO_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXTO register.                                */
79427 
79428 /* EVENTS_RXTO @Bit 0 : Receiver timeout */
79429   #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL)    /*!< Position of EVENTS_RXTO field.                                       */
79430   #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field.   */
79431   #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Min (0x0UL)  /*!< Min enumerator value of EVENTS_RXTO field.                           */
79432   #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Max (0x1UL)  /*!< Max enumerator value of EVENTS_RXTO field.                           */
79433   #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated                                          */
79434   #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated                                                 */
79435 
79436 
79437 /* UARTE_EVENTS_RXSTARTED: UART receiver has started */
79438   #define UARTE_EVENTS_RXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXSTARTED register.                      */
79439 
79440 /* EVENTS_RXSTARTED @Bit 0 : UART receiver has started */
79441   #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field.                           */
79442   #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of
79443                                                                             EVENTS_RXSTARTED field.*/
79444   #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXSTARTED field.             */
79445   #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXSTARTED field.             */
79446   #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                */
79447   #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated                                       */
79448 
79449 
79450 /* UARTE_EVENTS_TXSTARTED: UART transmitter has started */
79451   #define UARTE_EVENTS_TXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXSTARTED register.                      */
79452 
79453 /* EVENTS_TXSTARTED @Bit 0 : UART transmitter has started */
79454   #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field.                           */
79455   #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of
79456                                                                             EVENTS_TXSTARTED field.*/
79457   #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXSTARTED field.             */
79458   #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXSTARTED field.             */
79459   #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated                                */
79460   #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated                                       */
79461 
79462 
79463 /* UARTE_EVENTS_TXSTOPPED: Transmitter stopped */
79464   #define UARTE_EVENTS_TXSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXSTOPPED register.                      */
79465 
79466 /* EVENTS_TXSTOPPED @Bit 0 : Transmitter stopped */
79467   #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field.                           */
79468   #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of
79469                                                                             EVENTS_TXSTOPPED field.*/
79470   #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXSTOPPED field.             */
79471   #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXSTOPPED field.             */
79472   #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated                                */
79473   #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated                                       */
79474 
79475 
79476 /* UARTE_EVENTS_RXBUSERROR: This event is generated if an error occurs during the bus transfer. */
79477   #define UARTE_EVENTS_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXBUSERROR register.                    */
79478 
79479 /* EVENTS_RXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
79480   #define UARTE_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos (0UL) /*!< Position of EVENTS_RXBUSERROR field.                        */
79481   #define UARTE_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Msk (0x1UL << UARTE_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Pos) /*!< Bit mask
79482                                                                             of EVENTS_RXBUSERROR field.*/
79483   #define UARTE_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXBUSERROR field.          */
79484   #define UARTE_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXBUSERROR field.          */
79485   #define UARTE_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                              */
79486   #define UARTE_EVENTS_RXBUSERROR_EVENTS_RXBUSERROR_Generated (0x1UL) /*!< Event generated                                     */
79487 
79488 
79489 /* UARTE_EVENTS_TXBUSERROR: This event is generated if an error occurs during the bus transfer. */
79490   #define UARTE_EVENTS_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXBUSERROR register.                    */
79491 
79492 /* EVENTS_TXBUSERROR @Bit 0 : This event is generated if an error occurs during the bus transfer. */
79493   #define UARTE_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos (0UL) /*!< Position of EVENTS_TXBUSERROR field.                        */
79494   #define UARTE_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Msk (0x1UL << UARTE_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Pos) /*!< Bit mask
79495                                                                             of EVENTS_TXBUSERROR field.*/
79496   #define UARTE_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXBUSERROR field.          */
79497   #define UARTE_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXBUSERROR field.          */
79498   #define UARTE_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_NotGenerated (0x0UL) /*!< Event not generated                              */
79499   #define UARTE_EVENTS_TXBUSERROR_EVENTS_TXBUSERROR_Generated (0x1UL) /*!< Event generated                                     */
79500 
79501 
79502 /* UARTE_PUBLISH_CTS: Publish configuration for event CTS */
79503   #define UARTE_PUBLISH_CTS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_CTS register.                                */
79504 
79505 /* CHIDX @Bits 0..7 : DPPI channel that event CTS will publish to */
79506   #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL)          /*!< Position of CHIDX field.                                             */
79507   #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field.                    */
79508   #define UARTE_PUBLISH_CTS_CHIDX_Min (0x0UL)        /*!< Min value of CHIDX field.                                            */
79509   #define UARTE_PUBLISH_CTS_CHIDX_Max (0xFFUL)       /*!< Max size of CHIDX field.                                             */
79510 
79511 /* EN @Bit 31 : (unspecified) */
79512   #define UARTE_PUBLISH_CTS_EN_Pos (31UL)            /*!< Position of EN field.                                                */
79513   #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field.                              */
79514   #define UARTE_PUBLISH_CTS_EN_Min (0x0UL)           /*!< Min enumerator value of EN field.                                    */
79515   #define UARTE_PUBLISH_CTS_EN_Max (0x1UL)           /*!< Max enumerator value of EN field.                                    */
79516   #define UARTE_PUBLISH_CTS_EN_Disabled (0x0UL)      /*!< Disable publishing                                                   */
79517   #define UARTE_PUBLISH_CTS_EN_Enabled (0x1UL)       /*!< Enable publishing                                                    */
79518 
79519 
79520 /* UARTE_PUBLISH_NCTS: Publish configuration for event NCTS */
79521   #define UARTE_PUBLISH_NCTS_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_NCTS register.                              */
79522 
79523 /* CHIDX @Bits 0..7 : DPPI channel that event NCTS will publish to */
79524   #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
79525   #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
79526   #define UARTE_PUBLISH_NCTS_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
79527   #define UARTE_PUBLISH_NCTS_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
79528 
79529 /* EN @Bit 31 : (unspecified) */
79530   #define UARTE_PUBLISH_NCTS_EN_Pos (31UL)           /*!< Position of EN field.                                                */
79531   #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field.                            */
79532   #define UARTE_PUBLISH_NCTS_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
79533   #define UARTE_PUBLISH_NCTS_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
79534   #define UARTE_PUBLISH_NCTS_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
79535   #define UARTE_PUBLISH_NCTS_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
79536 
79537 
79538 /* UARTE_PUBLISH_RXDRDY: Publish configuration for event RXDRDY */
79539   #define UARTE_PUBLISH_RXDRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXDRDY register.                          */
79540 
79541 /* CHIDX @Bits 0..7 : DPPI channel that event RXDRDY will publish to */
79542   #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
79543   #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
79544   #define UARTE_PUBLISH_RXDRDY_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
79545   #define UARTE_PUBLISH_RXDRDY_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
79546 
79547 /* EN @Bit 31 : (unspecified) */
79548   #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL)         /*!< Position of EN field.                                                */
79549   #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field.                        */
79550   #define UARTE_PUBLISH_RXDRDY_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
79551   #define UARTE_PUBLISH_RXDRDY_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
79552   #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
79553   #define UARTE_PUBLISH_RXDRDY_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
79554 
79555 
79556 /* UARTE_PUBLISH_ENDRX: Publish configuration for event ENDRX */
79557   #define UARTE_PUBLISH_ENDRX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDRX register.                            */
79558 
79559 /* CHIDX @Bits 0..7 : DPPI channel that event ENDRX will publish to */
79560   #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
79561   #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
79562   #define UARTE_PUBLISH_ENDRX_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
79563   #define UARTE_PUBLISH_ENDRX_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
79564 
79565 /* EN @Bit 31 : (unspecified) */
79566   #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL)          /*!< Position of EN field.                                                */
79567   #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field.                          */
79568   #define UARTE_PUBLISH_ENDRX_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
79569   #define UARTE_PUBLISH_ENDRX_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
79570   #define UARTE_PUBLISH_ENDRX_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
79571   #define UARTE_PUBLISH_ENDRX_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
79572 
79573 
79574 /* UARTE_PUBLISH_TXDRDY: Publish configuration for event TXDRDY */
79575   #define UARTE_PUBLISH_TXDRDY_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXDRDY register.                          */
79576 
79577 /* CHIDX @Bits 0..7 : DPPI channel that event TXDRDY will publish to */
79578   #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL)       /*!< Position of CHIDX field.                                             */
79579   #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field.              */
79580   #define UARTE_PUBLISH_TXDRDY_CHIDX_Min (0x0UL)     /*!< Min value of CHIDX field.                                            */
79581   #define UARTE_PUBLISH_TXDRDY_CHIDX_Max (0xFFUL)    /*!< Max size of CHIDX field.                                             */
79582 
79583 /* EN @Bit 31 : (unspecified) */
79584   #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL)         /*!< Position of EN field.                                                */
79585   #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field.                        */
79586   #define UARTE_PUBLISH_TXDRDY_EN_Min (0x0UL)        /*!< Min enumerator value of EN field.                                    */
79587   #define UARTE_PUBLISH_TXDRDY_EN_Max (0x1UL)        /*!< Max enumerator value of EN field.                                    */
79588   #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0x0UL)   /*!< Disable publishing                                                   */
79589   #define UARTE_PUBLISH_TXDRDY_EN_Enabled (0x1UL)    /*!< Enable publishing                                                    */
79590 
79591 
79592 /* UARTE_PUBLISH_ENDTX: Publish configuration for event ENDTX */
79593   #define UARTE_PUBLISH_ENDTX_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ENDTX register.                            */
79594 
79595 /* CHIDX @Bits 0..7 : DPPI channel that event ENDTX will publish to */
79596   #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
79597   #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
79598   #define UARTE_PUBLISH_ENDTX_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
79599   #define UARTE_PUBLISH_ENDTX_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
79600 
79601 /* EN @Bit 31 : (unspecified) */
79602   #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL)          /*!< Position of EN field.                                                */
79603   #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field.                          */
79604   #define UARTE_PUBLISH_ENDTX_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
79605   #define UARTE_PUBLISH_ENDTX_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
79606   #define UARTE_PUBLISH_ENDTX_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
79607   #define UARTE_PUBLISH_ENDTX_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
79608 
79609 
79610 /* UARTE_PUBLISH_ERROR: Publish configuration for event ERROR */
79611   #define UARTE_PUBLISH_ERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERROR register.                            */
79612 
79613 /* CHIDX @Bits 0..7 : DPPI channel that event ERROR will publish to */
79614   #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
79615   #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
79616   #define UARTE_PUBLISH_ERROR_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
79617   #define UARTE_PUBLISH_ERROR_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
79618 
79619 /* EN @Bit 31 : (unspecified) */
79620   #define UARTE_PUBLISH_ERROR_EN_Pos (31UL)          /*!< Position of EN field.                                                */
79621   #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field.                          */
79622   #define UARTE_PUBLISH_ERROR_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
79623   #define UARTE_PUBLISH_ERROR_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
79624   #define UARTE_PUBLISH_ERROR_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
79625   #define UARTE_PUBLISH_ERROR_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
79626 
79627 
79628 /* UARTE_PUBLISH_RXTO: Publish configuration for event RXTO */
79629   #define UARTE_PUBLISH_RXTO_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXTO register.                              */
79630 
79631 /* CHIDX @Bits 0..7 : DPPI channel that event RXTO will publish to */
79632   #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
79633   #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
79634   #define UARTE_PUBLISH_RXTO_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
79635   #define UARTE_PUBLISH_RXTO_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
79636 
79637 /* EN @Bit 31 : (unspecified) */
79638   #define UARTE_PUBLISH_RXTO_EN_Pos (31UL)           /*!< Position of EN field.                                                */
79639   #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field.                            */
79640   #define UARTE_PUBLISH_RXTO_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
79641   #define UARTE_PUBLISH_RXTO_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
79642   #define UARTE_PUBLISH_RXTO_EN_Disabled (0x0UL)     /*!< Disable publishing                                                   */
79643   #define UARTE_PUBLISH_RXTO_EN_Enabled (0x1UL)      /*!< Enable publishing                                                    */
79644 
79645 
79646 /* UARTE_PUBLISH_RXSTARTED: Publish configuration for event RXSTARTED */
79647   #define UARTE_PUBLISH_RXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXSTARTED register.                    */
79648 
79649 /* CHIDX @Bits 0..7 : DPPI channel that event RXSTARTED will publish to */
79650   #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
79651   #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
79652   #define UARTE_PUBLISH_RXSTARTED_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
79653   #define UARTE_PUBLISH_RXSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
79654 
79655 /* EN @Bit 31 : (unspecified) */
79656   #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL)      /*!< Position of EN field.                                                */
79657   #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field.                  */
79658   #define UARTE_PUBLISH_RXSTARTED_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
79659   #define UARTE_PUBLISH_RXSTARTED_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
79660   #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
79661   #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
79662 
79663 
79664 /* UARTE_PUBLISH_TXSTARTED: Publish configuration for event TXSTARTED */
79665   #define UARTE_PUBLISH_TXSTARTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXSTARTED register.                    */
79666 
79667 /* CHIDX @Bits 0..7 : DPPI channel that event TXSTARTED will publish to */
79668   #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
79669   #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
79670   #define UARTE_PUBLISH_TXSTARTED_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
79671   #define UARTE_PUBLISH_TXSTARTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
79672 
79673 /* EN @Bit 31 : (unspecified) */
79674   #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL)      /*!< Position of EN field.                                                */
79675   #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field.                  */
79676   #define UARTE_PUBLISH_TXSTARTED_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
79677   #define UARTE_PUBLISH_TXSTARTED_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
79678   #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
79679   #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
79680 
79681 
79682 /* UARTE_PUBLISH_TXSTOPPED: Publish configuration for event TXSTOPPED */
79683   #define UARTE_PUBLISH_TXSTOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXSTOPPED register.                    */
79684 
79685 /* CHIDX @Bits 0..7 : DPPI channel that event TXSTOPPED will publish to */
79686   #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL)    /*!< Position of CHIDX field.                                             */
79687   #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.        */
79688   #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Min (0x0UL)  /*!< Min value of CHIDX field.                                            */
79689   #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                             */
79690 
79691 /* EN @Bit 31 : (unspecified) */
79692   #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL)      /*!< Position of EN field.                                                */
79693   #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field.                  */
79694   #define UARTE_PUBLISH_TXSTOPPED_EN_Min (0x0UL)     /*!< Min enumerator value of EN field.                                    */
79695   #define UARTE_PUBLISH_TXSTOPPED_EN_Max (0x1UL)     /*!< Max enumerator value of EN field.                                    */
79696   #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing                                                  */
79697   #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing                                                    */
79698 
79699 
79700 /* UARTE_PUBLISH_RXBUSERROR: Publish configuration for event RXBUSERROR */
79701   #define UARTE_PUBLISH_RXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXBUSERROR register.                  */
79702 
79703 /* CHIDX @Bits 0..7 : DPPI channel that event RXBUSERROR will publish to */
79704   #define UARTE_PUBLISH_RXBUSERROR_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
79705   #define UARTE_PUBLISH_RXBUSERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
79706   #define UARTE_PUBLISH_RXBUSERROR_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
79707   #define UARTE_PUBLISH_RXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
79708 
79709 /* EN @Bit 31 : (unspecified) */
79710   #define UARTE_PUBLISH_RXBUSERROR_EN_Pos (31UL)     /*!< Position of EN field.                                                */
79711   #define UARTE_PUBLISH_RXBUSERROR_EN_Msk (0x1UL << UARTE_PUBLISH_RXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                */
79712   #define UARTE_PUBLISH_RXBUSERROR_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
79713   #define UARTE_PUBLISH_RXBUSERROR_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
79714   #define UARTE_PUBLISH_RXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
79715   #define UARTE_PUBLISH_RXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */
79716 
79717 
79718 /* UARTE_PUBLISH_TXBUSERROR: Publish configuration for event TXBUSERROR */
79719   #define UARTE_PUBLISH_TXBUSERROR_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXBUSERROR register.                  */
79720 
79721 /* CHIDX @Bits 0..7 : DPPI channel that event TXBUSERROR will publish to */
79722   #define UARTE_PUBLISH_TXBUSERROR_CHIDX_Pos (0UL)   /*!< Position of CHIDX field.                                             */
79723   #define UARTE_PUBLISH_TXBUSERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXBUSERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field.      */
79724   #define UARTE_PUBLISH_TXBUSERROR_CHIDX_Min (0x0UL) /*!< Min value of CHIDX field.                                            */
79725   #define UARTE_PUBLISH_TXBUSERROR_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field.                                            */
79726 
79727 /* EN @Bit 31 : (unspecified) */
79728   #define UARTE_PUBLISH_TXBUSERROR_EN_Pos (31UL)     /*!< Position of EN field.                                                */
79729   #define UARTE_PUBLISH_TXBUSERROR_EN_Msk (0x1UL << UARTE_PUBLISH_TXBUSERROR_EN_Pos) /*!< Bit mask of EN field.                */
79730   #define UARTE_PUBLISH_TXBUSERROR_EN_Min (0x0UL)    /*!< Min enumerator value of EN field.                                    */
79731   #define UARTE_PUBLISH_TXBUSERROR_EN_Max (0x1UL)    /*!< Max enumerator value of EN field.                                    */
79732   #define UARTE_PUBLISH_TXBUSERROR_EN_Disabled (0x0UL) /*!< Disable publishing                                                 */
79733   #define UARTE_PUBLISH_TXBUSERROR_EN_Enabled (0x1UL) /*!< Enable publishing                                                   */
79734 
79735 
79736 /* UARTE_SHORTS: Shortcuts between local events and tasks */
79737   #define UARTE_SHORTS_ResetValue (0x00000000UL)     /*!< Reset value of SHORTS register.                                      */
79738 
79739 /* ENDRX_STARTRX @Bit 5 : Shortcut between event ENDRX and task STARTRX */
79740   #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL)       /*!< Position of ENDRX_STARTRX field.                                     */
79741   #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field.       */
79742   #define UARTE_SHORTS_ENDRX_STARTRX_Min (0x0UL)     /*!< Min enumerator value of ENDRX_STARTRX field.                         */
79743   #define UARTE_SHORTS_ENDRX_STARTRX_Max (0x1UL)     /*!< Max enumerator value of ENDRX_STARTRX field.                         */
79744   #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut                                                    */
79745   #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut                                                      */
79746 
79747 /* ENDRX_STOPRX @Bit 6 : Shortcut between event ENDRX and task STOPRX */
79748   #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL)        /*!< Position of ENDRX_STOPRX field.                                      */
79749   #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field.          */
79750   #define UARTE_SHORTS_ENDRX_STOPRX_Min (0x0UL)      /*!< Min enumerator value of ENDRX_STOPRX field.                          */
79751   #define UARTE_SHORTS_ENDRX_STOPRX_Max (0x1UL)      /*!< Max enumerator value of ENDRX_STOPRX field.                          */
79752   #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0x0UL) /*!< Disable shortcut                                                     */
79753   #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (0x1UL)  /*!< Enable shortcut                                                      */
79754 
79755 
79756 /* UARTE_INTEN: Enable or disable interrupt */
79757   #define UARTE_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */
79758 
79759 /* CTS @Bit 0 : Enable or disable interrupt for event CTS */
79760   #define UARTE_INTEN_CTS_Pos (0UL)                  /*!< Position of CTS field.                                               */
79761   #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field.                                       */
79762   #define UARTE_INTEN_CTS_Min (0x0UL)                /*!< Min enumerator value of CTS field.                                   */
79763   #define UARTE_INTEN_CTS_Max (0x1UL)                /*!< Max enumerator value of CTS field.                                   */
79764   #define UARTE_INTEN_CTS_Disabled (0x0UL)           /*!< Disable                                                              */
79765   #define UARTE_INTEN_CTS_Enabled (0x1UL)            /*!< Enable                                                               */
79766 
79767 /* NCTS @Bit 1 : Enable or disable interrupt for event NCTS */
79768   #define UARTE_INTEN_NCTS_Pos (1UL)                 /*!< Position of NCTS field.                                              */
79769   #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field.                                    */
79770   #define UARTE_INTEN_NCTS_Min (0x0UL)               /*!< Min enumerator value of NCTS field.                                  */
79771   #define UARTE_INTEN_NCTS_Max (0x1UL)               /*!< Max enumerator value of NCTS field.                                  */
79772   #define UARTE_INTEN_NCTS_Disabled (0x0UL)          /*!< Disable                                                              */
79773   #define UARTE_INTEN_NCTS_Enabled (0x1UL)           /*!< Enable                                                               */
79774 
79775 /* RXDRDY @Bit 2 : Enable or disable interrupt for event RXDRDY */
79776   #define UARTE_INTEN_RXDRDY_Pos (2UL)               /*!< Position of RXDRDY field.                                            */
79777   #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field.                              */
79778   #define UARTE_INTEN_RXDRDY_Min (0x0UL)             /*!< Min enumerator value of RXDRDY field.                                */
79779   #define UARTE_INTEN_RXDRDY_Max (0x1UL)             /*!< Max enumerator value of RXDRDY field.                                */
79780   #define UARTE_INTEN_RXDRDY_Disabled (0x0UL)        /*!< Disable                                                              */
79781   #define UARTE_INTEN_RXDRDY_Enabled (0x1UL)         /*!< Enable                                                               */
79782 
79783 /* ENDRX @Bit 4 : Enable or disable interrupt for event ENDRX */
79784   #define UARTE_INTEN_ENDRX_Pos (4UL)                /*!< Position of ENDRX field.                                             */
79785   #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field.                                 */
79786   #define UARTE_INTEN_ENDRX_Min (0x0UL)              /*!< Min enumerator value of ENDRX field.                                 */
79787   #define UARTE_INTEN_ENDRX_Max (0x1UL)              /*!< Max enumerator value of ENDRX field.                                 */
79788   #define UARTE_INTEN_ENDRX_Disabled (0x0UL)         /*!< Disable                                                              */
79789   #define UARTE_INTEN_ENDRX_Enabled (0x1UL)          /*!< Enable                                                               */
79790 
79791 /* TXDRDY @Bit 7 : Enable or disable interrupt for event TXDRDY */
79792   #define UARTE_INTEN_TXDRDY_Pos (7UL)               /*!< Position of TXDRDY field.                                            */
79793   #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field.                              */
79794   #define UARTE_INTEN_TXDRDY_Min (0x0UL)             /*!< Min enumerator value of TXDRDY field.                                */
79795   #define UARTE_INTEN_TXDRDY_Max (0x1UL)             /*!< Max enumerator value of TXDRDY field.                                */
79796   #define UARTE_INTEN_TXDRDY_Disabled (0x0UL)        /*!< Disable                                                              */
79797   #define UARTE_INTEN_TXDRDY_Enabled (0x1UL)         /*!< Enable                                                               */
79798 
79799 /* ENDTX @Bit 8 : Enable or disable interrupt for event ENDTX */
79800   #define UARTE_INTEN_ENDTX_Pos (8UL)                /*!< Position of ENDTX field.                                             */
79801   #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field.                                 */
79802   #define UARTE_INTEN_ENDTX_Min (0x0UL)              /*!< Min enumerator value of ENDTX field.                                 */
79803   #define UARTE_INTEN_ENDTX_Max (0x1UL)              /*!< Max enumerator value of ENDTX field.                                 */
79804   #define UARTE_INTEN_ENDTX_Disabled (0x0UL)         /*!< Disable                                                              */
79805   #define UARTE_INTEN_ENDTX_Enabled (0x1UL)          /*!< Enable                                                               */
79806 
79807 /* ERROR @Bit 9 : Enable or disable interrupt for event ERROR */
79808   #define UARTE_INTEN_ERROR_Pos (9UL)                /*!< Position of ERROR field.                                             */
79809   #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field.                                 */
79810   #define UARTE_INTEN_ERROR_Min (0x0UL)              /*!< Min enumerator value of ERROR field.                                 */
79811   #define UARTE_INTEN_ERROR_Max (0x1UL)              /*!< Max enumerator value of ERROR field.                                 */
79812   #define UARTE_INTEN_ERROR_Disabled (0x0UL)         /*!< Disable                                                              */
79813   #define UARTE_INTEN_ERROR_Enabled (0x1UL)          /*!< Enable                                                               */
79814 
79815 /* RXTO @Bit 17 : Enable or disable interrupt for event RXTO */
79816   #define UARTE_INTEN_RXTO_Pos (17UL)                /*!< Position of RXTO field.                                              */
79817   #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field.                                    */
79818   #define UARTE_INTEN_RXTO_Min (0x0UL)               /*!< Min enumerator value of RXTO field.                                  */
79819   #define UARTE_INTEN_RXTO_Max (0x1UL)               /*!< Max enumerator value of RXTO field.                                  */
79820   #define UARTE_INTEN_RXTO_Disabled (0x0UL)          /*!< Disable                                                              */
79821   #define UARTE_INTEN_RXTO_Enabled (0x1UL)           /*!< Enable                                                               */
79822 
79823 /* RXSTARTED @Bit 19 : Enable or disable interrupt for event RXSTARTED */
79824   #define UARTE_INTEN_RXSTARTED_Pos (19UL)           /*!< Position of RXSTARTED field.                                         */
79825   #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.                     */
79826   #define UARTE_INTEN_RXSTARTED_Min (0x0UL)          /*!< Min enumerator value of RXSTARTED field.                             */
79827   #define UARTE_INTEN_RXSTARTED_Max (0x1UL)          /*!< Max enumerator value of RXSTARTED field.                             */
79828   #define UARTE_INTEN_RXSTARTED_Disabled (0x0UL)     /*!< Disable                                                              */
79829   #define UARTE_INTEN_RXSTARTED_Enabled (0x1UL)      /*!< Enable                                                               */
79830 
79831 /* TXSTARTED @Bit 20 : Enable or disable interrupt for event TXSTARTED */
79832   #define UARTE_INTEN_TXSTARTED_Pos (20UL)           /*!< Position of TXSTARTED field.                                         */
79833   #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.                     */
79834   #define UARTE_INTEN_TXSTARTED_Min (0x0UL)          /*!< Min enumerator value of TXSTARTED field.                             */
79835   #define UARTE_INTEN_TXSTARTED_Max (0x1UL)          /*!< Max enumerator value of TXSTARTED field.                             */
79836   #define UARTE_INTEN_TXSTARTED_Disabled (0x0UL)     /*!< Disable                                                              */
79837   #define UARTE_INTEN_TXSTARTED_Enabled (0x1UL)      /*!< Enable                                                               */
79838 
79839 /* TXSTOPPED @Bit 22 : Enable or disable interrupt for event TXSTOPPED */
79840   #define UARTE_INTEN_TXSTOPPED_Pos (22UL)           /*!< Position of TXSTOPPED field.                                         */
79841   #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field.                     */
79842   #define UARTE_INTEN_TXSTOPPED_Min (0x0UL)          /*!< Min enumerator value of TXSTOPPED field.                             */
79843   #define UARTE_INTEN_TXSTOPPED_Max (0x1UL)          /*!< Max enumerator value of TXSTOPPED field.                             */
79844   #define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL)     /*!< Disable                                                              */
79845   #define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL)      /*!< Enable                                                               */
79846 
79847 /* RXBUSERROR @Bit 29 : Enable or disable interrupt for event RXBUSERROR */
79848   #define UARTE_INTEN_RXBUSERROR_Pos (29UL)          /*!< Position of RXBUSERROR field.                                        */
79849   #define UARTE_INTEN_RXBUSERROR_Msk (0x1UL << UARTE_INTEN_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.                  */
79850   #define UARTE_INTEN_RXBUSERROR_Min (0x0UL)         /*!< Min enumerator value of RXBUSERROR field.                            */
79851   #define UARTE_INTEN_RXBUSERROR_Max (0x1UL)         /*!< Max enumerator value of RXBUSERROR field.                            */
79852   #define UARTE_INTEN_RXBUSERROR_Disabled (0x0UL)    /*!< Disable                                                              */
79853   #define UARTE_INTEN_RXBUSERROR_Enabled (0x1UL)     /*!< Enable                                                               */
79854 
79855 /* TXBUSERROR @Bit 30 : Enable or disable interrupt for event TXBUSERROR */
79856   #define UARTE_INTEN_TXBUSERROR_Pos (30UL)          /*!< Position of TXBUSERROR field.                                        */
79857   #define UARTE_INTEN_TXBUSERROR_Msk (0x1UL << UARTE_INTEN_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.                  */
79858   #define UARTE_INTEN_TXBUSERROR_Min (0x0UL)         /*!< Min enumerator value of TXBUSERROR field.                            */
79859   #define UARTE_INTEN_TXBUSERROR_Max (0x1UL)         /*!< Max enumerator value of TXBUSERROR field.                            */
79860   #define UARTE_INTEN_TXBUSERROR_Disabled (0x0UL)    /*!< Disable                                                              */
79861   #define UARTE_INTEN_TXBUSERROR_Enabled (0x1UL)     /*!< Enable                                                               */
79862 
79863 
79864 /* UARTE_INTENSET: Enable interrupt */
79865   #define UARTE_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */
79866 
79867 /* CTS @Bit 0 : Write '1' to enable interrupt for event CTS */
79868   #define UARTE_INTENSET_CTS_Pos (0UL)               /*!< Position of CTS field.                                               */
79869   #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field.                                 */
79870   #define UARTE_INTENSET_CTS_Min (0x0UL)             /*!< Min enumerator value of CTS field.                                   */
79871   #define UARTE_INTENSET_CTS_Max (0x1UL)             /*!< Max enumerator value of CTS field.                                   */
79872   #define UARTE_INTENSET_CTS_Set (0x1UL)             /*!< Enable                                                               */
79873   #define UARTE_INTENSET_CTS_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
79874   #define UARTE_INTENSET_CTS_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
79875 
79876 /* NCTS @Bit 1 : Write '1' to enable interrupt for event NCTS */
79877   #define UARTE_INTENSET_NCTS_Pos (1UL)              /*!< Position of NCTS field.                                              */
79878   #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field.                              */
79879   #define UARTE_INTENSET_NCTS_Min (0x0UL)            /*!< Min enumerator value of NCTS field.                                  */
79880   #define UARTE_INTENSET_NCTS_Max (0x1UL)            /*!< Max enumerator value of NCTS field.                                  */
79881   #define UARTE_INTENSET_NCTS_Set (0x1UL)            /*!< Enable                                                               */
79882   #define UARTE_INTENSET_NCTS_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
79883   #define UARTE_INTENSET_NCTS_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
79884 
79885 /* RXDRDY @Bit 2 : Write '1' to enable interrupt for event RXDRDY */
79886   #define UARTE_INTENSET_RXDRDY_Pos (2UL)            /*!< Position of RXDRDY field.                                            */
79887   #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field.                        */
79888   #define UARTE_INTENSET_RXDRDY_Min (0x0UL)          /*!< Min enumerator value of RXDRDY field.                                */
79889   #define UARTE_INTENSET_RXDRDY_Max (0x1UL)          /*!< Max enumerator value of RXDRDY field.                                */
79890   #define UARTE_INTENSET_RXDRDY_Set (0x1UL)          /*!< Enable                                                               */
79891   #define UARTE_INTENSET_RXDRDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
79892   #define UARTE_INTENSET_RXDRDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
79893 
79894 /* ENDRX @Bit 4 : Write '1' to enable interrupt for event ENDRX */
79895   #define UARTE_INTENSET_ENDRX_Pos (4UL)             /*!< Position of ENDRX field.                                             */
79896   #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field.                           */
79897   #define UARTE_INTENSET_ENDRX_Min (0x0UL)           /*!< Min enumerator value of ENDRX field.                                 */
79898   #define UARTE_INTENSET_ENDRX_Max (0x1UL)           /*!< Max enumerator value of ENDRX field.                                 */
79899   #define UARTE_INTENSET_ENDRX_Set (0x1UL)           /*!< Enable                                                               */
79900   #define UARTE_INTENSET_ENDRX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
79901   #define UARTE_INTENSET_ENDRX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
79902 
79903 /* TXDRDY @Bit 7 : Write '1' to enable interrupt for event TXDRDY */
79904   #define UARTE_INTENSET_TXDRDY_Pos (7UL)            /*!< Position of TXDRDY field.                                            */
79905   #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field.                        */
79906   #define UARTE_INTENSET_TXDRDY_Min (0x0UL)          /*!< Min enumerator value of TXDRDY field.                                */
79907   #define UARTE_INTENSET_TXDRDY_Max (0x1UL)          /*!< Max enumerator value of TXDRDY field.                                */
79908   #define UARTE_INTENSET_TXDRDY_Set (0x1UL)          /*!< Enable                                                               */
79909   #define UARTE_INTENSET_TXDRDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
79910   #define UARTE_INTENSET_TXDRDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
79911 
79912 /* ENDTX @Bit 8 : Write '1' to enable interrupt for event ENDTX */
79913   #define UARTE_INTENSET_ENDTX_Pos (8UL)             /*!< Position of ENDTX field.                                             */
79914   #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field.                           */
79915   #define UARTE_INTENSET_ENDTX_Min (0x0UL)           /*!< Min enumerator value of ENDTX field.                                 */
79916   #define UARTE_INTENSET_ENDTX_Max (0x1UL)           /*!< Max enumerator value of ENDTX field.                                 */
79917   #define UARTE_INTENSET_ENDTX_Set (0x1UL)           /*!< Enable                                                               */
79918   #define UARTE_INTENSET_ENDTX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
79919   #define UARTE_INTENSET_ENDTX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
79920 
79921 /* ERROR @Bit 9 : Write '1' to enable interrupt for event ERROR */
79922   #define UARTE_INTENSET_ERROR_Pos (9UL)             /*!< Position of ERROR field.                                             */
79923   #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field.                           */
79924   #define UARTE_INTENSET_ERROR_Min (0x0UL)           /*!< Min enumerator value of ERROR field.                                 */
79925   #define UARTE_INTENSET_ERROR_Max (0x1UL)           /*!< Max enumerator value of ERROR field.                                 */
79926   #define UARTE_INTENSET_ERROR_Set (0x1UL)           /*!< Enable                                                               */
79927   #define UARTE_INTENSET_ERROR_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
79928   #define UARTE_INTENSET_ERROR_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
79929 
79930 /* RXTO @Bit 17 : Write '1' to enable interrupt for event RXTO */
79931   #define UARTE_INTENSET_RXTO_Pos (17UL)             /*!< Position of RXTO field.                                              */
79932   #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field.                              */
79933   #define UARTE_INTENSET_RXTO_Min (0x0UL)            /*!< Min enumerator value of RXTO field.                                  */
79934   #define UARTE_INTENSET_RXTO_Max (0x1UL)            /*!< Max enumerator value of RXTO field.                                  */
79935   #define UARTE_INTENSET_RXTO_Set (0x1UL)            /*!< Enable                                                               */
79936   #define UARTE_INTENSET_RXTO_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
79937   #define UARTE_INTENSET_RXTO_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
79938 
79939 /* RXSTARTED @Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
79940   #define UARTE_INTENSET_RXSTARTED_Pos (19UL)        /*!< Position of RXSTARTED field.                                         */
79941   #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.               */
79942   #define UARTE_INTENSET_RXSTARTED_Min (0x0UL)       /*!< Min enumerator value of RXSTARTED field.                             */
79943   #define UARTE_INTENSET_RXSTARTED_Max (0x1UL)       /*!< Max enumerator value of RXSTARTED field.                             */
79944   #define UARTE_INTENSET_RXSTARTED_Set (0x1UL)       /*!< Enable                                                               */
79945   #define UARTE_INTENSET_RXSTARTED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
79946   #define UARTE_INTENSET_RXSTARTED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
79947 
79948 /* TXSTARTED @Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
79949   #define UARTE_INTENSET_TXSTARTED_Pos (20UL)        /*!< Position of TXSTARTED field.                                         */
79950   #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.               */
79951   #define UARTE_INTENSET_TXSTARTED_Min (0x0UL)       /*!< Min enumerator value of TXSTARTED field.                             */
79952   #define UARTE_INTENSET_TXSTARTED_Max (0x1UL)       /*!< Max enumerator value of TXSTARTED field.                             */
79953   #define UARTE_INTENSET_TXSTARTED_Set (0x1UL)       /*!< Enable                                                               */
79954   #define UARTE_INTENSET_TXSTARTED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
79955   #define UARTE_INTENSET_TXSTARTED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
79956 
79957 /* TXSTOPPED @Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
79958   #define UARTE_INTENSET_TXSTOPPED_Pos (22UL)        /*!< Position of TXSTOPPED field.                                         */
79959   #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field.               */
79960   #define UARTE_INTENSET_TXSTOPPED_Min (0x0UL)       /*!< Min enumerator value of TXSTOPPED field.                             */
79961   #define UARTE_INTENSET_TXSTOPPED_Max (0x1UL)       /*!< Max enumerator value of TXSTOPPED field.                             */
79962   #define UARTE_INTENSET_TXSTOPPED_Set (0x1UL)       /*!< Enable                                                               */
79963   #define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
79964   #define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
79965 
79966 /* RXBUSERROR @Bit 29 : Write '1' to enable interrupt for event RXBUSERROR */
79967   #define UARTE_INTENSET_RXBUSERROR_Pos (29UL)       /*!< Position of RXBUSERROR field.                                        */
79968   #define UARTE_INTENSET_RXBUSERROR_Msk (0x1UL << UARTE_INTENSET_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.            */
79969   #define UARTE_INTENSET_RXBUSERROR_Min (0x0UL)      /*!< Min enumerator value of RXBUSERROR field.                            */
79970   #define UARTE_INTENSET_RXBUSERROR_Max (0x1UL)      /*!< Max enumerator value of RXBUSERROR field.                            */
79971   #define UARTE_INTENSET_RXBUSERROR_Set (0x1UL)      /*!< Enable                                                               */
79972   #define UARTE_INTENSET_RXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
79973   #define UARTE_INTENSET_RXBUSERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
79974 
79975 /* TXBUSERROR @Bit 30 : Write '1' to enable interrupt for event TXBUSERROR */
79976   #define UARTE_INTENSET_TXBUSERROR_Pos (30UL)       /*!< Position of TXBUSERROR field.                                        */
79977   #define UARTE_INTENSET_TXBUSERROR_Msk (0x1UL << UARTE_INTENSET_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.            */
79978   #define UARTE_INTENSET_TXBUSERROR_Min (0x0UL)      /*!< Min enumerator value of TXBUSERROR field.                            */
79979   #define UARTE_INTENSET_TXBUSERROR_Max (0x1UL)      /*!< Max enumerator value of TXBUSERROR field.                            */
79980   #define UARTE_INTENSET_TXBUSERROR_Set (0x1UL)      /*!< Enable                                                               */
79981   #define UARTE_INTENSET_TXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
79982   #define UARTE_INTENSET_TXBUSERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
79983 
79984 
79985 /* UARTE_INTENCLR: Disable interrupt */
79986   #define UARTE_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */
79987 
79988 /* CTS @Bit 0 : Write '1' to disable interrupt for event CTS */
79989   #define UARTE_INTENCLR_CTS_Pos (0UL)               /*!< Position of CTS field.                                               */
79990   #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field.                                 */
79991   #define UARTE_INTENCLR_CTS_Min (0x0UL)             /*!< Min enumerator value of CTS field.                                   */
79992   #define UARTE_INTENCLR_CTS_Max (0x1UL)             /*!< Max enumerator value of CTS field.                                   */
79993   #define UARTE_INTENCLR_CTS_Clear (0x1UL)           /*!< Disable                                                              */
79994   #define UARTE_INTENCLR_CTS_Disabled (0x0UL)        /*!< Read: Disabled                                                       */
79995   #define UARTE_INTENCLR_CTS_Enabled (0x1UL)         /*!< Read: Enabled                                                        */
79996 
79997 /* NCTS @Bit 1 : Write '1' to disable interrupt for event NCTS */
79998   #define UARTE_INTENCLR_NCTS_Pos (1UL)              /*!< Position of NCTS field.                                              */
79999   #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field.                              */
80000   #define UARTE_INTENCLR_NCTS_Min (0x0UL)            /*!< Min enumerator value of NCTS field.                                  */
80001   #define UARTE_INTENCLR_NCTS_Max (0x1UL)            /*!< Max enumerator value of NCTS field.                                  */
80002   #define UARTE_INTENCLR_NCTS_Clear (0x1UL)          /*!< Disable                                                              */
80003   #define UARTE_INTENCLR_NCTS_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
80004   #define UARTE_INTENCLR_NCTS_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
80005 
80006 /* RXDRDY @Bit 2 : Write '1' to disable interrupt for event RXDRDY */
80007   #define UARTE_INTENCLR_RXDRDY_Pos (2UL)            /*!< Position of RXDRDY field.                                            */
80008   #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field.                        */
80009   #define UARTE_INTENCLR_RXDRDY_Min (0x0UL)          /*!< Min enumerator value of RXDRDY field.                                */
80010   #define UARTE_INTENCLR_RXDRDY_Max (0x1UL)          /*!< Max enumerator value of RXDRDY field.                                */
80011   #define UARTE_INTENCLR_RXDRDY_Clear (0x1UL)        /*!< Disable                                                              */
80012   #define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
80013   #define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
80014 
80015 /* ENDRX @Bit 4 : Write '1' to disable interrupt for event ENDRX */
80016   #define UARTE_INTENCLR_ENDRX_Pos (4UL)             /*!< Position of ENDRX field.                                             */
80017   #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field.                           */
80018   #define UARTE_INTENCLR_ENDRX_Min (0x0UL)           /*!< Min enumerator value of ENDRX field.                                 */
80019   #define UARTE_INTENCLR_ENDRX_Max (0x1UL)           /*!< Max enumerator value of ENDRX field.                                 */
80020   #define UARTE_INTENCLR_ENDRX_Clear (0x1UL)         /*!< Disable                                                              */
80021   #define UARTE_INTENCLR_ENDRX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
80022   #define UARTE_INTENCLR_ENDRX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
80023 
80024 /* TXDRDY @Bit 7 : Write '1' to disable interrupt for event TXDRDY */
80025   #define UARTE_INTENCLR_TXDRDY_Pos (7UL)            /*!< Position of TXDRDY field.                                            */
80026   #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field.                        */
80027   #define UARTE_INTENCLR_TXDRDY_Min (0x0UL)          /*!< Min enumerator value of TXDRDY field.                                */
80028   #define UARTE_INTENCLR_TXDRDY_Max (0x1UL)          /*!< Max enumerator value of TXDRDY field.                                */
80029   #define UARTE_INTENCLR_TXDRDY_Clear (0x1UL)        /*!< Disable                                                              */
80030   #define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL)     /*!< Read: Disabled                                                       */
80031   #define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL)      /*!< Read: Enabled                                                        */
80032 
80033 /* ENDTX @Bit 8 : Write '1' to disable interrupt for event ENDTX */
80034   #define UARTE_INTENCLR_ENDTX_Pos (8UL)             /*!< Position of ENDTX field.                                             */
80035   #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field.                           */
80036   #define UARTE_INTENCLR_ENDTX_Min (0x0UL)           /*!< Min enumerator value of ENDTX field.                                 */
80037   #define UARTE_INTENCLR_ENDTX_Max (0x1UL)           /*!< Max enumerator value of ENDTX field.                                 */
80038   #define UARTE_INTENCLR_ENDTX_Clear (0x1UL)         /*!< Disable                                                              */
80039   #define UARTE_INTENCLR_ENDTX_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
80040   #define UARTE_INTENCLR_ENDTX_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
80041 
80042 /* ERROR @Bit 9 : Write '1' to disable interrupt for event ERROR */
80043   #define UARTE_INTENCLR_ERROR_Pos (9UL)             /*!< Position of ERROR field.                                             */
80044   #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field.                           */
80045   #define UARTE_INTENCLR_ERROR_Min (0x0UL)           /*!< Min enumerator value of ERROR field.                                 */
80046   #define UARTE_INTENCLR_ERROR_Max (0x1UL)           /*!< Max enumerator value of ERROR field.                                 */
80047   #define UARTE_INTENCLR_ERROR_Clear (0x1UL)         /*!< Disable                                                              */
80048   #define UARTE_INTENCLR_ERROR_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
80049   #define UARTE_INTENCLR_ERROR_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
80050 
80051 /* RXTO @Bit 17 : Write '1' to disable interrupt for event RXTO */
80052   #define UARTE_INTENCLR_RXTO_Pos (17UL)             /*!< Position of RXTO field.                                              */
80053   #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field.                              */
80054   #define UARTE_INTENCLR_RXTO_Min (0x0UL)            /*!< Min enumerator value of RXTO field.                                  */
80055   #define UARTE_INTENCLR_RXTO_Max (0x1UL)            /*!< Max enumerator value of RXTO field.                                  */
80056   #define UARTE_INTENCLR_RXTO_Clear (0x1UL)          /*!< Disable                                                              */
80057   #define UARTE_INTENCLR_RXTO_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
80058   #define UARTE_INTENCLR_RXTO_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
80059 
80060 /* RXSTARTED @Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
80061   #define UARTE_INTENCLR_RXSTARTED_Pos (19UL)        /*!< Position of RXSTARTED field.                                         */
80062   #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field.               */
80063   #define UARTE_INTENCLR_RXSTARTED_Min (0x0UL)       /*!< Min enumerator value of RXSTARTED field.                             */
80064   #define UARTE_INTENCLR_RXSTARTED_Max (0x1UL)       /*!< Max enumerator value of RXSTARTED field.                             */
80065   #define UARTE_INTENCLR_RXSTARTED_Clear (0x1UL)     /*!< Disable                                                              */
80066   #define UARTE_INTENCLR_RXSTARTED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
80067   #define UARTE_INTENCLR_RXSTARTED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
80068 
80069 /* TXSTARTED @Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
80070   #define UARTE_INTENCLR_TXSTARTED_Pos (20UL)        /*!< Position of TXSTARTED field.                                         */
80071   #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field.               */
80072   #define UARTE_INTENCLR_TXSTARTED_Min (0x0UL)       /*!< Min enumerator value of TXSTARTED field.                             */
80073   #define UARTE_INTENCLR_TXSTARTED_Max (0x1UL)       /*!< Max enumerator value of TXSTARTED field.                             */
80074   #define UARTE_INTENCLR_TXSTARTED_Clear (0x1UL)     /*!< Disable                                                              */
80075   #define UARTE_INTENCLR_TXSTARTED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
80076   #define UARTE_INTENCLR_TXSTARTED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
80077 
80078 /* TXSTOPPED @Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
80079   #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL)        /*!< Position of TXSTOPPED field.                                         */
80080   #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field.               */
80081   #define UARTE_INTENCLR_TXSTOPPED_Min (0x0UL)       /*!< Min enumerator value of TXSTOPPED field.                             */
80082   #define UARTE_INTENCLR_TXSTOPPED_Max (0x1UL)       /*!< Max enumerator value of TXSTOPPED field.                             */
80083   #define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL)     /*!< Disable                                                              */
80084   #define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
80085   #define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
80086 
80087 /* RXBUSERROR @Bit 29 : Write '1' to disable interrupt for event RXBUSERROR */
80088   #define UARTE_INTENCLR_RXBUSERROR_Pos (29UL)       /*!< Position of RXBUSERROR field.                                        */
80089   #define UARTE_INTENCLR_RXBUSERROR_Msk (0x1UL << UARTE_INTENCLR_RXBUSERROR_Pos) /*!< Bit mask of RXBUSERROR field.            */
80090   #define UARTE_INTENCLR_RXBUSERROR_Min (0x0UL)      /*!< Min enumerator value of RXBUSERROR field.                            */
80091   #define UARTE_INTENCLR_RXBUSERROR_Max (0x1UL)      /*!< Max enumerator value of RXBUSERROR field.                            */
80092   #define UARTE_INTENCLR_RXBUSERROR_Clear (0x1UL)    /*!< Disable                                                              */
80093   #define UARTE_INTENCLR_RXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
80094   #define UARTE_INTENCLR_RXBUSERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
80095 
80096 /* TXBUSERROR @Bit 30 : Write '1' to disable interrupt for event TXBUSERROR */
80097   #define UARTE_INTENCLR_TXBUSERROR_Pos (30UL)       /*!< Position of TXBUSERROR field.                                        */
80098   #define UARTE_INTENCLR_TXBUSERROR_Msk (0x1UL << UARTE_INTENCLR_TXBUSERROR_Pos) /*!< Bit mask of TXBUSERROR field.            */
80099   #define UARTE_INTENCLR_TXBUSERROR_Min (0x0UL)      /*!< Min enumerator value of TXBUSERROR field.                            */
80100   #define UARTE_INTENCLR_TXBUSERROR_Max (0x1UL)      /*!< Max enumerator value of TXBUSERROR field.                            */
80101   #define UARTE_INTENCLR_TXBUSERROR_Clear (0x1UL)    /*!< Disable                                                              */
80102   #define UARTE_INTENCLR_TXBUSERROR_Disabled (0x0UL) /*!< Read: Disabled                                                       */
80103   #define UARTE_INTENCLR_TXBUSERROR_Enabled (0x1UL)  /*!< Read: Enabled                                                        */
80104 
80105 
80106 /* UARTE_ERRORSRC: Error source */
80107   #define UARTE_ERRORSRC_ResetValue (0x00000000UL)   /*!< Reset value of ERRORSRC register.                                    */
80108 
80109 /* OVERRUN @Bit 0 : Overrun error */
80110   #define UARTE_ERRORSRC_OVERRUN_Pos (0UL)           /*!< Position of OVERRUN field.                                           */
80111   #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field.                     */
80112   #define UARTE_ERRORSRC_OVERRUN_Min (0x0UL)         /*!< Min enumerator value of OVERRUN field.                               */
80113   #define UARTE_ERRORSRC_OVERRUN_Max (0x1UL)         /*!< Max enumerator value of OVERRUN field.                               */
80114   #define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL)  /*!< Read: error not present                                              */
80115   #define UARTE_ERRORSRC_OVERRUN_Present (0x1UL)     /*!< Read: error present                                                  */
80116 
80117 /* PARITY @Bit 1 : Parity error */
80118   #define UARTE_ERRORSRC_PARITY_Pos (1UL)            /*!< Position of PARITY field.                                            */
80119   #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field.                        */
80120   #define UARTE_ERRORSRC_PARITY_Min (0x0UL)          /*!< Min enumerator value of PARITY field.                                */
80121   #define UARTE_ERRORSRC_PARITY_Max (0x1UL)          /*!< Max enumerator value of PARITY field.                                */
80122   #define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL)   /*!< Read: error not present                                              */
80123   #define UARTE_ERRORSRC_PARITY_Present (0x1UL)      /*!< Read: error present                                                  */
80124 
80125 /* FRAMING @Bit 2 : Framing error occurred */
80126   #define UARTE_ERRORSRC_FRAMING_Pos (2UL)           /*!< Position of FRAMING field.                                           */
80127   #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field.                     */
80128   #define UARTE_ERRORSRC_FRAMING_Min (0x0UL)         /*!< Min enumerator value of FRAMING field.                               */
80129   #define UARTE_ERRORSRC_FRAMING_Max (0x1UL)         /*!< Max enumerator value of FRAMING field.                               */
80130   #define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL)  /*!< Read: error not present                                              */
80131   #define UARTE_ERRORSRC_FRAMING_Present (0x1UL)     /*!< Read: error present                                                  */
80132 
80133 /* BREAK @Bit 3 : Break condition */
80134   #define UARTE_ERRORSRC_BREAK_Pos (3UL)             /*!< Position of BREAK field.                                             */
80135   #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field.                           */
80136   #define UARTE_ERRORSRC_BREAK_Min (0x0UL)           /*!< Min enumerator value of BREAK field.                                 */
80137   #define UARTE_ERRORSRC_BREAK_Max (0x1UL)           /*!< Max enumerator value of BREAK field.                                 */
80138   #define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL)    /*!< Read: error not present                                              */
80139   #define UARTE_ERRORSRC_BREAK_Present (0x1UL)       /*!< Read: error present                                                  */
80140 
80141 
80142 /* UARTE_ENABLE: Enable UART */
80143   #define UARTE_ENABLE_ResetValue (0x00000000UL)     /*!< Reset value of ENABLE register.                                      */
80144 
80145 /* ENABLE @Bits 0..3 : Enable or disable UARTE */
80146   #define UARTE_ENABLE_ENABLE_Pos (0UL)              /*!< Position of ENABLE field.                                            */
80147   #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field.                            */
80148   #define UARTE_ENABLE_ENABLE_Min (0x0UL)            /*!< Min enumerator value of ENABLE field.                                */
80149   #define UARTE_ENABLE_ENABLE_Max (0x8UL)            /*!< Max enumerator value of ENABLE field.                                */
80150   #define UARTE_ENABLE_ENABLE_Disabled (0x0UL)       /*!< Disable UARTE                                                        */
80151   #define UARTE_ENABLE_ENABLE_Enabled (0x8UL)        /*!< Enable UARTE                                                         */
80152 
80153 
80154 /* UARTE_BAUDRATE: Baud rate. Accuracy depends on the HFCLK source selected. */
80155   #define UARTE_BAUDRATE_ResetValue (0x04000000UL)   /*!< Reset value of BAUDRATE register.                                    */
80156 
80157 /* BAUDRATE @Bits 0..31 : Baud rate */
80158   #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL)          /*!< Position of BAUDRATE field.                                          */
80159   #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field.           */
80160   #define UARTE_BAUDRATE_BAUDRATE_Min (0x4F000UL)    /*!< Min enumerator value of BAUDRATE field.                              */
80161   #define UARTE_BAUDRATE_BAUDRATE_Max (0x10000000UL) /*!< Max enumerator value of BAUDRATE field.                              */
80162   #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205)                                   */
80163   #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396)                                   */
80164   #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808)                                   */
80165   #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598)                                   */
80166   #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401)                                */
80167   #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208)                                */
80168   #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777)                                */
80169   #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud                                                     */
80170   #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369)                                */
80171   #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944)                                */
80172   #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554)                                */
80173   #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923)                                */
80174   #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108)                             */
80175   #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884)                             */
80176   #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud                                                   */
80177   #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143)                             */
80178   #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176)                             */
80179   #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud                                                        */
80180 
80181 
80182 /* UARTE_CONFIG: Configuration of parity and hardware flow control */
80183   #define UARTE_CONFIG_ResetValue (0x00000000UL)     /*!< Reset value of CONFIG register.                                      */
80184 
80185 /* HWFC @Bit 0 : Hardware flow control */
80186   #define UARTE_CONFIG_HWFC_Pos (0UL)                /*!< Position of HWFC field.                                              */
80187   #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field.                                  */
80188   #define UARTE_CONFIG_HWFC_Min (0x0UL)              /*!< Min enumerator value of HWFC field.                                  */
80189   #define UARTE_CONFIG_HWFC_Max (0x1UL)              /*!< Max enumerator value of HWFC field.                                  */
80190   #define UARTE_CONFIG_HWFC_Disabled (0x0UL)         /*!< Disabled                                                             */
80191   #define UARTE_CONFIG_HWFC_Enabled (0x1UL)          /*!< Enabled                                                              */
80192 
80193 /* PARITY @Bits 1..3 : Parity */
80194   #define UARTE_CONFIG_PARITY_Pos (1UL)              /*!< Position of PARITY field.                                            */
80195   #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field.                            */
80196   #define UARTE_CONFIG_PARITY_Min (0x0UL)            /*!< Min enumerator value of PARITY field.                                */
80197   #define UARTE_CONFIG_PARITY_Max (0x7UL)            /*!< Max enumerator value of PARITY field.                                */
80198   #define UARTE_CONFIG_PARITY_Excluded (0x0UL)       /*!< Exclude parity bit                                                   */
80199   #define UARTE_CONFIG_PARITY_Included (0x7UL)       /*!< Include even parity bit                                              */
80200 
80201 /* STOP @Bit 4 : Stop bits */
80202   #define UARTE_CONFIG_STOP_Pos (4UL)                /*!< Position of STOP field.                                              */
80203   #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field.                                  */
80204   #define UARTE_CONFIG_STOP_Min (0x0UL)              /*!< Min enumerator value of STOP field.                                  */
80205   #define UARTE_CONFIG_STOP_Max (0x1UL)              /*!< Max enumerator value of STOP field.                                  */
80206   #define UARTE_CONFIG_STOP_One (0x0UL)              /*!< One stop bit                                                         */
80207   #define UARTE_CONFIG_STOP_Two (0x1UL)              /*!< Two stop bits                                                        */
80208 
80209 /* PARITYTYPE @Bit 8 : Even or odd parity type */
80210   #define UARTE_CONFIG_PARITYTYPE_Pos (8UL)          /*!< Position of PARITYTYPE field.                                        */
80211   #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field.                */
80212   #define UARTE_CONFIG_PARITYTYPE_Min (0x0UL)        /*!< Min enumerator value of PARITYTYPE field.                            */
80213   #define UARTE_CONFIG_PARITYTYPE_Max (0x1UL)        /*!< Max enumerator value of PARITYTYPE field.                            */
80214   #define UARTE_CONFIG_PARITYTYPE_Even (0x0UL)       /*!< Even parity                                                          */
80215   #define UARTE_CONFIG_PARITYTYPE_Odd (0x1UL)        /*!< Odd parity                                                           */
80216 
80217 
80218 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
80219 
80220 /* =========================================================================================================================== */
80221 /* ================                                           UICR                                           ================ */
80222 /* =========================================================================================================================== */
80223 
80224 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
80225 
80226 /* ===================================================== Struct UICR_MEM ===================================================== */
80227 /**
80228   * @brief MEM [UICR_MEM] (unspecified)
80229   */
80230 typedef struct {
80231   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Memory configuration of the memory region             */
80232   __IOM uint32_t  SIZE;                              /*!< (@ 0x00000004) Size of the memory region                             */
80233 } NRF_UICR_MEM_Type;                                 /*!< Size = 8 (0x008)                                                     */
80234   #define UICR_MEM_MaxCount (16UL)                   /*!< Size of MEM[16] array.                                               */
80235   #define UICR_MEM_MaxIndex (15UL)                   /*!< Max index of MEM[16] array.                                          */
80236   #define UICR_MEM_MinIndex (0UL)                    /*!< Min index of MEM[16] array.                                          */
80237 
80238 /* UICR_MEM_CONFIG: Memory configuration of the memory region */
80239   #define UICR_MEM_CONFIG_ResetValue (0xFFFFFFFFUL)  /*!< Reset value of CONFIG register.                                      */
80240 
80241 /* READ @Bit 0 : (unspecified) */
80242   #define UICR_MEM_CONFIG_READ_Pos (0UL)             /*!< Position of READ field.                                              */
80243   #define UICR_MEM_CONFIG_READ_Msk (0x1UL << UICR_MEM_CONFIG_READ_Pos) /*!< Bit mask of READ field.                            */
80244   #define UICR_MEM_CONFIG_READ_Min (0x0UL)           /*!< Min enumerator value of READ field.                                  */
80245   #define UICR_MEM_CONFIG_READ_Max (0x1UL)           /*!< Max enumerator value of READ field.                                  */
80246   #define UICR_MEM_CONFIG_READ_NotAllowed (0x1UL)    /*!< Read access to MEM[n] is not allowed                                 */
80247   #define UICR_MEM_CONFIG_READ_Allowed (0x0UL)       /*!< Read access to MEM[n] is allowed                                     */
80248 
80249 /* WRITE @Bit 1 : (unspecified) */
80250   #define UICR_MEM_CONFIG_WRITE_Pos (1UL)            /*!< Position of WRITE field.                                             */
80251   #define UICR_MEM_CONFIG_WRITE_Msk (0x1UL << UICR_MEM_CONFIG_WRITE_Pos) /*!< Bit mask of WRITE field.                         */
80252   #define UICR_MEM_CONFIG_WRITE_Min (0x0UL)          /*!< Min enumerator value of WRITE field.                                 */
80253   #define UICR_MEM_CONFIG_WRITE_Max (0x1UL)          /*!< Max enumerator value of WRITE field.                                 */
80254   #define UICR_MEM_CONFIG_WRITE_NotAllowed (0x1UL)   /*!< Write access to MEM[n] is not allowed                                */
80255   #define UICR_MEM_CONFIG_WRITE_Allowed (0x0UL)      /*!< Write access to MEM[n] is allowed                                    */
80256 
80257 /* EXECUTE @Bit 2 : (unspecified) */
80258   #define UICR_MEM_CONFIG_EXECUTE_Pos (2UL)          /*!< Position of EXECUTE field.                                           */
80259   #define UICR_MEM_CONFIG_EXECUTE_Msk (0x1UL << UICR_MEM_CONFIG_EXECUTE_Pos) /*!< Bit mask of EXECUTE field.                   */
80260   #define UICR_MEM_CONFIG_EXECUTE_Min (0x0UL)        /*!< Min enumerator value of EXECUTE field.                               */
80261   #define UICR_MEM_CONFIG_EXECUTE_Max (0x1UL)        /*!< Max enumerator value of EXECUTE field.                               */
80262   #define UICR_MEM_CONFIG_EXECUTE_NotAllowed (0x1UL) /*!< SW execution from MEM[n] is not allowed                              */
80263   #define UICR_MEM_CONFIG_EXECUTE_Allowed (0x0UL)    /*!< SW execution from MEM[n] is allowed                                  */
80264 
80265 /* SECURE @Bit 3 : (unspecified) */
80266   #define UICR_MEM_CONFIG_SECURE_Pos (3UL)           /*!< Position of SECURE field.                                            */
80267   #define UICR_MEM_CONFIG_SECURE_Msk (0x1UL << UICR_MEM_CONFIG_SECURE_Pos) /*!< Bit mask of SECURE field.                      */
80268   #define UICR_MEM_CONFIG_SECURE_Min (0x0UL)         /*!< Min enumerator value of SECURE field.                                */
80269   #define UICR_MEM_CONFIG_SECURE_Max (0x1UL)         /*!< Max enumerator value of SECURE field.                                */
80270   #define UICR_MEM_CONFIG_SECURE_Secure (0x1UL)      /*!< Non-secure access to MEM[n] is not allowed                           */
80271   #define UICR_MEM_CONFIG_SECURE_NonSecure (0x0UL)   /*!< Non-secure access to MEM[n] is allowed                               */
80272 
80273 /* NSC @Bit 4 : (unspecified) */
80274   #define UICR_MEM_CONFIG_NSC_Pos (4UL)              /*!< Position of NSC field.                                               */
80275   #define UICR_MEM_CONFIG_NSC_Msk (0x1UL << UICR_MEM_CONFIG_NSC_Pos) /*!< Bit mask of NSC field.                               */
80276   #define UICR_MEM_CONFIG_NSC_Min (0x0UL)            /*!< Min enumerator value of NSC field.                                   */
80277   #define UICR_MEM_CONFIG_NSC_Max (0x1UL)            /*!< Max enumerator value of NSC field.                                   */
80278   #define UICR_MEM_CONFIG_NSC_Disabled (0x1UL)       /*!< Memory region is not non-secure callable                             */
80279   #define UICR_MEM_CONFIG_NSC_Enabled (0x0UL)        /*!< Memory region is non-secure callable                                 */
80280 
80281 /* OWNERID @Bits 8..11 : Memory owner identification */
80282   #define UICR_MEM_CONFIG_OWNERID_Pos (8UL)          /*!< Position of OWNERID field.                                           */
80283   #define UICR_MEM_CONFIG_OWNERID_Msk (0xFUL << UICR_MEM_CONFIG_OWNERID_Pos) /*!< Bit mask of OWNERID field.                   */
80284   #define UICR_MEM_CONFIG_OWNERID_Min (0x0UL)        /*!< Min value of OWNERID field.                                          */
80285   #define UICR_MEM_CONFIG_OWNERID_Max (0xFUL)        /*!< Max size of OWNERID field.                                           */
80286 
80287 /* ADDRESS @Bits 12..31 : Memory region start address, bits [31:12] */
80288   #define UICR_MEM_CONFIG_ADDRESS_Pos (12UL)         /*!< Position of ADDRESS field.                                           */
80289   #define UICR_MEM_CONFIG_ADDRESS_Msk (0xFFFFFUL << UICR_MEM_CONFIG_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.               */
80290 
80291 
80292 /* UICR_MEM_SIZE: Size of the memory region */
80293   #define UICR_MEM_SIZE_ResetValue (0xFFFFFFFFUL)    /*!< Reset value of SIZE register.                                        */
80294 
80295 /* SIZE @Bits 0..31 : Memory size in bytes */
80296   #define UICR_MEM_SIZE_SIZE_Pos (0UL)               /*!< Position of SIZE field.                                              */
80297   #define UICR_MEM_SIZE_SIZE_Msk (0xFFFFFFFFUL << UICR_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field.                         */
80298 
80299 
80300 
80301 /* =================================================== Struct UICR_PERIPH ==================================================== */
80302 /**
80303   * @brief PERIPH [UICR_PERIPH] (unspecified)
80304   */
80305 typedef struct {
80306   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000000) Peripheral configuration                              */
80307 } NRF_UICR_PERIPH_Type;                              /*!< Size = 4 (0x004)                                                     */
80308   #define UICR_PERIPH_MaxCount (192UL)               /*!< Size of PERIPH[192] array.                                           */
80309   #define UICR_PERIPH_MaxIndex (191UL)               /*!< Max index of PERIPH[192] array.                                      */
80310   #define UICR_PERIPH_MinIndex (0UL)                 /*!< Min index of PERIPH[192] array.                                      */
80311 
80312 /* UICR_PERIPH_CONFIG: Peripheral configuration */
80313   #define UICR_PERIPH_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register.                                    */
80314 
80315 /* SECURE @Bit 3 : Peripheral security mapping */
80316   #define UICR_PERIPH_CONFIG_SECURE_Pos (3UL)        /*!< Position of SECURE field.                                            */
80317   #define UICR_PERIPH_CONFIG_SECURE_Msk (0x1UL << UICR_PERIPH_CONFIG_SECURE_Pos) /*!< Bit mask of SECURE field.                */
80318   #define UICR_PERIPH_CONFIG_SECURE_Min (0x0UL)      /*!< Min enumerator value of SECURE field.                                */
80319   #define UICR_PERIPH_CONFIG_SECURE_Max (0x1UL)      /*!< Max enumerator value of SECURE field.                                */
80320   #define UICR_PERIPH_CONFIG_SECURE_Secure (0x1UL)   /*!< Peripheral is mapped in secure peripheral address space              */
80321   #define UICR_PERIPH_CONFIG_SECURE_NonSecure (0x0UL) /*!< Peripheral is mapped in non-secure peripheral address space.        */
80322 
80323 /* DMASEC @Bit 5 : Security attribution for the DMA transfer */
80324   #define UICR_PERIPH_CONFIG_DMASEC_Pos (5UL)        /*!< Position of DMASEC field.                                            */
80325   #define UICR_PERIPH_CONFIG_DMASEC_Msk (0x1UL << UICR_PERIPH_CONFIG_DMASEC_Pos) /*!< Bit mask of DMASEC field.                */
80326   #define UICR_PERIPH_CONFIG_DMASEC_Min (0x0UL)      /*!< Min enumerator value of DMASEC field.                                */
80327   #define UICR_PERIPH_CONFIG_DMASEC_Max (0x1UL)      /*!< Max enumerator value of DMASEC field.                                */
80328   #define UICR_PERIPH_CONFIG_DMASEC_Secure (0x1UL)   /*!< DMA transfers initiated by this peripheral have the secure attribute
80329                                                           set*/
80330   #define UICR_PERIPH_CONFIG_DMASEC_NonSecure (0x0UL) /*!< DMA transfers initiated by this peripheral have the non-secure
80331                                                            attribute set*/
80332 
80333 /* PROCESSOR @Bits 8..11 : Processor ID of the processor that will receive the peripheral IRQ */
80334   #define UICR_PERIPH_CONFIG_PROCESSOR_Pos (8UL)     /*!< Position of PROCESSOR field.                                         */
80335   #define UICR_PERIPH_CONFIG_PROCESSOR_Msk (0xFUL << UICR_PERIPH_CONFIG_PROCESSOR_Pos) /*!< Bit mask of PROCESSOR field.       */
80336 
80337 /* ADDRESS @Bits 12..31 : Peripheral address, bits [31:12] */
80338   #define UICR_PERIPH_CONFIG_ADDRESS_Pos (12UL)      /*!< Position of ADDRESS field.                                           */
80339   #define UICR_PERIPH_CONFIG_ADDRESS_Msk (0xFFFFFUL << UICR_PERIPH_CONFIG_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.         */
80340 
80341 
80342 
80343 /* ================================================== Struct UICR_GPIOTE_CH ================================================== */
80344 /**
80345   * @brief CH [UICR_GPIOTE_CH] (unspecified)
80346   */
80347 typedef struct {
80348   __IOM uint32_t  OWN;                               /*!< (@ 0x00000000) Request ownership of the channels of GPIOTE[n]        */
80349   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Request permission for the channels of GPIOTE[n]      */
80350 } NRF_UICR_GPIOTE_CH_Type;                           /*!< Size = 8 (0x008)                                                     */
80351 
80352 /* UICR_GPIOTE_CH_OWN: Request ownership of the channels of GPIOTE[n] */
80353   #define UICR_GPIOTE_CH_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register.                                       */
80354 
80355 /* CH0 @Bit 0 : Channel number */
80356   #define UICR_GPIOTE_CH_OWN_CH0_Pos (0UL)           /*!< Position of CH0 field.                                               */
80357   #define UICR_GPIOTE_CH_OWN_CH0_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH0_Pos) /*!< Bit mask of CH0 field.                         */
80358   #define UICR_GPIOTE_CH_OWN_CH0_Min (0x0UL)         /*!< Min enumerator value of CH0 field.                                   */
80359   #define UICR_GPIOTE_CH_OWN_CH0_Max (0x1UL)         /*!< Max enumerator value of CH0 field.                                   */
80360   #define UICR_GPIOTE_CH_OWN_CH0_NotOwn (0x1UL)      /*!< Do not own the channel 0                                             */
80361   #define UICR_GPIOTE_CH_OWN_CH0_Own (0x0UL)         /*!< Own the channel 0                                                    */
80362 
80363 /* CH1 @Bit 1 : Channel number */
80364   #define UICR_GPIOTE_CH_OWN_CH1_Pos (1UL)           /*!< Position of CH1 field.                                               */
80365   #define UICR_GPIOTE_CH_OWN_CH1_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH1_Pos) /*!< Bit mask of CH1 field.                         */
80366   #define UICR_GPIOTE_CH_OWN_CH1_Min (0x0UL)         /*!< Min enumerator value of CH1 field.                                   */
80367   #define UICR_GPIOTE_CH_OWN_CH1_Max (0x1UL)         /*!< Max enumerator value of CH1 field.                                   */
80368   #define UICR_GPIOTE_CH_OWN_CH1_NotOwn (0x1UL)      /*!< Do not own the channel 1                                             */
80369   #define UICR_GPIOTE_CH_OWN_CH1_Own (0x0UL)         /*!< Own the channel 1                                                    */
80370 
80371 /* CH2 @Bit 2 : Channel number */
80372   #define UICR_GPIOTE_CH_OWN_CH2_Pos (2UL)           /*!< Position of CH2 field.                                               */
80373   #define UICR_GPIOTE_CH_OWN_CH2_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH2_Pos) /*!< Bit mask of CH2 field.                         */
80374   #define UICR_GPIOTE_CH_OWN_CH2_Min (0x0UL)         /*!< Min enumerator value of CH2 field.                                   */
80375   #define UICR_GPIOTE_CH_OWN_CH2_Max (0x1UL)         /*!< Max enumerator value of CH2 field.                                   */
80376   #define UICR_GPIOTE_CH_OWN_CH2_NotOwn (0x1UL)      /*!< Do not own the channel 2                                             */
80377   #define UICR_GPIOTE_CH_OWN_CH2_Own (0x0UL)         /*!< Own the channel 2                                                    */
80378 
80379 /* CH3 @Bit 3 : Channel number */
80380   #define UICR_GPIOTE_CH_OWN_CH3_Pos (3UL)           /*!< Position of CH3 field.                                               */
80381   #define UICR_GPIOTE_CH_OWN_CH3_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH3_Pos) /*!< Bit mask of CH3 field.                         */
80382   #define UICR_GPIOTE_CH_OWN_CH3_Min (0x0UL)         /*!< Min enumerator value of CH3 field.                                   */
80383   #define UICR_GPIOTE_CH_OWN_CH3_Max (0x1UL)         /*!< Max enumerator value of CH3 field.                                   */
80384   #define UICR_GPIOTE_CH_OWN_CH3_NotOwn (0x1UL)      /*!< Do not own the channel 3                                             */
80385   #define UICR_GPIOTE_CH_OWN_CH3_Own (0x0UL)         /*!< Own the channel 3                                                    */
80386 
80387 /* CH4 @Bit 4 : Channel number */
80388   #define UICR_GPIOTE_CH_OWN_CH4_Pos (4UL)           /*!< Position of CH4 field.                                               */
80389   #define UICR_GPIOTE_CH_OWN_CH4_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH4_Pos) /*!< Bit mask of CH4 field.                         */
80390   #define UICR_GPIOTE_CH_OWN_CH4_Min (0x0UL)         /*!< Min enumerator value of CH4 field.                                   */
80391   #define UICR_GPIOTE_CH_OWN_CH4_Max (0x1UL)         /*!< Max enumerator value of CH4 field.                                   */
80392   #define UICR_GPIOTE_CH_OWN_CH4_NotOwn (0x1UL)      /*!< Do not own the channel 4                                             */
80393   #define UICR_GPIOTE_CH_OWN_CH4_Own (0x0UL)         /*!< Own the channel 4                                                    */
80394 
80395 /* CH5 @Bit 5 : Channel number */
80396   #define UICR_GPIOTE_CH_OWN_CH5_Pos (5UL)           /*!< Position of CH5 field.                                               */
80397   #define UICR_GPIOTE_CH_OWN_CH5_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH5_Pos) /*!< Bit mask of CH5 field.                         */
80398   #define UICR_GPIOTE_CH_OWN_CH5_Min (0x0UL)         /*!< Min enumerator value of CH5 field.                                   */
80399   #define UICR_GPIOTE_CH_OWN_CH5_Max (0x1UL)         /*!< Max enumerator value of CH5 field.                                   */
80400   #define UICR_GPIOTE_CH_OWN_CH5_NotOwn (0x1UL)      /*!< Do not own the channel 5                                             */
80401   #define UICR_GPIOTE_CH_OWN_CH5_Own (0x0UL)         /*!< Own the channel 5                                                    */
80402 
80403 /* CH6 @Bit 6 : Channel number */
80404   #define UICR_GPIOTE_CH_OWN_CH6_Pos (6UL)           /*!< Position of CH6 field.                                               */
80405   #define UICR_GPIOTE_CH_OWN_CH6_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH6_Pos) /*!< Bit mask of CH6 field.                         */
80406   #define UICR_GPIOTE_CH_OWN_CH6_Min (0x0UL)         /*!< Min enumerator value of CH6 field.                                   */
80407   #define UICR_GPIOTE_CH_OWN_CH6_Max (0x1UL)         /*!< Max enumerator value of CH6 field.                                   */
80408   #define UICR_GPIOTE_CH_OWN_CH6_NotOwn (0x1UL)      /*!< Do not own the channel 6                                             */
80409   #define UICR_GPIOTE_CH_OWN_CH6_Own (0x0UL)         /*!< Own the channel 6                                                    */
80410 
80411 /* CH7 @Bit 7 : Channel number */
80412   #define UICR_GPIOTE_CH_OWN_CH7_Pos (7UL)           /*!< Position of CH7 field.                                               */
80413   #define UICR_GPIOTE_CH_OWN_CH7_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH7_Pos) /*!< Bit mask of CH7 field.                         */
80414   #define UICR_GPIOTE_CH_OWN_CH7_Min (0x0UL)         /*!< Min enumerator value of CH7 field.                                   */
80415   #define UICR_GPIOTE_CH_OWN_CH7_Max (0x1UL)         /*!< Max enumerator value of CH7 field.                                   */
80416   #define UICR_GPIOTE_CH_OWN_CH7_NotOwn (0x1UL)      /*!< Do not own the channel 7                                             */
80417   #define UICR_GPIOTE_CH_OWN_CH7_Own (0x0UL)         /*!< Own the channel 7                                                    */
80418 
80419 /* CH8 @Bit 8 : Channel number */
80420   #define UICR_GPIOTE_CH_OWN_CH8_Pos (8UL)           /*!< Position of CH8 field.                                               */
80421   #define UICR_GPIOTE_CH_OWN_CH8_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH8_Pos) /*!< Bit mask of CH8 field.                         */
80422   #define UICR_GPIOTE_CH_OWN_CH8_Min (0x0UL)         /*!< Min enumerator value of CH8 field.                                   */
80423   #define UICR_GPIOTE_CH_OWN_CH8_Max (0x1UL)         /*!< Max enumerator value of CH8 field.                                   */
80424   #define UICR_GPIOTE_CH_OWN_CH8_NotOwn (0x1UL)      /*!< Do not own the channel 8                                             */
80425   #define UICR_GPIOTE_CH_OWN_CH8_Own (0x0UL)         /*!< Own the channel 8                                                    */
80426 
80427 /* CH9 @Bit 9 : Channel number */
80428   #define UICR_GPIOTE_CH_OWN_CH9_Pos (9UL)           /*!< Position of CH9 field.                                               */
80429   #define UICR_GPIOTE_CH_OWN_CH9_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH9_Pos) /*!< Bit mask of CH9 field.                         */
80430   #define UICR_GPIOTE_CH_OWN_CH9_Min (0x0UL)         /*!< Min enumerator value of CH9 field.                                   */
80431   #define UICR_GPIOTE_CH_OWN_CH9_Max (0x1UL)         /*!< Max enumerator value of CH9 field.                                   */
80432   #define UICR_GPIOTE_CH_OWN_CH9_NotOwn (0x1UL)      /*!< Do not own the channel 9                                             */
80433   #define UICR_GPIOTE_CH_OWN_CH9_Own (0x0UL)         /*!< Own the channel 9                                                    */
80434 
80435 /* CH10 @Bit 10 : Channel number */
80436   #define UICR_GPIOTE_CH_OWN_CH10_Pos (10UL)         /*!< Position of CH10 field.                                              */
80437   #define UICR_GPIOTE_CH_OWN_CH10_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH10_Pos) /*!< Bit mask of CH10 field.                      */
80438   #define UICR_GPIOTE_CH_OWN_CH10_Min (0x0UL)        /*!< Min enumerator value of CH10 field.                                  */
80439   #define UICR_GPIOTE_CH_OWN_CH10_Max (0x1UL)        /*!< Max enumerator value of CH10 field.                                  */
80440   #define UICR_GPIOTE_CH_OWN_CH10_NotOwn (0x1UL)     /*!< Do not own the channel 10                                            */
80441   #define UICR_GPIOTE_CH_OWN_CH10_Own (0x0UL)        /*!< Own the channel 10                                                   */
80442 
80443 /* CH11 @Bit 11 : Channel number */
80444   #define UICR_GPIOTE_CH_OWN_CH11_Pos (11UL)         /*!< Position of CH11 field.                                              */
80445   #define UICR_GPIOTE_CH_OWN_CH11_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH11_Pos) /*!< Bit mask of CH11 field.                      */
80446   #define UICR_GPIOTE_CH_OWN_CH11_Min (0x0UL)        /*!< Min enumerator value of CH11 field.                                  */
80447   #define UICR_GPIOTE_CH_OWN_CH11_Max (0x1UL)        /*!< Max enumerator value of CH11 field.                                  */
80448   #define UICR_GPIOTE_CH_OWN_CH11_NotOwn (0x1UL)     /*!< Do not own the channel 11                                            */
80449   #define UICR_GPIOTE_CH_OWN_CH11_Own (0x0UL)        /*!< Own the channel 11                                                   */
80450 
80451 /* CH12 @Bit 12 : Channel number */
80452   #define UICR_GPIOTE_CH_OWN_CH12_Pos (12UL)         /*!< Position of CH12 field.                                              */
80453   #define UICR_GPIOTE_CH_OWN_CH12_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH12_Pos) /*!< Bit mask of CH12 field.                      */
80454   #define UICR_GPIOTE_CH_OWN_CH12_Min (0x0UL)        /*!< Min enumerator value of CH12 field.                                  */
80455   #define UICR_GPIOTE_CH_OWN_CH12_Max (0x1UL)        /*!< Max enumerator value of CH12 field.                                  */
80456   #define UICR_GPIOTE_CH_OWN_CH12_NotOwn (0x1UL)     /*!< Do not own the channel 12                                            */
80457   #define UICR_GPIOTE_CH_OWN_CH12_Own (0x0UL)        /*!< Own the channel 12                                                   */
80458 
80459 /* CH13 @Bit 13 : Channel number */
80460   #define UICR_GPIOTE_CH_OWN_CH13_Pos (13UL)         /*!< Position of CH13 field.                                              */
80461   #define UICR_GPIOTE_CH_OWN_CH13_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH13_Pos) /*!< Bit mask of CH13 field.                      */
80462   #define UICR_GPIOTE_CH_OWN_CH13_Min (0x0UL)        /*!< Min enumerator value of CH13 field.                                  */
80463   #define UICR_GPIOTE_CH_OWN_CH13_Max (0x1UL)        /*!< Max enumerator value of CH13 field.                                  */
80464   #define UICR_GPIOTE_CH_OWN_CH13_NotOwn (0x1UL)     /*!< Do not own the channel 13                                            */
80465   #define UICR_GPIOTE_CH_OWN_CH13_Own (0x0UL)        /*!< Own the channel 13                                                   */
80466 
80467 /* CH14 @Bit 14 : Channel number */
80468   #define UICR_GPIOTE_CH_OWN_CH14_Pos (14UL)         /*!< Position of CH14 field.                                              */
80469   #define UICR_GPIOTE_CH_OWN_CH14_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH14_Pos) /*!< Bit mask of CH14 field.                      */
80470   #define UICR_GPIOTE_CH_OWN_CH14_Min (0x0UL)        /*!< Min enumerator value of CH14 field.                                  */
80471   #define UICR_GPIOTE_CH_OWN_CH14_Max (0x1UL)        /*!< Max enumerator value of CH14 field.                                  */
80472   #define UICR_GPIOTE_CH_OWN_CH14_NotOwn (0x1UL)     /*!< Do not own the channel 14                                            */
80473   #define UICR_GPIOTE_CH_OWN_CH14_Own (0x0UL)        /*!< Own the channel 14                                                   */
80474 
80475 /* CH15 @Bit 15 : Channel number */
80476   #define UICR_GPIOTE_CH_OWN_CH15_Pos (15UL)         /*!< Position of CH15 field.                                              */
80477   #define UICR_GPIOTE_CH_OWN_CH15_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH15_Pos) /*!< Bit mask of CH15 field.                      */
80478   #define UICR_GPIOTE_CH_OWN_CH15_Min (0x0UL)        /*!< Min enumerator value of CH15 field.                                  */
80479   #define UICR_GPIOTE_CH_OWN_CH15_Max (0x1UL)        /*!< Max enumerator value of CH15 field.                                  */
80480   #define UICR_GPIOTE_CH_OWN_CH15_NotOwn (0x1UL)     /*!< Do not own the channel 15                                            */
80481   #define UICR_GPIOTE_CH_OWN_CH15_Own (0x0UL)        /*!< Own the channel 15                                                   */
80482 
80483 /* CH16 @Bit 16 : Channel number */
80484   #define UICR_GPIOTE_CH_OWN_CH16_Pos (16UL)         /*!< Position of CH16 field.                                              */
80485   #define UICR_GPIOTE_CH_OWN_CH16_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH16_Pos) /*!< Bit mask of CH16 field.                      */
80486   #define UICR_GPIOTE_CH_OWN_CH16_Min (0x0UL)        /*!< Min enumerator value of CH16 field.                                  */
80487   #define UICR_GPIOTE_CH_OWN_CH16_Max (0x1UL)        /*!< Max enumerator value of CH16 field.                                  */
80488   #define UICR_GPIOTE_CH_OWN_CH16_NotOwn (0x1UL)     /*!< Do not own the channel 16                                            */
80489   #define UICR_GPIOTE_CH_OWN_CH16_Own (0x0UL)        /*!< Own the channel 16                                                   */
80490 
80491 /* CH17 @Bit 17 : Channel number */
80492   #define UICR_GPIOTE_CH_OWN_CH17_Pos (17UL)         /*!< Position of CH17 field.                                              */
80493   #define UICR_GPIOTE_CH_OWN_CH17_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH17_Pos) /*!< Bit mask of CH17 field.                      */
80494   #define UICR_GPIOTE_CH_OWN_CH17_Min (0x0UL)        /*!< Min enumerator value of CH17 field.                                  */
80495   #define UICR_GPIOTE_CH_OWN_CH17_Max (0x1UL)        /*!< Max enumerator value of CH17 field.                                  */
80496   #define UICR_GPIOTE_CH_OWN_CH17_NotOwn (0x1UL)     /*!< Do not own the channel 17                                            */
80497   #define UICR_GPIOTE_CH_OWN_CH17_Own (0x0UL)        /*!< Own the channel 17                                                   */
80498 
80499 /* CH18 @Bit 18 : Channel number */
80500   #define UICR_GPIOTE_CH_OWN_CH18_Pos (18UL)         /*!< Position of CH18 field.                                              */
80501   #define UICR_GPIOTE_CH_OWN_CH18_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH18_Pos) /*!< Bit mask of CH18 field.                      */
80502   #define UICR_GPIOTE_CH_OWN_CH18_Min (0x0UL)        /*!< Min enumerator value of CH18 field.                                  */
80503   #define UICR_GPIOTE_CH_OWN_CH18_Max (0x1UL)        /*!< Max enumerator value of CH18 field.                                  */
80504   #define UICR_GPIOTE_CH_OWN_CH18_NotOwn (0x1UL)     /*!< Do not own the channel 18                                            */
80505   #define UICR_GPIOTE_CH_OWN_CH18_Own (0x0UL)        /*!< Own the channel 18                                                   */
80506 
80507 /* CH19 @Bit 19 : Channel number */
80508   #define UICR_GPIOTE_CH_OWN_CH19_Pos (19UL)         /*!< Position of CH19 field.                                              */
80509   #define UICR_GPIOTE_CH_OWN_CH19_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH19_Pos) /*!< Bit mask of CH19 field.                      */
80510   #define UICR_GPIOTE_CH_OWN_CH19_Min (0x0UL)        /*!< Min enumerator value of CH19 field.                                  */
80511   #define UICR_GPIOTE_CH_OWN_CH19_Max (0x1UL)        /*!< Max enumerator value of CH19 field.                                  */
80512   #define UICR_GPIOTE_CH_OWN_CH19_NotOwn (0x1UL)     /*!< Do not own the channel 19                                            */
80513   #define UICR_GPIOTE_CH_OWN_CH19_Own (0x0UL)        /*!< Own the channel 19                                                   */
80514 
80515 /* CH20 @Bit 20 : Channel number */
80516   #define UICR_GPIOTE_CH_OWN_CH20_Pos (20UL)         /*!< Position of CH20 field.                                              */
80517   #define UICR_GPIOTE_CH_OWN_CH20_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH20_Pos) /*!< Bit mask of CH20 field.                      */
80518   #define UICR_GPIOTE_CH_OWN_CH20_Min (0x0UL)        /*!< Min enumerator value of CH20 field.                                  */
80519   #define UICR_GPIOTE_CH_OWN_CH20_Max (0x1UL)        /*!< Max enumerator value of CH20 field.                                  */
80520   #define UICR_GPIOTE_CH_OWN_CH20_NotOwn (0x1UL)     /*!< Do not own the channel 20                                            */
80521   #define UICR_GPIOTE_CH_OWN_CH20_Own (0x0UL)        /*!< Own the channel 20                                                   */
80522 
80523 /* CH21 @Bit 21 : Channel number */
80524   #define UICR_GPIOTE_CH_OWN_CH21_Pos (21UL)         /*!< Position of CH21 field.                                              */
80525   #define UICR_GPIOTE_CH_OWN_CH21_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH21_Pos) /*!< Bit mask of CH21 field.                      */
80526   #define UICR_GPIOTE_CH_OWN_CH21_Min (0x0UL)        /*!< Min enumerator value of CH21 field.                                  */
80527   #define UICR_GPIOTE_CH_OWN_CH21_Max (0x1UL)        /*!< Max enumerator value of CH21 field.                                  */
80528   #define UICR_GPIOTE_CH_OWN_CH21_NotOwn (0x1UL)     /*!< Do not own the channel 21                                            */
80529   #define UICR_GPIOTE_CH_OWN_CH21_Own (0x0UL)        /*!< Own the channel 21                                                   */
80530 
80531 /* CH22 @Bit 22 : Channel number */
80532   #define UICR_GPIOTE_CH_OWN_CH22_Pos (22UL)         /*!< Position of CH22 field.                                              */
80533   #define UICR_GPIOTE_CH_OWN_CH22_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH22_Pos) /*!< Bit mask of CH22 field.                      */
80534   #define UICR_GPIOTE_CH_OWN_CH22_Min (0x0UL)        /*!< Min enumerator value of CH22 field.                                  */
80535   #define UICR_GPIOTE_CH_OWN_CH22_Max (0x1UL)        /*!< Max enumerator value of CH22 field.                                  */
80536   #define UICR_GPIOTE_CH_OWN_CH22_NotOwn (0x1UL)     /*!< Do not own the channel 22                                            */
80537   #define UICR_GPIOTE_CH_OWN_CH22_Own (0x0UL)        /*!< Own the channel 22                                                   */
80538 
80539 /* CH23 @Bit 23 : Channel number */
80540   #define UICR_GPIOTE_CH_OWN_CH23_Pos (23UL)         /*!< Position of CH23 field.                                              */
80541   #define UICR_GPIOTE_CH_OWN_CH23_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH23_Pos) /*!< Bit mask of CH23 field.                      */
80542   #define UICR_GPIOTE_CH_OWN_CH23_Min (0x0UL)        /*!< Min enumerator value of CH23 field.                                  */
80543   #define UICR_GPIOTE_CH_OWN_CH23_Max (0x1UL)        /*!< Max enumerator value of CH23 field.                                  */
80544   #define UICR_GPIOTE_CH_OWN_CH23_NotOwn (0x1UL)     /*!< Do not own the channel 23                                            */
80545   #define UICR_GPIOTE_CH_OWN_CH23_Own (0x0UL)        /*!< Own the channel 23                                                   */
80546 
80547 /* CH24 @Bit 24 : Channel number */
80548   #define UICR_GPIOTE_CH_OWN_CH24_Pos (24UL)         /*!< Position of CH24 field.                                              */
80549   #define UICR_GPIOTE_CH_OWN_CH24_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH24_Pos) /*!< Bit mask of CH24 field.                      */
80550   #define UICR_GPIOTE_CH_OWN_CH24_Min (0x0UL)        /*!< Min enumerator value of CH24 field.                                  */
80551   #define UICR_GPIOTE_CH_OWN_CH24_Max (0x1UL)        /*!< Max enumerator value of CH24 field.                                  */
80552   #define UICR_GPIOTE_CH_OWN_CH24_NotOwn (0x1UL)     /*!< Do not own the channel 24                                            */
80553   #define UICR_GPIOTE_CH_OWN_CH24_Own (0x0UL)        /*!< Own the channel 24                                                   */
80554 
80555 /* CH25 @Bit 25 : Channel number */
80556   #define UICR_GPIOTE_CH_OWN_CH25_Pos (25UL)         /*!< Position of CH25 field.                                              */
80557   #define UICR_GPIOTE_CH_OWN_CH25_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH25_Pos) /*!< Bit mask of CH25 field.                      */
80558   #define UICR_GPIOTE_CH_OWN_CH25_Min (0x0UL)        /*!< Min enumerator value of CH25 field.                                  */
80559   #define UICR_GPIOTE_CH_OWN_CH25_Max (0x1UL)        /*!< Max enumerator value of CH25 field.                                  */
80560   #define UICR_GPIOTE_CH_OWN_CH25_NotOwn (0x1UL)     /*!< Do not own the channel 25                                            */
80561   #define UICR_GPIOTE_CH_OWN_CH25_Own (0x0UL)        /*!< Own the channel 25                                                   */
80562 
80563 /* CH26 @Bit 26 : Channel number */
80564   #define UICR_GPIOTE_CH_OWN_CH26_Pos (26UL)         /*!< Position of CH26 field.                                              */
80565   #define UICR_GPIOTE_CH_OWN_CH26_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH26_Pos) /*!< Bit mask of CH26 field.                      */
80566   #define UICR_GPIOTE_CH_OWN_CH26_Min (0x0UL)        /*!< Min enumerator value of CH26 field.                                  */
80567   #define UICR_GPIOTE_CH_OWN_CH26_Max (0x1UL)        /*!< Max enumerator value of CH26 field.                                  */
80568   #define UICR_GPIOTE_CH_OWN_CH26_NotOwn (0x1UL)     /*!< Do not own the channel 26                                            */
80569   #define UICR_GPIOTE_CH_OWN_CH26_Own (0x0UL)        /*!< Own the channel 26                                                   */
80570 
80571 /* CH27 @Bit 27 : Channel number */
80572   #define UICR_GPIOTE_CH_OWN_CH27_Pos (27UL)         /*!< Position of CH27 field.                                              */
80573   #define UICR_GPIOTE_CH_OWN_CH27_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH27_Pos) /*!< Bit mask of CH27 field.                      */
80574   #define UICR_GPIOTE_CH_OWN_CH27_Min (0x0UL)        /*!< Min enumerator value of CH27 field.                                  */
80575   #define UICR_GPIOTE_CH_OWN_CH27_Max (0x1UL)        /*!< Max enumerator value of CH27 field.                                  */
80576   #define UICR_GPIOTE_CH_OWN_CH27_NotOwn (0x1UL)     /*!< Do not own the channel 27                                            */
80577   #define UICR_GPIOTE_CH_OWN_CH27_Own (0x0UL)        /*!< Own the channel 27                                                   */
80578 
80579 /* CH28 @Bit 28 : Channel number */
80580   #define UICR_GPIOTE_CH_OWN_CH28_Pos (28UL)         /*!< Position of CH28 field.                                              */
80581   #define UICR_GPIOTE_CH_OWN_CH28_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH28_Pos) /*!< Bit mask of CH28 field.                      */
80582   #define UICR_GPIOTE_CH_OWN_CH28_Min (0x0UL)        /*!< Min enumerator value of CH28 field.                                  */
80583   #define UICR_GPIOTE_CH_OWN_CH28_Max (0x1UL)        /*!< Max enumerator value of CH28 field.                                  */
80584   #define UICR_GPIOTE_CH_OWN_CH28_NotOwn (0x1UL)     /*!< Do not own the channel 28                                            */
80585   #define UICR_GPIOTE_CH_OWN_CH28_Own (0x0UL)        /*!< Own the channel 28                                                   */
80586 
80587 /* CH29 @Bit 29 : Channel number */
80588   #define UICR_GPIOTE_CH_OWN_CH29_Pos (29UL)         /*!< Position of CH29 field.                                              */
80589   #define UICR_GPIOTE_CH_OWN_CH29_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH29_Pos) /*!< Bit mask of CH29 field.                      */
80590   #define UICR_GPIOTE_CH_OWN_CH29_Min (0x0UL)        /*!< Min enumerator value of CH29 field.                                  */
80591   #define UICR_GPIOTE_CH_OWN_CH29_Max (0x1UL)        /*!< Max enumerator value of CH29 field.                                  */
80592   #define UICR_GPIOTE_CH_OWN_CH29_NotOwn (0x1UL)     /*!< Do not own the channel 29                                            */
80593   #define UICR_GPIOTE_CH_OWN_CH29_Own (0x0UL)        /*!< Own the channel 29                                                   */
80594 
80595 /* CH30 @Bit 30 : Channel number */
80596   #define UICR_GPIOTE_CH_OWN_CH30_Pos (30UL)         /*!< Position of CH30 field.                                              */
80597   #define UICR_GPIOTE_CH_OWN_CH30_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH30_Pos) /*!< Bit mask of CH30 field.                      */
80598   #define UICR_GPIOTE_CH_OWN_CH30_Min (0x0UL)        /*!< Min enumerator value of CH30 field.                                  */
80599   #define UICR_GPIOTE_CH_OWN_CH30_Max (0x1UL)        /*!< Max enumerator value of CH30 field.                                  */
80600   #define UICR_GPIOTE_CH_OWN_CH30_NotOwn (0x1UL)     /*!< Do not own the channel 30                                            */
80601   #define UICR_GPIOTE_CH_OWN_CH30_Own (0x0UL)        /*!< Own the channel 30                                                   */
80602 
80603 /* CH31 @Bit 31 : Channel number */
80604   #define UICR_GPIOTE_CH_OWN_CH31_Pos (31UL)         /*!< Position of CH31 field.                                              */
80605   #define UICR_GPIOTE_CH_OWN_CH31_Msk (0x1UL << UICR_GPIOTE_CH_OWN_CH31_Pos) /*!< Bit mask of CH31 field.                      */
80606   #define UICR_GPIOTE_CH_OWN_CH31_Min (0x0UL)        /*!< Min enumerator value of CH31 field.                                  */
80607   #define UICR_GPIOTE_CH_OWN_CH31_Max (0x1UL)        /*!< Max enumerator value of CH31 field.                                  */
80608   #define UICR_GPIOTE_CH_OWN_CH31_NotOwn (0x1UL)     /*!< Do not own the channel 31                                            */
80609   #define UICR_GPIOTE_CH_OWN_CH31_Own (0x0UL)        /*!< Own the channel 31                                                   */
80610 
80611 
80612 /* UICR_GPIOTE_CH_SECURE: Request permission for the channels of GPIOTE[n] */
80613   #define UICR_GPIOTE_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                                 */
80614 
80615 /* CH0 @Bit 0 : Channel number */
80616   #define UICR_GPIOTE_CH_SECURE_CH0_Pos (0UL)        /*!< Position of CH0 field.                                               */
80617   #define UICR_GPIOTE_CH_SECURE_CH0_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field.                   */
80618   #define UICR_GPIOTE_CH_SECURE_CH0_Min (0x0UL)      /*!< Min enumerator value of CH0 field.                                   */
80619   #define UICR_GPIOTE_CH_SECURE_CH0_Max (0x1UL)      /*!< Max enumerator value of CH0 field.                                   */
80620   #define UICR_GPIOTE_CH_SECURE_CH0_Secure (0x1UL)   /*!< The channel 0 is secure                                              */
80621   #define UICR_GPIOTE_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure                                         */
80622 
80623 /* CH1 @Bit 1 : Channel number */
80624   #define UICR_GPIOTE_CH_SECURE_CH1_Pos (1UL)        /*!< Position of CH1 field.                                               */
80625   #define UICR_GPIOTE_CH_SECURE_CH1_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field.                   */
80626   #define UICR_GPIOTE_CH_SECURE_CH1_Min (0x0UL)      /*!< Min enumerator value of CH1 field.                                   */
80627   #define UICR_GPIOTE_CH_SECURE_CH1_Max (0x1UL)      /*!< Max enumerator value of CH1 field.                                   */
80628   #define UICR_GPIOTE_CH_SECURE_CH1_Secure (0x1UL)   /*!< The channel 1 is secure                                              */
80629   #define UICR_GPIOTE_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure                                         */
80630 
80631 /* CH2 @Bit 2 : Channel number */
80632   #define UICR_GPIOTE_CH_SECURE_CH2_Pos (2UL)        /*!< Position of CH2 field.                                               */
80633   #define UICR_GPIOTE_CH_SECURE_CH2_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field.                   */
80634   #define UICR_GPIOTE_CH_SECURE_CH2_Min (0x0UL)      /*!< Min enumerator value of CH2 field.                                   */
80635   #define UICR_GPIOTE_CH_SECURE_CH2_Max (0x1UL)      /*!< Max enumerator value of CH2 field.                                   */
80636   #define UICR_GPIOTE_CH_SECURE_CH2_Secure (0x1UL)   /*!< The channel 2 is secure                                              */
80637   #define UICR_GPIOTE_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure                                         */
80638 
80639 /* CH3 @Bit 3 : Channel number */
80640   #define UICR_GPIOTE_CH_SECURE_CH3_Pos (3UL)        /*!< Position of CH3 field.                                               */
80641   #define UICR_GPIOTE_CH_SECURE_CH3_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field.                   */
80642   #define UICR_GPIOTE_CH_SECURE_CH3_Min (0x0UL)      /*!< Min enumerator value of CH3 field.                                   */
80643   #define UICR_GPIOTE_CH_SECURE_CH3_Max (0x1UL)      /*!< Max enumerator value of CH3 field.                                   */
80644   #define UICR_GPIOTE_CH_SECURE_CH3_Secure (0x1UL)   /*!< The channel 3 is secure                                              */
80645   #define UICR_GPIOTE_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure                                         */
80646 
80647 /* CH4 @Bit 4 : Channel number */
80648   #define UICR_GPIOTE_CH_SECURE_CH4_Pos (4UL)        /*!< Position of CH4 field.                                               */
80649   #define UICR_GPIOTE_CH_SECURE_CH4_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field.                   */
80650   #define UICR_GPIOTE_CH_SECURE_CH4_Min (0x0UL)      /*!< Min enumerator value of CH4 field.                                   */
80651   #define UICR_GPIOTE_CH_SECURE_CH4_Max (0x1UL)      /*!< Max enumerator value of CH4 field.                                   */
80652   #define UICR_GPIOTE_CH_SECURE_CH4_Secure (0x1UL)   /*!< The channel 4 is secure                                              */
80653   #define UICR_GPIOTE_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure                                         */
80654 
80655 /* CH5 @Bit 5 : Channel number */
80656   #define UICR_GPIOTE_CH_SECURE_CH5_Pos (5UL)        /*!< Position of CH5 field.                                               */
80657   #define UICR_GPIOTE_CH_SECURE_CH5_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field.                   */
80658   #define UICR_GPIOTE_CH_SECURE_CH5_Min (0x0UL)      /*!< Min enumerator value of CH5 field.                                   */
80659   #define UICR_GPIOTE_CH_SECURE_CH5_Max (0x1UL)      /*!< Max enumerator value of CH5 field.                                   */
80660   #define UICR_GPIOTE_CH_SECURE_CH5_Secure (0x1UL)   /*!< The channel 5 is secure                                              */
80661   #define UICR_GPIOTE_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure                                         */
80662 
80663 /* CH6 @Bit 6 : Channel number */
80664   #define UICR_GPIOTE_CH_SECURE_CH6_Pos (6UL)        /*!< Position of CH6 field.                                               */
80665   #define UICR_GPIOTE_CH_SECURE_CH6_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field.                   */
80666   #define UICR_GPIOTE_CH_SECURE_CH6_Min (0x0UL)      /*!< Min enumerator value of CH6 field.                                   */
80667   #define UICR_GPIOTE_CH_SECURE_CH6_Max (0x1UL)      /*!< Max enumerator value of CH6 field.                                   */
80668   #define UICR_GPIOTE_CH_SECURE_CH6_Secure (0x1UL)   /*!< The channel 6 is secure                                              */
80669   #define UICR_GPIOTE_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure                                         */
80670 
80671 /* CH7 @Bit 7 : Channel number */
80672   #define UICR_GPIOTE_CH_SECURE_CH7_Pos (7UL)        /*!< Position of CH7 field.                                               */
80673   #define UICR_GPIOTE_CH_SECURE_CH7_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field.                   */
80674   #define UICR_GPIOTE_CH_SECURE_CH7_Min (0x0UL)      /*!< Min enumerator value of CH7 field.                                   */
80675   #define UICR_GPIOTE_CH_SECURE_CH7_Max (0x1UL)      /*!< Max enumerator value of CH7 field.                                   */
80676   #define UICR_GPIOTE_CH_SECURE_CH7_Secure (0x1UL)   /*!< The channel 7 is secure                                              */
80677   #define UICR_GPIOTE_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure                                         */
80678 
80679 /* CH8 @Bit 8 : Channel number */
80680   #define UICR_GPIOTE_CH_SECURE_CH8_Pos (8UL)        /*!< Position of CH8 field.                                               */
80681   #define UICR_GPIOTE_CH_SECURE_CH8_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field.                   */
80682   #define UICR_GPIOTE_CH_SECURE_CH8_Min (0x0UL)      /*!< Min enumerator value of CH8 field.                                   */
80683   #define UICR_GPIOTE_CH_SECURE_CH8_Max (0x1UL)      /*!< Max enumerator value of CH8 field.                                   */
80684   #define UICR_GPIOTE_CH_SECURE_CH8_Secure (0x1UL)   /*!< The channel 8 is secure                                              */
80685   #define UICR_GPIOTE_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure                                         */
80686 
80687 /* CH9 @Bit 9 : Channel number */
80688   #define UICR_GPIOTE_CH_SECURE_CH9_Pos (9UL)        /*!< Position of CH9 field.                                               */
80689   #define UICR_GPIOTE_CH_SECURE_CH9_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field.                   */
80690   #define UICR_GPIOTE_CH_SECURE_CH9_Min (0x0UL)      /*!< Min enumerator value of CH9 field.                                   */
80691   #define UICR_GPIOTE_CH_SECURE_CH9_Max (0x1UL)      /*!< Max enumerator value of CH9 field.                                   */
80692   #define UICR_GPIOTE_CH_SECURE_CH9_Secure (0x1UL)   /*!< The channel 9 is secure                                              */
80693   #define UICR_GPIOTE_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure                                         */
80694 
80695 /* CH10 @Bit 10 : Channel number */
80696   #define UICR_GPIOTE_CH_SECURE_CH10_Pos (10UL)      /*!< Position of CH10 field.                                              */
80697   #define UICR_GPIOTE_CH_SECURE_CH10_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field.                */
80698   #define UICR_GPIOTE_CH_SECURE_CH10_Min (0x0UL)     /*!< Min enumerator value of CH10 field.                                  */
80699   #define UICR_GPIOTE_CH_SECURE_CH10_Max (0x1UL)     /*!< Max enumerator value of CH10 field.                                  */
80700   #define UICR_GPIOTE_CH_SECURE_CH10_Secure (0x1UL)  /*!< The channel 10 is secure                                             */
80701   #define UICR_GPIOTE_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure                                       */
80702 
80703 /* CH11 @Bit 11 : Channel number */
80704   #define UICR_GPIOTE_CH_SECURE_CH11_Pos (11UL)      /*!< Position of CH11 field.                                              */
80705   #define UICR_GPIOTE_CH_SECURE_CH11_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field.                */
80706   #define UICR_GPIOTE_CH_SECURE_CH11_Min (0x0UL)     /*!< Min enumerator value of CH11 field.                                  */
80707   #define UICR_GPIOTE_CH_SECURE_CH11_Max (0x1UL)     /*!< Max enumerator value of CH11 field.                                  */
80708   #define UICR_GPIOTE_CH_SECURE_CH11_Secure (0x1UL)  /*!< The channel 11 is secure                                             */
80709   #define UICR_GPIOTE_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure                                       */
80710 
80711 /* CH12 @Bit 12 : Channel number */
80712   #define UICR_GPIOTE_CH_SECURE_CH12_Pos (12UL)      /*!< Position of CH12 field.                                              */
80713   #define UICR_GPIOTE_CH_SECURE_CH12_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field.                */
80714   #define UICR_GPIOTE_CH_SECURE_CH12_Min (0x0UL)     /*!< Min enumerator value of CH12 field.                                  */
80715   #define UICR_GPIOTE_CH_SECURE_CH12_Max (0x1UL)     /*!< Max enumerator value of CH12 field.                                  */
80716   #define UICR_GPIOTE_CH_SECURE_CH12_Secure (0x1UL)  /*!< The channel 12 is secure                                             */
80717   #define UICR_GPIOTE_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure                                       */
80718 
80719 /* CH13 @Bit 13 : Channel number */
80720   #define UICR_GPIOTE_CH_SECURE_CH13_Pos (13UL)      /*!< Position of CH13 field.                                              */
80721   #define UICR_GPIOTE_CH_SECURE_CH13_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field.                */
80722   #define UICR_GPIOTE_CH_SECURE_CH13_Min (0x0UL)     /*!< Min enumerator value of CH13 field.                                  */
80723   #define UICR_GPIOTE_CH_SECURE_CH13_Max (0x1UL)     /*!< Max enumerator value of CH13 field.                                  */
80724   #define UICR_GPIOTE_CH_SECURE_CH13_Secure (0x1UL)  /*!< The channel 13 is secure                                             */
80725   #define UICR_GPIOTE_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure                                       */
80726 
80727 /* CH14 @Bit 14 : Channel number */
80728   #define UICR_GPIOTE_CH_SECURE_CH14_Pos (14UL)      /*!< Position of CH14 field.                                              */
80729   #define UICR_GPIOTE_CH_SECURE_CH14_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field.                */
80730   #define UICR_GPIOTE_CH_SECURE_CH14_Min (0x0UL)     /*!< Min enumerator value of CH14 field.                                  */
80731   #define UICR_GPIOTE_CH_SECURE_CH14_Max (0x1UL)     /*!< Max enumerator value of CH14 field.                                  */
80732   #define UICR_GPIOTE_CH_SECURE_CH14_Secure (0x1UL)  /*!< The channel 14 is secure                                             */
80733   #define UICR_GPIOTE_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure                                       */
80734 
80735 /* CH15 @Bit 15 : Channel number */
80736   #define UICR_GPIOTE_CH_SECURE_CH15_Pos (15UL)      /*!< Position of CH15 field.                                              */
80737   #define UICR_GPIOTE_CH_SECURE_CH15_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field.                */
80738   #define UICR_GPIOTE_CH_SECURE_CH15_Min (0x0UL)     /*!< Min enumerator value of CH15 field.                                  */
80739   #define UICR_GPIOTE_CH_SECURE_CH15_Max (0x1UL)     /*!< Max enumerator value of CH15 field.                                  */
80740   #define UICR_GPIOTE_CH_SECURE_CH15_Secure (0x1UL)  /*!< The channel 15 is secure                                             */
80741   #define UICR_GPIOTE_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure                                       */
80742 
80743 /* CH16 @Bit 16 : Channel number */
80744   #define UICR_GPIOTE_CH_SECURE_CH16_Pos (16UL)      /*!< Position of CH16 field.                                              */
80745   #define UICR_GPIOTE_CH_SECURE_CH16_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field.                */
80746   #define UICR_GPIOTE_CH_SECURE_CH16_Min (0x0UL)     /*!< Min enumerator value of CH16 field.                                  */
80747   #define UICR_GPIOTE_CH_SECURE_CH16_Max (0x1UL)     /*!< Max enumerator value of CH16 field.                                  */
80748   #define UICR_GPIOTE_CH_SECURE_CH16_Secure (0x1UL)  /*!< The channel 16 is secure                                             */
80749   #define UICR_GPIOTE_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure                                       */
80750 
80751 /* CH17 @Bit 17 : Channel number */
80752   #define UICR_GPIOTE_CH_SECURE_CH17_Pos (17UL)      /*!< Position of CH17 field.                                              */
80753   #define UICR_GPIOTE_CH_SECURE_CH17_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field.                */
80754   #define UICR_GPIOTE_CH_SECURE_CH17_Min (0x0UL)     /*!< Min enumerator value of CH17 field.                                  */
80755   #define UICR_GPIOTE_CH_SECURE_CH17_Max (0x1UL)     /*!< Max enumerator value of CH17 field.                                  */
80756   #define UICR_GPIOTE_CH_SECURE_CH17_Secure (0x1UL)  /*!< The channel 17 is secure                                             */
80757   #define UICR_GPIOTE_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure                                       */
80758 
80759 /* CH18 @Bit 18 : Channel number */
80760   #define UICR_GPIOTE_CH_SECURE_CH18_Pos (18UL)      /*!< Position of CH18 field.                                              */
80761   #define UICR_GPIOTE_CH_SECURE_CH18_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field.                */
80762   #define UICR_GPIOTE_CH_SECURE_CH18_Min (0x0UL)     /*!< Min enumerator value of CH18 field.                                  */
80763   #define UICR_GPIOTE_CH_SECURE_CH18_Max (0x1UL)     /*!< Max enumerator value of CH18 field.                                  */
80764   #define UICR_GPIOTE_CH_SECURE_CH18_Secure (0x1UL)  /*!< The channel 18 is secure                                             */
80765   #define UICR_GPIOTE_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure                                       */
80766 
80767 /* CH19 @Bit 19 : Channel number */
80768   #define UICR_GPIOTE_CH_SECURE_CH19_Pos (19UL)      /*!< Position of CH19 field.                                              */
80769   #define UICR_GPIOTE_CH_SECURE_CH19_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field.                */
80770   #define UICR_GPIOTE_CH_SECURE_CH19_Min (0x0UL)     /*!< Min enumerator value of CH19 field.                                  */
80771   #define UICR_GPIOTE_CH_SECURE_CH19_Max (0x1UL)     /*!< Max enumerator value of CH19 field.                                  */
80772   #define UICR_GPIOTE_CH_SECURE_CH19_Secure (0x1UL)  /*!< The channel 19 is secure                                             */
80773   #define UICR_GPIOTE_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure                                       */
80774 
80775 /* CH20 @Bit 20 : Channel number */
80776   #define UICR_GPIOTE_CH_SECURE_CH20_Pos (20UL)      /*!< Position of CH20 field.                                              */
80777   #define UICR_GPIOTE_CH_SECURE_CH20_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field.                */
80778   #define UICR_GPIOTE_CH_SECURE_CH20_Min (0x0UL)     /*!< Min enumerator value of CH20 field.                                  */
80779   #define UICR_GPIOTE_CH_SECURE_CH20_Max (0x1UL)     /*!< Max enumerator value of CH20 field.                                  */
80780   #define UICR_GPIOTE_CH_SECURE_CH20_Secure (0x1UL)  /*!< The channel 20 is secure                                             */
80781   #define UICR_GPIOTE_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure                                       */
80782 
80783 /* CH21 @Bit 21 : Channel number */
80784   #define UICR_GPIOTE_CH_SECURE_CH21_Pos (21UL)      /*!< Position of CH21 field.                                              */
80785   #define UICR_GPIOTE_CH_SECURE_CH21_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field.                */
80786   #define UICR_GPIOTE_CH_SECURE_CH21_Min (0x0UL)     /*!< Min enumerator value of CH21 field.                                  */
80787   #define UICR_GPIOTE_CH_SECURE_CH21_Max (0x1UL)     /*!< Max enumerator value of CH21 field.                                  */
80788   #define UICR_GPIOTE_CH_SECURE_CH21_Secure (0x1UL)  /*!< The channel 21 is secure                                             */
80789   #define UICR_GPIOTE_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure                                       */
80790 
80791 /* CH22 @Bit 22 : Channel number */
80792   #define UICR_GPIOTE_CH_SECURE_CH22_Pos (22UL)      /*!< Position of CH22 field.                                              */
80793   #define UICR_GPIOTE_CH_SECURE_CH22_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field.                */
80794   #define UICR_GPIOTE_CH_SECURE_CH22_Min (0x0UL)     /*!< Min enumerator value of CH22 field.                                  */
80795   #define UICR_GPIOTE_CH_SECURE_CH22_Max (0x1UL)     /*!< Max enumerator value of CH22 field.                                  */
80796   #define UICR_GPIOTE_CH_SECURE_CH22_Secure (0x1UL)  /*!< The channel 22 is secure                                             */
80797   #define UICR_GPIOTE_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure                                       */
80798 
80799 /* CH23 @Bit 23 : Channel number */
80800   #define UICR_GPIOTE_CH_SECURE_CH23_Pos (23UL)      /*!< Position of CH23 field.                                              */
80801   #define UICR_GPIOTE_CH_SECURE_CH23_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field.                */
80802   #define UICR_GPIOTE_CH_SECURE_CH23_Min (0x0UL)     /*!< Min enumerator value of CH23 field.                                  */
80803   #define UICR_GPIOTE_CH_SECURE_CH23_Max (0x1UL)     /*!< Max enumerator value of CH23 field.                                  */
80804   #define UICR_GPIOTE_CH_SECURE_CH23_Secure (0x1UL)  /*!< The channel 23 is secure                                             */
80805   #define UICR_GPIOTE_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure                                       */
80806 
80807 /* CH24 @Bit 24 : Channel number */
80808   #define UICR_GPIOTE_CH_SECURE_CH24_Pos (24UL)      /*!< Position of CH24 field.                                              */
80809   #define UICR_GPIOTE_CH_SECURE_CH24_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field.                */
80810   #define UICR_GPIOTE_CH_SECURE_CH24_Min (0x0UL)     /*!< Min enumerator value of CH24 field.                                  */
80811   #define UICR_GPIOTE_CH_SECURE_CH24_Max (0x1UL)     /*!< Max enumerator value of CH24 field.                                  */
80812   #define UICR_GPIOTE_CH_SECURE_CH24_Secure (0x1UL)  /*!< The channel 24 is secure                                             */
80813   #define UICR_GPIOTE_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure                                       */
80814 
80815 /* CH25 @Bit 25 : Channel number */
80816   #define UICR_GPIOTE_CH_SECURE_CH25_Pos (25UL)      /*!< Position of CH25 field.                                              */
80817   #define UICR_GPIOTE_CH_SECURE_CH25_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field.                */
80818   #define UICR_GPIOTE_CH_SECURE_CH25_Min (0x0UL)     /*!< Min enumerator value of CH25 field.                                  */
80819   #define UICR_GPIOTE_CH_SECURE_CH25_Max (0x1UL)     /*!< Max enumerator value of CH25 field.                                  */
80820   #define UICR_GPIOTE_CH_SECURE_CH25_Secure (0x1UL)  /*!< The channel 25 is secure                                             */
80821   #define UICR_GPIOTE_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure                                       */
80822 
80823 /* CH26 @Bit 26 : Channel number */
80824   #define UICR_GPIOTE_CH_SECURE_CH26_Pos (26UL)      /*!< Position of CH26 field.                                              */
80825   #define UICR_GPIOTE_CH_SECURE_CH26_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field.                */
80826   #define UICR_GPIOTE_CH_SECURE_CH26_Min (0x0UL)     /*!< Min enumerator value of CH26 field.                                  */
80827   #define UICR_GPIOTE_CH_SECURE_CH26_Max (0x1UL)     /*!< Max enumerator value of CH26 field.                                  */
80828   #define UICR_GPIOTE_CH_SECURE_CH26_Secure (0x1UL)  /*!< The channel 26 is secure                                             */
80829   #define UICR_GPIOTE_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure                                       */
80830 
80831 /* CH27 @Bit 27 : Channel number */
80832   #define UICR_GPIOTE_CH_SECURE_CH27_Pos (27UL)      /*!< Position of CH27 field.                                              */
80833   #define UICR_GPIOTE_CH_SECURE_CH27_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field.                */
80834   #define UICR_GPIOTE_CH_SECURE_CH27_Min (0x0UL)     /*!< Min enumerator value of CH27 field.                                  */
80835   #define UICR_GPIOTE_CH_SECURE_CH27_Max (0x1UL)     /*!< Max enumerator value of CH27 field.                                  */
80836   #define UICR_GPIOTE_CH_SECURE_CH27_Secure (0x1UL)  /*!< The channel 27 is secure                                             */
80837   #define UICR_GPIOTE_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure                                       */
80838 
80839 /* CH28 @Bit 28 : Channel number */
80840   #define UICR_GPIOTE_CH_SECURE_CH28_Pos (28UL)      /*!< Position of CH28 field.                                              */
80841   #define UICR_GPIOTE_CH_SECURE_CH28_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field.                */
80842   #define UICR_GPIOTE_CH_SECURE_CH28_Min (0x0UL)     /*!< Min enumerator value of CH28 field.                                  */
80843   #define UICR_GPIOTE_CH_SECURE_CH28_Max (0x1UL)     /*!< Max enumerator value of CH28 field.                                  */
80844   #define UICR_GPIOTE_CH_SECURE_CH28_Secure (0x1UL)  /*!< The channel 28 is secure                                             */
80845   #define UICR_GPIOTE_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure                                       */
80846 
80847 /* CH29 @Bit 29 : Channel number */
80848   #define UICR_GPIOTE_CH_SECURE_CH29_Pos (29UL)      /*!< Position of CH29 field.                                              */
80849   #define UICR_GPIOTE_CH_SECURE_CH29_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field.                */
80850   #define UICR_GPIOTE_CH_SECURE_CH29_Min (0x0UL)     /*!< Min enumerator value of CH29 field.                                  */
80851   #define UICR_GPIOTE_CH_SECURE_CH29_Max (0x1UL)     /*!< Max enumerator value of CH29 field.                                  */
80852   #define UICR_GPIOTE_CH_SECURE_CH29_Secure (0x1UL)  /*!< The channel 29 is secure                                             */
80853   #define UICR_GPIOTE_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure                                       */
80854 
80855 /* CH30 @Bit 30 : Channel number */
80856   #define UICR_GPIOTE_CH_SECURE_CH30_Pos (30UL)      /*!< Position of CH30 field.                                              */
80857   #define UICR_GPIOTE_CH_SECURE_CH30_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field.                */
80858   #define UICR_GPIOTE_CH_SECURE_CH30_Min (0x0UL)     /*!< Min enumerator value of CH30 field.                                  */
80859   #define UICR_GPIOTE_CH_SECURE_CH30_Max (0x1UL)     /*!< Max enumerator value of CH30 field.                                  */
80860   #define UICR_GPIOTE_CH_SECURE_CH30_Secure (0x1UL)  /*!< The channel 30 is secure                                             */
80861   #define UICR_GPIOTE_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure                                       */
80862 
80863 /* CH31 @Bit 31 : Channel number */
80864   #define UICR_GPIOTE_CH_SECURE_CH31_Pos (31UL)      /*!< Position of CH31 field.                                              */
80865   #define UICR_GPIOTE_CH_SECURE_CH31_Msk (0x1UL << UICR_GPIOTE_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field.                */
80866   #define UICR_GPIOTE_CH_SECURE_CH31_Min (0x0UL)     /*!< Min enumerator value of CH31 field.                                  */
80867   #define UICR_GPIOTE_CH_SECURE_CH31_Max (0x1UL)     /*!< Max enumerator value of CH31 field.                                  */
80868   #define UICR_GPIOTE_CH_SECURE_CH31_Secure (0x1UL)  /*!< The channel 31 is secure                                             */
80869   #define UICR_GPIOTE_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure                                       */
80870 
80871 
80872 
80873 /* =================================================== Struct UICR_GPIOTE ==================================================== */
80874 /**
80875   * @brief GPIOTE [UICR_GPIOTE] (unspecified)
80876   */
80877 typedef struct {
80878   __IOM uint32_t  INSTANCE;                          /*!< (@ 0x00000000) Address of the GPIOTE instance associated with
80879                                                                          GPIOTE[n]*/
80880   __IOM NRF_UICR_GPIOTE_CH_Type CH;                  /*!< (@ 0x00000004) (unspecified)                                         */
80881 } NRF_UICR_GPIOTE_Type;                              /*!< Size = 12 (0x00C)                                                    */
80882   #define UICR_GPIOTE_MaxCount (4UL)                 /*!< Size of GPIOTE[4] array.                                             */
80883   #define UICR_GPIOTE_MaxIndex (3UL)                 /*!< Max index of GPIOTE[4] array.                                        */
80884   #define UICR_GPIOTE_MinIndex (0UL)                 /*!< Min index of GPIOTE[4] array.                                        */
80885 
80886 /* UICR_GPIOTE_INSTANCE: Address of the GPIOTE instance associated with GPIOTE[n] */
80887   #define UICR_GPIOTE_INSTANCE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INSTANCE register.                                */
80888 
80889 /* ADDRESS @Bits 0..31 : Instance address */
80890   #define UICR_GPIOTE_INSTANCE_ADDRESS_Pos (0UL)     /*!< Position of ADDRESS field.                                           */
80891   #define UICR_GPIOTE_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICR_GPIOTE_INSTANCE_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.  */
80892 
80893 
80894 
80895 /* ================================================ Struct UICR_IPCT_LOCAL_CH ================================================ */
80896 /**
80897   * @brief CH [UICR_IPCT_LOCAL_CH] (unspecified)
80898   */
80899 typedef struct {
80900   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000000) Request permission for the channels of IPCT in the
80901                                                                          local domain*/
80902 } NRF_UICR_IPCT_LOCAL_CH_Type;                       /*!< Size = 4 (0x004)                                                     */
80903 
80904 /* UICR_IPCT_LOCAL_CH_SECURE: Request permission for the channels of IPCT in the local domain */
80905   #define UICR_IPCT_LOCAL_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                             */
80906 
80907 /* CH0 @Bit 0 : Channel number */
80908   #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Pos (0UL)    /*!< Position of CH0 field.                                               */
80909   #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field.           */
80910   #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Min (0x0UL)  /*!< Min enumerator value of CH0 field.                                   */
80911   #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Max (0x1UL)  /*!< Max enumerator value of CH0 field.                                   */
80912   #define UICR_IPCT_LOCAL_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure                                            */
80913   #define UICR_IPCT_LOCAL_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure                                     */
80914 
80915 /* CH1 @Bit 1 : Channel number */
80916   #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Pos (1UL)    /*!< Position of CH1 field.                                               */
80917   #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field.           */
80918   #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Min (0x0UL)  /*!< Min enumerator value of CH1 field.                                   */
80919   #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Max (0x1UL)  /*!< Max enumerator value of CH1 field.                                   */
80920   #define UICR_IPCT_LOCAL_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure                                            */
80921   #define UICR_IPCT_LOCAL_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure                                     */
80922 
80923 /* CH2 @Bit 2 : Channel number */
80924   #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Pos (2UL)    /*!< Position of CH2 field.                                               */
80925   #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field.           */
80926   #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Min (0x0UL)  /*!< Min enumerator value of CH2 field.                                   */
80927   #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Max (0x1UL)  /*!< Max enumerator value of CH2 field.                                   */
80928   #define UICR_IPCT_LOCAL_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure                                            */
80929   #define UICR_IPCT_LOCAL_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure                                     */
80930 
80931 /* CH3 @Bit 3 : Channel number */
80932   #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Pos (3UL)    /*!< Position of CH3 field.                                               */
80933   #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field.           */
80934   #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Min (0x0UL)  /*!< Min enumerator value of CH3 field.                                   */
80935   #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Max (0x1UL)  /*!< Max enumerator value of CH3 field.                                   */
80936   #define UICR_IPCT_LOCAL_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure                                            */
80937   #define UICR_IPCT_LOCAL_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure                                     */
80938 
80939 /* CH4 @Bit 4 : Channel number */
80940   #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Pos (4UL)    /*!< Position of CH4 field.                                               */
80941   #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field.           */
80942   #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Min (0x0UL)  /*!< Min enumerator value of CH4 field.                                   */
80943   #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Max (0x1UL)  /*!< Max enumerator value of CH4 field.                                   */
80944   #define UICR_IPCT_LOCAL_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure                                            */
80945   #define UICR_IPCT_LOCAL_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure                                     */
80946 
80947 /* CH5 @Bit 5 : Channel number */
80948   #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Pos (5UL)    /*!< Position of CH5 field.                                               */
80949   #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field.           */
80950   #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Min (0x0UL)  /*!< Min enumerator value of CH5 field.                                   */
80951   #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Max (0x1UL)  /*!< Max enumerator value of CH5 field.                                   */
80952   #define UICR_IPCT_LOCAL_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure                                            */
80953   #define UICR_IPCT_LOCAL_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure                                     */
80954 
80955 /* CH6 @Bit 6 : Channel number */
80956   #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Pos (6UL)    /*!< Position of CH6 field.                                               */
80957   #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field.           */
80958   #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Min (0x0UL)  /*!< Min enumerator value of CH6 field.                                   */
80959   #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Max (0x1UL)  /*!< Max enumerator value of CH6 field.                                   */
80960   #define UICR_IPCT_LOCAL_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure                                            */
80961   #define UICR_IPCT_LOCAL_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure                                     */
80962 
80963 /* CH7 @Bit 7 : Channel number */
80964   #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Pos (7UL)    /*!< Position of CH7 field.                                               */
80965   #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field.           */
80966   #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Min (0x0UL)  /*!< Min enumerator value of CH7 field.                                   */
80967   #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Max (0x1UL)  /*!< Max enumerator value of CH7 field.                                   */
80968   #define UICR_IPCT_LOCAL_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure                                            */
80969   #define UICR_IPCT_LOCAL_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure                                     */
80970 
80971 /* CH8 @Bit 8 : Channel number */
80972   #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Pos (8UL)    /*!< Position of CH8 field.                                               */
80973   #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field.           */
80974   #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Min (0x0UL)  /*!< Min enumerator value of CH8 field.                                   */
80975   #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Max (0x1UL)  /*!< Max enumerator value of CH8 field.                                   */
80976   #define UICR_IPCT_LOCAL_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure                                            */
80977   #define UICR_IPCT_LOCAL_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure                                     */
80978 
80979 /* CH9 @Bit 9 : Channel number */
80980   #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Pos (9UL)    /*!< Position of CH9 field.                                               */
80981   #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field.           */
80982   #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Min (0x0UL)  /*!< Min enumerator value of CH9 field.                                   */
80983   #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Max (0x1UL)  /*!< Max enumerator value of CH9 field.                                   */
80984   #define UICR_IPCT_LOCAL_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure                                            */
80985   #define UICR_IPCT_LOCAL_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure                                     */
80986 
80987 /* CH10 @Bit 10 : Channel number */
80988   #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Pos (10UL)  /*!< Position of CH10 field.                                              */
80989   #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field.        */
80990   #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field.                                  */
80991   #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field.                                  */
80992   #define UICR_IPCT_LOCAL_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure                                          */
80993   #define UICR_IPCT_LOCAL_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure                                   */
80994 
80995 /* CH11 @Bit 11 : Channel number */
80996   #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Pos (11UL)  /*!< Position of CH11 field.                                              */
80997   #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field.        */
80998   #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field.                                  */
80999   #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field.                                  */
81000   #define UICR_IPCT_LOCAL_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure                                          */
81001   #define UICR_IPCT_LOCAL_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure                                   */
81002 
81003 /* CH12 @Bit 12 : Channel number */
81004   #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Pos (12UL)  /*!< Position of CH12 field.                                              */
81005   #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field.        */
81006   #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field.                                  */
81007   #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field.                                  */
81008   #define UICR_IPCT_LOCAL_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure                                          */
81009   #define UICR_IPCT_LOCAL_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure                                   */
81010 
81011 /* CH13 @Bit 13 : Channel number */
81012   #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Pos (13UL)  /*!< Position of CH13 field.                                              */
81013   #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field.        */
81014   #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field.                                  */
81015   #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field.                                  */
81016   #define UICR_IPCT_LOCAL_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure                                          */
81017   #define UICR_IPCT_LOCAL_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure                                   */
81018 
81019 /* CH14 @Bit 14 : Channel number */
81020   #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Pos (14UL)  /*!< Position of CH14 field.                                              */
81021   #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field.        */
81022   #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field.                                  */
81023   #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field.                                  */
81024   #define UICR_IPCT_LOCAL_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure                                          */
81025   #define UICR_IPCT_LOCAL_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure                                   */
81026 
81027 /* CH15 @Bit 15 : Channel number */
81028   #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Pos (15UL)  /*!< Position of CH15 field.                                              */
81029   #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field.        */
81030   #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field.                                  */
81031   #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field.                                  */
81032   #define UICR_IPCT_LOCAL_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure                                          */
81033   #define UICR_IPCT_LOCAL_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure                                   */
81034 
81035 /* CH16 @Bit 16 : Channel number */
81036   #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Pos (16UL)  /*!< Position of CH16 field.                                              */
81037   #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field.        */
81038   #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field.                                  */
81039   #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field.                                  */
81040   #define UICR_IPCT_LOCAL_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure                                          */
81041   #define UICR_IPCT_LOCAL_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure                                   */
81042 
81043 /* CH17 @Bit 17 : Channel number */
81044   #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Pos (17UL)  /*!< Position of CH17 field.                                              */
81045   #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field.        */
81046   #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field.                                  */
81047   #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field.                                  */
81048   #define UICR_IPCT_LOCAL_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure                                          */
81049   #define UICR_IPCT_LOCAL_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure                                   */
81050 
81051 /* CH18 @Bit 18 : Channel number */
81052   #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Pos (18UL)  /*!< Position of CH18 field.                                              */
81053   #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field.        */
81054   #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field.                                  */
81055   #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field.                                  */
81056   #define UICR_IPCT_LOCAL_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure                                          */
81057   #define UICR_IPCT_LOCAL_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure                                   */
81058 
81059 /* CH19 @Bit 19 : Channel number */
81060   #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Pos (19UL)  /*!< Position of CH19 field.                                              */
81061   #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field.        */
81062   #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field.                                  */
81063   #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field.                                  */
81064   #define UICR_IPCT_LOCAL_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure                                          */
81065   #define UICR_IPCT_LOCAL_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure                                   */
81066 
81067 /* CH20 @Bit 20 : Channel number */
81068   #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Pos (20UL)  /*!< Position of CH20 field.                                              */
81069   #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field.        */
81070   #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field.                                  */
81071   #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field.                                  */
81072   #define UICR_IPCT_LOCAL_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure                                          */
81073   #define UICR_IPCT_LOCAL_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure                                   */
81074 
81075 /* CH21 @Bit 21 : Channel number */
81076   #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Pos (21UL)  /*!< Position of CH21 field.                                              */
81077   #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field.        */
81078   #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field.                                  */
81079   #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field.                                  */
81080   #define UICR_IPCT_LOCAL_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure                                          */
81081   #define UICR_IPCT_LOCAL_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure                                   */
81082 
81083 /* CH22 @Bit 22 : Channel number */
81084   #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Pos (22UL)  /*!< Position of CH22 field.                                              */
81085   #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field.        */
81086   #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field.                                  */
81087   #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field.                                  */
81088   #define UICR_IPCT_LOCAL_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure                                          */
81089   #define UICR_IPCT_LOCAL_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure                                   */
81090 
81091 /* CH23 @Bit 23 : Channel number */
81092   #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Pos (23UL)  /*!< Position of CH23 field.                                              */
81093   #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field.        */
81094   #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field.                                  */
81095   #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field.                                  */
81096   #define UICR_IPCT_LOCAL_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure                                          */
81097   #define UICR_IPCT_LOCAL_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure                                   */
81098 
81099 /* CH24 @Bit 24 : Channel number */
81100   #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Pos (24UL)  /*!< Position of CH24 field.                                              */
81101   #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field.        */
81102   #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field.                                  */
81103   #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field.                                  */
81104   #define UICR_IPCT_LOCAL_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure                                          */
81105   #define UICR_IPCT_LOCAL_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure                                   */
81106 
81107 /* CH25 @Bit 25 : Channel number */
81108   #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Pos (25UL)  /*!< Position of CH25 field.                                              */
81109   #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field.        */
81110   #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field.                                  */
81111   #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field.                                  */
81112   #define UICR_IPCT_LOCAL_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure                                          */
81113   #define UICR_IPCT_LOCAL_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure                                   */
81114 
81115 /* CH26 @Bit 26 : Channel number */
81116   #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Pos (26UL)  /*!< Position of CH26 field.                                              */
81117   #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field.        */
81118   #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field.                                  */
81119   #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field.                                  */
81120   #define UICR_IPCT_LOCAL_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure                                          */
81121   #define UICR_IPCT_LOCAL_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure                                   */
81122 
81123 /* CH27 @Bit 27 : Channel number */
81124   #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Pos (27UL)  /*!< Position of CH27 field.                                              */
81125   #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field.        */
81126   #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field.                                  */
81127   #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field.                                  */
81128   #define UICR_IPCT_LOCAL_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure                                          */
81129   #define UICR_IPCT_LOCAL_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure                                   */
81130 
81131 /* CH28 @Bit 28 : Channel number */
81132   #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Pos (28UL)  /*!< Position of CH28 field.                                              */
81133   #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field.        */
81134   #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field.                                  */
81135   #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field.                                  */
81136   #define UICR_IPCT_LOCAL_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure                                          */
81137   #define UICR_IPCT_LOCAL_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure                                   */
81138 
81139 /* CH29 @Bit 29 : Channel number */
81140   #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Pos (29UL)  /*!< Position of CH29 field.                                              */
81141   #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field.        */
81142   #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field.                                  */
81143   #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field.                                  */
81144   #define UICR_IPCT_LOCAL_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure                                          */
81145   #define UICR_IPCT_LOCAL_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure                                   */
81146 
81147 /* CH30 @Bit 30 : Channel number */
81148   #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Pos (30UL)  /*!< Position of CH30 field.                                              */
81149   #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field.        */
81150   #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field.                                  */
81151   #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field.                                  */
81152   #define UICR_IPCT_LOCAL_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure                                          */
81153   #define UICR_IPCT_LOCAL_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure                                   */
81154 
81155 /* CH31 @Bit 31 : Channel number */
81156   #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Pos (31UL)  /*!< Position of CH31 field.                                              */
81157   #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Msk (0x1UL << UICR_IPCT_LOCAL_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field.        */
81158   #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field.                                  */
81159   #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field.                                  */
81160   #define UICR_IPCT_LOCAL_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure                                          */
81161   #define UICR_IPCT_LOCAL_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure                                   */
81162 
81163 
81164 
81165 /* ============================================ Struct UICR_IPCT_LOCAL_INTERRUPT ============================================= */
81166 /**
81167   * @brief INTERRUPT [UICR_IPCT_LOCAL_INTERRUPT] (unspecified)
81168   */
81169 typedef struct {
81170   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000000) Request permission for the interrupts of IPCT in the
81171                                                                          local domain*/
81172 } NRF_UICR_IPCT_LOCAL_INTERRUPT_Type;                /*!< Size = 4 (0x004)                                                     */
81173 
81174 /* UICR_IPCT_LOCAL_INTERRUPT_SECURE: Request permission for the interrupts of IPCT in the local domain */
81175   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                      */
81176 
81177 /* INT0 @Bit 0 : Interrupt number */
81178   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Pos (0UL) /*!< Position of INT0 field.                                         */
81179   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Pos) /*!< Bit mask of INT0
81180                                                                             field.*/
81181   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Min (0x0UL) /*!< Min enumerator value of INT0 field.                           */
81182   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Max (0x1UL) /*!< Max enumerator value of INT0 field.                           */
81183   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_Secure (0x1UL) /*!< The interrupt 0 is secure                                  */
81184   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT0_NonSecure (0x0UL) /*!< The interrupt 0 is non-secure                           */
81185 
81186 /* INT1 @Bit 1 : Interrupt number */
81187   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Pos (1UL) /*!< Position of INT1 field.                                         */
81188   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Pos) /*!< Bit mask of INT1
81189                                                                             field.*/
81190   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Min (0x0UL) /*!< Min enumerator value of INT1 field.                           */
81191   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Max (0x1UL) /*!< Max enumerator value of INT1 field.                           */
81192   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_Secure (0x1UL) /*!< The interrupt 1 is secure                                  */
81193   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT1_NonSecure (0x0UL) /*!< The interrupt 1 is non-secure                           */
81194 
81195 /* INT2 @Bit 2 : Interrupt number */
81196   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Pos (2UL) /*!< Position of INT2 field.                                         */
81197   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Pos) /*!< Bit mask of INT2
81198                                                                             field.*/
81199   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Min (0x0UL) /*!< Min enumerator value of INT2 field.                           */
81200   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Max (0x1UL) /*!< Max enumerator value of INT2 field.                           */
81201   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_Secure (0x1UL) /*!< The interrupt 2 is secure                                  */
81202   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT2_NonSecure (0x0UL) /*!< The interrupt 2 is non-secure                           */
81203 
81204 /* INT3 @Bit 3 : Interrupt number */
81205   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Pos (3UL) /*!< Position of INT3 field.                                         */
81206   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Pos) /*!< Bit mask of INT3
81207                                                                             field.*/
81208   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Min (0x0UL) /*!< Min enumerator value of INT3 field.                           */
81209   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Max (0x1UL) /*!< Max enumerator value of INT3 field.                           */
81210   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_Secure (0x1UL) /*!< The interrupt 3 is secure                                  */
81211   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT3_NonSecure (0x0UL) /*!< The interrupt 3 is non-secure                           */
81212 
81213 /* INT4 @Bit 4 : Interrupt number */
81214   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Pos (4UL) /*!< Position of INT4 field.                                         */
81215   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Pos) /*!< Bit mask of INT4
81216                                                                             field.*/
81217   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Min (0x0UL) /*!< Min enumerator value of INT4 field.                           */
81218   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Max (0x1UL) /*!< Max enumerator value of INT4 field.                           */
81219   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_Secure (0x1UL) /*!< The interrupt 4 is secure                                  */
81220   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT4_NonSecure (0x0UL) /*!< The interrupt 4 is non-secure                           */
81221 
81222 /* INT5 @Bit 5 : Interrupt number */
81223   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Pos (5UL) /*!< Position of INT5 field.                                         */
81224   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Pos) /*!< Bit mask of INT5
81225                                                                             field.*/
81226   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Min (0x0UL) /*!< Min enumerator value of INT5 field.                           */
81227   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Max (0x1UL) /*!< Max enumerator value of INT5 field.                           */
81228   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_Secure (0x1UL) /*!< The interrupt 5 is secure                                  */
81229   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT5_NonSecure (0x0UL) /*!< The interrupt 5 is non-secure                           */
81230 
81231 /* INT6 @Bit 6 : Interrupt number */
81232   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Pos (6UL) /*!< Position of INT6 field.                                         */
81233   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Pos) /*!< Bit mask of INT6
81234                                                                             field.*/
81235   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Min (0x0UL) /*!< Min enumerator value of INT6 field.                           */
81236   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Max (0x1UL) /*!< Max enumerator value of INT6 field.                           */
81237   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_Secure (0x1UL) /*!< The interrupt 6 is secure                                  */
81238   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT6_NonSecure (0x0UL) /*!< The interrupt 6 is non-secure                           */
81239 
81240 /* INT7 @Bit 7 : Interrupt number */
81241   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Pos (7UL) /*!< Position of INT7 field.                                         */
81242   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Pos) /*!< Bit mask of INT7
81243                                                                             field.*/
81244   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Min (0x0UL) /*!< Min enumerator value of INT7 field.                           */
81245   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Max (0x1UL) /*!< Max enumerator value of INT7 field.                           */
81246   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_Secure (0x1UL) /*!< The interrupt 7 is secure                                  */
81247   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT7_NonSecure (0x0UL) /*!< The interrupt 7 is non-secure                           */
81248 
81249 /* INT8 @Bit 8 : Interrupt number */
81250   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Pos (8UL) /*!< Position of INT8 field.                                         */
81251   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Pos) /*!< Bit mask of INT8
81252                                                                             field.*/
81253   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Min (0x0UL) /*!< Min enumerator value of INT8 field.                           */
81254   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Max (0x1UL) /*!< Max enumerator value of INT8 field.                           */
81255   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_Secure (0x1UL) /*!< The interrupt 8 is secure                                  */
81256   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT8_NonSecure (0x0UL) /*!< The interrupt 8 is non-secure                           */
81257 
81258 /* INT9 @Bit 9 : Interrupt number */
81259   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Pos (9UL) /*!< Position of INT9 field.                                         */
81260   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Pos) /*!< Bit mask of INT9
81261                                                                             field.*/
81262   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Min (0x0UL) /*!< Min enumerator value of INT9 field.                           */
81263   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Max (0x1UL) /*!< Max enumerator value of INT9 field.                           */
81264   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_Secure (0x1UL) /*!< The interrupt 9 is secure                                  */
81265   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT9_NonSecure (0x0UL) /*!< The interrupt 9 is non-secure                           */
81266 
81267 /* INT10 @Bit 10 : Interrupt number */
81268   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Pos (10UL) /*!< Position of INT10 field.                                      */
81269   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Pos) /*!< Bit mask of
81270                                                                             INT10 field.*/
81271   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Min (0x0UL) /*!< Min enumerator value of INT10 field.                         */
81272   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Max (0x1UL) /*!< Max enumerator value of INT10 field.                         */
81273   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_Secure (0x1UL) /*!< The interrupt 10 is secure                                */
81274   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT10_NonSecure (0x0UL) /*!< The interrupt 10 is non-secure                         */
81275 
81276 /* INT11 @Bit 11 : Interrupt number */
81277   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Pos (11UL) /*!< Position of INT11 field.                                      */
81278   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Pos) /*!< Bit mask of
81279                                                                             INT11 field.*/
81280   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Min (0x0UL) /*!< Min enumerator value of INT11 field.                         */
81281   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Max (0x1UL) /*!< Max enumerator value of INT11 field.                         */
81282   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_Secure (0x1UL) /*!< The interrupt 11 is secure                                */
81283   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT11_NonSecure (0x0UL) /*!< The interrupt 11 is non-secure                         */
81284 
81285 /* INT12 @Bit 12 : Interrupt number */
81286   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Pos (12UL) /*!< Position of INT12 field.                                      */
81287   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Pos) /*!< Bit mask of
81288                                                                             INT12 field.*/
81289   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Min (0x0UL) /*!< Min enumerator value of INT12 field.                         */
81290   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Max (0x1UL) /*!< Max enumerator value of INT12 field.                         */
81291   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_Secure (0x1UL) /*!< The interrupt 12 is secure                                */
81292   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT12_NonSecure (0x0UL) /*!< The interrupt 12 is non-secure                         */
81293 
81294 /* INT13 @Bit 13 : Interrupt number */
81295   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Pos (13UL) /*!< Position of INT13 field.                                      */
81296   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Pos) /*!< Bit mask of
81297                                                                             INT13 field.*/
81298   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Min (0x0UL) /*!< Min enumerator value of INT13 field.                         */
81299   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Max (0x1UL) /*!< Max enumerator value of INT13 field.                         */
81300   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_Secure (0x1UL) /*!< The interrupt 13 is secure                                */
81301   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT13_NonSecure (0x0UL) /*!< The interrupt 13 is non-secure                         */
81302 
81303 /* INT14 @Bit 14 : Interrupt number */
81304   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Pos (14UL) /*!< Position of INT14 field.                                      */
81305   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Pos) /*!< Bit mask of
81306                                                                             INT14 field.*/
81307   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Min (0x0UL) /*!< Min enumerator value of INT14 field.                         */
81308   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Max (0x1UL) /*!< Max enumerator value of INT14 field.                         */
81309   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_Secure (0x1UL) /*!< The interrupt 14 is secure                                */
81310   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT14_NonSecure (0x0UL) /*!< The interrupt 14 is non-secure                         */
81311 
81312 /* INT15 @Bit 15 : Interrupt number */
81313   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Pos (15UL) /*!< Position of INT15 field.                                      */
81314   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Pos) /*!< Bit mask of
81315                                                                             INT15 field.*/
81316   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Min (0x0UL) /*!< Min enumerator value of INT15 field.                         */
81317   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Max (0x1UL) /*!< Max enumerator value of INT15 field.                         */
81318   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_Secure (0x1UL) /*!< The interrupt 15 is secure                                */
81319   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT15_NonSecure (0x0UL) /*!< The interrupt 15 is non-secure                         */
81320 
81321 /* INT16 @Bit 16 : Interrupt number */
81322   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Pos (16UL) /*!< Position of INT16 field.                                      */
81323   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Pos) /*!< Bit mask of
81324                                                                             INT16 field.*/
81325   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Min (0x0UL) /*!< Min enumerator value of INT16 field.                         */
81326   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Max (0x1UL) /*!< Max enumerator value of INT16 field.                         */
81327   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_Secure (0x1UL) /*!< The interrupt 16 is secure                                */
81328   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT16_NonSecure (0x0UL) /*!< The interrupt 16 is non-secure                         */
81329 
81330 /* INT17 @Bit 17 : Interrupt number */
81331   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Pos (17UL) /*!< Position of INT17 field.                                      */
81332   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Pos) /*!< Bit mask of
81333                                                                             INT17 field.*/
81334   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Min (0x0UL) /*!< Min enumerator value of INT17 field.                         */
81335   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Max (0x1UL) /*!< Max enumerator value of INT17 field.                         */
81336   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_Secure (0x1UL) /*!< The interrupt 17 is secure                                */
81337   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT17_NonSecure (0x0UL) /*!< The interrupt 17 is non-secure                         */
81338 
81339 /* INT18 @Bit 18 : Interrupt number */
81340   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Pos (18UL) /*!< Position of INT18 field.                                      */
81341   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Pos) /*!< Bit mask of
81342                                                                             INT18 field.*/
81343   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Min (0x0UL) /*!< Min enumerator value of INT18 field.                         */
81344   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Max (0x1UL) /*!< Max enumerator value of INT18 field.                         */
81345   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_Secure (0x1UL) /*!< The interrupt 18 is secure                                */
81346   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT18_NonSecure (0x0UL) /*!< The interrupt 18 is non-secure                         */
81347 
81348 /* INT19 @Bit 19 : Interrupt number */
81349   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Pos (19UL) /*!< Position of INT19 field.                                      */
81350   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Pos) /*!< Bit mask of
81351                                                                             INT19 field.*/
81352   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Min (0x0UL) /*!< Min enumerator value of INT19 field.                         */
81353   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Max (0x1UL) /*!< Max enumerator value of INT19 field.                         */
81354   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_Secure (0x1UL) /*!< The interrupt 19 is secure                                */
81355   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT19_NonSecure (0x0UL) /*!< The interrupt 19 is non-secure                         */
81356 
81357 /* INT20 @Bit 20 : Interrupt number */
81358   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Pos (20UL) /*!< Position of INT20 field.                                      */
81359   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Pos) /*!< Bit mask of
81360                                                                             INT20 field.*/
81361   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Min (0x0UL) /*!< Min enumerator value of INT20 field.                         */
81362   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Max (0x1UL) /*!< Max enumerator value of INT20 field.                         */
81363   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_Secure (0x1UL) /*!< The interrupt 20 is secure                                */
81364   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT20_NonSecure (0x0UL) /*!< The interrupt 20 is non-secure                         */
81365 
81366 /* INT21 @Bit 21 : Interrupt number */
81367   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Pos (21UL) /*!< Position of INT21 field.                                      */
81368   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Pos) /*!< Bit mask of
81369                                                                             INT21 field.*/
81370   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Min (0x0UL) /*!< Min enumerator value of INT21 field.                         */
81371   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Max (0x1UL) /*!< Max enumerator value of INT21 field.                         */
81372   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_Secure (0x1UL) /*!< The interrupt 21 is secure                                */
81373   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT21_NonSecure (0x0UL) /*!< The interrupt 21 is non-secure                         */
81374 
81375 /* INT22 @Bit 22 : Interrupt number */
81376   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Pos (22UL) /*!< Position of INT22 field.                                      */
81377   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Pos) /*!< Bit mask of
81378                                                                             INT22 field.*/
81379   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Min (0x0UL) /*!< Min enumerator value of INT22 field.                         */
81380   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Max (0x1UL) /*!< Max enumerator value of INT22 field.                         */
81381   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_Secure (0x1UL) /*!< The interrupt 22 is secure                                */
81382   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT22_NonSecure (0x0UL) /*!< The interrupt 22 is non-secure                         */
81383 
81384 /* INT23 @Bit 23 : Interrupt number */
81385   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Pos (23UL) /*!< Position of INT23 field.                                      */
81386   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Pos) /*!< Bit mask of
81387                                                                             INT23 field.*/
81388   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Min (0x0UL) /*!< Min enumerator value of INT23 field.                         */
81389   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Max (0x1UL) /*!< Max enumerator value of INT23 field.                         */
81390   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_Secure (0x1UL) /*!< The interrupt 23 is secure                                */
81391   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT23_NonSecure (0x0UL) /*!< The interrupt 23 is non-secure                         */
81392 
81393 /* INT24 @Bit 24 : Interrupt number */
81394   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Pos (24UL) /*!< Position of INT24 field.                                      */
81395   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Pos) /*!< Bit mask of
81396                                                                             INT24 field.*/
81397   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Min (0x0UL) /*!< Min enumerator value of INT24 field.                         */
81398   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Max (0x1UL) /*!< Max enumerator value of INT24 field.                         */
81399   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_Secure (0x1UL) /*!< The interrupt 24 is secure                                */
81400   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT24_NonSecure (0x0UL) /*!< The interrupt 24 is non-secure                         */
81401 
81402 /* INT25 @Bit 25 : Interrupt number */
81403   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Pos (25UL) /*!< Position of INT25 field.                                      */
81404   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Pos) /*!< Bit mask of
81405                                                                             INT25 field.*/
81406   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Min (0x0UL) /*!< Min enumerator value of INT25 field.                         */
81407   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Max (0x1UL) /*!< Max enumerator value of INT25 field.                         */
81408   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_Secure (0x1UL) /*!< The interrupt 25 is secure                                */
81409   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT25_NonSecure (0x0UL) /*!< The interrupt 25 is non-secure                         */
81410 
81411 /* INT26 @Bit 26 : Interrupt number */
81412   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Pos (26UL) /*!< Position of INT26 field.                                      */
81413   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Pos) /*!< Bit mask of
81414                                                                             INT26 field.*/
81415   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Min (0x0UL) /*!< Min enumerator value of INT26 field.                         */
81416   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Max (0x1UL) /*!< Max enumerator value of INT26 field.                         */
81417   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_Secure (0x1UL) /*!< The interrupt 26 is secure                                */
81418   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT26_NonSecure (0x0UL) /*!< The interrupt 26 is non-secure                         */
81419 
81420 /* INT27 @Bit 27 : Interrupt number */
81421   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Pos (27UL) /*!< Position of INT27 field.                                      */
81422   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Pos) /*!< Bit mask of
81423                                                                             INT27 field.*/
81424   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Min (0x0UL) /*!< Min enumerator value of INT27 field.                         */
81425   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Max (0x1UL) /*!< Max enumerator value of INT27 field.                         */
81426   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_Secure (0x1UL) /*!< The interrupt 27 is secure                                */
81427   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT27_NonSecure (0x0UL) /*!< The interrupt 27 is non-secure                         */
81428 
81429 /* INT28 @Bit 28 : Interrupt number */
81430   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Pos (28UL) /*!< Position of INT28 field.                                      */
81431   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Pos) /*!< Bit mask of
81432                                                                             INT28 field.*/
81433   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Min (0x0UL) /*!< Min enumerator value of INT28 field.                         */
81434   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Max (0x1UL) /*!< Max enumerator value of INT28 field.                         */
81435   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_Secure (0x1UL) /*!< The interrupt 28 is secure                                */
81436   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT28_NonSecure (0x0UL) /*!< The interrupt 28 is non-secure                         */
81437 
81438 /* INT29 @Bit 29 : Interrupt number */
81439   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Pos (29UL) /*!< Position of INT29 field.                                      */
81440   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Pos) /*!< Bit mask of
81441                                                                             INT29 field.*/
81442   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Min (0x0UL) /*!< Min enumerator value of INT29 field.                         */
81443   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Max (0x1UL) /*!< Max enumerator value of INT29 field.                         */
81444   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_Secure (0x1UL) /*!< The interrupt 29 is secure                                */
81445   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT29_NonSecure (0x0UL) /*!< The interrupt 29 is non-secure                         */
81446 
81447 /* INT30 @Bit 30 : Interrupt number */
81448   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Pos (30UL) /*!< Position of INT30 field.                                      */
81449   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Pos) /*!< Bit mask of
81450                                                                             INT30 field.*/
81451   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Min (0x0UL) /*!< Min enumerator value of INT30 field.                         */
81452   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Max (0x1UL) /*!< Max enumerator value of INT30 field.                         */
81453   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_Secure (0x1UL) /*!< The interrupt 30 is secure                                */
81454   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT30_NonSecure (0x0UL) /*!< The interrupt 30 is non-secure                         */
81455 
81456 /* INT31 @Bit 31 : Interrupt number */
81457   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Pos (31UL) /*!< Position of INT31 field.                                      */
81458   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Msk (0x1UL << UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Pos) /*!< Bit mask of
81459                                                                             INT31 field.*/
81460   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Min (0x0UL) /*!< Min enumerator value of INT31 field.                         */
81461   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Max (0x1UL) /*!< Max enumerator value of INT31 field.                         */
81462   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_Secure (0x1UL) /*!< The interrupt 31 is secure                                */
81463   #define UICR_IPCT_LOCAL_INTERRUPT_SECURE_INT31_NonSecure (0x0UL) /*!< The interrupt 31 is non-secure                         */
81464 
81465 
81466 
81467 /* ================================================= Struct UICR_IPCT_LOCAL ================================================== */
81468 /**
81469   * @brief LOCAL [UICR_IPCT_LOCAL] (unspecified)
81470   */
81471 typedef struct {
81472   __IOM NRF_UICR_IPCT_LOCAL_CH_Type CH;              /*!< (@ 0x00000000) (unspecified)                                         */
81473   __IOM NRF_UICR_IPCT_LOCAL_INTERRUPT_Type INTERRUPT; /*!< (@ 0x00000004) (unspecified)                                        */
81474 } NRF_UICR_IPCT_LOCAL_Type;                          /*!< Size = 8 (0x008)                                                     */
81475 
81476 
81477 /* =============================================== Struct UICR_IPCT_GLOBAL_CH ================================================ */
81478 /**
81479   * @brief CH [UICR_IPCT_GLOBAL_CH] (unspecified)
81480   */
81481 typedef struct {
81482   __IOM uint32_t  OWN;                               /*!< (@ 0x00000000) Request ownership of the channels of IPCT[n] in Global
81483                                                                          domain*/
81484   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Request permission for the channels of IPCT[n] in
81485                                                                          Global domain*/
81486 } NRF_UICR_IPCT_GLOBAL_CH_Type;                      /*!< Size = 8 (0x008)                                                     */
81487 
81488 /* UICR_IPCT_GLOBAL_CH_OWN: Request ownership of the channels of IPCT[n] in Global domain */
81489   #define UICR_IPCT_GLOBAL_CH_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register.                                  */
81490 
81491 /* CH0 @Bit 0 : Channel number */
81492   #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Pos (0UL)      /*!< Position of CH0 field.                                               */
81493   #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH0_Pos) /*!< Bit mask of CH0 field.               */
81494   #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Min (0x0UL)    /*!< Min enumerator value of CH0 field.                                   */
81495   #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Max (0x1UL)    /*!< Max enumerator value of CH0 field.                                   */
81496   #define UICR_IPCT_GLOBAL_CH_OWN_CH0_NotOwn (0x1UL) /*!< Do not own the channel 0                                             */
81497   #define UICR_IPCT_GLOBAL_CH_OWN_CH0_Own (0x0UL)    /*!< Own the channel 0                                                    */
81498 
81499 /* CH1 @Bit 1 : Channel number */
81500   #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Pos (1UL)      /*!< Position of CH1 field.                                               */
81501   #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH1_Pos) /*!< Bit mask of CH1 field.               */
81502   #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Min (0x0UL)    /*!< Min enumerator value of CH1 field.                                   */
81503   #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Max (0x1UL)    /*!< Max enumerator value of CH1 field.                                   */
81504   #define UICR_IPCT_GLOBAL_CH_OWN_CH1_NotOwn (0x1UL) /*!< Do not own the channel 1                                             */
81505   #define UICR_IPCT_GLOBAL_CH_OWN_CH1_Own (0x0UL)    /*!< Own the channel 1                                                    */
81506 
81507 /* CH2 @Bit 2 : Channel number */
81508   #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Pos (2UL)      /*!< Position of CH2 field.                                               */
81509   #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH2_Pos) /*!< Bit mask of CH2 field.               */
81510   #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Min (0x0UL)    /*!< Min enumerator value of CH2 field.                                   */
81511   #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Max (0x1UL)    /*!< Max enumerator value of CH2 field.                                   */
81512   #define UICR_IPCT_GLOBAL_CH_OWN_CH2_NotOwn (0x1UL) /*!< Do not own the channel 2                                             */
81513   #define UICR_IPCT_GLOBAL_CH_OWN_CH2_Own (0x0UL)    /*!< Own the channel 2                                                    */
81514 
81515 /* CH3 @Bit 3 : Channel number */
81516   #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Pos (3UL)      /*!< Position of CH3 field.                                               */
81517   #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH3_Pos) /*!< Bit mask of CH3 field.               */
81518   #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Min (0x0UL)    /*!< Min enumerator value of CH3 field.                                   */
81519   #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Max (0x1UL)    /*!< Max enumerator value of CH3 field.                                   */
81520   #define UICR_IPCT_GLOBAL_CH_OWN_CH3_NotOwn (0x1UL) /*!< Do not own the channel 3                                             */
81521   #define UICR_IPCT_GLOBAL_CH_OWN_CH3_Own (0x0UL)    /*!< Own the channel 3                                                    */
81522 
81523 /* CH4 @Bit 4 : Channel number */
81524   #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Pos (4UL)      /*!< Position of CH4 field.                                               */
81525   #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH4_Pos) /*!< Bit mask of CH4 field.               */
81526   #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Min (0x0UL)    /*!< Min enumerator value of CH4 field.                                   */
81527   #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Max (0x1UL)    /*!< Max enumerator value of CH4 field.                                   */
81528   #define UICR_IPCT_GLOBAL_CH_OWN_CH4_NotOwn (0x1UL) /*!< Do not own the channel 4                                             */
81529   #define UICR_IPCT_GLOBAL_CH_OWN_CH4_Own (0x0UL)    /*!< Own the channel 4                                                    */
81530 
81531 /* CH5 @Bit 5 : Channel number */
81532   #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Pos (5UL)      /*!< Position of CH5 field.                                               */
81533   #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH5_Pos) /*!< Bit mask of CH5 field.               */
81534   #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Min (0x0UL)    /*!< Min enumerator value of CH5 field.                                   */
81535   #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Max (0x1UL)    /*!< Max enumerator value of CH5 field.                                   */
81536   #define UICR_IPCT_GLOBAL_CH_OWN_CH5_NotOwn (0x1UL) /*!< Do not own the channel 5                                             */
81537   #define UICR_IPCT_GLOBAL_CH_OWN_CH5_Own (0x0UL)    /*!< Own the channel 5                                                    */
81538 
81539 /* CH6 @Bit 6 : Channel number */
81540   #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Pos (6UL)      /*!< Position of CH6 field.                                               */
81541   #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH6_Pos) /*!< Bit mask of CH6 field.               */
81542   #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Min (0x0UL)    /*!< Min enumerator value of CH6 field.                                   */
81543   #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Max (0x1UL)    /*!< Max enumerator value of CH6 field.                                   */
81544   #define UICR_IPCT_GLOBAL_CH_OWN_CH6_NotOwn (0x1UL) /*!< Do not own the channel 6                                             */
81545   #define UICR_IPCT_GLOBAL_CH_OWN_CH6_Own (0x0UL)    /*!< Own the channel 6                                                    */
81546 
81547 /* CH7 @Bit 7 : Channel number */
81548   #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Pos (7UL)      /*!< Position of CH7 field.                                               */
81549   #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH7_Pos) /*!< Bit mask of CH7 field.               */
81550   #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Min (0x0UL)    /*!< Min enumerator value of CH7 field.                                   */
81551   #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Max (0x1UL)    /*!< Max enumerator value of CH7 field.                                   */
81552   #define UICR_IPCT_GLOBAL_CH_OWN_CH7_NotOwn (0x1UL) /*!< Do not own the channel 7                                             */
81553   #define UICR_IPCT_GLOBAL_CH_OWN_CH7_Own (0x0UL)    /*!< Own the channel 7                                                    */
81554 
81555 /* CH8 @Bit 8 : Channel number */
81556   #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Pos (8UL)      /*!< Position of CH8 field.                                               */
81557   #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH8_Pos) /*!< Bit mask of CH8 field.               */
81558   #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Min (0x0UL)    /*!< Min enumerator value of CH8 field.                                   */
81559   #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Max (0x1UL)    /*!< Max enumerator value of CH8 field.                                   */
81560   #define UICR_IPCT_GLOBAL_CH_OWN_CH8_NotOwn (0x1UL) /*!< Do not own the channel 8                                             */
81561   #define UICR_IPCT_GLOBAL_CH_OWN_CH8_Own (0x0UL)    /*!< Own the channel 8                                                    */
81562 
81563 /* CH9 @Bit 9 : Channel number */
81564   #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Pos (9UL)      /*!< Position of CH9 field.                                               */
81565   #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH9_Pos) /*!< Bit mask of CH9 field.               */
81566   #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Min (0x0UL)    /*!< Min enumerator value of CH9 field.                                   */
81567   #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Max (0x1UL)    /*!< Max enumerator value of CH9 field.                                   */
81568   #define UICR_IPCT_GLOBAL_CH_OWN_CH9_NotOwn (0x1UL) /*!< Do not own the channel 9                                             */
81569   #define UICR_IPCT_GLOBAL_CH_OWN_CH9_Own (0x0UL)    /*!< Own the channel 9                                                    */
81570 
81571 /* CH10 @Bit 10 : Channel number */
81572   #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Pos (10UL)    /*!< Position of CH10 field.                                              */
81573   #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH10_Pos) /*!< Bit mask of CH10 field.            */
81574   #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Min (0x0UL)   /*!< Min enumerator value of CH10 field.                                  */
81575   #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Max (0x1UL)   /*!< Max enumerator value of CH10 field.                                  */
81576   #define UICR_IPCT_GLOBAL_CH_OWN_CH10_NotOwn (0x1UL) /*!< Do not own the channel 10                                           */
81577   #define UICR_IPCT_GLOBAL_CH_OWN_CH10_Own (0x0UL)   /*!< Own the channel 10                                                   */
81578 
81579 /* CH11 @Bit 11 : Channel number */
81580   #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Pos (11UL)    /*!< Position of CH11 field.                                              */
81581   #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH11_Pos) /*!< Bit mask of CH11 field.            */
81582   #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Min (0x0UL)   /*!< Min enumerator value of CH11 field.                                  */
81583   #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Max (0x1UL)   /*!< Max enumerator value of CH11 field.                                  */
81584   #define UICR_IPCT_GLOBAL_CH_OWN_CH11_NotOwn (0x1UL) /*!< Do not own the channel 11                                           */
81585   #define UICR_IPCT_GLOBAL_CH_OWN_CH11_Own (0x0UL)   /*!< Own the channel 11                                                   */
81586 
81587 /* CH12 @Bit 12 : Channel number */
81588   #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Pos (12UL)    /*!< Position of CH12 field.                                              */
81589   #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH12_Pos) /*!< Bit mask of CH12 field.            */
81590   #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Min (0x0UL)   /*!< Min enumerator value of CH12 field.                                  */
81591   #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Max (0x1UL)   /*!< Max enumerator value of CH12 field.                                  */
81592   #define UICR_IPCT_GLOBAL_CH_OWN_CH12_NotOwn (0x1UL) /*!< Do not own the channel 12                                           */
81593   #define UICR_IPCT_GLOBAL_CH_OWN_CH12_Own (0x0UL)   /*!< Own the channel 12                                                   */
81594 
81595 /* CH13 @Bit 13 : Channel number */
81596   #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Pos (13UL)    /*!< Position of CH13 field.                                              */
81597   #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH13_Pos) /*!< Bit mask of CH13 field.            */
81598   #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Min (0x0UL)   /*!< Min enumerator value of CH13 field.                                  */
81599   #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Max (0x1UL)   /*!< Max enumerator value of CH13 field.                                  */
81600   #define UICR_IPCT_GLOBAL_CH_OWN_CH13_NotOwn (0x1UL) /*!< Do not own the channel 13                                           */
81601   #define UICR_IPCT_GLOBAL_CH_OWN_CH13_Own (0x0UL)   /*!< Own the channel 13                                                   */
81602 
81603 /* CH14 @Bit 14 : Channel number */
81604   #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Pos (14UL)    /*!< Position of CH14 field.                                              */
81605   #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH14_Pos) /*!< Bit mask of CH14 field.            */
81606   #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Min (0x0UL)   /*!< Min enumerator value of CH14 field.                                  */
81607   #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Max (0x1UL)   /*!< Max enumerator value of CH14 field.                                  */
81608   #define UICR_IPCT_GLOBAL_CH_OWN_CH14_NotOwn (0x1UL) /*!< Do not own the channel 14                                           */
81609   #define UICR_IPCT_GLOBAL_CH_OWN_CH14_Own (0x0UL)   /*!< Own the channel 14                                                   */
81610 
81611 /* CH15 @Bit 15 : Channel number */
81612   #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Pos (15UL)    /*!< Position of CH15 field.                                              */
81613   #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH15_Pos) /*!< Bit mask of CH15 field.            */
81614   #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Min (0x0UL)   /*!< Min enumerator value of CH15 field.                                  */
81615   #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Max (0x1UL)   /*!< Max enumerator value of CH15 field.                                  */
81616   #define UICR_IPCT_GLOBAL_CH_OWN_CH15_NotOwn (0x1UL) /*!< Do not own the channel 15                                           */
81617   #define UICR_IPCT_GLOBAL_CH_OWN_CH15_Own (0x0UL)   /*!< Own the channel 15                                                   */
81618 
81619 /* CH16 @Bit 16 : Channel number */
81620   #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Pos (16UL)    /*!< Position of CH16 field.                                              */
81621   #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH16_Pos) /*!< Bit mask of CH16 field.            */
81622   #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Min (0x0UL)   /*!< Min enumerator value of CH16 field.                                  */
81623   #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Max (0x1UL)   /*!< Max enumerator value of CH16 field.                                  */
81624   #define UICR_IPCT_GLOBAL_CH_OWN_CH16_NotOwn (0x1UL) /*!< Do not own the channel 16                                           */
81625   #define UICR_IPCT_GLOBAL_CH_OWN_CH16_Own (0x0UL)   /*!< Own the channel 16                                                   */
81626 
81627 /* CH17 @Bit 17 : Channel number */
81628   #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Pos (17UL)    /*!< Position of CH17 field.                                              */
81629   #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH17_Pos) /*!< Bit mask of CH17 field.            */
81630   #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Min (0x0UL)   /*!< Min enumerator value of CH17 field.                                  */
81631   #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Max (0x1UL)   /*!< Max enumerator value of CH17 field.                                  */
81632   #define UICR_IPCT_GLOBAL_CH_OWN_CH17_NotOwn (0x1UL) /*!< Do not own the channel 17                                           */
81633   #define UICR_IPCT_GLOBAL_CH_OWN_CH17_Own (0x0UL)   /*!< Own the channel 17                                                   */
81634 
81635 /* CH18 @Bit 18 : Channel number */
81636   #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Pos (18UL)    /*!< Position of CH18 field.                                              */
81637   #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH18_Pos) /*!< Bit mask of CH18 field.            */
81638   #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Min (0x0UL)   /*!< Min enumerator value of CH18 field.                                  */
81639   #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Max (0x1UL)   /*!< Max enumerator value of CH18 field.                                  */
81640   #define UICR_IPCT_GLOBAL_CH_OWN_CH18_NotOwn (0x1UL) /*!< Do not own the channel 18                                           */
81641   #define UICR_IPCT_GLOBAL_CH_OWN_CH18_Own (0x0UL)   /*!< Own the channel 18                                                   */
81642 
81643 /* CH19 @Bit 19 : Channel number */
81644   #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Pos (19UL)    /*!< Position of CH19 field.                                              */
81645   #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH19_Pos) /*!< Bit mask of CH19 field.            */
81646   #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Min (0x0UL)   /*!< Min enumerator value of CH19 field.                                  */
81647   #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Max (0x1UL)   /*!< Max enumerator value of CH19 field.                                  */
81648   #define UICR_IPCT_GLOBAL_CH_OWN_CH19_NotOwn (0x1UL) /*!< Do not own the channel 19                                           */
81649   #define UICR_IPCT_GLOBAL_CH_OWN_CH19_Own (0x0UL)   /*!< Own the channel 19                                                   */
81650 
81651 /* CH20 @Bit 20 : Channel number */
81652   #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Pos (20UL)    /*!< Position of CH20 field.                                              */
81653   #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH20_Pos) /*!< Bit mask of CH20 field.            */
81654   #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Min (0x0UL)   /*!< Min enumerator value of CH20 field.                                  */
81655   #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Max (0x1UL)   /*!< Max enumerator value of CH20 field.                                  */
81656   #define UICR_IPCT_GLOBAL_CH_OWN_CH20_NotOwn (0x1UL) /*!< Do not own the channel 20                                           */
81657   #define UICR_IPCT_GLOBAL_CH_OWN_CH20_Own (0x0UL)   /*!< Own the channel 20                                                   */
81658 
81659 /* CH21 @Bit 21 : Channel number */
81660   #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Pos (21UL)    /*!< Position of CH21 field.                                              */
81661   #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH21_Pos) /*!< Bit mask of CH21 field.            */
81662   #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Min (0x0UL)   /*!< Min enumerator value of CH21 field.                                  */
81663   #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Max (0x1UL)   /*!< Max enumerator value of CH21 field.                                  */
81664   #define UICR_IPCT_GLOBAL_CH_OWN_CH21_NotOwn (0x1UL) /*!< Do not own the channel 21                                           */
81665   #define UICR_IPCT_GLOBAL_CH_OWN_CH21_Own (0x0UL)   /*!< Own the channel 21                                                   */
81666 
81667 /* CH22 @Bit 22 : Channel number */
81668   #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Pos (22UL)    /*!< Position of CH22 field.                                              */
81669   #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH22_Pos) /*!< Bit mask of CH22 field.            */
81670   #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Min (0x0UL)   /*!< Min enumerator value of CH22 field.                                  */
81671   #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Max (0x1UL)   /*!< Max enumerator value of CH22 field.                                  */
81672   #define UICR_IPCT_GLOBAL_CH_OWN_CH22_NotOwn (0x1UL) /*!< Do not own the channel 22                                           */
81673   #define UICR_IPCT_GLOBAL_CH_OWN_CH22_Own (0x0UL)   /*!< Own the channel 22                                                   */
81674 
81675 /* CH23 @Bit 23 : Channel number */
81676   #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Pos (23UL)    /*!< Position of CH23 field.                                              */
81677   #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH23_Pos) /*!< Bit mask of CH23 field.            */
81678   #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Min (0x0UL)   /*!< Min enumerator value of CH23 field.                                  */
81679   #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Max (0x1UL)   /*!< Max enumerator value of CH23 field.                                  */
81680   #define UICR_IPCT_GLOBAL_CH_OWN_CH23_NotOwn (0x1UL) /*!< Do not own the channel 23                                           */
81681   #define UICR_IPCT_GLOBAL_CH_OWN_CH23_Own (0x0UL)   /*!< Own the channel 23                                                   */
81682 
81683 /* CH24 @Bit 24 : Channel number */
81684   #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Pos (24UL)    /*!< Position of CH24 field.                                              */
81685   #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH24_Pos) /*!< Bit mask of CH24 field.            */
81686   #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Min (0x0UL)   /*!< Min enumerator value of CH24 field.                                  */
81687   #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Max (0x1UL)   /*!< Max enumerator value of CH24 field.                                  */
81688   #define UICR_IPCT_GLOBAL_CH_OWN_CH24_NotOwn (0x1UL) /*!< Do not own the channel 24                                           */
81689   #define UICR_IPCT_GLOBAL_CH_OWN_CH24_Own (0x0UL)   /*!< Own the channel 24                                                   */
81690 
81691 /* CH25 @Bit 25 : Channel number */
81692   #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Pos (25UL)    /*!< Position of CH25 field.                                              */
81693   #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH25_Pos) /*!< Bit mask of CH25 field.            */
81694   #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Min (0x0UL)   /*!< Min enumerator value of CH25 field.                                  */
81695   #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Max (0x1UL)   /*!< Max enumerator value of CH25 field.                                  */
81696   #define UICR_IPCT_GLOBAL_CH_OWN_CH25_NotOwn (0x1UL) /*!< Do not own the channel 25                                           */
81697   #define UICR_IPCT_GLOBAL_CH_OWN_CH25_Own (0x0UL)   /*!< Own the channel 25                                                   */
81698 
81699 /* CH26 @Bit 26 : Channel number */
81700   #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Pos (26UL)    /*!< Position of CH26 field.                                              */
81701   #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH26_Pos) /*!< Bit mask of CH26 field.            */
81702   #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Min (0x0UL)   /*!< Min enumerator value of CH26 field.                                  */
81703   #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Max (0x1UL)   /*!< Max enumerator value of CH26 field.                                  */
81704   #define UICR_IPCT_GLOBAL_CH_OWN_CH26_NotOwn (0x1UL) /*!< Do not own the channel 26                                           */
81705   #define UICR_IPCT_GLOBAL_CH_OWN_CH26_Own (0x0UL)   /*!< Own the channel 26                                                   */
81706 
81707 /* CH27 @Bit 27 : Channel number */
81708   #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Pos (27UL)    /*!< Position of CH27 field.                                              */
81709   #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH27_Pos) /*!< Bit mask of CH27 field.            */
81710   #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Min (0x0UL)   /*!< Min enumerator value of CH27 field.                                  */
81711   #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Max (0x1UL)   /*!< Max enumerator value of CH27 field.                                  */
81712   #define UICR_IPCT_GLOBAL_CH_OWN_CH27_NotOwn (0x1UL) /*!< Do not own the channel 27                                           */
81713   #define UICR_IPCT_GLOBAL_CH_OWN_CH27_Own (0x0UL)   /*!< Own the channel 27                                                   */
81714 
81715 /* CH28 @Bit 28 : Channel number */
81716   #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Pos (28UL)    /*!< Position of CH28 field.                                              */
81717   #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH28_Pos) /*!< Bit mask of CH28 field.            */
81718   #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Min (0x0UL)   /*!< Min enumerator value of CH28 field.                                  */
81719   #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Max (0x1UL)   /*!< Max enumerator value of CH28 field.                                  */
81720   #define UICR_IPCT_GLOBAL_CH_OWN_CH28_NotOwn (0x1UL) /*!< Do not own the channel 28                                           */
81721   #define UICR_IPCT_GLOBAL_CH_OWN_CH28_Own (0x0UL)   /*!< Own the channel 28                                                   */
81722 
81723 /* CH29 @Bit 29 : Channel number */
81724   #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Pos (29UL)    /*!< Position of CH29 field.                                              */
81725   #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH29_Pos) /*!< Bit mask of CH29 field.            */
81726   #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Min (0x0UL)   /*!< Min enumerator value of CH29 field.                                  */
81727   #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Max (0x1UL)   /*!< Max enumerator value of CH29 field.                                  */
81728   #define UICR_IPCT_GLOBAL_CH_OWN_CH29_NotOwn (0x1UL) /*!< Do not own the channel 29                                           */
81729   #define UICR_IPCT_GLOBAL_CH_OWN_CH29_Own (0x0UL)   /*!< Own the channel 29                                                   */
81730 
81731 /* CH30 @Bit 30 : Channel number */
81732   #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Pos (30UL)    /*!< Position of CH30 field.                                              */
81733   #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH30_Pos) /*!< Bit mask of CH30 field.            */
81734   #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Min (0x0UL)   /*!< Min enumerator value of CH30 field.                                  */
81735   #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Max (0x1UL)   /*!< Max enumerator value of CH30 field.                                  */
81736   #define UICR_IPCT_GLOBAL_CH_OWN_CH30_NotOwn (0x1UL) /*!< Do not own the channel 30                                           */
81737   #define UICR_IPCT_GLOBAL_CH_OWN_CH30_Own (0x0UL)   /*!< Own the channel 30                                                   */
81738 
81739 /* CH31 @Bit 31 : Channel number */
81740   #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Pos (31UL)    /*!< Position of CH31 field.                                              */
81741   #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_OWN_CH31_Pos) /*!< Bit mask of CH31 field.            */
81742   #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Min (0x0UL)   /*!< Min enumerator value of CH31 field.                                  */
81743   #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Max (0x1UL)   /*!< Max enumerator value of CH31 field.                                  */
81744   #define UICR_IPCT_GLOBAL_CH_OWN_CH31_NotOwn (0x1UL) /*!< Do not own the channel 31                                           */
81745   #define UICR_IPCT_GLOBAL_CH_OWN_CH31_Own (0x0UL)   /*!< Own the channel 31                                                   */
81746 
81747 
81748 /* UICR_IPCT_GLOBAL_CH_SECURE: Request permission for the channels of IPCT[n] in Global domain */
81749   #define UICR_IPCT_GLOBAL_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                            */
81750 
81751 /* CH0 @Bit 0 : Channel number */
81752   #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Pos (0UL)   /*!< Position of CH0 field.                                               */
81753   #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field.         */
81754   #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field.                                   */
81755   #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field.                                   */
81756   #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure                                           */
81757   #define UICR_IPCT_GLOBAL_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure                                    */
81758 
81759 /* CH1 @Bit 1 : Channel number */
81760   #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Pos (1UL)   /*!< Position of CH1 field.                                               */
81761   #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field.         */
81762   #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field.                                   */
81763   #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field.                                   */
81764   #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure                                           */
81765   #define UICR_IPCT_GLOBAL_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure                                    */
81766 
81767 /* CH2 @Bit 2 : Channel number */
81768   #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Pos (2UL)   /*!< Position of CH2 field.                                               */
81769   #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field.         */
81770   #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field.                                   */
81771   #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field.                                   */
81772   #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure                                           */
81773   #define UICR_IPCT_GLOBAL_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure                                    */
81774 
81775 /* CH3 @Bit 3 : Channel number */
81776   #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Pos (3UL)   /*!< Position of CH3 field.                                               */
81777   #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field.         */
81778   #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field.                                   */
81779   #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field.                                   */
81780   #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure                                           */
81781   #define UICR_IPCT_GLOBAL_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure                                    */
81782 
81783 /* CH4 @Bit 4 : Channel number */
81784   #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Pos (4UL)   /*!< Position of CH4 field.                                               */
81785   #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field.         */
81786   #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field.                                   */
81787   #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field.                                   */
81788   #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure                                           */
81789   #define UICR_IPCT_GLOBAL_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure                                    */
81790 
81791 /* CH5 @Bit 5 : Channel number */
81792   #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Pos (5UL)   /*!< Position of CH5 field.                                               */
81793   #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field.         */
81794   #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field.                                   */
81795   #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field.                                   */
81796   #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure                                           */
81797   #define UICR_IPCT_GLOBAL_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure                                    */
81798 
81799 /* CH6 @Bit 6 : Channel number */
81800   #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Pos (6UL)   /*!< Position of CH6 field.                                               */
81801   #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field.         */
81802   #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field.                                   */
81803   #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field.                                   */
81804   #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure                                           */
81805   #define UICR_IPCT_GLOBAL_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure                                    */
81806 
81807 /* CH7 @Bit 7 : Channel number */
81808   #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Pos (7UL)   /*!< Position of CH7 field.                                               */
81809   #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field.         */
81810   #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field.                                   */
81811   #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field.                                   */
81812   #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure                                           */
81813   #define UICR_IPCT_GLOBAL_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure                                    */
81814 
81815 /* CH8 @Bit 8 : Channel number */
81816   #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Pos (8UL)   /*!< Position of CH8 field.                                               */
81817   #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field.         */
81818   #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field.                                   */
81819   #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field.                                   */
81820   #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure                                           */
81821   #define UICR_IPCT_GLOBAL_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure                                    */
81822 
81823 /* CH9 @Bit 9 : Channel number */
81824   #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Pos (9UL)   /*!< Position of CH9 field.                                               */
81825   #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field.         */
81826   #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field.                                   */
81827   #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field.                                   */
81828   #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure                                           */
81829   #define UICR_IPCT_GLOBAL_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure                                    */
81830 
81831 /* CH10 @Bit 10 : Channel number */
81832   #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Pos (10UL) /*!< Position of CH10 field.                                              */
81833   #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field.      */
81834   #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field.                                 */
81835   #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field.                                 */
81836   #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure                                         */
81837   #define UICR_IPCT_GLOBAL_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure                                  */
81838 
81839 /* CH11 @Bit 11 : Channel number */
81840   #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Pos (11UL) /*!< Position of CH11 field.                                              */
81841   #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field.      */
81842   #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field.                                 */
81843   #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field.                                 */
81844   #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure                                         */
81845   #define UICR_IPCT_GLOBAL_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure                                  */
81846 
81847 /* CH12 @Bit 12 : Channel number */
81848   #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Pos (12UL) /*!< Position of CH12 field.                                              */
81849   #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field.      */
81850   #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field.                                 */
81851   #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field.                                 */
81852   #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure                                         */
81853   #define UICR_IPCT_GLOBAL_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure                                  */
81854 
81855 /* CH13 @Bit 13 : Channel number */
81856   #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Pos (13UL) /*!< Position of CH13 field.                                              */
81857   #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field.      */
81858   #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field.                                 */
81859   #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field.                                 */
81860   #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure                                         */
81861   #define UICR_IPCT_GLOBAL_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure                                  */
81862 
81863 /* CH14 @Bit 14 : Channel number */
81864   #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Pos (14UL) /*!< Position of CH14 field.                                              */
81865   #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field.      */
81866   #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field.                                 */
81867   #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field.                                 */
81868   #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure                                         */
81869   #define UICR_IPCT_GLOBAL_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure                                  */
81870 
81871 /* CH15 @Bit 15 : Channel number */
81872   #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Pos (15UL) /*!< Position of CH15 field.                                              */
81873   #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field.      */
81874   #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field.                                 */
81875   #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field.                                 */
81876   #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure                                         */
81877   #define UICR_IPCT_GLOBAL_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure                                  */
81878 
81879 /* CH16 @Bit 16 : Channel number */
81880   #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Pos (16UL) /*!< Position of CH16 field.                                              */
81881   #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field.      */
81882   #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field.                                 */
81883   #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field.                                 */
81884   #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure                                         */
81885   #define UICR_IPCT_GLOBAL_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure                                  */
81886 
81887 /* CH17 @Bit 17 : Channel number */
81888   #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Pos (17UL) /*!< Position of CH17 field.                                              */
81889   #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field.      */
81890   #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field.                                 */
81891   #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field.                                 */
81892   #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure                                         */
81893   #define UICR_IPCT_GLOBAL_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure                                  */
81894 
81895 /* CH18 @Bit 18 : Channel number */
81896   #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Pos (18UL) /*!< Position of CH18 field.                                              */
81897   #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field.      */
81898   #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field.                                 */
81899   #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field.                                 */
81900   #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure                                         */
81901   #define UICR_IPCT_GLOBAL_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure                                  */
81902 
81903 /* CH19 @Bit 19 : Channel number */
81904   #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Pos (19UL) /*!< Position of CH19 field.                                              */
81905   #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field.      */
81906   #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field.                                 */
81907   #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field.                                 */
81908   #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure                                         */
81909   #define UICR_IPCT_GLOBAL_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure                                  */
81910 
81911 /* CH20 @Bit 20 : Channel number */
81912   #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Pos (20UL) /*!< Position of CH20 field.                                              */
81913   #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field.      */
81914   #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field.                                 */
81915   #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field.                                 */
81916   #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure                                         */
81917   #define UICR_IPCT_GLOBAL_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure                                  */
81918 
81919 /* CH21 @Bit 21 : Channel number */
81920   #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Pos (21UL) /*!< Position of CH21 field.                                              */
81921   #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field.      */
81922   #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field.                                 */
81923   #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field.                                 */
81924   #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure                                         */
81925   #define UICR_IPCT_GLOBAL_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure                                  */
81926 
81927 /* CH22 @Bit 22 : Channel number */
81928   #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Pos (22UL) /*!< Position of CH22 field.                                              */
81929   #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field.      */
81930   #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field.                                 */
81931   #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field.                                 */
81932   #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure                                         */
81933   #define UICR_IPCT_GLOBAL_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure                                  */
81934 
81935 /* CH23 @Bit 23 : Channel number */
81936   #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Pos (23UL) /*!< Position of CH23 field.                                              */
81937   #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field.      */
81938   #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field.                                 */
81939   #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field.                                 */
81940   #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure                                         */
81941   #define UICR_IPCT_GLOBAL_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure                                  */
81942 
81943 /* CH24 @Bit 24 : Channel number */
81944   #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Pos (24UL) /*!< Position of CH24 field.                                              */
81945   #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field.      */
81946   #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field.                                 */
81947   #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field.                                 */
81948   #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure                                         */
81949   #define UICR_IPCT_GLOBAL_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure                                  */
81950 
81951 /* CH25 @Bit 25 : Channel number */
81952   #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Pos (25UL) /*!< Position of CH25 field.                                              */
81953   #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field.      */
81954   #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field.                                 */
81955   #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field.                                 */
81956   #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure                                         */
81957   #define UICR_IPCT_GLOBAL_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure                                  */
81958 
81959 /* CH26 @Bit 26 : Channel number */
81960   #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Pos (26UL) /*!< Position of CH26 field.                                              */
81961   #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field.      */
81962   #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field.                                 */
81963   #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field.                                 */
81964   #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure                                         */
81965   #define UICR_IPCT_GLOBAL_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure                                  */
81966 
81967 /* CH27 @Bit 27 : Channel number */
81968   #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Pos (27UL) /*!< Position of CH27 field.                                              */
81969   #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field.      */
81970   #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field.                                 */
81971   #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field.                                 */
81972   #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure                                         */
81973   #define UICR_IPCT_GLOBAL_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure                                  */
81974 
81975 /* CH28 @Bit 28 : Channel number */
81976   #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Pos (28UL) /*!< Position of CH28 field.                                              */
81977   #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field.      */
81978   #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field.                                 */
81979   #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field.                                 */
81980   #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure                                         */
81981   #define UICR_IPCT_GLOBAL_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure                                  */
81982 
81983 /* CH29 @Bit 29 : Channel number */
81984   #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Pos (29UL) /*!< Position of CH29 field.                                              */
81985   #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field.      */
81986   #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field.                                 */
81987   #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field.                                 */
81988   #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure                                         */
81989   #define UICR_IPCT_GLOBAL_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure                                  */
81990 
81991 /* CH30 @Bit 30 : Channel number */
81992   #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Pos (30UL) /*!< Position of CH30 field.                                              */
81993   #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field.      */
81994   #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field.                                 */
81995   #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field.                                 */
81996   #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure                                         */
81997   #define UICR_IPCT_GLOBAL_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure                                  */
81998 
81999 /* CH31 @Bit 31 : Channel number */
82000   #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Pos (31UL) /*!< Position of CH31 field.                                              */
82001   #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Msk (0x1UL << UICR_IPCT_GLOBAL_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field.      */
82002   #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field.                                 */
82003   #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field.                                 */
82004   #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure                                         */
82005   #define UICR_IPCT_GLOBAL_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure                                  */
82006 
82007 
82008 
82009 /* ============================================ Struct UICR_IPCT_GLOBAL_INTERRUPT ============================================ */
82010 /**
82011   * @brief INTERRUPT [UICR_IPCT_GLOBAL_INTERRUPT] (unspecified)
82012   */
82013 typedef struct {
82014   __IOM uint32_t  OWN;                               /*!< (@ 0x00000000) Request ownership of the interrupts of IPCT[n] in
82015                                                                          Global domain*/
82016   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Request permission for the interrupts of IPCT[n] in
82017                                                                          Global domain*/
82018 } NRF_UICR_IPCT_GLOBAL_INTERRUPT_Type;               /*!< Size = 8 (0x008)                                                     */
82019 
82020 /* UICR_IPCT_GLOBAL_INTERRUPT_OWN: Request ownership of the interrupts of IPCT[n] in Global domain */
82021   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register.                           */
82022 
82023 /* INT0 @Bit 0 : Interrupt number */
82024   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Pos (0UL) /*!< Position of INT0 field.                                           */
82025   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Pos) /*!< Bit mask of INT0
82026                                                                             field.*/
82027   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Min (0x0UL) /*!< Min enumerator value of INT0 field.                             */
82028   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Max (0x1UL) /*!< Max enumerator value of INT0 field.                             */
82029   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_NotOwn (0x1UL) /*!< Do not own the interrupt 0                                   */
82030   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT0_Own (0x0UL) /*!< Own the interrupt 0                                             */
82031 
82032 /* INT1 @Bit 1 : Interrupt number */
82033   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Pos (1UL) /*!< Position of INT1 field.                                           */
82034   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Pos) /*!< Bit mask of INT1
82035                                                                             field.*/
82036   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Min (0x0UL) /*!< Min enumerator value of INT1 field.                             */
82037   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Max (0x1UL) /*!< Max enumerator value of INT1 field.                             */
82038   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_NotOwn (0x1UL) /*!< Do not own the interrupt 1                                   */
82039   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT1_Own (0x0UL) /*!< Own the interrupt 1                                             */
82040 
82041 /* INT2 @Bit 2 : Interrupt number */
82042   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Pos (2UL) /*!< Position of INT2 field.                                           */
82043   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Pos) /*!< Bit mask of INT2
82044                                                                             field.*/
82045   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Min (0x0UL) /*!< Min enumerator value of INT2 field.                             */
82046   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Max (0x1UL) /*!< Max enumerator value of INT2 field.                             */
82047   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_NotOwn (0x1UL) /*!< Do not own the interrupt 2                                   */
82048   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT2_Own (0x0UL) /*!< Own the interrupt 2                                             */
82049 
82050 /* INT3 @Bit 3 : Interrupt number */
82051   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Pos (3UL) /*!< Position of INT3 field.                                           */
82052   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Pos) /*!< Bit mask of INT3
82053                                                                             field.*/
82054   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Min (0x0UL) /*!< Min enumerator value of INT3 field.                             */
82055   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Max (0x1UL) /*!< Max enumerator value of INT3 field.                             */
82056   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_NotOwn (0x1UL) /*!< Do not own the interrupt 3                                   */
82057   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT3_Own (0x0UL) /*!< Own the interrupt 3                                             */
82058 
82059 /* INT4 @Bit 4 : Interrupt number */
82060   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Pos (4UL) /*!< Position of INT4 field.                                           */
82061   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Pos) /*!< Bit mask of INT4
82062                                                                             field.*/
82063   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Min (0x0UL) /*!< Min enumerator value of INT4 field.                             */
82064   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Max (0x1UL) /*!< Max enumerator value of INT4 field.                             */
82065   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_NotOwn (0x1UL) /*!< Do not own the interrupt 4                                   */
82066   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT4_Own (0x0UL) /*!< Own the interrupt 4                                             */
82067 
82068 /* INT5 @Bit 5 : Interrupt number */
82069   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Pos (5UL) /*!< Position of INT5 field.                                           */
82070   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Pos) /*!< Bit mask of INT5
82071                                                                             field.*/
82072   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Min (0x0UL) /*!< Min enumerator value of INT5 field.                             */
82073   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Max (0x1UL) /*!< Max enumerator value of INT5 field.                             */
82074   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_NotOwn (0x1UL) /*!< Do not own the interrupt 5                                   */
82075   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT5_Own (0x0UL) /*!< Own the interrupt 5                                             */
82076 
82077 /* INT6 @Bit 6 : Interrupt number */
82078   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Pos (6UL) /*!< Position of INT6 field.                                           */
82079   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Pos) /*!< Bit mask of INT6
82080                                                                             field.*/
82081   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Min (0x0UL) /*!< Min enumerator value of INT6 field.                             */
82082   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Max (0x1UL) /*!< Max enumerator value of INT6 field.                             */
82083   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_NotOwn (0x1UL) /*!< Do not own the interrupt 6                                   */
82084   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT6_Own (0x0UL) /*!< Own the interrupt 6                                             */
82085 
82086 /* INT7 @Bit 7 : Interrupt number */
82087   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Pos (7UL) /*!< Position of INT7 field.                                           */
82088   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Pos) /*!< Bit mask of INT7
82089                                                                             field.*/
82090   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Min (0x0UL) /*!< Min enumerator value of INT7 field.                             */
82091   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Max (0x1UL) /*!< Max enumerator value of INT7 field.                             */
82092   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_NotOwn (0x1UL) /*!< Do not own the interrupt 7                                   */
82093   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT7_Own (0x0UL) /*!< Own the interrupt 7                                             */
82094 
82095 /* INT8 @Bit 8 : Interrupt number */
82096   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Pos (8UL) /*!< Position of INT8 field.                                           */
82097   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Pos) /*!< Bit mask of INT8
82098                                                                             field.*/
82099   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Min (0x0UL) /*!< Min enumerator value of INT8 field.                             */
82100   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Max (0x1UL) /*!< Max enumerator value of INT8 field.                             */
82101   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_NotOwn (0x1UL) /*!< Do not own the interrupt 8                                   */
82102   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT8_Own (0x0UL) /*!< Own the interrupt 8                                             */
82103 
82104 /* INT9 @Bit 9 : Interrupt number */
82105   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Pos (9UL) /*!< Position of INT9 field.                                           */
82106   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Pos) /*!< Bit mask of INT9
82107                                                                             field.*/
82108   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Min (0x0UL) /*!< Min enumerator value of INT9 field.                             */
82109   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Max (0x1UL) /*!< Max enumerator value of INT9 field.                             */
82110   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_NotOwn (0x1UL) /*!< Do not own the interrupt 9                                   */
82111   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT9_Own (0x0UL) /*!< Own the interrupt 9                                             */
82112 
82113 /* INT10 @Bit 10 : Interrupt number */
82114   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Pos (10UL) /*!< Position of INT10 field.                                        */
82115   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Pos) /*!< Bit mask of INT10
82116                                                                             field.*/
82117   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Min (0x0UL) /*!< Min enumerator value of INT10 field.                           */
82118   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Max (0x1UL) /*!< Max enumerator value of INT10 field.                           */
82119   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_NotOwn (0x1UL) /*!< Do not own the interrupt 10                                 */
82120   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT10_Own (0x0UL) /*!< Own the interrupt 10                                           */
82121 
82122 /* INT11 @Bit 11 : Interrupt number */
82123   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Pos (11UL) /*!< Position of INT11 field.                                        */
82124   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Pos) /*!< Bit mask of INT11
82125                                                                             field.*/
82126   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Min (0x0UL) /*!< Min enumerator value of INT11 field.                           */
82127   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Max (0x1UL) /*!< Max enumerator value of INT11 field.                           */
82128   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_NotOwn (0x1UL) /*!< Do not own the interrupt 11                                 */
82129   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT11_Own (0x0UL) /*!< Own the interrupt 11                                           */
82130 
82131 /* INT12 @Bit 12 : Interrupt number */
82132   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Pos (12UL) /*!< Position of INT12 field.                                        */
82133   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Pos) /*!< Bit mask of INT12
82134                                                                             field.*/
82135   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Min (0x0UL) /*!< Min enumerator value of INT12 field.                           */
82136   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Max (0x1UL) /*!< Max enumerator value of INT12 field.                           */
82137   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_NotOwn (0x1UL) /*!< Do not own the interrupt 12                                 */
82138   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT12_Own (0x0UL) /*!< Own the interrupt 12                                           */
82139 
82140 /* INT13 @Bit 13 : Interrupt number */
82141   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Pos (13UL) /*!< Position of INT13 field.                                        */
82142   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Pos) /*!< Bit mask of INT13
82143                                                                             field.*/
82144   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Min (0x0UL) /*!< Min enumerator value of INT13 field.                           */
82145   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Max (0x1UL) /*!< Max enumerator value of INT13 field.                           */
82146   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_NotOwn (0x1UL) /*!< Do not own the interrupt 13                                 */
82147   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT13_Own (0x0UL) /*!< Own the interrupt 13                                           */
82148 
82149 /* INT14 @Bit 14 : Interrupt number */
82150   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Pos (14UL) /*!< Position of INT14 field.                                        */
82151   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Pos) /*!< Bit mask of INT14
82152                                                                             field.*/
82153   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Min (0x0UL) /*!< Min enumerator value of INT14 field.                           */
82154   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Max (0x1UL) /*!< Max enumerator value of INT14 field.                           */
82155   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_NotOwn (0x1UL) /*!< Do not own the interrupt 14                                 */
82156   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT14_Own (0x0UL) /*!< Own the interrupt 14                                           */
82157 
82158 /* INT15 @Bit 15 : Interrupt number */
82159   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Pos (15UL) /*!< Position of INT15 field.                                        */
82160   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Pos) /*!< Bit mask of INT15
82161                                                                             field.*/
82162   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Min (0x0UL) /*!< Min enumerator value of INT15 field.                           */
82163   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Max (0x1UL) /*!< Max enumerator value of INT15 field.                           */
82164   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_NotOwn (0x1UL) /*!< Do not own the interrupt 15                                 */
82165   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT15_Own (0x0UL) /*!< Own the interrupt 15                                           */
82166 
82167 /* INT16 @Bit 16 : Interrupt number */
82168   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Pos (16UL) /*!< Position of INT16 field.                                        */
82169   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Pos) /*!< Bit mask of INT16
82170                                                                             field.*/
82171   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Min (0x0UL) /*!< Min enumerator value of INT16 field.                           */
82172   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Max (0x1UL) /*!< Max enumerator value of INT16 field.                           */
82173   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_NotOwn (0x1UL) /*!< Do not own the interrupt 16                                 */
82174   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT16_Own (0x0UL) /*!< Own the interrupt 16                                           */
82175 
82176 /* INT17 @Bit 17 : Interrupt number */
82177   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Pos (17UL) /*!< Position of INT17 field.                                        */
82178   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Pos) /*!< Bit mask of INT17
82179                                                                             field.*/
82180   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Min (0x0UL) /*!< Min enumerator value of INT17 field.                           */
82181   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Max (0x1UL) /*!< Max enumerator value of INT17 field.                           */
82182   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_NotOwn (0x1UL) /*!< Do not own the interrupt 17                                 */
82183   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT17_Own (0x0UL) /*!< Own the interrupt 17                                           */
82184 
82185 /* INT18 @Bit 18 : Interrupt number */
82186   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Pos (18UL) /*!< Position of INT18 field.                                        */
82187   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Pos) /*!< Bit mask of INT18
82188                                                                             field.*/
82189   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Min (0x0UL) /*!< Min enumerator value of INT18 field.                           */
82190   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Max (0x1UL) /*!< Max enumerator value of INT18 field.                           */
82191   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_NotOwn (0x1UL) /*!< Do not own the interrupt 18                                 */
82192   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT18_Own (0x0UL) /*!< Own the interrupt 18                                           */
82193 
82194 /* INT19 @Bit 19 : Interrupt number */
82195   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Pos (19UL) /*!< Position of INT19 field.                                        */
82196   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Pos) /*!< Bit mask of INT19
82197                                                                             field.*/
82198   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Min (0x0UL) /*!< Min enumerator value of INT19 field.                           */
82199   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Max (0x1UL) /*!< Max enumerator value of INT19 field.                           */
82200   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_NotOwn (0x1UL) /*!< Do not own the interrupt 19                                 */
82201   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT19_Own (0x0UL) /*!< Own the interrupt 19                                           */
82202 
82203 /* INT20 @Bit 20 : Interrupt number */
82204   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Pos (20UL) /*!< Position of INT20 field.                                        */
82205   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Pos) /*!< Bit mask of INT20
82206                                                                             field.*/
82207   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Min (0x0UL) /*!< Min enumerator value of INT20 field.                           */
82208   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Max (0x1UL) /*!< Max enumerator value of INT20 field.                           */
82209   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_NotOwn (0x1UL) /*!< Do not own the interrupt 20                                 */
82210   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT20_Own (0x0UL) /*!< Own the interrupt 20                                           */
82211 
82212 /* INT21 @Bit 21 : Interrupt number */
82213   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Pos (21UL) /*!< Position of INT21 field.                                        */
82214   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Pos) /*!< Bit mask of INT21
82215                                                                             field.*/
82216   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Min (0x0UL) /*!< Min enumerator value of INT21 field.                           */
82217   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Max (0x1UL) /*!< Max enumerator value of INT21 field.                           */
82218   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_NotOwn (0x1UL) /*!< Do not own the interrupt 21                                 */
82219   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT21_Own (0x0UL) /*!< Own the interrupt 21                                           */
82220 
82221 /* INT22 @Bit 22 : Interrupt number */
82222   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Pos (22UL) /*!< Position of INT22 field.                                        */
82223   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Pos) /*!< Bit mask of INT22
82224                                                                             field.*/
82225   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Min (0x0UL) /*!< Min enumerator value of INT22 field.                           */
82226   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Max (0x1UL) /*!< Max enumerator value of INT22 field.                           */
82227   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_NotOwn (0x1UL) /*!< Do not own the interrupt 22                                 */
82228   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT22_Own (0x0UL) /*!< Own the interrupt 22                                           */
82229 
82230 /* INT23 @Bit 23 : Interrupt number */
82231   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Pos (23UL) /*!< Position of INT23 field.                                        */
82232   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Pos) /*!< Bit mask of INT23
82233                                                                             field.*/
82234   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Min (0x0UL) /*!< Min enumerator value of INT23 field.                           */
82235   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Max (0x1UL) /*!< Max enumerator value of INT23 field.                           */
82236   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_NotOwn (0x1UL) /*!< Do not own the interrupt 23                                 */
82237   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT23_Own (0x0UL) /*!< Own the interrupt 23                                           */
82238 
82239 /* INT24 @Bit 24 : Interrupt number */
82240   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Pos (24UL) /*!< Position of INT24 field.                                        */
82241   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Pos) /*!< Bit mask of INT24
82242                                                                             field.*/
82243   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Min (0x0UL) /*!< Min enumerator value of INT24 field.                           */
82244   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Max (0x1UL) /*!< Max enumerator value of INT24 field.                           */
82245   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_NotOwn (0x1UL) /*!< Do not own the interrupt 24                                 */
82246   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT24_Own (0x0UL) /*!< Own the interrupt 24                                           */
82247 
82248 /* INT25 @Bit 25 : Interrupt number */
82249   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Pos (25UL) /*!< Position of INT25 field.                                        */
82250   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Pos) /*!< Bit mask of INT25
82251                                                                             field.*/
82252   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Min (0x0UL) /*!< Min enumerator value of INT25 field.                           */
82253   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Max (0x1UL) /*!< Max enumerator value of INT25 field.                           */
82254   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_NotOwn (0x1UL) /*!< Do not own the interrupt 25                                 */
82255   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT25_Own (0x0UL) /*!< Own the interrupt 25                                           */
82256 
82257 /* INT26 @Bit 26 : Interrupt number */
82258   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Pos (26UL) /*!< Position of INT26 field.                                        */
82259   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Pos) /*!< Bit mask of INT26
82260                                                                             field.*/
82261   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Min (0x0UL) /*!< Min enumerator value of INT26 field.                           */
82262   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Max (0x1UL) /*!< Max enumerator value of INT26 field.                           */
82263   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_NotOwn (0x1UL) /*!< Do not own the interrupt 26                                 */
82264   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT26_Own (0x0UL) /*!< Own the interrupt 26                                           */
82265 
82266 /* INT27 @Bit 27 : Interrupt number */
82267   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Pos (27UL) /*!< Position of INT27 field.                                        */
82268   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Pos) /*!< Bit mask of INT27
82269                                                                             field.*/
82270   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Min (0x0UL) /*!< Min enumerator value of INT27 field.                           */
82271   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Max (0x1UL) /*!< Max enumerator value of INT27 field.                           */
82272   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_NotOwn (0x1UL) /*!< Do not own the interrupt 27                                 */
82273   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT27_Own (0x0UL) /*!< Own the interrupt 27                                           */
82274 
82275 /* INT28 @Bit 28 : Interrupt number */
82276   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Pos (28UL) /*!< Position of INT28 field.                                        */
82277   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Pos) /*!< Bit mask of INT28
82278                                                                             field.*/
82279   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Min (0x0UL) /*!< Min enumerator value of INT28 field.                           */
82280   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Max (0x1UL) /*!< Max enumerator value of INT28 field.                           */
82281   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_NotOwn (0x1UL) /*!< Do not own the interrupt 28                                 */
82282   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT28_Own (0x0UL) /*!< Own the interrupt 28                                           */
82283 
82284 /* INT29 @Bit 29 : Interrupt number */
82285   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Pos (29UL) /*!< Position of INT29 field.                                        */
82286   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Pos) /*!< Bit mask of INT29
82287                                                                             field.*/
82288   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Min (0x0UL) /*!< Min enumerator value of INT29 field.                           */
82289   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Max (0x1UL) /*!< Max enumerator value of INT29 field.                           */
82290   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_NotOwn (0x1UL) /*!< Do not own the interrupt 29                                 */
82291   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT29_Own (0x0UL) /*!< Own the interrupt 29                                           */
82292 
82293 /* INT30 @Bit 30 : Interrupt number */
82294   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Pos (30UL) /*!< Position of INT30 field.                                        */
82295   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Pos) /*!< Bit mask of INT30
82296                                                                             field.*/
82297   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Min (0x0UL) /*!< Min enumerator value of INT30 field.                           */
82298   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Max (0x1UL) /*!< Max enumerator value of INT30 field.                           */
82299   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_NotOwn (0x1UL) /*!< Do not own the interrupt 30                                 */
82300   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT30_Own (0x0UL) /*!< Own the interrupt 30                                           */
82301 
82302 /* INT31 @Bit 31 : Interrupt number */
82303   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Pos (31UL) /*!< Position of INT31 field.                                        */
82304   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Pos) /*!< Bit mask of INT31
82305                                                                             field.*/
82306   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Min (0x0UL) /*!< Min enumerator value of INT31 field.                           */
82307   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Max (0x1UL) /*!< Max enumerator value of INT31 field.                           */
82308   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_NotOwn (0x1UL) /*!< Do not own the interrupt 31                                 */
82309   #define UICR_IPCT_GLOBAL_INTERRUPT_OWN_INT31_Own (0x0UL) /*!< Own the interrupt 31                                           */
82310 
82311 
82312 /* UICR_IPCT_GLOBAL_INTERRUPT_SECURE: Request permission for the interrupts of IPCT[n] in Global domain */
82313   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                     */
82314 
82315 /* INT0 @Bit 0 : Interrupt number */
82316   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Pos (0UL) /*!< Position of INT0 field.                                        */
82317   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Pos) /*!< Bit mask of INT0
82318                                                                             field.*/
82319   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Min (0x0UL) /*!< Min enumerator value of INT0 field.                          */
82320   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Max (0x1UL) /*!< Max enumerator value of INT0 field.                          */
82321   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_Secure (0x1UL) /*!< The interrupt 0 is secure                                 */
82322   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT0_NonSecure (0x0UL) /*!< The interrupt 0 is non-secure                          */
82323 
82324 /* INT1 @Bit 1 : Interrupt number */
82325   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Pos (1UL) /*!< Position of INT1 field.                                        */
82326   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Pos) /*!< Bit mask of INT1
82327                                                                             field.*/
82328   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Min (0x0UL) /*!< Min enumerator value of INT1 field.                          */
82329   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Max (0x1UL) /*!< Max enumerator value of INT1 field.                          */
82330   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_Secure (0x1UL) /*!< The interrupt 1 is secure                                 */
82331   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT1_NonSecure (0x0UL) /*!< The interrupt 1 is non-secure                          */
82332 
82333 /* INT2 @Bit 2 : Interrupt number */
82334   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Pos (2UL) /*!< Position of INT2 field.                                        */
82335   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Pos) /*!< Bit mask of INT2
82336                                                                             field.*/
82337   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Min (0x0UL) /*!< Min enumerator value of INT2 field.                          */
82338   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Max (0x1UL) /*!< Max enumerator value of INT2 field.                          */
82339   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_Secure (0x1UL) /*!< The interrupt 2 is secure                                 */
82340   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT2_NonSecure (0x0UL) /*!< The interrupt 2 is non-secure                          */
82341 
82342 /* INT3 @Bit 3 : Interrupt number */
82343   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Pos (3UL) /*!< Position of INT3 field.                                        */
82344   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Pos) /*!< Bit mask of INT3
82345                                                                             field.*/
82346   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Min (0x0UL) /*!< Min enumerator value of INT3 field.                          */
82347   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Max (0x1UL) /*!< Max enumerator value of INT3 field.                          */
82348   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_Secure (0x1UL) /*!< The interrupt 3 is secure                                 */
82349   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT3_NonSecure (0x0UL) /*!< The interrupt 3 is non-secure                          */
82350 
82351 /* INT4 @Bit 4 : Interrupt number */
82352   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Pos (4UL) /*!< Position of INT4 field.                                        */
82353   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Pos) /*!< Bit mask of INT4
82354                                                                             field.*/
82355   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Min (0x0UL) /*!< Min enumerator value of INT4 field.                          */
82356   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Max (0x1UL) /*!< Max enumerator value of INT4 field.                          */
82357   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_Secure (0x1UL) /*!< The interrupt 4 is secure                                 */
82358   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT4_NonSecure (0x0UL) /*!< The interrupt 4 is non-secure                          */
82359 
82360 /* INT5 @Bit 5 : Interrupt number */
82361   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Pos (5UL) /*!< Position of INT5 field.                                        */
82362   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Pos) /*!< Bit mask of INT5
82363                                                                             field.*/
82364   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Min (0x0UL) /*!< Min enumerator value of INT5 field.                          */
82365   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Max (0x1UL) /*!< Max enumerator value of INT5 field.                          */
82366   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_Secure (0x1UL) /*!< The interrupt 5 is secure                                 */
82367   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT5_NonSecure (0x0UL) /*!< The interrupt 5 is non-secure                          */
82368 
82369 /* INT6 @Bit 6 : Interrupt number */
82370   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Pos (6UL) /*!< Position of INT6 field.                                        */
82371   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Pos) /*!< Bit mask of INT6
82372                                                                             field.*/
82373   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Min (0x0UL) /*!< Min enumerator value of INT6 field.                          */
82374   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Max (0x1UL) /*!< Max enumerator value of INT6 field.                          */
82375   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_Secure (0x1UL) /*!< The interrupt 6 is secure                                 */
82376   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT6_NonSecure (0x0UL) /*!< The interrupt 6 is non-secure                          */
82377 
82378 /* INT7 @Bit 7 : Interrupt number */
82379   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Pos (7UL) /*!< Position of INT7 field.                                        */
82380   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Pos) /*!< Bit mask of INT7
82381                                                                             field.*/
82382   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Min (0x0UL) /*!< Min enumerator value of INT7 field.                          */
82383   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Max (0x1UL) /*!< Max enumerator value of INT7 field.                          */
82384   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_Secure (0x1UL) /*!< The interrupt 7 is secure                                 */
82385   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT7_NonSecure (0x0UL) /*!< The interrupt 7 is non-secure                          */
82386 
82387 /* INT8 @Bit 8 : Interrupt number */
82388   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Pos (8UL) /*!< Position of INT8 field.                                        */
82389   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Pos) /*!< Bit mask of INT8
82390                                                                             field.*/
82391   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Min (0x0UL) /*!< Min enumerator value of INT8 field.                          */
82392   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Max (0x1UL) /*!< Max enumerator value of INT8 field.                          */
82393   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_Secure (0x1UL) /*!< The interrupt 8 is secure                                 */
82394   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT8_NonSecure (0x0UL) /*!< The interrupt 8 is non-secure                          */
82395 
82396 /* INT9 @Bit 9 : Interrupt number */
82397   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Pos (9UL) /*!< Position of INT9 field.                                        */
82398   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Pos) /*!< Bit mask of INT9
82399                                                                             field.*/
82400   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Min (0x0UL) /*!< Min enumerator value of INT9 field.                          */
82401   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Max (0x1UL) /*!< Max enumerator value of INT9 field.                          */
82402   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_Secure (0x1UL) /*!< The interrupt 9 is secure                                 */
82403   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT9_NonSecure (0x0UL) /*!< The interrupt 9 is non-secure                          */
82404 
82405 /* INT10 @Bit 10 : Interrupt number */
82406   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Pos (10UL) /*!< Position of INT10 field.                                     */
82407   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Pos) /*!< Bit mask of
82408                                                                             INT10 field.*/
82409   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Min (0x0UL) /*!< Min enumerator value of INT10 field.                        */
82410   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Max (0x1UL) /*!< Max enumerator value of INT10 field.                        */
82411   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_Secure (0x1UL) /*!< The interrupt 10 is secure                               */
82412   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT10_NonSecure (0x0UL) /*!< The interrupt 10 is non-secure                        */
82413 
82414 /* INT11 @Bit 11 : Interrupt number */
82415   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Pos (11UL) /*!< Position of INT11 field.                                     */
82416   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Pos) /*!< Bit mask of
82417                                                                             INT11 field.*/
82418   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Min (0x0UL) /*!< Min enumerator value of INT11 field.                        */
82419   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Max (0x1UL) /*!< Max enumerator value of INT11 field.                        */
82420   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_Secure (0x1UL) /*!< The interrupt 11 is secure                               */
82421   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT11_NonSecure (0x0UL) /*!< The interrupt 11 is non-secure                        */
82422 
82423 /* INT12 @Bit 12 : Interrupt number */
82424   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Pos (12UL) /*!< Position of INT12 field.                                     */
82425   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Pos) /*!< Bit mask of
82426                                                                             INT12 field.*/
82427   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Min (0x0UL) /*!< Min enumerator value of INT12 field.                        */
82428   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Max (0x1UL) /*!< Max enumerator value of INT12 field.                        */
82429   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_Secure (0x1UL) /*!< The interrupt 12 is secure                               */
82430   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT12_NonSecure (0x0UL) /*!< The interrupt 12 is non-secure                        */
82431 
82432 /* INT13 @Bit 13 : Interrupt number */
82433   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Pos (13UL) /*!< Position of INT13 field.                                     */
82434   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Pos) /*!< Bit mask of
82435                                                                             INT13 field.*/
82436   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Min (0x0UL) /*!< Min enumerator value of INT13 field.                        */
82437   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Max (0x1UL) /*!< Max enumerator value of INT13 field.                        */
82438   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_Secure (0x1UL) /*!< The interrupt 13 is secure                               */
82439   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT13_NonSecure (0x0UL) /*!< The interrupt 13 is non-secure                        */
82440 
82441 /* INT14 @Bit 14 : Interrupt number */
82442   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Pos (14UL) /*!< Position of INT14 field.                                     */
82443   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Pos) /*!< Bit mask of
82444                                                                             INT14 field.*/
82445   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Min (0x0UL) /*!< Min enumerator value of INT14 field.                        */
82446   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Max (0x1UL) /*!< Max enumerator value of INT14 field.                        */
82447   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_Secure (0x1UL) /*!< The interrupt 14 is secure                               */
82448   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT14_NonSecure (0x0UL) /*!< The interrupt 14 is non-secure                        */
82449 
82450 /* INT15 @Bit 15 : Interrupt number */
82451   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Pos (15UL) /*!< Position of INT15 field.                                     */
82452   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Pos) /*!< Bit mask of
82453                                                                             INT15 field.*/
82454   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Min (0x0UL) /*!< Min enumerator value of INT15 field.                        */
82455   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Max (0x1UL) /*!< Max enumerator value of INT15 field.                        */
82456   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_Secure (0x1UL) /*!< The interrupt 15 is secure                               */
82457   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT15_NonSecure (0x0UL) /*!< The interrupt 15 is non-secure                        */
82458 
82459 /* INT16 @Bit 16 : Interrupt number */
82460   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Pos (16UL) /*!< Position of INT16 field.                                     */
82461   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Pos) /*!< Bit mask of
82462                                                                             INT16 field.*/
82463   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Min (0x0UL) /*!< Min enumerator value of INT16 field.                        */
82464   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Max (0x1UL) /*!< Max enumerator value of INT16 field.                        */
82465   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_Secure (0x1UL) /*!< The interrupt 16 is secure                               */
82466   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT16_NonSecure (0x0UL) /*!< The interrupt 16 is non-secure                        */
82467 
82468 /* INT17 @Bit 17 : Interrupt number */
82469   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Pos (17UL) /*!< Position of INT17 field.                                     */
82470   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Pos) /*!< Bit mask of
82471                                                                             INT17 field.*/
82472   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Min (0x0UL) /*!< Min enumerator value of INT17 field.                        */
82473   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Max (0x1UL) /*!< Max enumerator value of INT17 field.                        */
82474   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_Secure (0x1UL) /*!< The interrupt 17 is secure                               */
82475   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT17_NonSecure (0x0UL) /*!< The interrupt 17 is non-secure                        */
82476 
82477 /* INT18 @Bit 18 : Interrupt number */
82478   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Pos (18UL) /*!< Position of INT18 field.                                     */
82479   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Pos) /*!< Bit mask of
82480                                                                             INT18 field.*/
82481   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Min (0x0UL) /*!< Min enumerator value of INT18 field.                        */
82482   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Max (0x1UL) /*!< Max enumerator value of INT18 field.                        */
82483   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_Secure (0x1UL) /*!< The interrupt 18 is secure                               */
82484   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT18_NonSecure (0x0UL) /*!< The interrupt 18 is non-secure                        */
82485 
82486 /* INT19 @Bit 19 : Interrupt number */
82487   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Pos (19UL) /*!< Position of INT19 field.                                     */
82488   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Pos) /*!< Bit mask of
82489                                                                             INT19 field.*/
82490   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Min (0x0UL) /*!< Min enumerator value of INT19 field.                        */
82491   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Max (0x1UL) /*!< Max enumerator value of INT19 field.                        */
82492   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_Secure (0x1UL) /*!< The interrupt 19 is secure                               */
82493   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT19_NonSecure (0x0UL) /*!< The interrupt 19 is non-secure                        */
82494 
82495 /* INT20 @Bit 20 : Interrupt number */
82496   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Pos (20UL) /*!< Position of INT20 field.                                     */
82497   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Pos) /*!< Bit mask of
82498                                                                             INT20 field.*/
82499   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Min (0x0UL) /*!< Min enumerator value of INT20 field.                        */
82500   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Max (0x1UL) /*!< Max enumerator value of INT20 field.                        */
82501   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_Secure (0x1UL) /*!< The interrupt 20 is secure                               */
82502   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT20_NonSecure (0x0UL) /*!< The interrupt 20 is non-secure                        */
82503 
82504 /* INT21 @Bit 21 : Interrupt number */
82505   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Pos (21UL) /*!< Position of INT21 field.                                     */
82506   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Pos) /*!< Bit mask of
82507                                                                             INT21 field.*/
82508   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Min (0x0UL) /*!< Min enumerator value of INT21 field.                        */
82509   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Max (0x1UL) /*!< Max enumerator value of INT21 field.                        */
82510   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_Secure (0x1UL) /*!< The interrupt 21 is secure                               */
82511   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT21_NonSecure (0x0UL) /*!< The interrupt 21 is non-secure                        */
82512 
82513 /* INT22 @Bit 22 : Interrupt number */
82514   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Pos (22UL) /*!< Position of INT22 field.                                     */
82515   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Pos) /*!< Bit mask of
82516                                                                             INT22 field.*/
82517   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Min (0x0UL) /*!< Min enumerator value of INT22 field.                        */
82518   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Max (0x1UL) /*!< Max enumerator value of INT22 field.                        */
82519   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_Secure (0x1UL) /*!< The interrupt 22 is secure                               */
82520   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT22_NonSecure (0x0UL) /*!< The interrupt 22 is non-secure                        */
82521 
82522 /* INT23 @Bit 23 : Interrupt number */
82523   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Pos (23UL) /*!< Position of INT23 field.                                     */
82524   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Pos) /*!< Bit mask of
82525                                                                             INT23 field.*/
82526   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Min (0x0UL) /*!< Min enumerator value of INT23 field.                        */
82527   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Max (0x1UL) /*!< Max enumerator value of INT23 field.                        */
82528   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_Secure (0x1UL) /*!< The interrupt 23 is secure                               */
82529   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT23_NonSecure (0x0UL) /*!< The interrupt 23 is non-secure                        */
82530 
82531 /* INT24 @Bit 24 : Interrupt number */
82532   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Pos (24UL) /*!< Position of INT24 field.                                     */
82533   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Pos) /*!< Bit mask of
82534                                                                             INT24 field.*/
82535   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Min (0x0UL) /*!< Min enumerator value of INT24 field.                        */
82536   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Max (0x1UL) /*!< Max enumerator value of INT24 field.                        */
82537   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_Secure (0x1UL) /*!< The interrupt 24 is secure                               */
82538   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT24_NonSecure (0x0UL) /*!< The interrupt 24 is non-secure                        */
82539 
82540 /* INT25 @Bit 25 : Interrupt number */
82541   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Pos (25UL) /*!< Position of INT25 field.                                     */
82542   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Pos) /*!< Bit mask of
82543                                                                             INT25 field.*/
82544   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Min (0x0UL) /*!< Min enumerator value of INT25 field.                        */
82545   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Max (0x1UL) /*!< Max enumerator value of INT25 field.                        */
82546   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_Secure (0x1UL) /*!< The interrupt 25 is secure                               */
82547   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT25_NonSecure (0x0UL) /*!< The interrupt 25 is non-secure                        */
82548 
82549 /* INT26 @Bit 26 : Interrupt number */
82550   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Pos (26UL) /*!< Position of INT26 field.                                     */
82551   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Pos) /*!< Bit mask of
82552                                                                             INT26 field.*/
82553   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Min (0x0UL) /*!< Min enumerator value of INT26 field.                        */
82554   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Max (0x1UL) /*!< Max enumerator value of INT26 field.                        */
82555   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_Secure (0x1UL) /*!< The interrupt 26 is secure                               */
82556   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT26_NonSecure (0x0UL) /*!< The interrupt 26 is non-secure                        */
82557 
82558 /* INT27 @Bit 27 : Interrupt number */
82559   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Pos (27UL) /*!< Position of INT27 field.                                     */
82560   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Pos) /*!< Bit mask of
82561                                                                             INT27 field.*/
82562   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Min (0x0UL) /*!< Min enumerator value of INT27 field.                        */
82563   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Max (0x1UL) /*!< Max enumerator value of INT27 field.                        */
82564   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_Secure (0x1UL) /*!< The interrupt 27 is secure                               */
82565   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT27_NonSecure (0x0UL) /*!< The interrupt 27 is non-secure                        */
82566 
82567 /* INT28 @Bit 28 : Interrupt number */
82568   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Pos (28UL) /*!< Position of INT28 field.                                     */
82569   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Pos) /*!< Bit mask of
82570                                                                             INT28 field.*/
82571   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Min (0x0UL) /*!< Min enumerator value of INT28 field.                        */
82572   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Max (0x1UL) /*!< Max enumerator value of INT28 field.                        */
82573   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_Secure (0x1UL) /*!< The interrupt 28 is secure                               */
82574   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT28_NonSecure (0x0UL) /*!< The interrupt 28 is non-secure                        */
82575 
82576 /* INT29 @Bit 29 : Interrupt number */
82577   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Pos (29UL) /*!< Position of INT29 field.                                     */
82578   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Pos) /*!< Bit mask of
82579                                                                             INT29 field.*/
82580   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Min (0x0UL) /*!< Min enumerator value of INT29 field.                        */
82581   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Max (0x1UL) /*!< Max enumerator value of INT29 field.                        */
82582   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_Secure (0x1UL) /*!< The interrupt 29 is secure                               */
82583   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT29_NonSecure (0x0UL) /*!< The interrupt 29 is non-secure                        */
82584 
82585 /* INT30 @Bit 30 : Interrupt number */
82586   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Pos (30UL) /*!< Position of INT30 field.                                     */
82587   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Pos) /*!< Bit mask of
82588                                                                             INT30 field.*/
82589   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Min (0x0UL) /*!< Min enumerator value of INT30 field.                        */
82590   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Max (0x1UL) /*!< Max enumerator value of INT30 field.                        */
82591   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_Secure (0x1UL) /*!< The interrupt 30 is secure                               */
82592   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT30_NonSecure (0x0UL) /*!< The interrupt 30 is non-secure                        */
82593 
82594 /* INT31 @Bit 31 : Interrupt number */
82595   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Pos (31UL) /*!< Position of INT31 field.                                     */
82596   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Msk (0x1UL << UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Pos) /*!< Bit mask of
82597                                                                             INT31 field.*/
82598   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Min (0x0UL) /*!< Min enumerator value of INT31 field.                        */
82599   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Max (0x1UL) /*!< Max enumerator value of INT31 field.                        */
82600   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_Secure (0x1UL) /*!< The interrupt 31 is secure                               */
82601   #define UICR_IPCT_GLOBAL_INTERRUPT_SECURE_INT31_NonSecure (0x0UL) /*!< The interrupt 31 is non-secure                        */
82602 
82603 
82604 
82605 /* ================================================= Struct UICR_IPCT_GLOBAL ================================================= */
82606 /**
82607   * @brief GLOBAL [UICR_IPCT_GLOBAL] (unspecified)
82608   */
82609 typedef struct {
82610   __IOM uint32_t  INSTANCE;                          /*!< (@ 0x00000000) Address of the IPCT instance associated with
82611                                                                          IPCT[n].GLOBAL*/
82612   __IOM NRF_UICR_IPCT_GLOBAL_CH_Type CH;             /*!< (@ 0x00000004) (unspecified)                                         */
82613   __IOM NRF_UICR_IPCT_GLOBAL_INTERRUPT_Type INTERRUPT; /*!< (@ 0x0000000C) (unspecified)                                       */
82614 } NRF_UICR_IPCT_GLOBAL_Type;                         /*!< Size = 20 (0x014)                                                    */
82615   #define UICR_IPCT_GLOBAL_MaxCount (2UL)            /*!< Size of GLOBAL[2] array.                                             */
82616   #define UICR_IPCT_GLOBAL_MaxIndex (1UL)            /*!< Max index of GLOBAL[2] array.                                        */
82617   #define UICR_IPCT_GLOBAL_MinIndex (0UL)            /*!< Min index of GLOBAL[2] array.                                        */
82618 
82619 /* UICR_IPCT_GLOBAL_INSTANCE: Address of the IPCT instance associated with IPCT[n].GLOBAL */
82620   #define UICR_IPCT_GLOBAL_INSTANCE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INSTANCE register.                           */
82621 
82622 /* ADDRESS @Bits 0..31 : Instance address */
82623   #define UICR_IPCT_GLOBAL_INSTANCE_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                          */
82624   #define UICR_IPCT_GLOBAL_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICR_IPCT_GLOBAL_INSTANCE_ADDRESS_Pos) /*!< Bit mask of ADDRESS
82625                                                                             field.*/
82626 
82627 
82628 
82629 /* ==================================================== Struct UICR_IPCT ===================================================== */
82630 /**
82631   * @brief IPCT [UICR_IPCT] (unspecified)
82632   */
82633 typedef struct {
82634   __IOM NRF_UICR_IPCT_LOCAL_Type LOCAL;              /*!< (@ 0x00000000) (unspecified)                                         */
82635   __IOM NRF_UICR_IPCT_GLOBAL_Type GLOBAL[2];         /*!< (@ 0x00000008) (unspecified)                                         */
82636 } NRF_UICR_IPCT_Type;                                /*!< Size = 48 (0x030)                                                    */
82637 
82638 
82639 /* ============================================= Struct UICR_DPPI_LOCAL_CH_LINK ============================================== */
82640 /**
82641   * @brief LINK [UICR_DPPI_LOCAL_CH_LINK] (unspecified)
82642   */
82643 typedef struct {
82644   __IOM uint32_t  DIR;                               /*!< (@ 0x00000000) Request linking the channels of DPPI[n] in local domain
82645                                                                          as source or sink*/
82646   __IOM uint32_t  EN;                                /*!< (@ 0x00000004) Request linking of the channels of DPPI[n] in the local
82647                                                                          domain*/
82648 } NRF_UICR_DPPI_LOCAL_CH_LINK_Type;                  /*!< Size = 8 (0x008)                                                     */
82649 
82650 /* UICR_DPPI_LOCAL_CH_LINK_DIR: Request linking the channels of DPPI[n] in local domain as source or sink */
82651   #define UICR_DPPI_LOCAL_CH_LINK_DIR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIR register.                              */
82652 
82653 /* CH0 @Bit 0 : Link direction */
82654   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Pos (0UL)  /*!< Position of CH0 field.                                               */
82655   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Pos) /*!< Bit mask of CH0 field.       */
82656   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field.                                  */
82657   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field.                                  */
82658   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Source (0x1UL) /*!< The channel 0 is linked as source                                */
82659   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH0_Sink (0x0UL) /*!< The channel 0 is linked as sink                                    */
82660 
82661 /* CH1 @Bit 1 : Link direction */
82662   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Pos (1UL)  /*!< Position of CH1 field.                                               */
82663   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Pos) /*!< Bit mask of CH1 field.       */
82664   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field.                                  */
82665   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field.                                  */
82666   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Source (0x1UL) /*!< The channel 1 is linked as source                                */
82667   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH1_Sink (0x0UL) /*!< The channel 1 is linked as sink                                    */
82668 
82669 /* CH2 @Bit 2 : Link direction */
82670   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Pos (2UL)  /*!< Position of CH2 field.                                               */
82671   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Pos) /*!< Bit mask of CH2 field.       */
82672   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field.                                  */
82673   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field.                                  */
82674   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Source (0x1UL) /*!< The channel 2 is linked as source                                */
82675   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH2_Sink (0x0UL) /*!< The channel 2 is linked as sink                                    */
82676 
82677 /* CH3 @Bit 3 : Link direction */
82678   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Pos (3UL)  /*!< Position of CH3 field.                                               */
82679   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Pos) /*!< Bit mask of CH3 field.       */
82680   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field.                                  */
82681   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field.                                  */
82682   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Source (0x1UL) /*!< The channel 3 is linked as source                                */
82683   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH3_Sink (0x0UL) /*!< The channel 3 is linked as sink                                    */
82684 
82685 /* CH4 @Bit 4 : Link direction */
82686   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Pos (4UL)  /*!< Position of CH4 field.                                               */
82687   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Pos) /*!< Bit mask of CH4 field.       */
82688   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field.                                  */
82689   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field.                                  */
82690   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Source (0x1UL) /*!< The channel 4 is linked as source                                */
82691   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH4_Sink (0x0UL) /*!< The channel 4 is linked as sink                                    */
82692 
82693 /* CH5 @Bit 5 : Link direction */
82694   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Pos (5UL)  /*!< Position of CH5 field.                                               */
82695   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Pos) /*!< Bit mask of CH5 field.       */
82696   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field.                                  */
82697   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field.                                  */
82698   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Source (0x1UL) /*!< The channel 5 is linked as source                                */
82699   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH5_Sink (0x0UL) /*!< The channel 5 is linked as sink                                    */
82700 
82701 /* CH6 @Bit 6 : Link direction */
82702   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Pos (6UL)  /*!< Position of CH6 field.                                               */
82703   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Pos) /*!< Bit mask of CH6 field.       */
82704   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field.                                  */
82705   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field.                                  */
82706   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Source (0x1UL) /*!< The channel 6 is linked as source                                */
82707   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH6_Sink (0x0UL) /*!< The channel 6 is linked as sink                                    */
82708 
82709 /* CH7 @Bit 7 : Link direction */
82710   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Pos (7UL)  /*!< Position of CH7 field.                                               */
82711   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Pos) /*!< Bit mask of CH7 field.       */
82712   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field.                                  */
82713   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field.                                  */
82714   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Source (0x1UL) /*!< The channel 7 is linked as source                                */
82715   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH7_Sink (0x0UL) /*!< The channel 7 is linked as sink                                    */
82716 
82717 /* CH8 @Bit 8 : Link direction */
82718   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Pos (8UL)  /*!< Position of CH8 field.                                               */
82719   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Pos) /*!< Bit mask of CH8 field.       */
82720   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field.                                  */
82721   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field.                                  */
82722   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Source (0x1UL) /*!< The channel 8 is linked as source                                */
82723   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH8_Sink (0x0UL) /*!< The channel 8 is linked as sink                                    */
82724 
82725 /* CH9 @Bit 9 : Link direction */
82726   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Pos (9UL)  /*!< Position of CH9 field.                                               */
82727   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Pos) /*!< Bit mask of CH9 field.       */
82728   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field.                                  */
82729   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field.                                  */
82730   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Source (0x1UL) /*!< The channel 9 is linked as source                                */
82731   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH9_Sink (0x0UL) /*!< The channel 9 is linked as sink                                    */
82732 
82733 /* CH10 @Bit 10 : Link direction */
82734   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Pos (10UL) /*!< Position of CH10 field.                                             */
82735   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Pos) /*!< Bit mask of CH10 field.    */
82736   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field.                                */
82737   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field.                                */
82738   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Source (0x1UL) /*!< The channel 10 is linked as source                              */
82739   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH10_Sink (0x0UL) /*!< The channel 10 is linked as sink                                  */
82740 
82741 /* CH11 @Bit 11 : Link direction */
82742   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Pos (11UL) /*!< Position of CH11 field.                                             */
82743   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Pos) /*!< Bit mask of CH11 field.    */
82744   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field.                                */
82745   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field.                                */
82746   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Source (0x1UL) /*!< The channel 11 is linked as source                              */
82747   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH11_Sink (0x0UL) /*!< The channel 11 is linked as sink                                  */
82748 
82749 /* CH12 @Bit 12 : Link direction */
82750   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Pos (12UL) /*!< Position of CH12 field.                                             */
82751   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Pos) /*!< Bit mask of CH12 field.    */
82752   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field.                                */
82753   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field.                                */
82754   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Source (0x1UL) /*!< The channel 12 is linked as source                              */
82755   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH12_Sink (0x0UL) /*!< The channel 12 is linked as sink                                  */
82756 
82757 /* CH13 @Bit 13 : Link direction */
82758   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Pos (13UL) /*!< Position of CH13 field.                                             */
82759   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Pos) /*!< Bit mask of CH13 field.    */
82760   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field.                                */
82761   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field.                                */
82762   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Source (0x1UL) /*!< The channel 13 is linked as source                              */
82763   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH13_Sink (0x0UL) /*!< The channel 13 is linked as sink                                  */
82764 
82765 /* CH14 @Bit 14 : Link direction */
82766   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Pos (14UL) /*!< Position of CH14 field.                                             */
82767   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Pos) /*!< Bit mask of CH14 field.    */
82768   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field.                                */
82769   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field.                                */
82770   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Source (0x1UL) /*!< The channel 14 is linked as source                              */
82771   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH14_Sink (0x0UL) /*!< The channel 14 is linked as sink                                  */
82772 
82773 /* CH15 @Bit 15 : Link direction */
82774   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Pos (15UL) /*!< Position of CH15 field.                                             */
82775   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Pos) /*!< Bit mask of CH15 field.    */
82776   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field.                                */
82777   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field.                                */
82778   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Source (0x1UL) /*!< The channel 15 is linked as source                              */
82779   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH15_Sink (0x0UL) /*!< The channel 15 is linked as sink                                  */
82780 
82781 /* CH16 @Bit 16 : Link direction */
82782   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Pos (16UL) /*!< Position of CH16 field.                                             */
82783   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Pos) /*!< Bit mask of CH16 field.    */
82784   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field.                                */
82785   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field.                                */
82786   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Source (0x1UL) /*!< The channel 16 is linked as source                              */
82787   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH16_Sink (0x0UL) /*!< The channel 16 is linked as sink                                  */
82788 
82789 /* CH17 @Bit 17 : Link direction */
82790   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Pos (17UL) /*!< Position of CH17 field.                                             */
82791   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Pos) /*!< Bit mask of CH17 field.    */
82792   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field.                                */
82793   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field.                                */
82794   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Source (0x1UL) /*!< The channel 17 is linked as source                              */
82795   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH17_Sink (0x0UL) /*!< The channel 17 is linked as sink                                  */
82796 
82797 /* CH18 @Bit 18 : Link direction */
82798   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Pos (18UL) /*!< Position of CH18 field.                                             */
82799   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Pos) /*!< Bit mask of CH18 field.    */
82800   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field.                                */
82801   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field.                                */
82802   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Source (0x1UL) /*!< The channel 18 is linked as source                              */
82803   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH18_Sink (0x0UL) /*!< The channel 18 is linked as sink                                  */
82804 
82805 /* CH19 @Bit 19 : Link direction */
82806   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Pos (19UL) /*!< Position of CH19 field.                                             */
82807   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Pos) /*!< Bit mask of CH19 field.    */
82808   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field.                                */
82809   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field.                                */
82810   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Source (0x1UL) /*!< The channel 19 is linked as source                              */
82811   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH19_Sink (0x0UL) /*!< The channel 19 is linked as sink                                  */
82812 
82813 /* CH20 @Bit 20 : Link direction */
82814   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Pos (20UL) /*!< Position of CH20 field.                                             */
82815   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Pos) /*!< Bit mask of CH20 field.    */
82816   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field.                                */
82817   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field.                                */
82818   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Source (0x1UL) /*!< The channel 20 is linked as source                              */
82819   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH20_Sink (0x0UL) /*!< The channel 20 is linked as sink                                  */
82820 
82821 /* CH21 @Bit 21 : Link direction */
82822   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Pos (21UL) /*!< Position of CH21 field.                                             */
82823   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Pos) /*!< Bit mask of CH21 field.    */
82824   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field.                                */
82825   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field.                                */
82826   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Source (0x1UL) /*!< The channel 21 is linked as source                              */
82827   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH21_Sink (0x0UL) /*!< The channel 21 is linked as sink                                  */
82828 
82829 /* CH22 @Bit 22 : Link direction */
82830   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Pos (22UL) /*!< Position of CH22 field.                                             */
82831   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Pos) /*!< Bit mask of CH22 field.    */
82832   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field.                                */
82833   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field.                                */
82834   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Source (0x1UL) /*!< The channel 22 is linked as source                              */
82835   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH22_Sink (0x0UL) /*!< The channel 22 is linked as sink                                  */
82836 
82837 /* CH23 @Bit 23 : Link direction */
82838   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Pos (23UL) /*!< Position of CH23 field.                                             */
82839   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Pos) /*!< Bit mask of CH23 field.    */
82840   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field.                                */
82841   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field.                                */
82842   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Source (0x1UL) /*!< The channel 23 is linked as source                              */
82843   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH23_Sink (0x0UL) /*!< The channel 23 is linked as sink                                  */
82844 
82845 /* CH24 @Bit 24 : Link direction */
82846   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Pos (24UL) /*!< Position of CH24 field.                                             */
82847   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Pos) /*!< Bit mask of CH24 field.    */
82848   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field.                                */
82849   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field.                                */
82850   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Source (0x1UL) /*!< The channel 24 is linked as source                              */
82851   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH24_Sink (0x0UL) /*!< The channel 24 is linked as sink                                  */
82852 
82853 /* CH25 @Bit 25 : Link direction */
82854   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Pos (25UL) /*!< Position of CH25 field.                                             */
82855   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Pos) /*!< Bit mask of CH25 field.    */
82856   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field.                                */
82857   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field.                                */
82858   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Source (0x1UL) /*!< The channel 25 is linked as source                              */
82859   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH25_Sink (0x0UL) /*!< The channel 25 is linked as sink                                  */
82860 
82861 /* CH26 @Bit 26 : Link direction */
82862   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Pos (26UL) /*!< Position of CH26 field.                                             */
82863   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Pos) /*!< Bit mask of CH26 field.    */
82864   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field.                                */
82865   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field.                                */
82866   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Source (0x1UL) /*!< The channel 26 is linked as source                              */
82867   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH26_Sink (0x0UL) /*!< The channel 26 is linked as sink                                  */
82868 
82869 /* CH27 @Bit 27 : Link direction */
82870   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Pos (27UL) /*!< Position of CH27 field.                                             */
82871   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Pos) /*!< Bit mask of CH27 field.    */
82872   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field.                                */
82873   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field.                                */
82874   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Source (0x1UL) /*!< The channel 27 is linked as source                              */
82875   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH27_Sink (0x0UL) /*!< The channel 27 is linked as sink                                  */
82876 
82877 /* CH28 @Bit 28 : Link direction */
82878   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Pos (28UL) /*!< Position of CH28 field.                                             */
82879   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Pos) /*!< Bit mask of CH28 field.    */
82880   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field.                                */
82881   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field.                                */
82882   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Source (0x1UL) /*!< The channel 28 is linked as source                              */
82883   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH28_Sink (0x0UL) /*!< The channel 28 is linked as sink                                  */
82884 
82885 /* CH29 @Bit 29 : Link direction */
82886   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Pos (29UL) /*!< Position of CH29 field.                                             */
82887   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Pos) /*!< Bit mask of CH29 field.    */
82888   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field.                                */
82889   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field.                                */
82890   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Source (0x1UL) /*!< The channel 29 is linked as source                              */
82891   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH29_Sink (0x0UL) /*!< The channel 29 is linked as sink                                  */
82892 
82893 /* CH30 @Bit 30 : Link direction */
82894   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Pos (30UL) /*!< Position of CH30 field.                                             */
82895   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Pos) /*!< Bit mask of CH30 field.    */
82896   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field.                                */
82897   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field.                                */
82898   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Source (0x1UL) /*!< The channel 30 is linked as source                              */
82899   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH30_Sink (0x0UL) /*!< The channel 30 is linked as sink                                  */
82900 
82901 /* CH31 @Bit 31 : Link direction */
82902   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Pos (31UL) /*!< Position of CH31 field.                                             */
82903   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Pos) /*!< Bit mask of CH31 field.    */
82904   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field.                                */
82905   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field.                                */
82906   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Source (0x1UL) /*!< The channel 31 is linked as source                              */
82907   #define UICR_DPPI_LOCAL_CH_LINK_DIR_CH31_Sink (0x0UL) /*!< The channel 31 is linked as sink                                  */
82908 
82909 
82910 /* UICR_DPPI_LOCAL_CH_LINK_EN: Request linking of the channels of DPPI[n] in the local domain */
82911   #define UICR_DPPI_LOCAL_CH_LINK_EN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of EN register.                                */
82912 
82913 /* CH0 @Bit 0 : Link enable */
82914   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Pos (0UL)   /*!< Position of CH0 field.                                               */
82915   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Pos) /*!< Bit mask of CH0 field.         */
82916   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field.                                   */
82917   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field.                                   */
82918   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Disabled (0x1UL) /*!< The channel 0 is disabled                                       */
82919   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH0_Enabled (0x0UL) /*!< The channel 0 is enabled                                         */
82920 
82921 /* CH1 @Bit 1 : Link enable */
82922   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Pos (1UL)   /*!< Position of CH1 field.                                               */
82923   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Pos) /*!< Bit mask of CH1 field.         */
82924   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field.                                   */
82925   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field.                                   */
82926   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Disabled (0x1UL) /*!< The channel 1 is disabled                                       */
82927   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH1_Enabled (0x0UL) /*!< The channel 1 is enabled                                         */
82928 
82929 /* CH2 @Bit 2 : Link enable */
82930   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Pos (2UL)   /*!< Position of CH2 field.                                               */
82931   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Pos) /*!< Bit mask of CH2 field.         */
82932   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field.                                   */
82933   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field.                                   */
82934   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Disabled (0x1UL) /*!< The channel 2 is disabled                                       */
82935   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH2_Enabled (0x0UL) /*!< The channel 2 is enabled                                         */
82936 
82937 /* CH3 @Bit 3 : Link enable */
82938   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Pos (3UL)   /*!< Position of CH3 field.                                               */
82939   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Pos) /*!< Bit mask of CH3 field.         */
82940   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field.                                   */
82941   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field.                                   */
82942   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Disabled (0x1UL) /*!< The channel 3 is disabled                                       */
82943   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH3_Enabled (0x0UL) /*!< The channel 3 is enabled                                         */
82944 
82945 /* CH4 @Bit 4 : Link enable */
82946   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Pos (4UL)   /*!< Position of CH4 field.                                               */
82947   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Pos) /*!< Bit mask of CH4 field.         */
82948   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field.                                   */
82949   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field.                                   */
82950   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Disabled (0x1UL) /*!< The channel 4 is disabled                                       */
82951   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH4_Enabled (0x0UL) /*!< The channel 4 is enabled                                         */
82952 
82953 /* CH5 @Bit 5 : Link enable */
82954   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Pos (5UL)   /*!< Position of CH5 field.                                               */
82955   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Pos) /*!< Bit mask of CH5 field.         */
82956   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field.                                   */
82957   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field.                                   */
82958   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Disabled (0x1UL) /*!< The channel 5 is disabled                                       */
82959   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH5_Enabled (0x0UL) /*!< The channel 5 is enabled                                         */
82960 
82961 /* CH6 @Bit 6 : Link enable */
82962   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Pos (6UL)   /*!< Position of CH6 field.                                               */
82963   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Pos) /*!< Bit mask of CH6 field.         */
82964   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field.                                   */
82965   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field.                                   */
82966   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Disabled (0x1UL) /*!< The channel 6 is disabled                                       */
82967   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH6_Enabled (0x0UL) /*!< The channel 6 is enabled                                         */
82968 
82969 /* CH7 @Bit 7 : Link enable */
82970   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Pos (7UL)   /*!< Position of CH7 field.                                               */
82971   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Pos) /*!< Bit mask of CH7 field.         */
82972   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field.                                   */
82973   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field.                                   */
82974   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Disabled (0x1UL) /*!< The channel 7 is disabled                                       */
82975   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH7_Enabled (0x0UL) /*!< The channel 7 is enabled                                         */
82976 
82977 /* CH8 @Bit 8 : Link enable */
82978   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Pos (8UL)   /*!< Position of CH8 field.                                               */
82979   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Pos) /*!< Bit mask of CH8 field.         */
82980   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field.                                   */
82981   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field.                                   */
82982   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Disabled (0x1UL) /*!< The channel 8 is disabled                                       */
82983   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH8_Enabled (0x0UL) /*!< The channel 8 is enabled                                         */
82984 
82985 /* CH9 @Bit 9 : Link enable */
82986   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Pos (9UL)   /*!< Position of CH9 field.                                               */
82987   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Pos) /*!< Bit mask of CH9 field.         */
82988   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field.                                   */
82989   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field.                                   */
82990   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Disabled (0x1UL) /*!< The channel 9 is disabled                                       */
82991   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH9_Enabled (0x0UL) /*!< The channel 9 is enabled                                         */
82992 
82993 /* CH10 @Bit 10 : Link enable */
82994   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Pos (10UL) /*!< Position of CH10 field.                                              */
82995   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Pos) /*!< Bit mask of CH10 field.      */
82996   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field.                                 */
82997   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field.                                 */
82998   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Disabled (0x1UL) /*!< The channel 10 is disabled                                     */
82999   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH10_Enabled (0x0UL) /*!< The channel 10 is enabled                                       */
83000 
83001 /* CH11 @Bit 11 : Link enable */
83002   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Pos (11UL) /*!< Position of CH11 field.                                              */
83003   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Pos) /*!< Bit mask of CH11 field.      */
83004   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field.                                 */
83005   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field.                                 */
83006   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Disabled (0x1UL) /*!< The channel 11 is disabled                                     */
83007   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH11_Enabled (0x0UL) /*!< The channel 11 is enabled                                       */
83008 
83009 /* CH12 @Bit 12 : Link enable */
83010   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Pos (12UL) /*!< Position of CH12 field.                                              */
83011   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Pos) /*!< Bit mask of CH12 field.      */
83012   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field.                                 */
83013   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field.                                 */
83014   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Disabled (0x1UL) /*!< The channel 12 is disabled                                     */
83015   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH12_Enabled (0x0UL) /*!< The channel 12 is enabled                                       */
83016 
83017 /* CH13 @Bit 13 : Link enable */
83018   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Pos (13UL) /*!< Position of CH13 field.                                              */
83019   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Pos) /*!< Bit mask of CH13 field.      */
83020   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field.                                 */
83021   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field.                                 */
83022   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Disabled (0x1UL) /*!< The channel 13 is disabled                                     */
83023   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH13_Enabled (0x0UL) /*!< The channel 13 is enabled                                       */
83024 
83025 /* CH14 @Bit 14 : Link enable */
83026   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Pos (14UL) /*!< Position of CH14 field.                                              */
83027   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Pos) /*!< Bit mask of CH14 field.      */
83028   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field.                                 */
83029   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field.                                 */
83030   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Disabled (0x1UL) /*!< The channel 14 is disabled                                     */
83031   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH14_Enabled (0x0UL) /*!< The channel 14 is enabled                                       */
83032 
83033 /* CH15 @Bit 15 : Link enable */
83034   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Pos (15UL) /*!< Position of CH15 field.                                              */
83035   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Pos) /*!< Bit mask of CH15 field.      */
83036   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field.                                 */
83037   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field.                                 */
83038   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Disabled (0x1UL) /*!< The channel 15 is disabled                                     */
83039   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH15_Enabled (0x0UL) /*!< The channel 15 is enabled                                       */
83040 
83041 /* CH16 @Bit 16 : Link enable */
83042   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Pos (16UL) /*!< Position of CH16 field.                                              */
83043   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Pos) /*!< Bit mask of CH16 field.      */
83044   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field.                                 */
83045   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field.                                 */
83046   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Disabled (0x1UL) /*!< The channel 16 is disabled                                     */
83047   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH16_Enabled (0x0UL) /*!< The channel 16 is enabled                                       */
83048 
83049 /* CH17 @Bit 17 : Link enable */
83050   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Pos (17UL) /*!< Position of CH17 field.                                              */
83051   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Pos) /*!< Bit mask of CH17 field.      */
83052   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field.                                 */
83053   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field.                                 */
83054   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Disabled (0x1UL) /*!< The channel 17 is disabled                                     */
83055   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH17_Enabled (0x0UL) /*!< The channel 17 is enabled                                       */
83056 
83057 /* CH18 @Bit 18 : Link enable */
83058   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Pos (18UL) /*!< Position of CH18 field.                                              */
83059   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Pos) /*!< Bit mask of CH18 field.      */
83060   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field.                                 */
83061   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field.                                 */
83062   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Disabled (0x1UL) /*!< The channel 18 is disabled                                     */
83063   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH18_Enabled (0x0UL) /*!< The channel 18 is enabled                                       */
83064 
83065 /* CH19 @Bit 19 : Link enable */
83066   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Pos (19UL) /*!< Position of CH19 field.                                              */
83067   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Pos) /*!< Bit mask of CH19 field.      */
83068   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field.                                 */
83069   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field.                                 */
83070   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Disabled (0x1UL) /*!< The channel 19 is disabled                                     */
83071   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH19_Enabled (0x0UL) /*!< The channel 19 is enabled                                       */
83072 
83073 /* CH20 @Bit 20 : Link enable */
83074   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Pos (20UL) /*!< Position of CH20 field.                                              */
83075   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Pos) /*!< Bit mask of CH20 field.      */
83076   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field.                                 */
83077   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field.                                 */
83078   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Disabled (0x1UL) /*!< The channel 20 is disabled                                     */
83079   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH20_Enabled (0x0UL) /*!< The channel 20 is enabled                                       */
83080 
83081 /* CH21 @Bit 21 : Link enable */
83082   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Pos (21UL) /*!< Position of CH21 field.                                              */
83083   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Pos) /*!< Bit mask of CH21 field.      */
83084   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field.                                 */
83085   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field.                                 */
83086   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Disabled (0x1UL) /*!< The channel 21 is disabled                                     */
83087   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH21_Enabled (0x0UL) /*!< The channel 21 is enabled                                       */
83088 
83089 /* CH22 @Bit 22 : Link enable */
83090   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Pos (22UL) /*!< Position of CH22 field.                                              */
83091   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Pos) /*!< Bit mask of CH22 field.      */
83092   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field.                                 */
83093   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field.                                 */
83094   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Disabled (0x1UL) /*!< The channel 22 is disabled                                     */
83095   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH22_Enabled (0x0UL) /*!< The channel 22 is enabled                                       */
83096 
83097 /* CH23 @Bit 23 : Link enable */
83098   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Pos (23UL) /*!< Position of CH23 field.                                              */
83099   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Pos) /*!< Bit mask of CH23 field.      */
83100   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field.                                 */
83101   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field.                                 */
83102   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Disabled (0x1UL) /*!< The channel 23 is disabled                                     */
83103   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH23_Enabled (0x0UL) /*!< The channel 23 is enabled                                       */
83104 
83105 /* CH24 @Bit 24 : Link enable */
83106   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Pos (24UL) /*!< Position of CH24 field.                                              */
83107   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Pos) /*!< Bit mask of CH24 field.      */
83108   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field.                                 */
83109   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field.                                 */
83110   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Disabled (0x1UL) /*!< The channel 24 is disabled                                     */
83111   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH24_Enabled (0x0UL) /*!< The channel 24 is enabled                                       */
83112 
83113 /* CH25 @Bit 25 : Link enable */
83114   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Pos (25UL) /*!< Position of CH25 field.                                              */
83115   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Pos) /*!< Bit mask of CH25 field.      */
83116   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field.                                 */
83117   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field.                                 */
83118   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Disabled (0x1UL) /*!< The channel 25 is disabled                                     */
83119   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH25_Enabled (0x0UL) /*!< The channel 25 is enabled                                       */
83120 
83121 /* CH26 @Bit 26 : Link enable */
83122   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Pos (26UL) /*!< Position of CH26 field.                                              */
83123   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Pos) /*!< Bit mask of CH26 field.      */
83124   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field.                                 */
83125   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field.                                 */
83126   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Disabled (0x1UL) /*!< The channel 26 is disabled                                     */
83127   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH26_Enabled (0x0UL) /*!< The channel 26 is enabled                                       */
83128 
83129 /* CH27 @Bit 27 : Link enable */
83130   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Pos (27UL) /*!< Position of CH27 field.                                              */
83131   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Pos) /*!< Bit mask of CH27 field.      */
83132   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field.                                 */
83133   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field.                                 */
83134   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Disabled (0x1UL) /*!< The channel 27 is disabled                                     */
83135   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH27_Enabled (0x0UL) /*!< The channel 27 is enabled                                       */
83136 
83137 /* CH28 @Bit 28 : Link enable */
83138   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Pos (28UL) /*!< Position of CH28 field.                                              */
83139   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Pos) /*!< Bit mask of CH28 field.      */
83140   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field.                                 */
83141   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field.                                 */
83142   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Disabled (0x1UL) /*!< The channel 28 is disabled                                     */
83143   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH28_Enabled (0x0UL) /*!< The channel 28 is enabled                                       */
83144 
83145 /* CH29 @Bit 29 : Link enable */
83146   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Pos (29UL) /*!< Position of CH29 field.                                              */
83147   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Pos) /*!< Bit mask of CH29 field.      */
83148   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field.                                 */
83149   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field.                                 */
83150   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Disabled (0x1UL) /*!< The channel 29 is disabled                                     */
83151   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH29_Enabled (0x0UL) /*!< The channel 29 is enabled                                       */
83152 
83153 /* CH30 @Bit 30 : Link enable */
83154   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Pos (30UL) /*!< Position of CH30 field.                                              */
83155   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Pos) /*!< Bit mask of CH30 field.      */
83156   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field.                                 */
83157   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field.                                 */
83158   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Disabled (0x1UL) /*!< The channel 30 is disabled                                     */
83159   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH30_Enabled (0x0UL) /*!< The channel 30 is enabled                                       */
83160 
83161 /* CH31 @Bit 31 : Link enable */
83162   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Pos (31UL) /*!< Position of CH31 field.                                              */
83163   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Msk (0x1UL << UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Pos) /*!< Bit mask of CH31 field.      */
83164   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field.                                 */
83165   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field.                                 */
83166   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Disabled (0x1UL) /*!< The channel 31 is disabled                                     */
83167   #define UICR_DPPI_LOCAL_CH_LINK_EN_CH31_Enabled (0x0UL) /*!< The channel 31 is enabled                                       */
83168 
83169 
83170 
83171 /* ================================================ Struct UICR_DPPI_LOCAL_CH ================================================ */
83172 /**
83173   * @brief CH [UICR_DPPI_LOCAL_CH] (unspecified)
83174   */
83175 typedef struct {
83176   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000000) Request permission for the channels of DPPI[n] in the
83177                                                                          local domain*/
83178   __IOM NRF_UICR_DPPI_LOCAL_CH_LINK_Type LINK;       /*!< (@ 0x00000004) (unspecified)                                         */
83179 } NRF_UICR_DPPI_LOCAL_CH_Type;                       /*!< Size = 12 (0x00C)                                                    */
83180 
83181 /* UICR_DPPI_LOCAL_CH_SECURE: Request permission for the channels of DPPI[n] in the local domain */
83182   #define UICR_DPPI_LOCAL_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                             */
83183 
83184 /* CH0 @Bit 0 : Channel number */
83185   #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Pos (0UL)    /*!< Position of CH0 field.                                               */
83186   #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field.           */
83187   #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Min (0x0UL)  /*!< Min enumerator value of CH0 field.                                   */
83188   #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Max (0x1UL)  /*!< Max enumerator value of CH0 field.                                   */
83189   #define UICR_DPPI_LOCAL_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure                                            */
83190   #define UICR_DPPI_LOCAL_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure                                     */
83191 
83192 /* CH1 @Bit 1 : Channel number */
83193   #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Pos (1UL)    /*!< Position of CH1 field.                                               */
83194   #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field.           */
83195   #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Min (0x0UL)  /*!< Min enumerator value of CH1 field.                                   */
83196   #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Max (0x1UL)  /*!< Max enumerator value of CH1 field.                                   */
83197   #define UICR_DPPI_LOCAL_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure                                            */
83198   #define UICR_DPPI_LOCAL_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure                                     */
83199 
83200 /* CH2 @Bit 2 : Channel number */
83201   #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Pos (2UL)    /*!< Position of CH2 field.                                               */
83202   #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field.           */
83203   #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Min (0x0UL)  /*!< Min enumerator value of CH2 field.                                   */
83204   #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Max (0x1UL)  /*!< Max enumerator value of CH2 field.                                   */
83205   #define UICR_DPPI_LOCAL_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure                                            */
83206   #define UICR_DPPI_LOCAL_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure                                     */
83207 
83208 /* CH3 @Bit 3 : Channel number */
83209   #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Pos (3UL)    /*!< Position of CH3 field.                                               */
83210   #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field.           */
83211   #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Min (0x0UL)  /*!< Min enumerator value of CH3 field.                                   */
83212   #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Max (0x1UL)  /*!< Max enumerator value of CH3 field.                                   */
83213   #define UICR_DPPI_LOCAL_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure                                            */
83214   #define UICR_DPPI_LOCAL_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure                                     */
83215 
83216 /* CH4 @Bit 4 : Channel number */
83217   #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Pos (4UL)    /*!< Position of CH4 field.                                               */
83218   #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field.           */
83219   #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Min (0x0UL)  /*!< Min enumerator value of CH4 field.                                   */
83220   #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Max (0x1UL)  /*!< Max enumerator value of CH4 field.                                   */
83221   #define UICR_DPPI_LOCAL_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure                                            */
83222   #define UICR_DPPI_LOCAL_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure                                     */
83223 
83224 /* CH5 @Bit 5 : Channel number */
83225   #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Pos (5UL)    /*!< Position of CH5 field.                                               */
83226   #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field.           */
83227   #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Min (0x0UL)  /*!< Min enumerator value of CH5 field.                                   */
83228   #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Max (0x1UL)  /*!< Max enumerator value of CH5 field.                                   */
83229   #define UICR_DPPI_LOCAL_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure                                            */
83230   #define UICR_DPPI_LOCAL_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure                                     */
83231 
83232 /* CH6 @Bit 6 : Channel number */
83233   #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Pos (6UL)    /*!< Position of CH6 field.                                               */
83234   #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field.           */
83235   #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Min (0x0UL)  /*!< Min enumerator value of CH6 field.                                   */
83236   #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Max (0x1UL)  /*!< Max enumerator value of CH6 field.                                   */
83237   #define UICR_DPPI_LOCAL_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure                                            */
83238   #define UICR_DPPI_LOCAL_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure                                     */
83239 
83240 /* CH7 @Bit 7 : Channel number */
83241   #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Pos (7UL)    /*!< Position of CH7 field.                                               */
83242   #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field.           */
83243   #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Min (0x0UL)  /*!< Min enumerator value of CH7 field.                                   */
83244   #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Max (0x1UL)  /*!< Max enumerator value of CH7 field.                                   */
83245   #define UICR_DPPI_LOCAL_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure                                            */
83246   #define UICR_DPPI_LOCAL_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure                                     */
83247 
83248 /* CH8 @Bit 8 : Channel number */
83249   #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Pos (8UL)    /*!< Position of CH8 field.                                               */
83250   #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field.           */
83251   #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Min (0x0UL)  /*!< Min enumerator value of CH8 field.                                   */
83252   #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Max (0x1UL)  /*!< Max enumerator value of CH8 field.                                   */
83253   #define UICR_DPPI_LOCAL_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure                                            */
83254   #define UICR_DPPI_LOCAL_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure                                     */
83255 
83256 /* CH9 @Bit 9 : Channel number */
83257   #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Pos (9UL)    /*!< Position of CH9 field.                                               */
83258   #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field.           */
83259   #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Min (0x0UL)  /*!< Min enumerator value of CH9 field.                                   */
83260   #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Max (0x1UL)  /*!< Max enumerator value of CH9 field.                                   */
83261   #define UICR_DPPI_LOCAL_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure                                            */
83262   #define UICR_DPPI_LOCAL_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure                                     */
83263 
83264 /* CH10 @Bit 10 : Channel number */
83265   #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Pos (10UL)  /*!< Position of CH10 field.                                              */
83266   #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field.        */
83267   #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field.                                  */
83268   #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field.                                  */
83269   #define UICR_DPPI_LOCAL_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure                                          */
83270   #define UICR_DPPI_LOCAL_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure                                   */
83271 
83272 /* CH11 @Bit 11 : Channel number */
83273   #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Pos (11UL)  /*!< Position of CH11 field.                                              */
83274   #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field.        */
83275   #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field.                                  */
83276   #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field.                                  */
83277   #define UICR_DPPI_LOCAL_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure                                          */
83278   #define UICR_DPPI_LOCAL_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure                                   */
83279 
83280 /* CH12 @Bit 12 : Channel number */
83281   #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Pos (12UL)  /*!< Position of CH12 field.                                              */
83282   #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field.        */
83283   #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field.                                  */
83284   #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field.                                  */
83285   #define UICR_DPPI_LOCAL_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure                                          */
83286   #define UICR_DPPI_LOCAL_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure                                   */
83287 
83288 /* CH13 @Bit 13 : Channel number */
83289   #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Pos (13UL)  /*!< Position of CH13 field.                                              */
83290   #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field.        */
83291   #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field.                                  */
83292   #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field.                                  */
83293   #define UICR_DPPI_LOCAL_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure                                          */
83294   #define UICR_DPPI_LOCAL_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure                                   */
83295 
83296 /* CH14 @Bit 14 : Channel number */
83297   #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Pos (14UL)  /*!< Position of CH14 field.                                              */
83298   #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field.        */
83299   #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field.                                  */
83300   #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field.                                  */
83301   #define UICR_DPPI_LOCAL_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure                                          */
83302   #define UICR_DPPI_LOCAL_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure                                   */
83303 
83304 /* CH15 @Bit 15 : Channel number */
83305   #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Pos (15UL)  /*!< Position of CH15 field.                                              */
83306   #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field.        */
83307   #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field.                                  */
83308   #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field.                                  */
83309   #define UICR_DPPI_LOCAL_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure                                          */
83310   #define UICR_DPPI_LOCAL_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure                                   */
83311 
83312 /* CH16 @Bit 16 : Channel number */
83313   #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Pos (16UL)  /*!< Position of CH16 field.                                              */
83314   #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field.        */
83315   #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field.                                  */
83316   #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field.                                  */
83317   #define UICR_DPPI_LOCAL_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure                                          */
83318   #define UICR_DPPI_LOCAL_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure                                   */
83319 
83320 /* CH17 @Bit 17 : Channel number */
83321   #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Pos (17UL)  /*!< Position of CH17 field.                                              */
83322   #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field.        */
83323   #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field.                                  */
83324   #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field.                                  */
83325   #define UICR_DPPI_LOCAL_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure                                          */
83326   #define UICR_DPPI_LOCAL_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure                                   */
83327 
83328 /* CH18 @Bit 18 : Channel number */
83329   #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Pos (18UL)  /*!< Position of CH18 field.                                              */
83330   #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field.        */
83331   #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field.                                  */
83332   #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field.                                  */
83333   #define UICR_DPPI_LOCAL_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure                                          */
83334   #define UICR_DPPI_LOCAL_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure                                   */
83335 
83336 /* CH19 @Bit 19 : Channel number */
83337   #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Pos (19UL)  /*!< Position of CH19 field.                                              */
83338   #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field.        */
83339   #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field.                                  */
83340   #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field.                                  */
83341   #define UICR_DPPI_LOCAL_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure                                          */
83342   #define UICR_DPPI_LOCAL_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure                                   */
83343 
83344 /* CH20 @Bit 20 : Channel number */
83345   #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Pos (20UL)  /*!< Position of CH20 field.                                              */
83346   #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field.        */
83347   #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field.                                  */
83348   #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field.                                  */
83349   #define UICR_DPPI_LOCAL_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure                                          */
83350   #define UICR_DPPI_LOCAL_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure                                   */
83351 
83352 /* CH21 @Bit 21 : Channel number */
83353   #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Pos (21UL)  /*!< Position of CH21 field.                                              */
83354   #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field.        */
83355   #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field.                                  */
83356   #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field.                                  */
83357   #define UICR_DPPI_LOCAL_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure                                          */
83358   #define UICR_DPPI_LOCAL_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure                                   */
83359 
83360 /* CH22 @Bit 22 : Channel number */
83361   #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Pos (22UL)  /*!< Position of CH22 field.                                              */
83362   #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field.        */
83363   #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field.                                  */
83364   #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field.                                  */
83365   #define UICR_DPPI_LOCAL_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure                                          */
83366   #define UICR_DPPI_LOCAL_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure                                   */
83367 
83368 /* CH23 @Bit 23 : Channel number */
83369   #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Pos (23UL)  /*!< Position of CH23 field.                                              */
83370   #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field.        */
83371   #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field.                                  */
83372   #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field.                                  */
83373   #define UICR_DPPI_LOCAL_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure                                          */
83374   #define UICR_DPPI_LOCAL_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure                                   */
83375 
83376 /* CH24 @Bit 24 : Channel number */
83377   #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Pos (24UL)  /*!< Position of CH24 field.                                              */
83378   #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field.        */
83379   #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field.                                  */
83380   #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field.                                  */
83381   #define UICR_DPPI_LOCAL_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure                                          */
83382   #define UICR_DPPI_LOCAL_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure                                   */
83383 
83384 /* CH25 @Bit 25 : Channel number */
83385   #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Pos (25UL)  /*!< Position of CH25 field.                                              */
83386   #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field.        */
83387   #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field.                                  */
83388   #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field.                                  */
83389   #define UICR_DPPI_LOCAL_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure                                          */
83390   #define UICR_DPPI_LOCAL_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure                                   */
83391 
83392 /* CH26 @Bit 26 : Channel number */
83393   #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Pos (26UL)  /*!< Position of CH26 field.                                              */
83394   #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field.        */
83395   #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field.                                  */
83396   #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field.                                  */
83397   #define UICR_DPPI_LOCAL_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure                                          */
83398   #define UICR_DPPI_LOCAL_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure                                   */
83399 
83400 /* CH27 @Bit 27 : Channel number */
83401   #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Pos (27UL)  /*!< Position of CH27 field.                                              */
83402   #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field.        */
83403   #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field.                                  */
83404   #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field.                                  */
83405   #define UICR_DPPI_LOCAL_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure                                          */
83406   #define UICR_DPPI_LOCAL_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure                                   */
83407 
83408 /* CH28 @Bit 28 : Channel number */
83409   #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Pos (28UL)  /*!< Position of CH28 field.                                              */
83410   #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field.        */
83411   #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field.                                  */
83412   #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field.                                  */
83413   #define UICR_DPPI_LOCAL_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure                                          */
83414   #define UICR_DPPI_LOCAL_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure                                   */
83415 
83416 /* CH29 @Bit 29 : Channel number */
83417   #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Pos (29UL)  /*!< Position of CH29 field.                                              */
83418   #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field.        */
83419   #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field.                                  */
83420   #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field.                                  */
83421   #define UICR_DPPI_LOCAL_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure                                          */
83422   #define UICR_DPPI_LOCAL_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure                                   */
83423 
83424 /* CH30 @Bit 30 : Channel number */
83425   #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Pos (30UL)  /*!< Position of CH30 field.                                              */
83426   #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field.        */
83427   #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field.                                  */
83428   #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field.                                  */
83429   #define UICR_DPPI_LOCAL_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure                                          */
83430   #define UICR_DPPI_LOCAL_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure                                   */
83431 
83432 /* CH31 @Bit 31 : Channel number */
83433   #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Pos (31UL)  /*!< Position of CH31 field.                                              */
83434   #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Msk (0x1UL << UICR_DPPI_LOCAL_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field.        */
83435   #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field.                                  */
83436   #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field.                                  */
83437   #define UICR_DPPI_LOCAL_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure                                          */
83438   #define UICR_DPPI_LOCAL_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure                                   */
83439 
83440 
83441 
83442 /* =============================================== Struct UICR_DPPI_LOCAL_CHG ================================================ */
83443 /**
83444   * @brief CHG [UICR_DPPI_LOCAL_CHG] (unspecified)
83445   */
83446 typedef struct {
83447   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000000) Request permission for the channel groups of DPPI[n] in
83448                                                                          the local domain*/
83449 } NRF_UICR_DPPI_LOCAL_CHG_Type;                      /*!< Size = 4 (0x004)                                                     */
83450 
83451 /* UICR_DPPI_LOCAL_CHG_SECURE: Request permission for the channel groups of DPPI[n] in the local domain */
83452   #define UICR_DPPI_LOCAL_CHG_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                            */
83453 
83454 /* CHG0 @Bit 0 : Channel group number */
83455   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Pos (0UL)  /*!< Position of CHG0 field.                                              */
83456   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Pos) /*!< Bit mask of CHG0 field.      */
83457   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Min (0x0UL) /*!< Min enumerator value of CHG0 field.                                 */
83458   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Max (0x1UL) /*!< Max enumerator value of CHG0 field.                                 */
83459   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_Secure (0x1UL) /*!< The channel group 0 is secure                                    */
83460   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG0_NonSecure (0x0UL) /*!< The channel group 0 is non-secure                             */
83461 
83462 /* CHG1 @Bit 1 : Channel group number */
83463   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Pos (1UL)  /*!< Position of CHG1 field.                                              */
83464   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Pos) /*!< Bit mask of CHG1 field.      */
83465   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Min (0x0UL) /*!< Min enumerator value of CHG1 field.                                 */
83466   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Max (0x1UL) /*!< Max enumerator value of CHG1 field.                                 */
83467   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_Secure (0x1UL) /*!< The channel group 1 is secure                                    */
83468   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG1_NonSecure (0x0UL) /*!< The channel group 1 is non-secure                             */
83469 
83470 /* CHG2 @Bit 2 : Channel group number */
83471   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Pos (2UL)  /*!< Position of CHG2 field.                                              */
83472   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Pos) /*!< Bit mask of CHG2 field.      */
83473   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Min (0x0UL) /*!< Min enumerator value of CHG2 field.                                 */
83474   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Max (0x1UL) /*!< Max enumerator value of CHG2 field.                                 */
83475   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_Secure (0x1UL) /*!< The channel group 2 is secure                                    */
83476   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG2_NonSecure (0x0UL) /*!< The channel group 2 is non-secure                             */
83477 
83478 /* CHG3 @Bit 3 : Channel group number */
83479   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Pos (3UL)  /*!< Position of CHG3 field.                                              */
83480   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Pos) /*!< Bit mask of CHG3 field.      */
83481   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Min (0x0UL) /*!< Min enumerator value of CHG3 field.                                 */
83482   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Max (0x1UL) /*!< Max enumerator value of CHG3 field.                                 */
83483   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_Secure (0x1UL) /*!< The channel group 3 is secure                                    */
83484   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG3_NonSecure (0x0UL) /*!< The channel group 3 is non-secure                             */
83485 
83486 /* CHG4 @Bit 4 : Channel group number */
83487   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Pos (4UL)  /*!< Position of CHG4 field.                                              */
83488   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Pos) /*!< Bit mask of CHG4 field.      */
83489   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Min (0x0UL) /*!< Min enumerator value of CHG4 field.                                 */
83490   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Max (0x1UL) /*!< Max enumerator value of CHG4 field.                                 */
83491   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_Secure (0x1UL) /*!< The channel group 4 is secure                                    */
83492   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG4_NonSecure (0x0UL) /*!< The channel group 4 is non-secure                             */
83493 
83494 /* CHG5 @Bit 5 : Channel group number */
83495   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Pos (5UL)  /*!< Position of CHG5 field.                                              */
83496   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Pos) /*!< Bit mask of CHG5 field.      */
83497   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Min (0x0UL) /*!< Min enumerator value of CHG5 field.                                 */
83498   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Max (0x1UL) /*!< Max enumerator value of CHG5 field.                                 */
83499   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_Secure (0x1UL) /*!< The channel group 5 is secure                                    */
83500   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG5_NonSecure (0x0UL) /*!< The channel group 5 is non-secure                             */
83501 
83502 /* CHG6 @Bit 6 : Channel group number */
83503   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Pos (6UL)  /*!< Position of CHG6 field.                                              */
83504   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Pos) /*!< Bit mask of CHG6 field.      */
83505   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Min (0x0UL) /*!< Min enumerator value of CHG6 field.                                 */
83506   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Max (0x1UL) /*!< Max enumerator value of CHG6 field.                                 */
83507   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_Secure (0x1UL) /*!< The channel group 6 is secure                                    */
83508   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG6_NonSecure (0x0UL) /*!< The channel group 6 is non-secure                             */
83509 
83510 /* CHG7 @Bit 7 : Channel group number */
83511   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Pos (7UL)  /*!< Position of CHG7 field.                                              */
83512   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Pos) /*!< Bit mask of CHG7 field.      */
83513   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Min (0x0UL) /*!< Min enumerator value of CHG7 field.                                 */
83514   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Max (0x1UL) /*!< Max enumerator value of CHG7 field.                                 */
83515   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_Secure (0x1UL) /*!< The channel group 7 is secure                                    */
83516   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG7_NonSecure (0x0UL) /*!< The channel group 7 is non-secure                             */
83517 
83518 /* CHG8 @Bit 8 : Channel group number */
83519   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Pos (8UL)  /*!< Position of CHG8 field.                                              */
83520   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Pos) /*!< Bit mask of CHG8 field.      */
83521   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Min (0x0UL) /*!< Min enumerator value of CHG8 field.                                 */
83522   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Max (0x1UL) /*!< Max enumerator value of CHG8 field.                                 */
83523   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_Secure (0x1UL) /*!< The channel group 8 is secure                                    */
83524   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG8_NonSecure (0x0UL) /*!< The channel group 8 is non-secure                             */
83525 
83526 /* CHG9 @Bit 9 : Channel group number */
83527   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Pos (9UL)  /*!< Position of CHG9 field.                                              */
83528   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Pos) /*!< Bit mask of CHG9 field.      */
83529   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Min (0x0UL) /*!< Min enumerator value of CHG9 field.                                 */
83530   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Max (0x1UL) /*!< Max enumerator value of CHG9 field.                                 */
83531   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_Secure (0x1UL) /*!< The channel group 9 is secure                                    */
83532   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG9_NonSecure (0x0UL) /*!< The channel group 9 is non-secure                             */
83533 
83534 /* CHG10 @Bit 10 : Channel group number */
83535   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Pos (10UL) /*!< Position of CHG10 field.                                            */
83536   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Pos) /*!< Bit mask of CHG10 field.   */
83537   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Min (0x0UL) /*!< Min enumerator value of CHG10 field.                               */
83538   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Max (0x1UL) /*!< Max enumerator value of CHG10 field.                               */
83539   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_Secure (0x1UL) /*!< The channel group 10 is secure                                  */
83540   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG10_NonSecure (0x0UL) /*!< The channel group 10 is non-secure                           */
83541 
83542 /* CHG11 @Bit 11 : Channel group number */
83543   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Pos (11UL) /*!< Position of CHG11 field.                                            */
83544   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Pos) /*!< Bit mask of CHG11 field.   */
83545   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Min (0x0UL) /*!< Min enumerator value of CHG11 field.                               */
83546   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Max (0x1UL) /*!< Max enumerator value of CHG11 field.                               */
83547   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_Secure (0x1UL) /*!< The channel group 11 is secure                                  */
83548   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG11_NonSecure (0x0UL) /*!< The channel group 11 is non-secure                           */
83549 
83550 /* CHG12 @Bit 12 : Channel group number */
83551   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Pos (12UL) /*!< Position of CHG12 field.                                            */
83552   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Pos) /*!< Bit mask of CHG12 field.   */
83553   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Min (0x0UL) /*!< Min enumerator value of CHG12 field.                               */
83554   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Max (0x1UL) /*!< Max enumerator value of CHG12 field.                               */
83555   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_Secure (0x1UL) /*!< The channel group 12 is secure                                  */
83556   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG12_NonSecure (0x0UL) /*!< The channel group 12 is non-secure                           */
83557 
83558 /* CHG13 @Bit 13 : Channel group number */
83559   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Pos (13UL) /*!< Position of CHG13 field.                                            */
83560   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Pos) /*!< Bit mask of CHG13 field.   */
83561   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Min (0x0UL) /*!< Min enumerator value of CHG13 field.                               */
83562   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Max (0x1UL) /*!< Max enumerator value of CHG13 field.                               */
83563   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_Secure (0x1UL) /*!< The channel group 13 is secure                                  */
83564   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG13_NonSecure (0x0UL) /*!< The channel group 13 is non-secure                           */
83565 
83566 /* CHG14 @Bit 14 : Channel group number */
83567   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Pos (14UL) /*!< Position of CHG14 field.                                            */
83568   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Pos) /*!< Bit mask of CHG14 field.   */
83569   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Min (0x0UL) /*!< Min enumerator value of CHG14 field.                               */
83570   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Max (0x1UL) /*!< Max enumerator value of CHG14 field.                               */
83571   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_Secure (0x1UL) /*!< The channel group 14 is secure                                  */
83572   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG14_NonSecure (0x0UL) /*!< The channel group 14 is non-secure                           */
83573 
83574 /* CHG15 @Bit 15 : Channel group number */
83575   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Pos (15UL) /*!< Position of CHG15 field.                                            */
83576   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Pos) /*!< Bit mask of CHG15 field.   */
83577   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Min (0x0UL) /*!< Min enumerator value of CHG15 field.                               */
83578   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Max (0x1UL) /*!< Max enumerator value of CHG15 field.                               */
83579   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_Secure (0x1UL) /*!< The channel group 15 is secure                                  */
83580   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG15_NonSecure (0x0UL) /*!< The channel group 15 is non-secure                           */
83581 
83582 /* CHG16 @Bit 16 : Channel group number */
83583   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Pos (16UL) /*!< Position of CHG16 field.                                            */
83584   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Pos) /*!< Bit mask of CHG16 field.   */
83585   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Min (0x0UL) /*!< Min enumerator value of CHG16 field.                               */
83586   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Max (0x1UL) /*!< Max enumerator value of CHG16 field.                               */
83587   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_Secure (0x1UL) /*!< The channel group 16 is secure                                  */
83588   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG16_NonSecure (0x0UL) /*!< The channel group 16 is non-secure                           */
83589 
83590 /* CHG17 @Bit 17 : Channel group number */
83591   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Pos (17UL) /*!< Position of CHG17 field.                                            */
83592   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Pos) /*!< Bit mask of CHG17 field.   */
83593   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Min (0x0UL) /*!< Min enumerator value of CHG17 field.                               */
83594   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Max (0x1UL) /*!< Max enumerator value of CHG17 field.                               */
83595   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_Secure (0x1UL) /*!< The channel group 17 is secure                                  */
83596   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG17_NonSecure (0x0UL) /*!< The channel group 17 is non-secure                           */
83597 
83598 /* CHG18 @Bit 18 : Channel group number */
83599   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Pos (18UL) /*!< Position of CHG18 field.                                            */
83600   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Pos) /*!< Bit mask of CHG18 field.   */
83601   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Min (0x0UL) /*!< Min enumerator value of CHG18 field.                               */
83602   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Max (0x1UL) /*!< Max enumerator value of CHG18 field.                               */
83603   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_Secure (0x1UL) /*!< The channel group 18 is secure                                  */
83604   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG18_NonSecure (0x0UL) /*!< The channel group 18 is non-secure                           */
83605 
83606 /* CHG19 @Bit 19 : Channel group number */
83607   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Pos (19UL) /*!< Position of CHG19 field.                                            */
83608   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Pos) /*!< Bit mask of CHG19 field.   */
83609   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Min (0x0UL) /*!< Min enumerator value of CHG19 field.                               */
83610   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Max (0x1UL) /*!< Max enumerator value of CHG19 field.                               */
83611   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_Secure (0x1UL) /*!< The channel group 19 is secure                                  */
83612   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG19_NonSecure (0x0UL) /*!< The channel group 19 is non-secure                           */
83613 
83614 /* CHG20 @Bit 20 : Channel group number */
83615   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Pos (20UL) /*!< Position of CHG20 field.                                            */
83616   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Pos) /*!< Bit mask of CHG20 field.   */
83617   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Min (0x0UL) /*!< Min enumerator value of CHG20 field.                               */
83618   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Max (0x1UL) /*!< Max enumerator value of CHG20 field.                               */
83619   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_Secure (0x1UL) /*!< The channel group 20 is secure                                  */
83620   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG20_NonSecure (0x0UL) /*!< The channel group 20 is non-secure                           */
83621 
83622 /* CHG21 @Bit 21 : Channel group number */
83623   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Pos (21UL) /*!< Position of CHG21 field.                                            */
83624   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Pos) /*!< Bit mask of CHG21 field.   */
83625   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Min (0x0UL) /*!< Min enumerator value of CHG21 field.                               */
83626   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Max (0x1UL) /*!< Max enumerator value of CHG21 field.                               */
83627   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_Secure (0x1UL) /*!< The channel group 21 is secure                                  */
83628   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG21_NonSecure (0x0UL) /*!< The channel group 21 is non-secure                           */
83629 
83630 /* CHG22 @Bit 22 : Channel group number */
83631   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Pos (22UL) /*!< Position of CHG22 field.                                            */
83632   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Pos) /*!< Bit mask of CHG22 field.   */
83633   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Min (0x0UL) /*!< Min enumerator value of CHG22 field.                               */
83634   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Max (0x1UL) /*!< Max enumerator value of CHG22 field.                               */
83635   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_Secure (0x1UL) /*!< The channel group 22 is secure                                  */
83636   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG22_NonSecure (0x0UL) /*!< The channel group 22 is non-secure                           */
83637 
83638 /* CHG23 @Bit 23 : Channel group number */
83639   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Pos (23UL) /*!< Position of CHG23 field.                                            */
83640   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Pos) /*!< Bit mask of CHG23 field.   */
83641   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Min (0x0UL) /*!< Min enumerator value of CHG23 field.                               */
83642   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Max (0x1UL) /*!< Max enumerator value of CHG23 field.                               */
83643   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_Secure (0x1UL) /*!< The channel group 23 is secure                                  */
83644   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG23_NonSecure (0x0UL) /*!< The channel group 23 is non-secure                           */
83645 
83646 /* CHG24 @Bit 24 : Channel group number */
83647   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Pos (24UL) /*!< Position of CHG24 field.                                            */
83648   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Pos) /*!< Bit mask of CHG24 field.   */
83649   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Min (0x0UL) /*!< Min enumerator value of CHG24 field.                               */
83650   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Max (0x1UL) /*!< Max enumerator value of CHG24 field.                               */
83651   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_Secure (0x1UL) /*!< The channel group 24 is secure                                  */
83652   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG24_NonSecure (0x0UL) /*!< The channel group 24 is non-secure                           */
83653 
83654 /* CHG25 @Bit 25 : Channel group number */
83655   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Pos (25UL) /*!< Position of CHG25 field.                                            */
83656   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Pos) /*!< Bit mask of CHG25 field.   */
83657   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Min (0x0UL) /*!< Min enumerator value of CHG25 field.                               */
83658   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Max (0x1UL) /*!< Max enumerator value of CHG25 field.                               */
83659   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_Secure (0x1UL) /*!< The channel group 25 is secure                                  */
83660   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG25_NonSecure (0x0UL) /*!< The channel group 25 is non-secure                           */
83661 
83662 /* CHG26 @Bit 26 : Channel group number */
83663   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Pos (26UL) /*!< Position of CHG26 field.                                            */
83664   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Pos) /*!< Bit mask of CHG26 field.   */
83665   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Min (0x0UL) /*!< Min enumerator value of CHG26 field.                               */
83666   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Max (0x1UL) /*!< Max enumerator value of CHG26 field.                               */
83667   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_Secure (0x1UL) /*!< The channel group 26 is secure                                  */
83668   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG26_NonSecure (0x0UL) /*!< The channel group 26 is non-secure                           */
83669 
83670 /* CHG27 @Bit 27 : Channel group number */
83671   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Pos (27UL) /*!< Position of CHG27 field.                                            */
83672   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Pos) /*!< Bit mask of CHG27 field.   */
83673   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Min (0x0UL) /*!< Min enumerator value of CHG27 field.                               */
83674   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Max (0x1UL) /*!< Max enumerator value of CHG27 field.                               */
83675   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_Secure (0x1UL) /*!< The channel group 27 is secure                                  */
83676   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG27_NonSecure (0x0UL) /*!< The channel group 27 is non-secure                           */
83677 
83678 /* CHG28 @Bit 28 : Channel group number */
83679   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Pos (28UL) /*!< Position of CHG28 field.                                            */
83680   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Pos) /*!< Bit mask of CHG28 field.   */
83681   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Min (0x0UL) /*!< Min enumerator value of CHG28 field.                               */
83682   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Max (0x1UL) /*!< Max enumerator value of CHG28 field.                               */
83683   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_Secure (0x1UL) /*!< The channel group 28 is secure                                  */
83684   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG28_NonSecure (0x0UL) /*!< The channel group 28 is non-secure                           */
83685 
83686 /* CHG29 @Bit 29 : Channel group number */
83687   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Pos (29UL) /*!< Position of CHG29 field.                                            */
83688   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Pos) /*!< Bit mask of CHG29 field.   */
83689   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Min (0x0UL) /*!< Min enumerator value of CHG29 field.                               */
83690   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Max (0x1UL) /*!< Max enumerator value of CHG29 field.                               */
83691   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_Secure (0x1UL) /*!< The channel group 29 is secure                                  */
83692   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG29_NonSecure (0x0UL) /*!< The channel group 29 is non-secure                           */
83693 
83694 /* CHG30 @Bit 30 : Channel group number */
83695   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Pos (30UL) /*!< Position of CHG30 field.                                            */
83696   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Pos) /*!< Bit mask of CHG30 field.   */
83697   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Min (0x0UL) /*!< Min enumerator value of CHG30 field.                               */
83698   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Max (0x1UL) /*!< Max enumerator value of CHG30 field.                               */
83699   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_Secure (0x1UL) /*!< The channel group 30 is secure                                  */
83700   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG30_NonSecure (0x0UL) /*!< The channel group 30 is non-secure                           */
83701 
83702 /* CHG31 @Bit 31 : Channel group number */
83703   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Pos (31UL) /*!< Position of CHG31 field.                                            */
83704   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Msk (0x1UL << UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Pos) /*!< Bit mask of CHG31 field.   */
83705   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Min (0x0UL) /*!< Min enumerator value of CHG31 field.                               */
83706   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Max (0x1UL) /*!< Max enumerator value of CHG31 field.                               */
83707   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_Secure (0x1UL) /*!< The channel group 31 is secure                                  */
83708   #define UICR_DPPI_LOCAL_CHG_SECURE_CHG31_NonSecure (0x0UL) /*!< The channel group 31 is non-secure                           */
83709 
83710 
83711 
83712 /* ================================================= Struct UICR_DPPI_LOCAL ================================================== */
83713 /**
83714   * @brief LOCAL [UICR_DPPI_LOCAL] (unspecified)
83715   */
83716 typedef struct {
83717   __IOM uint32_t  INSTANCE;                          /*!< (@ 0x00000000) Address of the DPPI instance associated with
83718                                                                          DPPI[n].LOCAL*/
83719   __IOM NRF_UICR_DPPI_LOCAL_CH_Type CH;              /*!< (@ 0x00000004) (unspecified)                                         */
83720   __IOM NRF_UICR_DPPI_LOCAL_CHG_Type CHG;            /*!< (@ 0x00000010) (unspecified)                                         */
83721 } NRF_UICR_DPPI_LOCAL_Type;                          /*!< Size = 20 (0x014)                                                    */
83722   #define UICR_DPPI_LOCAL_MaxCount (2UL)             /*!< Size of LOCAL[2] array.                                              */
83723   #define UICR_DPPI_LOCAL_MaxIndex (1UL)             /*!< Max index of LOCAL[2] array.                                         */
83724   #define UICR_DPPI_LOCAL_MinIndex (0UL)             /*!< Min index of LOCAL[2] array.                                         */
83725 
83726 /* UICR_DPPI_LOCAL_INSTANCE: Address of the DPPI instance associated with DPPI[n].LOCAL */
83727   #define UICR_DPPI_LOCAL_INSTANCE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INSTANCE register.                            */
83728 
83729 /* ADDRESS @Bits 0..31 : Instance address */
83730   #define UICR_DPPI_LOCAL_INSTANCE_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                           */
83731   #define UICR_DPPI_LOCAL_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICR_DPPI_LOCAL_INSTANCE_ADDRESS_Pos) /*!< Bit mask of ADDRESS
83732                                                                             field.*/
83733 
83734 
83735 
83736 /* ============================================= Struct UICR_DPPI_GLOBAL_CH_LINK ============================================= */
83737 /**
83738   * @brief LINK [UICR_DPPI_GLOBAL_CH_LINK] (unspecified)
83739   */
83740 typedef struct {
83741   __IOM uint32_t  DIR;                               /*!< (@ 0x00000000) Request linking the channels of DPPI[n] in Global
83742                                                                          domain as source or sink*/
83743   __IOM uint32_t  EN;                                /*!< (@ 0x00000004) Request linking of the channels of DPPI[n] in the
83744                                                                          Global domain*/
83745 } NRF_UICR_DPPI_GLOBAL_CH_LINK_Type;                 /*!< Size = 8 (0x008)                                                     */
83746 
83747 /* UICR_DPPI_GLOBAL_CH_LINK_DIR: Request linking the channels of DPPI[n] in Global domain as source or sink */
83748   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_ResetValue (0xFFFFFFFFUL) /*!< Reset value of DIR register.                             */
83749 
83750 /* CH0 @Bit 0 : Link direction */
83751   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Pos (0UL) /*!< Position of CH0 field.                                               */
83752   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Pos) /*!< Bit mask of CH0 field.     */
83753   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field.                                 */
83754   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field.                                 */
83755   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Source (0x1UL) /*!< The channel 0 is linked as source                               */
83756   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH0_Sink (0x0UL) /*!< The channel 0 is linked as sink                                   */
83757 
83758 /* CH1 @Bit 1 : Link direction */
83759   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Pos (1UL) /*!< Position of CH1 field.                                               */
83760   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Pos) /*!< Bit mask of CH1 field.     */
83761   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field.                                 */
83762   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field.                                 */
83763   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Source (0x1UL) /*!< The channel 1 is linked as source                               */
83764   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH1_Sink (0x0UL) /*!< The channel 1 is linked as sink                                   */
83765 
83766 /* CH2 @Bit 2 : Link direction */
83767   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Pos (2UL) /*!< Position of CH2 field.                                               */
83768   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Pos) /*!< Bit mask of CH2 field.     */
83769   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field.                                 */
83770   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field.                                 */
83771   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Source (0x1UL) /*!< The channel 2 is linked as source                               */
83772   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH2_Sink (0x0UL) /*!< The channel 2 is linked as sink                                   */
83773 
83774 /* CH3 @Bit 3 : Link direction */
83775   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Pos (3UL) /*!< Position of CH3 field.                                               */
83776   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Pos) /*!< Bit mask of CH3 field.     */
83777   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field.                                 */
83778   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field.                                 */
83779   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Source (0x1UL) /*!< The channel 3 is linked as source                               */
83780   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH3_Sink (0x0UL) /*!< The channel 3 is linked as sink                                   */
83781 
83782 /* CH4 @Bit 4 : Link direction */
83783   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Pos (4UL) /*!< Position of CH4 field.                                               */
83784   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Pos) /*!< Bit mask of CH4 field.     */
83785   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field.                                 */
83786   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field.                                 */
83787   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Source (0x1UL) /*!< The channel 4 is linked as source                               */
83788   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH4_Sink (0x0UL) /*!< The channel 4 is linked as sink                                   */
83789 
83790 /* CH5 @Bit 5 : Link direction */
83791   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Pos (5UL) /*!< Position of CH5 field.                                               */
83792   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Pos) /*!< Bit mask of CH5 field.     */
83793   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field.                                 */
83794   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field.                                 */
83795   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Source (0x1UL) /*!< The channel 5 is linked as source                               */
83796   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH5_Sink (0x0UL) /*!< The channel 5 is linked as sink                                   */
83797 
83798 /* CH6 @Bit 6 : Link direction */
83799   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Pos (6UL) /*!< Position of CH6 field.                                               */
83800   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Pos) /*!< Bit mask of CH6 field.     */
83801   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field.                                 */
83802   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field.                                 */
83803   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Source (0x1UL) /*!< The channel 6 is linked as source                               */
83804   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH6_Sink (0x0UL) /*!< The channel 6 is linked as sink                                   */
83805 
83806 /* CH7 @Bit 7 : Link direction */
83807   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Pos (7UL) /*!< Position of CH7 field.                                               */
83808   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Pos) /*!< Bit mask of CH7 field.     */
83809   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field.                                 */
83810   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field.                                 */
83811   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Source (0x1UL) /*!< The channel 7 is linked as source                               */
83812   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH7_Sink (0x0UL) /*!< The channel 7 is linked as sink                                   */
83813 
83814 /* CH8 @Bit 8 : Link direction */
83815   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Pos (8UL) /*!< Position of CH8 field.                                               */
83816   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Pos) /*!< Bit mask of CH8 field.     */
83817   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field.                                 */
83818   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field.                                 */
83819   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Source (0x1UL) /*!< The channel 8 is linked as source                               */
83820   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH8_Sink (0x0UL) /*!< The channel 8 is linked as sink                                   */
83821 
83822 /* CH9 @Bit 9 : Link direction */
83823   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Pos (9UL) /*!< Position of CH9 field.                                               */
83824   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Pos) /*!< Bit mask of CH9 field.     */
83825   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field.                                 */
83826   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field.                                 */
83827   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Source (0x1UL) /*!< The channel 9 is linked as source                               */
83828   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH9_Sink (0x0UL) /*!< The channel 9 is linked as sink                                   */
83829 
83830 /* CH10 @Bit 10 : Link direction */
83831   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Pos (10UL) /*!< Position of CH10 field.                                            */
83832   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Pos) /*!< Bit mask of CH10 field.  */
83833   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field.                               */
83834   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field.                               */
83835   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Source (0x1UL) /*!< The channel 10 is linked as source                             */
83836   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH10_Sink (0x0UL) /*!< The channel 10 is linked as sink                                 */
83837 
83838 /* CH11 @Bit 11 : Link direction */
83839   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Pos (11UL) /*!< Position of CH11 field.                                            */
83840   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Pos) /*!< Bit mask of CH11 field.  */
83841   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field.                               */
83842   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field.                               */
83843   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Source (0x1UL) /*!< The channel 11 is linked as source                             */
83844   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH11_Sink (0x0UL) /*!< The channel 11 is linked as sink                                 */
83845 
83846 /* CH12 @Bit 12 : Link direction */
83847   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Pos (12UL) /*!< Position of CH12 field.                                            */
83848   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Pos) /*!< Bit mask of CH12 field.  */
83849   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field.                               */
83850   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field.                               */
83851   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Source (0x1UL) /*!< The channel 12 is linked as source                             */
83852   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH12_Sink (0x0UL) /*!< The channel 12 is linked as sink                                 */
83853 
83854 /* CH13 @Bit 13 : Link direction */
83855   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Pos (13UL) /*!< Position of CH13 field.                                            */
83856   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Pos) /*!< Bit mask of CH13 field.  */
83857   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field.                               */
83858   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field.                               */
83859   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Source (0x1UL) /*!< The channel 13 is linked as source                             */
83860   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH13_Sink (0x0UL) /*!< The channel 13 is linked as sink                                 */
83861 
83862 /* CH14 @Bit 14 : Link direction */
83863   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Pos (14UL) /*!< Position of CH14 field.                                            */
83864   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Pos) /*!< Bit mask of CH14 field.  */
83865   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field.                               */
83866   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field.                               */
83867   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Source (0x1UL) /*!< The channel 14 is linked as source                             */
83868   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH14_Sink (0x0UL) /*!< The channel 14 is linked as sink                                 */
83869 
83870 /* CH15 @Bit 15 : Link direction */
83871   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Pos (15UL) /*!< Position of CH15 field.                                            */
83872   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Pos) /*!< Bit mask of CH15 field.  */
83873   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field.                               */
83874   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field.                               */
83875   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Source (0x1UL) /*!< The channel 15 is linked as source                             */
83876   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH15_Sink (0x0UL) /*!< The channel 15 is linked as sink                                 */
83877 
83878 /* CH16 @Bit 16 : Link direction */
83879   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Pos (16UL) /*!< Position of CH16 field.                                            */
83880   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Pos) /*!< Bit mask of CH16 field.  */
83881   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field.                               */
83882   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field.                               */
83883   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Source (0x1UL) /*!< The channel 16 is linked as source                             */
83884   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH16_Sink (0x0UL) /*!< The channel 16 is linked as sink                                 */
83885 
83886 /* CH17 @Bit 17 : Link direction */
83887   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Pos (17UL) /*!< Position of CH17 field.                                            */
83888   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Pos) /*!< Bit mask of CH17 field.  */
83889   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field.                               */
83890   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field.                               */
83891   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Source (0x1UL) /*!< The channel 17 is linked as source                             */
83892   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH17_Sink (0x0UL) /*!< The channel 17 is linked as sink                                 */
83893 
83894 /* CH18 @Bit 18 : Link direction */
83895   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Pos (18UL) /*!< Position of CH18 field.                                            */
83896   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Pos) /*!< Bit mask of CH18 field.  */
83897   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field.                               */
83898   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field.                               */
83899   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Source (0x1UL) /*!< The channel 18 is linked as source                             */
83900   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH18_Sink (0x0UL) /*!< The channel 18 is linked as sink                                 */
83901 
83902 /* CH19 @Bit 19 : Link direction */
83903   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Pos (19UL) /*!< Position of CH19 field.                                            */
83904   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Pos) /*!< Bit mask of CH19 field.  */
83905   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field.                               */
83906   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field.                               */
83907   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Source (0x1UL) /*!< The channel 19 is linked as source                             */
83908   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH19_Sink (0x0UL) /*!< The channel 19 is linked as sink                                 */
83909 
83910 /* CH20 @Bit 20 : Link direction */
83911   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Pos (20UL) /*!< Position of CH20 field.                                            */
83912   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Pos) /*!< Bit mask of CH20 field.  */
83913   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field.                               */
83914   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field.                               */
83915   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Source (0x1UL) /*!< The channel 20 is linked as source                             */
83916   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH20_Sink (0x0UL) /*!< The channel 20 is linked as sink                                 */
83917 
83918 /* CH21 @Bit 21 : Link direction */
83919   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Pos (21UL) /*!< Position of CH21 field.                                            */
83920   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Pos) /*!< Bit mask of CH21 field.  */
83921   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field.                               */
83922   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field.                               */
83923   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Source (0x1UL) /*!< The channel 21 is linked as source                             */
83924   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH21_Sink (0x0UL) /*!< The channel 21 is linked as sink                                 */
83925 
83926 /* CH22 @Bit 22 : Link direction */
83927   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Pos (22UL) /*!< Position of CH22 field.                                            */
83928   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Pos) /*!< Bit mask of CH22 field.  */
83929   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field.                               */
83930   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field.                               */
83931   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Source (0x1UL) /*!< The channel 22 is linked as source                             */
83932   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH22_Sink (0x0UL) /*!< The channel 22 is linked as sink                                 */
83933 
83934 /* CH23 @Bit 23 : Link direction */
83935   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Pos (23UL) /*!< Position of CH23 field.                                            */
83936   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Pos) /*!< Bit mask of CH23 field.  */
83937   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field.                               */
83938   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field.                               */
83939   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Source (0x1UL) /*!< The channel 23 is linked as source                             */
83940   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH23_Sink (0x0UL) /*!< The channel 23 is linked as sink                                 */
83941 
83942 /* CH24 @Bit 24 : Link direction */
83943   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Pos (24UL) /*!< Position of CH24 field.                                            */
83944   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Pos) /*!< Bit mask of CH24 field.  */
83945   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field.                               */
83946   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field.                               */
83947   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Source (0x1UL) /*!< The channel 24 is linked as source                             */
83948   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH24_Sink (0x0UL) /*!< The channel 24 is linked as sink                                 */
83949 
83950 /* CH25 @Bit 25 : Link direction */
83951   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Pos (25UL) /*!< Position of CH25 field.                                            */
83952   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Pos) /*!< Bit mask of CH25 field.  */
83953   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field.                               */
83954   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field.                               */
83955   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Source (0x1UL) /*!< The channel 25 is linked as source                             */
83956   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH25_Sink (0x0UL) /*!< The channel 25 is linked as sink                                 */
83957 
83958 /* CH26 @Bit 26 : Link direction */
83959   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Pos (26UL) /*!< Position of CH26 field.                                            */
83960   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Pos) /*!< Bit mask of CH26 field.  */
83961   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field.                               */
83962   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field.                               */
83963   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Source (0x1UL) /*!< The channel 26 is linked as source                             */
83964   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH26_Sink (0x0UL) /*!< The channel 26 is linked as sink                                 */
83965 
83966 /* CH27 @Bit 27 : Link direction */
83967   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Pos (27UL) /*!< Position of CH27 field.                                            */
83968   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Pos) /*!< Bit mask of CH27 field.  */
83969   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field.                               */
83970   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field.                               */
83971   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Source (0x1UL) /*!< The channel 27 is linked as source                             */
83972   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH27_Sink (0x0UL) /*!< The channel 27 is linked as sink                                 */
83973 
83974 /* CH28 @Bit 28 : Link direction */
83975   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Pos (28UL) /*!< Position of CH28 field.                                            */
83976   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Pos) /*!< Bit mask of CH28 field.  */
83977   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field.                               */
83978   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field.                               */
83979   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Source (0x1UL) /*!< The channel 28 is linked as source                             */
83980   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH28_Sink (0x0UL) /*!< The channel 28 is linked as sink                                 */
83981 
83982 /* CH29 @Bit 29 : Link direction */
83983   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Pos (29UL) /*!< Position of CH29 field.                                            */
83984   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Pos) /*!< Bit mask of CH29 field.  */
83985   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field.                               */
83986   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field.                               */
83987   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Source (0x1UL) /*!< The channel 29 is linked as source                             */
83988   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH29_Sink (0x0UL) /*!< The channel 29 is linked as sink                                 */
83989 
83990 /* CH30 @Bit 30 : Link direction */
83991   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Pos (30UL) /*!< Position of CH30 field.                                            */
83992   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Pos) /*!< Bit mask of CH30 field.  */
83993   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field.                               */
83994   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field.                               */
83995   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Source (0x1UL) /*!< The channel 30 is linked as source                             */
83996   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH30_Sink (0x0UL) /*!< The channel 30 is linked as sink                                 */
83997 
83998 /* CH31 @Bit 31 : Link direction */
83999   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Pos (31UL) /*!< Position of CH31 field.                                            */
84000   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Pos) /*!< Bit mask of CH31 field.  */
84001   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field.                               */
84002   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field.                               */
84003   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Source (0x1UL) /*!< The channel 31 is linked as source                             */
84004   #define UICR_DPPI_GLOBAL_CH_LINK_DIR_CH31_Sink (0x0UL) /*!< The channel 31 is linked as sink                                 */
84005 
84006 
84007 /* UICR_DPPI_GLOBAL_CH_LINK_EN: Request linking of the channels of DPPI[n] in the Global domain */
84008   #define UICR_DPPI_GLOBAL_CH_LINK_EN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of EN register.                               */
84009 
84010 /* CH0 @Bit 0 : Link enable */
84011   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Pos (0UL)  /*!< Position of CH0 field.                                               */
84012   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Pos) /*!< Bit mask of CH0 field.       */
84013   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field.                                  */
84014   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field.                                  */
84015   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Disabled (0x1UL) /*!< The channel 0 is disabled                                      */
84016   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH0_Enabled (0x0UL) /*!< The channel 0 is enabled                                        */
84017 
84018 /* CH1 @Bit 1 : Link enable */
84019   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Pos (1UL)  /*!< Position of CH1 field.                                               */
84020   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Pos) /*!< Bit mask of CH1 field.       */
84021   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field.                                  */
84022   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field.                                  */
84023   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Disabled (0x1UL) /*!< The channel 1 is disabled                                      */
84024   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH1_Enabled (0x0UL) /*!< The channel 1 is enabled                                        */
84025 
84026 /* CH2 @Bit 2 : Link enable */
84027   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Pos (2UL)  /*!< Position of CH2 field.                                               */
84028   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Pos) /*!< Bit mask of CH2 field.       */
84029   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field.                                  */
84030   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field.                                  */
84031   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Disabled (0x1UL) /*!< The channel 2 is disabled                                      */
84032   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH2_Enabled (0x0UL) /*!< The channel 2 is enabled                                        */
84033 
84034 /* CH3 @Bit 3 : Link enable */
84035   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Pos (3UL)  /*!< Position of CH3 field.                                               */
84036   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Pos) /*!< Bit mask of CH3 field.       */
84037   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field.                                  */
84038   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field.                                  */
84039   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Disabled (0x1UL) /*!< The channel 3 is disabled                                      */
84040   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH3_Enabled (0x0UL) /*!< The channel 3 is enabled                                        */
84041 
84042 /* CH4 @Bit 4 : Link enable */
84043   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Pos (4UL)  /*!< Position of CH4 field.                                               */
84044   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Pos) /*!< Bit mask of CH4 field.       */
84045   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field.                                  */
84046   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field.                                  */
84047   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Disabled (0x1UL) /*!< The channel 4 is disabled                                      */
84048   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH4_Enabled (0x0UL) /*!< The channel 4 is enabled                                        */
84049 
84050 /* CH5 @Bit 5 : Link enable */
84051   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Pos (5UL)  /*!< Position of CH5 field.                                               */
84052   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Pos) /*!< Bit mask of CH5 field.       */
84053   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field.                                  */
84054   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field.                                  */
84055   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Disabled (0x1UL) /*!< The channel 5 is disabled                                      */
84056   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH5_Enabled (0x0UL) /*!< The channel 5 is enabled                                        */
84057 
84058 /* CH6 @Bit 6 : Link enable */
84059   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Pos (6UL)  /*!< Position of CH6 field.                                               */
84060   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Pos) /*!< Bit mask of CH6 field.       */
84061   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field.                                  */
84062   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field.                                  */
84063   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Disabled (0x1UL) /*!< The channel 6 is disabled                                      */
84064   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH6_Enabled (0x0UL) /*!< The channel 6 is enabled                                        */
84065 
84066 /* CH7 @Bit 7 : Link enable */
84067   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Pos (7UL)  /*!< Position of CH7 field.                                               */
84068   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Pos) /*!< Bit mask of CH7 field.       */
84069   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field.                                  */
84070   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field.                                  */
84071   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Disabled (0x1UL) /*!< The channel 7 is disabled                                      */
84072   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH7_Enabled (0x0UL) /*!< The channel 7 is enabled                                        */
84073 
84074 /* CH8 @Bit 8 : Link enable */
84075   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Pos (8UL)  /*!< Position of CH8 field.                                               */
84076   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Pos) /*!< Bit mask of CH8 field.       */
84077   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field.                                  */
84078   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field.                                  */
84079   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Disabled (0x1UL) /*!< The channel 8 is disabled                                      */
84080   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH8_Enabled (0x0UL) /*!< The channel 8 is enabled                                        */
84081 
84082 /* CH9 @Bit 9 : Link enable */
84083   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Pos (9UL)  /*!< Position of CH9 field.                                               */
84084   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Pos) /*!< Bit mask of CH9 field.       */
84085   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field.                                  */
84086   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field.                                  */
84087   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Disabled (0x1UL) /*!< The channel 9 is disabled                                      */
84088   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH9_Enabled (0x0UL) /*!< The channel 9 is enabled                                        */
84089 
84090 /* CH10 @Bit 10 : Link enable */
84091   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Pos (10UL) /*!< Position of CH10 field.                                             */
84092   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Pos) /*!< Bit mask of CH10 field.    */
84093   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field.                                */
84094   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field.                                */
84095   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Disabled (0x1UL) /*!< The channel 10 is disabled                                    */
84096   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH10_Enabled (0x0UL) /*!< The channel 10 is enabled                                      */
84097 
84098 /* CH11 @Bit 11 : Link enable */
84099   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Pos (11UL) /*!< Position of CH11 field.                                             */
84100   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Pos) /*!< Bit mask of CH11 field.    */
84101   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field.                                */
84102   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field.                                */
84103   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Disabled (0x1UL) /*!< The channel 11 is disabled                                    */
84104   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH11_Enabled (0x0UL) /*!< The channel 11 is enabled                                      */
84105 
84106 /* CH12 @Bit 12 : Link enable */
84107   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Pos (12UL) /*!< Position of CH12 field.                                             */
84108   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Pos) /*!< Bit mask of CH12 field.    */
84109   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field.                                */
84110   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field.                                */
84111   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Disabled (0x1UL) /*!< The channel 12 is disabled                                    */
84112   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH12_Enabled (0x0UL) /*!< The channel 12 is enabled                                      */
84113 
84114 /* CH13 @Bit 13 : Link enable */
84115   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Pos (13UL) /*!< Position of CH13 field.                                             */
84116   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Pos) /*!< Bit mask of CH13 field.    */
84117   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field.                                */
84118   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field.                                */
84119   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Disabled (0x1UL) /*!< The channel 13 is disabled                                    */
84120   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH13_Enabled (0x0UL) /*!< The channel 13 is enabled                                      */
84121 
84122 /* CH14 @Bit 14 : Link enable */
84123   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Pos (14UL) /*!< Position of CH14 field.                                             */
84124   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Pos) /*!< Bit mask of CH14 field.    */
84125   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field.                                */
84126   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field.                                */
84127   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Disabled (0x1UL) /*!< The channel 14 is disabled                                    */
84128   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH14_Enabled (0x0UL) /*!< The channel 14 is enabled                                      */
84129 
84130 /* CH15 @Bit 15 : Link enable */
84131   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Pos (15UL) /*!< Position of CH15 field.                                             */
84132   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Pos) /*!< Bit mask of CH15 field.    */
84133   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field.                                */
84134   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field.                                */
84135   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Disabled (0x1UL) /*!< The channel 15 is disabled                                    */
84136   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH15_Enabled (0x0UL) /*!< The channel 15 is enabled                                      */
84137 
84138 /* CH16 @Bit 16 : Link enable */
84139   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Pos (16UL) /*!< Position of CH16 field.                                             */
84140   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Pos) /*!< Bit mask of CH16 field.    */
84141   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field.                                */
84142   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field.                                */
84143   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Disabled (0x1UL) /*!< The channel 16 is disabled                                    */
84144   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH16_Enabled (0x0UL) /*!< The channel 16 is enabled                                      */
84145 
84146 /* CH17 @Bit 17 : Link enable */
84147   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Pos (17UL) /*!< Position of CH17 field.                                             */
84148   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Pos) /*!< Bit mask of CH17 field.    */
84149   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field.                                */
84150   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field.                                */
84151   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Disabled (0x1UL) /*!< The channel 17 is disabled                                    */
84152   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH17_Enabled (0x0UL) /*!< The channel 17 is enabled                                      */
84153 
84154 /* CH18 @Bit 18 : Link enable */
84155   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Pos (18UL) /*!< Position of CH18 field.                                             */
84156   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Pos) /*!< Bit mask of CH18 field.    */
84157   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field.                                */
84158   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field.                                */
84159   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Disabled (0x1UL) /*!< The channel 18 is disabled                                    */
84160   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH18_Enabled (0x0UL) /*!< The channel 18 is enabled                                      */
84161 
84162 /* CH19 @Bit 19 : Link enable */
84163   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Pos (19UL) /*!< Position of CH19 field.                                             */
84164   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Pos) /*!< Bit mask of CH19 field.    */
84165   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field.                                */
84166   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field.                                */
84167   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Disabled (0x1UL) /*!< The channel 19 is disabled                                    */
84168   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH19_Enabled (0x0UL) /*!< The channel 19 is enabled                                      */
84169 
84170 /* CH20 @Bit 20 : Link enable */
84171   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Pos (20UL) /*!< Position of CH20 field.                                             */
84172   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Pos) /*!< Bit mask of CH20 field.    */
84173   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field.                                */
84174   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field.                                */
84175   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Disabled (0x1UL) /*!< The channel 20 is disabled                                    */
84176   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH20_Enabled (0x0UL) /*!< The channel 20 is enabled                                      */
84177 
84178 /* CH21 @Bit 21 : Link enable */
84179   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Pos (21UL) /*!< Position of CH21 field.                                             */
84180   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Pos) /*!< Bit mask of CH21 field.    */
84181   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field.                                */
84182   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field.                                */
84183   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Disabled (0x1UL) /*!< The channel 21 is disabled                                    */
84184   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH21_Enabled (0x0UL) /*!< The channel 21 is enabled                                      */
84185 
84186 /* CH22 @Bit 22 : Link enable */
84187   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Pos (22UL) /*!< Position of CH22 field.                                             */
84188   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Pos) /*!< Bit mask of CH22 field.    */
84189   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field.                                */
84190   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field.                                */
84191   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Disabled (0x1UL) /*!< The channel 22 is disabled                                    */
84192   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH22_Enabled (0x0UL) /*!< The channel 22 is enabled                                      */
84193 
84194 /* CH23 @Bit 23 : Link enable */
84195   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Pos (23UL) /*!< Position of CH23 field.                                             */
84196   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Pos) /*!< Bit mask of CH23 field.    */
84197   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field.                                */
84198   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field.                                */
84199   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Disabled (0x1UL) /*!< The channel 23 is disabled                                    */
84200   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH23_Enabled (0x0UL) /*!< The channel 23 is enabled                                      */
84201 
84202 /* CH24 @Bit 24 : Link enable */
84203   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Pos (24UL) /*!< Position of CH24 field.                                             */
84204   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Pos) /*!< Bit mask of CH24 field.    */
84205   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field.                                */
84206   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field.                                */
84207   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Disabled (0x1UL) /*!< The channel 24 is disabled                                    */
84208   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH24_Enabled (0x0UL) /*!< The channel 24 is enabled                                      */
84209 
84210 /* CH25 @Bit 25 : Link enable */
84211   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Pos (25UL) /*!< Position of CH25 field.                                             */
84212   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Pos) /*!< Bit mask of CH25 field.    */
84213   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field.                                */
84214   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field.                                */
84215   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Disabled (0x1UL) /*!< The channel 25 is disabled                                    */
84216   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH25_Enabled (0x0UL) /*!< The channel 25 is enabled                                      */
84217 
84218 /* CH26 @Bit 26 : Link enable */
84219   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Pos (26UL) /*!< Position of CH26 field.                                             */
84220   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Pos) /*!< Bit mask of CH26 field.    */
84221   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field.                                */
84222   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field.                                */
84223   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Disabled (0x1UL) /*!< The channel 26 is disabled                                    */
84224   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH26_Enabled (0x0UL) /*!< The channel 26 is enabled                                      */
84225 
84226 /* CH27 @Bit 27 : Link enable */
84227   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Pos (27UL) /*!< Position of CH27 field.                                             */
84228   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Pos) /*!< Bit mask of CH27 field.    */
84229   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field.                                */
84230   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field.                                */
84231   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Disabled (0x1UL) /*!< The channel 27 is disabled                                    */
84232   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH27_Enabled (0x0UL) /*!< The channel 27 is enabled                                      */
84233 
84234 /* CH28 @Bit 28 : Link enable */
84235   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Pos (28UL) /*!< Position of CH28 field.                                             */
84236   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Pos) /*!< Bit mask of CH28 field.    */
84237   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field.                                */
84238   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field.                                */
84239   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Disabled (0x1UL) /*!< The channel 28 is disabled                                    */
84240   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH28_Enabled (0x0UL) /*!< The channel 28 is enabled                                      */
84241 
84242 /* CH29 @Bit 29 : Link enable */
84243   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Pos (29UL) /*!< Position of CH29 field.                                             */
84244   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Pos) /*!< Bit mask of CH29 field.    */
84245   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field.                                */
84246   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field.                                */
84247   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Disabled (0x1UL) /*!< The channel 29 is disabled                                    */
84248   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH29_Enabled (0x0UL) /*!< The channel 29 is enabled                                      */
84249 
84250 /* CH30 @Bit 30 : Link enable */
84251   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Pos (30UL) /*!< Position of CH30 field.                                             */
84252   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Pos) /*!< Bit mask of CH30 field.    */
84253   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field.                                */
84254   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field.                                */
84255   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Disabled (0x1UL) /*!< The channel 30 is disabled                                    */
84256   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH30_Enabled (0x0UL) /*!< The channel 30 is enabled                                      */
84257 
84258 /* CH31 @Bit 31 : Link enable */
84259   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Pos (31UL) /*!< Position of CH31 field.                                             */
84260   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Pos) /*!< Bit mask of CH31 field.    */
84261   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field.                                */
84262   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field.                                */
84263   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Disabled (0x1UL) /*!< The channel 31 is disabled                                    */
84264   #define UICR_DPPI_GLOBAL_CH_LINK_EN_CH31_Enabled (0x0UL) /*!< The channel 31 is enabled                                      */
84265 
84266 
84267 
84268 /* =============================================== Struct UICR_DPPI_GLOBAL_CH ================================================ */
84269 /**
84270   * @brief CH [UICR_DPPI_GLOBAL_CH] (unspecified)
84271   */
84272 typedef struct {
84273   __IOM uint32_t  OWN;                               /*!< (@ 0x00000000) Request ownership of the channels of DPPI[n] in Global
84274                                                                          Domain*/
84275   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Request permission for the channels of DPPI[n] in
84276                                                                          Global domain*/
84277   __IOM NRF_UICR_DPPI_GLOBAL_CH_LINK_Type LINK;      /*!< (@ 0x00000008) (unspecified)                                         */
84278 } NRF_UICR_DPPI_GLOBAL_CH_Type;                      /*!< Size = 16 (0x010)                                                    */
84279 
84280 /* UICR_DPPI_GLOBAL_CH_OWN: Request ownership of the channels of DPPI[n] in Global Domain */
84281   #define UICR_DPPI_GLOBAL_CH_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register.                                  */
84282 
84283 /* CH0 @Bit 0 : Channel number */
84284   #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Pos (0UL)      /*!< Position of CH0 field.                                               */
84285   #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH0_Pos) /*!< Bit mask of CH0 field.               */
84286   #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Min (0x0UL)    /*!< Min enumerator value of CH0 field.                                   */
84287   #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Max (0x1UL)    /*!< Max enumerator value of CH0 field.                                   */
84288   #define UICR_DPPI_GLOBAL_CH_OWN_CH0_NotOwn (0x1UL) /*!< Do not own the channel 0                                             */
84289   #define UICR_DPPI_GLOBAL_CH_OWN_CH0_Own (0x0UL)    /*!< Own the channel 0                                                    */
84290 
84291 /* CH1 @Bit 1 : Channel number */
84292   #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Pos (1UL)      /*!< Position of CH1 field.                                               */
84293   #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH1_Pos) /*!< Bit mask of CH1 field.               */
84294   #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Min (0x0UL)    /*!< Min enumerator value of CH1 field.                                   */
84295   #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Max (0x1UL)    /*!< Max enumerator value of CH1 field.                                   */
84296   #define UICR_DPPI_GLOBAL_CH_OWN_CH1_NotOwn (0x1UL) /*!< Do not own the channel 1                                             */
84297   #define UICR_DPPI_GLOBAL_CH_OWN_CH1_Own (0x0UL)    /*!< Own the channel 1                                                    */
84298 
84299 /* CH2 @Bit 2 : Channel number */
84300   #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Pos (2UL)      /*!< Position of CH2 field.                                               */
84301   #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH2_Pos) /*!< Bit mask of CH2 field.               */
84302   #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Min (0x0UL)    /*!< Min enumerator value of CH2 field.                                   */
84303   #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Max (0x1UL)    /*!< Max enumerator value of CH2 field.                                   */
84304   #define UICR_DPPI_GLOBAL_CH_OWN_CH2_NotOwn (0x1UL) /*!< Do not own the channel 2                                             */
84305   #define UICR_DPPI_GLOBAL_CH_OWN_CH2_Own (0x0UL)    /*!< Own the channel 2                                                    */
84306 
84307 /* CH3 @Bit 3 : Channel number */
84308   #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Pos (3UL)      /*!< Position of CH3 field.                                               */
84309   #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH3_Pos) /*!< Bit mask of CH3 field.               */
84310   #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Min (0x0UL)    /*!< Min enumerator value of CH3 field.                                   */
84311   #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Max (0x1UL)    /*!< Max enumerator value of CH3 field.                                   */
84312   #define UICR_DPPI_GLOBAL_CH_OWN_CH3_NotOwn (0x1UL) /*!< Do not own the channel 3                                             */
84313   #define UICR_DPPI_GLOBAL_CH_OWN_CH3_Own (0x0UL)    /*!< Own the channel 3                                                    */
84314 
84315 /* CH4 @Bit 4 : Channel number */
84316   #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Pos (4UL)      /*!< Position of CH4 field.                                               */
84317   #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH4_Pos) /*!< Bit mask of CH4 field.               */
84318   #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Min (0x0UL)    /*!< Min enumerator value of CH4 field.                                   */
84319   #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Max (0x1UL)    /*!< Max enumerator value of CH4 field.                                   */
84320   #define UICR_DPPI_GLOBAL_CH_OWN_CH4_NotOwn (0x1UL) /*!< Do not own the channel 4                                             */
84321   #define UICR_DPPI_GLOBAL_CH_OWN_CH4_Own (0x0UL)    /*!< Own the channel 4                                                    */
84322 
84323 /* CH5 @Bit 5 : Channel number */
84324   #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Pos (5UL)      /*!< Position of CH5 field.                                               */
84325   #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH5_Pos) /*!< Bit mask of CH5 field.               */
84326   #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Min (0x0UL)    /*!< Min enumerator value of CH5 field.                                   */
84327   #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Max (0x1UL)    /*!< Max enumerator value of CH5 field.                                   */
84328   #define UICR_DPPI_GLOBAL_CH_OWN_CH5_NotOwn (0x1UL) /*!< Do not own the channel 5                                             */
84329   #define UICR_DPPI_GLOBAL_CH_OWN_CH5_Own (0x0UL)    /*!< Own the channel 5                                                    */
84330 
84331 /* CH6 @Bit 6 : Channel number */
84332   #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Pos (6UL)      /*!< Position of CH6 field.                                               */
84333   #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH6_Pos) /*!< Bit mask of CH6 field.               */
84334   #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Min (0x0UL)    /*!< Min enumerator value of CH6 field.                                   */
84335   #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Max (0x1UL)    /*!< Max enumerator value of CH6 field.                                   */
84336   #define UICR_DPPI_GLOBAL_CH_OWN_CH6_NotOwn (0x1UL) /*!< Do not own the channel 6                                             */
84337   #define UICR_DPPI_GLOBAL_CH_OWN_CH6_Own (0x0UL)    /*!< Own the channel 6                                                    */
84338 
84339 /* CH7 @Bit 7 : Channel number */
84340   #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Pos (7UL)      /*!< Position of CH7 field.                                               */
84341   #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH7_Pos) /*!< Bit mask of CH7 field.               */
84342   #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Min (0x0UL)    /*!< Min enumerator value of CH7 field.                                   */
84343   #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Max (0x1UL)    /*!< Max enumerator value of CH7 field.                                   */
84344   #define UICR_DPPI_GLOBAL_CH_OWN_CH7_NotOwn (0x1UL) /*!< Do not own the channel 7                                             */
84345   #define UICR_DPPI_GLOBAL_CH_OWN_CH7_Own (0x0UL)    /*!< Own the channel 7                                                    */
84346 
84347 /* CH8 @Bit 8 : Channel number */
84348   #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Pos (8UL)      /*!< Position of CH8 field.                                               */
84349   #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH8_Pos) /*!< Bit mask of CH8 field.               */
84350   #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Min (0x0UL)    /*!< Min enumerator value of CH8 field.                                   */
84351   #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Max (0x1UL)    /*!< Max enumerator value of CH8 field.                                   */
84352   #define UICR_DPPI_GLOBAL_CH_OWN_CH8_NotOwn (0x1UL) /*!< Do not own the channel 8                                             */
84353   #define UICR_DPPI_GLOBAL_CH_OWN_CH8_Own (0x0UL)    /*!< Own the channel 8                                                    */
84354 
84355 /* CH9 @Bit 9 : Channel number */
84356   #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Pos (9UL)      /*!< Position of CH9 field.                                               */
84357   #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH9_Pos) /*!< Bit mask of CH9 field.               */
84358   #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Min (0x0UL)    /*!< Min enumerator value of CH9 field.                                   */
84359   #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Max (0x1UL)    /*!< Max enumerator value of CH9 field.                                   */
84360   #define UICR_DPPI_GLOBAL_CH_OWN_CH9_NotOwn (0x1UL) /*!< Do not own the channel 9                                             */
84361   #define UICR_DPPI_GLOBAL_CH_OWN_CH9_Own (0x0UL)    /*!< Own the channel 9                                                    */
84362 
84363 /* CH10 @Bit 10 : Channel number */
84364   #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Pos (10UL)    /*!< Position of CH10 field.                                              */
84365   #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH10_Pos) /*!< Bit mask of CH10 field.            */
84366   #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Min (0x0UL)   /*!< Min enumerator value of CH10 field.                                  */
84367   #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Max (0x1UL)   /*!< Max enumerator value of CH10 field.                                  */
84368   #define UICR_DPPI_GLOBAL_CH_OWN_CH10_NotOwn (0x1UL) /*!< Do not own the channel 10                                           */
84369   #define UICR_DPPI_GLOBAL_CH_OWN_CH10_Own (0x0UL)   /*!< Own the channel 10                                                   */
84370 
84371 /* CH11 @Bit 11 : Channel number */
84372   #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Pos (11UL)    /*!< Position of CH11 field.                                              */
84373   #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH11_Pos) /*!< Bit mask of CH11 field.            */
84374   #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Min (0x0UL)   /*!< Min enumerator value of CH11 field.                                  */
84375   #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Max (0x1UL)   /*!< Max enumerator value of CH11 field.                                  */
84376   #define UICR_DPPI_GLOBAL_CH_OWN_CH11_NotOwn (0x1UL) /*!< Do not own the channel 11                                           */
84377   #define UICR_DPPI_GLOBAL_CH_OWN_CH11_Own (0x0UL)   /*!< Own the channel 11                                                   */
84378 
84379 /* CH12 @Bit 12 : Channel number */
84380   #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Pos (12UL)    /*!< Position of CH12 field.                                              */
84381   #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH12_Pos) /*!< Bit mask of CH12 field.            */
84382   #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Min (0x0UL)   /*!< Min enumerator value of CH12 field.                                  */
84383   #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Max (0x1UL)   /*!< Max enumerator value of CH12 field.                                  */
84384   #define UICR_DPPI_GLOBAL_CH_OWN_CH12_NotOwn (0x1UL) /*!< Do not own the channel 12                                           */
84385   #define UICR_DPPI_GLOBAL_CH_OWN_CH12_Own (0x0UL)   /*!< Own the channel 12                                                   */
84386 
84387 /* CH13 @Bit 13 : Channel number */
84388   #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Pos (13UL)    /*!< Position of CH13 field.                                              */
84389   #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH13_Pos) /*!< Bit mask of CH13 field.            */
84390   #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Min (0x0UL)   /*!< Min enumerator value of CH13 field.                                  */
84391   #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Max (0x1UL)   /*!< Max enumerator value of CH13 field.                                  */
84392   #define UICR_DPPI_GLOBAL_CH_OWN_CH13_NotOwn (0x1UL) /*!< Do not own the channel 13                                           */
84393   #define UICR_DPPI_GLOBAL_CH_OWN_CH13_Own (0x0UL)   /*!< Own the channel 13                                                   */
84394 
84395 /* CH14 @Bit 14 : Channel number */
84396   #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Pos (14UL)    /*!< Position of CH14 field.                                              */
84397   #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH14_Pos) /*!< Bit mask of CH14 field.            */
84398   #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Min (0x0UL)   /*!< Min enumerator value of CH14 field.                                  */
84399   #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Max (0x1UL)   /*!< Max enumerator value of CH14 field.                                  */
84400   #define UICR_DPPI_GLOBAL_CH_OWN_CH14_NotOwn (0x1UL) /*!< Do not own the channel 14                                           */
84401   #define UICR_DPPI_GLOBAL_CH_OWN_CH14_Own (0x0UL)   /*!< Own the channel 14                                                   */
84402 
84403 /* CH15 @Bit 15 : Channel number */
84404   #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Pos (15UL)    /*!< Position of CH15 field.                                              */
84405   #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH15_Pos) /*!< Bit mask of CH15 field.            */
84406   #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Min (0x0UL)   /*!< Min enumerator value of CH15 field.                                  */
84407   #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Max (0x1UL)   /*!< Max enumerator value of CH15 field.                                  */
84408   #define UICR_DPPI_GLOBAL_CH_OWN_CH15_NotOwn (0x1UL) /*!< Do not own the channel 15                                           */
84409   #define UICR_DPPI_GLOBAL_CH_OWN_CH15_Own (0x0UL)   /*!< Own the channel 15                                                   */
84410 
84411 /* CH16 @Bit 16 : Channel number */
84412   #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Pos (16UL)    /*!< Position of CH16 field.                                              */
84413   #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH16_Pos) /*!< Bit mask of CH16 field.            */
84414   #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Min (0x0UL)   /*!< Min enumerator value of CH16 field.                                  */
84415   #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Max (0x1UL)   /*!< Max enumerator value of CH16 field.                                  */
84416   #define UICR_DPPI_GLOBAL_CH_OWN_CH16_NotOwn (0x1UL) /*!< Do not own the channel 16                                           */
84417   #define UICR_DPPI_GLOBAL_CH_OWN_CH16_Own (0x0UL)   /*!< Own the channel 16                                                   */
84418 
84419 /* CH17 @Bit 17 : Channel number */
84420   #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Pos (17UL)    /*!< Position of CH17 field.                                              */
84421   #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH17_Pos) /*!< Bit mask of CH17 field.            */
84422   #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Min (0x0UL)   /*!< Min enumerator value of CH17 field.                                  */
84423   #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Max (0x1UL)   /*!< Max enumerator value of CH17 field.                                  */
84424   #define UICR_DPPI_GLOBAL_CH_OWN_CH17_NotOwn (0x1UL) /*!< Do not own the channel 17                                           */
84425   #define UICR_DPPI_GLOBAL_CH_OWN_CH17_Own (0x0UL)   /*!< Own the channel 17                                                   */
84426 
84427 /* CH18 @Bit 18 : Channel number */
84428   #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Pos (18UL)    /*!< Position of CH18 field.                                              */
84429   #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH18_Pos) /*!< Bit mask of CH18 field.            */
84430   #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Min (0x0UL)   /*!< Min enumerator value of CH18 field.                                  */
84431   #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Max (0x1UL)   /*!< Max enumerator value of CH18 field.                                  */
84432   #define UICR_DPPI_GLOBAL_CH_OWN_CH18_NotOwn (0x1UL) /*!< Do not own the channel 18                                           */
84433   #define UICR_DPPI_GLOBAL_CH_OWN_CH18_Own (0x0UL)   /*!< Own the channel 18                                                   */
84434 
84435 /* CH19 @Bit 19 : Channel number */
84436   #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Pos (19UL)    /*!< Position of CH19 field.                                              */
84437   #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH19_Pos) /*!< Bit mask of CH19 field.            */
84438   #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Min (0x0UL)   /*!< Min enumerator value of CH19 field.                                  */
84439   #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Max (0x1UL)   /*!< Max enumerator value of CH19 field.                                  */
84440   #define UICR_DPPI_GLOBAL_CH_OWN_CH19_NotOwn (0x1UL) /*!< Do not own the channel 19                                           */
84441   #define UICR_DPPI_GLOBAL_CH_OWN_CH19_Own (0x0UL)   /*!< Own the channel 19                                                   */
84442 
84443 /* CH20 @Bit 20 : Channel number */
84444   #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Pos (20UL)    /*!< Position of CH20 field.                                              */
84445   #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH20_Pos) /*!< Bit mask of CH20 field.            */
84446   #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Min (0x0UL)   /*!< Min enumerator value of CH20 field.                                  */
84447   #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Max (0x1UL)   /*!< Max enumerator value of CH20 field.                                  */
84448   #define UICR_DPPI_GLOBAL_CH_OWN_CH20_NotOwn (0x1UL) /*!< Do not own the channel 20                                           */
84449   #define UICR_DPPI_GLOBAL_CH_OWN_CH20_Own (0x0UL)   /*!< Own the channel 20                                                   */
84450 
84451 /* CH21 @Bit 21 : Channel number */
84452   #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Pos (21UL)    /*!< Position of CH21 field.                                              */
84453   #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH21_Pos) /*!< Bit mask of CH21 field.            */
84454   #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Min (0x0UL)   /*!< Min enumerator value of CH21 field.                                  */
84455   #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Max (0x1UL)   /*!< Max enumerator value of CH21 field.                                  */
84456   #define UICR_DPPI_GLOBAL_CH_OWN_CH21_NotOwn (0x1UL) /*!< Do not own the channel 21                                           */
84457   #define UICR_DPPI_GLOBAL_CH_OWN_CH21_Own (0x0UL)   /*!< Own the channel 21                                                   */
84458 
84459 /* CH22 @Bit 22 : Channel number */
84460   #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Pos (22UL)    /*!< Position of CH22 field.                                              */
84461   #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH22_Pos) /*!< Bit mask of CH22 field.            */
84462   #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Min (0x0UL)   /*!< Min enumerator value of CH22 field.                                  */
84463   #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Max (0x1UL)   /*!< Max enumerator value of CH22 field.                                  */
84464   #define UICR_DPPI_GLOBAL_CH_OWN_CH22_NotOwn (0x1UL) /*!< Do not own the channel 22                                           */
84465   #define UICR_DPPI_GLOBAL_CH_OWN_CH22_Own (0x0UL)   /*!< Own the channel 22                                                   */
84466 
84467 /* CH23 @Bit 23 : Channel number */
84468   #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Pos (23UL)    /*!< Position of CH23 field.                                              */
84469   #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH23_Pos) /*!< Bit mask of CH23 field.            */
84470   #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Min (0x0UL)   /*!< Min enumerator value of CH23 field.                                  */
84471   #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Max (0x1UL)   /*!< Max enumerator value of CH23 field.                                  */
84472   #define UICR_DPPI_GLOBAL_CH_OWN_CH23_NotOwn (0x1UL) /*!< Do not own the channel 23                                           */
84473   #define UICR_DPPI_GLOBAL_CH_OWN_CH23_Own (0x0UL)   /*!< Own the channel 23                                                   */
84474 
84475 /* CH24 @Bit 24 : Channel number */
84476   #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Pos (24UL)    /*!< Position of CH24 field.                                              */
84477   #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH24_Pos) /*!< Bit mask of CH24 field.            */
84478   #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Min (0x0UL)   /*!< Min enumerator value of CH24 field.                                  */
84479   #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Max (0x1UL)   /*!< Max enumerator value of CH24 field.                                  */
84480   #define UICR_DPPI_GLOBAL_CH_OWN_CH24_NotOwn (0x1UL) /*!< Do not own the channel 24                                           */
84481   #define UICR_DPPI_GLOBAL_CH_OWN_CH24_Own (0x0UL)   /*!< Own the channel 24                                                   */
84482 
84483 /* CH25 @Bit 25 : Channel number */
84484   #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Pos (25UL)    /*!< Position of CH25 field.                                              */
84485   #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH25_Pos) /*!< Bit mask of CH25 field.            */
84486   #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Min (0x0UL)   /*!< Min enumerator value of CH25 field.                                  */
84487   #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Max (0x1UL)   /*!< Max enumerator value of CH25 field.                                  */
84488   #define UICR_DPPI_GLOBAL_CH_OWN_CH25_NotOwn (0x1UL) /*!< Do not own the channel 25                                           */
84489   #define UICR_DPPI_GLOBAL_CH_OWN_CH25_Own (0x0UL)   /*!< Own the channel 25                                                   */
84490 
84491 /* CH26 @Bit 26 : Channel number */
84492   #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Pos (26UL)    /*!< Position of CH26 field.                                              */
84493   #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH26_Pos) /*!< Bit mask of CH26 field.            */
84494   #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Min (0x0UL)   /*!< Min enumerator value of CH26 field.                                  */
84495   #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Max (0x1UL)   /*!< Max enumerator value of CH26 field.                                  */
84496   #define UICR_DPPI_GLOBAL_CH_OWN_CH26_NotOwn (0x1UL) /*!< Do not own the channel 26                                           */
84497   #define UICR_DPPI_GLOBAL_CH_OWN_CH26_Own (0x0UL)   /*!< Own the channel 26                                                   */
84498 
84499 /* CH27 @Bit 27 : Channel number */
84500   #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Pos (27UL)    /*!< Position of CH27 field.                                              */
84501   #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH27_Pos) /*!< Bit mask of CH27 field.            */
84502   #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Min (0x0UL)   /*!< Min enumerator value of CH27 field.                                  */
84503   #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Max (0x1UL)   /*!< Max enumerator value of CH27 field.                                  */
84504   #define UICR_DPPI_GLOBAL_CH_OWN_CH27_NotOwn (0x1UL) /*!< Do not own the channel 27                                           */
84505   #define UICR_DPPI_GLOBAL_CH_OWN_CH27_Own (0x0UL)   /*!< Own the channel 27                                                   */
84506 
84507 /* CH28 @Bit 28 : Channel number */
84508   #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Pos (28UL)    /*!< Position of CH28 field.                                              */
84509   #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH28_Pos) /*!< Bit mask of CH28 field.            */
84510   #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Min (0x0UL)   /*!< Min enumerator value of CH28 field.                                  */
84511   #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Max (0x1UL)   /*!< Max enumerator value of CH28 field.                                  */
84512   #define UICR_DPPI_GLOBAL_CH_OWN_CH28_NotOwn (0x1UL) /*!< Do not own the channel 28                                           */
84513   #define UICR_DPPI_GLOBAL_CH_OWN_CH28_Own (0x0UL)   /*!< Own the channel 28                                                   */
84514 
84515 /* CH29 @Bit 29 : Channel number */
84516   #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Pos (29UL)    /*!< Position of CH29 field.                                              */
84517   #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH29_Pos) /*!< Bit mask of CH29 field.            */
84518   #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Min (0x0UL)   /*!< Min enumerator value of CH29 field.                                  */
84519   #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Max (0x1UL)   /*!< Max enumerator value of CH29 field.                                  */
84520   #define UICR_DPPI_GLOBAL_CH_OWN_CH29_NotOwn (0x1UL) /*!< Do not own the channel 29                                           */
84521   #define UICR_DPPI_GLOBAL_CH_OWN_CH29_Own (0x0UL)   /*!< Own the channel 29                                                   */
84522 
84523 /* CH30 @Bit 30 : Channel number */
84524   #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Pos (30UL)    /*!< Position of CH30 field.                                              */
84525   #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH30_Pos) /*!< Bit mask of CH30 field.            */
84526   #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Min (0x0UL)   /*!< Min enumerator value of CH30 field.                                  */
84527   #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Max (0x1UL)   /*!< Max enumerator value of CH30 field.                                  */
84528   #define UICR_DPPI_GLOBAL_CH_OWN_CH30_NotOwn (0x1UL) /*!< Do not own the channel 30                                           */
84529   #define UICR_DPPI_GLOBAL_CH_OWN_CH30_Own (0x0UL)   /*!< Own the channel 30                                                   */
84530 
84531 /* CH31 @Bit 31 : Channel number */
84532   #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Pos (31UL)    /*!< Position of CH31 field.                                              */
84533   #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_OWN_CH31_Pos) /*!< Bit mask of CH31 field.            */
84534   #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Min (0x0UL)   /*!< Min enumerator value of CH31 field.                                  */
84535   #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Max (0x1UL)   /*!< Max enumerator value of CH31 field.                                  */
84536   #define UICR_DPPI_GLOBAL_CH_OWN_CH31_NotOwn (0x1UL) /*!< Do not own the channel 31                                           */
84537   #define UICR_DPPI_GLOBAL_CH_OWN_CH31_Own (0x0UL)   /*!< Own the channel 31                                                   */
84538 
84539 
84540 /* UICR_DPPI_GLOBAL_CH_SECURE: Request permission for the channels of DPPI[n] in Global domain */
84541   #define UICR_DPPI_GLOBAL_CH_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                            */
84542 
84543 /* CH0 @Bit 0 : Channel number */
84544   #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Pos (0UL)   /*!< Position of CH0 field.                                               */
84545   #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH0_Pos) /*!< Bit mask of CH0 field.         */
84546   #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Min (0x0UL) /*!< Min enumerator value of CH0 field.                                   */
84547   #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Max (0x1UL) /*!< Max enumerator value of CH0 field.                                   */
84548   #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_Secure (0x1UL) /*!< The channel 0 is secure                                           */
84549   #define UICR_DPPI_GLOBAL_CH_SECURE_CH0_NonSecure (0x0UL) /*!< The channel 0 is non-secure                                    */
84550 
84551 /* CH1 @Bit 1 : Channel number */
84552   #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Pos (1UL)   /*!< Position of CH1 field.                                               */
84553   #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH1_Pos) /*!< Bit mask of CH1 field.         */
84554   #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Min (0x0UL) /*!< Min enumerator value of CH1 field.                                   */
84555   #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Max (0x1UL) /*!< Max enumerator value of CH1 field.                                   */
84556   #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_Secure (0x1UL) /*!< The channel 1 is secure                                           */
84557   #define UICR_DPPI_GLOBAL_CH_SECURE_CH1_NonSecure (0x0UL) /*!< The channel 1 is non-secure                                    */
84558 
84559 /* CH2 @Bit 2 : Channel number */
84560   #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Pos (2UL)   /*!< Position of CH2 field.                                               */
84561   #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH2_Pos) /*!< Bit mask of CH2 field.         */
84562   #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Min (0x0UL) /*!< Min enumerator value of CH2 field.                                   */
84563   #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Max (0x1UL) /*!< Max enumerator value of CH2 field.                                   */
84564   #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_Secure (0x1UL) /*!< The channel 2 is secure                                           */
84565   #define UICR_DPPI_GLOBAL_CH_SECURE_CH2_NonSecure (0x0UL) /*!< The channel 2 is non-secure                                    */
84566 
84567 /* CH3 @Bit 3 : Channel number */
84568   #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Pos (3UL)   /*!< Position of CH3 field.                                               */
84569   #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH3_Pos) /*!< Bit mask of CH3 field.         */
84570   #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Min (0x0UL) /*!< Min enumerator value of CH3 field.                                   */
84571   #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Max (0x1UL) /*!< Max enumerator value of CH3 field.                                   */
84572   #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_Secure (0x1UL) /*!< The channel 3 is secure                                           */
84573   #define UICR_DPPI_GLOBAL_CH_SECURE_CH3_NonSecure (0x0UL) /*!< The channel 3 is non-secure                                    */
84574 
84575 /* CH4 @Bit 4 : Channel number */
84576   #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Pos (4UL)   /*!< Position of CH4 field.                                               */
84577   #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH4_Pos) /*!< Bit mask of CH4 field.         */
84578   #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Min (0x0UL) /*!< Min enumerator value of CH4 field.                                   */
84579   #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Max (0x1UL) /*!< Max enumerator value of CH4 field.                                   */
84580   #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_Secure (0x1UL) /*!< The channel 4 is secure                                           */
84581   #define UICR_DPPI_GLOBAL_CH_SECURE_CH4_NonSecure (0x0UL) /*!< The channel 4 is non-secure                                    */
84582 
84583 /* CH5 @Bit 5 : Channel number */
84584   #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Pos (5UL)   /*!< Position of CH5 field.                                               */
84585   #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH5_Pos) /*!< Bit mask of CH5 field.         */
84586   #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Min (0x0UL) /*!< Min enumerator value of CH5 field.                                   */
84587   #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Max (0x1UL) /*!< Max enumerator value of CH5 field.                                   */
84588   #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_Secure (0x1UL) /*!< The channel 5 is secure                                           */
84589   #define UICR_DPPI_GLOBAL_CH_SECURE_CH5_NonSecure (0x0UL) /*!< The channel 5 is non-secure                                    */
84590 
84591 /* CH6 @Bit 6 : Channel number */
84592   #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Pos (6UL)   /*!< Position of CH6 field.                                               */
84593   #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH6_Pos) /*!< Bit mask of CH6 field.         */
84594   #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Min (0x0UL) /*!< Min enumerator value of CH6 field.                                   */
84595   #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Max (0x1UL) /*!< Max enumerator value of CH6 field.                                   */
84596   #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_Secure (0x1UL) /*!< The channel 6 is secure                                           */
84597   #define UICR_DPPI_GLOBAL_CH_SECURE_CH6_NonSecure (0x0UL) /*!< The channel 6 is non-secure                                    */
84598 
84599 /* CH7 @Bit 7 : Channel number */
84600   #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Pos (7UL)   /*!< Position of CH7 field.                                               */
84601   #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH7_Pos) /*!< Bit mask of CH7 field.         */
84602   #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Min (0x0UL) /*!< Min enumerator value of CH7 field.                                   */
84603   #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Max (0x1UL) /*!< Max enumerator value of CH7 field.                                   */
84604   #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_Secure (0x1UL) /*!< The channel 7 is secure                                           */
84605   #define UICR_DPPI_GLOBAL_CH_SECURE_CH7_NonSecure (0x0UL) /*!< The channel 7 is non-secure                                    */
84606 
84607 /* CH8 @Bit 8 : Channel number */
84608   #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Pos (8UL)   /*!< Position of CH8 field.                                               */
84609   #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH8_Pos) /*!< Bit mask of CH8 field.         */
84610   #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Min (0x0UL) /*!< Min enumerator value of CH8 field.                                   */
84611   #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Max (0x1UL) /*!< Max enumerator value of CH8 field.                                   */
84612   #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_Secure (0x1UL) /*!< The channel 8 is secure                                           */
84613   #define UICR_DPPI_GLOBAL_CH_SECURE_CH8_NonSecure (0x0UL) /*!< The channel 8 is non-secure                                    */
84614 
84615 /* CH9 @Bit 9 : Channel number */
84616   #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Pos (9UL)   /*!< Position of CH9 field.                                               */
84617   #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH9_Pos) /*!< Bit mask of CH9 field.         */
84618   #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Min (0x0UL) /*!< Min enumerator value of CH9 field.                                   */
84619   #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Max (0x1UL) /*!< Max enumerator value of CH9 field.                                   */
84620   #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_Secure (0x1UL) /*!< The channel 9 is secure                                           */
84621   #define UICR_DPPI_GLOBAL_CH_SECURE_CH9_NonSecure (0x0UL) /*!< The channel 9 is non-secure                                    */
84622 
84623 /* CH10 @Bit 10 : Channel number */
84624   #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Pos (10UL) /*!< Position of CH10 field.                                              */
84625   #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH10_Pos) /*!< Bit mask of CH10 field.      */
84626   #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Min (0x0UL) /*!< Min enumerator value of CH10 field.                                 */
84627   #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Max (0x1UL) /*!< Max enumerator value of CH10 field.                                 */
84628   #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_Secure (0x1UL) /*!< The channel 10 is secure                                         */
84629   #define UICR_DPPI_GLOBAL_CH_SECURE_CH10_NonSecure (0x0UL) /*!< The channel 10 is non-secure                                  */
84630 
84631 /* CH11 @Bit 11 : Channel number */
84632   #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Pos (11UL) /*!< Position of CH11 field.                                              */
84633   #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH11_Pos) /*!< Bit mask of CH11 field.      */
84634   #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Min (0x0UL) /*!< Min enumerator value of CH11 field.                                 */
84635   #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Max (0x1UL) /*!< Max enumerator value of CH11 field.                                 */
84636   #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_Secure (0x1UL) /*!< The channel 11 is secure                                         */
84637   #define UICR_DPPI_GLOBAL_CH_SECURE_CH11_NonSecure (0x0UL) /*!< The channel 11 is non-secure                                  */
84638 
84639 /* CH12 @Bit 12 : Channel number */
84640   #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Pos (12UL) /*!< Position of CH12 field.                                              */
84641   #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH12_Pos) /*!< Bit mask of CH12 field.      */
84642   #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Min (0x0UL) /*!< Min enumerator value of CH12 field.                                 */
84643   #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Max (0x1UL) /*!< Max enumerator value of CH12 field.                                 */
84644   #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_Secure (0x1UL) /*!< The channel 12 is secure                                         */
84645   #define UICR_DPPI_GLOBAL_CH_SECURE_CH12_NonSecure (0x0UL) /*!< The channel 12 is non-secure                                  */
84646 
84647 /* CH13 @Bit 13 : Channel number */
84648   #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Pos (13UL) /*!< Position of CH13 field.                                              */
84649   #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH13_Pos) /*!< Bit mask of CH13 field.      */
84650   #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Min (0x0UL) /*!< Min enumerator value of CH13 field.                                 */
84651   #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Max (0x1UL) /*!< Max enumerator value of CH13 field.                                 */
84652   #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_Secure (0x1UL) /*!< The channel 13 is secure                                         */
84653   #define UICR_DPPI_GLOBAL_CH_SECURE_CH13_NonSecure (0x0UL) /*!< The channel 13 is non-secure                                  */
84654 
84655 /* CH14 @Bit 14 : Channel number */
84656   #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Pos (14UL) /*!< Position of CH14 field.                                              */
84657   #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH14_Pos) /*!< Bit mask of CH14 field.      */
84658   #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Min (0x0UL) /*!< Min enumerator value of CH14 field.                                 */
84659   #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Max (0x1UL) /*!< Max enumerator value of CH14 field.                                 */
84660   #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_Secure (0x1UL) /*!< The channel 14 is secure                                         */
84661   #define UICR_DPPI_GLOBAL_CH_SECURE_CH14_NonSecure (0x0UL) /*!< The channel 14 is non-secure                                  */
84662 
84663 /* CH15 @Bit 15 : Channel number */
84664   #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Pos (15UL) /*!< Position of CH15 field.                                              */
84665   #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH15_Pos) /*!< Bit mask of CH15 field.      */
84666   #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Min (0x0UL) /*!< Min enumerator value of CH15 field.                                 */
84667   #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Max (0x1UL) /*!< Max enumerator value of CH15 field.                                 */
84668   #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_Secure (0x1UL) /*!< The channel 15 is secure                                         */
84669   #define UICR_DPPI_GLOBAL_CH_SECURE_CH15_NonSecure (0x0UL) /*!< The channel 15 is non-secure                                  */
84670 
84671 /* CH16 @Bit 16 : Channel number */
84672   #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Pos (16UL) /*!< Position of CH16 field.                                              */
84673   #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH16_Pos) /*!< Bit mask of CH16 field.      */
84674   #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Min (0x0UL) /*!< Min enumerator value of CH16 field.                                 */
84675   #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Max (0x1UL) /*!< Max enumerator value of CH16 field.                                 */
84676   #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_Secure (0x1UL) /*!< The channel 16 is secure                                         */
84677   #define UICR_DPPI_GLOBAL_CH_SECURE_CH16_NonSecure (0x0UL) /*!< The channel 16 is non-secure                                  */
84678 
84679 /* CH17 @Bit 17 : Channel number */
84680   #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Pos (17UL) /*!< Position of CH17 field.                                              */
84681   #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH17_Pos) /*!< Bit mask of CH17 field.      */
84682   #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Min (0x0UL) /*!< Min enumerator value of CH17 field.                                 */
84683   #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Max (0x1UL) /*!< Max enumerator value of CH17 field.                                 */
84684   #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_Secure (0x1UL) /*!< The channel 17 is secure                                         */
84685   #define UICR_DPPI_GLOBAL_CH_SECURE_CH17_NonSecure (0x0UL) /*!< The channel 17 is non-secure                                  */
84686 
84687 /* CH18 @Bit 18 : Channel number */
84688   #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Pos (18UL) /*!< Position of CH18 field.                                              */
84689   #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH18_Pos) /*!< Bit mask of CH18 field.      */
84690   #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Min (0x0UL) /*!< Min enumerator value of CH18 field.                                 */
84691   #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Max (0x1UL) /*!< Max enumerator value of CH18 field.                                 */
84692   #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_Secure (0x1UL) /*!< The channel 18 is secure                                         */
84693   #define UICR_DPPI_GLOBAL_CH_SECURE_CH18_NonSecure (0x0UL) /*!< The channel 18 is non-secure                                  */
84694 
84695 /* CH19 @Bit 19 : Channel number */
84696   #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Pos (19UL) /*!< Position of CH19 field.                                              */
84697   #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH19_Pos) /*!< Bit mask of CH19 field.      */
84698   #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Min (0x0UL) /*!< Min enumerator value of CH19 field.                                 */
84699   #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Max (0x1UL) /*!< Max enumerator value of CH19 field.                                 */
84700   #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_Secure (0x1UL) /*!< The channel 19 is secure                                         */
84701   #define UICR_DPPI_GLOBAL_CH_SECURE_CH19_NonSecure (0x0UL) /*!< The channel 19 is non-secure                                  */
84702 
84703 /* CH20 @Bit 20 : Channel number */
84704   #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Pos (20UL) /*!< Position of CH20 field.                                              */
84705   #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH20_Pos) /*!< Bit mask of CH20 field.      */
84706   #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Min (0x0UL) /*!< Min enumerator value of CH20 field.                                 */
84707   #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Max (0x1UL) /*!< Max enumerator value of CH20 field.                                 */
84708   #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_Secure (0x1UL) /*!< The channel 20 is secure                                         */
84709   #define UICR_DPPI_GLOBAL_CH_SECURE_CH20_NonSecure (0x0UL) /*!< The channel 20 is non-secure                                  */
84710 
84711 /* CH21 @Bit 21 : Channel number */
84712   #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Pos (21UL) /*!< Position of CH21 field.                                              */
84713   #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH21_Pos) /*!< Bit mask of CH21 field.      */
84714   #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Min (0x0UL) /*!< Min enumerator value of CH21 field.                                 */
84715   #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Max (0x1UL) /*!< Max enumerator value of CH21 field.                                 */
84716   #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_Secure (0x1UL) /*!< The channel 21 is secure                                         */
84717   #define UICR_DPPI_GLOBAL_CH_SECURE_CH21_NonSecure (0x0UL) /*!< The channel 21 is non-secure                                  */
84718 
84719 /* CH22 @Bit 22 : Channel number */
84720   #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Pos (22UL) /*!< Position of CH22 field.                                              */
84721   #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH22_Pos) /*!< Bit mask of CH22 field.      */
84722   #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Min (0x0UL) /*!< Min enumerator value of CH22 field.                                 */
84723   #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Max (0x1UL) /*!< Max enumerator value of CH22 field.                                 */
84724   #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_Secure (0x1UL) /*!< The channel 22 is secure                                         */
84725   #define UICR_DPPI_GLOBAL_CH_SECURE_CH22_NonSecure (0x0UL) /*!< The channel 22 is non-secure                                  */
84726 
84727 /* CH23 @Bit 23 : Channel number */
84728   #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Pos (23UL) /*!< Position of CH23 field.                                              */
84729   #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH23_Pos) /*!< Bit mask of CH23 field.      */
84730   #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Min (0x0UL) /*!< Min enumerator value of CH23 field.                                 */
84731   #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Max (0x1UL) /*!< Max enumerator value of CH23 field.                                 */
84732   #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_Secure (0x1UL) /*!< The channel 23 is secure                                         */
84733   #define UICR_DPPI_GLOBAL_CH_SECURE_CH23_NonSecure (0x0UL) /*!< The channel 23 is non-secure                                  */
84734 
84735 /* CH24 @Bit 24 : Channel number */
84736   #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Pos (24UL) /*!< Position of CH24 field.                                              */
84737   #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH24_Pos) /*!< Bit mask of CH24 field.      */
84738   #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Min (0x0UL) /*!< Min enumerator value of CH24 field.                                 */
84739   #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Max (0x1UL) /*!< Max enumerator value of CH24 field.                                 */
84740   #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_Secure (0x1UL) /*!< The channel 24 is secure                                         */
84741   #define UICR_DPPI_GLOBAL_CH_SECURE_CH24_NonSecure (0x0UL) /*!< The channel 24 is non-secure                                  */
84742 
84743 /* CH25 @Bit 25 : Channel number */
84744   #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Pos (25UL) /*!< Position of CH25 field.                                              */
84745   #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH25_Pos) /*!< Bit mask of CH25 field.      */
84746   #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Min (0x0UL) /*!< Min enumerator value of CH25 field.                                 */
84747   #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Max (0x1UL) /*!< Max enumerator value of CH25 field.                                 */
84748   #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_Secure (0x1UL) /*!< The channel 25 is secure                                         */
84749   #define UICR_DPPI_GLOBAL_CH_SECURE_CH25_NonSecure (0x0UL) /*!< The channel 25 is non-secure                                  */
84750 
84751 /* CH26 @Bit 26 : Channel number */
84752   #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Pos (26UL) /*!< Position of CH26 field.                                              */
84753   #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH26_Pos) /*!< Bit mask of CH26 field.      */
84754   #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Min (0x0UL) /*!< Min enumerator value of CH26 field.                                 */
84755   #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Max (0x1UL) /*!< Max enumerator value of CH26 field.                                 */
84756   #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_Secure (0x1UL) /*!< The channel 26 is secure                                         */
84757   #define UICR_DPPI_GLOBAL_CH_SECURE_CH26_NonSecure (0x0UL) /*!< The channel 26 is non-secure                                  */
84758 
84759 /* CH27 @Bit 27 : Channel number */
84760   #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Pos (27UL) /*!< Position of CH27 field.                                              */
84761   #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH27_Pos) /*!< Bit mask of CH27 field.      */
84762   #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Min (0x0UL) /*!< Min enumerator value of CH27 field.                                 */
84763   #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Max (0x1UL) /*!< Max enumerator value of CH27 field.                                 */
84764   #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_Secure (0x1UL) /*!< The channel 27 is secure                                         */
84765   #define UICR_DPPI_GLOBAL_CH_SECURE_CH27_NonSecure (0x0UL) /*!< The channel 27 is non-secure                                  */
84766 
84767 /* CH28 @Bit 28 : Channel number */
84768   #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Pos (28UL) /*!< Position of CH28 field.                                              */
84769   #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH28_Pos) /*!< Bit mask of CH28 field.      */
84770   #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Min (0x0UL) /*!< Min enumerator value of CH28 field.                                 */
84771   #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Max (0x1UL) /*!< Max enumerator value of CH28 field.                                 */
84772   #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_Secure (0x1UL) /*!< The channel 28 is secure                                         */
84773   #define UICR_DPPI_GLOBAL_CH_SECURE_CH28_NonSecure (0x0UL) /*!< The channel 28 is non-secure                                  */
84774 
84775 /* CH29 @Bit 29 : Channel number */
84776   #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Pos (29UL) /*!< Position of CH29 field.                                              */
84777   #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH29_Pos) /*!< Bit mask of CH29 field.      */
84778   #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Min (0x0UL) /*!< Min enumerator value of CH29 field.                                 */
84779   #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Max (0x1UL) /*!< Max enumerator value of CH29 field.                                 */
84780   #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_Secure (0x1UL) /*!< The channel 29 is secure                                         */
84781   #define UICR_DPPI_GLOBAL_CH_SECURE_CH29_NonSecure (0x0UL) /*!< The channel 29 is non-secure                                  */
84782 
84783 /* CH30 @Bit 30 : Channel number */
84784   #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Pos (30UL) /*!< Position of CH30 field.                                              */
84785   #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH30_Pos) /*!< Bit mask of CH30 field.      */
84786   #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Min (0x0UL) /*!< Min enumerator value of CH30 field.                                 */
84787   #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Max (0x1UL) /*!< Max enumerator value of CH30 field.                                 */
84788   #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_Secure (0x1UL) /*!< The channel 30 is secure                                         */
84789   #define UICR_DPPI_GLOBAL_CH_SECURE_CH30_NonSecure (0x0UL) /*!< The channel 30 is non-secure                                  */
84790 
84791 /* CH31 @Bit 31 : Channel number */
84792   #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Pos (31UL) /*!< Position of CH31 field.                                              */
84793   #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Msk (0x1UL << UICR_DPPI_GLOBAL_CH_SECURE_CH31_Pos) /*!< Bit mask of CH31 field.      */
84794   #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Min (0x0UL) /*!< Min enumerator value of CH31 field.                                 */
84795   #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Max (0x1UL) /*!< Max enumerator value of CH31 field.                                 */
84796   #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_Secure (0x1UL) /*!< The channel 31 is secure                                         */
84797   #define UICR_DPPI_GLOBAL_CH_SECURE_CH31_NonSecure (0x0UL) /*!< The channel 31 is non-secure                                  */
84798 
84799 
84800 
84801 /* =============================================== Struct UICR_DPPI_GLOBAL_CHG =============================================== */
84802 /**
84803   * @brief CHG [UICR_DPPI_GLOBAL_CHG] (unspecified)
84804   */
84805 typedef struct {
84806   __IOM uint32_t  OWN;                               /*!< (@ 0x00000000) Request ownership of the channel groups of DPPI[n] in
84807                                                                          Global domain*/
84808   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Request permission for the channel groups of DPPI[n] in
84809                                                                          Global domain*/
84810 } NRF_UICR_DPPI_GLOBAL_CHG_Type;                     /*!< Size = 8 (0x008)                                                     */
84811 
84812 /* UICR_DPPI_GLOBAL_CHG_OWN: Request ownership of the channel groups of DPPI[n] in Global domain */
84813   #define UICR_DPPI_GLOBAL_CHG_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register.                                 */
84814 
84815 /* CHG0 @Bit 0 : Channel group number */
84816   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Pos (0UL)    /*!< Position of CHG0 field.                                              */
84817   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Pos) /*!< Bit mask of CHG0 field.          */
84818   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Min (0x0UL)  /*!< Min enumerator value of CHG0 field.                                  */
84819   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Max (0x1UL)  /*!< Max enumerator value of CHG0 field.                                  */
84820   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_NotOwn (0x1UL) /*!< Do not own the channel group 0                                     */
84821   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG0_Own (0x0UL)  /*!< Own the channel group 0                                              */
84822 
84823 /* CHG1 @Bit 1 : Channel group number */
84824   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Pos (1UL)    /*!< Position of CHG1 field.                                              */
84825   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Pos) /*!< Bit mask of CHG1 field.          */
84826   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Min (0x0UL)  /*!< Min enumerator value of CHG1 field.                                  */
84827   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Max (0x1UL)  /*!< Max enumerator value of CHG1 field.                                  */
84828   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_NotOwn (0x1UL) /*!< Do not own the channel group 1                                     */
84829   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG1_Own (0x0UL)  /*!< Own the channel group 1                                              */
84830 
84831 /* CHG2 @Bit 2 : Channel group number */
84832   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Pos (2UL)    /*!< Position of CHG2 field.                                              */
84833   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Pos) /*!< Bit mask of CHG2 field.          */
84834   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Min (0x0UL)  /*!< Min enumerator value of CHG2 field.                                  */
84835   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Max (0x1UL)  /*!< Max enumerator value of CHG2 field.                                  */
84836   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_NotOwn (0x1UL) /*!< Do not own the channel group 2                                     */
84837   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG2_Own (0x0UL)  /*!< Own the channel group 2                                              */
84838 
84839 /* CHG3 @Bit 3 : Channel group number */
84840   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Pos (3UL)    /*!< Position of CHG3 field.                                              */
84841   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Pos) /*!< Bit mask of CHG3 field.          */
84842   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Min (0x0UL)  /*!< Min enumerator value of CHG3 field.                                  */
84843   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Max (0x1UL)  /*!< Max enumerator value of CHG3 field.                                  */
84844   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_NotOwn (0x1UL) /*!< Do not own the channel group 3                                     */
84845   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG3_Own (0x0UL)  /*!< Own the channel group 3                                              */
84846 
84847 /* CHG4 @Bit 4 : Channel group number */
84848   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Pos (4UL)    /*!< Position of CHG4 field.                                              */
84849   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Pos) /*!< Bit mask of CHG4 field.          */
84850   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Min (0x0UL)  /*!< Min enumerator value of CHG4 field.                                  */
84851   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Max (0x1UL)  /*!< Max enumerator value of CHG4 field.                                  */
84852   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_NotOwn (0x1UL) /*!< Do not own the channel group 4                                     */
84853   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG4_Own (0x0UL)  /*!< Own the channel group 4                                              */
84854 
84855 /* CHG5 @Bit 5 : Channel group number */
84856   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Pos (5UL)    /*!< Position of CHG5 field.                                              */
84857   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Pos) /*!< Bit mask of CHG5 field.          */
84858   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Min (0x0UL)  /*!< Min enumerator value of CHG5 field.                                  */
84859   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Max (0x1UL)  /*!< Max enumerator value of CHG5 field.                                  */
84860   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_NotOwn (0x1UL) /*!< Do not own the channel group 5                                     */
84861   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG5_Own (0x0UL)  /*!< Own the channel group 5                                              */
84862 
84863 /* CHG6 @Bit 6 : Channel group number */
84864   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Pos (6UL)    /*!< Position of CHG6 field.                                              */
84865   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Pos) /*!< Bit mask of CHG6 field.          */
84866   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Min (0x0UL)  /*!< Min enumerator value of CHG6 field.                                  */
84867   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Max (0x1UL)  /*!< Max enumerator value of CHG6 field.                                  */
84868   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_NotOwn (0x1UL) /*!< Do not own the channel group 6                                     */
84869   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG6_Own (0x0UL)  /*!< Own the channel group 6                                              */
84870 
84871 /* CHG7 @Bit 7 : Channel group number */
84872   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Pos (7UL)    /*!< Position of CHG7 field.                                              */
84873   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Pos) /*!< Bit mask of CHG7 field.          */
84874   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Min (0x0UL)  /*!< Min enumerator value of CHG7 field.                                  */
84875   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Max (0x1UL)  /*!< Max enumerator value of CHG7 field.                                  */
84876   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_NotOwn (0x1UL) /*!< Do not own the channel group 7                                     */
84877   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG7_Own (0x0UL)  /*!< Own the channel group 7                                              */
84878 
84879 /* CHG8 @Bit 8 : Channel group number */
84880   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Pos (8UL)    /*!< Position of CHG8 field.                                              */
84881   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Pos) /*!< Bit mask of CHG8 field.          */
84882   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Min (0x0UL)  /*!< Min enumerator value of CHG8 field.                                  */
84883   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Max (0x1UL)  /*!< Max enumerator value of CHG8 field.                                  */
84884   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_NotOwn (0x1UL) /*!< Do not own the channel group 8                                     */
84885   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG8_Own (0x0UL)  /*!< Own the channel group 8                                              */
84886 
84887 /* CHG9 @Bit 9 : Channel group number */
84888   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Pos (9UL)    /*!< Position of CHG9 field.                                              */
84889   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Pos) /*!< Bit mask of CHG9 field.          */
84890   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Min (0x0UL)  /*!< Min enumerator value of CHG9 field.                                  */
84891   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Max (0x1UL)  /*!< Max enumerator value of CHG9 field.                                  */
84892   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_NotOwn (0x1UL) /*!< Do not own the channel group 9                                     */
84893   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG9_Own (0x0UL)  /*!< Own the channel group 9                                              */
84894 
84895 /* CHG10 @Bit 10 : Channel group number */
84896   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Pos (10UL)  /*!< Position of CHG10 field.                                             */
84897   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Pos) /*!< Bit mask of CHG10 field.       */
84898   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Min (0x0UL) /*!< Min enumerator value of CHG10 field.                                 */
84899   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Max (0x1UL) /*!< Max enumerator value of CHG10 field.                                 */
84900   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_NotOwn (0x1UL) /*!< Do not own the channel group 10                                   */
84901   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG10_Own (0x0UL) /*!< Own the channel group 10                                             */
84902 
84903 /* CHG11 @Bit 11 : Channel group number */
84904   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Pos (11UL)  /*!< Position of CHG11 field.                                             */
84905   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Pos) /*!< Bit mask of CHG11 field.       */
84906   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Min (0x0UL) /*!< Min enumerator value of CHG11 field.                                 */
84907   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Max (0x1UL) /*!< Max enumerator value of CHG11 field.                                 */
84908   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_NotOwn (0x1UL) /*!< Do not own the channel group 11                                   */
84909   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG11_Own (0x0UL) /*!< Own the channel group 11                                             */
84910 
84911 /* CHG12 @Bit 12 : Channel group number */
84912   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Pos (12UL)  /*!< Position of CHG12 field.                                             */
84913   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Pos) /*!< Bit mask of CHG12 field.       */
84914   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Min (0x0UL) /*!< Min enumerator value of CHG12 field.                                 */
84915   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Max (0x1UL) /*!< Max enumerator value of CHG12 field.                                 */
84916   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_NotOwn (0x1UL) /*!< Do not own the channel group 12                                   */
84917   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG12_Own (0x0UL) /*!< Own the channel group 12                                             */
84918 
84919 /* CHG13 @Bit 13 : Channel group number */
84920   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Pos (13UL)  /*!< Position of CHG13 field.                                             */
84921   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Pos) /*!< Bit mask of CHG13 field.       */
84922   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Min (0x0UL) /*!< Min enumerator value of CHG13 field.                                 */
84923   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Max (0x1UL) /*!< Max enumerator value of CHG13 field.                                 */
84924   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_NotOwn (0x1UL) /*!< Do not own the channel group 13                                   */
84925   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG13_Own (0x0UL) /*!< Own the channel group 13                                             */
84926 
84927 /* CHG14 @Bit 14 : Channel group number */
84928   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Pos (14UL)  /*!< Position of CHG14 field.                                             */
84929   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Pos) /*!< Bit mask of CHG14 field.       */
84930   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Min (0x0UL) /*!< Min enumerator value of CHG14 field.                                 */
84931   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Max (0x1UL) /*!< Max enumerator value of CHG14 field.                                 */
84932   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_NotOwn (0x1UL) /*!< Do not own the channel group 14                                   */
84933   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG14_Own (0x0UL) /*!< Own the channel group 14                                             */
84934 
84935 /* CHG15 @Bit 15 : Channel group number */
84936   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Pos (15UL)  /*!< Position of CHG15 field.                                             */
84937   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Pos) /*!< Bit mask of CHG15 field.       */
84938   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Min (0x0UL) /*!< Min enumerator value of CHG15 field.                                 */
84939   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Max (0x1UL) /*!< Max enumerator value of CHG15 field.                                 */
84940   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_NotOwn (0x1UL) /*!< Do not own the channel group 15                                   */
84941   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG15_Own (0x0UL) /*!< Own the channel group 15                                             */
84942 
84943 /* CHG16 @Bit 16 : Channel group number */
84944   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Pos (16UL)  /*!< Position of CHG16 field.                                             */
84945   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Pos) /*!< Bit mask of CHG16 field.       */
84946   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Min (0x0UL) /*!< Min enumerator value of CHG16 field.                                 */
84947   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Max (0x1UL) /*!< Max enumerator value of CHG16 field.                                 */
84948   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_NotOwn (0x1UL) /*!< Do not own the channel group 16                                   */
84949   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG16_Own (0x0UL) /*!< Own the channel group 16                                             */
84950 
84951 /* CHG17 @Bit 17 : Channel group number */
84952   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Pos (17UL)  /*!< Position of CHG17 field.                                             */
84953   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Pos) /*!< Bit mask of CHG17 field.       */
84954   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Min (0x0UL) /*!< Min enumerator value of CHG17 field.                                 */
84955   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Max (0x1UL) /*!< Max enumerator value of CHG17 field.                                 */
84956   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_NotOwn (0x1UL) /*!< Do not own the channel group 17                                   */
84957   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG17_Own (0x0UL) /*!< Own the channel group 17                                             */
84958 
84959 /* CHG18 @Bit 18 : Channel group number */
84960   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Pos (18UL)  /*!< Position of CHG18 field.                                             */
84961   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Pos) /*!< Bit mask of CHG18 field.       */
84962   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Min (0x0UL) /*!< Min enumerator value of CHG18 field.                                 */
84963   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Max (0x1UL) /*!< Max enumerator value of CHG18 field.                                 */
84964   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_NotOwn (0x1UL) /*!< Do not own the channel group 18                                   */
84965   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG18_Own (0x0UL) /*!< Own the channel group 18                                             */
84966 
84967 /* CHG19 @Bit 19 : Channel group number */
84968   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Pos (19UL)  /*!< Position of CHG19 field.                                             */
84969   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Pos) /*!< Bit mask of CHG19 field.       */
84970   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Min (0x0UL) /*!< Min enumerator value of CHG19 field.                                 */
84971   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Max (0x1UL) /*!< Max enumerator value of CHG19 field.                                 */
84972   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_NotOwn (0x1UL) /*!< Do not own the channel group 19                                   */
84973   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG19_Own (0x0UL) /*!< Own the channel group 19                                             */
84974 
84975 /* CHG20 @Bit 20 : Channel group number */
84976   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Pos (20UL)  /*!< Position of CHG20 field.                                             */
84977   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Pos) /*!< Bit mask of CHG20 field.       */
84978   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Min (0x0UL) /*!< Min enumerator value of CHG20 field.                                 */
84979   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Max (0x1UL) /*!< Max enumerator value of CHG20 field.                                 */
84980   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_NotOwn (0x1UL) /*!< Do not own the channel group 20                                   */
84981   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG20_Own (0x0UL) /*!< Own the channel group 20                                             */
84982 
84983 /* CHG21 @Bit 21 : Channel group number */
84984   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Pos (21UL)  /*!< Position of CHG21 field.                                             */
84985   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Pos) /*!< Bit mask of CHG21 field.       */
84986   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Min (0x0UL) /*!< Min enumerator value of CHG21 field.                                 */
84987   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Max (0x1UL) /*!< Max enumerator value of CHG21 field.                                 */
84988   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_NotOwn (0x1UL) /*!< Do not own the channel group 21                                   */
84989   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG21_Own (0x0UL) /*!< Own the channel group 21                                             */
84990 
84991 /* CHG22 @Bit 22 : Channel group number */
84992   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Pos (22UL)  /*!< Position of CHG22 field.                                             */
84993   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Pos) /*!< Bit mask of CHG22 field.       */
84994   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Min (0x0UL) /*!< Min enumerator value of CHG22 field.                                 */
84995   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Max (0x1UL) /*!< Max enumerator value of CHG22 field.                                 */
84996   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_NotOwn (0x1UL) /*!< Do not own the channel group 22                                   */
84997   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG22_Own (0x0UL) /*!< Own the channel group 22                                             */
84998 
84999 /* CHG23 @Bit 23 : Channel group number */
85000   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Pos (23UL)  /*!< Position of CHG23 field.                                             */
85001   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Pos) /*!< Bit mask of CHG23 field.       */
85002   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Min (0x0UL) /*!< Min enumerator value of CHG23 field.                                 */
85003   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Max (0x1UL) /*!< Max enumerator value of CHG23 field.                                 */
85004   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_NotOwn (0x1UL) /*!< Do not own the channel group 23                                   */
85005   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG23_Own (0x0UL) /*!< Own the channel group 23                                             */
85006 
85007 /* CHG24 @Bit 24 : Channel group number */
85008   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Pos (24UL)  /*!< Position of CHG24 field.                                             */
85009   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Pos) /*!< Bit mask of CHG24 field.       */
85010   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Min (0x0UL) /*!< Min enumerator value of CHG24 field.                                 */
85011   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Max (0x1UL) /*!< Max enumerator value of CHG24 field.                                 */
85012   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_NotOwn (0x1UL) /*!< Do not own the channel group 24                                   */
85013   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG24_Own (0x0UL) /*!< Own the channel group 24                                             */
85014 
85015 /* CHG25 @Bit 25 : Channel group number */
85016   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Pos (25UL)  /*!< Position of CHG25 field.                                             */
85017   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Pos) /*!< Bit mask of CHG25 field.       */
85018   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Min (0x0UL) /*!< Min enumerator value of CHG25 field.                                 */
85019   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Max (0x1UL) /*!< Max enumerator value of CHG25 field.                                 */
85020   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_NotOwn (0x1UL) /*!< Do not own the channel group 25                                   */
85021   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG25_Own (0x0UL) /*!< Own the channel group 25                                             */
85022 
85023 /* CHG26 @Bit 26 : Channel group number */
85024   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Pos (26UL)  /*!< Position of CHG26 field.                                             */
85025   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Pos) /*!< Bit mask of CHG26 field.       */
85026   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Min (0x0UL) /*!< Min enumerator value of CHG26 field.                                 */
85027   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Max (0x1UL) /*!< Max enumerator value of CHG26 field.                                 */
85028   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_NotOwn (0x1UL) /*!< Do not own the channel group 26                                   */
85029   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG26_Own (0x0UL) /*!< Own the channel group 26                                             */
85030 
85031 /* CHG27 @Bit 27 : Channel group number */
85032   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Pos (27UL)  /*!< Position of CHG27 field.                                             */
85033   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Pos) /*!< Bit mask of CHG27 field.       */
85034   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Min (0x0UL) /*!< Min enumerator value of CHG27 field.                                 */
85035   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Max (0x1UL) /*!< Max enumerator value of CHG27 field.                                 */
85036   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_NotOwn (0x1UL) /*!< Do not own the channel group 27                                   */
85037   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG27_Own (0x0UL) /*!< Own the channel group 27                                             */
85038 
85039 /* CHG28 @Bit 28 : Channel group number */
85040   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Pos (28UL)  /*!< Position of CHG28 field.                                             */
85041   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Pos) /*!< Bit mask of CHG28 field.       */
85042   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Min (0x0UL) /*!< Min enumerator value of CHG28 field.                                 */
85043   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Max (0x1UL) /*!< Max enumerator value of CHG28 field.                                 */
85044   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_NotOwn (0x1UL) /*!< Do not own the channel group 28                                   */
85045   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG28_Own (0x0UL) /*!< Own the channel group 28                                             */
85046 
85047 /* CHG29 @Bit 29 : Channel group number */
85048   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Pos (29UL)  /*!< Position of CHG29 field.                                             */
85049   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Pos) /*!< Bit mask of CHG29 field.       */
85050   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Min (0x0UL) /*!< Min enumerator value of CHG29 field.                                 */
85051   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Max (0x1UL) /*!< Max enumerator value of CHG29 field.                                 */
85052   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_NotOwn (0x1UL) /*!< Do not own the channel group 29                                   */
85053   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG29_Own (0x0UL) /*!< Own the channel group 29                                             */
85054 
85055 /* CHG30 @Bit 30 : Channel group number */
85056   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Pos (30UL)  /*!< Position of CHG30 field.                                             */
85057   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Pos) /*!< Bit mask of CHG30 field.       */
85058   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Min (0x0UL) /*!< Min enumerator value of CHG30 field.                                 */
85059   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Max (0x1UL) /*!< Max enumerator value of CHG30 field.                                 */
85060   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_NotOwn (0x1UL) /*!< Do not own the channel group 30                                   */
85061   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG30_Own (0x0UL) /*!< Own the channel group 30                                             */
85062 
85063 /* CHG31 @Bit 31 : Channel group number */
85064   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Pos (31UL)  /*!< Position of CHG31 field.                                             */
85065   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Pos) /*!< Bit mask of CHG31 field.       */
85066   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Min (0x0UL) /*!< Min enumerator value of CHG31 field.                                 */
85067   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Max (0x1UL) /*!< Max enumerator value of CHG31 field.                                 */
85068   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_NotOwn (0x1UL) /*!< Do not own the channel group 31                                   */
85069   #define UICR_DPPI_GLOBAL_CHG_OWN_CHG31_Own (0x0UL) /*!< Own the channel group 31                                             */
85070 
85071 
85072 /* UICR_DPPI_GLOBAL_CHG_SECURE: Request permission for the channel groups of DPPI[n] in Global domain */
85073   #define UICR_DPPI_GLOBAL_CHG_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                           */
85074 
85075 /* CHG0 @Bit 0 : Channel group number */
85076   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Pos (0UL) /*!< Position of CHG0 field.                                              */
85077   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Pos) /*!< Bit mask of CHG0 field.    */
85078   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Min (0x0UL) /*!< Min enumerator value of CHG0 field.                                */
85079   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Max (0x1UL) /*!< Max enumerator value of CHG0 field.                                */
85080   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_Secure (0x1UL) /*!< The channel group 0 is secure                                   */
85081   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG0_NonSecure (0x0UL) /*!< The channel group 0 is non-secure                            */
85082 
85083 /* CHG1 @Bit 1 : Channel group number */
85084   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Pos (1UL) /*!< Position of CHG1 field.                                              */
85085   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Pos) /*!< Bit mask of CHG1 field.    */
85086   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Min (0x0UL) /*!< Min enumerator value of CHG1 field.                                */
85087   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Max (0x1UL) /*!< Max enumerator value of CHG1 field.                                */
85088   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_Secure (0x1UL) /*!< The channel group 1 is secure                                   */
85089   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG1_NonSecure (0x0UL) /*!< The channel group 1 is non-secure                            */
85090 
85091 /* CHG2 @Bit 2 : Channel group number */
85092   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Pos (2UL) /*!< Position of CHG2 field.                                              */
85093   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Pos) /*!< Bit mask of CHG2 field.    */
85094   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Min (0x0UL) /*!< Min enumerator value of CHG2 field.                                */
85095   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Max (0x1UL) /*!< Max enumerator value of CHG2 field.                                */
85096   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_Secure (0x1UL) /*!< The channel group 2 is secure                                   */
85097   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG2_NonSecure (0x0UL) /*!< The channel group 2 is non-secure                            */
85098 
85099 /* CHG3 @Bit 3 : Channel group number */
85100   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Pos (3UL) /*!< Position of CHG3 field.                                              */
85101   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Pos) /*!< Bit mask of CHG3 field.    */
85102   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Min (0x0UL) /*!< Min enumerator value of CHG3 field.                                */
85103   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Max (0x1UL) /*!< Max enumerator value of CHG3 field.                                */
85104   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_Secure (0x1UL) /*!< The channel group 3 is secure                                   */
85105   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG3_NonSecure (0x0UL) /*!< The channel group 3 is non-secure                            */
85106 
85107 /* CHG4 @Bit 4 : Channel group number */
85108   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Pos (4UL) /*!< Position of CHG4 field.                                              */
85109   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Pos) /*!< Bit mask of CHG4 field.    */
85110   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Min (0x0UL) /*!< Min enumerator value of CHG4 field.                                */
85111   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Max (0x1UL) /*!< Max enumerator value of CHG4 field.                                */
85112   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_Secure (0x1UL) /*!< The channel group 4 is secure                                   */
85113   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG4_NonSecure (0x0UL) /*!< The channel group 4 is non-secure                            */
85114 
85115 /* CHG5 @Bit 5 : Channel group number */
85116   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Pos (5UL) /*!< Position of CHG5 field.                                              */
85117   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Pos) /*!< Bit mask of CHG5 field.    */
85118   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Min (0x0UL) /*!< Min enumerator value of CHG5 field.                                */
85119   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Max (0x1UL) /*!< Max enumerator value of CHG5 field.                                */
85120   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_Secure (0x1UL) /*!< The channel group 5 is secure                                   */
85121   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG5_NonSecure (0x0UL) /*!< The channel group 5 is non-secure                            */
85122 
85123 /* CHG6 @Bit 6 : Channel group number */
85124   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Pos (6UL) /*!< Position of CHG6 field.                                              */
85125   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Pos) /*!< Bit mask of CHG6 field.    */
85126   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Min (0x0UL) /*!< Min enumerator value of CHG6 field.                                */
85127   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Max (0x1UL) /*!< Max enumerator value of CHG6 field.                                */
85128   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_Secure (0x1UL) /*!< The channel group 6 is secure                                   */
85129   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG6_NonSecure (0x0UL) /*!< The channel group 6 is non-secure                            */
85130 
85131 /* CHG7 @Bit 7 : Channel group number */
85132   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Pos (7UL) /*!< Position of CHG7 field.                                              */
85133   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Pos) /*!< Bit mask of CHG7 field.    */
85134   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Min (0x0UL) /*!< Min enumerator value of CHG7 field.                                */
85135   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Max (0x1UL) /*!< Max enumerator value of CHG7 field.                                */
85136   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_Secure (0x1UL) /*!< The channel group 7 is secure                                   */
85137   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG7_NonSecure (0x0UL) /*!< The channel group 7 is non-secure                            */
85138 
85139 /* CHG8 @Bit 8 : Channel group number */
85140   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Pos (8UL) /*!< Position of CHG8 field.                                              */
85141   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Pos) /*!< Bit mask of CHG8 field.    */
85142   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Min (0x0UL) /*!< Min enumerator value of CHG8 field.                                */
85143   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Max (0x1UL) /*!< Max enumerator value of CHG8 field.                                */
85144   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_Secure (0x1UL) /*!< The channel group 8 is secure                                   */
85145   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG8_NonSecure (0x0UL) /*!< The channel group 8 is non-secure                            */
85146 
85147 /* CHG9 @Bit 9 : Channel group number */
85148   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Pos (9UL) /*!< Position of CHG9 field.                                              */
85149   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Pos) /*!< Bit mask of CHG9 field.    */
85150   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Min (0x0UL) /*!< Min enumerator value of CHG9 field.                                */
85151   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Max (0x1UL) /*!< Max enumerator value of CHG9 field.                                */
85152   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_Secure (0x1UL) /*!< The channel group 9 is secure                                   */
85153   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG9_NonSecure (0x0UL) /*!< The channel group 9 is non-secure                            */
85154 
85155 /* CHG10 @Bit 10 : Channel group number */
85156   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Pos (10UL) /*!< Position of CHG10 field.                                           */
85157   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Pos) /*!< Bit mask of CHG10 field. */
85158   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Min (0x0UL) /*!< Min enumerator value of CHG10 field.                              */
85159   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Max (0x1UL) /*!< Max enumerator value of CHG10 field.                              */
85160   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_Secure (0x1UL) /*!< The channel group 10 is secure                                 */
85161   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG10_NonSecure (0x0UL) /*!< The channel group 10 is non-secure                          */
85162 
85163 /* CHG11 @Bit 11 : Channel group number */
85164   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Pos (11UL) /*!< Position of CHG11 field.                                           */
85165   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Pos) /*!< Bit mask of CHG11 field. */
85166   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Min (0x0UL) /*!< Min enumerator value of CHG11 field.                              */
85167   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Max (0x1UL) /*!< Max enumerator value of CHG11 field.                              */
85168   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_Secure (0x1UL) /*!< The channel group 11 is secure                                 */
85169   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG11_NonSecure (0x0UL) /*!< The channel group 11 is non-secure                          */
85170 
85171 /* CHG12 @Bit 12 : Channel group number */
85172   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Pos (12UL) /*!< Position of CHG12 field.                                           */
85173   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Pos) /*!< Bit mask of CHG12 field. */
85174   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Min (0x0UL) /*!< Min enumerator value of CHG12 field.                              */
85175   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Max (0x1UL) /*!< Max enumerator value of CHG12 field.                              */
85176   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_Secure (0x1UL) /*!< The channel group 12 is secure                                 */
85177   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG12_NonSecure (0x0UL) /*!< The channel group 12 is non-secure                          */
85178 
85179 /* CHG13 @Bit 13 : Channel group number */
85180   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Pos (13UL) /*!< Position of CHG13 field.                                           */
85181   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Pos) /*!< Bit mask of CHG13 field. */
85182   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Min (0x0UL) /*!< Min enumerator value of CHG13 field.                              */
85183   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Max (0x1UL) /*!< Max enumerator value of CHG13 field.                              */
85184   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_Secure (0x1UL) /*!< The channel group 13 is secure                                 */
85185   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG13_NonSecure (0x0UL) /*!< The channel group 13 is non-secure                          */
85186 
85187 /* CHG14 @Bit 14 : Channel group number */
85188   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Pos (14UL) /*!< Position of CHG14 field.                                           */
85189   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Pos) /*!< Bit mask of CHG14 field. */
85190   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Min (0x0UL) /*!< Min enumerator value of CHG14 field.                              */
85191   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Max (0x1UL) /*!< Max enumerator value of CHG14 field.                              */
85192   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_Secure (0x1UL) /*!< The channel group 14 is secure                                 */
85193   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG14_NonSecure (0x0UL) /*!< The channel group 14 is non-secure                          */
85194 
85195 /* CHG15 @Bit 15 : Channel group number */
85196   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Pos (15UL) /*!< Position of CHG15 field.                                           */
85197   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Pos) /*!< Bit mask of CHG15 field. */
85198   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Min (0x0UL) /*!< Min enumerator value of CHG15 field.                              */
85199   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Max (0x1UL) /*!< Max enumerator value of CHG15 field.                              */
85200   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_Secure (0x1UL) /*!< The channel group 15 is secure                                 */
85201   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG15_NonSecure (0x0UL) /*!< The channel group 15 is non-secure                          */
85202 
85203 /* CHG16 @Bit 16 : Channel group number */
85204   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Pos (16UL) /*!< Position of CHG16 field.                                           */
85205   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Pos) /*!< Bit mask of CHG16 field. */
85206   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Min (0x0UL) /*!< Min enumerator value of CHG16 field.                              */
85207   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Max (0x1UL) /*!< Max enumerator value of CHG16 field.                              */
85208   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_Secure (0x1UL) /*!< The channel group 16 is secure                                 */
85209   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG16_NonSecure (0x0UL) /*!< The channel group 16 is non-secure                          */
85210 
85211 /* CHG17 @Bit 17 : Channel group number */
85212   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Pos (17UL) /*!< Position of CHG17 field.                                           */
85213   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Pos) /*!< Bit mask of CHG17 field. */
85214   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Min (0x0UL) /*!< Min enumerator value of CHG17 field.                              */
85215   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Max (0x1UL) /*!< Max enumerator value of CHG17 field.                              */
85216   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_Secure (0x1UL) /*!< The channel group 17 is secure                                 */
85217   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG17_NonSecure (0x0UL) /*!< The channel group 17 is non-secure                          */
85218 
85219 /* CHG18 @Bit 18 : Channel group number */
85220   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Pos (18UL) /*!< Position of CHG18 field.                                           */
85221   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Pos) /*!< Bit mask of CHG18 field. */
85222   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Min (0x0UL) /*!< Min enumerator value of CHG18 field.                              */
85223   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Max (0x1UL) /*!< Max enumerator value of CHG18 field.                              */
85224   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_Secure (0x1UL) /*!< The channel group 18 is secure                                 */
85225   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG18_NonSecure (0x0UL) /*!< The channel group 18 is non-secure                          */
85226 
85227 /* CHG19 @Bit 19 : Channel group number */
85228   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Pos (19UL) /*!< Position of CHG19 field.                                           */
85229   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Pos) /*!< Bit mask of CHG19 field. */
85230   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Min (0x0UL) /*!< Min enumerator value of CHG19 field.                              */
85231   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Max (0x1UL) /*!< Max enumerator value of CHG19 field.                              */
85232   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_Secure (0x1UL) /*!< The channel group 19 is secure                                 */
85233   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG19_NonSecure (0x0UL) /*!< The channel group 19 is non-secure                          */
85234 
85235 /* CHG20 @Bit 20 : Channel group number */
85236   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Pos (20UL) /*!< Position of CHG20 field.                                           */
85237   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Pos) /*!< Bit mask of CHG20 field. */
85238   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Min (0x0UL) /*!< Min enumerator value of CHG20 field.                              */
85239   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Max (0x1UL) /*!< Max enumerator value of CHG20 field.                              */
85240   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_Secure (0x1UL) /*!< The channel group 20 is secure                                 */
85241   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG20_NonSecure (0x0UL) /*!< The channel group 20 is non-secure                          */
85242 
85243 /* CHG21 @Bit 21 : Channel group number */
85244   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Pos (21UL) /*!< Position of CHG21 field.                                           */
85245   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Pos) /*!< Bit mask of CHG21 field. */
85246   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Min (0x0UL) /*!< Min enumerator value of CHG21 field.                              */
85247   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Max (0x1UL) /*!< Max enumerator value of CHG21 field.                              */
85248   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_Secure (0x1UL) /*!< The channel group 21 is secure                                 */
85249   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG21_NonSecure (0x0UL) /*!< The channel group 21 is non-secure                          */
85250 
85251 /* CHG22 @Bit 22 : Channel group number */
85252   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Pos (22UL) /*!< Position of CHG22 field.                                           */
85253   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Pos) /*!< Bit mask of CHG22 field. */
85254   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Min (0x0UL) /*!< Min enumerator value of CHG22 field.                              */
85255   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Max (0x1UL) /*!< Max enumerator value of CHG22 field.                              */
85256   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_Secure (0x1UL) /*!< The channel group 22 is secure                                 */
85257   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG22_NonSecure (0x0UL) /*!< The channel group 22 is non-secure                          */
85258 
85259 /* CHG23 @Bit 23 : Channel group number */
85260   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Pos (23UL) /*!< Position of CHG23 field.                                           */
85261   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Pos) /*!< Bit mask of CHG23 field. */
85262   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Min (0x0UL) /*!< Min enumerator value of CHG23 field.                              */
85263   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Max (0x1UL) /*!< Max enumerator value of CHG23 field.                              */
85264   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_Secure (0x1UL) /*!< The channel group 23 is secure                                 */
85265   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG23_NonSecure (0x0UL) /*!< The channel group 23 is non-secure                          */
85266 
85267 /* CHG24 @Bit 24 : Channel group number */
85268   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Pos (24UL) /*!< Position of CHG24 field.                                           */
85269   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Pos) /*!< Bit mask of CHG24 field. */
85270   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Min (0x0UL) /*!< Min enumerator value of CHG24 field.                              */
85271   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Max (0x1UL) /*!< Max enumerator value of CHG24 field.                              */
85272   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_Secure (0x1UL) /*!< The channel group 24 is secure                                 */
85273   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG24_NonSecure (0x0UL) /*!< The channel group 24 is non-secure                          */
85274 
85275 /* CHG25 @Bit 25 : Channel group number */
85276   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Pos (25UL) /*!< Position of CHG25 field.                                           */
85277   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Pos) /*!< Bit mask of CHG25 field. */
85278   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Min (0x0UL) /*!< Min enumerator value of CHG25 field.                              */
85279   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Max (0x1UL) /*!< Max enumerator value of CHG25 field.                              */
85280   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_Secure (0x1UL) /*!< The channel group 25 is secure                                 */
85281   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG25_NonSecure (0x0UL) /*!< The channel group 25 is non-secure                          */
85282 
85283 /* CHG26 @Bit 26 : Channel group number */
85284   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Pos (26UL) /*!< Position of CHG26 field.                                           */
85285   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Pos) /*!< Bit mask of CHG26 field. */
85286   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Min (0x0UL) /*!< Min enumerator value of CHG26 field.                              */
85287   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Max (0x1UL) /*!< Max enumerator value of CHG26 field.                              */
85288   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_Secure (0x1UL) /*!< The channel group 26 is secure                                 */
85289   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG26_NonSecure (0x0UL) /*!< The channel group 26 is non-secure                          */
85290 
85291 /* CHG27 @Bit 27 : Channel group number */
85292   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Pos (27UL) /*!< Position of CHG27 field.                                           */
85293   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Pos) /*!< Bit mask of CHG27 field. */
85294   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Min (0x0UL) /*!< Min enumerator value of CHG27 field.                              */
85295   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Max (0x1UL) /*!< Max enumerator value of CHG27 field.                              */
85296   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_Secure (0x1UL) /*!< The channel group 27 is secure                                 */
85297   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG27_NonSecure (0x0UL) /*!< The channel group 27 is non-secure                          */
85298 
85299 /* CHG28 @Bit 28 : Channel group number */
85300   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Pos (28UL) /*!< Position of CHG28 field.                                           */
85301   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Pos) /*!< Bit mask of CHG28 field. */
85302   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Min (0x0UL) /*!< Min enumerator value of CHG28 field.                              */
85303   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Max (0x1UL) /*!< Max enumerator value of CHG28 field.                              */
85304   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_Secure (0x1UL) /*!< The channel group 28 is secure                                 */
85305   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG28_NonSecure (0x0UL) /*!< The channel group 28 is non-secure                          */
85306 
85307 /* CHG29 @Bit 29 : Channel group number */
85308   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Pos (29UL) /*!< Position of CHG29 field.                                           */
85309   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Pos) /*!< Bit mask of CHG29 field. */
85310   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Min (0x0UL) /*!< Min enumerator value of CHG29 field.                              */
85311   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Max (0x1UL) /*!< Max enumerator value of CHG29 field.                              */
85312   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_Secure (0x1UL) /*!< The channel group 29 is secure                                 */
85313   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG29_NonSecure (0x0UL) /*!< The channel group 29 is non-secure                          */
85314 
85315 /* CHG30 @Bit 30 : Channel group number */
85316   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Pos (30UL) /*!< Position of CHG30 field.                                           */
85317   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Pos) /*!< Bit mask of CHG30 field. */
85318   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Min (0x0UL) /*!< Min enumerator value of CHG30 field.                              */
85319   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Max (0x1UL) /*!< Max enumerator value of CHG30 field.                              */
85320   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_Secure (0x1UL) /*!< The channel group 30 is secure                                 */
85321   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG30_NonSecure (0x0UL) /*!< The channel group 30 is non-secure                          */
85322 
85323 /* CHG31 @Bit 31 : Channel group number */
85324   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Pos (31UL) /*!< Position of CHG31 field.                                           */
85325   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Msk (0x1UL << UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Pos) /*!< Bit mask of CHG31 field. */
85326   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Min (0x0UL) /*!< Min enumerator value of CHG31 field.                              */
85327   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Max (0x1UL) /*!< Max enumerator value of CHG31 field.                              */
85328   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_Secure (0x1UL) /*!< The channel group 31 is secure                                 */
85329   #define UICR_DPPI_GLOBAL_CHG_SECURE_CHG31_NonSecure (0x0UL) /*!< The channel group 31 is non-secure                          */
85330 
85331 
85332 
85333 /* ================================================= Struct UICR_DPPI_GLOBAL ================================================= */
85334 /**
85335   * @brief GLOBAL [UICR_DPPI_GLOBAL] (unspecified)
85336   */
85337 typedef struct {
85338   __IOM uint32_t  INSTANCE;                          /*!< (@ 0x00000000) Address of the DPPI instance associated with
85339                                                                          DPPI[n].GLOBAL*/
85340   __IOM NRF_UICR_DPPI_GLOBAL_CH_Type CH;             /*!< (@ 0x00000004) (unspecified)                                         */
85341   __IOM NRF_UICR_DPPI_GLOBAL_CHG_Type CHG;           /*!< (@ 0x00000014) (unspecified)                                         */
85342 } NRF_UICR_DPPI_GLOBAL_Type;                         /*!< Size = 28 (0x01C)                                                    */
85343   #define UICR_DPPI_GLOBAL_MaxCount (12UL)           /*!< Size of GLOBAL[12] array.                                            */
85344   #define UICR_DPPI_GLOBAL_MaxIndex (11UL)           /*!< Max index of GLOBAL[12] array.                                       */
85345   #define UICR_DPPI_GLOBAL_MinIndex (0UL)            /*!< Min index of GLOBAL[12] array.                                       */
85346 
85347 /* UICR_DPPI_GLOBAL_INSTANCE: Address of the DPPI instance associated with DPPI[n].GLOBAL */
85348   #define UICR_DPPI_GLOBAL_INSTANCE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of INSTANCE register.                           */
85349 
85350 /* ADDRESS @Bits 0..31 : Instance address */
85351   #define UICR_DPPI_GLOBAL_INSTANCE_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field.                                          */
85352   #define UICR_DPPI_GLOBAL_INSTANCE_ADDRESS_Msk (0xFFFFFFFFUL << UICR_DPPI_GLOBAL_INSTANCE_ADDRESS_Pos) /*!< Bit mask of ADDRESS
85353                                                                             field.*/
85354 
85355 
85356 
85357 /* ==================================================== Struct UICR_DPPI ===================================================== */
85358 /**
85359   * @brief DPPI [UICR_DPPI] (unspecified)
85360   */
85361 typedef struct {
85362   __IOM NRF_UICR_DPPI_LOCAL_Type LOCAL[2];           /*!< (@ 0x00000000) (unspecified)                                         */
85363   __IOM NRF_UICR_DPPI_GLOBAL_Type GLOBAL[12];        /*!< (@ 0x00000028) (unspecified)                                         */
85364 } NRF_UICR_DPPI_Type;                                /*!< Size = 376 (0x178)                                                   */
85365 
85366 
85367 /* =================================================== Struct UICR_GRTC_CC =================================================== */
85368 /**
85369   * @brief CC [UICR_GRTC_CC] (unspecified)
85370   */
85371 typedef struct {
85372   __IOM uint32_t  OWN;                               /*!< (@ 0x00000000) Request ownership of the CCs of GRTCGRTC              */
85373   __IOM uint32_t  SECURE;                            /*!< (@ 0x00000004) Request permission for the CCs of GRTC                */
85374 } NRF_UICR_GRTC_CC_Type;                             /*!< Size = 8 (0x008)                                                     */
85375 
85376 /* UICR_GRTC_CC_OWN: Request ownership of the CCs of GRTCGRTC */
85377   #define UICR_GRTC_CC_OWN_ResetValue (0xFFFFFFFFUL) /*!< Reset value of OWN register.                                         */
85378 
85379 /* CC0 @Bit 0 : Capture/compare register number */
85380   #define UICR_GRTC_CC_OWN_CC0_Pos (0UL)             /*!< Position of CC0 field.                                               */
85381   #define UICR_GRTC_CC_OWN_CC0_Msk (0x1UL << UICR_GRTC_CC_OWN_CC0_Pos) /*!< Bit mask of CC0 field.                             */
85382   #define UICR_GRTC_CC_OWN_CC0_Min (0x0UL)           /*!< Min enumerator value of CC0 field.                                   */
85383   #define UICR_GRTC_CC_OWN_CC0_Max (0x1UL)           /*!< Max enumerator value of CC0 field.                                   */
85384   #define UICR_GRTC_CC_OWN_CC0_NotOwn (0x1UL)        /*!< Do not own the CC register 0                                         */
85385   #define UICR_GRTC_CC_OWN_CC0_Own (0x0UL)           /*!< Own the CC register 0                                                */
85386 
85387 /* CC1 @Bit 1 : Capture/compare register number */
85388   #define UICR_GRTC_CC_OWN_CC1_Pos (1UL)             /*!< Position of CC1 field.                                               */
85389   #define UICR_GRTC_CC_OWN_CC1_Msk (0x1UL << UICR_GRTC_CC_OWN_CC1_Pos) /*!< Bit mask of CC1 field.                             */
85390   #define UICR_GRTC_CC_OWN_CC1_Min (0x0UL)           /*!< Min enumerator value of CC1 field.                                   */
85391   #define UICR_GRTC_CC_OWN_CC1_Max (0x1UL)           /*!< Max enumerator value of CC1 field.                                   */
85392   #define UICR_GRTC_CC_OWN_CC1_NotOwn (0x1UL)        /*!< Do not own the CC register 1                                         */
85393   #define UICR_GRTC_CC_OWN_CC1_Own (0x0UL)           /*!< Own the CC register 1                                                */
85394 
85395 /* CC2 @Bit 2 : Capture/compare register number */
85396   #define UICR_GRTC_CC_OWN_CC2_Pos (2UL)             /*!< Position of CC2 field.                                               */
85397   #define UICR_GRTC_CC_OWN_CC2_Msk (0x1UL << UICR_GRTC_CC_OWN_CC2_Pos) /*!< Bit mask of CC2 field.                             */
85398   #define UICR_GRTC_CC_OWN_CC2_Min (0x0UL)           /*!< Min enumerator value of CC2 field.                                   */
85399   #define UICR_GRTC_CC_OWN_CC2_Max (0x1UL)           /*!< Max enumerator value of CC2 field.                                   */
85400   #define UICR_GRTC_CC_OWN_CC2_NotOwn (0x1UL)        /*!< Do not own the CC register 2                                         */
85401   #define UICR_GRTC_CC_OWN_CC2_Own (0x0UL)           /*!< Own the CC register 2                                                */
85402 
85403 /* CC3 @Bit 3 : Capture/compare register number */
85404   #define UICR_GRTC_CC_OWN_CC3_Pos (3UL)             /*!< Position of CC3 field.                                               */
85405   #define UICR_GRTC_CC_OWN_CC3_Msk (0x1UL << UICR_GRTC_CC_OWN_CC3_Pos) /*!< Bit mask of CC3 field.                             */
85406   #define UICR_GRTC_CC_OWN_CC3_Min (0x0UL)           /*!< Min enumerator value of CC3 field.                                   */
85407   #define UICR_GRTC_CC_OWN_CC3_Max (0x1UL)           /*!< Max enumerator value of CC3 field.                                   */
85408   #define UICR_GRTC_CC_OWN_CC3_NotOwn (0x1UL)        /*!< Do not own the CC register 3                                         */
85409   #define UICR_GRTC_CC_OWN_CC3_Own (0x0UL)           /*!< Own the CC register 3                                                */
85410 
85411 /* CC4 @Bit 4 : Capture/compare register number */
85412   #define UICR_GRTC_CC_OWN_CC4_Pos (4UL)             /*!< Position of CC4 field.                                               */
85413   #define UICR_GRTC_CC_OWN_CC4_Msk (0x1UL << UICR_GRTC_CC_OWN_CC4_Pos) /*!< Bit mask of CC4 field.                             */
85414   #define UICR_GRTC_CC_OWN_CC4_Min (0x0UL)           /*!< Min enumerator value of CC4 field.                                   */
85415   #define UICR_GRTC_CC_OWN_CC4_Max (0x1UL)           /*!< Max enumerator value of CC4 field.                                   */
85416   #define UICR_GRTC_CC_OWN_CC4_NotOwn (0x1UL)        /*!< Do not own the CC register 4                                         */
85417   #define UICR_GRTC_CC_OWN_CC4_Own (0x0UL)           /*!< Own the CC register 4                                                */
85418 
85419 /* CC5 @Bit 5 : Capture/compare register number */
85420   #define UICR_GRTC_CC_OWN_CC5_Pos (5UL)             /*!< Position of CC5 field.                                               */
85421   #define UICR_GRTC_CC_OWN_CC5_Msk (0x1UL << UICR_GRTC_CC_OWN_CC5_Pos) /*!< Bit mask of CC5 field.                             */
85422   #define UICR_GRTC_CC_OWN_CC5_Min (0x0UL)           /*!< Min enumerator value of CC5 field.                                   */
85423   #define UICR_GRTC_CC_OWN_CC5_Max (0x1UL)           /*!< Max enumerator value of CC5 field.                                   */
85424   #define UICR_GRTC_CC_OWN_CC5_NotOwn (0x1UL)        /*!< Do not own the CC register 5                                         */
85425   #define UICR_GRTC_CC_OWN_CC5_Own (0x0UL)           /*!< Own the CC register 5                                                */
85426 
85427 /* CC6 @Bit 6 : Capture/compare register number */
85428   #define UICR_GRTC_CC_OWN_CC6_Pos (6UL)             /*!< Position of CC6 field.                                               */
85429   #define UICR_GRTC_CC_OWN_CC6_Msk (0x1UL << UICR_GRTC_CC_OWN_CC6_Pos) /*!< Bit mask of CC6 field.                             */
85430   #define UICR_GRTC_CC_OWN_CC6_Min (0x0UL)           /*!< Min enumerator value of CC6 field.                                   */
85431   #define UICR_GRTC_CC_OWN_CC6_Max (0x1UL)           /*!< Max enumerator value of CC6 field.                                   */
85432   #define UICR_GRTC_CC_OWN_CC6_NotOwn (0x1UL)        /*!< Do not own the CC register 6                                         */
85433   #define UICR_GRTC_CC_OWN_CC6_Own (0x0UL)           /*!< Own the CC register 6                                                */
85434 
85435 /* CC7 @Bit 7 : Capture/compare register number */
85436   #define UICR_GRTC_CC_OWN_CC7_Pos (7UL)             /*!< Position of CC7 field.                                               */
85437   #define UICR_GRTC_CC_OWN_CC7_Msk (0x1UL << UICR_GRTC_CC_OWN_CC7_Pos) /*!< Bit mask of CC7 field.                             */
85438   #define UICR_GRTC_CC_OWN_CC7_Min (0x0UL)           /*!< Min enumerator value of CC7 field.                                   */
85439   #define UICR_GRTC_CC_OWN_CC7_Max (0x1UL)           /*!< Max enumerator value of CC7 field.                                   */
85440   #define UICR_GRTC_CC_OWN_CC7_NotOwn (0x1UL)        /*!< Do not own the CC register 7                                         */
85441   #define UICR_GRTC_CC_OWN_CC7_Own (0x0UL)           /*!< Own the CC register 7                                                */
85442 
85443 /* CC8 @Bit 8 : Capture/compare register number */
85444   #define UICR_GRTC_CC_OWN_CC8_Pos (8UL)             /*!< Position of CC8 field.                                               */
85445   #define UICR_GRTC_CC_OWN_CC8_Msk (0x1UL << UICR_GRTC_CC_OWN_CC8_Pos) /*!< Bit mask of CC8 field.                             */
85446   #define UICR_GRTC_CC_OWN_CC8_Min (0x0UL)           /*!< Min enumerator value of CC8 field.                                   */
85447   #define UICR_GRTC_CC_OWN_CC8_Max (0x1UL)           /*!< Max enumerator value of CC8 field.                                   */
85448   #define UICR_GRTC_CC_OWN_CC8_NotOwn (0x1UL)        /*!< Do not own the CC register 8                                         */
85449   #define UICR_GRTC_CC_OWN_CC8_Own (0x0UL)           /*!< Own the CC register 8                                                */
85450 
85451 /* CC9 @Bit 9 : Capture/compare register number */
85452   #define UICR_GRTC_CC_OWN_CC9_Pos (9UL)             /*!< Position of CC9 field.                                               */
85453   #define UICR_GRTC_CC_OWN_CC9_Msk (0x1UL << UICR_GRTC_CC_OWN_CC9_Pos) /*!< Bit mask of CC9 field.                             */
85454   #define UICR_GRTC_CC_OWN_CC9_Min (0x0UL)           /*!< Min enumerator value of CC9 field.                                   */
85455   #define UICR_GRTC_CC_OWN_CC9_Max (0x1UL)           /*!< Max enumerator value of CC9 field.                                   */
85456   #define UICR_GRTC_CC_OWN_CC9_NotOwn (0x1UL)        /*!< Do not own the CC register 9                                         */
85457   #define UICR_GRTC_CC_OWN_CC9_Own (0x0UL)           /*!< Own the CC register 9                                                */
85458 
85459 /* CC10 @Bit 10 : Capture/compare register number */
85460   #define UICR_GRTC_CC_OWN_CC10_Pos (10UL)           /*!< Position of CC10 field.                                              */
85461   #define UICR_GRTC_CC_OWN_CC10_Msk (0x1UL << UICR_GRTC_CC_OWN_CC10_Pos) /*!< Bit mask of CC10 field.                          */
85462   #define UICR_GRTC_CC_OWN_CC10_Min (0x0UL)          /*!< Min enumerator value of CC10 field.                                  */
85463   #define UICR_GRTC_CC_OWN_CC10_Max (0x1UL)          /*!< Max enumerator value of CC10 field.                                  */
85464   #define UICR_GRTC_CC_OWN_CC10_NotOwn (0x1UL)       /*!< Do not own the CC register 10                                        */
85465   #define UICR_GRTC_CC_OWN_CC10_Own (0x0UL)          /*!< Own the CC register 10                                               */
85466 
85467 /* CC11 @Bit 11 : Capture/compare register number */
85468   #define UICR_GRTC_CC_OWN_CC11_Pos (11UL)           /*!< Position of CC11 field.                                              */
85469   #define UICR_GRTC_CC_OWN_CC11_Msk (0x1UL << UICR_GRTC_CC_OWN_CC11_Pos) /*!< Bit mask of CC11 field.                          */
85470   #define UICR_GRTC_CC_OWN_CC11_Min (0x0UL)          /*!< Min enumerator value of CC11 field.                                  */
85471   #define UICR_GRTC_CC_OWN_CC11_Max (0x1UL)          /*!< Max enumerator value of CC11 field.                                  */
85472   #define UICR_GRTC_CC_OWN_CC11_NotOwn (0x1UL)       /*!< Do not own the CC register 11                                        */
85473   #define UICR_GRTC_CC_OWN_CC11_Own (0x0UL)          /*!< Own the CC register 11                                               */
85474 
85475 /* CC12 @Bit 12 : Capture/compare register number */
85476   #define UICR_GRTC_CC_OWN_CC12_Pos (12UL)           /*!< Position of CC12 field.                                              */
85477   #define UICR_GRTC_CC_OWN_CC12_Msk (0x1UL << UICR_GRTC_CC_OWN_CC12_Pos) /*!< Bit mask of CC12 field.                          */
85478   #define UICR_GRTC_CC_OWN_CC12_Min (0x0UL)          /*!< Min enumerator value of CC12 field.                                  */
85479   #define UICR_GRTC_CC_OWN_CC12_Max (0x1UL)          /*!< Max enumerator value of CC12 field.                                  */
85480   #define UICR_GRTC_CC_OWN_CC12_NotOwn (0x1UL)       /*!< Do not own the CC register 12                                        */
85481   #define UICR_GRTC_CC_OWN_CC12_Own (0x0UL)          /*!< Own the CC register 12                                               */
85482 
85483 /* CC13 @Bit 13 : Capture/compare register number */
85484   #define UICR_GRTC_CC_OWN_CC13_Pos (13UL)           /*!< Position of CC13 field.                                              */
85485   #define UICR_GRTC_CC_OWN_CC13_Msk (0x1UL << UICR_GRTC_CC_OWN_CC13_Pos) /*!< Bit mask of CC13 field.                          */
85486   #define UICR_GRTC_CC_OWN_CC13_Min (0x0UL)          /*!< Min enumerator value of CC13 field.                                  */
85487   #define UICR_GRTC_CC_OWN_CC13_Max (0x1UL)          /*!< Max enumerator value of CC13 field.                                  */
85488   #define UICR_GRTC_CC_OWN_CC13_NotOwn (0x1UL)       /*!< Do not own the CC register 13                                        */
85489   #define UICR_GRTC_CC_OWN_CC13_Own (0x0UL)          /*!< Own the CC register 13                                               */
85490 
85491 /* CC14 @Bit 14 : Capture/compare register number */
85492   #define UICR_GRTC_CC_OWN_CC14_Pos (14UL)           /*!< Position of CC14 field.                                              */
85493   #define UICR_GRTC_CC_OWN_CC14_Msk (0x1UL << UICR_GRTC_CC_OWN_CC14_Pos) /*!< Bit mask of CC14 field.                          */
85494   #define UICR_GRTC_CC_OWN_CC14_Min (0x0UL)          /*!< Min enumerator value of CC14 field.                                  */
85495   #define UICR_GRTC_CC_OWN_CC14_Max (0x1UL)          /*!< Max enumerator value of CC14 field.                                  */
85496   #define UICR_GRTC_CC_OWN_CC14_NotOwn (0x1UL)       /*!< Do not own the CC register 14                                        */
85497   #define UICR_GRTC_CC_OWN_CC14_Own (0x0UL)          /*!< Own the CC register 14                                               */
85498 
85499 /* CC15 @Bit 15 : Capture/compare register number */
85500   #define UICR_GRTC_CC_OWN_CC15_Pos (15UL)           /*!< Position of CC15 field.                                              */
85501   #define UICR_GRTC_CC_OWN_CC15_Msk (0x1UL << UICR_GRTC_CC_OWN_CC15_Pos) /*!< Bit mask of CC15 field.                          */
85502   #define UICR_GRTC_CC_OWN_CC15_Min (0x0UL)          /*!< Min enumerator value of CC15 field.                                  */
85503   #define UICR_GRTC_CC_OWN_CC15_Max (0x1UL)          /*!< Max enumerator value of CC15 field.                                  */
85504   #define UICR_GRTC_CC_OWN_CC15_NotOwn (0x1UL)       /*!< Do not own the CC register 15                                        */
85505   #define UICR_GRTC_CC_OWN_CC15_Own (0x0UL)          /*!< Own the CC register 15                                               */
85506 
85507 
85508 /* UICR_GRTC_CC_SECURE: Request permission for the CCs of GRTC */
85509   #define UICR_GRTC_CC_SECURE_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SECURE register.                                   */
85510 
85511 /* CC0 @Bit 0 : Capture/compare register number */
85512   #define UICR_GRTC_CC_SECURE_CC0_Pos (0UL)          /*!< Position of CC0 field.                                               */
85513   #define UICR_GRTC_CC_SECURE_CC0_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC0_Pos) /*!< Bit mask of CC0 field.                       */
85514   #define UICR_GRTC_CC_SECURE_CC0_Min (0x0UL)        /*!< Min enumerator value of CC0 field.                                   */
85515   #define UICR_GRTC_CC_SECURE_CC0_Max (0x1UL)        /*!< Max enumerator value of CC0 field.                                   */
85516   #define UICR_GRTC_CC_SECURE_CC0_Secure (0x1UL)     /*!< The CC register 0 is secure                                          */
85517   #define UICR_GRTC_CC_SECURE_CC0_NonSecure (0x0UL)  /*!< The CC register 0 is non-secure                                      */
85518 
85519 /* CC1 @Bit 1 : Capture/compare register number */
85520   #define UICR_GRTC_CC_SECURE_CC1_Pos (1UL)          /*!< Position of CC1 field.                                               */
85521   #define UICR_GRTC_CC_SECURE_CC1_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC1_Pos) /*!< Bit mask of CC1 field.                       */
85522   #define UICR_GRTC_CC_SECURE_CC1_Min (0x0UL)        /*!< Min enumerator value of CC1 field.                                   */
85523   #define UICR_GRTC_CC_SECURE_CC1_Max (0x1UL)        /*!< Max enumerator value of CC1 field.                                   */
85524   #define UICR_GRTC_CC_SECURE_CC1_Secure (0x1UL)     /*!< The CC register 1 is secure                                          */
85525   #define UICR_GRTC_CC_SECURE_CC1_NonSecure (0x0UL)  /*!< The CC register 1 is non-secure                                      */
85526 
85527 /* CC2 @Bit 2 : Capture/compare register number */
85528   #define UICR_GRTC_CC_SECURE_CC2_Pos (2UL)          /*!< Position of CC2 field.                                               */
85529   #define UICR_GRTC_CC_SECURE_CC2_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC2_Pos) /*!< Bit mask of CC2 field.                       */
85530   #define UICR_GRTC_CC_SECURE_CC2_Min (0x0UL)        /*!< Min enumerator value of CC2 field.                                   */
85531   #define UICR_GRTC_CC_SECURE_CC2_Max (0x1UL)        /*!< Max enumerator value of CC2 field.                                   */
85532   #define UICR_GRTC_CC_SECURE_CC2_Secure (0x1UL)     /*!< The CC register 2 is secure                                          */
85533   #define UICR_GRTC_CC_SECURE_CC2_NonSecure (0x0UL)  /*!< The CC register 2 is non-secure                                      */
85534 
85535 /* CC3 @Bit 3 : Capture/compare register number */
85536   #define UICR_GRTC_CC_SECURE_CC3_Pos (3UL)          /*!< Position of CC3 field.                                               */
85537   #define UICR_GRTC_CC_SECURE_CC3_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC3_Pos) /*!< Bit mask of CC3 field.                       */
85538   #define UICR_GRTC_CC_SECURE_CC3_Min (0x0UL)        /*!< Min enumerator value of CC3 field.                                   */
85539   #define UICR_GRTC_CC_SECURE_CC3_Max (0x1UL)        /*!< Max enumerator value of CC3 field.                                   */
85540   #define UICR_GRTC_CC_SECURE_CC3_Secure (0x1UL)     /*!< The CC register 3 is secure                                          */
85541   #define UICR_GRTC_CC_SECURE_CC3_NonSecure (0x0UL)  /*!< The CC register 3 is non-secure                                      */
85542 
85543 /* CC4 @Bit 4 : Capture/compare register number */
85544   #define UICR_GRTC_CC_SECURE_CC4_Pos (4UL)          /*!< Position of CC4 field.                                               */
85545   #define UICR_GRTC_CC_SECURE_CC4_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC4_Pos) /*!< Bit mask of CC4 field.                       */
85546   #define UICR_GRTC_CC_SECURE_CC4_Min (0x0UL)        /*!< Min enumerator value of CC4 field.                                   */
85547   #define UICR_GRTC_CC_SECURE_CC4_Max (0x1UL)        /*!< Max enumerator value of CC4 field.                                   */
85548   #define UICR_GRTC_CC_SECURE_CC4_Secure (0x1UL)     /*!< The CC register 4 is secure                                          */
85549   #define UICR_GRTC_CC_SECURE_CC4_NonSecure (0x0UL)  /*!< The CC register 4 is non-secure                                      */
85550 
85551 /* CC5 @Bit 5 : Capture/compare register number */
85552   #define UICR_GRTC_CC_SECURE_CC5_Pos (5UL)          /*!< Position of CC5 field.                                               */
85553   #define UICR_GRTC_CC_SECURE_CC5_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC5_Pos) /*!< Bit mask of CC5 field.                       */
85554   #define UICR_GRTC_CC_SECURE_CC5_Min (0x0UL)        /*!< Min enumerator value of CC5 field.                                   */
85555   #define UICR_GRTC_CC_SECURE_CC5_Max (0x1UL)        /*!< Max enumerator value of CC5 field.                                   */
85556   #define UICR_GRTC_CC_SECURE_CC5_Secure (0x1UL)     /*!< The CC register 5 is secure                                          */
85557   #define UICR_GRTC_CC_SECURE_CC5_NonSecure (0x0UL)  /*!< The CC register 5 is non-secure                                      */
85558 
85559 /* CC6 @Bit 6 : Capture/compare register number */
85560   #define UICR_GRTC_CC_SECURE_CC6_Pos (6UL)          /*!< Position of CC6 field.                                               */
85561   #define UICR_GRTC_CC_SECURE_CC6_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC6_Pos) /*!< Bit mask of CC6 field.                       */
85562   #define UICR_GRTC_CC_SECURE_CC6_Min (0x0UL)        /*!< Min enumerator value of CC6 field.                                   */
85563   #define UICR_GRTC_CC_SECURE_CC6_Max (0x1UL)        /*!< Max enumerator value of CC6 field.                                   */
85564   #define UICR_GRTC_CC_SECURE_CC6_Secure (0x1UL)     /*!< The CC register 6 is secure                                          */
85565   #define UICR_GRTC_CC_SECURE_CC6_NonSecure (0x0UL)  /*!< The CC register 6 is non-secure                                      */
85566 
85567 /* CC7 @Bit 7 : Capture/compare register number */
85568   #define UICR_GRTC_CC_SECURE_CC7_Pos (7UL)          /*!< Position of CC7 field.                                               */
85569   #define UICR_GRTC_CC_SECURE_CC7_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC7_Pos) /*!< Bit mask of CC7 field.                       */
85570   #define UICR_GRTC_CC_SECURE_CC7_Min (0x0UL)        /*!< Min enumerator value of CC7 field.                                   */
85571   #define UICR_GRTC_CC_SECURE_CC7_Max (0x1UL)        /*!< Max enumerator value of CC7 field.                                   */
85572   #define UICR_GRTC_CC_SECURE_CC7_Secure (0x1UL)     /*!< The CC register 7 is secure                                          */
85573   #define UICR_GRTC_CC_SECURE_CC7_NonSecure (0x0UL)  /*!< The CC register 7 is non-secure                                      */
85574 
85575 /* CC8 @Bit 8 : Capture/compare register number */
85576   #define UICR_GRTC_CC_SECURE_CC8_Pos (8UL)          /*!< Position of CC8 field.                                               */
85577   #define UICR_GRTC_CC_SECURE_CC8_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC8_Pos) /*!< Bit mask of CC8 field.                       */
85578   #define UICR_GRTC_CC_SECURE_CC8_Min (0x0UL)        /*!< Min enumerator value of CC8 field.                                   */
85579   #define UICR_GRTC_CC_SECURE_CC8_Max (0x1UL)        /*!< Max enumerator value of CC8 field.                                   */
85580   #define UICR_GRTC_CC_SECURE_CC8_Secure (0x1UL)     /*!< The CC register 8 is secure                                          */
85581   #define UICR_GRTC_CC_SECURE_CC8_NonSecure (0x0UL)  /*!< The CC register 8 is non-secure                                      */
85582 
85583 /* CC9 @Bit 9 : Capture/compare register number */
85584   #define UICR_GRTC_CC_SECURE_CC9_Pos (9UL)          /*!< Position of CC9 field.                                               */
85585   #define UICR_GRTC_CC_SECURE_CC9_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC9_Pos) /*!< Bit mask of CC9 field.                       */
85586   #define UICR_GRTC_CC_SECURE_CC9_Min (0x0UL)        /*!< Min enumerator value of CC9 field.                                   */
85587   #define UICR_GRTC_CC_SECURE_CC9_Max (0x1UL)        /*!< Max enumerator value of CC9 field.                                   */
85588   #define UICR_GRTC_CC_SECURE_CC9_Secure (0x1UL)     /*!< The CC register 9 is secure                                          */
85589   #define UICR_GRTC_CC_SECURE_CC9_NonSecure (0x0UL)  /*!< The CC register 9 is non-secure                                      */
85590 
85591 /* CC10 @Bit 10 : Capture/compare register number */
85592   #define UICR_GRTC_CC_SECURE_CC10_Pos (10UL)        /*!< Position of CC10 field.                                              */
85593   #define UICR_GRTC_CC_SECURE_CC10_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC10_Pos) /*!< Bit mask of CC10 field.                    */
85594   #define UICR_GRTC_CC_SECURE_CC10_Min (0x0UL)       /*!< Min enumerator value of CC10 field.                                  */
85595   #define UICR_GRTC_CC_SECURE_CC10_Max (0x1UL)       /*!< Max enumerator value of CC10 field.                                  */
85596   #define UICR_GRTC_CC_SECURE_CC10_Secure (0x1UL)    /*!< The CC register 10 is secure                                         */
85597   #define UICR_GRTC_CC_SECURE_CC10_NonSecure (0x0UL) /*!< The CC register 10 is non-secure                                     */
85598 
85599 /* CC11 @Bit 11 : Capture/compare register number */
85600   #define UICR_GRTC_CC_SECURE_CC11_Pos (11UL)        /*!< Position of CC11 field.                                              */
85601   #define UICR_GRTC_CC_SECURE_CC11_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC11_Pos) /*!< Bit mask of CC11 field.                    */
85602   #define UICR_GRTC_CC_SECURE_CC11_Min (0x0UL)       /*!< Min enumerator value of CC11 field.                                  */
85603   #define UICR_GRTC_CC_SECURE_CC11_Max (0x1UL)       /*!< Max enumerator value of CC11 field.                                  */
85604   #define UICR_GRTC_CC_SECURE_CC11_Secure (0x1UL)    /*!< The CC register 11 is secure                                         */
85605   #define UICR_GRTC_CC_SECURE_CC11_NonSecure (0x0UL) /*!< The CC register 11 is non-secure                                     */
85606 
85607 /* CC12 @Bit 12 : Capture/compare register number */
85608   #define UICR_GRTC_CC_SECURE_CC12_Pos (12UL)        /*!< Position of CC12 field.                                              */
85609   #define UICR_GRTC_CC_SECURE_CC12_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC12_Pos) /*!< Bit mask of CC12 field.                    */
85610   #define UICR_GRTC_CC_SECURE_CC12_Min (0x0UL)       /*!< Min enumerator value of CC12 field.                                  */
85611   #define UICR_GRTC_CC_SECURE_CC12_Max (0x1UL)       /*!< Max enumerator value of CC12 field.                                  */
85612   #define UICR_GRTC_CC_SECURE_CC12_Secure (0x1UL)    /*!< The CC register 12 is secure                                         */
85613   #define UICR_GRTC_CC_SECURE_CC12_NonSecure (0x0UL) /*!< The CC register 12 is non-secure                                     */
85614 
85615 /* CC13 @Bit 13 : Capture/compare register number */
85616   #define UICR_GRTC_CC_SECURE_CC13_Pos (13UL)        /*!< Position of CC13 field.                                              */
85617   #define UICR_GRTC_CC_SECURE_CC13_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC13_Pos) /*!< Bit mask of CC13 field.                    */
85618   #define UICR_GRTC_CC_SECURE_CC13_Min (0x0UL)       /*!< Min enumerator value of CC13 field.                                  */
85619   #define UICR_GRTC_CC_SECURE_CC13_Max (0x1UL)       /*!< Max enumerator value of CC13 field.                                  */
85620   #define UICR_GRTC_CC_SECURE_CC13_Secure (0x1UL)    /*!< The CC register 13 is secure                                         */
85621   #define UICR_GRTC_CC_SECURE_CC13_NonSecure (0x0UL) /*!< The CC register 13 is non-secure                                     */
85622 
85623 /* CC14 @Bit 14 : Capture/compare register number */
85624   #define UICR_GRTC_CC_SECURE_CC14_Pos (14UL)        /*!< Position of CC14 field.                                              */
85625   #define UICR_GRTC_CC_SECURE_CC14_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC14_Pos) /*!< Bit mask of CC14 field.                    */
85626   #define UICR_GRTC_CC_SECURE_CC14_Min (0x0UL)       /*!< Min enumerator value of CC14 field.                                  */
85627   #define UICR_GRTC_CC_SECURE_CC14_Max (0x1UL)       /*!< Max enumerator value of CC14 field.                                  */
85628   #define UICR_GRTC_CC_SECURE_CC14_Secure (0x1UL)    /*!< The CC register 14 is secure                                         */
85629   #define UICR_GRTC_CC_SECURE_CC14_NonSecure (0x0UL) /*!< The CC register 14 is non-secure                                     */
85630 
85631 /* CC15 @Bit 15 : Capture/compare register number */
85632   #define UICR_GRTC_CC_SECURE_CC15_Pos (15UL)        /*!< Position of CC15 field.                                              */
85633   #define UICR_GRTC_CC_SECURE_CC15_Msk (0x1UL << UICR_GRTC_CC_SECURE_CC15_Pos) /*!< Bit mask of CC15 field.                    */
85634   #define UICR_GRTC_CC_SECURE_CC15_Min (0x0UL)       /*!< Min enumerator value of CC15 field.                                  */
85635   #define UICR_GRTC_CC_SECURE_CC15_Max (0x1UL)       /*!< Max enumerator value of CC15 field.                                  */
85636   #define UICR_GRTC_CC_SECURE_CC15_Secure (0x1UL)    /*!< The CC register 15 is secure                                         */
85637   #define UICR_GRTC_CC_SECURE_CC15_NonSecure (0x0UL) /*!< The CC register 15 is non-secure                                     */
85638 
85639 
85640 
85641 /* ==================================================== Struct UICR_GRTC ===================================================== */
85642 /**
85643   * @brief GRTC [UICR_GRTC] (unspecified)
85644   */
85645 typedef struct {
85646   __IOM NRF_UICR_GRTC_CC_Type CC;                    /*!< (@ 0x00000000) (unspecified)                                         */
85647 } NRF_UICR_GRTC_Type;                                /*!< Size = 8 (0x008)                                                     */
85648 
85649 
85650 /* =================================================== Struct UICR_MAILBOX =================================================== */
85651 /**
85652   * @brief MAILBOX [UICR_MAILBOX] (unspecified)
85653   */
85654 typedef struct {
85655   __IOM uint32_t  ADDRESS;                           /*!< (@ 0x00000000) Memory start address of mailbox n                     */
85656   __IOM uint32_t  CONFIG;                            /*!< (@ 0x00000004) Configuration of mailbox n                            */
85657 } NRF_UICR_MAILBOX_Type;                             /*!< Size = 8 (0x008)                                                     */
85658   #define UICR_MAILBOX_MaxCount (8UL)                /*!< Size of MAILBOX[8] array.                                            */
85659   #define UICR_MAILBOX_MaxIndex (7UL)                /*!< Max index of MAILBOX[8] array.                                       */
85660   #define UICR_MAILBOX_MinIndex (0UL)                /*!< Min index of MAILBOX[8] array.                                       */
85661 
85662 /* UICR_MAILBOX_ADDRESS: Memory start address of mailbox n */
85663   #define UICR_MAILBOX_ADDRESS_ResetValue (0xFFFFFFFFUL) /*!< Reset value of ADDRESS register.                                 */
85664 
85665 /* ADDRESS @Bits 0..31 : Memory address */
85666   #define UICR_MAILBOX_ADDRESS_ADDRESS_Pos (0UL)     /*!< Position of ADDRESS field.                                           */
85667   #define UICR_MAILBOX_ADDRESS_ADDRESS_Msk (0xFFFFFFFFUL << UICR_MAILBOX_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field.  */
85668 
85669 
85670 /* UICR_MAILBOX_CONFIG: Configuration of mailbox n */
85671   #define UICR_MAILBOX_CONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of CONFIG register.                                   */
85672 
85673 /* SECURE @Bit 3 : Permission */
85674   #define UICR_MAILBOX_CONFIG_SECURE_Pos (3UL)       /*!< Position of SECURE field.                                            */
85675   #define UICR_MAILBOX_CONFIG_SECURE_Msk (0x1UL << UICR_MAILBOX_CONFIG_SECURE_Pos) /*!< Bit mask of SECURE field.              */
85676   #define UICR_MAILBOX_CONFIG_SECURE_Min (0x0UL)     /*!< Min enumerator value of SECURE field.                                */
85677   #define UICR_MAILBOX_CONFIG_SECURE_Max (0x1UL)     /*!< Max enumerator value of SECURE field.                                */
85678   #define UICR_MAILBOX_CONFIG_SECURE_Secure (0x1UL)  /*!< The mailbox memory is secure                                         */
85679   #define UICR_MAILBOX_CONFIG_SECURE_NonSecure (0x0UL) /*!< The mailbox memory is non-secure                                   */
85680 
85681 /* OWNERID @Bits 8..11 : Remote owner identification */
85682   #define UICR_MAILBOX_CONFIG_OWNERID_Pos (8UL)      /*!< Position of OWNERID field.                                           */
85683   #define UICR_MAILBOX_CONFIG_OWNERID_Msk (0xFUL << UICR_MAILBOX_CONFIG_OWNERID_Pos) /*!< Bit mask of OWNERID field.           */
85684   #define UICR_MAILBOX_CONFIG_OWNERID_Min (0x0UL)    /*!< Min value of OWNERID field.                                          */
85685   #define UICR_MAILBOX_CONFIG_OWNERID_Max (0xFUL)    /*!< Max size of OWNERID field.                                           */
85686 
85687 /* SIZE @Bits 16..31 : Memory size */
85688   #define UICR_MAILBOX_CONFIG_SIZE_Pos (16UL)        /*!< Position of SIZE field.                                              */
85689   #define UICR_MAILBOX_CONFIG_SIZE_Msk (0xFFFFUL << UICR_MAILBOX_CONFIG_SIZE_Pos) /*!< Bit mask of SIZE field.                 */
85690 
85691 
85692 
85693 /* ================================================ Struct UICR_TRACE_ETBSINK ================================================ */
85694 /**
85695   * @brief ETBSINK [UICR_TRACE_ETBSINK] (unspecified)
85696   */
85697 typedef struct {
85698   __IOM uint32_t  SOURCES;                           /*!< (@ 0x00000000) (unspecified)                                         */
85699 } NRF_UICR_TRACE_ETBSINK_Type;                       /*!< Size = 4 (0x004)                                                     */
85700 
85701 /* UICR_TRACE_ETBSINK_SOURCES: (unspecified) */
85702   #define UICR_TRACE_ETBSINK_SOURCES_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SOURCES register.                           */
85703 
85704 /* STMMAINCORE @Bit 0 : STM trace from the domain main CPU */
85705   #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Pos (0UL) /*!< Position of STMMAINCORE field.                                 */
85706   #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Pos) /*!< Bit mask of
85707                                                                             STMMAINCORE field.*/
85708   #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Min (0x0UL) /*!< Min enumerator value of STMMAINCORE field.                   */
85709   #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Max (0x1UL) /*!< Max enumerator value of STMMAINCORE field.                   */
85710   #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_NotRequested (0x1UL) /*!< Not Requested                                       */
85711   #define UICR_TRACE_ETBSINK_SOURCES_STMMAINCORE_Requested (0x0UL) /*!< Requested                                              */
85712 
85713 /* ETMMAINCORE @Bit 1 : ETM trace from the domain main CPU */
85714   #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Pos (1UL) /*!< Position of ETMMAINCORE field.                                 */
85715   #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Pos) /*!< Bit mask of
85716                                                                             ETMMAINCORE field.*/
85717   #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Min (0x0UL) /*!< Min enumerator value of ETMMAINCORE field.                   */
85718   #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Max (0x1UL) /*!< Max enumerator value of ETMMAINCORE field.                   */
85719   #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_NotRequested (0x1UL) /*!< Not Requested                                       */
85720   #define UICR_TRACE_ETBSINK_SOURCES_ETMMAINCORE_Requested (0x0UL) /*!< Requested                                              */
85721 
85722 /* STMHWEVENTS @Bit 2 : STM HW events trace */
85723   #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Pos (2UL) /*!< Position of STMHWEVENTS field.                                 */
85724   #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Pos) /*!< Bit mask of
85725                                                                             STMHWEVENTS field.*/
85726   #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Min (0x0UL) /*!< Min enumerator value of STMHWEVENTS field.                   */
85727   #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Max (0x1UL) /*!< Max enumerator value of STMHWEVENTS field.                   */
85728   #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_NotRequested (0x1UL) /*!< Not Requested                                       */
85729   #define UICR_TRACE_ETBSINK_SOURCES_STMHWEVENTS_Requested (0x0UL) /*!< Requested                                              */
85730 
85731 /* STMPPR @Bit 3 : STM trace from PPR CPU */
85732   #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Pos (3UL) /*!< Position of STMPPR field.                                           */
85733   #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_STMPPR_Pos) /*!< Bit mask of STMPPR field.*/
85734   #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Min (0x0UL) /*!< Min enumerator value of STMPPR field.                             */
85735   #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Max (0x1UL) /*!< Max enumerator value of STMPPR field.                             */
85736   #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_NotRequested (0x1UL) /*!< Not Requested                                            */
85737   #define UICR_TRACE_ETBSINK_SOURCES_STMPPR_Requested (0x0UL) /*!< Requested                                                   */
85738 
85739 /* STMFLPR @Bit 4 : STM trace from FLPR CPU */
85740   #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Pos (4UL) /*!< Position of STMFLPR field.                                         */
85741   #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Msk (0x1UL << UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Pos) /*!< Bit mask of STMFLPR
85742                                                                             field.*/
85743   #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Min (0x0UL) /*!< Min enumerator value of STMFLPR field.                           */
85744   #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Max (0x1UL) /*!< Max enumerator value of STMFLPR field.                           */
85745   #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_NotRequested (0x1UL) /*!< Not Requested                                           */
85746   #define UICR_TRACE_ETBSINK_SOURCES_STMFLPR_Requested (0x0UL) /*!< Requested                                                  */
85747 
85748 
85749 
85750 /* =============================================== Struct UICR_TRACE_TPIUSINK ================================================ */
85751 /**
85752   * @brief TPIUSINK [UICR_TRACE_TPIUSINK] (unspecified)
85753   */
85754 typedef struct {
85755   __IOM uint32_t  SOURCES;                           /*!< (@ 0x00000000) (unspecified)                                         */
85756 } NRF_UICR_TRACE_TPIUSINK_Type;                      /*!< Size = 4 (0x004)                                                     */
85757 
85758 /* UICR_TRACE_TPIUSINK_SOURCES: (unspecified) */
85759   #define UICR_TRACE_TPIUSINK_SOURCES_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SOURCES register.                          */
85760 
85761 /* STMMAINCORE @Bit 0 : STM trace from the domain main CPU */
85762   #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Pos (0UL) /*!< Position of STMMAINCORE field.                                */
85763   #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Pos) /*!< Bit mask of
85764                                                                             STMMAINCORE field.*/
85765   #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Min (0x0UL) /*!< Min enumerator value of STMMAINCORE field.                  */
85766   #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Max (0x1UL) /*!< Max enumerator value of STMMAINCORE field.                  */
85767   #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_NotRequested (0x1UL) /*!< Not Requested                                      */
85768   #define UICR_TRACE_TPIUSINK_SOURCES_STMMAINCORE_Requested (0x0UL) /*!< Requested                                             */
85769 
85770 /* ETMMAINCORE @Bit 1 : ETM trace from the domain main CPU */
85771   #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Pos (1UL) /*!< Position of ETMMAINCORE field.                                */
85772   #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Pos) /*!< Bit mask of
85773                                                                             ETMMAINCORE field.*/
85774   #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Min (0x0UL) /*!< Min enumerator value of ETMMAINCORE field.                  */
85775   #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Max (0x1UL) /*!< Max enumerator value of ETMMAINCORE field.                  */
85776   #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_NotRequested (0x1UL) /*!< Not Requested                                      */
85777   #define UICR_TRACE_TPIUSINK_SOURCES_ETMMAINCORE_Requested (0x0UL) /*!< Requested                                             */
85778 
85779 /* STMHWEVENTS @Bit 2 : STM HW events trace */
85780   #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Pos (2UL) /*!< Position of STMHWEVENTS field.                                */
85781   #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Pos) /*!< Bit mask of
85782                                                                             STMHWEVENTS field.*/
85783   #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Min (0x0UL) /*!< Min enumerator value of STMHWEVENTS field.                  */
85784   #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Max (0x1UL) /*!< Max enumerator value of STMHWEVENTS field.                  */
85785   #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_NotRequested (0x1UL) /*!< Not Requested                                      */
85786   #define UICR_TRACE_TPIUSINK_SOURCES_STMHWEVENTS_Requested (0x0UL) /*!< Requested                                             */
85787 
85788 /* STMPPR @Bit 3 : STM trace from PPR CPU */
85789   #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Pos (3UL) /*!< Position of STMPPR field.                                          */
85790   #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Pos) /*!< Bit mask of STMPPR
85791                                                                             field.*/
85792   #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Min (0x0UL) /*!< Min enumerator value of STMPPR field.                            */
85793   #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Max (0x1UL) /*!< Max enumerator value of STMPPR field.                            */
85794   #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_NotRequested (0x1UL) /*!< Not Requested                                           */
85795   #define UICR_TRACE_TPIUSINK_SOURCES_STMPPR_Requested (0x0UL) /*!< Requested                                                  */
85796 
85797 /* STMFLPR @Bit 4 : STM trace from FLPR CPU */
85798   #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Pos (4UL) /*!< Position of STMFLPR field.                                        */
85799   #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Msk (0x1UL << UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Pos) /*!< Bit mask of STMFLPR
85800                                                                             field.*/
85801   #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Min (0x0UL) /*!< Min enumerator value of STMFLPR field.                          */
85802   #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Max (0x1UL) /*!< Max enumerator value of STMFLPR field.                          */
85803   #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_NotRequested (0x1UL) /*!< Not Requested                                          */
85804   #define UICR_TRACE_TPIUSINK_SOURCES_STMFLPR_Requested (0x0UL) /*!< Requested                                                 */
85805 
85806 
85807 
85808 /* ================================================ Struct UICR_TRACE_ETRSINK ================================================ */
85809 /**
85810   * @brief ETRSINK [UICR_TRACE_ETRSINK] (unspecified)
85811   */
85812 typedef struct {
85813   __IOM uint32_t  SOURCES;                           /*!< (@ 0x00000000) (unspecified)                                         */
85814 } NRF_UICR_TRACE_ETRSINK_Type;                       /*!< Size = 4 (0x004)                                                     */
85815 
85816 /* UICR_TRACE_ETRSINK_SOURCES: (unspecified) */
85817   #define UICR_TRACE_ETRSINK_SOURCES_ResetValue (0xFFFFFFFFUL) /*!< Reset value of SOURCES register.                           */
85818 
85819 /* STMMAINCORE @Bit 0 : STM trace from the domain main CPU */
85820   #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Pos (0UL) /*!< Position of STMMAINCORE field.                                 */
85821   #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Pos) /*!< Bit mask of
85822                                                                             STMMAINCORE field.*/
85823   #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Min (0x0UL) /*!< Min enumerator value of STMMAINCORE field.                   */
85824   #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Max (0x1UL) /*!< Max enumerator value of STMMAINCORE field.                   */
85825   #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_NotRequested (0x1UL) /*!< Not Requested                                       */
85826   #define UICR_TRACE_ETRSINK_SOURCES_STMMAINCORE_Requested (0x0UL) /*!< Requested                                              */
85827 
85828 /* ETMMAINCORE @Bit 1 : ETM trace from the domain main CPU */
85829   #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Pos (1UL) /*!< Position of ETMMAINCORE field.                                 */
85830   #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Pos) /*!< Bit mask of
85831                                                                             ETMMAINCORE field.*/
85832   #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Min (0x0UL) /*!< Min enumerator value of ETMMAINCORE field.                   */
85833   #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Max (0x1UL) /*!< Max enumerator value of ETMMAINCORE field.                   */
85834   #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_NotRequested (0x1UL) /*!< Not Requested                                       */
85835   #define UICR_TRACE_ETRSINK_SOURCES_ETMMAINCORE_Requested (0x0UL) /*!< Requested                                              */
85836 
85837 /* STMHWEVENTS @Bit 2 : STM HW events trace */
85838   #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Pos (2UL) /*!< Position of STMHWEVENTS field.                                 */
85839   #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Pos) /*!< Bit mask of
85840                                                                             STMHWEVENTS field.*/
85841   #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Min (0x0UL) /*!< Min enumerator value of STMHWEVENTS field.                   */
85842   #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Max (0x1UL) /*!< Max enumerator value of STMHWEVENTS field.                   */
85843   #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_NotRequested (0x1UL) /*!< Not Requested                                       */
85844   #define UICR_TRACE_ETRSINK_SOURCES_STMHWEVENTS_Requested (0x0UL) /*!< Requested                                              */
85845 
85846 /* STMPPR @Bit 3 : STM trace from PPR CPU */
85847   #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Pos (3UL) /*!< Position of STMPPR field.                                           */
85848   #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_STMPPR_Pos) /*!< Bit mask of STMPPR field.*/
85849   #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Min (0x0UL) /*!< Min enumerator value of STMPPR field.                             */
85850   #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Max (0x1UL) /*!< Max enumerator value of STMPPR field.                             */
85851   #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_NotRequested (0x1UL) /*!< Not Requested                                            */
85852   #define UICR_TRACE_ETRSINK_SOURCES_STMPPR_Requested (0x0UL) /*!< Requested                                                   */
85853 
85854 /* STMFLPR @Bit 4 : STM trace from FLPR CPU */
85855   #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Pos (4UL) /*!< Position of STMFLPR field.                                         */
85856   #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Msk (0x1UL << UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Pos) /*!< Bit mask of STMFLPR
85857                                                                             field.*/
85858   #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Min (0x0UL) /*!< Min enumerator value of STMFLPR field.                           */
85859   #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Max (0x1UL) /*!< Max enumerator value of STMFLPR field.                           */
85860   #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_NotRequested (0x1UL) /*!< Not Requested                                           */
85861   #define UICR_TRACE_ETRSINK_SOURCES_STMFLPR_Requested (0x0UL) /*!< Requested                                                  */
85862 
85863 
85864 
85865 /* ==================================================== Struct UICR_TRACE ==================================================== */
85866 /**
85867   * @brief TRACE [UICR_TRACE] (unspecified)
85868   */
85869 typedef struct {
85870   __IOM NRF_UICR_TRACE_ETBSINK_Type ETBSINK;         /*!< (@ 0x00000000) (unspecified)                                         */
85871   __IOM NRF_UICR_TRACE_TPIUSINK_Type TPIUSINK;       /*!< (@ 0x00000004) (unspecified)                                         */
85872   __IOM NRF_UICR_TRACE_ETRSINK_Type ETRSINK;         /*!< (@ 0x00000008) (unspecified)                                         */
85873   __IOM uint32_t  PORTCONFIG;                        /*!< (@ 0x0000000C) Trace port speed configuration                        */
85874 } NRF_UICR_TRACE_Type;                               /*!< Size = 16 (0x010)                                                    */
85875 
85876 /* UICR_TRACE_PORTCONFIG: Trace port speed configuration */
85877   #define UICR_TRACE_PORTCONFIG_ResetValue (0xFFFFFFFFUL) /*!< Reset value of PORTCONFIG register.                             */
85878 
85879 /* PORTCONFIG @Bits 0..1 : (unspecified) */
85880   #define UICR_TRACE_PORTCONFIG_PORTCONFIG_Pos (0UL) /*!< Position of PORTCONFIG field.                                        */
85881   #define UICR_TRACE_PORTCONFIG_PORTCONFIG_Msk (0x3UL << UICR_TRACE_PORTCONFIG_PORTCONFIG_Pos) /*!< Bit mask of PORTCONFIG
85882                                                                             field.*/
85883   #define UICR_TRACE_PORTCONFIG_PORTCONFIG_Min (0x0UL) /*!< Min enumerator value of PORTCONFIG field.                          */
85884   #define UICR_TRACE_PORTCONFIG_PORTCONFIG_Max (0x3UL) /*!< Max enumerator value of PORTCONFIG field.                          */
85885   #define UICR_TRACE_PORTCONFIG_PORTCONFIG_FullSpeed (0x3UL) /*!< Full speed                                                   */
85886   #define UICR_TRACE_PORTCONFIG_PORTCONFIG_HalfSpeed (0x2UL) /*!< Half speed                                                   */
85887   #define UICR_TRACE_PORTCONFIG_PORTCONFIG_QuarterSpeed (0x1UL) /*!< One quarter speed                                         */
85888   #define UICR_TRACE_PORTCONFIG_PORTCONFIG_EightSpeed (0x0UL) /*!< One eigth speed                                             */
85889 
85890 
85891 /* ======================================================= Struct UICR ======================================================= */
85892 /**
85893   * @brief User information configuration registers
85894   */
85895   typedef struct {                                   /*!< UICR Structure                                                       */
85896     __IOM NRF_UICR_MEM_Type MEM[16];                 /*!< (@ 0x00000000) (unspecified)                                         */
85897     __IM uint32_t RESERVED[32];
85898     __IOM NRF_UICR_PERIPH_Type PERIPH[192];          /*!< (@ 0x00000100) (unspecified)                                         */
85899     __IM uint32_t RESERVED1[32];
85900     __IOM NRF_UICR_GPIOTE_Type GPIOTE[4];            /*!< (@ 0x00000480) (unspecified)                                         */
85901     __IOM NRF_UICR_IPCT_Type IPCT;                   /*!< (@ 0x000004B0) (unspecified)                                         */
85902     __IOM NRF_UICR_DPPI_Type DPPI;                   /*!< (@ 0x000004E0) (unspecified)                                         */
85903     __IM uint32_t RESERVED2[2];
85904     __IOM NRF_UICR_GRTC_Type GRTC;                   /*!< (@ 0x00000660) (unspecified)                                         */
85905     __IM uint32_t RESERVED3[6];
85906     __IOM uint32_t IPCMAP[16];                       /*!< (@ 0x00000680) Request configuration for the channel n of IPCMAP     */
85907     __IM uint32_t RESERVED4[16];
85908     __IOM NRF_UICR_MAILBOX_Type MAILBOX[8];          /*!< (@ 0x00000700) (unspecified)                                         */
85909     __IOM NRF_UICR_TRACE_Type TRACE;                 /*!< (@ 0x00000740) (unspecified)                                         */
85910     __IM uint32_t RESERVED5[12];
85911     __IOM uint32_t INITSVTOR;                        /*!< (@ 0x00000780) Initial value of the secure VTOR (Vector Table Offset
85912                                                                          Register) after CPU reset.*/
85913     __IOM uint32_t INITNSVTOR;                       /*!< (@ 0x00000784) Initial value of the non-secure VTOR (Vector Table
85914                                                                          Offset Register).*/
85915     __IM uint32_t RESERVED6[29];
85916     __IOM uint32_t PTREXTUICR;                       /*!< (@ 0x000007FC) Pointer to extended UICR.                             */
85917   } NRF_UICR_Type;                                   /*!< Size = 2048 (0x800)                                                  */
85918 
85919 /* UICR_IPCMAP: Request configuration for the channel n of IPCMAP */
85920   #define UICR_IPCMAP_MaxCount (16UL)                /*!< Max size of IPCMAP[16] array.                                        */
85921   #define UICR_IPCMAP_MaxIndex (15UL)                /*!< Max index of IPCMAP[16] array.                                       */
85922   #define UICR_IPCMAP_MinIndex (0UL)                 /*!< Min index of IPCMAP[16] array.                                       */
85923   #define UICR_IPCMAP_ResetValue (0xFFFFFFFFUL)      /*!< Reset value of IPCMAP[16] register.                                  */
85924 
85925 /* IPCTCHSINK @Bits 0..7 : IPCT channel number (sink side) */
85926   #define UICR_IPCMAP_IPCTCHSINK_Pos (0UL)           /*!< Position of IPCTCHSINK field.                                        */
85927   #define UICR_IPCMAP_IPCTCHSINK_Msk (0xFFUL << UICR_IPCMAP_IPCTCHSINK_Pos) /*!< Bit mask of IPCTCHSINK field.                 */
85928 
85929 /* DOMAINIDSINK @Bits 8..11 : Domain ID (sink side) */
85930   #define UICR_IPCMAP_DOMAINIDSINK_Pos (8UL)         /*!< Position of DOMAINIDSINK field.                                      */
85931   #define UICR_IPCMAP_DOMAINIDSINK_Msk (0xFUL << UICR_IPCMAP_DOMAINIDSINK_Pos) /*!< Bit mask of DOMAINIDSINK field.            */
85932 
85933 /* IPCTCHSOURCE @Bits 16..23 : IPCT channel number (source side) */
85934   #define UICR_IPCMAP_IPCTCHSOURCE_Pos (16UL)        /*!< Position of IPCTCHSOURCE field.                                      */
85935   #define UICR_IPCMAP_IPCTCHSOURCE_Msk (0xFFUL << UICR_IPCMAP_IPCTCHSOURCE_Pos) /*!< Bit mask of IPCTCHSOURCE field.           */
85936 
85937 /* DOMAINIDSOURCE @Bits 24..27 : Domain ID (source side) */
85938   #define UICR_IPCMAP_DOMAINIDSOURCE_Pos (24UL)      /*!< Position of DOMAINIDSOURCE field.                                    */
85939   #define UICR_IPCMAP_DOMAINIDSOURCE_Msk (0xFUL << UICR_IPCMAP_DOMAINIDSOURCE_Pos) /*!< Bit mask of DOMAINIDSOURCE field.      */
85940 
85941 
85942 /* UICR_INITSVTOR: Initial value of the secure VTOR (Vector Table Offset Register) after CPU reset. */
85943   #define UICR_INITSVTOR_ResetValue (0xFFFFFFFFUL)   /*!< Reset value of INITSVTOR register.                                   */
85944 
85945 /* INITSVTOR @Bits 0..31 : Initial value of the VTOR. */
85946   #define UICR_INITSVTOR_INITSVTOR_Pos (0UL)         /*!< Position of INITSVTOR field.                                         */
85947   #define UICR_INITSVTOR_INITSVTOR_Msk (0xFFFFFFFFUL << UICR_INITSVTOR_INITSVTOR_Pos) /*!< Bit mask of INITSVTOR field.        */
85948 
85949 
85950 /* UICR_INITNSVTOR: Initial value of the non-secure VTOR (Vector Table Offset Register). */
85951   #define UICR_INITNSVTOR_ResetValue (0xFFFFFFFFUL)  /*!< Reset value of INITNSVTOR register.                                  */
85952 
85953 /* INITNSVTOR @Bits 0..31 : Initial value of the VTOR. */
85954   #define UICR_INITNSVTOR_INITNSVTOR_Pos (0UL)       /*!< Position of INITNSVTOR field.                                        */
85955   #define UICR_INITNSVTOR_INITNSVTOR_Msk (0xFFFFFFFFUL << UICR_INITNSVTOR_INITNSVTOR_Pos) /*!< Bit mask of INITNSVTOR field.   */
85956 
85957 
85958 /* UICR_PTREXTUICR: Pointer to extended UICR. */
85959   #define UICR_PTREXTUICR_ResetValue (0xFFFFFFFFUL)  /*!< Reset value of PTREXTUICR register.                                  */
85960 
85961 /* PTREXTUICR @Bits 0..31 : Pointer to extended UICR. */
85962   #define UICR_PTREXTUICR_PTREXTUICR_Pos (0UL)       /*!< Position of PTREXTUICR field.                                        */
85963   #define UICR_PTREXTUICR_PTREXTUICR_Msk (0xFFFFFFFFUL << UICR_PTREXTUICR_PTREXTUICR_Pos) /*!< Bit mask of PTREXTUICR field.   */
85964 
85965 
85966 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
85967 
85968 /* =========================================================================================================================== */
85969 /* ================                                           USBHS                                           ================ */
85970 /* =========================================================================================================================== */
85971 
85972 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
85973 /* ====================================================== Struct USBHS ======================================================= */
85974 /**
85975   * @brief USBHS
85976   */
85977   typedef struct {                                   /*!< USBHS Structure                                                      */
85978     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start the USB peripheral.                             */
85979     __IM uint32_t RESERVED[63];
85980     __IOM uint32_t EVENTS_CORE;                      /*!< (@ 0x00000100) Event indicating that interrupt triggered at USBHS
85981                                                                          core*/
85982     __IM uint32_t RESERVED1[127];
85983     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
85984     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
85985     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
85986     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
85987     __IM uint32_t RESERVED2[60];
85988     __IOM uint32_t ENABLE;                           /*!< (@ 0x00000400) Enable USB peripheral.                                */
85989   } NRF_USBHS_Type;                                  /*!< Size = 1028 (0x404)                                                  */
85990 
85991 /* USBHS_TASKS_START: Start the USB peripheral. */
85992   #define USBHS_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register.                                */
85993 
85994 /* TASKS_START @Bit 0 : Start the USB peripheral. */
85995   #define USBHS_TASKS_START_TASKS_START_Pos (0UL)    /*!< Position of TASKS_START field.                                       */
85996   #define USBHS_TASKS_START_TASKS_START_Msk (0x1UL << USBHS_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.   */
85997   #define USBHS_TASKS_START_TASKS_START_Min (0x1UL)  /*!< Min enumerator value of TASKS_START field.                           */
85998   #define USBHS_TASKS_START_TASKS_START_Max (0x1UL)  /*!< Max enumerator value of TASKS_START field.                           */
85999   #define USBHS_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                      */
86000 
86001 
86002 /* USBHS_EVENTS_CORE: Event indicating that interrupt triggered at USBHS core */
86003   #define USBHS_EVENTS_CORE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_CORE register.                                */
86004 
86005 /* EVENTS_CORE @Bit 0 : Event indicating that interrupt triggered at USBHS core */
86006   #define USBHS_EVENTS_CORE_EVENTS_CORE_Pos (0UL)    /*!< Position of EVENTS_CORE field.                                       */
86007   #define USBHS_EVENTS_CORE_EVENTS_CORE_Msk (0x1UL << USBHS_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field.   */
86008   #define USBHS_EVENTS_CORE_EVENTS_CORE_Min (0x0UL)  /*!< Min enumerator value of EVENTS_CORE field.                           */
86009   #define USBHS_EVENTS_CORE_EVENTS_CORE_Max (0x1UL)  /*!< Max enumerator value of EVENTS_CORE field.                           */
86010   #define USBHS_EVENTS_CORE_EVENTS_CORE_NotGenerated (0x0UL) /*!< Event not generated                                          */
86011   #define USBHS_EVENTS_CORE_EVENTS_CORE_Generated (0x1UL) /*!< Event generated                                                 */
86012 
86013 
86014 /* USBHS_INTEN: Enable or disable interrupt */
86015   #define USBHS_INTEN_ResetValue (0x00000000UL)      /*!< Reset value of INTEN register.                                       */
86016 
86017 /* CORE @Bit 0 : Enable or disable interrupt for event CORE */
86018   #define USBHS_INTEN_CORE_Pos (0UL)                 /*!< Position of CORE field.                                              */
86019   #define USBHS_INTEN_CORE_Msk (0x1UL << USBHS_INTEN_CORE_Pos) /*!< Bit mask of CORE field.                                    */
86020   #define USBHS_INTEN_CORE_Min (0x0UL)               /*!< Min enumerator value of CORE field.                                  */
86021   #define USBHS_INTEN_CORE_Max (0x1UL)               /*!< Max enumerator value of CORE field.                                  */
86022   #define USBHS_INTEN_CORE_Disabled (0x0UL)          /*!< Disable                                                              */
86023   #define USBHS_INTEN_CORE_Enabled (0x1UL)           /*!< Enable                                                               */
86024 
86025 
86026 /* USBHS_INTENSET: Enable interrupt */
86027   #define USBHS_INTENSET_ResetValue (0x00000000UL)   /*!< Reset value of INTENSET register.                                    */
86028 
86029 /* CORE @Bit 0 : Write '1' to enable interrupt for event CORE */
86030   #define USBHS_INTENSET_CORE_Pos (0UL)              /*!< Position of CORE field.                                              */
86031   #define USBHS_INTENSET_CORE_Msk (0x1UL << USBHS_INTENSET_CORE_Pos) /*!< Bit mask of CORE field.                              */
86032   #define USBHS_INTENSET_CORE_Min (0x0UL)            /*!< Min enumerator value of CORE field.                                  */
86033   #define USBHS_INTENSET_CORE_Max (0x1UL)            /*!< Max enumerator value of CORE field.                                  */
86034   #define USBHS_INTENSET_CORE_Set (0x1UL)            /*!< Enable                                                               */
86035   #define USBHS_INTENSET_CORE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
86036   #define USBHS_INTENSET_CORE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
86037 
86038 
86039 /* USBHS_INTENCLR: Disable interrupt */
86040   #define USBHS_INTENCLR_ResetValue (0x00000000UL)   /*!< Reset value of INTENCLR register.                                    */
86041 
86042 /* CORE @Bit 0 : Write '1' to disable interrupt for event CORE */
86043   #define USBHS_INTENCLR_CORE_Pos (0UL)              /*!< Position of CORE field.                                              */
86044   #define USBHS_INTENCLR_CORE_Msk (0x1UL << USBHS_INTENCLR_CORE_Pos) /*!< Bit mask of CORE field.                              */
86045   #define USBHS_INTENCLR_CORE_Min (0x0UL)            /*!< Min enumerator value of CORE field.                                  */
86046   #define USBHS_INTENCLR_CORE_Max (0x1UL)            /*!< Max enumerator value of CORE field.                                  */
86047   #define USBHS_INTENCLR_CORE_Clear (0x1UL)          /*!< Disable                                                              */
86048   #define USBHS_INTENCLR_CORE_Disabled (0x0UL)       /*!< Read: Disabled                                                       */
86049   #define USBHS_INTENCLR_CORE_Enabled (0x1UL)        /*!< Read: Enabled                                                        */
86050 
86051 
86052 /* USBHS_INTPEND: Pending interrupts */
86053   #define USBHS_INTPEND_ResetValue (0x00000000UL)    /*!< Reset value of INTPEND register.                                     */
86054 
86055 /* CORE @Bit 0 : Read pending status of interrupt for event CORE */
86056   #define USBHS_INTPEND_CORE_Pos (0UL)               /*!< Position of CORE field.                                              */
86057   #define USBHS_INTPEND_CORE_Msk (0x1UL << USBHS_INTPEND_CORE_Pos) /*!< Bit mask of CORE field.                                */
86058   #define USBHS_INTPEND_CORE_Min (0x0UL)             /*!< Min enumerator value of CORE field.                                  */
86059   #define USBHS_INTPEND_CORE_Max (0x1UL)             /*!< Max enumerator value of CORE field.                                  */
86060   #define USBHS_INTPEND_CORE_NotPending (0x0UL)      /*!< Read: Not pending                                                    */
86061   #define USBHS_INTPEND_CORE_Pending (0x1UL)         /*!< Read: Pending                                                        */
86062 
86063 
86064 /* USBHS_ENABLE: Enable USB peripheral. */
86065   #define USBHS_ENABLE_ResetValue (0x00000000UL)     /*!< Reset value of ENABLE register.                                      */
86066 
86067 /* CORE @Bit 0 : Enable USB Controller */
86068   #define USBHS_ENABLE_CORE_Pos (0UL)                /*!< Position of CORE field.                                              */
86069   #define USBHS_ENABLE_CORE_Msk (0x1UL << USBHS_ENABLE_CORE_Pos) /*!< Bit mask of CORE field.                                  */
86070   #define USBHS_ENABLE_CORE_Min (0x0UL)              /*!< Min enumerator value of CORE field.                                  */
86071   #define USBHS_ENABLE_CORE_Max (0x1UL)              /*!< Max enumerator value of CORE field.                                  */
86072   #define USBHS_ENABLE_CORE_Disabled (0x0UL)         /*!< USB Controller disabled.                                             */
86073   #define USBHS_ENABLE_CORE_Enabled (0x1UL)          /*!< USB Controller enabled.                                              */
86074 
86075 /* PHY @Bit 1 : Enable USB PHY */
86076   #define USBHS_ENABLE_PHY_Pos (1UL)                 /*!< Position of PHY field.                                               */
86077   #define USBHS_ENABLE_PHY_Msk (0x1UL << USBHS_ENABLE_PHY_Pos) /*!< Bit mask of PHY field.                                     */
86078   #define USBHS_ENABLE_PHY_Min (0x0UL)               /*!< Min enumerator value of PHY field.                                   */
86079   #define USBHS_ENABLE_PHY_Max (0x1UL)               /*!< Max enumerator value of PHY field.                                   */
86080   #define USBHS_ENABLE_PHY_Disabled (0x0UL)          /*!< USB PHY disabled.                                                    */
86081   #define USBHS_ENABLE_PHY_Enabled (0x1UL)           /*!< USB PHY enabled.                                                     */
86082 
86083 
86084 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
86085 
86086 /* =========================================================================================================================== */
86087 /* ================                                         USBHSCORE                                         ================ */
86088 /* =========================================================================================================================== */
86089 
86090 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
86091 
86092 /* =================================================== Struct USBHSCORE_HC =================================================== */
86093 /**
86094   * @brief HC [USBHSCORE_HC] (unspecified)
86095   */
86096 typedef struct {
86097   __IOM uint32_t  CHAR;                              /*!< (@ 0x00000000) Host Channel n Characteristics Register               */
86098   __IM  uint32_t  RESERVED;
86099   __IOM uint32_t  INT;                               /*!< (@ 0x00000008) Host Channel n Interrupt Register                     */
86100   __IOM uint32_t  INTMSK;                            /*!< (@ 0x0000000C) Host Channel n Interrupt Mask Register                */
86101   __IOM uint32_t  TSIZ;                              /*!< (@ 0x00000010) Host Channel n Transfer Size Register                 */
86102   __IOM uint32_t  DMA;                               /*!< (@ 0x00000014) Host Channel n DMA Address Register                   */
86103   __IM  uint32_t  RESERVED1[2];
86104 } NRF_USBHSCORE_HC_Type;                             /*!< Size = 32 (0x020)                                                    */
86105   #define USBHSCORE_HC_MaxCount (16UL)               /*!< Size of HC[16] array.                                                */
86106   #define USBHSCORE_HC_MaxIndex (15UL)               /*!< Max index of HC[16] array.                                           */
86107   #define USBHSCORE_HC_MinIndex (0UL)                /*!< Min index of HC[16] array.                                           */
86108 
86109 /* USBHSCORE_HC_CHAR: Host Channel n Characteristics Register */
86110   #define USBHSCORE_HC_CHAR_ResetValue (0x00000000UL) /*!< Reset value of CHAR register.                                       */
86111 
86112 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
86113   #define USBHSCORE_HC_CHAR_MPS_Pos (0UL)            /*!< Position of MPS field.                                               */
86114   #define USBHSCORE_HC_CHAR_MPS_Msk (0x7FFUL << USBHSCORE_HC_CHAR_MPS_Pos) /*!< Bit mask of MPS field.                         */
86115 
86116 /* EPNUM @Bits 11..14 : Endpoint Number (EPNum) */
86117   #define USBHSCORE_HC_CHAR_EPNUM_Pos (11UL)         /*!< Position of EPNUM field.                                             */
86118   #define USBHSCORE_HC_CHAR_EPNUM_Msk (0xFUL << USBHSCORE_HC_CHAR_EPNUM_Pos) /*!< Bit mask of EPNUM field.                     */
86119   #define USBHSCORE_HC_CHAR_EPNUM_Min (0x0UL)        /*!< Min enumerator value of EPNUM field.                                 */
86120   #define USBHSCORE_HC_CHAR_EPNUM_Max (0xFUL)        /*!< Max enumerator value of EPNUM field.                                 */
86121   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT0 (0x0UL)     /*!< (unspecified)                                                        */
86122   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT1 (0x1UL)     /*!< (unspecified)                                                        */
86123   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT2 (0x2UL)     /*!< (unspecified)                                                        */
86124   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT3 (0x3UL)     /*!< (unspecified)                                                        */
86125   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT4 (0x4UL)     /*!< (unspecified)                                                        */
86126   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT5 (0x5UL)     /*!< (unspecified)                                                        */
86127   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT6 (0x6UL)     /*!< (unspecified)                                                        */
86128   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT7 (0x7UL)     /*!< (unspecified)                                                        */
86129   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT8 (0x8UL)     /*!< (unspecified)                                                        */
86130   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT9 (0x9UL)     /*!< (unspecified)                                                        */
86131   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT10 (0xAUL)    /*!< (unspecified)                                                        */
86132   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT11 (0xBUL)    /*!< (unspecified)                                                        */
86133   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT12 (0xCUL)    /*!< (unspecified)                                                        */
86134   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT13 (0xDUL)    /*!< (unspecified)                                                        */
86135   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT14 (0xEUL)    /*!< (unspecified)                                                        */
86136   #define USBHSCORE_HC_CHAR_EPNUM_ENDPT15 (0xFUL)    /*!< (unspecified)                                                        */
86137 
86138 /* EPDIR @Bit 15 : Endpoint Direction (EPDir) */
86139   #define USBHSCORE_HC_CHAR_EPDIR_Pos (15UL)         /*!< Position of EPDIR field.                                             */
86140   #define USBHSCORE_HC_CHAR_EPDIR_Msk (0x1UL << USBHSCORE_HC_CHAR_EPDIR_Pos) /*!< Bit mask of EPDIR field.                     */
86141   #define USBHSCORE_HC_CHAR_EPDIR_Min (0x0UL)        /*!< Min enumerator value of EPDIR field.                                 */
86142   #define USBHSCORE_HC_CHAR_EPDIR_Max (0x1UL)        /*!< Max enumerator value of EPDIR field.                                 */
86143   #define USBHSCORE_HC_CHAR_EPDIR_OUT (0x0UL)        /*!< (unspecified)                                                        */
86144   #define USBHSCORE_HC_CHAR_EPDIR_IN (0x1UL)         /*!< (unspecified)                                                        */
86145 
86146 /* LSPDDEV @Bit 17 : Low-Speed Device (LSpdDev) */
86147   #define USBHSCORE_HC_CHAR_LSPDDEV_Pos (17UL)       /*!< Position of LSPDDEV field.                                           */
86148   #define USBHSCORE_HC_CHAR_LSPDDEV_Msk (0x1UL << USBHSCORE_HC_CHAR_LSPDDEV_Pos) /*!< Bit mask of LSPDDEV field.               */
86149   #define USBHSCORE_HC_CHAR_LSPDDEV_Min (0x0UL)      /*!< Min enumerator value of LSPDDEV field.                               */
86150   #define USBHSCORE_HC_CHAR_LSPDDEV_Max (0x1UL)      /*!< Max enumerator value of LSPDDEV field.                               */
86151   #define USBHSCORE_HC_CHAR_LSPDDEV_DISABLED (0x0UL) /*!< (unspecified)                                                        */
86152   #define USBHSCORE_HC_CHAR_LSPDDEV_ENABLED (0x1UL)  /*!< (unspecified)                                                        */
86153 
86154 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
86155   #define USBHSCORE_HC_CHAR_EPTYPE_Pos (18UL)        /*!< Position of EPTYPE field.                                            */
86156   #define USBHSCORE_HC_CHAR_EPTYPE_Msk (0x3UL << USBHSCORE_HC_CHAR_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                  */
86157   #define USBHSCORE_HC_CHAR_EPTYPE_Min (0x0UL)       /*!< Min enumerator value of EPTYPE field.                                */
86158   #define USBHSCORE_HC_CHAR_EPTYPE_Max (0x3UL)       /*!< Max enumerator value of EPTYPE field.                                */
86159   #define USBHSCORE_HC_CHAR_EPTYPE_CTRL (0x0UL)      /*!< (unspecified)                                                        */
86160   #define USBHSCORE_HC_CHAR_EPTYPE_ISOC (0x1UL)      /*!< (unspecified)                                                        */
86161   #define USBHSCORE_HC_CHAR_EPTYPE_BULK (0x2UL)      /*!< (unspecified)                                                        */
86162   #define USBHSCORE_HC_CHAR_EPTYPE_INTERR (0x3UL)    /*!< (unspecified)                                                        */
86163 
86164 /* EC @Bits 20..21 : Multi Count (MC) / Error Count (EC) */
86165   #define USBHSCORE_HC_CHAR_EC_Pos (20UL)            /*!< Position of EC field.                                                */
86166   #define USBHSCORE_HC_CHAR_EC_Msk (0x3UL << USBHSCORE_HC_CHAR_EC_Pos) /*!< Bit mask of EC field.                              */
86167   #define USBHSCORE_HC_CHAR_EC_Min (0x1UL)           /*!< Min enumerator value of EC field.                                    */
86168   #define USBHSCORE_HC_CHAR_EC_Max (0x3UL)           /*!< Max enumerator value of EC field.                                    */
86169   #define USBHSCORE_HC_CHAR_EC_TRANSONE (0x1UL)      /*!< (unspecified)                                                        */
86170   #define USBHSCORE_HC_CHAR_EC_TRANSTWO (0x2UL)      /*!< (unspecified)                                                        */
86171   #define USBHSCORE_HC_CHAR_EC_TRANSTHREE (0x3UL)    /*!< (unspecified)                                                        */
86172 
86173 /* DEVADDR @Bits 22..28 : Device Address (DevAddr) */
86174   #define USBHSCORE_HC_CHAR_DEVADDR_Pos (22UL)       /*!< Position of DEVADDR field.                                           */
86175   #define USBHSCORE_HC_CHAR_DEVADDR_Msk (0x7FUL << USBHSCORE_HC_CHAR_DEVADDR_Pos) /*!< Bit mask of DEVADDR field.              */
86176 
86177 /* ODDFRM @Bit 29 : Odd Frame (OddFrm) */
86178   #define USBHSCORE_HC_CHAR_ODDFRM_Pos (29UL)        /*!< Position of ODDFRM field.                                            */
86179   #define USBHSCORE_HC_CHAR_ODDFRM_Msk (0x1UL << USBHSCORE_HC_CHAR_ODDFRM_Pos) /*!< Bit mask of ODDFRM field.                  */
86180   #define USBHSCORE_HC_CHAR_ODDFRM_Min (0x0UL)       /*!< Min enumerator value of ODDFRM field.                                */
86181   #define USBHSCORE_HC_CHAR_ODDFRM_Max (0x1UL)       /*!< Max enumerator value of ODDFRM field.                                */
86182   #define USBHSCORE_HC_CHAR_ODDFRM_EFRAME (0x0UL)    /*!< (unspecified)                                                        */
86183   #define USBHSCORE_HC_CHAR_ODDFRM_OFRAME (0x1UL)    /*!< (unspecified)                                                        */
86184 
86185 /* CHDIS @Bit 30 : Channel Disable (ChDis) */
86186   #define USBHSCORE_HC_CHAR_CHDIS_Pos (30UL)         /*!< Position of CHDIS field.                                             */
86187   #define USBHSCORE_HC_CHAR_CHDIS_Msk (0x1UL << USBHSCORE_HC_CHAR_CHDIS_Pos) /*!< Bit mask of CHDIS field.                     */
86188   #define USBHSCORE_HC_CHAR_CHDIS_Min (0x0UL)        /*!< Min enumerator value of CHDIS field.                                 */
86189   #define USBHSCORE_HC_CHAR_CHDIS_Max (0x1UL)        /*!< Max enumerator value of CHDIS field.                                 */
86190   #define USBHSCORE_HC_CHAR_CHDIS_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
86191   #define USBHSCORE_HC_CHAR_CHDIS_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
86192 
86193 /* CHENA @Bit 31 : Channel Enable (ChEna) */
86194   #define USBHSCORE_HC_CHAR_CHENA_Pos (31UL)         /*!< Position of CHENA field.                                             */
86195   #define USBHSCORE_HC_CHAR_CHENA_Msk (0x1UL << USBHSCORE_HC_CHAR_CHENA_Pos) /*!< Bit mask of CHENA field.                     */
86196   #define USBHSCORE_HC_CHAR_CHENA_Min (0x0UL)        /*!< Min enumerator value of CHENA field.                                 */
86197   #define USBHSCORE_HC_CHAR_CHENA_Max (0x1UL)        /*!< Max enumerator value of CHENA field.                                 */
86198   #define USBHSCORE_HC_CHAR_CHENA_DISABLED (0x0UL)   /*!< (unspecified)                                                        */
86199   #define USBHSCORE_HC_CHAR_CHENA_ENABLED (0x1UL)    /*!< (unspecified)                                                        */
86200 
86201 
86202 /* USBHSCORE_HC_INT: Host Channel n Interrupt Register */
86203   #define USBHSCORE_HC_INT_ResetValue (0x00000000UL) /*!< Reset value of INT register.                                         */
86204 
86205 /* XFERCOMPL @Bit 0 : Transfer Completed (XferCompl) */
86206   #define USBHSCORE_HC_INT_XFERCOMPL_Pos (0UL)       /*!< Position of XFERCOMPL field.                                         */
86207   #define USBHSCORE_HC_INT_XFERCOMPL_Msk (0x1UL << USBHSCORE_HC_INT_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.           */
86208   #define USBHSCORE_HC_INT_XFERCOMPL_Min (0x0UL)     /*!< Min enumerator value of XFERCOMPL field.                             */
86209   #define USBHSCORE_HC_INT_XFERCOMPL_Max (0x1UL)     /*!< Max enumerator value of XFERCOMPL field.                             */
86210   #define USBHSCORE_HC_INT_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
86211   #define USBHSCORE_HC_INT_XFERCOMPL_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
86212 
86213 /* CHHLTD @Bit 1 : Channel Halted (ChHltd) */
86214   #define USBHSCORE_HC_INT_CHHLTD_Pos (1UL)          /*!< Position of CHHLTD field.                                            */
86215   #define USBHSCORE_HC_INT_CHHLTD_Msk (0x1UL << USBHSCORE_HC_INT_CHHLTD_Pos) /*!< Bit mask of CHHLTD field.                    */
86216   #define USBHSCORE_HC_INT_CHHLTD_Min (0x0UL)        /*!< Min enumerator value of CHHLTD field.                                */
86217   #define USBHSCORE_HC_INT_CHHLTD_Max (0x1UL)        /*!< Max enumerator value of CHHLTD field.                                */
86218   #define USBHSCORE_HC_INT_CHHLTD_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
86219   #define USBHSCORE_HC_INT_CHHLTD_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
86220 
86221 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
86222   #define USBHSCORE_HC_INT_AHBERR_Pos (2UL)          /*!< Position of AHBERR field.                                            */
86223   #define USBHSCORE_HC_INT_AHBERR_Msk (0x1UL << USBHSCORE_HC_INT_AHBERR_Pos) /*!< Bit mask of AHBERR field.                    */
86224   #define USBHSCORE_HC_INT_AHBERR_Min (0x0UL)        /*!< Min enumerator value of AHBERR field.                                */
86225   #define USBHSCORE_HC_INT_AHBERR_Max (0x1UL)        /*!< Max enumerator value of AHBERR field.                                */
86226   #define USBHSCORE_HC_INT_AHBERR_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
86227   #define USBHSCORE_HC_INT_AHBERR_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
86228 
86229 /* STALL @Bit 3 : STALL Response Received Interrupt (STALL) */
86230   #define USBHSCORE_HC_INT_STALL_Pos (3UL)           /*!< Position of STALL field.                                             */
86231   #define USBHSCORE_HC_INT_STALL_Msk (0x1UL << USBHSCORE_HC_INT_STALL_Pos) /*!< Bit mask of STALL field.                       */
86232   #define USBHSCORE_HC_INT_STALL_Min (0x0UL)         /*!< Min enumerator value of STALL field.                                 */
86233   #define USBHSCORE_HC_INT_STALL_Max (0x1UL)         /*!< Max enumerator value of STALL field.                                 */
86234   #define USBHSCORE_HC_INT_STALL_INACTIVE (0x0UL)    /*!< (unspecified)                                                        */
86235   #define USBHSCORE_HC_INT_STALL_ACTIVE (0x1UL)      /*!< (unspecified)                                                        */
86236 
86237 /* NAK @Bit 4 : NAK Response Received Interrupt (NAK) */
86238   #define USBHSCORE_HC_INT_NAK_Pos (4UL)             /*!< Position of NAK field.                                               */
86239   #define USBHSCORE_HC_INT_NAK_Msk (0x1UL << USBHSCORE_HC_INT_NAK_Pos) /*!< Bit mask of NAK field.                             */
86240   #define USBHSCORE_HC_INT_NAK_Min (0x0UL)           /*!< Min enumerator value of NAK field.                                   */
86241   #define USBHSCORE_HC_INT_NAK_Max (0x1UL)           /*!< Max enumerator value of NAK field.                                   */
86242   #define USBHSCORE_HC_INT_NAK_INACTIVE (0x0UL)      /*!< (unspecified)                                                        */
86243   #define USBHSCORE_HC_INT_NAK_ACTIVE (0x1UL)        /*!< (unspecified)                                                        */
86244 
86245 /* ACK @Bit 5 : ACK Response Received/Transmitted Interrupt (ACK) */
86246   #define USBHSCORE_HC_INT_ACK_Pos (5UL)             /*!< Position of ACK field.                                               */
86247   #define USBHSCORE_HC_INT_ACK_Msk (0x1UL << USBHSCORE_HC_INT_ACK_Pos) /*!< Bit mask of ACK field.                             */
86248   #define USBHSCORE_HC_INT_ACK_Min (0x0UL)           /*!< Min enumerator value of ACK field.                                   */
86249   #define USBHSCORE_HC_INT_ACK_Max (0x1UL)           /*!< Max enumerator value of ACK field.                                   */
86250   #define USBHSCORE_HC_INT_ACK_INACTIVE (0x0UL)      /*!< (unspecified)                                                        */
86251   #define USBHSCORE_HC_INT_ACK_ACTIVE (0x1UL)        /*!< (unspecified)                                                        */
86252 
86253 /* NYET @Bit 6 : NYET Response Received Interrupt (NYET) */
86254   #define USBHSCORE_HC_INT_NYET_Pos (6UL)            /*!< Position of NYET field.                                              */
86255   #define USBHSCORE_HC_INT_NYET_Msk (0x1UL << USBHSCORE_HC_INT_NYET_Pos) /*!< Bit mask of NYET field.                          */
86256   #define USBHSCORE_HC_INT_NYET_Min (0x0UL)          /*!< Min enumerator value of NYET field.                                  */
86257   #define USBHSCORE_HC_INT_NYET_Max (0x1UL)          /*!< Max enumerator value of NYET field.                                  */
86258   #define USBHSCORE_HC_INT_NYET_INACTIVE (0x0UL)     /*!< (unspecified)                                                        */
86259   #define USBHSCORE_HC_INT_NYET_ACTIVE (0x1UL)       /*!< (unspecified)                                                        */
86260 
86261 /* XACTERR @Bit 7 : Transaction Error (XactErr) */
86262   #define USBHSCORE_HC_INT_XACTERR_Pos (7UL)         /*!< Position of XACTERR field.                                           */
86263   #define USBHSCORE_HC_INT_XACTERR_Msk (0x1UL << USBHSCORE_HC_INT_XACTERR_Pos) /*!< Bit mask of XACTERR field.                 */
86264   #define USBHSCORE_HC_INT_XACTERR_Min (0x0UL)       /*!< Min enumerator value of XACTERR field.                               */
86265   #define USBHSCORE_HC_INT_XACTERR_Max (0x1UL)       /*!< Max enumerator value of XACTERR field.                               */
86266   #define USBHSCORE_HC_INT_XACTERR_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
86267   #define USBHSCORE_HC_INT_XACTERR_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
86268 
86269 /* BBLERR @Bit 8 : Babble Error (BblErr) */
86270   #define USBHSCORE_HC_INT_BBLERR_Pos (8UL)          /*!< Position of BBLERR field.                                            */
86271   #define USBHSCORE_HC_INT_BBLERR_Msk (0x1UL << USBHSCORE_HC_INT_BBLERR_Pos) /*!< Bit mask of BBLERR field.                    */
86272   #define USBHSCORE_HC_INT_BBLERR_Min (0x0UL)        /*!< Min enumerator value of BBLERR field.                                */
86273   #define USBHSCORE_HC_INT_BBLERR_Max (0x1UL)        /*!< Max enumerator value of BBLERR field.                                */
86274   #define USBHSCORE_HC_INT_BBLERR_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
86275   #define USBHSCORE_HC_INT_BBLERR_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
86276 
86277 /* FRMOVRUN @Bit 9 : Frame Overrun (FrmOvrun). */
86278   #define USBHSCORE_HC_INT_FRMOVRUN_Pos (9UL)        /*!< Position of FRMOVRUN field.                                          */
86279   #define USBHSCORE_HC_INT_FRMOVRUN_Msk (0x1UL << USBHSCORE_HC_INT_FRMOVRUN_Pos) /*!< Bit mask of FRMOVRUN field.              */
86280   #define USBHSCORE_HC_INT_FRMOVRUN_Min (0x0UL)      /*!< Min enumerator value of FRMOVRUN field.                              */
86281   #define USBHSCORE_HC_INT_FRMOVRUN_Max (0x1UL)      /*!< Max enumerator value of FRMOVRUN field.                              */
86282   #define USBHSCORE_HC_INT_FRMOVRUN_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
86283   #define USBHSCORE_HC_INT_FRMOVRUN_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
86284 
86285 /* DATATGLERR @Bit 10 : Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1
86286                         to clear */
86287 
86288   #define USBHSCORE_HC_INT_DATATGLERR_Pos (10UL)     /*!< Position of DATATGLERR field.                                        */
86289   #define USBHSCORE_HC_INT_DATATGLERR_Msk (0x1UL << USBHSCORE_HC_INT_DATATGLERR_Pos) /*!< Bit mask of DATATGLERR field.        */
86290   #define USBHSCORE_HC_INT_DATATGLERR_Min (0x0UL)    /*!< Min enumerator value of DATATGLERR field.                            */
86291   #define USBHSCORE_HC_INT_DATATGLERR_Max (0x1UL)    /*!< Max enumerator value of DATATGLERR field.                            */
86292   #define USBHSCORE_HC_INT_DATATGLERR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
86293   #define USBHSCORE_HC_INT_DATATGLERR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
86294 
86295 
86296 /* USBHSCORE_HC_INTMSK: Host Channel n Interrupt Mask Register */
86297   #define USBHSCORE_HC_INTMSK_ResetValue (0x00000000UL) /*!< Reset value of INTMSK register.                                   */
86298 
86299 /* XFERCOMPLMSK @Bit 0 : Transfer Completed Mask (XferComplMsk) */
86300   #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Pos (0UL) /*!< Position of XFERCOMPLMSK field.                                      */
86301   #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK
86302                                                                             field.*/
86303   #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field.                        */
86304   #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field.                        */
86305   #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< (unspecified)                                                     */
86306   #define USBHSCORE_HC_INTMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< (unspecified)                                                   */
86307 
86308 /* CHHLTDMSK @Bit 1 : Channel Halted Mask (ChHltdMsk) */
86309   #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Pos (1UL)    /*!< Position of CHHLTDMSK field.                                         */
86310   #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_CHHLTDMSK_Pos) /*!< Bit mask of CHHLTDMSK field.     */
86311   #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Min (0x0UL)  /*!< Min enumerator value of CHHLTDMSK field.                             */
86312   #define USBHSCORE_HC_INTMSK_CHHLTDMSK_Max (0x1UL)  /*!< Max enumerator value of CHHLTDMSK field.                             */
86313   #define USBHSCORE_HC_INTMSK_CHHLTDMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
86314   #define USBHSCORE_HC_INTMSK_CHHLTDMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
86315 
86316 /* AHBERRMSK @Bit 2 : AHB Error Mask (AHBErrMsk) */
86317   #define USBHSCORE_HC_INTMSK_AHBERRMSK_Pos (2UL)    /*!< Position of AHBERRMSK field.                                         */
86318   #define USBHSCORE_HC_INTMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field.     */
86319   #define USBHSCORE_HC_INTMSK_AHBERRMSK_Min (0x0UL)  /*!< Min enumerator value of AHBERRMSK field.                             */
86320   #define USBHSCORE_HC_INTMSK_AHBERRMSK_Max (0x1UL)  /*!< Max enumerator value of AHBERRMSK field.                             */
86321   #define USBHSCORE_HC_INTMSK_AHBERRMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
86322   #define USBHSCORE_HC_INTMSK_AHBERRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
86323 
86324 /* STALLMSK @Bit 3 : STALL Response Received Interrupt Mask (StallMsk) */
86325   #define USBHSCORE_HC_INTMSK_STALLMSK_Pos (3UL)     /*!< Position of STALLMSK field.                                          */
86326   #define USBHSCORE_HC_INTMSK_STALLMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_STALLMSK_Pos) /*!< Bit mask of STALLMSK field.        */
86327   #define USBHSCORE_HC_INTMSK_STALLMSK_Min (0x0UL)   /*!< Min enumerator value of STALLMSK field.                              */
86328   #define USBHSCORE_HC_INTMSK_STALLMSK_Max (0x1UL)   /*!< Max enumerator value of STALLMSK field.                              */
86329   #define USBHSCORE_HC_INTMSK_STALLMSK_MASK (0x0UL)  /*!< (unspecified)                                                        */
86330   #define USBHSCORE_HC_INTMSK_STALLMSK_NOMASK (0x1UL) /*!< (unspecified)                                                       */
86331 
86332 /* NAKMSK @Bit 4 : NAK Response Received Interrupt Mask (NakMsk) */
86333   #define USBHSCORE_HC_INTMSK_NAKMSK_Pos (4UL)       /*!< Position of NAKMSK field.                                            */
86334   #define USBHSCORE_HC_INTMSK_NAKMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field.              */
86335   #define USBHSCORE_HC_INTMSK_NAKMSK_Min (0x0UL)     /*!< Min enumerator value of NAKMSK field.                                */
86336   #define USBHSCORE_HC_INTMSK_NAKMSK_Max (0x1UL)     /*!< Max enumerator value of NAKMSK field.                                */
86337   #define USBHSCORE_HC_INTMSK_NAKMSK_MASK (0x0UL)    /*!< (unspecified)                                                        */
86338   #define USBHSCORE_HC_INTMSK_NAKMSK_NOMASK (0x1UL)  /*!< (unspecified)                                                        */
86339 
86340 /* ACKMSK @Bit 5 : ACK Response Received/Transmitted Interrupt Mask (AckMsk) */
86341   #define USBHSCORE_HC_INTMSK_ACKMSK_Pos (5UL)       /*!< Position of ACKMSK field.                                            */
86342   #define USBHSCORE_HC_INTMSK_ACKMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_ACKMSK_Pos) /*!< Bit mask of ACKMSK field.              */
86343   #define USBHSCORE_HC_INTMSK_ACKMSK_Min (0x0UL)     /*!< Min enumerator value of ACKMSK field.                                */
86344   #define USBHSCORE_HC_INTMSK_ACKMSK_Max (0x1UL)     /*!< Max enumerator value of ACKMSK field.                                */
86345   #define USBHSCORE_HC_INTMSK_ACKMSK_MASK (0x0UL)    /*!< (unspecified)                                                        */
86346   #define USBHSCORE_HC_INTMSK_ACKMSK_NOMASK (0x1UL)  /*!< (unspecified)                                                        */
86347 
86348 /* NYETMSK @Bit 6 : NYET Response Received Interrupt Mask (NyetMsk) */
86349   #define USBHSCORE_HC_INTMSK_NYETMSK_Pos (6UL)      /*!< Position of NYETMSK field.                                           */
86350   #define USBHSCORE_HC_INTMSK_NYETMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_NYETMSK_Pos) /*!< Bit mask of NYETMSK field.           */
86351   #define USBHSCORE_HC_INTMSK_NYETMSK_Min (0x0UL)    /*!< Min enumerator value of NYETMSK field.                               */
86352   #define USBHSCORE_HC_INTMSK_NYETMSK_Max (0x1UL)    /*!< Max enumerator value of NYETMSK field.                               */
86353   #define USBHSCORE_HC_INTMSK_NYETMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
86354   #define USBHSCORE_HC_INTMSK_NYETMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
86355 
86356 /* XACTERRMSK @Bit 7 : Transaction Error Mask (XactErrMsk) */
86357   #define USBHSCORE_HC_INTMSK_XACTERRMSK_Pos (7UL)   /*!< Position of XACTERRMSK field.                                        */
86358   #define USBHSCORE_HC_INTMSK_XACTERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_XACTERRMSK_Pos) /*!< Bit mask of XACTERRMSK field.  */
86359   #define USBHSCORE_HC_INTMSK_XACTERRMSK_Min (0x0UL) /*!< Min enumerator value of XACTERRMSK field.                            */
86360   #define USBHSCORE_HC_INTMSK_XACTERRMSK_Max (0x1UL) /*!< Max enumerator value of XACTERRMSK field.                            */
86361   #define USBHSCORE_HC_INTMSK_XACTERRMSK_MASK (0x0UL) /*!< (unspecified)                                                       */
86362   #define USBHSCORE_HC_INTMSK_XACTERRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                     */
86363 
86364 /* BBLERRMSK @Bit 8 : Babble Error Mask (BblErrMsk) */
86365   #define USBHSCORE_HC_INTMSK_BBLERRMSK_Pos (8UL)    /*!< Position of BBLERRMSK field.                                         */
86366   #define USBHSCORE_HC_INTMSK_BBLERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_BBLERRMSK_Pos) /*!< Bit mask of BBLERRMSK field.     */
86367   #define USBHSCORE_HC_INTMSK_BBLERRMSK_Min (0x0UL)  /*!< Min enumerator value of BBLERRMSK field.                             */
86368   #define USBHSCORE_HC_INTMSK_BBLERRMSK_Max (0x1UL)  /*!< Max enumerator value of BBLERRMSK field.                             */
86369   #define USBHSCORE_HC_INTMSK_BBLERRMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
86370   #define USBHSCORE_HC_INTMSK_BBLERRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
86371 
86372 /* FRMOVRUNMSK @Bit 9 : Frame Overrun Mask (FrmOvrunMsk) */
86373   #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Pos (9UL)  /*!< Position of FRMOVRUNMSK field.                                       */
86374   #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Pos) /*!< Bit mask of FRMOVRUNMSK
86375                                                                             field.*/
86376   #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Min (0x0UL) /*!< Min enumerator value of FRMOVRUNMSK field.                          */
86377   #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_Max (0x1UL) /*!< Max enumerator value of FRMOVRUNMSK field.                          */
86378   #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_MASK (0x0UL) /*!< (unspecified)                                                      */
86379   #define USBHSCORE_HC_INTMSK_FRMOVRUNMSK_NOMASK (0x1UL) /*!< (unspecified)                                                    */
86380 
86381 /* DATATGLERRMSK @Bit 10 : Data Toggle Error Mask (DataTglErrMsk) */
86382   #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Pos (10UL) /*!< Position of DATATGLERRMSK field.                                   */
86383   #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Msk (0x1UL << USBHSCORE_HC_INTMSK_DATATGLERRMSK_Pos) /*!< Bit mask of DATATGLERRMSK
86384                                                                             field.*/
86385   #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Min (0x0UL) /*!< Min enumerator value of DATATGLERRMSK field.                      */
86386   #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_Max (0x1UL) /*!< Max enumerator value of DATATGLERRMSK field.                      */
86387   #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_MASK (0x0UL) /*!< (unspecified)                                                    */
86388   #define USBHSCORE_HC_INTMSK_DATATGLERRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                  */
86389 
86390 
86391 /* USBHSCORE_HC_TSIZ: Host Channel n Transfer Size Register */
86392   #define USBHSCORE_HC_TSIZ_ResetValue (0x00000000UL) /*!< Reset value of TSIZ register.                                       */
86393 
86394 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
86395   #define USBHSCORE_HC_TSIZ_XFERSIZE_Pos (0UL)       /*!< Position of XFERSIZE field.                                          */
86396   #define USBHSCORE_HC_TSIZ_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_HC_TSIZ_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.        */
86397 
86398 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
86399   #define USBHSCORE_HC_TSIZ_PKTCNT_Pos (19UL)        /*!< Position of PKTCNT field.                                            */
86400   #define USBHSCORE_HC_TSIZ_PKTCNT_Msk (0x3FFUL << USBHSCORE_HC_TSIZ_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.                */
86401 
86402 /* PID @Bits 29..30 : PID (Pid) */
86403   #define USBHSCORE_HC_TSIZ_PID_Pos (29UL)           /*!< Position of PID field.                                               */
86404   #define USBHSCORE_HC_TSIZ_PID_Msk (0x3UL << USBHSCORE_HC_TSIZ_PID_Pos) /*!< Bit mask of PID field.                           */
86405   #define USBHSCORE_HC_TSIZ_PID_Min (0x0UL)          /*!< Min enumerator value of PID field.                                   */
86406   #define USBHSCORE_HC_TSIZ_PID_Max (0x3UL)          /*!< Max enumerator value of PID field.                                   */
86407   #define USBHSCORE_HC_TSIZ_PID_DATA0 (0x0UL)        /*!< (unspecified)                                                        */
86408   #define USBHSCORE_HC_TSIZ_PID_DATA2 (0x1UL)        /*!< (unspecified)                                                        */
86409   #define USBHSCORE_HC_TSIZ_PID_DATA1 (0x2UL)        /*!< (unspecified)                                                        */
86410   #define USBHSCORE_HC_TSIZ_PID_MDATA (0x3UL)        /*!< (unspecified)                                                        */
86411 
86412 /* DOPNG @Bit 31 : Do Ping (DoPng) */
86413   #define USBHSCORE_HC_TSIZ_DOPNG_Pos (31UL)         /*!< Position of DOPNG field.                                             */
86414   #define USBHSCORE_HC_TSIZ_DOPNG_Msk (0x1UL << USBHSCORE_HC_TSIZ_DOPNG_Pos) /*!< Bit mask of DOPNG field.                     */
86415   #define USBHSCORE_HC_TSIZ_DOPNG_Min (0x0UL)        /*!< Min enumerator value of DOPNG field.                                 */
86416   #define USBHSCORE_HC_TSIZ_DOPNG_Max (0x1UL)        /*!< Max enumerator value of DOPNG field.                                 */
86417   #define USBHSCORE_HC_TSIZ_DOPNG_NOPING (0x0UL)     /*!< (unspecified)                                                        */
86418   #define USBHSCORE_HC_TSIZ_DOPNG_PING (0x1UL)       /*!< (unspecified)                                                        */
86419 
86420 
86421 /* USBHSCORE_HC_DMA: Host Channel n DMA Address Register */
86422   #define USBHSCORE_HC_DMA_ResetValue (0x00000000UL) /*!< Reset value of DMA register.                                         */
86423 
86424 /* DMAADDR @Bits 0..31 : In Buffer DMA Mode: */
86425   #define USBHSCORE_HC_DMA_DMAADDR_Pos (0UL)         /*!< Position of DMAADDR field.                                           */
86426   #define USBHSCORE_HC_DMA_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_HC_DMA_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.          */
86427 
86428 
86429 
86430 /* ============================================== Struct USBHSCORE_DWCOTGDFIFO =============================================== */
86431 /**
86432   * @brief DWCOTGDFIFO [USBHSCORE_DWCOTGDFIFO] (unspecified)
86433   */
86434 typedef struct {
86435   __IOM uint32_t  DATA[1025];                        /*!< (@ 0x00000000) Data buffer for FIFO n                                */
86436 } NRF_USBHSCORE_DWCOTGDFIFO_Type;                    /*!< Size = 4100 (0x1004)                                                 */
86437   #define USBHSCORE_DWCOTGDFIFO_MaxCount (16UL)      /*!< Size of DWCOTGDFIFO[16] array.                                       */
86438   #define USBHSCORE_DWCOTGDFIFO_MaxIndex (15UL)      /*!< Max index of DWCOTGDFIFO[16] array.                                  */
86439   #define USBHSCORE_DWCOTGDFIFO_MinIndex (0UL)       /*!< Min index of DWCOTGDFIFO[16] array.                                  */
86440 
86441 
86442 /* ======================================== Struct USBHSCORE_DWCOTGDFIFODIRECTACCESS ========================================= */
86443 /**
86444   * @brief DWCOTGDFIFODIRECTACCESS [USBHSCORE_DWCOTGDFIFODIRECTACCESS] (unspecified)
86445   */
86446 typedef struct {
86447   __IOM uint32_t  DATA[4097];                        /*!< (@ 0x00000000) Data buffer FIFO Direct Access                        */
86448 } NRF_USBHSCORE_DWCOTGDFIFODIRECTACCESS_Type;        /*!< Size = 16388 (0x4004)                                                */
86449 
86450 /* ==================================================== Struct USBHSCORE ===================================================== */
86451 /**
86452   * @brief USBHSCORE
86453   */
86454   typedef struct {                                   /*!< USBHSCORE Structure                                                  */
86455     __IOM uint32_t GOTGCTL;                          /*!< (@ 0x00000000) OTG Control and Status Register                       */
86456     __IOM uint32_t GOTGINT;                          /*!< (@ 0x00000004) OTG Interrupt Register                                */
86457     __IOM uint32_t GAHBCFG;                          /*!< (@ 0x00000008) AHB Configuration Register                            */
86458     __IOM uint32_t GUSBCFG;                          /*!< (@ 0x0000000C) USB Configuration Register                            */
86459     __IOM uint32_t GRSTCTL;                          /*!< (@ 0x00000010) Reset Register                                        */
86460     __IOM uint32_t GINTSTS;                          /*!< (@ 0x00000014) Interrupt Register                                    */
86461     __IOM uint32_t GINTMSK;                          /*!< (@ 0x00000018) Interrupt Mask Register                               */
86462     __IOM uint32_t GRXSTSR;                          /*!< (@ 0x0000001C) Receive Status Debug Read Register                    */
86463     __IOM uint32_t GRXSTSP;                          /*!< (@ 0x00000020) Receive Status Read/Pop Register                      */
86464     __IOM uint32_t GRXFSIZ;                          /*!< (@ 0x00000024) Receive FIFO Size Register                            */
86465     __IOM uint32_t GNPTXFSIZ;                        /*!< (@ 0x00000028) Non-periodic Transmit FIFO Size Register              */
86466     __IOM uint32_t GNPTXSTS;                         /*!< (@ 0x0000002C) Non-periodic Transmit FIFO/Queue Status Register      */
86467     __IM uint32_t RESERVED[2];
86468     __IOM uint32_t GGPIO;                            /*!< (@ 0x00000038) General Purpose Input/Output Register                 */
86469     __IOM uint32_t GUID;                             /*!< (@ 0x0000003C) User ID Register                                      */
86470     __IOM uint32_t GSNPSID;                          /*!< (@ 0x00000040) Synopsys ID Register                                  */
86471     __IOM uint32_t GHWCFG1;                          /*!< (@ 0x00000044) User Hardware Configuration 1 Register                */
86472     __IOM uint32_t GHWCFG2;                          /*!< (@ 0x00000048) User Hardware Configuration 2 Register                */
86473     __IOM uint32_t GHWCFG3;                          /*!< (@ 0x0000004C) User Hardware Configuration 3 Register                */
86474     __IOM uint32_t GHWCFG4;                          /*!< (@ 0x00000050) User Hardware Configuration 4 Register                */
86475     __IOM uint32_t GLPMCFG;                          /*!< (@ 0x00000054) LPM Config Register                                   */
86476     __IOM uint32_t GPWRDN;                           /*!< (@ 0x00000058) Global Power Down register                            */
86477     __IOM uint32_t GDFIFOCFG;                        /*!< (@ 0x0000005C) Global DFIFO Configuration Register                   */
86478     __IM uint32_t RESERVED1[2];
86479     __IOM uint32_t GINTMSK2;                         /*!< (@ 0x00000068) Interrupt Mask Register 2                             */
86480     __IOM uint32_t GINTSTS2;                         /*!< (@ 0x0000006C) Interrupt Register 2                                  */
86481     __IM uint32_t RESERVED2[36];
86482     __IOM uint32_t HPTXFSIZ;                         /*!< (@ 0x00000100) Host Periodic Transmit FIFO Size Register             */
86483     __IOM uint32_t DIEPTXF1;                         /*!< (@ 0x00000104) Device IN Endpoint Transmit FIFO Size Register 1      */
86484     __IOM uint32_t DIEPTXF2;                         /*!< (@ 0x00000108) Device IN Endpoint Transmit FIFO Size Register 2      */
86485     __IOM uint32_t DIEPTXF3;                         /*!< (@ 0x0000010C) Device IN Endpoint Transmit FIFO Size Register 3      */
86486     __IOM uint32_t DIEPTXF4;                         /*!< (@ 0x00000110) Device IN Endpoint Transmit FIFO Size Register 4      */
86487     __IOM uint32_t DIEPTXF5;                         /*!< (@ 0x00000114) Device IN Endpoint Transmit FIFO Size Register 5      */
86488     __IOM uint32_t DIEPTXF6;                         /*!< (@ 0x00000118) Device IN Endpoint Transmit FIFO Size Register 6      */
86489     __IOM uint32_t DIEPTXF7;                         /*!< (@ 0x0000011C) Device IN Endpoint Transmit FIFO Size Register 7      */
86490     __IM uint32_t RESERVED3[184];
86491     __IOM uint32_t HCFG;                             /*!< (@ 0x00000400) Host Configuration Register                           */
86492     __IOM uint32_t HFIR;                             /*!< (@ 0x00000404) Host Frame Interval Register                          */
86493     __IOM uint32_t HFNUM;                            /*!< (@ 0x00000408) Host Frame Number/Frame Time Remaining Register       */
86494     __IM uint32_t RESERVED4[2];
86495     __IOM uint32_t HAINT;                            /*!< (@ 0x00000414) Host All Channels Interrupt Register                  */
86496     __IOM uint32_t HAINTMSK;                         /*!< (@ 0x00000418) Host All Channels Interrupt Mask Register             */
86497     __IM uint32_t RESERVED5[9];
86498     __IOM uint32_t HPRT;                             /*!< (@ 0x00000440) Host Port Control and Status Register                 */
86499     __IM uint32_t RESERVED6[47];
86500     __IOM NRF_USBHSCORE_HC_Type HC[16];              /*!< (@ 0x00000500) (unspecified)                                         */
86501     __IM uint32_t RESERVED7[64];
86502     __IOM uint32_t DCFG;                             /*!< (@ 0x00000800) Device Configuration Register                         */
86503     __IOM uint32_t DCTL;                             /*!< (@ 0x00000804) Device Control Register                               */
86504     __IOM uint32_t DSTS;                             /*!< (@ 0x00000808) Device Status Register                                */
86505     __IM uint32_t RESERVED8;
86506     __IOM uint32_t DIEPMSK;                          /*!< (@ 0x00000810) Device IN Endpoint Common Interrupt Mask Register     */
86507     __IOM uint32_t DOEPMSK;                          /*!< (@ 0x00000814) Device OUT Endpoint Common Interrupt Mask Register    */
86508     __IOM uint32_t DAINT;                            /*!< (@ 0x00000818) Device All Endpoints Interrupt Register               */
86509     __IOM uint32_t DAINTMSK;                         /*!< (@ 0x0000081C) Device All Endpoints Interrupt Mask Register          */
86510     __IM uint32_t RESERVED9[2];
86511     __IOM uint32_t DVBUSDIS;                         /*!< (@ 0x00000828) Device VBUS Discharge Time Register                   */
86512     __IOM uint32_t DVBUSPULSE;                       /*!< (@ 0x0000082C) Device VBUS Pulsing Time Register                     */
86513     __IOM uint32_t DTHRCTL;                          /*!< (@ 0x00000830) Device Threshold Control Register                     */
86514     __IOM uint32_t DIEPEMPMSK;                       /*!< (@ 0x00000834) Device IN Endpoint FIFO Empty Interrupt Mask Register */
86515     __IM uint32_t RESERVED10[50];
86516     __IOM uint32_t DIEPCTL0;                         /*!< (@ 0x00000900) Device Control IN Endpoint 0 Control Register         */
86517     __IM uint32_t RESERVED11;
86518     __IOM uint32_t DIEPINT0;                         /*!< (@ 0x00000908) Device IN Endpoint 0 Interrupt Register               */
86519     __IM uint32_t RESERVED12;
86520     __IOM uint32_t DIEPTSIZ0;                        /*!< (@ 0x00000910) Device IN Endpoint 0 Transfer Size Register           */
86521     __IOM uint32_t DIEPDMA0;                         /*!< (@ 0x00000914) Device IN Endpoint 0 DMA Address Register             */
86522     __IOM uint32_t DTXFSTS0;                         /*!< (@ 0x00000918) Device IN Endpoint Transmit FIFO Status Register 0    */
86523     __IM uint32_t RESERVED13;
86524     __IOM uint32_t DIEPCTL1;                         /*!< (@ 0x00000920) Device Control IN Endpoint 1 Control Register         */
86525     __IM uint32_t RESERVED14;
86526     __IOM uint32_t DIEPINT1;                         /*!< (@ 0x00000928) Device IN Endpoint 1 Interrupt Register               */
86527     __IM uint32_t RESERVED15;
86528     __IOM uint32_t DIEPTSIZ1;                        /*!< (@ 0x00000930) Device IN Endpoint 1 Transfer Size Register           */
86529     __IOM uint32_t DIEPDMA1;                         /*!< (@ 0x00000934) Device IN Endpoint 1 DMA Address Register             */
86530     __IOM uint32_t DTXFSTS1;                         /*!< (@ 0x00000938) This register reflects the status of the IN Endpoint
86531                                                                          Transmit FIFO Status Register 1 of the Device
86532                                                                          controller.*/
86533     __IM uint32_t RESERVED16;
86534     __IOM uint32_t DIEPCTL2;                         /*!< (@ 0x00000940) Device Control IN Endpoint 2 Control Register         */
86535     __IM uint32_t RESERVED17;
86536     __IOM uint32_t DIEPINT2;                         /*!< (@ 0x00000948) Device IN Endpoint 2 Interrupt Register               */
86537     __IM uint32_t RESERVED18;
86538     __IOM uint32_t DIEPTSIZ2;                        /*!< (@ 0x00000950) Device IN Endpoint 2 Transfer Size Register           */
86539     __IOM uint32_t DIEPDMA2;                         /*!< (@ 0x00000954) Device IN Endpoint 2 DMA Address Register             */
86540     __IOM uint32_t DTXFSTS2;                         /*!< (@ 0x00000958) Device IN Endpoint Transmit FIFO Status Register 2    */
86541     __IM uint32_t RESERVED19;
86542     __IOM uint32_t DIEPCTL3;                         /*!< (@ 0x00000960) Device Control IN Endpoint 3 Control Register         */
86543     __IM uint32_t RESERVED20;
86544     __IOM uint32_t DIEPINT3;                         /*!< (@ 0x00000968) Device IN Endpoint 3 Interrupt Register               */
86545     __IM uint32_t RESERVED21;
86546     __IOM uint32_t DIEPTSIZ3;                        /*!< (@ 0x00000970) Device IN Endpoint 3 Transfer Size Register           */
86547     __IOM uint32_t DIEPDMA3;                         /*!< (@ 0x00000974) Device IN Endpoint 3 DMA Address Register             */
86548     __IOM uint32_t DTXFSTS3;                         /*!< (@ 0x00000978) Device IN Endpoint Transmit FIFO Status Register 3    */
86549     __IM uint32_t RESERVED22;
86550     __IOM uint32_t DIEPCTL4;                         /*!< (@ 0x00000980) Device Control IN Endpoint 4 Control Register         */
86551     __IM uint32_t RESERVED23;
86552     __IOM uint32_t DIEPINT4;                         /*!< (@ 0x00000988) Device IN Endpoint 4 Interrupt Register               */
86553     __IM uint32_t RESERVED24;
86554     __IOM uint32_t DIEPTSIZ4;                        /*!< (@ 0x00000990) Device IN Endpoint 4 Transfer Size Register           */
86555     __IOM uint32_t DIEPDMA4;                         /*!< (@ 0x00000994) Device IN Endpoint 4 DMA Address Register             */
86556     __IOM uint32_t DTXFSTS4;                         /*!< (@ 0x00000998) Device IN Endpoint Transmit FIFO Status Register 4    */
86557     __IM uint32_t RESERVED25;
86558     __IOM uint32_t DIEPCTL5;                         /*!< (@ 0x000009A0) Device Control IN Endpoint 5 Control Register         */
86559     __IM uint32_t RESERVED26;
86560     __IOM uint32_t DIEPINT5;                         /*!< (@ 0x000009A8) Device IN Endpoint 5 Interrupt Register               */
86561     __IM uint32_t RESERVED27;
86562     __IOM uint32_t DIEPTSIZ5;                        /*!< (@ 0x000009B0) Device IN Endpoint 5 Transfer Size Register           */
86563     __IOM uint32_t DIEPDMA5;                         /*!< (@ 0x000009B4) Device IN Endpoint 5 DMA Address Register             */
86564     __IOM uint32_t DTXFSTS5;                         /*!< (@ 0x000009B8) Device IN Endpoint Transmit FIFO Status Register 5    */
86565     __IM uint32_t RESERVED28;
86566     __IOM uint32_t DIEPCTL6;                         /*!< (@ 0x000009C0) Device Control IN Endpoint 6 Control Register         */
86567     __IM uint32_t RESERVED29;
86568     __IOM uint32_t DIEPINT6;                         /*!< (@ 0x000009C8) Device IN Endpoint 6 Interrupt Register               */
86569     __IM uint32_t RESERVED30;
86570     __IOM uint32_t DIEPTSIZ6;                        /*!< (@ 0x000009D0) Device IN Endpoint 6 Transfer Size Register           */
86571     __IOM uint32_t DIEPDMA6;                         /*!< (@ 0x000009D4) Device IN Endpoint 6 DMA Address Register             */
86572     __IOM uint32_t DTXFSTS6;                         /*!< (@ 0x000009D8) Device IN Endpoint Transmit FIFO Status Register 6    */
86573     __IM uint32_t RESERVED31;
86574     __IOM uint32_t DIEPCTL7;                         /*!< (@ 0x000009E0) Device Control IN Endpoint 7 Control Register         */
86575     __IM uint32_t RESERVED32;
86576     __IOM uint32_t DIEPINT7;                         /*!< (@ 0x000009E8) Device IN Endpoint 7 Interrupt Register               */
86577     __IM uint32_t RESERVED33;
86578     __IOM uint32_t DIEPTSIZ7;                        /*!< (@ 0x000009F0) Device IN Endpoint 7 Transfer Size Register           */
86579     __IOM uint32_t DIEPDMA7;                         /*!< (@ 0x000009F4) Device IN Endpoint 7 DMA Address Register             */
86580     __IOM uint32_t DTXFSTS7;                         /*!< (@ 0x000009F8) Device IN Endpoint Transmit FIFO Status Register 7    */
86581     __IM uint32_t RESERVED34;
86582     __IOM uint32_t DIEPCTL8;                         /*!< (@ 0x00000A00) Device Control IN Endpoint 8 Control Register         */
86583     __IM uint32_t RESERVED35;
86584     __IOM uint32_t DIEPINT8;                         /*!< (@ 0x00000A08) Device IN Endpoint 8 Interrupt Register               */
86585     __IM uint32_t RESERVED36;
86586     __IOM uint32_t DIEPTSIZ8;                        /*!< (@ 0x00000A10) Device IN Endpoint 8 Transfer Size Register           */
86587     __IOM uint32_t DIEPDMA8;                         /*!< (@ 0x00000A14) Device IN Endpoint 8 DMA Address Register             */
86588     __IOM uint32_t DTXFSTS8;                         /*!< (@ 0x00000A18) Device IN Endpoint Transmit FIFO Status Register 8    */
86589     __IM uint32_t RESERVED37;
86590     __IOM uint32_t DIEPCTL9;                         /*!< (@ 0x00000A20) Device Control IN Endpoint 9 Control Register         */
86591     __IM uint32_t RESERVED38;
86592     __IOM uint32_t DIEPINT9;                         /*!< (@ 0x00000A28) Device IN Endpoint 9 Interrupt Register               */
86593     __IM uint32_t RESERVED39;
86594     __IOM uint32_t DIEPTSIZ9;                        /*!< (@ 0x00000A30) Device IN Endpoint 9 Transfer Size Register           */
86595     __IOM uint32_t DIEPDMA9;                         /*!< (@ 0x00000A34) Device IN Endpoint 9 DMA Address Register             */
86596     __IOM uint32_t DTXFSTS9;                         /*!< (@ 0x00000A38) Device IN Endpoint Transmit FIFO Status Register 9    */
86597     __IM uint32_t RESERVED40;
86598     __IOM uint32_t DIEPCTL10;                        /*!< (@ 0x00000A40) Device Control IN Endpoint 10 Control Register        */
86599     __IM uint32_t RESERVED41;
86600     __IOM uint32_t DIEPINT10;                        /*!< (@ 0x00000A48) Device IN Endpoint 10 Interrupt Register              */
86601     __IM uint32_t RESERVED42;
86602     __IOM uint32_t DIEPTSIZ10;                       /*!< (@ 0x00000A50) Device IN Endpoint 10 Transfer Size Register          */
86603     __IOM uint32_t DIEPDMA10;                        /*!< (@ 0x00000A54) Device IN Endpoint 10 DMA Address Register            */
86604     __IOM uint32_t DTXFSTS10;                        /*!< (@ 0x00000A58) Device IN Endpoint Transmit FIFO Status Register 10   */
86605     __IM uint32_t RESERVED43;
86606     __IOM uint32_t DIEPCTL11;                        /*!< (@ 0x00000A60) Device Control IN Endpoint 11 Control Register        */
86607     __IM uint32_t RESERVED44;
86608     __IOM uint32_t DIEPINT11;                        /*!< (@ 0x00000A68) Device IN Endpoint 11 Interrupt Register              */
86609     __IM uint32_t RESERVED45;
86610     __IOM uint32_t DIEPTSIZ11;                       /*!< (@ 0x00000A70) Device IN Endpoint 11 Transfer Size Register          */
86611     __IOM uint32_t DIEPDMA11;                        /*!< (@ 0x00000A74) Device IN Endpoint 11 DMA Address Register            */
86612     __IOM uint32_t DTXFSTS11;                        /*!< (@ 0x00000A78) Device IN Endpoint Transmit FIFO Status Register 11   */
86613     __IM uint32_t RESERVED46[33];
86614     __IOM uint32_t DOEPCTL0;                         /*!< (@ 0x00000B00) Device Control OUT Endpoint 0 Control Register        */
86615     __IM uint32_t RESERVED47;
86616     __IOM uint32_t DOEPINT0;                         /*!< (@ 0x00000B08) Device OUT Endpoint 0 Interrupt Register              */
86617     __IM uint32_t RESERVED48;
86618     __IOM uint32_t DOEPTSIZ0;                        /*!< (@ 0x00000B10) Device OUT Endpoint 0 Transfer Size Register          */
86619     __IOM uint32_t DOEPDMA0;                         /*!< (@ 0x00000B14) Device OUT Endpoint 0 DMA Address Register            */
86620     __IM uint32_t RESERVED49[2];
86621     __IOM uint32_t DOEPCTL1;                         /*!< (@ 0x00000B20) Device Control OUT Endpoint 1 Control Register        */
86622     __IM uint32_t RESERVED50;
86623     __IOM uint32_t DOEPINT1;                         /*!< (@ 0x00000B28) Device OUT Endpoint 1 Interrupt Register              */
86624     __IM uint32_t RESERVED51;
86625     __IOM uint32_t DOEPTSIZ1;                        /*!< (@ 0x00000B30) Device OUT Endpoint 1 Transfer Size Register          */
86626     __IOM uint32_t DOEPDMA1;                         /*!< (@ 0x00000B34) Device OUT Endpoint 1 DMA Address Register            */
86627     __IM uint32_t RESERVED52[2];
86628     __IOM uint32_t DOEPCTL2;                         /*!< (@ 0x00000B40) Device Control OUT Endpoint 2 Control Register        */
86629     __IM uint32_t RESERVED53;
86630     __IOM uint32_t DOEPINT2;                         /*!< (@ 0x00000B48) Device OUT Endpoint 2 Interrupt Register              */
86631     __IM uint32_t RESERVED54;
86632     __IOM uint32_t DOEPTSIZ2;                        /*!< (@ 0x00000B50) Device OUT Endpoint 2 Transfer Size Register          */
86633     __IOM uint32_t DOEPDMA2;                         /*!< (@ 0x00000B54) Device OUT Endpoint 2 DMA Address Register            */
86634     __IM uint32_t RESERVED55[2];
86635     __IOM uint32_t DOEPCTL3;                         /*!< (@ 0x00000B60) Device Control OUT Endpoint 3 Control Register        */
86636     __IM uint32_t RESERVED56;
86637     __IOM uint32_t DOEPINT3;                         /*!< (@ 0x00000B68) Device OUT Endpoint 3 Interrupt Register              */
86638     __IM uint32_t RESERVED57;
86639     __IOM uint32_t DOEPTSIZ3;                        /*!< (@ 0x00000B70) Device OUT Endpoint 3 Transfer Size Register          */
86640     __IOM uint32_t DOEPDMA3;                         /*!< (@ 0x00000B74) Device OUT Endpoint 3 DMA Address Register            */
86641     __IM uint32_t RESERVED58[2];
86642     __IOM uint32_t DOEPCTL4;                         /*!< (@ 0x00000B80) Device Control OUT Endpoint 4 Control Register        */
86643     __IM uint32_t RESERVED59;
86644     __IOM uint32_t DOEPINT4;                         /*!< (@ 0x00000B88) Device OUT Endpoint 4 Interrupt Register              */
86645     __IM uint32_t RESERVED60;
86646     __IOM uint32_t DOEPTSIZ4;                        /*!< (@ 0x00000B90) Device OUT Endpoint 4 Transfer Size Register          */
86647     __IOM uint32_t DOEPDMA4;                         /*!< (@ 0x00000B94) Device OUT Endpoint 4 DMA Address Register            */
86648     __IM uint32_t RESERVED61[2];
86649     __IOM uint32_t DOEPCTL5;                         /*!< (@ 0x00000BA0) Device Control OUT Endpoint 5 Control Register        */
86650     __IM uint32_t RESERVED62;
86651     __IOM uint32_t DOEPINT5;                         /*!< (@ 0x00000BA8) Device OUT Endpoint 5 Interrupt Register              */
86652     __IM uint32_t RESERVED63;
86653     __IOM uint32_t DOEPTSIZ5;                        /*!< (@ 0x00000BB0) Device OUT Endpoint 5 Transfer Size Register          */
86654     __IOM uint32_t DOEPDMA5;                         /*!< (@ 0x00000BB4) Device OUT Endpoint 5 DMA Address Register            */
86655     __IM uint32_t RESERVED64[50];
86656     __IOM uint32_t DOEPCTL12;                        /*!< (@ 0x00000C80) Device Control OUT Endpoint 12 Control Register       */
86657     __IM uint32_t RESERVED65;
86658     __IOM uint32_t DOEPINT12;                        /*!< (@ 0x00000C88) Device OUT Endpoint 12 Interrupt Register             */
86659     __IM uint32_t RESERVED66;
86660     __IOM uint32_t DOEPTSIZ12;                       /*!< (@ 0x00000C90) Device OUT Endpoint 12 Transfer Size Register         */
86661     __IOM uint32_t DOEPDMA12;                        /*!< (@ 0x00000C94) Device OUT Endpoint 12 DMA Address Register           */
86662     __IM uint32_t RESERVED67[2];
86663     __IOM uint32_t DOEPCTL13;                        /*!< (@ 0x00000CA0) Device Control OUT Endpoint 13 Control Register       */
86664     __IM uint32_t RESERVED68;
86665     __IOM uint32_t DOEPINT13;                        /*!< (@ 0x00000CA8) Device OUT Endpoint 13 Interrupt Register             */
86666     __IM uint32_t RESERVED69;
86667     __IOM uint32_t DOEPTSIZ13;                       /*!< (@ 0x00000CB0) Device OUT Endpoint 13 Transfer Size Register         */
86668     __IOM uint32_t DOEPDMA13;                        /*!< (@ 0x00000CB4) Device OUT Endpoint 13 DMA Address Register           */
86669     __IM uint32_t RESERVED70[2];
86670     __IOM uint32_t DOEPCTL14;                        /*!< (@ 0x00000CC0) Device Control OUT Endpoint 14 Control Register       */
86671     __IM uint32_t RESERVED71;
86672     __IOM uint32_t DOEPINT14;                        /*!< (@ 0x00000CC8) Device OUT Endpoint 14 Interrupt Register             */
86673     __IM uint32_t RESERVED72;
86674     __IOM uint32_t DOEPTSIZ14;                       /*!< (@ 0x00000CD0) Device OUT Endpoint 14 Transfer Size Register         */
86675     __IOM uint32_t DOEPDMA14;                        /*!< (@ 0x00000CD4) Device OUT Endpoint 14 DMA Address Register           */
86676     __IM uint32_t RESERVED73[2];
86677     __IOM uint32_t DOEPCTL15;                        /*!< (@ 0x00000CE0) Device Control OUT Endpoint 15 Control Register       */
86678     __IM uint32_t RESERVED74;
86679     __IOM uint32_t DOEPINT15;                        /*!< (@ 0x00000CE8) Device OUT Endpoint 15 Interrupt Register             */
86680     __IM uint32_t RESERVED75;
86681     __IOM uint32_t DOEPTSIZ15;                       /*!< (@ 0x00000CF0) Device OUT Endpoint 15 Transfer Size Register         */
86682     __IOM uint32_t DOEPDMA15;                        /*!< (@ 0x00000CF4) Device OUT Endpoint 15 DMA Address Register           */
86683     __IM uint32_t RESERVED76[66];
86684     __IOM uint32_t PCGCCTL;                          /*!< (@ 0x00000E00) Power and Clock Gating Control Register               */
86685     __IM uint32_t RESERVED77[127];
86686     __IOM NRF_USBHSCORE_DWCOTGDFIFO_Type DWCOTGDFIFO[16]; /*!< (@ 0x00001000) (unspecified)                                    */
86687     __IM uint32_t RESERVED78[15344];
86688     __IOM NRF_USBHSCORE_DWCOTGDFIFODIRECTACCESS_Type DWCOTGDFIFODIRECTACCESS; /*!< (@ 0x00020000) (unspecified)                */
86689   } NRF_USBHSCORE_Type;                              /*!< Size = 147460 (0x24004)                                              */
86690 
86691 /* USBHSCORE_GOTGCTL: OTG Control and Status Register */
86692   #define USBHSCORE_GOTGCTL_ResetValue (0x000D0000UL) /*!< Reset value of GOTGCTL register.                                    */
86693 
86694 /* SESREQSCS @Bit 0 : Mode: Device only. Session Request Success (SesReqScs) */
86695   #define USBHSCORE_GOTGCTL_SESREQSCS_Pos (0UL)      /*!< Position of SESREQSCS field.                                         */
86696   #define USBHSCORE_GOTGCTL_SESREQSCS_Msk (0x1UL << USBHSCORE_GOTGCTL_SESREQSCS_Pos) /*!< Bit mask of SESREQSCS field.         */
86697   #define USBHSCORE_GOTGCTL_SESREQSCS_Min (0x0UL)    /*!< Min enumerator value of SESREQSCS field.                             */
86698   #define USBHSCORE_GOTGCTL_SESREQSCS_Max (0x1UL)    /*!< Max enumerator value of SESREQSCS field.                             */
86699   #define USBHSCORE_GOTGCTL_SESREQSCS_FAIL (0x0UL)   /*!< (unspecified)                                                        */
86700   #define USBHSCORE_GOTGCTL_SESREQSCS_SUCCESS (0x1UL) /*!< (unspecified)                                                       */
86701 
86702 /* SESREQ @Bit 1 : Mode: Device only. Session Request (SesReq) */
86703   #define USBHSCORE_GOTGCTL_SESREQ_Pos (1UL)         /*!< Position of SESREQ field.                                            */
86704   #define USBHSCORE_GOTGCTL_SESREQ_Msk (0x1UL << USBHSCORE_GOTGCTL_SESREQ_Pos) /*!< Bit mask of SESREQ field.                  */
86705   #define USBHSCORE_GOTGCTL_SESREQ_Min (0x0UL)       /*!< Min enumerator value of SESREQ field.                                */
86706   #define USBHSCORE_GOTGCTL_SESREQ_Max (0x1UL)       /*!< Max enumerator value of SESREQ field.                                */
86707   #define USBHSCORE_GOTGCTL_SESREQ_NOREQUEST (0x0UL) /*!< (unspecified)                                                        */
86708   #define USBHSCORE_GOTGCTL_SESREQ_REQUEST (0x1UL)   /*!< (unspecified)                                                        */
86709 
86710 /* VBVALIDOVEN @Bit 2 : Mode: Host only. VBUS Valid Override Enable (VbvalidOvEn) */
86711   #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Pos (2UL)    /*!< Position of VBVALIDOVEN field.                                       */
86712   #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_VBVALIDOVEN_Pos) /*!< Bit mask of VBVALIDOVEN field.   */
86713   #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Min (0x0UL)  /*!< Min enumerator value of VBVALIDOVEN field.                           */
86714   #define USBHSCORE_GOTGCTL_VBVALIDOVEN_Max (0x1UL)  /*!< Max enumerator value of VBVALIDOVEN field.                           */
86715   #define USBHSCORE_GOTGCTL_VBVALIDOVEN_DISABLED (0x0UL) /*!< (unspecified)                                                    */
86716   #define USBHSCORE_GOTGCTL_VBVALIDOVEN_ENABLED (0x1UL) /*!< (unspecified)                                                     */
86717 
86718 /* VBVALIDOVVAL @Bit 3 : Mode: Host only. VBUS Valid OverrideValue (VbvalidOvVal) */
86719   #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Pos (3UL)   /*!< Position of VBVALIDOVVAL field.                                      */
86720   #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_VBVALIDOVVAL_Pos) /*!< Bit mask of VBVALIDOVVAL field.*/
86721   #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Min (0x0UL) /*!< Min enumerator value of VBVALIDOVVAL field.                          */
86722   #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_Max (0x1UL) /*!< Max enumerator value of VBVALIDOVVAL field.                          */
86723   #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_SET0 (0x0UL) /*!< (unspecified)                                                       */
86724   #define USBHSCORE_GOTGCTL_VBVALIDOVVAL_SET1 (0x1UL) /*!< (unspecified)                                                       */
86725 
86726 /* AVALIDOVEN @Bit 4 : Mode: Host only. A-Peripheral Session Valid Override Enable (AvalidOvEn) */
86727   #define USBHSCORE_GOTGCTL_AVALIDOVEN_Pos (4UL)     /*!< Position of AVALIDOVEN field.                                        */
86728   #define USBHSCORE_GOTGCTL_AVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_AVALIDOVEN_Pos) /*!< Bit mask of AVALIDOVEN field.      */
86729   #define USBHSCORE_GOTGCTL_AVALIDOVEN_Min (0x0UL)   /*!< Min enumerator value of AVALIDOVEN field.                            */
86730   #define USBHSCORE_GOTGCTL_AVALIDOVEN_Max (0x1UL)   /*!< Max enumerator value of AVALIDOVEN field.                            */
86731   #define USBHSCORE_GOTGCTL_AVALIDOVEN_DISABLED (0x0UL) /*!< (unspecified)                                                     */
86732   #define USBHSCORE_GOTGCTL_AVALIDOVEN_ENABLED (0x1UL) /*!< (unspecified)                                                      */
86733 
86734 /* AVALIDOVVAL @Bit 5 : Mode: Host only A-Peripheral Session Valid OverrideValue (AvalidOvVal) */
86735   #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Pos (5UL)    /*!< Position of AVALIDOVVAL field.                                       */
86736   #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_AVALIDOVVAL_Pos) /*!< Bit mask of AVALIDOVVAL field.   */
86737   #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Min (0x0UL)  /*!< Min enumerator value of AVALIDOVVAL field.                           */
86738   #define USBHSCORE_GOTGCTL_AVALIDOVVAL_Max (0x1UL)  /*!< Max enumerator value of AVALIDOVVAL field.                           */
86739   #define USBHSCORE_GOTGCTL_AVALIDOVVAL_VALUE0 (0x0UL) /*!< (unspecified)                                                      */
86740   #define USBHSCORE_GOTGCTL_AVALIDOVVAL_VALUE1 (0x1UL) /*!< (unspecified)                                                      */
86741 
86742 /* BVALIDOVEN @Bit 6 : Mode: Device only. B-Peripheral Session Valid Override Value (BvalidOvEn) */
86743   #define USBHSCORE_GOTGCTL_BVALIDOVEN_Pos (6UL)     /*!< Position of BVALIDOVEN field.                                        */
86744   #define USBHSCORE_GOTGCTL_BVALIDOVEN_Msk (0x1UL << USBHSCORE_GOTGCTL_BVALIDOVEN_Pos) /*!< Bit mask of BVALIDOVEN field.      */
86745   #define USBHSCORE_GOTGCTL_BVALIDOVEN_Min (0x0UL)   /*!< Min enumerator value of BVALIDOVEN field.                            */
86746   #define USBHSCORE_GOTGCTL_BVALIDOVEN_Max (0x1UL)   /*!< Max enumerator value of BVALIDOVEN field.                            */
86747   #define USBHSCORE_GOTGCTL_BVALIDOVEN_DISABLED (0x0UL) /*!< (unspecified)                                                     */
86748   #define USBHSCORE_GOTGCTL_BVALIDOVEN_ENABLED (0x1UL) /*!< (unspecified)                                                      */
86749 
86750 /* BVALIDOVVAL @Bit 7 : Mode: Device only. B-Peripheral Session Valid OverrideValue (BvalidOvVal) */
86751   #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Pos (7UL)    /*!< Position of BVALIDOVVAL field.                                       */
86752   #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Msk (0x1UL << USBHSCORE_GOTGCTL_BVALIDOVVAL_Pos) /*!< Bit mask of BVALIDOVVAL field.   */
86753   #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Min (0x0UL)  /*!< Min enumerator value of BVALIDOVVAL field.                           */
86754   #define USBHSCORE_GOTGCTL_BVALIDOVVAL_Max (0x1UL)  /*!< Max enumerator value of BVALIDOVVAL field.                           */
86755   #define USBHSCORE_GOTGCTL_BVALIDOVVAL_VALUE0 (0x0UL) /*!< (unspecified)                                                      */
86756   #define USBHSCORE_GOTGCTL_BVALIDOVVAL_VALUE1 (0x1UL) /*!< (unspecified)                                                      */
86757 
86758 /* DBNCEFLTRBYPASS @Bit 15 : Mode: Host and Device */
86759   #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Pos (15UL) /*!< Position of DBNCEFLTRBYPASS field.                                 */
86760   #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Msk (0x1UL << USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Pos) /*!< Bit mask of
86761                                                                             DBNCEFLTRBYPASS field.*/
86762   #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Min (0x0UL) /*!< Min enumerator value of DBNCEFLTRBYPASS field.                    */
86763   #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_Max (0x1UL) /*!< Max enumerator value of DBNCEFLTRBYPASS field.                    */
86764   #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_DISABLED (0x0UL) /*!< (unspecified)                                                */
86765   #define USBHSCORE_GOTGCTL_DBNCEFLTRBYPASS_ENABLED (0x1UL) /*!< (unspecified)                                                 */
86766 
86767 /* CONIDSTS @Bit 16 : Mode: Host and Device. Connector ID Status (ConIDSts) */
86768   #define USBHSCORE_GOTGCTL_CONIDSTS_Pos (16UL)      /*!< Position of CONIDSTS field.                                          */
86769   #define USBHSCORE_GOTGCTL_CONIDSTS_Msk (0x1UL << USBHSCORE_GOTGCTL_CONIDSTS_Pos) /*!< Bit mask of CONIDSTS field.            */
86770   #define USBHSCORE_GOTGCTL_CONIDSTS_Min (0x0UL)     /*!< Min enumerator value of CONIDSTS field.                              */
86771   #define USBHSCORE_GOTGCTL_CONIDSTS_Max (0x1UL)     /*!< Max enumerator value of CONIDSTS field.                              */
86772   #define USBHSCORE_GOTGCTL_CONIDSTS_MODEA (0x0UL)   /*!< (unspecified)                                                        */
86773   #define USBHSCORE_GOTGCTL_CONIDSTS_MODEB (0x1UL)   /*!< (unspecified)                                                        */
86774 
86775 /* DBNCTIME @Bit 17 : Mode: Host only. Long/Short Debounce Time (DbncTime) */
86776   #define USBHSCORE_GOTGCTL_DBNCTIME_Pos (17UL)      /*!< Position of DBNCTIME field.                                          */
86777   #define USBHSCORE_GOTGCTL_DBNCTIME_Msk (0x1UL << USBHSCORE_GOTGCTL_DBNCTIME_Pos) /*!< Bit mask of DBNCTIME field.            */
86778   #define USBHSCORE_GOTGCTL_DBNCTIME_Min (0x0UL)     /*!< Min enumerator value of DBNCTIME field.                              */
86779   #define USBHSCORE_GOTGCTL_DBNCTIME_Max (0x1UL)     /*!< Max enumerator value of DBNCTIME field.                              */
86780   #define USBHSCORE_GOTGCTL_DBNCTIME_LONG (0x0UL)    /*!< (unspecified)                                                        */
86781   #define USBHSCORE_GOTGCTL_DBNCTIME_SHORT (0x1UL)   /*!< (unspecified)                                                        */
86782 
86783 /* ASESVLD @Bit 18 : Mode: Host only. A-Session Valid (ASesVld) */
86784   #define USBHSCORE_GOTGCTL_ASESVLD_Pos (18UL)       /*!< Position of ASESVLD field.                                           */
86785   #define USBHSCORE_GOTGCTL_ASESVLD_Msk (0x1UL << USBHSCORE_GOTGCTL_ASESVLD_Pos) /*!< Bit mask of ASESVLD field.               */
86786   #define USBHSCORE_GOTGCTL_ASESVLD_Min (0x0UL)      /*!< Min enumerator value of ASESVLD field.                               */
86787   #define USBHSCORE_GOTGCTL_ASESVLD_Max (0x1UL)      /*!< Max enumerator value of ASESVLD field.                               */
86788   #define USBHSCORE_GOTGCTL_ASESVLD_NOTVALID (0x0UL) /*!< (unspecified)                                                        */
86789   #define USBHSCORE_GOTGCTL_ASESVLD_VALID (0x1UL)    /*!< (unspecified)                                                        */
86790 
86791 /* BSESVLD @Bit 19 : Mode: Device only. B-Session Valid (BSesVld) */
86792   #define USBHSCORE_GOTGCTL_BSESVLD_Pos (19UL)       /*!< Position of BSESVLD field.                                           */
86793   #define USBHSCORE_GOTGCTL_BSESVLD_Msk (0x1UL << USBHSCORE_GOTGCTL_BSESVLD_Pos) /*!< Bit mask of BSESVLD field.               */
86794   #define USBHSCORE_GOTGCTL_BSESVLD_Min (0x0UL)      /*!< Min enumerator value of BSESVLD field.                               */
86795   #define USBHSCORE_GOTGCTL_BSESVLD_Max (0x1UL)      /*!< Max enumerator value of BSESVLD field.                               */
86796   #define USBHSCORE_GOTGCTL_BSESVLD_NOTVALID (0x0UL) /*!< (unspecified)                                                        */
86797   #define USBHSCORE_GOTGCTL_BSESVLD_VALID (0x1UL)    /*!< (unspecified)                                                        */
86798 
86799 /* OTGVER @Bit 20 : OTG Version (OTGVer) */
86800   #define USBHSCORE_GOTGCTL_OTGVER_Pos (20UL)        /*!< Position of OTGVER field.                                            */
86801   #define USBHSCORE_GOTGCTL_OTGVER_Msk (0x1UL << USBHSCORE_GOTGCTL_OTGVER_Pos) /*!< Bit mask of OTGVER field.                  */
86802   #define USBHSCORE_GOTGCTL_OTGVER_Min (0x0UL)       /*!< Min enumerator value of OTGVER field.                                */
86803   #define USBHSCORE_GOTGCTL_OTGVER_Max (0x1UL)       /*!< Max enumerator value of OTGVER field.                                */
86804   #define USBHSCORE_GOTGCTL_OTGVER_VER13 (0x0UL)     /*!< (unspecified)                                                        */
86805   #define USBHSCORE_GOTGCTL_OTGVER_VER20 (0x1UL)     /*!< (unspecified)                                                        */
86806 
86807 /* CURMOD @Bit 21 : Current Mode of Operation (CurMod) */
86808   #define USBHSCORE_GOTGCTL_CURMOD_Pos (21UL)        /*!< Position of CURMOD field.                                            */
86809   #define USBHSCORE_GOTGCTL_CURMOD_Msk (0x1UL << USBHSCORE_GOTGCTL_CURMOD_Pos) /*!< Bit mask of CURMOD field.                  */
86810   #define USBHSCORE_GOTGCTL_CURMOD_Min (0x0UL)       /*!< Min enumerator value of CURMOD field.                                */
86811   #define USBHSCORE_GOTGCTL_CURMOD_Max (0x1UL)       /*!< Max enumerator value of CURMOD field.                                */
86812   #define USBHSCORE_GOTGCTL_CURMOD_DEVICEMODE (0x0UL) /*!< (unspecified)                                                       */
86813   #define USBHSCORE_GOTGCTL_CURMOD_HOSTMODE (0x1UL)  /*!< (unspecified)                                                        */
86814 
86815 /* MULTVALIDBC @Bits 22..26 : Mode: Host and Device. Multi Valued ID pin (MultValIdBC) */
86816   #define USBHSCORE_GOTGCTL_MULTVALIDBC_Pos (22UL)   /*!< Position of MULTVALIDBC field.                                       */
86817   #define USBHSCORE_GOTGCTL_MULTVALIDBC_Msk (0x1FUL << USBHSCORE_GOTGCTL_MULTVALIDBC_Pos) /*!< Bit mask of MULTVALIDBC field.  */
86818   #define USBHSCORE_GOTGCTL_MULTVALIDBC_Min (0x1UL)  /*!< Min enumerator value of MULTVALIDBC field.                           */
86819   #define USBHSCORE_GOTGCTL_MULTVALIDBC_Max (0x10UL) /*!< Max enumerator value of MULTVALIDBC field.                           */
86820   #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_C (0x01UL) /*!< (unspecified)                                                      */
86821   #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_B (0x02UL) /*!< (unspecified)                                                      */
86822   #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_A (0x04UL) /*!< (unspecified)                                                      */
86823   #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_GND (0x08UL) /*!< (unspecified)                                                    */
86824   #define USBHSCORE_GOTGCTL_MULTVALIDBC_RID_FLOAT (0x10UL) /*!< (unspecified)                                                  */
86825 
86826 /* CHIRPEN @Bit 27 : Mode: Device Only */
86827   #define USBHSCORE_GOTGCTL_CHIRPEN_Pos (27UL)       /*!< Position of CHIRPEN field.                                           */
86828   #define USBHSCORE_GOTGCTL_CHIRPEN_Msk (0x1UL << USBHSCORE_GOTGCTL_CHIRPEN_Pos) /*!< Bit mask of CHIRPEN field.               */
86829   #define USBHSCORE_GOTGCTL_CHIRPEN_Min (0x0UL)      /*!< Min enumerator value of CHIRPEN field.                               */
86830   #define USBHSCORE_GOTGCTL_CHIRPEN_Max (0x1UL)      /*!< Max enumerator value of CHIRPEN field.                               */
86831   #define USBHSCORE_GOTGCTL_CHIRPEN_CHIRP_DISABLE (0x0UL) /*!< (unspecified)                                                   */
86832   #define USBHSCORE_GOTGCTL_CHIRPEN_CHIRP_ENABLE (0x1UL) /*!< (unspecified)                                                    */
86833 
86834 
86835 /* USBHSCORE_GOTGINT: OTG Interrupt Register */
86836   #define USBHSCORE_GOTGINT_ResetValue (0x00000000UL) /*!< Reset value of GOTGINT register.                                    */
86837 
86838 /* SESENDDET @Bit 2 : Mode: Host and Device. Session End Detected (SesEndDet) */
86839   #define USBHSCORE_GOTGINT_SESENDDET_Pos (2UL)      /*!< Position of SESENDDET field.                                         */
86840   #define USBHSCORE_GOTGINT_SESENDDET_Msk (0x1UL << USBHSCORE_GOTGINT_SESENDDET_Pos) /*!< Bit mask of SESENDDET field.         */
86841   #define USBHSCORE_GOTGINT_SESENDDET_Min (0x0UL)    /*!< Min enumerator value of SESENDDET field.                             */
86842   #define USBHSCORE_GOTGINT_SESENDDET_Max (0x1UL)    /*!< Max enumerator value of SESENDDET field.                             */
86843   #define USBHSCORE_GOTGINT_SESENDDET_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
86844   #define USBHSCORE_GOTGINT_SESENDDET_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
86845 
86846 /* SESREQSUCSTSCHNG @Bit 8 : Mode: Host and Device. Session Request Success Status Change (SesReqSucStsChng) */
86847   #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Pos (8UL) /*!< Position of SESREQSUCSTSCHNG field.                                */
86848   #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Pos) /*!< Bit mask of
86849                                                                             SESREQSUCSTSCHNG field.*/
86850   #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Min (0x0UL) /*!< Min enumerator value of SESREQSUCSTSCHNG field.                  */
86851   #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_Max (0x1UL) /*!< Max enumerator value of SESREQSUCSTSCHNG field.                  */
86852   #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_INACTIVE (0x0UL) /*!< (unspecified)                                               */
86853   #define USBHSCORE_GOTGINT_SESREQSUCSTSCHNG_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
86854 
86855 /* HSTNEGSUCSTSCHNG @Bit 9 : Mode: Host and Device. Host Negotiation Success Status Change (HstNegSucStsChng) */
86856   #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Pos (9UL) /*!< Position of HSTNEGSUCSTSCHNG field.                                */
86857   #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Pos) /*!< Bit mask of
86858                                                                             HSTNEGSUCSTSCHNG field.*/
86859   #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Min (0x0UL) /*!< Min enumerator value of HSTNEGSUCSTSCHNG field.                  */
86860   #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_Max (0x1UL) /*!< Max enumerator value of HSTNEGSUCSTSCHNG field.                  */
86861   #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_INACTIVE (0x0UL) /*!< (unspecified)                                               */
86862   #define USBHSCORE_GOTGINT_HSTNEGSUCSTSCHNG_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
86863 
86864 /* HSTNEGDET @Bit 17 : Mode:Host and Device. Host Negotiation Detected (HstNegDet) */
86865   #define USBHSCORE_GOTGINT_HSTNEGDET_Pos (17UL)     /*!< Position of HSTNEGDET field.                                         */
86866   #define USBHSCORE_GOTGINT_HSTNEGDET_Msk (0x1UL << USBHSCORE_GOTGINT_HSTNEGDET_Pos) /*!< Bit mask of HSTNEGDET field.         */
86867   #define USBHSCORE_GOTGINT_HSTNEGDET_Min (0x0UL)    /*!< Min enumerator value of HSTNEGDET field.                             */
86868   #define USBHSCORE_GOTGINT_HSTNEGDET_Max (0x1UL)    /*!< Max enumerator value of HSTNEGDET field.                             */
86869   #define USBHSCORE_GOTGINT_HSTNEGDET_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
86870   #define USBHSCORE_GOTGINT_HSTNEGDET_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
86871 
86872 /* ADEVTOUTCHG @Bit 18 : Mode: Host and Device. A-Device Timeout Change (ADevTOUTChg) */
86873   #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Pos (18UL)   /*!< Position of ADEVTOUTCHG field.                                       */
86874   #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Msk (0x1UL << USBHSCORE_GOTGINT_ADEVTOUTCHG_Pos) /*!< Bit mask of ADEVTOUTCHG field.   */
86875   #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Min (0x0UL)  /*!< Min enumerator value of ADEVTOUTCHG field.                           */
86876   #define USBHSCORE_GOTGINT_ADEVTOUTCHG_Max (0x1UL)  /*!< Max enumerator value of ADEVTOUTCHG field.                           */
86877   #define USBHSCORE_GOTGINT_ADEVTOUTCHG_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
86878   #define USBHSCORE_GOTGINT_ADEVTOUTCHG_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
86879 
86880 /* DBNCEDONE @Bit 19 : Mode: Host only. Debounce Done (DbnceDone) */
86881   #define USBHSCORE_GOTGINT_DBNCEDONE_Pos (19UL)     /*!< Position of DBNCEDONE field.                                         */
86882   #define USBHSCORE_GOTGINT_DBNCEDONE_Msk (0x1UL << USBHSCORE_GOTGINT_DBNCEDONE_Pos) /*!< Bit mask of DBNCEDONE field.         */
86883   #define USBHSCORE_GOTGINT_DBNCEDONE_Min (0x0UL)    /*!< Min enumerator value of DBNCEDONE field.                             */
86884   #define USBHSCORE_GOTGINT_DBNCEDONE_Max (0x1UL)    /*!< Max enumerator value of DBNCEDONE field.                             */
86885   #define USBHSCORE_GOTGINT_DBNCEDONE_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
86886   #define USBHSCORE_GOTGINT_DBNCEDONE_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
86887 
86888 /* MULTVALIPCHNG @Bit 20 : This bit when set indicates that there is a change in the value of at least one ACA pin value. */
86889   #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Pos (20UL) /*!< Position of MULTVALIPCHNG field.                                     */
86890   #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Msk (0x1UL << USBHSCORE_GOTGINT_MULTVALIPCHNG_Pos) /*!< Bit mask of MULTVALIPCHNG
86891                                                                             field.*/
86892   #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Min (0x0UL) /*!< Min enumerator value of MULTVALIPCHNG field.                        */
86893   #define USBHSCORE_GOTGINT_MULTVALIPCHNG_Max (0x1UL) /*!< Max enumerator value of MULTVALIPCHNG field.                        */
86894   #define USBHSCORE_GOTGINT_MULTVALIPCHNG_NO_ACA_PIN_CHANGE (0x0UL) /*!< (unspecified)                                         */
86895   #define USBHSCORE_GOTGINT_MULTVALIPCHNG_ACA_PIN_CHANGE (0x1UL) /*!< (unspecified)                                            */
86896 
86897 
86898 /* USBHSCORE_GAHBCFG: AHB Configuration Register */
86899   #define USBHSCORE_GAHBCFG_ResetValue (0x00000000UL) /*!< Reset value of GAHBCFG register.                                    */
86900 
86901 /* GLBLINTRMSK @Bit 0 : Mode: Host and device. Global Interrupt Mask (GlblIntrMsk) */
86902   #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Pos (0UL)    /*!< Position of GLBLINTRMSK field.                                       */
86903   #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Msk (0x1UL << USBHSCORE_GAHBCFG_GLBLINTRMSK_Pos) /*!< Bit mask of GLBLINTRMSK field.   */
86904   #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Min (0x0UL)  /*!< Min enumerator value of GLBLINTRMSK field.                           */
86905   #define USBHSCORE_GAHBCFG_GLBLINTRMSK_Max (0x1UL)  /*!< Max enumerator value of GLBLINTRMSK field.                           */
86906   #define USBHSCORE_GAHBCFG_GLBLINTRMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
86907   #define USBHSCORE_GAHBCFG_GLBLINTRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
86908 
86909 /* HBSTLEN @Bits 1..4 : Mode: Host and device. Burst Length/Type (HBstLen) */
86910   #define USBHSCORE_GAHBCFG_HBSTLEN_Pos (1UL)        /*!< Position of HBSTLEN field.                                           */
86911   #define USBHSCORE_GAHBCFG_HBSTLEN_Msk (0xFUL << USBHSCORE_GAHBCFG_HBSTLEN_Pos) /*!< Bit mask of HBSTLEN field.               */
86912   #define USBHSCORE_GAHBCFG_HBSTLEN_Min (0x0UL)      /*!< Min enumerator value of HBSTLEN field.                               */
86913   #define USBHSCORE_GAHBCFG_HBSTLEN_Max (0x8UL)      /*!< Max enumerator value of HBSTLEN field.                               */
86914   #define USBHSCORE_GAHBCFG_HBSTLEN_WORD1ORSINGLE (0x0UL) /*!< (unspecified)                                                   */
86915   #define USBHSCORE_GAHBCFG_HBSTLEN_WORD4ORINCR (0x1UL) /*!< (unspecified)                                                     */
86916   #define USBHSCORE_GAHBCFG_HBSTLEN_WORD8 (0x2UL)    /*!< (unspecified)                                                        */
86917   #define USBHSCORE_GAHBCFG_HBSTLEN_WORD16ORINCR4 (0x3UL) /*!< (unspecified)                                                   */
86918   #define USBHSCORE_GAHBCFG_HBSTLEN_WORD32 (0x4UL)   /*!< (unspecified)                                                        */
86919   #define USBHSCORE_GAHBCFG_HBSTLEN_WORD64ORINCR8 (0x5UL) /*!< (unspecified)                                                   */
86920   #define USBHSCORE_GAHBCFG_HBSTLEN_WORD128 (0x6UL)  /*!< (unspecified)                                                        */
86921   #define USBHSCORE_GAHBCFG_HBSTLEN_WORD256ORINCR16 (0x7UL) /*!< (unspecified)                                                 */
86922   #define USBHSCORE_GAHBCFG_HBSTLEN_WORDX (0x8UL)    /*!< (unspecified)                                                        */
86923 
86924 /* DMAEN @Bit 5 : Mode: Host and device. DMA Enable (DMAEn) */
86925   #define USBHSCORE_GAHBCFG_DMAEN_Pos (5UL)          /*!< Position of DMAEN field.                                             */
86926   #define USBHSCORE_GAHBCFG_DMAEN_Msk (0x1UL << USBHSCORE_GAHBCFG_DMAEN_Pos) /*!< Bit mask of DMAEN field.                     */
86927   #define USBHSCORE_GAHBCFG_DMAEN_Min (0x0UL)        /*!< Min enumerator value of DMAEN field.                                 */
86928   #define USBHSCORE_GAHBCFG_DMAEN_Max (0x1UL)        /*!< Max enumerator value of DMAEN field.                                 */
86929   #define USBHSCORE_GAHBCFG_DMAEN_SLAVEMODE (0x0UL)  /*!< (unspecified)                                                        */
86930   #define USBHSCORE_GAHBCFG_DMAEN_DMAMODE (0x1UL)    /*!< (unspecified)                                                        */
86931 
86932 /* NPTXFEMPLVL @Bit 7 : Mode: Host and device. Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl) */
86933   #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Pos (7UL)    /*!< Position of NPTXFEMPLVL field.                                       */
86934   #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Msk (0x1UL << USBHSCORE_GAHBCFG_NPTXFEMPLVL_Pos) /*!< Bit mask of NPTXFEMPLVL field.   */
86935   #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Min (0x0UL)  /*!< Min enumerator value of NPTXFEMPLVL field.                           */
86936   #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_Max (0x1UL)  /*!< Max enumerator value of NPTXFEMPLVL field.                           */
86937   #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (0x0UL) /*!< (unspecified)                                                   */
86938   #define USBHSCORE_GAHBCFG_NPTXFEMPLVL_EMPTY (0x1UL) /*!< (unspecified)                                                       */
86939 
86940 /* REMMEMSUPP @Bit 21 : Mode: Host and Device. Remote Memory Support (RemMemSupp) */
86941   #define USBHSCORE_GAHBCFG_REMMEMSUPP_Pos (21UL)    /*!< Position of REMMEMSUPP field.                                        */
86942   #define USBHSCORE_GAHBCFG_REMMEMSUPP_Msk (0x1UL << USBHSCORE_GAHBCFG_REMMEMSUPP_Pos) /*!< Bit mask of REMMEMSUPP field.      */
86943   #define USBHSCORE_GAHBCFG_REMMEMSUPP_Min (0x0UL)   /*!< Min enumerator value of REMMEMSUPP field.                            */
86944   #define USBHSCORE_GAHBCFG_REMMEMSUPP_Max (0x1UL)   /*!< Max enumerator value of REMMEMSUPP field.                            */
86945   #define USBHSCORE_GAHBCFG_REMMEMSUPP_DISABLED (0x0UL) /*!< (unspecified)                                                     */
86946   #define USBHSCORE_GAHBCFG_REMMEMSUPP_ENABLED (0x1UL) /*!< (unspecified)                                                      */
86947 
86948 /* NOTIALLDMAWRIT @Bit 22 : Mode: Host and Device. Notify All DMA Write Transactions (NotiAllDmaWrit) */
86949   #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Pos (22UL) /*!< Position of NOTIALLDMAWRIT field.                                   */
86950   #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Msk (0x1UL << USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Pos) /*!< Bit mask of NOTIALLDMAWRIT
86951                                                                             field.*/
86952   #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Min (0x0UL) /*!< Min enumerator value of NOTIALLDMAWRIT field.                      */
86953   #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_Max (0x1UL) /*!< Max enumerator value of NOTIALLDMAWRIT field.                      */
86954   #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_LASTTRANS (0x0UL) /*!< (unspecified)                                                */
86955   #define USBHSCORE_GAHBCFG_NOTIALLDMAWRIT_ALLTRANS (0x1UL) /*!< (unspecified)                                                 */
86956 
86957 /* AHBSINGLE @Bit 23 : Mode: Host and Device. AHB Single Support (AHBSingle) */
86958   #define USBHSCORE_GAHBCFG_AHBSINGLE_Pos (23UL)     /*!< Position of AHBSINGLE field.                                         */
86959   #define USBHSCORE_GAHBCFG_AHBSINGLE_Msk (0x1UL << USBHSCORE_GAHBCFG_AHBSINGLE_Pos) /*!< Bit mask of AHBSINGLE field.         */
86960   #define USBHSCORE_GAHBCFG_AHBSINGLE_Min (0x0UL)    /*!< Min enumerator value of AHBSINGLE field.                             */
86961   #define USBHSCORE_GAHBCFG_AHBSINGLE_Max (0x1UL)    /*!< Max enumerator value of AHBSINGLE field.                             */
86962   #define USBHSCORE_GAHBCFG_AHBSINGLE_INCRBURST (0x0UL) /*!< (unspecified)                                                     */
86963   #define USBHSCORE_GAHBCFG_AHBSINGLE_SINGLEBURST (0x1UL) /*!< (unspecified)                                                   */
86964 
86965 
86966 /* USBHSCORE_GUSBCFG: USB Configuration Register */
86967   #define USBHSCORE_GUSBCFG_ResetValue (0x00001400UL) /*!< Reset value of GUSBCFG register.                                    */
86968 
86969 /* TOUTCAL @Bits 0..2 : Mode: Host and Device. HS/FS Timeout Calibration (TOutCal) */
86970   #define USBHSCORE_GUSBCFG_TOUTCAL_Pos (0UL)        /*!< Position of TOUTCAL field.                                           */
86971   #define USBHSCORE_GUSBCFG_TOUTCAL_Msk (0x7UL << USBHSCORE_GUSBCFG_TOUTCAL_Pos) /*!< Bit mask of TOUTCAL field.               */
86972 
86973 /* PHYIF @Bit 3 : Mode: Host and Device. PHY Interface (PHYIf) */
86974   #define USBHSCORE_GUSBCFG_PHYIF_Pos (3UL)          /*!< Position of PHYIF field.                                             */
86975   #define USBHSCORE_GUSBCFG_PHYIF_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYIF_Pos) /*!< Bit mask of PHYIF field.                     */
86976   #define USBHSCORE_GUSBCFG_PHYIF_Min (0x0UL)        /*!< Min enumerator value of PHYIF field.                                 */
86977   #define USBHSCORE_GUSBCFG_PHYIF_Max (0x1UL)        /*!< Max enumerator value of PHYIF field.                                 */
86978   #define USBHSCORE_GUSBCFG_PHYIF_BITS8 (0x0UL)      /*!< (unspecified)                                                        */
86979   #define USBHSCORE_GUSBCFG_PHYIF_BITS16 (0x1UL)     /*!< (unspecified)                                                        */
86980 
86981 /* ULPIUTMISEL @Bit 4 : Mode: Host and Device. ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
86982   #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Pos (4UL)    /*!< Position of ULPIUTMISEL field.                                       */
86983   #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Msk (0x1UL << USBHSCORE_GUSBCFG_ULPIUTMISEL_Pos) /*!< Bit mask of ULPIUTMISEL field.   */
86984   #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Min (0x0UL)  /*!< Min enumerator value of ULPIUTMISEL field.                           */
86985   #define USBHSCORE_GUSBCFG_ULPIUTMISEL_Max (0x1UL)  /*!< Max enumerator value of ULPIUTMISEL field.                           */
86986   #define USBHSCORE_GUSBCFG_ULPIUTMISEL_UTMI (0x0UL) /*!< (unspecified)                                                        */
86987   #define USBHSCORE_GUSBCFG_ULPIUTMISEL_ULPI (0x1UL) /*!< (unspecified)                                                        */
86988 
86989 /* FSINTF @Bit 5 : Mode: Host and Device. Full-Speed Serial Interface Select (FSIntf) */
86990   #define USBHSCORE_GUSBCFG_FSINTF_Pos (5UL)         /*!< Position of FSINTF field.                                            */
86991   #define USBHSCORE_GUSBCFG_FSINTF_Msk (0x1UL << USBHSCORE_GUSBCFG_FSINTF_Pos) /*!< Bit mask of FSINTF field.                  */
86992   #define USBHSCORE_GUSBCFG_FSINTF_Min (0x0UL)       /*!< Min enumerator value of FSINTF field.                                */
86993   #define USBHSCORE_GUSBCFG_FSINTF_Max (0x1UL)       /*!< Max enumerator value of FSINTF field.                                */
86994   #define USBHSCORE_GUSBCFG_FSINTF_FS6PIN (0x0UL)    /*!< (unspecified)                                                        */
86995   #define USBHSCORE_GUSBCFG_FSINTF_FS3PIN (0x1UL)    /*!< (unspecified)                                                        */
86996 
86997 /* PHYSEL @Bit 6 : PHYSel */
86998   #define USBHSCORE_GUSBCFG_PHYSEL_Pos (6UL)         /*!< Position of PHYSEL field.                                            */
86999   #define USBHSCORE_GUSBCFG_PHYSEL_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYSEL_Pos) /*!< Bit mask of PHYSEL field.                  */
87000   #define USBHSCORE_GUSBCFG_PHYSEL_Min (0x0UL)       /*!< Min enumerator value of PHYSEL field.                                */
87001   #define USBHSCORE_GUSBCFG_PHYSEL_Max (0x1UL)       /*!< Max enumerator value of PHYSEL field.                                */
87002   #define USBHSCORE_GUSBCFG_PHYSEL_USB20 (0x0UL)     /*!< (unspecified)                                                        */
87003   #define USBHSCORE_GUSBCFG_PHYSEL_USB11 (0x1UL)     /*!< (unspecified)                                                        */
87004 
87005 /* USBTRDTIM @Bits 10..13 : Mode: Device only. USB Turnaround Time (USBTrdTim) */
87006   #define USBHSCORE_GUSBCFG_USBTRDTIM_Pos (10UL)     /*!< Position of USBTRDTIM field.                                         */
87007   #define USBHSCORE_GUSBCFG_USBTRDTIM_Msk (0xFUL << USBHSCORE_GUSBCFG_USBTRDTIM_Pos) /*!< Bit mask of USBTRDTIM field.         */
87008   #define USBHSCORE_GUSBCFG_USBTRDTIM_Min (0x5UL)    /*!< Min enumerator value of USBTRDTIM field.                             */
87009   #define USBHSCORE_GUSBCFG_USBTRDTIM_Max (0x9UL)    /*!< Max enumerator value of USBTRDTIM field.                             */
87010   #define USBHSCORE_GUSBCFG_USBTRDTIM_TURNTIME16BIT (0x5UL) /*!< (unspecified)                                                 */
87011   #define USBHSCORE_GUSBCFG_USBTRDTIM_TURNTIME8BIT (0x9UL) /*!< (unspecified)                                                  */
87012 
87013 /* PHYLPWRCLKSEL @Bit 15 : PHY Low-Power Clock Select (PhyLPwrClkSel) */
87014   #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Pos (15UL) /*!< Position of PHYLPWRCLKSEL field.                                     */
87015   #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Msk (0x1UL << USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Pos) /*!< Bit mask of PHYLPWRCLKSEL
87016                                                                             field.*/
87017   #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Min (0x0UL) /*!< Min enumerator value of PHYLPWRCLKSEL field.                        */
87018   #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_Max (0x1UL) /*!< Max enumerator value of PHYLPWRCLKSEL field.                        */
87019   #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_INTPLLCLK (0x0UL) /*!< (unspecified)                                                 */
87020   #define USBHSCORE_GUSBCFG_PHYLPWRCLKSEL_EXTCLK (0x1UL) /*!< (unspecified)                                                    */
87021 
87022 /* TERMSELDLPULSE @Bit 22 : Mode: Device only. TermSel DLine Pulsing Selection (TermSelDLPulse) */
87023   #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Pos (22UL) /*!< Position of TERMSELDLPULSE field.                                   */
87024   #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Msk (0x1UL << USBHSCORE_GUSBCFG_TERMSELDLPULSE_Pos) /*!< Bit mask of TERMSELDLPULSE
87025                                                                             field.*/
87026   #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Min (0x0UL) /*!< Min enumerator value of TERMSELDLPULSE field.                      */
87027   #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_Max (0x1UL) /*!< Max enumerator value of TERMSELDLPULSE field.                      */
87028   #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_TXVALID (0x0UL) /*!< (unspecified)                                                  */
87029   #define USBHSCORE_GUSBCFG_TERMSELDLPULSE_TERMSEL (0x1UL) /*!< (unspecified)                                                  */
87030 
87031 /* ICUSBCAP @Bit 26 : Mode: Host and Device. IC_USB-Capable (IC_USBCap) */
87032   #define USBHSCORE_GUSBCFG_ICUSBCAP_Pos (26UL)      /*!< Position of ICUSBCAP field.                                          */
87033   #define USBHSCORE_GUSBCFG_ICUSBCAP_Msk (0x1UL << USBHSCORE_GUSBCFG_ICUSBCAP_Pos) /*!< Bit mask of ICUSBCAP field.            */
87034   #define USBHSCORE_GUSBCFG_ICUSBCAP_Min (0x0UL)     /*!< Min enumerator value of ICUSBCAP field.                              */
87035   #define USBHSCORE_GUSBCFG_ICUSBCAP_Max (0x1UL)     /*!< Max enumerator value of ICUSBCAP field.                              */
87036   #define USBHSCORE_GUSBCFG_ICUSBCAP_NOTSELECTED (0x0UL) /*!< (unspecified)                                                    */
87037   #define USBHSCORE_GUSBCFG_ICUSBCAP_SELECTED (0x1UL) /*!< (unspecified)                                                       */
87038 
87039 /* TXENDDELAY @Bit 28 : Mode: Device only. Tx End Delay (TxEndDelay) */
87040   #define USBHSCORE_GUSBCFG_TXENDDELAY_Pos (28UL)    /*!< Position of TXENDDELAY field.                                        */
87041   #define USBHSCORE_GUSBCFG_TXENDDELAY_Msk (0x1UL << USBHSCORE_GUSBCFG_TXENDDELAY_Pos) /*!< Bit mask of TXENDDELAY field.      */
87042   #define USBHSCORE_GUSBCFG_TXENDDELAY_Min (0x0UL)   /*!< Min enumerator value of TXENDDELAY field.                            */
87043   #define USBHSCORE_GUSBCFG_TXENDDELAY_Max (0x1UL)   /*!< Max enumerator value of TXENDDELAY field.                            */
87044   #define USBHSCORE_GUSBCFG_TXENDDELAY_DISABLED (0x0UL) /*!< (unspecified)                                                     */
87045   #define USBHSCORE_GUSBCFG_TXENDDELAY_ENABLED (0x1UL) /*!< (unspecified)                                                      */
87046 
87047 /* FORCEHSTMODE @Bit 29 : Mode: Host and device. Force Host Mode (ForceHstMode) */
87048   #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Pos (29UL)  /*!< Position of FORCEHSTMODE field.                                      */
87049   #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Msk (0x1UL << USBHSCORE_GUSBCFG_FORCEHSTMODE_Pos) /*!< Bit mask of FORCEHSTMODE field.*/
87050   #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Min (0x0UL) /*!< Min enumerator value of FORCEHSTMODE field.                          */
87051   #define USBHSCORE_GUSBCFG_FORCEHSTMODE_Max (0x1UL) /*!< Max enumerator value of FORCEHSTMODE field.                          */
87052   #define USBHSCORE_GUSBCFG_FORCEHSTMODE_DISABLED (0x0UL) /*!< (unspecified)                                                   */
87053   #define USBHSCORE_GUSBCFG_FORCEHSTMODE_ENABLED (0x1UL) /*!< (unspecified)                                                    */
87054 
87055 /* FORCEDEVMODE @Bit 30 : Mode:Host and device. Force Device Mode (ForceDevMode) */
87056   #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Pos (30UL)  /*!< Position of FORCEDEVMODE field.                                      */
87057   #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Msk (0x1UL << USBHSCORE_GUSBCFG_FORCEDEVMODE_Pos) /*!< Bit mask of FORCEDEVMODE field.*/
87058   #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Min (0x0UL) /*!< Min enumerator value of FORCEDEVMODE field.                          */
87059   #define USBHSCORE_GUSBCFG_FORCEDEVMODE_Max (0x1UL) /*!< Max enumerator value of FORCEDEVMODE field.                          */
87060   #define USBHSCORE_GUSBCFG_FORCEDEVMODE_DISABLED (0x0UL) /*!< (unspecified)                                                   */
87061   #define USBHSCORE_GUSBCFG_FORCEDEVMODE_ENABLED (0x1UL) /*!< (unspecified)                                                    */
87062 
87063 /* CORRUPTTXPKT @Bit 31 : Mode: Host and device. Corrupt Tx packet (CorruptTxPkt) */
87064   #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Pos (31UL)  /*!< Position of CORRUPTTXPKT field.                                      */
87065   #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Msk (0x1UL << USBHSCORE_GUSBCFG_CORRUPTTXPKT_Pos) /*!< Bit mask of CORRUPTTXPKT field.*/
87066   #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Min (0x0UL) /*!< Min enumerator value of CORRUPTTXPKT field.                          */
87067   #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Max (0x1UL) /*!< Max enumerator value of CORRUPTTXPKT field.                          */
87068   #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Disabled (0x0UL) /*!< (unspecified)                                                   */
87069   #define USBHSCORE_GUSBCFG_CORRUPTTXPKT_Enabled (0x1UL) /*!< (unspecified)                                                    */
87070 
87071 
87072 /* USBHSCORE_GRSTCTL: Reset Register */
87073   #define USBHSCORE_GRSTCTL_ResetValue (0x80000000UL) /*!< Reset value of GRSTCTL register.                                    */
87074 
87075 /* CSFTRST @Bit 0 : Mode: Host and Device. Core Soft Reset (CSftRst) */
87076   #define USBHSCORE_GRSTCTL_CSFTRST_Pos (0UL)        /*!< Position of CSFTRST field.                                           */
87077   #define USBHSCORE_GRSTCTL_CSFTRST_Msk (0x1UL << USBHSCORE_GRSTCTL_CSFTRST_Pos) /*!< Bit mask of CSFTRST field.               */
87078   #define USBHSCORE_GRSTCTL_CSFTRST_Min (0x0UL)      /*!< Min enumerator value of CSFTRST field.                               */
87079   #define USBHSCORE_GRSTCTL_CSFTRST_Max (0x1UL)      /*!< Max enumerator value of CSFTRST field.                               */
87080   #define USBHSCORE_GRSTCTL_CSFTRST_NOTACTIVE (0x0UL) /*!< (unspecified)                                                       */
87081   #define USBHSCORE_GRSTCTL_CSFTRST_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
87082 
87083 /* PIUFSSFTRST @Bit 1 : Mode: Host and Device. PIU FS Dedicated Controller Soft Reset (PIUFSSftRst) */
87084   #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Pos (1UL)    /*!< Position of PIUFSSFTRST field.                                       */
87085   #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Msk (0x1UL << USBHSCORE_GRSTCTL_PIUFSSFTRST_Pos) /*!< Bit mask of PIUFSSFTRST field.   */
87086   #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Min (0x0UL)  /*!< Min enumerator value of PIUFSSFTRST field.                           */
87087   #define USBHSCORE_GRSTCTL_PIUFSSFTRST_Max (0x1UL)  /*!< Max enumerator value of PIUFSSFTRST field.                           */
87088   #define USBHSCORE_GRSTCTL_PIUFSSFTRST_RESET_INACTIVE (0x0UL) /*!< (unspecified)                                              */
87089   #define USBHSCORE_GRSTCTL_PIUFSSFTRST_RESET_ACTIVE (0x1UL) /*!< (unspecified)                                                */
87090 
87091 /* FRMCNTRRST @Bit 2 : Mode: Host only. Host Frame Counter Reset (FrmCntrRst) */
87092   #define USBHSCORE_GRSTCTL_FRMCNTRRST_Pos (2UL)     /*!< Position of FRMCNTRRST field.                                        */
87093   #define USBHSCORE_GRSTCTL_FRMCNTRRST_Msk (0x1UL << USBHSCORE_GRSTCTL_FRMCNTRRST_Pos) /*!< Bit mask of FRMCNTRRST field.      */
87094   #define USBHSCORE_GRSTCTL_FRMCNTRRST_Min (0x0UL)   /*!< Min enumerator value of FRMCNTRRST field.                            */
87095   #define USBHSCORE_GRSTCTL_FRMCNTRRST_Max (0x1UL)   /*!< Max enumerator value of FRMCNTRRST field.                            */
87096   #define USBHSCORE_GRSTCTL_FRMCNTRRST_NOTACTIVE (0x0UL) /*!< (unspecified)                                                    */
87097   #define USBHSCORE_GRSTCTL_FRMCNTRRST_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
87098 
87099 /* RXFFLSH @Bit 4 : Mode: Host and Device. RxFIFO Flush (RxFFlsh) */
87100   #define USBHSCORE_GRSTCTL_RXFFLSH_Pos (4UL)        /*!< Position of RXFFLSH field.                                           */
87101   #define USBHSCORE_GRSTCTL_RXFFLSH_Msk (0x1UL << USBHSCORE_GRSTCTL_RXFFLSH_Pos) /*!< Bit mask of RXFFLSH field.               */
87102   #define USBHSCORE_GRSTCTL_RXFFLSH_Min (0x0UL)      /*!< Min enumerator value of RXFFLSH field.                               */
87103   #define USBHSCORE_GRSTCTL_RXFFLSH_Max (0x1UL)      /*!< Max enumerator value of RXFFLSH field.                               */
87104   #define USBHSCORE_GRSTCTL_RXFFLSH_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
87105   #define USBHSCORE_GRSTCTL_RXFFLSH_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
87106 
87107 /* TXFFLSH @Bit 5 : Mode: Host and Device. TxFIFO Flush (TxFFlsh) */
87108   #define USBHSCORE_GRSTCTL_TXFFLSH_Pos (5UL)        /*!< Position of TXFFLSH field.                                           */
87109   #define USBHSCORE_GRSTCTL_TXFFLSH_Msk (0x1UL << USBHSCORE_GRSTCTL_TXFFLSH_Pos) /*!< Bit mask of TXFFLSH field.               */
87110   #define USBHSCORE_GRSTCTL_TXFFLSH_Min (0x0UL)      /*!< Min enumerator value of TXFFLSH field.                               */
87111   #define USBHSCORE_GRSTCTL_TXFFLSH_Max (0x1UL)      /*!< Max enumerator value of TXFFLSH field.                               */
87112   #define USBHSCORE_GRSTCTL_TXFFLSH_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
87113   #define USBHSCORE_GRSTCTL_TXFFLSH_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
87114 
87115 /* TXFNUM @Bits 6..10 : Mode: Host and Device. TxFIFO Number (TxFNum) */
87116   #define USBHSCORE_GRSTCTL_TXFNUM_Pos (6UL)         /*!< Position of TXFNUM field.                                            */
87117   #define USBHSCORE_GRSTCTL_TXFNUM_Msk (0x1FUL << USBHSCORE_GRSTCTL_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                 */
87118   #define USBHSCORE_GRSTCTL_TXFNUM_Min (0x0UL)       /*!< Min enumerator value of TXFNUM field.                                */
87119   #define USBHSCORE_GRSTCTL_TXFNUM_Max (0x10UL)      /*!< Max enumerator value of TXFNUM field.                                */
87120   #define USBHSCORE_GRSTCTL_TXFNUM_TXF0 (0x00UL)     /*!< (unspecified)                                                        */
87121   #define USBHSCORE_GRSTCTL_TXFNUM_TXF1 (0x01UL)     /*!< (unspecified)                                                        */
87122   #define USBHSCORE_GRSTCTL_TXFNUM_TXF2 (0x02UL)     /*!< (unspecified)                                                        */
87123   #define USBHSCORE_GRSTCTL_TXFNUM_TXF3 (0x03UL)     /*!< (unspecified)                                                        */
87124   #define USBHSCORE_GRSTCTL_TXFNUM_TXF4 (0x04UL)     /*!< (unspecified)                                                        */
87125   #define USBHSCORE_GRSTCTL_TXFNUM_TXF5 (0x05UL)     /*!< (unspecified)                                                        */
87126   #define USBHSCORE_GRSTCTL_TXFNUM_TXF6 (0x06UL)     /*!< (unspecified)                                                        */
87127   #define USBHSCORE_GRSTCTL_TXFNUM_TXF7 (0x07UL)     /*!< (unspecified)                                                        */
87128   #define USBHSCORE_GRSTCTL_TXFNUM_TXF8 (0x08UL)     /*!< (unspecified)                                                        */
87129   #define USBHSCORE_GRSTCTL_TXFNUM_TXF9 (0x09UL)     /*!< (unspecified)                                                        */
87130   #define USBHSCORE_GRSTCTL_TXFNUM_TXF10 (0x0AUL)    /*!< (unspecified)                                                        */
87131   #define USBHSCORE_GRSTCTL_TXFNUM_TXF11 (0x0BUL)    /*!< (unspecified)                                                        */
87132   #define USBHSCORE_GRSTCTL_TXFNUM_TXF12 (0x0CUL)    /*!< (unspecified)                                                        */
87133   #define USBHSCORE_GRSTCTL_TXFNUM_TXF13 (0x0DUL)    /*!< (unspecified)                                                        */
87134   #define USBHSCORE_GRSTCTL_TXFNUM_TXF14 (0x0EUL)    /*!< (unspecified)                                                        */
87135   #define USBHSCORE_GRSTCTL_TXFNUM_TXF15 (0x0FUL)    /*!< (unspecified)                                                        */
87136   #define USBHSCORE_GRSTCTL_TXFNUM_TXF16 (0x10UL)    /*!< (unspecified)                                                        */
87137 
87138 /* CSFTRSTDONE @Bit 29 : Mode: Host and Device */
87139   #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Pos (29UL)   /*!< Position of CSFTRSTDONE field.                                       */
87140   #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Msk (0x1UL << USBHSCORE_GRSTCTL_CSFTRSTDONE_Pos) /*!< Bit mask of CSFTRSTDONE field.   */
87141   #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Min (0x0UL)  /*!< Min enumerator value of CSFTRSTDONE field.                           */
87142   #define USBHSCORE_GRSTCTL_CSFTRSTDONE_Max (0x1UL)  /*!< Max enumerator value of CSFTRSTDONE field.                           */
87143   #define USBHSCORE_GRSTCTL_CSFTRSTDONE_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
87144   #define USBHSCORE_GRSTCTL_CSFTRSTDONE_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
87145 
87146 /* DMAREQ @Bit 30 : Mode: Host and Device. DMA Request Signal (DMAReq) */
87147   #define USBHSCORE_GRSTCTL_DMAREQ_Pos (30UL)        /*!< Position of DMAREQ field.                                            */
87148   #define USBHSCORE_GRSTCTL_DMAREQ_Msk (0x1UL << USBHSCORE_GRSTCTL_DMAREQ_Pos) /*!< Bit mask of DMAREQ field.                  */
87149   #define USBHSCORE_GRSTCTL_DMAREQ_Min (0x0UL)       /*!< Min enumerator value of DMAREQ field.                                */
87150   #define USBHSCORE_GRSTCTL_DMAREQ_Max (0x1UL)       /*!< Max enumerator value of DMAREQ field.                                */
87151   #define USBHSCORE_GRSTCTL_DMAREQ_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87152   #define USBHSCORE_GRSTCTL_DMAREQ_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87153 
87154 /* AHBIDLE @Bit 31 : Mode: Host and Device. AHB Master Idle (AHBIdle) */
87155   #define USBHSCORE_GRSTCTL_AHBIDLE_Pos (31UL)       /*!< Position of AHBIDLE field.                                           */
87156   #define USBHSCORE_GRSTCTL_AHBIDLE_Msk (0x1UL << USBHSCORE_GRSTCTL_AHBIDLE_Pos) /*!< Bit mask of AHBIDLE field.               */
87157   #define USBHSCORE_GRSTCTL_AHBIDLE_Min (0x0UL)      /*!< Min enumerator value of AHBIDLE field.                               */
87158   #define USBHSCORE_GRSTCTL_AHBIDLE_Max (0x1UL)      /*!< Max enumerator value of AHBIDLE field.                               */
87159   #define USBHSCORE_GRSTCTL_AHBIDLE_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
87160   #define USBHSCORE_GRSTCTL_AHBIDLE_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
87161 
87162 
87163 /* USBHSCORE_GINTSTS: Interrupt Register */
87164   #define USBHSCORE_GINTSTS_ResetValue (0x00000020UL) /*!< Reset value of GINTSTS register.                                    */
87165 
87166 /* CURMOD @Bit 0 : Mode: Host and Device. Current Mode of Operation (CurMod) */
87167   #define USBHSCORE_GINTSTS_CURMOD_Pos (0UL)         /*!< Position of CURMOD field.                                            */
87168   #define USBHSCORE_GINTSTS_CURMOD_Msk (0x1UL << USBHSCORE_GINTSTS_CURMOD_Pos) /*!< Bit mask of CURMOD field.                  */
87169   #define USBHSCORE_GINTSTS_CURMOD_Min (0x0UL)       /*!< Min enumerator value of CURMOD field.                                */
87170   #define USBHSCORE_GINTSTS_CURMOD_Max (0x1UL)       /*!< Max enumerator value of CURMOD field.                                */
87171   #define USBHSCORE_GINTSTS_CURMOD_DEVICE (0x0UL)    /*!< (unspecified)                                                        */
87172   #define USBHSCORE_GINTSTS_CURMOD_HOST (0x1UL)      /*!< (unspecified)                                                        */
87173 
87174 /* MODEMIS @Bit 1 : Mode: Host and Device. Mode Mismatch Interrupt (ModeMis) */
87175   #define USBHSCORE_GINTSTS_MODEMIS_Pos (1UL)        /*!< Position of MODEMIS field.                                           */
87176   #define USBHSCORE_GINTSTS_MODEMIS_Msk (0x1UL << USBHSCORE_GINTSTS_MODEMIS_Pos) /*!< Bit mask of MODEMIS field.               */
87177   #define USBHSCORE_GINTSTS_MODEMIS_Min (0x0UL)      /*!< Min enumerator value of MODEMIS field.                               */
87178   #define USBHSCORE_GINTSTS_MODEMIS_Max (0x1UL)      /*!< Max enumerator value of MODEMIS field.                               */
87179   #define USBHSCORE_GINTSTS_MODEMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
87180   #define USBHSCORE_GINTSTS_MODEMIS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
87181 
87182 /* OTGINT @Bit 2 : Mode: Host and Device. OTG Interrupt (OTGInt) */
87183   #define USBHSCORE_GINTSTS_OTGINT_Pos (2UL)         /*!< Position of OTGINT field.                                            */
87184   #define USBHSCORE_GINTSTS_OTGINT_Msk (0x1UL << USBHSCORE_GINTSTS_OTGINT_Pos) /*!< Bit mask of OTGINT field.                  */
87185   #define USBHSCORE_GINTSTS_OTGINT_Min (0x0UL)       /*!< Min enumerator value of OTGINT field.                                */
87186   #define USBHSCORE_GINTSTS_OTGINT_Max (0x1UL)       /*!< Max enumerator value of OTGINT field.                                */
87187   #define USBHSCORE_GINTSTS_OTGINT_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87188   #define USBHSCORE_GINTSTS_OTGINT_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87189 
87190 /* SOF @Bit 3 : Mode: Host and Device. Start of (micro)Frame (Sof) */
87191   #define USBHSCORE_GINTSTS_SOF_Pos (3UL)            /*!< Position of SOF field.                                               */
87192   #define USBHSCORE_GINTSTS_SOF_Msk (0x1UL << USBHSCORE_GINTSTS_SOF_Pos) /*!< Bit mask of SOF field.                           */
87193   #define USBHSCORE_GINTSTS_SOF_Min (0x0UL)          /*!< Min enumerator value of SOF field.                                   */
87194   #define USBHSCORE_GINTSTS_SOF_Max (0x1UL)          /*!< Max enumerator value of SOF field.                                   */
87195   #define USBHSCORE_GINTSTS_SOF_INTACTIVE (0x0UL)    /*!< (unspecified)                                                        */
87196   #define USBHSCORE_GINTSTS_SOF_ACTIVE (0x1UL)       /*!< (unspecified)                                                        */
87197 
87198 /* RXFLVL @Bit 4 : Mode: Host and Device. RxFIFO Non-Empty (RxFLvl) */
87199   #define USBHSCORE_GINTSTS_RXFLVL_Pos (4UL)         /*!< Position of RXFLVL field.                                            */
87200   #define USBHSCORE_GINTSTS_RXFLVL_Msk (0x1UL << USBHSCORE_GINTSTS_RXFLVL_Pos) /*!< Bit mask of RXFLVL field.                  */
87201   #define USBHSCORE_GINTSTS_RXFLVL_Min (0x0UL)       /*!< Min enumerator value of RXFLVL field.                                */
87202   #define USBHSCORE_GINTSTS_RXFLVL_Max (0x1UL)       /*!< Max enumerator value of RXFLVL field.                                */
87203   #define USBHSCORE_GINTSTS_RXFLVL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87204   #define USBHSCORE_GINTSTS_RXFLVL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87205 
87206 /* NPTXFEMP @Bit 5 : Mode: Host and Device. Non-periodic TxFIFO Empty (NPTxFEmp) */
87207   #define USBHSCORE_GINTSTS_NPTXFEMP_Pos (5UL)       /*!< Position of NPTXFEMP field.                                          */
87208   #define USBHSCORE_GINTSTS_NPTXFEMP_Msk (0x1UL << USBHSCORE_GINTSTS_NPTXFEMP_Pos) /*!< Bit mask of NPTXFEMP field.            */
87209   #define USBHSCORE_GINTSTS_NPTXFEMP_Min (0x0UL)     /*!< Min enumerator value of NPTXFEMP field.                              */
87210   #define USBHSCORE_GINTSTS_NPTXFEMP_Max (0x1UL)     /*!< Max enumerator value of NPTXFEMP field.                              */
87211   #define USBHSCORE_GINTSTS_NPTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
87212   #define USBHSCORE_GINTSTS_NPTXFEMP_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
87213 
87214 /* GINNAKEFF @Bit 6 : Mode: Device only. Global IN Non-periodic NAK Effective (GINNakEff) */
87215   #define USBHSCORE_GINTSTS_GINNAKEFF_Pos (6UL)      /*!< Position of GINNAKEFF field.                                         */
87216   #define USBHSCORE_GINTSTS_GINNAKEFF_Msk (0x1UL << USBHSCORE_GINTSTS_GINNAKEFF_Pos) /*!< Bit mask of GINNAKEFF field.         */
87217   #define USBHSCORE_GINTSTS_GINNAKEFF_Min (0x0UL)    /*!< Min enumerator value of GINNAKEFF field.                             */
87218   #define USBHSCORE_GINTSTS_GINNAKEFF_Max (0x1UL)    /*!< Max enumerator value of GINNAKEFF field.                             */
87219   #define USBHSCORE_GINTSTS_GINNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
87220   #define USBHSCORE_GINTSTS_GINNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
87221 
87222 /* GOUTNAKEFF @Bit 7 : Mode: Device only. Global OUT NAK Effective (GOUTNakEff) */
87223   #define USBHSCORE_GINTSTS_GOUTNAKEFF_Pos (7UL)     /*!< Position of GOUTNAKEFF field.                                        */
87224   #define USBHSCORE_GINTSTS_GOUTNAKEFF_Msk (0x1UL << USBHSCORE_GINTSTS_GOUTNAKEFF_Pos) /*!< Bit mask of GOUTNAKEFF field.      */
87225   #define USBHSCORE_GINTSTS_GOUTNAKEFF_Min (0x0UL)   /*!< Min enumerator value of GOUTNAKEFF field.                            */
87226   #define USBHSCORE_GINTSTS_GOUTNAKEFF_Max (0x1UL)   /*!< Max enumerator value of GOUTNAKEFF field.                            */
87227   #define USBHSCORE_GINTSTS_GOUTNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
87228   #define USBHSCORE_GINTSTS_GOUTNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
87229 
87230 /* ERLYSUSP @Bit 10 : Mode: Device only. Early Suspend (ErlySusp) */
87231   #define USBHSCORE_GINTSTS_ERLYSUSP_Pos (10UL)      /*!< Position of ERLYSUSP field.                                          */
87232   #define USBHSCORE_GINTSTS_ERLYSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_ERLYSUSP_Pos) /*!< Bit mask of ERLYSUSP field.            */
87233   #define USBHSCORE_GINTSTS_ERLYSUSP_Min (0x0UL)     /*!< Min enumerator value of ERLYSUSP field.                              */
87234   #define USBHSCORE_GINTSTS_ERLYSUSP_Max (0x1UL)     /*!< Max enumerator value of ERLYSUSP field.                              */
87235   #define USBHSCORE_GINTSTS_ERLYSUSP_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
87236   #define USBHSCORE_GINTSTS_ERLYSUSP_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
87237 
87238 /* USBSUSP @Bit 11 : Mode: Device only. USB Suspend (USBSusp) */
87239   #define USBHSCORE_GINTSTS_USBSUSP_Pos (11UL)       /*!< Position of USBSUSP field.                                           */
87240   #define USBHSCORE_GINTSTS_USBSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_USBSUSP_Pos) /*!< Bit mask of USBSUSP field.               */
87241   #define USBHSCORE_GINTSTS_USBSUSP_Min (0x0UL)      /*!< Min enumerator value of USBSUSP field.                               */
87242   #define USBHSCORE_GINTSTS_USBSUSP_Max (0x1UL)      /*!< Max enumerator value of USBSUSP field.                               */
87243   #define USBHSCORE_GINTSTS_USBSUSP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
87244   #define USBHSCORE_GINTSTS_USBSUSP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
87245 
87246 /* USBRST @Bit 12 : Mode: Device only. USB Reset (USBRst) */
87247   #define USBHSCORE_GINTSTS_USBRST_Pos (12UL)        /*!< Position of USBRST field.                                            */
87248   #define USBHSCORE_GINTSTS_USBRST_Msk (0x1UL << USBHSCORE_GINTSTS_USBRST_Pos) /*!< Bit mask of USBRST field.                  */
87249   #define USBHSCORE_GINTSTS_USBRST_Min (0x0UL)       /*!< Min enumerator value of USBRST field.                                */
87250   #define USBHSCORE_GINTSTS_USBRST_Max (0x1UL)       /*!< Max enumerator value of USBRST field.                                */
87251   #define USBHSCORE_GINTSTS_USBRST_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87252   #define USBHSCORE_GINTSTS_USBRST_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87253 
87254 /* ENUMDONE @Bit 13 : Mode: Device only. Enumeration Done (EnumDone) */
87255   #define USBHSCORE_GINTSTS_ENUMDONE_Pos (13UL)      /*!< Position of ENUMDONE field.                                          */
87256   #define USBHSCORE_GINTSTS_ENUMDONE_Msk (0x1UL << USBHSCORE_GINTSTS_ENUMDONE_Pos) /*!< Bit mask of ENUMDONE field.            */
87257   #define USBHSCORE_GINTSTS_ENUMDONE_Min (0x0UL)     /*!< Min enumerator value of ENUMDONE field.                              */
87258   #define USBHSCORE_GINTSTS_ENUMDONE_Max (0x1UL)     /*!< Max enumerator value of ENUMDONE field.                              */
87259   #define USBHSCORE_GINTSTS_ENUMDONE_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
87260   #define USBHSCORE_GINTSTS_ENUMDONE_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
87261 
87262 /* ISOOUTDROP @Bit 14 : Mode: Device only. Isochronous OUT Packet Dropped Interrupt (ISOOutDrop) */
87263   #define USBHSCORE_GINTSTS_ISOOUTDROP_Pos (14UL)    /*!< Position of ISOOUTDROP field.                                        */
87264   #define USBHSCORE_GINTSTS_ISOOUTDROP_Msk (0x1UL << USBHSCORE_GINTSTS_ISOOUTDROP_Pos) /*!< Bit mask of ISOOUTDROP field.      */
87265   #define USBHSCORE_GINTSTS_ISOOUTDROP_Min (0x0UL)   /*!< Min enumerator value of ISOOUTDROP field.                            */
87266   #define USBHSCORE_GINTSTS_ISOOUTDROP_Max (0x1UL)   /*!< Max enumerator value of ISOOUTDROP field.                            */
87267   #define USBHSCORE_GINTSTS_ISOOUTDROP_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
87268   #define USBHSCORE_GINTSTS_ISOOUTDROP_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
87269 
87270 /* EOPF @Bit 15 : Mode: Device only. End of Periodic Frame Interrupt (EOPF) */
87271   #define USBHSCORE_GINTSTS_EOPF_Pos (15UL)          /*!< Position of EOPF field.                                              */
87272   #define USBHSCORE_GINTSTS_EOPF_Msk (0x1UL << USBHSCORE_GINTSTS_EOPF_Pos) /*!< Bit mask of EOPF field.                        */
87273   #define USBHSCORE_GINTSTS_EOPF_Min (0x0UL)         /*!< Min enumerator value of EOPF field.                                  */
87274   #define USBHSCORE_GINTSTS_EOPF_Max (0x1UL)         /*!< Max enumerator value of EOPF field.                                  */
87275   #define USBHSCORE_GINTSTS_EOPF_INACTIVE (0x0UL)    /*!< (unspecified)                                                        */
87276   #define USBHSCORE_GINTSTS_EOPF_ACTIVE (0x1UL)      /*!< (unspecified)                                                        */
87277 
87278 /* RSTRDONEINT @Bit 16 : Mode: Device only. Restore Done Interrupt (RstrDoneInt) */
87279   #define USBHSCORE_GINTSTS_RSTRDONEINT_Pos (16UL)   /*!< Position of RSTRDONEINT field.                                       */
87280   #define USBHSCORE_GINTSTS_RSTRDONEINT_Msk (0x1UL << USBHSCORE_GINTSTS_RSTRDONEINT_Pos) /*!< Bit mask of RSTRDONEINT field.   */
87281   #define USBHSCORE_GINTSTS_RSTRDONEINT_Min (0x0UL)  /*!< Min enumerator value of RSTRDONEINT field.                           */
87282   #define USBHSCORE_GINTSTS_RSTRDONEINT_Max (0x1UL)  /*!< Max enumerator value of RSTRDONEINT field.                           */
87283   #define USBHSCORE_GINTSTS_RSTRDONEINT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
87284   #define USBHSCORE_GINTSTS_RSTRDONEINT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
87285 
87286 /* EPMIS @Bit 17 : Mode: Device only. Endpoint Mismatch Interrupt (EPMis) */
87287   #define USBHSCORE_GINTSTS_EPMIS_Pos (17UL)         /*!< Position of EPMIS field.                                             */
87288   #define USBHSCORE_GINTSTS_EPMIS_Msk (0x1UL << USBHSCORE_GINTSTS_EPMIS_Pos) /*!< Bit mask of EPMIS field.                     */
87289   #define USBHSCORE_GINTSTS_EPMIS_Min (0x0UL)        /*!< Min enumerator value of EPMIS field.                                 */
87290   #define USBHSCORE_GINTSTS_EPMIS_Max (0x1UL)        /*!< Max enumerator value of EPMIS field.                                 */
87291   #define USBHSCORE_GINTSTS_EPMIS_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
87292   #define USBHSCORE_GINTSTS_EPMIS_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
87293 
87294 /* IEPINT @Bit 18 : Mode: Device only. IN Endpoints Interrupt (IEPInt) */
87295   #define USBHSCORE_GINTSTS_IEPINT_Pos (18UL)        /*!< Position of IEPINT field.                                            */
87296   #define USBHSCORE_GINTSTS_IEPINT_Msk (0x1UL << USBHSCORE_GINTSTS_IEPINT_Pos) /*!< Bit mask of IEPINT field.                  */
87297   #define USBHSCORE_GINTSTS_IEPINT_Min (0x0UL)       /*!< Min enumerator value of IEPINT field.                                */
87298   #define USBHSCORE_GINTSTS_IEPINT_Max (0x1UL)       /*!< Max enumerator value of IEPINT field.                                */
87299   #define USBHSCORE_GINTSTS_IEPINT_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87300   #define USBHSCORE_GINTSTS_IEPINT_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87301 
87302 /* OEPINT @Bit 19 : Mode: Device only. OUT Endpoints Interrupt (OEPInt) */
87303   #define USBHSCORE_GINTSTS_OEPINT_Pos (19UL)        /*!< Position of OEPINT field.                                            */
87304   #define USBHSCORE_GINTSTS_OEPINT_Msk (0x1UL << USBHSCORE_GINTSTS_OEPINT_Pos) /*!< Bit mask of OEPINT field.                  */
87305   #define USBHSCORE_GINTSTS_OEPINT_Min (0x0UL)       /*!< Min enumerator value of OEPINT field.                                */
87306   #define USBHSCORE_GINTSTS_OEPINT_Max (0x1UL)       /*!< Max enumerator value of OEPINT field.                                */
87307   #define USBHSCORE_GINTSTS_OEPINT_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87308   #define USBHSCORE_GINTSTS_OEPINT_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87309 
87310 /* INCOMPISOIN @Bit 20 : Mode: Device only. Incomplete Isochronous IN Transfer (incompISOIN) */
87311   #define USBHSCORE_GINTSTS_INCOMPISOIN_Pos (20UL)   /*!< Position of INCOMPISOIN field.                                       */
87312   #define USBHSCORE_GINTSTS_INCOMPISOIN_Msk (0x1UL << USBHSCORE_GINTSTS_INCOMPISOIN_Pos) /*!< Bit mask of INCOMPISOIN field.   */
87313   #define USBHSCORE_GINTSTS_INCOMPISOIN_Min (0x0UL)  /*!< Min enumerator value of INCOMPISOIN field.                           */
87314   #define USBHSCORE_GINTSTS_INCOMPISOIN_Max (0x1UL)  /*!< Max enumerator value of INCOMPISOIN field.                           */
87315   #define USBHSCORE_GINTSTS_INCOMPISOIN_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
87316   #define USBHSCORE_GINTSTS_INCOMPISOIN_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
87317 
87318 /* INCOMPLP @Bit 21 : Incomplete Periodic Transfer (incomplP) */
87319   #define USBHSCORE_GINTSTS_INCOMPLP_Pos (21UL)      /*!< Position of INCOMPLP field.                                          */
87320   #define USBHSCORE_GINTSTS_INCOMPLP_Msk (0x1UL << USBHSCORE_GINTSTS_INCOMPLP_Pos) /*!< Bit mask of INCOMPLP field.            */
87321   #define USBHSCORE_GINTSTS_INCOMPLP_Min (0x0UL)     /*!< Min enumerator value of INCOMPLP field.                              */
87322   #define USBHSCORE_GINTSTS_INCOMPLP_Max (0x1UL)     /*!< Max enumerator value of INCOMPLP field.                              */
87323   #define USBHSCORE_GINTSTS_INCOMPLP_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
87324   #define USBHSCORE_GINTSTS_INCOMPLP_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
87325 
87326 /* FETSUSP @Bit 22 : Mode: Device only. Data Fetch Suspended (FetSusp) */
87327   #define USBHSCORE_GINTSTS_FETSUSP_Pos (22UL)       /*!< Position of FETSUSP field.                                           */
87328   #define USBHSCORE_GINTSTS_FETSUSP_Msk (0x1UL << USBHSCORE_GINTSTS_FETSUSP_Pos) /*!< Bit mask of FETSUSP field.               */
87329   #define USBHSCORE_GINTSTS_FETSUSP_Min (0x0UL)      /*!< Min enumerator value of FETSUSP field.                               */
87330   #define USBHSCORE_GINTSTS_FETSUSP_Max (0x1UL)      /*!< Max enumerator value of FETSUSP field.                               */
87331   #define USBHSCORE_GINTSTS_FETSUSP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
87332   #define USBHSCORE_GINTSTS_FETSUSP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
87333 
87334 /* RESETDET @Bit 23 : Mode: Device only. Reset detected Interrupt (ResetDet) */
87335   #define USBHSCORE_GINTSTS_RESETDET_Pos (23UL)      /*!< Position of RESETDET field.                                          */
87336   #define USBHSCORE_GINTSTS_RESETDET_Msk (0x1UL << USBHSCORE_GINTSTS_RESETDET_Pos) /*!< Bit mask of RESETDET field.            */
87337   #define USBHSCORE_GINTSTS_RESETDET_Min (0x0UL)     /*!< Min enumerator value of RESETDET field.                              */
87338   #define USBHSCORE_GINTSTS_RESETDET_Max (0x1UL)     /*!< Max enumerator value of RESETDET field.                              */
87339   #define USBHSCORE_GINTSTS_RESETDET_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
87340   #define USBHSCORE_GINTSTS_RESETDET_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
87341 
87342 /* PRTINT @Bit 24 : Mode: Host only. Host Port Interrupt (PrtInt) */
87343   #define USBHSCORE_GINTSTS_PRTINT_Pos (24UL)        /*!< Position of PRTINT field.                                            */
87344   #define USBHSCORE_GINTSTS_PRTINT_Msk (0x1UL << USBHSCORE_GINTSTS_PRTINT_Pos) /*!< Bit mask of PRTINT field.                  */
87345   #define USBHSCORE_GINTSTS_PRTINT_Min (0x0UL)       /*!< Min enumerator value of PRTINT field.                                */
87346   #define USBHSCORE_GINTSTS_PRTINT_Max (0x1UL)       /*!< Max enumerator value of PRTINT field.                                */
87347   #define USBHSCORE_GINTSTS_PRTINT_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87348   #define USBHSCORE_GINTSTS_PRTINT_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87349 
87350 /* HCHINT @Bit 25 : Mode: Host only. Host Channels Interrupt (HChInt) */
87351   #define USBHSCORE_GINTSTS_HCHINT_Pos (25UL)        /*!< Position of HCHINT field.                                            */
87352   #define USBHSCORE_GINTSTS_HCHINT_Msk (0x1UL << USBHSCORE_GINTSTS_HCHINT_Pos) /*!< Bit mask of HCHINT field.                  */
87353   #define USBHSCORE_GINTSTS_HCHINT_Min (0x0UL)       /*!< Min enumerator value of HCHINT field.                                */
87354   #define USBHSCORE_GINTSTS_HCHINT_Max (0x1UL)       /*!< Max enumerator value of HCHINT field.                                */
87355   #define USBHSCORE_GINTSTS_HCHINT_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87356   #define USBHSCORE_GINTSTS_HCHINT_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87357 
87358 /* LPMINT @Bit 27 : Mode: Host and Device */
87359   #define USBHSCORE_GINTSTS_LPMINT_Pos (27UL)        /*!< Position of LPMINT field.                                            */
87360   #define USBHSCORE_GINTSTS_LPMINT_Msk (0x1UL << USBHSCORE_GINTSTS_LPMINT_Pos) /*!< Bit mask of LPMINT field.                  */
87361   #define USBHSCORE_GINTSTS_LPMINT_Min (0x0UL)       /*!< Min enumerator value of LPMINT field.                                */
87362   #define USBHSCORE_GINTSTS_LPMINT_Max (0x1UL)       /*!< Max enumerator value of LPMINT field.                                */
87363   #define USBHSCORE_GINTSTS_LPMINT_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
87364   #define USBHSCORE_GINTSTS_LPMINT_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
87365 
87366 /* CONIDSTSCHNG @Bit 28 : Mode: Host and Device. Connector ID Status Change (ConIDStsChng) */
87367   #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Pos (28UL)  /*!< Position of CONIDSTSCHNG field.                                      */
87368   #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Msk (0x1UL << USBHSCORE_GINTSTS_CONIDSTSCHNG_Pos) /*!< Bit mask of CONIDSTSCHNG field.*/
87369   #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Min (0x0UL) /*!< Min enumerator value of CONIDSTSCHNG field.                          */
87370   #define USBHSCORE_GINTSTS_CONIDSTSCHNG_Max (0x1UL) /*!< Max enumerator value of CONIDSTSCHNG field.                          */
87371   #define USBHSCORE_GINTSTS_CONIDSTSCHNG_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
87372   #define USBHSCORE_GINTSTS_CONIDSTSCHNG_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
87373 
87374 /* DISCONNINT @Bit 29 : Mode: Host only. Disconnect Detected Interrupt (DisconnInt) */
87375   #define USBHSCORE_GINTSTS_DISCONNINT_Pos (29UL)    /*!< Position of DISCONNINT field.                                        */
87376   #define USBHSCORE_GINTSTS_DISCONNINT_Msk (0x1UL << USBHSCORE_GINTSTS_DISCONNINT_Pos) /*!< Bit mask of DISCONNINT field.      */
87377   #define USBHSCORE_GINTSTS_DISCONNINT_Min (0x0UL)   /*!< Min enumerator value of DISCONNINT field.                            */
87378   #define USBHSCORE_GINTSTS_DISCONNINT_Max (0x1UL)   /*!< Max enumerator value of DISCONNINT field.                            */
87379   #define USBHSCORE_GINTSTS_DISCONNINT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
87380   #define USBHSCORE_GINTSTS_DISCONNINT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
87381 
87382 /* SESSREQINT @Bit 30 : Mode: Host and Device. Session Request/New Session Detected Interrupt (SessReqInt) */
87383   #define USBHSCORE_GINTSTS_SESSREQINT_Pos (30UL)    /*!< Position of SESSREQINT field.                                        */
87384   #define USBHSCORE_GINTSTS_SESSREQINT_Msk (0x1UL << USBHSCORE_GINTSTS_SESSREQINT_Pos) /*!< Bit mask of SESSREQINT field.      */
87385   #define USBHSCORE_GINTSTS_SESSREQINT_Min (0x0UL)   /*!< Min enumerator value of SESSREQINT field.                            */
87386   #define USBHSCORE_GINTSTS_SESSREQINT_Max (0x1UL)   /*!< Max enumerator value of SESSREQINT field.                            */
87387   #define USBHSCORE_GINTSTS_SESSREQINT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
87388   #define USBHSCORE_GINTSTS_SESSREQINT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
87389 
87390 /* WKUPINT @Bit 31 : Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt (WkUpInt) */
87391   #define USBHSCORE_GINTSTS_WKUPINT_Pos (31UL)       /*!< Position of WKUPINT field.                                           */
87392   #define USBHSCORE_GINTSTS_WKUPINT_Msk (0x1UL << USBHSCORE_GINTSTS_WKUPINT_Pos) /*!< Bit mask of WKUPINT field.               */
87393   #define USBHSCORE_GINTSTS_WKUPINT_Min (0x0UL)      /*!< Min enumerator value of WKUPINT field.                               */
87394   #define USBHSCORE_GINTSTS_WKUPINT_Max (0x1UL)      /*!< Max enumerator value of WKUPINT field.                               */
87395   #define USBHSCORE_GINTSTS_WKUPINT_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
87396   #define USBHSCORE_GINTSTS_WKUPINT_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
87397 
87398 
87399 /* USBHSCORE_GINTMSK: Interrupt Mask Register */
87400   #define USBHSCORE_GINTMSK_ResetValue (0x00000000UL) /*!< Reset value of GINTMSK register.                                    */
87401 
87402 /* MODEMISMSK @Bit 1 : Mode: Host and Device */
87403   #define USBHSCORE_GINTMSK_MODEMISMSK_Pos (1UL)     /*!< Position of MODEMISMSK field.                                        */
87404   #define USBHSCORE_GINTMSK_MODEMISMSK_Msk (0x1UL << USBHSCORE_GINTMSK_MODEMISMSK_Pos) /*!< Bit mask of MODEMISMSK field.      */
87405   #define USBHSCORE_GINTMSK_MODEMISMSK_Min (0x0UL)   /*!< Min enumerator value of MODEMISMSK field.                            */
87406   #define USBHSCORE_GINTMSK_MODEMISMSK_Max (0x1UL)   /*!< Max enumerator value of MODEMISMSK field.                            */
87407   #define USBHSCORE_GINTMSK_MODEMISMSK_MASK (0x0UL)  /*!< (unspecified)                                                        */
87408   #define USBHSCORE_GINTMSK_MODEMISMSK_NOMASK (0x1UL) /*!< (unspecified)                                                       */
87409 
87410 /* OTGINTMSK @Bit 2 : Mode: Host and Device */
87411   #define USBHSCORE_GINTMSK_OTGINTMSK_Pos (2UL)      /*!< Position of OTGINTMSK field.                                         */
87412   #define USBHSCORE_GINTMSK_OTGINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_OTGINTMSK_Pos) /*!< Bit mask of OTGINTMSK field.         */
87413   #define USBHSCORE_GINTMSK_OTGINTMSK_Min (0x0UL)    /*!< Min enumerator value of OTGINTMSK field.                             */
87414   #define USBHSCORE_GINTMSK_OTGINTMSK_Max (0x1UL)    /*!< Max enumerator value of OTGINTMSK field.                             */
87415   #define USBHSCORE_GINTMSK_OTGINTMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
87416   #define USBHSCORE_GINTMSK_OTGINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
87417 
87418 /* SOFMSK @Bit 3 : Mode: Host and Device */
87419   #define USBHSCORE_GINTMSK_SOFMSK_Pos (3UL)         /*!< Position of SOFMSK field.                                            */
87420   #define USBHSCORE_GINTMSK_SOFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_SOFMSK_Pos) /*!< Bit mask of SOFMSK field.                  */
87421   #define USBHSCORE_GINTMSK_SOFMSK_Min (0x0UL)       /*!< Min enumerator value of SOFMSK field.                                */
87422   #define USBHSCORE_GINTMSK_SOFMSK_Max (0x1UL)       /*!< Max enumerator value of SOFMSK field.                                */
87423   #define USBHSCORE_GINTMSK_SOFMSK_MASK (0x0UL)      /*!< (unspecified)                                                        */
87424   #define USBHSCORE_GINTMSK_SOFMSK_NOMASK (0x1UL)    /*!< (unspecified)                                                        */
87425 
87426 /* RXFLVLMSK @Bit 4 : Mode: Host and Device */
87427   #define USBHSCORE_GINTMSK_RXFLVLMSK_Pos (4UL)      /*!< Position of RXFLVLMSK field.                                         */
87428   #define USBHSCORE_GINTMSK_RXFLVLMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RXFLVLMSK_Pos) /*!< Bit mask of RXFLVLMSK field.         */
87429   #define USBHSCORE_GINTMSK_RXFLVLMSK_Min (0x0UL)    /*!< Min enumerator value of RXFLVLMSK field.                             */
87430   #define USBHSCORE_GINTMSK_RXFLVLMSK_Max (0x1UL)    /*!< Max enumerator value of RXFLVLMSK field.                             */
87431   #define USBHSCORE_GINTMSK_RXFLVLMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
87432   #define USBHSCORE_GINTMSK_RXFLVLMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
87433 
87434 /* NPTXFEMPMSK @Bit 5 : Mode: Host and Device */
87435   #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Pos (5UL)    /*!< Position of NPTXFEMPMSK field.                                       */
87436   #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_NPTXFEMPMSK_Pos) /*!< Bit mask of NPTXFEMPMSK field.   */
87437   #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Min (0x0UL)  /*!< Min enumerator value of NPTXFEMPMSK field.                           */
87438   #define USBHSCORE_GINTMSK_NPTXFEMPMSK_Max (0x1UL)  /*!< Max enumerator value of NPTXFEMPMSK field.                           */
87439   #define USBHSCORE_GINTMSK_NPTXFEMPMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
87440   #define USBHSCORE_GINTMSK_NPTXFEMPMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
87441 
87442 /* GINNAKEFFMSK @Bit 6 : Mode: Device only, */
87443   #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Pos (6UL)   /*!< Position of GINNAKEFFMSK field.                                      */
87444   #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_GINNAKEFFMSK_Pos) /*!< Bit mask of GINNAKEFFMSK field.*/
87445   #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of GINNAKEFFMSK field.                          */
87446   #define USBHSCORE_GINTMSK_GINNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of GINNAKEFFMSK field.                          */
87447   #define USBHSCORE_GINTMSK_GINNAKEFFMSK_MASK (0x0UL) /*!< (unspecified)                                                       */
87448   #define USBHSCORE_GINTMSK_GINNAKEFFMSK_NOMASK (0x1UL) /*!< (unspecified)                                                     */
87449 
87450 /* GOUTNAKEFFMSK @Bit 7 : Mode: Device only. Global OUT NAK Effective Mask (GOUTNakEffMsk) */
87451   #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Pos (7UL)  /*!< Position of GOUTNAKEFFMSK field.                                     */
87452   #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Pos) /*!< Bit mask of GOUTNAKEFFMSK
87453                                                                             field.*/
87454   #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of GOUTNAKEFFMSK field.                        */
87455   #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of GOUTNAKEFFMSK field.                        */
87456   #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_MASK (0x0UL) /*!< (unspecified)                                                      */
87457   #define USBHSCORE_GINTMSK_GOUTNAKEFFMSK_NOMASK (0x1UL) /*!< (unspecified)                                                    */
87458 
87459 /* ERLYSUSPMSK @Bit 10 : Mode: Device only. Early Suspend Mask (ErlySuspMsk) */
87460   #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Pos (10UL)   /*!< Position of ERLYSUSPMSK field.                                       */
87461   #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ERLYSUSPMSK_Pos) /*!< Bit mask of ERLYSUSPMSK field.   */
87462   #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Min (0x0UL)  /*!< Min enumerator value of ERLYSUSPMSK field.                           */
87463   #define USBHSCORE_GINTMSK_ERLYSUSPMSK_Max (0x1UL)  /*!< Max enumerator value of ERLYSUSPMSK field.                           */
87464   #define USBHSCORE_GINTMSK_ERLYSUSPMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
87465   #define USBHSCORE_GINTMSK_ERLYSUSPMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
87466 
87467 /* USBSUSPMSK @Bit 11 : Mode: Device only. USB Suspend Mask (USBSuspMsk) */
87468   #define USBHSCORE_GINTMSK_USBSUSPMSK_Pos (11UL)    /*!< Position of USBSUSPMSK field.                                        */
87469   #define USBHSCORE_GINTMSK_USBSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_USBSUSPMSK_Pos) /*!< Bit mask of USBSUSPMSK field.      */
87470   #define USBHSCORE_GINTMSK_USBSUSPMSK_Min (0x0UL)   /*!< Min enumerator value of USBSUSPMSK field.                            */
87471   #define USBHSCORE_GINTMSK_USBSUSPMSK_Max (0x1UL)   /*!< Max enumerator value of USBSUSPMSK field.                            */
87472   #define USBHSCORE_GINTMSK_USBSUSPMSK_MASK (0x0UL)  /*!< (unspecified)                                                        */
87473   #define USBHSCORE_GINTMSK_USBSUSPMSK_NOMASK (0x1UL) /*!< (unspecified)                                                       */
87474 
87475 /* USBRSTMSK @Bit 12 : Mode: Device only. USB Reset Mask (USBRstMsk) */
87476   #define USBHSCORE_GINTMSK_USBRSTMSK_Pos (12UL)     /*!< Position of USBRSTMSK field.                                         */
87477   #define USBHSCORE_GINTMSK_USBRSTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_USBRSTMSK_Pos) /*!< Bit mask of USBRSTMSK field.         */
87478   #define USBHSCORE_GINTMSK_USBRSTMSK_Min (0x0UL)    /*!< Min enumerator value of USBRSTMSK field.                             */
87479   #define USBHSCORE_GINTMSK_USBRSTMSK_Max (0x1UL)    /*!< Max enumerator value of USBRSTMSK field.                             */
87480   #define USBHSCORE_GINTMSK_USBRSTMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
87481   #define USBHSCORE_GINTMSK_USBRSTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
87482 
87483 /* ENUMDONEMSK @Bit 13 : Mode: Device only. Enumeration Done Mask (EnumDoneMsk) */
87484   #define USBHSCORE_GINTMSK_ENUMDONEMSK_Pos (13UL)   /*!< Position of ENUMDONEMSK field.                                       */
87485   #define USBHSCORE_GINTMSK_ENUMDONEMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ENUMDONEMSK_Pos) /*!< Bit mask of ENUMDONEMSK field.   */
87486   #define USBHSCORE_GINTMSK_ENUMDONEMSK_Min (0x0UL)  /*!< Min enumerator value of ENUMDONEMSK field.                           */
87487   #define USBHSCORE_GINTMSK_ENUMDONEMSK_Max (0x1UL)  /*!< Max enumerator value of ENUMDONEMSK field.                           */
87488   #define USBHSCORE_GINTMSK_ENUMDONEMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
87489   #define USBHSCORE_GINTMSK_ENUMDONEMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
87490 
87491 /* ISOOUTDROPMSK @Bit 14 : Mode: Device only. Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk) */
87492   #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Pos (14UL) /*!< Position of ISOOUTDROPMSK field.                                     */
87493   #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_ISOOUTDROPMSK_Pos) /*!< Bit mask of ISOOUTDROPMSK
87494                                                                             field.*/
87495   #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Min (0x0UL) /*!< Min enumerator value of ISOOUTDROPMSK field.                        */
87496   #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_Max (0x1UL) /*!< Max enumerator value of ISOOUTDROPMSK field.                        */
87497   #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_MASK (0x0UL) /*!< (unspecified)                                                      */
87498   #define USBHSCORE_GINTMSK_ISOOUTDROPMSK_NOMASK (0x1UL) /*!< (unspecified)                                                    */
87499 
87500 /* EOPFMSK @Bit 15 : Mode: Device only. End of Periodic Frame Interrupt Mask (EOPFMsk) */
87501   #define USBHSCORE_GINTMSK_EOPFMSK_Pos (15UL)       /*!< Position of EOPFMSK field.                                           */
87502   #define USBHSCORE_GINTMSK_EOPFMSK_Msk (0x1UL << USBHSCORE_GINTMSK_EOPFMSK_Pos) /*!< Bit mask of EOPFMSK field.               */
87503   #define USBHSCORE_GINTMSK_EOPFMSK_Min (0x0UL)      /*!< Min enumerator value of EOPFMSK field.                               */
87504   #define USBHSCORE_GINTMSK_EOPFMSK_Max (0x1UL)      /*!< Max enumerator value of EOPFMSK field.                               */
87505   #define USBHSCORE_GINTMSK_EOPFMSK_MASK (0x0UL)     /*!< (unspecified)                                                        */
87506   #define USBHSCORE_GINTMSK_EOPFMSK_NOMASK (0x1UL)   /*!< (unspecified)                                                        */
87507 
87508 /* RSTRDONEINTMSK @Bit 16 : Mode: Host and Device */
87509   #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Pos (16UL) /*!< Position of RSTRDONEINTMSK field.                                   */
87510   #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RSTRDONEINTMSK_Pos) /*!< Bit mask of RSTRDONEINTMSK
87511                                                                             field.*/
87512   #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Min (0x0UL) /*!< Min enumerator value of RSTRDONEINTMSK field.                      */
87513   #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_Max (0x1UL) /*!< Max enumerator value of RSTRDONEINTMSK field.                      */
87514   #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_MASK (0x0UL) /*!< (unspecified)                                                     */
87515   #define USBHSCORE_GINTMSK_RSTRDONEINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                   */
87516 
87517 /* EPMISMSK @Bit 17 : Mode: Device only. Endpoint Mismatch Interrupt Mask (EPMisMsk) */
87518   #define USBHSCORE_GINTMSK_EPMISMSK_Pos (17UL)      /*!< Position of EPMISMSK field.                                          */
87519   #define USBHSCORE_GINTMSK_EPMISMSK_Msk (0x1UL << USBHSCORE_GINTMSK_EPMISMSK_Pos) /*!< Bit mask of EPMISMSK field.            */
87520   #define USBHSCORE_GINTMSK_EPMISMSK_Min (0x0UL)     /*!< Min enumerator value of EPMISMSK field.                              */
87521   #define USBHSCORE_GINTMSK_EPMISMSK_Max (0x1UL)     /*!< Max enumerator value of EPMISMSK field.                              */
87522   #define USBHSCORE_GINTMSK_EPMISMSK_MASK (0x0UL)    /*!< (unspecified)                                                        */
87523   #define USBHSCORE_GINTMSK_EPMISMSK_NOMASK (0x1UL)  /*!< (unspecified)                                                        */
87524 
87525 /* IEPINTMSK @Bit 18 : Mode: Device only. IN Endpoints Interrupt Mask (IEPIntMsk) */
87526   #define USBHSCORE_GINTMSK_IEPINTMSK_Pos (18UL)     /*!< Position of IEPINTMSK field.                                         */
87527   #define USBHSCORE_GINTMSK_IEPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_IEPINTMSK_Pos) /*!< Bit mask of IEPINTMSK field.         */
87528   #define USBHSCORE_GINTMSK_IEPINTMSK_Min (0x0UL)    /*!< Min enumerator value of IEPINTMSK field.                             */
87529   #define USBHSCORE_GINTMSK_IEPINTMSK_Max (0x1UL)    /*!< Max enumerator value of IEPINTMSK field.                             */
87530   #define USBHSCORE_GINTMSK_IEPINTMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
87531   #define USBHSCORE_GINTMSK_IEPINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
87532 
87533 /* OEPINTMSK @Bit 19 : Mode: Device only. OUT Endpoints Interrupt Mask (OEPIntMsk) */
87534   #define USBHSCORE_GINTMSK_OEPINTMSK_Pos (19UL)     /*!< Position of OEPINTMSK field.                                         */
87535   #define USBHSCORE_GINTMSK_OEPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_OEPINTMSK_Pos) /*!< Bit mask of OEPINTMSK field.         */
87536   #define USBHSCORE_GINTMSK_OEPINTMSK_Min (0x0UL)    /*!< Min enumerator value of OEPINTMSK field.                             */
87537   #define USBHSCORE_GINTMSK_OEPINTMSK_Max (0x1UL)    /*!< Max enumerator value of OEPINTMSK field.                             */
87538   #define USBHSCORE_GINTMSK_OEPINTMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
87539   #define USBHSCORE_GINTMSK_OEPINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
87540 
87541 /* INCOMPLPMSK @Bit 21 : Incomplete Periodic Transfer Mask (incomplPMsk) */
87542   #define USBHSCORE_GINTMSK_INCOMPLPMSK_Pos (21UL)   /*!< Position of INCOMPLPMSK field.                                       */
87543   #define USBHSCORE_GINTMSK_INCOMPLPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_INCOMPLPMSK_Pos) /*!< Bit mask of INCOMPLPMSK field.   */
87544   #define USBHSCORE_GINTMSK_INCOMPLPMSK_Min (0x0UL)  /*!< Min enumerator value of INCOMPLPMSK field.                           */
87545   #define USBHSCORE_GINTMSK_INCOMPLPMSK_Max (0x1UL)  /*!< Max enumerator value of INCOMPLPMSK field.                           */
87546   #define USBHSCORE_GINTMSK_INCOMPLPMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
87547   #define USBHSCORE_GINTMSK_INCOMPLPMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
87548 
87549 /* FETSUSPMSK @Bit 22 : Mode: Device only. Data Fetch Suspended Mask (FetSuspMsk) */
87550   #define USBHSCORE_GINTMSK_FETSUSPMSK_Pos (22UL)    /*!< Position of FETSUSPMSK field.                                        */
87551   #define USBHSCORE_GINTMSK_FETSUSPMSK_Msk (0x1UL << USBHSCORE_GINTMSK_FETSUSPMSK_Pos) /*!< Bit mask of FETSUSPMSK field.      */
87552   #define USBHSCORE_GINTMSK_FETSUSPMSK_Min (0x0UL)   /*!< Min enumerator value of FETSUSPMSK field.                            */
87553   #define USBHSCORE_GINTMSK_FETSUSPMSK_Max (0x1UL)   /*!< Max enumerator value of FETSUSPMSK field.                            */
87554   #define USBHSCORE_GINTMSK_FETSUSPMSK_MASK (0x0UL)  /*!< (unspecified)                                                        */
87555   #define USBHSCORE_GINTMSK_FETSUSPMSK_NOMASK (0x1UL) /*!< (unspecified)                                                       */
87556 
87557 /* RESETDETMSK @Bit 23 : Mode: Device only. Reset detected Interrupt Mask (ResetDetMsk) */
87558   #define USBHSCORE_GINTMSK_RESETDETMSK_Pos (23UL)   /*!< Position of RESETDETMSK field.                                       */
87559   #define USBHSCORE_GINTMSK_RESETDETMSK_Msk (0x1UL << USBHSCORE_GINTMSK_RESETDETMSK_Pos) /*!< Bit mask of RESETDETMSK field.   */
87560   #define USBHSCORE_GINTMSK_RESETDETMSK_Min (0x0UL)  /*!< Min enumerator value of RESETDETMSK field.                           */
87561   #define USBHSCORE_GINTMSK_RESETDETMSK_Max (0x1UL)  /*!< Max enumerator value of RESETDETMSK field.                           */
87562   #define USBHSCORE_GINTMSK_RESETDETMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
87563   #define USBHSCORE_GINTMSK_RESETDETMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
87564 
87565 /* PRTINTMSK @Bit 24 : Mode: Host only. Host Port Interrupt Mask (PrtIntMsk) */
87566   #define USBHSCORE_GINTMSK_PRTINTMSK_Pos (24UL)     /*!< Position of PRTINTMSK field.                                         */
87567   #define USBHSCORE_GINTMSK_PRTINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_PRTINTMSK_Pos) /*!< Bit mask of PRTINTMSK field.         */
87568   #define USBHSCORE_GINTMSK_PRTINTMSK_Min (0x0UL)    /*!< Min enumerator value of PRTINTMSK field.                             */
87569   #define USBHSCORE_GINTMSK_PRTINTMSK_Max (0x1UL)    /*!< Max enumerator value of PRTINTMSK field.                             */
87570   #define USBHSCORE_GINTMSK_PRTINTMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
87571   #define USBHSCORE_GINTMSK_PRTINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
87572 
87573 /* HCHINTMSK @Bit 25 : Mode: Host only. Host Channels Interrupt Mask (HChIntMsk) */
87574   #define USBHSCORE_GINTMSK_HCHINTMSK_Pos (25UL)     /*!< Position of HCHINTMSK field.                                         */
87575   #define USBHSCORE_GINTMSK_HCHINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_HCHINTMSK_Pos) /*!< Bit mask of HCHINTMSK field.         */
87576   #define USBHSCORE_GINTMSK_HCHINTMSK_Min (0x0UL)    /*!< Min enumerator value of HCHINTMSK field.                             */
87577   #define USBHSCORE_GINTMSK_HCHINTMSK_Max (0x1UL)    /*!< Max enumerator value of HCHINTMSK field.                             */
87578   #define USBHSCORE_GINTMSK_HCHINTMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
87579   #define USBHSCORE_GINTMSK_HCHINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
87580 
87581 /* LPMINTMSK @Bit 27 : Mode: Host and Device. LPM Transaction Received Interrupt (LPM_Int) */
87582   #define USBHSCORE_GINTMSK_LPMINTMSK_Pos (27UL)     /*!< Position of LPMINTMSK field.                                         */
87583   #define USBHSCORE_GINTMSK_LPMINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_LPMINTMSK_Pos) /*!< Bit mask of LPMINTMSK field.         */
87584   #define USBHSCORE_GINTMSK_LPMINTMSK_Min (0x0UL)    /*!< Min enumerator value of LPMINTMSK field.                             */
87585   #define USBHSCORE_GINTMSK_LPMINTMSK_Max (0x1UL)    /*!< Max enumerator value of LPMINTMSK field.                             */
87586   #define USBHSCORE_GINTMSK_LPMINTMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
87587   #define USBHSCORE_GINTMSK_LPMINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
87588 
87589 /* CONIDSTSCHNGMSK @Bit 28 : Mode: Host and Device */
87590   #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Pos (28UL) /*!< Position of CONIDSTSCHNGMSK field.                                 */
87591   #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Msk (0x1UL << USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Pos) /*!< Bit mask of
87592                                                                             CONIDSTSCHNGMSK field.*/
87593   #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Min (0x0UL) /*!< Min enumerator value of CONIDSTSCHNGMSK field.                    */
87594   #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_Max (0x1UL) /*!< Max enumerator value of CONIDSTSCHNGMSK field.                    */
87595   #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_MASK (0x0UL) /*!< (unspecified)                                                    */
87596   #define USBHSCORE_GINTMSK_CONIDSTSCHNGMSK_NOMASK (0x1UL) /*!< (unspecified)                                                  */
87597 
87598 /* DISCONNINTMSK @Bit 29 : Mode: Host and Device */
87599   #define USBHSCORE_GINTMSK_DISCONNINTMSK_Pos (29UL) /*!< Position of DISCONNINTMSK field.                                     */
87600   #define USBHSCORE_GINTMSK_DISCONNINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_DISCONNINTMSK_Pos) /*!< Bit mask of DISCONNINTMSK
87601                                                                             field.*/
87602   #define USBHSCORE_GINTMSK_DISCONNINTMSK_Min (0x0UL) /*!< Min enumerator value of DISCONNINTMSK field.                        */
87603   #define USBHSCORE_GINTMSK_DISCONNINTMSK_Max (0x1UL) /*!< Max enumerator value of DISCONNINTMSK field.                        */
87604   #define USBHSCORE_GINTMSK_DISCONNINTMSK_MASK (0x0UL) /*!< (unspecified)                                                      */
87605   #define USBHSCORE_GINTMSK_DISCONNINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                    */
87606 
87607 /* SESSREQINTMSK @Bit 30 : Mode: Host and Device */
87608   #define USBHSCORE_GINTMSK_SESSREQINTMSK_Pos (30UL) /*!< Position of SESSREQINTMSK field.                                     */
87609   #define USBHSCORE_GINTMSK_SESSREQINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_SESSREQINTMSK_Pos) /*!< Bit mask of SESSREQINTMSK
87610                                                                             field.*/
87611   #define USBHSCORE_GINTMSK_SESSREQINTMSK_Min (0x0UL) /*!< Min enumerator value of SESSREQINTMSK field.                        */
87612   #define USBHSCORE_GINTMSK_SESSREQINTMSK_Max (0x1UL) /*!< Max enumerator value of SESSREQINTMSK field.                        */
87613   #define USBHSCORE_GINTMSK_SESSREQINTMSK_MASK (0x0UL) /*!< (unspecified)                                                      */
87614   #define USBHSCORE_GINTMSK_SESSREQINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                    */
87615 
87616 /* WKUPINTMSK @Bit 31 : Mode: Host and Device. Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk) */
87617   #define USBHSCORE_GINTMSK_WKUPINTMSK_Pos (31UL)    /*!< Position of WKUPINTMSK field.                                        */
87618   #define USBHSCORE_GINTMSK_WKUPINTMSK_Msk (0x1UL << USBHSCORE_GINTMSK_WKUPINTMSK_Pos) /*!< Bit mask of WKUPINTMSK field.      */
87619   #define USBHSCORE_GINTMSK_WKUPINTMSK_Min (0x0UL)   /*!< Min enumerator value of WKUPINTMSK field.                            */
87620   #define USBHSCORE_GINTMSK_WKUPINTMSK_Max (0x1UL)   /*!< Max enumerator value of WKUPINTMSK field.                            */
87621   #define USBHSCORE_GINTMSK_WKUPINTMSK_MASK (0x0UL)  /*!< (unspecified)                                                        */
87622   #define USBHSCORE_GINTMSK_WKUPINTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                       */
87623 
87624 
87625 /* USBHSCORE_GRXSTSR: Receive Status Debug Read Register */
87626   #define USBHSCORE_GRXSTSR_ResetValue (0x00000000UL) /*!< Reset value of GRXSTSR register.                                    */
87627 
87628 /* CHNUM @Bits 0..3 : Channel Number (ChNum) */
87629   #define USBHSCORE_GRXSTSR_CHNUM_Pos (0UL)          /*!< Position of CHNUM field.                                             */
87630   #define USBHSCORE_GRXSTSR_CHNUM_Msk (0xFUL << USBHSCORE_GRXSTSR_CHNUM_Pos) /*!< Bit mask of CHNUM field.                     */
87631   #define USBHSCORE_GRXSTSR_CHNUM_Min (0x0UL)        /*!< Min enumerator value of CHNUM field.                                 */
87632   #define USBHSCORE_GRXSTSR_CHNUM_Max (0xFUL)        /*!< Max enumerator value of CHNUM field.                                 */
87633   #define USBHSCORE_GRXSTSR_CHNUM_CHEP0 (0x0UL)      /*!< (unspecified)                                                        */
87634   #define USBHSCORE_GRXSTSR_CHNUM_CHEP1 (0x1UL)      /*!< (unspecified)                                                        */
87635   #define USBHSCORE_GRXSTSR_CHNUM_CHEP2 (0x2UL)      /*!< (unspecified)                                                        */
87636   #define USBHSCORE_GRXSTSR_CHNUM_CHEP3 (0x3UL)      /*!< (unspecified)                                                        */
87637   #define USBHSCORE_GRXSTSR_CHNUM_CHEP4 (0x4UL)      /*!< (unspecified)                                                        */
87638   #define USBHSCORE_GRXSTSR_CHNUM_CHEP5 (0x5UL)      /*!< (unspecified)                                                        */
87639   #define USBHSCORE_GRXSTSR_CHNUM_CHEP6 (0x6UL)      /*!< (unspecified)                                                        */
87640   #define USBHSCORE_GRXSTSR_CHNUM_CHEP7 (0x7UL)      /*!< (unspecified)                                                        */
87641   #define USBHSCORE_GRXSTSR_CHNUM_CHEP8 (0x8UL)      /*!< (unspecified)                                                        */
87642   #define USBHSCORE_GRXSTSR_CHNUM_CHEP9 (0x9UL)      /*!< (unspecified)                                                        */
87643   #define USBHSCORE_GRXSTSR_CHNUM_CHEP10 (0xAUL)     /*!< (unspecified)                                                        */
87644   #define USBHSCORE_GRXSTSR_CHNUM_CHEP11 (0xBUL)     /*!< (unspecified)                                                        */
87645   #define USBHSCORE_GRXSTSR_CHNUM_CHEP12 (0xCUL)     /*!< (unspecified)                                                        */
87646   #define USBHSCORE_GRXSTSR_CHNUM_CHEP13 (0xDUL)     /*!< (unspecified)                                                        */
87647   #define USBHSCORE_GRXSTSR_CHNUM_CHEP14 (0xEUL)     /*!< (unspecified)                                                        */
87648   #define USBHSCORE_GRXSTSR_CHNUM_CHEP15 (0xFUL)     /*!< (unspecified)                                                        */
87649 
87650 /* BCNT @Bits 4..14 : Byte Count (BCnt) */
87651   #define USBHSCORE_GRXSTSR_BCNT_Pos (4UL)           /*!< Position of BCNT field.                                              */
87652   #define USBHSCORE_GRXSTSR_BCNT_Msk (0x7FFUL << USBHSCORE_GRXSTSR_BCNT_Pos) /*!< Bit mask of BCNT field.                      */
87653 
87654 /* DPID @Bits 15..16 : Data PID (DPID) */
87655   #define USBHSCORE_GRXSTSR_DPID_Pos (15UL)          /*!< Position of DPID field.                                              */
87656   #define USBHSCORE_GRXSTSR_DPID_Msk (0x3UL << USBHSCORE_GRXSTSR_DPID_Pos) /*!< Bit mask of DPID field.                        */
87657   #define USBHSCORE_GRXSTSR_DPID_Min (0x0UL)         /*!< Min enumerator value of DPID field.                                  */
87658   #define USBHSCORE_GRXSTSR_DPID_Max (0x3UL)         /*!< Max enumerator value of DPID field.                                  */
87659   #define USBHSCORE_GRXSTSR_DPID_DATA0 (0x0UL)       /*!< (unspecified)                                                        */
87660   #define USBHSCORE_GRXSTSR_DPID_DATA2 (0x1UL)       /*!< (unspecified)                                                        */
87661   #define USBHSCORE_GRXSTSR_DPID_DATA1 (0x2UL)       /*!< (unspecified)                                                        */
87662   #define USBHSCORE_GRXSTSR_DPID_MDATA (0x3UL)       /*!< (unspecified)                                                        */
87663 
87664 /* PKTSTS @Bits 17..20 : Packet Status (PktSts) indicates the status of the received packet. */
87665   #define USBHSCORE_GRXSTSR_PKTSTS_Pos (17UL)        /*!< Position of PKTSTS field.                                            */
87666   #define USBHSCORE_GRXSTSR_PKTSTS_Msk (0xFUL << USBHSCORE_GRXSTSR_PKTSTS_Pos) /*!< Bit mask of PKTSTS field.                  */
87667   #define USBHSCORE_GRXSTSR_PKTSTS_Min (0x1UL)       /*!< Min enumerator value of PKTSTS field.                                */
87668   #define USBHSCORE_GRXSTSR_PKTSTS_Max (0x7UL)       /*!< Max enumerator value of PKTSTS field.                                */
87669   #define USBHSCORE_GRXSTSR_PKTSTS_OUTNAK (0x1UL)    /*!< (unspecified)                                                        */
87670   #define USBHSCORE_GRXSTSR_PKTSTS_INOUTDPRX (0x2UL) /*!< (unspecified)                                                        */
87671   #define USBHSCORE_GRXSTSR_PKTSTS_INOUTTRCOM (0x3UL) /*!< (unspecified)                                                       */
87672   #define USBHSCORE_GRXSTSR_PKTSTS_DSETUPCOM (0x4UL) /*!< (unspecified)                                                        */
87673   #define USBHSCORE_GRXSTSR_PKTSTS_DTTOG (0x5UL)     /*!< (unspecified)                                                        */
87674   #define USBHSCORE_GRXSTSR_PKTSTS_DSETUPRX (0x6UL)  /*!< (unspecified)                                                        */
87675   #define USBHSCORE_GRXSTSR_PKTSTS_CHHALT (0x7UL)    /*!< (unspecified)                                                        */
87676 
87677 /* FN @Bits 21..24 : Mode: Device only. Frame Number (FN) */
87678   #define USBHSCORE_GRXSTSR_FN_Pos (21UL)            /*!< Position of FN field.                                                */
87679   #define USBHSCORE_GRXSTSR_FN_Msk (0xFUL << USBHSCORE_GRXSTSR_FN_Pos) /*!< Bit mask of FN field.                              */
87680 
87681 
87682 /* USBHSCORE_GRXSTSP: Receive Status Read/Pop Register */
87683   #define USBHSCORE_GRXSTSP_ResetValue (0x00000000UL) /*!< Reset value of GRXSTSP register.                                    */
87684 
87685 /* CHNUM @Bits 0..3 : Channel Number (ChNum) */
87686   #define USBHSCORE_GRXSTSP_CHNUM_Pos (0UL)          /*!< Position of CHNUM field.                                             */
87687   #define USBHSCORE_GRXSTSP_CHNUM_Msk (0xFUL << USBHSCORE_GRXSTSP_CHNUM_Pos) /*!< Bit mask of CHNUM field.                     */
87688   #define USBHSCORE_GRXSTSP_CHNUM_Min (0x0UL)        /*!< Min enumerator value of CHNUM field.                                 */
87689   #define USBHSCORE_GRXSTSP_CHNUM_Max (0xFUL)        /*!< Max enumerator value of CHNUM field.                                 */
87690   #define USBHSCORE_GRXSTSP_CHNUM_CHEP0 (0x0UL)      /*!< (unspecified)                                                        */
87691   #define USBHSCORE_GRXSTSP_CHNUM_CHEP1 (0x1UL)      /*!< (unspecified)                                                        */
87692   #define USBHSCORE_GRXSTSP_CHNUM_CHEP2 (0x2UL)      /*!< (unspecified)                                                        */
87693   #define USBHSCORE_GRXSTSP_CHNUM_CHEP3 (0x3UL)      /*!< (unspecified)                                                        */
87694   #define USBHSCORE_GRXSTSP_CHNUM_CHEP4 (0x4UL)      /*!< (unspecified)                                                        */
87695   #define USBHSCORE_GRXSTSP_CHNUM_CHEP5 (0x5UL)      /*!< (unspecified)                                                        */
87696   #define USBHSCORE_GRXSTSP_CHNUM_CHEP6 (0x6UL)      /*!< (unspecified)                                                        */
87697   #define USBHSCORE_GRXSTSP_CHNUM_CHEP7 (0x7UL)      /*!< (unspecified)                                                        */
87698   #define USBHSCORE_GRXSTSP_CHNUM_CHEP8 (0x8UL)      /*!< (unspecified)                                                        */
87699   #define USBHSCORE_GRXSTSP_CHNUM_CHEP9 (0x9UL)      /*!< (unspecified)                                                        */
87700   #define USBHSCORE_GRXSTSP_CHNUM_CHEP10 (0xAUL)     /*!< (unspecified)                                                        */
87701   #define USBHSCORE_GRXSTSP_CHNUM_CHEP11 (0xBUL)     /*!< (unspecified)                                                        */
87702   #define USBHSCORE_GRXSTSP_CHNUM_CHEP12 (0xCUL)     /*!< (unspecified)                                                        */
87703   #define USBHSCORE_GRXSTSP_CHNUM_CHEP13 (0xDUL)     /*!< (unspecified)                                                        */
87704   #define USBHSCORE_GRXSTSP_CHNUM_CHEP14 (0xEUL)     /*!< (unspecified)                                                        */
87705   #define USBHSCORE_GRXSTSP_CHNUM_CHEP15 (0xFUL)     /*!< (unspecified)                                                        */
87706 
87707 /* BCNT @Bits 4..14 : Byte Count (BCnt) */
87708   #define USBHSCORE_GRXSTSP_BCNT_Pos (4UL)           /*!< Position of BCNT field.                                              */
87709   #define USBHSCORE_GRXSTSP_BCNT_Msk (0x7FFUL << USBHSCORE_GRXSTSP_BCNT_Pos) /*!< Bit mask of BCNT field.                      */
87710 
87711 /* DPID @Bits 15..16 : Data PID (DPID) */
87712   #define USBHSCORE_GRXSTSP_DPID_Pos (15UL)          /*!< Position of DPID field.                                              */
87713   #define USBHSCORE_GRXSTSP_DPID_Msk (0x3UL << USBHSCORE_GRXSTSP_DPID_Pos) /*!< Bit mask of DPID field.                        */
87714   #define USBHSCORE_GRXSTSP_DPID_Min (0x0UL)         /*!< Min enumerator value of DPID field.                                  */
87715   #define USBHSCORE_GRXSTSP_DPID_Max (0x3UL)         /*!< Max enumerator value of DPID field.                                  */
87716   #define USBHSCORE_GRXSTSP_DPID_DATA0 (0x0UL)       /*!< (unspecified)                                                        */
87717   #define USBHSCORE_GRXSTSP_DPID_DATA2 (0x1UL)       /*!< (unspecified)                                                        */
87718   #define USBHSCORE_GRXSTSP_DPID_DATA1 (0x2UL)       /*!< (unspecified)                                                        */
87719   #define USBHSCORE_GRXSTSP_DPID_MDATA (0x3UL)       /*!< (unspecified)                                                        */
87720 
87721 /* PKTSTS @Bits 17..20 : Packet Status (PktSts) indicates the status of the received packet. */
87722   #define USBHSCORE_GRXSTSP_PKTSTS_Pos (17UL)        /*!< Position of PKTSTS field.                                            */
87723   #define USBHSCORE_GRXSTSP_PKTSTS_Msk (0xFUL << USBHSCORE_GRXSTSP_PKTSTS_Pos) /*!< Bit mask of PKTSTS field.                  */
87724   #define USBHSCORE_GRXSTSP_PKTSTS_Min (0x1UL)       /*!< Min enumerator value of PKTSTS field.                                */
87725   #define USBHSCORE_GRXSTSP_PKTSTS_Max (0x5UL)       /*!< Max enumerator value of PKTSTS field.                                */
87726   #define USBHSCORE_GRXSTSP_PKTSTS_OUTNAK (0x1UL)    /*!< (unspecified)                                                        */
87727   #define USBHSCORE_GRXSTSP_PKTSTS_INOUTDPRX (0x2UL) /*!< (unspecified)                                                        */
87728   #define USBHSCORE_GRXSTSP_PKTSTS_INOUTTRCOM (0x3UL) /*!< (unspecified)                                                       */
87729   #define USBHSCORE_GRXSTSP_PKTSTS_DSETUPCOM (0x4UL) /*!< (unspecified)                                                        */
87730   #define USBHSCORE_GRXSTSP_PKTSTS_DTTOG (0x5UL)     /*!< (unspecified)                                                        */
87731 
87732 /* FN @Bits 21..24 : Mode: Device only. Frame Number (FN) */
87733   #define USBHSCORE_GRXSTSP_FN_Pos (21UL)            /*!< Position of FN field.                                                */
87734   #define USBHSCORE_GRXSTSP_FN_Msk (0xFUL << USBHSCORE_GRXSTSP_FN_Pos) /*!< Bit mask of FN field.                              */
87735 
87736 
87737 /* USBHSCORE_GRXFSIZ: Receive FIFO Size Register */
87738   #define USBHSCORE_GRXFSIZ_ResetValue (0x00000224UL) /*!< Reset value of GRXFSIZ register.                                    */
87739 
87740 /* RXFDEP @Bits 0..9 : Mode: Host and Device. RxFIFO Depth (RxFDep) */
87741   #define USBHSCORE_GRXFSIZ_RXFDEP_Pos (0UL)         /*!< Position of RXFDEP field.                                            */
87742   #define USBHSCORE_GRXFSIZ_RXFDEP_Msk (0x3FFUL << USBHSCORE_GRXFSIZ_RXFDEP_Pos) /*!< Bit mask of RXFDEP field.                */
87743 
87744 
87745 /* USBHSCORE_GNPTXFSIZ: Non-periodic Transmit FIFO Size Register */
87746   #define USBHSCORE_GNPTXFSIZ_ResetValue (0x02000224UL) /*!< Reset value of GNPTXFSIZ register.                                */
87747 
87748 /* NPTXFSTADDR @Bits 0..9 : Non-periodic Transmit RAM Start Address (NPTxFStAddr) */
87749   #define USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Pos (0UL)  /*!< Position of NPTXFSTADDR field.                                       */
87750   #define USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Msk (0x3FFUL << USBHSCORE_GNPTXFSIZ_NPTXFSTADDR_Pos) /*!< Bit mask of NPTXFSTADDR
87751                                                                             field.*/
87752 
87753 /* NPTXFDEP @Bits 16..25 : Mode: Host only. Non-periodic TxFIFO Depth (NPTxFDep) */
87754   #define USBHSCORE_GNPTXFSIZ_NPTXFDEP_Pos (16UL)    /*!< Position of NPTXFDEP field.                                          */
87755   #define USBHSCORE_GNPTXFSIZ_NPTXFDEP_Msk (0x3FFUL << USBHSCORE_GNPTXFSIZ_NPTXFDEP_Pos) /*!< Bit mask of NPTXFDEP field.      */
87756 
87757 
87758 /* USBHSCORE_GNPTXSTS: Non-periodic Transmit FIFO/Queue Status Register */
87759   #define USBHSCORE_GNPTXSTS_ResetValue (0x00080200UL) /*!< Reset value of GNPTXSTS register.                                  */
87760 
87761 /* NPTXFSPCAVAIL @Bits 0..15 : Non-periodic TxFIFO Space Avail (NPTxFSpcAvail) */
87762   #define USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Pos (0UL) /*!< Position of NPTXFSPCAVAIL field.                                     */
87763   #define USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_GNPTXSTS_NPTXFSPCAVAIL_Pos) /*!< Bit mask of NPTXFSPCAVAIL
87764                                                                             field.*/
87765 
87766 /* NPTXQSPCAVAIL @Bits 16..23 : Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail) */
87767   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Pos (16UL) /*!< Position of NPTXQSPCAVAIL field.                                    */
87768   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Msk (0xFFUL << USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Pos) /*!< Bit mask of NPTXQSPCAVAIL
87769                                                                             field.*/
87770   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Min (0x0UL) /*!< Min enumerator value of NPTXQSPCAVAIL field.                       */
87771   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_Max (0x8UL) /*!< Max enumerator value of NPTXQSPCAVAIL field.                       */
87772   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_FULL (0x00UL) /*!< (unspecified)                                                    */
87773   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE1 (0x01UL) /*!< (unspecified)                                                    */
87774   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE2 (0x02UL) /*!< (unspecified)                                                    */
87775   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE3 (0x03UL) /*!< (unspecified)                                                    */
87776   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE4 (0x04UL) /*!< (unspecified)                                                    */
87777   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE5 (0x05UL) /*!< (unspecified)                                                    */
87778   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE6 (0x06UL) /*!< (unspecified)                                                    */
87779   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE7 (0x07UL) /*!< (unspecified)                                                    */
87780   #define USBHSCORE_GNPTXSTS_NPTXQSPCAVAIL_QUE8 (0x08UL) /*!< (unspecified)                                                    */
87781 
87782 /* NPTXQTOP @Bits 24..30 : Top of the Non-periodic Transmit Request Queue (NPTxQTop) */
87783   #define USBHSCORE_GNPTXSTS_NPTXQTOP_Pos (24UL)     /*!< Position of NPTXQTOP field.                                          */
87784   #define USBHSCORE_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USBHSCORE_GNPTXSTS_NPTXQTOP_Pos) /*!< Bit mask of NPTXQTOP field.         */
87785   #define USBHSCORE_GNPTXSTS_NPTXQTOP_Min (0x0UL)    /*!< Min enumerator value of NPTXQTOP field.                              */
87786   #define USBHSCORE_GNPTXSTS_NPTXQTOP_Max (0x3UL)    /*!< Max enumerator value of NPTXQTOP field.                              */
87787   #define USBHSCORE_GNPTXSTS_NPTXQTOP_INOUTTK (0x00UL) /*!< (unspecified)                                                      */
87788   #define USBHSCORE_GNPTXSTS_NPTXQTOP_ZEROTX (0x01UL) /*!< (unspecified)                                                       */
87789   #define USBHSCORE_GNPTXSTS_NPTXQTOP_PINGCSPLIT (0x02UL) /*!< (unspecified)                                                   */
87790   #define USBHSCORE_GNPTXSTS_NPTXQTOP_CHNHALT (0x03UL) /*!< (unspecified)                                                      */
87791 
87792 
87793 /* USBHSCORE_GGPIO: General Purpose Input/Output Register */
87794   #define USBHSCORE_GGPIO_ResetValue (0x00000000UL)  /*!< Reset value of GGPIO register.                                       */
87795 
87796 /* GPI @Bits 0..15 : General Purpose Input (GPI) */
87797   #define USBHSCORE_GGPIO_GPI_Pos (0UL)              /*!< Position of GPI field.                                               */
87798   #define USBHSCORE_GGPIO_GPI_Msk (0xFFFFUL << USBHSCORE_GGPIO_GPI_Pos) /*!< Bit mask of GPI field.                            */
87799 
87800 /* GPO @Bits 16..31 : General Purpose Output (GPO) */
87801   #define USBHSCORE_GGPIO_GPO_Pos (16UL)             /*!< Position of GPO field.                                               */
87802   #define USBHSCORE_GGPIO_GPO_Msk (0xFFFFUL << USBHSCORE_GGPIO_GPO_Pos) /*!< Bit mask of GPO field.                            */
87803 
87804 
87805 /* USBHSCORE_GUID: User ID Register */
87806   #define USBHSCORE_GUID_ResetValue (0x12345678UL)   /*!< Reset value of GUID register.                                        */
87807 
87808 /* GUID @Bits 0..31 : User ID (UserID) */
87809   #define USBHSCORE_GUID_GUID_Pos (0UL)              /*!< Position of GUID field.                                              */
87810   #define USBHSCORE_GUID_GUID_Msk (0xFFFFFFFFUL << USBHSCORE_GUID_GUID_Pos) /*!< Bit mask of GUID field.                       */
87811 
87812 
87813 /* USBHSCORE_GSNPSID: Synopsys ID Register */
87814   #define USBHSCORE_GSNPSID_ResetValue (0x4F54400AUL) /*!< Reset value of GSNPSID register.                                    */
87815 
87816 /* SYNOPSYSID @Bits 0..31 : Release number of the controller being used currently. */
87817   #define USBHSCORE_GSNPSID_SYNOPSYSID_Pos (0UL)     /*!< Position of SYNOPSYSID field.                                        */
87818   #define USBHSCORE_GSNPSID_SYNOPSYSID_Msk (0xFFFFFFFFUL << USBHSCORE_GSNPSID_SYNOPSYSID_Pos) /*!< Bit mask of SYNOPSYSID
87819                                                                             field.*/
87820 
87821 
87822 /* USBHSCORE_GHWCFG1: User Hardware Configuration 1 Register */
87823   #define USBHSCORE_GHWCFG1_ResetValue (0xAA555000UL) /*!< Reset value of GHWCFG1 register.                                    */
87824 
87825 /* EPDIR @Bits 0..31 : This 32-bit field uses two bits per */
87826   #define USBHSCORE_GHWCFG1_EPDIR_Pos (0UL)          /*!< Position of EPDIR field.                                             */
87827   #define USBHSCORE_GHWCFG1_EPDIR_Msk (0xFFFFFFFFUL << USBHSCORE_GHWCFG1_EPDIR_Pos) /*!< Bit mask of EPDIR field.              */
87828 
87829 
87830 /* USBHSCORE_GHWCFG2: User Hardware Configuration 2 Register */
87831   #define USBHSCORE_GHWCFG2_ResetValue (0x228BFC72UL) /*!< Reset value of GHWCFG2 register.                                    */
87832 
87833 /* OTGMODE @Bits 0..2 : Mode of Operation (OtgMode). - 3b000: */
87834   #define USBHSCORE_GHWCFG2_OTGMODE_Pos (0UL)        /*!< Position of OTGMODE field.                                           */
87835   #define USBHSCORE_GHWCFG2_OTGMODE_Msk (0x7UL << USBHSCORE_GHWCFG2_OTGMODE_Pos) /*!< Bit mask of OTGMODE field.               */
87836   #define USBHSCORE_GHWCFG2_OTGMODE_Min (0x0UL)      /*!< Min enumerator value of OTGMODE field.                               */
87837   #define USBHSCORE_GHWCFG2_OTGMODE_Max (0x6UL)      /*!< Max enumerator value of OTGMODE field.                               */
87838   #define USBHSCORE_GHWCFG2_OTGMODE_HNPSRP (0x0UL)   /*!< (unspecified)                                                        */
87839   #define USBHSCORE_GHWCFG2_OTGMODE_SRPOTG (0x1UL)   /*!< (unspecified)                                                        */
87840   #define USBHSCORE_GHWCFG2_OTGMODE_NHNPNSRP (0x2UL) /*!< (unspecified)                                                        */
87841   #define USBHSCORE_GHWCFG2_OTGMODE_SRPCAPD (0x3UL)  /*!< (unspecified)                                                        */
87842   #define USBHSCORE_GHWCFG2_OTGMODE_NONOTGD (0x4UL)  /*!< (unspecified)                                                        */
87843   #define USBHSCORE_GHWCFG2_OTGMODE_SRPCAPH (0x5UL)  /*!< (unspecified)                                                        */
87844   #define USBHSCORE_GHWCFG2_OTGMODE_NONOTGH (0x6UL)  /*!< (unspecified)                                                        */
87845 
87846 /* OTGARCH @Bits 3..4 : Architecture (OtgArch) */
87847   #define USBHSCORE_GHWCFG2_OTGARCH_Pos (3UL)        /*!< Position of OTGARCH field.                                           */
87848   #define USBHSCORE_GHWCFG2_OTGARCH_Msk (0x3UL << USBHSCORE_GHWCFG2_OTGARCH_Pos) /*!< Bit mask of OTGARCH field.               */
87849   #define USBHSCORE_GHWCFG2_OTGARCH_Min (0x0UL)      /*!< Min enumerator value of OTGARCH field.                               */
87850   #define USBHSCORE_GHWCFG2_OTGARCH_Max (0x2UL)      /*!< Max enumerator value of OTGARCH field.                               */
87851   #define USBHSCORE_GHWCFG2_OTGARCH_SLAVEMODE (0x0UL) /*!< (unspecified)                                                       */
87852   #define USBHSCORE_GHWCFG2_OTGARCH_EXTERNALDMA (0x1UL) /*!< (unspecified)                                                     */
87853   #define USBHSCORE_GHWCFG2_OTGARCH_INTERNALDMA (0x2UL) /*!< (unspecified)                                                     */
87854 
87855 /* SINGPNT @Bit 5 : Point-to-Point (SingPnt) */
87856   #define USBHSCORE_GHWCFG2_SINGPNT_Pos (5UL)        /*!< Position of SINGPNT field.                                           */
87857   #define USBHSCORE_GHWCFG2_SINGPNT_Msk (0x1UL << USBHSCORE_GHWCFG2_SINGPNT_Pos) /*!< Bit mask of SINGPNT field.               */
87858   #define USBHSCORE_GHWCFG2_SINGPNT_Min (0x0UL)      /*!< Min enumerator value of SINGPNT field.                               */
87859   #define USBHSCORE_GHWCFG2_SINGPNT_Max (0x1UL)      /*!< Max enumerator value of SINGPNT field.                               */
87860   #define USBHSCORE_GHWCFG2_SINGPNT_MULTIPOINT (0x0UL) /*!< (unspecified)                                                      */
87861   #define USBHSCORE_GHWCFG2_SINGPNT_SINGLEPOINT (0x1UL) /*!< (unspecified)                                                     */
87862 
87863 /* HSPHYTYPE @Bits 6..7 : High-Speed PHY Interface Type (HSPhyType) */
87864   #define USBHSCORE_GHWCFG2_HSPHYTYPE_Pos (6UL)      /*!< Position of HSPHYTYPE field.                                         */
87865   #define USBHSCORE_GHWCFG2_HSPHYTYPE_Msk (0x3UL << USBHSCORE_GHWCFG2_HSPHYTYPE_Pos) /*!< Bit mask of HSPHYTYPE field.         */
87866   #define USBHSCORE_GHWCFG2_HSPHYTYPE_Min (0x0UL)    /*!< Min enumerator value of HSPHYTYPE field.                             */
87867   #define USBHSCORE_GHWCFG2_HSPHYTYPE_Max (0x3UL)    /*!< Max enumerator value of HSPHYTYPE field.                             */
87868   #define USBHSCORE_GHWCFG2_HSPHYTYPE_NOHS (0x0UL)   /*!< (unspecified)                                                        */
87869   #define USBHSCORE_GHWCFG2_HSPHYTYPE_UTMIPLUS (0x1UL) /*!< (unspecified)                                                      */
87870   #define USBHSCORE_GHWCFG2_HSPHYTYPE_ULPI (0x2UL)   /*!< (unspecified)                                                        */
87871   #define USBHSCORE_GHWCFG2_HSPHYTYPE_UTMIPUSULPI (0x3UL) /*!< (unspecified)                                                   */
87872 
87873 /* FSPHYTYPE @Bits 8..9 : Full-Speed PHY Interface Type (FSPhyType) */
87874   #define USBHSCORE_GHWCFG2_FSPHYTYPE_Pos (8UL)      /*!< Position of FSPHYTYPE field.                                         */
87875   #define USBHSCORE_GHWCFG2_FSPHYTYPE_Msk (0x3UL << USBHSCORE_GHWCFG2_FSPHYTYPE_Pos) /*!< Bit mask of FSPHYTYPE field.         */
87876   #define USBHSCORE_GHWCFG2_FSPHYTYPE_Min (0x0UL)    /*!< Min enumerator value of FSPHYTYPE field.                             */
87877   #define USBHSCORE_GHWCFG2_FSPHYTYPE_Max (0x3UL)    /*!< Max enumerator value of FSPHYTYPE field.                             */
87878   #define USBHSCORE_GHWCFG2_FSPHYTYPE_NO_FS (0x0UL)  /*!< (unspecified)                                                        */
87879   #define USBHSCORE_GHWCFG2_FSPHYTYPE_FS (0x1UL)     /*!< (unspecified)                                                        */
87880   #define USBHSCORE_GHWCFG2_FSPHYTYPE_FSPLUSUTMI (0x2UL) /*!< (unspecified)                                                    */
87881   #define USBHSCORE_GHWCFG2_FSPHYTYPE_FSPLUSULPI (0x3UL) /*!< (unspecified)                                                    */
87882 
87883 /* NUMDEVEPS @Bits 10..13 : Number of Device Endpoints (NumDevEps) */
87884   #define USBHSCORE_GHWCFG2_NUMDEVEPS_Pos (10UL)     /*!< Position of NUMDEVEPS field.                                         */
87885   #define USBHSCORE_GHWCFG2_NUMDEVEPS_Msk (0xFUL << USBHSCORE_GHWCFG2_NUMDEVEPS_Pos) /*!< Bit mask of NUMDEVEPS field.         */
87886   #define USBHSCORE_GHWCFG2_NUMDEVEPS_Min (0x0UL)    /*!< Min enumerator value of NUMDEVEPS field.                             */
87887   #define USBHSCORE_GHWCFG2_NUMDEVEPS_Max (0xFUL)    /*!< Max enumerator value of NUMDEVEPS field.                             */
87888   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT0 (0x0UL) /*!< (unspecified)                                                        */
87889   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT1 (0x1UL) /*!< (unspecified)                                                        */
87890   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT2 (0x2UL) /*!< (unspecified)                                                        */
87891   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT3 (0x3UL) /*!< (unspecified)                                                        */
87892   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT4 (0x4UL) /*!< (unspecified)                                                        */
87893   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT5 (0x5UL) /*!< (unspecified)                                                        */
87894   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT6 (0x6UL) /*!< (unspecified)                                                        */
87895   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT7 (0x7UL) /*!< (unspecified)                                                        */
87896   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT8 (0x8UL) /*!< (unspecified)                                                        */
87897   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT9 (0x9UL) /*!< (unspecified)                                                        */
87898   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT10 (0xAUL) /*!< (unspecified)                                                       */
87899   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT11 (0xBUL) /*!< (unspecified)                                                       */
87900   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT12 (0xCUL) /*!< (unspecified)                                                       */
87901   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT13 (0xDUL) /*!< (unspecified)                                                       */
87902   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT14 (0xEUL) /*!< (unspecified)                                                       */
87903   #define USBHSCORE_GHWCFG2_NUMDEVEPS_ENDPT15 (0xFUL) /*!< (unspecified)                                                       */
87904 
87905 /* NUMHSTCHNL @Bits 14..17 : Number of Host Channels (NumHstChnl) */
87906   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Pos (14UL)    /*!< Position of NUMHSTCHNL field.                                        */
87907   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Msk (0xFUL << USBHSCORE_GHWCFG2_NUMHSTCHNL_Pos) /*!< Bit mask of NUMHSTCHNL field.      */
87908   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Min (0x0UL)   /*!< Min enumerator value of NUMHSTCHNL field.                            */
87909   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_Max (0xFUL)   /*!< Max enumerator value of NUMHSTCHNL field.                            */
87910   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH0 (0x0UL) /*!< (unspecified)                                                      */
87911   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH1 (0x1UL) /*!< (unspecified)                                                      */
87912   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH2 (0x2UL) /*!< (unspecified)                                                      */
87913   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH3 (0x3UL) /*!< (unspecified)                                                      */
87914   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH4 (0x4UL) /*!< (unspecified)                                                      */
87915   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH5 (0x5UL) /*!< (unspecified)                                                      */
87916   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH6 (0x6UL) /*!< (unspecified)                                                      */
87917   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH7 (0x7UL) /*!< (unspecified)                                                      */
87918   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH8 (0x8UL) /*!< (unspecified)                                                      */
87919   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH9 (0x9UL) /*!< (unspecified)                                                      */
87920   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH10 (0xAUL) /*!< (unspecified)                                                     */
87921   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH11 (0xBUL) /*!< (unspecified)                                                     */
87922   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH12 (0xCUL) /*!< (unspecified)                                                     */
87923   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH13 (0xDUL) /*!< (unspecified)                                                     */
87924   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH14 (0xEUL) /*!< (unspecified)                                                     */
87925   #define USBHSCORE_GHWCFG2_NUMHSTCHNL_HOSTCH15 (0xFUL) /*!< (unspecified)                                                     */
87926 
87927 /* PERIOSUPPORT @Bit 18 : Periodic OUT Channels Supported in Host Mode (PerioSupport) */
87928   #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Pos (18UL)  /*!< Position of PERIOSUPPORT field.                                      */
87929   #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG2_PERIOSUPPORT_Pos) /*!< Bit mask of PERIOSUPPORT field.*/
87930   #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Min (0x0UL) /*!< Min enumerator value of PERIOSUPPORT field.                          */
87931   #define USBHSCORE_GHWCFG2_PERIOSUPPORT_Max (0x1UL) /*!< Max enumerator value of PERIOSUPPORT field.                          */
87932   #define USBHSCORE_GHWCFG2_PERIOSUPPORT_DISABLED (0x0UL) /*!< (unspecified)                                                   */
87933   #define USBHSCORE_GHWCFG2_PERIOSUPPORT_ENABLED (0x1UL) /*!< (unspecified)                                                    */
87934 
87935 /* DYNFIFOSIZING @Bit 19 : Dynamic FIFO Sizing Enabled (DynFifoSizing) */
87936   #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Pos (19UL) /*!< Position of DYNFIFOSIZING field.                                     */
87937   #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Msk (0x1UL << USBHSCORE_GHWCFG2_DYNFIFOSIZING_Pos) /*!< Bit mask of DYNFIFOSIZING
87938                                                                             field.*/
87939   #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Min (0x0UL) /*!< Min enumerator value of DYNFIFOSIZING field.                        */
87940   #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_Max (0x1UL) /*!< Max enumerator value of DYNFIFOSIZING field.                        */
87941   #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_DISABLED (0x0UL) /*!< (unspecified)                                                  */
87942   #define USBHSCORE_GHWCFG2_DYNFIFOSIZING_ENABLED (0x1UL) /*!< (unspecified)                                                   */
87943 
87944 /* MULTIPROCINTRPT @Bit 20 : Multi Processor Interrupt Enabled (MultiProcIntrpt) */
87945   #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Pos (20UL) /*!< Position of MULTIPROCINTRPT field.                                 */
87946   #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Msk (0x1UL << USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Pos) /*!< Bit mask of
87947                                                                             MULTIPROCINTRPT field.*/
87948   #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Min (0x0UL) /*!< Min enumerator value of MULTIPROCINTRPT field.                    */
87949   #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_Max (0x1UL) /*!< Max enumerator value of MULTIPROCINTRPT field.                    */
87950   #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_DISABLED (0x0UL) /*!< (unspecified)                                                */
87951   #define USBHSCORE_GHWCFG2_MULTIPROCINTRPT_ENABLED (0x1UL) /*!< (unspecified)                                                 */
87952 
87953 /* NPTXQDEPTH @Bits 22..23 : Non-periodic Request Queue Depth (NPTxQDepth) */
87954   #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Pos (22UL)    /*!< Position of NPTXQDEPTH field.                                        */
87955   #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Msk (0x3UL << USBHSCORE_GHWCFG2_NPTXQDEPTH_Pos) /*!< Bit mask of NPTXQDEPTH field.      */
87956   #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Min (0x0UL)   /*!< Min enumerator value of NPTXQDEPTH field.                            */
87957   #define USBHSCORE_GHWCFG2_NPTXQDEPTH_Max (0x2UL)   /*!< Max enumerator value of NPTXQDEPTH field.                            */
87958   #define USBHSCORE_GHWCFG2_NPTXQDEPTH_TWO (0x0UL)   /*!< (unspecified)                                                        */
87959   #define USBHSCORE_GHWCFG2_NPTXQDEPTH_FOUR (0x1UL)  /*!< (unspecified)                                                        */
87960   #define USBHSCORE_GHWCFG2_NPTXQDEPTH_EIGHT (0x2UL) /*!< (unspecified)                                                        */
87961 
87962 /* PTXQDEPTH @Bits 24..25 : Host Mode Periodic Request Queue Depth (PTxQDepth) */
87963   #define USBHSCORE_GHWCFG2_PTXQDEPTH_Pos (24UL)     /*!< Position of PTXQDEPTH field.                                         */
87964   #define USBHSCORE_GHWCFG2_PTXQDEPTH_Msk (0x3UL << USBHSCORE_GHWCFG2_PTXQDEPTH_Pos) /*!< Bit mask of PTXQDEPTH field.         */
87965   #define USBHSCORE_GHWCFG2_PTXQDEPTH_Min (0x0UL)    /*!< Min enumerator value of PTXQDEPTH field.                             */
87966   #define USBHSCORE_GHWCFG2_PTXQDEPTH_Max (0x3UL)    /*!< Max enumerator value of PTXQDEPTH field.                             */
87967   #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE2 (0x0UL)   /*!< (unspecified)                                                        */
87968   #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE4 (0x1UL)   /*!< (unspecified)                                                        */
87969   #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE8 (0x2UL)   /*!< (unspecified)                                                        */
87970   #define USBHSCORE_GHWCFG2_PTXQDEPTH_QUE16 (0x3UL)  /*!< (unspecified)                                                        */
87971 
87972 /* TKNQDEPTH @Bits 26..30 : Device Mode IN Token Sequence Learning Queue Depth (TknQDepth) */
87973   #define USBHSCORE_GHWCFG2_TKNQDEPTH_Pos (26UL)     /*!< Position of TKNQDEPTH field.                                         */
87974   #define USBHSCORE_GHWCFG2_TKNQDEPTH_Msk (0x1FUL << USBHSCORE_GHWCFG2_TKNQDEPTH_Pos) /*!< Bit mask of TKNQDEPTH field.        */
87975 
87976 
87977 /* USBHSCORE_GHWCFG3: User Hardware Configuration 3 Register */
87978   #define USBHSCORE_GHWCFG3_ResetValue (0x0BEAC0E8UL) /*!< Reset value of GHWCFG3 register.                                    */
87979 
87980 /* XFERSIZEWIDTH @Bits 0..3 : Width of Transfer Size Counters (XferSizeWidth) */
87981   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Pos (0UL)  /*!< Position of XFERSIZEWIDTH field.                                     */
87982   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Msk (0xFUL << USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Pos) /*!< Bit mask of XFERSIZEWIDTH
87983                                                                             field.*/
87984   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Min (0x0UL) /*!< Min enumerator value of XFERSIZEWIDTH field.                        */
87985   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_Max (0x8UL) /*!< Max enumerator value of XFERSIZEWIDTH field.                        */
87986   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH11 (0x0UL) /*!< (unspecified)                                                   */
87987   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH12 (0x1UL) /*!< (unspecified)                                                   */
87988   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH13 (0x2UL) /*!< (unspecified)                                                   */
87989   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH14 (0x3UL) /*!< (unspecified)                                                   */
87990   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH15 (0x4UL) /*!< (unspecified)                                                   */
87991   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH16 (0x5UL) /*!< (unspecified)                                                   */
87992   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH17 (0x6UL) /*!< (unspecified)                                                   */
87993   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH18 (0x7UL) /*!< (unspecified)                                                   */
87994   #define USBHSCORE_GHWCFG3_XFERSIZEWIDTH_WIDTH19 (0x8UL) /*!< (unspecified)                                                   */
87995 
87996 /* PKTSIZEWIDTH @Bits 4..6 : Width of Packet Size Counters (PktSizeWidth) */
87997   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Pos (4UL)   /*!< Position of PKTSIZEWIDTH field.                                      */
87998   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Msk (0x7UL << USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Pos) /*!< Bit mask of PKTSIZEWIDTH field.*/
87999   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Min (0x0UL) /*!< Min enumerator value of PKTSIZEWIDTH field.                          */
88000   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_Max (0x6UL) /*!< Max enumerator value of PKTSIZEWIDTH field.                          */
88001   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS4 (0x0UL) /*!< (unspecified)                                                      */
88002   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS5 (0x1UL) /*!< (unspecified)                                                      */
88003   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS6 (0x2UL) /*!< (unspecified)                                                      */
88004   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS7 (0x3UL) /*!< (unspecified)                                                      */
88005   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS8 (0x4UL) /*!< (unspecified)                                                      */
88006   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS9 (0x5UL) /*!< (unspecified)                                                      */
88007   #define USBHSCORE_GHWCFG3_PKTSIZEWIDTH_BITS10 (0x6UL) /*!< (unspecified)                                                     */
88008 
88009 /* OTGEN @Bit 7 : OTG Function Enabled (OtgEn) */
88010   #define USBHSCORE_GHWCFG3_OTGEN_Pos (7UL)          /*!< Position of OTGEN field.                                             */
88011   #define USBHSCORE_GHWCFG3_OTGEN_Msk (0x1UL << USBHSCORE_GHWCFG3_OTGEN_Pos) /*!< Bit mask of OTGEN field.                     */
88012   #define USBHSCORE_GHWCFG3_OTGEN_Min (0x0UL)        /*!< Min enumerator value of OTGEN field.                                 */
88013   #define USBHSCORE_GHWCFG3_OTGEN_Max (0x1UL)        /*!< Max enumerator value of OTGEN field.                                 */
88014   #define USBHSCORE_GHWCFG3_OTGEN_DISABLED (0x0UL)   /*!< (unspecified)                                                        */
88015   #define USBHSCORE_GHWCFG3_OTGEN_ENABLED (0x1UL)    /*!< (unspecified)                                                        */
88016 
88017 /* I2CINTSEL @Bit 8 : I2C Selection (I2CIntSel) */
88018   #define USBHSCORE_GHWCFG3_I2CINTSEL_Pos (8UL)      /*!< Position of I2CINTSEL field.                                         */
88019   #define USBHSCORE_GHWCFG3_I2CINTSEL_Msk (0x1UL << USBHSCORE_GHWCFG3_I2CINTSEL_Pos) /*!< Bit mask of I2CINTSEL field.         */
88020   #define USBHSCORE_GHWCFG3_I2CINTSEL_Min (0x0UL)    /*!< Min enumerator value of I2CINTSEL field.                             */
88021   #define USBHSCORE_GHWCFG3_I2CINTSEL_Max (0x1UL)    /*!< Max enumerator value of I2CINTSEL field.                             */
88022   #define USBHSCORE_GHWCFG3_I2CINTSEL_DISABLED (0x0UL) /*!< (unspecified)                                                      */
88023   #define USBHSCORE_GHWCFG3_I2CINTSEL_ENABLED (0x1UL) /*!< (unspecified)                                                       */
88024 
88025 /* VNDCTLSUPT @Bit 9 : Vendor Control Interface Support (VndctlSupt) */
88026   #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Pos (9UL)     /*!< Position of VNDCTLSUPT field.                                        */
88027   #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Msk (0x1UL << USBHSCORE_GHWCFG3_VNDCTLSUPT_Pos) /*!< Bit mask of VNDCTLSUPT field.      */
88028   #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Min (0x0UL)   /*!< Min enumerator value of VNDCTLSUPT field.                            */
88029   #define USBHSCORE_GHWCFG3_VNDCTLSUPT_Max (0x1UL)   /*!< Max enumerator value of VNDCTLSUPT field.                            */
88030   #define USBHSCORE_GHWCFG3_VNDCTLSUPT_DISABLED (0x0UL) /*!< (unspecified)                                                     */
88031   #define USBHSCORE_GHWCFG3_VNDCTLSUPT_ENABLED (0x1UL) /*!< (unspecified)                                                      */
88032 
88033 /* OPTFEATURE @Bit 10 : Optional Features Removed (OptFeature) */
88034   #define USBHSCORE_GHWCFG3_OPTFEATURE_Pos (10UL)    /*!< Position of OPTFEATURE field.                                        */
88035   #define USBHSCORE_GHWCFG3_OPTFEATURE_Msk (0x1UL << USBHSCORE_GHWCFG3_OPTFEATURE_Pos) /*!< Bit mask of OPTFEATURE field.      */
88036   #define USBHSCORE_GHWCFG3_OPTFEATURE_Min (0x0UL)   /*!< Min enumerator value of OPTFEATURE field.                            */
88037   #define USBHSCORE_GHWCFG3_OPTFEATURE_Max (0x1UL)   /*!< Max enumerator value of OPTFEATURE field.                            */
88038   #define USBHSCORE_GHWCFG3_OPTFEATURE_DISABLED (0x0UL) /*!< (unspecified)                                                     */
88039   #define USBHSCORE_GHWCFG3_OPTFEATURE_ENABLED (0x1UL) /*!< (unspecified)                                                      */
88040 
88041 /* RSTTYPE @Bit 11 : Reset Style for Clocked always Blocks in RTL (RstType) */
88042   #define USBHSCORE_GHWCFG3_RSTTYPE_Pos (11UL)       /*!< Position of RSTTYPE field.                                           */
88043   #define USBHSCORE_GHWCFG3_RSTTYPE_Msk (0x1UL << USBHSCORE_GHWCFG3_RSTTYPE_Pos) /*!< Bit mask of RSTTYPE field.               */
88044   #define USBHSCORE_GHWCFG3_RSTTYPE_Min (0x0UL)      /*!< Min enumerator value of RSTTYPE field.                               */
88045   #define USBHSCORE_GHWCFG3_RSTTYPE_Max (0x1UL)      /*!< Max enumerator value of RSTTYPE field.                               */
88046   #define USBHSCORE_GHWCFG3_RSTTYPE_ASYNCRST (0x0UL) /*!< (unspecified)                                                        */
88047   #define USBHSCORE_GHWCFG3_RSTTYPE_SYNCRST (0x1UL)  /*!< (unspecified)                                                        */
88048 
88049 /* ADPSUPPORT @Bit 12 : This bit indicates whether ADP logic is present within or external to the controller */
88050   #define USBHSCORE_GHWCFG3_ADPSUPPORT_Pos (12UL)    /*!< Position of ADPSUPPORT field.                                        */
88051   #define USBHSCORE_GHWCFG3_ADPSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG3_ADPSUPPORT_Pos) /*!< Bit mask of ADPSUPPORT field.      */
88052   #define USBHSCORE_GHWCFG3_ADPSUPPORT_Min (0x0UL)   /*!< Min enumerator value of ADPSUPPORT field.                            */
88053   #define USBHSCORE_GHWCFG3_ADPSUPPORT_Max (0x1UL)   /*!< Max enumerator value of ADPSUPPORT field.                            */
88054   #define USBHSCORE_GHWCFG3_ADPSUPPORT_DISABLED (0x0UL) /*!< (unspecified)                                                     */
88055   #define USBHSCORE_GHWCFG3_ADPSUPPORT_ENABLED (0x1UL) /*!< (unspecified)                                                      */
88056 
88057 /* HSICMODE @Bit 13 : HSIC mode specified for Mode of Operation */
88058   #define USBHSCORE_GHWCFG3_HSICMODE_Pos (13UL)      /*!< Position of HSICMODE field.                                          */
88059   #define USBHSCORE_GHWCFG3_HSICMODE_Msk (0x1UL << USBHSCORE_GHWCFG3_HSICMODE_Pos) /*!< Bit mask of HSICMODE field.            */
88060   #define USBHSCORE_GHWCFG3_HSICMODE_Min (0x0UL)     /*!< Min enumerator value of HSICMODE field.                              */
88061   #define USBHSCORE_GHWCFG3_HSICMODE_Max (0x1UL)     /*!< Max enumerator value of HSICMODE field.                              */
88062   #define USBHSCORE_GHWCFG3_HSICMODE_DISABLED (0x0UL) /*!< (unspecified)                                                       */
88063   #define USBHSCORE_GHWCFG3_HSICMODE_ENABLED (0x1UL) /*!< (unspecified)                                                        */
88064 
88065 /* BCSUPPORT @Bit 14 : This bit indicates the controller support for Battery Charger. */
88066   #define USBHSCORE_GHWCFG3_BCSUPPORT_Pos (14UL)     /*!< Position of BCSUPPORT field.                                         */
88067   #define USBHSCORE_GHWCFG3_BCSUPPORT_Msk (0x1UL << USBHSCORE_GHWCFG3_BCSUPPORT_Pos) /*!< Bit mask of BCSUPPORT field.         */
88068   #define USBHSCORE_GHWCFG3_BCSUPPORT_Min (0x0UL)    /*!< Min enumerator value of BCSUPPORT field.                             */
88069   #define USBHSCORE_GHWCFG3_BCSUPPORT_Max (0x1UL)    /*!< Max enumerator value of BCSUPPORT field.                             */
88070   #define USBHSCORE_GHWCFG3_BCSUPPORT_DISABLED (0x0UL) /*!< (unspecified)                                                      */
88071   #define USBHSCORE_GHWCFG3_BCSUPPORT_ENABLED (0x1UL) /*!< (unspecified)                                                       */
88072 
88073 /* LPMMODE @Bit 15 : LPM mode specified for Mode of Operation. */
88074   #define USBHSCORE_GHWCFG3_LPMMODE_Pos (15UL)       /*!< Position of LPMMODE field.                                           */
88075   #define USBHSCORE_GHWCFG3_LPMMODE_Msk (0x1UL << USBHSCORE_GHWCFG3_LPMMODE_Pos) /*!< Bit mask of LPMMODE field.               */
88076   #define USBHSCORE_GHWCFG3_LPMMODE_Min (0x0UL)      /*!< Min enumerator value of LPMMODE field.                               */
88077   #define USBHSCORE_GHWCFG3_LPMMODE_Max (0x1UL)      /*!< Max enumerator value of LPMMODE field.                               */
88078   #define USBHSCORE_GHWCFG3_LPMMODE_DISABLED (0x0UL) /*!< (unspecified)                                                        */
88079   #define USBHSCORE_GHWCFG3_LPMMODE_ENABLED (0x1UL)  /*!< (unspecified)                                                        */
88080 
88081 /* DFIFODEPTH @Bits 16..31 : DFIFO Depth (DfifoDepth - EP_LOC_CNT) */
88082   #define USBHSCORE_GHWCFG3_DFIFODEPTH_Pos (16UL)    /*!< Position of DFIFODEPTH field.                                        */
88083   #define USBHSCORE_GHWCFG3_DFIFODEPTH_Msk (0xFFFFUL << USBHSCORE_GHWCFG3_DFIFODEPTH_Pos) /*!< Bit mask of DFIFODEPTH field.   */
88084 
88085 
88086 /* USBHSCORE_GHWCFG4: User Hardware Configuration 4 Register */
88087   #define USBHSCORE_GHWCFG4_ResetValue (0x1FF0AA60UL) /*!< Reset value of GHWCFG4 register.                                    */
88088 
88089 /* NUMDEVPERIOEPS @Bits 0..3 : Number of Device Mode Periodic IN Endpoints (NumDevPerioEps) */
88090   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Pos (0UL) /*!< Position of NUMDEVPERIOEPS field.                                    */
88091   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Pos) /*!< Bit mask of NUMDEVPERIOEPS
88092                                                                             field.*/
88093   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Min (0x0UL) /*!< Min enumerator value of NUMDEVPERIOEPS field.                      */
88094   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Max (0xFUL) /*!< Max enumerator value of NUMDEVPERIOEPS field.                      */
88095   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value0 (0x0UL) /*!< (unspecified)                                                   */
88096   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value1 (0x1UL) /*!< (unspecified)                                                   */
88097   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value2 (0x2UL) /*!< (unspecified)                                                   */
88098   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value3 (0x3UL) /*!< (unspecified)                                                   */
88099   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value4 (0x4UL) /*!< (unspecified)                                                   */
88100   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value5 (0x5UL) /*!< (unspecified)                                                   */
88101   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value6 (0x6UL) /*!< (unspecified)                                                   */
88102   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value7 (0x7UL) /*!< (unspecified)                                                   */
88103   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value8 (0x8UL) /*!< (unspecified)                                                   */
88104   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value9 (0x9UL) /*!< (unspecified)                                                   */
88105   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value10 (0xAUL) /*!< (unspecified)                                                  */
88106   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value11 (0xBUL) /*!< (unspecified)                                                  */
88107   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value12 (0xCUL) /*!< (unspecified)                                                  */
88108   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value13 (0xDUL) /*!< (unspecified)                                                  */
88109   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value14 (0xEUL) /*!< (unspecified)                                                  */
88110   #define USBHSCORE_GHWCFG4_NUMDEVPERIOEPS_Value15 (0xFUL) /*!< (unspecified)                                                  */
88111 
88112 /* PARTIALPWRDN @Bit 4 : Enable Partial Power Down (PartialPwrDn) */
88113   #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Pos (4UL)   /*!< Position of PARTIALPWRDN field.                                      */
88114   #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Msk (0x1UL << USBHSCORE_GHWCFG4_PARTIALPWRDN_Pos) /*!< Bit mask of PARTIALPWRDN field.*/
88115   #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Min (0x0UL) /*!< Min enumerator value of PARTIALPWRDN field.                          */
88116   #define USBHSCORE_GHWCFG4_PARTIALPWRDN_Max (0x1UL) /*!< Max enumerator value of PARTIALPWRDN field.                          */
88117   #define USBHSCORE_GHWCFG4_PARTIALPWRDN_DISABLED (0x0UL) /*!< (unspecified)                                                   */
88118   #define USBHSCORE_GHWCFG4_PARTIALPWRDN_ENABLED (0x1UL) /*!< (unspecified)                                                    */
88119 
88120 /* AHBFREQ @Bit 5 : Minimum AHB Frequency Less Than 60 MHz (AhbFreq) */
88121   #define USBHSCORE_GHWCFG4_AHBFREQ_Pos (5UL)        /*!< Position of AHBFREQ field.                                           */
88122   #define USBHSCORE_GHWCFG4_AHBFREQ_Msk (0x1UL << USBHSCORE_GHWCFG4_AHBFREQ_Pos) /*!< Bit mask of AHBFREQ field.               */
88123   #define USBHSCORE_GHWCFG4_AHBFREQ_Min (0x0UL)      /*!< Min enumerator value of AHBFREQ field.                               */
88124   #define USBHSCORE_GHWCFG4_AHBFREQ_Max (0x1UL)      /*!< Max enumerator value of AHBFREQ field.                               */
88125   #define USBHSCORE_GHWCFG4_AHBFREQ_DISABLED (0x0UL) /*!< (unspecified)                                                        */
88126   #define USBHSCORE_GHWCFG4_AHBFREQ_ENABLED (0x1UL)  /*!< (unspecified)                                                        */
88127 
88128 /* HIBERNATION @Bit 6 : Enable Hibernation (Hibernation) */
88129   #define USBHSCORE_GHWCFG4_HIBERNATION_Pos (6UL)    /*!< Position of HIBERNATION field.                                       */
88130   #define USBHSCORE_GHWCFG4_HIBERNATION_Msk (0x1UL << USBHSCORE_GHWCFG4_HIBERNATION_Pos) /*!< Bit mask of HIBERNATION field.   */
88131   #define USBHSCORE_GHWCFG4_HIBERNATION_Min (0x0UL)  /*!< Min enumerator value of HIBERNATION field.                           */
88132   #define USBHSCORE_GHWCFG4_HIBERNATION_Max (0x1UL)  /*!< Max enumerator value of HIBERNATION field.                           */
88133   #define USBHSCORE_GHWCFG4_HIBERNATION_DISABLED (0x0UL) /*!< (unspecified)                                                    */
88134   #define USBHSCORE_GHWCFG4_HIBERNATION_ENABLED (0x1UL) /*!< (unspecified)                                                     */
88135 
88136 /* EXTENDEDHIBERNATION @Bit 7 : Enable Hibernation */
88137   #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Pos (7UL) /*!< Position of EXTENDEDHIBERNATION field.                          */
88138   #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Msk (0x1UL << USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Pos) /*!< Bit mask of
88139                                                                             EXTENDEDHIBERNATION field.*/
88140   #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Min (0x0UL) /*!< Min enumerator value of EXTENDEDHIBERNATION field.            */
88141   #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_Max (0x1UL) /*!< Max enumerator value of EXTENDEDHIBERNATION field.            */
88142   #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_DISABLED (0x0UL) /*!< (unspecified)                                            */
88143   #define USBHSCORE_GHWCFG4_EXTENDEDHIBERNATION_ENABLED (0x1UL) /*!< (unspecified)                                             */
88144 
88145 /* ENHANCEDLPMSUPT1 @Bit 9 : Enhanced LPM Support1 (EnhancedLPMSupt1) */
88146   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Pos (9UL) /*!< Position of ENHANCEDLPMSUPT1 field.                                */
88147   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Msk (0x1UL << USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Pos) /*!< Bit mask of
88148                                                                             ENHANCEDLPMSUPT1 field.*/
88149   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Min (0x0UL) /*!< Min enumerator value of ENHANCEDLPMSUPT1 field.                  */
88150   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_Max (0x1UL) /*!< Max enumerator value of ENHANCEDLPMSUPT1 field.                  */
88151   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_DISABLED (0x0UL) /*!< (unspecified)                                               */
88152   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT1_ENABLED (0x1UL) /*!< (unspecified)                                                */
88153 
88154 /* SERVINTFLOW @Bit 10 : Service Interval Flow */
88155   #define USBHSCORE_GHWCFG4_SERVINTFLOW_Pos (10UL)   /*!< Position of SERVINTFLOW field.                                       */
88156   #define USBHSCORE_GHWCFG4_SERVINTFLOW_Msk (0x1UL << USBHSCORE_GHWCFG4_SERVINTFLOW_Pos) /*!< Bit mask of SERVINTFLOW field.   */
88157   #define USBHSCORE_GHWCFG4_SERVINTFLOW_Min (0x0UL)  /*!< Min enumerator value of SERVINTFLOW field.                           */
88158   #define USBHSCORE_GHWCFG4_SERVINTFLOW_Max (0x1UL)  /*!< Max enumerator value of SERVINTFLOW field.                           */
88159   #define USBHSCORE_GHWCFG4_SERVINTFLOW_DISABLED (0x0UL) /*!< (unspecified)                                                    */
88160   #define USBHSCORE_GHWCFG4_SERVINTFLOW_ENABLED (0x1UL) /*!< (unspecified)                                                     */
88161 
88162 /* IPGISOCSUPT @Bit 11 : Interpacket Gap ISOC OUT Worst-case Support (ipgisocSupt) */
88163   #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Pos (11UL)   /*!< Position of IPGISOCSUPT field.                                       */
88164   #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_IPGISOCSUPT_Pos) /*!< Bit mask of IPGISOCSUPT field.   */
88165   #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Min (0x0UL)  /*!< Min enumerator value of IPGISOCSUPT field.                           */
88166   #define USBHSCORE_GHWCFG4_IPGISOCSUPT_Max (0x1UL)  /*!< Max enumerator value of IPGISOCSUPT field.                           */
88167   #define USBHSCORE_GHWCFG4_IPGISOCSUPT_DISABLED (0x0UL) /*!< (unspecified)                                                    */
88168   #define USBHSCORE_GHWCFG4_IPGISOCSUPT_ENABLED (0x1UL) /*!< (unspecified)                                                     */
88169 
88170 /* ACGSUPT @Bit 12 : Active Clock Gating Support */
88171   #define USBHSCORE_GHWCFG4_ACGSUPT_Pos (12UL)       /*!< Position of ACGSUPT field.                                           */
88172   #define USBHSCORE_GHWCFG4_ACGSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_ACGSUPT_Pos) /*!< Bit mask of ACGSUPT field.               */
88173   #define USBHSCORE_GHWCFG4_ACGSUPT_Min (0x0UL)      /*!< Min enumerator value of ACGSUPT field.                               */
88174   #define USBHSCORE_GHWCFG4_ACGSUPT_Max (0x1UL)      /*!< Max enumerator value of ACGSUPT field.                               */
88175   #define USBHSCORE_GHWCFG4_ACGSUPT_DISABLED (0x0UL) /*!< (unspecified)                                                        */
88176   #define USBHSCORE_GHWCFG4_ACGSUPT_ENABLED (0x1UL)  /*!< (unspecified)                                                        */
88177 
88178 /* ENHANCEDLPMSUPT @Bit 13 : Enhanced LPM Support (EnhancedLPMSupt) */
88179   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Pos (13UL) /*!< Position of ENHANCEDLPMSUPT field.                                 */
88180   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Msk (0x1UL << USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Pos) /*!< Bit mask of
88181                                                                             ENHANCEDLPMSUPT field.*/
88182   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Min (0x1UL) /*!< Min enumerator value of ENHANCEDLPMSUPT field.                    */
88183   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_Max (0x1UL) /*!< Max enumerator value of ENHANCEDLPMSUPT field.                    */
88184   #define USBHSCORE_GHWCFG4_ENHANCEDLPMSUPT_ENABLED (0x1UL) /*!< (unspecified)                                                 */
88185 
88186 /* PHYDATAWIDTH @Bits 14..15 : UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */
88187   #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Pos (14UL)  /*!< Position of PHYDATAWIDTH field.                                      */
88188   #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Msk (0x3UL << USBHSCORE_GHWCFG4_PHYDATAWIDTH_Pos) /*!< Bit mask of PHYDATAWIDTH field.*/
88189   #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Min (0x0UL) /*!< Min enumerator value of PHYDATAWIDTH field.                          */
88190   #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_Max (0x2UL) /*!< Max enumerator value of PHYDATAWIDTH field.                          */
88191   #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH1 (0x0UL) /*!< (unspecified)                                                     */
88192   #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH2 (0x1UL) /*!< (unspecified)                                                     */
88193   #define USBHSCORE_GHWCFG4_PHYDATAWIDTH_WIDTH3 (0x2UL) /*!< (unspecified)                                                     */
88194 
88195 /* NUMCTLEPS @Bits 16..19 : Number of Device Mode Control Endpoints in Addition to */
88196   #define USBHSCORE_GHWCFG4_NUMCTLEPS_Pos (16UL)     /*!< Position of NUMCTLEPS field.                                         */
88197   #define USBHSCORE_GHWCFG4_NUMCTLEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_NUMCTLEPS_Pos) /*!< Bit mask of NUMCTLEPS field.         */
88198   #define USBHSCORE_GHWCFG4_NUMCTLEPS_Min (0x0UL)    /*!< Min enumerator value of NUMCTLEPS field.                             */
88199   #define USBHSCORE_GHWCFG4_NUMCTLEPS_Max (0xFUL)    /*!< Max enumerator value of NUMCTLEPS field.                             */
88200   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT0 (0x0UL) /*!< (unspecified)                                                        */
88201   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT1 (0x1UL) /*!< (unspecified)                                                        */
88202   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT2 (0x2UL) /*!< (unspecified)                                                        */
88203   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT3 (0x3UL) /*!< (unspecified)                                                        */
88204   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT4 (0x4UL) /*!< (unspecified)                                                        */
88205   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT5 (0x5UL) /*!< (unspecified)                                                        */
88206   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT6 (0x6UL) /*!< (unspecified)                                                        */
88207   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT7 (0x7UL) /*!< (unspecified)                                                        */
88208   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT8 (0x8UL) /*!< (unspecified)                                                        */
88209   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT9 (0x9UL) /*!< (unspecified)                                                        */
88210   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT10 (0xAUL) /*!< (unspecified)                                                       */
88211   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT11 (0xBUL) /*!< (unspecified)                                                       */
88212   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT12 (0xCUL) /*!< (unspecified)                                                       */
88213   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT13 (0xDUL) /*!< (unspecified)                                                       */
88214   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT14 (0xEUL) /*!< (unspecified)                                                       */
88215   #define USBHSCORE_GHWCFG4_NUMCTLEPS_ENDPT15 (0xFUL) /*!< (unspecified)                                                       */
88216 
88217 /* IDDGFLTR @Bit 20 : IDDIG Filter Enable (IddgFltr) */
88218   #define USBHSCORE_GHWCFG4_IDDGFLTR_Pos (20UL)      /*!< Position of IDDGFLTR field.                                          */
88219   #define USBHSCORE_GHWCFG4_IDDGFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_IDDGFLTR_Pos) /*!< Bit mask of IDDGFLTR field.            */
88220   #define USBHSCORE_GHWCFG4_IDDGFLTR_Min (0x0UL)     /*!< Min enumerator value of IDDGFLTR field.                              */
88221   #define USBHSCORE_GHWCFG4_IDDGFLTR_Max (0x1UL)     /*!< Max enumerator value of IDDGFLTR field.                              */
88222   #define USBHSCORE_GHWCFG4_IDDGFLTR_DISABLED (0x0UL) /*!< (unspecified)                                                       */
88223   #define USBHSCORE_GHWCFG4_IDDGFLTR_ENABLED (0x1UL) /*!< (unspecified)                                                        */
88224 
88225 /* VBUSVALIDFLTR @Bit 21 : VBUS Valid Filter Enabled (VBusValidFltr) */
88226   #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Pos (21UL) /*!< Position of VBUSVALIDFLTR field.                                     */
88227   #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Pos) /*!< Bit mask of VBUSVALIDFLTR
88228                                                                             field.*/
88229   #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Min (0x0UL) /*!< Min enumerator value of VBUSVALIDFLTR field.                        */
88230   #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_Max (0x1UL) /*!< Max enumerator value of VBUSVALIDFLTR field.                        */
88231   #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_DISABLED (0x0UL) /*!< (unspecified)                                                  */
88232   #define USBHSCORE_GHWCFG4_VBUSVALIDFLTR_ENABLED (0x1UL) /*!< (unspecified)                                                   */
88233 
88234 /* AVALIDFLTR @Bit 22 : a_valid Filter Enabled (AValidFltr) */
88235   #define USBHSCORE_GHWCFG4_AVALIDFLTR_Pos (22UL)    /*!< Position of AVALIDFLTR field.                                        */
88236   #define USBHSCORE_GHWCFG4_AVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_AVALIDFLTR_Pos) /*!< Bit mask of AVALIDFLTR field.      */
88237   #define USBHSCORE_GHWCFG4_AVALIDFLTR_Min (0x0UL)   /*!< Min enumerator value of AVALIDFLTR field.                            */
88238   #define USBHSCORE_GHWCFG4_AVALIDFLTR_Max (0x1UL)   /*!< Max enumerator value of AVALIDFLTR field.                            */
88239   #define USBHSCORE_GHWCFG4_AVALIDFLTR_DISABLED (0x0UL) /*!< (unspecified)                                                     */
88240   #define USBHSCORE_GHWCFG4_AVALIDFLTR_ENABLED (0x1UL) /*!< (unspecified)                                                      */
88241 
88242 /* BVALIDFLTR @Bit 23 : b_valid Filter Enabled (BValidFltr) */
88243   #define USBHSCORE_GHWCFG4_BVALIDFLTR_Pos (23UL)    /*!< Position of BVALIDFLTR field.                                        */
88244   #define USBHSCORE_GHWCFG4_BVALIDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_BVALIDFLTR_Pos) /*!< Bit mask of BVALIDFLTR field.      */
88245   #define USBHSCORE_GHWCFG4_BVALIDFLTR_Min (0x0UL)   /*!< Min enumerator value of BVALIDFLTR field.                            */
88246   #define USBHSCORE_GHWCFG4_BVALIDFLTR_Max (0x1UL)   /*!< Max enumerator value of BVALIDFLTR field.                            */
88247   #define USBHSCORE_GHWCFG4_BVALIDFLTR_DISABLED (0x0UL) /*!< (unspecified)                                                     */
88248   #define USBHSCORE_GHWCFG4_BVALIDFLTR_ENABLED (0x1UL) /*!< (unspecified)                                                      */
88249 
88250 /* SESSENDFLTR @Bit 24 : session_end Filter Enabled (SessEndFltr) */
88251   #define USBHSCORE_GHWCFG4_SESSENDFLTR_Pos (24UL)   /*!< Position of SESSENDFLTR field.                                       */
88252   #define USBHSCORE_GHWCFG4_SESSENDFLTR_Msk (0x1UL << USBHSCORE_GHWCFG4_SESSENDFLTR_Pos) /*!< Bit mask of SESSENDFLTR field.   */
88253   #define USBHSCORE_GHWCFG4_SESSENDFLTR_Min (0x0UL)  /*!< Min enumerator value of SESSENDFLTR field.                           */
88254   #define USBHSCORE_GHWCFG4_SESSENDFLTR_Max (0x1UL)  /*!< Max enumerator value of SESSENDFLTR field.                           */
88255   #define USBHSCORE_GHWCFG4_SESSENDFLTR_DISABLED (0x0UL) /*!< (unspecified)                                                    */
88256   #define USBHSCORE_GHWCFG4_SESSENDFLTR_ENABLED (0x1UL) /*!< (unspecified)                                                     */
88257 
88258 /* DEDFIFOMODE @Bit 25 : Enable Dedicated Transmit FIFO for device IN Endpoints */
88259   #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Pos (25UL)   /*!< Position of DEDFIFOMODE field.                                       */
88260   #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Msk (0x1UL << USBHSCORE_GHWCFG4_DEDFIFOMODE_Pos) /*!< Bit mask of DEDFIFOMODE field.   */
88261   #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Min (0x0UL)  /*!< Min enumerator value of DEDFIFOMODE field.                           */
88262   #define USBHSCORE_GHWCFG4_DEDFIFOMODE_Max (0x1UL)  /*!< Max enumerator value of DEDFIFOMODE field.                           */
88263   #define USBHSCORE_GHWCFG4_DEDFIFOMODE_DISABLED (0x0UL) /*!< (unspecified)                                                    */
88264   #define USBHSCORE_GHWCFG4_DEDFIFOMODE_ENABLED (0x1UL) /*!< (unspecified)                                                     */
88265 
88266 /* INEPS @Bits 26..29 : Number of Device Mode IN Endpoints Including Control Endpoints (INEps) */
88267   #define USBHSCORE_GHWCFG4_INEPS_Pos (26UL)         /*!< Position of INEPS field.                                             */
88268   #define USBHSCORE_GHWCFG4_INEPS_Msk (0xFUL << USBHSCORE_GHWCFG4_INEPS_Pos) /*!< Bit mask of INEPS field.                     */
88269   #define USBHSCORE_GHWCFG4_INEPS_Min (0x0UL)        /*!< Min enumerator value of INEPS field.                                 */
88270   #define USBHSCORE_GHWCFG4_INEPS_Max (0xFUL)        /*!< Max enumerator value of INEPS field.                                 */
88271   #define USBHSCORE_GHWCFG4_INEPS_ENDPT1 (0x0UL)     /*!< (unspecified)                                                        */
88272   #define USBHSCORE_GHWCFG4_INEPS_ENDPT2 (0x1UL)     /*!< (unspecified)                                                        */
88273   #define USBHSCORE_GHWCFG4_INEPS_ENDPT3 (0x2UL)     /*!< (unspecified)                                                        */
88274   #define USBHSCORE_GHWCFG4_INEPS_ENDPT4 (0x3UL)     /*!< (unspecified)                                                        */
88275   #define USBHSCORE_GHWCFG4_INEPS_ENDPT5 (0x4UL)     /*!< (unspecified)                                                        */
88276   #define USBHSCORE_GHWCFG4_INEPS_ENDPT6 (0x5UL)     /*!< (unspecified)                                                        */
88277   #define USBHSCORE_GHWCFG4_INEPS_ENDPT7 (0x6UL)     /*!< (unspecified)                                                        */
88278   #define USBHSCORE_GHWCFG4_INEPS_ENDPT8 (0x7UL)     /*!< (unspecified)                                                        */
88279   #define USBHSCORE_GHWCFG4_INEPS_ENDPT9 (0x8UL)     /*!< (unspecified)                                                        */
88280   #define USBHSCORE_GHWCFG4_INEPS_ENDPT10 (0x9UL)    /*!< (unspecified)                                                        */
88281   #define USBHSCORE_GHWCFG4_INEPS_ENDPT11 (0xAUL)    /*!< (unspecified)                                                        */
88282   #define USBHSCORE_GHWCFG4_INEPS_ENDPT12 (0xBUL)    /*!< (unspecified)                                                        */
88283   #define USBHSCORE_GHWCFG4_INEPS_ENDPT13 (0xCUL)    /*!< (unspecified)                                                        */
88284   #define USBHSCORE_GHWCFG4_INEPS_ENDPT14 (0xDUL)    /*!< (unspecified)                                                        */
88285   #define USBHSCORE_GHWCFG4_INEPS_ENDPT15 (0xEUL)    /*!< (unspecified)                                                        */
88286   #define USBHSCORE_GHWCFG4_INEPS_ENDPT16 (0xFUL)    /*!< (unspecified)                                                        */
88287 
88288 /* DESCDMAENABLED @Bit 30 : Scatter/Gather DMA configuration */
88289   #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Pos (30UL) /*!< Position of DESCDMAENABLED field.                                   */
88290   #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Msk (0x1UL << USBHSCORE_GHWCFG4_DESCDMAENABLED_Pos) /*!< Bit mask of DESCDMAENABLED
88291                                                                             field.*/
88292   #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Min (0x0UL) /*!< Min enumerator value of DESCDMAENABLED field.                      */
88293   #define USBHSCORE_GHWCFG4_DESCDMAENABLED_Max (0x1UL) /*!< Max enumerator value of DESCDMAENABLED field.                      */
88294   #define USBHSCORE_GHWCFG4_DESCDMAENABLED_DISABLE (0x0UL) /*!< (unspecified)                                                  */
88295   #define USBHSCORE_GHWCFG4_DESCDMAENABLED_ENABLE (0x1UL) /*!< (unspecified)                                                   */
88296 
88297 /* DESCDMA @Bit 31 : Scatter/Gather DMA configuration */
88298   #define USBHSCORE_GHWCFG4_DESCDMA_Pos (31UL)       /*!< Position of DESCDMA field.                                           */
88299   #define USBHSCORE_GHWCFG4_DESCDMA_Msk (0x1UL << USBHSCORE_GHWCFG4_DESCDMA_Pos) /*!< Bit mask of DESCDMA field.               */
88300   #define USBHSCORE_GHWCFG4_DESCDMA_Min (0x0UL)      /*!< Min enumerator value of DESCDMA field.                               */
88301   #define USBHSCORE_GHWCFG4_DESCDMA_Max (0x1UL)      /*!< Max enumerator value of DESCDMA field.                               */
88302   #define USBHSCORE_GHWCFG4_DESCDMA_CONFIG1 (0x0UL)  /*!< (unspecified)                                                        */
88303   #define USBHSCORE_GHWCFG4_DESCDMA_CONFIG2 (0x1UL)  /*!< (unspecified)                                                        */
88304 
88305 
88306 /* USBHSCORE_GLPMCFG: LPM Config Register */
88307   #define USBHSCORE_GLPMCFG_ResetValue (0x00000000UL) /*!< Reset value of GLPMCFG register.                                    */
88308 
88309 /* LPMCAP @Bit 0 : LPM-Capable (LPMCap) */
88310   #define USBHSCORE_GLPMCFG_LPMCAP_Pos (0UL)         /*!< Position of LPMCAP field.                                            */
88311   #define USBHSCORE_GLPMCFG_LPMCAP_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMCAP_Pos) /*!< Bit mask of LPMCAP field.                  */
88312   #define USBHSCORE_GLPMCFG_LPMCAP_Min (0x0UL)       /*!< Min enumerator value of LPMCAP field.                                */
88313   #define USBHSCORE_GLPMCFG_LPMCAP_Max (0x1UL)       /*!< Max enumerator value of LPMCAP field.                                */
88314   #define USBHSCORE_GLPMCFG_LPMCAP_DISABLED (0x0UL)  /*!< (unspecified)                                                        */
88315   #define USBHSCORE_GLPMCFG_LPMCAP_ENABLED (0x1UL)   /*!< (unspecified)                                                        */
88316 
88317 /* APPL1RES @Bit 1 : Mode: Device only. LPM response programmed by application (AppL1Res) */
88318   #define USBHSCORE_GLPMCFG_APPL1RES_Pos (1UL)       /*!< Position of APPL1RES field.                                          */
88319   #define USBHSCORE_GLPMCFG_APPL1RES_Msk (0x1UL << USBHSCORE_GLPMCFG_APPL1RES_Pos) /*!< Bit mask of APPL1RES field.            */
88320   #define USBHSCORE_GLPMCFG_APPL1RES_Min (0x0UL)     /*!< Min enumerator value of APPL1RES field.                              */
88321   #define USBHSCORE_GLPMCFG_APPL1RES_Max (0x1UL)     /*!< Max enumerator value of APPL1RES field.                              */
88322   #define USBHSCORE_GLPMCFG_APPL1RES_NYET_RESP (0x0UL) /*!< (unspecified)                                                      */
88323   #define USBHSCORE_GLPMCFG_APPL1RES_ACK_RESP (0x1UL) /*!< (unspecified)                                                       */
88324 
88325 /* HIRD @Bits 2..5 : Host-Initiated Resume Duration (HIRD) */
88326   #define USBHSCORE_GLPMCFG_HIRD_Pos (2UL)           /*!< Position of HIRD field.                                              */
88327   #define USBHSCORE_GLPMCFG_HIRD_Msk (0xFUL << USBHSCORE_GLPMCFG_HIRD_Pos) /*!< Bit mask of HIRD field.                        */
88328 
88329 /* BREMOTEWAKE @Bit 6 : RemoteWakeEnable (bRemoteWake) */
88330   #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Pos (6UL)    /*!< Position of BREMOTEWAKE field.                                       */
88331   #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Msk (0x1UL << USBHSCORE_GLPMCFG_BREMOTEWAKE_Pos) /*!< Bit mask of BREMOTEWAKE field.   */
88332   #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Min (0x0UL)  /*!< Min enumerator value of BREMOTEWAKE field.                           */
88333   #define USBHSCORE_GLPMCFG_BREMOTEWAKE_Max (0x1UL)  /*!< Max enumerator value of BREMOTEWAKE field.                           */
88334   #define USBHSCORE_GLPMCFG_BREMOTEWAKE_DISABLED (0x0UL) /*!< (unspecified)                                                    */
88335   #define USBHSCORE_GLPMCFG_BREMOTEWAKE_ENABLED (0x1UL) /*!< (unspecified)                                                     */
88336 
88337 /* ENBLSLPM @Bit 7 : Enable utmi_sleep_n (EnblSlpM) */
88338   #define USBHSCORE_GLPMCFG_ENBLSLPM_Pos (7UL)       /*!< Position of ENBLSLPM field.                                          */
88339   #define USBHSCORE_GLPMCFG_ENBLSLPM_Msk (0x1UL << USBHSCORE_GLPMCFG_ENBLSLPM_Pos) /*!< Bit mask of ENBLSLPM field.            */
88340   #define USBHSCORE_GLPMCFG_ENBLSLPM_Min (0x0UL)     /*!< Min enumerator value of ENBLSLPM field.                              */
88341   #define USBHSCORE_GLPMCFG_ENBLSLPM_Max (0x1UL)     /*!< Max enumerator value of ENBLSLPM field.                              */
88342   #define USBHSCORE_GLPMCFG_ENBLSLPM_DISABLED (0x0UL) /*!< (unspecified)                                                       */
88343   #define USBHSCORE_GLPMCFG_ENBLSLPM_ENABLED (0x1UL) /*!< (unspecified)                                                        */
88344 
88345 /* HIRDTHRES @Bits 8..12 : BESL/HIRD Threshold (HIRD_Thres) */
88346   #define USBHSCORE_GLPMCFG_HIRDTHRES_Pos (8UL)      /*!< Position of HIRDTHRES field.                                         */
88347   #define USBHSCORE_GLPMCFG_HIRDTHRES_Msk (0x1FUL << USBHSCORE_GLPMCFG_HIRDTHRES_Pos) /*!< Bit mask of HIRDTHRES field.        */
88348 
88349 /* COREL1RES @Bits 13..14 : LPM Response (CoreL1Res) */
88350   #define USBHSCORE_GLPMCFG_COREL1RES_Pos (13UL)     /*!< Position of COREL1RES field.                                         */
88351   #define USBHSCORE_GLPMCFG_COREL1RES_Msk (0x3UL << USBHSCORE_GLPMCFG_COREL1RES_Pos) /*!< Bit mask of COREL1RES field.         */
88352   #define USBHSCORE_GLPMCFG_COREL1RES_Min (0x0UL)    /*!< Min enumerator value of COREL1RES field.                             */
88353   #define USBHSCORE_GLPMCFG_COREL1RES_Max (0x3UL)    /*!< Max enumerator value of COREL1RES field.                             */
88354   #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP1 (0x0UL) /*!< (unspecified)                                                      */
88355   #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP2 (0x1UL) /*!< (unspecified)                                                      */
88356   #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP3 (0x2UL) /*!< (unspecified)                                                      */
88357   #define USBHSCORE_GLPMCFG_COREL1RES_LPMRESP4 (0x3UL) /*!< (unspecified)                                                      */
88358 
88359 /* SLPSTS @Bit 15 : Port Sleep Status (SlpSts) */
88360   #define USBHSCORE_GLPMCFG_SLPSTS_Pos (15UL)        /*!< Position of SLPSTS field.                                            */
88361   #define USBHSCORE_GLPMCFG_SLPSTS_Msk (0x1UL << USBHSCORE_GLPMCFG_SLPSTS_Pos) /*!< Bit mask of SLPSTS field.                  */
88362   #define USBHSCORE_GLPMCFG_SLPSTS_Min (0x0UL)       /*!< Min enumerator value of SLPSTS field.                                */
88363   #define USBHSCORE_GLPMCFG_SLPSTS_Max (0x1UL)       /*!< Max enumerator value of SLPSTS field.                                */
88364   #define USBHSCORE_GLPMCFG_SLPSTS_CORE_NOT_IN_L1 (0x0UL) /*!< (unspecified)                                                   */
88365   #define USBHSCORE_GLPMCFG_SLPSTS_CORE_IN_L1 (0x1UL) /*!< (unspecified)                                                       */
88366 
88367 /* L1RESUMEOK @Bit 16 : Sleep State Resume OK (L1ResumeOK) */
88368   #define USBHSCORE_GLPMCFG_L1RESUMEOK_Pos (16UL)    /*!< Position of L1RESUMEOK field.                                        */
88369   #define USBHSCORE_GLPMCFG_L1RESUMEOK_Msk (0x1UL << USBHSCORE_GLPMCFG_L1RESUMEOK_Pos) /*!< Bit mask of L1RESUMEOK field.      */
88370   #define USBHSCORE_GLPMCFG_L1RESUMEOK_Min (0x0UL)   /*!< Min enumerator value of L1RESUMEOK field.                            */
88371   #define USBHSCORE_GLPMCFG_L1RESUMEOK_Max (0x1UL)   /*!< Max enumerator value of L1RESUMEOK field.                            */
88372   #define USBHSCORE_GLPMCFG_L1RESUMEOK_NOTOK (0x0UL) /*!< (unspecified)                                                        */
88373   #define USBHSCORE_GLPMCFG_L1RESUMEOK_OK (0x1UL)    /*!< (unspecified)                                                        */
88374 
88375 /* LPMCHNLINDX @Bits 17..20 : LPM Channel Index */
88376   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Pos (17UL)   /*!< Position of LPMCHNLINDX field.                                       */
88377   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Msk (0xFUL << USBHSCORE_GLPMCFG_LPMCHNLINDX_Pos) /*!< Bit mask of LPMCHNLINDX field.   */
88378   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Min (0x0UL)  /*!< Min enumerator value of LPMCHNLINDX field.                           */
88379   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_Max (0xFUL)  /*!< Max enumerator value of LPMCHNLINDX field.                           */
88380   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH0 (0x0UL)  /*!< (unspecified)                                                        */
88381   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH1 (0x1UL)  /*!< (unspecified)                                                        */
88382   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH2 (0x2UL)  /*!< (unspecified)                                                        */
88383   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH3 (0x3UL)  /*!< (unspecified)                                                        */
88384   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH4 (0x4UL)  /*!< (unspecified)                                                        */
88385   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH5 (0x5UL)  /*!< (unspecified)                                                        */
88386   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH6 (0x6UL)  /*!< (unspecified)                                                        */
88387   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH7 (0x7UL)  /*!< (unspecified)                                                        */
88388   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH8 (0x8UL)  /*!< (unspecified)                                                        */
88389   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH9 (0x9UL)  /*!< (unspecified)                                                        */
88390   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH10 (0xAUL) /*!< (unspecified)                                                        */
88391   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH11 (0xBUL) /*!< (unspecified)                                                        */
88392   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH12 (0xCUL) /*!< (unspecified)                                                        */
88393   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH13 (0xDUL) /*!< (unspecified)                                                        */
88394   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH14 (0xEUL) /*!< (unspecified)                                                        */
88395   #define USBHSCORE_GLPMCFG_LPMCHNLINDX_CH15 (0xFUL) /*!< (unspecified)                                                        */
88396 
88397 /* LPMRETRYCNT @Bits 21..23 : LPM Retry Count (LPM_Retry_Cnt) */
88398   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Pos (21UL)   /*!< Position of LPMRETRYCNT field.                                       */
88399   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Msk (0x7UL << USBHSCORE_GLPMCFG_LPMRETRYCNT_Pos) /*!< Bit mask of LPMRETRYCNT field.   */
88400   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Min (0x0UL)  /*!< Min enumerator value of LPMRETRYCNT field.                           */
88401   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_Max (0x7UL)  /*!< Max enumerator value of LPMRETRYCNT field.                           */
88402   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY0 (0x0UL) /*!< (unspecified)                                                      */
88403   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY1 (0x1UL) /*!< (unspecified)                                                      */
88404   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY2 (0x2UL) /*!< (unspecified)                                                      */
88405   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY3 (0x3UL) /*!< (unspecified)                                                      */
88406   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY4 (0x4UL) /*!< (unspecified)                                                      */
88407   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY5 (0x5UL) /*!< (unspecified)                                                      */
88408   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY6 (0x6UL) /*!< (unspecified)                                                      */
88409   #define USBHSCORE_GLPMCFG_LPMRETRYCNT_RETRY7 (0x7UL) /*!< (unspecified)                                                      */
88410 
88411 /* SNDLPM @Bit 24 : Send LPM Transaction (SndLPM) */
88412   #define USBHSCORE_GLPMCFG_SNDLPM_Pos (24UL)        /*!< Position of SNDLPM field.                                            */
88413   #define USBHSCORE_GLPMCFG_SNDLPM_Msk (0x1UL << USBHSCORE_GLPMCFG_SNDLPM_Pos) /*!< Bit mask of SNDLPM field.                  */
88414   #define USBHSCORE_GLPMCFG_SNDLPM_Min (0x0UL)       /*!< Min enumerator value of SNDLPM field.                                */
88415   #define USBHSCORE_GLPMCFG_SNDLPM_Max (0x1UL)       /*!< Max enumerator value of SNDLPM field.                                */
88416   #define USBHSCORE_GLPMCFG_SNDLPM_DISABLED (0x0UL)  /*!< (unspecified)                                                        */
88417   #define USBHSCORE_GLPMCFG_SNDLPM_ENABLED (0x1UL)   /*!< (unspecified)                                                        */
88418 
88419 /* LPMRETRYCNTSTS @Bits 25..27 : LPM Retry Count Status (LPM_RetryCnt_Sts) */
88420   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Pos (25UL) /*!< Position of LPMRETRYCNTSTS field.                                   */
88421   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Msk (0x7UL << USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Pos) /*!< Bit mask of LPMRETRYCNTSTS
88422                                                                             field.*/
88423   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Min (0x0UL) /*!< Min enumerator value of LPMRETRYCNTSTS field.                      */
88424   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_Max (0x7UL) /*!< Max enumerator value of LPMRETRYCNTSTS field.                      */
88425   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM0 (0x0UL) /*!< (unspecified)                                               */
88426   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM1 (0x1UL) /*!< (unspecified)                                               */
88427   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM2 (0x2UL) /*!< (unspecified)                                               */
88428   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM3 (0x3UL) /*!< (unspecified)                                               */
88429   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM4 (0x4UL) /*!< (unspecified)                                               */
88430   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM5 (0x5UL) /*!< (unspecified)                                               */
88431   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM6 (0x6UL) /*!< (unspecified)                                               */
88432   #define USBHSCORE_GLPMCFG_LPMRETRYCNTSTS_RETRY_REM7 (0x7UL) /*!< (unspecified)                                               */
88433 
88434 /* LPMENBESL @Bit 28 : LPM Enable BESL (LPM_EnBESL) */
88435   #define USBHSCORE_GLPMCFG_LPMENBESL_Pos (28UL)     /*!< Position of LPMENBESL field.                                         */
88436   #define USBHSCORE_GLPMCFG_LPMENBESL_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMENBESL_Pos) /*!< Bit mask of LPMENBESL field.         */
88437   #define USBHSCORE_GLPMCFG_LPMENBESL_Min (0x0UL)    /*!< Min enumerator value of LPMENBESL field.                             */
88438   #define USBHSCORE_GLPMCFG_LPMENBESL_Max (0x1UL)    /*!< Max enumerator value of LPMENBESL field.                             */
88439   #define USBHSCORE_GLPMCFG_LPMENBESL_DISABLED (0x0UL) /*!< (unspecified)                                                      */
88440   #define USBHSCORE_GLPMCFG_LPMENBESL_ENABLED (0x1UL) /*!< (unspecified)                                                       */
88441 
88442 /* LPMRESTORESLPSTS @Bit 29 : LPM Restore Sleep Status (LPM_RestoreSlpSts) */
88443   #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Pos (29UL) /*!< Position of LPMRESTORESLPSTS field.                               */
88444   #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Msk (0x1UL << USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Pos) /*!< Bit mask of
88445                                                                             LPMRESTORESLPSTS field.*/
88446   #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Min (0x0UL) /*!< Min enumerator value of LPMRESTORESLPSTS field.                  */
88447   #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_Max (0x1UL) /*!< Max enumerator value of LPMRESTORESLPSTS field.                  */
88448   #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_DISABLED (0x0UL) /*!< (unspecified)                                               */
88449   #define USBHSCORE_GLPMCFG_LPMRESTORESLPSTS_ENABLED (0x1UL) /*!< (unspecified)                                                */
88450 
88451 
88452 /* USBHSCORE_GPWRDN: Global Power Down register */
88453   #define USBHSCORE_GPWRDN_ResetValue (0x00000010UL) /*!< Reset value of GPWRDN register.                                      */
88454 
88455 /* PMUINTSEL @Bit 0 : PMU Interrupt Select (PMUIntSel) */
88456   #define USBHSCORE_GPWRDN_PMUINTSEL_Pos (0UL)       /*!< Position of PMUINTSEL field.                                         */
88457   #define USBHSCORE_GPWRDN_PMUINTSEL_Msk (0x1UL << USBHSCORE_GPWRDN_PMUINTSEL_Pos) /*!< Bit mask of PMUINTSEL field.           */
88458   #define USBHSCORE_GPWRDN_PMUINTSEL_Min (0x0UL)     /*!< Min enumerator value of PMUINTSEL field.                             */
88459   #define USBHSCORE_GPWRDN_PMUINTSEL_Max (0x1UL)     /*!< Max enumerator value of PMUINTSEL field.                             */
88460   #define USBHSCORE_GPWRDN_PMUINTSEL_DISABLE (0x0UL) /*!< (unspecified)                                                        */
88461   #define USBHSCORE_GPWRDN_PMUINTSEL_ENABLE (0x1UL)  /*!< (unspecified)                                                        */
88462 
88463 /* PMUACTV @Bit 1 : PMU Active (PMUActv) */
88464   #define USBHSCORE_GPWRDN_PMUACTV_Pos (1UL)         /*!< Position of PMUACTV field.                                           */
88465   #define USBHSCORE_GPWRDN_PMUACTV_Msk (0x1UL << USBHSCORE_GPWRDN_PMUACTV_Pos) /*!< Bit mask of PMUACTV field.                 */
88466   #define USBHSCORE_GPWRDN_PMUACTV_Min (0x0UL)       /*!< Min enumerator value of PMUACTV field.                               */
88467   #define USBHSCORE_GPWRDN_PMUACTV_Max (0x1UL)       /*!< Max enumerator value of PMUACTV field.                               */
88468   #define USBHSCORE_GPWRDN_PMUACTV_DISABLE (0x0UL)   /*!< (unspecified)                                                        */
88469   #define USBHSCORE_GPWRDN_PMUACTV_ENABLE (0x1UL)    /*!< (unspecified)                                                        */
88470 
88471 /* RESTORE @Bit 2 : Restore */
88472   #define USBHSCORE_GPWRDN_RESTORE_Pos (2UL)         /*!< Position of RESTORE field.                                           */
88473   #define USBHSCORE_GPWRDN_RESTORE_Msk (0x1UL << USBHSCORE_GPWRDN_RESTORE_Pos) /*!< Bit mask of RESTORE field.                 */
88474   #define USBHSCORE_GPWRDN_RESTORE_Min (0x0UL)       /*!< Min enumerator value of RESTORE field.                               */
88475   #define USBHSCORE_GPWRDN_RESTORE_Max (0x1UL)       /*!< Max enumerator value of RESTORE field.                               */
88476   #define USBHSCORE_GPWRDN_RESTORE_DISABLE (0x0UL)   /*!< (unspecified)                                                        */
88477   #define USBHSCORE_GPWRDN_RESTORE_ENABLE (0x1UL)    /*!< (unspecified)                                                        */
88478 
88479 /* PWRDNCLMP @Bit 3 : Power Down Clamp (PwrDnClmp) */
88480   #define USBHSCORE_GPWRDN_PWRDNCLMP_Pos (3UL)       /*!< Position of PWRDNCLMP field.                                         */
88481   #define USBHSCORE_GPWRDN_PWRDNCLMP_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNCLMP_Pos) /*!< Bit mask of PWRDNCLMP field.           */
88482   #define USBHSCORE_GPWRDN_PWRDNCLMP_Min (0x0UL)     /*!< Min enumerator value of PWRDNCLMP field.                             */
88483   #define USBHSCORE_GPWRDN_PWRDNCLMP_Max (0x1UL)     /*!< Max enumerator value of PWRDNCLMP field.                             */
88484   #define USBHSCORE_GPWRDN_PWRDNCLMP_DISABLE (0x0UL) /*!< (unspecified)                                                        */
88485   #define USBHSCORE_GPWRDN_PWRDNCLMP_ENABLE (0x1UL)  /*!< (unspecified)                                                        */
88486 
88487 /* PWRDNRSTN @Bit 4 : Power Down ResetN (PwrDnRst_n) */
88488   #define USBHSCORE_GPWRDN_PWRDNRSTN_Pos (4UL)       /*!< Position of PWRDNRSTN field.                                         */
88489   #define USBHSCORE_GPWRDN_PWRDNRSTN_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNRSTN_Pos) /*!< Bit mask of PWRDNRSTN field.           */
88490   #define USBHSCORE_GPWRDN_PWRDNRSTN_Min (0x0UL)     /*!< Min enumerator value of PWRDNRSTN field.                             */
88491   #define USBHSCORE_GPWRDN_PWRDNRSTN_Max (0x1UL)     /*!< Max enumerator value of PWRDNRSTN field.                             */
88492   #define USBHSCORE_GPWRDN_PWRDNRSTN_DISABLE (0x0UL) /*!< (unspecified)                                                        */
88493   #define USBHSCORE_GPWRDN_PWRDNRSTN_ENABLE (0x1UL)  /*!< (unspecified)                                                        */
88494 
88495 /* PWRDNSWTCH @Bit 5 : Power Down Switch (PwrDnSwtch) */
88496   #define USBHSCORE_GPWRDN_PWRDNSWTCH_Pos (5UL)      /*!< Position of PWRDNSWTCH field.                                        */
88497   #define USBHSCORE_GPWRDN_PWRDNSWTCH_Msk (0x1UL << USBHSCORE_GPWRDN_PWRDNSWTCH_Pos) /*!< Bit mask of PWRDNSWTCH field.        */
88498   #define USBHSCORE_GPWRDN_PWRDNSWTCH_Min (0x0UL)    /*!< Min enumerator value of PWRDNSWTCH field.                            */
88499   #define USBHSCORE_GPWRDN_PWRDNSWTCH_Max (0x1UL)    /*!< Max enumerator value of PWRDNSWTCH field.                            */
88500   #define USBHSCORE_GPWRDN_PWRDNSWTCH_ON (0x0UL)     /*!< (unspecified)                                                        */
88501   #define USBHSCORE_GPWRDN_PWRDNSWTCH_OFF (0x1UL)    /*!< (unspecified)                                                        */
88502 
88503 /* DISABLEVBUS @Bit 6 : DisableVBUS */
88504   #define USBHSCORE_GPWRDN_DISABLEVBUS_Pos (6UL)     /*!< Position of DISABLEVBUS field.                                       */
88505   #define USBHSCORE_GPWRDN_DISABLEVBUS_Msk (0x1UL << USBHSCORE_GPWRDN_DISABLEVBUS_Pos) /*!< Bit mask of DISABLEVBUS field.     */
88506   #define USBHSCORE_GPWRDN_DISABLEVBUS_Min (0x0UL)   /*!< Min enumerator value of DISABLEVBUS field.                           */
88507   #define USBHSCORE_GPWRDN_DISABLEVBUS_Max (0x1UL)   /*!< Max enumerator value of DISABLEVBUS field.                           */
88508   #define USBHSCORE_GPWRDN_DISABLEVBUS_DISABLED (0x0UL) /*!< (unspecified)                                                     */
88509   #define USBHSCORE_GPWRDN_DISABLEVBUS_ENABLED (0x1UL) /*!< (unspecified)                                                      */
88510 
88511 /* LNSTSCHNG @Bit 7 : Line State Change (LnStsChng) */
88512   #define USBHSCORE_GPWRDN_LNSTSCHNG_Pos (7UL)       /*!< Position of LNSTSCHNG field.                                         */
88513   #define USBHSCORE_GPWRDN_LNSTSCHNG_Msk (0x1UL << USBHSCORE_GPWRDN_LNSTSCHNG_Pos) /*!< Bit mask of LNSTSCHNG field.           */
88514   #define USBHSCORE_GPWRDN_LNSTSCHNG_Min (0x0UL)     /*!< Min enumerator value of LNSTSCHNG field.                             */
88515   #define USBHSCORE_GPWRDN_LNSTSCHNG_Max (0x1UL)     /*!< Max enumerator value of LNSTSCHNG field.                             */
88516   #define USBHSCORE_GPWRDN_LNSTSCHNG_DISABLED (0x0UL) /*!< (unspecified)                                                       */
88517   #define USBHSCORE_GPWRDN_LNSTSCHNG_ENABLED (0x1UL) /*!< (unspecified)                                                        */
88518 
88519 /* LINESTAGECHANGEMSK @Bit 8 : LineStageChangeMsk */
88520   #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Pos (8UL) /*!< Position of LINESTAGECHANGEMSK field.                             */
88521   #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Msk (0x1UL << USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Pos) /*!< Bit mask of
88522                                                                             LINESTAGECHANGEMSK field.*/
88523   #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Min (0x0UL) /*!< Min enumerator value of LINESTAGECHANGEMSK field.               */
88524   #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_Max (0x1UL) /*!< Max enumerator value of LINESTAGECHANGEMSK field.               */
88525   #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_NOMASK (0x0UL) /*!< (unspecified)                                                */
88526   #define USBHSCORE_GPWRDN_LINESTAGECHANGEMSK_MASK (0x1UL) /*!< (unspecified)                                                  */
88527 
88528 /* RESETDETECTED @Bit 9 : ResetDetected */
88529   #define USBHSCORE_GPWRDN_RESETDETECTED_Pos (9UL)   /*!< Position of RESETDETECTED field.                                     */
88530   #define USBHSCORE_GPWRDN_RESETDETECTED_Msk (0x1UL << USBHSCORE_GPWRDN_RESETDETECTED_Pos) /*!< Bit mask of RESETDETECTED
88531                                                                             field.*/
88532   #define USBHSCORE_GPWRDN_RESETDETECTED_Min (0x0UL) /*!< Min enumerator value of RESETDETECTED field.                         */
88533   #define USBHSCORE_GPWRDN_RESETDETECTED_Max (0x1UL) /*!< Max enumerator value of RESETDETECTED field.                         */
88534   #define USBHSCORE_GPWRDN_RESETDETECTED_DISABLED (0x0UL) /*!< (unspecified)                                                   */
88535   #define USBHSCORE_GPWRDN_RESETDETECTED_ENABLED (0x1UL) /*!< (unspecified)                                                    */
88536 
88537 /* RESETDETMSK @Bit 10 : ResetDetMsk */
88538   #define USBHSCORE_GPWRDN_RESETDETMSK_Pos (10UL)    /*!< Position of RESETDETMSK field.                                       */
88539   #define USBHSCORE_GPWRDN_RESETDETMSK_Msk (0x1UL << USBHSCORE_GPWRDN_RESETDETMSK_Pos) /*!< Bit mask of RESETDETMSK field.     */
88540   #define USBHSCORE_GPWRDN_RESETDETMSK_Min (0x0UL)   /*!< Min enumerator value of RESETDETMSK field.                           */
88541   #define USBHSCORE_GPWRDN_RESETDETMSK_Max (0x1UL)   /*!< Max enumerator value of RESETDETMSK field.                           */
88542   #define USBHSCORE_GPWRDN_RESETDETMSK_NOMASK (0x0UL) /*!< (unspecified)                                                       */
88543   #define USBHSCORE_GPWRDN_RESETDETMSK_MASK (0x1UL)  /*!< (unspecified)                                                        */
88544 
88545 /* DISCONNECTDETECT @Bit 11 : DisconnectDetect */
88546   #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Pos (11UL) /*!< Position of DISCONNECTDETECT field.                                */
88547   #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Msk (0x1UL << USBHSCORE_GPWRDN_DISCONNECTDETECT_Pos) /*!< Bit mask of
88548                                                                             DISCONNECTDETECT field.*/
88549   #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Min (0x0UL) /*!< Min enumerator value of DISCONNECTDETECT field.                   */
88550   #define USBHSCORE_GPWRDN_DISCONNECTDETECT_Max (0x1UL) /*!< Max enumerator value of DISCONNECTDETECT field.                   */
88551   #define USBHSCORE_GPWRDN_DISCONNECTDETECT_DISABLED (0x0UL) /*!< (unspecified)                                                */
88552   #define USBHSCORE_GPWRDN_DISCONNECTDETECT_ENABLED (0x1UL) /*!< (unspecified)                                                 */
88553 
88554 /* DISCONNECTDETECTMSK @Bit 12 : DisconnectDetectMsk */
88555   #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Pos (12UL) /*!< Position of DISCONNECTDETECTMSK field.                          */
88556   #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Pos) /*!< Bit mask of
88557                                                                             DISCONNECTDETECTMSK field.*/
88558   #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Min (0x0UL) /*!< Min enumerator value of DISCONNECTDETECTMSK field.             */
88559   #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_Max (0x1UL) /*!< Max enumerator value of DISCONNECTDETECTMSK field.             */
88560   #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_NOMASK (0x0UL) /*!< (unspecified)                                               */
88561   #define USBHSCORE_GPWRDN_DISCONNECTDETECTMSK_MASK (0x1UL) /*!< (unspecified)                                                 */
88562 
88563 /* CONNECTDET @Bit 13 : ConnectDet */
88564   #define USBHSCORE_GPWRDN_CONNECTDET_Pos (13UL)     /*!< Position of CONNECTDET field.                                        */
88565   #define USBHSCORE_GPWRDN_CONNECTDET_Msk (0x1UL << USBHSCORE_GPWRDN_CONNECTDET_Pos) /*!< Bit mask of CONNECTDET field.        */
88566   #define USBHSCORE_GPWRDN_CONNECTDET_Min (0x0UL)    /*!< Min enumerator value of CONNECTDET field.                            */
88567   #define USBHSCORE_GPWRDN_CONNECTDET_Max (0x1UL)    /*!< Max enumerator value of CONNECTDET field.                            */
88568   #define USBHSCORE_GPWRDN_CONNECTDET_DISABLED (0x0UL) /*!< (unspecified)                                                      */
88569   #define USBHSCORE_GPWRDN_CONNECTDET_ENABLED (0x1UL) /*!< (unspecified)                                                       */
88570 
88571 /* CONNDETMSK @Bit 14 : ConnDetMsk */
88572   #define USBHSCORE_GPWRDN_CONNDETMSK_Pos (14UL)     /*!< Position of CONNDETMSK field.                                        */
88573   #define USBHSCORE_GPWRDN_CONNDETMSK_Msk (0x1UL << USBHSCORE_GPWRDN_CONNDETMSK_Pos) /*!< Bit mask of CONNDETMSK field.        */
88574   #define USBHSCORE_GPWRDN_CONNDETMSK_Min (0x0UL)    /*!< Min enumerator value of CONNDETMSK field.                            */
88575   #define USBHSCORE_GPWRDN_CONNDETMSK_Max (0x1UL)    /*!< Max enumerator value of CONNDETMSK field.                            */
88576   #define USBHSCORE_GPWRDN_CONNDETMSK_NOMASK (0x0UL) /*!< (unspecified)                                                        */
88577   #define USBHSCORE_GPWRDN_CONNDETMSK_MASK (0x1UL)   /*!< (unspecified)                                                        */
88578 
88579 /* SRPDETECT @Bit 15 : SRPDetect */
88580   #define USBHSCORE_GPWRDN_SRPDETECT_Pos (15UL)      /*!< Position of SRPDETECT field.                                         */
88581   #define USBHSCORE_GPWRDN_SRPDETECT_Msk (0x1UL << USBHSCORE_GPWRDN_SRPDETECT_Pos) /*!< Bit mask of SRPDETECT field.           */
88582   #define USBHSCORE_GPWRDN_SRPDETECT_Min (0x0UL)     /*!< Min enumerator value of SRPDETECT field.                             */
88583   #define USBHSCORE_GPWRDN_SRPDETECT_Max (0x1UL)     /*!< Max enumerator value of SRPDETECT field.                             */
88584   #define USBHSCORE_GPWRDN_SRPDETECT_DISABLED (0x0UL) /*!< (unspecified)                                                       */
88585   #define USBHSCORE_GPWRDN_SRPDETECT_ENABLED (0x1UL) /*!< (unspecified)                                                        */
88586 
88587 /* SRPDETECTMSK @Bit 16 : SRPDetectMsk */
88588   #define USBHSCORE_GPWRDN_SRPDETECTMSK_Pos (16UL)   /*!< Position of SRPDETECTMSK field.                                      */
88589   #define USBHSCORE_GPWRDN_SRPDETECTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_SRPDETECTMSK_Pos) /*!< Bit mask of SRPDETECTMSK field.  */
88590   #define USBHSCORE_GPWRDN_SRPDETECTMSK_Min (0x0UL)  /*!< Min enumerator value of SRPDETECTMSK field.                          */
88591   #define USBHSCORE_GPWRDN_SRPDETECTMSK_Max (0x1UL)  /*!< Max enumerator value of SRPDETECTMSK field.                          */
88592   #define USBHSCORE_GPWRDN_SRPDETECTMSK_NOMASK (0x0UL) /*!< (unspecified)                                                      */
88593   #define USBHSCORE_GPWRDN_SRPDETECTMSK_MASK (0x1UL) /*!< (unspecified)                                                        */
88594 
88595 /* STSCHNGINT @Bit 17 : Status Change Interrupt (StsChngInt) */
88596   #define USBHSCORE_GPWRDN_STSCHNGINT_Pos (17UL)     /*!< Position of STSCHNGINT field.                                        */
88597   #define USBHSCORE_GPWRDN_STSCHNGINT_Msk (0x1UL << USBHSCORE_GPWRDN_STSCHNGINT_Pos) /*!< Bit mask of STSCHNGINT field.        */
88598   #define USBHSCORE_GPWRDN_STSCHNGINT_Min (0x0UL)    /*!< Min enumerator value of STSCHNGINT field.                            */
88599   #define USBHSCORE_GPWRDN_STSCHNGINT_Max (0x1UL)    /*!< Max enumerator value of STSCHNGINT field.                            */
88600   #define USBHSCORE_GPWRDN_STSCHNGINT_DISABLED (0x0UL) /*!< (unspecified)                                                      */
88601   #define USBHSCORE_GPWRDN_STSCHNGINT_ENABLED (0x1UL) /*!< (unspecified)                                                       */
88602 
88603 /* STSCHNGINTMSK @Bit 18 : StsChngIntMsk */
88604   #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Pos (18UL)  /*!< Position of STSCHNGINTMSK field.                                     */
88605   #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Msk (0x1UL << USBHSCORE_GPWRDN_STSCHNGINTMSK_Pos) /*!< Bit mask of STSCHNGINTMSK
88606                                                                             field.*/
88607   #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Min (0x0UL) /*!< Min enumerator value of STSCHNGINTMSK field.                         */
88608   #define USBHSCORE_GPWRDN_STSCHNGINTMSK_Max (0x1UL) /*!< Max enumerator value of STSCHNGINTMSK field.                         */
88609   #define USBHSCORE_GPWRDN_STSCHNGINTMSK_NOMASK (0x0UL) /*!< (unspecified)                                                     */
88610   #define USBHSCORE_GPWRDN_STSCHNGINTMSK_MASK (0x1UL) /*!< (unspecified)                                                       */
88611 
88612 /* LINESTATE @Bits 19..20 : LineState */
88613   #define USBHSCORE_GPWRDN_LINESTATE_Pos (19UL)      /*!< Position of LINESTATE field.                                         */
88614   #define USBHSCORE_GPWRDN_LINESTATE_Msk (0x3UL << USBHSCORE_GPWRDN_LINESTATE_Pos) /*!< Bit mask of LINESTATE field.           */
88615   #define USBHSCORE_GPWRDN_LINESTATE_Min (0x0UL)     /*!< Min enumerator value of LINESTATE field.                             */
88616   #define USBHSCORE_GPWRDN_LINESTATE_Max (0x3UL)     /*!< Max enumerator value of LINESTATE field.                             */
88617   #define USBHSCORE_GPWRDN_LINESTATE_LS1 (0x0UL)     /*!< (unspecified)                                                        */
88618   #define USBHSCORE_GPWRDN_LINESTATE_LS2 (0x1UL)     /*!< (unspecified)                                                        */
88619   #define USBHSCORE_GPWRDN_LINESTATE_LS3 (0x2UL)     /*!< (unspecified)                                                        */
88620   #define USBHSCORE_GPWRDN_LINESTATE_LS4 (0x3UL)     /*!< (unspecified)                                                        */
88621 
88622 /* IDDIG @Bit 21 : This bit indicates the status of the signal IDDIG. */
88623   #define USBHSCORE_GPWRDN_IDDIG_Pos (21UL)          /*!< Position of IDDIG field.                                             */
88624   #define USBHSCORE_GPWRDN_IDDIG_Msk (0x1UL << USBHSCORE_GPWRDN_IDDIG_Pos) /*!< Bit mask of IDDIG field.                       */
88625   #define USBHSCORE_GPWRDN_IDDIG_Min (0x0UL)         /*!< Min enumerator value of IDDIG field.                                 */
88626   #define USBHSCORE_GPWRDN_IDDIG_Max (0x1UL)         /*!< Max enumerator value of IDDIG field.                                 */
88627   #define USBHSCORE_GPWRDN_IDDIG_DISABLED (0x0UL)    /*!< (unspecified)                                                        */
88628   #define USBHSCORE_GPWRDN_IDDIG_ENABLED (0x1UL)     /*!< (unspecified)                                                        */
88629 
88630 /* BSESSVLD @Bit 22 : B Session Valid (BSessVld) */
88631   #define USBHSCORE_GPWRDN_BSESSVLD_Pos (22UL)       /*!< Position of BSESSVLD field.                                          */
88632   #define USBHSCORE_GPWRDN_BSESSVLD_Msk (0x1UL << USBHSCORE_GPWRDN_BSESSVLD_Pos) /*!< Bit mask of BSESSVLD field.              */
88633   #define USBHSCORE_GPWRDN_BSESSVLD_Min (0x0UL)      /*!< Min enumerator value of BSESSVLD field.                              */
88634   #define USBHSCORE_GPWRDN_BSESSVLD_Max (0x1UL)      /*!< Max enumerator value of BSESSVLD field.                              */
88635   #define USBHSCORE_GPWRDN_BSESSVLD_NOTVALID (0x0UL) /*!< (unspecified)                                                        */
88636   #define USBHSCORE_GPWRDN_BSESSVLD_VALID (0x1UL)    /*!< (unspecified)                                                        */
88637 
88638 /* MULTVALIDBC @Bits 24..28 : MultValIdBC */
88639   #define USBHSCORE_GPWRDN_MULTVALIDBC_Pos (24UL)    /*!< Position of MULTVALIDBC field.                                       */
88640   #define USBHSCORE_GPWRDN_MULTVALIDBC_Msk (0x1FUL << USBHSCORE_GPWRDN_MULTVALIDBC_Pos) /*!< Bit mask of MULTVALIDBC field.    */
88641   #define USBHSCORE_GPWRDN_MULTVALIDBC_Min (0x0UL)   /*!< Min enumerator value of MULTVALIDBC field.                           */
88642   #define USBHSCORE_GPWRDN_MULTVALIDBC_Max (0x1FUL)  /*!< Max enumerator value of MULTVALIDBC field.                           */
88643   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_0 (0x00UL) /*!< (unspecified)                                                       */
88644   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_C (0x01UL) /*!< (unspecified)                                                       */
88645   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_B (0x02UL) /*!< (unspecified)                                                       */
88646   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_A (0x04UL) /*!< (unspecified)                                                       */
88647   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_GND (0x08UL) /*!< (unspecified)                                                     */
88648   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_A_RID_GND (0x0CUL) /*!< (unspecified)                                               */
88649   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_FLOAT (0x10UL) /*!< (unspecified)                                                   */
88650   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_C_RID_FLOAT (0x11UL) /*!< (unspecified)                                             */
88651   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_B_RID_FLOAT (0x12UL) /*!< (unspecified)                                             */
88652   #define USBHSCORE_GPWRDN_MULTVALIDBC_RID_1 (0x1FUL) /*!< (unspecified)                                                       */
88653 
88654 
88655 /* USBHSCORE_GDFIFOCFG: Global DFIFO Configuration Register */
88656   #define USBHSCORE_GDFIFOCFG_ResetValue (0x0BEA0C00UL) /*!< Reset value of GDFIFOCFG register.                                */
88657 
88658 /* GDFIFOCFG @Bits 0..15 : GDFIFOCfg */
88659   #define USBHSCORE_GDFIFOCFG_GDFIFOCFG_Pos (0UL)    /*!< Position of GDFIFOCFG field.                                         */
88660   #define USBHSCORE_GDFIFOCFG_GDFIFOCFG_Msk (0xFFFFUL << USBHSCORE_GDFIFOCFG_GDFIFOCFG_Pos) /*!< Bit mask of GDFIFOCFG field.  */
88661 
88662 /* EPINFOBASEADDR @Bits 16..31 : EPInfoBaseAddr */
88663   #define USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Pos (16UL) /*!< Position of EPINFOBASEADDR field.                                 */
88664   #define USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Msk (0xFFFFUL << USBHSCORE_GDFIFOCFG_EPINFOBASEADDR_Pos) /*!< Bit mask of
88665                                                                             EPINFOBASEADDR field.*/
88666 
88667 
88668 /* USBHSCORE_GINTMSK2: Interrupt Mask Register 2 */
88669   #define USBHSCORE_GINTMSK2_ResetValue (0x00000000UL) /*!< Reset value of GINTMSK2 register.                                  */
88670 
88671 /* GINTMSK2 @Bits 0..31 : (unspecified) */
88672   #define USBHSCORE_GINTMSK2_GINTMSK2_Pos (0UL)      /*!< Position of GINTMSK2 field.                                          */
88673   #define USBHSCORE_GINTMSK2_GINTMSK2_Msk (0xFFFFFFFFUL << USBHSCORE_GINTMSK2_GINTMSK2_Pos) /*!< Bit mask of GINTMSK2 field.   */
88674 
88675 
88676 /* USBHSCORE_GINTSTS2: Interrupt Register 2 */
88677   #define USBHSCORE_GINTSTS2_ResetValue (0x00000000UL) /*!< Reset value of GINTSTS2 register.                                  */
88678 
88679 /* GINTSTS2 @Bits 0..31 : (unspecified) */
88680   #define USBHSCORE_GINTSTS2_GINTSTS2_Pos (0UL)      /*!< Position of GINTSTS2 field.                                          */
88681   #define USBHSCORE_GINTSTS2_GINTSTS2_Msk (0xFFFFFFFFUL << USBHSCORE_GINTSTS2_GINTSTS2_Pos) /*!< Bit mask of GINTSTS2 field.   */
88682 
88683 
88684 /* USBHSCORE_HPTXFSIZ: Host Periodic Transmit FIFO Size Register */
88685   #define USBHSCORE_HPTXFSIZ_ResetValue (0x04000424UL) /*!< Reset value of HPTXFSIZ register.                                  */
88686 
88687 /* PTXFSTADDR @Bits 0..10 : Host Periodic TxFIFO Start Address (PTxFStAddr) */
88688   #define USBHSCORE_HPTXFSIZ_PTXFSTADDR_Pos (0UL)    /*!< Position of PTXFSTADDR field.                                        */
88689   #define USBHSCORE_HPTXFSIZ_PTXFSTADDR_Msk (0x7FFUL << USBHSCORE_HPTXFSIZ_PTXFSTADDR_Pos) /*!< Bit mask of PTXFSTADDR field.  */
88690 
88691 /* PTXFSIZE @Bits 16..26 : Host Periodic TxFIFO Depth (PTxFSize) */
88692   #define USBHSCORE_HPTXFSIZ_PTXFSIZE_Pos (16UL)     /*!< Position of PTXFSIZE field.                                          */
88693   #define USBHSCORE_HPTXFSIZ_PTXFSIZE_Msk (0x7FFUL << USBHSCORE_HPTXFSIZ_PTXFSIZE_Pos) /*!< Bit mask of PTXFSIZE field.        */
88694 
88695 
88696 /* USBHSCORE_DIEPTXF1: Device IN Endpoint Transmit FIFO Size Register 1 */
88697   #define USBHSCORE_DIEPTXF1_ResetValue (0x02000424UL) /*!< Reset value of DIEPTXF1 register.                                  */
88698 
88699 /* INEPNTXFSTADDR @Bits 0..10 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */
88700   #define USBHSCORE_DIEPTXF1_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field.                                   */
88701   #define USBHSCORE_DIEPTXF1_INEPNTXFSTADDR_Msk (0x7FFUL << USBHSCORE_DIEPTXF1_INEPNTXFSTADDR_Pos) /*!< Bit mask of
88702                                                                             INEPNTXFSTADDR field.*/
88703 
88704 /* INEPNTXFDEP @Bits 16..25 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */
88705   #define USBHSCORE_DIEPTXF1_INEPNTXFDEP_Pos (16UL)  /*!< Position of INEPNTXFDEP field.                                       */
88706   #define USBHSCORE_DIEPTXF1_INEPNTXFDEP_Msk (0x3FFUL << USBHSCORE_DIEPTXF1_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP
88707                                                                             field.*/
88708 
88709 
88710 /* USBHSCORE_DIEPTXF2: Device IN Endpoint Transmit FIFO Size Register 2 */
88711   #define USBHSCORE_DIEPTXF2_ResetValue (0x02000624UL) /*!< Reset value of DIEPTXF2 register.                                  */
88712 
88713 /* INEPNTXFSTADDR @Bits 0..10 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */
88714   #define USBHSCORE_DIEPTXF2_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field.                                   */
88715   #define USBHSCORE_DIEPTXF2_INEPNTXFSTADDR_Msk (0x7FFUL << USBHSCORE_DIEPTXF2_INEPNTXFSTADDR_Pos) /*!< Bit mask of
88716                                                                             INEPNTXFSTADDR field.*/
88717 
88718 /* INEPNTXFDEP @Bits 16..25 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */
88719   #define USBHSCORE_DIEPTXF2_INEPNTXFDEP_Pos (16UL)  /*!< Position of INEPNTXFDEP field.                                       */
88720   #define USBHSCORE_DIEPTXF2_INEPNTXFDEP_Msk (0x3FFUL << USBHSCORE_DIEPTXF2_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP
88721                                                                             field.*/
88722 
88723 
88724 /* USBHSCORE_DIEPTXF3: Device IN Endpoint Transmit FIFO Size Register 3 */
88725   #define USBHSCORE_DIEPTXF3_ResetValue (0x02000824UL) /*!< Reset value of DIEPTXF3 register.                                  */
88726 
88727 /* INEPNTXFSTADDR @Bits 0..11 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */
88728   #define USBHSCORE_DIEPTXF3_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field.                                   */
88729   #define USBHSCORE_DIEPTXF3_INEPNTXFSTADDR_Msk (0xFFFUL << USBHSCORE_DIEPTXF3_INEPNTXFSTADDR_Pos) /*!< Bit mask of
88730                                                                             INEPNTXFSTADDR field.*/
88731 
88732 /* INEPNTXFDEP @Bits 16..25 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */
88733   #define USBHSCORE_DIEPTXF3_INEPNTXFDEP_Pos (16UL)  /*!< Position of INEPNTXFDEP field.                                       */
88734   #define USBHSCORE_DIEPTXF3_INEPNTXFDEP_Msk (0x3FFUL << USBHSCORE_DIEPTXF3_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP
88735                                                                             field.*/
88736 
88737 
88738 /* USBHSCORE_DIEPTXF4: Device IN Endpoint Transmit FIFO Size Register 4 */
88739   #define USBHSCORE_DIEPTXF4_ResetValue (0x02000A24UL) /*!< Reset value of DIEPTXF4 register.                                  */
88740 
88741 /* INEPNTXFSTADDR @Bits 0..11 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */
88742   #define USBHSCORE_DIEPTXF4_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field.                                   */
88743   #define USBHSCORE_DIEPTXF4_INEPNTXFSTADDR_Msk (0xFFFUL << USBHSCORE_DIEPTXF4_INEPNTXFSTADDR_Pos) /*!< Bit mask of
88744                                                                             INEPNTXFSTADDR field.*/
88745 
88746 /* INEPNTXFDEP @Bits 16..25 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */
88747   #define USBHSCORE_DIEPTXF4_INEPNTXFDEP_Pos (16UL)  /*!< Position of INEPNTXFDEP field.                                       */
88748   #define USBHSCORE_DIEPTXF4_INEPNTXFDEP_Msk (0x3FFUL << USBHSCORE_DIEPTXF4_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP
88749                                                                             field.*/
88750 
88751 
88752 /* USBHSCORE_DIEPTXF5: Device IN Endpoint Transmit FIFO Size Register 5 */
88753   #define USBHSCORE_DIEPTXF5_ResetValue (0x02000C24UL) /*!< Reset value of DIEPTXF5 register.                                  */
88754 
88755 /* INEPNTXFSTADDR @Bits 0..11 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */
88756   #define USBHSCORE_DIEPTXF5_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field.                                   */
88757   #define USBHSCORE_DIEPTXF5_INEPNTXFSTADDR_Msk (0xFFFUL << USBHSCORE_DIEPTXF5_INEPNTXFSTADDR_Pos) /*!< Bit mask of
88758                                                                             INEPNTXFSTADDR field.*/
88759 
88760 /* INEPNTXFDEP @Bits 16..25 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */
88761   #define USBHSCORE_DIEPTXF5_INEPNTXFDEP_Pos (16UL)  /*!< Position of INEPNTXFDEP field.                                       */
88762   #define USBHSCORE_DIEPTXF5_INEPNTXFDEP_Msk (0x3FFUL << USBHSCORE_DIEPTXF5_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP
88763                                                                             field.*/
88764 
88765 
88766 /* USBHSCORE_DIEPTXF6: Device IN Endpoint Transmit FIFO Size Register 6 */
88767   #define USBHSCORE_DIEPTXF6_ResetValue (0x02000E24UL) /*!< Reset value of DIEPTXF6 register.                                  */
88768 
88769 /* INEPNTXFSTADDR @Bits 0..11 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */
88770   #define USBHSCORE_DIEPTXF6_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field.                                   */
88771   #define USBHSCORE_DIEPTXF6_INEPNTXFSTADDR_Msk (0xFFFUL << USBHSCORE_DIEPTXF6_INEPNTXFSTADDR_Pos) /*!< Bit mask of
88772                                                                             INEPNTXFSTADDR field.*/
88773 
88774 /* INEPNTXFDEP @Bits 16..25 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */
88775   #define USBHSCORE_DIEPTXF6_INEPNTXFDEP_Pos (16UL)  /*!< Position of INEPNTXFDEP field.                                       */
88776   #define USBHSCORE_DIEPTXF6_INEPNTXFDEP_Msk (0x3FFUL << USBHSCORE_DIEPTXF6_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP
88777                                                                             field.*/
88778 
88779 
88780 /* USBHSCORE_DIEPTXF7: Device IN Endpoint Transmit FIFO Size Register 7 */
88781   #define USBHSCORE_DIEPTXF7_ResetValue (0x02001024UL) /*!< Reset value of DIEPTXF7 register.                                  */
88782 
88783 /* INEPNTXFSTADDR @Bits 0..12 : IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr) */
88784   #define USBHSCORE_DIEPTXF7_INEPNTXFSTADDR_Pos (0UL) /*!< Position of INEPNTXFSTADDR field.                                   */
88785   #define USBHSCORE_DIEPTXF7_INEPNTXFSTADDR_Msk (0x1FFFUL << USBHSCORE_DIEPTXF7_INEPNTXFSTADDR_Pos) /*!< Bit mask of
88786                                                                             INEPNTXFSTADDR field.*/
88787 
88788 /* INEPNTXFDEP @Bits 16..25 : IN Endpoint TxFIFO Depth (INEPnTxFDep) */
88789   #define USBHSCORE_DIEPTXF7_INEPNTXFDEP_Pos (16UL)  /*!< Position of INEPNTXFDEP field.                                       */
88790   #define USBHSCORE_DIEPTXF7_INEPNTXFDEP_Msk (0x3FFUL << USBHSCORE_DIEPTXF7_INEPNTXFDEP_Pos) /*!< Bit mask of INEPNTXFDEP
88791                                                                             field.*/
88792 
88793 
88794 /* USBHSCORE_HCFG: Host Configuration Register */
88795   #define USBHSCORE_HCFG_ResetValue (0x00000200UL)   /*!< Reset value of HCFG register.                                        */
88796 
88797 /* FSLSPCLKSEL @Bits 0..1 : FS/LS PHY Clock Select (FSLSPclkSel) */
88798   #define USBHSCORE_HCFG_FSLSPCLKSEL_Pos (0UL)       /*!< Position of FSLSPCLKSEL field.                                       */
88799   #define USBHSCORE_HCFG_FSLSPCLKSEL_Msk (0x3UL << USBHSCORE_HCFG_FSLSPCLKSEL_Pos) /*!< Bit mask of FSLSPCLKSEL field.         */
88800   #define USBHSCORE_HCFG_FSLSPCLKSEL_Min (0x0UL)     /*!< Min enumerator value of FSLSPCLKSEL field.                           */
88801   #define USBHSCORE_HCFG_FSLSPCLKSEL_Max (0x2UL)     /*!< Max enumerator value of FSLSPCLKSEL field.                           */
88802   #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK3060 (0x0UL) /*!< (unspecified)                                                        */
88803   #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK48 (0x1UL)   /*!< (unspecified)                                                        */
88804   #define USBHSCORE_HCFG_FSLSPCLKSEL_CLK6 (0x2UL)    /*!< (unspecified)                                                        */
88805 
88806 /* FSLSSUPP @Bit 2 : FS- and LS-Only Support (FSLSSupp) */
88807   #define USBHSCORE_HCFG_FSLSSUPP_Pos (2UL)          /*!< Position of FSLSSUPP field.                                          */
88808   #define USBHSCORE_HCFG_FSLSSUPP_Msk (0x1UL << USBHSCORE_HCFG_FSLSSUPP_Pos) /*!< Bit mask of FSLSSUPP field.                  */
88809   #define USBHSCORE_HCFG_FSLSSUPP_Min (0x0UL)        /*!< Min enumerator value of FSLSSUPP field.                              */
88810   #define USBHSCORE_HCFG_FSLSSUPP_Max (0x1UL)        /*!< Max enumerator value of FSLSSUPP field.                              */
88811   #define USBHSCORE_HCFG_FSLSSUPP_HSFSLS (0x0UL)     /*!< (unspecified)                                                        */
88812   #define USBHSCORE_HCFG_FSLSSUPP_FSLS (0x1UL)       /*!< (unspecified)                                                        */
88813 
88814 /* ENA32KHZS @Bit 7 : Enable 32 KHz Suspend mode (Ena32KHzS) */
88815   #define USBHSCORE_HCFG_ENA32KHZS_Pos (7UL)         /*!< Position of ENA32KHZS field.                                         */
88816   #define USBHSCORE_HCFG_ENA32KHZS_Msk (0x1UL << USBHSCORE_HCFG_ENA32KHZS_Pos) /*!< Bit mask of ENA32KHZS field.               */
88817   #define USBHSCORE_HCFG_ENA32KHZS_Min (0x0UL)       /*!< Min enumerator value of ENA32KHZS field.                             */
88818   #define USBHSCORE_HCFG_ENA32KHZS_Max (0x1UL)       /*!< Max enumerator value of ENA32KHZS field.                             */
88819   #define USBHSCORE_HCFG_ENA32KHZS_DISABLED (0x0UL)  /*!< (unspecified)                                                        */
88820   #define USBHSCORE_HCFG_ENA32KHZS_ENABLED (0x1UL)   /*!< (unspecified)                                                        */
88821 
88822 /* RESVALID @Bits 8..15 : Resume Validation Period (ResValid) */
88823   #define USBHSCORE_HCFG_RESVALID_Pos (8UL)          /*!< Position of RESVALID field.                                          */
88824   #define USBHSCORE_HCFG_RESVALID_Msk (0xFFUL << USBHSCORE_HCFG_RESVALID_Pos) /*!< Bit mask of RESVALID field.                 */
88825 
88826 /* MODECHTIMEN @Bit 31 : Mode Change Ready Timer Enable (ModeChTimEn) */
88827   #define USBHSCORE_HCFG_MODECHTIMEN_Pos (31UL)      /*!< Position of MODECHTIMEN field.                                       */
88828   #define USBHSCORE_HCFG_MODECHTIMEN_Msk (0x1UL << USBHSCORE_HCFG_MODECHTIMEN_Pos) /*!< Bit mask of MODECHTIMEN field.         */
88829   #define USBHSCORE_HCFG_MODECHTIMEN_Min (0x0UL)     /*!< Min enumerator value of MODECHTIMEN field.                           */
88830   #define USBHSCORE_HCFG_MODECHTIMEN_Max (0x1UL)     /*!< Max enumerator value of MODECHTIMEN field.                           */
88831   #define USBHSCORE_HCFG_MODECHTIMEN_ENABLED (0x0UL) /*!< (unspecified)                                                        */
88832   #define USBHSCORE_HCFG_MODECHTIMEN_DISABLED (0x1UL) /*!< (unspecified)                                                       */
88833 
88834 
88835 /* USBHSCORE_HFIR: Host Frame Interval Register */
88836   #define USBHSCORE_HFIR_ResetValue (0x0000EA60UL)   /*!< Reset value of HFIR register.                                        */
88837 
88838 /* FRINT @Bits 0..15 : Frame Interval (FrInt) */
88839   #define USBHSCORE_HFIR_FRINT_Pos (0UL)             /*!< Position of FRINT field.                                             */
88840   #define USBHSCORE_HFIR_FRINT_Msk (0xFFFFUL << USBHSCORE_HFIR_FRINT_Pos) /*!< Bit mask of FRINT field.                        */
88841 
88842 /* HFIRRLDCTRL @Bit 16 : Reload Control (HFIRRldCtrl) */
88843   #define USBHSCORE_HFIR_HFIRRLDCTRL_Pos (16UL)      /*!< Position of HFIRRLDCTRL field.                                       */
88844   #define USBHSCORE_HFIR_HFIRRLDCTRL_Msk (0x1UL << USBHSCORE_HFIR_HFIRRLDCTRL_Pos) /*!< Bit mask of HFIRRLDCTRL field.         */
88845   #define USBHSCORE_HFIR_HFIRRLDCTRL_Min (0x0UL)     /*!< Min enumerator value of HFIRRLDCTRL field.                           */
88846   #define USBHSCORE_HFIR_HFIRRLDCTRL_Max (0x1UL)     /*!< Max enumerator value of HFIRRLDCTRL field.                           */
88847   #define USBHSCORE_HFIR_HFIRRLDCTRL_DISABLED (0x0UL) /*!< (unspecified)                                                       */
88848   #define USBHSCORE_HFIR_HFIRRLDCTRL_ENABLED (0x1UL) /*!< (unspecified)                                                        */
88849 
88850 
88851 /* USBHSCORE_HFNUM: Host Frame Number/Frame Time Remaining Register */
88852   #define USBHSCORE_HFNUM_ResetValue (0x00003FFFUL)  /*!< Reset value of HFNUM register.                                       */
88853 
88854 /* FRNUM @Bits 0..15 : Frame Number (FrNum) */
88855   #define USBHSCORE_HFNUM_FRNUM_Pos (0UL)            /*!< Position of FRNUM field.                                             */
88856   #define USBHSCORE_HFNUM_FRNUM_Msk (0xFFFFUL << USBHSCORE_HFNUM_FRNUM_Pos) /*!< Bit mask of FRNUM field.                      */
88857   #define USBHSCORE_HFNUM_FRNUM_Min (0x0UL)          /*!< Min enumerator value of FRNUM field.                                 */
88858   #define USBHSCORE_HFNUM_FRNUM_Max (0x1UL)          /*!< Max enumerator value of FRNUM field.                                 */
88859   #define USBHSCORE_HFNUM_FRNUM_INACTIVE (0x0000UL)  /*!< (unspecified)                                                        */
88860   #define USBHSCORE_HFNUM_FRNUM_ACTIVE (0x0001UL)    /*!< (unspecified)                                                        */
88861 
88862 /* FRREM @Bits 16..31 : Frame Time Remaining (FrRem) */
88863   #define USBHSCORE_HFNUM_FRREM_Pos (16UL)           /*!< Position of FRREM field.                                             */
88864   #define USBHSCORE_HFNUM_FRREM_Msk (0xFFFFUL << USBHSCORE_HFNUM_FRREM_Pos) /*!< Bit mask of FRREM field.                      */
88865 
88866 
88867 /* USBHSCORE_HAINT: Host All Channels Interrupt Register */
88868   #define USBHSCORE_HAINT_ResetValue (0x00000000UL)  /*!< Reset value of HAINT register.                                       */
88869 
88870 /* HAINT @Bits 0..15 : Channel Interrupt for channel no. */
88871   #define USBHSCORE_HAINT_HAINT_Pos (0UL)            /*!< Position of HAINT field.                                             */
88872   #define USBHSCORE_HAINT_HAINT_Msk (0xFFFFUL << USBHSCORE_HAINT_HAINT_Pos) /*!< Bit mask of HAINT field.                      */
88873   #define USBHSCORE_HAINT_HAINT_Min (0x0UL)          /*!< Min enumerator value of HAINT field.                                 */
88874   #define USBHSCORE_HAINT_HAINT_Max (0x1UL)          /*!< Max enumerator value of HAINT field.                                 */
88875   #define USBHSCORE_HAINT_HAINT_INACTIVE (0x0000UL)  /*!< (unspecified)                                                        */
88876   #define USBHSCORE_HAINT_HAINT_ACTIVE (0x0001UL)    /*!< (unspecified)                                                        */
88877 
88878 
88879 /* USBHSCORE_HAINTMSK: Host All Channels Interrupt Mask Register */
88880   #define USBHSCORE_HAINTMSK_ResetValue (0x00000000UL) /*!< Reset value of HAINTMSK register.                                  */
88881 
88882 /* HAINTMSK @Bits 0..15 : Channel Interrupt Mask (HAINTMsk) */
88883   #define USBHSCORE_HAINTMSK_HAINTMSK_Pos (0UL)      /*!< Position of HAINTMSK field.                                          */
88884   #define USBHSCORE_HAINTMSK_HAINTMSK_Msk (0xFFFFUL << USBHSCORE_HAINTMSK_HAINTMSK_Pos) /*!< Bit mask of HAINTMSK field.       */
88885   #define USBHSCORE_HAINTMSK_HAINTMSK_Min (0x0UL)    /*!< Min enumerator value of HAINTMSK field.                              */
88886   #define USBHSCORE_HAINTMSK_HAINTMSK_Max (0x1UL)    /*!< Max enumerator value of HAINTMSK field.                              */
88887   #define USBHSCORE_HAINTMSK_HAINTMSK_UNMASK (0x0000UL) /*!< (unspecified)                                                     */
88888   #define USBHSCORE_HAINTMSK_HAINTMSK_MASK (0x0001UL) /*!< (unspecified)                                                       */
88889 
88890 
88891 /* USBHSCORE_HPRT: Host Port Control and Status Register */
88892   #define USBHSCORE_HPRT_ResetValue (0x00000000UL)   /*!< Reset value of HPRT register.                                        */
88893 
88894 /* PRTCONNSTS @Bit 0 : Port Connect Status (PrtConnSts) */
88895   #define USBHSCORE_HPRT_PRTCONNSTS_Pos (0UL)        /*!< Position of PRTCONNSTS field.                                        */
88896   #define USBHSCORE_HPRT_PRTCONNSTS_Msk (0x1UL << USBHSCORE_HPRT_PRTCONNSTS_Pos) /*!< Bit mask of PRTCONNSTS field.            */
88897   #define USBHSCORE_HPRT_PRTCONNSTS_Min (0x0UL)      /*!< Min enumerator value of PRTCONNSTS field.                            */
88898   #define USBHSCORE_HPRT_PRTCONNSTS_Max (0x1UL)      /*!< Max enumerator value of PRTCONNSTS field.                            */
88899   #define USBHSCORE_HPRT_PRTCONNSTS_NOTATTACHED (0x0UL) /*!< (unspecified)                                                     */
88900   #define USBHSCORE_HPRT_PRTCONNSTS_ATTACHED (0x1UL) /*!< (unspecified)                                                        */
88901 
88902 /* PRTCONNDET @Bit 1 : Port Connect Detected (PrtConnDet) */
88903   #define USBHSCORE_HPRT_PRTCONNDET_Pos (1UL)        /*!< Position of PRTCONNDET field.                                        */
88904   #define USBHSCORE_HPRT_PRTCONNDET_Msk (0x1UL << USBHSCORE_HPRT_PRTCONNDET_Pos) /*!< Bit mask of PRTCONNDET field.            */
88905   #define USBHSCORE_HPRT_PRTCONNDET_Min (0x0UL)      /*!< Min enumerator value of PRTCONNDET field.                            */
88906   #define USBHSCORE_HPRT_PRTCONNDET_Max (0x1UL)      /*!< Max enumerator value of PRTCONNDET field.                            */
88907   #define USBHSCORE_HPRT_PRTCONNDET_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
88908   #define USBHSCORE_HPRT_PRTCONNDET_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
88909 
88910 /* PRTENA @Bit 2 : Port Enable (PrtEna) */
88911   #define USBHSCORE_HPRT_PRTENA_Pos (2UL)            /*!< Position of PRTENA field.                                            */
88912   #define USBHSCORE_HPRT_PRTENA_Msk (0x1UL << USBHSCORE_HPRT_PRTENA_Pos) /*!< Bit mask of PRTENA field.                        */
88913   #define USBHSCORE_HPRT_PRTENA_Min (0x0UL)          /*!< Min enumerator value of PRTENA field.                                */
88914   #define USBHSCORE_HPRT_PRTENA_Max (0x1UL)          /*!< Max enumerator value of PRTENA field.                                */
88915   #define USBHSCORE_HPRT_PRTENA_DISABLED (0x0UL)     /*!< (unspecified)                                                        */
88916   #define USBHSCORE_HPRT_PRTENA_ENABLED (0x1UL)      /*!< (unspecified)                                                        */
88917 
88918 /* PRTENCHNG @Bit 3 : Port Enable/Disable Change (PrtEnChng) */
88919   #define USBHSCORE_HPRT_PRTENCHNG_Pos (3UL)         /*!< Position of PRTENCHNG field.                                         */
88920   #define USBHSCORE_HPRT_PRTENCHNG_Msk (0x1UL << USBHSCORE_HPRT_PRTENCHNG_Pos) /*!< Bit mask of PRTENCHNG field.               */
88921   #define USBHSCORE_HPRT_PRTENCHNG_Min (0x0UL)       /*!< Min enumerator value of PRTENCHNG field.                             */
88922   #define USBHSCORE_HPRT_PRTENCHNG_Max (0x1UL)       /*!< Max enumerator value of PRTENCHNG field.                             */
88923   #define USBHSCORE_HPRT_PRTENCHNG_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
88924   #define USBHSCORE_HPRT_PRTENCHNG_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
88925 
88926 /* PRTOVRCURRACT @Bit 4 : Port Overcurrent Active (PrtOvrCurrAct) */
88927   #define USBHSCORE_HPRT_PRTOVRCURRACT_Pos (4UL)     /*!< Position of PRTOVRCURRACT field.                                     */
88928   #define USBHSCORE_HPRT_PRTOVRCURRACT_Msk (0x1UL << USBHSCORE_HPRT_PRTOVRCURRACT_Pos) /*!< Bit mask of PRTOVRCURRACT field.   */
88929   #define USBHSCORE_HPRT_PRTOVRCURRACT_Min (0x0UL)   /*!< Min enumerator value of PRTOVRCURRACT field.                         */
88930   #define USBHSCORE_HPRT_PRTOVRCURRACT_Max (0x1UL)   /*!< Max enumerator value of PRTOVRCURRACT field.                         */
88931   #define USBHSCORE_HPRT_PRTOVRCURRACT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
88932   #define USBHSCORE_HPRT_PRTOVRCURRACT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
88933 
88934 /* PRTOVRCURRCHNG @Bit 5 : Port Overcurrent Change (PrtOvrCurrChng) */
88935   #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Pos (5UL)    /*!< Position of PRTOVRCURRCHNG field.                                    */
88936   #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Msk (0x1UL << USBHSCORE_HPRT_PRTOVRCURRCHNG_Pos) /*!< Bit mask of PRTOVRCURRCHNG field.*/
88937   #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Min (0x0UL)  /*!< Min enumerator value of PRTOVRCURRCHNG field.                        */
88938   #define USBHSCORE_HPRT_PRTOVRCURRCHNG_Max (0x1UL)  /*!< Max enumerator value of PRTOVRCURRCHNG field.                        */
88939   #define USBHSCORE_HPRT_PRTOVRCURRCHNG_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
88940   #define USBHSCORE_HPRT_PRTOVRCURRCHNG_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
88941 
88942 /* PRTRES @Bit 6 : Port Resume (PrtRes) */
88943   #define USBHSCORE_HPRT_PRTRES_Pos (6UL)            /*!< Position of PRTRES field.                                            */
88944   #define USBHSCORE_HPRT_PRTRES_Msk (0x1UL << USBHSCORE_HPRT_PRTRES_Pos) /*!< Bit mask of PRTRES field.                        */
88945   #define USBHSCORE_HPRT_PRTRES_Min (0x0UL)          /*!< Min enumerator value of PRTRES field.                                */
88946   #define USBHSCORE_HPRT_PRTRES_Max (0x1UL)          /*!< Max enumerator value of PRTRES field.                                */
88947   #define USBHSCORE_HPRT_PRTRES_NORESUME (0x0UL)     /*!< (unspecified)                                                        */
88948   #define USBHSCORE_HPRT_PRTRES_RESUME (0x1UL)       /*!< (unspecified)                                                        */
88949 
88950 /* PRTSUSP @Bit 7 : Port Suspend (PrtSusp) */
88951   #define USBHSCORE_HPRT_PRTSUSP_Pos (7UL)           /*!< Position of PRTSUSP field.                                           */
88952   #define USBHSCORE_HPRT_PRTSUSP_Msk (0x1UL << USBHSCORE_HPRT_PRTSUSP_Pos) /*!< Bit mask of PRTSUSP field.                     */
88953   #define USBHSCORE_HPRT_PRTSUSP_Min (0x0UL)         /*!< Min enumerator value of PRTSUSP field.                               */
88954   #define USBHSCORE_HPRT_PRTSUSP_Max (0x1UL)         /*!< Max enumerator value of PRTSUSP field.                               */
88955   #define USBHSCORE_HPRT_PRTSUSP_INACTIVE (0x0UL)    /*!< (unspecified)                                                        */
88956   #define USBHSCORE_HPRT_PRTSUSP_ACTIVE (0x1UL)      /*!< (unspecified)                                                        */
88957 
88958 /* PRTRST @Bit 8 : Port Reset (PrtRst) */
88959   #define USBHSCORE_HPRT_PRTRST_Pos (8UL)            /*!< Position of PRTRST field.                                            */
88960   #define USBHSCORE_HPRT_PRTRST_Msk (0x1UL << USBHSCORE_HPRT_PRTRST_Pos) /*!< Bit mask of PRTRST field.                        */
88961   #define USBHSCORE_HPRT_PRTRST_Min (0x0UL)          /*!< Min enumerator value of PRTRST field.                                */
88962   #define USBHSCORE_HPRT_PRTRST_Max (0x1UL)          /*!< Max enumerator value of PRTRST field.                                */
88963   #define USBHSCORE_HPRT_PRTRST_DISABLED (0x0UL)     /*!< (unspecified)                                                        */
88964   #define USBHSCORE_HPRT_PRTRST_ENABLED (0x1UL)      /*!< (unspecified)                                                        */
88965 
88966 /* PRTLNSTS @Bits 10..11 : Port Line Status (PrtLnSts) */
88967   #define USBHSCORE_HPRT_PRTLNSTS_Pos (10UL)         /*!< Position of PRTLNSTS field.                                          */
88968   #define USBHSCORE_HPRT_PRTLNSTS_Msk (0x3UL << USBHSCORE_HPRT_PRTLNSTS_Pos) /*!< Bit mask of PRTLNSTS field.                  */
88969   #define USBHSCORE_HPRT_PRTLNSTS_Min (0x1UL)        /*!< Min enumerator value of PRTLNSTS field.                              */
88970   #define USBHSCORE_HPRT_PRTLNSTS_Max (0x2UL)        /*!< Max enumerator value of PRTLNSTS field.                              */
88971   #define USBHSCORE_HPRT_PRTLNSTS_PLUSD (0x1UL)      /*!< (unspecified)                                                        */
88972   #define USBHSCORE_HPRT_PRTLNSTS_MINUSD (0x2UL)     /*!< (unspecified)                                                        */
88973 
88974 /* PRTPWR @Bit 12 : Port Power (PrtPwr) */
88975   #define USBHSCORE_HPRT_PRTPWR_Pos (12UL)           /*!< Position of PRTPWR field.                                            */
88976   #define USBHSCORE_HPRT_PRTPWR_Msk (0x1UL << USBHSCORE_HPRT_PRTPWR_Pos) /*!< Bit mask of PRTPWR field.                        */
88977   #define USBHSCORE_HPRT_PRTPWR_Min (0x0UL)          /*!< Min enumerator value of PRTPWR field.                                */
88978   #define USBHSCORE_HPRT_PRTPWR_Max (0x1UL)          /*!< Max enumerator value of PRTPWR field.                                */
88979   #define USBHSCORE_HPRT_PRTPWR_OFF (0x0UL)          /*!< (unspecified)                                                        */
88980   #define USBHSCORE_HPRT_PRTPWR_ON (0x1UL)           /*!< (unspecified)                                                        */
88981 
88982 /* PRTTSTCTL @Bits 13..16 : Port Test Control (PrtTstCtl) */
88983   #define USBHSCORE_HPRT_PRTTSTCTL_Pos (13UL)        /*!< Position of PRTTSTCTL field.                                         */
88984   #define USBHSCORE_HPRT_PRTTSTCTL_Msk (0xFUL << USBHSCORE_HPRT_PRTTSTCTL_Pos) /*!< Bit mask of PRTTSTCTL field.               */
88985   #define USBHSCORE_HPRT_PRTTSTCTL_Min (0x0UL)       /*!< Min enumerator value of PRTTSTCTL field.                             */
88986   #define USBHSCORE_HPRT_PRTTSTCTL_Max (0x5UL)       /*!< Max enumerator value of PRTTSTCTL field.                             */
88987   #define USBHSCORE_HPRT_PRTTSTCTL_DISABLED (0x0UL)  /*!< (unspecified)                                                        */
88988   #define USBHSCORE_HPRT_PRTTSTCTL_TESTJ (0x1UL)     /*!< (unspecified)                                                        */
88989   #define USBHSCORE_HPRT_PRTTSTCTL_TESTK (0x2UL)     /*!< (unspecified)                                                        */
88990   #define USBHSCORE_HPRT_PRTTSTCTL_TESTSN (0x3UL)    /*!< (unspecified)                                                        */
88991   #define USBHSCORE_HPRT_PRTTSTCTL_TESTPM (0x4UL)    /*!< (unspecified)                                                        */
88992   #define USBHSCORE_HPRT_PRTTSTCTL_TESTFENB (0x5UL)  /*!< (unspecified)                                                        */
88993 
88994 /* PRTSPD @Bits 17..18 : Port Speed (PrtSpd) */
88995   #define USBHSCORE_HPRT_PRTSPD_Pos (17UL)           /*!< Position of PRTSPD field.                                            */
88996   #define USBHSCORE_HPRT_PRTSPD_Msk (0x3UL << USBHSCORE_HPRT_PRTSPD_Pos) /*!< Bit mask of PRTSPD field.                        */
88997   #define USBHSCORE_HPRT_PRTSPD_Min (0x0UL)          /*!< Min enumerator value of PRTSPD field.                                */
88998   #define USBHSCORE_HPRT_PRTSPD_Max (0x2UL)          /*!< Max enumerator value of PRTSPD field.                                */
88999   #define USBHSCORE_HPRT_PRTSPD_HIGHSPD (0x0UL)      /*!< (unspecified)                                                        */
89000   #define USBHSCORE_HPRT_PRTSPD_FULLSPD (0x1UL)      /*!< (unspecified)                                                        */
89001   #define USBHSCORE_HPRT_PRTSPD_LOWSPD (0x2UL)       /*!< (unspecified)                                                        */
89002 
89003 
89004 /* USBHSCORE_DCFG: Device Configuration Register */
89005   #define USBHSCORE_DCFG_ResetValue (0x08020000UL)   /*!< Reset value of DCFG register.                                        */
89006 
89007 /* DEVSPD @Bits 0..1 : Device Speed (DevSpd) */
89008   #define USBHSCORE_DCFG_DEVSPD_Pos (0UL)            /*!< Position of DEVSPD field.                                            */
89009   #define USBHSCORE_DCFG_DEVSPD_Msk (0x3UL << USBHSCORE_DCFG_DEVSPD_Pos) /*!< Bit mask of DEVSPD field.                        */
89010   #define USBHSCORE_DCFG_DEVSPD_Min (0x0UL)          /*!< Min enumerator value of DEVSPD field.                                */
89011   #define USBHSCORE_DCFG_DEVSPD_Max (0x3UL)          /*!< Max enumerator value of DEVSPD field.                                */
89012   #define USBHSCORE_DCFG_DEVSPD_USBHS20 (0x0UL)      /*!< (unspecified)                                                        */
89013   #define USBHSCORE_DCFG_DEVSPD_USBFS20 (0x1UL)      /*!< (unspecified)                                                        */
89014   #define USBHSCORE_DCFG_DEVSPD_USBLS116 (0x2UL)     /*!< (unspecified)                                                        */
89015   #define USBHSCORE_DCFG_DEVSPD_USBFS1148 (0x3UL)    /*!< (unspecified)                                                        */
89016 
89017 /* NZSTSOUTHSHK @Bit 2 : Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) */
89018   #define USBHSCORE_DCFG_NZSTSOUTHSHK_Pos (2UL)      /*!< Position of NZSTSOUTHSHK field.                                      */
89019   #define USBHSCORE_DCFG_NZSTSOUTHSHK_Msk (0x1UL << USBHSCORE_DCFG_NZSTSOUTHSHK_Pos) /*!< Bit mask of NZSTSOUTHSHK field.      */
89020   #define USBHSCORE_DCFG_NZSTSOUTHSHK_Min (0x0UL)    /*!< Min enumerator value of NZSTSOUTHSHK field.                          */
89021   #define USBHSCORE_DCFG_NZSTSOUTHSHK_Max (0x1UL)    /*!< Max enumerator value of NZSTSOUTHSHK field.                          */
89022   #define USBHSCORE_DCFG_NZSTSOUTHSHK_SENDOUT (0x0UL) /*!< (unspecified)                                                       */
89023   #define USBHSCORE_DCFG_NZSTSOUTHSHK_SENDSTALL (0x1UL) /*!< (unspecified)                                                     */
89024 
89025 /* ENA32KHZSUSP @Bit 3 : Enable 32 KHz Suspend mode (Ena32KHzSusp) */
89026   #define USBHSCORE_DCFG_ENA32KHZSUSP_Pos (3UL)      /*!< Position of ENA32KHZSUSP field.                                      */
89027   #define USBHSCORE_DCFG_ENA32KHZSUSP_Msk (0x1UL << USBHSCORE_DCFG_ENA32KHZSUSP_Pos) /*!< Bit mask of ENA32KHZSUSP field.      */
89028   #define USBHSCORE_DCFG_ENA32KHZSUSP_Min (0x0UL)    /*!< Min enumerator value of ENA32KHZSUSP field.                          */
89029   #define USBHSCORE_DCFG_ENA32KHZSUSP_Max (0x1UL)    /*!< Max enumerator value of ENA32KHZSUSP field.                          */
89030   #define USBHSCORE_DCFG_ENA32KHZSUSP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
89031   #define USBHSCORE_DCFG_ENA32KHZSUSP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
89032 
89033 /* DEVADDR @Bits 4..10 : Device Address (DevAddr) */
89034   #define USBHSCORE_DCFG_DEVADDR_Pos (4UL)           /*!< Position of DEVADDR field.                                           */
89035   #define USBHSCORE_DCFG_DEVADDR_Msk (0x7FUL << USBHSCORE_DCFG_DEVADDR_Pos) /*!< Bit mask of DEVADDR field.                    */
89036 
89037 /* PERFRINT @Bits 11..12 : Periodic Frame Interval (PerFrInt) */
89038   #define USBHSCORE_DCFG_PERFRINT_Pos (11UL)         /*!< Position of PERFRINT field.                                          */
89039   #define USBHSCORE_DCFG_PERFRINT_Msk (0x3UL << USBHSCORE_DCFG_PERFRINT_Pos) /*!< Bit mask of PERFRINT field.                  */
89040   #define USBHSCORE_DCFG_PERFRINT_Min (0x0UL)        /*!< Min enumerator value of PERFRINT field.                              */
89041   #define USBHSCORE_DCFG_PERFRINT_Max (0x3UL)        /*!< Max enumerator value of PERFRINT field.                              */
89042   #define USBHSCORE_DCFG_PERFRINT_EOPF80 (0x0UL)     /*!< (unspecified)                                                        */
89043   #define USBHSCORE_DCFG_PERFRINT_EOPF85 (0x1UL)     /*!< (unspecified)                                                        */
89044   #define USBHSCORE_DCFG_PERFRINT_EOPF90 (0x2UL)     /*!< (unspecified)                                                        */
89045   #define USBHSCORE_DCFG_PERFRINT_EOPF95 (0x3UL)     /*!< (unspecified)                                                        */
89046 
89047 /* XCVRDLY @Bit 14 : XCVRDLY */
89048   #define USBHSCORE_DCFG_XCVRDLY_Pos (14UL)          /*!< Position of XCVRDLY field.                                           */
89049   #define USBHSCORE_DCFG_XCVRDLY_Msk (0x1UL << USBHSCORE_DCFG_XCVRDLY_Pos) /*!< Bit mask of XCVRDLY field.                     */
89050   #define USBHSCORE_DCFG_XCVRDLY_Min (0x0UL)         /*!< Min enumerator value of XCVRDLY field.                               */
89051   #define USBHSCORE_DCFG_XCVRDLY_Max (0x1UL)         /*!< Max enumerator value of XCVRDLY field.                               */
89052   #define USBHSCORE_DCFG_XCVRDLY_DISABLE (0x0UL)     /*!< (unspecified)                                                        */
89053   #define USBHSCORE_DCFG_XCVRDLY_ENABLE (0x1UL)      /*!< (unspecified)                                                        */
89054 
89055 /* ERRATICINTMSK @Bit 15 : Erratic Error Interrupt Mask */
89056   #define USBHSCORE_DCFG_ERRATICINTMSK_Pos (15UL)    /*!< Position of ERRATICINTMSK field.                                     */
89057   #define USBHSCORE_DCFG_ERRATICINTMSK_Msk (0x1UL << USBHSCORE_DCFG_ERRATICINTMSK_Pos) /*!< Bit mask of ERRATICINTMSK field.   */
89058   #define USBHSCORE_DCFG_ERRATICINTMSK_Min (0x0UL)   /*!< Min enumerator value of ERRATICINTMSK field.                         */
89059   #define USBHSCORE_DCFG_ERRATICINTMSK_Max (0x1UL)   /*!< Max enumerator value of ERRATICINTMSK field.                         */
89060   #define USBHSCORE_DCFG_ERRATICINTMSK_NOMASK (0x0UL) /*!< (unspecified)                                                       */
89061   #define USBHSCORE_DCFG_ERRATICINTMSK_MASK (0x1UL)  /*!< (unspecified)                                                        */
89062 
89063 /* IPGISOCSUPT @Bit 17 : Worst-Case Inter-Packet Gap ISOC OUT Support (ipgisocSupt) */
89064   #define USBHSCORE_DCFG_IPGISOCSUPT_Pos (17UL)      /*!< Position of IPGISOCSUPT field.                                       */
89065   #define USBHSCORE_DCFG_IPGISOCSUPT_Msk (0x1UL << USBHSCORE_DCFG_IPGISOCSUPT_Pos) /*!< Bit mask of IPGISOCSUPT field.         */
89066   #define USBHSCORE_DCFG_IPGISOCSUPT_Min (0x0UL)     /*!< Min enumerator value of IPGISOCSUPT field.                           */
89067   #define USBHSCORE_DCFG_IPGISOCSUPT_Max (0x1UL)     /*!< Max enumerator value of IPGISOCSUPT field.                           */
89068   #define USBHSCORE_DCFG_IPGISOCSUPT_DISABLED (0x0UL) /*!< (unspecified)                                                       */
89069   #define USBHSCORE_DCFG_IPGISOCSUPT_ENABLED (0x1UL) /*!< (unspecified)                                                        */
89070 
89071 /* PERSCHINTVL @Bits 24..25 : Periodic Scheduling Interval (PerSchIntvl) */
89072   #define USBHSCORE_DCFG_PERSCHINTVL_Pos (24UL)      /*!< Position of PERSCHINTVL field.                                       */
89073   #define USBHSCORE_DCFG_PERSCHINTVL_Msk (0x3UL << USBHSCORE_DCFG_PERSCHINTVL_Pos) /*!< Bit mask of PERSCHINTVL field.         */
89074   #define USBHSCORE_DCFG_PERSCHINTVL_Min (0x0UL)     /*!< Min enumerator value of PERSCHINTVL field.                           */
89075   #define USBHSCORE_DCFG_PERSCHINTVL_Max (0x2UL)     /*!< Max enumerator value of PERSCHINTVL field.                           */
89076   #define USBHSCORE_DCFG_PERSCHINTVL_MF25 (0x0UL)    /*!< (unspecified)                                                        */
89077   #define USBHSCORE_DCFG_PERSCHINTVL_MF50 (0x1UL)    /*!< (unspecified)                                                        */
89078   #define USBHSCORE_DCFG_PERSCHINTVL_MF75 (0x2UL)    /*!< (unspecified)                                                        */
89079 
89080 /* RESVALID @Bits 26..31 : Resume Validation Period (ResValid) */
89081   #define USBHSCORE_DCFG_RESVALID_Pos (26UL)         /*!< Position of RESVALID field.                                          */
89082   #define USBHSCORE_DCFG_RESVALID_Msk (0x3FUL << USBHSCORE_DCFG_RESVALID_Pos) /*!< Bit mask of RESVALID field.                 */
89083 
89084 
89085 /* USBHSCORE_DCTL: Device Control Register */
89086   #define USBHSCORE_DCTL_ResetValue (0x00000002UL)   /*!< Reset value of DCTL register.                                        */
89087 
89088 /* RMTWKUPSIG @Bit 0 : Remote Wakeup Signaling (RmtWkUpSig) */
89089   #define USBHSCORE_DCTL_RMTWKUPSIG_Pos (0UL)        /*!< Position of RMTWKUPSIG field.                                        */
89090   #define USBHSCORE_DCTL_RMTWKUPSIG_Msk (0x1UL << USBHSCORE_DCTL_RMTWKUPSIG_Pos) /*!< Bit mask of RMTWKUPSIG field.            */
89091   #define USBHSCORE_DCTL_RMTWKUPSIG_Min (0x0UL)      /*!< Min enumerator value of RMTWKUPSIG field.                            */
89092   #define USBHSCORE_DCTL_RMTWKUPSIG_Max (0x1UL)      /*!< Max enumerator value of RMTWKUPSIG field.                            */
89093   #define USBHSCORE_DCTL_RMTWKUPSIG_DISABLEDRMWKUP (0x0UL) /*!< (unspecified)                                                  */
89094   #define USBHSCORE_DCTL_RMTWKUPSIG_ENABLERMWKUP (0x1UL) /*!< (unspecified)                                                    */
89095 
89096 /* SFTDISCON @Bit 1 : Soft Disconnect (SftDiscon) */
89097   #define USBHSCORE_DCTL_SFTDISCON_Pos (1UL)         /*!< Position of SFTDISCON field.                                         */
89098   #define USBHSCORE_DCTL_SFTDISCON_Msk (0x1UL << USBHSCORE_DCTL_SFTDISCON_Pos) /*!< Bit mask of SFTDISCON field.               */
89099   #define USBHSCORE_DCTL_SFTDISCON_Min (0x0UL)       /*!< Min enumerator value of SFTDISCON field.                             */
89100   #define USBHSCORE_DCTL_SFTDISCON_Max (0x1UL)       /*!< Max enumerator value of SFTDISCON field.                             */
89101   #define USBHSCORE_DCTL_SFTDISCON_NODISCONNECT (0x0UL) /*!< (unspecified)                                                     */
89102   #define USBHSCORE_DCTL_SFTDISCON_DISCONNECT (0x1UL) /*!< (unspecified)                                                       */
89103 
89104 /* GNPINNAKSTS @Bit 2 : Global Non-periodic IN NAK Status (GNPINNakSts) */
89105   #define USBHSCORE_DCTL_GNPINNAKSTS_Pos (2UL)       /*!< Position of GNPINNAKSTS field.                                       */
89106   #define USBHSCORE_DCTL_GNPINNAKSTS_Msk (0x1UL << USBHSCORE_DCTL_GNPINNAKSTS_Pos) /*!< Bit mask of GNPINNAKSTS field.         */
89107   #define USBHSCORE_DCTL_GNPINNAKSTS_Min (0x0UL)     /*!< Min enumerator value of GNPINNAKSTS field.                           */
89108   #define USBHSCORE_DCTL_GNPINNAKSTS_Max (0x1UL)     /*!< Max enumerator value of GNPINNAKSTS field.                           */
89109   #define USBHSCORE_DCTL_GNPINNAKSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
89110   #define USBHSCORE_DCTL_GNPINNAKSTS_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
89111 
89112 /* GOUTNAKSTS @Bit 3 : Global OUT NAK Status (GOUTNakSts) */
89113   #define USBHSCORE_DCTL_GOUTNAKSTS_Pos (3UL)        /*!< Position of GOUTNAKSTS field.                                        */
89114   #define USBHSCORE_DCTL_GOUTNAKSTS_Msk (0x1UL << USBHSCORE_DCTL_GOUTNAKSTS_Pos) /*!< Bit mask of GOUTNAKSTS field.            */
89115   #define USBHSCORE_DCTL_GOUTNAKSTS_Min (0x0UL)      /*!< Min enumerator value of GOUTNAKSTS field.                            */
89116   #define USBHSCORE_DCTL_GOUTNAKSTS_Max (0x1UL)      /*!< Max enumerator value of GOUTNAKSTS field.                            */
89117   #define USBHSCORE_DCTL_GOUTNAKSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89118   #define USBHSCORE_DCTL_GOUTNAKSTS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89119 
89120 /* TSTCTL @Bits 4..6 : Test Control (TstCtl) */
89121   #define USBHSCORE_DCTL_TSTCTL_Pos (4UL)            /*!< Position of TSTCTL field.                                            */
89122   #define USBHSCORE_DCTL_TSTCTL_Msk (0x7UL << USBHSCORE_DCTL_TSTCTL_Pos) /*!< Bit mask of TSTCTL field.                        */
89123   #define USBHSCORE_DCTL_TSTCTL_Min (0x0UL)          /*!< Min enumerator value of TSTCTL field.                                */
89124   #define USBHSCORE_DCTL_TSTCTL_Max (0x5UL)          /*!< Max enumerator value of TSTCTL field.                                */
89125   #define USBHSCORE_DCTL_TSTCTL_DISABLED (0x0UL)     /*!< (unspecified)                                                        */
89126   #define USBHSCORE_DCTL_TSTCTL_TESTJ (0x1UL)        /*!< (unspecified)                                                        */
89127   #define USBHSCORE_DCTL_TSTCTL_TESTK (0x2UL)        /*!< (unspecified)                                                        */
89128   #define USBHSCORE_DCTL_TSTCTL_TESTSN (0x3UL)       /*!< (unspecified)                                                        */
89129   #define USBHSCORE_DCTL_TSTCTL_TESTPM (0x4UL)       /*!< (unspecified)                                                        */
89130   #define USBHSCORE_DCTL_TSTCTL_TESTFE (0x5UL)       /*!< (unspecified)                                                        */
89131 
89132 /* SGNPINNAK @Bit 7 : Set Global Non-periodic IN NAK (SGNPInNak) */
89133   #define USBHSCORE_DCTL_SGNPINNAK_Pos (7UL)         /*!< Position of SGNPINNAK field.                                         */
89134   #define USBHSCORE_DCTL_SGNPINNAK_Msk (0x1UL << USBHSCORE_DCTL_SGNPINNAK_Pos) /*!< Bit mask of SGNPINNAK field.               */
89135   #define USBHSCORE_DCTL_SGNPINNAK_Min (0x0UL)       /*!< Min enumerator value of SGNPINNAK field.                             */
89136   #define USBHSCORE_DCTL_SGNPINNAK_Max (0x1UL)       /*!< Max enumerator value of SGNPINNAK field.                             */
89137   #define USBHSCORE_DCTL_SGNPINNAK_DISABLE (0x0UL)   /*!< (unspecified)                                                        */
89138   #define USBHSCORE_DCTL_SGNPINNAK_ENABLE (0x1UL)    /*!< (unspecified)                                                        */
89139 
89140 /* CGNPINNAK @Bit 8 : Clear Global Non-periodic IN NAK (CGNPInNak) */
89141   #define USBHSCORE_DCTL_CGNPINNAK_Pos (8UL)         /*!< Position of CGNPINNAK field.                                         */
89142   #define USBHSCORE_DCTL_CGNPINNAK_Msk (0x1UL << USBHSCORE_DCTL_CGNPINNAK_Pos) /*!< Bit mask of CGNPINNAK field.               */
89143   #define USBHSCORE_DCTL_CGNPINNAK_Min (0x0UL)       /*!< Min enumerator value of CGNPINNAK field.                             */
89144   #define USBHSCORE_DCTL_CGNPINNAK_Max (0x1UL)       /*!< Max enumerator value of CGNPINNAK field.                             */
89145   #define USBHSCORE_DCTL_CGNPINNAK_DISABLE (0x0UL)   /*!< (unspecified)                                                        */
89146   #define USBHSCORE_DCTL_CGNPINNAK_ENABLE (0x1UL)    /*!< (unspecified)                                                        */
89147 
89148 /* SGOUTNAK @Bit 9 : Set Global OUT NAK (SGOUTNak) */
89149   #define USBHSCORE_DCTL_SGOUTNAK_Pos (9UL)          /*!< Position of SGOUTNAK field.                                          */
89150   #define USBHSCORE_DCTL_SGOUTNAK_Msk (0x1UL << USBHSCORE_DCTL_SGOUTNAK_Pos) /*!< Bit mask of SGOUTNAK field.                  */
89151   #define USBHSCORE_DCTL_SGOUTNAK_Min (0x0UL)        /*!< Min enumerator value of SGOUTNAK field.                              */
89152   #define USBHSCORE_DCTL_SGOUTNAK_Max (0x1UL)        /*!< Max enumerator value of SGOUTNAK field.                              */
89153   #define USBHSCORE_DCTL_SGOUTNAK_DISABLED (0x0UL)   /*!< (unspecified)                                                        */
89154   #define USBHSCORE_DCTL_SGOUTNAK_ENABLED (0x1UL)    /*!< (unspecified)                                                        */
89155 
89156 /* CGOUTNAK @Bit 10 : Clear Global OUT NAK (CGOUTNak) */
89157   #define USBHSCORE_DCTL_CGOUTNAK_Pos (10UL)         /*!< Position of CGOUTNAK field.                                          */
89158   #define USBHSCORE_DCTL_CGOUTNAK_Msk (0x1UL << USBHSCORE_DCTL_CGOUTNAK_Pos) /*!< Bit mask of CGOUTNAK field.                  */
89159   #define USBHSCORE_DCTL_CGOUTNAK_Min (0x0UL)        /*!< Min enumerator value of CGOUTNAK field.                              */
89160   #define USBHSCORE_DCTL_CGOUTNAK_Max (0x1UL)        /*!< Max enumerator value of CGOUTNAK field.                              */
89161   #define USBHSCORE_DCTL_CGOUTNAK_DISABLED (0x0UL)   /*!< (unspecified)                                                        */
89162   #define USBHSCORE_DCTL_CGOUTNAK_ENABLED (0x1UL)    /*!< (unspecified)                                                        */
89163 
89164 /* PWRONPRGDONE @Bit 11 : Power-On Programming Done (PWROnPrgDone) */
89165   #define USBHSCORE_DCTL_PWRONPRGDONE_Pos (11UL)     /*!< Position of PWRONPRGDONE field.                                      */
89166   #define USBHSCORE_DCTL_PWRONPRGDONE_Msk (0x1UL << USBHSCORE_DCTL_PWRONPRGDONE_Pos) /*!< Bit mask of PWRONPRGDONE field.      */
89167   #define USBHSCORE_DCTL_PWRONPRGDONE_Min (0x0UL)    /*!< Min enumerator value of PWRONPRGDONE field.                          */
89168   #define USBHSCORE_DCTL_PWRONPRGDONE_Max (0x1UL)    /*!< Max enumerator value of PWRONPRGDONE field.                          */
89169   #define USBHSCORE_DCTL_PWRONPRGDONE_NOTDONE (0x0UL) /*!< (unspecified)                                                       */
89170   #define USBHSCORE_DCTL_PWRONPRGDONE_DONE (0x1UL)   /*!< (unspecified)                                                        */
89171 
89172 /* IGNRFRMNUM @Bit 15 : Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum) */
89173   #define USBHSCORE_DCTL_IGNRFRMNUM_Pos (15UL)       /*!< Position of IGNRFRMNUM field.                                        */
89174   #define USBHSCORE_DCTL_IGNRFRMNUM_Msk (0x1UL << USBHSCORE_DCTL_IGNRFRMNUM_Pos) /*!< Bit mask of IGNRFRMNUM field.            */
89175   #define USBHSCORE_DCTL_IGNRFRMNUM_Min (0x0UL)      /*!< Min enumerator value of IGNRFRMNUM field.                            */
89176   #define USBHSCORE_DCTL_IGNRFRMNUM_Max (0x1UL)      /*!< Max enumerator value of IGNRFRMNUM field.                            */
89177   #define USBHSCORE_DCTL_IGNRFRMNUM_DISABLED (0x0UL) /*!< (unspecified)                                                        */
89178   #define USBHSCORE_DCTL_IGNRFRMNUM_ENABLED (0x1UL)  /*!< (unspecified)                                                        */
89179 
89180 /* NAKONBBLE @Bit 16 : NAK on Babble Error (NakOnBble) */
89181   #define USBHSCORE_DCTL_NAKONBBLE_Pos (16UL)        /*!< Position of NAKONBBLE field.                                         */
89182   #define USBHSCORE_DCTL_NAKONBBLE_Msk (0x1UL << USBHSCORE_DCTL_NAKONBBLE_Pos) /*!< Bit mask of NAKONBBLE field.               */
89183   #define USBHSCORE_DCTL_NAKONBBLE_Min (0x0UL)       /*!< Min enumerator value of NAKONBBLE field.                             */
89184   #define USBHSCORE_DCTL_NAKONBBLE_Max (0x1UL)       /*!< Max enumerator value of NAKONBBLE field.                             */
89185   #define USBHSCORE_DCTL_NAKONBBLE_DISABLED (0x0UL)  /*!< (unspecified)                                                        */
89186   #define USBHSCORE_DCTL_NAKONBBLE_ENABLED (0x1UL)   /*!< (unspecified)                                                        */
89187 
89188 /* DEEPSLEEPBESLREJECT @Bit 18 : DeepSleepBESLReject */
89189   #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Pos (18UL) /*!< Position of DEEPSLEEPBESLREJECT field.                            */
89190   #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Msk (0x1UL << USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Pos) /*!< Bit mask of
89191                                                                             DEEPSLEEPBESLREJECT field.*/
89192   #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Min (0x0UL) /*!< Min enumerator value of DEEPSLEEPBESLREJECT field.               */
89193   #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_Max (0x1UL) /*!< Max enumerator value of DEEPSLEEPBESLREJECT field.               */
89194   #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_DISABLED (0x0UL) /*!< (unspecified)                                               */
89195   #define USBHSCORE_DCTL_DEEPSLEEPBESLREJECT_ENABLED (0x1UL) /*!< (unspecified)                                                */
89196 
89197 /* SERVINT @Bit 19 : Service Interval based scheduling for Isochronous IN Endpoints */
89198   #define USBHSCORE_DCTL_SERVINT_Pos (19UL)          /*!< Position of SERVINT field.                                           */
89199   #define USBHSCORE_DCTL_SERVINT_Msk (0x1UL << USBHSCORE_DCTL_SERVINT_Pos) /*!< Bit mask of SERVINT field.                     */
89200   #define USBHSCORE_DCTL_SERVINT_Min (0x0UL)         /*!< Min enumerator value of SERVINT field.                               */
89201   #define USBHSCORE_DCTL_SERVINT_Max (0x1UL)         /*!< Max enumerator value of SERVINT field.                               */
89202   #define USBHSCORE_DCTL_SERVINT_DISABLED (0x0UL)    /*!< (unspecified)                                                        */
89203   #define USBHSCORE_DCTL_SERVINT_ENABLED (0x1UL)     /*!< (unspecified)                                                        */
89204 
89205 
89206 /* USBHSCORE_DSTS: Device Status Register */
89207   #define USBHSCORE_DSTS_ResetValue (0x00000002UL)   /*!< Reset value of DSTS register.                                        */
89208 
89209 /* SUSPSTS @Bit 0 : Suspend Status (SuspSts) */
89210   #define USBHSCORE_DSTS_SUSPSTS_Pos (0UL)           /*!< Position of SUSPSTS field.                                           */
89211   #define USBHSCORE_DSTS_SUSPSTS_Msk (0x1UL << USBHSCORE_DSTS_SUSPSTS_Pos) /*!< Bit mask of SUSPSTS field.                     */
89212   #define USBHSCORE_DSTS_SUSPSTS_Min (0x0UL)         /*!< Min enumerator value of SUSPSTS field.                               */
89213   #define USBHSCORE_DSTS_SUSPSTS_Max (0x1UL)         /*!< Max enumerator value of SUSPSTS field.                               */
89214   #define USBHSCORE_DSTS_SUSPSTS_INACTIVE (0x0UL)    /*!< (unspecified)                                                        */
89215   #define USBHSCORE_DSTS_SUSPSTS_ACTIVE (0x1UL)      /*!< (unspecified)                                                        */
89216 
89217 /* ENUMSPD @Bits 1..2 : Enumerated Speed (EnumSpd) */
89218   #define USBHSCORE_DSTS_ENUMSPD_Pos (1UL)           /*!< Position of ENUMSPD field.                                           */
89219   #define USBHSCORE_DSTS_ENUMSPD_Msk (0x3UL << USBHSCORE_DSTS_ENUMSPD_Pos) /*!< Bit mask of ENUMSPD field.                     */
89220   #define USBHSCORE_DSTS_ENUMSPD_Min (0x0UL)         /*!< Min enumerator value of ENUMSPD field.                               */
89221   #define USBHSCORE_DSTS_ENUMSPD_Max (0x3UL)         /*!< Max enumerator value of ENUMSPD field.                               */
89222   #define USBHSCORE_DSTS_ENUMSPD_HS3060 (0x0UL)      /*!< (unspecified)                                                        */
89223   #define USBHSCORE_DSTS_ENUMSPD_FS3060 (0x1UL)      /*!< (unspecified)                                                        */
89224   #define USBHSCORE_DSTS_ENUMSPD_LS6 (0x2UL)         /*!< (unspecified)                                                        */
89225   #define USBHSCORE_DSTS_ENUMSPD_FS48 (0x3UL)        /*!< (unspecified)                                                        */
89226 
89227 /* ERRTICERR @Bit 3 : Erratic Error (ErrticErr) */
89228   #define USBHSCORE_DSTS_ERRTICERR_Pos (3UL)         /*!< Position of ERRTICERR field.                                         */
89229   #define USBHSCORE_DSTS_ERRTICERR_Msk (0x1UL << USBHSCORE_DSTS_ERRTICERR_Pos) /*!< Bit mask of ERRTICERR field.               */
89230   #define USBHSCORE_DSTS_ERRTICERR_Min (0x0UL)       /*!< Min enumerator value of ERRTICERR field.                             */
89231   #define USBHSCORE_DSTS_ERRTICERR_Max (0x1UL)       /*!< Max enumerator value of ERRTICERR field.                             */
89232   #define USBHSCORE_DSTS_ERRTICERR_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89233   #define USBHSCORE_DSTS_ERRTICERR_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89234 
89235 /* SOFFN @Bits 8..21 : Frame or Microframe Number of the Received SOF (SOFFN) */
89236   #define USBHSCORE_DSTS_SOFFN_Pos (8UL)             /*!< Position of SOFFN field.                                             */
89237   #define USBHSCORE_DSTS_SOFFN_Msk (0x3FFFUL << USBHSCORE_DSTS_SOFFN_Pos) /*!< Bit mask of SOFFN field.                        */
89238 
89239 /* DEVLNSTS @Bits 22..23 : Device Line Status (DevLnSts) */
89240   #define USBHSCORE_DSTS_DEVLNSTS_Pos (22UL)         /*!< Position of DEVLNSTS field.                                          */
89241   #define USBHSCORE_DSTS_DEVLNSTS_Msk (0x3UL << USBHSCORE_DSTS_DEVLNSTS_Pos) /*!< Bit mask of DEVLNSTS field.                  */
89242 
89243 
89244 /* USBHSCORE_DIEPMSK: Device IN Endpoint Common Interrupt Mask Register */
89245   #define USBHSCORE_DIEPMSK_ResetValue (0x00000000UL) /*!< Reset value of DIEPMSK register.                                    */
89246 
89247 /* XFERCOMPLMSK @Bit 0 : Transfer Completed Interrupt Mask (XferComplMsk) */
89248   #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Pos (0UL)   /*!< Position of XFERCOMPLMSK field.                                      */
89249   #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK field.*/
89250   #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field.                          */
89251   #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field.                          */
89252   #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< (unspecified)                                                       */
89253   #define USBHSCORE_DIEPMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< (unspecified)                                                     */
89254 
89255 /* EPDISBLDMSK @Bit 1 : Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
89256   #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Pos (1UL)    /*!< Position of EPDISBLDMSK field.                                       */
89257   #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_EPDISBLDMSK_Pos) /*!< Bit mask of EPDISBLDMSK field.   */
89258   #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Min (0x0UL)  /*!< Min enumerator value of EPDISBLDMSK field.                           */
89259   #define USBHSCORE_DIEPMSK_EPDISBLDMSK_Max (0x1UL)  /*!< Max enumerator value of EPDISBLDMSK field.                           */
89260   #define USBHSCORE_DIEPMSK_EPDISBLDMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
89261   #define USBHSCORE_DIEPMSK_EPDISBLDMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
89262 
89263 /* AHBERRMSK @Bit 2 : AHB Error Mask (AHBErrMsk) */
89264   #define USBHSCORE_DIEPMSK_AHBERRMSK_Pos (2UL)      /*!< Position of AHBERRMSK field.                                         */
89265   #define USBHSCORE_DIEPMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field.         */
89266   #define USBHSCORE_DIEPMSK_AHBERRMSK_Min (0x0UL)    /*!< Min enumerator value of AHBERRMSK field.                             */
89267   #define USBHSCORE_DIEPMSK_AHBERRMSK_Max (0x1UL)    /*!< Max enumerator value of AHBERRMSK field.                             */
89268   #define USBHSCORE_DIEPMSK_AHBERRMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
89269   #define USBHSCORE_DIEPMSK_AHBERRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89270 
89271 /* TIMEOUTMSK @Bit 3 : Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints) */
89272   #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Pos (3UL)     /*!< Position of TIMEOUTMSK field.                                        */
89273   #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_TIMEOUTMSK_Pos) /*!< Bit mask of TIMEOUTMSK field.      */
89274   #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Min (0x0UL)   /*!< Min enumerator value of TIMEOUTMSK field.                            */
89275   #define USBHSCORE_DIEPMSK_TIMEOUTMSK_Max (0x1UL)   /*!< Max enumerator value of TIMEOUTMSK field.                            */
89276   #define USBHSCORE_DIEPMSK_TIMEOUTMSK_MASK (0x0UL)  /*!< (unspecified)                                                        */
89277   #define USBHSCORE_DIEPMSK_TIMEOUTMSK_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89278 
89279 /* INTKNTXFEMPMSK @Bit 4 : IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk) */
89280   #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Pos (4UL) /*!< Position of INTKNTXFEMPMSK field.                                    */
89281   #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Pos) /*!< Bit mask of INTKNTXFEMPMSK
89282                                                                             field.*/
89283   #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMPMSK field.                      */
89284   #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMPMSK field.                      */
89285   #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_MASK (0x0UL) /*!< (unspecified)                                                     */
89286   #define USBHSCORE_DIEPMSK_INTKNTXFEMPMSK_NOMASK (0x1UL) /*!< (unspecified)                                                   */
89287 
89288 /* INTKNEPMISMSK @Bit 5 : IN Token received with EP Mismatch Mask (INTknEPMisMsk) */
89289   #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Pos (5UL)  /*!< Position of INTKNEPMISMSK field.                                     */
89290   #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INTKNEPMISMSK_Pos) /*!< Bit mask of INTKNEPMISMSK
89291                                                                             field.*/
89292   #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Min (0x0UL) /*!< Min enumerator value of INTKNEPMISMSK field.                        */
89293   #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_Max (0x1UL) /*!< Max enumerator value of INTKNEPMISMSK field.                        */
89294   #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_MASK (0x0UL) /*!< (unspecified)                                                      */
89295   #define USBHSCORE_DIEPMSK_INTKNEPMISMSK_NOMASK (0x1UL) /*!< (unspecified)                                                    */
89296 
89297 /* INEPNAKEFFMSK @Bit 6 : IN Endpoint NAK Effective Mask (INEPNakEffMsk) */
89298   #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Pos (6UL)  /*!< Position of INEPNAKEFFMSK field.                                     */
89299   #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Pos) /*!< Bit mask of INEPNAKEFFMSK
89300                                                                             field.*/
89301   #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFFMSK field.                        */
89302   #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFFMSK field.                        */
89303   #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_MASK (0x0UL) /*!< (unspecified)                                                      */
89304   #define USBHSCORE_DIEPMSK_INEPNAKEFFMSK_NOMASK (0x1UL) /*!< (unspecified)                                                    */
89305 
89306 /* TXFIFOUNDRNMSK @Bit 8 : Fifo Underrun Mask (TxfifoUndrnMsk) */
89307   #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Pos (8UL) /*!< Position of TXFIFOUNDRNMSK field.                                    */
89308   #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Pos) /*!< Bit mask of TXFIFOUNDRNMSK
89309                                                                             field.*/
89310   #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRNMSK field.                      */
89311   #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRNMSK field.                      */
89312   #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_MASK (0x0UL) /*!< (unspecified)                                                     */
89313   #define USBHSCORE_DIEPMSK_TXFIFOUNDRNMSK_NOMASK (0x1UL) /*!< (unspecified)                                                   */
89314 
89315 /* NAKMSK @Bit 13 : NAK interrupt Mask (NAKMsk) */
89316   #define USBHSCORE_DIEPMSK_NAKMSK_Pos (13UL)        /*!< Position of NAKMSK field.                                            */
89317   #define USBHSCORE_DIEPMSK_NAKMSK_Msk (0x1UL << USBHSCORE_DIEPMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field.                  */
89318   #define USBHSCORE_DIEPMSK_NAKMSK_Min (0x0UL)       /*!< Min enumerator value of NAKMSK field.                                */
89319   #define USBHSCORE_DIEPMSK_NAKMSK_Max (0x1UL)       /*!< Max enumerator value of NAKMSK field.                                */
89320   #define USBHSCORE_DIEPMSK_NAKMSK_MASK (0x0UL)      /*!< (unspecified)                                                        */
89321   #define USBHSCORE_DIEPMSK_NAKMSK_NOMASK (0x1UL)    /*!< (unspecified)                                                        */
89322 
89323 
89324 /* USBHSCORE_DOEPMSK: Device OUT Endpoint Common Interrupt Mask Register */
89325   #define USBHSCORE_DOEPMSK_ResetValue (0x00000000UL) /*!< Reset value of DOEPMSK register.                                    */
89326 
89327 /* XFERCOMPLMSK @Bit 0 : Transfer Completed Interrupt Mask (XferComplMsk) */
89328   #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Pos (0UL)   /*!< Position of XFERCOMPLMSK field.                                      */
89329   #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_XFERCOMPLMSK_Pos) /*!< Bit mask of XFERCOMPLMSK field.*/
89330   #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLMSK field.                          */
89331   #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLMSK field.                          */
89332   #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_MASK (0x0UL) /*!< (unspecified)                                                       */
89333   #define USBHSCORE_DOEPMSK_XFERCOMPLMSK_NOMASK (0x1UL) /*!< (unspecified)                                                     */
89334 
89335 /* EPDISBLDMSK @Bit 1 : Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
89336   #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Pos (1UL)    /*!< Position of EPDISBLDMSK field.                                       */
89337   #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_EPDISBLDMSK_Pos) /*!< Bit mask of EPDISBLDMSK field.   */
89338   #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Min (0x0UL)  /*!< Min enumerator value of EPDISBLDMSK field.                           */
89339   #define USBHSCORE_DOEPMSK_EPDISBLDMSK_Max (0x1UL)  /*!< Max enumerator value of EPDISBLDMSK field.                           */
89340   #define USBHSCORE_DOEPMSK_EPDISBLDMSK_MASK (0x0UL) /*!< (unspecified)                                                        */
89341   #define USBHSCORE_DOEPMSK_EPDISBLDMSK_NOMASK (0x1UL) /*!< (unspecified)                                                      */
89342 
89343 /* AHBERRMSK @Bit 2 : AHB Error (AHBErrMsk) */
89344   #define USBHSCORE_DOEPMSK_AHBERRMSK_Pos (2UL)      /*!< Position of AHBERRMSK field.                                         */
89345   #define USBHSCORE_DOEPMSK_AHBERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_AHBERRMSK_Pos) /*!< Bit mask of AHBERRMSK field.         */
89346   #define USBHSCORE_DOEPMSK_AHBERRMSK_Min (0x0UL)    /*!< Min enumerator value of AHBERRMSK field.                             */
89347   #define USBHSCORE_DOEPMSK_AHBERRMSK_Max (0x1UL)    /*!< Max enumerator value of AHBERRMSK field.                             */
89348   #define USBHSCORE_DOEPMSK_AHBERRMSK_MASK (0x0UL)   /*!< (unspecified)                                                        */
89349   #define USBHSCORE_DOEPMSK_AHBERRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89350 
89351 /* SETUPMSK @Bit 3 : SETUP Phase Done Mask (SetUPMsk) */
89352   #define USBHSCORE_DOEPMSK_SETUPMSK_Pos (3UL)       /*!< Position of SETUPMSK field.                                          */
89353   #define USBHSCORE_DOEPMSK_SETUPMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_SETUPMSK_Pos) /*!< Bit mask of SETUPMSK field.            */
89354   #define USBHSCORE_DOEPMSK_SETUPMSK_Min (0x0UL)     /*!< Min enumerator value of SETUPMSK field.                              */
89355   #define USBHSCORE_DOEPMSK_SETUPMSK_Max (0x1UL)     /*!< Max enumerator value of SETUPMSK field.                              */
89356   #define USBHSCORE_DOEPMSK_SETUPMSK_MASK (0x0UL)    /*!< (unspecified)                                                        */
89357   #define USBHSCORE_DOEPMSK_SETUPMSK_NOMASK (0x1UL)  /*!< (unspecified)                                                        */
89358 
89359 /* OUTTKNEPDISMSK @Bit 4 : OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk) */
89360   #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Pos (4UL) /*!< Position of OUTTKNEPDISMSK field.                                    */
89361   #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Pos) /*!< Bit mask of OUTTKNEPDISMSK
89362                                                                             field.*/
89363   #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDISMSK field.                      */
89364   #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDISMSK field.                      */
89365   #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_MASK (0x0UL) /*!< (unspecified)                                                     */
89366   #define USBHSCORE_DOEPMSK_OUTTKNEPDISMSK_NOMASK (0x1UL) /*!< (unspecified)                                                   */
89367 
89368 /* STSPHSERCVDMSK @Bit 5 : Status Phase Received Mask (StsPhseRcvdMsk) */
89369   #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Pos (5UL) /*!< Position of STSPHSERCVDMSK field.                                    */
89370   #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Pos) /*!< Bit mask of STSPHSERCVDMSK
89371                                                                             field.*/
89372   #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVDMSK field.                      */
89373   #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVDMSK field.                      */
89374   #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_MASK (0x0UL) /*!< (unspecified)                                                     */
89375   #define USBHSCORE_DOEPMSK_STSPHSERCVDMSK_NOMASK (0x1UL) /*!< (unspecified)                                                   */
89376 
89377 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received Mask (Back2BackSETup) */
89378   #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                    */
89379   #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPMSK_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP
89380                                                                             field.*/
89381   #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                      */
89382   #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                      */
89383   #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_MASK (0x0UL) /*!< (unspecified)                                                     */
89384   #define USBHSCORE_DOEPMSK_BACK2BACKSETUP_NOMASK (0x1UL) /*!< (unspecified)                                                   */
89385 
89386 /* OUTPKTERRMSK @Bit 8 : OUT Packet Error Mask (OutPktErrMsk) */
89387   #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Pos (8UL)   /*!< Position of OUTPKTERRMSK field.                                      */
89388   #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_OUTPKTERRMSK_Pos) /*!< Bit mask of OUTPKTERRMSK field.*/
89389   #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Min (0x0UL) /*!< Min enumerator value of OUTPKTERRMSK field.                          */
89390   #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_Max (0x1UL) /*!< Max enumerator value of OUTPKTERRMSK field.                          */
89391   #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_MASK (0x0UL) /*!< (unspecified)                                                       */
89392   #define USBHSCORE_DOEPMSK_OUTPKTERRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                     */
89393 
89394 /* BBLEERRMSK @Bit 12 : Babble Error interrupt Mask (BbleErrMsk) */
89395   #define USBHSCORE_DOEPMSK_BBLEERRMSK_Pos (12UL)    /*!< Position of BBLEERRMSK field.                                        */
89396   #define USBHSCORE_DOEPMSK_BBLEERRMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_BBLEERRMSK_Pos) /*!< Bit mask of BBLEERRMSK field.      */
89397   #define USBHSCORE_DOEPMSK_BBLEERRMSK_Min (0x0UL)   /*!< Min enumerator value of BBLEERRMSK field.                            */
89398   #define USBHSCORE_DOEPMSK_BBLEERRMSK_Max (0x1UL)   /*!< Max enumerator value of BBLEERRMSK field.                            */
89399   #define USBHSCORE_DOEPMSK_BBLEERRMSK_MASK (0x0UL)  /*!< (unspecified)                                                        */
89400   #define USBHSCORE_DOEPMSK_BBLEERRMSK_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89401 
89402 /* NAKMSK @Bit 13 : NAK interrupt Mask (NAKMsk) */
89403   #define USBHSCORE_DOEPMSK_NAKMSK_Pos (13UL)        /*!< Position of NAKMSK field.                                            */
89404   #define USBHSCORE_DOEPMSK_NAKMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_NAKMSK_Pos) /*!< Bit mask of NAKMSK field.                  */
89405   #define USBHSCORE_DOEPMSK_NAKMSK_Min (0x0UL)       /*!< Min enumerator value of NAKMSK field.                                */
89406   #define USBHSCORE_DOEPMSK_NAKMSK_Max (0x1UL)       /*!< Max enumerator value of NAKMSK field.                                */
89407   #define USBHSCORE_DOEPMSK_NAKMSK_MASK (0x0UL)      /*!< (unspecified)                                                        */
89408   #define USBHSCORE_DOEPMSK_NAKMSK_NOMASK (0x1UL)    /*!< (unspecified)                                                        */
89409 
89410 /* NYETMSK @Bit 14 : NYET interrupt Mask (NYETMsk) */
89411   #define USBHSCORE_DOEPMSK_NYETMSK_Pos (14UL)       /*!< Position of NYETMSK field.                                           */
89412   #define USBHSCORE_DOEPMSK_NYETMSK_Msk (0x1UL << USBHSCORE_DOEPMSK_NYETMSK_Pos) /*!< Bit mask of NYETMSK field.               */
89413   #define USBHSCORE_DOEPMSK_NYETMSK_Min (0x0UL)      /*!< Min enumerator value of NYETMSK field.                               */
89414   #define USBHSCORE_DOEPMSK_NYETMSK_Max (0x1UL)      /*!< Max enumerator value of NYETMSK field.                               */
89415   #define USBHSCORE_DOEPMSK_NYETMSK_MASK (0x0UL)     /*!< (unspecified)                                                        */
89416   #define USBHSCORE_DOEPMSK_NYETMSK_NOMASK (0x1UL)   /*!< (unspecified)                                                        */
89417 
89418 
89419 /* USBHSCORE_DAINT: Device All Endpoints Interrupt Register */
89420   #define USBHSCORE_DAINT_ResetValue (0x00000000UL)  /*!< Reset value of DAINT register.                                       */
89421 
89422 /* INEPINT0 @Bit 0 : IN Endpoint 0 Interrupt Bit */
89423   #define USBHSCORE_DAINT_INEPINT0_Pos (0UL)         /*!< Position of INEPINT0 field.                                          */
89424   #define USBHSCORE_DAINT_INEPINT0_Msk (0x1UL << USBHSCORE_DAINT_INEPINT0_Pos) /*!< Bit mask of INEPINT0 field.                */
89425   #define USBHSCORE_DAINT_INEPINT0_Min (0x0UL)       /*!< Min enumerator value of INEPINT0 field.                              */
89426   #define USBHSCORE_DAINT_INEPINT0_Max (0x1UL)       /*!< Max enumerator value of INEPINT0 field.                              */
89427   #define USBHSCORE_DAINT_INEPINT0_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89428   #define USBHSCORE_DAINT_INEPINT0_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89429 
89430 /* INEPINT1 @Bit 1 : IN Endpoint 1 Interrupt Bit */
89431   #define USBHSCORE_DAINT_INEPINT1_Pos (1UL)         /*!< Position of INEPINT1 field.                                          */
89432   #define USBHSCORE_DAINT_INEPINT1_Msk (0x1UL << USBHSCORE_DAINT_INEPINT1_Pos) /*!< Bit mask of INEPINT1 field.                */
89433   #define USBHSCORE_DAINT_INEPINT1_Min (0x0UL)       /*!< Min enumerator value of INEPINT1 field.                              */
89434   #define USBHSCORE_DAINT_INEPINT1_Max (0x1UL)       /*!< Max enumerator value of INEPINT1 field.                              */
89435   #define USBHSCORE_DAINT_INEPINT1_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89436   #define USBHSCORE_DAINT_INEPINT1_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89437 
89438 /* INEPINT2 @Bit 2 : IN Endpoint 2 Interrupt Bit */
89439   #define USBHSCORE_DAINT_INEPINT2_Pos (2UL)         /*!< Position of INEPINT2 field.                                          */
89440   #define USBHSCORE_DAINT_INEPINT2_Msk (0x1UL << USBHSCORE_DAINT_INEPINT2_Pos) /*!< Bit mask of INEPINT2 field.                */
89441   #define USBHSCORE_DAINT_INEPINT2_Min (0x0UL)       /*!< Min enumerator value of INEPINT2 field.                              */
89442   #define USBHSCORE_DAINT_INEPINT2_Max (0x1UL)       /*!< Max enumerator value of INEPINT2 field.                              */
89443   #define USBHSCORE_DAINT_INEPINT2_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89444   #define USBHSCORE_DAINT_INEPINT2_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89445 
89446 /* INEPINT3 @Bit 3 : IN Endpoint 3 Interrupt Bit */
89447   #define USBHSCORE_DAINT_INEPINT3_Pos (3UL)         /*!< Position of INEPINT3 field.                                          */
89448   #define USBHSCORE_DAINT_INEPINT3_Msk (0x1UL << USBHSCORE_DAINT_INEPINT3_Pos) /*!< Bit mask of INEPINT3 field.                */
89449   #define USBHSCORE_DAINT_INEPINT3_Min (0x0UL)       /*!< Min enumerator value of INEPINT3 field.                              */
89450   #define USBHSCORE_DAINT_INEPINT3_Max (0x1UL)       /*!< Max enumerator value of INEPINT3 field.                              */
89451   #define USBHSCORE_DAINT_INEPINT3_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89452   #define USBHSCORE_DAINT_INEPINT3_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89453 
89454 /* INEPINT4 @Bit 4 : IN Endpoint 4 Interrupt Bit */
89455   #define USBHSCORE_DAINT_INEPINT4_Pos (4UL)         /*!< Position of INEPINT4 field.                                          */
89456   #define USBHSCORE_DAINT_INEPINT4_Msk (0x1UL << USBHSCORE_DAINT_INEPINT4_Pos) /*!< Bit mask of INEPINT4 field.                */
89457   #define USBHSCORE_DAINT_INEPINT4_Min (0x0UL)       /*!< Min enumerator value of INEPINT4 field.                              */
89458   #define USBHSCORE_DAINT_INEPINT4_Max (0x1UL)       /*!< Max enumerator value of INEPINT4 field.                              */
89459   #define USBHSCORE_DAINT_INEPINT4_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89460   #define USBHSCORE_DAINT_INEPINT4_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89461 
89462 /* INEPINT5 @Bit 5 : IN Endpoint 5 Interrupt Bit */
89463   #define USBHSCORE_DAINT_INEPINT5_Pos (5UL)         /*!< Position of INEPINT5 field.                                          */
89464   #define USBHSCORE_DAINT_INEPINT5_Msk (0x1UL << USBHSCORE_DAINT_INEPINT5_Pos) /*!< Bit mask of INEPINT5 field.                */
89465   #define USBHSCORE_DAINT_INEPINT5_Min (0x0UL)       /*!< Min enumerator value of INEPINT5 field.                              */
89466   #define USBHSCORE_DAINT_INEPINT5_Max (0x1UL)       /*!< Max enumerator value of INEPINT5 field.                              */
89467   #define USBHSCORE_DAINT_INEPINT5_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89468   #define USBHSCORE_DAINT_INEPINT5_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89469 
89470 /* INEPINT6 @Bit 6 : IN Endpoint 6 Interrupt Bit */
89471   #define USBHSCORE_DAINT_INEPINT6_Pos (6UL)         /*!< Position of INEPINT6 field.                                          */
89472   #define USBHSCORE_DAINT_INEPINT6_Msk (0x1UL << USBHSCORE_DAINT_INEPINT6_Pos) /*!< Bit mask of INEPINT6 field.                */
89473   #define USBHSCORE_DAINT_INEPINT6_Min (0x0UL)       /*!< Min enumerator value of INEPINT6 field.                              */
89474   #define USBHSCORE_DAINT_INEPINT6_Max (0x1UL)       /*!< Max enumerator value of INEPINT6 field.                              */
89475   #define USBHSCORE_DAINT_INEPINT6_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89476   #define USBHSCORE_DAINT_INEPINT6_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89477 
89478 /* INEPINT7 @Bit 7 : IN Endpoint 7 Interrupt Bit */
89479   #define USBHSCORE_DAINT_INEPINT7_Pos (7UL)         /*!< Position of INEPINT7 field.                                          */
89480   #define USBHSCORE_DAINT_INEPINT7_Msk (0x1UL << USBHSCORE_DAINT_INEPINT7_Pos) /*!< Bit mask of INEPINT7 field.                */
89481   #define USBHSCORE_DAINT_INEPINT7_Min (0x0UL)       /*!< Min enumerator value of INEPINT7 field.                              */
89482   #define USBHSCORE_DAINT_INEPINT7_Max (0x1UL)       /*!< Max enumerator value of INEPINT7 field.                              */
89483   #define USBHSCORE_DAINT_INEPINT7_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89484   #define USBHSCORE_DAINT_INEPINT7_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89485 
89486 /* INEPINT8 @Bit 8 : IN Endpoint 8 Interrupt Bit */
89487   #define USBHSCORE_DAINT_INEPINT8_Pos (8UL)         /*!< Position of INEPINT8 field.                                          */
89488   #define USBHSCORE_DAINT_INEPINT8_Msk (0x1UL << USBHSCORE_DAINT_INEPINT8_Pos) /*!< Bit mask of INEPINT8 field.                */
89489   #define USBHSCORE_DAINT_INEPINT8_Min (0x0UL)       /*!< Min enumerator value of INEPINT8 field.                              */
89490   #define USBHSCORE_DAINT_INEPINT8_Max (0x1UL)       /*!< Max enumerator value of INEPINT8 field.                              */
89491   #define USBHSCORE_DAINT_INEPINT8_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89492   #define USBHSCORE_DAINT_INEPINT8_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89493 
89494 /* INEPINT9 @Bit 9 : IN Endpoint 9 Interrupt Bit */
89495   #define USBHSCORE_DAINT_INEPINT9_Pos (9UL)         /*!< Position of INEPINT9 field.                                          */
89496   #define USBHSCORE_DAINT_INEPINT9_Msk (0x1UL << USBHSCORE_DAINT_INEPINT9_Pos) /*!< Bit mask of INEPINT9 field.                */
89497   #define USBHSCORE_DAINT_INEPINT9_Min (0x0UL)       /*!< Min enumerator value of INEPINT9 field.                              */
89498   #define USBHSCORE_DAINT_INEPINT9_Max (0x1UL)       /*!< Max enumerator value of INEPINT9 field.                              */
89499   #define USBHSCORE_DAINT_INEPINT9_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89500   #define USBHSCORE_DAINT_INEPINT9_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89501 
89502 /* INEPINT10 @Bit 10 : IN Endpoint 10 Interrupt Bit */
89503   #define USBHSCORE_DAINT_INEPINT10_Pos (10UL)       /*!< Position of INEPINT10 field.                                         */
89504   #define USBHSCORE_DAINT_INEPINT10_Msk (0x1UL << USBHSCORE_DAINT_INEPINT10_Pos) /*!< Bit mask of INEPINT10 field.             */
89505   #define USBHSCORE_DAINT_INEPINT10_Min (0x0UL)      /*!< Min enumerator value of INEPINT10 field.                             */
89506   #define USBHSCORE_DAINT_INEPINT10_Max (0x1UL)      /*!< Max enumerator value of INEPINT10 field.                             */
89507   #define USBHSCORE_DAINT_INEPINT10_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89508   #define USBHSCORE_DAINT_INEPINT10_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89509 
89510 /* INEPINT11 @Bit 11 : IN Endpoint 11 Interrupt Bit */
89511   #define USBHSCORE_DAINT_INEPINT11_Pos (11UL)       /*!< Position of INEPINT11 field.                                         */
89512   #define USBHSCORE_DAINT_INEPINT11_Msk (0x1UL << USBHSCORE_DAINT_INEPINT11_Pos) /*!< Bit mask of INEPINT11 field.             */
89513   #define USBHSCORE_DAINT_INEPINT11_Min (0x0UL)      /*!< Min enumerator value of INEPINT11 field.                             */
89514   #define USBHSCORE_DAINT_INEPINT11_Max (0x1UL)      /*!< Max enumerator value of INEPINT11 field.                             */
89515   #define USBHSCORE_DAINT_INEPINT11_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89516   #define USBHSCORE_DAINT_INEPINT11_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89517 
89518 /* OUTEPINT0 @Bit 16 : OUT Endpoint 0 Interrupt Bit */
89519   #define USBHSCORE_DAINT_OUTEPINT0_Pos (16UL)       /*!< Position of OUTEPINT0 field.                                         */
89520   #define USBHSCORE_DAINT_OUTEPINT0_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT0_Pos) /*!< Bit mask of OUTEPINT0 field.             */
89521   #define USBHSCORE_DAINT_OUTEPINT0_Min (0x0UL)      /*!< Min enumerator value of OUTEPINT0 field.                             */
89522   #define USBHSCORE_DAINT_OUTEPINT0_Max (0x1UL)      /*!< Max enumerator value of OUTEPINT0 field.                             */
89523   #define USBHSCORE_DAINT_OUTEPINT0_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89524   #define USBHSCORE_DAINT_OUTEPINT0_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89525 
89526 /* OUTEPINT1 @Bit 17 : OUT Endpoint 1 Interrupt Bit */
89527   #define USBHSCORE_DAINT_OUTEPINT1_Pos (17UL)       /*!< Position of OUTEPINT1 field.                                         */
89528   #define USBHSCORE_DAINT_OUTEPINT1_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT1_Pos) /*!< Bit mask of OUTEPINT1 field.             */
89529   #define USBHSCORE_DAINT_OUTEPINT1_Min (0x0UL)      /*!< Min enumerator value of OUTEPINT1 field.                             */
89530   #define USBHSCORE_DAINT_OUTEPINT1_Max (0x1UL)      /*!< Max enumerator value of OUTEPINT1 field.                             */
89531   #define USBHSCORE_DAINT_OUTEPINT1_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89532   #define USBHSCORE_DAINT_OUTEPINT1_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89533 
89534 /* OUTEPINT2 @Bit 18 : OUT Endpoint 2 Interrupt Bit */
89535   #define USBHSCORE_DAINT_OUTEPINT2_Pos (18UL)       /*!< Position of OUTEPINT2 field.                                         */
89536   #define USBHSCORE_DAINT_OUTEPINT2_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT2_Pos) /*!< Bit mask of OUTEPINT2 field.             */
89537   #define USBHSCORE_DAINT_OUTEPINT2_Min (0x0UL)      /*!< Min enumerator value of OUTEPINT2 field.                             */
89538   #define USBHSCORE_DAINT_OUTEPINT2_Max (0x1UL)      /*!< Max enumerator value of OUTEPINT2 field.                             */
89539   #define USBHSCORE_DAINT_OUTEPINT2_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89540   #define USBHSCORE_DAINT_OUTEPINT2_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89541 
89542 /* OUTEPINT3 @Bit 19 : OUT Endpoint 3 Interrupt Bit */
89543   #define USBHSCORE_DAINT_OUTEPINT3_Pos (19UL)       /*!< Position of OUTEPINT3 field.                                         */
89544   #define USBHSCORE_DAINT_OUTEPINT3_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT3_Pos) /*!< Bit mask of OUTEPINT3 field.             */
89545   #define USBHSCORE_DAINT_OUTEPINT3_Min (0x0UL)      /*!< Min enumerator value of OUTEPINT3 field.                             */
89546   #define USBHSCORE_DAINT_OUTEPINT3_Max (0x1UL)      /*!< Max enumerator value of OUTEPINT3 field.                             */
89547   #define USBHSCORE_DAINT_OUTEPINT3_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89548   #define USBHSCORE_DAINT_OUTEPINT3_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89549 
89550 /* OUTEPINT4 @Bit 20 : OUT Endpoint 4 Interrupt Bit */
89551   #define USBHSCORE_DAINT_OUTEPINT4_Pos (20UL)       /*!< Position of OUTEPINT4 field.                                         */
89552   #define USBHSCORE_DAINT_OUTEPINT4_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT4_Pos) /*!< Bit mask of OUTEPINT4 field.             */
89553   #define USBHSCORE_DAINT_OUTEPINT4_Min (0x0UL)      /*!< Min enumerator value of OUTEPINT4 field.                             */
89554   #define USBHSCORE_DAINT_OUTEPINT4_Max (0x1UL)      /*!< Max enumerator value of OUTEPINT4 field.                             */
89555   #define USBHSCORE_DAINT_OUTEPINT4_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89556   #define USBHSCORE_DAINT_OUTEPINT4_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89557 
89558 /* OUTEPINT5 @Bit 21 : OUT Endpoint 5 Interrupt Bit */
89559   #define USBHSCORE_DAINT_OUTEPINT5_Pos (21UL)       /*!< Position of OUTEPINT5 field.                                         */
89560   #define USBHSCORE_DAINT_OUTEPINT5_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT5_Pos) /*!< Bit mask of OUTEPINT5 field.             */
89561   #define USBHSCORE_DAINT_OUTEPINT5_Min (0x0UL)      /*!< Min enumerator value of OUTEPINT5 field.                             */
89562   #define USBHSCORE_DAINT_OUTEPINT5_Max (0x1UL)      /*!< Max enumerator value of OUTEPINT5 field.                             */
89563   #define USBHSCORE_DAINT_OUTEPINT5_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89564   #define USBHSCORE_DAINT_OUTEPINT5_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89565 
89566 /* OUTEPINT12 @Bit 28 : OUT Endpoint 12 Interrupt Bit */
89567   #define USBHSCORE_DAINT_OUTEPINT12_Pos (28UL)      /*!< Position of OUTEPINT12 field.                                        */
89568   #define USBHSCORE_DAINT_OUTEPINT12_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT12_Pos) /*!< Bit mask of OUTEPINT12 field.          */
89569   #define USBHSCORE_DAINT_OUTEPINT12_Min (0x0UL)     /*!< Min enumerator value of OUTEPINT12 field.                            */
89570   #define USBHSCORE_DAINT_OUTEPINT12_Max (0x1UL)     /*!< Max enumerator value of OUTEPINT12 field.                            */
89571   #define USBHSCORE_DAINT_OUTEPINT12_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
89572   #define USBHSCORE_DAINT_OUTEPINT12_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
89573 
89574 /* OUTEPINT13 @Bit 29 : OUT Endpoint 13 Interrupt Bit */
89575   #define USBHSCORE_DAINT_OUTEPINT13_Pos (29UL)      /*!< Position of OUTEPINT13 field.                                        */
89576   #define USBHSCORE_DAINT_OUTEPINT13_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT13_Pos) /*!< Bit mask of OUTEPINT13 field.          */
89577   #define USBHSCORE_DAINT_OUTEPINT13_Min (0x0UL)     /*!< Min enumerator value of OUTEPINT13 field.                            */
89578   #define USBHSCORE_DAINT_OUTEPINT13_Max (0x1UL)     /*!< Max enumerator value of OUTEPINT13 field.                            */
89579   #define USBHSCORE_DAINT_OUTEPINT13_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
89580   #define USBHSCORE_DAINT_OUTEPINT13_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
89581 
89582 /* OUTEPINT14 @Bit 30 : OUT Endpoint 14 Interrupt Bit */
89583   #define USBHSCORE_DAINT_OUTEPINT14_Pos (30UL)      /*!< Position of OUTEPINT14 field.                                        */
89584   #define USBHSCORE_DAINT_OUTEPINT14_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT14_Pos) /*!< Bit mask of OUTEPINT14 field.          */
89585   #define USBHSCORE_DAINT_OUTEPINT14_Min (0x0UL)     /*!< Min enumerator value of OUTEPINT14 field.                            */
89586   #define USBHSCORE_DAINT_OUTEPINT14_Max (0x1UL)     /*!< Max enumerator value of OUTEPINT14 field.                            */
89587   #define USBHSCORE_DAINT_OUTEPINT14_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
89588   #define USBHSCORE_DAINT_OUTEPINT14_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
89589 
89590 /* OUTEPINT15 @Bit 31 : OUT Endpoint 15 Interrupt Bit */
89591   #define USBHSCORE_DAINT_OUTEPINT15_Pos (31UL)      /*!< Position of OUTEPINT15 field.                                        */
89592   #define USBHSCORE_DAINT_OUTEPINT15_Msk (0x1UL << USBHSCORE_DAINT_OUTEPINT15_Pos) /*!< Bit mask of OUTEPINT15 field.          */
89593   #define USBHSCORE_DAINT_OUTEPINT15_Min (0x0UL)     /*!< Min enumerator value of OUTEPINT15 field.                            */
89594   #define USBHSCORE_DAINT_OUTEPINT15_Max (0x1UL)     /*!< Max enumerator value of OUTEPINT15 field.                            */
89595   #define USBHSCORE_DAINT_OUTEPINT15_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
89596   #define USBHSCORE_DAINT_OUTEPINT15_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
89597 
89598 
89599 /* USBHSCORE_DAINTMSK: Device All Endpoints Interrupt Mask Register */
89600   #define USBHSCORE_DAINTMSK_ResetValue (0x00000000UL) /*!< Reset value of DAINTMSK register.                                  */
89601 
89602 /* INEPMSK0 @Bit 0 : IN Endpoint 0 Interrupt mask Bit */
89603   #define USBHSCORE_DAINTMSK_INEPMSK0_Pos (0UL)      /*!< Position of INEPMSK0 field.                                          */
89604   #define USBHSCORE_DAINTMSK_INEPMSK0_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK0_Pos) /*!< Bit mask of INEPMSK0 field.          */
89605   #define USBHSCORE_DAINTMSK_INEPMSK0_Min (0x0UL)    /*!< Min enumerator value of INEPMSK0 field.                              */
89606   #define USBHSCORE_DAINTMSK_INEPMSK0_Max (0x1UL)    /*!< Max enumerator value of INEPMSK0 field.                              */
89607   #define USBHSCORE_DAINTMSK_INEPMSK0_MASK (0x0UL)   /*!< (unspecified)                                                        */
89608   #define USBHSCORE_DAINTMSK_INEPMSK0_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89609 
89610 /* INEPMSK1 @Bit 1 : IN Endpoint 1 Interrupt mask Bit */
89611   #define USBHSCORE_DAINTMSK_INEPMSK1_Pos (1UL)      /*!< Position of INEPMSK1 field.                                          */
89612   #define USBHSCORE_DAINTMSK_INEPMSK1_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK1_Pos) /*!< Bit mask of INEPMSK1 field.          */
89613   #define USBHSCORE_DAINTMSK_INEPMSK1_Min (0x0UL)    /*!< Min enumerator value of INEPMSK1 field.                              */
89614   #define USBHSCORE_DAINTMSK_INEPMSK1_Max (0x1UL)    /*!< Max enumerator value of INEPMSK1 field.                              */
89615   #define USBHSCORE_DAINTMSK_INEPMSK1_MASK (0x0UL)   /*!< (unspecified)                                                        */
89616   #define USBHSCORE_DAINTMSK_INEPMSK1_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89617 
89618 /* INEPMSK2 @Bit 2 : IN Endpoint 2 Interrupt mask Bit */
89619   #define USBHSCORE_DAINTMSK_INEPMSK2_Pos (2UL)      /*!< Position of INEPMSK2 field.                                          */
89620   #define USBHSCORE_DAINTMSK_INEPMSK2_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK2_Pos) /*!< Bit mask of INEPMSK2 field.          */
89621   #define USBHSCORE_DAINTMSK_INEPMSK2_Min (0x0UL)    /*!< Min enumerator value of INEPMSK2 field.                              */
89622   #define USBHSCORE_DAINTMSK_INEPMSK2_Max (0x1UL)    /*!< Max enumerator value of INEPMSK2 field.                              */
89623   #define USBHSCORE_DAINTMSK_INEPMSK2_MASK (0x0UL)   /*!< (unspecified)                                                        */
89624   #define USBHSCORE_DAINTMSK_INEPMSK2_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89625 
89626 /* INEPMSK3 @Bit 3 : IN Endpoint 3 Interrupt mask Bit */
89627   #define USBHSCORE_DAINTMSK_INEPMSK3_Pos (3UL)      /*!< Position of INEPMSK3 field.                                          */
89628   #define USBHSCORE_DAINTMSK_INEPMSK3_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK3_Pos) /*!< Bit mask of INEPMSK3 field.          */
89629   #define USBHSCORE_DAINTMSK_INEPMSK3_Min (0x0UL)    /*!< Min enumerator value of INEPMSK3 field.                              */
89630   #define USBHSCORE_DAINTMSK_INEPMSK3_Max (0x1UL)    /*!< Max enumerator value of INEPMSK3 field.                              */
89631   #define USBHSCORE_DAINTMSK_INEPMSK3_MASK (0x0UL)   /*!< (unspecified)                                                        */
89632   #define USBHSCORE_DAINTMSK_INEPMSK3_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89633 
89634 /* INEPMSK4 @Bit 4 : IN Endpoint 4 Interrupt mask Bit */
89635   #define USBHSCORE_DAINTMSK_INEPMSK4_Pos (4UL)      /*!< Position of INEPMSK4 field.                                          */
89636   #define USBHSCORE_DAINTMSK_INEPMSK4_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK4_Pos) /*!< Bit mask of INEPMSK4 field.          */
89637   #define USBHSCORE_DAINTMSK_INEPMSK4_Min (0x0UL)    /*!< Min enumerator value of INEPMSK4 field.                              */
89638   #define USBHSCORE_DAINTMSK_INEPMSK4_Max (0x1UL)    /*!< Max enumerator value of INEPMSK4 field.                              */
89639   #define USBHSCORE_DAINTMSK_INEPMSK4_MASK (0x0UL)   /*!< (unspecified)                                                        */
89640   #define USBHSCORE_DAINTMSK_INEPMSK4_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89641 
89642 /* INEPMSK5 @Bit 5 : IN Endpoint 5 Interrupt mask Bit */
89643   #define USBHSCORE_DAINTMSK_INEPMSK5_Pos (5UL)      /*!< Position of INEPMSK5 field.                                          */
89644   #define USBHSCORE_DAINTMSK_INEPMSK5_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK5_Pos) /*!< Bit mask of INEPMSK5 field.          */
89645   #define USBHSCORE_DAINTMSK_INEPMSK5_Min (0x0UL)    /*!< Min enumerator value of INEPMSK5 field.                              */
89646   #define USBHSCORE_DAINTMSK_INEPMSK5_Max (0x1UL)    /*!< Max enumerator value of INEPMSK5 field.                              */
89647   #define USBHSCORE_DAINTMSK_INEPMSK5_MASK (0x0UL)   /*!< (unspecified)                                                        */
89648   #define USBHSCORE_DAINTMSK_INEPMSK5_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89649 
89650 /* INEPMSK6 @Bit 6 : IN Endpoint 6 Interrupt mask Bit */
89651   #define USBHSCORE_DAINTMSK_INEPMSK6_Pos (6UL)      /*!< Position of INEPMSK6 field.                                          */
89652   #define USBHSCORE_DAINTMSK_INEPMSK6_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK6_Pos) /*!< Bit mask of INEPMSK6 field.          */
89653   #define USBHSCORE_DAINTMSK_INEPMSK6_Min (0x0UL)    /*!< Min enumerator value of INEPMSK6 field.                              */
89654   #define USBHSCORE_DAINTMSK_INEPMSK6_Max (0x1UL)    /*!< Max enumerator value of INEPMSK6 field.                              */
89655   #define USBHSCORE_DAINTMSK_INEPMSK6_MASK (0x0UL)   /*!< (unspecified)                                                        */
89656   #define USBHSCORE_DAINTMSK_INEPMSK6_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89657 
89658 /* INEPMSK7 @Bit 7 : IN Endpoint 7 Interrupt mask Bit */
89659   #define USBHSCORE_DAINTMSK_INEPMSK7_Pos (7UL)      /*!< Position of INEPMSK7 field.                                          */
89660   #define USBHSCORE_DAINTMSK_INEPMSK7_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK7_Pos) /*!< Bit mask of INEPMSK7 field.          */
89661   #define USBHSCORE_DAINTMSK_INEPMSK7_Min (0x0UL)    /*!< Min enumerator value of INEPMSK7 field.                              */
89662   #define USBHSCORE_DAINTMSK_INEPMSK7_Max (0x1UL)    /*!< Max enumerator value of INEPMSK7 field.                              */
89663   #define USBHSCORE_DAINTMSK_INEPMSK7_MASK (0x0UL)   /*!< (unspecified)                                                        */
89664   #define USBHSCORE_DAINTMSK_INEPMSK7_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89665 
89666 /* INEPMSK8 @Bit 8 : IN Endpoint 8 Interrupt mask Bit */
89667   #define USBHSCORE_DAINTMSK_INEPMSK8_Pos (8UL)      /*!< Position of INEPMSK8 field.                                          */
89668   #define USBHSCORE_DAINTMSK_INEPMSK8_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK8_Pos) /*!< Bit mask of INEPMSK8 field.          */
89669   #define USBHSCORE_DAINTMSK_INEPMSK8_Min (0x0UL)    /*!< Min enumerator value of INEPMSK8 field.                              */
89670   #define USBHSCORE_DAINTMSK_INEPMSK8_Max (0x1UL)    /*!< Max enumerator value of INEPMSK8 field.                              */
89671   #define USBHSCORE_DAINTMSK_INEPMSK8_MASK (0x0UL)   /*!< (unspecified)                                                        */
89672   #define USBHSCORE_DAINTMSK_INEPMSK8_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89673 
89674 /* INEPMSK9 @Bit 9 : IN Endpoint 9 Interrupt mask Bit */
89675   #define USBHSCORE_DAINTMSK_INEPMSK9_Pos (9UL)      /*!< Position of INEPMSK9 field.                                          */
89676   #define USBHSCORE_DAINTMSK_INEPMSK9_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK9_Pos) /*!< Bit mask of INEPMSK9 field.          */
89677   #define USBHSCORE_DAINTMSK_INEPMSK9_Min (0x0UL)    /*!< Min enumerator value of INEPMSK9 field.                              */
89678   #define USBHSCORE_DAINTMSK_INEPMSK9_Max (0x1UL)    /*!< Max enumerator value of INEPMSK9 field.                              */
89679   #define USBHSCORE_DAINTMSK_INEPMSK9_MASK (0x0UL)   /*!< (unspecified)                                                        */
89680   #define USBHSCORE_DAINTMSK_INEPMSK9_NOMASK (0x1UL) /*!< (unspecified)                                                        */
89681 
89682 /* INEPMSK10 @Bit 10 : IN Endpoint 10 Interrupt mask Bit */
89683   #define USBHSCORE_DAINTMSK_INEPMSK10_Pos (10UL)    /*!< Position of INEPMSK10 field.                                         */
89684   #define USBHSCORE_DAINTMSK_INEPMSK10_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK10_Pos) /*!< Bit mask of INEPMSK10 field.       */
89685   #define USBHSCORE_DAINTMSK_INEPMSK10_Min (0x0UL)   /*!< Min enumerator value of INEPMSK10 field.                             */
89686   #define USBHSCORE_DAINTMSK_INEPMSK10_Max (0x1UL)   /*!< Max enumerator value of INEPMSK10 field.                             */
89687   #define USBHSCORE_DAINTMSK_INEPMSK10_MASK (0x0UL)  /*!< (unspecified)                                                        */
89688   #define USBHSCORE_DAINTMSK_INEPMSK10_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89689 
89690 /* INEPMSK11 @Bit 11 : IN Endpoint 11 Interrupt mask Bit */
89691   #define USBHSCORE_DAINTMSK_INEPMSK11_Pos (11UL)    /*!< Position of INEPMSK11 field.                                         */
89692   #define USBHSCORE_DAINTMSK_INEPMSK11_Msk (0x1UL << USBHSCORE_DAINTMSK_INEPMSK11_Pos) /*!< Bit mask of INEPMSK11 field.       */
89693   #define USBHSCORE_DAINTMSK_INEPMSK11_Min (0x0UL)   /*!< Min enumerator value of INEPMSK11 field.                             */
89694   #define USBHSCORE_DAINTMSK_INEPMSK11_Max (0x1UL)   /*!< Max enumerator value of INEPMSK11 field.                             */
89695   #define USBHSCORE_DAINTMSK_INEPMSK11_MASK (0x0UL)  /*!< (unspecified)                                                        */
89696   #define USBHSCORE_DAINTMSK_INEPMSK11_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89697 
89698 /* OUTEPMSK0 @Bit 16 : OUT Endpoint 0 Interrupt mask Bit */
89699   #define USBHSCORE_DAINTMSK_OUTEPMSK0_Pos (16UL)    /*!< Position of OUTEPMSK0 field.                                         */
89700   #define USBHSCORE_DAINTMSK_OUTEPMSK0_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK0_Pos) /*!< Bit mask of OUTEPMSK0 field.       */
89701   #define USBHSCORE_DAINTMSK_OUTEPMSK0_Min (0x0UL)   /*!< Min enumerator value of OUTEPMSK0 field.                             */
89702   #define USBHSCORE_DAINTMSK_OUTEPMSK0_Max (0x1UL)   /*!< Max enumerator value of OUTEPMSK0 field.                             */
89703   #define USBHSCORE_DAINTMSK_OUTEPMSK0_MASK (0x0UL)  /*!< (unspecified)                                                        */
89704   #define USBHSCORE_DAINTMSK_OUTEPMSK0_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89705 
89706 /* OUTEPMSK1 @Bit 17 : OUT Endpoint 1 Interrupt mask Bit */
89707   #define USBHSCORE_DAINTMSK_OUTEPMSK1_Pos (17UL)    /*!< Position of OUTEPMSK1 field.                                         */
89708   #define USBHSCORE_DAINTMSK_OUTEPMSK1_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK1_Pos) /*!< Bit mask of OUTEPMSK1 field.       */
89709   #define USBHSCORE_DAINTMSK_OUTEPMSK1_Min (0x0UL)   /*!< Min enumerator value of OUTEPMSK1 field.                             */
89710   #define USBHSCORE_DAINTMSK_OUTEPMSK1_Max (0x1UL)   /*!< Max enumerator value of OUTEPMSK1 field.                             */
89711   #define USBHSCORE_DAINTMSK_OUTEPMSK1_MASK (0x0UL)  /*!< (unspecified)                                                        */
89712   #define USBHSCORE_DAINTMSK_OUTEPMSK1_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89713 
89714 /* OUTEPMSK2 @Bit 18 : OUT Endpoint 2 Interrupt mask Bit */
89715   #define USBHSCORE_DAINTMSK_OUTEPMSK2_Pos (18UL)    /*!< Position of OUTEPMSK2 field.                                         */
89716   #define USBHSCORE_DAINTMSK_OUTEPMSK2_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK2_Pos) /*!< Bit mask of OUTEPMSK2 field.       */
89717   #define USBHSCORE_DAINTMSK_OUTEPMSK2_Min (0x0UL)   /*!< Min enumerator value of OUTEPMSK2 field.                             */
89718   #define USBHSCORE_DAINTMSK_OUTEPMSK2_Max (0x1UL)   /*!< Max enumerator value of OUTEPMSK2 field.                             */
89719   #define USBHSCORE_DAINTMSK_OUTEPMSK2_MASK (0x0UL)  /*!< (unspecified)                                                        */
89720   #define USBHSCORE_DAINTMSK_OUTEPMSK2_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89721 
89722 /* OUTEPMSK3 @Bit 19 : OUT Endpoint 3 Interrupt mask Bit */
89723   #define USBHSCORE_DAINTMSK_OUTEPMSK3_Pos (19UL)    /*!< Position of OUTEPMSK3 field.                                         */
89724   #define USBHSCORE_DAINTMSK_OUTEPMSK3_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK3_Pos) /*!< Bit mask of OUTEPMSK3 field.       */
89725   #define USBHSCORE_DAINTMSK_OUTEPMSK3_Min (0x0UL)   /*!< Min enumerator value of OUTEPMSK3 field.                             */
89726   #define USBHSCORE_DAINTMSK_OUTEPMSK3_Max (0x1UL)   /*!< Max enumerator value of OUTEPMSK3 field.                             */
89727   #define USBHSCORE_DAINTMSK_OUTEPMSK3_MASK (0x0UL)  /*!< (unspecified)                                                        */
89728   #define USBHSCORE_DAINTMSK_OUTEPMSK3_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89729 
89730 /* OUTEPMSK4 @Bit 20 : OUT Endpoint 4 Interrupt mask Bit */
89731   #define USBHSCORE_DAINTMSK_OUTEPMSK4_Pos (20UL)    /*!< Position of OUTEPMSK4 field.                                         */
89732   #define USBHSCORE_DAINTMSK_OUTEPMSK4_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK4_Pos) /*!< Bit mask of OUTEPMSK4 field.       */
89733   #define USBHSCORE_DAINTMSK_OUTEPMSK4_Min (0x0UL)   /*!< Min enumerator value of OUTEPMSK4 field.                             */
89734   #define USBHSCORE_DAINTMSK_OUTEPMSK4_Max (0x1UL)   /*!< Max enumerator value of OUTEPMSK4 field.                             */
89735   #define USBHSCORE_DAINTMSK_OUTEPMSK4_MASK (0x0UL)  /*!< (unspecified)                                                        */
89736   #define USBHSCORE_DAINTMSK_OUTEPMSK4_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89737 
89738 /* OUTEPMSK5 @Bit 21 : OUT Endpoint 5 Interrupt mask Bit */
89739   #define USBHSCORE_DAINTMSK_OUTEPMSK5_Pos (21UL)    /*!< Position of OUTEPMSK5 field.                                         */
89740   #define USBHSCORE_DAINTMSK_OUTEPMSK5_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK5_Pos) /*!< Bit mask of OUTEPMSK5 field.       */
89741   #define USBHSCORE_DAINTMSK_OUTEPMSK5_Min (0x0UL)   /*!< Min enumerator value of OUTEPMSK5 field.                             */
89742   #define USBHSCORE_DAINTMSK_OUTEPMSK5_Max (0x1UL)   /*!< Max enumerator value of OUTEPMSK5 field.                             */
89743   #define USBHSCORE_DAINTMSK_OUTEPMSK5_MASK (0x0UL)  /*!< (unspecified)                                                        */
89744   #define USBHSCORE_DAINTMSK_OUTEPMSK5_NOMASK (0x1UL) /*!< (unspecified)                                                       */
89745 
89746 /* OUTEPMSK12 @Bit 28 : OUT Endpoint 12 Interrupt mask Bit */
89747   #define USBHSCORE_DAINTMSK_OUTEPMSK12_Pos (28UL)   /*!< Position of OUTEPMSK12 field.                                        */
89748   #define USBHSCORE_DAINTMSK_OUTEPMSK12_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK12_Pos) /*!< Bit mask of OUTEPMSK12 field.    */
89749   #define USBHSCORE_DAINTMSK_OUTEPMSK12_Min (0x0UL)  /*!< Min enumerator value of OUTEPMSK12 field.                            */
89750   #define USBHSCORE_DAINTMSK_OUTEPMSK12_Max (0x1UL)  /*!< Max enumerator value of OUTEPMSK12 field.                            */
89751   #define USBHSCORE_DAINTMSK_OUTEPMSK12_MASK (0x0UL) /*!< (unspecified)                                                        */
89752   #define USBHSCORE_DAINTMSK_OUTEPMSK12_NOMASK (0x1UL) /*!< (unspecified)                                                      */
89753 
89754 /* OUTEPMSK13 @Bit 29 : OUT Endpoint 13 Interrupt mask Bit */
89755   #define USBHSCORE_DAINTMSK_OUTEPMSK13_Pos (29UL)   /*!< Position of OUTEPMSK13 field.                                        */
89756   #define USBHSCORE_DAINTMSK_OUTEPMSK13_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK13_Pos) /*!< Bit mask of OUTEPMSK13 field.    */
89757   #define USBHSCORE_DAINTMSK_OUTEPMSK13_Min (0x0UL)  /*!< Min enumerator value of OUTEPMSK13 field.                            */
89758   #define USBHSCORE_DAINTMSK_OUTEPMSK13_Max (0x1UL)  /*!< Max enumerator value of OUTEPMSK13 field.                            */
89759   #define USBHSCORE_DAINTMSK_OUTEPMSK13_MASK (0x0UL) /*!< (unspecified)                                                        */
89760   #define USBHSCORE_DAINTMSK_OUTEPMSK13_NOMASK (0x1UL) /*!< (unspecified)                                                      */
89761 
89762 /* OUTEPMSK14 @Bit 30 : OUT Endpoint 14 Interrupt mask Bit */
89763   #define USBHSCORE_DAINTMSK_OUTEPMSK14_Pos (30UL)   /*!< Position of OUTEPMSK14 field.                                        */
89764   #define USBHSCORE_DAINTMSK_OUTEPMSK14_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK14_Pos) /*!< Bit mask of OUTEPMSK14 field.    */
89765   #define USBHSCORE_DAINTMSK_OUTEPMSK14_Min (0x0UL)  /*!< Min enumerator value of OUTEPMSK14 field.                            */
89766   #define USBHSCORE_DAINTMSK_OUTEPMSK14_Max (0x1UL)  /*!< Max enumerator value of OUTEPMSK14 field.                            */
89767   #define USBHSCORE_DAINTMSK_OUTEPMSK14_MASK (0x0UL) /*!< (unspecified)                                                        */
89768   #define USBHSCORE_DAINTMSK_OUTEPMSK14_NOMASK (0x1UL) /*!< (unspecified)                                                      */
89769 
89770 /* OUTEPMSK15 @Bit 31 : OUT Endpoint 15 Interrupt mask Bit */
89771   #define USBHSCORE_DAINTMSK_OUTEPMSK15_Pos (31UL)   /*!< Position of OUTEPMSK15 field.                                        */
89772   #define USBHSCORE_DAINTMSK_OUTEPMSK15_Msk (0x1UL << USBHSCORE_DAINTMSK_OUTEPMSK15_Pos) /*!< Bit mask of OUTEPMSK15 field.    */
89773   #define USBHSCORE_DAINTMSK_OUTEPMSK15_Min (0x0UL)  /*!< Min enumerator value of OUTEPMSK15 field.                            */
89774   #define USBHSCORE_DAINTMSK_OUTEPMSK15_Max (0x1UL)  /*!< Max enumerator value of OUTEPMSK15 field.                            */
89775   #define USBHSCORE_DAINTMSK_OUTEPMSK15_MASK (0x0UL) /*!< (unspecified)                                                        */
89776   #define USBHSCORE_DAINTMSK_OUTEPMSK15_NOMASK (0x1UL) /*!< (unspecified)                                                      */
89777 
89778 
89779 /* USBHSCORE_DVBUSDIS: Device VBUS Discharge Time Register */
89780   #define USBHSCORE_DVBUSDIS_ResetValue (0x000017D7UL) /*!< Reset value of DVBUSDIS register.                                  */
89781 
89782 /* DVBUSDIS @Bits 0..15 : Device VBUS Discharge Time (DVBUSDis) */
89783   #define USBHSCORE_DVBUSDIS_DVBUSDIS_Pos (0UL)      /*!< Position of DVBUSDIS field.                                          */
89784   #define USBHSCORE_DVBUSDIS_DVBUSDIS_Msk (0xFFFFUL << USBHSCORE_DVBUSDIS_DVBUSDIS_Pos) /*!< Bit mask of DVBUSDIS field.       */
89785 
89786 
89787 /* USBHSCORE_DVBUSPULSE: Device VBUS Pulsing Time Register */
89788   #define USBHSCORE_DVBUSPULSE_ResetValue (0x000005B8UL) /*!< Reset value of DVBUSPULSE register.                              */
89789 
89790 /* DVBUSPULSE @Bits 0..11 : Device VBUS Pulsing Time (DVBUSPulse) */
89791   #define USBHSCORE_DVBUSPULSE_DVBUSPULSE_Pos (0UL)  /*!< Position of DVBUSPULSE field.                                        */
89792   #define USBHSCORE_DVBUSPULSE_DVBUSPULSE_Msk (0xFFFUL << USBHSCORE_DVBUSPULSE_DVBUSPULSE_Pos) /*!< Bit mask of DVBUSPULSE
89793                                                                             field.*/
89794 
89795 
89796 /* USBHSCORE_DTHRCTL: Device Threshold Control Register */
89797   #define USBHSCORE_DTHRCTL_ResetValue (0x08100020UL) /*!< Reset value of DTHRCTL register.                                    */
89798 
89799 /* NONISOTHREN @Bit 0 : Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) */
89800   #define USBHSCORE_DTHRCTL_NONISOTHREN_Pos (0UL)    /*!< Position of NONISOTHREN field.                                       */
89801   #define USBHSCORE_DTHRCTL_NONISOTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_NONISOTHREN_Pos) /*!< Bit mask of NONISOTHREN field.   */
89802   #define USBHSCORE_DTHRCTL_NONISOTHREN_Min (0x0UL)  /*!< Min enumerator value of NONISOTHREN field.                           */
89803   #define USBHSCORE_DTHRCTL_NONISOTHREN_Max (0x1UL)  /*!< Max enumerator value of NONISOTHREN field.                           */
89804   #define USBHSCORE_DTHRCTL_NONISOTHREN_DISABLED (0x0UL) /*!< (unspecified)                                                    */
89805   #define USBHSCORE_DTHRCTL_NONISOTHREN_ENABLED (0x1UL) /*!< (unspecified)                                                     */
89806 
89807 /* ISOTHREN @Bit 1 : ISO IN Endpoints Threshold Enable. (ISOThrEn) */
89808   #define USBHSCORE_DTHRCTL_ISOTHREN_Pos (1UL)       /*!< Position of ISOTHREN field.                                          */
89809   #define USBHSCORE_DTHRCTL_ISOTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_ISOTHREN_Pos) /*!< Bit mask of ISOTHREN field.            */
89810   #define USBHSCORE_DTHRCTL_ISOTHREN_Min (0x0UL)     /*!< Min enumerator value of ISOTHREN field.                              */
89811   #define USBHSCORE_DTHRCTL_ISOTHREN_Max (0x1UL)     /*!< Max enumerator value of ISOTHREN field.                              */
89812   #define USBHSCORE_DTHRCTL_ISOTHREN_DISABLED (0x0UL) /*!< (unspecified)                                                       */
89813   #define USBHSCORE_DTHRCTL_ISOTHREN_ENABLED (0x1UL) /*!< (unspecified)                                                        */
89814 
89815 /* TXTHRLEN @Bits 2..10 : Transmit Threshold Length (TxThrLen) */
89816   #define USBHSCORE_DTHRCTL_TXTHRLEN_Pos (2UL)       /*!< Position of TXTHRLEN field.                                          */
89817   #define USBHSCORE_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USBHSCORE_DTHRCTL_TXTHRLEN_Pos) /*!< Bit mask of TXTHRLEN field.          */
89818 
89819 /* AHBTHRRATIO @Bits 11..12 : AHB Threshold Ratio (AHBThrRatio) */
89820   #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Pos (11UL)   /*!< Position of AHBTHRRATIO field.                                       */
89821   #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Msk (0x3UL << USBHSCORE_DTHRCTL_AHBTHRRATIO_Pos) /*!< Bit mask of AHBTHRRATIO field.   */
89822   #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Min (0x0UL)  /*!< Min enumerator value of AHBTHRRATIO field.                           */
89823   #define USBHSCORE_DTHRCTL_AHBTHRRATIO_Max (0x3UL)  /*!< Max enumerator value of AHBTHRRATIO field.                           */
89824   #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESZERO (0x0UL) /*!< (unspecified)                                                   */
89825   #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESONE (0x1UL) /*!< (unspecified)                                                    */
89826   #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESTWO (0x2UL) /*!< (unspecified)                                                    */
89827   #define USBHSCORE_DTHRCTL_AHBTHRRATIO_THRESTHREE (0x3UL) /*!< (unspecified)                                                  */
89828 
89829 /* RXTHREN @Bit 16 : Receive Threshold Enable (RxThrEn) */
89830   #define USBHSCORE_DTHRCTL_RXTHREN_Pos (16UL)       /*!< Position of RXTHREN field.                                           */
89831   #define USBHSCORE_DTHRCTL_RXTHREN_Msk (0x1UL << USBHSCORE_DTHRCTL_RXTHREN_Pos) /*!< Bit mask of RXTHREN field.               */
89832   #define USBHSCORE_DTHRCTL_RXTHREN_Min (0x0UL)      /*!< Min enumerator value of RXTHREN field.                               */
89833   #define USBHSCORE_DTHRCTL_RXTHREN_Max (0x1UL)      /*!< Max enumerator value of RXTHREN field.                               */
89834   #define USBHSCORE_DTHRCTL_RXTHREN_DISABLED (0x0UL) /*!< (unspecified)                                                        */
89835   #define USBHSCORE_DTHRCTL_RXTHREN_ENABLED (0x1UL)  /*!< (unspecified)                                                        */
89836 
89837 /* RXTHRLEN @Bits 17..25 : Receive Threshold Length (RxThrLen) */
89838   #define USBHSCORE_DTHRCTL_RXTHRLEN_Pos (17UL)      /*!< Position of RXTHRLEN field.                                          */
89839   #define USBHSCORE_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USBHSCORE_DTHRCTL_RXTHRLEN_Pos) /*!< Bit mask of RXTHRLEN field.          */
89840 
89841 /* ARBPRKEN @Bit 27 : Arbiter Parking Enable (ArbPrkEn) */
89842   #define USBHSCORE_DTHRCTL_ARBPRKEN_Pos (27UL)      /*!< Position of ARBPRKEN field.                                          */
89843   #define USBHSCORE_DTHRCTL_ARBPRKEN_Msk (0x1UL << USBHSCORE_DTHRCTL_ARBPRKEN_Pos) /*!< Bit mask of ARBPRKEN field.            */
89844   #define USBHSCORE_DTHRCTL_ARBPRKEN_Min (0x0UL)     /*!< Min enumerator value of ARBPRKEN field.                              */
89845   #define USBHSCORE_DTHRCTL_ARBPRKEN_Max (0x1UL)     /*!< Max enumerator value of ARBPRKEN field.                              */
89846   #define USBHSCORE_DTHRCTL_ARBPRKEN_DISABLED (0x0UL) /*!< (unspecified)                                                       */
89847   #define USBHSCORE_DTHRCTL_ARBPRKEN_ENABLED (0x1UL) /*!< (unspecified)                                                        */
89848 
89849 
89850 /* USBHSCORE_DIEPEMPMSK: Device IN Endpoint FIFO Empty Interrupt Mask Register */
89851   #define USBHSCORE_DIEPEMPMSK_ResetValue (0x00000000UL) /*!< Reset value of DIEPEMPMSK register.                              */
89852 
89853 /* INEPTXFEMPMSK @Bits 0..15 : IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk) */
89854   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Pos (0UL) /*!< Position of INEPTXFEMPMSK field.                                   */
89855   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Msk (0xFFFFUL << USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Pos) /*!< Bit mask of
89856                                                                             INEPTXFEMPMSK field.*/
89857   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Min (0x1UL) /*!< Min enumerator value of INEPTXFEMPMSK field.                     */
89858   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_Max (0x8000UL) /*!< Max enumerator value of INEPTXFEMPMSK field.                  */
89859   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP0_MASK (0x0001UL) /*!< (unspecified)                                            */
89860   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP1_MASK (0x0002UL) /*!< (unspecified)                                            */
89861   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP2_MASK (0x0004UL) /*!< (unspecified)                                            */
89862   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP3_MASK (0x0008UL) /*!< (unspecified)                                            */
89863   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP4_MASK (0x0010UL) /*!< (unspecified)                                            */
89864   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP5_MASK (0x0020UL) /*!< (unspecified)                                            */
89865   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP6_MASK (0x0040UL) /*!< (unspecified)                                            */
89866   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP7_MASK (0x0080UL) /*!< (unspecified)                                            */
89867   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP8_MASK (0x0100UL) /*!< (unspecified)                                            */
89868   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP9_MASK (0x0200UL) /*!< (unspecified)                                            */
89869   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP10_MASK (0x0400UL) /*!< (unspecified)                                           */
89870   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP11_MASK (0x0800UL) /*!< (unspecified)                                           */
89871   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP12_MASK (0x1000UL) /*!< (unspecified)                                           */
89872   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP13_MASK (0x2000UL) /*!< (unspecified)                                           */
89873   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP14_MASK (0x4000UL) /*!< (unspecified)                                           */
89874   #define USBHSCORE_DIEPEMPMSK_INEPTXFEMPMSK_EP15_MASK (0x8000UL) /*!< (unspecified)                                           */
89875 
89876 
89877 /* USBHSCORE_DIEPCTL0: Device Control IN Endpoint 0 Control Register */
89878   #define USBHSCORE_DIEPCTL0_ResetValue (0x00008000UL) /*!< Reset value of DIEPCTL0 register.                                  */
89879 
89880 /* MPS @Bits 0..1 : Maximum Packet Size (MPS) */
89881   #define USBHSCORE_DIEPCTL0_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
89882   #define USBHSCORE_DIEPCTL0_MPS_Msk (0x3UL << USBHSCORE_DIEPCTL0_MPS_Pos) /*!< Bit mask of MPS field.                         */
89883   #define USBHSCORE_DIEPCTL0_MPS_Min (0x0UL)         /*!< Min enumerator value of MPS field.                                   */
89884   #define USBHSCORE_DIEPCTL0_MPS_Max (0x3UL)         /*!< Max enumerator value of MPS field.                                   */
89885   #define USBHSCORE_DIEPCTL0_MPS_BYTES64 (0x0UL)     /*!< (unspecified)                                                        */
89886   #define USBHSCORE_DIEPCTL0_MPS_BYTES32 (0x1UL)     /*!< (unspecified)                                                        */
89887   #define USBHSCORE_DIEPCTL0_MPS_BYTES16 (0x2UL)     /*!< (unspecified)                                                        */
89888   #define USBHSCORE_DIEPCTL0_MPS_BYTES8 (0x3UL)      /*!< (unspecified)                                                        */
89889 
89890 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
89891   #define USBHSCORE_DIEPCTL0_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
89892   #define USBHSCORE_DIEPCTL0_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL0_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
89893   #define USBHSCORE_DIEPCTL0_USBACTEP_Min (0x1UL)    /*!< Min enumerator value of USBACTEP field.                              */
89894   #define USBHSCORE_DIEPCTL0_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
89895   #define USBHSCORE_DIEPCTL0_USBACTEP_ACTIVE0 (0x1UL) /*!< (unspecified)                                                       */
89896 
89897 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
89898   #define USBHSCORE_DIEPCTL0_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
89899   #define USBHSCORE_DIEPCTL0_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL0_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
89900   #define USBHSCORE_DIEPCTL0_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
89901   #define USBHSCORE_DIEPCTL0_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
89902   #define USBHSCORE_DIEPCTL0_NAKSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
89903   #define USBHSCORE_DIEPCTL0_NAKSTS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
89904 
89905 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
89906   #define USBHSCORE_DIEPCTL0_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
89907   #define USBHSCORE_DIEPCTL0_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL0_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
89908   #define USBHSCORE_DIEPCTL0_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
89909   #define USBHSCORE_DIEPCTL0_EPTYPE_Max (0x0UL)      /*!< Max enumerator value of EPTYPE field.                                */
89910   #define USBHSCORE_DIEPCTL0_EPTYPE_ACTIVE (0x0UL)   /*!< (unspecified)                                                        */
89911 
89912 /* STALL @Bit 21 : STALL Handshake (Stall) */
89913   #define USBHSCORE_DIEPCTL0_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
89914   #define USBHSCORE_DIEPCTL0_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL0_STALL_Pos) /*!< Bit mask of STALL field.                   */
89915   #define USBHSCORE_DIEPCTL0_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
89916   #define USBHSCORE_DIEPCTL0_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
89917   #define USBHSCORE_DIEPCTL0_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89918   #define USBHSCORE_DIEPCTL0_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89919 
89920 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
89921   #define USBHSCORE_DIEPCTL0_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
89922   #define USBHSCORE_DIEPCTL0_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL0_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
89923   #define USBHSCORE_DIEPCTL0_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
89924   #define USBHSCORE_DIEPCTL0_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
89925   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
89926   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
89927   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
89928   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
89929   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
89930   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
89931   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
89932   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
89933   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
89934   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
89935   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
89936   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
89937   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
89938   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
89939   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
89940   #define USBHSCORE_DIEPCTL0_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
89941 
89942 /* CNAK @Bit 26 : Clear NAK (CNAK) */
89943   #define USBHSCORE_DIEPCTL0_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
89944   #define USBHSCORE_DIEPCTL0_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL0_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
89945   #define USBHSCORE_DIEPCTL0_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
89946   #define USBHSCORE_DIEPCTL0_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
89947   #define USBHSCORE_DIEPCTL0_CNAK_NOCLEAR (0x0UL)    /*!< (unspecified)                                                        */
89948   #define USBHSCORE_DIEPCTL0_CNAK_CLEAR (0x1UL)      /*!< (unspecified)                                                        */
89949 
89950 /* SNAK @Bit 27 : Set NAK (SNAK) */
89951   #define USBHSCORE_DIEPCTL0_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
89952   #define USBHSCORE_DIEPCTL0_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL0_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
89953   #define USBHSCORE_DIEPCTL0_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
89954   #define USBHSCORE_DIEPCTL0_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
89955   #define USBHSCORE_DIEPCTL0_SNAK_NOSET (0x0UL)      /*!< (unspecified)                                                        */
89956   #define USBHSCORE_DIEPCTL0_SNAK_SET (0x1UL)        /*!< (unspecified)                                                        */
89957 
89958 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
89959   #define USBHSCORE_DIEPCTL0_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
89960   #define USBHSCORE_DIEPCTL0_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL0_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
89961   #define USBHSCORE_DIEPCTL0_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
89962   #define USBHSCORE_DIEPCTL0_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
89963   #define USBHSCORE_DIEPCTL0_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89964   #define USBHSCORE_DIEPCTL0_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89965 
89966 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
89967   #define USBHSCORE_DIEPCTL0_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
89968   #define USBHSCORE_DIEPCTL0_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL0_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
89969   #define USBHSCORE_DIEPCTL0_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
89970   #define USBHSCORE_DIEPCTL0_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
89971   #define USBHSCORE_DIEPCTL0_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
89972   #define USBHSCORE_DIEPCTL0_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
89973 
89974 
89975 /* USBHSCORE_DIEPINT0: Device IN Endpoint 0 Interrupt Register */
89976   #define USBHSCORE_DIEPINT0_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT0 register.                                  */
89977 
89978 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
89979   #define USBHSCORE_DIEPINT0_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
89980   #define USBHSCORE_DIEPINT0_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT0_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
89981   #define USBHSCORE_DIEPINT0_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
89982   #define USBHSCORE_DIEPINT0_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
89983   #define USBHSCORE_DIEPINT0_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
89984   #define USBHSCORE_DIEPINT0_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
89985 
89986 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
89987   #define USBHSCORE_DIEPINT0_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
89988   #define USBHSCORE_DIEPINT0_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT0_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
89989   #define USBHSCORE_DIEPINT0_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
89990   #define USBHSCORE_DIEPINT0_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
89991   #define USBHSCORE_DIEPINT0_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
89992   #define USBHSCORE_DIEPINT0_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
89993 
89994 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
89995   #define USBHSCORE_DIEPINT0_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
89996   #define USBHSCORE_DIEPINT0_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT0_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
89997   #define USBHSCORE_DIEPINT0_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
89998   #define USBHSCORE_DIEPINT0_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
89999   #define USBHSCORE_DIEPINT0_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
90000   #define USBHSCORE_DIEPINT0_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
90001 
90002 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
90003   #define USBHSCORE_DIEPINT0_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
90004   #define USBHSCORE_DIEPINT0_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT0_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
90005   #define USBHSCORE_DIEPINT0_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
90006   #define USBHSCORE_DIEPINT0_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
90007   #define USBHSCORE_DIEPINT0_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90008   #define USBHSCORE_DIEPINT0_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90009 
90010 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
90011   #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
90012   #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT0_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
90013   #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
90014   #define USBHSCORE_DIEPINT0_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
90015   #define USBHSCORE_DIEPINT0_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
90016   #define USBHSCORE_DIEPINT0_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
90017 
90018 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
90019   #define USBHSCORE_DIEPINT0_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
90020   #define USBHSCORE_DIEPINT0_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT0_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
90021   #define USBHSCORE_DIEPINT0_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
90022   #define USBHSCORE_DIEPINT0_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
90023   #define USBHSCORE_DIEPINT0_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90024   #define USBHSCORE_DIEPINT0_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90025 
90026 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
90027   #define USBHSCORE_DIEPINT0_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
90028   #define USBHSCORE_DIEPINT0_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT0_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
90029   #define USBHSCORE_DIEPINT0_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
90030   #define USBHSCORE_DIEPINT0_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
90031   #define USBHSCORE_DIEPINT0_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90032   #define USBHSCORE_DIEPINT0_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90033 
90034 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
90035   #define USBHSCORE_DIEPINT0_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
90036   #define USBHSCORE_DIEPINT0_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT0_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
90037   #define USBHSCORE_DIEPINT0_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
90038   #define USBHSCORE_DIEPINT0_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
90039   #define USBHSCORE_DIEPINT0_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
90040   #define USBHSCORE_DIEPINT0_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
90041 
90042 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
90043   #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
90044   #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT0_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
90045   #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
90046   #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
90047   #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
90048   #define USBHSCORE_DIEPINT0_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
90049 
90050 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
90051   #define USBHSCORE_DIEPINT0_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
90052   #define USBHSCORE_DIEPINT0_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT0_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
90053   #define USBHSCORE_DIEPINT0_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
90054   #define USBHSCORE_DIEPINT0_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
90055   #define USBHSCORE_DIEPINT0_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90056   #define USBHSCORE_DIEPINT0_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90057 
90058 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
90059   #define USBHSCORE_DIEPINT0_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
90060   #define USBHSCORE_DIEPINT0_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT0_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
90061   #define USBHSCORE_DIEPINT0_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
90062   #define USBHSCORE_DIEPINT0_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
90063   #define USBHSCORE_DIEPINT0_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90064   #define USBHSCORE_DIEPINT0_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90065 
90066 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
90067   #define USBHSCORE_DIEPINT0_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
90068   #define USBHSCORE_DIEPINT0_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT0_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
90069   #define USBHSCORE_DIEPINT0_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
90070   #define USBHSCORE_DIEPINT0_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
90071   #define USBHSCORE_DIEPINT0_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90072   #define USBHSCORE_DIEPINT0_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90073 
90074 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
90075   #define USBHSCORE_DIEPINT0_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
90076   #define USBHSCORE_DIEPINT0_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT0_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
90077   #define USBHSCORE_DIEPINT0_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
90078   #define USBHSCORE_DIEPINT0_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
90079   #define USBHSCORE_DIEPINT0_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90080   #define USBHSCORE_DIEPINT0_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90081 
90082 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
90083   #define USBHSCORE_DIEPINT0_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
90084   #define USBHSCORE_DIEPINT0_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT0_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
90085   #define USBHSCORE_DIEPINT0_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
90086   #define USBHSCORE_DIEPINT0_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
90087   #define USBHSCORE_DIEPINT0_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90088   #define USBHSCORE_DIEPINT0_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90089 
90090 
90091 /* USBHSCORE_DIEPTSIZ0: Device IN Endpoint 0 Transfer Size Register */
90092   #define USBHSCORE_DIEPTSIZ0_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ0 register.                                */
90093 
90094 /* XFERSIZE @Bits 0..6 : Transfer Size (XferSize) */
90095   #define USBHSCORE_DIEPTSIZ0_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
90096   #define USBHSCORE_DIEPTSIZ0_XFERSIZE_Msk (0x7FUL << USBHSCORE_DIEPTSIZ0_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.       */
90097 
90098 /* PKTCNT @Bits 19..20 : Packet Count (PktCnt) */
90099   #define USBHSCORE_DIEPTSIZ0_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
90100   #define USBHSCORE_DIEPTSIZ0_PKTCNT_Msk (0x3UL << USBHSCORE_DIEPTSIZ0_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.              */
90101 
90102 
90103 /* USBHSCORE_DIEPDMA0: Device IN Endpoint 0 DMA Address Register */
90104   #define USBHSCORE_DIEPDMA0_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA0 register.                                  */
90105 
90106 /* DMAADDR @Bits 0..31 : DMAAddr */
90107   #define USBHSCORE_DIEPDMA0_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
90108   #define USBHSCORE_DIEPDMA0_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA0_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
90109 
90110 
90111 /* USBHSCORE_DTXFSTS0: Device IN Endpoint Transmit FIFO Status Register 0 */
90112   #define USBHSCORE_DTXFSTS0_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS0 register.                                  */
90113 
90114 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
90115   #define USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
90116   #define USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS0_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
90117                                                                             INEPTXFSPCAVAIL field.*/
90118 
90119 
90120 /* USBHSCORE_DIEPCTL1: Device Control IN Endpoint 1 Control Register */
90121   #define USBHSCORE_DIEPCTL1_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL1 register.                                  */
90122 
90123 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
90124   #define USBHSCORE_DIEPCTL1_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
90125   #define USBHSCORE_DIEPCTL1_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL1_MPS_Pos) /*!< Bit mask of MPS field.                       */
90126 
90127 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
90128   #define USBHSCORE_DIEPCTL1_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
90129   #define USBHSCORE_DIEPCTL1_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL1_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
90130   #define USBHSCORE_DIEPCTL1_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
90131   #define USBHSCORE_DIEPCTL1_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
90132   #define USBHSCORE_DIEPCTL1_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90133   #define USBHSCORE_DIEPCTL1_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90134 
90135 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
90136   #define USBHSCORE_DIEPCTL1_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
90137   #define USBHSCORE_DIEPCTL1_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL1_DPID_Pos) /*!< Bit mask of DPID field.                      */
90138   #define USBHSCORE_DIEPCTL1_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
90139   #define USBHSCORE_DIEPCTL1_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
90140   #define USBHSCORE_DIEPCTL1_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
90141   #define USBHSCORE_DIEPCTL1_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
90142 
90143 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
90144   #define USBHSCORE_DIEPCTL1_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
90145   #define USBHSCORE_DIEPCTL1_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL1_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
90146   #define USBHSCORE_DIEPCTL1_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
90147   #define USBHSCORE_DIEPCTL1_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
90148   #define USBHSCORE_DIEPCTL1_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
90149   #define USBHSCORE_DIEPCTL1_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
90150 
90151 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
90152   #define USBHSCORE_DIEPCTL1_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
90153   #define USBHSCORE_DIEPCTL1_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL1_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
90154   #define USBHSCORE_DIEPCTL1_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
90155   #define USBHSCORE_DIEPCTL1_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
90156   #define USBHSCORE_DIEPCTL1_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
90157   #define USBHSCORE_DIEPCTL1_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
90158   #define USBHSCORE_DIEPCTL1_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
90159   #define USBHSCORE_DIEPCTL1_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
90160 
90161 /* STALL @Bit 21 : STALL Handshake (Stall) */
90162   #define USBHSCORE_DIEPCTL1_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
90163   #define USBHSCORE_DIEPCTL1_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL1_STALL_Pos) /*!< Bit mask of STALL field.                   */
90164   #define USBHSCORE_DIEPCTL1_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
90165   #define USBHSCORE_DIEPCTL1_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
90166   #define USBHSCORE_DIEPCTL1_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90167   #define USBHSCORE_DIEPCTL1_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90168 
90169 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
90170   #define USBHSCORE_DIEPCTL1_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
90171   #define USBHSCORE_DIEPCTL1_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL1_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
90172   #define USBHSCORE_DIEPCTL1_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
90173   #define USBHSCORE_DIEPCTL1_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
90174   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
90175   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
90176   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
90177   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
90178   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
90179   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
90180   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
90181   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
90182   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
90183   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
90184   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
90185   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
90186   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
90187   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
90188   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
90189   #define USBHSCORE_DIEPCTL1_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
90190 
90191 /* CNAK @Bit 26 : Clear NAK (CNAK) */
90192   #define USBHSCORE_DIEPCTL1_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
90193   #define USBHSCORE_DIEPCTL1_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL1_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
90194   #define USBHSCORE_DIEPCTL1_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
90195   #define USBHSCORE_DIEPCTL1_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
90196   #define USBHSCORE_DIEPCTL1_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
90197   #define USBHSCORE_DIEPCTL1_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
90198 
90199 /* SNAK @Bit 27 : Set NAK (SNAK) */
90200   #define USBHSCORE_DIEPCTL1_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
90201   #define USBHSCORE_DIEPCTL1_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL1_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
90202   #define USBHSCORE_DIEPCTL1_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
90203   #define USBHSCORE_DIEPCTL1_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
90204   #define USBHSCORE_DIEPCTL1_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
90205   #define USBHSCORE_DIEPCTL1_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
90206 
90207 /* SETD0PID @Bit 28 : SetD0PID */
90208   #define USBHSCORE_DIEPCTL1_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
90209   #define USBHSCORE_DIEPCTL1_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL1_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
90210   #define USBHSCORE_DIEPCTL1_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
90211   #define USBHSCORE_DIEPCTL1_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
90212   #define USBHSCORE_DIEPCTL1_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90213   #define USBHSCORE_DIEPCTL1_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90214 
90215 /* SETD1PID @Bit 29 : SetD1PID */
90216   #define USBHSCORE_DIEPCTL1_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
90217   #define USBHSCORE_DIEPCTL1_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL1_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
90218   #define USBHSCORE_DIEPCTL1_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
90219   #define USBHSCORE_DIEPCTL1_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
90220   #define USBHSCORE_DIEPCTL1_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90221   #define USBHSCORE_DIEPCTL1_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90222 
90223 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
90224   #define USBHSCORE_DIEPCTL1_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
90225   #define USBHSCORE_DIEPCTL1_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL1_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
90226   #define USBHSCORE_DIEPCTL1_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
90227   #define USBHSCORE_DIEPCTL1_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
90228   #define USBHSCORE_DIEPCTL1_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90229   #define USBHSCORE_DIEPCTL1_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90230 
90231 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
90232   #define USBHSCORE_DIEPCTL1_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
90233   #define USBHSCORE_DIEPCTL1_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL1_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
90234   #define USBHSCORE_DIEPCTL1_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
90235   #define USBHSCORE_DIEPCTL1_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
90236   #define USBHSCORE_DIEPCTL1_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90237   #define USBHSCORE_DIEPCTL1_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90238 
90239 
90240 /* USBHSCORE_DIEPINT1: Device IN Endpoint 1 Interrupt Register */
90241   #define USBHSCORE_DIEPINT1_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT1 register.                                  */
90242 
90243 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
90244   #define USBHSCORE_DIEPINT1_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
90245   #define USBHSCORE_DIEPINT1_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT1_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
90246   #define USBHSCORE_DIEPINT1_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
90247   #define USBHSCORE_DIEPINT1_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
90248   #define USBHSCORE_DIEPINT1_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90249   #define USBHSCORE_DIEPINT1_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90250 
90251 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
90252   #define USBHSCORE_DIEPINT1_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
90253   #define USBHSCORE_DIEPINT1_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT1_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
90254   #define USBHSCORE_DIEPINT1_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
90255   #define USBHSCORE_DIEPINT1_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
90256   #define USBHSCORE_DIEPINT1_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
90257   #define USBHSCORE_DIEPINT1_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
90258 
90259 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
90260   #define USBHSCORE_DIEPINT1_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
90261   #define USBHSCORE_DIEPINT1_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT1_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
90262   #define USBHSCORE_DIEPINT1_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
90263   #define USBHSCORE_DIEPINT1_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
90264   #define USBHSCORE_DIEPINT1_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
90265   #define USBHSCORE_DIEPINT1_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
90266 
90267 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
90268   #define USBHSCORE_DIEPINT1_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
90269   #define USBHSCORE_DIEPINT1_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT1_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
90270   #define USBHSCORE_DIEPINT1_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
90271   #define USBHSCORE_DIEPINT1_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
90272   #define USBHSCORE_DIEPINT1_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90273   #define USBHSCORE_DIEPINT1_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90274 
90275 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
90276   #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
90277   #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT1_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
90278   #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
90279   #define USBHSCORE_DIEPINT1_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
90280   #define USBHSCORE_DIEPINT1_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
90281   #define USBHSCORE_DIEPINT1_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
90282 
90283 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
90284   #define USBHSCORE_DIEPINT1_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
90285   #define USBHSCORE_DIEPINT1_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT1_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
90286   #define USBHSCORE_DIEPINT1_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
90287   #define USBHSCORE_DIEPINT1_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
90288   #define USBHSCORE_DIEPINT1_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90289   #define USBHSCORE_DIEPINT1_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90290 
90291 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
90292   #define USBHSCORE_DIEPINT1_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
90293   #define USBHSCORE_DIEPINT1_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT1_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
90294   #define USBHSCORE_DIEPINT1_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
90295   #define USBHSCORE_DIEPINT1_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
90296   #define USBHSCORE_DIEPINT1_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90297   #define USBHSCORE_DIEPINT1_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90298 
90299 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
90300   #define USBHSCORE_DIEPINT1_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
90301   #define USBHSCORE_DIEPINT1_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT1_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
90302   #define USBHSCORE_DIEPINT1_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
90303   #define USBHSCORE_DIEPINT1_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
90304   #define USBHSCORE_DIEPINT1_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
90305   #define USBHSCORE_DIEPINT1_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
90306 
90307 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
90308   #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
90309   #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT1_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
90310   #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
90311   #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
90312   #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
90313   #define USBHSCORE_DIEPINT1_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
90314 
90315 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
90316   #define USBHSCORE_DIEPINT1_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
90317   #define USBHSCORE_DIEPINT1_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT1_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
90318   #define USBHSCORE_DIEPINT1_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
90319   #define USBHSCORE_DIEPINT1_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
90320   #define USBHSCORE_DIEPINT1_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90321   #define USBHSCORE_DIEPINT1_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90322 
90323 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
90324   #define USBHSCORE_DIEPINT1_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
90325   #define USBHSCORE_DIEPINT1_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT1_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
90326   #define USBHSCORE_DIEPINT1_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
90327   #define USBHSCORE_DIEPINT1_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
90328   #define USBHSCORE_DIEPINT1_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90329   #define USBHSCORE_DIEPINT1_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90330 
90331 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
90332   #define USBHSCORE_DIEPINT1_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
90333   #define USBHSCORE_DIEPINT1_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT1_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
90334   #define USBHSCORE_DIEPINT1_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
90335   #define USBHSCORE_DIEPINT1_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
90336   #define USBHSCORE_DIEPINT1_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90337   #define USBHSCORE_DIEPINT1_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90338 
90339 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
90340   #define USBHSCORE_DIEPINT1_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
90341   #define USBHSCORE_DIEPINT1_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT1_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
90342   #define USBHSCORE_DIEPINT1_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
90343   #define USBHSCORE_DIEPINT1_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
90344   #define USBHSCORE_DIEPINT1_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90345   #define USBHSCORE_DIEPINT1_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90346 
90347 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
90348   #define USBHSCORE_DIEPINT1_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
90349   #define USBHSCORE_DIEPINT1_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT1_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
90350   #define USBHSCORE_DIEPINT1_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
90351   #define USBHSCORE_DIEPINT1_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
90352   #define USBHSCORE_DIEPINT1_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90353   #define USBHSCORE_DIEPINT1_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90354 
90355 
90356 /* USBHSCORE_DIEPTSIZ1: Device IN Endpoint 1 Transfer Size Register */
90357   #define USBHSCORE_DIEPTSIZ1_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ1 register.                                */
90358 
90359 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
90360   #define USBHSCORE_DIEPTSIZ1_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
90361   #define USBHSCORE_DIEPTSIZ1_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ1_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
90362 
90363 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
90364   #define USBHSCORE_DIEPTSIZ1_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
90365   #define USBHSCORE_DIEPTSIZ1_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ1_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
90366 
90367 /* MC @Bits 29..30 : MC */
90368   #define USBHSCORE_DIEPTSIZ1_MC_Pos (29UL)          /*!< Position of MC field.                                                */
90369   #define USBHSCORE_DIEPTSIZ1_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ1_MC_Pos) /*!< Bit mask of MC field.                          */
90370   #define USBHSCORE_DIEPTSIZ1_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
90371   #define USBHSCORE_DIEPTSIZ1_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
90372   #define USBHSCORE_DIEPTSIZ1_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
90373   #define USBHSCORE_DIEPTSIZ1_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
90374   #define USBHSCORE_DIEPTSIZ1_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
90375 
90376 
90377 /* USBHSCORE_DIEPDMA1: Device IN Endpoint 1 DMA Address Register */
90378   #define USBHSCORE_DIEPDMA1_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA1 register.                                  */
90379 
90380 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
90381   #define USBHSCORE_DIEPDMA1_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
90382   #define USBHSCORE_DIEPDMA1_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA1_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
90383 
90384 
90385 /* USBHSCORE_DTXFSTS1: This register reflects the status of the IN Endpoint Transmit FIFO Status Register 1 of the Device
90386                         controller. */
90387 
90388   #define USBHSCORE_DTXFSTS1_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS1 register.                                  */
90389 
90390 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
90391   #define USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
90392   #define USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS1_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
90393                                                                             INEPTXFSPCAVAIL field.*/
90394 
90395 
90396 /* USBHSCORE_DIEPCTL2: Device Control IN Endpoint 2 Control Register */
90397   #define USBHSCORE_DIEPCTL2_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL2 register.                                  */
90398 
90399 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
90400   #define USBHSCORE_DIEPCTL2_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
90401   #define USBHSCORE_DIEPCTL2_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL2_MPS_Pos) /*!< Bit mask of MPS field.                       */
90402 
90403 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
90404   #define USBHSCORE_DIEPCTL2_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
90405   #define USBHSCORE_DIEPCTL2_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL2_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
90406   #define USBHSCORE_DIEPCTL2_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
90407   #define USBHSCORE_DIEPCTL2_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
90408   #define USBHSCORE_DIEPCTL2_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90409   #define USBHSCORE_DIEPCTL2_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90410 
90411 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
90412   #define USBHSCORE_DIEPCTL2_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
90413   #define USBHSCORE_DIEPCTL2_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL2_DPID_Pos) /*!< Bit mask of DPID field.                      */
90414   #define USBHSCORE_DIEPCTL2_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
90415   #define USBHSCORE_DIEPCTL2_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
90416   #define USBHSCORE_DIEPCTL2_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
90417   #define USBHSCORE_DIEPCTL2_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
90418 
90419 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
90420   #define USBHSCORE_DIEPCTL2_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
90421   #define USBHSCORE_DIEPCTL2_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL2_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
90422   #define USBHSCORE_DIEPCTL2_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
90423   #define USBHSCORE_DIEPCTL2_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
90424   #define USBHSCORE_DIEPCTL2_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
90425   #define USBHSCORE_DIEPCTL2_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
90426 
90427 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
90428   #define USBHSCORE_DIEPCTL2_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
90429   #define USBHSCORE_DIEPCTL2_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL2_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
90430   #define USBHSCORE_DIEPCTL2_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
90431   #define USBHSCORE_DIEPCTL2_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
90432   #define USBHSCORE_DIEPCTL2_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
90433   #define USBHSCORE_DIEPCTL2_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
90434   #define USBHSCORE_DIEPCTL2_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
90435   #define USBHSCORE_DIEPCTL2_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
90436 
90437 /* STALL @Bit 21 : STALL Handshake (Stall) */
90438   #define USBHSCORE_DIEPCTL2_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
90439   #define USBHSCORE_DIEPCTL2_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL2_STALL_Pos) /*!< Bit mask of STALL field.                   */
90440   #define USBHSCORE_DIEPCTL2_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
90441   #define USBHSCORE_DIEPCTL2_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
90442   #define USBHSCORE_DIEPCTL2_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90443   #define USBHSCORE_DIEPCTL2_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90444 
90445 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
90446   #define USBHSCORE_DIEPCTL2_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
90447   #define USBHSCORE_DIEPCTL2_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL2_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
90448   #define USBHSCORE_DIEPCTL2_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
90449   #define USBHSCORE_DIEPCTL2_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
90450   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
90451   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
90452   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
90453   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
90454   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
90455   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
90456   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
90457   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
90458   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
90459   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
90460   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
90461   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
90462   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
90463   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
90464   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
90465   #define USBHSCORE_DIEPCTL2_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
90466 
90467 /* CNAK @Bit 26 : Clear NAK (CNAK) */
90468   #define USBHSCORE_DIEPCTL2_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
90469   #define USBHSCORE_DIEPCTL2_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL2_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
90470   #define USBHSCORE_DIEPCTL2_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
90471   #define USBHSCORE_DIEPCTL2_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
90472   #define USBHSCORE_DIEPCTL2_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
90473   #define USBHSCORE_DIEPCTL2_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
90474 
90475 /* SNAK @Bit 27 : Set NAK (SNAK) */
90476   #define USBHSCORE_DIEPCTL2_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
90477   #define USBHSCORE_DIEPCTL2_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL2_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
90478   #define USBHSCORE_DIEPCTL2_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
90479   #define USBHSCORE_DIEPCTL2_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
90480   #define USBHSCORE_DIEPCTL2_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
90481   #define USBHSCORE_DIEPCTL2_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
90482 
90483 /* SETD0PID @Bit 28 : SetD0PID */
90484   #define USBHSCORE_DIEPCTL2_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
90485   #define USBHSCORE_DIEPCTL2_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL2_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
90486   #define USBHSCORE_DIEPCTL2_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
90487   #define USBHSCORE_DIEPCTL2_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
90488   #define USBHSCORE_DIEPCTL2_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90489   #define USBHSCORE_DIEPCTL2_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90490 
90491 /* SETD1PID @Bit 29 : SetD1PID */
90492   #define USBHSCORE_DIEPCTL2_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
90493   #define USBHSCORE_DIEPCTL2_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL2_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
90494   #define USBHSCORE_DIEPCTL2_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
90495   #define USBHSCORE_DIEPCTL2_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
90496   #define USBHSCORE_DIEPCTL2_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90497   #define USBHSCORE_DIEPCTL2_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90498 
90499 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
90500   #define USBHSCORE_DIEPCTL2_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
90501   #define USBHSCORE_DIEPCTL2_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL2_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
90502   #define USBHSCORE_DIEPCTL2_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
90503   #define USBHSCORE_DIEPCTL2_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
90504   #define USBHSCORE_DIEPCTL2_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90505   #define USBHSCORE_DIEPCTL2_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90506 
90507 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
90508   #define USBHSCORE_DIEPCTL2_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
90509   #define USBHSCORE_DIEPCTL2_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL2_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
90510   #define USBHSCORE_DIEPCTL2_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
90511   #define USBHSCORE_DIEPCTL2_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
90512   #define USBHSCORE_DIEPCTL2_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90513   #define USBHSCORE_DIEPCTL2_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90514 
90515 
90516 /* USBHSCORE_DIEPINT2: Device IN Endpoint 2 Interrupt Register */
90517   #define USBHSCORE_DIEPINT2_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT2 register.                                  */
90518 
90519 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
90520   #define USBHSCORE_DIEPINT2_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
90521   #define USBHSCORE_DIEPINT2_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT2_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
90522   #define USBHSCORE_DIEPINT2_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
90523   #define USBHSCORE_DIEPINT2_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
90524   #define USBHSCORE_DIEPINT2_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90525   #define USBHSCORE_DIEPINT2_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90526 
90527 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
90528   #define USBHSCORE_DIEPINT2_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
90529   #define USBHSCORE_DIEPINT2_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT2_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
90530   #define USBHSCORE_DIEPINT2_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
90531   #define USBHSCORE_DIEPINT2_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
90532   #define USBHSCORE_DIEPINT2_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
90533   #define USBHSCORE_DIEPINT2_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
90534 
90535 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
90536   #define USBHSCORE_DIEPINT2_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
90537   #define USBHSCORE_DIEPINT2_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT2_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
90538   #define USBHSCORE_DIEPINT2_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
90539   #define USBHSCORE_DIEPINT2_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
90540   #define USBHSCORE_DIEPINT2_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
90541   #define USBHSCORE_DIEPINT2_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
90542 
90543 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
90544   #define USBHSCORE_DIEPINT2_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
90545   #define USBHSCORE_DIEPINT2_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT2_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
90546   #define USBHSCORE_DIEPINT2_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
90547   #define USBHSCORE_DIEPINT2_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
90548   #define USBHSCORE_DIEPINT2_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90549   #define USBHSCORE_DIEPINT2_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90550 
90551 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
90552   #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
90553   #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT2_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
90554   #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
90555   #define USBHSCORE_DIEPINT2_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
90556   #define USBHSCORE_DIEPINT2_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
90557   #define USBHSCORE_DIEPINT2_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
90558 
90559 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
90560   #define USBHSCORE_DIEPINT2_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
90561   #define USBHSCORE_DIEPINT2_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT2_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
90562   #define USBHSCORE_DIEPINT2_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
90563   #define USBHSCORE_DIEPINT2_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
90564   #define USBHSCORE_DIEPINT2_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90565   #define USBHSCORE_DIEPINT2_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90566 
90567 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
90568   #define USBHSCORE_DIEPINT2_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
90569   #define USBHSCORE_DIEPINT2_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT2_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
90570   #define USBHSCORE_DIEPINT2_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
90571   #define USBHSCORE_DIEPINT2_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
90572   #define USBHSCORE_DIEPINT2_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90573   #define USBHSCORE_DIEPINT2_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90574 
90575 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
90576   #define USBHSCORE_DIEPINT2_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
90577   #define USBHSCORE_DIEPINT2_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT2_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
90578   #define USBHSCORE_DIEPINT2_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
90579   #define USBHSCORE_DIEPINT2_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
90580   #define USBHSCORE_DIEPINT2_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
90581   #define USBHSCORE_DIEPINT2_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
90582 
90583 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
90584   #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
90585   #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT2_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
90586   #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
90587   #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
90588   #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
90589   #define USBHSCORE_DIEPINT2_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
90590 
90591 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
90592   #define USBHSCORE_DIEPINT2_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
90593   #define USBHSCORE_DIEPINT2_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT2_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
90594   #define USBHSCORE_DIEPINT2_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
90595   #define USBHSCORE_DIEPINT2_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
90596   #define USBHSCORE_DIEPINT2_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90597   #define USBHSCORE_DIEPINT2_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90598 
90599 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
90600   #define USBHSCORE_DIEPINT2_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
90601   #define USBHSCORE_DIEPINT2_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT2_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
90602   #define USBHSCORE_DIEPINT2_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
90603   #define USBHSCORE_DIEPINT2_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
90604   #define USBHSCORE_DIEPINT2_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90605   #define USBHSCORE_DIEPINT2_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90606 
90607 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
90608   #define USBHSCORE_DIEPINT2_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
90609   #define USBHSCORE_DIEPINT2_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT2_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
90610   #define USBHSCORE_DIEPINT2_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
90611   #define USBHSCORE_DIEPINT2_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
90612   #define USBHSCORE_DIEPINT2_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90613   #define USBHSCORE_DIEPINT2_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90614 
90615 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
90616   #define USBHSCORE_DIEPINT2_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
90617   #define USBHSCORE_DIEPINT2_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT2_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
90618   #define USBHSCORE_DIEPINT2_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
90619   #define USBHSCORE_DIEPINT2_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
90620   #define USBHSCORE_DIEPINT2_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90621   #define USBHSCORE_DIEPINT2_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90622 
90623 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
90624   #define USBHSCORE_DIEPINT2_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
90625   #define USBHSCORE_DIEPINT2_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT2_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
90626   #define USBHSCORE_DIEPINT2_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
90627   #define USBHSCORE_DIEPINT2_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
90628   #define USBHSCORE_DIEPINT2_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90629   #define USBHSCORE_DIEPINT2_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90630 
90631 
90632 /* USBHSCORE_DIEPTSIZ2: Device IN Endpoint 2 Transfer Size Register */
90633   #define USBHSCORE_DIEPTSIZ2_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ2 register.                                */
90634 
90635 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
90636   #define USBHSCORE_DIEPTSIZ2_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
90637   #define USBHSCORE_DIEPTSIZ2_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ2_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
90638 
90639 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
90640   #define USBHSCORE_DIEPTSIZ2_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
90641   #define USBHSCORE_DIEPTSIZ2_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ2_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
90642 
90643 /* MC @Bits 29..30 : MC */
90644   #define USBHSCORE_DIEPTSIZ2_MC_Pos (29UL)          /*!< Position of MC field.                                                */
90645   #define USBHSCORE_DIEPTSIZ2_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ2_MC_Pos) /*!< Bit mask of MC field.                          */
90646   #define USBHSCORE_DIEPTSIZ2_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
90647   #define USBHSCORE_DIEPTSIZ2_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
90648   #define USBHSCORE_DIEPTSIZ2_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
90649   #define USBHSCORE_DIEPTSIZ2_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
90650   #define USBHSCORE_DIEPTSIZ2_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
90651 
90652 
90653 /* USBHSCORE_DIEPDMA2: Device IN Endpoint 2 DMA Address Register */
90654   #define USBHSCORE_DIEPDMA2_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA2 register.                                  */
90655 
90656 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
90657   #define USBHSCORE_DIEPDMA2_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
90658   #define USBHSCORE_DIEPDMA2_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA2_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
90659 
90660 
90661 /* USBHSCORE_DTXFSTS2: Device IN Endpoint Transmit FIFO Status Register 2 */
90662   #define USBHSCORE_DTXFSTS2_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS2 register.                                  */
90663 
90664 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
90665   #define USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
90666   #define USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS2_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
90667                                                                             INEPTXFSPCAVAIL field.*/
90668 
90669 
90670 /* USBHSCORE_DIEPCTL3: Device Control IN Endpoint 3 Control Register */
90671   #define USBHSCORE_DIEPCTL3_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL3 register.                                  */
90672 
90673 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
90674   #define USBHSCORE_DIEPCTL3_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
90675   #define USBHSCORE_DIEPCTL3_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL3_MPS_Pos) /*!< Bit mask of MPS field.                       */
90676 
90677 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
90678   #define USBHSCORE_DIEPCTL3_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
90679   #define USBHSCORE_DIEPCTL3_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL3_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
90680   #define USBHSCORE_DIEPCTL3_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
90681   #define USBHSCORE_DIEPCTL3_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
90682   #define USBHSCORE_DIEPCTL3_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90683   #define USBHSCORE_DIEPCTL3_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90684 
90685 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
90686   #define USBHSCORE_DIEPCTL3_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
90687   #define USBHSCORE_DIEPCTL3_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL3_DPID_Pos) /*!< Bit mask of DPID field.                      */
90688   #define USBHSCORE_DIEPCTL3_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
90689   #define USBHSCORE_DIEPCTL3_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
90690   #define USBHSCORE_DIEPCTL3_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
90691   #define USBHSCORE_DIEPCTL3_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
90692 
90693 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
90694   #define USBHSCORE_DIEPCTL3_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
90695   #define USBHSCORE_DIEPCTL3_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL3_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
90696   #define USBHSCORE_DIEPCTL3_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
90697   #define USBHSCORE_DIEPCTL3_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
90698   #define USBHSCORE_DIEPCTL3_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
90699   #define USBHSCORE_DIEPCTL3_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
90700 
90701 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
90702   #define USBHSCORE_DIEPCTL3_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
90703   #define USBHSCORE_DIEPCTL3_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL3_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
90704   #define USBHSCORE_DIEPCTL3_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
90705   #define USBHSCORE_DIEPCTL3_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
90706   #define USBHSCORE_DIEPCTL3_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
90707   #define USBHSCORE_DIEPCTL3_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
90708   #define USBHSCORE_DIEPCTL3_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
90709   #define USBHSCORE_DIEPCTL3_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
90710 
90711 /* STALL @Bit 21 : STALL Handshake (Stall) */
90712   #define USBHSCORE_DIEPCTL3_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
90713   #define USBHSCORE_DIEPCTL3_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL3_STALL_Pos) /*!< Bit mask of STALL field.                   */
90714   #define USBHSCORE_DIEPCTL3_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
90715   #define USBHSCORE_DIEPCTL3_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
90716   #define USBHSCORE_DIEPCTL3_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90717   #define USBHSCORE_DIEPCTL3_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90718 
90719 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
90720   #define USBHSCORE_DIEPCTL3_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
90721   #define USBHSCORE_DIEPCTL3_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL3_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
90722   #define USBHSCORE_DIEPCTL3_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
90723   #define USBHSCORE_DIEPCTL3_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
90724   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
90725   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
90726   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
90727   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
90728   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
90729   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
90730   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
90731   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
90732   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
90733   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
90734   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
90735   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
90736   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
90737   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
90738   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
90739   #define USBHSCORE_DIEPCTL3_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
90740 
90741 /* CNAK @Bit 26 : Clear NAK (CNAK) */
90742   #define USBHSCORE_DIEPCTL3_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
90743   #define USBHSCORE_DIEPCTL3_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL3_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
90744   #define USBHSCORE_DIEPCTL3_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
90745   #define USBHSCORE_DIEPCTL3_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
90746   #define USBHSCORE_DIEPCTL3_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
90747   #define USBHSCORE_DIEPCTL3_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
90748 
90749 /* SNAK @Bit 27 : Set NAK (SNAK) */
90750   #define USBHSCORE_DIEPCTL3_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
90751   #define USBHSCORE_DIEPCTL3_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL3_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
90752   #define USBHSCORE_DIEPCTL3_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
90753   #define USBHSCORE_DIEPCTL3_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
90754   #define USBHSCORE_DIEPCTL3_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
90755   #define USBHSCORE_DIEPCTL3_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
90756 
90757 /* SETD0PID @Bit 28 : SetD0PID */
90758   #define USBHSCORE_DIEPCTL3_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
90759   #define USBHSCORE_DIEPCTL3_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL3_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
90760   #define USBHSCORE_DIEPCTL3_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
90761   #define USBHSCORE_DIEPCTL3_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
90762   #define USBHSCORE_DIEPCTL3_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90763   #define USBHSCORE_DIEPCTL3_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90764 
90765 /* SETD1PID @Bit 29 : SetD1PID */
90766   #define USBHSCORE_DIEPCTL3_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
90767   #define USBHSCORE_DIEPCTL3_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL3_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
90768   #define USBHSCORE_DIEPCTL3_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
90769   #define USBHSCORE_DIEPCTL3_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
90770   #define USBHSCORE_DIEPCTL3_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90771   #define USBHSCORE_DIEPCTL3_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90772 
90773 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
90774   #define USBHSCORE_DIEPCTL3_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
90775   #define USBHSCORE_DIEPCTL3_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL3_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
90776   #define USBHSCORE_DIEPCTL3_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
90777   #define USBHSCORE_DIEPCTL3_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
90778   #define USBHSCORE_DIEPCTL3_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90779   #define USBHSCORE_DIEPCTL3_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90780 
90781 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
90782   #define USBHSCORE_DIEPCTL3_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
90783   #define USBHSCORE_DIEPCTL3_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL3_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
90784   #define USBHSCORE_DIEPCTL3_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
90785   #define USBHSCORE_DIEPCTL3_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
90786   #define USBHSCORE_DIEPCTL3_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90787   #define USBHSCORE_DIEPCTL3_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90788 
90789 
90790 /* USBHSCORE_DIEPINT3: Device IN Endpoint 3 Interrupt Register */
90791   #define USBHSCORE_DIEPINT3_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT3 register.                                  */
90792 
90793 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
90794   #define USBHSCORE_DIEPINT3_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
90795   #define USBHSCORE_DIEPINT3_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT3_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
90796   #define USBHSCORE_DIEPINT3_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
90797   #define USBHSCORE_DIEPINT3_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
90798   #define USBHSCORE_DIEPINT3_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90799   #define USBHSCORE_DIEPINT3_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90800 
90801 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
90802   #define USBHSCORE_DIEPINT3_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
90803   #define USBHSCORE_DIEPINT3_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT3_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
90804   #define USBHSCORE_DIEPINT3_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
90805   #define USBHSCORE_DIEPINT3_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
90806   #define USBHSCORE_DIEPINT3_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
90807   #define USBHSCORE_DIEPINT3_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
90808 
90809 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
90810   #define USBHSCORE_DIEPINT3_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
90811   #define USBHSCORE_DIEPINT3_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT3_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
90812   #define USBHSCORE_DIEPINT3_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
90813   #define USBHSCORE_DIEPINT3_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
90814   #define USBHSCORE_DIEPINT3_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
90815   #define USBHSCORE_DIEPINT3_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
90816 
90817 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
90818   #define USBHSCORE_DIEPINT3_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
90819   #define USBHSCORE_DIEPINT3_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT3_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
90820   #define USBHSCORE_DIEPINT3_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
90821   #define USBHSCORE_DIEPINT3_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
90822   #define USBHSCORE_DIEPINT3_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90823   #define USBHSCORE_DIEPINT3_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90824 
90825 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
90826   #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
90827   #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT3_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
90828   #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
90829   #define USBHSCORE_DIEPINT3_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
90830   #define USBHSCORE_DIEPINT3_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
90831   #define USBHSCORE_DIEPINT3_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
90832 
90833 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
90834   #define USBHSCORE_DIEPINT3_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
90835   #define USBHSCORE_DIEPINT3_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT3_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
90836   #define USBHSCORE_DIEPINT3_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
90837   #define USBHSCORE_DIEPINT3_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
90838   #define USBHSCORE_DIEPINT3_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90839   #define USBHSCORE_DIEPINT3_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90840 
90841 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
90842   #define USBHSCORE_DIEPINT3_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
90843   #define USBHSCORE_DIEPINT3_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT3_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
90844   #define USBHSCORE_DIEPINT3_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
90845   #define USBHSCORE_DIEPINT3_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
90846   #define USBHSCORE_DIEPINT3_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90847   #define USBHSCORE_DIEPINT3_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90848 
90849 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
90850   #define USBHSCORE_DIEPINT3_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
90851   #define USBHSCORE_DIEPINT3_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT3_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
90852   #define USBHSCORE_DIEPINT3_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
90853   #define USBHSCORE_DIEPINT3_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
90854   #define USBHSCORE_DIEPINT3_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
90855   #define USBHSCORE_DIEPINT3_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
90856 
90857 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
90858   #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
90859   #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT3_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
90860   #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
90861   #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
90862   #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
90863   #define USBHSCORE_DIEPINT3_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
90864 
90865 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
90866   #define USBHSCORE_DIEPINT3_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
90867   #define USBHSCORE_DIEPINT3_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT3_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
90868   #define USBHSCORE_DIEPINT3_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
90869   #define USBHSCORE_DIEPINT3_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
90870   #define USBHSCORE_DIEPINT3_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90871   #define USBHSCORE_DIEPINT3_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90872 
90873 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
90874   #define USBHSCORE_DIEPINT3_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
90875   #define USBHSCORE_DIEPINT3_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT3_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
90876   #define USBHSCORE_DIEPINT3_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
90877   #define USBHSCORE_DIEPINT3_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
90878   #define USBHSCORE_DIEPINT3_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90879   #define USBHSCORE_DIEPINT3_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90880 
90881 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
90882   #define USBHSCORE_DIEPINT3_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
90883   #define USBHSCORE_DIEPINT3_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT3_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
90884   #define USBHSCORE_DIEPINT3_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
90885   #define USBHSCORE_DIEPINT3_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
90886   #define USBHSCORE_DIEPINT3_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
90887   #define USBHSCORE_DIEPINT3_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
90888 
90889 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
90890   #define USBHSCORE_DIEPINT3_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
90891   #define USBHSCORE_DIEPINT3_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT3_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
90892   #define USBHSCORE_DIEPINT3_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
90893   #define USBHSCORE_DIEPINT3_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
90894   #define USBHSCORE_DIEPINT3_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
90895   #define USBHSCORE_DIEPINT3_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
90896 
90897 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
90898   #define USBHSCORE_DIEPINT3_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
90899   #define USBHSCORE_DIEPINT3_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT3_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
90900   #define USBHSCORE_DIEPINT3_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
90901   #define USBHSCORE_DIEPINT3_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
90902   #define USBHSCORE_DIEPINT3_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
90903   #define USBHSCORE_DIEPINT3_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
90904 
90905 
90906 /* USBHSCORE_DIEPTSIZ3: Device IN Endpoint 3 Transfer Size Register */
90907   #define USBHSCORE_DIEPTSIZ3_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ3 register.                                */
90908 
90909 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
90910   #define USBHSCORE_DIEPTSIZ3_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
90911   #define USBHSCORE_DIEPTSIZ3_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ3_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
90912 
90913 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
90914   #define USBHSCORE_DIEPTSIZ3_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
90915   #define USBHSCORE_DIEPTSIZ3_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ3_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
90916 
90917 /* MC @Bits 29..30 : MC */
90918   #define USBHSCORE_DIEPTSIZ3_MC_Pos (29UL)          /*!< Position of MC field.                                                */
90919   #define USBHSCORE_DIEPTSIZ3_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ3_MC_Pos) /*!< Bit mask of MC field.                          */
90920   #define USBHSCORE_DIEPTSIZ3_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
90921   #define USBHSCORE_DIEPTSIZ3_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
90922   #define USBHSCORE_DIEPTSIZ3_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
90923   #define USBHSCORE_DIEPTSIZ3_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
90924   #define USBHSCORE_DIEPTSIZ3_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
90925 
90926 
90927 /* USBHSCORE_DIEPDMA3: Device IN Endpoint 3 DMA Address Register */
90928   #define USBHSCORE_DIEPDMA3_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA3 register.                                  */
90929 
90930 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
90931   #define USBHSCORE_DIEPDMA3_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
90932   #define USBHSCORE_DIEPDMA3_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA3_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
90933 
90934 
90935 /* USBHSCORE_DTXFSTS3: Device IN Endpoint Transmit FIFO Status Register 3 */
90936   #define USBHSCORE_DTXFSTS3_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS3 register.                                  */
90937 
90938 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
90939   #define USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
90940   #define USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS3_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
90941                                                                             INEPTXFSPCAVAIL field.*/
90942 
90943 
90944 /* USBHSCORE_DIEPCTL4: Device Control IN Endpoint 4 Control Register */
90945   #define USBHSCORE_DIEPCTL4_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL4 register.                                  */
90946 
90947 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
90948   #define USBHSCORE_DIEPCTL4_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
90949   #define USBHSCORE_DIEPCTL4_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL4_MPS_Pos) /*!< Bit mask of MPS field.                       */
90950 
90951 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
90952   #define USBHSCORE_DIEPCTL4_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
90953   #define USBHSCORE_DIEPCTL4_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL4_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
90954   #define USBHSCORE_DIEPCTL4_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
90955   #define USBHSCORE_DIEPCTL4_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
90956   #define USBHSCORE_DIEPCTL4_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
90957   #define USBHSCORE_DIEPCTL4_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
90958 
90959 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
90960   #define USBHSCORE_DIEPCTL4_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
90961   #define USBHSCORE_DIEPCTL4_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL4_DPID_Pos) /*!< Bit mask of DPID field.                      */
90962   #define USBHSCORE_DIEPCTL4_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
90963   #define USBHSCORE_DIEPCTL4_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
90964   #define USBHSCORE_DIEPCTL4_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
90965   #define USBHSCORE_DIEPCTL4_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
90966 
90967 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
90968   #define USBHSCORE_DIEPCTL4_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
90969   #define USBHSCORE_DIEPCTL4_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL4_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
90970   #define USBHSCORE_DIEPCTL4_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
90971   #define USBHSCORE_DIEPCTL4_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
90972   #define USBHSCORE_DIEPCTL4_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
90973   #define USBHSCORE_DIEPCTL4_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
90974 
90975 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
90976   #define USBHSCORE_DIEPCTL4_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
90977   #define USBHSCORE_DIEPCTL4_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL4_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
90978   #define USBHSCORE_DIEPCTL4_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
90979   #define USBHSCORE_DIEPCTL4_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
90980   #define USBHSCORE_DIEPCTL4_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
90981   #define USBHSCORE_DIEPCTL4_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
90982   #define USBHSCORE_DIEPCTL4_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
90983   #define USBHSCORE_DIEPCTL4_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
90984 
90985 /* STALL @Bit 21 : STALL Handshake (Stall) */
90986   #define USBHSCORE_DIEPCTL4_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
90987   #define USBHSCORE_DIEPCTL4_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL4_STALL_Pos) /*!< Bit mask of STALL field.                   */
90988   #define USBHSCORE_DIEPCTL4_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
90989   #define USBHSCORE_DIEPCTL4_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
90990   #define USBHSCORE_DIEPCTL4_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
90991   #define USBHSCORE_DIEPCTL4_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
90992 
90993 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
90994   #define USBHSCORE_DIEPCTL4_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
90995   #define USBHSCORE_DIEPCTL4_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL4_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
90996   #define USBHSCORE_DIEPCTL4_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
90997   #define USBHSCORE_DIEPCTL4_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
90998   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
90999   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
91000   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
91001   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
91002   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
91003   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
91004   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
91005   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
91006   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
91007   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
91008   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
91009   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
91010   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
91011   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
91012   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
91013   #define USBHSCORE_DIEPCTL4_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
91014 
91015 /* CNAK @Bit 26 : Clear NAK (CNAK) */
91016   #define USBHSCORE_DIEPCTL4_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
91017   #define USBHSCORE_DIEPCTL4_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL4_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
91018   #define USBHSCORE_DIEPCTL4_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
91019   #define USBHSCORE_DIEPCTL4_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
91020   #define USBHSCORE_DIEPCTL4_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
91021   #define USBHSCORE_DIEPCTL4_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
91022 
91023 /* SNAK @Bit 27 : Set NAK (SNAK) */
91024   #define USBHSCORE_DIEPCTL4_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
91025   #define USBHSCORE_DIEPCTL4_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL4_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
91026   #define USBHSCORE_DIEPCTL4_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
91027   #define USBHSCORE_DIEPCTL4_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
91028   #define USBHSCORE_DIEPCTL4_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
91029   #define USBHSCORE_DIEPCTL4_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
91030 
91031 /* SETD0PID @Bit 28 : SetD0PID */
91032   #define USBHSCORE_DIEPCTL4_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
91033   #define USBHSCORE_DIEPCTL4_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL4_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
91034   #define USBHSCORE_DIEPCTL4_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
91035   #define USBHSCORE_DIEPCTL4_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
91036   #define USBHSCORE_DIEPCTL4_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91037   #define USBHSCORE_DIEPCTL4_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91038 
91039 /* SETD1PID @Bit 29 : SetD1PID */
91040   #define USBHSCORE_DIEPCTL4_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
91041   #define USBHSCORE_DIEPCTL4_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL4_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
91042   #define USBHSCORE_DIEPCTL4_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
91043   #define USBHSCORE_DIEPCTL4_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
91044   #define USBHSCORE_DIEPCTL4_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91045   #define USBHSCORE_DIEPCTL4_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91046 
91047 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
91048   #define USBHSCORE_DIEPCTL4_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
91049   #define USBHSCORE_DIEPCTL4_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL4_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
91050   #define USBHSCORE_DIEPCTL4_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
91051   #define USBHSCORE_DIEPCTL4_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
91052   #define USBHSCORE_DIEPCTL4_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91053   #define USBHSCORE_DIEPCTL4_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91054 
91055 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
91056   #define USBHSCORE_DIEPCTL4_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
91057   #define USBHSCORE_DIEPCTL4_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL4_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
91058   #define USBHSCORE_DIEPCTL4_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
91059   #define USBHSCORE_DIEPCTL4_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
91060   #define USBHSCORE_DIEPCTL4_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91061   #define USBHSCORE_DIEPCTL4_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91062 
91063 
91064 /* USBHSCORE_DIEPINT4: Device IN Endpoint 4 Interrupt Register */
91065   #define USBHSCORE_DIEPINT4_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT4 register.                                  */
91066 
91067 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
91068   #define USBHSCORE_DIEPINT4_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
91069   #define USBHSCORE_DIEPINT4_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT4_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
91070   #define USBHSCORE_DIEPINT4_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
91071   #define USBHSCORE_DIEPINT4_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
91072   #define USBHSCORE_DIEPINT4_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91073   #define USBHSCORE_DIEPINT4_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91074 
91075 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
91076   #define USBHSCORE_DIEPINT4_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
91077   #define USBHSCORE_DIEPINT4_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT4_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
91078   #define USBHSCORE_DIEPINT4_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
91079   #define USBHSCORE_DIEPINT4_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
91080   #define USBHSCORE_DIEPINT4_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
91081   #define USBHSCORE_DIEPINT4_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
91082 
91083 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
91084   #define USBHSCORE_DIEPINT4_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
91085   #define USBHSCORE_DIEPINT4_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT4_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
91086   #define USBHSCORE_DIEPINT4_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
91087   #define USBHSCORE_DIEPINT4_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
91088   #define USBHSCORE_DIEPINT4_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
91089   #define USBHSCORE_DIEPINT4_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
91090 
91091 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
91092   #define USBHSCORE_DIEPINT4_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
91093   #define USBHSCORE_DIEPINT4_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT4_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
91094   #define USBHSCORE_DIEPINT4_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
91095   #define USBHSCORE_DIEPINT4_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
91096   #define USBHSCORE_DIEPINT4_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91097   #define USBHSCORE_DIEPINT4_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91098 
91099 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
91100   #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
91101   #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT4_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
91102   #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
91103   #define USBHSCORE_DIEPINT4_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
91104   #define USBHSCORE_DIEPINT4_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
91105   #define USBHSCORE_DIEPINT4_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
91106 
91107 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
91108   #define USBHSCORE_DIEPINT4_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
91109   #define USBHSCORE_DIEPINT4_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT4_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
91110   #define USBHSCORE_DIEPINT4_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
91111   #define USBHSCORE_DIEPINT4_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
91112   #define USBHSCORE_DIEPINT4_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91113   #define USBHSCORE_DIEPINT4_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91114 
91115 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
91116   #define USBHSCORE_DIEPINT4_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
91117   #define USBHSCORE_DIEPINT4_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT4_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
91118   #define USBHSCORE_DIEPINT4_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
91119   #define USBHSCORE_DIEPINT4_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
91120   #define USBHSCORE_DIEPINT4_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91121   #define USBHSCORE_DIEPINT4_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91122 
91123 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
91124   #define USBHSCORE_DIEPINT4_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
91125   #define USBHSCORE_DIEPINT4_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT4_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
91126   #define USBHSCORE_DIEPINT4_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
91127   #define USBHSCORE_DIEPINT4_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
91128   #define USBHSCORE_DIEPINT4_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
91129   #define USBHSCORE_DIEPINT4_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
91130 
91131 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
91132   #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
91133   #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT4_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
91134   #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
91135   #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
91136   #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
91137   #define USBHSCORE_DIEPINT4_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
91138 
91139 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
91140   #define USBHSCORE_DIEPINT4_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
91141   #define USBHSCORE_DIEPINT4_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT4_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
91142   #define USBHSCORE_DIEPINT4_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
91143   #define USBHSCORE_DIEPINT4_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
91144   #define USBHSCORE_DIEPINT4_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91145   #define USBHSCORE_DIEPINT4_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91146 
91147 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
91148   #define USBHSCORE_DIEPINT4_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
91149   #define USBHSCORE_DIEPINT4_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT4_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
91150   #define USBHSCORE_DIEPINT4_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
91151   #define USBHSCORE_DIEPINT4_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
91152   #define USBHSCORE_DIEPINT4_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91153   #define USBHSCORE_DIEPINT4_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91154 
91155 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
91156   #define USBHSCORE_DIEPINT4_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
91157   #define USBHSCORE_DIEPINT4_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT4_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
91158   #define USBHSCORE_DIEPINT4_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
91159   #define USBHSCORE_DIEPINT4_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
91160   #define USBHSCORE_DIEPINT4_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91161   #define USBHSCORE_DIEPINT4_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91162 
91163 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
91164   #define USBHSCORE_DIEPINT4_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
91165   #define USBHSCORE_DIEPINT4_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT4_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
91166   #define USBHSCORE_DIEPINT4_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
91167   #define USBHSCORE_DIEPINT4_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
91168   #define USBHSCORE_DIEPINT4_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91169   #define USBHSCORE_DIEPINT4_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91170 
91171 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
91172   #define USBHSCORE_DIEPINT4_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
91173   #define USBHSCORE_DIEPINT4_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT4_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
91174   #define USBHSCORE_DIEPINT4_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
91175   #define USBHSCORE_DIEPINT4_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
91176   #define USBHSCORE_DIEPINT4_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91177   #define USBHSCORE_DIEPINT4_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91178 
91179 
91180 /* USBHSCORE_DIEPTSIZ4: Device IN Endpoint 4 Transfer Size Register */
91181   #define USBHSCORE_DIEPTSIZ4_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ4 register.                                */
91182 
91183 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
91184   #define USBHSCORE_DIEPTSIZ4_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
91185   #define USBHSCORE_DIEPTSIZ4_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ4_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
91186 
91187 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
91188   #define USBHSCORE_DIEPTSIZ4_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
91189   #define USBHSCORE_DIEPTSIZ4_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ4_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
91190 
91191 /* MC @Bits 29..30 : MC */
91192   #define USBHSCORE_DIEPTSIZ4_MC_Pos (29UL)          /*!< Position of MC field.                                                */
91193   #define USBHSCORE_DIEPTSIZ4_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ4_MC_Pos) /*!< Bit mask of MC field.                          */
91194   #define USBHSCORE_DIEPTSIZ4_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
91195   #define USBHSCORE_DIEPTSIZ4_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
91196   #define USBHSCORE_DIEPTSIZ4_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
91197   #define USBHSCORE_DIEPTSIZ4_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
91198   #define USBHSCORE_DIEPTSIZ4_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
91199 
91200 
91201 /* USBHSCORE_DIEPDMA4: Device IN Endpoint 4 DMA Address Register */
91202   #define USBHSCORE_DIEPDMA4_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA4 register.                                  */
91203 
91204 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
91205   #define USBHSCORE_DIEPDMA4_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
91206   #define USBHSCORE_DIEPDMA4_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA4_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
91207 
91208 
91209 /* USBHSCORE_DTXFSTS4: Device IN Endpoint Transmit FIFO Status Register 4 */
91210   #define USBHSCORE_DTXFSTS4_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS4 register.                                  */
91211 
91212 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
91213   #define USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
91214   #define USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS4_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
91215                                                                             INEPTXFSPCAVAIL field.*/
91216 
91217 
91218 /* USBHSCORE_DIEPCTL5: Device Control IN Endpoint 5 Control Register */
91219   #define USBHSCORE_DIEPCTL5_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL5 register.                                  */
91220 
91221 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
91222   #define USBHSCORE_DIEPCTL5_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
91223   #define USBHSCORE_DIEPCTL5_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL5_MPS_Pos) /*!< Bit mask of MPS field.                       */
91224 
91225 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
91226   #define USBHSCORE_DIEPCTL5_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
91227   #define USBHSCORE_DIEPCTL5_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL5_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
91228   #define USBHSCORE_DIEPCTL5_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
91229   #define USBHSCORE_DIEPCTL5_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
91230   #define USBHSCORE_DIEPCTL5_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91231   #define USBHSCORE_DIEPCTL5_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91232 
91233 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
91234   #define USBHSCORE_DIEPCTL5_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
91235   #define USBHSCORE_DIEPCTL5_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL5_DPID_Pos) /*!< Bit mask of DPID field.                      */
91236   #define USBHSCORE_DIEPCTL5_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
91237   #define USBHSCORE_DIEPCTL5_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
91238   #define USBHSCORE_DIEPCTL5_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
91239   #define USBHSCORE_DIEPCTL5_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
91240 
91241 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
91242   #define USBHSCORE_DIEPCTL5_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
91243   #define USBHSCORE_DIEPCTL5_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL5_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
91244   #define USBHSCORE_DIEPCTL5_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
91245   #define USBHSCORE_DIEPCTL5_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
91246   #define USBHSCORE_DIEPCTL5_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
91247   #define USBHSCORE_DIEPCTL5_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
91248 
91249 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
91250   #define USBHSCORE_DIEPCTL5_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
91251   #define USBHSCORE_DIEPCTL5_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL5_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
91252   #define USBHSCORE_DIEPCTL5_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
91253   #define USBHSCORE_DIEPCTL5_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
91254   #define USBHSCORE_DIEPCTL5_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
91255   #define USBHSCORE_DIEPCTL5_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
91256   #define USBHSCORE_DIEPCTL5_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
91257   #define USBHSCORE_DIEPCTL5_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
91258 
91259 /* STALL @Bit 21 : STALL Handshake (Stall) */
91260   #define USBHSCORE_DIEPCTL5_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
91261   #define USBHSCORE_DIEPCTL5_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL5_STALL_Pos) /*!< Bit mask of STALL field.                   */
91262   #define USBHSCORE_DIEPCTL5_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
91263   #define USBHSCORE_DIEPCTL5_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
91264   #define USBHSCORE_DIEPCTL5_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91265   #define USBHSCORE_DIEPCTL5_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91266 
91267 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
91268   #define USBHSCORE_DIEPCTL5_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
91269   #define USBHSCORE_DIEPCTL5_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL5_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
91270   #define USBHSCORE_DIEPCTL5_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
91271   #define USBHSCORE_DIEPCTL5_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
91272   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
91273   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
91274   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
91275   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
91276   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
91277   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
91278   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
91279   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
91280   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
91281   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
91282   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
91283   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
91284   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
91285   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
91286   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
91287   #define USBHSCORE_DIEPCTL5_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
91288 
91289 /* CNAK @Bit 26 : Clear NAK (CNAK) */
91290   #define USBHSCORE_DIEPCTL5_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
91291   #define USBHSCORE_DIEPCTL5_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL5_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
91292   #define USBHSCORE_DIEPCTL5_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
91293   #define USBHSCORE_DIEPCTL5_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
91294   #define USBHSCORE_DIEPCTL5_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
91295   #define USBHSCORE_DIEPCTL5_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
91296 
91297 /* SNAK @Bit 27 : Set NAK (SNAK) */
91298   #define USBHSCORE_DIEPCTL5_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
91299   #define USBHSCORE_DIEPCTL5_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL5_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
91300   #define USBHSCORE_DIEPCTL5_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
91301   #define USBHSCORE_DIEPCTL5_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
91302   #define USBHSCORE_DIEPCTL5_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
91303   #define USBHSCORE_DIEPCTL5_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
91304 
91305 /* SETD0PID @Bit 28 : SetD0PID */
91306   #define USBHSCORE_DIEPCTL5_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
91307   #define USBHSCORE_DIEPCTL5_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL5_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
91308   #define USBHSCORE_DIEPCTL5_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
91309   #define USBHSCORE_DIEPCTL5_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
91310   #define USBHSCORE_DIEPCTL5_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91311   #define USBHSCORE_DIEPCTL5_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91312 
91313 /* SETD1PID @Bit 29 : SetD1PID */
91314   #define USBHSCORE_DIEPCTL5_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
91315   #define USBHSCORE_DIEPCTL5_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL5_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
91316   #define USBHSCORE_DIEPCTL5_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
91317   #define USBHSCORE_DIEPCTL5_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
91318   #define USBHSCORE_DIEPCTL5_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91319   #define USBHSCORE_DIEPCTL5_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91320 
91321 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
91322   #define USBHSCORE_DIEPCTL5_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
91323   #define USBHSCORE_DIEPCTL5_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL5_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
91324   #define USBHSCORE_DIEPCTL5_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
91325   #define USBHSCORE_DIEPCTL5_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
91326   #define USBHSCORE_DIEPCTL5_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91327   #define USBHSCORE_DIEPCTL5_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91328 
91329 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
91330   #define USBHSCORE_DIEPCTL5_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
91331   #define USBHSCORE_DIEPCTL5_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL5_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
91332   #define USBHSCORE_DIEPCTL5_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
91333   #define USBHSCORE_DIEPCTL5_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
91334   #define USBHSCORE_DIEPCTL5_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91335   #define USBHSCORE_DIEPCTL5_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91336 
91337 
91338 /* USBHSCORE_DIEPINT5: Device IN Endpoint 5 Interrupt Register */
91339   #define USBHSCORE_DIEPINT5_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT5 register.                                  */
91340 
91341 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
91342   #define USBHSCORE_DIEPINT5_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
91343   #define USBHSCORE_DIEPINT5_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT5_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
91344   #define USBHSCORE_DIEPINT5_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
91345   #define USBHSCORE_DIEPINT5_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
91346   #define USBHSCORE_DIEPINT5_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91347   #define USBHSCORE_DIEPINT5_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91348 
91349 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
91350   #define USBHSCORE_DIEPINT5_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
91351   #define USBHSCORE_DIEPINT5_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT5_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
91352   #define USBHSCORE_DIEPINT5_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
91353   #define USBHSCORE_DIEPINT5_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
91354   #define USBHSCORE_DIEPINT5_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
91355   #define USBHSCORE_DIEPINT5_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
91356 
91357 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
91358   #define USBHSCORE_DIEPINT5_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
91359   #define USBHSCORE_DIEPINT5_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT5_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
91360   #define USBHSCORE_DIEPINT5_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
91361   #define USBHSCORE_DIEPINT5_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
91362   #define USBHSCORE_DIEPINT5_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
91363   #define USBHSCORE_DIEPINT5_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
91364 
91365 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
91366   #define USBHSCORE_DIEPINT5_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
91367   #define USBHSCORE_DIEPINT5_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT5_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
91368   #define USBHSCORE_DIEPINT5_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
91369   #define USBHSCORE_DIEPINT5_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
91370   #define USBHSCORE_DIEPINT5_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91371   #define USBHSCORE_DIEPINT5_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91372 
91373 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
91374   #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
91375   #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT5_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
91376   #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
91377   #define USBHSCORE_DIEPINT5_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
91378   #define USBHSCORE_DIEPINT5_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
91379   #define USBHSCORE_DIEPINT5_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
91380 
91381 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
91382   #define USBHSCORE_DIEPINT5_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
91383   #define USBHSCORE_DIEPINT5_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT5_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
91384   #define USBHSCORE_DIEPINT5_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
91385   #define USBHSCORE_DIEPINT5_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
91386   #define USBHSCORE_DIEPINT5_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91387   #define USBHSCORE_DIEPINT5_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91388 
91389 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
91390   #define USBHSCORE_DIEPINT5_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
91391   #define USBHSCORE_DIEPINT5_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT5_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
91392   #define USBHSCORE_DIEPINT5_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
91393   #define USBHSCORE_DIEPINT5_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
91394   #define USBHSCORE_DIEPINT5_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91395   #define USBHSCORE_DIEPINT5_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91396 
91397 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
91398   #define USBHSCORE_DIEPINT5_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
91399   #define USBHSCORE_DIEPINT5_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT5_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
91400   #define USBHSCORE_DIEPINT5_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
91401   #define USBHSCORE_DIEPINT5_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
91402   #define USBHSCORE_DIEPINT5_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
91403   #define USBHSCORE_DIEPINT5_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
91404 
91405 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
91406   #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
91407   #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT5_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
91408   #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
91409   #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
91410   #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
91411   #define USBHSCORE_DIEPINT5_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
91412 
91413 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
91414   #define USBHSCORE_DIEPINT5_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
91415   #define USBHSCORE_DIEPINT5_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT5_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
91416   #define USBHSCORE_DIEPINT5_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
91417   #define USBHSCORE_DIEPINT5_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
91418   #define USBHSCORE_DIEPINT5_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91419   #define USBHSCORE_DIEPINT5_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91420 
91421 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
91422   #define USBHSCORE_DIEPINT5_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
91423   #define USBHSCORE_DIEPINT5_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT5_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
91424   #define USBHSCORE_DIEPINT5_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
91425   #define USBHSCORE_DIEPINT5_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
91426   #define USBHSCORE_DIEPINT5_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91427   #define USBHSCORE_DIEPINT5_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91428 
91429 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
91430   #define USBHSCORE_DIEPINT5_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
91431   #define USBHSCORE_DIEPINT5_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT5_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
91432   #define USBHSCORE_DIEPINT5_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
91433   #define USBHSCORE_DIEPINT5_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
91434   #define USBHSCORE_DIEPINT5_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91435   #define USBHSCORE_DIEPINT5_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91436 
91437 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
91438   #define USBHSCORE_DIEPINT5_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
91439   #define USBHSCORE_DIEPINT5_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT5_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
91440   #define USBHSCORE_DIEPINT5_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
91441   #define USBHSCORE_DIEPINT5_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
91442   #define USBHSCORE_DIEPINT5_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91443   #define USBHSCORE_DIEPINT5_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91444 
91445 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
91446   #define USBHSCORE_DIEPINT5_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
91447   #define USBHSCORE_DIEPINT5_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT5_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
91448   #define USBHSCORE_DIEPINT5_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
91449   #define USBHSCORE_DIEPINT5_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
91450   #define USBHSCORE_DIEPINT5_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91451   #define USBHSCORE_DIEPINT5_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91452 
91453 
91454 /* USBHSCORE_DIEPTSIZ5: Device IN Endpoint 5 Transfer Size Register */
91455   #define USBHSCORE_DIEPTSIZ5_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ5 register.                                */
91456 
91457 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
91458   #define USBHSCORE_DIEPTSIZ5_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
91459   #define USBHSCORE_DIEPTSIZ5_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ5_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
91460 
91461 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
91462   #define USBHSCORE_DIEPTSIZ5_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
91463   #define USBHSCORE_DIEPTSIZ5_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ5_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
91464 
91465 /* MC @Bits 29..30 : MC */
91466   #define USBHSCORE_DIEPTSIZ5_MC_Pos (29UL)          /*!< Position of MC field.                                                */
91467   #define USBHSCORE_DIEPTSIZ5_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ5_MC_Pos) /*!< Bit mask of MC field.                          */
91468   #define USBHSCORE_DIEPTSIZ5_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
91469   #define USBHSCORE_DIEPTSIZ5_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
91470   #define USBHSCORE_DIEPTSIZ5_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
91471   #define USBHSCORE_DIEPTSIZ5_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
91472   #define USBHSCORE_DIEPTSIZ5_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
91473 
91474 
91475 /* USBHSCORE_DIEPDMA5: Device IN Endpoint 5 DMA Address Register */
91476   #define USBHSCORE_DIEPDMA5_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA5 register.                                  */
91477 
91478 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
91479   #define USBHSCORE_DIEPDMA5_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
91480   #define USBHSCORE_DIEPDMA5_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA5_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
91481 
91482 
91483 /* USBHSCORE_DTXFSTS5: Device IN Endpoint Transmit FIFO Status Register 5 */
91484   #define USBHSCORE_DTXFSTS5_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS5 register.                                  */
91485 
91486 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
91487   #define USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
91488   #define USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS5_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
91489                                                                             INEPTXFSPCAVAIL field.*/
91490 
91491 
91492 /* USBHSCORE_DIEPCTL6: Device Control IN Endpoint 6 Control Register */
91493   #define USBHSCORE_DIEPCTL6_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL6 register.                                  */
91494 
91495 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
91496   #define USBHSCORE_DIEPCTL6_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
91497   #define USBHSCORE_DIEPCTL6_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL6_MPS_Pos) /*!< Bit mask of MPS field.                       */
91498 
91499 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
91500   #define USBHSCORE_DIEPCTL6_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
91501   #define USBHSCORE_DIEPCTL6_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL6_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
91502   #define USBHSCORE_DIEPCTL6_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
91503   #define USBHSCORE_DIEPCTL6_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
91504   #define USBHSCORE_DIEPCTL6_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91505   #define USBHSCORE_DIEPCTL6_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91506 
91507 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
91508   #define USBHSCORE_DIEPCTL6_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
91509   #define USBHSCORE_DIEPCTL6_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL6_DPID_Pos) /*!< Bit mask of DPID field.                      */
91510   #define USBHSCORE_DIEPCTL6_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
91511   #define USBHSCORE_DIEPCTL6_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
91512   #define USBHSCORE_DIEPCTL6_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
91513   #define USBHSCORE_DIEPCTL6_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
91514 
91515 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
91516   #define USBHSCORE_DIEPCTL6_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
91517   #define USBHSCORE_DIEPCTL6_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL6_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
91518   #define USBHSCORE_DIEPCTL6_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
91519   #define USBHSCORE_DIEPCTL6_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
91520   #define USBHSCORE_DIEPCTL6_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
91521   #define USBHSCORE_DIEPCTL6_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
91522 
91523 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
91524   #define USBHSCORE_DIEPCTL6_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
91525   #define USBHSCORE_DIEPCTL6_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL6_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
91526   #define USBHSCORE_DIEPCTL6_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
91527   #define USBHSCORE_DIEPCTL6_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
91528   #define USBHSCORE_DIEPCTL6_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
91529   #define USBHSCORE_DIEPCTL6_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
91530   #define USBHSCORE_DIEPCTL6_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
91531   #define USBHSCORE_DIEPCTL6_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
91532 
91533 /* STALL @Bit 21 : STALL Handshake (Stall) */
91534   #define USBHSCORE_DIEPCTL6_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
91535   #define USBHSCORE_DIEPCTL6_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL6_STALL_Pos) /*!< Bit mask of STALL field.                   */
91536   #define USBHSCORE_DIEPCTL6_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
91537   #define USBHSCORE_DIEPCTL6_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
91538   #define USBHSCORE_DIEPCTL6_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91539   #define USBHSCORE_DIEPCTL6_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91540 
91541 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
91542   #define USBHSCORE_DIEPCTL6_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
91543   #define USBHSCORE_DIEPCTL6_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL6_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
91544   #define USBHSCORE_DIEPCTL6_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
91545   #define USBHSCORE_DIEPCTL6_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
91546   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
91547   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
91548   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
91549   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
91550   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
91551   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
91552   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
91553   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
91554   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
91555   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
91556   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
91557   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
91558   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
91559   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
91560   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
91561   #define USBHSCORE_DIEPCTL6_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
91562 
91563 /* CNAK @Bit 26 : Clear NAK (CNAK) */
91564   #define USBHSCORE_DIEPCTL6_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
91565   #define USBHSCORE_DIEPCTL6_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL6_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
91566   #define USBHSCORE_DIEPCTL6_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
91567   #define USBHSCORE_DIEPCTL6_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
91568   #define USBHSCORE_DIEPCTL6_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
91569   #define USBHSCORE_DIEPCTL6_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
91570 
91571 /* SNAK @Bit 27 : Set NAK (SNAK) */
91572   #define USBHSCORE_DIEPCTL6_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
91573   #define USBHSCORE_DIEPCTL6_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL6_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
91574   #define USBHSCORE_DIEPCTL6_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
91575   #define USBHSCORE_DIEPCTL6_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
91576   #define USBHSCORE_DIEPCTL6_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
91577   #define USBHSCORE_DIEPCTL6_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
91578 
91579 /* SETD0PID @Bit 28 : SetD0PID */
91580   #define USBHSCORE_DIEPCTL6_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
91581   #define USBHSCORE_DIEPCTL6_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL6_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
91582   #define USBHSCORE_DIEPCTL6_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
91583   #define USBHSCORE_DIEPCTL6_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
91584   #define USBHSCORE_DIEPCTL6_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91585   #define USBHSCORE_DIEPCTL6_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91586 
91587 /* SETD1PID @Bit 29 : SetD1PID */
91588   #define USBHSCORE_DIEPCTL6_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
91589   #define USBHSCORE_DIEPCTL6_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL6_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
91590   #define USBHSCORE_DIEPCTL6_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
91591   #define USBHSCORE_DIEPCTL6_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
91592   #define USBHSCORE_DIEPCTL6_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91593   #define USBHSCORE_DIEPCTL6_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91594 
91595 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
91596   #define USBHSCORE_DIEPCTL6_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
91597   #define USBHSCORE_DIEPCTL6_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL6_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
91598   #define USBHSCORE_DIEPCTL6_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
91599   #define USBHSCORE_DIEPCTL6_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
91600   #define USBHSCORE_DIEPCTL6_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91601   #define USBHSCORE_DIEPCTL6_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91602 
91603 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
91604   #define USBHSCORE_DIEPCTL6_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
91605   #define USBHSCORE_DIEPCTL6_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL6_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
91606   #define USBHSCORE_DIEPCTL6_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
91607   #define USBHSCORE_DIEPCTL6_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
91608   #define USBHSCORE_DIEPCTL6_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91609   #define USBHSCORE_DIEPCTL6_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91610 
91611 
91612 /* USBHSCORE_DIEPINT6: Device IN Endpoint 6 Interrupt Register */
91613   #define USBHSCORE_DIEPINT6_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT6 register.                                  */
91614 
91615 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
91616   #define USBHSCORE_DIEPINT6_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
91617   #define USBHSCORE_DIEPINT6_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT6_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
91618   #define USBHSCORE_DIEPINT6_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
91619   #define USBHSCORE_DIEPINT6_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
91620   #define USBHSCORE_DIEPINT6_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91621   #define USBHSCORE_DIEPINT6_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91622 
91623 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
91624   #define USBHSCORE_DIEPINT6_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
91625   #define USBHSCORE_DIEPINT6_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT6_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
91626   #define USBHSCORE_DIEPINT6_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
91627   #define USBHSCORE_DIEPINT6_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
91628   #define USBHSCORE_DIEPINT6_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
91629   #define USBHSCORE_DIEPINT6_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
91630 
91631 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
91632   #define USBHSCORE_DIEPINT6_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
91633   #define USBHSCORE_DIEPINT6_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT6_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
91634   #define USBHSCORE_DIEPINT6_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
91635   #define USBHSCORE_DIEPINT6_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
91636   #define USBHSCORE_DIEPINT6_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
91637   #define USBHSCORE_DIEPINT6_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
91638 
91639 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
91640   #define USBHSCORE_DIEPINT6_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
91641   #define USBHSCORE_DIEPINT6_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT6_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
91642   #define USBHSCORE_DIEPINT6_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
91643   #define USBHSCORE_DIEPINT6_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
91644   #define USBHSCORE_DIEPINT6_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91645   #define USBHSCORE_DIEPINT6_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91646 
91647 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
91648   #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
91649   #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT6_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
91650   #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
91651   #define USBHSCORE_DIEPINT6_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
91652   #define USBHSCORE_DIEPINT6_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
91653   #define USBHSCORE_DIEPINT6_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
91654 
91655 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
91656   #define USBHSCORE_DIEPINT6_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
91657   #define USBHSCORE_DIEPINT6_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT6_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
91658   #define USBHSCORE_DIEPINT6_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
91659   #define USBHSCORE_DIEPINT6_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
91660   #define USBHSCORE_DIEPINT6_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91661   #define USBHSCORE_DIEPINT6_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91662 
91663 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
91664   #define USBHSCORE_DIEPINT6_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
91665   #define USBHSCORE_DIEPINT6_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT6_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
91666   #define USBHSCORE_DIEPINT6_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
91667   #define USBHSCORE_DIEPINT6_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
91668   #define USBHSCORE_DIEPINT6_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91669   #define USBHSCORE_DIEPINT6_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91670 
91671 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
91672   #define USBHSCORE_DIEPINT6_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
91673   #define USBHSCORE_DIEPINT6_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT6_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
91674   #define USBHSCORE_DIEPINT6_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
91675   #define USBHSCORE_DIEPINT6_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
91676   #define USBHSCORE_DIEPINT6_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
91677   #define USBHSCORE_DIEPINT6_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
91678 
91679 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
91680   #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
91681   #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT6_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
91682   #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
91683   #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
91684   #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
91685   #define USBHSCORE_DIEPINT6_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
91686 
91687 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
91688   #define USBHSCORE_DIEPINT6_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
91689   #define USBHSCORE_DIEPINT6_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT6_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
91690   #define USBHSCORE_DIEPINT6_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
91691   #define USBHSCORE_DIEPINT6_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
91692   #define USBHSCORE_DIEPINT6_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91693   #define USBHSCORE_DIEPINT6_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91694 
91695 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
91696   #define USBHSCORE_DIEPINT6_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
91697   #define USBHSCORE_DIEPINT6_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT6_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
91698   #define USBHSCORE_DIEPINT6_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
91699   #define USBHSCORE_DIEPINT6_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
91700   #define USBHSCORE_DIEPINT6_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91701   #define USBHSCORE_DIEPINT6_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91702 
91703 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
91704   #define USBHSCORE_DIEPINT6_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
91705   #define USBHSCORE_DIEPINT6_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT6_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
91706   #define USBHSCORE_DIEPINT6_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
91707   #define USBHSCORE_DIEPINT6_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
91708   #define USBHSCORE_DIEPINT6_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91709   #define USBHSCORE_DIEPINT6_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91710 
91711 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
91712   #define USBHSCORE_DIEPINT6_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
91713   #define USBHSCORE_DIEPINT6_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT6_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
91714   #define USBHSCORE_DIEPINT6_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
91715   #define USBHSCORE_DIEPINT6_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
91716   #define USBHSCORE_DIEPINT6_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91717   #define USBHSCORE_DIEPINT6_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91718 
91719 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
91720   #define USBHSCORE_DIEPINT6_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
91721   #define USBHSCORE_DIEPINT6_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT6_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
91722   #define USBHSCORE_DIEPINT6_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
91723   #define USBHSCORE_DIEPINT6_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
91724   #define USBHSCORE_DIEPINT6_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91725   #define USBHSCORE_DIEPINT6_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91726 
91727 
91728 /* USBHSCORE_DIEPTSIZ6: Device IN Endpoint 6 Transfer Size Register */
91729   #define USBHSCORE_DIEPTSIZ6_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ6 register.                                */
91730 
91731 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
91732   #define USBHSCORE_DIEPTSIZ6_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
91733   #define USBHSCORE_DIEPTSIZ6_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ6_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
91734 
91735 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
91736   #define USBHSCORE_DIEPTSIZ6_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
91737   #define USBHSCORE_DIEPTSIZ6_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ6_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
91738 
91739 /* MC @Bits 29..30 : MC */
91740   #define USBHSCORE_DIEPTSIZ6_MC_Pos (29UL)          /*!< Position of MC field.                                                */
91741   #define USBHSCORE_DIEPTSIZ6_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ6_MC_Pos) /*!< Bit mask of MC field.                          */
91742   #define USBHSCORE_DIEPTSIZ6_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
91743   #define USBHSCORE_DIEPTSIZ6_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
91744   #define USBHSCORE_DIEPTSIZ6_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
91745   #define USBHSCORE_DIEPTSIZ6_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
91746   #define USBHSCORE_DIEPTSIZ6_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
91747 
91748 
91749 /* USBHSCORE_DIEPDMA6: Device IN Endpoint 6 DMA Address Register */
91750   #define USBHSCORE_DIEPDMA6_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA6 register.                                  */
91751 
91752 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
91753   #define USBHSCORE_DIEPDMA6_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
91754   #define USBHSCORE_DIEPDMA6_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA6_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
91755 
91756 
91757 /* USBHSCORE_DTXFSTS6: Device IN Endpoint Transmit FIFO Status Register 6 */
91758   #define USBHSCORE_DTXFSTS6_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS6 register.                                  */
91759 
91760 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
91761   #define USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
91762   #define USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS6_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
91763                                                                             INEPTXFSPCAVAIL field.*/
91764 
91765 
91766 /* USBHSCORE_DIEPCTL7: Device Control IN Endpoint 7 Control Register */
91767   #define USBHSCORE_DIEPCTL7_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL7 register.                                  */
91768 
91769 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
91770   #define USBHSCORE_DIEPCTL7_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
91771   #define USBHSCORE_DIEPCTL7_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL7_MPS_Pos) /*!< Bit mask of MPS field.                       */
91772 
91773 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
91774   #define USBHSCORE_DIEPCTL7_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
91775   #define USBHSCORE_DIEPCTL7_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL7_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
91776   #define USBHSCORE_DIEPCTL7_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
91777   #define USBHSCORE_DIEPCTL7_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
91778   #define USBHSCORE_DIEPCTL7_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91779   #define USBHSCORE_DIEPCTL7_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91780 
91781 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
91782   #define USBHSCORE_DIEPCTL7_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
91783   #define USBHSCORE_DIEPCTL7_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL7_DPID_Pos) /*!< Bit mask of DPID field.                      */
91784   #define USBHSCORE_DIEPCTL7_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
91785   #define USBHSCORE_DIEPCTL7_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
91786   #define USBHSCORE_DIEPCTL7_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
91787   #define USBHSCORE_DIEPCTL7_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
91788 
91789 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
91790   #define USBHSCORE_DIEPCTL7_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
91791   #define USBHSCORE_DIEPCTL7_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL7_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
91792   #define USBHSCORE_DIEPCTL7_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
91793   #define USBHSCORE_DIEPCTL7_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
91794   #define USBHSCORE_DIEPCTL7_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
91795   #define USBHSCORE_DIEPCTL7_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
91796 
91797 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
91798   #define USBHSCORE_DIEPCTL7_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
91799   #define USBHSCORE_DIEPCTL7_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL7_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
91800   #define USBHSCORE_DIEPCTL7_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
91801   #define USBHSCORE_DIEPCTL7_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
91802   #define USBHSCORE_DIEPCTL7_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
91803   #define USBHSCORE_DIEPCTL7_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
91804   #define USBHSCORE_DIEPCTL7_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
91805   #define USBHSCORE_DIEPCTL7_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
91806 
91807 /* STALL @Bit 21 : STALL Handshake (Stall) */
91808   #define USBHSCORE_DIEPCTL7_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
91809   #define USBHSCORE_DIEPCTL7_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL7_STALL_Pos) /*!< Bit mask of STALL field.                   */
91810   #define USBHSCORE_DIEPCTL7_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
91811   #define USBHSCORE_DIEPCTL7_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
91812   #define USBHSCORE_DIEPCTL7_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91813   #define USBHSCORE_DIEPCTL7_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91814 
91815 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
91816   #define USBHSCORE_DIEPCTL7_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
91817   #define USBHSCORE_DIEPCTL7_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL7_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
91818   #define USBHSCORE_DIEPCTL7_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
91819   #define USBHSCORE_DIEPCTL7_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
91820   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
91821   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
91822   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
91823   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
91824   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
91825   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
91826   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
91827   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
91828   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
91829   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
91830   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
91831   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
91832   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
91833   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
91834   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
91835   #define USBHSCORE_DIEPCTL7_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
91836 
91837 /* CNAK @Bit 26 : Clear NAK (CNAK) */
91838   #define USBHSCORE_DIEPCTL7_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
91839   #define USBHSCORE_DIEPCTL7_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL7_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
91840   #define USBHSCORE_DIEPCTL7_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
91841   #define USBHSCORE_DIEPCTL7_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
91842   #define USBHSCORE_DIEPCTL7_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
91843   #define USBHSCORE_DIEPCTL7_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
91844 
91845 /* SNAK @Bit 27 : Set NAK (SNAK) */
91846   #define USBHSCORE_DIEPCTL7_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
91847   #define USBHSCORE_DIEPCTL7_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL7_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
91848   #define USBHSCORE_DIEPCTL7_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
91849   #define USBHSCORE_DIEPCTL7_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
91850   #define USBHSCORE_DIEPCTL7_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
91851   #define USBHSCORE_DIEPCTL7_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
91852 
91853 /* SETD0PID @Bit 28 : SetD0PID */
91854   #define USBHSCORE_DIEPCTL7_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
91855   #define USBHSCORE_DIEPCTL7_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL7_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
91856   #define USBHSCORE_DIEPCTL7_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
91857   #define USBHSCORE_DIEPCTL7_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
91858   #define USBHSCORE_DIEPCTL7_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91859   #define USBHSCORE_DIEPCTL7_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91860 
91861 /* SETD1PID @Bit 29 : SetD1PID */
91862   #define USBHSCORE_DIEPCTL7_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
91863   #define USBHSCORE_DIEPCTL7_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL7_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
91864   #define USBHSCORE_DIEPCTL7_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
91865   #define USBHSCORE_DIEPCTL7_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
91866   #define USBHSCORE_DIEPCTL7_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
91867   #define USBHSCORE_DIEPCTL7_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
91868 
91869 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
91870   #define USBHSCORE_DIEPCTL7_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
91871   #define USBHSCORE_DIEPCTL7_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL7_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
91872   #define USBHSCORE_DIEPCTL7_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
91873   #define USBHSCORE_DIEPCTL7_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
91874   #define USBHSCORE_DIEPCTL7_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91875   #define USBHSCORE_DIEPCTL7_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91876 
91877 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
91878   #define USBHSCORE_DIEPCTL7_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
91879   #define USBHSCORE_DIEPCTL7_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL7_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
91880   #define USBHSCORE_DIEPCTL7_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
91881   #define USBHSCORE_DIEPCTL7_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
91882   #define USBHSCORE_DIEPCTL7_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
91883   #define USBHSCORE_DIEPCTL7_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
91884 
91885 
91886 /* USBHSCORE_DIEPINT7: Device IN Endpoint 7 Interrupt Register */
91887   #define USBHSCORE_DIEPINT7_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT7 register.                                  */
91888 
91889 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
91890   #define USBHSCORE_DIEPINT7_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
91891   #define USBHSCORE_DIEPINT7_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT7_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
91892   #define USBHSCORE_DIEPINT7_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
91893   #define USBHSCORE_DIEPINT7_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
91894   #define USBHSCORE_DIEPINT7_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91895   #define USBHSCORE_DIEPINT7_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91896 
91897 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
91898   #define USBHSCORE_DIEPINT7_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
91899   #define USBHSCORE_DIEPINT7_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT7_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
91900   #define USBHSCORE_DIEPINT7_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
91901   #define USBHSCORE_DIEPINT7_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
91902   #define USBHSCORE_DIEPINT7_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
91903   #define USBHSCORE_DIEPINT7_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
91904 
91905 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
91906   #define USBHSCORE_DIEPINT7_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
91907   #define USBHSCORE_DIEPINT7_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT7_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
91908   #define USBHSCORE_DIEPINT7_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
91909   #define USBHSCORE_DIEPINT7_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
91910   #define USBHSCORE_DIEPINT7_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
91911   #define USBHSCORE_DIEPINT7_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
91912 
91913 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
91914   #define USBHSCORE_DIEPINT7_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
91915   #define USBHSCORE_DIEPINT7_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT7_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
91916   #define USBHSCORE_DIEPINT7_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
91917   #define USBHSCORE_DIEPINT7_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
91918   #define USBHSCORE_DIEPINT7_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91919   #define USBHSCORE_DIEPINT7_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91920 
91921 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
91922   #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
91923   #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT7_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
91924   #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
91925   #define USBHSCORE_DIEPINT7_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
91926   #define USBHSCORE_DIEPINT7_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
91927   #define USBHSCORE_DIEPINT7_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
91928 
91929 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
91930   #define USBHSCORE_DIEPINT7_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
91931   #define USBHSCORE_DIEPINT7_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT7_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
91932   #define USBHSCORE_DIEPINT7_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
91933   #define USBHSCORE_DIEPINT7_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
91934   #define USBHSCORE_DIEPINT7_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91935   #define USBHSCORE_DIEPINT7_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91936 
91937 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
91938   #define USBHSCORE_DIEPINT7_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
91939   #define USBHSCORE_DIEPINT7_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT7_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
91940   #define USBHSCORE_DIEPINT7_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
91941   #define USBHSCORE_DIEPINT7_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
91942   #define USBHSCORE_DIEPINT7_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91943   #define USBHSCORE_DIEPINT7_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
91944 
91945 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
91946   #define USBHSCORE_DIEPINT7_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
91947   #define USBHSCORE_DIEPINT7_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT7_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
91948   #define USBHSCORE_DIEPINT7_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
91949   #define USBHSCORE_DIEPINT7_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
91950   #define USBHSCORE_DIEPINT7_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
91951   #define USBHSCORE_DIEPINT7_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
91952 
91953 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
91954   #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
91955   #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT7_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
91956   #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
91957   #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
91958   #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
91959   #define USBHSCORE_DIEPINT7_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
91960 
91961 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
91962   #define USBHSCORE_DIEPINT7_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
91963   #define USBHSCORE_DIEPINT7_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT7_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
91964   #define USBHSCORE_DIEPINT7_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
91965   #define USBHSCORE_DIEPINT7_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
91966   #define USBHSCORE_DIEPINT7_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91967   #define USBHSCORE_DIEPINT7_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91968 
91969 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
91970   #define USBHSCORE_DIEPINT7_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
91971   #define USBHSCORE_DIEPINT7_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT7_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
91972   #define USBHSCORE_DIEPINT7_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
91973   #define USBHSCORE_DIEPINT7_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
91974   #define USBHSCORE_DIEPINT7_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91975   #define USBHSCORE_DIEPINT7_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91976 
91977 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
91978   #define USBHSCORE_DIEPINT7_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
91979   #define USBHSCORE_DIEPINT7_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT7_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
91980   #define USBHSCORE_DIEPINT7_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
91981   #define USBHSCORE_DIEPINT7_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
91982   #define USBHSCORE_DIEPINT7_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
91983   #define USBHSCORE_DIEPINT7_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
91984 
91985 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
91986   #define USBHSCORE_DIEPINT7_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
91987   #define USBHSCORE_DIEPINT7_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT7_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
91988   #define USBHSCORE_DIEPINT7_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
91989   #define USBHSCORE_DIEPINT7_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
91990   #define USBHSCORE_DIEPINT7_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
91991   #define USBHSCORE_DIEPINT7_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
91992 
91993 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
91994   #define USBHSCORE_DIEPINT7_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
91995   #define USBHSCORE_DIEPINT7_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT7_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
91996   #define USBHSCORE_DIEPINT7_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
91997   #define USBHSCORE_DIEPINT7_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
91998   #define USBHSCORE_DIEPINT7_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
91999   #define USBHSCORE_DIEPINT7_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92000 
92001 
92002 /* USBHSCORE_DIEPTSIZ7: Device IN Endpoint 7 Transfer Size Register */
92003   #define USBHSCORE_DIEPTSIZ7_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ7 register.                                */
92004 
92005 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
92006   #define USBHSCORE_DIEPTSIZ7_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
92007   #define USBHSCORE_DIEPTSIZ7_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ7_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
92008 
92009 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
92010   #define USBHSCORE_DIEPTSIZ7_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
92011   #define USBHSCORE_DIEPTSIZ7_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ7_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
92012 
92013 /* MC @Bits 29..30 : MC */
92014   #define USBHSCORE_DIEPTSIZ7_MC_Pos (29UL)          /*!< Position of MC field.                                                */
92015   #define USBHSCORE_DIEPTSIZ7_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ7_MC_Pos) /*!< Bit mask of MC field.                          */
92016   #define USBHSCORE_DIEPTSIZ7_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
92017   #define USBHSCORE_DIEPTSIZ7_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
92018   #define USBHSCORE_DIEPTSIZ7_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
92019   #define USBHSCORE_DIEPTSIZ7_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
92020   #define USBHSCORE_DIEPTSIZ7_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
92021 
92022 
92023 /* USBHSCORE_DIEPDMA7: Device IN Endpoint 7 DMA Address Register */
92024   #define USBHSCORE_DIEPDMA7_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA7 register.                                  */
92025 
92026 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
92027   #define USBHSCORE_DIEPDMA7_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
92028   #define USBHSCORE_DIEPDMA7_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA7_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
92029 
92030 
92031 /* USBHSCORE_DTXFSTS7: Device IN Endpoint Transmit FIFO Status Register 7 */
92032   #define USBHSCORE_DTXFSTS7_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS7 register.                                  */
92033 
92034 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
92035   #define USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
92036   #define USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS7_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
92037                                                                             INEPTXFSPCAVAIL field.*/
92038 
92039 
92040 /* USBHSCORE_DIEPCTL8: Device Control IN Endpoint 8 Control Register */
92041   #define USBHSCORE_DIEPCTL8_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL8 register.                                  */
92042 
92043 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
92044   #define USBHSCORE_DIEPCTL8_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
92045   #define USBHSCORE_DIEPCTL8_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL8_MPS_Pos) /*!< Bit mask of MPS field.                       */
92046 
92047 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
92048   #define USBHSCORE_DIEPCTL8_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
92049   #define USBHSCORE_DIEPCTL8_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL8_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
92050   #define USBHSCORE_DIEPCTL8_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
92051   #define USBHSCORE_DIEPCTL8_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
92052   #define USBHSCORE_DIEPCTL8_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
92053   #define USBHSCORE_DIEPCTL8_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
92054 
92055 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
92056   #define USBHSCORE_DIEPCTL8_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
92057   #define USBHSCORE_DIEPCTL8_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL8_DPID_Pos) /*!< Bit mask of DPID field.                      */
92058   #define USBHSCORE_DIEPCTL8_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
92059   #define USBHSCORE_DIEPCTL8_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
92060   #define USBHSCORE_DIEPCTL8_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
92061   #define USBHSCORE_DIEPCTL8_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
92062 
92063 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
92064   #define USBHSCORE_DIEPCTL8_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
92065   #define USBHSCORE_DIEPCTL8_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL8_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
92066   #define USBHSCORE_DIEPCTL8_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
92067   #define USBHSCORE_DIEPCTL8_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
92068   #define USBHSCORE_DIEPCTL8_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
92069   #define USBHSCORE_DIEPCTL8_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
92070 
92071 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
92072   #define USBHSCORE_DIEPCTL8_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
92073   #define USBHSCORE_DIEPCTL8_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL8_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
92074   #define USBHSCORE_DIEPCTL8_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
92075   #define USBHSCORE_DIEPCTL8_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
92076   #define USBHSCORE_DIEPCTL8_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
92077   #define USBHSCORE_DIEPCTL8_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
92078   #define USBHSCORE_DIEPCTL8_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
92079   #define USBHSCORE_DIEPCTL8_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
92080 
92081 /* STALL @Bit 21 : STALL Handshake (Stall) */
92082   #define USBHSCORE_DIEPCTL8_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
92083   #define USBHSCORE_DIEPCTL8_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL8_STALL_Pos) /*!< Bit mask of STALL field.                   */
92084   #define USBHSCORE_DIEPCTL8_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
92085   #define USBHSCORE_DIEPCTL8_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
92086   #define USBHSCORE_DIEPCTL8_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92087   #define USBHSCORE_DIEPCTL8_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92088 
92089 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
92090   #define USBHSCORE_DIEPCTL8_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
92091   #define USBHSCORE_DIEPCTL8_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL8_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
92092   #define USBHSCORE_DIEPCTL8_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
92093   #define USBHSCORE_DIEPCTL8_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
92094   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
92095   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
92096   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
92097   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
92098   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
92099   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
92100   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
92101   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
92102   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
92103   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
92104   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
92105   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
92106   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
92107   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
92108   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
92109   #define USBHSCORE_DIEPCTL8_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
92110 
92111 /* CNAK @Bit 26 : Clear NAK (CNAK) */
92112   #define USBHSCORE_DIEPCTL8_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
92113   #define USBHSCORE_DIEPCTL8_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL8_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
92114   #define USBHSCORE_DIEPCTL8_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
92115   #define USBHSCORE_DIEPCTL8_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
92116   #define USBHSCORE_DIEPCTL8_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
92117   #define USBHSCORE_DIEPCTL8_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
92118 
92119 /* SNAK @Bit 27 : Set NAK (SNAK) */
92120   #define USBHSCORE_DIEPCTL8_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
92121   #define USBHSCORE_DIEPCTL8_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL8_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
92122   #define USBHSCORE_DIEPCTL8_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
92123   #define USBHSCORE_DIEPCTL8_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
92124   #define USBHSCORE_DIEPCTL8_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
92125   #define USBHSCORE_DIEPCTL8_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
92126 
92127 /* SETD0PID @Bit 28 : SetD0PID */
92128   #define USBHSCORE_DIEPCTL8_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
92129   #define USBHSCORE_DIEPCTL8_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL8_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
92130   #define USBHSCORE_DIEPCTL8_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
92131   #define USBHSCORE_DIEPCTL8_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
92132   #define USBHSCORE_DIEPCTL8_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
92133   #define USBHSCORE_DIEPCTL8_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
92134 
92135 /* SETD1PID @Bit 29 : SetD1PID */
92136   #define USBHSCORE_DIEPCTL8_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
92137   #define USBHSCORE_DIEPCTL8_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL8_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
92138   #define USBHSCORE_DIEPCTL8_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
92139   #define USBHSCORE_DIEPCTL8_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
92140   #define USBHSCORE_DIEPCTL8_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
92141   #define USBHSCORE_DIEPCTL8_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
92142 
92143 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
92144   #define USBHSCORE_DIEPCTL8_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
92145   #define USBHSCORE_DIEPCTL8_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL8_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
92146   #define USBHSCORE_DIEPCTL8_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
92147   #define USBHSCORE_DIEPCTL8_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
92148   #define USBHSCORE_DIEPCTL8_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92149   #define USBHSCORE_DIEPCTL8_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92150 
92151 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
92152   #define USBHSCORE_DIEPCTL8_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
92153   #define USBHSCORE_DIEPCTL8_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL8_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
92154   #define USBHSCORE_DIEPCTL8_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
92155   #define USBHSCORE_DIEPCTL8_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
92156   #define USBHSCORE_DIEPCTL8_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92157   #define USBHSCORE_DIEPCTL8_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92158 
92159 
92160 /* USBHSCORE_DIEPINT8: Device IN Endpoint 8 Interrupt Register */
92161   #define USBHSCORE_DIEPINT8_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT8 register.                                  */
92162 
92163 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
92164   #define USBHSCORE_DIEPINT8_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
92165   #define USBHSCORE_DIEPINT8_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT8_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
92166   #define USBHSCORE_DIEPINT8_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
92167   #define USBHSCORE_DIEPINT8_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
92168   #define USBHSCORE_DIEPINT8_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
92169   #define USBHSCORE_DIEPINT8_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
92170 
92171 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
92172   #define USBHSCORE_DIEPINT8_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
92173   #define USBHSCORE_DIEPINT8_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT8_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
92174   #define USBHSCORE_DIEPINT8_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
92175   #define USBHSCORE_DIEPINT8_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
92176   #define USBHSCORE_DIEPINT8_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
92177   #define USBHSCORE_DIEPINT8_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
92178 
92179 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
92180   #define USBHSCORE_DIEPINT8_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
92181   #define USBHSCORE_DIEPINT8_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT8_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
92182   #define USBHSCORE_DIEPINT8_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
92183   #define USBHSCORE_DIEPINT8_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
92184   #define USBHSCORE_DIEPINT8_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92185   #define USBHSCORE_DIEPINT8_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92186 
92187 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
92188   #define USBHSCORE_DIEPINT8_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
92189   #define USBHSCORE_DIEPINT8_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT8_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
92190   #define USBHSCORE_DIEPINT8_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
92191   #define USBHSCORE_DIEPINT8_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
92192   #define USBHSCORE_DIEPINT8_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
92193   #define USBHSCORE_DIEPINT8_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
92194 
92195 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
92196   #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
92197   #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT8_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
92198   #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
92199   #define USBHSCORE_DIEPINT8_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
92200   #define USBHSCORE_DIEPINT8_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
92201   #define USBHSCORE_DIEPINT8_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
92202 
92203 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
92204   #define USBHSCORE_DIEPINT8_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
92205   #define USBHSCORE_DIEPINT8_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT8_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
92206   #define USBHSCORE_DIEPINT8_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
92207   #define USBHSCORE_DIEPINT8_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
92208   #define USBHSCORE_DIEPINT8_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92209   #define USBHSCORE_DIEPINT8_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92210 
92211 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
92212   #define USBHSCORE_DIEPINT8_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
92213   #define USBHSCORE_DIEPINT8_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT8_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
92214   #define USBHSCORE_DIEPINT8_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
92215   #define USBHSCORE_DIEPINT8_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
92216   #define USBHSCORE_DIEPINT8_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92217   #define USBHSCORE_DIEPINT8_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92218 
92219 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
92220   #define USBHSCORE_DIEPINT8_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
92221   #define USBHSCORE_DIEPINT8_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT8_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
92222   #define USBHSCORE_DIEPINT8_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
92223   #define USBHSCORE_DIEPINT8_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
92224   #define USBHSCORE_DIEPINT8_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92225   #define USBHSCORE_DIEPINT8_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92226 
92227 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
92228   #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
92229   #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT8_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
92230   #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
92231   #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
92232   #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
92233   #define USBHSCORE_DIEPINT8_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
92234 
92235 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
92236   #define USBHSCORE_DIEPINT8_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
92237   #define USBHSCORE_DIEPINT8_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT8_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
92238   #define USBHSCORE_DIEPINT8_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
92239   #define USBHSCORE_DIEPINT8_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
92240   #define USBHSCORE_DIEPINT8_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
92241   #define USBHSCORE_DIEPINT8_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
92242 
92243 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
92244   #define USBHSCORE_DIEPINT8_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
92245   #define USBHSCORE_DIEPINT8_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT8_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
92246   #define USBHSCORE_DIEPINT8_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
92247   #define USBHSCORE_DIEPINT8_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
92248   #define USBHSCORE_DIEPINT8_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
92249   #define USBHSCORE_DIEPINT8_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
92250 
92251 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
92252   #define USBHSCORE_DIEPINT8_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
92253   #define USBHSCORE_DIEPINT8_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT8_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
92254   #define USBHSCORE_DIEPINT8_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
92255   #define USBHSCORE_DIEPINT8_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
92256   #define USBHSCORE_DIEPINT8_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
92257   #define USBHSCORE_DIEPINT8_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
92258 
92259 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
92260   #define USBHSCORE_DIEPINT8_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
92261   #define USBHSCORE_DIEPINT8_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT8_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
92262   #define USBHSCORE_DIEPINT8_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
92263   #define USBHSCORE_DIEPINT8_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
92264   #define USBHSCORE_DIEPINT8_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
92265   #define USBHSCORE_DIEPINT8_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
92266 
92267 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
92268   #define USBHSCORE_DIEPINT8_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
92269   #define USBHSCORE_DIEPINT8_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT8_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
92270   #define USBHSCORE_DIEPINT8_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
92271   #define USBHSCORE_DIEPINT8_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
92272   #define USBHSCORE_DIEPINT8_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92273   #define USBHSCORE_DIEPINT8_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92274 
92275 
92276 /* USBHSCORE_DIEPTSIZ8: Device IN Endpoint 8 Transfer Size Register */
92277   #define USBHSCORE_DIEPTSIZ8_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ8 register.                                */
92278 
92279 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
92280   #define USBHSCORE_DIEPTSIZ8_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
92281   #define USBHSCORE_DIEPTSIZ8_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ8_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
92282 
92283 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
92284   #define USBHSCORE_DIEPTSIZ8_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
92285   #define USBHSCORE_DIEPTSIZ8_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ8_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
92286 
92287 /* MC @Bits 29..30 : MC */
92288   #define USBHSCORE_DIEPTSIZ8_MC_Pos (29UL)          /*!< Position of MC field.                                                */
92289   #define USBHSCORE_DIEPTSIZ8_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ8_MC_Pos) /*!< Bit mask of MC field.                          */
92290   #define USBHSCORE_DIEPTSIZ8_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
92291   #define USBHSCORE_DIEPTSIZ8_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
92292   #define USBHSCORE_DIEPTSIZ8_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
92293   #define USBHSCORE_DIEPTSIZ8_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
92294   #define USBHSCORE_DIEPTSIZ8_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
92295 
92296 
92297 /* USBHSCORE_DIEPDMA8: Device IN Endpoint 8 DMA Address Register */
92298   #define USBHSCORE_DIEPDMA8_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA8 register.                                  */
92299 
92300 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
92301   #define USBHSCORE_DIEPDMA8_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
92302   #define USBHSCORE_DIEPDMA8_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA8_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
92303 
92304 
92305 /* USBHSCORE_DTXFSTS8: Device IN Endpoint Transmit FIFO Status Register 8 */
92306   #define USBHSCORE_DTXFSTS8_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS8 register.                                  */
92307 
92308 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
92309   #define USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
92310   #define USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS8_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
92311                                                                             INEPTXFSPCAVAIL field.*/
92312 
92313 
92314 /* USBHSCORE_DIEPCTL9: Device Control IN Endpoint 9 Control Register */
92315   #define USBHSCORE_DIEPCTL9_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL9 register.                                  */
92316 
92317 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
92318   #define USBHSCORE_DIEPCTL9_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
92319   #define USBHSCORE_DIEPCTL9_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL9_MPS_Pos) /*!< Bit mask of MPS field.                       */
92320 
92321 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
92322   #define USBHSCORE_DIEPCTL9_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
92323   #define USBHSCORE_DIEPCTL9_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL9_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
92324   #define USBHSCORE_DIEPCTL9_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
92325   #define USBHSCORE_DIEPCTL9_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
92326   #define USBHSCORE_DIEPCTL9_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
92327   #define USBHSCORE_DIEPCTL9_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
92328 
92329 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
92330   #define USBHSCORE_DIEPCTL9_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
92331   #define USBHSCORE_DIEPCTL9_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL9_DPID_Pos) /*!< Bit mask of DPID field.                      */
92332   #define USBHSCORE_DIEPCTL9_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
92333   #define USBHSCORE_DIEPCTL9_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
92334   #define USBHSCORE_DIEPCTL9_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                      */
92335   #define USBHSCORE_DIEPCTL9_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                       */
92336 
92337 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
92338   #define USBHSCORE_DIEPCTL9_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
92339   #define USBHSCORE_DIEPCTL9_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL9_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
92340   #define USBHSCORE_DIEPCTL9_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
92341   #define USBHSCORE_DIEPCTL9_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
92342   #define USBHSCORE_DIEPCTL9_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
92343   #define USBHSCORE_DIEPCTL9_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
92344 
92345 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
92346   #define USBHSCORE_DIEPCTL9_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
92347   #define USBHSCORE_DIEPCTL9_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL9_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
92348   #define USBHSCORE_DIEPCTL9_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
92349   #define USBHSCORE_DIEPCTL9_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
92350   #define USBHSCORE_DIEPCTL9_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
92351   #define USBHSCORE_DIEPCTL9_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
92352   #define USBHSCORE_DIEPCTL9_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
92353   #define USBHSCORE_DIEPCTL9_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                        */
92354 
92355 /* STALL @Bit 21 : STALL Handshake (Stall) */
92356   #define USBHSCORE_DIEPCTL9_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
92357   #define USBHSCORE_DIEPCTL9_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL9_STALL_Pos) /*!< Bit mask of STALL field.                   */
92358   #define USBHSCORE_DIEPCTL9_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
92359   #define USBHSCORE_DIEPCTL9_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
92360   #define USBHSCORE_DIEPCTL9_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92361   #define USBHSCORE_DIEPCTL9_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92362 
92363 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
92364   #define USBHSCORE_DIEPCTL9_TXFNUM_Pos (22UL)       /*!< Position of TXFNUM field.                                            */
92365   #define USBHSCORE_DIEPCTL9_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL9_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.                */
92366   #define USBHSCORE_DIEPCTL9_TXFNUM_Min (0x0UL)      /*!< Min enumerator value of TXFNUM field.                                */
92367   #define USBHSCORE_DIEPCTL9_TXFNUM_Max (0xFUL)      /*!< Max enumerator value of TXFNUM field.                                */
92368   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO0 (0x0UL)  /*!< (unspecified)                                                        */
92369   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO1 (0x1UL)  /*!< (unspecified)                                                        */
92370   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO2 (0x2UL)  /*!< (unspecified)                                                        */
92371   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO3 (0x3UL)  /*!< (unspecified)                                                        */
92372   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO4 (0x4UL)  /*!< (unspecified)                                                        */
92373   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO5 (0x5UL)  /*!< (unspecified)                                                        */
92374   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO6 (0x6UL)  /*!< (unspecified)                                                        */
92375   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO7 (0x7UL)  /*!< (unspecified)                                                        */
92376   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO8 (0x8UL)  /*!< (unspecified)                                                        */
92377   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO9 (0x9UL)  /*!< (unspecified)                                                        */
92378   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                        */
92379   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                        */
92380   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                        */
92381   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                        */
92382   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                        */
92383   #define USBHSCORE_DIEPCTL9_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                        */
92384 
92385 /* CNAK @Bit 26 : Clear NAK (CNAK) */
92386   #define USBHSCORE_DIEPCTL9_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
92387   #define USBHSCORE_DIEPCTL9_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL9_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
92388   #define USBHSCORE_DIEPCTL9_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
92389   #define USBHSCORE_DIEPCTL9_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
92390   #define USBHSCORE_DIEPCTL9_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
92391   #define USBHSCORE_DIEPCTL9_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
92392 
92393 /* SNAK @Bit 27 : Set NAK (SNAK) */
92394   #define USBHSCORE_DIEPCTL9_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
92395   #define USBHSCORE_DIEPCTL9_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL9_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
92396   #define USBHSCORE_DIEPCTL9_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
92397   #define USBHSCORE_DIEPCTL9_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
92398   #define USBHSCORE_DIEPCTL9_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
92399   #define USBHSCORE_DIEPCTL9_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
92400 
92401 /* SETD0PID @Bit 28 : SetD0PID */
92402   #define USBHSCORE_DIEPCTL9_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
92403   #define USBHSCORE_DIEPCTL9_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL9_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
92404   #define USBHSCORE_DIEPCTL9_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
92405   #define USBHSCORE_DIEPCTL9_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
92406   #define USBHSCORE_DIEPCTL9_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
92407   #define USBHSCORE_DIEPCTL9_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
92408 
92409 /* SETD1PID @Bit 29 : SetD1PID */
92410   #define USBHSCORE_DIEPCTL9_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
92411   #define USBHSCORE_DIEPCTL9_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL9_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
92412   #define USBHSCORE_DIEPCTL9_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
92413   #define USBHSCORE_DIEPCTL9_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
92414   #define USBHSCORE_DIEPCTL9_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
92415   #define USBHSCORE_DIEPCTL9_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
92416 
92417 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
92418   #define USBHSCORE_DIEPCTL9_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
92419   #define USBHSCORE_DIEPCTL9_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL9_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
92420   #define USBHSCORE_DIEPCTL9_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
92421   #define USBHSCORE_DIEPCTL9_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
92422   #define USBHSCORE_DIEPCTL9_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92423   #define USBHSCORE_DIEPCTL9_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92424 
92425 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
92426   #define USBHSCORE_DIEPCTL9_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
92427   #define USBHSCORE_DIEPCTL9_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL9_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
92428   #define USBHSCORE_DIEPCTL9_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
92429   #define USBHSCORE_DIEPCTL9_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
92430   #define USBHSCORE_DIEPCTL9_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92431   #define USBHSCORE_DIEPCTL9_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92432 
92433 
92434 /* USBHSCORE_DIEPINT9: Device IN Endpoint 9 Interrupt Register */
92435   #define USBHSCORE_DIEPINT9_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT9 register.                                  */
92436 
92437 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
92438   #define USBHSCORE_DIEPINT9_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
92439   #define USBHSCORE_DIEPINT9_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT9_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
92440   #define USBHSCORE_DIEPINT9_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
92441   #define USBHSCORE_DIEPINT9_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
92442   #define USBHSCORE_DIEPINT9_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
92443   #define USBHSCORE_DIEPINT9_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
92444 
92445 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
92446   #define USBHSCORE_DIEPINT9_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
92447   #define USBHSCORE_DIEPINT9_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT9_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
92448   #define USBHSCORE_DIEPINT9_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
92449   #define USBHSCORE_DIEPINT9_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
92450   #define USBHSCORE_DIEPINT9_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
92451   #define USBHSCORE_DIEPINT9_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
92452 
92453 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
92454   #define USBHSCORE_DIEPINT9_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
92455   #define USBHSCORE_DIEPINT9_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT9_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
92456   #define USBHSCORE_DIEPINT9_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
92457   #define USBHSCORE_DIEPINT9_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
92458   #define USBHSCORE_DIEPINT9_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92459   #define USBHSCORE_DIEPINT9_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92460 
92461 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
92462   #define USBHSCORE_DIEPINT9_TIMEOUT_Pos (3UL)       /*!< Position of TIMEOUT field.                                           */
92463   #define USBHSCORE_DIEPINT9_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT9_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.             */
92464   #define USBHSCORE_DIEPINT9_TIMEOUT_Min (0x0UL)     /*!< Min enumerator value of TIMEOUT field.                               */
92465   #define USBHSCORE_DIEPINT9_TIMEOUT_Max (0x1UL)     /*!< Max enumerator value of TIMEOUT field.                               */
92466   #define USBHSCORE_DIEPINT9_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
92467   #define USBHSCORE_DIEPINT9_TIMEOUT_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
92468 
92469 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
92470   #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Pos (4UL)   /*!< Position of INTKNTXFEMP field.                                       */
92471   #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT9_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP field. */
92472   #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                           */
92473   #define USBHSCORE_DIEPINT9_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                           */
92474   #define USBHSCORE_DIEPINT9_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
92475   #define USBHSCORE_DIEPINT9_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
92476 
92477 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
92478   #define USBHSCORE_DIEPINT9_INTKNEPMIS_Pos (5UL)    /*!< Position of INTKNEPMIS field.                                        */
92479   #define USBHSCORE_DIEPINT9_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT9_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.    */
92480   #define USBHSCORE_DIEPINT9_INTKNEPMIS_Min (0x0UL)  /*!< Min enumerator value of INTKNEPMIS field.                            */
92481   #define USBHSCORE_DIEPINT9_INTKNEPMIS_Max (0x1UL)  /*!< Max enumerator value of INTKNEPMIS field.                            */
92482   #define USBHSCORE_DIEPINT9_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92483   #define USBHSCORE_DIEPINT9_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92484 
92485 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
92486   #define USBHSCORE_DIEPINT9_INEPNAKEFF_Pos (6UL)    /*!< Position of INEPNAKEFF field.                                        */
92487   #define USBHSCORE_DIEPINT9_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT9_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.    */
92488   #define USBHSCORE_DIEPINT9_INEPNAKEFF_Min (0x0UL)  /*!< Min enumerator value of INEPNAKEFF field.                            */
92489   #define USBHSCORE_DIEPINT9_INEPNAKEFF_Max (0x1UL)  /*!< Max enumerator value of INEPNAKEFF field.                            */
92490   #define USBHSCORE_DIEPINT9_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92491   #define USBHSCORE_DIEPINT9_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92492 
92493 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
92494   #define USBHSCORE_DIEPINT9_TXFEMP_Pos (7UL)        /*!< Position of TXFEMP field.                                            */
92495   #define USBHSCORE_DIEPINT9_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT9_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.                */
92496   #define USBHSCORE_DIEPINT9_TXFEMP_Min (0x0UL)      /*!< Min enumerator value of TXFEMP field.                                */
92497   #define USBHSCORE_DIEPINT9_TXFEMP_Max (0x1UL)      /*!< Max enumerator value of TXFEMP field.                                */
92498   #define USBHSCORE_DIEPINT9_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92499   #define USBHSCORE_DIEPINT9_TXFEMP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92500 
92501 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
92502   #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Pos (8UL)   /*!< Position of TXFIFOUNDRN field.                                       */
92503   #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT9_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN field. */
92504   #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                           */
92505   #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                           */
92506   #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
92507   #define USBHSCORE_DIEPINT9_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
92508 
92509 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
92510   #define USBHSCORE_DIEPINT9_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
92511   #define USBHSCORE_DIEPINT9_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT9_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
92512   #define USBHSCORE_DIEPINT9_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
92513   #define USBHSCORE_DIEPINT9_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
92514   #define USBHSCORE_DIEPINT9_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
92515   #define USBHSCORE_DIEPINT9_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
92516 
92517 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
92518   #define USBHSCORE_DIEPINT9_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
92519   #define USBHSCORE_DIEPINT9_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT9_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
92520   #define USBHSCORE_DIEPINT9_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
92521   #define USBHSCORE_DIEPINT9_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
92522   #define USBHSCORE_DIEPINT9_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
92523   #define USBHSCORE_DIEPINT9_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
92524 
92525 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
92526   #define USBHSCORE_DIEPINT9_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
92527   #define USBHSCORE_DIEPINT9_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT9_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
92528   #define USBHSCORE_DIEPINT9_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
92529   #define USBHSCORE_DIEPINT9_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
92530   #define USBHSCORE_DIEPINT9_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
92531   #define USBHSCORE_DIEPINT9_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
92532 
92533 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
92534   #define USBHSCORE_DIEPINT9_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
92535   #define USBHSCORE_DIEPINT9_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT9_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
92536   #define USBHSCORE_DIEPINT9_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
92537   #define USBHSCORE_DIEPINT9_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
92538   #define USBHSCORE_DIEPINT9_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
92539   #define USBHSCORE_DIEPINT9_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
92540 
92541 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
92542   #define USBHSCORE_DIEPINT9_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
92543   #define USBHSCORE_DIEPINT9_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT9_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
92544   #define USBHSCORE_DIEPINT9_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
92545   #define USBHSCORE_DIEPINT9_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
92546   #define USBHSCORE_DIEPINT9_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92547   #define USBHSCORE_DIEPINT9_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92548 
92549 
92550 /* USBHSCORE_DIEPTSIZ9: Device IN Endpoint 9 Transfer Size Register */
92551   #define USBHSCORE_DIEPTSIZ9_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ9 register.                                */
92552 
92553 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
92554   #define USBHSCORE_DIEPTSIZ9_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
92555   #define USBHSCORE_DIEPTSIZ9_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ9_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
92556 
92557 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
92558   #define USBHSCORE_DIEPTSIZ9_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
92559   #define USBHSCORE_DIEPTSIZ9_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ9_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
92560 
92561 /* MC @Bits 29..30 : MC */
92562   #define USBHSCORE_DIEPTSIZ9_MC_Pos (29UL)          /*!< Position of MC field.                                                */
92563   #define USBHSCORE_DIEPTSIZ9_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ9_MC_Pos) /*!< Bit mask of MC field.                          */
92564   #define USBHSCORE_DIEPTSIZ9_MC_Min (0x1UL)         /*!< Min enumerator value of MC field.                                    */
92565   #define USBHSCORE_DIEPTSIZ9_MC_Max (0x3UL)         /*!< Max enumerator value of MC field.                                    */
92566   #define USBHSCORE_DIEPTSIZ9_MC_PACKETONE (0x1UL)   /*!< (unspecified)                                                        */
92567   #define USBHSCORE_DIEPTSIZ9_MC_PACKETTWO (0x2UL)   /*!< (unspecified)                                                        */
92568   #define USBHSCORE_DIEPTSIZ9_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                        */
92569 
92570 
92571 /* USBHSCORE_DIEPDMA9: Device IN Endpoint 9 DMA Address Register */
92572   #define USBHSCORE_DIEPDMA9_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA9 register.                                  */
92573 
92574 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
92575   #define USBHSCORE_DIEPDMA9_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
92576   #define USBHSCORE_DIEPDMA9_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA9_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
92577 
92578 
92579 /* USBHSCORE_DTXFSTS9: Device IN Endpoint Transmit FIFO Status Register 9 */
92580   #define USBHSCORE_DTXFSTS9_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS9 register.                                  */
92581 
92582 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
92583   #define USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                 */
92584   #define USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS9_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
92585                                                                             INEPTXFSPCAVAIL field.*/
92586 
92587 
92588 /* USBHSCORE_DIEPCTL10: Device Control IN Endpoint 10 Control Register */
92589   #define USBHSCORE_DIEPCTL10_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL10 register.                                */
92590 
92591 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
92592   #define USBHSCORE_DIEPCTL10_MPS_Pos (0UL)          /*!< Position of MPS field.                                               */
92593   #define USBHSCORE_DIEPCTL10_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL10_MPS_Pos) /*!< Bit mask of MPS field.                     */
92594 
92595 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
92596   #define USBHSCORE_DIEPCTL10_USBACTEP_Pos (15UL)    /*!< Position of USBACTEP field.                                          */
92597   #define USBHSCORE_DIEPCTL10_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL10_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.        */
92598   #define USBHSCORE_DIEPCTL10_USBACTEP_Min (0x0UL)   /*!< Min enumerator value of USBACTEP field.                              */
92599   #define USBHSCORE_DIEPCTL10_USBACTEP_Max (0x1UL)   /*!< Max enumerator value of USBACTEP field.                              */
92600   #define USBHSCORE_DIEPCTL10_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                     */
92601   #define USBHSCORE_DIEPCTL10_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                      */
92602 
92603 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
92604   #define USBHSCORE_DIEPCTL10_DPID_Pos (16UL)        /*!< Position of DPID field.                                              */
92605   #define USBHSCORE_DIEPCTL10_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL10_DPID_Pos) /*!< Bit mask of DPID field.                    */
92606   #define USBHSCORE_DIEPCTL10_DPID_Min (0x0UL)       /*!< Min enumerator value of DPID field.                                  */
92607   #define USBHSCORE_DIEPCTL10_DPID_Max (0x1UL)       /*!< Max enumerator value of DPID field.                                  */
92608   #define USBHSCORE_DIEPCTL10_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                     */
92609   #define USBHSCORE_DIEPCTL10_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                      */
92610 
92611 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
92612   #define USBHSCORE_DIEPCTL10_NAKSTS_Pos (17UL)      /*!< Position of NAKSTS field.                                            */
92613   #define USBHSCORE_DIEPCTL10_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL10_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.              */
92614   #define USBHSCORE_DIEPCTL10_NAKSTS_Min (0x0UL)     /*!< Min enumerator value of NAKSTS field.                                */
92615   #define USBHSCORE_DIEPCTL10_NAKSTS_Max (0x1UL)     /*!< Max enumerator value of NAKSTS field.                                */
92616   #define USBHSCORE_DIEPCTL10_NAKSTS_NONNAK (0x0UL)  /*!< (unspecified)                                                        */
92617   #define USBHSCORE_DIEPCTL10_NAKSTS_NAK (0x1UL)     /*!< (unspecified)                                                        */
92618 
92619 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
92620   #define USBHSCORE_DIEPCTL10_EPTYPE_Pos (18UL)      /*!< Position of EPTYPE field.                                            */
92621   #define USBHSCORE_DIEPCTL10_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL10_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.              */
92622   #define USBHSCORE_DIEPCTL10_EPTYPE_Min (0x0UL)     /*!< Min enumerator value of EPTYPE field.                                */
92623   #define USBHSCORE_DIEPCTL10_EPTYPE_Max (0x3UL)     /*!< Max enumerator value of EPTYPE field.                                */
92624   #define USBHSCORE_DIEPCTL10_EPTYPE_CONTROL (0x0UL) /*!< (unspecified)                                                        */
92625   #define USBHSCORE_DIEPCTL10_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                    */
92626   #define USBHSCORE_DIEPCTL10_EPTYPE_BULK (0x2UL)    /*!< (unspecified)                                                        */
92627   #define USBHSCORE_DIEPCTL10_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                       */
92628 
92629 /* STALL @Bit 21 : STALL Handshake (Stall) */
92630   #define USBHSCORE_DIEPCTL10_STALL_Pos (21UL)       /*!< Position of STALL field.                                             */
92631   #define USBHSCORE_DIEPCTL10_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL10_STALL_Pos) /*!< Bit mask of STALL field.                 */
92632   #define USBHSCORE_DIEPCTL10_STALL_Min (0x0UL)      /*!< Min enumerator value of STALL field.                                 */
92633   #define USBHSCORE_DIEPCTL10_STALL_Max (0x1UL)      /*!< Max enumerator value of STALL field.                                 */
92634   #define USBHSCORE_DIEPCTL10_STALL_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92635   #define USBHSCORE_DIEPCTL10_STALL_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92636 
92637 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
92638   #define USBHSCORE_DIEPCTL10_TXFNUM_Pos (22UL)      /*!< Position of TXFNUM field.                                            */
92639   #define USBHSCORE_DIEPCTL10_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL10_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.              */
92640   #define USBHSCORE_DIEPCTL10_TXFNUM_Min (0x0UL)     /*!< Min enumerator value of TXFNUM field.                                */
92641   #define USBHSCORE_DIEPCTL10_TXFNUM_Max (0xFUL)     /*!< Max enumerator value of TXFNUM field.                                */
92642   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO0 (0x0UL) /*!< (unspecified)                                                        */
92643   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO1 (0x1UL) /*!< (unspecified)                                                        */
92644   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO2 (0x2UL) /*!< (unspecified)                                                        */
92645   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO3 (0x3UL) /*!< (unspecified)                                                        */
92646   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO4 (0x4UL) /*!< (unspecified)                                                        */
92647   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO5 (0x5UL) /*!< (unspecified)                                                        */
92648   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO6 (0x6UL) /*!< (unspecified)                                                        */
92649   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO7 (0x7UL) /*!< (unspecified)                                                        */
92650   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO8 (0x8UL) /*!< (unspecified)                                                        */
92651   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO9 (0x9UL) /*!< (unspecified)                                                        */
92652   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                       */
92653   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                       */
92654   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                       */
92655   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                       */
92656   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                       */
92657   #define USBHSCORE_DIEPCTL10_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                       */
92658 
92659 /* CNAK @Bit 26 : Clear NAK (CNAK) */
92660   #define USBHSCORE_DIEPCTL10_CNAK_Pos (26UL)        /*!< Position of CNAK field.                                              */
92661   #define USBHSCORE_DIEPCTL10_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL10_CNAK_Pos) /*!< Bit mask of CNAK field.                    */
92662   #define USBHSCORE_DIEPCTL10_CNAK_Min (0x0UL)       /*!< Min enumerator value of CNAK field.                                  */
92663   #define USBHSCORE_DIEPCTL10_CNAK_Max (0x1UL)       /*!< Max enumerator value of CNAK field.                                  */
92664   #define USBHSCORE_DIEPCTL10_CNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92665   #define USBHSCORE_DIEPCTL10_CNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92666 
92667 /* SNAK @Bit 27 : Set NAK (SNAK) */
92668   #define USBHSCORE_DIEPCTL10_SNAK_Pos (27UL)        /*!< Position of SNAK field.                                              */
92669   #define USBHSCORE_DIEPCTL10_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL10_SNAK_Pos) /*!< Bit mask of SNAK field.                    */
92670   #define USBHSCORE_DIEPCTL10_SNAK_Min (0x0UL)       /*!< Min enumerator value of SNAK field.                                  */
92671   #define USBHSCORE_DIEPCTL10_SNAK_Max (0x1UL)       /*!< Max enumerator value of SNAK field.                                  */
92672   #define USBHSCORE_DIEPCTL10_SNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92673   #define USBHSCORE_DIEPCTL10_SNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92674 
92675 /* SETD0PID @Bit 28 : SetD0PID */
92676   #define USBHSCORE_DIEPCTL10_SETD0PID_Pos (28UL)    /*!< Position of SETD0PID field.                                          */
92677   #define USBHSCORE_DIEPCTL10_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL10_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.        */
92678   #define USBHSCORE_DIEPCTL10_SETD0PID_Min (0x0UL)   /*!< Min enumerator value of SETD0PID field.                              */
92679   #define USBHSCORE_DIEPCTL10_SETD0PID_Max (0x1UL)   /*!< Max enumerator value of SETD0PID field.                              */
92680   #define USBHSCORE_DIEPCTL10_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
92681   #define USBHSCORE_DIEPCTL10_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
92682 
92683 /* SETD1PID @Bit 29 : SetD1PID */
92684   #define USBHSCORE_DIEPCTL10_SETD1PID_Pos (29UL)    /*!< Position of SETD1PID field.                                          */
92685   #define USBHSCORE_DIEPCTL10_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL10_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.        */
92686   #define USBHSCORE_DIEPCTL10_SETD1PID_Min (0x0UL)   /*!< Min enumerator value of SETD1PID field.                              */
92687   #define USBHSCORE_DIEPCTL10_SETD1PID_Max (0x1UL)   /*!< Max enumerator value of SETD1PID field.                              */
92688   #define USBHSCORE_DIEPCTL10_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
92689   #define USBHSCORE_DIEPCTL10_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
92690 
92691 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
92692   #define USBHSCORE_DIEPCTL10_EPDIS_Pos (30UL)       /*!< Position of EPDIS field.                                             */
92693   #define USBHSCORE_DIEPCTL10_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL10_EPDIS_Pos) /*!< Bit mask of EPDIS field.                 */
92694   #define USBHSCORE_DIEPCTL10_EPDIS_Min (0x0UL)      /*!< Min enumerator value of EPDIS field.                                 */
92695   #define USBHSCORE_DIEPCTL10_EPDIS_Max (0x1UL)      /*!< Max enumerator value of EPDIS field.                                 */
92696   #define USBHSCORE_DIEPCTL10_EPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92697   #define USBHSCORE_DIEPCTL10_EPDIS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92698 
92699 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
92700   #define USBHSCORE_DIEPCTL10_EPENA_Pos (31UL)       /*!< Position of EPENA field.                                             */
92701   #define USBHSCORE_DIEPCTL10_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL10_EPENA_Pos) /*!< Bit mask of EPENA field.                 */
92702   #define USBHSCORE_DIEPCTL10_EPENA_Min (0x0UL)      /*!< Min enumerator value of EPENA field.                                 */
92703   #define USBHSCORE_DIEPCTL10_EPENA_Max (0x1UL)      /*!< Max enumerator value of EPENA field.                                 */
92704   #define USBHSCORE_DIEPCTL10_EPENA_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92705   #define USBHSCORE_DIEPCTL10_EPENA_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92706 
92707 
92708 /* USBHSCORE_DIEPINT10: Device IN Endpoint 10 Interrupt Register */
92709   #define USBHSCORE_DIEPINT10_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT10 register.                                */
92710 
92711 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
92712   #define USBHSCORE_DIEPINT10_XFERCOMPL_Pos (0UL)    /*!< Position of XFERCOMPL field.                                         */
92713   #define USBHSCORE_DIEPINT10_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT10_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.     */
92714   #define USBHSCORE_DIEPINT10_XFERCOMPL_Min (0x0UL)  /*!< Min enumerator value of XFERCOMPL field.                             */
92715   #define USBHSCORE_DIEPINT10_XFERCOMPL_Max (0x1UL)  /*!< Max enumerator value of XFERCOMPL field.                             */
92716   #define USBHSCORE_DIEPINT10_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92717   #define USBHSCORE_DIEPINT10_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92718 
92719 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
92720   #define USBHSCORE_DIEPINT10_EPDISBLD_Pos (1UL)     /*!< Position of EPDISBLD field.                                          */
92721   #define USBHSCORE_DIEPINT10_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT10_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.        */
92722   #define USBHSCORE_DIEPINT10_EPDISBLD_Min (0x0UL)   /*!< Min enumerator value of EPDISBLD field.                              */
92723   #define USBHSCORE_DIEPINT10_EPDISBLD_Max (0x1UL)   /*!< Max enumerator value of EPDISBLD field.                              */
92724   #define USBHSCORE_DIEPINT10_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
92725   #define USBHSCORE_DIEPINT10_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
92726 
92727 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
92728   #define USBHSCORE_DIEPINT10_AHBERR_Pos (2UL)       /*!< Position of AHBERR field.                                            */
92729   #define USBHSCORE_DIEPINT10_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT10_AHBERR_Pos) /*!< Bit mask of AHBERR field.              */
92730   #define USBHSCORE_DIEPINT10_AHBERR_Min (0x0UL)     /*!< Min enumerator value of AHBERR field.                                */
92731   #define USBHSCORE_DIEPINT10_AHBERR_Max (0x1UL)     /*!< Max enumerator value of AHBERR field.                                */
92732   #define USBHSCORE_DIEPINT10_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
92733   #define USBHSCORE_DIEPINT10_AHBERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
92734 
92735 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
92736   #define USBHSCORE_DIEPINT10_TIMEOUT_Pos (3UL)      /*!< Position of TIMEOUT field.                                           */
92737   #define USBHSCORE_DIEPINT10_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT10_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.           */
92738   #define USBHSCORE_DIEPINT10_TIMEOUT_Min (0x0UL)    /*!< Min enumerator value of TIMEOUT field.                               */
92739   #define USBHSCORE_DIEPINT10_TIMEOUT_Max (0x1UL)    /*!< Max enumerator value of TIMEOUT field.                               */
92740   #define USBHSCORE_DIEPINT10_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
92741   #define USBHSCORE_DIEPINT10_TIMEOUT_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
92742 
92743 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
92744   #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Pos (4UL)  /*!< Position of INTKNTXFEMP field.                                       */
92745   #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT10_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP
92746                                                                             field.*/
92747   #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                          */
92748   #define USBHSCORE_DIEPINT10_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                          */
92749   #define USBHSCORE_DIEPINT10_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
92750   #define USBHSCORE_DIEPINT10_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
92751 
92752 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
92753   #define USBHSCORE_DIEPINT10_INTKNEPMIS_Pos (5UL)   /*!< Position of INTKNEPMIS field.                                        */
92754   #define USBHSCORE_DIEPINT10_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT10_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.  */
92755   #define USBHSCORE_DIEPINT10_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field.                            */
92756   #define USBHSCORE_DIEPINT10_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field.                            */
92757   #define USBHSCORE_DIEPINT10_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
92758   #define USBHSCORE_DIEPINT10_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
92759 
92760 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
92761   #define USBHSCORE_DIEPINT10_INEPNAKEFF_Pos (6UL)   /*!< Position of INEPNAKEFF field.                                        */
92762   #define USBHSCORE_DIEPINT10_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT10_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.  */
92763   #define USBHSCORE_DIEPINT10_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field.                            */
92764   #define USBHSCORE_DIEPINT10_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field.                            */
92765   #define USBHSCORE_DIEPINT10_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
92766   #define USBHSCORE_DIEPINT10_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
92767 
92768 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
92769   #define USBHSCORE_DIEPINT10_TXFEMP_Pos (7UL)       /*!< Position of TXFEMP field.                                            */
92770   #define USBHSCORE_DIEPINT10_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT10_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.              */
92771   #define USBHSCORE_DIEPINT10_TXFEMP_Min (0x0UL)     /*!< Min enumerator value of TXFEMP field.                                */
92772   #define USBHSCORE_DIEPINT10_TXFEMP_Max (0x1UL)     /*!< Max enumerator value of TXFEMP field.                                */
92773   #define USBHSCORE_DIEPINT10_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
92774   #define USBHSCORE_DIEPINT10_TXFEMP_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
92775 
92776 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
92777   #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Pos (8UL)  /*!< Position of TXFIFOUNDRN field.                                       */
92778   #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT10_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN
92779                                                                             field.*/
92780   #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                          */
92781   #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                          */
92782   #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
92783   #define USBHSCORE_DIEPINT10_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
92784 
92785 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
92786   #define USBHSCORE_DIEPINT10_BNAINTR_Pos (9UL)      /*!< Position of BNAINTR field.                                           */
92787   #define USBHSCORE_DIEPINT10_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT10_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.           */
92788   #define USBHSCORE_DIEPINT10_BNAINTR_Min (0x0UL)    /*!< Min enumerator value of BNAINTR field.                               */
92789   #define USBHSCORE_DIEPINT10_BNAINTR_Max (0x1UL)    /*!< Max enumerator value of BNAINTR field.                               */
92790   #define USBHSCORE_DIEPINT10_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
92791   #define USBHSCORE_DIEPINT10_BNAINTR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
92792 
92793 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
92794   #define USBHSCORE_DIEPINT10_PKTDRPSTS_Pos (11UL)   /*!< Position of PKTDRPSTS field.                                         */
92795   #define USBHSCORE_DIEPINT10_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT10_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.     */
92796   #define USBHSCORE_DIEPINT10_PKTDRPSTS_Min (0x0UL)  /*!< Min enumerator value of PKTDRPSTS field.                             */
92797   #define USBHSCORE_DIEPINT10_PKTDRPSTS_Max (0x1UL)  /*!< Max enumerator value of PKTDRPSTS field.                             */
92798   #define USBHSCORE_DIEPINT10_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92799   #define USBHSCORE_DIEPINT10_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92800 
92801 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
92802   #define USBHSCORE_DIEPINT10_BBLEERR_Pos (12UL)     /*!< Position of BBLEERR field.                                           */
92803   #define USBHSCORE_DIEPINT10_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT10_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.           */
92804   #define USBHSCORE_DIEPINT10_BBLEERR_Min (0x0UL)    /*!< Min enumerator value of BBLEERR field.                               */
92805   #define USBHSCORE_DIEPINT10_BBLEERR_Max (0x1UL)    /*!< Max enumerator value of BBLEERR field.                               */
92806   #define USBHSCORE_DIEPINT10_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
92807   #define USBHSCORE_DIEPINT10_BBLEERR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
92808 
92809 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
92810   #define USBHSCORE_DIEPINT10_NAKINTRPT_Pos (13UL)   /*!< Position of NAKINTRPT field.                                         */
92811   #define USBHSCORE_DIEPINT10_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT10_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.     */
92812   #define USBHSCORE_DIEPINT10_NAKINTRPT_Min (0x0UL)  /*!< Min enumerator value of NAKINTRPT field.                             */
92813   #define USBHSCORE_DIEPINT10_NAKINTRPT_Max (0x1UL)  /*!< Max enumerator value of NAKINTRPT field.                             */
92814   #define USBHSCORE_DIEPINT10_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92815   #define USBHSCORE_DIEPINT10_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92816 
92817 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
92818   #define USBHSCORE_DIEPINT10_NYETINTRPT_Pos (14UL)  /*!< Position of NYETINTRPT field.                                        */
92819   #define USBHSCORE_DIEPINT10_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT10_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.  */
92820   #define USBHSCORE_DIEPINT10_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field.                            */
92821   #define USBHSCORE_DIEPINT10_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field.                            */
92822   #define USBHSCORE_DIEPINT10_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
92823   #define USBHSCORE_DIEPINT10_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
92824 
92825 
92826 /* USBHSCORE_DIEPTSIZ10: Device IN Endpoint 10 Transfer Size Register */
92827   #define USBHSCORE_DIEPTSIZ10_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ10 register.                              */
92828 
92829 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
92830   #define USBHSCORE_DIEPTSIZ10_XFERSIZE_Pos (0UL)    /*!< Position of XFERSIZE field.                                          */
92831   #define USBHSCORE_DIEPTSIZ10_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ10_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.  */
92832 
92833 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
92834   #define USBHSCORE_DIEPTSIZ10_PKTCNT_Pos (19UL)     /*!< Position of PKTCNT field.                                            */
92835   #define USBHSCORE_DIEPTSIZ10_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ10_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.          */
92836 
92837 /* MC @Bits 29..30 : MC */
92838   #define USBHSCORE_DIEPTSIZ10_MC_Pos (29UL)         /*!< Position of MC field.                                                */
92839   #define USBHSCORE_DIEPTSIZ10_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ10_MC_Pos) /*!< Bit mask of MC field.                        */
92840   #define USBHSCORE_DIEPTSIZ10_MC_Min (0x1UL)        /*!< Min enumerator value of MC field.                                    */
92841   #define USBHSCORE_DIEPTSIZ10_MC_Max (0x3UL)        /*!< Max enumerator value of MC field.                                    */
92842   #define USBHSCORE_DIEPTSIZ10_MC_PACKETONE (0x1UL)  /*!< (unspecified)                                                        */
92843   #define USBHSCORE_DIEPTSIZ10_MC_PACKETTWO (0x2UL)  /*!< (unspecified)                                                        */
92844   #define USBHSCORE_DIEPTSIZ10_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                       */
92845 
92846 
92847 /* USBHSCORE_DIEPDMA10: Device IN Endpoint 10 DMA Address Register */
92848   #define USBHSCORE_DIEPDMA10_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA10 register.                                */
92849 
92850 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
92851   #define USBHSCORE_DIEPDMA10_DMAADDR_Pos (0UL)      /*!< Position of DMAADDR field.                                           */
92852   #define USBHSCORE_DIEPDMA10_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA10_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.    */
92853 
92854 
92855 /* USBHSCORE_DTXFSTS10: Device IN Endpoint Transmit FIFO Status Register 10 */
92856   #define USBHSCORE_DTXFSTS10_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS10 register.                                */
92857 
92858 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
92859   #define USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                */
92860   #define USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS10_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
92861                                                                             INEPTXFSPCAVAIL field.*/
92862 
92863 
92864 /* USBHSCORE_DIEPCTL11: Device Control IN Endpoint 11 Control Register */
92865   #define USBHSCORE_DIEPCTL11_ResetValue (0x00000000UL) /*!< Reset value of DIEPCTL11 register.                                */
92866 
92867 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
92868   #define USBHSCORE_DIEPCTL11_MPS_Pos (0UL)          /*!< Position of MPS field.                                               */
92869   #define USBHSCORE_DIEPCTL11_MPS_Msk (0x7FFUL << USBHSCORE_DIEPCTL11_MPS_Pos) /*!< Bit mask of MPS field.                     */
92870 
92871 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
92872   #define USBHSCORE_DIEPCTL11_USBACTEP_Pos (15UL)    /*!< Position of USBACTEP field.                                          */
92873   #define USBHSCORE_DIEPCTL11_USBACTEP_Msk (0x1UL << USBHSCORE_DIEPCTL11_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.        */
92874   #define USBHSCORE_DIEPCTL11_USBACTEP_Min (0x0UL)   /*!< Min enumerator value of USBACTEP field.                              */
92875   #define USBHSCORE_DIEPCTL11_USBACTEP_Max (0x1UL)   /*!< Max enumerator value of USBACTEP field.                              */
92876   #define USBHSCORE_DIEPCTL11_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                     */
92877   #define USBHSCORE_DIEPCTL11_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                      */
92878 
92879 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
92880   #define USBHSCORE_DIEPCTL11_DPID_Pos (16UL)        /*!< Position of DPID field.                                              */
92881   #define USBHSCORE_DIEPCTL11_DPID_Msk (0x1UL << USBHSCORE_DIEPCTL11_DPID_Pos) /*!< Bit mask of DPID field.                    */
92882   #define USBHSCORE_DIEPCTL11_DPID_Min (0x0UL)       /*!< Min enumerator value of DPID field.                                  */
92883   #define USBHSCORE_DIEPCTL11_DPID_Max (0x1UL)       /*!< Max enumerator value of DPID field.                                  */
92884   #define USBHSCORE_DIEPCTL11_DPID_DATA0EVENFRM (0x0UL) /*!< (unspecified)                                                     */
92885   #define USBHSCORE_DIEPCTL11_DPID_DATA1ODDFRM (0x1UL) /*!< (unspecified)                                                      */
92886 
92887 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
92888   #define USBHSCORE_DIEPCTL11_NAKSTS_Pos (17UL)      /*!< Position of NAKSTS field.                                            */
92889   #define USBHSCORE_DIEPCTL11_NAKSTS_Msk (0x1UL << USBHSCORE_DIEPCTL11_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.              */
92890   #define USBHSCORE_DIEPCTL11_NAKSTS_Min (0x0UL)     /*!< Min enumerator value of NAKSTS field.                                */
92891   #define USBHSCORE_DIEPCTL11_NAKSTS_Max (0x1UL)     /*!< Max enumerator value of NAKSTS field.                                */
92892   #define USBHSCORE_DIEPCTL11_NAKSTS_NONNAK (0x0UL)  /*!< (unspecified)                                                        */
92893   #define USBHSCORE_DIEPCTL11_NAKSTS_NAK (0x1UL)     /*!< (unspecified)                                                        */
92894 
92895 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
92896   #define USBHSCORE_DIEPCTL11_EPTYPE_Pos (18UL)      /*!< Position of EPTYPE field.                                            */
92897   #define USBHSCORE_DIEPCTL11_EPTYPE_Msk (0x3UL << USBHSCORE_DIEPCTL11_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.              */
92898   #define USBHSCORE_DIEPCTL11_EPTYPE_Min (0x0UL)     /*!< Min enumerator value of EPTYPE field.                                */
92899   #define USBHSCORE_DIEPCTL11_EPTYPE_Max (0x3UL)     /*!< Max enumerator value of EPTYPE field.                                */
92900   #define USBHSCORE_DIEPCTL11_EPTYPE_CONTROL (0x0UL) /*!< (unspecified)                                                        */
92901   #define USBHSCORE_DIEPCTL11_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                    */
92902   #define USBHSCORE_DIEPCTL11_EPTYPE_BULK (0x2UL)    /*!< (unspecified)                                                        */
92903   #define USBHSCORE_DIEPCTL11_EPTYPE_INTERRUP (0x3UL) /*!< (unspecified)                                                       */
92904 
92905 /* STALL @Bit 21 : STALL Handshake (Stall) */
92906   #define USBHSCORE_DIEPCTL11_STALL_Pos (21UL)       /*!< Position of STALL field.                                             */
92907   #define USBHSCORE_DIEPCTL11_STALL_Msk (0x1UL << USBHSCORE_DIEPCTL11_STALL_Pos) /*!< Bit mask of STALL field.                 */
92908   #define USBHSCORE_DIEPCTL11_STALL_Min (0x0UL)      /*!< Min enumerator value of STALL field.                                 */
92909   #define USBHSCORE_DIEPCTL11_STALL_Max (0x1UL)      /*!< Max enumerator value of STALL field.                                 */
92910   #define USBHSCORE_DIEPCTL11_STALL_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92911   #define USBHSCORE_DIEPCTL11_STALL_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92912 
92913 /* TXFNUM @Bits 22..25 : TxFIFO Number (TxFNum) */
92914   #define USBHSCORE_DIEPCTL11_TXFNUM_Pos (22UL)      /*!< Position of TXFNUM field.                                            */
92915   #define USBHSCORE_DIEPCTL11_TXFNUM_Msk (0xFUL << USBHSCORE_DIEPCTL11_TXFNUM_Pos) /*!< Bit mask of TXFNUM field.              */
92916   #define USBHSCORE_DIEPCTL11_TXFNUM_Min (0x0UL)     /*!< Min enumerator value of TXFNUM field.                                */
92917   #define USBHSCORE_DIEPCTL11_TXFNUM_Max (0xFUL)     /*!< Max enumerator value of TXFNUM field.                                */
92918   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO0 (0x0UL) /*!< (unspecified)                                                        */
92919   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO1 (0x1UL) /*!< (unspecified)                                                        */
92920   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO2 (0x2UL) /*!< (unspecified)                                                        */
92921   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO3 (0x3UL) /*!< (unspecified)                                                        */
92922   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO4 (0x4UL) /*!< (unspecified)                                                        */
92923   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO5 (0x5UL) /*!< (unspecified)                                                        */
92924   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO6 (0x6UL) /*!< (unspecified)                                                        */
92925   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO7 (0x7UL) /*!< (unspecified)                                                        */
92926   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO8 (0x8UL) /*!< (unspecified)                                                        */
92927   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO9 (0x9UL) /*!< (unspecified)                                                        */
92928   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO10 (0xAUL) /*!< (unspecified)                                                       */
92929   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO11 (0xBUL) /*!< (unspecified)                                                       */
92930   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO12 (0xCUL) /*!< (unspecified)                                                       */
92931   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO13 (0xDUL) /*!< (unspecified)                                                       */
92932   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO14 (0xEUL) /*!< (unspecified)                                                       */
92933   #define USBHSCORE_DIEPCTL11_TXFNUM_TXFIFO15 (0xFUL) /*!< (unspecified)                                                       */
92934 
92935 /* CNAK @Bit 26 : Clear NAK (CNAK) */
92936   #define USBHSCORE_DIEPCTL11_CNAK_Pos (26UL)        /*!< Position of CNAK field.                                              */
92937   #define USBHSCORE_DIEPCTL11_CNAK_Msk (0x1UL << USBHSCORE_DIEPCTL11_CNAK_Pos) /*!< Bit mask of CNAK field.                    */
92938   #define USBHSCORE_DIEPCTL11_CNAK_Min (0x0UL)       /*!< Min enumerator value of CNAK field.                                  */
92939   #define USBHSCORE_DIEPCTL11_CNAK_Max (0x1UL)       /*!< Max enumerator value of CNAK field.                                  */
92940   #define USBHSCORE_DIEPCTL11_CNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92941   #define USBHSCORE_DIEPCTL11_CNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92942 
92943 /* SNAK @Bit 27 : Set NAK (SNAK) */
92944   #define USBHSCORE_DIEPCTL11_SNAK_Pos (27UL)        /*!< Position of SNAK field.                                              */
92945   #define USBHSCORE_DIEPCTL11_SNAK_Msk (0x1UL << USBHSCORE_DIEPCTL11_SNAK_Pos) /*!< Bit mask of SNAK field.                    */
92946   #define USBHSCORE_DIEPCTL11_SNAK_Min (0x0UL)       /*!< Min enumerator value of SNAK field.                                  */
92947   #define USBHSCORE_DIEPCTL11_SNAK_Max (0x1UL)       /*!< Max enumerator value of SNAK field.                                  */
92948   #define USBHSCORE_DIEPCTL11_SNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
92949   #define USBHSCORE_DIEPCTL11_SNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
92950 
92951 /* SETD0PID @Bit 28 : SetD0PID */
92952   #define USBHSCORE_DIEPCTL11_SETD0PID_Pos (28UL)    /*!< Position of SETD0PID field.                                          */
92953   #define USBHSCORE_DIEPCTL11_SETD0PID_Msk (0x1UL << USBHSCORE_DIEPCTL11_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.        */
92954   #define USBHSCORE_DIEPCTL11_SETD0PID_Min (0x0UL)   /*!< Min enumerator value of SETD0PID field.                              */
92955   #define USBHSCORE_DIEPCTL11_SETD0PID_Max (0x1UL)   /*!< Max enumerator value of SETD0PID field.                              */
92956   #define USBHSCORE_DIEPCTL11_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
92957   #define USBHSCORE_DIEPCTL11_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
92958 
92959 /* SETD1PID @Bit 29 : SetD1PID */
92960   #define USBHSCORE_DIEPCTL11_SETD1PID_Pos (29UL)    /*!< Position of SETD1PID field.                                          */
92961   #define USBHSCORE_DIEPCTL11_SETD1PID_Msk (0x1UL << USBHSCORE_DIEPCTL11_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.        */
92962   #define USBHSCORE_DIEPCTL11_SETD1PID_Min (0x0UL)   /*!< Min enumerator value of SETD1PID field.                              */
92963   #define USBHSCORE_DIEPCTL11_SETD1PID_Max (0x1UL)   /*!< Max enumerator value of SETD1PID field.                              */
92964   #define USBHSCORE_DIEPCTL11_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
92965   #define USBHSCORE_DIEPCTL11_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
92966 
92967 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
92968   #define USBHSCORE_DIEPCTL11_EPDIS_Pos (30UL)       /*!< Position of EPDIS field.                                             */
92969   #define USBHSCORE_DIEPCTL11_EPDIS_Msk (0x1UL << USBHSCORE_DIEPCTL11_EPDIS_Pos) /*!< Bit mask of EPDIS field.                 */
92970   #define USBHSCORE_DIEPCTL11_EPDIS_Min (0x0UL)      /*!< Min enumerator value of EPDIS field.                                 */
92971   #define USBHSCORE_DIEPCTL11_EPDIS_Max (0x1UL)      /*!< Max enumerator value of EPDIS field.                                 */
92972   #define USBHSCORE_DIEPCTL11_EPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92973   #define USBHSCORE_DIEPCTL11_EPDIS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92974 
92975 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
92976   #define USBHSCORE_DIEPCTL11_EPENA_Pos (31UL)       /*!< Position of EPENA field.                                             */
92977   #define USBHSCORE_DIEPCTL11_EPENA_Msk (0x1UL << USBHSCORE_DIEPCTL11_EPENA_Pos) /*!< Bit mask of EPENA field.                 */
92978   #define USBHSCORE_DIEPCTL11_EPENA_Min (0x0UL)      /*!< Min enumerator value of EPENA field.                                 */
92979   #define USBHSCORE_DIEPCTL11_EPENA_Max (0x1UL)      /*!< Max enumerator value of EPENA field.                                 */
92980   #define USBHSCORE_DIEPCTL11_EPENA_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
92981   #define USBHSCORE_DIEPCTL11_EPENA_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
92982 
92983 
92984 /* USBHSCORE_DIEPINT11: Device IN Endpoint 11 Interrupt Register */
92985   #define USBHSCORE_DIEPINT11_ResetValue (0x00000080UL) /*!< Reset value of DIEPINT11 register.                                */
92986 
92987 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
92988   #define USBHSCORE_DIEPINT11_XFERCOMPL_Pos (0UL)    /*!< Position of XFERCOMPL field.                                         */
92989   #define USBHSCORE_DIEPINT11_XFERCOMPL_Msk (0x1UL << USBHSCORE_DIEPINT11_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.     */
92990   #define USBHSCORE_DIEPINT11_XFERCOMPL_Min (0x0UL)  /*!< Min enumerator value of XFERCOMPL field.                             */
92991   #define USBHSCORE_DIEPINT11_XFERCOMPL_Max (0x1UL)  /*!< Max enumerator value of XFERCOMPL field.                             */
92992   #define USBHSCORE_DIEPINT11_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
92993   #define USBHSCORE_DIEPINT11_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
92994 
92995 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
92996   #define USBHSCORE_DIEPINT11_EPDISBLD_Pos (1UL)     /*!< Position of EPDISBLD field.                                          */
92997   #define USBHSCORE_DIEPINT11_EPDISBLD_Msk (0x1UL << USBHSCORE_DIEPINT11_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.        */
92998   #define USBHSCORE_DIEPINT11_EPDISBLD_Min (0x0UL)   /*!< Min enumerator value of EPDISBLD field.                              */
92999   #define USBHSCORE_DIEPINT11_EPDISBLD_Max (0x1UL)   /*!< Max enumerator value of EPDISBLD field.                              */
93000   #define USBHSCORE_DIEPINT11_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93001   #define USBHSCORE_DIEPINT11_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93002 
93003 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
93004   #define USBHSCORE_DIEPINT11_AHBERR_Pos (2UL)       /*!< Position of AHBERR field.                                            */
93005   #define USBHSCORE_DIEPINT11_AHBERR_Msk (0x1UL << USBHSCORE_DIEPINT11_AHBERR_Pos) /*!< Bit mask of AHBERR field.              */
93006   #define USBHSCORE_DIEPINT11_AHBERR_Min (0x0UL)     /*!< Min enumerator value of AHBERR field.                                */
93007   #define USBHSCORE_DIEPINT11_AHBERR_Max (0x1UL)     /*!< Max enumerator value of AHBERR field.                                */
93008   #define USBHSCORE_DIEPINT11_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
93009   #define USBHSCORE_DIEPINT11_AHBERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
93010 
93011 /* TIMEOUT @Bit 3 : Timeout Condition (TimeOUT) */
93012   #define USBHSCORE_DIEPINT11_TIMEOUT_Pos (3UL)      /*!< Position of TIMEOUT field.                                           */
93013   #define USBHSCORE_DIEPINT11_TIMEOUT_Msk (0x1UL << USBHSCORE_DIEPINT11_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.           */
93014   #define USBHSCORE_DIEPINT11_TIMEOUT_Min (0x0UL)    /*!< Min enumerator value of TIMEOUT field.                               */
93015   #define USBHSCORE_DIEPINT11_TIMEOUT_Max (0x1UL)    /*!< Max enumerator value of TIMEOUT field.                               */
93016   #define USBHSCORE_DIEPINT11_TIMEOUT_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
93017   #define USBHSCORE_DIEPINT11_TIMEOUT_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
93018 
93019 /* INTKNTXFEMP @Bit 4 : IN Token Received When TxFIFO is Empty (INTknTXFEmp) */
93020   #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Pos (4UL)  /*!< Position of INTKNTXFEMP field.                                       */
93021   #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT11_INTKNTXFEMP_Pos) /*!< Bit mask of INTKNTXFEMP
93022                                                                             field.*/
93023   #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Min (0x0UL) /*!< Min enumerator value of INTKNTXFEMP field.                          */
93024   #define USBHSCORE_DIEPINT11_INTKNTXFEMP_Max (0x1UL) /*!< Max enumerator value of INTKNTXFEMP field.                          */
93025   #define USBHSCORE_DIEPINT11_INTKNTXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
93026   #define USBHSCORE_DIEPINT11_INTKNTXFEMP_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
93027 
93028 /* INTKNEPMIS @Bit 5 : IN Token Received with EP Mismatch (INTknEPMis) */
93029   #define USBHSCORE_DIEPINT11_INTKNEPMIS_Pos (5UL)   /*!< Position of INTKNEPMIS field.                                        */
93030   #define USBHSCORE_DIEPINT11_INTKNEPMIS_Msk (0x1UL << USBHSCORE_DIEPINT11_INTKNEPMIS_Pos) /*!< Bit mask of INTKNEPMIS field.  */
93031   #define USBHSCORE_DIEPINT11_INTKNEPMIS_Min (0x0UL) /*!< Min enumerator value of INTKNEPMIS field.                            */
93032   #define USBHSCORE_DIEPINT11_INTKNEPMIS_Max (0x1UL) /*!< Max enumerator value of INTKNEPMIS field.                            */
93033   #define USBHSCORE_DIEPINT11_INTKNEPMIS_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93034   #define USBHSCORE_DIEPINT11_INTKNEPMIS_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93035 
93036 /* INEPNAKEFF @Bit 6 : IN Endpoint NAK Effective (INEPNakEff) */
93037   #define USBHSCORE_DIEPINT11_INEPNAKEFF_Pos (6UL)   /*!< Position of INEPNAKEFF field.                                        */
93038   #define USBHSCORE_DIEPINT11_INEPNAKEFF_Msk (0x1UL << USBHSCORE_DIEPINT11_INEPNAKEFF_Pos) /*!< Bit mask of INEPNAKEFF field.  */
93039   #define USBHSCORE_DIEPINT11_INEPNAKEFF_Min (0x0UL) /*!< Min enumerator value of INEPNAKEFF field.                            */
93040   #define USBHSCORE_DIEPINT11_INEPNAKEFF_Max (0x1UL) /*!< Max enumerator value of INEPNAKEFF field.                            */
93041   #define USBHSCORE_DIEPINT11_INEPNAKEFF_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93042   #define USBHSCORE_DIEPINT11_INEPNAKEFF_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93043 
93044 /* TXFEMP @Bit 7 : Transmit FIFO Empty (TxFEmp) */
93045   #define USBHSCORE_DIEPINT11_TXFEMP_Pos (7UL)       /*!< Position of TXFEMP field.                                            */
93046   #define USBHSCORE_DIEPINT11_TXFEMP_Msk (0x1UL << USBHSCORE_DIEPINT11_TXFEMP_Pos) /*!< Bit mask of TXFEMP field.              */
93047   #define USBHSCORE_DIEPINT11_TXFEMP_Min (0x0UL)     /*!< Min enumerator value of TXFEMP field.                                */
93048   #define USBHSCORE_DIEPINT11_TXFEMP_Max (0x1UL)     /*!< Max enumerator value of TXFEMP field.                                */
93049   #define USBHSCORE_DIEPINT11_TXFEMP_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
93050   #define USBHSCORE_DIEPINT11_TXFEMP_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
93051 
93052 /* TXFIFOUNDRN @Bit 8 : Fifo Underrun (TxfifoUndrn) */
93053   #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Pos (8UL)  /*!< Position of TXFIFOUNDRN field.                                       */
93054   #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Msk (0x1UL << USBHSCORE_DIEPINT11_TXFIFOUNDRN_Pos) /*!< Bit mask of TXFIFOUNDRN
93055                                                                             field.*/
93056   #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Min (0x0UL) /*!< Min enumerator value of TXFIFOUNDRN field.                          */
93057   #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_Max (0x1UL) /*!< Max enumerator value of TXFIFOUNDRN field.                          */
93058   #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
93059   #define USBHSCORE_DIEPINT11_TXFIFOUNDRN_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
93060 
93061 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
93062   #define USBHSCORE_DIEPINT11_BNAINTR_Pos (9UL)      /*!< Position of BNAINTR field.                                           */
93063   #define USBHSCORE_DIEPINT11_BNAINTR_Msk (0x1UL << USBHSCORE_DIEPINT11_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.           */
93064   #define USBHSCORE_DIEPINT11_BNAINTR_Min (0x0UL)    /*!< Min enumerator value of BNAINTR field.                               */
93065   #define USBHSCORE_DIEPINT11_BNAINTR_Max (0x1UL)    /*!< Max enumerator value of BNAINTR field.                               */
93066   #define USBHSCORE_DIEPINT11_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
93067   #define USBHSCORE_DIEPINT11_BNAINTR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
93068 
93069 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
93070   #define USBHSCORE_DIEPINT11_PKTDRPSTS_Pos (11UL)   /*!< Position of PKTDRPSTS field.                                         */
93071   #define USBHSCORE_DIEPINT11_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DIEPINT11_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.     */
93072   #define USBHSCORE_DIEPINT11_PKTDRPSTS_Min (0x0UL)  /*!< Min enumerator value of PKTDRPSTS field.                             */
93073   #define USBHSCORE_DIEPINT11_PKTDRPSTS_Max (0x1UL)  /*!< Max enumerator value of PKTDRPSTS field.                             */
93074   #define USBHSCORE_DIEPINT11_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
93075   #define USBHSCORE_DIEPINT11_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
93076 
93077 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
93078   #define USBHSCORE_DIEPINT11_BBLEERR_Pos (12UL)     /*!< Position of BBLEERR field.                                           */
93079   #define USBHSCORE_DIEPINT11_BBLEERR_Msk (0x1UL << USBHSCORE_DIEPINT11_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.           */
93080   #define USBHSCORE_DIEPINT11_BBLEERR_Min (0x0UL)    /*!< Min enumerator value of BBLEERR field.                               */
93081   #define USBHSCORE_DIEPINT11_BBLEERR_Max (0x1UL)    /*!< Max enumerator value of BBLEERR field.                               */
93082   #define USBHSCORE_DIEPINT11_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
93083   #define USBHSCORE_DIEPINT11_BBLEERR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
93084 
93085 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
93086   #define USBHSCORE_DIEPINT11_NAKINTRPT_Pos (13UL)   /*!< Position of NAKINTRPT field.                                         */
93087   #define USBHSCORE_DIEPINT11_NAKINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT11_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.     */
93088   #define USBHSCORE_DIEPINT11_NAKINTRPT_Min (0x0UL)  /*!< Min enumerator value of NAKINTRPT field.                             */
93089   #define USBHSCORE_DIEPINT11_NAKINTRPT_Max (0x1UL)  /*!< Max enumerator value of NAKINTRPT field.                             */
93090   #define USBHSCORE_DIEPINT11_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
93091   #define USBHSCORE_DIEPINT11_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
93092 
93093 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
93094   #define USBHSCORE_DIEPINT11_NYETINTRPT_Pos (14UL)  /*!< Position of NYETINTRPT field.                                        */
93095   #define USBHSCORE_DIEPINT11_NYETINTRPT_Msk (0x1UL << USBHSCORE_DIEPINT11_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.  */
93096   #define USBHSCORE_DIEPINT11_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field.                            */
93097   #define USBHSCORE_DIEPINT11_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field.                            */
93098   #define USBHSCORE_DIEPINT11_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93099   #define USBHSCORE_DIEPINT11_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93100 
93101 
93102 /* USBHSCORE_DIEPTSIZ11: Device IN Endpoint 11 Transfer Size Register */
93103   #define USBHSCORE_DIEPTSIZ11_ResetValue (0x00000000UL) /*!< Reset value of DIEPTSIZ11 register.                              */
93104 
93105 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
93106   #define USBHSCORE_DIEPTSIZ11_XFERSIZE_Pos (0UL)    /*!< Position of XFERSIZE field.                                          */
93107   #define USBHSCORE_DIEPTSIZ11_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DIEPTSIZ11_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.  */
93108 
93109 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
93110   #define USBHSCORE_DIEPTSIZ11_PKTCNT_Pos (19UL)     /*!< Position of PKTCNT field.                                            */
93111   #define USBHSCORE_DIEPTSIZ11_PKTCNT_Msk (0x3FFUL << USBHSCORE_DIEPTSIZ11_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.          */
93112 
93113 /* MC @Bits 29..30 : MC */
93114   #define USBHSCORE_DIEPTSIZ11_MC_Pos (29UL)         /*!< Position of MC field.                                                */
93115   #define USBHSCORE_DIEPTSIZ11_MC_Msk (0x3UL << USBHSCORE_DIEPTSIZ11_MC_Pos) /*!< Bit mask of MC field.                        */
93116   #define USBHSCORE_DIEPTSIZ11_MC_Min (0x1UL)        /*!< Min enumerator value of MC field.                                    */
93117   #define USBHSCORE_DIEPTSIZ11_MC_Max (0x3UL)        /*!< Max enumerator value of MC field.                                    */
93118   #define USBHSCORE_DIEPTSIZ11_MC_PACKETONE (0x1UL)  /*!< (unspecified)                                                        */
93119   #define USBHSCORE_DIEPTSIZ11_MC_PACKETTWO (0x2UL)  /*!< (unspecified)                                                        */
93120   #define USBHSCORE_DIEPTSIZ11_MC_PACKETTHREE (0x3UL) /*!< (unspecified)                                                       */
93121 
93122 
93123 /* USBHSCORE_DIEPDMA11: Device IN Endpoint 11 DMA Address Register */
93124   #define USBHSCORE_DIEPDMA11_ResetValue (0x00000000UL) /*!< Reset value of DIEPDMA11 register.                                */
93125 
93126 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
93127   #define USBHSCORE_DIEPDMA11_DMAADDR_Pos (0UL)      /*!< Position of DMAADDR field.                                           */
93128   #define USBHSCORE_DIEPDMA11_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DIEPDMA11_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.    */
93129 
93130 
93131 /* USBHSCORE_DTXFSTS11: Device IN Endpoint Transmit FIFO Status Register 11 */
93132   #define USBHSCORE_DTXFSTS11_ResetValue (0x00000200UL) /*!< Reset value of DTXFSTS11 register.                                */
93133 
93134 /* INEPTXFSPCAVAIL @Bits 0..15 : IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) */
93135   #define USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Pos (0UL) /*!< Position of INEPTXFSPCAVAIL field.                                */
93136   #define USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Msk (0xFFFFUL << USBHSCORE_DTXFSTS11_INEPTXFSPCAVAIL_Pos) /*!< Bit mask of
93137                                                                             INEPTXFSPCAVAIL field.*/
93138 
93139 
93140 /* USBHSCORE_DOEPCTL0: Device Control OUT Endpoint 0 Control Register */
93141   #define USBHSCORE_DOEPCTL0_ResetValue (0x00008000UL) /*!< Reset value of DOEPCTL0 register.                                  */
93142 
93143 /* MPS @Bits 0..1 : Maximum Packet Size (MPS) */
93144   #define USBHSCORE_DOEPCTL0_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
93145   #define USBHSCORE_DOEPCTL0_MPS_Msk (0x3UL << USBHSCORE_DOEPCTL0_MPS_Pos) /*!< Bit mask of MPS field.                         */
93146   #define USBHSCORE_DOEPCTL0_MPS_Min (0x0UL)         /*!< Min enumerator value of MPS field.                                   */
93147   #define USBHSCORE_DOEPCTL0_MPS_Max (0x3UL)         /*!< Max enumerator value of MPS field.                                   */
93148   #define USBHSCORE_DOEPCTL0_MPS_BYTE64 (0x0UL)      /*!< (unspecified)                                                        */
93149   #define USBHSCORE_DOEPCTL0_MPS_BYTE32 (0x1UL)      /*!< (unspecified)                                                        */
93150   #define USBHSCORE_DOEPCTL0_MPS_BYTE16 (0x2UL)      /*!< (unspecified)                                                        */
93151   #define USBHSCORE_DOEPCTL0_MPS_BYTE8 (0x3UL)       /*!< (unspecified)                                                        */
93152 
93153 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
93154   #define USBHSCORE_DOEPCTL0_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
93155   #define USBHSCORE_DOEPCTL0_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL0_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
93156   #define USBHSCORE_DOEPCTL0_USBACTEP_Min (0x1UL)    /*!< Min enumerator value of USBACTEP field.                              */
93157   #define USBHSCORE_DOEPCTL0_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
93158   #define USBHSCORE_DOEPCTL0_USBACTEP_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
93159 
93160 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
93161   #define USBHSCORE_DOEPCTL0_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
93162   #define USBHSCORE_DOEPCTL0_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL0_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
93163   #define USBHSCORE_DOEPCTL0_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
93164   #define USBHSCORE_DOEPCTL0_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
93165   #define USBHSCORE_DOEPCTL0_NAKSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
93166   #define USBHSCORE_DOEPCTL0_NAKSTS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
93167 
93168 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
93169   #define USBHSCORE_DOEPCTL0_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
93170   #define USBHSCORE_DOEPCTL0_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL0_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
93171   #define USBHSCORE_DOEPCTL0_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
93172   #define USBHSCORE_DOEPCTL0_EPTYPE_Max (0x0UL)      /*!< Max enumerator value of EPTYPE field.                                */
93173   #define USBHSCORE_DOEPCTL0_EPTYPE_ACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93174 
93175 /* STALL @Bit 21 : STALL Handshake (Stall) */
93176   #define USBHSCORE_DOEPCTL0_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
93177   #define USBHSCORE_DOEPCTL0_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL0_STALL_Pos) /*!< Bit mask of STALL field.                   */
93178   #define USBHSCORE_DOEPCTL0_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
93179   #define USBHSCORE_DOEPCTL0_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
93180   #define USBHSCORE_DOEPCTL0_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93181   #define USBHSCORE_DOEPCTL0_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93182 
93183 /* CNAK @Bit 26 : Clear NAK (CNAK) */
93184   #define USBHSCORE_DOEPCTL0_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
93185   #define USBHSCORE_DOEPCTL0_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL0_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
93186   #define USBHSCORE_DOEPCTL0_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
93187   #define USBHSCORE_DOEPCTL0_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
93188   #define USBHSCORE_DOEPCTL0_CNAK_NOCLEAR (0x0UL)    /*!< (unspecified)                                                        */
93189   #define USBHSCORE_DOEPCTL0_CNAK_CLEAR (0x1UL)      /*!< (unspecified)                                                        */
93190 
93191 /* SNAK @Bit 27 : Set NAK (SNAK) */
93192   #define USBHSCORE_DOEPCTL0_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
93193   #define USBHSCORE_DOEPCTL0_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL0_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
93194   #define USBHSCORE_DOEPCTL0_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
93195   #define USBHSCORE_DOEPCTL0_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
93196   #define USBHSCORE_DOEPCTL0_SNAK_NOSET (0x0UL)      /*!< (unspecified)                                                        */
93197   #define USBHSCORE_DOEPCTL0_SNAK_SET (0x1UL)        /*!< (unspecified)                                                        */
93198 
93199 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
93200   #define USBHSCORE_DOEPCTL0_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
93201   #define USBHSCORE_DOEPCTL0_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL0_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
93202   #define USBHSCORE_DOEPCTL0_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
93203   #define USBHSCORE_DOEPCTL0_EPDIS_Max (0x0UL)       /*!< Max enumerator value of EPDIS field.                                 */
93204   #define USBHSCORE_DOEPCTL0_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93205 
93206 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
93207   #define USBHSCORE_DOEPCTL0_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
93208   #define USBHSCORE_DOEPCTL0_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL0_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
93209   #define USBHSCORE_DOEPCTL0_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
93210   #define USBHSCORE_DOEPCTL0_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
93211   #define USBHSCORE_DOEPCTL0_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93212   #define USBHSCORE_DOEPCTL0_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93213 
93214 
93215 /* USBHSCORE_DOEPINT0: Device OUT Endpoint 0 Interrupt Register */
93216   #define USBHSCORE_DOEPINT0_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT0 register.                                  */
93217 
93218 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
93219   #define USBHSCORE_DOEPINT0_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
93220   #define USBHSCORE_DOEPINT0_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT0_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
93221   #define USBHSCORE_DOEPINT0_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
93222   #define USBHSCORE_DOEPINT0_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
93223   #define USBHSCORE_DOEPINT0_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93224   #define USBHSCORE_DOEPINT0_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93225 
93226 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
93227   #define USBHSCORE_DOEPINT0_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
93228   #define USBHSCORE_DOEPINT0_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT0_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
93229   #define USBHSCORE_DOEPINT0_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
93230   #define USBHSCORE_DOEPINT0_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
93231   #define USBHSCORE_DOEPINT0_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
93232   #define USBHSCORE_DOEPINT0_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
93233 
93234 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
93235   #define USBHSCORE_DOEPINT0_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
93236   #define USBHSCORE_DOEPINT0_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT0_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
93237   #define USBHSCORE_DOEPINT0_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
93238   #define USBHSCORE_DOEPINT0_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
93239   #define USBHSCORE_DOEPINT0_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
93240   #define USBHSCORE_DOEPINT0_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
93241 
93242 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
93243   #define USBHSCORE_DOEPINT0_SETUP_Pos (3UL)         /*!< Position of SETUP field.                                             */
93244   #define USBHSCORE_DOEPINT0_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT0_SETUP_Pos) /*!< Bit mask of SETUP field.                   */
93245   #define USBHSCORE_DOEPINT0_SETUP_Min (0x0UL)       /*!< Min enumerator value of SETUP field.                                 */
93246   #define USBHSCORE_DOEPINT0_SETUP_Max (0x1UL)       /*!< Max enumerator value of SETUP field.                                 */
93247   #define USBHSCORE_DOEPINT0_SETUP_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93248   #define USBHSCORE_DOEPINT0_SETUP_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93249 
93250 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
93251   #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Pos (4UL)   /*!< Position of OUTTKNEPDIS field.                                       */
93252   #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT0_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */
93253   #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                           */
93254   #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                           */
93255   #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93256   #define USBHSCORE_DOEPINT0_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93257 
93258 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
93259   #define USBHSCORE_DOEPINT0_STSPHSERCVD_Pos (5UL)   /*!< Position of STSPHSERCVD field.                                       */
93260   #define USBHSCORE_DOEPINT0_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT0_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */
93261   #define USBHSCORE_DOEPINT0_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                           */
93262   #define USBHSCORE_DOEPINT0_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                           */
93263   #define USBHSCORE_DOEPINT0_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93264   #define USBHSCORE_DOEPINT0_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93265 
93266 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
93267   #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                   */
93268   #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT0_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP
93269                                                                             field.*/
93270   #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                     */
93271   #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                     */
93272   #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                */
93273   #define USBHSCORE_DOEPINT0_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
93274 
93275 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
93276   #define USBHSCORE_DOEPINT0_OUTPKTERR_Pos (8UL)     /*!< Position of OUTPKTERR field.                                         */
93277   #define USBHSCORE_DOEPINT0_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT0_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.       */
93278   #define USBHSCORE_DOEPINT0_OUTPKTERR_Min (0x0UL)   /*!< Min enumerator value of OUTPKTERR field.                             */
93279   #define USBHSCORE_DOEPINT0_OUTPKTERR_Max (0x1UL)   /*!< Max enumerator value of OUTPKTERR field.                             */
93280   #define USBHSCORE_DOEPINT0_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93281   #define USBHSCORE_DOEPINT0_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93282 
93283 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
93284   #define USBHSCORE_DOEPINT0_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
93285   #define USBHSCORE_DOEPINT0_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT0_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
93286   #define USBHSCORE_DOEPINT0_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
93287   #define USBHSCORE_DOEPINT0_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
93288   #define USBHSCORE_DOEPINT0_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
93289   #define USBHSCORE_DOEPINT0_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
93290 
93291 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
93292   #define USBHSCORE_DOEPINT0_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
93293   #define USBHSCORE_DOEPINT0_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT0_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
93294   #define USBHSCORE_DOEPINT0_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
93295   #define USBHSCORE_DOEPINT0_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
93296   #define USBHSCORE_DOEPINT0_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93297   #define USBHSCORE_DOEPINT0_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93298 
93299 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
93300   #define USBHSCORE_DOEPINT0_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
93301   #define USBHSCORE_DOEPINT0_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT0_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
93302   #define USBHSCORE_DOEPINT0_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
93303   #define USBHSCORE_DOEPINT0_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
93304   #define USBHSCORE_DOEPINT0_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
93305   #define USBHSCORE_DOEPINT0_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
93306 
93307 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
93308   #define USBHSCORE_DOEPINT0_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
93309   #define USBHSCORE_DOEPINT0_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT0_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
93310   #define USBHSCORE_DOEPINT0_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
93311   #define USBHSCORE_DOEPINT0_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
93312   #define USBHSCORE_DOEPINT0_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93313   #define USBHSCORE_DOEPINT0_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93314 
93315 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
93316   #define USBHSCORE_DOEPINT0_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
93317   #define USBHSCORE_DOEPINT0_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT0_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
93318   #define USBHSCORE_DOEPINT0_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
93319   #define USBHSCORE_DOEPINT0_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
93320   #define USBHSCORE_DOEPINT0_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
93321   #define USBHSCORE_DOEPINT0_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
93322 
93323 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
93324   #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Pos (15UL)  /*!< Position of STUPPKTRCVD field.                                       */
93325   #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT0_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */
93326   #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                           */
93327   #define USBHSCORE_DOEPINT0_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                           */
93328   #define USBHSCORE_DOEPINT0_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                   */
93329   #define USBHSCORE_DOEPINT0_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                       */
93330 
93331 
93332 /* USBHSCORE_DOEPTSIZ0: Device OUT Endpoint 0 Transfer Size Register */
93333   #define USBHSCORE_DOEPTSIZ0_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ0 register.                                */
93334 
93335 /* XFERSIZE @Bits 0..6 : Transfer Size (XferSize) */
93336   #define USBHSCORE_DOEPTSIZ0_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
93337   #define USBHSCORE_DOEPTSIZ0_XFERSIZE_Msk (0x7FUL << USBHSCORE_DOEPTSIZ0_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.       */
93338 
93339 /* PKTCNT @Bit 19 : Packet Count (PktCnt) */
93340   #define USBHSCORE_DOEPTSIZ0_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
93341   #define USBHSCORE_DOEPTSIZ0_PKTCNT_Msk (0x1UL << USBHSCORE_DOEPTSIZ0_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.              */
93342 
93343 /* SUPCNT @Bits 29..30 : SETUP Packet Count (SUPCnt) */
93344   #define USBHSCORE_DOEPTSIZ0_SUPCNT_Pos (29UL)      /*!< Position of SUPCNT field.                                            */
93345   #define USBHSCORE_DOEPTSIZ0_SUPCNT_Msk (0x3UL << USBHSCORE_DOEPTSIZ0_SUPCNT_Pos) /*!< Bit mask of SUPCNT field.              */
93346   #define USBHSCORE_DOEPTSIZ0_SUPCNT_Min (0x1UL)     /*!< Min enumerator value of SUPCNT field.                                */
93347   #define USBHSCORE_DOEPTSIZ0_SUPCNT_Max (0x3UL)     /*!< Max enumerator value of SUPCNT field.                                */
93348   #define USBHSCORE_DOEPTSIZ0_SUPCNT_ONEPACKET (0x1UL) /*!< (unspecified)                                                      */
93349   #define USBHSCORE_DOEPTSIZ0_SUPCNT_TWOPACKET (0x2UL) /*!< (unspecified)                                                      */
93350   #define USBHSCORE_DOEPTSIZ0_SUPCNT_THREEPACKET (0x3UL) /*!< (unspecified)                                                    */
93351 
93352 
93353 /* USBHSCORE_DOEPDMA0: Device OUT Endpoint 0 DMA Address Register */
93354   #define USBHSCORE_DOEPDMA0_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA0 register.                                  */
93355 
93356 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
93357   #define USBHSCORE_DOEPDMA0_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
93358   #define USBHSCORE_DOEPDMA0_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA0_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
93359 
93360 
93361 /* USBHSCORE_DOEPCTL1: Device Control OUT Endpoint 1 Control Register */
93362   #define USBHSCORE_DOEPCTL1_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL1 register.                                  */
93363 
93364 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
93365   #define USBHSCORE_DOEPCTL1_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
93366   #define USBHSCORE_DOEPCTL1_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL1_MPS_Pos) /*!< Bit mask of MPS field.                       */
93367 
93368 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
93369   #define USBHSCORE_DOEPCTL1_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
93370   #define USBHSCORE_DOEPCTL1_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL1_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
93371   #define USBHSCORE_DOEPCTL1_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
93372   #define USBHSCORE_DOEPCTL1_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
93373   #define USBHSCORE_DOEPCTL1_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93374   #define USBHSCORE_DOEPCTL1_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93375 
93376 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
93377   #define USBHSCORE_DOEPCTL1_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
93378   #define USBHSCORE_DOEPCTL1_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL1_DPID_Pos) /*!< Bit mask of DPID field.                      */
93379   #define USBHSCORE_DOEPCTL1_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
93380   #define USBHSCORE_DOEPCTL1_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
93381   #define USBHSCORE_DOEPCTL1_DPID_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93382   #define USBHSCORE_DOEPCTL1_DPID_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93383 
93384 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
93385   #define USBHSCORE_DOEPCTL1_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
93386   #define USBHSCORE_DOEPCTL1_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL1_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
93387   #define USBHSCORE_DOEPCTL1_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
93388   #define USBHSCORE_DOEPCTL1_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
93389   #define USBHSCORE_DOEPCTL1_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
93390   #define USBHSCORE_DOEPCTL1_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
93391 
93392 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
93393   #define USBHSCORE_DOEPCTL1_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
93394   #define USBHSCORE_DOEPCTL1_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL1_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
93395   #define USBHSCORE_DOEPCTL1_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
93396   #define USBHSCORE_DOEPCTL1_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
93397   #define USBHSCORE_DOEPCTL1_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
93398   #define USBHSCORE_DOEPCTL1_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
93399   #define USBHSCORE_DOEPCTL1_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
93400   #define USBHSCORE_DOEPCTL1_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                       */
93401 
93402 /* STALL @Bit 21 : STALL Handshake (Stall) */
93403   #define USBHSCORE_DOEPCTL1_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
93404   #define USBHSCORE_DOEPCTL1_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL1_STALL_Pos) /*!< Bit mask of STALL field.                   */
93405   #define USBHSCORE_DOEPCTL1_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
93406   #define USBHSCORE_DOEPCTL1_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
93407   #define USBHSCORE_DOEPCTL1_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93408   #define USBHSCORE_DOEPCTL1_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93409 
93410 /* CNAK @Bit 26 : Clear NAK (CNAK) */
93411   #define USBHSCORE_DOEPCTL1_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
93412   #define USBHSCORE_DOEPCTL1_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL1_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
93413   #define USBHSCORE_DOEPCTL1_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
93414   #define USBHSCORE_DOEPCTL1_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
93415   #define USBHSCORE_DOEPCTL1_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93416   #define USBHSCORE_DOEPCTL1_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93417 
93418 /* SNAK @Bit 27 : Set NAK (SNAK) */
93419   #define USBHSCORE_DOEPCTL1_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
93420   #define USBHSCORE_DOEPCTL1_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL1_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
93421   #define USBHSCORE_DOEPCTL1_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
93422   #define USBHSCORE_DOEPCTL1_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
93423   #define USBHSCORE_DOEPCTL1_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93424   #define USBHSCORE_DOEPCTL1_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93425 
93426 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
93427   #define USBHSCORE_DOEPCTL1_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
93428   #define USBHSCORE_DOEPCTL1_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL1_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
93429   #define USBHSCORE_DOEPCTL1_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
93430   #define USBHSCORE_DOEPCTL1_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
93431   #define USBHSCORE_DOEPCTL1_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93432   #define USBHSCORE_DOEPCTL1_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93433 
93434 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
93435   #define USBHSCORE_DOEPCTL1_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
93436   #define USBHSCORE_DOEPCTL1_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL1_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
93437   #define USBHSCORE_DOEPCTL1_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
93438   #define USBHSCORE_DOEPCTL1_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
93439   #define USBHSCORE_DOEPCTL1_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93440   #define USBHSCORE_DOEPCTL1_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93441 
93442 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
93443   #define USBHSCORE_DOEPCTL1_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
93444   #define USBHSCORE_DOEPCTL1_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL1_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
93445   #define USBHSCORE_DOEPCTL1_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
93446   #define USBHSCORE_DOEPCTL1_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
93447   #define USBHSCORE_DOEPCTL1_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93448   #define USBHSCORE_DOEPCTL1_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93449 
93450 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
93451   #define USBHSCORE_DOEPCTL1_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
93452   #define USBHSCORE_DOEPCTL1_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL1_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
93453   #define USBHSCORE_DOEPCTL1_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
93454   #define USBHSCORE_DOEPCTL1_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
93455   #define USBHSCORE_DOEPCTL1_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93456   #define USBHSCORE_DOEPCTL1_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93457 
93458 
93459 /* USBHSCORE_DOEPINT1: Device OUT Endpoint 1 Interrupt Register */
93460   #define USBHSCORE_DOEPINT1_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT1 register.                                  */
93461 
93462 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
93463   #define USBHSCORE_DOEPINT1_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
93464   #define USBHSCORE_DOEPINT1_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT1_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
93465   #define USBHSCORE_DOEPINT1_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
93466   #define USBHSCORE_DOEPINT1_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
93467   #define USBHSCORE_DOEPINT1_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93468   #define USBHSCORE_DOEPINT1_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93469 
93470 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
93471   #define USBHSCORE_DOEPINT1_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
93472   #define USBHSCORE_DOEPINT1_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT1_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
93473   #define USBHSCORE_DOEPINT1_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
93474   #define USBHSCORE_DOEPINT1_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
93475   #define USBHSCORE_DOEPINT1_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
93476   #define USBHSCORE_DOEPINT1_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
93477 
93478 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
93479   #define USBHSCORE_DOEPINT1_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
93480   #define USBHSCORE_DOEPINT1_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT1_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
93481   #define USBHSCORE_DOEPINT1_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
93482   #define USBHSCORE_DOEPINT1_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
93483   #define USBHSCORE_DOEPINT1_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
93484   #define USBHSCORE_DOEPINT1_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
93485 
93486 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
93487   #define USBHSCORE_DOEPINT1_SETUP_Pos (3UL)         /*!< Position of SETUP field.                                             */
93488   #define USBHSCORE_DOEPINT1_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT1_SETUP_Pos) /*!< Bit mask of SETUP field.                   */
93489   #define USBHSCORE_DOEPINT1_SETUP_Min (0x0UL)       /*!< Min enumerator value of SETUP field.                                 */
93490   #define USBHSCORE_DOEPINT1_SETUP_Max (0x1UL)       /*!< Max enumerator value of SETUP field.                                 */
93491   #define USBHSCORE_DOEPINT1_SETUP_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93492   #define USBHSCORE_DOEPINT1_SETUP_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93493 
93494 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
93495   #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Pos (4UL)   /*!< Position of OUTTKNEPDIS field.                                       */
93496   #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT1_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */
93497   #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                           */
93498   #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                           */
93499   #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93500   #define USBHSCORE_DOEPINT1_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93501 
93502 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
93503   #define USBHSCORE_DOEPINT1_STSPHSERCVD_Pos (5UL)   /*!< Position of STSPHSERCVD field.                                       */
93504   #define USBHSCORE_DOEPINT1_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT1_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */
93505   #define USBHSCORE_DOEPINT1_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                           */
93506   #define USBHSCORE_DOEPINT1_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                           */
93507   #define USBHSCORE_DOEPINT1_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93508   #define USBHSCORE_DOEPINT1_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93509 
93510 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
93511   #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                   */
93512   #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT1_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP
93513                                                                             field.*/
93514   #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                     */
93515   #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                     */
93516   #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                */
93517   #define USBHSCORE_DOEPINT1_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
93518 
93519 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
93520   #define USBHSCORE_DOEPINT1_OUTPKTERR_Pos (8UL)     /*!< Position of OUTPKTERR field.                                         */
93521   #define USBHSCORE_DOEPINT1_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT1_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.       */
93522   #define USBHSCORE_DOEPINT1_OUTPKTERR_Min (0x0UL)   /*!< Min enumerator value of OUTPKTERR field.                             */
93523   #define USBHSCORE_DOEPINT1_OUTPKTERR_Max (0x1UL)   /*!< Max enumerator value of OUTPKTERR field.                             */
93524   #define USBHSCORE_DOEPINT1_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93525   #define USBHSCORE_DOEPINT1_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93526 
93527 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
93528   #define USBHSCORE_DOEPINT1_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
93529   #define USBHSCORE_DOEPINT1_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT1_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
93530   #define USBHSCORE_DOEPINT1_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
93531   #define USBHSCORE_DOEPINT1_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
93532   #define USBHSCORE_DOEPINT1_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
93533   #define USBHSCORE_DOEPINT1_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
93534 
93535 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
93536   #define USBHSCORE_DOEPINT1_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
93537   #define USBHSCORE_DOEPINT1_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT1_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
93538   #define USBHSCORE_DOEPINT1_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
93539   #define USBHSCORE_DOEPINT1_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
93540   #define USBHSCORE_DOEPINT1_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93541   #define USBHSCORE_DOEPINT1_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93542 
93543 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
93544   #define USBHSCORE_DOEPINT1_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
93545   #define USBHSCORE_DOEPINT1_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT1_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
93546   #define USBHSCORE_DOEPINT1_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
93547   #define USBHSCORE_DOEPINT1_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
93548   #define USBHSCORE_DOEPINT1_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
93549   #define USBHSCORE_DOEPINT1_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
93550 
93551 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
93552   #define USBHSCORE_DOEPINT1_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
93553   #define USBHSCORE_DOEPINT1_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT1_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
93554   #define USBHSCORE_DOEPINT1_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
93555   #define USBHSCORE_DOEPINT1_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
93556   #define USBHSCORE_DOEPINT1_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93557   #define USBHSCORE_DOEPINT1_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93558 
93559 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
93560   #define USBHSCORE_DOEPINT1_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
93561   #define USBHSCORE_DOEPINT1_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT1_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
93562   #define USBHSCORE_DOEPINT1_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
93563   #define USBHSCORE_DOEPINT1_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
93564   #define USBHSCORE_DOEPINT1_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
93565   #define USBHSCORE_DOEPINT1_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
93566 
93567 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
93568   #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Pos (15UL)  /*!< Position of STUPPKTRCVD field.                                       */
93569   #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT1_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */
93570   #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                           */
93571   #define USBHSCORE_DOEPINT1_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                           */
93572   #define USBHSCORE_DOEPINT1_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                   */
93573   #define USBHSCORE_DOEPINT1_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                       */
93574 
93575 
93576 /* USBHSCORE_DOEPTSIZ1: Device OUT Endpoint 1 Transfer Size Register */
93577   #define USBHSCORE_DOEPTSIZ1_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ1 register.                                */
93578 
93579 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
93580   #define USBHSCORE_DOEPTSIZ1_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
93581   #define USBHSCORE_DOEPTSIZ1_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ1_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
93582 
93583 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
93584   #define USBHSCORE_DOEPTSIZ1_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
93585   #define USBHSCORE_DOEPTSIZ1_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ1_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
93586 
93587 /* RXDPID @Bits 29..30 : RxDPID */
93588   #define USBHSCORE_DOEPTSIZ1_RXDPID_Pos (29UL)      /*!< Position of RXDPID field.                                            */
93589   #define USBHSCORE_DOEPTSIZ1_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ1_RXDPID_Pos) /*!< Bit mask of RXDPID field.              */
93590   #define USBHSCORE_DOEPTSIZ1_RXDPID_Min (0x0UL)     /*!< Min enumerator value of RXDPID field.                                */
93591   #define USBHSCORE_DOEPTSIZ1_RXDPID_Max (0x3UL)     /*!< Max enumerator value of RXDPID field.                                */
93592   #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA0 (0x0UL)   /*!< (unspecified)                                                        */
93593   #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                   */
93594   #define USBHSCORE_DOEPTSIZ1_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                   */
93595   #define USBHSCORE_DOEPTSIZ1_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                   */
93596 
93597 
93598 /* USBHSCORE_DOEPDMA1: Device OUT Endpoint 1 DMA Address Register */
93599   #define USBHSCORE_DOEPDMA1_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA1 register.                                  */
93600 
93601 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
93602   #define USBHSCORE_DOEPDMA1_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
93603   #define USBHSCORE_DOEPDMA1_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA1_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
93604 
93605 
93606 /* USBHSCORE_DOEPCTL2: Device Control OUT Endpoint 2 Control Register */
93607   #define USBHSCORE_DOEPCTL2_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL2 register.                                  */
93608 
93609 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
93610   #define USBHSCORE_DOEPCTL2_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
93611   #define USBHSCORE_DOEPCTL2_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL2_MPS_Pos) /*!< Bit mask of MPS field.                       */
93612 
93613 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
93614   #define USBHSCORE_DOEPCTL2_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
93615   #define USBHSCORE_DOEPCTL2_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL2_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
93616   #define USBHSCORE_DOEPCTL2_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
93617   #define USBHSCORE_DOEPCTL2_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
93618   #define USBHSCORE_DOEPCTL2_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93619   #define USBHSCORE_DOEPCTL2_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93620 
93621 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
93622   #define USBHSCORE_DOEPCTL2_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
93623   #define USBHSCORE_DOEPCTL2_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL2_DPID_Pos) /*!< Bit mask of DPID field.                      */
93624   #define USBHSCORE_DOEPCTL2_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
93625   #define USBHSCORE_DOEPCTL2_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
93626   #define USBHSCORE_DOEPCTL2_DPID_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93627   #define USBHSCORE_DOEPCTL2_DPID_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93628 
93629 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
93630   #define USBHSCORE_DOEPCTL2_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
93631   #define USBHSCORE_DOEPCTL2_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL2_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
93632   #define USBHSCORE_DOEPCTL2_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
93633   #define USBHSCORE_DOEPCTL2_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
93634   #define USBHSCORE_DOEPCTL2_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
93635   #define USBHSCORE_DOEPCTL2_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
93636 
93637 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
93638   #define USBHSCORE_DOEPCTL2_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
93639   #define USBHSCORE_DOEPCTL2_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL2_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
93640   #define USBHSCORE_DOEPCTL2_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
93641   #define USBHSCORE_DOEPCTL2_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
93642   #define USBHSCORE_DOEPCTL2_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
93643   #define USBHSCORE_DOEPCTL2_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
93644   #define USBHSCORE_DOEPCTL2_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
93645   #define USBHSCORE_DOEPCTL2_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                       */
93646 
93647 /* STALL @Bit 21 : STALL Handshake (Stall) */
93648   #define USBHSCORE_DOEPCTL2_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
93649   #define USBHSCORE_DOEPCTL2_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL2_STALL_Pos) /*!< Bit mask of STALL field.                   */
93650   #define USBHSCORE_DOEPCTL2_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
93651   #define USBHSCORE_DOEPCTL2_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
93652   #define USBHSCORE_DOEPCTL2_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93653   #define USBHSCORE_DOEPCTL2_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93654 
93655 /* CNAK @Bit 26 : Clear NAK (CNAK) */
93656   #define USBHSCORE_DOEPCTL2_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
93657   #define USBHSCORE_DOEPCTL2_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL2_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
93658   #define USBHSCORE_DOEPCTL2_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
93659   #define USBHSCORE_DOEPCTL2_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
93660   #define USBHSCORE_DOEPCTL2_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93661   #define USBHSCORE_DOEPCTL2_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93662 
93663 /* SNAK @Bit 27 : Set NAK (SNAK) */
93664   #define USBHSCORE_DOEPCTL2_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
93665   #define USBHSCORE_DOEPCTL2_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL2_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
93666   #define USBHSCORE_DOEPCTL2_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
93667   #define USBHSCORE_DOEPCTL2_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
93668   #define USBHSCORE_DOEPCTL2_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93669   #define USBHSCORE_DOEPCTL2_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93670 
93671 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
93672   #define USBHSCORE_DOEPCTL2_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
93673   #define USBHSCORE_DOEPCTL2_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL2_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
93674   #define USBHSCORE_DOEPCTL2_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
93675   #define USBHSCORE_DOEPCTL2_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
93676   #define USBHSCORE_DOEPCTL2_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93677   #define USBHSCORE_DOEPCTL2_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93678 
93679 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
93680   #define USBHSCORE_DOEPCTL2_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
93681   #define USBHSCORE_DOEPCTL2_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL2_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
93682   #define USBHSCORE_DOEPCTL2_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
93683   #define USBHSCORE_DOEPCTL2_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
93684   #define USBHSCORE_DOEPCTL2_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93685   #define USBHSCORE_DOEPCTL2_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93686 
93687 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
93688   #define USBHSCORE_DOEPCTL2_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
93689   #define USBHSCORE_DOEPCTL2_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL2_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
93690   #define USBHSCORE_DOEPCTL2_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
93691   #define USBHSCORE_DOEPCTL2_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
93692   #define USBHSCORE_DOEPCTL2_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93693   #define USBHSCORE_DOEPCTL2_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93694 
93695 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
93696   #define USBHSCORE_DOEPCTL2_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
93697   #define USBHSCORE_DOEPCTL2_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL2_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
93698   #define USBHSCORE_DOEPCTL2_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
93699   #define USBHSCORE_DOEPCTL2_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
93700   #define USBHSCORE_DOEPCTL2_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93701   #define USBHSCORE_DOEPCTL2_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93702 
93703 
93704 /* USBHSCORE_DOEPINT2: Device OUT Endpoint 2 Interrupt Register */
93705   #define USBHSCORE_DOEPINT2_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT2 register.                                  */
93706 
93707 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
93708   #define USBHSCORE_DOEPINT2_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
93709   #define USBHSCORE_DOEPINT2_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT2_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
93710   #define USBHSCORE_DOEPINT2_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
93711   #define USBHSCORE_DOEPINT2_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
93712   #define USBHSCORE_DOEPINT2_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93713   #define USBHSCORE_DOEPINT2_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93714 
93715 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
93716   #define USBHSCORE_DOEPINT2_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
93717   #define USBHSCORE_DOEPINT2_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT2_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
93718   #define USBHSCORE_DOEPINT2_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
93719   #define USBHSCORE_DOEPINT2_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
93720   #define USBHSCORE_DOEPINT2_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
93721   #define USBHSCORE_DOEPINT2_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
93722 
93723 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
93724   #define USBHSCORE_DOEPINT2_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
93725   #define USBHSCORE_DOEPINT2_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT2_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
93726   #define USBHSCORE_DOEPINT2_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
93727   #define USBHSCORE_DOEPINT2_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
93728   #define USBHSCORE_DOEPINT2_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
93729   #define USBHSCORE_DOEPINT2_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
93730 
93731 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
93732   #define USBHSCORE_DOEPINT2_SETUP_Pos (3UL)         /*!< Position of SETUP field.                                             */
93733   #define USBHSCORE_DOEPINT2_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT2_SETUP_Pos) /*!< Bit mask of SETUP field.                   */
93734   #define USBHSCORE_DOEPINT2_SETUP_Min (0x0UL)       /*!< Min enumerator value of SETUP field.                                 */
93735   #define USBHSCORE_DOEPINT2_SETUP_Max (0x1UL)       /*!< Max enumerator value of SETUP field.                                 */
93736   #define USBHSCORE_DOEPINT2_SETUP_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93737   #define USBHSCORE_DOEPINT2_SETUP_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93738 
93739 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
93740   #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Pos (4UL)   /*!< Position of OUTTKNEPDIS field.                                       */
93741   #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT2_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */
93742   #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                           */
93743   #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                           */
93744   #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93745   #define USBHSCORE_DOEPINT2_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93746 
93747 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
93748   #define USBHSCORE_DOEPINT2_STSPHSERCVD_Pos (5UL)   /*!< Position of STSPHSERCVD field.                                       */
93749   #define USBHSCORE_DOEPINT2_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT2_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */
93750   #define USBHSCORE_DOEPINT2_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                           */
93751   #define USBHSCORE_DOEPINT2_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                           */
93752   #define USBHSCORE_DOEPINT2_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93753   #define USBHSCORE_DOEPINT2_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93754 
93755 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
93756   #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                   */
93757   #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT2_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP
93758                                                                             field.*/
93759   #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                     */
93760   #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                     */
93761   #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                */
93762   #define USBHSCORE_DOEPINT2_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
93763 
93764 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
93765   #define USBHSCORE_DOEPINT2_OUTPKTERR_Pos (8UL)     /*!< Position of OUTPKTERR field.                                         */
93766   #define USBHSCORE_DOEPINT2_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT2_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.       */
93767   #define USBHSCORE_DOEPINT2_OUTPKTERR_Min (0x0UL)   /*!< Min enumerator value of OUTPKTERR field.                             */
93768   #define USBHSCORE_DOEPINT2_OUTPKTERR_Max (0x1UL)   /*!< Max enumerator value of OUTPKTERR field.                             */
93769   #define USBHSCORE_DOEPINT2_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93770   #define USBHSCORE_DOEPINT2_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93771 
93772 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
93773   #define USBHSCORE_DOEPINT2_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
93774   #define USBHSCORE_DOEPINT2_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT2_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
93775   #define USBHSCORE_DOEPINT2_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
93776   #define USBHSCORE_DOEPINT2_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
93777   #define USBHSCORE_DOEPINT2_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
93778   #define USBHSCORE_DOEPINT2_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
93779 
93780 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
93781   #define USBHSCORE_DOEPINT2_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
93782   #define USBHSCORE_DOEPINT2_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT2_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
93783   #define USBHSCORE_DOEPINT2_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
93784   #define USBHSCORE_DOEPINT2_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
93785   #define USBHSCORE_DOEPINT2_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93786   #define USBHSCORE_DOEPINT2_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93787 
93788 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
93789   #define USBHSCORE_DOEPINT2_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
93790   #define USBHSCORE_DOEPINT2_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT2_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
93791   #define USBHSCORE_DOEPINT2_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
93792   #define USBHSCORE_DOEPINT2_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
93793   #define USBHSCORE_DOEPINT2_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
93794   #define USBHSCORE_DOEPINT2_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
93795 
93796 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
93797   #define USBHSCORE_DOEPINT2_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
93798   #define USBHSCORE_DOEPINT2_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT2_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
93799   #define USBHSCORE_DOEPINT2_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
93800   #define USBHSCORE_DOEPINT2_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
93801   #define USBHSCORE_DOEPINT2_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93802   #define USBHSCORE_DOEPINT2_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93803 
93804 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
93805   #define USBHSCORE_DOEPINT2_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
93806   #define USBHSCORE_DOEPINT2_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT2_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
93807   #define USBHSCORE_DOEPINT2_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
93808   #define USBHSCORE_DOEPINT2_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
93809   #define USBHSCORE_DOEPINT2_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
93810   #define USBHSCORE_DOEPINT2_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
93811 
93812 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
93813   #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Pos (15UL)  /*!< Position of STUPPKTRCVD field.                                       */
93814   #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT2_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */
93815   #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                           */
93816   #define USBHSCORE_DOEPINT2_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                           */
93817   #define USBHSCORE_DOEPINT2_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                   */
93818   #define USBHSCORE_DOEPINT2_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                       */
93819 
93820 
93821 /* USBHSCORE_DOEPTSIZ2: Device OUT Endpoint 2 Transfer Size Register */
93822   #define USBHSCORE_DOEPTSIZ2_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ2 register.                                */
93823 
93824 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
93825   #define USBHSCORE_DOEPTSIZ2_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
93826   #define USBHSCORE_DOEPTSIZ2_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ2_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
93827 
93828 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
93829   #define USBHSCORE_DOEPTSIZ2_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
93830   #define USBHSCORE_DOEPTSIZ2_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ2_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
93831 
93832 /* RXDPID @Bits 29..30 : RxDPID */
93833   #define USBHSCORE_DOEPTSIZ2_RXDPID_Pos (29UL)      /*!< Position of RXDPID field.                                            */
93834   #define USBHSCORE_DOEPTSIZ2_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ2_RXDPID_Pos) /*!< Bit mask of RXDPID field.              */
93835   #define USBHSCORE_DOEPTSIZ2_RXDPID_Min (0x0UL)     /*!< Min enumerator value of RXDPID field.                                */
93836   #define USBHSCORE_DOEPTSIZ2_RXDPID_Max (0x3UL)     /*!< Max enumerator value of RXDPID field.                                */
93837   #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA0 (0x0UL)   /*!< (unspecified)                                                        */
93838   #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                   */
93839   #define USBHSCORE_DOEPTSIZ2_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                   */
93840   #define USBHSCORE_DOEPTSIZ2_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                   */
93841 
93842 
93843 /* USBHSCORE_DOEPDMA2: Device OUT Endpoint 2 DMA Address Register */
93844   #define USBHSCORE_DOEPDMA2_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA2 register.                                  */
93845 
93846 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
93847   #define USBHSCORE_DOEPDMA2_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
93848   #define USBHSCORE_DOEPDMA2_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA2_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
93849 
93850 
93851 /* USBHSCORE_DOEPCTL3: Device Control OUT Endpoint 3 Control Register */
93852   #define USBHSCORE_DOEPCTL3_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL3 register.                                  */
93853 
93854 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
93855   #define USBHSCORE_DOEPCTL3_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
93856   #define USBHSCORE_DOEPCTL3_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL3_MPS_Pos) /*!< Bit mask of MPS field.                       */
93857 
93858 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
93859   #define USBHSCORE_DOEPCTL3_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
93860   #define USBHSCORE_DOEPCTL3_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL3_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
93861   #define USBHSCORE_DOEPCTL3_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
93862   #define USBHSCORE_DOEPCTL3_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
93863   #define USBHSCORE_DOEPCTL3_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93864   #define USBHSCORE_DOEPCTL3_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93865 
93866 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
93867   #define USBHSCORE_DOEPCTL3_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
93868   #define USBHSCORE_DOEPCTL3_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL3_DPID_Pos) /*!< Bit mask of DPID field.                      */
93869   #define USBHSCORE_DOEPCTL3_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
93870   #define USBHSCORE_DOEPCTL3_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
93871   #define USBHSCORE_DOEPCTL3_DPID_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93872   #define USBHSCORE_DOEPCTL3_DPID_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93873 
93874 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
93875   #define USBHSCORE_DOEPCTL3_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
93876   #define USBHSCORE_DOEPCTL3_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL3_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
93877   #define USBHSCORE_DOEPCTL3_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
93878   #define USBHSCORE_DOEPCTL3_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
93879   #define USBHSCORE_DOEPCTL3_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
93880   #define USBHSCORE_DOEPCTL3_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
93881 
93882 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
93883   #define USBHSCORE_DOEPCTL3_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
93884   #define USBHSCORE_DOEPCTL3_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL3_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
93885   #define USBHSCORE_DOEPCTL3_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
93886   #define USBHSCORE_DOEPCTL3_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
93887   #define USBHSCORE_DOEPCTL3_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
93888   #define USBHSCORE_DOEPCTL3_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
93889   #define USBHSCORE_DOEPCTL3_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
93890   #define USBHSCORE_DOEPCTL3_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                       */
93891 
93892 /* STALL @Bit 21 : STALL Handshake (Stall) */
93893   #define USBHSCORE_DOEPCTL3_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
93894   #define USBHSCORE_DOEPCTL3_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL3_STALL_Pos) /*!< Bit mask of STALL field.                   */
93895   #define USBHSCORE_DOEPCTL3_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
93896   #define USBHSCORE_DOEPCTL3_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
93897   #define USBHSCORE_DOEPCTL3_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93898   #define USBHSCORE_DOEPCTL3_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93899 
93900 /* CNAK @Bit 26 : Clear NAK (CNAK) */
93901   #define USBHSCORE_DOEPCTL3_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
93902   #define USBHSCORE_DOEPCTL3_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL3_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
93903   #define USBHSCORE_DOEPCTL3_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
93904   #define USBHSCORE_DOEPCTL3_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
93905   #define USBHSCORE_DOEPCTL3_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93906   #define USBHSCORE_DOEPCTL3_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93907 
93908 /* SNAK @Bit 27 : Set NAK (SNAK) */
93909   #define USBHSCORE_DOEPCTL3_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
93910   #define USBHSCORE_DOEPCTL3_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL3_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
93911   #define USBHSCORE_DOEPCTL3_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
93912   #define USBHSCORE_DOEPCTL3_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
93913   #define USBHSCORE_DOEPCTL3_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
93914   #define USBHSCORE_DOEPCTL3_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
93915 
93916 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
93917   #define USBHSCORE_DOEPCTL3_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
93918   #define USBHSCORE_DOEPCTL3_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL3_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
93919   #define USBHSCORE_DOEPCTL3_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
93920   #define USBHSCORE_DOEPCTL3_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
93921   #define USBHSCORE_DOEPCTL3_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93922   #define USBHSCORE_DOEPCTL3_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93923 
93924 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
93925   #define USBHSCORE_DOEPCTL3_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
93926   #define USBHSCORE_DOEPCTL3_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL3_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
93927   #define USBHSCORE_DOEPCTL3_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
93928   #define USBHSCORE_DOEPCTL3_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
93929   #define USBHSCORE_DOEPCTL3_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
93930   #define USBHSCORE_DOEPCTL3_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
93931 
93932 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
93933   #define USBHSCORE_DOEPCTL3_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
93934   #define USBHSCORE_DOEPCTL3_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL3_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
93935   #define USBHSCORE_DOEPCTL3_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
93936   #define USBHSCORE_DOEPCTL3_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
93937   #define USBHSCORE_DOEPCTL3_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93938   #define USBHSCORE_DOEPCTL3_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93939 
93940 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
93941   #define USBHSCORE_DOEPCTL3_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
93942   #define USBHSCORE_DOEPCTL3_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL3_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
93943   #define USBHSCORE_DOEPCTL3_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
93944   #define USBHSCORE_DOEPCTL3_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
93945   #define USBHSCORE_DOEPCTL3_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93946   #define USBHSCORE_DOEPCTL3_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93947 
93948 
93949 /* USBHSCORE_DOEPINT3: Device OUT Endpoint 3 Interrupt Register */
93950   #define USBHSCORE_DOEPINT3_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT3 register.                                  */
93951 
93952 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
93953   #define USBHSCORE_DOEPINT3_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
93954   #define USBHSCORE_DOEPINT3_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT3_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
93955   #define USBHSCORE_DOEPINT3_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
93956   #define USBHSCORE_DOEPINT3_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
93957   #define USBHSCORE_DOEPINT3_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
93958   #define USBHSCORE_DOEPINT3_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
93959 
93960 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
93961   #define USBHSCORE_DOEPINT3_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
93962   #define USBHSCORE_DOEPINT3_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT3_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
93963   #define USBHSCORE_DOEPINT3_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
93964   #define USBHSCORE_DOEPINT3_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
93965   #define USBHSCORE_DOEPINT3_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
93966   #define USBHSCORE_DOEPINT3_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
93967 
93968 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
93969   #define USBHSCORE_DOEPINT3_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
93970   #define USBHSCORE_DOEPINT3_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT3_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
93971   #define USBHSCORE_DOEPINT3_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
93972   #define USBHSCORE_DOEPINT3_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
93973   #define USBHSCORE_DOEPINT3_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
93974   #define USBHSCORE_DOEPINT3_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
93975 
93976 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
93977   #define USBHSCORE_DOEPINT3_SETUP_Pos (3UL)         /*!< Position of SETUP field.                                             */
93978   #define USBHSCORE_DOEPINT3_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT3_SETUP_Pos) /*!< Bit mask of SETUP field.                   */
93979   #define USBHSCORE_DOEPINT3_SETUP_Min (0x0UL)       /*!< Min enumerator value of SETUP field.                                 */
93980   #define USBHSCORE_DOEPINT3_SETUP_Max (0x1UL)       /*!< Max enumerator value of SETUP field.                                 */
93981   #define USBHSCORE_DOEPINT3_SETUP_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
93982   #define USBHSCORE_DOEPINT3_SETUP_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
93983 
93984 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
93985   #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Pos (4UL)   /*!< Position of OUTTKNEPDIS field.                                       */
93986   #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT3_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */
93987   #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                           */
93988   #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                           */
93989   #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93990   #define USBHSCORE_DOEPINT3_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93991 
93992 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
93993   #define USBHSCORE_DOEPINT3_STSPHSERCVD_Pos (5UL)   /*!< Position of STSPHSERCVD field.                                       */
93994   #define USBHSCORE_DOEPINT3_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT3_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */
93995   #define USBHSCORE_DOEPINT3_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                           */
93996   #define USBHSCORE_DOEPINT3_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                           */
93997   #define USBHSCORE_DOEPINT3_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
93998   #define USBHSCORE_DOEPINT3_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
93999 
94000 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
94001   #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                   */
94002   #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT3_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP
94003                                                                             field.*/
94004   #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                     */
94005   #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                     */
94006   #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                */
94007   #define USBHSCORE_DOEPINT3_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
94008 
94009 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
94010   #define USBHSCORE_DOEPINT3_OUTPKTERR_Pos (8UL)     /*!< Position of OUTPKTERR field.                                         */
94011   #define USBHSCORE_DOEPINT3_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT3_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.       */
94012   #define USBHSCORE_DOEPINT3_OUTPKTERR_Min (0x0UL)   /*!< Min enumerator value of OUTPKTERR field.                             */
94013   #define USBHSCORE_DOEPINT3_OUTPKTERR_Max (0x1UL)   /*!< Max enumerator value of OUTPKTERR field.                             */
94014   #define USBHSCORE_DOEPINT3_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94015   #define USBHSCORE_DOEPINT3_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94016 
94017 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
94018   #define USBHSCORE_DOEPINT3_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
94019   #define USBHSCORE_DOEPINT3_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT3_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
94020   #define USBHSCORE_DOEPINT3_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
94021   #define USBHSCORE_DOEPINT3_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
94022   #define USBHSCORE_DOEPINT3_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
94023   #define USBHSCORE_DOEPINT3_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
94024 
94025 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
94026   #define USBHSCORE_DOEPINT3_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
94027   #define USBHSCORE_DOEPINT3_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT3_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
94028   #define USBHSCORE_DOEPINT3_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
94029   #define USBHSCORE_DOEPINT3_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
94030   #define USBHSCORE_DOEPINT3_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94031   #define USBHSCORE_DOEPINT3_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94032 
94033 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
94034   #define USBHSCORE_DOEPINT3_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
94035   #define USBHSCORE_DOEPINT3_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT3_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
94036   #define USBHSCORE_DOEPINT3_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
94037   #define USBHSCORE_DOEPINT3_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
94038   #define USBHSCORE_DOEPINT3_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
94039   #define USBHSCORE_DOEPINT3_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
94040 
94041 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
94042   #define USBHSCORE_DOEPINT3_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
94043   #define USBHSCORE_DOEPINT3_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT3_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
94044   #define USBHSCORE_DOEPINT3_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
94045   #define USBHSCORE_DOEPINT3_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
94046   #define USBHSCORE_DOEPINT3_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94047   #define USBHSCORE_DOEPINT3_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94048 
94049 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
94050   #define USBHSCORE_DOEPINT3_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
94051   #define USBHSCORE_DOEPINT3_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT3_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
94052   #define USBHSCORE_DOEPINT3_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
94053   #define USBHSCORE_DOEPINT3_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
94054   #define USBHSCORE_DOEPINT3_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
94055   #define USBHSCORE_DOEPINT3_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
94056 
94057 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
94058   #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Pos (15UL)  /*!< Position of STUPPKTRCVD field.                                       */
94059   #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT3_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */
94060   #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                           */
94061   #define USBHSCORE_DOEPINT3_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                           */
94062   #define USBHSCORE_DOEPINT3_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                   */
94063   #define USBHSCORE_DOEPINT3_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                       */
94064 
94065 
94066 /* USBHSCORE_DOEPTSIZ3: Device OUT Endpoint 3 Transfer Size Register */
94067   #define USBHSCORE_DOEPTSIZ3_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ3 register.                                */
94068 
94069 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
94070   #define USBHSCORE_DOEPTSIZ3_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
94071   #define USBHSCORE_DOEPTSIZ3_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ3_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
94072 
94073 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
94074   #define USBHSCORE_DOEPTSIZ3_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
94075   #define USBHSCORE_DOEPTSIZ3_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ3_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
94076 
94077 /* RXDPID @Bits 29..30 : RxDPID */
94078   #define USBHSCORE_DOEPTSIZ3_RXDPID_Pos (29UL)      /*!< Position of RXDPID field.                                            */
94079   #define USBHSCORE_DOEPTSIZ3_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ3_RXDPID_Pos) /*!< Bit mask of RXDPID field.              */
94080   #define USBHSCORE_DOEPTSIZ3_RXDPID_Min (0x0UL)     /*!< Min enumerator value of RXDPID field.                                */
94081   #define USBHSCORE_DOEPTSIZ3_RXDPID_Max (0x3UL)     /*!< Max enumerator value of RXDPID field.                                */
94082   #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA0 (0x0UL)   /*!< (unspecified)                                                        */
94083   #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                   */
94084   #define USBHSCORE_DOEPTSIZ3_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                   */
94085   #define USBHSCORE_DOEPTSIZ3_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                   */
94086 
94087 
94088 /* USBHSCORE_DOEPDMA3: Device OUT Endpoint 3 DMA Address Register */
94089   #define USBHSCORE_DOEPDMA3_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA3 register.                                  */
94090 
94091 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
94092   #define USBHSCORE_DOEPDMA3_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
94093   #define USBHSCORE_DOEPDMA3_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA3_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
94094 
94095 
94096 /* USBHSCORE_DOEPCTL4: Device Control OUT Endpoint 4 Control Register */
94097   #define USBHSCORE_DOEPCTL4_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL4 register.                                  */
94098 
94099 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
94100   #define USBHSCORE_DOEPCTL4_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
94101   #define USBHSCORE_DOEPCTL4_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL4_MPS_Pos) /*!< Bit mask of MPS field.                       */
94102 
94103 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
94104   #define USBHSCORE_DOEPCTL4_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
94105   #define USBHSCORE_DOEPCTL4_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL4_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
94106   #define USBHSCORE_DOEPCTL4_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
94107   #define USBHSCORE_DOEPCTL4_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
94108   #define USBHSCORE_DOEPCTL4_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
94109   #define USBHSCORE_DOEPCTL4_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
94110 
94111 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
94112   #define USBHSCORE_DOEPCTL4_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
94113   #define USBHSCORE_DOEPCTL4_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL4_DPID_Pos) /*!< Bit mask of DPID field.                      */
94114   #define USBHSCORE_DOEPCTL4_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
94115   #define USBHSCORE_DOEPCTL4_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
94116   #define USBHSCORE_DOEPCTL4_DPID_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
94117   #define USBHSCORE_DOEPCTL4_DPID_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
94118 
94119 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
94120   #define USBHSCORE_DOEPCTL4_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
94121   #define USBHSCORE_DOEPCTL4_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL4_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
94122   #define USBHSCORE_DOEPCTL4_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
94123   #define USBHSCORE_DOEPCTL4_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
94124   #define USBHSCORE_DOEPCTL4_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
94125   #define USBHSCORE_DOEPCTL4_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
94126 
94127 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
94128   #define USBHSCORE_DOEPCTL4_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
94129   #define USBHSCORE_DOEPCTL4_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL4_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
94130   #define USBHSCORE_DOEPCTL4_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
94131   #define USBHSCORE_DOEPCTL4_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
94132   #define USBHSCORE_DOEPCTL4_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
94133   #define USBHSCORE_DOEPCTL4_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
94134   #define USBHSCORE_DOEPCTL4_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
94135   #define USBHSCORE_DOEPCTL4_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                       */
94136 
94137 /* STALL @Bit 21 : STALL Handshake (Stall) */
94138   #define USBHSCORE_DOEPCTL4_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
94139   #define USBHSCORE_DOEPCTL4_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL4_STALL_Pos) /*!< Bit mask of STALL field.                   */
94140   #define USBHSCORE_DOEPCTL4_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
94141   #define USBHSCORE_DOEPCTL4_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
94142   #define USBHSCORE_DOEPCTL4_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94143   #define USBHSCORE_DOEPCTL4_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94144 
94145 /* CNAK @Bit 26 : Clear NAK (CNAK) */
94146   #define USBHSCORE_DOEPCTL4_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
94147   #define USBHSCORE_DOEPCTL4_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL4_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
94148   #define USBHSCORE_DOEPCTL4_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
94149   #define USBHSCORE_DOEPCTL4_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
94150   #define USBHSCORE_DOEPCTL4_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
94151   #define USBHSCORE_DOEPCTL4_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
94152 
94153 /* SNAK @Bit 27 : Set NAK (SNAK) */
94154   #define USBHSCORE_DOEPCTL4_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
94155   #define USBHSCORE_DOEPCTL4_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL4_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
94156   #define USBHSCORE_DOEPCTL4_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
94157   #define USBHSCORE_DOEPCTL4_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
94158   #define USBHSCORE_DOEPCTL4_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
94159   #define USBHSCORE_DOEPCTL4_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
94160 
94161 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
94162   #define USBHSCORE_DOEPCTL4_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
94163   #define USBHSCORE_DOEPCTL4_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL4_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
94164   #define USBHSCORE_DOEPCTL4_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
94165   #define USBHSCORE_DOEPCTL4_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
94166   #define USBHSCORE_DOEPCTL4_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
94167   #define USBHSCORE_DOEPCTL4_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
94168 
94169 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
94170   #define USBHSCORE_DOEPCTL4_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
94171   #define USBHSCORE_DOEPCTL4_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL4_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
94172   #define USBHSCORE_DOEPCTL4_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
94173   #define USBHSCORE_DOEPCTL4_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
94174   #define USBHSCORE_DOEPCTL4_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
94175   #define USBHSCORE_DOEPCTL4_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
94176 
94177 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
94178   #define USBHSCORE_DOEPCTL4_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
94179   #define USBHSCORE_DOEPCTL4_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL4_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
94180   #define USBHSCORE_DOEPCTL4_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
94181   #define USBHSCORE_DOEPCTL4_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
94182   #define USBHSCORE_DOEPCTL4_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94183   #define USBHSCORE_DOEPCTL4_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94184 
94185 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
94186   #define USBHSCORE_DOEPCTL4_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
94187   #define USBHSCORE_DOEPCTL4_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL4_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
94188   #define USBHSCORE_DOEPCTL4_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
94189   #define USBHSCORE_DOEPCTL4_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
94190   #define USBHSCORE_DOEPCTL4_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94191   #define USBHSCORE_DOEPCTL4_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94192 
94193 
94194 /* USBHSCORE_DOEPINT4: Device OUT Endpoint 4 Interrupt Register */
94195   #define USBHSCORE_DOEPINT4_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT4 register.                                  */
94196 
94197 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
94198   #define USBHSCORE_DOEPINT4_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
94199   #define USBHSCORE_DOEPINT4_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT4_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
94200   #define USBHSCORE_DOEPINT4_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
94201   #define USBHSCORE_DOEPINT4_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
94202   #define USBHSCORE_DOEPINT4_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94203   #define USBHSCORE_DOEPINT4_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94204 
94205 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
94206   #define USBHSCORE_DOEPINT4_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
94207   #define USBHSCORE_DOEPINT4_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT4_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
94208   #define USBHSCORE_DOEPINT4_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
94209   #define USBHSCORE_DOEPINT4_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
94210   #define USBHSCORE_DOEPINT4_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
94211   #define USBHSCORE_DOEPINT4_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
94212 
94213 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
94214   #define USBHSCORE_DOEPINT4_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
94215   #define USBHSCORE_DOEPINT4_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT4_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
94216   #define USBHSCORE_DOEPINT4_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
94217   #define USBHSCORE_DOEPINT4_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
94218   #define USBHSCORE_DOEPINT4_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94219   #define USBHSCORE_DOEPINT4_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94220 
94221 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
94222   #define USBHSCORE_DOEPINT4_SETUP_Pos (3UL)         /*!< Position of SETUP field.                                             */
94223   #define USBHSCORE_DOEPINT4_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT4_SETUP_Pos) /*!< Bit mask of SETUP field.                   */
94224   #define USBHSCORE_DOEPINT4_SETUP_Min (0x0UL)       /*!< Min enumerator value of SETUP field.                                 */
94225   #define USBHSCORE_DOEPINT4_SETUP_Max (0x1UL)       /*!< Max enumerator value of SETUP field.                                 */
94226   #define USBHSCORE_DOEPINT4_SETUP_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94227   #define USBHSCORE_DOEPINT4_SETUP_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94228 
94229 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
94230   #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Pos (4UL)   /*!< Position of OUTTKNEPDIS field.                                       */
94231   #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT4_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */
94232   #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                           */
94233   #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                           */
94234   #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
94235   #define USBHSCORE_DOEPINT4_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
94236 
94237 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
94238   #define USBHSCORE_DOEPINT4_STSPHSERCVD_Pos (5UL)   /*!< Position of STSPHSERCVD field.                                       */
94239   #define USBHSCORE_DOEPINT4_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT4_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */
94240   #define USBHSCORE_DOEPINT4_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                           */
94241   #define USBHSCORE_DOEPINT4_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                           */
94242   #define USBHSCORE_DOEPINT4_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
94243   #define USBHSCORE_DOEPINT4_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
94244 
94245 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
94246   #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                   */
94247   #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT4_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP
94248                                                                             field.*/
94249   #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                     */
94250   #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                     */
94251   #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                */
94252   #define USBHSCORE_DOEPINT4_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
94253 
94254 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
94255   #define USBHSCORE_DOEPINT4_OUTPKTERR_Pos (8UL)     /*!< Position of OUTPKTERR field.                                         */
94256   #define USBHSCORE_DOEPINT4_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT4_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.       */
94257   #define USBHSCORE_DOEPINT4_OUTPKTERR_Min (0x0UL)   /*!< Min enumerator value of OUTPKTERR field.                             */
94258   #define USBHSCORE_DOEPINT4_OUTPKTERR_Max (0x1UL)   /*!< Max enumerator value of OUTPKTERR field.                             */
94259   #define USBHSCORE_DOEPINT4_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94260   #define USBHSCORE_DOEPINT4_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94261 
94262 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
94263   #define USBHSCORE_DOEPINT4_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
94264   #define USBHSCORE_DOEPINT4_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT4_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
94265   #define USBHSCORE_DOEPINT4_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
94266   #define USBHSCORE_DOEPINT4_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
94267   #define USBHSCORE_DOEPINT4_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
94268   #define USBHSCORE_DOEPINT4_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
94269 
94270 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
94271   #define USBHSCORE_DOEPINT4_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
94272   #define USBHSCORE_DOEPINT4_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT4_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
94273   #define USBHSCORE_DOEPINT4_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
94274   #define USBHSCORE_DOEPINT4_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
94275   #define USBHSCORE_DOEPINT4_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94276   #define USBHSCORE_DOEPINT4_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94277 
94278 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
94279   #define USBHSCORE_DOEPINT4_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
94280   #define USBHSCORE_DOEPINT4_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT4_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
94281   #define USBHSCORE_DOEPINT4_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
94282   #define USBHSCORE_DOEPINT4_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
94283   #define USBHSCORE_DOEPINT4_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
94284   #define USBHSCORE_DOEPINT4_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
94285 
94286 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
94287   #define USBHSCORE_DOEPINT4_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
94288   #define USBHSCORE_DOEPINT4_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT4_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
94289   #define USBHSCORE_DOEPINT4_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
94290   #define USBHSCORE_DOEPINT4_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
94291   #define USBHSCORE_DOEPINT4_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94292   #define USBHSCORE_DOEPINT4_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94293 
94294 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
94295   #define USBHSCORE_DOEPINT4_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
94296   #define USBHSCORE_DOEPINT4_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT4_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
94297   #define USBHSCORE_DOEPINT4_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
94298   #define USBHSCORE_DOEPINT4_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
94299   #define USBHSCORE_DOEPINT4_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
94300   #define USBHSCORE_DOEPINT4_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
94301 
94302 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
94303   #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Pos (15UL)  /*!< Position of STUPPKTRCVD field.                                       */
94304   #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT4_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */
94305   #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                           */
94306   #define USBHSCORE_DOEPINT4_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                           */
94307   #define USBHSCORE_DOEPINT4_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                   */
94308   #define USBHSCORE_DOEPINT4_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                       */
94309 
94310 
94311 /* USBHSCORE_DOEPTSIZ4: Device OUT Endpoint 4 Transfer Size Register */
94312   #define USBHSCORE_DOEPTSIZ4_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ4 register.                                */
94313 
94314 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
94315   #define USBHSCORE_DOEPTSIZ4_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
94316   #define USBHSCORE_DOEPTSIZ4_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ4_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
94317 
94318 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
94319   #define USBHSCORE_DOEPTSIZ4_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
94320   #define USBHSCORE_DOEPTSIZ4_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ4_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
94321 
94322 /* RXDPID @Bits 29..30 : RxDPID */
94323   #define USBHSCORE_DOEPTSIZ4_RXDPID_Pos (29UL)      /*!< Position of RXDPID field.                                            */
94324   #define USBHSCORE_DOEPTSIZ4_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ4_RXDPID_Pos) /*!< Bit mask of RXDPID field.              */
94325   #define USBHSCORE_DOEPTSIZ4_RXDPID_Min (0x0UL)     /*!< Min enumerator value of RXDPID field.                                */
94326   #define USBHSCORE_DOEPTSIZ4_RXDPID_Max (0x3UL)     /*!< Max enumerator value of RXDPID field.                                */
94327   #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA0 (0x0UL)   /*!< (unspecified)                                                        */
94328   #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                   */
94329   #define USBHSCORE_DOEPTSIZ4_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                   */
94330   #define USBHSCORE_DOEPTSIZ4_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                   */
94331 
94332 
94333 /* USBHSCORE_DOEPDMA4: Device OUT Endpoint 4 DMA Address Register */
94334   #define USBHSCORE_DOEPDMA4_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA4 register.                                  */
94335 
94336 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
94337   #define USBHSCORE_DOEPDMA4_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
94338   #define USBHSCORE_DOEPDMA4_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA4_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
94339 
94340 
94341 /* USBHSCORE_DOEPCTL5: Device Control OUT Endpoint 5 Control Register */
94342   #define USBHSCORE_DOEPCTL5_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL5 register.                                  */
94343 
94344 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
94345   #define USBHSCORE_DOEPCTL5_MPS_Pos (0UL)           /*!< Position of MPS field.                                               */
94346   #define USBHSCORE_DOEPCTL5_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL5_MPS_Pos) /*!< Bit mask of MPS field.                       */
94347 
94348 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
94349   #define USBHSCORE_DOEPCTL5_USBACTEP_Pos (15UL)     /*!< Position of USBACTEP field.                                          */
94350   #define USBHSCORE_DOEPCTL5_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL5_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.          */
94351   #define USBHSCORE_DOEPCTL5_USBACTEP_Min (0x0UL)    /*!< Min enumerator value of USBACTEP field.                              */
94352   #define USBHSCORE_DOEPCTL5_USBACTEP_Max (0x1UL)    /*!< Max enumerator value of USBACTEP field.                              */
94353   #define USBHSCORE_DOEPCTL5_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                      */
94354   #define USBHSCORE_DOEPCTL5_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                       */
94355 
94356 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
94357   #define USBHSCORE_DOEPCTL5_DPID_Pos (16UL)         /*!< Position of DPID field.                                              */
94358   #define USBHSCORE_DOEPCTL5_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL5_DPID_Pos) /*!< Bit mask of DPID field.                      */
94359   #define USBHSCORE_DOEPCTL5_DPID_Min (0x0UL)        /*!< Min enumerator value of DPID field.                                  */
94360   #define USBHSCORE_DOEPCTL5_DPID_Max (0x1UL)        /*!< Max enumerator value of DPID field.                                  */
94361   #define USBHSCORE_DOEPCTL5_DPID_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
94362   #define USBHSCORE_DOEPCTL5_DPID_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
94363 
94364 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
94365   #define USBHSCORE_DOEPCTL5_NAKSTS_Pos (17UL)       /*!< Position of NAKSTS field.                                            */
94366   #define USBHSCORE_DOEPCTL5_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL5_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.                */
94367   #define USBHSCORE_DOEPCTL5_NAKSTS_Min (0x0UL)      /*!< Min enumerator value of NAKSTS field.                                */
94368   #define USBHSCORE_DOEPCTL5_NAKSTS_Max (0x1UL)      /*!< Max enumerator value of NAKSTS field.                                */
94369   #define USBHSCORE_DOEPCTL5_NAKSTS_NONNAK (0x0UL)   /*!< (unspecified)                                                        */
94370   #define USBHSCORE_DOEPCTL5_NAKSTS_NAK (0x1UL)      /*!< (unspecified)                                                        */
94371 
94372 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
94373   #define USBHSCORE_DOEPCTL5_EPTYPE_Pos (18UL)       /*!< Position of EPTYPE field.                                            */
94374   #define USBHSCORE_DOEPCTL5_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL5_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.                */
94375   #define USBHSCORE_DOEPCTL5_EPTYPE_Min (0x0UL)      /*!< Min enumerator value of EPTYPE field.                                */
94376   #define USBHSCORE_DOEPCTL5_EPTYPE_Max (0x3UL)      /*!< Max enumerator value of EPTYPE field.                                */
94377   #define USBHSCORE_DOEPCTL5_EPTYPE_CONTROL (0x0UL)  /*!< (unspecified)                                                        */
94378   #define USBHSCORE_DOEPCTL5_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                     */
94379   #define USBHSCORE_DOEPCTL5_EPTYPE_BULK (0x2UL)     /*!< (unspecified)                                                        */
94380   #define USBHSCORE_DOEPCTL5_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                       */
94381 
94382 /* STALL @Bit 21 : STALL Handshake (Stall) */
94383   #define USBHSCORE_DOEPCTL5_STALL_Pos (21UL)        /*!< Position of STALL field.                                             */
94384   #define USBHSCORE_DOEPCTL5_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL5_STALL_Pos) /*!< Bit mask of STALL field.                   */
94385   #define USBHSCORE_DOEPCTL5_STALL_Min (0x0UL)       /*!< Min enumerator value of STALL field.                                 */
94386   #define USBHSCORE_DOEPCTL5_STALL_Max (0x1UL)       /*!< Max enumerator value of STALL field.                                 */
94387   #define USBHSCORE_DOEPCTL5_STALL_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94388   #define USBHSCORE_DOEPCTL5_STALL_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94389 
94390 /* CNAK @Bit 26 : Clear NAK (CNAK) */
94391   #define USBHSCORE_DOEPCTL5_CNAK_Pos (26UL)         /*!< Position of CNAK field.                                              */
94392   #define USBHSCORE_DOEPCTL5_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL5_CNAK_Pos) /*!< Bit mask of CNAK field.                      */
94393   #define USBHSCORE_DOEPCTL5_CNAK_Min (0x0UL)        /*!< Min enumerator value of CNAK field.                                  */
94394   #define USBHSCORE_DOEPCTL5_CNAK_Max (0x1UL)        /*!< Max enumerator value of CNAK field.                                  */
94395   #define USBHSCORE_DOEPCTL5_CNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
94396   #define USBHSCORE_DOEPCTL5_CNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
94397 
94398 /* SNAK @Bit 27 : Set NAK (SNAK) */
94399   #define USBHSCORE_DOEPCTL5_SNAK_Pos (27UL)         /*!< Position of SNAK field.                                              */
94400   #define USBHSCORE_DOEPCTL5_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL5_SNAK_Pos) /*!< Bit mask of SNAK field.                      */
94401   #define USBHSCORE_DOEPCTL5_SNAK_Min (0x0UL)        /*!< Min enumerator value of SNAK field.                                  */
94402   #define USBHSCORE_DOEPCTL5_SNAK_Max (0x1UL)        /*!< Max enumerator value of SNAK field.                                  */
94403   #define USBHSCORE_DOEPCTL5_SNAK_INACTIVE (0x0UL)   /*!< (unspecified)                                                        */
94404   #define USBHSCORE_DOEPCTL5_SNAK_ACTIVE (0x1UL)     /*!< (unspecified)                                                        */
94405 
94406 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
94407   #define USBHSCORE_DOEPCTL5_SETD0PID_Pos (28UL)     /*!< Position of SETD0PID field.                                          */
94408   #define USBHSCORE_DOEPCTL5_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL5_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.          */
94409   #define USBHSCORE_DOEPCTL5_SETD0PID_Min (0x0UL)    /*!< Min enumerator value of SETD0PID field.                              */
94410   #define USBHSCORE_DOEPCTL5_SETD0PID_Max (0x1UL)    /*!< Max enumerator value of SETD0PID field.                              */
94411   #define USBHSCORE_DOEPCTL5_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
94412   #define USBHSCORE_DOEPCTL5_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
94413 
94414 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
94415   #define USBHSCORE_DOEPCTL5_SETD1PID_Pos (29UL)     /*!< Position of SETD1PID field.                                          */
94416   #define USBHSCORE_DOEPCTL5_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL5_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.          */
94417   #define USBHSCORE_DOEPCTL5_SETD1PID_Min (0x0UL)    /*!< Min enumerator value of SETD1PID field.                              */
94418   #define USBHSCORE_DOEPCTL5_SETD1PID_Max (0x1UL)    /*!< Max enumerator value of SETD1PID field.                              */
94419   #define USBHSCORE_DOEPCTL5_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                      */
94420   #define USBHSCORE_DOEPCTL5_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                       */
94421 
94422 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
94423   #define USBHSCORE_DOEPCTL5_EPDIS_Pos (30UL)        /*!< Position of EPDIS field.                                             */
94424   #define USBHSCORE_DOEPCTL5_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL5_EPDIS_Pos) /*!< Bit mask of EPDIS field.                   */
94425   #define USBHSCORE_DOEPCTL5_EPDIS_Min (0x0UL)       /*!< Min enumerator value of EPDIS field.                                 */
94426   #define USBHSCORE_DOEPCTL5_EPDIS_Max (0x1UL)       /*!< Max enumerator value of EPDIS field.                                 */
94427   #define USBHSCORE_DOEPCTL5_EPDIS_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94428   #define USBHSCORE_DOEPCTL5_EPDIS_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94429 
94430 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
94431   #define USBHSCORE_DOEPCTL5_EPENA_Pos (31UL)        /*!< Position of EPENA field.                                             */
94432   #define USBHSCORE_DOEPCTL5_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL5_EPENA_Pos) /*!< Bit mask of EPENA field.                   */
94433   #define USBHSCORE_DOEPCTL5_EPENA_Min (0x0UL)       /*!< Min enumerator value of EPENA field.                                 */
94434   #define USBHSCORE_DOEPCTL5_EPENA_Max (0x1UL)       /*!< Max enumerator value of EPENA field.                                 */
94435   #define USBHSCORE_DOEPCTL5_EPENA_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94436   #define USBHSCORE_DOEPCTL5_EPENA_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94437 
94438 
94439 /* USBHSCORE_DOEPINT5: Device OUT Endpoint 5 Interrupt Register */
94440   #define USBHSCORE_DOEPINT5_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT5 register.                                  */
94441 
94442 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
94443   #define USBHSCORE_DOEPINT5_XFERCOMPL_Pos (0UL)     /*!< Position of XFERCOMPL field.                                         */
94444   #define USBHSCORE_DOEPINT5_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT5_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.       */
94445   #define USBHSCORE_DOEPINT5_XFERCOMPL_Min (0x0UL)   /*!< Min enumerator value of XFERCOMPL field.                             */
94446   #define USBHSCORE_DOEPINT5_XFERCOMPL_Max (0x1UL)   /*!< Max enumerator value of XFERCOMPL field.                             */
94447   #define USBHSCORE_DOEPINT5_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94448   #define USBHSCORE_DOEPINT5_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94449 
94450 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
94451   #define USBHSCORE_DOEPINT5_EPDISBLD_Pos (1UL)      /*!< Position of EPDISBLD field.                                          */
94452   #define USBHSCORE_DOEPINT5_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT5_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.          */
94453   #define USBHSCORE_DOEPINT5_EPDISBLD_Min (0x0UL)    /*!< Min enumerator value of EPDISBLD field.                              */
94454   #define USBHSCORE_DOEPINT5_EPDISBLD_Max (0x1UL)    /*!< Max enumerator value of EPDISBLD field.                              */
94455   #define USBHSCORE_DOEPINT5_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
94456   #define USBHSCORE_DOEPINT5_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
94457 
94458 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
94459   #define USBHSCORE_DOEPINT5_AHBERR_Pos (2UL)        /*!< Position of AHBERR field.                                            */
94460   #define USBHSCORE_DOEPINT5_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT5_AHBERR_Pos) /*!< Bit mask of AHBERR field.                */
94461   #define USBHSCORE_DOEPINT5_AHBERR_Min (0x0UL)      /*!< Min enumerator value of AHBERR field.                                */
94462   #define USBHSCORE_DOEPINT5_AHBERR_Max (0x1UL)      /*!< Max enumerator value of AHBERR field.                                */
94463   #define USBHSCORE_DOEPINT5_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94464   #define USBHSCORE_DOEPINT5_AHBERR_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94465 
94466 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
94467   #define USBHSCORE_DOEPINT5_SETUP_Pos (3UL)         /*!< Position of SETUP field.                                             */
94468   #define USBHSCORE_DOEPINT5_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT5_SETUP_Pos) /*!< Bit mask of SETUP field.                   */
94469   #define USBHSCORE_DOEPINT5_SETUP_Min (0x0UL)       /*!< Min enumerator value of SETUP field.                                 */
94470   #define USBHSCORE_DOEPINT5_SETUP_Max (0x1UL)       /*!< Max enumerator value of SETUP field.                                 */
94471   #define USBHSCORE_DOEPINT5_SETUP_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94472   #define USBHSCORE_DOEPINT5_SETUP_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94473 
94474 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
94475   #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Pos (4UL)   /*!< Position of OUTTKNEPDIS field.                                       */
94476   #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT5_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS field. */
94477   #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                           */
94478   #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                           */
94479   #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
94480   #define USBHSCORE_DOEPINT5_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
94481 
94482 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
94483   #define USBHSCORE_DOEPINT5_STSPHSERCVD_Pos (5UL)   /*!< Position of STSPHSERCVD field.                                       */
94484   #define USBHSCORE_DOEPINT5_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT5_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD field. */
94485   #define USBHSCORE_DOEPINT5_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                           */
94486   #define USBHSCORE_DOEPINT5_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                           */
94487   #define USBHSCORE_DOEPINT5_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
94488   #define USBHSCORE_DOEPINT5_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
94489 
94490 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
94491   #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                   */
94492   #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT5_BACK2BACKSETUP_Pos) /*!< Bit mask of BACK2BACKSETUP
94493                                                                             field.*/
94494   #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                     */
94495   #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                     */
94496   #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                */
94497   #define USBHSCORE_DOEPINT5_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                  */
94498 
94499 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
94500   #define USBHSCORE_DOEPINT5_OUTPKTERR_Pos (8UL)     /*!< Position of OUTPKTERR field.                                         */
94501   #define USBHSCORE_DOEPINT5_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT5_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.       */
94502   #define USBHSCORE_DOEPINT5_OUTPKTERR_Min (0x0UL)   /*!< Min enumerator value of OUTPKTERR field.                             */
94503   #define USBHSCORE_DOEPINT5_OUTPKTERR_Max (0x1UL)   /*!< Max enumerator value of OUTPKTERR field.                             */
94504   #define USBHSCORE_DOEPINT5_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94505   #define USBHSCORE_DOEPINT5_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94506 
94507 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
94508   #define USBHSCORE_DOEPINT5_BNAINTR_Pos (9UL)       /*!< Position of BNAINTR field.                                           */
94509   #define USBHSCORE_DOEPINT5_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT5_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.             */
94510   #define USBHSCORE_DOEPINT5_BNAINTR_Min (0x0UL)     /*!< Min enumerator value of BNAINTR field.                               */
94511   #define USBHSCORE_DOEPINT5_BNAINTR_Max (0x1UL)     /*!< Max enumerator value of BNAINTR field.                               */
94512   #define USBHSCORE_DOEPINT5_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
94513   #define USBHSCORE_DOEPINT5_BNAINTR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
94514 
94515 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
94516   #define USBHSCORE_DOEPINT5_PKTDRPSTS_Pos (11UL)    /*!< Position of PKTDRPSTS field.                                         */
94517   #define USBHSCORE_DOEPINT5_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT5_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.       */
94518   #define USBHSCORE_DOEPINT5_PKTDRPSTS_Min (0x0UL)   /*!< Min enumerator value of PKTDRPSTS field.                             */
94519   #define USBHSCORE_DOEPINT5_PKTDRPSTS_Max (0x1UL)   /*!< Max enumerator value of PKTDRPSTS field.                             */
94520   #define USBHSCORE_DOEPINT5_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94521   #define USBHSCORE_DOEPINT5_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94522 
94523 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
94524   #define USBHSCORE_DOEPINT5_BBLEERR_Pos (12UL)      /*!< Position of BBLEERR field.                                           */
94525   #define USBHSCORE_DOEPINT5_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT5_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.             */
94526   #define USBHSCORE_DOEPINT5_BBLEERR_Min (0x0UL)     /*!< Min enumerator value of BBLEERR field.                               */
94527   #define USBHSCORE_DOEPINT5_BBLEERR_Max (0x1UL)     /*!< Max enumerator value of BBLEERR field.                               */
94528   #define USBHSCORE_DOEPINT5_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
94529   #define USBHSCORE_DOEPINT5_BBLEERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
94530 
94531 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
94532   #define USBHSCORE_DOEPINT5_NAKINTRPT_Pos (13UL)    /*!< Position of NAKINTRPT field.                                         */
94533   #define USBHSCORE_DOEPINT5_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT5_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.       */
94534   #define USBHSCORE_DOEPINT5_NAKINTRPT_Min (0x0UL)   /*!< Min enumerator value of NAKINTRPT field.                             */
94535   #define USBHSCORE_DOEPINT5_NAKINTRPT_Max (0x1UL)   /*!< Max enumerator value of NAKINTRPT field.                             */
94536   #define USBHSCORE_DOEPINT5_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94537   #define USBHSCORE_DOEPINT5_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94538 
94539 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
94540   #define USBHSCORE_DOEPINT5_NYETINTRPT_Pos (14UL)   /*!< Position of NYETINTRPT field.                                        */
94541   #define USBHSCORE_DOEPINT5_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT5_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.    */
94542   #define USBHSCORE_DOEPINT5_NYETINTRPT_Min (0x0UL)  /*!< Min enumerator value of NYETINTRPT field.                            */
94543   #define USBHSCORE_DOEPINT5_NYETINTRPT_Max (0x1UL)  /*!< Max enumerator value of NYETINTRPT field.                            */
94544   #define USBHSCORE_DOEPINT5_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
94545   #define USBHSCORE_DOEPINT5_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
94546 
94547 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
94548   #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Pos (15UL)  /*!< Position of STUPPKTRCVD field.                                       */
94549   #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT5_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD field. */
94550   #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                           */
94551   #define USBHSCORE_DOEPINT5_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                           */
94552   #define USBHSCORE_DOEPINT5_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                   */
94553   #define USBHSCORE_DOEPINT5_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                       */
94554 
94555 
94556 /* USBHSCORE_DOEPTSIZ5: Device OUT Endpoint 5 Transfer Size Register */
94557   #define USBHSCORE_DOEPTSIZ5_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ5 register.                                */
94558 
94559 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
94560   #define USBHSCORE_DOEPTSIZ5_XFERSIZE_Pos (0UL)     /*!< Position of XFERSIZE field.                                          */
94561   #define USBHSCORE_DOEPTSIZ5_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ5_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.    */
94562 
94563 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
94564   #define USBHSCORE_DOEPTSIZ5_PKTCNT_Pos (19UL)      /*!< Position of PKTCNT field.                                            */
94565   #define USBHSCORE_DOEPTSIZ5_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ5_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.            */
94566 
94567 /* RXDPID @Bits 29..30 : RxDPID */
94568   #define USBHSCORE_DOEPTSIZ5_RXDPID_Pos (29UL)      /*!< Position of RXDPID field.                                            */
94569   #define USBHSCORE_DOEPTSIZ5_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ5_RXDPID_Pos) /*!< Bit mask of RXDPID field.              */
94570   #define USBHSCORE_DOEPTSIZ5_RXDPID_Min (0x0UL)     /*!< Min enumerator value of RXDPID field.                                */
94571   #define USBHSCORE_DOEPTSIZ5_RXDPID_Max (0x3UL)     /*!< Max enumerator value of RXDPID field.                                */
94572   #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA0 (0x0UL)   /*!< (unspecified)                                                        */
94573   #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                   */
94574   #define USBHSCORE_DOEPTSIZ5_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                   */
94575   #define USBHSCORE_DOEPTSIZ5_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                   */
94576 
94577 
94578 /* USBHSCORE_DOEPDMA5: Device OUT Endpoint 5 DMA Address Register */
94579   #define USBHSCORE_DOEPDMA5_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA5 register.                                  */
94580 
94581 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
94582   #define USBHSCORE_DOEPDMA5_DMAADDR_Pos (0UL)       /*!< Position of DMAADDR field.                                           */
94583   #define USBHSCORE_DOEPDMA5_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA5_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.      */
94584 
94585 
94586 /* USBHSCORE_DOEPCTL12: Device Control OUT Endpoint 12 Control Register */
94587   #define USBHSCORE_DOEPCTL12_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL12 register.                                */
94588 
94589 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
94590   #define USBHSCORE_DOEPCTL12_MPS_Pos (0UL)          /*!< Position of MPS field.                                               */
94591   #define USBHSCORE_DOEPCTL12_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL12_MPS_Pos) /*!< Bit mask of MPS field.                     */
94592 
94593 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
94594   #define USBHSCORE_DOEPCTL12_USBACTEP_Pos (15UL)    /*!< Position of USBACTEP field.                                          */
94595   #define USBHSCORE_DOEPCTL12_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL12_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.        */
94596   #define USBHSCORE_DOEPCTL12_USBACTEP_Min (0x0UL)   /*!< Min enumerator value of USBACTEP field.                              */
94597   #define USBHSCORE_DOEPCTL12_USBACTEP_Max (0x1UL)   /*!< Max enumerator value of USBACTEP field.                              */
94598   #define USBHSCORE_DOEPCTL12_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                     */
94599   #define USBHSCORE_DOEPCTL12_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                      */
94600 
94601 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
94602   #define USBHSCORE_DOEPCTL12_DPID_Pos (16UL)        /*!< Position of DPID field.                                              */
94603   #define USBHSCORE_DOEPCTL12_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL12_DPID_Pos) /*!< Bit mask of DPID field.                    */
94604   #define USBHSCORE_DOEPCTL12_DPID_Min (0x0UL)       /*!< Min enumerator value of DPID field.                                  */
94605   #define USBHSCORE_DOEPCTL12_DPID_Max (0x1UL)       /*!< Max enumerator value of DPID field.                                  */
94606   #define USBHSCORE_DOEPCTL12_DPID_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94607   #define USBHSCORE_DOEPCTL12_DPID_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94608 
94609 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
94610   #define USBHSCORE_DOEPCTL12_NAKSTS_Pos (17UL)      /*!< Position of NAKSTS field.                                            */
94611   #define USBHSCORE_DOEPCTL12_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL12_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.              */
94612   #define USBHSCORE_DOEPCTL12_NAKSTS_Min (0x0UL)     /*!< Min enumerator value of NAKSTS field.                                */
94613   #define USBHSCORE_DOEPCTL12_NAKSTS_Max (0x1UL)     /*!< Max enumerator value of NAKSTS field.                                */
94614   #define USBHSCORE_DOEPCTL12_NAKSTS_NONNAK (0x0UL)  /*!< (unspecified)                                                        */
94615   #define USBHSCORE_DOEPCTL12_NAKSTS_NAK (0x1UL)     /*!< (unspecified)                                                        */
94616 
94617 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
94618   #define USBHSCORE_DOEPCTL12_EPTYPE_Pos (18UL)      /*!< Position of EPTYPE field.                                            */
94619   #define USBHSCORE_DOEPCTL12_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL12_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.              */
94620   #define USBHSCORE_DOEPCTL12_EPTYPE_Min (0x0UL)     /*!< Min enumerator value of EPTYPE field.                                */
94621   #define USBHSCORE_DOEPCTL12_EPTYPE_Max (0x3UL)     /*!< Max enumerator value of EPTYPE field.                                */
94622   #define USBHSCORE_DOEPCTL12_EPTYPE_CONTROL (0x0UL) /*!< (unspecified)                                                        */
94623   #define USBHSCORE_DOEPCTL12_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                    */
94624   #define USBHSCORE_DOEPCTL12_EPTYPE_BULK (0x2UL)    /*!< (unspecified)                                                        */
94625   #define USBHSCORE_DOEPCTL12_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                      */
94626 
94627 /* STALL @Bit 21 : STALL Handshake (Stall) */
94628   #define USBHSCORE_DOEPCTL12_STALL_Pos (21UL)       /*!< Position of STALL field.                                             */
94629   #define USBHSCORE_DOEPCTL12_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL12_STALL_Pos) /*!< Bit mask of STALL field.                 */
94630   #define USBHSCORE_DOEPCTL12_STALL_Min (0x0UL)      /*!< Min enumerator value of STALL field.                                 */
94631   #define USBHSCORE_DOEPCTL12_STALL_Max (0x1UL)      /*!< Max enumerator value of STALL field.                                 */
94632   #define USBHSCORE_DOEPCTL12_STALL_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94633   #define USBHSCORE_DOEPCTL12_STALL_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94634 
94635 /* CNAK @Bit 26 : Clear NAK (CNAK) */
94636   #define USBHSCORE_DOEPCTL12_CNAK_Pos (26UL)        /*!< Position of CNAK field.                                              */
94637   #define USBHSCORE_DOEPCTL12_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL12_CNAK_Pos) /*!< Bit mask of CNAK field.                    */
94638   #define USBHSCORE_DOEPCTL12_CNAK_Min (0x0UL)       /*!< Min enumerator value of CNAK field.                                  */
94639   #define USBHSCORE_DOEPCTL12_CNAK_Max (0x1UL)       /*!< Max enumerator value of CNAK field.                                  */
94640   #define USBHSCORE_DOEPCTL12_CNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94641   #define USBHSCORE_DOEPCTL12_CNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94642 
94643 /* SNAK @Bit 27 : Set NAK (SNAK) */
94644   #define USBHSCORE_DOEPCTL12_SNAK_Pos (27UL)        /*!< Position of SNAK field.                                              */
94645   #define USBHSCORE_DOEPCTL12_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL12_SNAK_Pos) /*!< Bit mask of SNAK field.                    */
94646   #define USBHSCORE_DOEPCTL12_SNAK_Min (0x0UL)       /*!< Min enumerator value of SNAK field.                                  */
94647   #define USBHSCORE_DOEPCTL12_SNAK_Max (0x1UL)       /*!< Max enumerator value of SNAK field.                                  */
94648   #define USBHSCORE_DOEPCTL12_SNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94649   #define USBHSCORE_DOEPCTL12_SNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94650 
94651 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
94652   #define USBHSCORE_DOEPCTL12_SETD0PID_Pos (28UL)    /*!< Position of SETD0PID field.                                          */
94653   #define USBHSCORE_DOEPCTL12_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL12_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.        */
94654   #define USBHSCORE_DOEPCTL12_SETD0PID_Min (0x0UL)   /*!< Min enumerator value of SETD0PID field.                              */
94655   #define USBHSCORE_DOEPCTL12_SETD0PID_Max (0x1UL)   /*!< Max enumerator value of SETD0PID field.                              */
94656   #define USBHSCORE_DOEPCTL12_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
94657   #define USBHSCORE_DOEPCTL12_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
94658 
94659 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
94660   #define USBHSCORE_DOEPCTL12_SETD1PID_Pos (29UL)    /*!< Position of SETD1PID field.                                          */
94661   #define USBHSCORE_DOEPCTL12_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL12_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.        */
94662   #define USBHSCORE_DOEPCTL12_SETD1PID_Min (0x0UL)   /*!< Min enumerator value of SETD1PID field.                              */
94663   #define USBHSCORE_DOEPCTL12_SETD1PID_Max (0x1UL)   /*!< Max enumerator value of SETD1PID field.                              */
94664   #define USBHSCORE_DOEPCTL12_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
94665   #define USBHSCORE_DOEPCTL12_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
94666 
94667 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
94668   #define USBHSCORE_DOEPCTL12_EPDIS_Pos (30UL)       /*!< Position of EPDIS field.                                             */
94669   #define USBHSCORE_DOEPCTL12_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL12_EPDIS_Pos) /*!< Bit mask of EPDIS field.                 */
94670   #define USBHSCORE_DOEPCTL12_EPDIS_Min (0x0UL)      /*!< Min enumerator value of EPDIS field.                                 */
94671   #define USBHSCORE_DOEPCTL12_EPDIS_Max (0x1UL)      /*!< Max enumerator value of EPDIS field.                                 */
94672   #define USBHSCORE_DOEPCTL12_EPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94673   #define USBHSCORE_DOEPCTL12_EPDIS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94674 
94675 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
94676   #define USBHSCORE_DOEPCTL12_EPENA_Pos (31UL)       /*!< Position of EPENA field.                                             */
94677   #define USBHSCORE_DOEPCTL12_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL12_EPENA_Pos) /*!< Bit mask of EPENA field.                 */
94678   #define USBHSCORE_DOEPCTL12_EPENA_Min (0x0UL)      /*!< Min enumerator value of EPENA field.                                 */
94679   #define USBHSCORE_DOEPCTL12_EPENA_Max (0x1UL)      /*!< Max enumerator value of EPENA field.                                 */
94680   #define USBHSCORE_DOEPCTL12_EPENA_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94681   #define USBHSCORE_DOEPCTL12_EPENA_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94682 
94683 
94684 /* USBHSCORE_DOEPINT12: Device OUT Endpoint 12 Interrupt Register */
94685   #define USBHSCORE_DOEPINT12_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT12 register.                                */
94686 
94687 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
94688   #define USBHSCORE_DOEPINT12_XFERCOMPL_Pos (0UL)    /*!< Position of XFERCOMPL field.                                         */
94689   #define USBHSCORE_DOEPINT12_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT12_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.     */
94690   #define USBHSCORE_DOEPINT12_XFERCOMPL_Min (0x0UL)  /*!< Min enumerator value of XFERCOMPL field.                             */
94691   #define USBHSCORE_DOEPINT12_XFERCOMPL_Max (0x1UL)  /*!< Max enumerator value of XFERCOMPL field.                             */
94692   #define USBHSCORE_DOEPINT12_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
94693   #define USBHSCORE_DOEPINT12_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
94694 
94695 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
94696   #define USBHSCORE_DOEPINT12_EPDISBLD_Pos (1UL)     /*!< Position of EPDISBLD field.                                          */
94697   #define USBHSCORE_DOEPINT12_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT12_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.        */
94698   #define USBHSCORE_DOEPINT12_EPDISBLD_Min (0x0UL)   /*!< Min enumerator value of EPDISBLD field.                              */
94699   #define USBHSCORE_DOEPINT12_EPDISBLD_Max (0x1UL)   /*!< Max enumerator value of EPDISBLD field.                              */
94700   #define USBHSCORE_DOEPINT12_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94701   #define USBHSCORE_DOEPINT12_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94702 
94703 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
94704   #define USBHSCORE_DOEPINT12_AHBERR_Pos (2UL)       /*!< Position of AHBERR field.                                            */
94705   #define USBHSCORE_DOEPINT12_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT12_AHBERR_Pos) /*!< Bit mask of AHBERR field.              */
94706   #define USBHSCORE_DOEPINT12_AHBERR_Min (0x0UL)     /*!< Min enumerator value of AHBERR field.                                */
94707   #define USBHSCORE_DOEPINT12_AHBERR_Max (0x1UL)     /*!< Max enumerator value of AHBERR field.                                */
94708   #define USBHSCORE_DOEPINT12_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
94709   #define USBHSCORE_DOEPINT12_AHBERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
94710 
94711 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
94712   #define USBHSCORE_DOEPINT12_SETUP_Pos (3UL)        /*!< Position of SETUP field.                                             */
94713   #define USBHSCORE_DOEPINT12_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT12_SETUP_Pos) /*!< Bit mask of SETUP field.                 */
94714   #define USBHSCORE_DOEPINT12_SETUP_Min (0x0UL)      /*!< Min enumerator value of SETUP field.                                 */
94715   #define USBHSCORE_DOEPINT12_SETUP_Max (0x1UL)      /*!< Max enumerator value of SETUP field.                                 */
94716   #define USBHSCORE_DOEPINT12_SETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94717   #define USBHSCORE_DOEPINT12_SETUP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94718 
94719 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
94720   #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Pos (4UL)  /*!< Position of OUTTKNEPDIS field.                                       */
94721   #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT12_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS
94722                                                                             field.*/
94723   #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                          */
94724   #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                          */
94725   #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
94726   #define USBHSCORE_DOEPINT12_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
94727 
94728 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
94729   #define USBHSCORE_DOEPINT12_STSPHSERCVD_Pos (5UL)  /*!< Position of STSPHSERCVD field.                                       */
94730   #define USBHSCORE_DOEPINT12_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT12_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD
94731                                                                             field.*/
94732   #define USBHSCORE_DOEPINT12_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                          */
94733   #define USBHSCORE_DOEPINT12_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                          */
94734   #define USBHSCORE_DOEPINT12_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
94735   #define USBHSCORE_DOEPINT12_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
94736 
94737 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
94738   #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                  */
94739   #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT12_BACK2BACKSETUP_Pos) /*!< Bit mask of
94740                                                                             BACK2BACKSETUP field.*/
94741   #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                    */
94742   #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                    */
94743   #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                               */
94744   #define USBHSCORE_DOEPINT12_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
94745 
94746 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
94747   #define USBHSCORE_DOEPINT12_OUTPKTERR_Pos (8UL)    /*!< Position of OUTPKTERR field.                                         */
94748   #define USBHSCORE_DOEPINT12_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT12_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.     */
94749   #define USBHSCORE_DOEPINT12_OUTPKTERR_Min (0x0UL)  /*!< Min enumerator value of OUTPKTERR field.                             */
94750   #define USBHSCORE_DOEPINT12_OUTPKTERR_Max (0x1UL)  /*!< Max enumerator value of OUTPKTERR field.                             */
94751   #define USBHSCORE_DOEPINT12_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
94752   #define USBHSCORE_DOEPINT12_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
94753 
94754 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
94755   #define USBHSCORE_DOEPINT12_BNAINTR_Pos (9UL)      /*!< Position of BNAINTR field.                                           */
94756   #define USBHSCORE_DOEPINT12_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT12_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.           */
94757   #define USBHSCORE_DOEPINT12_BNAINTR_Min (0x0UL)    /*!< Min enumerator value of BNAINTR field.                               */
94758   #define USBHSCORE_DOEPINT12_BNAINTR_Max (0x1UL)    /*!< Max enumerator value of BNAINTR field.                               */
94759   #define USBHSCORE_DOEPINT12_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
94760   #define USBHSCORE_DOEPINT12_BNAINTR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
94761 
94762 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
94763   #define USBHSCORE_DOEPINT12_PKTDRPSTS_Pos (11UL)   /*!< Position of PKTDRPSTS field.                                         */
94764   #define USBHSCORE_DOEPINT12_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT12_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.     */
94765   #define USBHSCORE_DOEPINT12_PKTDRPSTS_Min (0x0UL)  /*!< Min enumerator value of PKTDRPSTS field.                             */
94766   #define USBHSCORE_DOEPINT12_PKTDRPSTS_Max (0x1UL)  /*!< Max enumerator value of PKTDRPSTS field.                             */
94767   #define USBHSCORE_DOEPINT12_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
94768   #define USBHSCORE_DOEPINT12_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
94769 
94770 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
94771   #define USBHSCORE_DOEPINT12_BBLEERR_Pos (12UL)     /*!< Position of BBLEERR field.                                           */
94772   #define USBHSCORE_DOEPINT12_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT12_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.           */
94773   #define USBHSCORE_DOEPINT12_BBLEERR_Min (0x0UL)    /*!< Min enumerator value of BBLEERR field.                               */
94774   #define USBHSCORE_DOEPINT12_BBLEERR_Max (0x1UL)    /*!< Max enumerator value of BBLEERR field.                               */
94775   #define USBHSCORE_DOEPINT12_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
94776   #define USBHSCORE_DOEPINT12_BBLEERR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
94777 
94778 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
94779   #define USBHSCORE_DOEPINT12_NAKINTRPT_Pos (13UL)   /*!< Position of NAKINTRPT field.                                         */
94780   #define USBHSCORE_DOEPINT12_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT12_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.     */
94781   #define USBHSCORE_DOEPINT12_NAKINTRPT_Min (0x0UL)  /*!< Min enumerator value of NAKINTRPT field.                             */
94782   #define USBHSCORE_DOEPINT12_NAKINTRPT_Max (0x1UL)  /*!< Max enumerator value of NAKINTRPT field.                             */
94783   #define USBHSCORE_DOEPINT12_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
94784   #define USBHSCORE_DOEPINT12_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
94785 
94786 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
94787   #define USBHSCORE_DOEPINT12_NYETINTRPT_Pos (14UL)  /*!< Position of NYETINTRPT field.                                        */
94788   #define USBHSCORE_DOEPINT12_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT12_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.  */
94789   #define USBHSCORE_DOEPINT12_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field.                            */
94790   #define USBHSCORE_DOEPINT12_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field.                            */
94791   #define USBHSCORE_DOEPINT12_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
94792   #define USBHSCORE_DOEPINT12_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
94793 
94794 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
94795   #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field.                                       */
94796   #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT12_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD
94797                                                                             field.*/
94798   #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                          */
94799   #define USBHSCORE_DOEPINT12_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                          */
94800   #define USBHSCORE_DOEPINT12_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                  */
94801   #define USBHSCORE_DOEPINT12_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                      */
94802 
94803 
94804 /* USBHSCORE_DOEPTSIZ12: Device OUT Endpoint 12 Transfer Size Register */
94805   #define USBHSCORE_DOEPTSIZ12_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ12 register.                              */
94806 
94807 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
94808   #define USBHSCORE_DOEPTSIZ12_XFERSIZE_Pos (0UL)    /*!< Position of XFERSIZE field.                                          */
94809   #define USBHSCORE_DOEPTSIZ12_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ12_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.  */
94810 
94811 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
94812   #define USBHSCORE_DOEPTSIZ12_PKTCNT_Pos (19UL)     /*!< Position of PKTCNT field.                                            */
94813   #define USBHSCORE_DOEPTSIZ12_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ12_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.          */
94814 
94815 /* RXDPID @Bits 29..30 : RxDPID */
94816   #define USBHSCORE_DOEPTSIZ12_RXDPID_Pos (29UL)     /*!< Position of RXDPID field.                                            */
94817   #define USBHSCORE_DOEPTSIZ12_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ12_RXDPID_Pos) /*!< Bit mask of RXDPID field.            */
94818   #define USBHSCORE_DOEPTSIZ12_RXDPID_Min (0x0UL)    /*!< Min enumerator value of RXDPID field.                                */
94819   #define USBHSCORE_DOEPTSIZ12_RXDPID_Max (0x3UL)    /*!< Max enumerator value of RXDPID field.                                */
94820   #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA0 (0x0UL)  /*!< (unspecified)                                                        */
94821   #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                  */
94822   #define USBHSCORE_DOEPTSIZ12_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                  */
94823   #define USBHSCORE_DOEPTSIZ12_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                  */
94824 
94825 
94826 /* USBHSCORE_DOEPDMA12: Device OUT Endpoint 12 DMA Address Register */
94827   #define USBHSCORE_DOEPDMA12_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA12 register.                                */
94828 
94829 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
94830   #define USBHSCORE_DOEPDMA12_DMAADDR_Pos (0UL)      /*!< Position of DMAADDR field.                                           */
94831   #define USBHSCORE_DOEPDMA12_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA12_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.    */
94832 
94833 
94834 /* USBHSCORE_DOEPCTL13: Device Control OUT Endpoint 13 Control Register */
94835   #define USBHSCORE_DOEPCTL13_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL13 register.                                */
94836 
94837 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
94838   #define USBHSCORE_DOEPCTL13_MPS_Pos (0UL)          /*!< Position of MPS field.                                               */
94839   #define USBHSCORE_DOEPCTL13_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL13_MPS_Pos) /*!< Bit mask of MPS field.                     */
94840 
94841 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
94842   #define USBHSCORE_DOEPCTL13_USBACTEP_Pos (15UL)    /*!< Position of USBACTEP field.                                          */
94843   #define USBHSCORE_DOEPCTL13_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL13_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.        */
94844   #define USBHSCORE_DOEPCTL13_USBACTEP_Min (0x0UL)   /*!< Min enumerator value of USBACTEP field.                              */
94845   #define USBHSCORE_DOEPCTL13_USBACTEP_Max (0x1UL)   /*!< Max enumerator value of USBACTEP field.                              */
94846   #define USBHSCORE_DOEPCTL13_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                     */
94847   #define USBHSCORE_DOEPCTL13_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                      */
94848 
94849 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
94850   #define USBHSCORE_DOEPCTL13_DPID_Pos (16UL)        /*!< Position of DPID field.                                              */
94851   #define USBHSCORE_DOEPCTL13_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL13_DPID_Pos) /*!< Bit mask of DPID field.                    */
94852   #define USBHSCORE_DOEPCTL13_DPID_Min (0x0UL)       /*!< Min enumerator value of DPID field.                                  */
94853   #define USBHSCORE_DOEPCTL13_DPID_Max (0x1UL)       /*!< Max enumerator value of DPID field.                                  */
94854   #define USBHSCORE_DOEPCTL13_DPID_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94855   #define USBHSCORE_DOEPCTL13_DPID_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94856 
94857 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
94858   #define USBHSCORE_DOEPCTL13_NAKSTS_Pos (17UL)      /*!< Position of NAKSTS field.                                            */
94859   #define USBHSCORE_DOEPCTL13_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL13_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.              */
94860   #define USBHSCORE_DOEPCTL13_NAKSTS_Min (0x0UL)     /*!< Min enumerator value of NAKSTS field.                                */
94861   #define USBHSCORE_DOEPCTL13_NAKSTS_Max (0x1UL)     /*!< Max enumerator value of NAKSTS field.                                */
94862   #define USBHSCORE_DOEPCTL13_NAKSTS_NONNAK (0x0UL)  /*!< (unspecified)                                                        */
94863   #define USBHSCORE_DOEPCTL13_NAKSTS_NAK (0x1UL)     /*!< (unspecified)                                                        */
94864 
94865 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
94866   #define USBHSCORE_DOEPCTL13_EPTYPE_Pos (18UL)      /*!< Position of EPTYPE field.                                            */
94867   #define USBHSCORE_DOEPCTL13_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL13_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.              */
94868   #define USBHSCORE_DOEPCTL13_EPTYPE_Min (0x0UL)     /*!< Min enumerator value of EPTYPE field.                                */
94869   #define USBHSCORE_DOEPCTL13_EPTYPE_Max (0x3UL)     /*!< Max enumerator value of EPTYPE field.                                */
94870   #define USBHSCORE_DOEPCTL13_EPTYPE_CONTROL (0x0UL) /*!< (unspecified)                                                        */
94871   #define USBHSCORE_DOEPCTL13_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                    */
94872   #define USBHSCORE_DOEPCTL13_EPTYPE_BULK (0x2UL)    /*!< (unspecified)                                                        */
94873   #define USBHSCORE_DOEPCTL13_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                      */
94874 
94875 /* STALL @Bit 21 : STALL Handshake (Stall) */
94876   #define USBHSCORE_DOEPCTL13_STALL_Pos (21UL)       /*!< Position of STALL field.                                             */
94877   #define USBHSCORE_DOEPCTL13_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL13_STALL_Pos) /*!< Bit mask of STALL field.                 */
94878   #define USBHSCORE_DOEPCTL13_STALL_Min (0x0UL)      /*!< Min enumerator value of STALL field.                                 */
94879   #define USBHSCORE_DOEPCTL13_STALL_Max (0x1UL)      /*!< Max enumerator value of STALL field.                                 */
94880   #define USBHSCORE_DOEPCTL13_STALL_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94881   #define USBHSCORE_DOEPCTL13_STALL_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94882 
94883 /* CNAK @Bit 26 : Clear NAK (CNAK) */
94884   #define USBHSCORE_DOEPCTL13_CNAK_Pos (26UL)        /*!< Position of CNAK field.                                              */
94885   #define USBHSCORE_DOEPCTL13_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL13_CNAK_Pos) /*!< Bit mask of CNAK field.                    */
94886   #define USBHSCORE_DOEPCTL13_CNAK_Min (0x0UL)       /*!< Min enumerator value of CNAK field.                                  */
94887   #define USBHSCORE_DOEPCTL13_CNAK_Max (0x1UL)       /*!< Max enumerator value of CNAK field.                                  */
94888   #define USBHSCORE_DOEPCTL13_CNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94889   #define USBHSCORE_DOEPCTL13_CNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94890 
94891 /* SNAK @Bit 27 : Set NAK (SNAK) */
94892   #define USBHSCORE_DOEPCTL13_SNAK_Pos (27UL)        /*!< Position of SNAK field.                                              */
94893   #define USBHSCORE_DOEPCTL13_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL13_SNAK_Pos) /*!< Bit mask of SNAK field.                    */
94894   #define USBHSCORE_DOEPCTL13_SNAK_Min (0x0UL)       /*!< Min enumerator value of SNAK field.                                  */
94895   #define USBHSCORE_DOEPCTL13_SNAK_Max (0x1UL)       /*!< Max enumerator value of SNAK field.                                  */
94896   #define USBHSCORE_DOEPCTL13_SNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
94897   #define USBHSCORE_DOEPCTL13_SNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
94898 
94899 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
94900   #define USBHSCORE_DOEPCTL13_SETD0PID_Pos (28UL)    /*!< Position of SETD0PID field.                                          */
94901   #define USBHSCORE_DOEPCTL13_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL13_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.        */
94902   #define USBHSCORE_DOEPCTL13_SETD0PID_Min (0x0UL)   /*!< Min enumerator value of SETD0PID field.                              */
94903   #define USBHSCORE_DOEPCTL13_SETD0PID_Max (0x1UL)   /*!< Max enumerator value of SETD0PID field.                              */
94904   #define USBHSCORE_DOEPCTL13_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
94905   #define USBHSCORE_DOEPCTL13_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
94906 
94907 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
94908   #define USBHSCORE_DOEPCTL13_SETD1PID_Pos (29UL)    /*!< Position of SETD1PID field.                                          */
94909   #define USBHSCORE_DOEPCTL13_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL13_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.        */
94910   #define USBHSCORE_DOEPCTL13_SETD1PID_Min (0x0UL)   /*!< Min enumerator value of SETD1PID field.                              */
94911   #define USBHSCORE_DOEPCTL13_SETD1PID_Max (0x1UL)   /*!< Max enumerator value of SETD1PID field.                              */
94912   #define USBHSCORE_DOEPCTL13_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
94913   #define USBHSCORE_DOEPCTL13_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
94914 
94915 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
94916   #define USBHSCORE_DOEPCTL13_EPDIS_Pos (30UL)       /*!< Position of EPDIS field.                                             */
94917   #define USBHSCORE_DOEPCTL13_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL13_EPDIS_Pos) /*!< Bit mask of EPDIS field.                 */
94918   #define USBHSCORE_DOEPCTL13_EPDIS_Min (0x0UL)      /*!< Min enumerator value of EPDIS field.                                 */
94919   #define USBHSCORE_DOEPCTL13_EPDIS_Max (0x1UL)      /*!< Max enumerator value of EPDIS field.                                 */
94920   #define USBHSCORE_DOEPCTL13_EPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94921   #define USBHSCORE_DOEPCTL13_EPDIS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94922 
94923 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
94924   #define USBHSCORE_DOEPCTL13_EPENA_Pos (31UL)       /*!< Position of EPENA field.                                             */
94925   #define USBHSCORE_DOEPCTL13_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL13_EPENA_Pos) /*!< Bit mask of EPENA field.                 */
94926   #define USBHSCORE_DOEPCTL13_EPENA_Min (0x0UL)      /*!< Min enumerator value of EPENA field.                                 */
94927   #define USBHSCORE_DOEPCTL13_EPENA_Max (0x1UL)      /*!< Max enumerator value of EPENA field.                                 */
94928   #define USBHSCORE_DOEPCTL13_EPENA_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94929   #define USBHSCORE_DOEPCTL13_EPENA_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94930 
94931 
94932 /* USBHSCORE_DOEPINT13: Device OUT Endpoint 13 Interrupt Register */
94933   #define USBHSCORE_DOEPINT13_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT13 register.                                */
94934 
94935 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
94936   #define USBHSCORE_DOEPINT13_XFERCOMPL_Pos (0UL)    /*!< Position of XFERCOMPL field.                                         */
94937   #define USBHSCORE_DOEPINT13_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT13_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.     */
94938   #define USBHSCORE_DOEPINT13_XFERCOMPL_Min (0x0UL)  /*!< Min enumerator value of XFERCOMPL field.                             */
94939   #define USBHSCORE_DOEPINT13_XFERCOMPL_Max (0x1UL)  /*!< Max enumerator value of XFERCOMPL field.                             */
94940   #define USBHSCORE_DOEPINT13_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
94941   #define USBHSCORE_DOEPINT13_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
94942 
94943 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
94944   #define USBHSCORE_DOEPINT13_EPDISBLD_Pos (1UL)     /*!< Position of EPDISBLD field.                                          */
94945   #define USBHSCORE_DOEPINT13_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT13_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.        */
94946   #define USBHSCORE_DOEPINT13_EPDISBLD_Min (0x0UL)   /*!< Min enumerator value of EPDISBLD field.                              */
94947   #define USBHSCORE_DOEPINT13_EPDISBLD_Max (0x1UL)   /*!< Max enumerator value of EPDISBLD field.                              */
94948   #define USBHSCORE_DOEPINT13_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
94949   #define USBHSCORE_DOEPINT13_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
94950 
94951 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
94952   #define USBHSCORE_DOEPINT13_AHBERR_Pos (2UL)       /*!< Position of AHBERR field.                                            */
94953   #define USBHSCORE_DOEPINT13_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT13_AHBERR_Pos) /*!< Bit mask of AHBERR field.              */
94954   #define USBHSCORE_DOEPINT13_AHBERR_Min (0x0UL)     /*!< Min enumerator value of AHBERR field.                                */
94955   #define USBHSCORE_DOEPINT13_AHBERR_Max (0x1UL)     /*!< Max enumerator value of AHBERR field.                                */
94956   #define USBHSCORE_DOEPINT13_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
94957   #define USBHSCORE_DOEPINT13_AHBERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
94958 
94959 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
94960   #define USBHSCORE_DOEPINT13_SETUP_Pos (3UL)        /*!< Position of SETUP field.                                             */
94961   #define USBHSCORE_DOEPINT13_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT13_SETUP_Pos) /*!< Bit mask of SETUP field.                 */
94962   #define USBHSCORE_DOEPINT13_SETUP_Min (0x0UL)      /*!< Min enumerator value of SETUP field.                                 */
94963   #define USBHSCORE_DOEPINT13_SETUP_Max (0x1UL)      /*!< Max enumerator value of SETUP field.                                 */
94964   #define USBHSCORE_DOEPINT13_SETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
94965   #define USBHSCORE_DOEPINT13_SETUP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
94966 
94967 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
94968   #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Pos (4UL)  /*!< Position of OUTTKNEPDIS field.                                       */
94969   #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT13_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS
94970                                                                             field.*/
94971   #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                          */
94972   #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                          */
94973   #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
94974   #define USBHSCORE_DOEPINT13_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
94975 
94976 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
94977   #define USBHSCORE_DOEPINT13_STSPHSERCVD_Pos (5UL)  /*!< Position of STSPHSERCVD field.                                       */
94978   #define USBHSCORE_DOEPINT13_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT13_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD
94979                                                                             field.*/
94980   #define USBHSCORE_DOEPINT13_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                          */
94981   #define USBHSCORE_DOEPINT13_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                          */
94982   #define USBHSCORE_DOEPINT13_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
94983   #define USBHSCORE_DOEPINT13_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
94984 
94985 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
94986   #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                  */
94987   #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT13_BACK2BACKSETUP_Pos) /*!< Bit mask of
94988                                                                             BACK2BACKSETUP field.*/
94989   #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                    */
94990   #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                    */
94991   #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                               */
94992   #define USBHSCORE_DOEPINT13_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
94993 
94994 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
94995   #define USBHSCORE_DOEPINT13_OUTPKTERR_Pos (8UL)    /*!< Position of OUTPKTERR field.                                         */
94996   #define USBHSCORE_DOEPINT13_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT13_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.     */
94997   #define USBHSCORE_DOEPINT13_OUTPKTERR_Min (0x0UL)  /*!< Min enumerator value of OUTPKTERR field.                             */
94998   #define USBHSCORE_DOEPINT13_OUTPKTERR_Max (0x1UL)  /*!< Max enumerator value of OUTPKTERR field.                             */
94999   #define USBHSCORE_DOEPINT13_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95000   #define USBHSCORE_DOEPINT13_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95001 
95002 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
95003   #define USBHSCORE_DOEPINT13_BNAINTR_Pos (9UL)      /*!< Position of BNAINTR field.                                           */
95004   #define USBHSCORE_DOEPINT13_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT13_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.           */
95005   #define USBHSCORE_DOEPINT13_BNAINTR_Min (0x0UL)    /*!< Min enumerator value of BNAINTR field.                               */
95006   #define USBHSCORE_DOEPINT13_BNAINTR_Max (0x1UL)    /*!< Max enumerator value of BNAINTR field.                               */
95007   #define USBHSCORE_DOEPINT13_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
95008   #define USBHSCORE_DOEPINT13_BNAINTR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
95009 
95010 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
95011   #define USBHSCORE_DOEPINT13_PKTDRPSTS_Pos (11UL)   /*!< Position of PKTDRPSTS field.                                         */
95012   #define USBHSCORE_DOEPINT13_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT13_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.     */
95013   #define USBHSCORE_DOEPINT13_PKTDRPSTS_Min (0x0UL)  /*!< Min enumerator value of PKTDRPSTS field.                             */
95014   #define USBHSCORE_DOEPINT13_PKTDRPSTS_Max (0x1UL)  /*!< Max enumerator value of PKTDRPSTS field.                             */
95015   #define USBHSCORE_DOEPINT13_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95016   #define USBHSCORE_DOEPINT13_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95017 
95018 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
95019   #define USBHSCORE_DOEPINT13_BBLEERR_Pos (12UL)     /*!< Position of BBLEERR field.                                           */
95020   #define USBHSCORE_DOEPINT13_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT13_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.           */
95021   #define USBHSCORE_DOEPINT13_BBLEERR_Min (0x0UL)    /*!< Min enumerator value of BBLEERR field.                               */
95022   #define USBHSCORE_DOEPINT13_BBLEERR_Max (0x1UL)    /*!< Max enumerator value of BBLEERR field.                               */
95023   #define USBHSCORE_DOEPINT13_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
95024   #define USBHSCORE_DOEPINT13_BBLEERR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
95025 
95026 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
95027   #define USBHSCORE_DOEPINT13_NAKINTRPT_Pos (13UL)   /*!< Position of NAKINTRPT field.                                         */
95028   #define USBHSCORE_DOEPINT13_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT13_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.     */
95029   #define USBHSCORE_DOEPINT13_NAKINTRPT_Min (0x0UL)  /*!< Min enumerator value of NAKINTRPT field.                             */
95030   #define USBHSCORE_DOEPINT13_NAKINTRPT_Max (0x1UL)  /*!< Max enumerator value of NAKINTRPT field.                             */
95031   #define USBHSCORE_DOEPINT13_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95032   #define USBHSCORE_DOEPINT13_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95033 
95034 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
95035   #define USBHSCORE_DOEPINT13_NYETINTRPT_Pos (14UL)  /*!< Position of NYETINTRPT field.                                        */
95036   #define USBHSCORE_DOEPINT13_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT13_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.  */
95037   #define USBHSCORE_DOEPINT13_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field.                            */
95038   #define USBHSCORE_DOEPINT13_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field.                            */
95039   #define USBHSCORE_DOEPINT13_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
95040   #define USBHSCORE_DOEPINT13_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
95041 
95042 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
95043   #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field.                                       */
95044   #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT13_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD
95045                                                                             field.*/
95046   #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                          */
95047   #define USBHSCORE_DOEPINT13_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                          */
95048   #define USBHSCORE_DOEPINT13_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                  */
95049   #define USBHSCORE_DOEPINT13_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                      */
95050 
95051 
95052 /* USBHSCORE_DOEPTSIZ13: Device OUT Endpoint 13 Transfer Size Register */
95053   #define USBHSCORE_DOEPTSIZ13_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ13 register.                              */
95054 
95055 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
95056   #define USBHSCORE_DOEPTSIZ13_XFERSIZE_Pos (0UL)    /*!< Position of XFERSIZE field.                                          */
95057   #define USBHSCORE_DOEPTSIZ13_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ13_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.  */
95058 
95059 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
95060   #define USBHSCORE_DOEPTSIZ13_PKTCNT_Pos (19UL)     /*!< Position of PKTCNT field.                                            */
95061   #define USBHSCORE_DOEPTSIZ13_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ13_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.          */
95062 
95063 /* RXDPID @Bits 29..30 : RxDPID */
95064   #define USBHSCORE_DOEPTSIZ13_RXDPID_Pos (29UL)     /*!< Position of RXDPID field.                                            */
95065   #define USBHSCORE_DOEPTSIZ13_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ13_RXDPID_Pos) /*!< Bit mask of RXDPID field.            */
95066   #define USBHSCORE_DOEPTSIZ13_RXDPID_Min (0x0UL)    /*!< Min enumerator value of RXDPID field.                                */
95067   #define USBHSCORE_DOEPTSIZ13_RXDPID_Max (0x3UL)    /*!< Max enumerator value of RXDPID field.                                */
95068   #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA0 (0x0UL)  /*!< (unspecified)                                                        */
95069   #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                  */
95070   #define USBHSCORE_DOEPTSIZ13_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                  */
95071   #define USBHSCORE_DOEPTSIZ13_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                  */
95072 
95073 
95074 /* USBHSCORE_DOEPDMA13: Device OUT Endpoint 13 DMA Address Register */
95075   #define USBHSCORE_DOEPDMA13_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA13 register.                                */
95076 
95077 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
95078   #define USBHSCORE_DOEPDMA13_DMAADDR_Pos (0UL)      /*!< Position of DMAADDR field.                                           */
95079   #define USBHSCORE_DOEPDMA13_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA13_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.    */
95080 
95081 
95082 /* USBHSCORE_DOEPCTL14: Device Control OUT Endpoint 14 Control Register */
95083   #define USBHSCORE_DOEPCTL14_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL14 register.                                */
95084 
95085 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
95086   #define USBHSCORE_DOEPCTL14_MPS_Pos (0UL)          /*!< Position of MPS field.                                               */
95087   #define USBHSCORE_DOEPCTL14_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL14_MPS_Pos) /*!< Bit mask of MPS field.                     */
95088 
95089 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
95090   #define USBHSCORE_DOEPCTL14_USBACTEP_Pos (15UL)    /*!< Position of USBACTEP field.                                          */
95091   #define USBHSCORE_DOEPCTL14_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL14_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.        */
95092   #define USBHSCORE_DOEPCTL14_USBACTEP_Min (0x0UL)   /*!< Min enumerator value of USBACTEP field.                              */
95093   #define USBHSCORE_DOEPCTL14_USBACTEP_Max (0x1UL)   /*!< Max enumerator value of USBACTEP field.                              */
95094   #define USBHSCORE_DOEPCTL14_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                     */
95095   #define USBHSCORE_DOEPCTL14_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                      */
95096 
95097 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
95098   #define USBHSCORE_DOEPCTL14_DPID_Pos (16UL)        /*!< Position of DPID field.                                              */
95099   #define USBHSCORE_DOEPCTL14_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL14_DPID_Pos) /*!< Bit mask of DPID field.                    */
95100   #define USBHSCORE_DOEPCTL14_DPID_Min (0x0UL)       /*!< Min enumerator value of DPID field.                                  */
95101   #define USBHSCORE_DOEPCTL14_DPID_Max (0x1UL)       /*!< Max enumerator value of DPID field.                                  */
95102   #define USBHSCORE_DOEPCTL14_DPID_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
95103   #define USBHSCORE_DOEPCTL14_DPID_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
95104 
95105 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
95106   #define USBHSCORE_DOEPCTL14_NAKSTS_Pos (17UL)      /*!< Position of NAKSTS field.                                            */
95107   #define USBHSCORE_DOEPCTL14_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL14_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.              */
95108   #define USBHSCORE_DOEPCTL14_NAKSTS_Min (0x0UL)     /*!< Min enumerator value of NAKSTS field.                                */
95109   #define USBHSCORE_DOEPCTL14_NAKSTS_Max (0x1UL)     /*!< Max enumerator value of NAKSTS field.                                */
95110   #define USBHSCORE_DOEPCTL14_NAKSTS_NONNAK (0x0UL)  /*!< (unspecified)                                                        */
95111   #define USBHSCORE_DOEPCTL14_NAKSTS_NAK (0x1UL)     /*!< (unspecified)                                                        */
95112 
95113 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
95114   #define USBHSCORE_DOEPCTL14_EPTYPE_Pos (18UL)      /*!< Position of EPTYPE field.                                            */
95115   #define USBHSCORE_DOEPCTL14_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL14_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.              */
95116   #define USBHSCORE_DOEPCTL14_EPTYPE_Min (0x0UL)     /*!< Min enumerator value of EPTYPE field.                                */
95117   #define USBHSCORE_DOEPCTL14_EPTYPE_Max (0x3UL)     /*!< Max enumerator value of EPTYPE field.                                */
95118   #define USBHSCORE_DOEPCTL14_EPTYPE_CONTROL (0x0UL) /*!< (unspecified)                                                        */
95119   #define USBHSCORE_DOEPCTL14_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                    */
95120   #define USBHSCORE_DOEPCTL14_EPTYPE_BULK (0x2UL)    /*!< (unspecified)                                                        */
95121   #define USBHSCORE_DOEPCTL14_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                      */
95122 
95123 /* STALL @Bit 21 : STALL Handshake (Stall) */
95124   #define USBHSCORE_DOEPCTL14_STALL_Pos (21UL)       /*!< Position of STALL field.                                             */
95125   #define USBHSCORE_DOEPCTL14_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL14_STALL_Pos) /*!< Bit mask of STALL field.                 */
95126   #define USBHSCORE_DOEPCTL14_STALL_Min (0x0UL)      /*!< Min enumerator value of STALL field.                                 */
95127   #define USBHSCORE_DOEPCTL14_STALL_Max (0x1UL)      /*!< Max enumerator value of STALL field.                                 */
95128   #define USBHSCORE_DOEPCTL14_STALL_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
95129   #define USBHSCORE_DOEPCTL14_STALL_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
95130 
95131 /* CNAK @Bit 26 : Clear NAK (CNAK) */
95132   #define USBHSCORE_DOEPCTL14_CNAK_Pos (26UL)        /*!< Position of CNAK field.                                              */
95133   #define USBHSCORE_DOEPCTL14_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL14_CNAK_Pos) /*!< Bit mask of CNAK field.                    */
95134   #define USBHSCORE_DOEPCTL14_CNAK_Min (0x0UL)       /*!< Min enumerator value of CNAK field.                                  */
95135   #define USBHSCORE_DOEPCTL14_CNAK_Max (0x1UL)       /*!< Max enumerator value of CNAK field.                                  */
95136   #define USBHSCORE_DOEPCTL14_CNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
95137   #define USBHSCORE_DOEPCTL14_CNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
95138 
95139 /* SNAK @Bit 27 : Set NAK (SNAK) */
95140   #define USBHSCORE_DOEPCTL14_SNAK_Pos (27UL)        /*!< Position of SNAK field.                                              */
95141   #define USBHSCORE_DOEPCTL14_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL14_SNAK_Pos) /*!< Bit mask of SNAK field.                    */
95142   #define USBHSCORE_DOEPCTL14_SNAK_Min (0x0UL)       /*!< Min enumerator value of SNAK field.                                  */
95143   #define USBHSCORE_DOEPCTL14_SNAK_Max (0x1UL)       /*!< Max enumerator value of SNAK field.                                  */
95144   #define USBHSCORE_DOEPCTL14_SNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
95145   #define USBHSCORE_DOEPCTL14_SNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
95146 
95147 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
95148   #define USBHSCORE_DOEPCTL14_SETD0PID_Pos (28UL)    /*!< Position of SETD0PID field.                                          */
95149   #define USBHSCORE_DOEPCTL14_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL14_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.        */
95150   #define USBHSCORE_DOEPCTL14_SETD0PID_Min (0x0UL)   /*!< Min enumerator value of SETD0PID field.                              */
95151   #define USBHSCORE_DOEPCTL14_SETD0PID_Max (0x1UL)   /*!< Max enumerator value of SETD0PID field.                              */
95152   #define USBHSCORE_DOEPCTL14_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
95153   #define USBHSCORE_DOEPCTL14_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
95154 
95155 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
95156   #define USBHSCORE_DOEPCTL14_SETD1PID_Pos (29UL)    /*!< Position of SETD1PID field.                                          */
95157   #define USBHSCORE_DOEPCTL14_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL14_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.        */
95158   #define USBHSCORE_DOEPCTL14_SETD1PID_Min (0x0UL)   /*!< Min enumerator value of SETD1PID field.                              */
95159   #define USBHSCORE_DOEPCTL14_SETD1PID_Max (0x1UL)   /*!< Max enumerator value of SETD1PID field.                              */
95160   #define USBHSCORE_DOEPCTL14_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
95161   #define USBHSCORE_DOEPCTL14_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
95162 
95163 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
95164   #define USBHSCORE_DOEPCTL14_EPDIS_Pos (30UL)       /*!< Position of EPDIS field.                                             */
95165   #define USBHSCORE_DOEPCTL14_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL14_EPDIS_Pos) /*!< Bit mask of EPDIS field.                 */
95166   #define USBHSCORE_DOEPCTL14_EPDIS_Min (0x0UL)      /*!< Min enumerator value of EPDIS field.                                 */
95167   #define USBHSCORE_DOEPCTL14_EPDIS_Max (0x1UL)      /*!< Max enumerator value of EPDIS field.                                 */
95168   #define USBHSCORE_DOEPCTL14_EPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
95169   #define USBHSCORE_DOEPCTL14_EPDIS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
95170 
95171 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
95172   #define USBHSCORE_DOEPCTL14_EPENA_Pos (31UL)       /*!< Position of EPENA field.                                             */
95173   #define USBHSCORE_DOEPCTL14_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL14_EPENA_Pos) /*!< Bit mask of EPENA field.                 */
95174   #define USBHSCORE_DOEPCTL14_EPENA_Min (0x0UL)      /*!< Min enumerator value of EPENA field.                                 */
95175   #define USBHSCORE_DOEPCTL14_EPENA_Max (0x1UL)      /*!< Max enumerator value of EPENA field.                                 */
95176   #define USBHSCORE_DOEPCTL14_EPENA_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
95177   #define USBHSCORE_DOEPCTL14_EPENA_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
95178 
95179 
95180 /* USBHSCORE_DOEPINT14: Device OUT Endpoint 14 Interrupt Register */
95181   #define USBHSCORE_DOEPINT14_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT14 register.                                */
95182 
95183 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
95184   #define USBHSCORE_DOEPINT14_XFERCOMPL_Pos (0UL)    /*!< Position of XFERCOMPL field.                                         */
95185   #define USBHSCORE_DOEPINT14_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT14_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.     */
95186   #define USBHSCORE_DOEPINT14_XFERCOMPL_Min (0x0UL)  /*!< Min enumerator value of XFERCOMPL field.                             */
95187   #define USBHSCORE_DOEPINT14_XFERCOMPL_Max (0x1UL)  /*!< Max enumerator value of XFERCOMPL field.                             */
95188   #define USBHSCORE_DOEPINT14_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95189   #define USBHSCORE_DOEPINT14_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95190 
95191 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
95192   #define USBHSCORE_DOEPINT14_EPDISBLD_Pos (1UL)     /*!< Position of EPDISBLD field.                                          */
95193   #define USBHSCORE_DOEPINT14_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT14_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.        */
95194   #define USBHSCORE_DOEPINT14_EPDISBLD_Min (0x0UL)   /*!< Min enumerator value of EPDISBLD field.                              */
95195   #define USBHSCORE_DOEPINT14_EPDISBLD_Max (0x1UL)   /*!< Max enumerator value of EPDISBLD field.                              */
95196   #define USBHSCORE_DOEPINT14_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
95197   #define USBHSCORE_DOEPINT14_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
95198 
95199 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
95200   #define USBHSCORE_DOEPINT14_AHBERR_Pos (2UL)       /*!< Position of AHBERR field.                                            */
95201   #define USBHSCORE_DOEPINT14_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT14_AHBERR_Pos) /*!< Bit mask of AHBERR field.              */
95202   #define USBHSCORE_DOEPINT14_AHBERR_Min (0x0UL)     /*!< Min enumerator value of AHBERR field.                                */
95203   #define USBHSCORE_DOEPINT14_AHBERR_Max (0x1UL)     /*!< Max enumerator value of AHBERR field.                                */
95204   #define USBHSCORE_DOEPINT14_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
95205   #define USBHSCORE_DOEPINT14_AHBERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
95206 
95207 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
95208   #define USBHSCORE_DOEPINT14_SETUP_Pos (3UL)        /*!< Position of SETUP field.                                             */
95209   #define USBHSCORE_DOEPINT14_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT14_SETUP_Pos) /*!< Bit mask of SETUP field.                 */
95210   #define USBHSCORE_DOEPINT14_SETUP_Min (0x0UL)      /*!< Min enumerator value of SETUP field.                                 */
95211   #define USBHSCORE_DOEPINT14_SETUP_Max (0x1UL)      /*!< Max enumerator value of SETUP field.                                 */
95212   #define USBHSCORE_DOEPINT14_SETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
95213   #define USBHSCORE_DOEPINT14_SETUP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
95214 
95215 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
95216   #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Pos (4UL)  /*!< Position of OUTTKNEPDIS field.                                       */
95217   #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT14_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS
95218                                                                             field.*/
95219   #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                          */
95220   #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                          */
95221   #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
95222   #define USBHSCORE_DOEPINT14_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
95223 
95224 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
95225   #define USBHSCORE_DOEPINT14_STSPHSERCVD_Pos (5UL)  /*!< Position of STSPHSERCVD field.                                       */
95226   #define USBHSCORE_DOEPINT14_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT14_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD
95227                                                                             field.*/
95228   #define USBHSCORE_DOEPINT14_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                          */
95229   #define USBHSCORE_DOEPINT14_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                          */
95230   #define USBHSCORE_DOEPINT14_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
95231   #define USBHSCORE_DOEPINT14_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
95232 
95233 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
95234   #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                  */
95235   #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT14_BACK2BACKSETUP_Pos) /*!< Bit mask of
95236                                                                             BACK2BACKSETUP field.*/
95237   #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                    */
95238   #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                    */
95239   #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                               */
95240   #define USBHSCORE_DOEPINT14_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
95241 
95242 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
95243   #define USBHSCORE_DOEPINT14_OUTPKTERR_Pos (8UL)    /*!< Position of OUTPKTERR field.                                         */
95244   #define USBHSCORE_DOEPINT14_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT14_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.     */
95245   #define USBHSCORE_DOEPINT14_OUTPKTERR_Min (0x0UL)  /*!< Min enumerator value of OUTPKTERR field.                             */
95246   #define USBHSCORE_DOEPINT14_OUTPKTERR_Max (0x1UL)  /*!< Max enumerator value of OUTPKTERR field.                             */
95247   #define USBHSCORE_DOEPINT14_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95248   #define USBHSCORE_DOEPINT14_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95249 
95250 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
95251   #define USBHSCORE_DOEPINT14_BNAINTR_Pos (9UL)      /*!< Position of BNAINTR field.                                           */
95252   #define USBHSCORE_DOEPINT14_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT14_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.           */
95253   #define USBHSCORE_DOEPINT14_BNAINTR_Min (0x0UL)    /*!< Min enumerator value of BNAINTR field.                               */
95254   #define USBHSCORE_DOEPINT14_BNAINTR_Max (0x1UL)    /*!< Max enumerator value of BNAINTR field.                               */
95255   #define USBHSCORE_DOEPINT14_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
95256   #define USBHSCORE_DOEPINT14_BNAINTR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
95257 
95258 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
95259   #define USBHSCORE_DOEPINT14_PKTDRPSTS_Pos (11UL)   /*!< Position of PKTDRPSTS field.                                         */
95260   #define USBHSCORE_DOEPINT14_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT14_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.     */
95261   #define USBHSCORE_DOEPINT14_PKTDRPSTS_Min (0x0UL)  /*!< Min enumerator value of PKTDRPSTS field.                             */
95262   #define USBHSCORE_DOEPINT14_PKTDRPSTS_Max (0x1UL)  /*!< Max enumerator value of PKTDRPSTS field.                             */
95263   #define USBHSCORE_DOEPINT14_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95264   #define USBHSCORE_DOEPINT14_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95265 
95266 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
95267   #define USBHSCORE_DOEPINT14_BBLEERR_Pos (12UL)     /*!< Position of BBLEERR field.                                           */
95268   #define USBHSCORE_DOEPINT14_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT14_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.           */
95269   #define USBHSCORE_DOEPINT14_BBLEERR_Min (0x0UL)    /*!< Min enumerator value of BBLEERR field.                               */
95270   #define USBHSCORE_DOEPINT14_BBLEERR_Max (0x1UL)    /*!< Max enumerator value of BBLEERR field.                               */
95271   #define USBHSCORE_DOEPINT14_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
95272   #define USBHSCORE_DOEPINT14_BBLEERR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
95273 
95274 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
95275   #define USBHSCORE_DOEPINT14_NAKINTRPT_Pos (13UL)   /*!< Position of NAKINTRPT field.                                         */
95276   #define USBHSCORE_DOEPINT14_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT14_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.     */
95277   #define USBHSCORE_DOEPINT14_NAKINTRPT_Min (0x0UL)  /*!< Min enumerator value of NAKINTRPT field.                             */
95278   #define USBHSCORE_DOEPINT14_NAKINTRPT_Max (0x1UL)  /*!< Max enumerator value of NAKINTRPT field.                             */
95279   #define USBHSCORE_DOEPINT14_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95280   #define USBHSCORE_DOEPINT14_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95281 
95282 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
95283   #define USBHSCORE_DOEPINT14_NYETINTRPT_Pos (14UL)  /*!< Position of NYETINTRPT field.                                        */
95284   #define USBHSCORE_DOEPINT14_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT14_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.  */
95285   #define USBHSCORE_DOEPINT14_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field.                            */
95286   #define USBHSCORE_DOEPINT14_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field.                            */
95287   #define USBHSCORE_DOEPINT14_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
95288   #define USBHSCORE_DOEPINT14_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
95289 
95290 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
95291   #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field.                                       */
95292   #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT14_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD
95293                                                                             field.*/
95294   #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                          */
95295   #define USBHSCORE_DOEPINT14_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                          */
95296   #define USBHSCORE_DOEPINT14_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                  */
95297   #define USBHSCORE_DOEPINT14_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                      */
95298 
95299 
95300 /* USBHSCORE_DOEPTSIZ14: Device OUT Endpoint 14 Transfer Size Register */
95301   #define USBHSCORE_DOEPTSIZ14_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ14 register.                              */
95302 
95303 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
95304   #define USBHSCORE_DOEPTSIZ14_XFERSIZE_Pos (0UL)    /*!< Position of XFERSIZE field.                                          */
95305   #define USBHSCORE_DOEPTSIZ14_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ14_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.  */
95306 
95307 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
95308   #define USBHSCORE_DOEPTSIZ14_PKTCNT_Pos (19UL)     /*!< Position of PKTCNT field.                                            */
95309   #define USBHSCORE_DOEPTSIZ14_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ14_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.          */
95310 
95311 /* RXDPID @Bits 29..30 : RxDPID */
95312   #define USBHSCORE_DOEPTSIZ14_RXDPID_Pos (29UL)     /*!< Position of RXDPID field.                                            */
95313   #define USBHSCORE_DOEPTSIZ14_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ14_RXDPID_Pos) /*!< Bit mask of RXDPID field.            */
95314   #define USBHSCORE_DOEPTSIZ14_RXDPID_Min (0x0UL)    /*!< Min enumerator value of RXDPID field.                                */
95315   #define USBHSCORE_DOEPTSIZ14_RXDPID_Max (0x3UL)    /*!< Max enumerator value of RXDPID field.                                */
95316   #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA0 (0x0UL)  /*!< (unspecified)                                                        */
95317   #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                  */
95318   #define USBHSCORE_DOEPTSIZ14_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                  */
95319   #define USBHSCORE_DOEPTSIZ14_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                  */
95320 
95321 
95322 /* USBHSCORE_DOEPDMA14: Device OUT Endpoint 14 DMA Address Register */
95323   #define USBHSCORE_DOEPDMA14_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA14 register.                                */
95324 
95325 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
95326   #define USBHSCORE_DOEPDMA14_DMAADDR_Pos (0UL)      /*!< Position of DMAADDR field.                                           */
95327   #define USBHSCORE_DOEPDMA14_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA14_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.    */
95328 
95329 
95330 /* USBHSCORE_DOEPCTL15: Device Control OUT Endpoint 15 Control Register */
95331   #define USBHSCORE_DOEPCTL15_ResetValue (0x00000000UL) /*!< Reset value of DOEPCTL15 register.                                */
95332 
95333 /* MPS @Bits 0..10 : Maximum Packet Size (MPS) */
95334   #define USBHSCORE_DOEPCTL15_MPS_Pos (0UL)          /*!< Position of MPS field.                                               */
95335   #define USBHSCORE_DOEPCTL15_MPS_Msk (0x7FFUL << USBHSCORE_DOEPCTL15_MPS_Pos) /*!< Bit mask of MPS field.                     */
95336 
95337 /* USBACTEP @Bit 15 : USB Active Endpoint (USBActEP) */
95338   #define USBHSCORE_DOEPCTL15_USBACTEP_Pos (15UL)    /*!< Position of USBACTEP field.                                          */
95339   #define USBHSCORE_DOEPCTL15_USBACTEP_Msk (0x1UL << USBHSCORE_DOEPCTL15_USBACTEP_Pos) /*!< Bit mask of USBACTEP field.        */
95340   #define USBHSCORE_DOEPCTL15_USBACTEP_Min (0x0UL)   /*!< Min enumerator value of USBACTEP field.                              */
95341   #define USBHSCORE_DOEPCTL15_USBACTEP_Max (0x1UL)   /*!< Max enumerator value of USBACTEP field.                              */
95342   #define USBHSCORE_DOEPCTL15_USBACTEP_DISABLED (0x0UL) /*!< (unspecified)                                                     */
95343   #define USBHSCORE_DOEPCTL15_USBACTEP_ENABLED (0x1UL) /*!< (unspecified)                                                      */
95344 
95345 /* DPID @Bit 16 : Endpoint Data PID (DPID) */
95346   #define USBHSCORE_DOEPCTL15_DPID_Pos (16UL)        /*!< Position of DPID field.                                              */
95347   #define USBHSCORE_DOEPCTL15_DPID_Msk (0x1UL << USBHSCORE_DOEPCTL15_DPID_Pos) /*!< Bit mask of DPID field.                    */
95348   #define USBHSCORE_DOEPCTL15_DPID_Min (0x0UL)       /*!< Min enumerator value of DPID field.                                  */
95349   #define USBHSCORE_DOEPCTL15_DPID_Max (0x1UL)       /*!< Max enumerator value of DPID field.                                  */
95350   #define USBHSCORE_DOEPCTL15_DPID_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
95351   #define USBHSCORE_DOEPCTL15_DPID_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
95352 
95353 /* NAKSTS @Bit 17 : NAK Status (NAKSts) */
95354   #define USBHSCORE_DOEPCTL15_NAKSTS_Pos (17UL)      /*!< Position of NAKSTS field.                                            */
95355   #define USBHSCORE_DOEPCTL15_NAKSTS_Msk (0x1UL << USBHSCORE_DOEPCTL15_NAKSTS_Pos) /*!< Bit mask of NAKSTS field.              */
95356   #define USBHSCORE_DOEPCTL15_NAKSTS_Min (0x0UL)     /*!< Min enumerator value of NAKSTS field.                                */
95357   #define USBHSCORE_DOEPCTL15_NAKSTS_Max (0x1UL)     /*!< Max enumerator value of NAKSTS field.                                */
95358   #define USBHSCORE_DOEPCTL15_NAKSTS_NONNAK (0x0UL)  /*!< (unspecified)                                                        */
95359   #define USBHSCORE_DOEPCTL15_NAKSTS_NAK (0x1UL)     /*!< (unspecified)                                                        */
95360 
95361 /* EPTYPE @Bits 18..19 : Endpoint Type (EPType) */
95362   #define USBHSCORE_DOEPCTL15_EPTYPE_Pos (18UL)      /*!< Position of EPTYPE field.                                            */
95363   #define USBHSCORE_DOEPCTL15_EPTYPE_Msk (0x3UL << USBHSCORE_DOEPCTL15_EPTYPE_Pos) /*!< Bit mask of EPTYPE field.              */
95364   #define USBHSCORE_DOEPCTL15_EPTYPE_Min (0x0UL)     /*!< Min enumerator value of EPTYPE field.                                */
95365   #define USBHSCORE_DOEPCTL15_EPTYPE_Max (0x3UL)     /*!< Max enumerator value of EPTYPE field.                                */
95366   #define USBHSCORE_DOEPCTL15_EPTYPE_CONTROL (0x0UL) /*!< (unspecified)                                                        */
95367   #define USBHSCORE_DOEPCTL15_EPTYPE_ISOCHRONOUS (0x1UL) /*!< (unspecified)                                                    */
95368   #define USBHSCORE_DOEPCTL15_EPTYPE_BULK (0x2UL)    /*!< (unspecified)                                                        */
95369   #define USBHSCORE_DOEPCTL15_EPTYPE_INTERRUPT (0x3UL) /*!< (unspecified)                                                      */
95370 
95371 /* STALL @Bit 21 : STALL Handshake (Stall) */
95372   #define USBHSCORE_DOEPCTL15_STALL_Pos (21UL)       /*!< Position of STALL field.                                             */
95373   #define USBHSCORE_DOEPCTL15_STALL_Msk (0x1UL << USBHSCORE_DOEPCTL15_STALL_Pos) /*!< Bit mask of STALL field.                 */
95374   #define USBHSCORE_DOEPCTL15_STALL_Min (0x0UL)      /*!< Min enumerator value of STALL field.                                 */
95375   #define USBHSCORE_DOEPCTL15_STALL_Max (0x1UL)      /*!< Max enumerator value of STALL field.                                 */
95376   #define USBHSCORE_DOEPCTL15_STALL_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
95377   #define USBHSCORE_DOEPCTL15_STALL_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
95378 
95379 /* CNAK @Bit 26 : Clear NAK (CNAK) */
95380   #define USBHSCORE_DOEPCTL15_CNAK_Pos (26UL)        /*!< Position of CNAK field.                                              */
95381   #define USBHSCORE_DOEPCTL15_CNAK_Msk (0x1UL << USBHSCORE_DOEPCTL15_CNAK_Pos) /*!< Bit mask of CNAK field.                    */
95382   #define USBHSCORE_DOEPCTL15_CNAK_Min (0x0UL)       /*!< Min enumerator value of CNAK field.                                  */
95383   #define USBHSCORE_DOEPCTL15_CNAK_Max (0x1UL)       /*!< Max enumerator value of CNAK field.                                  */
95384   #define USBHSCORE_DOEPCTL15_CNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
95385   #define USBHSCORE_DOEPCTL15_CNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
95386 
95387 /* SNAK @Bit 27 : Set NAK (SNAK) */
95388   #define USBHSCORE_DOEPCTL15_SNAK_Pos (27UL)        /*!< Position of SNAK field.                                              */
95389   #define USBHSCORE_DOEPCTL15_SNAK_Msk (0x1UL << USBHSCORE_DOEPCTL15_SNAK_Pos) /*!< Bit mask of SNAK field.                    */
95390   #define USBHSCORE_DOEPCTL15_SNAK_Min (0x0UL)       /*!< Min enumerator value of SNAK field.                                  */
95391   #define USBHSCORE_DOEPCTL15_SNAK_Max (0x1UL)       /*!< Max enumerator value of SNAK field.                                  */
95392   #define USBHSCORE_DOEPCTL15_SNAK_INACTIVE (0x0UL)  /*!< (unspecified)                                                        */
95393   #define USBHSCORE_DOEPCTL15_SNAK_ACTIVE (0x1UL)    /*!< (unspecified)                                                        */
95394 
95395 /* SETD0PID @Bit 28 : Set DATA0 PID (SetD0PID) */
95396   #define USBHSCORE_DOEPCTL15_SETD0PID_Pos (28UL)    /*!< Position of SETD0PID field.                                          */
95397   #define USBHSCORE_DOEPCTL15_SETD0PID_Msk (0x1UL << USBHSCORE_DOEPCTL15_SETD0PID_Pos) /*!< Bit mask of SETD0PID field.        */
95398   #define USBHSCORE_DOEPCTL15_SETD0PID_Min (0x0UL)   /*!< Min enumerator value of SETD0PID field.                              */
95399   #define USBHSCORE_DOEPCTL15_SETD0PID_Max (0x1UL)   /*!< Max enumerator value of SETD0PID field.                              */
95400   #define USBHSCORE_DOEPCTL15_SETD0PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
95401   #define USBHSCORE_DOEPCTL15_SETD0PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
95402 
95403 /* SETD1PID @Bit 29 : Set DATA1 PID (SetD1PID) */
95404   #define USBHSCORE_DOEPCTL15_SETD1PID_Pos (29UL)    /*!< Position of SETD1PID field.                                          */
95405   #define USBHSCORE_DOEPCTL15_SETD1PID_Msk (0x1UL << USBHSCORE_DOEPCTL15_SETD1PID_Pos) /*!< Bit mask of SETD1PID field.        */
95406   #define USBHSCORE_DOEPCTL15_SETD1PID_Min (0x0UL)   /*!< Min enumerator value of SETD1PID field.                              */
95407   #define USBHSCORE_DOEPCTL15_SETD1PID_Max (0x1UL)   /*!< Max enumerator value of SETD1PID field.                              */
95408   #define USBHSCORE_DOEPCTL15_SETD1PID_DISABLED (0x0UL) /*!< (unspecified)                                                     */
95409   #define USBHSCORE_DOEPCTL15_SETD1PID_ENABLED (0x1UL) /*!< (unspecified)                                                      */
95410 
95411 /* EPDIS @Bit 30 : Endpoint Disable (EPDis) */
95412   #define USBHSCORE_DOEPCTL15_EPDIS_Pos (30UL)       /*!< Position of EPDIS field.                                             */
95413   #define USBHSCORE_DOEPCTL15_EPDIS_Msk (0x1UL << USBHSCORE_DOEPCTL15_EPDIS_Pos) /*!< Bit mask of EPDIS field.                 */
95414   #define USBHSCORE_DOEPCTL15_EPDIS_Min (0x0UL)      /*!< Min enumerator value of EPDIS field.                                 */
95415   #define USBHSCORE_DOEPCTL15_EPDIS_Max (0x1UL)      /*!< Max enumerator value of EPDIS field.                                 */
95416   #define USBHSCORE_DOEPCTL15_EPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
95417   #define USBHSCORE_DOEPCTL15_EPDIS_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
95418 
95419 /* EPENA @Bit 31 : Endpoint Enable (EPEna) */
95420   #define USBHSCORE_DOEPCTL15_EPENA_Pos (31UL)       /*!< Position of EPENA field.                                             */
95421   #define USBHSCORE_DOEPCTL15_EPENA_Msk (0x1UL << USBHSCORE_DOEPCTL15_EPENA_Pos) /*!< Bit mask of EPENA field.                 */
95422   #define USBHSCORE_DOEPCTL15_EPENA_Min (0x0UL)      /*!< Min enumerator value of EPENA field.                                 */
95423   #define USBHSCORE_DOEPCTL15_EPENA_Max (0x1UL)      /*!< Max enumerator value of EPENA field.                                 */
95424   #define USBHSCORE_DOEPCTL15_EPENA_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
95425   #define USBHSCORE_DOEPCTL15_EPENA_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
95426 
95427 
95428 /* USBHSCORE_DOEPINT15: Device OUT Endpoint 15 Interrupt Register */
95429   #define USBHSCORE_DOEPINT15_ResetValue (0x00000000UL) /*!< Reset value of DOEPINT15 register.                                */
95430 
95431 /* XFERCOMPL @Bit 0 : Transfer Completed Interrupt (XferCompl) */
95432   #define USBHSCORE_DOEPINT15_XFERCOMPL_Pos (0UL)    /*!< Position of XFERCOMPL field.                                         */
95433   #define USBHSCORE_DOEPINT15_XFERCOMPL_Msk (0x1UL << USBHSCORE_DOEPINT15_XFERCOMPL_Pos) /*!< Bit mask of XFERCOMPL field.     */
95434   #define USBHSCORE_DOEPINT15_XFERCOMPL_Min (0x0UL)  /*!< Min enumerator value of XFERCOMPL field.                             */
95435   #define USBHSCORE_DOEPINT15_XFERCOMPL_Max (0x1UL)  /*!< Max enumerator value of XFERCOMPL field.                             */
95436   #define USBHSCORE_DOEPINT15_XFERCOMPL_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95437   #define USBHSCORE_DOEPINT15_XFERCOMPL_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95438 
95439 /* EPDISBLD @Bit 1 : Endpoint Disabled Interrupt (EPDisbld) */
95440   #define USBHSCORE_DOEPINT15_EPDISBLD_Pos (1UL)     /*!< Position of EPDISBLD field.                                          */
95441   #define USBHSCORE_DOEPINT15_EPDISBLD_Msk (0x1UL << USBHSCORE_DOEPINT15_EPDISBLD_Pos) /*!< Bit mask of EPDISBLD field.        */
95442   #define USBHSCORE_DOEPINT15_EPDISBLD_Min (0x0UL)   /*!< Min enumerator value of EPDISBLD field.                              */
95443   #define USBHSCORE_DOEPINT15_EPDISBLD_Max (0x1UL)   /*!< Max enumerator value of EPDISBLD field.                              */
95444   #define USBHSCORE_DOEPINT15_EPDISBLD_INACTIVE (0x0UL) /*!< (unspecified)                                                     */
95445   #define USBHSCORE_DOEPINT15_EPDISBLD_ACTIVE (0x1UL) /*!< (unspecified)                                                       */
95446 
95447 /* AHBERR @Bit 2 : AHB Error (AHBErr) */
95448   #define USBHSCORE_DOEPINT15_AHBERR_Pos (2UL)       /*!< Position of AHBERR field.                                            */
95449   #define USBHSCORE_DOEPINT15_AHBERR_Msk (0x1UL << USBHSCORE_DOEPINT15_AHBERR_Pos) /*!< Bit mask of AHBERR field.              */
95450   #define USBHSCORE_DOEPINT15_AHBERR_Min (0x0UL)     /*!< Min enumerator value of AHBERR field.                                */
95451   #define USBHSCORE_DOEPINT15_AHBERR_Max (0x1UL)     /*!< Max enumerator value of AHBERR field.                                */
95452   #define USBHSCORE_DOEPINT15_AHBERR_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
95453   #define USBHSCORE_DOEPINT15_AHBERR_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
95454 
95455 /* SETUP @Bit 3 : SETUP Phase Done (SetUp) */
95456   #define USBHSCORE_DOEPINT15_SETUP_Pos (3UL)        /*!< Position of SETUP field.                                             */
95457   #define USBHSCORE_DOEPINT15_SETUP_Msk (0x1UL << USBHSCORE_DOEPINT15_SETUP_Pos) /*!< Bit mask of SETUP field.                 */
95458   #define USBHSCORE_DOEPINT15_SETUP_Min (0x0UL)      /*!< Min enumerator value of SETUP field.                                 */
95459   #define USBHSCORE_DOEPINT15_SETUP_Max (0x1UL)      /*!< Max enumerator value of SETUP field.                                 */
95460   #define USBHSCORE_DOEPINT15_SETUP_INACTIVE (0x0UL) /*!< (unspecified)                                                        */
95461   #define USBHSCORE_DOEPINT15_SETUP_ACTIVE (0x1UL)   /*!< (unspecified)                                                        */
95462 
95463 /* OUTTKNEPDIS @Bit 4 : OUT Token Received When Endpoint Disabled (OUTTknEPdis) */
95464   #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Pos (4UL)  /*!< Position of OUTTKNEPDIS field.                                       */
95465   #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Msk (0x1UL << USBHSCORE_DOEPINT15_OUTTKNEPDIS_Pos) /*!< Bit mask of OUTTKNEPDIS
95466                                                                             field.*/
95467   #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Min (0x0UL) /*!< Min enumerator value of OUTTKNEPDIS field.                          */
95468   #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_Max (0x1UL) /*!< Max enumerator value of OUTTKNEPDIS field.                          */
95469   #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
95470   #define USBHSCORE_DOEPINT15_OUTTKNEPDIS_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
95471 
95472 /* STSPHSERCVD @Bit 5 : Status Phase Received for Control Write (StsPhseRcvd) */
95473   #define USBHSCORE_DOEPINT15_STSPHSERCVD_Pos (5UL)  /*!< Position of STSPHSERCVD field.                                       */
95474   #define USBHSCORE_DOEPINT15_STSPHSERCVD_Msk (0x1UL << USBHSCORE_DOEPINT15_STSPHSERCVD_Pos) /*!< Bit mask of STSPHSERCVD
95475                                                                             field.*/
95476   #define USBHSCORE_DOEPINT15_STSPHSERCVD_Min (0x0UL) /*!< Min enumerator value of STSPHSERCVD field.                          */
95477   #define USBHSCORE_DOEPINT15_STSPHSERCVD_Max (0x1UL) /*!< Max enumerator value of STSPHSERCVD field.                          */
95478   #define USBHSCORE_DOEPINT15_STSPHSERCVD_INACTIVE (0x0UL) /*!< (unspecified)                                                  */
95479   #define USBHSCORE_DOEPINT15_STSPHSERCVD_ACTIVE (0x1UL) /*!< (unspecified)                                                    */
95480 
95481 /* BACK2BACKSETUP @Bit 6 : Back-to-Back SETUP Packets Received (Back2BackSETup) */
95482   #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Pos (6UL) /*!< Position of BACK2BACKSETUP field.                                  */
95483   #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Msk (0x1UL << USBHSCORE_DOEPINT15_BACK2BACKSETUP_Pos) /*!< Bit mask of
95484                                                                             BACK2BACKSETUP field.*/
95485   #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Min (0x0UL) /*!< Min enumerator value of BACK2BACKSETUP field.                    */
95486   #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_Max (0x1UL) /*!< Max enumerator value of BACK2BACKSETUP field.                    */
95487   #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_INACTIVE (0x0UL) /*!< (unspecified)                                               */
95488   #define USBHSCORE_DOEPINT15_BACK2BACKSETUP_ACTIVE (0x1UL) /*!< (unspecified)                                                 */
95489 
95490 /* OUTPKTERR @Bit 8 : OUT Packet Error (OutPktErr) */
95491   #define USBHSCORE_DOEPINT15_OUTPKTERR_Pos (8UL)    /*!< Position of OUTPKTERR field.                                         */
95492   #define USBHSCORE_DOEPINT15_OUTPKTERR_Msk (0x1UL << USBHSCORE_DOEPINT15_OUTPKTERR_Pos) /*!< Bit mask of OUTPKTERR field.     */
95493   #define USBHSCORE_DOEPINT15_OUTPKTERR_Min (0x0UL)  /*!< Min enumerator value of OUTPKTERR field.                             */
95494   #define USBHSCORE_DOEPINT15_OUTPKTERR_Max (0x1UL)  /*!< Max enumerator value of OUTPKTERR field.                             */
95495   #define USBHSCORE_DOEPINT15_OUTPKTERR_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95496   #define USBHSCORE_DOEPINT15_OUTPKTERR_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95497 
95498 /* BNAINTR @Bit 9 : BNA (Buffer Not Available) Interrupt (BNAIntr) */
95499   #define USBHSCORE_DOEPINT15_BNAINTR_Pos (9UL)      /*!< Position of BNAINTR field.                                           */
95500   #define USBHSCORE_DOEPINT15_BNAINTR_Msk (0x1UL << USBHSCORE_DOEPINT15_BNAINTR_Pos) /*!< Bit mask of BNAINTR field.           */
95501   #define USBHSCORE_DOEPINT15_BNAINTR_Min (0x0UL)    /*!< Min enumerator value of BNAINTR field.                               */
95502   #define USBHSCORE_DOEPINT15_BNAINTR_Max (0x1UL)    /*!< Max enumerator value of BNAINTR field.                               */
95503   #define USBHSCORE_DOEPINT15_BNAINTR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
95504   #define USBHSCORE_DOEPINT15_BNAINTR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
95505 
95506 /* PKTDRPSTS @Bit 11 : Packet Drop Status (PktDrpSts) */
95507   #define USBHSCORE_DOEPINT15_PKTDRPSTS_Pos (11UL)   /*!< Position of PKTDRPSTS field.                                         */
95508   #define USBHSCORE_DOEPINT15_PKTDRPSTS_Msk (0x1UL << USBHSCORE_DOEPINT15_PKTDRPSTS_Pos) /*!< Bit mask of PKTDRPSTS field.     */
95509   #define USBHSCORE_DOEPINT15_PKTDRPSTS_Min (0x0UL)  /*!< Min enumerator value of PKTDRPSTS field.                             */
95510   #define USBHSCORE_DOEPINT15_PKTDRPSTS_Max (0x1UL)  /*!< Max enumerator value of PKTDRPSTS field.                             */
95511   #define USBHSCORE_DOEPINT15_PKTDRPSTS_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95512   #define USBHSCORE_DOEPINT15_PKTDRPSTS_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95513 
95514 /* BBLEERR @Bit 12 : NAK Interrupt (BbleErr) */
95515   #define USBHSCORE_DOEPINT15_BBLEERR_Pos (12UL)     /*!< Position of BBLEERR field.                                           */
95516   #define USBHSCORE_DOEPINT15_BBLEERR_Msk (0x1UL << USBHSCORE_DOEPINT15_BBLEERR_Pos) /*!< Bit mask of BBLEERR field.           */
95517   #define USBHSCORE_DOEPINT15_BBLEERR_Min (0x0UL)    /*!< Min enumerator value of BBLEERR field.                               */
95518   #define USBHSCORE_DOEPINT15_BBLEERR_Max (0x1UL)    /*!< Max enumerator value of BBLEERR field.                               */
95519   #define USBHSCORE_DOEPINT15_BBLEERR_INACTIVE (0x0UL) /*!< (unspecified)                                                      */
95520   #define USBHSCORE_DOEPINT15_BBLEERR_ACTIVE (0x1UL) /*!< (unspecified)                                                        */
95521 
95522 /* NAKINTRPT @Bit 13 : NAK Interrupt (NAKInterrupt) */
95523   #define USBHSCORE_DOEPINT15_NAKINTRPT_Pos (13UL)   /*!< Position of NAKINTRPT field.                                         */
95524   #define USBHSCORE_DOEPINT15_NAKINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT15_NAKINTRPT_Pos) /*!< Bit mask of NAKINTRPT field.     */
95525   #define USBHSCORE_DOEPINT15_NAKINTRPT_Min (0x0UL)  /*!< Min enumerator value of NAKINTRPT field.                             */
95526   #define USBHSCORE_DOEPINT15_NAKINTRPT_Max (0x1UL)  /*!< Max enumerator value of NAKINTRPT field.                             */
95527   #define USBHSCORE_DOEPINT15_NAKINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95528   #define USBHSCORE_DOEPINT15_NAKINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95529 
95530 /* NYETINTRPT @Bit 14 : NYET Interrupt (NYETIntrpt) */
95531   #define USBHSCORE_DOEPINT15_NYETINTRPT_Pos (14UL)  /*!< Position of NYETINTRPT field.                                        */
95532   #define USBHSCORE_DOEPINT15_NYETINTRPT_Msk (0x1UL << USBHSCORE_DOEPINT15_NYETINTRPT_Pos) /*!< Bit mask of NYETINTRPT field.  */
95533   #define USBHSCORE_DOEPINT15_NYETINTRPT_Min (0x0UL) /*!< Min enumerator value of NYETINTRPT field.                            */
95534   #define USBHSCORE_DOEPINT15_NYETINTRPT_Max (0x1UL) /*!< Max enumerator value of NYETINTRPT field.                            */
95535   #define USBHSCORE_DOEPINT15_NYETINTRPT_INACTIVE (0x0UL) /*!< (unspecified)                                                   */
95536   #define USBHSCORE_DOEPINT15_NYETINTRPT_ACTIVE (0x1UL) /*!< (unspecified)                                                     */
95537 
95538 /* STUPPKTRCVD @Bit 15 : Setup Packet Received */
95539   #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Pos (15UL) /*!< Position of STUPPKTRCVD field.                                       */
95540   #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Msk (0x1UL << USBHSCORE_DOEPINT15_STUPPKTRCVD_Pos) /*!< Bit mask of STUPPKTRCVD
95541                                                                             field.*/
95542   #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Min (0x0UL) /*!< Min enumerator value of STUPPKTRCVD field.                          */
95543   #define USBHSCORE_DOEPINT15_STUPPKTRCVD_Max (0x1UL) /*!< Max enumerator value of STUPPKTRCVD field.                          */
95544   #define USBHSCORE_DOEPINT15_STUPPKTRCVD_NOT_RCVD (0x0UL) /*!< (unspecified)                                                  */
95545   #define USBHSCORE_DOEPINT15_STUPPKTRCVD_RCVD (0x1UL) /*!< (unspecified)                                                      */
95546 
95547 
95548 /* USBHSCORE_DOEPTSIZ15: Device OUT Endpoint 15 Transfer Size Register */
95549   #define USBHSCORE_DOEPTSIZ15_ResetValue (0x00000000UL) /*!< Reset value of DOEPTSIZ15 register.                              */
95550 
95551 /* XFERSIZE @Bits 0..18 : Transfer Size (XferSize) */
95552   #define USBHSCORE_DOEPTSIZ15_XFERSIZE_Pos (0UL)    /*!< Position of XFERSIZE field.                                          */
95553   #define USBHSCORE_DOEPTSIZ15_XFERSIZE_Msk (0x7FFFFUL << USBHSCORE_DOEPTSIZ15_XFERSIZE_Pos) /*!< Bit mask of XFERSIZE field.  */
95554 
95555 /* PKTCNT @Bits 19..28 : Packet Count (PktCnt) */
95556   #define USBHSCORE_DOEPTSIZ15_PKTCNT_Pos (19UL)     /*!< Position of PKTCNT field.                                            */
95557   #define USBHSCORE_DOEPTSIZ15_PKTCNT_Msk (0x3FFUL << USBHSCORE_DOEPTSIZ15_PKTCNT_Pos) /*!< Bit mask of PKTCNT field.          */
95558 
95559 /* RXDPID @Bits 29..30 : RxDPID */
95560   #define USBHSCORE_DOEPTSIZ15_RXDPID_Pos (29UL)     /*!< Position of RXDPID field.                                            */
95561   #define USBHSCORE_DOEPTSIZ15_RXDPID_Msk (0x3UL << USBHSCORE_DOEPTSIZ15_RXDPID_Pos) /*!< Bit mask of RXDPID field.            */
95562   #define USBHSCORE_DOEPTSIZ15_RXDPID_Min (0x0UL)    /*!< Min enumerator value of RXDPID field.                                */
95563   #define USBHSCORE_DOEPTSIZ15_RXDPID_Max (0x3UL)    /*!< Max enumerator value of RXDPID field.                                */
95564   #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA0 (0x0UL)  /*!< (unspecified)                                                        */
95565   #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA2PACKET1 (0x1UL) /*!< (unspecified)                                                  */
95566   #define USBHSCORE_DOEPTSIZ15_RXDPID_DATA1PACKET2 (0x2UL) /*!< (unspecified)                                                  */
95567   #define USBHSCORE_DOEPTSIZ15_RXDPID_MDATAPACKET3 (0x3UL) /*!< (unspecified)                                                  */
95568 
95569 
95570 /* USBHSCORE_DOEPDMA15: Device OUT Endpoint 15 DMA Address Register */
95571   #define USBHSCORE_DOEPDMA15_ResetValue (0x00000000UL) /*!< Reset value of DOEPDMA15 register.                                */
95572 
95573 /* DMAADDR @Bits 0..31 : Holds the start address of the external memory for storing or fetching endpoint */
95574   #define USBHSCORE_DOEPDMA15_DMAADDR_Pos (0UL)      /*!< Position of DMAADDR field.                                           */
95575   #define USBHSCORE_DOEPDMA15_DMAADDR_Msk (0xFFFFFFFFUL << USBHSCORE_DOEPDMA15_DMAADDR_Pos) /*!< Bit mask of DMAADDR field.    */
95576 
95577 
95578 /* USBHSCORE_PCGCCTL: Power and Clock Gating Control Register */
95579   #define USBHSCORE_PCGCCTL_ResetValue (0x880A0000UL) /*!< Reset value of PCGCCTL register.                                    */
95580 
95581 /* STOPPCLK @Bit 0 : Stop Pclk (StopPclk) */
95582   #define USBHSCORE_PCGCCTL_STOPPCLK_Pos (0UL)       /*!< Position of STOPPCLK field.                                          */
95583   #define USBHSCORE_PCGCCTL_STOPPCLK_Msk (0x1UL << USBHSCORE_PCGCCTL_STOPPCLK_Pos) /*!< Bit mask of STOPPCLK field.            */
95584   #define USBHSCORE_PCGCCTL_STOPPCLK_Min (0x0UL)     /*!< Min enumerator value of STOPPCLK field.                              */
95585   #define USBHSCORE_PCGCCTL_STOPPCLK_Max (0x1UL)     /*!< Max enumerator value of STOPPCLK field.                              */
95586   #define USBHSCORE_PCGCCTL_STOPPCLK_DISABLED (0x0UL) /*!< (unspecified)                                                       */
95587   #define USBHSCORE_PCGCCTL_STOPPCLK_ENABLED (0x1UL) /*!< (unspecified)                                                        */
95588 
95589 /* RSTPDWNMODULE @Bit 3 : Reset Power-Down Modules (RstPdwnModule) */
95590   #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Pos (3UL)  /*!< Position of RSTPDWNMODULE field.                                     */
95591   #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Msk (0x1UL << USBHSCORE_PCGCCTL_RSTPDWNMODULE_Pos) /*!< Bit mask of RSTPDWNMODULE
95592                                                                             field.*/
95593   #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Min (0x0UL) /*!< Min enumerator value of RSTPDWNMODULE field.                        */
95594   #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_Max (0x1UL) /*!< Max enumerator value of RSTPDWNMODULE field.                        */
95595   #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_ON (0x0UL) /*!< (unspecified)                                                        */
95596   #define USBHSCORE_PCGCCTL_RSTPDWNMODULE_OFF (0x1UL) /*!< (unspecified)                                                       */
95597 
95598 /* ENBLL1GATING @Bit 5 : Enable Sleep Clock Gating */
95599   #define USBHSCORE_PCGCCTL_ENBLL1GATING_Pos (5UL)   /*!< Position of ENBLL1GATING field.                                      */
95600   #define USBHSCORE_PCGCCTL_ENBLL1GATING_Msk (0x1UL << USBHSCORE_PCGCCTL_ENBLL1GATING_Pos) /*!< Bit mask of ENBLL1GATING field.*/
95601   #define USBHSCORE_PCGCCTL_ENBLL1GATING_Min (0x0UL) /*!< Min enumerator value of ENBLL1GATING field.                          */
95602   #define USBHSCORE_PCGCCTL_ENBLL1GATING_Max (0x1UL) /*!< Max enumerator value of ENBLL1GATING field.                          */
95603   #define USBHSCORE_PCGCCTL_ENBLL1GATING_DISABLED (0x0UL) /*!< (unspecified)                                                   */
95604   #define USBHSCORE_PCGCCTL_ENBLL1GATING_ENABLED (0x1UL) /*!< (unspecified)                                                    */
95605 
95606 /* PHYSLEEP @Bit 6 : PHY In Sleep */
95607   #define USBHSCORE_PCGCCTL_PHYSLEEP_Pos (6UL)       /*!< Position of PHYSLEEP field.                                          */
95608   #define USBHSCORE_PCGCCTL_PHYSLEEP_Msk (0x1UL << USBHSCORE_PCGCCTL_PHYSLEEP_Pos) /*!< Bit mask of PHYSLEEP field.            */
95609   #define USBHSCORE_PCGCCTL_PHYSLEEP_Min (0x0UL)     /*!< Min enumerator value of PHYSLEEP field.                              */
95610   #define USBHSCORE_PCGCCTL_PHYSLEEP_Max (0x1UL)     /*!< Max enumerator value of PHYSLEEP field.                              */
95611   #define USBHSCORE_PCGCCTL_PHYSLEEP_INACTIVE (0x0UL) /*!< (unspecified)                                                       */
95612   #define USBHSCORE_PCGCCTL_PHYSLEEP_ACTIVE (0x1UL)  /*!< (unspecified)                                                        */
95613 
95614 /* L1SUSPENDED @Bit 7 : L1 Deep Sleep */
95615   #define USBHSCORE_PCGCCTL_L1SUSPENDED_Pos (7UL)    /*!< Position of L1SUSPENDED field.                                       */
95616   #define USBHSCORE_PCGCCTL_L1SUSPENDED_Msk (0x1UL << USBHSCORE_PCGCCTL_L1SUSPENDED_Pos) /*!< Bit mask of L1SUSPENDED field.   */
95617   #define USBHSCORE_PCGCCTL_L1SUSPENDED_Min (0x0UL)  /*!< Min enumerator value of L1SUSPENDED field.                           */
95618   #define USBHSCORE_PCGCCTL_L1SUSPENDED_Max (0x1UL)  /*!< Max enumerator value of L1SUSPENDED field.                           */
95619   #define USBHSCORE_PCGCCTL_L1SUSPENDED_INACTIVE (0x0UL) /*!< (unspecified)                                                    */
95620   #define USBHSCORE_PCGCCTL_L1SUSPENDED_ACTIVE (0x1UL) /*!< (unspecified)                                                      */
95621 
95622 /* RESTOREMODE @Bit 9 : Restore Mode (RestoreMode) */
95623   #define USBHSCORE_PCGCCTL_RESTOREMODE_Pos (9UL)    /*!< Position of RESTOREMODE field.                                       */
95624   #define USBHSCORE_PCGCCTL_RESTOREMODE_Msk (0x1UL << USBHSCORE_PCGCCTL_RESTOREMODE_Pos) /*!< Bit mask of RESTOREMODE field.   */
95625   #define USBHSCORE_PCGCCTL_RESTOREMODE_Min (0x0UL)  /*!< Min enumerator value of RESTOREMODE field.                           */
95626   #define USBHSCORE_PCGCCTL_RESTOREMODE_Max (0x1UL)  /*!< Max enumerator value of RESTOREMODE field.                           */
95627   #define USBHSCORE_PCGCCTL_RESTOREMODE_DISABLED (0x0UL) /*!< (unspecified)                                                    */
95628   #define USBHSCORE_PCGCCTL_RESTOREMODE_ENABLED (0x1UL) /*!< (unspecified)                                                     */
95629 
95630 /* ESSREGRESTORED @Bit 13 : Essential Register Values Restored (EssRegRestored) */
95631   #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Pos (13UL) /*!< Position of ESSREGRESTORED field.                                   */
95632   #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Msk (0x1UL << USBHSCORE_PCGCCTL_ESSREGRESTORED_Pos) /*!< Bit mask of ESSREGRESTORED
95633                                                                             field.*/
95634   #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Min (0x0UL) /*!< Min enumerator value of ESSREGRESTORED field.                      */
95635   #define USBHSCORE_PCGCCTL_ESSREGRESTORED_Max (0x1UL) /*!< Max enumerator value of ESSREGRESTORED field.                      */
95636   #define USBHSCORE_PCGCCTL_ESSREGRESTORED_NOT_RESTORED (0x0UL) /*!< (unspecified)                                             */
95637   #define USBHSCORE_PCGCCTL_ESSREGRESTORED_RESTORED (0x1UL) /*!< (unspecified)                                                 */
95638 
95639 /* RESTOREVALUE @Bits 14..31 : Restore Value (RestoreValue) */
95640   #define USBHSCORE_PCGCCTL_RESTOREVALUE_Pos (14UL)  /*!< Position of RESTOREVALUE field.                                      */
95641   #define USBHSCORE_PCGCCTL_RESTOREVALUE_Msk (0x3FFFFUL << USBHSCORE_PCGCCTL_RESTOREVALUE_Pos) /*!< Bit mask of RESTOREVALUE
95642                                                                             field.*/
95643 
95644 
95645 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
95646 
95647 /* =========================================================================================================================== */
95648 /* ================                                      VDMADESCRIPTOR                                      ================ */
95649 /* =========================================================================================================================== */
95650 
95651 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
95652 /* ================================================== Struct VDMADESCRIPTOR ================================================== */
95653 /**
95654   * @brief Job descriptor for vector-based DMA.
95655   */
95656   typedef struct {                                   /*!< VDMADESCRIPTOR Structure                                             */
95657     __IOM uint32_t PTR;                              /*!< (@ 0x00000000) Pointer to data buffer.                               */
95658     __IOM uint32_t CONFIG;                           /*!< (@ 0x00000004) Job configuration. Configuration of attributes and
95659                                                                          buffer length.*/
95660   } NRF_VDMADESCRIPTOR_Type;                         /*!< Size = 8 (0x008)                                                     */
95661 
95662 /* VDMADESCRIPTOR_PTR: Pointer to data buffer. */
95663   #define VDMADESCRIPTOR_PTR_ResetValue (0x00000000UL) /*!< Reset value of PTR register.                                       */
95664 
95665 /* PTR @Bits 0..31 : Pointer to data buffer. */
95666   #define VDMADESCRIPTOR_PTR_PTR_Pos (0UL)           /*!< Position of PTR field.                                               */
95667   #define VDMADESCRIPTOR_PTR_PTR_Msk (0xFFFFFFFFUL << VDMADESCRIPTOR_PTR_PTR_Pos) /*!< Bit mask of PTR field.                  */
95668 
95669 
95670 /* VDMADESCRIPTOR_CONFIG: Job configuration. Configuration of attributes and buffer length. */
95671   #define VDMADESCRIPTOR_CONFIG_ResetValue (0x00000000UL) /*!< Reset value of CONFIG register.                                 */
95672 
95673 /* CNT @Bits 0..23 : Maximum number of bytes in data buffer. */
95674   #define VDMADESCRIPTOR_CONFIG_CNT_Pos (0UL)        /*!< Position of CNT field.                                               */
95675   #define VDMADESCRIPTOR_CONFIG_CNT_Msk (0xFFFFFFUL << VDMADESCRIPTOR_CONFIG_CNT_Pos) /*!< Bit mask of CNT field.              */
95676 
95677 /* ATTRIBUTE @Bits 24..29 : Job attribute. */
95678   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos (24UL) /*!< Position of ATTRIBUTE field.                                         */
95679   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Msk (0x3FUL << VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos) /*!< Bit mask of ATTRIBUTE field.*/
95680   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Min (0x0UL) /*!< Min enumerator value of ATTRIBUTE field.                            */
95681   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Max (0x6UL) /*!< Max enumerator value of ATTRIBUTE field.                            */
95682   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_ByteSwap (0x00UL) /*!< Byte swap attribute.                                          */
95683   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_JobList (0x01UL) /*!< Job list attribute.                                            */
95684   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_BufferFill (0x02UL) /*!< Buffer fill attribute.                                      */
95685   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_FixedSize (0x03UL) /*!< Fixed size attribute.                                        */
95686   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_StaticAddress (0x04UL) /*!< Static address attribute.                                */
95687   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_PlainDataBufferWrite (0x05UL) /*!< Plain data buffer write attribute.                */
95688   #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Crc (0x06UL) /*!< CRC attribute.                                                     */
95689 
95690 /* ACCESSTYPE @Bit 30 : Type of access. */
95691   #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Pos (30UL) /*!< Position of ACCESSTYPE field.                                       */
95692   #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Msk (0x1UL << VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Pos) /*!< Bit mask of ACCESSTYPE
95693                                                                             field.*/
95694   #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Min (0x0UL) /*!< Min enumerator value of ACCESSTYPE field.                          */
95695   #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Max (0x1UL) /*!< Max enumerator value of ACCESSTYPE field.                          */
95696   #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Memory (0x0UL) /*!< Memory access.                                                  */
95697   #define VDMADESCRIPTOR_CONFIG_ACCESSTYPE_Peripheral (0x1UL) /*!< Peripheral register access.                                 */
95698 
95699 /* SELECTJOBENABLE @Bit 31 : Enables generation of event EVENTS_SELECTJOBDONE. */
95700   #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Pos (31UL) /*!< Position of SELECTJOBENABLE field.                             */
95701   #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Msk (0x1UL << VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Pos) /*!< Bit mask of
95702                                                                             SELECTJOBENABLE field.*/
95703   #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Min (0x0UL) /*!< Min enumerator value of SELECTJOBENABLE field.                */
95704   #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Max (0x1UL) /*!< Max enumerator value of SELECTJOBENABLE field.                */
95705   #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Disable (0x0UL) /*!< Event is not generated.                                   */
95706   #define VDMADESCRIPTOR_CONFIG_SELECTJOBENABLE_Enable (0x1UL) /*!< Event is generated.                                        */
95707 
95708 
95709 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
95710 
95711 /* =========================================================================================================================== */
95712 /* ================                                            VPR                                            ================ */
95713 /* =========================================================================================================================== */
95714 
95715 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
95716 
95717 /* =================================================== Struct VPR_DEBUGIF ==================================================== */
95718 /**
95719   * @brief DEBUGIF [VPR_DEBUGIF] (unspecified)
95720   */
95721 typedef struct {
95722   __IM  uint32_t  RESERVED[4];
95723   __IOM uint32_t  DATA0;                             /*!< (@ 0x00000010) Abstract Data 0. Read/write data for argument 0       */
95724   __IOM uint32_t  DATA1;                             /*!< (@ 0x00000014) Abstract Data 1. Read/write data for argument 1       */
95725   __IM  uint32_t  RESERVED1[10];
95726   __IOM uint32_t  DMCONTROL;                         /*!< (@ 0x00000040) Debug Module Control                                  */
95727   __IM  uint32_t  DMSTATUS;                          /*!< (@ 0x00000044) Debug Module Status                                   */
95728   __IOM uint32_t  HARTINFO;                          /*!< (@ 0x00000048) Hart Information                                      */
95729   __IOM uint32_t  HALTSUM1;                          /*!< (@ 0x0000004C) Halt Summary 1                                        */
95730   __IOM uint32_t  HAWINDOWSEL;                       /*!< (@ 0x00000050) Hart Array Window Select                              */
95731   __IOM uint32_t  HAWINDOW;                          /*!< (@ 0x00000054) Hart Array Window                                     */
95732   __IOM uint32_t  ABSTRACTCS;                        /*!< (@ 0x00000058) Abstract Control and Status                           */
95733   __OM  uint32_t  ABSTRACTCMD;                       /*!< (@ 0x0000005C) Abstract command                                      */
95734   __IOM uint32_t  ABSTRACTAUTO;                      /*!< (@ 0x00000060) Abstract Command Autoexec                             */
95735   __IOM uint32_t  CONFSTRPTR[4];                     /*!< (@ 0x00000064) Configuration String Pointer [n]                      */
95736   __IOM uint32_t  NEXTDM;                            /*!< (@ 0x00000074) Next Debug Module                                     */
95737   __IM  uint32_t  RESERVED2[2];
95738   __IOM uint32_t  PROGBUF[16];                       /*!< (@ 0x00000080) Program Buffer [n]                                    */
95739   __IOM uint32_t  AUTHDATA;                          /*!< (@ 0x000000C0) Authentication Data                                   */
95740   __IM  uint32_t  RESERVED3[3];
95741   __IOM uint32_t  HALTSUM2;                          /*!< (@ 0x000000D0) Halt Summary 2                                        */
95742   __IOM uint32_t  HALTSUM3;                          /*!< (@ 0x000000D4) Halt Summary 3                                        */
95743   __IM  uint32_t  RESERVED4;
95744   __IOM uint32_t  SBADDRESS3;                        /*!< (@ 0x000000DC) System Bus Addres 127:96                              */
95745   __IOM uint32_t  SBCS;                              /*!< (@ 0x000000E0) System Bus Access Control and Status                  */
95746   __IOM uint32_t  SBADDRESS0;                        /*!< (@ 0x000000E4) System Bus Addres 31:0                                */
95747   __IOM uint32_t  SBADDRESS1;                        /*!< (@ 0x000000E8) System Bus Addres 63:32                               */
95748   __IOM uint32_t  SBADDRESS2;                        /*!< (@ 0x000000EC) System Bus Addres 95:64                               */
95749   __IOM uint32_t  SBDATA0;                           /*!< (@ 0x000000F0) System Bus Data 31:0                                  */
95750   __IOM uint32_t  SBDATA1;                           /*!< (@ 0x000000F4) System Bus Data 63:32                                 */
95751   __IOM uint32_t  SBDATA2;                           /*!< (@ 0x000000F8) System Bus Data 95:64                                 */
95752   __IOM uint32_t  SBDATA3;                           /*!< (@ 0x000000FC) System Bus Data 127:96                                */
95753   __IOM uint32_t  HALTSUM0;                          /*!< (@ 0x00000100) Halt summary 0                                        */
95754 } NRF_VPR_DEBUGIF_Type;                              /*!< Size = 260 (0x104)                                                   */
95755 
95756 /* VPR_DEBUGIF_DATA0: Abstract Data 0. Read/write data for argument 0 */
95757   #define VPR_DEBUGIF_DATA0_ResetValue (0x00000000UL) /*!< Reset value of DATA0 register.                                      */
95758 
95759 /* DATA0 @Bits 0..31 : Abstract Data 0 */
95760   #define VPR_DEBUGIF_DATA0_DATA0_Pos (0UL)          /*!< Position of DATA0 field.                                             */
95761   #define VPR_DEBUGIF_DATA0_DATA0_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_DATA0_DATA0_Pos) /*!< Bit mask of DATA0 field.              */
95762 
95763 
95764 /* VPR_DEBUGIF_DATA1: Abstract Data 1. Read/write data for argument 1 */
95765   #define VPR_DEBUGIF_DATA1_ResetValue (0x00000000UL) /*!< Reset value of DATA1 register.                                      */
95766 
95767 /* DATA1 @Bits 0..31 : Abstract Data 1 */
95768   #define VPR_DEBUGIF_DATA1_DATA1_Pos (0UL)          /*!< Position of DATA1 field.                                             */
95769   #define VPR_DEBUGIF_DATA1_DATA1_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_DATA1_DATA1_Pos) /*!< Bit mask of DATA1 field.              */
95770 
95771 
95772 /* VPR_DEBUGIF_DMCONTROL: Debug Module Control */
95773   #define VPR_DEBUGIF_DMCONTROL_ResetValue (0x00000000UL) /*!< Reset value of DMCONTROL register.                              */
95774 
95775 /* DMACTIVE @Bit 0 : Reset signal for the debug module. */
95776   #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos (0UL)   /*!< Position of DMACTIVE field.                                          */
95777   #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos) /*!< Bit mask of DMACTIVE field.    */
95778   #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Min (0x0UL) /*!< Min enumerator value of DMACTIVE field.                              */
95779   #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Max (0x1UL) /*!< Max enumerator value of DMACTIVE field.                              */
95780   #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Disabled (0x0UL) /*!< Reset the debug module itself                                   */
95781   #define VPR_DEBUGIF_DMCONTROL_DMACTIVE_Enabled (0x1UL) /*!< Normal operation                                                 */
95782 
95783 /* NDMRESET @Bit 1 : Reset signal output from the debug module to the system. */
95784   #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos (1UL)   /*!< Position of NDMRESET field.                                          */
95785   #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos) /*!< Bit mask of NDMRESET field.    */
95786   #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Min (0x0UL) /*!< Min enumerator value of NDMRESET field.                              */
95787   #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Max (0x1UL) /*!< Max enumerator value of NDMRESET field.                              */
95788   #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Inactive (0x0UL) /*!< Reset inactive                                                  */
95789   #define VPR_DEBUGIF_DMCONTROL_NDMRESET_Active (0x1UL) /*!< Reset active                                                      */
95790 
95791 /* CLRRESETHALTREQ @Bit 2 : Clear the halt on reset request. */
95792   #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Pos (2UL) /*!< Position of CLRRESETHALTREQ field.                              */
95793   #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Pos) /*!< Bit mask of
95794                                                                             CLRRESETHALTREQ field.*/
95795   #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of CLRRESETHALTREQ field.                */
95796   #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of CLRRESETHALTREQ field.                */
95797   #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_NoOperation (0x0UL) /*!< No operation when written 0.                          */
95798   #define VPR_DEBUGIF_DMCONTROL_CLRRESETHALTREQ_Clear (0x1UL) /*!< Clears the halt on reset request                            */
95799 
95800 /* SETRESETHALTREQ @Bit 3 : Set the halt on reset request. */
95801   #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Pos (3UL) /*!< Position of SETRESETHALTREQ field.                              */
95802   #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Pos) /*!< Bit mask of
95803                                                                             SETRESETHALTREQ field.*/
95804   #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of SETRESETHALTREQ field.                */
95805   #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of SETRESETHALTREQ field.                */
95806   #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_NoOperation (0x0UL) /*!< No operation when written 0.                          */
95807   #define VPR_DEBUGIF_DMCONTROL_SETRESETHALTREQ_Clear (0x1UL) /*!< Sets the halt on reset request                              */
95808 
95809 /* HARTSELHI @Bits 6..15 : The high 10 bits of hartsel. */
95810   #define VPR_DEBUGIF_DMCONTROL_HARTSELHI_Pos (6UL)  /*!< Position of HARTSELHI field.                                         */
95811   #define VPR_DEBUGIF_DMCONTROL_HARTSELHI_Msk (0x3FFUL << VPR_DEBUGIF_DMCONTROL_HARTSELHI_Pos) /*!< Bit mask of HARTSELHI
95812                                                                             field.*/
95813 
95814 /* HARTSELLO @Bits 16..25 : The low 10 bits of hartsel. */
95815   #define VPR_DEBUGIF_DMCONTROL_HARTSELLO_Pos (16UL) /*!< Position of HARTSELLO field.                                         */
95816   #define VPR_DEBUGIF_DMCONTROL_HARTSELLO_Msk (0x3FFUL << VPR_DEBUGIF_DMCONTROL_HARTSELLO_Pos) /*!< Bit mask of HARTSELLO
95817                                                                             field.*/
95818 
95819 /* HASEL @Bit 26 : Definition of currently selected harts. */
95820   #define VPR_DEBUGIF_DMCONTROL_HASEL_Pos (26UL)     /*!< Position of HASEL field.                                             */
95821   #define VPR_DEBUGIF_DMCONTROL_HASEL_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HASEL_Pos) /*!< Bit mask of HASEL field.             */
95822   #define VPR_DEBUGIF_DMCONTROL_HASEL_Min (0x0UL)    /*!< Min enumerator value of HASEL field.                                 */
95823   #define VPR_DEBUGIF_DMCONTROL_HASEL_Max (0x1UL)    /*!< Max enumerator value of HASEL field.                                 */
95824   #define VPR_DEBUGIF_DMCONTROL_HASEL_Single (0x0UL) /*!< Single hart selected.                                                */
95825   #define VPR_DEBUGIF_DMCONTROL_HASEL_Multiple (0x1UL) /*!< Multiple harts selected                                            */
95826 
95827 /* ACKHAVERESET @Bit 28 : Clear the havereset. */
95828   #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Pos (28UL) /*!< Position of ACKHAVERESET field.                                   */
95829   #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Pos) /*!< Bit mask of ACKHAVERESET
95830                                                                             field.*/
95831   #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Min (0x0UL) /*!< Min enumerator value of ACKHAVERESET field.                      */
95832   #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Max (0x1UL) /*!< Max enumerator value of ACKHAVERESET field.                      */
95833   #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_NoOperation (0x0UL) /*!< No operation when written 0.                             */
95834   #define VPR_DEBUGIF_DMCONTROL_ACKHAVERESET_Clear (0x1UL) /*!< Clears the havereset for selected harts.                       */
95835 
95836 /* HARTRESET @Bit 29 : Reset harts. */
95837   #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Pos (29UL) /*!< Position of HARTRESET field.                                         */
95838   #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HARTRESET_Pos) /*!< Bit mask of HARTRESET field. */
95839   #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Min (0x0UL) /*!< Min enumerator value of HARTRESET field.                            */
95840   #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Max (0x1UL) /*!< Max enumerator value of HARTRESET field.                            */
95841   #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Deasserted (0x0UL) /*!< Reset de-asserted.                                           */
95842   #define VPR_DEBUGIF_DMCONTROL_HARTRESET_Asserted (0x1UL) /*!< Reset asserted.                                                */
95843 
95844 /* RESUMEREQ @Bit 30 : Resume currently selected harts. */
95845   #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Pos (30UL) /*!< Position of RESUMEREQ field.                                         */
95846   #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Pos) /*!< Bit mask of RESUMEREQ field. */
95847   #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Min (0x0UL) /*!< Min enumerator value of RESUMEREQ field.                            */
95848   #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Max (0x1UL) /*!< Max enumerator value of RESUMEREQ field.                            */
95849   #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_NoOperation (0x0UL) /*!< No operation when written 0.                                */
95850   #define VPR_DEBUGIF_DMCONTROL_RESUMEREQ_Resumed (0x1UL) /*!< Currently selected harts resumed.                               */
95851 
95852 /* HALTREQ @Bit 31 : Halt currently selected harts. */
95853   #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Pos (31UL)   /*!< Position of HALTREQ field.                                           */
95854   #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMCONTROL_HALTREQ_Pos) /*!< Bit mask of HALTREQ field.       */
95855   #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Min (0x0UL)  /*!< Min enumerator value of HALTREQ field.                               */
95856   #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Max (0x1UL)  /*!< Max enumerator value of HALTREQ field.                               */
95857   #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Clear (0x0UL) /*!< Clears halt request bit for all currently selected harts.           */
95858   #define VPR_DEBUGIF_DMCONTROL_HALTREQ_Halt (0x1UL) /*!< Currently selected harts halted.                                     */
95859 
95860 
95861 /* VPR_DEBUGIF_DMSTATUS: Debug Module Status */
95862   #define VPR_DEBUGIF_DMSTATUS_ResetValue (0x00400082UL) /*!< Reset value of DMSTATUS register.                                */
95863 
95864 /* VERSION @Bits 0..3 : Version of the debug module. */
95865   #define VPR_DEBUGIF_DMSTATUS_VERSION_Pos (0UL)     /*!< Position of VERSION field.                                           */
95866   #define VPR_DEBUGIF_DMSTATUS_VERSION_Msk (0xFUL << VPR_DEBUGIF_DMSTATUS_VERSION_Pos) /*!< Bit mask of VERSION field.         */
95867   #define VPR_DEBUGIF_DMSTATUS_VERSION_Min (0x0UL)   /*!< Min enumerator value of VERSION field.                               */
95868   #define VPR_DEBUGIF_DMSTATUS_VERSION_Max (0xFUL)   /*!< Max enumerator value of VERSION field.                               */
95869   #define VPR_DEBUGIF_DMSTATUS_VERSION_NotPresent (0x0UL) /*!< Debug module not present.                                       */
95870   #define VPR_DEBUGIF_DMSTATUS_VERSION_V011 (0x1UL)  /*!< There is a Debug Module and it conforms to version 0.11 of this
95871                                                           specifcation.*/
95872   #define VPR_DEBUGIF_DMSTATUS_VERSION_V013 (0x2UL)  /*!< There is a Debug Module and it conforms to version 0.13 of this
95873                                                           specifcation.*/
95874   #define VPR_DEBUGIF_DMSTATUS_VERSION_NonConform (0xFUL) /*!< There is a Debug Module but it does not conform to any available
95875                                                                version of the spec.*/
95876 
95877 /* CONFSTRPTRVALID @Bit 4 : Configuration string. */
95878   #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Pos (4UL) /*!< Position of CONFSTRPTRVALID field.                               */
95879   #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Pos) /*!< Bit mask of
95880                                                                             CONFSTRPTRVALID field.*/
95881   #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Min (0x0UL) /*!< Min enumerator value of CONFSTRPTRVALID field.                 */
95882   #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Max (0x1UL) /*!< Max enumerator value of CONFSTRPTRVALID field.                 */
95883   #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_NotRelevant (0x0UL) /*!< The confstrptr0..confstrptr3 holds information which is
95884                                                                         not relevant to the configuration string.*/
95885   #define VPR_DEBUGIF_DMSTATUS_CONFSTRPTRVALID_Address (0x1UL) /*!< The confstrptr0..confstrptr3 holds the address of the
95886                                                                     configuration string.*/
95887 
95888 /* HASRESETHALTREQ @Bit 5 : Halt-on-reset support status. */
95889   #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Pos (5UL) /*!< Position of HASRESETHALTREQ field.                               */
95890   #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Pos) /*!< Bit mask of
95891                                                                             HASRESETHALTREQ field.*/
95892   #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Min (0x0UL) /*!< Min enumerator value of HASRESETHALTREQ field.                 */
95893   #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Max (0x1UL) /*!< Max enumerator value of HASRESETHALTREQ field.                 */
95894   #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_No (0x0UL) /*!< Halt-on-reset is supported.                                     */
95895   #define VPR_DEBUGIF_DMSTATUS_HASRESETHALTREQ_Yes (0x1UL) /*!< Halt-on-reset is not supported.                                */
95896 
95897 /* AUTHBUSY @Bit 6 : Authentication busy status. */
95898   #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Pos (6UL)    /*!< Position of AUTHBUSY field.                                          */
95899   #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Pos) /*!< Bit mask of AUTHBUSY field.      */
95900   #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Min (0x0UL)  /*!< Min enumerator value of AUTHBUSY field.                              */
95901   #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Max (0x1UL)  /*!< Max enumerator value of AUTHBUSY field.                              */
95902   #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_No (0x0UL)   /*!< The authentication module is ready.                                  */
95903   #define VPR_DEBUGIF_DMSTATUS_AUTHBUSY_Yes (0x1UL)  /*!< The authentication module is busy.                                   */
95904 
95905 /* AUTHENTICATED @Bit 7 : Authentication status. */
95906   #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Pos (7UL) /*!< Position of AUTHENTICATED field.                                   */
95907   #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Pos) /*!< Bit mask of
95908                                                                             AUTHENTICATED field.*/
95909   #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Min (0x0UL) /*!< Min enumerator value of AUTHENTICATED field.                     */
95910   #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Max (0x1UL) /*!< Max enumerator value of AUTHENTICATED field.                     */
95911   #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_No (0x0UL) /*!< Authentication required before using the debug module.            */
95912   #define VPR_DEBUGIF_DMSTATUS_AUTHENTICATED_Yes (0x1UL) /*!< Authentication passed.                                           */
95913 
95914 /* ANYHALTED @Bit 8 : Any currently selected harts halted status. */
95915   #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Pos (8UL)   /*!< Position of ANYHALTED field.                                         */
95916   #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYHALTED_Pos) /*!< Bit mask of ANYHALTED field.   */
95917   #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Min (0x0UL) /*!< Min enumerator value of ANYHALTED field.                             */
95918   #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Max (0x1UL) /*!< Max enumerator value of ANYHALTED field.                             */
95919   #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_No (0x0UL)  /*!< None of the currently selected harts halted.                         */
95920   #define VPR_DEBUGIF_DMSTATUS_ANYHALTED_Yes (0x1UL) /*!< Any of the currently selected harts halted.                          */
95921 
95922 /* ALLHALTED @Bit 9 : All currently selected harts halted status. */
95923   #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Pos (9UL)   /*!< Position of ALLHALTED field.                                         */
95924   #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLHALTED_Pos) /*!< Bit mask of ALLHALTED field.   */
95925   #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Min (0x0UL) /*!< Min enumerator value of ALLHALTED field.                             */
95926   #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Max (0x1UL) /*!< Max enumerator value of ALLHALTED field.                             */
95927   #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_No (0x0UL)  /*!< Not all of the currently selected harts halted.                      */
95928   #define VPR_DEBUGIF_DMSTATUS_ALLHALTED_Yes (0x1UL) /*!< All of the currently selected harts halted.                          */
95929 
95930 /* ANYRUNNING @Bit 10 : Any currently selected harts running status. */
95931   #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Pos (10UL) /*!< Position of ANYRUNNING field.                                        */
95932   #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Pos) /*!< Bit mask of ANYRUNNING field.*/
95933   #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Min (0x0UL) /*!< Min enumerator value of ANYRUNNING field.                           */
95934   #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Max (0x1UL) /*!< Max enumerator value of ANYRUNNING field.                           */
95935   #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_No (0x0UL) /*!< None of the currently selected harts running.                        */
95936   #define VPR_DEBUGIF_DMSTATUS_ANYRUNNING_Yes (0x1UL) /*!< Any of the currently selected harts running.                        */
95937 
95938 /* ALLRUNNING @Bit 11 : All currently selected harts running status. */
95939   #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Pos (11UL) /*!< Position of ALLRUNNING field.                                        */
95940   #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Pos) /*!< Bit mask of ALLRUNNING field.*/
95941   #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Min (0x0UL) /*!< Min enumerator value of ALLRUNNING field.                           */
95942   #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Max (0x1UL) /*!< Max enumerator value of ALLRUNNING field.                           */
95943   #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_No (0x0UL) /*!< Not all of the currently selected harts running.                     */
95944   #define VPR_DEBUGIF_DMSTATUS_ALLRUNNING_Yes (0x1UL) /*!< All of the currently selected harts running.                        */
95945 
95946 /* ANYUNAVAIL @Bit 12 : Any currently selected harts unavailable status. */
95947   #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Pos (12UL) /*!< Position of ANYUNAVAIL field.                                        */
95948   #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Pos) /*!< Bit mask of ANYUNAVAIL field.*/
95949   #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Min (0x0UL) /*!< Min enumerator value of ANYUNAVAIL field.                           */
95950   #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Max (0x1UL) /*!< Max enumerator value of ANYUNAVAIL field.                           */
95951   #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_No (0x0UL) /*!< None of the currently selected harts unavailable.                    */
95952   #define VPR_DEBUGIF_DMSTATUS_ANYUNAVAIL_Yes (0x1UL) /*!< Any of the currently selected harts unavailable.                    */
95953 
95954 /* ALLUNAVAIL @Bit 13 : All currently selected harts unavailable status. */
95955   #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Pos (13UL) /*!< Position of ALLUNAVAIL field.                                        */
95956   #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Pos) /*!< Bit mask of ALLUNAVAIL field.*/
95957   #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Min (0x0UL) /*!< Min enumerator value of ALLUNAVAIL field.                           */
95958   #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Max (0x1UL) /*!< Max enumerator value of ALLUNAVAIL field.                           */
95959   #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_No (0x0UL) /*!< Not all of the currently selected harts unavailable.                 */
95960   #define VPR_DEBUGIF_DMSTATUS_ALLUNAVAIL_Yes (0x1UL) /*!< All of the currently selected harts unavailable.                    */
95961 
95962 /* ANYNONEXISTENT @Bit 14 : Any currently selected harts nonexistent status. */
95963   #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Pos (14UL) /*!< Position of ANYNONEXISTENT field.                                */
95964   #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Pos) /*!< Bit mask of
95965                                                                             ANYNONEXISTENT field.*/
95966   #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Min (0x0UL) /*!< Min enumerator value of ANYNONEXISTENT field.                   */
95967   #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Max (0x1UL) /*!< Max enumerator value of ANYNONEXISTENT field.                   */
95968   #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_No (0x0UL) /*!< None of the currently selected harts nonexistent.                */
95969   #define VPR_DEBUGIF_DMSTATUS_ANYNONEXISTENT_Yes (0x1UL) /*!< Any of the currently selected harts nonexistent.                */
95970 
95971 /* ALLNONEXISTENT @Bit 15 : All currently selected harts nonexistent status. */
95972   #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Pos (15UL) /*!< Position of ALLNONEXISTENT field.                                */
95973   #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Pos) /*!< Bit mask of
95974                                                                             ALLNONEXISTENT field.*/
95975   #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Min (0x0UL) /*!< Min enumerator value of ALLNONEXISTENT field.                   */
95976   #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Max (0x1UL) /*!< Max enumerator value of ALLNONEXISTENT field.                   */
95977   #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_No (0x0UL) /*!< Not all of the currently selected harts nonexistent.             */
95978   #define VPR_DEBUGIF_DMSTATUS_ALLNONEXISTENT_Yes (0x1UL) /*!< All of the currently selected harts nonexistent.                */
95979 
95980 /* ANYRESUMEACK @Bit 16 : Any currently selected harts acknowledged last resume request. */
95981   #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Pos (16UL) /*!< Position of ANYRESUMEACK field.                                    */
95982   #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Pos) /*!< Bit mask of ANYRESUMEACK
95983                                                                             field.*/
95984   #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Min (0x0UL) /*!< Min enumerator value of ANYRESUMEACK field.                       */
95985   #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Max (0x1UL) /*!< Max enumerator value of ANYRESUMEACK field.                       */
95986   #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_No (0x0UL) /*!< None of the currently selected harts acknowledged last resume
95987                                                             request.*/
95988   #define VPR_DEBUGIF_DMSTATUS_ANYRESUMEACK_Yes (0x1UL) /*!< Any of the currently selected harts acknowledged last resume
95989                                                              request.*/
95990 
95991 /* ALLRESUMEACK @Bit 17 : All currently selected harts acknowledged last resume */
95992   #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Pos (17UL) /*!< Position of ALLRESUMEACK field.                                    */
95993   #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Pos) /*!< Bit mask of ALLRESUMEACK
95994                                                                             field.*/
95995   #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Min (0x0UL) /*!< Min enumerator value of ALLRESUMEACK field.                       */
95996   #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Max (0x1UL) /*!< Max enumerator value of ALLRESUMEACK field.                       */
95997   #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_No (0x0UL) /*!< Not all of the currently selected harts acknowledged last resume
95998                                                             request.*/
95999   #define VPR_DEBUGIF_DMSTATUS_ALLRESUMEACK_Yes (0x1UL) /*!< All of the currently selected harts acknowledged last resume
96000                                                              request.*/
96001 
96002 /* ANYHAVERESET @Bit 18 : Any currently selected harts have been reset and reset is not acknowledged. */
96003   #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Pos (18UL) /*!< Position of ANYHAVERESET field.                                    */
96004   #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Pos) /*!< Bit mask of ANYHAVERESET
96005                                                                             field.*/
96006   #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Min (0x0UL) /*!< Min enumerator value of ANYHAVERESET field.                       */
96007   #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Max (0x1UL) /*!< Max enumerator value of ANYHAVERESET field.                       */
96008   #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_No (0x0UL) /*!< None of the currently selected harts have been reset and reset is
96009                                                             not acknowledget.*/
96010   #define VPR_DEBUGIF_DMSTATUS_ANYHAVERESET_Yes (0x1UL) /*!< Any of the currently selected harts have been reset and reset is
96011                                                              not acknowledge.*/
96012 
96013 /* ALLHAVERESET @Bit 19 : All currently selected harts have been reset and reset is not acknowledge */
96014   #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Pos (19UL) /*!< Position of ALLHAVERESET field.                                    */
96015   #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Pos) /*!< Bit mask of ALLHAVERESET
96016                                                                             field.*/
96017   #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Min (0x0UL) /*!< Min enumerator value of ALLHAVERESET field.                       */
96018   #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Max (0x1UL) /*!< Max enumerator value of ALLHAVERESET field.                       */
96019   #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_No (0x0UL) /*!< Not all of the currently selected harts have been reset and reset is
96020                                                             not acknowledge.*/
96021   #define VPR_DEBUGIF_DMSTATUS_ALLHAVERESET_Yes (0x1UL) /*!< All of the currently selected harts have been reset and reset is
96022                                                              not acknowledge.*/
96023 
96024 /* IMPEBREAK @Bit 22 : Implicit ebreak instruction at the non-existent word immediately after the Program Buffer. */
96025   #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Pos (22UL)  /*!< Position of IMPEBREAK field.                                         */
96026   #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Msk (0x1UL << VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Pos) /*!< Bit mask of IMPEBREAK field.   */
96027   #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Min (0x0UL) /*!< Min enumerator value of IMPEBREAK field.                             */
96028   #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Max (0x1UL) /*!< Max enumerator value of IMPEBREAK field.                             */
96029   #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_No (0x0UL)  /*!< No implicit ebreak instruction.                                      */
96030   #define VPR_DEBUGIF_DMSTATUS_IMPEBREAK_Yes (0x1UL) /*!< Implicit ebreak instruction.                                         */
96031 
96032 
96033 /* VPR_DEBUGIF_HARTINFO: Hart Information */
96034   #define VPR_DEBUGIF_HARTINFO_ResetValue (0x00000000UL) /*!< Reset value of HARTINFO register.                                */
96035 
96036 /* DATAADDR @Bits 0..11 : Data Address */
96037   #define VPR_DEBUGIF_HARTINFO_DATAADDR_Pos (0UL)    /*!< Position of DATAADDR field.                                          */
96038   #define VPR_DEBUGIF_HARTINFO_DATAADDR_Msk (0xFFFUL << VPR_DEBUGIF_HARTINFO_DATAADDR_Pos) /*!< Bit mask of DATAADDR field.    */
96039   #define VPR_DEBUGIF_HARTINFO_DATAADDR_Min (0xFFFFFFFFFFFFF800UL) /*!< Min value of DATAADDR field.                           */
96040   #define VPR_DEBUGIF_HARTINFO_DATAADDR_Max (0x7FFUL) /*!< Max size of DATAADDR field.                                         */
96041 
96042 /* DATASIZE @Bits 12..15 : Data Size */
96043   #define VPR_DEBUGIF_HARTINFO_DATASIZE_Pos (12UL)   /*!< Position of DATASIZE field.                                          */
96044   #define VPR_DEBUGIF_HARTINFO_DATASIZE_Msk (0xFUL << VPR_DEBUGIF_HARTINFO_DATASIZE_Pos) /*!< Bit mask of DATASIZE field.      */
96045   #define VPR_DEBUGIF_HARTINFO_DATASIZE_Min (0x0UL)  /*!< Min value of DATASIZE field.                                         */
96046   #define VPR_DEBUGIF_HARTINFO_DATASIZE_Max (0xCUL)  /*!< Max size of DATASIZE field.                                          */
96047 
96048 /* DATAACCESS @Bit 16 : Data Access */
96049   #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Pos (16UL) /*!< Position of DATAACCESS field.                                        */
96050   #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Msk (0x1UL << VPR_DEBUGIF_HARTINFO_DATAACCESS_Pos) /*!< Bit mask of DATAACCESS field.*/
96051   #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Min (0x0UL) /*!< Min enumerator value of DATAACCESS field.                           */
96052   #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Max (0x1UL) /*!< Max enumerator value of DATAACCESS field.                           */
96053   #define VPR_DEBUGIF_HARTINFO_DATAACCESS_No (0x0UL) /*!< The data registers are shadowed in the hart by CSRs. Each CSR is DXLEN
96054                                                           bits in size, and corresponds to a single argument.*/
96055   #define VPR_DEBUGIF_HARTINFO_DATAACCESS_Yes (0x1UL) /*!< The data registers are shadowed in the hart's memory map. Each
96056                                                            register takes up 4 bytes in the memory map.*/
96057 
96058 /* NSCRATCH @Bits 20..23 : Number of dscratch registers */
96059   #define VPR_DEBUGIF_HARTINFO_NSCRATCH_Pos (20UL)   /*!< Position of NSCRATCH field.                                          */
96060   #define VPR_DEBUGIF_HARTINFO_NSCRATCH_Msk (0xFUL << VPR_DEBUGIF_HARTINFO_NSCRATCH_Pos) /*!< Bit mask of NSCRATCH field.      */
96061 
96062 
96063 /* VPR_DEBUGIF_HALTSUM1: Halt Summary 1 */
96064   #define VPR_DEBUGIF_HALTSUM1_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM1 register.                                */
96065 
96066 /* HALTSUM1 @Bits 0..31 : Halt Summary 1 */
96067   #define VPR_DEBUGIF_HALTSUM1_HALTSUM1_Pos (0UL)    /*!< Position of HALTSUM1 field.                                          */
96068   #define VPR_DEBUGIF_HALTSUM1_HALTSUM1_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM1_HALTSUM1_Pos) /*!< Bit mask of HALTSUM1
96069                                                                             field.*/
96070 
96071 
96072 /* VPR_DEBUGIF_HAWINDOWSEL: Hart Array Window Select */
96073   #define VPR_DEBUGIF_HAWINDOWSEL_ResetValue (0x00000000UL) /*!< Reset value of HAWINDOWSEL register.                          */
96074 
96075 /* HAWINDOWSEL @Bits 0..14 : The high bits of this field may be tied to 0, depending on how large the array mask register is.
96076                              E.g. on a system with 48 harts only bit 0 of this field may actually be writable. */
96077 
96078   #define VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Pos (0UL) /*!< Position of HAWINDOWSEL field.                                    */
96079   #define VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Msk (0x7FFFUL << VPR_DEBUGIF_HAWINDOWSEL_HAWINDOWSEL_Pos) /*!< Bit mask of
96080                                                                             HAWINDOWSEL field.*/
96081 
96082 
96083 /* VPR_DEBUGIF_HAWINDOW: Hart Array Window */
96084   #define VPR_DEBUGIF_HAWINDOW_ResetValue (0x00000000UL) /*!< Reset value of HAWINDOW register.                                */
96085 
96086 /* MASKDATA @Bits 0..31 : Mask data. */
96087   #define VPR_DEBUGIF_HAWINDOW_MASKDATA_Pos (0UL)    /*!< Position of MASKDATA field.                                          */
96088   #define VPR_DEBUGIF_HAWINDOW_MASKDATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HAWINDOW_MASKDATA_Pos) /*!< Bit mask of MASKDATA
96089                                                                             field.*/
96090 
96091 
96092 /* VPR_DEBUGIF_ABSTRACTCS: Abstract Control and Status */
96093   #define VPR_DEBUGIF_ABSTRACTCS_ResetValue (0x01000002UL) /*!< Reset value of ABSTRACTCS register.                            */
96094 
96095 /* DATACOUNT @Bits 0..3 : Number of data registers that are implemented as part of the abstract command interface. Valid sizes
96096                           are 1..12. */
96097 
96098   #define VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Pos (0UL) /*!< Position of DATACOUNT field.                                         */
96099   #define VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Msk (0xFUL << VPR_DEBUGIF_ABSTRACTCS_DATACOUNT_Pos) /*!< Bit mask of DATACOUNT
96100                                                                             field.*/
96101 
96102 /* CMDERR @Bits 8..10 : Command error when the abstract command fails. */
96103   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Pos (8UL)    /*!< Position of CMDERR field.                                            */
96104   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Msk (0x7UL << VPR_DEBUGIF_ABSTRACTCS_CMDERR_Pos) /*!< Bit mask of CMDERR field.        */
96105   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Min (0x0UL)  /*!< Min enumerator value of CMDERR field.                                */
96106   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Max (0x7UL)  /*!< Max enumerator value of CMDERR field.                                */
96107   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_NoError (0x0UL) /*!< No error.                                                         */
96108   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Busy (0x1UL) /*!< An abstract command was executing while command, abstractcs, or
96109                                                           abstractauto was written, or when one of the data or progbuf registers
96110                                                           was read or written. This status is only written if cmderr contains 0*/
96111   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_NotSupported (0x2UL) /*!< The requested command is notsupported, regardless of whether
96112                                                                   the hart is running or not.*/
96113   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Exception (0x3UL) /*!< An exception occurred while executing the command (e.g. while
96114                                                                executing theProgram Buffer).*/
96115   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_HaltResume (0x4UL) /*!< The abstract command couldn't execute because the hart wasn't in
96116                                                                 the required state (running/halted). or unavailable.*/
96117   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Bus (0x5UL)  /*!< The abstract command failed due to abus error (e.g. alignment, access
96118                                                           size, or timeout).*/
96119   #define VPR_DEBUGIF_ABSTRACTCS_CMDERR_Other (0x7UL) /*!< The command failed for another reason.                              */
96120 
96121 /* BUSY @Bit 12 : Abstract command execution status. */
96122   #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Pos (12UL)     /*!< Position of BUSY field.                                              */
96123   #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Msk (0x1UL << VPR_DEBUGIF_ABSTRACTCS_BUSY_Pos) /*!< Bit mask of BUSY field.              */
96124   #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Min (0x0UL)    /*!< Min enumerator value of BUSY field.                                  */
96125   #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Max (0x1UL)    /*!< Max enumerator value of BUSY field.                                  */
96126   #define VPR_DEBUGIF_ABSTRACTCS_BUSY_NotBusy (0x0UL) /*!< Not busy.                                                           */
96127   #define VPR_DEBUGIF_ABSTRACTCS_BUSY_Busy (0x1UL)   /*!< An abstract command is currently being executed. This bit is set as
96128                                                           soon as command is written, and is not cleared until that command has
96129                                                           completed.*/
96130 
96131 /* PROGBUFSIZE @Bits 24..28 : Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 1. */
96132   #define VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Pos (24UL) /*!< Position of PROGBUFSIZE field.                                    */
96133   #define VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Msk (0x1FUL << VPR_DEBUGIF_ABSTRACTCS_PROGBUFSIZE_Pos) /*!< Bit mask of PROGBUFSIZE
96134                                                                             field.*/
96135 
96136 
96137 /* VPR_DEBUGIF_ABSTRACTCMD: Abstract command */
96138   #define VPR_DEBUGIF_ABSTRACTCMD_ResetValue (0x00000000UL) /*!< Reset value of ABSTRACTCMD register.                          */
96139 
96140 /* CONTROL @Bits 0..23 : This Field is interpreted in a command specific manner, described for each abstract command. */
96141   #define VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Pos (0UL)  /*!< Position of CONTROL field.                                           */
96142   #define VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Msk (0xFFFFFFUL << VPR_DEBUGIF_ABSTRACTCMD_CONTROL_Pos) /*!< Bit mask of CONTROL
96143                                                                             field.*/
96144 
96145 /* CMDTYPE @Bits 24..31 : The type determines the overall functionality of this abstract command. */
96146   #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Pos (24UL) /*!< Position of CMDTYPE field.                                           */
96147   #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Msk (0xFFUL << VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Pos) /*!< Bit mask of CMDTYPE field.  */
96148   #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Min (0x0UL) /*!< Min enumerator value of CMDTYPE field.                              */
96149   #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_Max (0x2UL) /*!< Max enumerator value of CMDTYPE field.                              */
96150   #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_REGACCESS (0x00UL) /*!< Register Access Command                                      */
96151   #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_QUICKACCESS (0x01UL) /*!< Quick Access Command                                       */
96152   #define VPR_DEBUGIF_ABSTRACTCMD_CMDTYPE_MEMACCESS (0x02UL) /*!< Memory Access Command                                        */
96153 
96154 
96155 /* VPR_DEBUGIF_ABSTRACTAUTO: Abstract Command Autoexec */
96156   #define VPR_DEBUGIF_ABSTRACTAUTO_ResetValue (0x00000000UL) /*!< Reset value of ABSTRACTAUTO register.                        */
96157 
96158 /* AUTOEXECDATA @Bits 0..11 : When a bit in this field is 1, read or write accesses to the corresponding data word cause the
96159                               command in command to be executed again. */
96160 
96161   #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Pos (0UL) /*!< Position of AUTOEXECDATA field.                                 */
96162   #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Msk (0xFFFUL << VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECDATA_Pos) /*!< Bit mask of
96163                                                                             AUTOEXECDATA field.*/
96164 
96165 /* AUTOEXECPROGBUF @Bits 16..31 : When a bit in this field is 1, read or write accesses to the corresponding progbuf word cause
96166                                   the command in command to be executed again. */
96167 
96168   #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Pos (16UL) /*!< Position of AUTOEXECPROGBUF field.                          */
96169   #define VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Msk (0xFFFFUL << VPR_DEBUGIF_ABSTRACTAUTO_AUTOEXECPROGBUF_Pos) /*!< Bit mask
96170                                                                             of AUTOEXECPROGBUF field.*/
96171 
96172 
96173 /* VPR_DEBUGIF_CONFSTRPTR: Configuration String Pointer [n] */
96174   #define VPR_DEBUGIF_CONFSTRPTR_MaxCount (4UL)      /*!< Max size of CONFSTRPTR[4] array.                                     */
96175   #define VPR_DEBUGIF_CONFSTRPTR_MaxIndex (3UL)      /*!< Max index of CONFSTRPTR[4] array.                                    */
96176   #define VPR_DEBUGIF_CONFSTRPTR_MinIndex (0UL)      /*!< Min index of CONFSTRPTR[4] array.                                    */
96177   #define VPR_DEBUGIF_CONFSTRPTR_ResetValue (0x00000000UL) /*!< Reset value of CONFSTRPTR[4] register.                         */
96178 
96179 /* ADDR @Bits 0..31 : Address */
96180   #define VPR_DEBUGIF_CONFSTRPTR_ADDR_Pos (0UL)      /*!< Position of ADDR field.                                              */
96181   #define VPR_DEBUGIF_CONFSTRPTR_ADDR_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_CONFSTRPTR_ADDR_Pos) /*!< Bit mask of ADDR field.       */
96182 
96183 
96184 /* VPR_DEBUGIF_NEXTDM: Next Debug Module */
96185   #define VPR_DEBUGIF_NEXTDM_ResetValue (0x00000000UL) /*!< Reset value of NEXTDM register.                                    */
96186 
96187 /* ADDR @Bits 0..31 : Address */
96188   #define VPR_DEBUGIF_NEXTDM_ADDR_Pos (0UL)          /*!< Position of ADDR field.                                              */
96189   #define VPR_DEBUGIF_NEXTDM_ADDR_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_NEXTDM_ADDR_Pos) /*!< Bit mask of ADDR field.               */
96190 
96191 
96192 /* VPR_DEBUGIF_PROGBUF: Program Buffer [n] */
96193   #define VPR_DEBUGIF_PROGBUF_MaxCount (16UL)        /*!< Max size of PROGBUF[16] array.                                       */
96194   #define VPR_DEBUGIF_PROGBUF_MaxIndex (15UL)        /*!< Max index of PROGBUF[16] array.                                      */
96195   #define VPR_DEBUGIF_PROGBUF_MinIndex (0UL)         /*!< Min index of PROGBUF[16] array.                                      */
96196   #define VPR_DEBUGIF_PROGBUF_ResetValue (0x00000000UL) /*!< Reset value of PROGBUF[16] register.                              */
96197 
96198 /* DATA @Bits 0..31 : Data */
96199   #define VPR_DEBUGIF_PROGBUF_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
96200   #define VPR_DEBUGIF_PROGBUF_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_PROGBUF_DATA_Pos) /*!< Bit mask of DATA field.             */
96201 
96202 
96203 /* VPR_DEBUGIF_AUTHDATA: Authentication Data */
96204   #define VPR_DEBUGIF_AUTHDATA_ResetValue (0x00000000UL) /*!< Reset value of AUTHDATA register.                                */
96205 
96206 /* DATA @Bits 0..31 : Data */
96207   #define VPR_DEBUGIF_AUTHDATA_DATA_Pos (0UL)        /*!< Position of DATA field.                                              */
96208   #define VPR_DEBUGIF_AUTHDATA_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_AUTHDATA_DATA_Pos) /*!< Bit mask of DATA field.           */
96209 
96210 
96211 /* VPR_DEBUGIF_HALTSUM2: Halt Summary 2 */
96212   #define VPR_DEBUGIF_HALTSUM2_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM2 register.                                */
96213 
96214 /* HALTSUM2 @Bits 0..31 : Halt Summary 2 */
96215   #define VPR_DEBUGIF_HALTSUM2_HALTSUM2_Pos (0UL)    /*!< Position of HALTSUM2 field.                                          */
96216   #define VPR_DEBUGIF_HALTSUM2_HALTSUM2_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM2_HALTSUM2_Pos) /*!< Bit mask of HALTSUM2
96217                                                                             field.*/
96218 
96219 
96220 /* VPR_DEBUGIF_HALTSUM3: Halt Summary 3 */
96221   #define VPR_DEBUGIF_HALTSUM3_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM3 register.                                */
96222 
96223 /* HALTSUM3 @Bits 0..31 : Halt Summary 3 */
96224   #define VPR_DEBUGIF_HALTSUM3_HALTSUM3_Pos (0UL)    /*!< Position of HALTSUM3 field.                                          */
96225   #define VPR_DEBUGIF_HALTSUM3_HALTSUM3_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM3_HALTSUM3_Pos) /*!< Bit mask of HALTSUM3
96226                                                                             field.*/
96227 
96228 
96229 /* VPR_DEBUGIF_SBADDRESS3: System Bus Addres 127:96 */
96230   #define VPR_DEBUGIF_SBADDRESS3_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS3 register.                            */
96231 
96232 /* ADDRESS @Bits 0..31 : Accesses bits 127:96 of the physical address in sbaddress (if the system address bus is that wide). */
96233   #define VPR_DEBUGIF_SBADDRESS3_ADDRESS_Pos (0UL)   /*!< Position of ADDRESS field.                                           */
96234   #define VPR_DEBUGIF_SBADDRESS3_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS3_ADDRESS_Pos) /*!< Bit mask of ADDRESS
96235                                                                             field.*/
96236 
96237 
96238 /* VPR_DEBUGIF_SBCS: System Bus Access Control and Status */
96239   #define VPR_DEBUGIF_SBCS_ResetValue (0x20000000UL) /*!< Reset value of SBCS register.                                        */
96240 
96241 /* SBACCESS8 @Bit 0 : (unspecified) */
96242   #define VPR_DEBUGIF_SBCS_SBACCESS8_Pos (0UL)       /*!< Position of SBACCESS8 field.                                         */
96243   #define VPR_DEBUGIF_SBCS_SBACCESS8_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS8_Pos) /*!< Bit mask of SBACCESS8 field.           */
96244   #define VPR_DEBUGIF_SBCS_SBACCESS8_Min (0x1UL)     /*!< Min enumerator value of SBACCESS8 field.                             */
96245   #define VPR_DEBUGIF_SBCS_SBACCESS8_Max (0x1UL)     /*!< Max enumerator value of SBACCESS8 field.                             */
96246   #define VPR_DEBUGIF_SBCS_SBACCESS8_sbaccess8 (0x1UL) /*!< 8-bit system bus accesses are supported.                           */
96247 
96248 /* SBACCESS16 @Bit 1 : (unspecified) */
96249   #define VPR_DEBUGIF_SBCS_SBACCESS16_Pos (1UL)      /*!< Position of SBACCESS16 field.                                        */
96250   #define VPR_DEBUGIF_SBCS_SBACCESS16_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS16_Pos) /*!< Bit mask of SBACCESS16 field.        */
96251   #define VPR_DEBUGIF_SBCS_SBACCESS16_Min (0x1UL)    /*!< Min enumerator value of SBACCESS16 field.                            */
96252   #define VPR_DEBUGIF_SBCS_SBACCESS16_Max (0x1UL)    /*!< Max enumerator value of SBACCESS16 field.                            */
96253   #define VPR_DEBUGIF_SBCS_SBACCESS16_sbaccess16 (0x1UL) /*!< 16-bit system bus accesses are supported.                        */
96254 
96255 /* SBACCESS32 @Bit 2 : (unspecified) */
96256   #define VPR_DEBUGIF_SBCS_SBACCESS32_Pos (2UL)      /*!< Position of SBACCESS32 field.                                        */
96257   #define VPR_DEBUGIF_SBCS_SBACCESS32_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS32_Pos) /*!< Bit mask of SBACCESS32 field.        */
96258   #define VPR_DEBUGIF_SBCS_SBACCESS32_Min (0x1UL)    /*!< Min enumerator value of SBACCESS32 field.                            */
96259   #define VPR_DEBUGIF_SBCS_SBACCESS32_Max (0x1UL)    /*!< Max enumerator value of SBACCESS32 field.                            */
96260   #define VPR_DEBUGIF_SBCS_SBACCESS32_sbaccess32 (0x1UL) /*!< 32-bit system bus accesses are supported.                        */
96261 
96262 /* SBACCESS64 @Bit 3 : (unspecified) */
96263   #define VPR_DEBUGIF_SBCS_SBACCESS64_Pos (3UL)      /*!< Position of SBACCESS64 field.                                        */
96264   #define VPR_DEBUGIF_SBCS_SBACCESS64_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS64_Pos) /*!< Bit mask of SBACCESS64 field.        */
96265   #define VPR_DEBUGIF_SBCS_SBACCESS64_Min (0x1UL)    /*!< Min enumerator value of SBACCESS64 field.                            */
96266   #define VPR_DEBUGIF_SBCS_SBACCESS64_Max (0x1UL)    /*!< Max enumerator value of SBACCESS64 field.                            */
96267   #define VPR_DEBUGIF_SBCS_SBACCESS64_sbaccess64 (0x1UL) /*!< 64-bit system bus accesses are supported.                        */
96268 
96269 /* SBACCESS128 @Bit 4 : (unspecified) */
96270   #define VPR_DEBUGIF_SBCS_SBACCESS128_Pos (4UL)     /*!< Position of SBACCESS128 field.                                       */
96271   #define VPR_DEBUGIF_SBCS_SBACCESS128_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBACCESS128_Pos) /*!< Bit mask of SBACCESS128 field.     */
96272   #define VPR_DEBUGIF_SBCS_SBACCESS128_Min (0x1UL)   /*!< Min enumerator value of SBACCESS128 field.                           */
96273   #define VPR_DEBUGIF_SBCS_SBACCESS128_Max (0x1UL)   /*!< Max enumerator value of SBACCESS128 field.                           */
96274   #define VPR_DEBUGIF_SBCS_SBACCESS128_sbaccess128 (0x1UL) /*!< 128-bit system bus accesses are supported.                     */
96275 
96276 /* SBASIZE @Bits 5..11 : Width of system bus addresses in bits. (0 indicates there is no bus access support.) */
96277   #define VPR_DEBUGIF_SBCS_SBASIZE_Pos (5UL)         /*!< Position of SBASIZE field.                                           */
96278   #define VPR_DEBUGIF_SBCS_SBASIZE_Msk (0x7FUL << VPR_DEBUGIF_SBCS_SBASIZE_Pos) /*!< Bit mask of SBASIZE field.                */
96279 
96280 /* SBERROR @Bits 12..14 : (unspecified) */
96281   #define VPR_DEBUGIF_SBCS_SBERROR_Pos (12UL)        /*!< Position of SBERROR field.                                           */
96282   #define VPR_DEBUGIF_SBCS_SBERROR_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBERROR_Pos) /*!< Bit mask of SBERROR field.                 */
96283   #define VPR_DEBUGIF_SBCS_SBERROR_Min (0x0UL)       /*!< Min enumerator value of SBERROR field.                               */
96284   #define VPR_DEBUGIF_SBCS_SBERROR_Max (0x7UL)       /*!< Max enumerator value of SBERROR field.                               */
96285   #define VPR_DEBUGIF_SBCS_SBERROR_Normal (0x0UL)    /*!< There was no bus error.                                              */
96286   #define VPR_DEBUGIF_SBCS_SBERROR_Timeout (0x1UL)   /*!< There was a timeout.                                                 */
96287   #define VPR_DEBUGIF_SBCS_SBERROR_Address (0x2UL)   /*!< A bad address was accessed.                                          */
96288   #define VPR_DEBUGIF_SBCS_SBERROR_Alignment (0x3UL) /*!< There was an alignment error.                                        */
96289   #define VPR_DEBUGIF_SBCS_SBERROR_Size (0x4UL)      /*!< An access of unsupported size was requested.                         */
96290   #define VPR_DEBUGIF_SBCS_SBERROR_Other (0x7UL)     /*!< Other.                                                               */
96291 
96292 /* SBREADONDATA @Bit 15 : (unspecified) */
96293   #define VPR_DEBUGIF_SBCS_SBREADONDATA_Pos (15UL)   /*!< Position of SBREADONDATA field.                                      */
96294   #define VPR_DEBUGIF_SBCS_SBREADONDATA_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBREADONDATA_Pos) /*!< Bit mask of SBREADONDATA field.  */
96295   #define VPR_DEBUGIF_SBCS_SBREADONDATA_Min (0x1UL)  /*!< Min enumerator value of SBREADONDATA field.                          */
96296   #define VPR_DEBUGIF_SBCS_SBREADONDATA_Max (0x1UL)  /*!< Max enumerator value of SBREADONDATA field.                          */
96297   #define VPR_DEBUGIF_SBCS_SBREADONDATA_sbreadondata (0x1UL) /*!< Every read from sbdata0 automatically triggers a system bus
96298                                                                   read at the (possibly autoincremented) address.*/
96299 
96300 /* SBAUTOINCREMENT @Bit 16 : (unspecified) */
96301   #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Pos (16UL) /*!< Position of SBAUTOINCREMENT field.                                  */
96302   #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Pos) /*!< Bit mask of SBAUTOINCREMENT
96303                                                                             field.*/
96304   #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Min (0x1UL) /*!< Min enumerator value of SBAUTOINCREMENT field.                     */
96305   #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_Max (0x1UL) /*!< Max enumerator value of SBAUTOINCREMENT field.                     */
96306   #define VPR_DEBUGIF_SBCS_SBAUTOINCREMENT_sbautoincrement (0x1UL) /*!< sbaddress is incremented by the access size (in bytes)
96307                                                                         selected in sbaccess after every system bus access.*/
96308 
96309 /* SBACCESS @Bits 17..19 : (unspecified) */
96310   #define VPR_DEBUGIF_SBCS_SBACCESS_Pos (17UL)       /*!< Position of SBACCESS field.                                          */
96311   #define VPR_DEBUGIF_SBCS_SBACCESS_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBACCESS_Pos) /*!< Bit mask of SBACCESS field.              */
96312   #define VPR_DEBUGIF_SBCS_SBACCESS_Min (0x0UL)      /*!< Min enumerator value of SBACCESS field.                              */
96313   #define VPR_DEBUGIF_SBCS_SBACCESS_Max (0x4UL)      /*!< Max enumerator value of SBACCESS field.                              */
96314   #define VPR_DEBUGIF_SBCS_SBACCESS_size8 (0x0UL)    /*!< 8-bit.                                                               */
96315   #define VPR_DEBUGIF_SBCS_SBACCESS_size16 (0x1UL)   /*!< 16-bit.                                                              */
96316   #define VPR_DEBUGIF_SBCS_SBACCESS_size32 (0x2UL)   /*!< 32-bit.                                                              */
96317   #define VPR_DEBUGIF_SBCS_SBACCESS_size64 (0x3UL)   /*!< 64-bit.                                                              */
96318   #define VPR_DEBUGIF_SBCS_SBACCESS_size128 (0x4UL)  /*!< 128-bit.                                                             */
96319 
96320 /* SBREADONADDR @Bit 20 : (unspecified) */
96321   #define VPR_DEBUGIF_SBCS_SBREADONADDR_Pos (20UL)   /*!< Position of SBREADONADDR field.                                      */
96322   #define VPR_DEBUGIF_SBCS_SBREADONADDR_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBREADONADDR_Pos) /*!< Bit mask of SBREADONADDR field.  */
96323   #define VPR_DEBUGIF_SBCS_SBREADONADDR_Min (0x1UL)  /*!< Min enumerator value of SBREADONADDR field.                          */
96324   #define VPR_DEBUGIF_SBCS_SBREADONADDR_Max (0x1UL)  /*!< Max enumerator value of SBREADONADDR field.                          */
96325   #define VPR_DEBUGIF_SBCS_SBREADONADDR_sbreadonaddr (0x1UL) /*!< Every write to sbaddress0 automatically triggers a system bus
96326                                                                   read at the new address.*/
96327 
96328 /* SBBUSY @Bit 21 : (unspecified) */
96329   #define VPR_DEBUGIF_SBCS_SBBUSY_Pos (21UL)         /*!< Position of SBBUSY field.                                            */
96330   #define VPR_DEBUGIF_SBCS_SBBUSY_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBBUSY_Pos) /*!< Bit mask of SBBUSY field.                    */
96331   #define VPR_DEBUGIF_SBCS_SBBUSY_Min (0x0UL)        /*!< Min enumerator value of SBBUSY field.                                */
96332   #define VPR_DEBUGIF_SBCS_SBBUSY_Max (0x1UL)        /*!< Max enumerator value of SBBUSY field.                                */
96333   #define VPR_DEBUGIF_SBCS_SBBUSY_notbusy (0x0UL)    /*!< System bus master is not busy.                                       */
96334   #define VPR_DEBUGIF_SBCS_SBBUSY_busy (0x1UL)       /*!< System bus master is busy.                                           */
96335 
96336 /* SBBUSYERROR @Bit 22 : (unspecified) */
96337   #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Pos (22UL)    /*!< Position of SBBUSYERROR field.                                       */
96338   #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Msk (0x1UL << VPR_DEBUGIF_SBCS_SBBUSYERROR_Pos) /*!< Bit mask of SBBUSYERROR field.     */
96339   #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Min (0x0UL)   /*!< Min enumerator value of SBBUSYERROR field.                           */
96340   #define VPR_DEBUGIF_SBCS_SBBUSYERROR_Max (0x1UL)   /*!< Max enumerator value of SBBUSYERROR field.                           */
96341   #define VPR_DEBUGIF_SBCS_SBBUSYERROR_noerror (0x0UL) /*!< No error.                                                          */
96342   #define VPR_DEBUGIF_SBCS_SBBUSYERROR_error (0x1UL) /*!< Debugger access attempted while one in progress.                     */
96343 
96344 /* SBVERSION @Bits 29..31 : (unspecified) */
96345   #define VPR_DEBUGIF_SBCS_SBVERSION_Pos (29UL)      /*!< Position of SBVERSION field.                                         */
96346   #define VPR_DEBUGIF_SBCS_SBVERSION_Msk (0x7UL << VPR_DEBUGIF_SBCS_SBVERSION_Pos) /*!< Bit mask of SBVERSION field.           */
96347   #define VPR_DEBUGIF_SBCS_SBVERSION_Min (0x0UL)     /*!< Min enumerator value of SBVERSION field.                             */
96348   #define VPR_DEBUGIF_SBCS_SBVERSION_Max (0x1UL)     /*!< Max enumerator value of SBVERSION field.                             */
96349   #define VPR_DEBUGIF_SBCS_SBVERSION_version0 (0x0UL) /*!< The System Bus interface conforms to mainline drafts of thia RISC-V
96350                                                            External Debug Support spec older than 1 January, 2018.*/
96351   #define VPR_DEBUGIF_SBCS_SBVERSION_version1 (0x1UL) /*!< The System Bus interface conforms to RISC-V External Debug Support
96352                                                            version 0.14.0-DRAFT. Other values are reserved for future versions.*/
96353 
96354 
96355 /* VPR_DEBUGIF_SBADDRESS0: System Bus Addres 31:0 */
96356   #define VPR_DEBUGIF_SBADDRESS0_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS0 register.                            */
96357 
96358 /* ADDRESS @Bits 0..31 : Accesses bits 31:0 of the physical address in sbaddress. */
96359   #define VPR_DEBUGIF_SBADDRESS0_ADDRESS_Pos (0UL)   /*!< Position of ADDRESS field.                                           */
96360   #define VPR_DEBUGIF_SBADDRESS0_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS0_ADDRESS_Pos) /*!< Bit mask of ADDRESS
96361                                                                             field.*/
96362 
96363 
96364 /* VPR_DEBUGIF_SBADDRESS1: System Bus Addres 63:32 */
96365   #define VPR_DEBUGIF_SBADDRESS1_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS1 register.                            */
96366 
96367 /* ADDRESS @Bits 0..31 : Accesses bits 63:32 of the physical address in sbaddress (if the system address bus is that wide). */
96368   #define VPR_DEBUGIF_SBADDRESS1_ADDRESS_Pos (0UL)   /*!< Position of ADDRESS field.                                           */
96369   #define VPR_DEBUGIF_SBADDRESS1_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS1_ADDRESS_Pos) /*!< Bit mask of ADDRESS
96370                                                                             field.*/
96371 
96372 
96373 /* VPR_DEBUGIF_SBADDRESS2: System Bus Addres 95:64 */
96374   #define VPR_DEBUGIF_SBADDRESS2_ResetValue (0x00000000UL) /*!< Reset value of SBADDRESS2 register.                            */
96375 
96376 /* ADDRESS @Bits 0..31 : Accesses bits 95:64 of the physical address in sbaddress (if the system address bus is that wide). */
96377   #define VPR_DEBUGIF_SBADDRESS2_ADDRESS_Pos (0UL)   /*!< Position of ADDRESS field.                                           */
96378   #define VPR_DEBUGIF_SBADDRESS2_ADDRESS_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBADDRESS2_ADDRESS_Pos) /*!< Bit mask of ADDRESS
96379                                                                             field.*/
96380 
96381 
96382 /* VPR_DEBUGIF_SBDATA0: System Bus Data 31:0 */
96383   #define VPR_DEBUGIF_SBDATA0_ResetValue (0x00000000UL) /*!< Reset value of SBDATA0 register.                                  */
96384 
96385 /* DATA @Bits 0..31 : Accesses bits 31:0 of sbdata */
96386   #define VPR_DEBUGIF_SBDATA0_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
96387   #define VPR_DEBUGIF_SBDATA0_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA0_DATA_Pos) /*!< Bit mask of DATA field.             */
96388 
96389 
96390 /* VPR_DEBUGIF_SBDATA1: System Bus Data 63:32 */
96391   #define VPR_DEBUGIF_SBDATA1_ResetValue (0x00000000UL) /*!< Reset value of SBDATA1 register.                                  */
96392 
96393 /* DATA @Bits 0..31 : Accesses bits 63:32 of sbdata (if the system bus is that wide). */
96394   #define VPR_DEBUGIF_SBDATA1_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
96395   #define VPR_DEBUGIF_SBDATA1_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA1_DATA_Pos) /*!< Bit mask of DATA field.             */
96396 
96397 
96398 /* VPR_DEBUGIF_SBDATA2: System Bus Data 95:64 */
96399   #define VPR_DEBUGIF_SBDATA2_ResetValue (0x00000000UL) /*!< Reset value of SBDATA2 register.                                  */
96400 
96401 /* DATA @Bits 0..31 : Accesses bits 95:64 of sbdata (if the system bus is that wide). */
96402   #define VPR_DEBUGIF_SBDATA2_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
96403   #define VPR_DEBUGIF_SBDATA2_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA2_DATA_Pos) /*!< Bit mask of DATA field.             */
96404 
96405 
96406 /* VPR_DEBUGIF_SBDATA3: System Bus Data 127:96 */
96407   #define VPR_DEBUGIF_SBDATA3_ResetValue (0x00000000UL) /*!< Reset value of SBDATA3 register.                                  */
96408 
96409 /* DATA @Bits 0..31 : Accesses bits 127:96 of sbdata (if the system bus is that wide). */
96410   #define VPR_DEBUGIF_SBDATA3_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
96411   #define VPR_DEBUGIF_SBDATA3_DATA_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_SBDATA3_DATA_Pos) /*!< Bit mask of DATA field.             */
96412 
96413 
96414 /* VPR_DEBUGIF_HALTSUM0: Halt summary 0 */
96415   #define VPR_DEBUGIF_HALTSUM0_ResetValue (0x00000000UL) /*!< Reset value of HALTSUM0 register.                                */
96416 
96417 /* HALTSUM0 @Bits 0..31 : Halt summary 0 */
96418   #define VPR_DEBUGIF_HALTSUM0_HALTSUM0_Pos (0UL)    /*!< Position of HALTSUM0 field.                                          */
96419   #define VPR_DEBUGIF_HALTSUM0_HALTSUM0_Msk (0xFFFFFFFFUL << VPR_DEBUGIF_HALTSUM0_HALTSUM0_Pos) /*!< Bit mask of HALTSUM0
96420                                                                             field.*/
96421 
96422 
96423 /* ======================================================= Struct VPR ======================================================== */
96424 /**
96425   * @brief VPR peripheral registers
96426   */
96427   typedef struct {                                   /*!< VPR Structure                                                        */
96428     __OM uint32_t TASKS_TRIGGER[32];                 /*!< (@ 0x00000000) VPR task [n] register                                 */
96429     __IOM uint32_t SUBSCRIBE_TRIGGER[32];            /*!< (@ 0x00000080) Subscribe configuration for task TASKS_TRIGGER[n]     */
96430     __IOM uint32_t EVENTS_TRIGGERED[32];             /*!< (@ 0x00000100) VPR event [n] register                                */
96431     __IOM uint32_t PUBLISH_TRIGGERED[32];            /*!< (@ 0x00000180) Publish configuration for event EVENTS_TRIGGERED[n]   */
96432     __IM uint32_t RESERVED[64];
96433     __IOM uint32_t INTEN;                            /*!< (@ 0x00000300) Enable or disable interrupt                           */
96434     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
96435     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
96436     __IM uint32_t INTPEND;                           /*!< (@ 0x0000030C) Pending interrupts                                    */
96437     __IM uint32_t RESERVED1[60];
96438     __IOM NRF_VPR_DEBUGIF_Type DEBUGIF;              /*!< (@ 0x00000400) (unspecified)                                         */
96439     __IM uint32_t RESERVED2[191];
96440     __IOM uint32_t CPURUN;                           /*!< (@ 0x00000800) State of the CPU after a core reset                   */
96441     __IM uint32_t RESERVED3;
96442     __IOM uint32_t INITPC;                           /*!< (@ 0x00000808) Initial value of the PC at CPU start.                 */
96443   } NRF_VPR_Type;                                    /*!< Size = 2060 (0x80C)                                                  */
96444 
96445 /* VPR_TASKS_TRIGGER: VPR task [n] register */
96446   #define VPR_TASKS_TRIGGER_MaxCount (32UL)          /*!< Max size of TASKS_TRIGGER[32] array.                                 */
96447   #define VPR_TASKS_TRIGGER_MaxIndex (31UL)          /*!< Max index of TASKS_TRIGGER[32] array.                                */
96448   #define VPR_TASKS_TRIGGER_MinIndex (0UL)           /*!< Min index of TASKS_TRIGGER[32] array.                                */
96449   #define VPR_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register.                          */
96450 
96451 /* TASKS_TRIGGER @Bit 0 : VPR task [n] register */
96452   #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL)  /*!< Position of TASKS_TRIGGER field.                                     */
96453   #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << VPR_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER
96454                                                                             field.*/
96455   #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field.                        */
96456   #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field.                        */
96457   #define VPR_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task                                                    */
96458 
96459 
96460 /* VPR_SUBSCRIBE_TRIGGER: Subscribe configuration for task TASKS_TRIGGER[n] */
96461   #define VPR_SUBSCRIBE_TRIGGER_MaxCount (32UL)      /*!< Max size of SUBSCRIBE_TRIGGER[32] array.                             */
96462   #define VPR_SUBSCRIBE_TRIGGER_MaxIndex (31UL)      /*!< Max index of SUBSCRIBE_TRIGGER[32] array.                            */
96463   #define VPR_SUBSCRIBE_TRIGGER_MinIndex (0UL)       /*!< Min index of SUBSCRIBE_TRIGGER[32] array.                            */
96464   #define VPR_SUBSCRIBE_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_TRIGGER[32] register.                  */
96465 
96466 /* EN @Bit 31 : Subscription enable bit */
96467   #define VPR_SUBSCRIBE_TRIGGER_EN_Pos (31UL)        /*!< Position of EN field.                                                */
96468   #define VPR_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << VPR_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field.                      */
96469   #define VPR_SUBSCRIBE_TRIGGER_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
96470   #define VPR_SUBSCRIBE_TRIGGER_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
96471   #define VPR_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL)  /*!< Disable subscription                                                 */
96472   #define VPR_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL)   /*!< Enable subscription                                                  */
96473 
96474 
96475 /* VPR_EVENTS_TRIGGERED: VPR event [n] register */
96476   #define VPR_EVENTS_TRIGGERED_MaxCount (32UL)       /*!< Max size of EVENTS_TRIGGERED[32] array.                              */
96477   #define VPR_EVENTS_TRIGGERED_MaxIndex (31UL)       /*!< Max index of EVENTS_TRIGGERED[32] array.                             */
96478   #define VPR_EVENTS_TRIGGERED_MinIndex (0UL)        /*!< Min index of EVENTS_TRIGGERED[32] array.                             */
96479   #define VPR_EVENTS_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TRIGGERED[32] register.                    */
96480 
96481 /* EVENTS_TRIGGERED @Bit 0 : VPR event [n] register */
96482   #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field.                             */
96483   #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of
96484                                                                             EVENTS_TRIGGERED field.*/
96485   #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Min (0x0UL) /*!< Min enumerator value of EVENTS_TRIGGERED field.               */
96486   #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Max (0x1UL) /*!< Max enumerator value of EVENTS_TRIGGERED field.               */
96487   #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated                                  */
96488   #define VPR_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated                                         */
96489 
96490 
96491 /* VPR_PUBLISH_TRIGGERED: Publish configuration for event EVENTS_TRIGGERED[n] */
96492   #define VPR_PUBLISH_TRIGGERED_MaxCount (32UL)      /*!< Max size of PUBLISH_TRIGGERED[32] array.                             */
96493   #define VPR_PUBLISH_TRIGGERED_MaxIndex (31UL)      /*!< Max index of PUBLISH_TRIGGERED[32] array.                            */
96494   #define VPR_PUBLISH_TRIGGERED_MinIndex (0UL)       /*!< Min index of PUBLISH_TRIGGERED[32] array.                            */
96495   #define VPR_PUBLISH_TRIGGERED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TRIGGERED[32] register.                  */
96496 
96497 /* EN @Bit 31 : Publication enable bit */
96498   #define VPR_PUBLISH_TRIGGERED_EN_Pos (31UL)        /*!< Position of EN field.                                                */
96499   #define VPR_PUBLISH_TRIGGERED_EN_Msk (0x1UL << VPR_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field.                      */
96500   #define VPR_PUBLISH_TRIGGERED_EN_Min (0x0UL)       /*!< Min enumerator value of EN field.                                    */
96501   #define VPR_PUBLISH_TRIGGERED_EN_Max (0x1UL)       /*!< Max enumerator value of EN field.                                    */
96502   #define VPR_PUBLISH_TRIGGERED_EN_Disabled (0x0UL)  /*!< Disable publishing                                                   */
96503   #define VPR_PUBLISH_TRIGGERED_EN_Enabled (0x1UL)   /*!< Enable publishing                                                    */
96504 
96505 
96506 /* VPR_INTEN: Enable or disable interrupt */
96507   #define VPR_INTEN_ResetValue (0x00000000UL)        /*!< Reset value of INTEN register.                                       */
96508 
96509 /* TRIGGERED0 @Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
96510   #define VPR_INTEN_TRIGGERED0_Pos (0UL)             /*!< Position of TRIGGERED0 field.                                        */
96511   #define VPR_INTEN_TRIGGERED0_Msk (0x1UL << VPR_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                      */
96512   #define VPR_INTEN_TRIGGERED0_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED0 field.                            */
96513   #define VPR_INTEN_TRIGGERED0_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED0 field.                            */
96514   #define VPR_INTEN_TRIGGERED0_Disabled (0x0UL)      /*!< Disable                                                              */
96515   #define VPR_INTEN_TRIGGERED0_Enabled (0x1UL)       /*!< Enable                                                               */
96516 
96517 /* TRIGGERED1 @Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
96518   #define VPR_INTEN_TRIGGERED1_Pos (1UL)             /*!< Position of TRIGGERED1 field.                                        */
96519   #define VPR_INTEN_TRIGGERED1_Msk (0x1UL << VPR_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                      */
96520   #define VPR_INTEN_TRIGGERED1_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED1 field.                            */
96521   #define VPR_INTEN_TRIGGERED1_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED1 field.                            */
96522   #define VPR_INTEN_TRIGGERED1_Disabled (0x0UL)      /*!< Disable                                                              */
96523   #define VPR_INTEN_TRIGGERED1_Enabled (0x1UL)       /*!< Enable                                                               */
96524 
96525 /* TRIGGERED2 @Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
96526   #define VPR_INTEN_TRIGGERED2_Pos (2UL)             /*!< Position of TRIGGERED2 field.                                        */
96527   #define VPR_INTEN_TRIGGERED2_Msk (0x1UL << VPR_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                      */
96528   #define VPR_INTEN_TRIGGERED2_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED2 field.                            */
96529   #define VPR_INTEN_TRIGGERED2_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED2 field.                            */
96530   #define VPR_INTEN_TRIGGERED2_Disabled (0x0UL)      /*!< Disable                                                              */
96531   #define VPR_INTEN_TRIGGERED2_Enabled (0x1UL)       /*!< Enable                                                               */
96532 
96533 /* TRIGGERED3 @Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
96534   #define VPR_INTEN_TRIGGERED3_Pos (3UL)             /*!< Position of TRIGGERED3 field.                                        */
96535   #define VPR_INTEN_TRIGGERED3_Msk (0x1UL << VPR_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                      */
96536   #define VPR_INTEN_TRIGGERED3_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED3 field.                            */
96537   #define VPR_INTEN_TRIGGERED3_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED3 field.                            */
96538   #define VPR_INTEN_TRIGGERED3_Disabled (0x0UL)      /*!< Disable                                                              */
96539   #define VPR_INTEN_TRIGGERED3_Enabled (0x1UL)       /*!< Enable                                                               */
96540 
96541 /* TRIGGERED4 @Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
96542   #define VPR_INTEN_TRIGGERED4_Pos (4UL)             /*!< Position of TRIGGERED4 field.                                        */
96543   #define VPR_INTEN_TRIGGERED4_Msk (0x1UL << VPR_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                      */
96544   #define VPR_INTEN_TRIGGERED4_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED4 field.                            */
96545   #define VPR_INTEN_TRIGGERED4_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED4 field.                            */
96546   #define VPR_INTEN_TRIGGERED4_Disabled (0x0UL)      /*!< Disable                                                              */
96547   #define VPR_INTEN_TRIGGERED4_Enabled (0x1UL)       /*!< Enable                                                               */
96548 
96549 /* TRIGGERED5 @Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
96550   #define VPR_INTEN_TRIGGERED5_Pos (5UL)             /*!< Position of TRIGGERED5 field.                                        */
96551   #define VPR_INTEN_TRIGGERED5_Msk (0x1UL << VPR_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                      */
96552   #define VPR_INTEN_TRIGGERED5_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED5 field.                            */
96553   #define VPR_INTEN_TRIGGERED5_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED5 field.                            */
96554   #define VPR_INTEN_TRIGGERED5_Disabled (0x0UL)      /*!< Disable                                                              */
96555   #define VPR_INTEN_TRIGGERED5_Enabled (0x1UL)       /*!< Enable                                                               */
96556 
96557 /* TRIGGERED6 @Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
96558   #define VPR_INTEN_TRIGGERED6_Pos (6UL)             /*!< Position of TRIGGERED6 field.                                        */
96559   #define VPR_INTEN_TRIGGERED6_Msk (0x1UL << VPR_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                      */
96560   #define VPR_INTEN_TRIGGERED6_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED6 field.                            */
96561   #define VPR_INTEN_TRIGGERED6_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED6 field.                            */
96562   #define VPR_INTEN_TRIGGERED6_Disabled (0x0UL)      /*!< Disable                                                              */
96563   #define VPR_INTEN_TRIGGERED6_Enabled (0x1UL)       /*!< Enable                                                               */
96564 
96565 /* TRIGGERED7 @Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
96566   #define VPR_INTEN_TRIGGERED7_Pos (7UL)             /*!< Position of TRIGGERED7 field.                                        */
96567   #define VPR_INTEN_TRIGGERED7_Msk (0x1UL << VPR_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                      */
96568   #define VPR_INTEN_TRIGGERED7_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED7 field.                            */
96569   #define VPR_INTEN_TRIGGERED7_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED7 field.                            */
96570   #define VPR_INTEN_TRIGGERED7_Disabled (0x0UL)      /*!< Disable                                                              */
96571   #define VPR_INTEN_TRIGGERED7_Enabled (0x1UL)       /*!< Enable                                                               */
96572 
96573 /* TRIGGERED8 @Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
96574   #define VPR_INTEN_TRIGGERED8_Pos (8UL)             /*!< Position of TRIGGERED8 field.                                        */
96575   #define VPR_INTEN_TRIGGERED8_Msk (0x1UL << VPR_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                      */
96576   #define VPR_INTEN_TRIGGERED8_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED8 field.                            */
96577   #define VPR_INTEN_TRIGGERED8_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED8 field.                            */
96578   #define VPR_INTEN_TRIGGERED8_Disabled (0x0UL)      /*!< Disable                                                              */
96579   #define VPR_INTEN_TRIGGERED8_Enabled (0x1UL)       /*!< Enable                                                               */
96580 
96581 /* TRIGGERED9 @Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
96582   #define VPR_INTEN_TRIGGERED9_Pos (9UL)             /*!< Position of TRIGGERED9 field.                                        */
96583   #define VPR_INTEN_TRIGGERED9_Msk (0x1UL << VPR_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                      */
96584   #define VPR_INTEN_TRIGGERED9_Min (0x0UL)           /*!< Min enumerator value of TRIGGERED9 field.                            */
96585   #define VPR_INTEN_TRIGGERED9_Max (0x1UL)           /*!< Max enumerator value of TRIGGERED9 field.                            */
96586   #define VPR_INTEN_TRIGGERED9_Disabled (0x0UL)      /*!< Disable                                                              */
96587   #define VPR_INTEN_TRIGGERED9_Enabled (0x1UL)       /*!< Enable                                                               */
96588 
96589 /* TRIGGERED10 @Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
96590   #define VPR_INTEN_TRIGGERED10_Pos (10UL)           /*!< Position of TRIGGERED10 field.                                       */
96591   #define VPR_INTEN_TRIGGERED10_Msk (0x1UL << VPR_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.                   */
96592   #define VPR_INTEN_TRIGGERED10_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED10 field.                           */
96593   #define VPR_INTEN_TRIGGERED10_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED10 field.                           */
96594   #define VPR_INTEN_TRIGGERED10_Disabled (0x0UL)     /*!< Disable                                                              */
96595   #define VPR_INTEN_TRIGGERED10_Enabled (0x1UL)      /*!< Enable                                                               */
96596 
96597 /* TRIGGERED11 @Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
96598   #define VPR_INTEN_TRIGGERED11_Pos (11UL)           /*!< Position of TRIGGERED11 field.                                       */
96599   #define VPR_INTEN_TRIGGERED11_Msk (0x1UL << VPR_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.                   */
96600   #define VPR_INTEN_TRIGGERED11_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED11 field.                           */
96601   #define VPR_INTEN_TRIGGERED11_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED11 field.                           */
96602   #define VPR_INTEN_TRIGGERED11_Disabled (0x0UL)     /*!< Disable                                                              */
96603   #define VPR_INTEN_TRIGGERED11_Enabled (0x1UL)      /*!< Enable                                                               */
96604 
96605 /* TRIGGERED12 @Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
96606   #define VPR_INTEN_TRIGGERED12_Pos (12UL)           /*!< Position of TRIGGERED12 field.                                       */
96607   #define VPR_INTEN_TRIGGERED12_Msk (0x1UL << VPR_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.                   */
96608   #define VPR_INTEN_TRIGGERED12_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED12 field.                           */
96609   #define VPR_INTEN_TRIGGERED12_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED12 field.                           */
96610   #define VPR_INTEN_TRIGGERED12_Disabled (0x0UL)     /*!< Disable                                                              */
96611   #define VPR_INTEN_TRIGGERED12_Enabled (0x1UL)      /*!< Enable                                                               */
96612 
96613 /* TRIGGERED13 @Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
96614   #define VPR_INTEN_TRIGGERED13_Pos (13UL)           /*!< Position of TRIGGERED13 field.                                       */
96615   #define VPR_INTEN_TRIGGERED13_Msk (0x1UL << VPR_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.                   */
96616   #define VPR_INTEN_TRIGGERED13_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED13 field.                           */
96617   #define VPR_INTEN_TRIGGERED13_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED13 field.                           */
96618   #define VPR_INTEN_TRIGGERED13_Disabled (0x0UL)     /*!< Disable                                                              */
96619   #define VPR_INTEN_TRIGGERED13_Enabled (0x1UL)      /*!< Enable                                                               */
96620 
96621 /* TRIGGERED14 @Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
96622   #define VPR_INTEN_TRIGGERED14_Pos (14UL)           /*!< Position of TRIGGERED14 field.                                       */
96623   #define VPR_INTEN_TRIGGERED14_Msk (0x1UL << VPR_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.                   */
96624   #define VPR_INTEN_TRIGGERED14_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED14 field.                           */
96625   #define VPR_INTEN_TRIGGERED14_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED14 field.                           */
96626   #define VPR_INTEN_TRIGGERED14_Disabled (0x0UL)     /*!< Disable                                                              */
96627   #define VPR_INTEN_TRIGGERED14_Enabled (0x1UL)      /*!< Enable                                                               */
96628 
96629 /* TRIGGERED15 @Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
96630   #define VPR_INTEN_TRIGGERED15_Pos (15UL)           /*!< Position of TRIGGERED15 field.                                       */
96631   #define VPR_INTEN_TRIGGERED15_Msk (0x1UL << VPR_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.                   */
96632   #define VPR_INTEN_TRIGGERED15_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED15 field.                           */
96633   #define VPR_INTEN_TRIGGERED15_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED15 field.                           */
96634   #define VPR_INTEN_TRIGGERED15_Disabled (0x0UL)     /*!< Disable                                                              */
96635   #define VPR_INTEN_TRIGGERED15_Enabled (0x1UL)      /*!< Enable                                                               */
96636 
96637 /* TRIGGERED16 @Bit 16 : Enable or disable interrupt for event TRIGGERED[16] */
96638   #define VPR_INTEN_TRIGGERED16_Pos (16UL)           /*!< Position of TRIGGERED16 field.                                       */
96639   #define VPR_INTEN_TRIGGERED16_Msk (0x1UL << VPR_INTEN_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.                   */
96640   #define VPR_INTEN_TRIGGERED16_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED16 field.                           */
96641   #define VPR_INTEN_TRIGGERED16_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED16 field.                           */
96642   #define VPR_INTEN_TRIGGERED16_Disabled (0x0UL)     /*!< Disable                                                              */
96643   #define VPR_INTEN_TRIGGERED16_Enabled (0x1UL)      /*!< Enable                                                               */
96644 
96645 /* TRIGGERED17 @Bit 17 : Enable or disable interrupt for event TRIGGERED[17] */
96646   #define VPR_INTEN_TRIGGERED17_Pos (17UL)           /*!< Position of TRIGGERED17 field.                                       */
96647   #define VPR_INTEN_TRIGGERED17_Msk (0x1UL << VPR_INTEN_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.                   */
96648   #define VPR_INTEN_TRIGGERED17_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED17 field.                           */
96649   #define VPR_INTEN_TRIGGERED17_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED17 field.                           */
96650   #define VPR_INTEN_TRIGGERED17_Disabled (0x0UL)     /*!< Disable                                                              */
96651   #define VPR_INTEN_TRIGGERED17_Enabled (0x1UL)      /*!< Enable                                                               */
96652 
96653 /* TRIGGERED18 @Bit 18 : Enable or disable interrupt for event TRIGGERED[18] */
96654   #define VPR_INTEN_TRIGGERED18_Pos (18UL)           /*!< Position of TRIGGERED18 field.                                       */
96655   #define VPR_INTEN_TRIGGERED18_Msk (0x1UL << VPR_INTEN_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.                   */
96656   #define VPR_INTEN_TRIGGERED18_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED18 field.                           */
96657   #define VPR_INTEN_TRIGGERED18_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED18 field.                           */
96658   #define VPR_INTEN_TRIGGERED18_Disabled (0x0UL)     /*!< Disable                                                              */
96659   #define VPR_INTEN_TRIGGERED18_Enabled (0x1UL)      /*!< Enable                                                               */
96660 
96661 /* TRIGGERED19 @Bit 19 : Enable or disable interrupt for event TRIGGERED[19] */
96662   #define VPR_INTEN_TRIGGERED19_Pos (19UL)           /*!< Position of TRIGGERED19 field.                                       */
96663   #define VPR_INTEN_TRIGGERED19_Msk (0x1UL << VPR_INTEN_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.                   */
96664   #define VPR_INTEN_TRIGGERED19_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED19 field.                           */
96665   #define VPR_INTEN_TRIGGERED19_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED19 field.                           */
96666   #define VPR_INTEN_TRIGGERED19_Disabled (0x0UL)     /*!< Disable                                                              */
96667   #define VPR_INTEN_TRIGGERED19_Enabled (0x1UL)      /*!< Enable                                                               */
96668 
96669 /* TRIGGERED20 @Bit 20 : Enable or disable interrupt for event TRIGGERED[20] */
96670   #define VPR_INTEN_TRIGGERED20_Pos (20UL)           /*!< Position of TRIGGERED20 field.                                       */
96671   #define VPR_INTEN_TRIGGERED20_Msk (0x1UL << VPR_INTEN_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.                   */
96672   #define VPR_INTEN_TRIGGERED20_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED20 field.                           */
96673   #define VPR_INTEN_TRIGGERED20_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED20 field.                           */
96674   #define VPR_INTEN_TRIGGERED20_Disabled (0x0UL)     /*!< Disable                                                              */
96675   #define VPR_INTEN_TRIGGERED20_Enabled (0x1UL)      /*!< Enable                                                               */
96676 
96677 /* TRIGGERED21 @Bit 21 : Enable or disable interrupt for event TRIGGERED[21] */
96678   #define VPR_INTEN_TRIGGERED21_Pos (21UL)           /*!< Position of TRIGGERED21 field.                                       */
96679   #define VPR_INTEN_TRIGGERED21_Msk (0x1UL << VPR_INTEN_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.                   */
96680   #define VPR_INTEN_TRIGGERED21_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED21 field.                           */
96681   #define VPR_INTEN_TRIGGERED21_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED21 field.                           */
96682   #define VPR_INTEN_TRIGGERED21_Disabled (0x0UL)     /*!< Disable                                                              */
96683   #define VPR_INTEN_TRIGGERED21_Enabled (0x1UL)      /*!< Enable                                                               */
96684 
96685 /* TRIGGERED22 @Bit 22 : Enable or disable interrupt for event TRIGGERED[22] */
96686   #define VPR_INTEN_TRIGGERED22_Pos (22UL)           /*!< Position of TRIGGERED22 field.                                       */
96687   #define VPR_INTEN_TRIGGERED22_Msk (0x1UL << VPR_INTEN_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.                   */
96688   #define VPR_INTEN_TRIGGERED22_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED22 field.                           */
96689   #define VPR_INTEN_TRIGGERED22_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED22 field.                           */
96690   #define VPR_INTEN_TRIGGERED22_Disabled (0x0UL)     /*!< Disable                                                              */
96691   #define VPR_INTEN_TRIGGERED22_Enabled (0x1UL)      /*!< Enable                                                               */
96692 
96693 /* TRIGGERED23 @Bit 23 : Enable or disable interrupt for event TRIGGERED[23] */
96694   #define VPR_INTEN_TRIGGERED23_Pos (23UL)           /*!< Position of TRIGGERED23 field.                                       */
96695   #define VPR_INTEN_TRIGGERED23_Msk (0x1UL << VPR_INTEN_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.                   */
96696   #define VPR_INTEN_TRIGGERED23_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED23 field.                           */
96697   #define VPR_INTEN_TRIGGERED23_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED23 field.                           */
96698   #define VPR_INTEN_TRIGGERED23_Disabled (0x0UL)     /*!< Disable                                                              */
96699   #define VPR_INTEN_TRIGGERED23_Enabled (0x1UL)      /*!< Enable                                                               */
96700 
96701 /* TRIGGERED24 @Bit 24 : Enable or disable interrupt for event TRIGGERED[24] */
96702   #define VPR_INTEN_TRIGGERED24_Pos (24UL)           /*!< Position of TRIGGERED24 field.                                       */
96703   #define VPR_INTEN_TRIGGERED24_Msk (0x1UL << VPR_INTEN_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.                   */
96704   #define VPR_INTEN_TRIGGERED24_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED24 field.                           */
96705   #define VPR_INTEN_TRIGGERED24_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED24 field.                           */
96706   #define VPR_INTEN_TRIGGERED24_Disabled (0x0UL)     /*!< Disable                                                              */
96707   #define VPR_INTEN_TRIGGERED24_Enabled (0x1UL)      /*!< Enable                                                               */
96708 
96709 /* TRIGGERED25 @Bit 25 : Enable or disable interrupt for event TRIGGERED[25] */
96710   #define VPR_INTEN_TRIGGERED25_Pos (25UL)           /*!< Position of TRIGGERED25 field.                                       */
96711   #define VPR_INTEN_TRIGGERED25_Msk (0x1UL << VPR_INTEN_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.                   */
96712   #define VPR_INTEN_TRIGGERED25_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED25 field.                           */
96713   #define VPR_INTEN_TRIGGERED25_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED25 field.                           */
96714   #define VPR_INTEN_TRIGGERED25_Disabled (0x0UL)     /*!< Disable                                                              */
96715   #define VPR_INTEN_TRIGGERED25_Enabled (0x1UL)      /*!< Enable                                                               */
96716 
96717 /* TRIGGERED26 @Bit 26 : Enable or disable interrupt for event TRIGGERED[26] */
96718   #define VPR_INTEN_TRIGGERED26_Pos (26UL)           /*!< Position of TRIGGERED26 field.                                       */
96719   #define VPR_INTEN_TRIGGERED26_Msk (0x1UL << VPR_INTEN_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.                   */
96720   #define VPR_INTEN_TRIGGERED26_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED26 field.                           */
96721   #define VPR_INTEN_TRIGGERED26_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED26 field.                           */
96722   #define VPR_INTEN_TRIGGERED26_Disabled (0x0UL)     /*!< Disable                                                              */
96723   #define VPR_INTEN_TRIGGERED26_Enabled (0x1UL)      /*!< Enable                                                               */
96724 
96725 /* TRIGGERED27 @Bit 27 : Enable or disable interrupt for event TRIGGERED[27] */
96726   #define VPR_INTEN_TRIGGERED27_Pos (27UL)           /*!< Position of TRIGGERED27 field.                                       */
96727   #define VPR_INTEN_TRIGGERED27_Msk (0x1UL << VPR_INTEN_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.                   */
96728   #define VPR_INTEN_TRIGGERED27_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED27 field.                           */
96729   #define VPR_INTEN_TRIGGERED27_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED27 field.                           */
96730   #define VPR_INTEN_TRIGGERED27_Disabled (0x0UL)     /*!< Disable                                                              */
96731   #define VPR_INTEN_TRIGGERED27_Enabled (0x1UL)      /*!< Enable                                                               */
96732 
96733 /* TRIGGERED28 @Bit 28 : Enable or disable interrupt for event TRIGGERED[28] */
96734   #define VPR_INTEN_TRIGGERED28_Pos (28UL)           /*!< Position of TRIGGERED28 field.                                       */
96735   #define VPR_INTEN_TRIGGERED28_Msk (0x1UL << VPR_INTEN_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.                   */
96736   #define VPR_INTEN_TRIGGERED28_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED28 field.                           */
96737   #define VPR_INTEN_TRIGGERED28_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED28 field.                           */
96738   #define VPR_INTEN_TRIGGERED28_Disabled (0x0UL)     /*!< Disable                                                              */
96739   #define VPR_INTEN_TRIGGERED28_Enabled (0x1UL)      /*!< Enable                                                               */
96740 
96741 /* TRIGGERED29 @Bit 29 : Enable or disable interrupt for event TRIGGERED[29] */
96742   #define VPR_INTEN_TRIGGERED29_Pos (29UL)           /*!< Position of TRIGGERED29 field.                                       */
96743   #define VPR_INTEN_TRIGGERED29_Msk (0x1UL << VPR_INTEN_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.                   */
96744   #define VPR_INTEN_TRIGGERED29_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED29 field.                           */
96745   #define VPR_INTEN_TRIGGERED29_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED29 field.                           */
96746   #define VPR_INTEN_TRIGGERED29_Disabled (0x0UL)     /*!< Disable                                                              */
96747   #define VPR_INTEN_TRIGGERED29_Enabled (0x1UL)      /*!< Enable                                                               */
96748 
96749 /* TRIGGERED30 @Bit 30 : Enable or disable interrupt for event TRIGGERED[30] */
96750   #define VPR_INTEN_TRIGGERED30_Pos (30UL)           /*!< Position of TRIGGERED30 field.                                       */
96751   #define VPR_INTEN_TRIGGERED30_Msk (0x1UL << VPR_INTEN_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.                   */
96752   #define VPR_INTEN_TRIGGERED30_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED30 field.                           */
96753   #define VPR_INTEN_TRIGGERED30_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED30 field.                           */
96754   #define VPR_INTEN_TRIGGERED30_Disabled (0x0UL)     /*!< Disable                                                              */
96755   #define VPR_INTEN_TRIGGERED30_Enabled (0x1UL)      /*!< Enable                                                               */
96756 
96757 /* TRIGGERED31 @Bit 31 : Enable or disable interrupt for event TRIGGERED[31] */
96758   #define VPR_INTEN_TRIGGERED31_Pos (31UL)           /*!< Position of TRIGGERED31 field.                                       */
96759   #define VPR_INTEN_TRIGGERED31_Msk (0x1UL << VPR_INTEN_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.                   */
96760   #define VPR_INTEN_TRIGGERED31_Min (0x0UL)          /*!< Min enumerator value of TRIGGERED31 field.                           */
96761   #define VPR_INTEN_TRIGGERED31_Max (0x1UL)          /*!< Max enumerator value of TRIGGERED31 field.                           */
96762   #define VPR_INTEN_TRIGGERED31_Disabled (0x0UL)     /*!< Disable                                                              */
96763   #define VPR_INTEN_TRIGGERED31_Enabled (0x1UL)      /*!< Enable                                                               */
96764 
96765 
96766 /* VPR_INTENSET: Enable interrupt */
96767   #define VPR_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
96768 
96769 /* TRIGGERED0 @Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
96770   #define VPR_INTENSET_TRIGGERED0_Pos (0UL)          /*!< Position of TRIGGERED0 field.                                        */
96771   #define VPR_INTENSET_TRIGGERED0_Msk (0x1UL << VPR_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                */
96772   #define VPR_INTENSET_TRIGGERED0_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED0 field.                            */
96773   #define VPR_INTENSET_TRIGGERED0_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED0 field.                            */
96774   #define VPR_INTENSET_TRIGGERED0_Set (0x1UL)        /*!< Enable                                                               */
96775   #define VPR_INTENSET_TRIGGERED0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96776   #define VPR_INTENSET_TRIGGERED0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96777 
96778 /* TRIGGERED1 @Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
96779   #define VPR_INTENSET_TRIGGERED1_Pos (1UL)          /*!< Position of TRIGGERED1 field.                                        */
96780   #define VPR_INTENSET_TRIGGERED1_Msk (0x1UL << VPR_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                */
96781   #define VPR_INTENSET_TRIGGERED1_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED1 field.                            */
96782   #define VPR_INTENSET_TRIGGERED1_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED1 field.                            */
96783   #define VPR_INTENSET_TRIGGERED1_Set (0x1UL)        /*!< Enable                                                               */
96784   #define VPR_INTENSET_TRIGGERED1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96785   #define VPR_INTENSET_TRIGGERED1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96786 
96787 /* TRIGGERED2 @Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
96788   #define VPR_INTENSET_TRIGGERED2_Pos (2UL)          /*!< Position of TRIGGERED2 field.                                        */
96789   #define VPR_INTENSET_TRIGGERED2_Msk (0x1UL << VPR_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                */
96790   #define VPR_INTENSET_TRIGGERED2_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED2 field.                            */
96791   #define VPR_INTENSET_TRIGGERED2_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED2 field.                            */
96792   #define VPR_INTENSET_TRIGGERED2_Set (0x1UL)        /*!< Enable                                                               */
96793   #define VPR_INTENSET_TRIGGERED2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96794   #define VPR_INTENSET_TRIGGERED2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96795 
96796 /* TRIGGERED3 @Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
96797   #define VPR_INTENSET_TRIGGERED3_Pos (3UL)          /*!< Position of TRIGGERED3 field.                                        */
96798   #define VPR_INTENSET_TRIGGERED3_Msk (0x1UL << VPR_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                */
96799   #define VPR_INTENSET_TRIGGERED3_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED3 field.                            */
96800   #define VPR_INTENSET_TRIGGERED3_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED3 field.                            */
96801   #define VPR_INTENSET_TRIGGERED3_Set (0x1UL)        /*!< Enable                                                               */
96802   #define VPR_INTENSET_TRIGGERED3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96803   #define VPR_INTENSET_TRIGGERED3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96804 
96805 /* TRIGGERED4 @Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
96806   #define VPR_INTENSET_TRIGGERED4_Pos (4UL)          /*!< Position of TRIGGERED4 field.                                        */
96807   #define VPR_INTENSET_TRIGGERED4_Msk (0x1UL << VPR_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                */
96808   #define VPR_INTENSET_TRIGGERED4_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED4 field.                            */
96809   #define VPR_INTENSET_TRIGGERED4_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED4 field.                            */
96810   #define VPR_INTENSET_TRIGGERED4_Set (0x1UL)        /*!< Enable                                                               */
96811   #define VPR_INTENSET_TRIGGERED4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96812   #define VPR_INTENSET_TRIGGERED4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96813 
96814 /* TRIGGERED5 @Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
96815   #define VPR_INTENSET_TRIGGERED5_Pos (5UL)          /*!< Position of TRIGGERED5 field.                                        */
96816   #define VPR_INTENSET_TRIGGERED5_Msk (0x1UL << VPR_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                */
96817   #define VPR_INTENSET_TRIGGERED5_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED5 field.                            */
96818   #define VPR_INTENSET_TRIGGERED5_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED5 field.                            */
96819   #define VPR_INTENSET_TRIGGERED5_Set (0x1UL)        /*!< Enable                                                               */
96820   #define VPR_INTENSET_TRIGGERED5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96821   #define VPR_INTENSET_TRIGGERED5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96822 
96823 /* TRIGGERED6 @Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
96824   #define VPR_INTENSET_TRIGGERED6_Pos (6UL)          /*!< Position of TRIGGERED6 field.                                        */
96825   #define VPR_INTENSET_TRIGGERED6_Msk (0x1UL << VPR_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                */
96826   #define VPR_INTENSET_TRIGGERED6_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED6 field.                            */
96827   #define VPR_INTENSET_TRIGGERED6_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED6 field.                            */
96828   #define VPR_INTENSET_TRIGGERED6_Set (0x1UL)        /*!< Enable                                                               */
96829   #define VPR_INTENSET_TRIGGERED6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96830   #define VPR_INTENSET_TRIGGERED6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96831 
96832 /* TRIGGERED7 @Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
96833   #define VPR_INTENSET_TRIGGERED7_Pos (7UL)          /*!< Position of TRIGGERED7 field.                                        */
96834   #define VPR_INTENSET_TRIGGERED7_Msk (0x1UL << VPR_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                */
96835   #define VPR_INTENSET_TRIGGERED7_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED7 field.                            */
96836   #define VPR_INTENSET_TRIGGERED7_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED7 field.                            */
96837   #define VPR_INTENSET_TRIGGERED7_Set (0x1UL)        /*!< Enable                                                               */
96838   #define VPR_INTENSET_TRIGGERED7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96839   #define VPR_INTENSET_TRIGGERED7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96840 
96841 /* TRIGGERED8 @Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
96842   #define VPR_INTENSET_TRIGGERED8_Pos (8UL)          /*!< Position of TRIGGERED8 field.                                        */
96843   #define VPR_INTENSET_TRIGGERED8_Msk (0x1UL << VPR_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                */
96844   #define VPR_INTENSET_TRIGGERED8_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED8 field.                            */
96845   #define VPR_INTENSET_TRIGGERED8_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED8 field.                            */
96846   #define VPR_INTENSET_TRIGGERED8_Set (0x1UL)        /*!< Enable                                                               */
96847   #define VPR_INTENSET_TRIGGERED8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96848   #define VPR_INTENSET_TRIGGERED8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96849 
96850 /* TRIGGERED9 @Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
96851   #define VPR_INTENSET_TRIGGERED9_Pos (9UL)          /*!< Position of TRIGGERED9 field.                                        */
96852   #define VPR_INTENSET_TRIGGERED9_Msk (0x1UL << VPR_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                */
96853   #define VPR_INTENSET_TRIGGERED9_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED9 field.                            */
96854   #define VPR_INTENSET_TRIGGERED9_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED9 field.                            */
96855   #define VPR_INTENSET_TRIGGERED9_Set (0x1UL)        /*!< Enable                                                               */
96856   #define VPR_INTENSET_TRIGGERED9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
96857   #define VPR_INTENSET_TRIGGERED9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
96858 
96859 /* TRIGGERED10 @Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
96860   #define VPR_INTENSET_TRIGGERED10_Pos (10UL)        /*!< Position of TRIGGERED10 field.                                       */
96861   #define VPR_INTENSET_TRIGGERED10_Msk (0x1UL << VPR_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.             */
96862   #define VPR_INTENSET_TRIGGERED10_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED10 field.                           */
96863   #define VPR_INTENSET_TRIGGERED10_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED10 field.                           */
96864   #define VPR_INTENSET_TRIGGERED10_Set (0x1UL)       /*!< Enable                                                               */
96865   #define VPR_INTENSET_TRIGGERED10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96866   #define VPR_INTENSET_TRIGGERED10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96867 
96868 /* TRIGGERED11 @Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
96869   #define VPR_INTENSET_TRIGGERED11_Pos (11UL)        /*!< Position of TRIGGERED11 field.                                       */
96870   #define VPR_INTENSET_TRIGGERED11_Msk (0x1UL << VPR_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.             */
96871   #define VPR_INTENSET_TRIGGERED11_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED11 field.                           */
96872   #define VPR_INTENSET_TRIGGERED11_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED11 field.                           */
96873   #define VPR_INTENSET_TRIGGERED11_Set (0x1UL)       /*!< Enable                                                               */
96874   #define VPR_INTENSET_TRIGGERED11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96875   #define VPR_INTENSET_TRIGGERED11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96876 
96877 /* TRIGGERED12 @Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
96878   #define VPR_INTENSET_TRIGGERED12_Pos (12UL)        /*!< Position of TRIGGERED12 field.                                       */
96879   #define VPR_INTENSET_TRIGGERED12_Msk (0x1UL << VPR_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.             */
96880   #define VPR_INTENSET_TRIGGERED12_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED12 field.                           */
96881   #define VPR_INTENSET_TRIGGERED12_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED12 field.                           */
96882   #define VPR_INTENSET_TRIGGERED12_Set (0x1UL)       /*!< Enable                                                               */
96883   #define VPR_INTENSET_TRIGGERED12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96884   #define VPR_INTENSET_TRIGGERED12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96885 
96886 /* TRIGGERED13 @Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
96887   #define VPR_INTENSET_TRIGGERED13_Pos (13UL)        /*!< Position of TRIGGERED13 field.                                       */
96888   #define VPR_INTENSET_TRIGGERED13_Msk (0x1UL << VPR_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.             */
96889   #define VPR_INTENSET_TRIGGERED13_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED13 field.                           */
96890   #define VPR_INTENSET_TRIGGERED13_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED13 field.                           */
96891   #define VPR_INTENSET_TRIGGERED13_Set (0x1UL)       /*!< Enable                                                               */
96892   #define VPR_INTENSET_TRIGGERED13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96893   #define VPR_INTENSET_TRIGGERED13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96894 
96895 /* TRIGGERED14 @Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
96896   #define VPR_INTENSET_TRIGGERED14_Pos (14UL)        /*!< Position of TRIGGERED14 field.                                       */
96897   #define VPR_INTENSET_TRIGGERED14_Msk (0x1UL << VPR_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.             */
96898   #define VPR_INTENSET_TRIGGERED14_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED14 field.                           */
96899   #define VPR_INTENSET_TRIGGERED14_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED14 field.                           */
96900   #define VPR_INTENSET_TRIGGERED14_Set (0x1UL)       /*!< Enable                                                               */
96901   #define VPR_INTENSET_TRIGGERED14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96902   #define VPR_INTENSET_TRIGGERED14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96903 
96904 /* TRIGGERED15 @Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
96905   #define VPR_INTENSET_TRIGGERED15_Pos (15UL)        /*!< Position of TRIGGERED15 field.                                       */
96906   #define VPR_INTENSET_TRIGGERED15_Msk (0x1UL << VPR_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.             */
96907   #define VPR_INTENSET_TRIGGERED15_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED15 field.                           */
96908   #define VPR_INTENSET_TRIGGERED15_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED15 field.                           */
96909   #define VPR_INTENSET_TRIGGERED15_Set (0x1UL)       /*!< Enable                                                               */
96910   #define VPR_INTENSET_TRIGGERED15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96911   #define VPR_INTENSET_TRIGGERED15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96912 
96913 /* TRIGGERED16 @Bit 16 : Write '1' to enable interrupt for event TRIGGERED[16] */
96914   #define VPR_INTENSET_TRIGGERED16_Pos (16UL)        /*!< Position of TRIGGERED16 field.                                       */
96915   #define VPR_INTENSET_TRIGGERED16_Msk (0x1UL << VPR_INTENSET_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.             */
96916   #define VPR_INTENSET_TRIGGERED16_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED16 field.                           */
96917   #define VPR_INTENSET_TRIGGERED16_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED16 field.                           */
96918   #define VPR_INTENSET_TRIGGERED16_Set (0x1UL)       /*!< Enable                                                               */
96919   #define VPR_INTENSET_TRIGGERED16_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96920   #define VPR_INTENSET_TRIGGERED16_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96921 
96922 /* TRIGGERED17 @Bit 17 : Write '1' to enable interrupt for event TRIGGERED[17] */
96923   #define VPR_INTENSET_TRIGGERED17_Pos (17UL)        /*!< Position of TRIGGERED17 field.                                       */
96924   #define VPR_INTENSET_TRIGGERED17_Msk (0x1UL << VPR_INTENSET_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.             */
96925   #define VPR_INTENSET_TRIGGERED17_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED17 field.                           */
96926   #define VPR_INTENSET_TRIGGERED17_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED17 field.                           */
96927   #define VPR_INTENSET_TRIGGERED17_Set (0x1UL)       /*!< Enable                                                               */
96928   #define VPR_INTENSET_TRIGGERED17_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96929   #define VPR_INTENSET_TRIGGERED17_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96930 
96931 /* TRIGGERED18 @Bit 18 : Write '1' to enable interrupt for event TRIGGERED[18] */
96932   #define VPR_INTENSET_TRIGGERED18_Pos (18UL)        /*!< Position of TRIGGERED18 field.                                       */
96933   #define VPR_INTENSET_TRIGGERED18_Msk (0x1UL << VPR_INTENSET_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.             */
96934   #define VPR_INTENSET_TRIGGERED18_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED18 field.                           */
96935   #define VPR_INTENSET_TRIGGERED18_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED18 field.                           */
96936   #define VPR_INTENSET_TRIGGERED18_Set (0x1UL)       /*!< Enable                                                               */
96937   #define VPR_INTENSET_TRIGGERED18_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96938   #define VPR_INTENSET_TRIGGERED18_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96939 
96940 /* TRIGGERED19 @Bit 19 : Write '1' to enable interrupt for event TRIGGERED[19] */
96941   #define VPR_INTENSET_TRIGGERED19_Pos (19UL)        /*!< Position of TRIGGERED19 field.                                       */
96942   #define VPR_INTENSET_TRIGGERED19_Msk (0x1UL << VPR_INTENSET_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.             */
96943   #define VPR_INTENSET_TRIGGERED19_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED19 field.                           */
96944   #define VPR_INTENSET_TRIGGERED19_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED19 field.                           */
96945   #define VPR_INTENSET_TRIGGERED19_Set (0x1UL)       /*!< Enable                                                               */
96946   #define VPR_INTENSET_TRIGGERED19_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96947   #define VPR_INTENSET_TRIGGERED19_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96948 
96949 /* TRIGGERED20 @Bit 20 : Write '1' to enable interrupt for event TRIGGERED[20] */
96950   #define VPR_INTENSET_TRIGGERED20_Pos (20UL)        /*!< Position of TRIGGERED20 field.                                       */
96951   #define VPR_INTENSET_TRIGGERED20_Msk (0x1UL << VPR_INTENSET_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.             */
96952   #define VPR_INTENSET_TRIGGERED20_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED20 field.                           */
96953   #define VPR_INTENSET_TRIGGERED20_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED20 field.                           */
96954   #define VPR_INTENSET_TRIGGERED20_Set (0x1UL)       /*!< Enable                                                               */
96955   #define VPR_INTENSET_TRIGGERED20_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96956   #define VPR_INTENSET_TRIGGERED20_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96957 
96958 /* TRIGGERED21 @Bit 21 : Write '1' to enable interrupt for event TRIGGERED[21] */
96959   #define VPR_INTENSET_TRIGGERED21_Pos (21UL)        /*!< Position of TRIGGERED21 field.                                       */
96960   #define VPR_INTENSET_TRIGGERED21_Msk (0x1UL << VPR_INTENSET_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.             */
96961   #define VPR_INTENSET_TRIGGERED21_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED21 field.                           */
96962   #define VPR_INTENSET_TRIGGERED21_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED21 field.                           */
96963   #define VPR_INTENSET_TRIGGERED21_Set (0x1UL)       /*!< Enable                                                               */
96964   #define VPR_INTENSET_TRIGGERED21_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96965   #define VPR_INTENSET_TRIGGERED21_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96966 
96967 /* TRIGGERED22 @Bit 22 : Write '1' to enable interrupt for event TRIGGERED[22] */
96968   #define VPR_INTENSET_TRIGGERED22_Pos (22UL)        /*!< Position of TRIGGERED22 field.                                       */
96969   #define VPR_INTENSET_TRIGGERED22_Msk (0x1UL << VPR_INTENSET_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.             */
96970   #define VPR_INTENSET_TRIGGERED22_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED22 field.                           */
96971   #define VPR_INTENSET_TRIGGERED22_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED22 field.                           */
96972   #define VPR_INTENSET_TRIGGERED22_Set (0x1UL)       /*!< Enable                                                               */
96973   #define VPR_INTENSET_TRIGGERED22_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96974   #define VPR_INTENSET_TRIGGERED22_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96975 
96976 /* TRIGGERED23 @Bit 23 : Write '1' to enable interrupt for event TRIGGERED[23] */
96977   #define VPR_INTENSET_TRIGGERED23_Pos (23UL)        /*!< Position of TRIGGERED23 field.                                       */
96978   #define VPR_INTENSET_TRIGGERED23_Msk (0x1UL << VPR_INTENSET_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.             */
96979   #define VPR_INTENSET_TRIGGERED23_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED23 field.                           */
96980   #define VPR_INTENSET_TRIGGERED23_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED23 field.                           */
96981   #define VPR_INTENSET_TRIGGERED23_Set (0x1UL)       /*!< Enable                                                               */
96982   #define VPR_INTENSET_TRIGGERED23_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96983   #define VPR_INTENSET_TRIGGERED23_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96984 
96985 /* TRIGGERED24 @Bit 24 : Write '1' to enable interrupt for event TRIGGERED[24] */
96986   #define VPR_INTENSET_TRIGGERED24_Pos (24UL)        /*!< Position of TRIGGERED24 field.                                       */
96987   #define VPR_INTENSET_TRIGGERED24_Msk (0x1UL << VPR_INTENSET_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.             */
96988   #define VPR_INTENSET_TRIGGERED24_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED24 field.                           */
96989   #define VPR_INTENSET_TRIGGERED24_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED24 field.                           */
96990   #define VPR_INTENSET_TRIGGERED24_Set (0x1UL)       /*!< Enable                                                               */
96991   #define VPR_INTENSET_TRIGGERED24_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
96992   #define VPR_INTENSET_TRIGGERED24_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
96993 
96994 /* TRIGGERED25 @Bit 25 : Write '1' to enable interrupt for event TRIGGERED[25] */
96995   #define VPR_INTENSET_TRIGGERED25_Pos (25UL)        /*!< Position of TRIGGERED25 field.                                       */
96996   #define VPR_INTENSET_TRIGGERED25_Msk (0x1UL << VPR_INTENSET_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.             */
96997   #define VPR_INTENSET_TRIGGERED25_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED25 field.                           */
96998   #define VPR_INTENSET_TRIGGERED25_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED25 field.                           */
96999   #define VPR_INTENSET_TRIGGERED25_Set (0x1UL)       /*!< Enable                                                               */
97000   #define VPR_INTENSET_TRIGGERED25_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97001   #define VPR_INTENSET_TRIGGERED25_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97002 
97003 /* TRIGGERED26 @Bit 26 : Write '1' to enable interrupt for event TRIGGERED[26] */
97004   #define VPR_INTENSET_TRIGGERED26_Pos (26UL)        /*!< Position of TRIGGERED26 field.                                       */
97005   #define VPR_INTENSET_TRIGGERED26_Msk (0x1UL << VPR_INTENSET_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.             */
97006   #define VPR_INTENSET_TRIGGERED26_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED26 field.                           */
97007   #define VPR_INTENSET_TRIGGERED26_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED26 field.                           */
97008   #define VPR_INTENSET_TRIGGERED26_Set (0x1UL)       /*!< Enable                                                               */
97009   #define VPR_INTENSET_TRIGGERED26_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97010   #define VPR_INTENSET_TRIGGERED26_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97011 
97012 /* TRIGGERED27 @Bit 27 : Write '1' to enable interrupt for event TRIGGERED[27] */
97013   #define VPR_INTENSET_TRIGGERED27_Pos (27UL)        /*!< Position of TRIGGERED27 field.                                       */
97014   #define VPR_INTENSET_TRIGGERED27_Msk (0x1UL << VPR_INTENSET_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.             */
97015   #define VPR_INTENSET_TRIGGERED27_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED27 field.                           */
97016   #define VPR_INTENSET_TRIGGERED27_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED27 field.                           */
97017   #define VPR_INTENSET_TRIGGERED27_Set (0x1UL)       /*!< Enable                                                               */
97018   #define VPR_INTENSET_TRIGGERED27_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97019   #define VPR_INTENSET_TRIGGERED27_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97020 
97021 /* TRIGGERED28 @Bit 28 : Write '1' to enable interrupt for event TRIGGERED[28] */
97022   #define VPR_INTENSET_TRIGGERED28_Pos (28UL)        /*!< Position of TRIGGERED28 field.                                       */
97023   #define VPR_INTENSET_TRIGGERED28_Msk (0x1UL << VPR_INTENSET_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.             */
97024   #define VPR_INTENSET_TRIGGERED28_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED28 field.                           */
97025   #define VPR_INTENSET_TRIGGERED28_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED28 field.                           */
97026   #define VPR_INTENSET_TRIGGERED28_Set (0x1UL)       /*!< Enable                                                               */
97027   #define VPR_INTENSET_TRIGGERED28_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97028   #define VPR_INTENSET_TRIGGERED28_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97029 
97030 /* TRIGGERED29 @Bit 29 : Write '1' to enable interrupt for event TRIGGERED[29] */
97031   #define VPR_INTENSET_TRIGGERED29_Pos (29UL)        /*!< Position of TRIGGERED29 field.                                       */
97032   #define VPR_INTENSET_TRIGGERED29_Msk (0x1UL << VPR_INTENSET_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.             */
97033   #define VPR_INTENSET_TRIGGERED29_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED29 field.                           */
97034   #define VPR_INTENSET_TRIGGERED29_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED29 field.                           */
97035   #define VPR_INTENSET_TRIGGERED29_Set (0x1UL)       /*!< Enable                                                               */
97036   #define VPR_INTENSET_TRIGGERED29_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97037   #define VPR_INTENSET_TRIGGERED29_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97038 
97039 /* TRIGGERED30 @Bit 30 : Write '1' to enable interrupt for event TRIGGERED[30] */
97040   #define VPR_INTENSET_TRIGGERED30_Pos (30UL)        /*!< Position of TRIGGERED30 field.                                       */
97041   #define VPR_INTENSET_TRIGGERED30_Msk (0x1UL << VPR_INTENSET_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.             */
97042   #define VPR_INTENSET_TRIGGERED30_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED30 field.                           */
97043   #define VPR_INTENSET_TRIGGERED30_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED30 field.                           */
97044   #define VPR_INTENSET_TRIGGERED30_Set (0x1UL)       /*!< Enable                                                               */
97045   #define VPR_INTENSET_TRIGGERED30_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97046   #define VPR_INTENSET_TRIGGERED30_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97047 
97048 /* TRIGGERED31 @Bit 31 : Write '1' to enable interrupt for event TRIGGERED[31] */
97049   #define VPR_INTENSET_TRIGGERED31_Pos (31UL)        /*!< Position of TRIGGERED31 field.                                       */
97050   #define VPR_INTENSET_TRIGGERED31_Msk (0x1UL << VPR_INTENSET_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.             */
97051   #define VPR_INTENSET_TRIGGERED31_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED31 field.                           */
97052   #define VPR_INTENSET_TRIGGERED31_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED31 field.                           */
97053   #define VPR_INTENSET_TRIGGERED31_Set (0x1UL)       /*!< Enable                                                               */
97054   #define VPR_INTENSET_TRIGGERED31_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97055   #define VPR_INTENSET_TRIGGERED31_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97056 
97057 
97058 /* VPR_INTENCLR: Disable interrupt */
97059   #define VPR_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
97060 
97061 /* TRIGGERED0 @Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
97062   #define VPR_INTENCLR_TRIGGERED0_Pos (0UL)          /*!< Position of TRIGGERED0 field.                                        */
97063   #define VPR_INTENCLR_TRIGGERED0_Msk (0x1UL << VPR_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                */
97064   #define VPR_INTENCLR_TRIGGERED0_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED0 field.                            */
97065   #define VPR_INTENCLR_TRIGGERED0_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED0 field.                            */
97066   #define VPR_INTENCLR_TRIGGERED0_Clear (0x1UL)      /*!< Disable                                                              */
97067   #define VPR_INTENCLR_TRIGGERED0_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97068   #define VPR_INTENCLR_TRIGGERED0_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97069 
97070 /* TRIGGERED1 @Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
97071   #define VPR_INTENCLR_TRIGGERED1_Pos (1UL)          /*!< Position of TRIGGERED1 field.                                        */
97072   #define VPR_INTENCLR_TRIGGERED1_Msk (0x1UL << VPR_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                */
97073   #define VPR_INTENCLR_TRIGGERED1_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED1 field.                            */
97074   #define VPR_INTENCLR_TRIGGERED1_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED1 field.                            */
97075   #define VPR_INTENCLR_TRIGGERED1_Clear (0x1UL)      /*!< Disable                                                              */
97076   #define VPR_INTENCLR_TRIGGERED1_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97077   #define VPR_INTENCLR_TRIGGERED1_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97078 
97079 /* TRIGGERED2 @Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
97080   #define VPR_INTENCLR_TRIGGERED2_Pos (2UL)          /*!< Position of TRIGGERED2 field.                                        */
97081   #define VPR_INTENCLR_TRIGGERED2_Msk (0x1UL << VPR_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                */
97082   #define VPR_INTENCLR_TRIGGERED2_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED2 field.                            */
97083   #define VPR_INTENCLR_TRIGGERED2_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED2 field.                            */
97084   #define VPR_INTENCLR_TRIGGERED2_Clear (0x1UL)      /*!< Disable                                                              */
97085   #define VPR_INTENCLR_TRIGGERED2_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97086   #define VPR_INTENCLR_TRIGGERED2_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97087 
97088 /* TRIGGERED3 @Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
97089   #define VPR_INTENCLR_TRIGGERED3_Pos (3UL)          /*!< Position of TRIGGERED3 field.                                        */
97090   #define VPR_INTENCLR_TRIGGERED3_Msk (0x1UL << VPR_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                */
97091   #define VPR_INTENCLR_TRIGGERED3_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED3 field.                            */
97092   #define VPR_INTENCLR_TRIGGERED3_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED3 field.                            */
97093   #define VPR_INTENCLR_TRIGGERED3_Clear (0x1UL)      /*!< Disable                                                              */
97094   #define VPR_INTENCLR_TRIGGERED3_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97095   #define VPR_INTENCLR_TRIGGERED3_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97096 
97097 /* TRIGGERED4 @Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
97098   #define VPR_INTENCLR_TRIGGERED4_Pos (4UL)          /*!< Position of TRIGGERED4 field.                                        */
97099   #define VPR_INTENCLR_TRIGGERED4_Msk (0x1UL << VPR_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                */
97100   #define VPR_INTENCLR_TRIGGERED4_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED4 field.                            */
97101   #define VPR_INTENCLR_TRIGGERED4_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED4 field.                            */
97102   #define VPR_INTENCLR_TRIGGERED4_Clear (0x1UL)      /*!< Disable                                                              */
97103   #define VPR_INTENCLR_TRIGGERED4_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97104   #define VPR_INTENCLR_TRIGGERED4_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97105 
97106 /* TRIGGERED5 @Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
97107   #define VPR_INTENCLR_TRIGGERED5_Pos (5UL)          /*!< Position of TRIGGERED5 field.                                        */
97108   #define VPR_INTENCLR_TRIGGERED5_Msk (0x1UL << VPR_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                */
97109   #define VPR_INTENCLR_TRIGGERED5_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED5 field.                            */
97110   #define VPR_INTENCLR_TRIGGERED5_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED5 field.                            */
97111   #define VPR_INTENCLR_TRIGGERED5_Clear (0x1UL)      /*!< Disable                                                              */
97112   #define VPR_INTENCLR_TRIGGERED5_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97113   #define VPR_INTENCLR_TRIGGERED5_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97114 
97115 /* TRIGGERED6 @Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
97116   #define VPR_INTENCLR_TRIGGERED6_Pos (6UL)          /*!< Position of TRIGGERED6 field.                                        */
97117   #define VPR_INTENCLR_TRIGGERED6_Msk (0x1UL << VPR_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                */
97118   #define VPR_INTENCLR_TRIGGERED6_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED6 field.                            */
97119   #define VPR_INTENCLR_TRIGGERED6_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED6 field.                            */
97120   #define VPR_INTENCLR_TRIGGERED6_Clear (0x1UL)      /*!< Disable                                                              */
97121   #define VPR_INTENCLR_TRIGGERED6_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97122   #define VPR_INTENCLR_TRIGGERED6_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97123 
97124 /* TRIGGERED7 @Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
97125   #define VPR_INTENCLR_TRIGGERED7_Pos (7UL)          /*!< Position of TRIGGERED7 field.                                        */
97126   #define VPR_INTENCLR_TRIGGERED7_Msk (0x1UL << VPR_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                */
97127   #define VPR_INTENCLR_TRIGGERED7_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED7 field.                            */
97128   #define VPR_INTENCLR_TRIGGERED7_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED7 field.                            */
97129   #define VPR_INTENCLR_TRIGGERED7_Clear (0x1UL)      /*!< Disable                                                              */
97130   #define VPR_INTENCLR_TRIGGERED7_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97131   #define VPR_INTENCLR_TRIGGERED7_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97132 
97133 /* TRIGGERED8 @Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
97134   #define VPR_INTENCLR_TRIGGERED8_Pos (8UL)          /*!< Position of TRIGGERED8 field.                                        */
97135   #define VPR_INTENCLR_TRIGGERED8_Msk (0x1UL << VPR_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                */
97136   #define VPR_INTENCLR_TRIGGERED8_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED8 field.                            */
97137   #define VPR_INTENCLR_TRIGGERED8_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED8 field.                            */
97138   #define VPR_INTENCLR_TRIGGERED8_Clear (0x1UL)      /*!< Disable                                                              */
97139   #define VPR_INTENCLR_TRIGGERED8_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97140   #define VPR_INTENCLR_TRIGGERED8_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97141 
97142 /* TRIGGERED9 @Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
97143   #define VPR_INTENCLR_TRIGGERED9_Pos (9UL)          /*!< Position of TRIGGERED9 field.                                        */
97144   #define VPR_INTENCLR_TRIGGERED9_Msk (0x1UL << VPR_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                */
97145   #define VPR_INTENCLR_TRIGGERED9_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED9 field.                            */
97146   #define VPR_INTENCLR_TRIGGERED9_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED9 field.                            */
97147   #define VPR_INTENCLR_TRIGGERED9_Clear (0x1UL)      /*!< Disable                                                              */
97148   #define VPR_INTENCLR_TRIGGERED9_Disabled (0x0UL)   /*!< Read: Disabled                                                       */
97149   #define VPR_INTENCLR_TRIGGERED9_Enabled (0x1UL)    /*!< Read: Enabled                                                        */
97150 
97151 /* TRIGGERED10 @Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
97152   #define VPR_INTENCLR_TRIGGERED10_Pos (10UL)        /*!< Position of TRIGGERED10 field.                                       */
97153   #define VPR_INTENCLR_TRIGGERED10_Msk (0x1UL << VPR_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.             */
97154   #define VPR_INTENCLR_TRIGGERED10_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED10 field.                           */
97155   #define VPR_INTENCLR_TRIGGERED10_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED10 field.                           */
97156   #define VPR_INTENCLR_TRIGGERED10_Clear (0x1UL)     /*!< Disable                                                              */
97157   #define VPR_INTENCLR_TRIGGERED10_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97158   #define VPR_INTENCLR_TRIGGERED10_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97159 
97160 /* TRIGGERED11 @Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
97161   #define VPR_INTENCLR_TRIGGERED11_Pos (11UL)        /*!< Position of TRIGGERED11 field.                                       */
97162   #define VPR_INTENCLR_TRIGGERED11_Msk (0x1UL << VPR_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.             */
97163   #define VPR_INTENCLR_TRIGGERED11_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED11 field.                           */
97164   #define VPR_INTENCLR_TRIGGERED11_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED11 field.                           */
97165   #define VPR_INTENCLR_TRIGGERED11_Clear (0x1UL)     /*!< Disable                                                              */
97166   #define VPR_INTENCLR_TRIGGERED11_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97167   #define VPR_INTENCLR_TRIGGERED11_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97168 
97169 /* TRIGGERED12 @Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
97170   #define VPR_INTENCLR_TRIGGERED12_Pos (12UL)        /*!< Position of TRIGGERED12 field.                                       */
97171   #define VPR_INTENCLR_TRIGGERED12_Msk (0x1UL << VPR_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.             */
97172   #define VPR_INTENCLR_TRIGGERED12_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED12 field.                           */
97173   #define VPR_INTENCLR_TRIGGERED12_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED12 field.                           */
97174   #define VPR_INTENCLR_TRIGGERED12_Clear (0x1UL)     /*!< Disable                                                              */
97175   #define VPR_INTENCLR_TRIGGERED12_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97176   #define VPR_INTENCLR_TRIGGERED12_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97177 
97178 /* TRIGGERED13 @Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
97179   #define VPR_INTENCLR_TRIGGERED13_Pos (13UL)        /*!< Position of TRIGGERED13 field.                                       */
97180   #define VPR_INTENCLR_TRIGGERED13_Msk (0x1UL << VPR_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.             */
97181   #define VPR_INTENCLR_TRIGGERED13_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED13 field.                           */
97182   #define VPR_INTENCLR_TRIGGERED13_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED13 field.                           */
97183   #define VPR_INTENCLR_TRIGGERED13_Clear (0x1UL)     /*!< Disable                                                              */
97184   #define VPR_INTENCLR_TRIGGERED13_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97185   #define VPR_INTENCLR_TRIGGERED13_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97186 
97187 /* TRIGGERED14 @Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
97188   #define VPR_INTENCLR_TRIGGERED14_Pos (14UL)        /*!< Position of TRIGGERED14 field.                                       */
97189   #define VPR_INTENCLR_TRIGGERED14_Msk (0x1UL << VPR_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.             */
97190   #define VPR_INTENCLR_TRIGGERED14_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED14 field.                           */
97191   #define VPR_INTENCLR_TRIGGERED14_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED14 field.                           */
97192   #define VPR_INTENCLR_TRIGGERED14_Clear (0x1UL)     /*!< Disable                                                              */
97193   #define VPR_INTENCLR_TRIGGERED14_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97194   #define VPR_INTENCLR_TRIGGERED14_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97195 
97196 /* TRIGGERED15 @Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
97197   #define VPR_INTENCLR_TRIGGERED15_Pos (15UL)        /*!< Position of TRIGGERED15 field.                                       */
97198   #define VPR_INTENCLR_TRIGGERED15_Msk (0x1UL << VPR_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.             */
97199   #define VPR_INTENCLR_TRIGGERED15_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED15 field.                           */
97200   #define VPR_INTENCLR_TRIGGERED15_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED15 field.                           */
97201   #define VPR_INTENCLR_TRIGGERED15_Clear (0x1UL)     /*!< Disable                                                              */
97202   #define VPR_INTENCLR_TRIGGERED15_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97203   #define VPR_INTENCLR_TRIGGERED15_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97204 
97205 /* TRIGGERED16 @Bit 16 : Write '1' to disable interrupt for event TRIGGERED[16] */
97206   #define VPR_INTENCLR_TRIGGERED16_Pos (16UL)        /*!< Position of TRIGGERED16 field.                                       */
97207   #define VPR_INTENCLR_TRIGGERED16_Msk (0x1UL << VPR_INTENCLR_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.             */
97208   #define VPR_INTENCLR_TRIGGERED16_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED16 field.                           */
97209   #define VPR_INTENCLR_TRIGGERED16_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED16 field.                           */
97210   #define VPR_INTENCLR_TRIGGERED16_Clear (0x1UL)     /*!< Disable                                                              */
97211   #define VPR_INTENCLR_TRIGGERED16_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97212   #define VPR_INTENCLR_TRIGGERED16_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97213 
97214 /* TRIGGERED17 @Bit 17 : Write '1' to disable interrupt for event TRIGGERED[17] */
97215   #define VPR_INTENCLR_TRIGGERED17_Pos (17UL)        /*!< Position of TRIGGERED17 field.                                       */
97216   #define VPR_INTENCLR_TRIGGERED17_Msk (0x1UL << VPR_INTENCLR_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.             */
97217   #define VPR_INTENCLR_TRIGGERED17_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED17 field.                           */
97218   #define VPR_INTENCLR_TRIGGERED17_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED17 field.                           */
97219   #define VPR_INTENCLR_TRIGGERED17_Clear (0x1UL)     /*!< Disable                                                              */
97220   #define VPR_INTENCLR_TRIGGERED17_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97221   #define VPR_INTENCLR_TRIGGERED17_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97222 
97223 /* TRIGGERED18 @Bit 18 : Write '1' to disable interrupt for event TRIGGERED[18] */
97224   #define VPR_INTENCLR_TRIGGERED18_Pos (18UL)        /*!< Position of TRIGGERED18 field.                                       */
97225   #define VPR_INTENCLR_TRIGGERED18_Msk (0x1UL << VPR_INTENCLR_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.             */
97226   #define VPR_INTENCLR_TRIGGERED18_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED18 field.                           */
97227   #define VPR_INTENCLR_TRIGGERED18_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED18 field.                           */
97228   #define VPR_INTENCLR_TRIGGERED18_Clear (0x1UL)     /*!< Disable                                                              */
97229   #define VPR_INTENCLR_TRIGGERED18_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97230   #define VPR_INTENCLR_TRIGGERED18_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97231 
97232 /* TRIGGERED19 @Bit 19 : Write '1' to disable interrupt for event TRIGGERED[19] */
97233   #define VPR_INTENCLR_TRIGGERED19_Pos (19UL)        /*!< Position of TRIGGERED19 field.                                       */
97234   #define VPR_INTENCLR_TRIGGERED19_Msk (0x1UL << VPR_INTENCLR_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.             */
97235   #define VPR_INTENCLR_TRIGGERED19_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED19 field.                           */
97236   #define VPR_INTENCLR_TRIGGERED19_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED19 field.                           */
97237   #define VPR_INTENCLR_TRIGGERED19_Clear (0x1UL)     /*!< Disable                                                              */
97238   #define VPR_INTENCLR_TRIGGERED19_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97239   #define VPR_INTENCLR_TRIGGERED19_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97240 
97241 /* TRIGGERED20 @Bit 20 : Write '1' to disable interrupt for event TRIGGERED[20] */
97242   #define VPR_INTENCLR_TRIGGERED20_Pos (20UL)        /*!< Position of TRIGGERED20 field.                                       */
97243   #define VPR_INTENCLR_TRIGGERED20_Msk (0x1UL << VPR_INTENCLR_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.             */
97244   #define VPR_INTENCLR_TRIGGERED20_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED20 field.                           */
97245   #define VPR_INTENCLR_TRIGGERED20_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED20 field.                           */
97246   #define VPR_INTENCLR_TRIGGERED20_Clear (0x1UL)     /*!< Disable                                                              */
97247   #define VPR_INTENCLR_TRIGGERED20_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97248   #define VPR_INTENCLR_TRIGGERED20_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97249 
97250 /* TRIGGERED21 @Bit 21 : Write '1' to disable interrupt for event TRIGGERED[21] */
97251   #define VPR_INTENCLR_TRIGGERED21_Pos (21UL)        /*!< Position of TRIGGERED21 field.                                       */
97252   #define VPR_INTENCLR_TRIGGERED21_Msk (0x1UL << VPR_INTENCLR_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.             */
97253   #define VPR_INTENCLR_TRIGGERED21_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED21 field.                           */
97254   #define VPR_INTENCLR_TRIGGERED21_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED21 field.                           */
97255   #define VPR_INTENCLR_TRIGGERED21_Clear (0x1UL)     /*!< Disable                                                              */
97256   #define VPR_INTENCLR_TRIGGERED21_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97257   #define VPR_INTENCLR_TRIGGERED21_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97258 
97259 /* TRIGGERED22 @Bit 22 : Write '1' to disable interrupt for event TRIGGERED[22] */
97260   #define VPR_INTENCLR_TRIGGERED22_Pos (22UL)        /*!< Position of TRIGGERED22 field.                                       */
97261   #define VPR_INTENCLR_TRIGGERED22_Msk (0x1UL << VPR_INTENCLR_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.             */
97262   #define VPR_INTENCLR_TRIGGERED22_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED22 field.                           */
97263   #define VPR_INTENCLR_TRIGGERED22_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED22 field.                           */
97264   #define VPR_INTENCLR_TRIGGERED22_Clear (0x1UL)     /*!< Disable                                                              */
97265   #define VPR_INTENCLR_TRIGGERED22_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97266   #define VPR_INTENCLR_TRIGGERED22_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97267 
97268 /* TRIGGERED23 @Bit 23 : Write '1' to disable interrupt for event TRIGGERED[23] */
97269   #define VPR_INTENCLR_TRIGGERED23_Pos (23UL)        /*!< Position of TRIGGERED23 field.                                       */
97270   #define VPR_INTENCLR_TRIGGERED23_Msk (0x1UL << VPR_INTENCLR_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.             */
97271   #define VPR_INTENCLR_TRIGGERED23_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED23 field.                           */
97272   #define VPR_INTENCLR_TRIGGERED23_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED23 field.                           */
97273   #define VPR_INTENCLR_TRIGGERED23_Clear (0x1UL)     /*!< Disable                                                              */
97274   #define VPR_INTENCLR_TRIGGERED23_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97275   #define VPR_INTENCLR_TRIGGERED23_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97276 
97277 /* TRIGGERED24 @Bit 24 : Write '1' to disable interrupt for event TRIGGERED[24] */
97278   #define VPR_INTENCLR_TRIGGERED24_Pos (24UL)        /*!< Position of TRIGGERED24 field.                                       */
97279   #define VPR_INTENCLR_TRIGGERED24_Msk (0x1UL << VPR_INTENCLR_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.             */
97280   #define VPR_INTENCLR_TRIGGERED24_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED24 field.                           */
97281   #define VPR_INTENCLR_TRIGGERED24_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED24 field.                           */
97282   #define VPR_INTENCLR_TRIGGERED24_Clear (0x1UL)     /*!< Disable                                                              */
97283   #define VPR_INTENCLR_TRIGGERED24_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97284   #define VPR_INTENCLR_TRIGGERED24_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97285 
97286 /* TRIGGERED25 @Bit 25 : Write '1' to disable interrupt for event TRIGGERED[25] */
97287   #define VPR_INTENCLR_TRIGGERED25_Pos (25UL)        /*!< Position of TRIGGERED25 field.                                       */
97288   #define VPR_INTENCLR_TRIGGERED25_Msk (0x1UL << VPR_INTENCLR_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.             */
97289   #define VPR_INTENCLR_TRIGGERED25_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED25 field.                           */
97290   #define VPR_INTENCLR_TRIGGERED25_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED25 field.                           */
97291   #define VPR_INTENCLR_TRIGGERED25_Clear (0x1UL)     /*!< Disable                                                              */
97292   #define VPR_INTENCLR_TRIGGERED25_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97293   #define VPR_INTENCLR_TRIGGERED25_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97294 
97295 /* TRIGGERED26 @Bit 26 : Write '1' to disable interrupt for event TRIGGERED[26] */
97296   #define VPR_INTENCLR_TRIGGERED26_Pos (26UL)        /*!< Position of TRIGGERED26 field.                                       */
97297   #define VPR_INTENCLR_TRIGGERED26_Msk (0x1UL << VPR_INTENCLR_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.             */
97298   #define VPR_INTENCLR_TRIGGERED26_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED26 field.                           */
97299   #define VPR_INTENCLR_TRIGGERED26_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED26 field.                           */
97300   #define VPR_INTENCLR_TRIGGERED26_Clear (0x1UL)     /*!< Disable                                                              */
97301   #define VPR_INTENCLR_TRIGGERED26_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97302   #define VPR_INTENCLR_TRIGGERED26_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97303 
97304 /* TRIGGERED27 @Bit 27 : Write '1' to disable interrupt for event TRIGGERED[27] */
97305   #define VPR_INTENCLR_TRIGGERED27_Pos (27UL)        /*!< Position of TRIGGERED27 field.                                       */
97306   #define VPR_INTENCLR_TRIGGERED27_Msk (0x1UL << VPR_INTENCLR_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.             */
97307   #define VPR_INTENCLR_TRIGGERED27_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED27 field.                           */
97308   #define VPR_INTENCLR_TRIGGERED27_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED27 field.                           */
97309   #define VPR_INTENCLR_TRIGGERED27_Clear (0x1UL)     /*!< Disable                                                              */
97310   #define VPR_INTENCLR_TRIGGERED27_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97311   #define VPR_INTENCLR_TRIGGERED27_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97312 
97313 /* TRIGGERED28 @Bit 28 : Write '1' to disable interrupt for event TRIGGERED[28] */
97314   #define VPR_INTENCLR_TRIGGERED28_Pos (28UL)        /*!< Position of TRIGGERED28 field.                                       */
97315   #define VPR_INTENCLR_TRIGGERED28_Msk (0x1UL << VPR_INTENCLR_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.             */
97316   #define VPR_INTENCLR_TRIGGERED28_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED28 field.                           */
97317   #define VPR_INTENCLR_TRIGGERED28_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED28 field.                           */
97318   #define VPR_INTENCLR_TRIGGERED28_Clear (0x1UL)     /*!< Disable                                                              */
97319   #define VPR_INTENCLR_TRIGGERED28_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97320   #define VPR_INTENCLR_TRIGGERED28_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97321 
97322 /* TRIGGERED29 @Bit 29 : Write '1' to disable interrupt for event TRIGGERED[29] */
97323   #define VPR_INTENCLR_TRIGGERED29_Pos (29UL)        /*!< Position of TRIGGERED29 field.                                       */
97324   #define VPR_INTENCLR_TRIGGERED29_Msk (0x1UL << VPR_INTENCLR_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.             */
97325   #define VPR_INTENCLR_TRIGGERED29_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED29 field.                           */
97326   #define VPR_INTENCLR_TRIGGERED29_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED29 field.                           */
97327   #define VPR_INTENCLR_TRIGGERED29_Clear (0x1UL)     /*!< Disable                                                              */
97328   #define VPR_INTENCLR_TRIGGERED29_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97329   #define VPR_INTENCLR_TRIGGERED29_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97330 
97331 /* TRIGGERED30 @Bit 30 : Write '1' to disable interrupt for event TRIGGERED[30] */
97332   #define VPR_INTENCLR_TRIGGERED30_Pos (30UL)        /*!< Position of TRIGGERED30 field.                                       */
97333   #define VPR_INTENCLR_TRIGGERED30_Msk (0x1UL << VPR_INTENCLR_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.             */
97334   #define VPR_INTENCLR_TRIGGERED30_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED30 field.                           */
97335   #define VPR_INTENCLR_TRIGGERED30_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED30 field.                           */
97336   #define VPR_INTENCLR_TRIGGERED30_Clear (0x1UL)     /*!< Disable                                                              */
97337   #define VPR_INTENCLR_TRIGGERED30_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97338   #define VPR_INTENCLR_TRIGGERED30_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97339 
97340 /* TRIGGERED31 @Bit 31 : Write '1' to disable interrupt for event TRIGGERED[31] */
97341   #define VPR_INTENCLR_TRIGGERED31_Pos (31UL)        /*!< Position of TRIGGERED31 field.                                       */
97342   #define VPR_INTENCLR_TRIGGERED31_Msk (0x1UL << VPR_INTENCLR_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.             */
97343   #define VPR_INTENCLR_TRIGGERED31_Min (0x0UL)       /*!< Min enumerator value of TRIGGERED31 field.                           */
97344   #define VPR_INTENCLR_TRIGGERED31_Max (0x1UL)       /*!< Max enumerator value of TRIGGERED31 field.                           */
97345   #define VPR_INTENCLR_TRIGGERED31_Clear (0x1UL)     /*!< Disable                                                              */
97346   #define VPR_INTENCLR_TRIGGERED31_Disabled (0x0UL)  /*!< Read: Disabled                                                       */
97347   #define VPR_INTENCLR_TRIGGERED31_Enabled (0x1UL)   /*!< Read: Enabled                                                        */
97348 
97349 
97350 /* VPR_INTPEND: Pending interrupts */
97351   #define VPR_INTPEND_ResetValue (0x00000000UL)      /*!< Reset value of INTPEND register.                                     */
97352 
97353 /* TRIGGERED0 @Bit 0 : Read pending status of interrupt for event TRIGGERED[0] */
97354   #define VPR_INTPEND_TRIGGERED0_Pos (0UL)           /*!< Position of TRIGGERED0 field.                                        */
97355   #define VPR_INTPEND_TRIGGERED0_Msk (0x1UL << VPR_INTPEND_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field.                  */
97356   #define VPR_INTPEND_TRIGGERED0_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED0 field.                            */
97357   #define VPR_INTPEND_TRIGGERED0_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED0 field.                            */
97358   #define VPR_INTPEND_TRIGGERED0_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97359   #define VPR_INTPEND_TRIGGERED0_Pending (0x1UL)     /*!< Read: Pending                                                        */
97360 
97361 /* TRIGGERED1 @Bit 1 : Read pending status of interrupt for event TRIGGERED[1] */
97362   #define VPR_INTPEND_TRIGGERED1_Pos (1UL)           /*!< Position of TRIGGERED1 field.                                        */
97363   #define VPR_INTPEND_TRIGGERED1_Msk (0x1UL << VPR_INTPEND_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field.                  */
97364   #define VPR_INTPEND_TRIGGERED1_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED1 field.                            */
97365   #define VPR_INTPEND_TRIGGERED1_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED1 field.                            */
97366   #define VPR_INTPEND_TRIGGERED1_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97367   #define VPR_INTPEND_TRIGGERED1_Pending (0x1UL)     /*!< Read: Pending                                                        */
97368 
97369 /* TRIGGERED2 @Bit 2 : Read pending status of interrupt for event TRIGGERED[2] */
97370   #define VPR_INTPEND_TRIGGERED2_Pos (2UL)           /*!< Position of TRIGGERED2 field.                                        */
97371   #define VPR_INTPEND_TRIGGERED2_Msk (0x1UL << VPR_INTPEND_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field.                  */
97372   #define VPR_INTPEND_TRIGGERED2_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED2 field.                            */
97373   #define VPR_INTPEND_TRIGGERED2_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED2 field.                            */
97374   #define VPR_INTPEND_TRIGGERED2_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97375   #define VPR_INTPEND_TRIGGERED2_Pending (0x1UL)     /*!< Read: Pending                                                        */
97376 
97377 /* TRIGGERED3 @Bit 3 : Read pending status of interrupt for event TRIGGERED[3] */
97378   #define VPR_INTPEND_TRIGGERED3_Pos (3UL)           /*!< Position of TRIGGERED3 field.                                        */
97379   #define VPR_INTPEND_TRIGGERED3_Msk (0x1UL << VPR_INTPEND_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field.                  */
97380   #define VPR_INTPEND_TRIGGERED3_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED3 field.                            */
97381   #define VPR_INTPEND_TRIGGERED3_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED3 field.                            */
97382   #define VPR_INTPEND_TRIGGERED3_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97383   #define VPR_INTPEND_TRIGGERED3_Pending (0x1UL)     /*!< Read: Pending                                                        */
97384 
97385 /* TRIGGERED4 @Bit 4 : Read pending status of interrupt for event TRIGGERED[4] */
97386   #define VPR_INTPEND_TRIGGERED4_Pos (4UL)           /*!< Position of TRIGGERED4 field.                                        */
97387   #define VPR_INTPEND_TRIGGERED4_Msk (0x1UL << VPR_INTPEND_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field.                  */
97388   #define VPR_INTPEND_TRIGGERED4_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED4 field.                            */
97389   #define VPR_INTPEND_TRIGGERED4_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED4 field.                            */
97390   #define VPR_INTPEND_TRIGGERED4_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97391   #define VPR_INTPEND_TRIGGERED4_Pending (0x1UL)     /*!< Read: Pending                                                        */
97392 
97393 /* TRIGGERED5 @Bit 5 : Read pending status of interrupt for event TRIGGERED[5] */
97394   #define VPR_INTPEND_TRIGGERED5_Pos (5UL)           /*!< Position of TRIGGERED5 field.                                        */
97395   #define VPR_INTPEND_TRIGGERED5_Msk (0x1UL << VPR_INTPEND_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field.                  */
97396   #define VPR_INTPEND_TRIGGERED5_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED5 field.                            */
97397   #define VPR_INTPEND_TRIGGERED5_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED5 field.                            */
97398   #define VPR_INTPEND_TRIGGERED5_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97399   #define VPR_INTPEND_TRIGGERED5_Pending (0x1UL)     /*!< Read: Pending                                                        */
97400 
97401 /* TRIGGERED6 @Bit 6 : Read pending status of interrupt for event TRIGGERED[6] */
97402   #define VPR_INTPEND_TRIGGERED6_Pos (6UL)           /*!< Position of TRIGGERED6 field.                                        */
97403   #define VPR_INTPEND_TRIGGERED6_Msk (0x1UL << VPR_INTPEND_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field.                  */
97404   #define VPR_INTPEND_TRIGGERED6_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED6 field.                            */
97405   #define VPR_INTPEND_TRIGGERED6_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED6 field.                            */
97406   #define VPR_INTPEND_TRIGGERED6_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97407   #define VPR_INTPEND_TRIGGERED6_Pending (0x1UL)     /*!< Read: Pending                                                        */
97408 
97409 /* TRIGGERED7 @Bit 7 : Read pending status of interrupt for event TRIGGERED[7] */
97410   #define VPR_INTPEND_TRIGGERED7_Pos (7UL)           /*!< Position of TRIGGERED7 field.                                        */
97411   #define VPR_INTPEND_TRIGGERED7_Msk (0x1UL << VPR_INTPEND_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field.                  */
97412   #define VPR_INTPEND_TRIGGERED7_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED7 field.                            */
97413   #define VPR_INTPEND_TRIGGERED7_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED7 field.                            */
97414   #define VPR_INTPEND_TRIGGERED7_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97415   #define VPR_INTPEND_TRIGGERED7_Pending (0x1UL)     /*!< Read: Pending                                                        */
97416 
97417 /* TRIGGERED8 @Bit 8 : Read pending status of interrupt for event TRIGGERED[8] */
97418   #define VPR_INTPEND_TRIGGERED8_Pos (8UL)           /*!< Position of TRIGGERED8 field.                                        */
97419   #define VPR_INTPEND_TRIGGERED8_Msk (0x1UL << VPR_INTPEND_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field.                  */
97420   #define VPR_INTPEND_TRIGGERED8_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED8 field.                            */
97421   #define VPR_INTPEND_TRIGGERED8_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED8 field.                            */
97422   #define VPR_INTPEND_TRIGGERED8_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97423   #define VPR_INTPEND_TRIGGERED8_Pending (0x1UL)     /*!< Read: Pending                                                        */
97424 
97425 /* TRIGGERED9 @Bit 9 : Read pending status of interrupt for event TRIGGERED[9] */
97426   #define VPR_INTPEND_TRIGGERED9_Pos (9UL)           /*!< Position of TRIGGERED9 field.                                        */
97427   #define VPR_INTPEND_TRIGGERED9_Msk (0x1UL << VPR_INTPEND_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field.                  */
97428   #define VPR_INTPEND_TRIGGERED9_Min (0x0UL)         /*!< Min enumerator value of TRIGGERED9 field.                            */
97429   #define VPR_INTPEND_TRIGGERED9_Max (0x1UL)         /*!< Max enumerator value of TRIGGERED9 field.                            */
97430   #define VPR_INTPEND_TRIGGERED9_NotPending (0x0UL)  /*!< Read: Not pending                                                    */
97431   #define VPR_INTPEND_TRIGGERED9_Pending (0x1UL)     /*!< Read: Pending                                                        */
97432 
97433 /* TRIGGERED10 @Bit 10 : Read pending status of interrupt for event TRIGGERED[10] */
97434   #define VPR_INTPEND_TRIGGERED10_Pos (10UL)         /*!< Position of TRIGGERED10 field.                                       */
97435   #define VPR_INTPEND_TRIGGERED10_Msk (0x1UL << VPR_INTPEND_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field.               */
97436   #define VPR_INTPEND_TRIGGERED10_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED10 field.                           */
97437   #define VPR_INTPEND_TRIGGERED10_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED10 field.                           */
97438   #define VPR_INTPEND_TRIGGERED10_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97439   #define VPR_INTPEND_TRIGGERED10_Pending (0x1UL)    /*!< Read: Pending                                                        */
97440 
97441 /* TRIGGERED11 @Bit 11 : Read pending status of interrupt for event TRIGGERED[11] */
97442   #define VPR_INTPEND_TRIGGERED11_Pos (11UL)         /*!< Position of TRIGGERED11 field.                                       */
97443   #define VPR_INTPEND_TRIGGERED11_Msk (0x1UL << VPR_INTPEND_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field.               */
97444   #define VPR_INTPEND_TRIGGERED11_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED11 field.                           */
97445   #define VPR_INTPEND_TRIGGERED11_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED11 field.                           */
97446   #define VPR_INTPEND_TRIGGERED11_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97447   #define VPR_INTPEND_TRIGGERED11_Pending (0x1UL)    /*!< Read: Pending                                                        */
97448 
97449 /* TRIGGERED12 @Bit 12 : Read pending status of interrupt for event TRIGGERED[12] */
97450   #define VPR_INTPEND_TRIGGERED12_Pos (12UL)         /*!< Position of TRIGGERED12 field.                                       */
97451   #define VPR_INTPEND_TRIGGERED12_Msk (0x1UL << VPR_INTPEND_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field.               */
97452   #define VPR_INTPEND_TRIGGERED12_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED12 field.                           */
97453   #define VPR_INTPEND_TRIGGERED12_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED12 field.                           */
97454   #define VPR_INTPEND_TRIGGERED12_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97455   #define VPR_INTPEND_TRIGGERED12_Pending (0x1UL)    /*!< Read: Pending                                                        */
97456 
97457 /* TRIGGERED13 @Bit 13 : Read pending status of interrupt for event TRIGGERED[13] */
97458   #define VPR_INTPEND_TRIGGERED13_Pos (13UL)         /*!< Position of TRIGGERED13 field.                                       */
97459   #define VPR_INTPEND_TRIGGERED13_Msk (0x1UL << VPR_INTPEND_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field.               */
97460   #define VPR_INTPEND_TRIGGERED13_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED13 field.                           */
97461   #define VPR_INTPEND_TRIGGERED13_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED13 field.                           */
97462   #define VPR_INTPEND_TRIGGERED13_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97463   #define VPR_INTPEND_TRIGGERED13_Pending (0x1UL)    /*!< Read: Pending                                                        */
97464 
97465 /* TRIGGERED14 @Bit 14 : Read pending status of interrupt for event TRIGGERED[14] */
97466   #define VPR_INTPEND_TRIGGERED14_Pos (14UL)         /*!< Position of TRIGGERED14 field.                                       */
97467   #define VPR_INTPEND_TRIGGERED14_Msk (0x1UL << VPR_INTPEND_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field.               */
97468   #define VPR_INTPEND_TRIGGERED14_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED14 field.                           */
97469   #define VPR_INTPEND_TRIGGERED14_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED14 field.                           */
97470   #define VPR_INTPEND_TRIGGERED14_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97471   #define VPR_INTPEND_TRIGGERED14_Pending (0x1UL)    /*!< Read: Pending                                                        */
97472 
97473 /* TRIGGERED15 @Bit 15 : Read pending status of interrupt for event TRIGGERED[15] */
97474   #define VPR_INTPEND_TRIGGERED15_Pos (15UL)         /*!< Position of TRIGGERED15 field.                                       */
97475   #define VPR_INTPEND_TRIGGERED15_Msk (0x1UL << VPR_INTPEND_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field.               */
97476   #define VPR_INTPEND_TRIGGERED15_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED15 field.                           */
97477   #define VPR_INTPEND_TRIGGERED15_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED15 field.                           */
97478   #define VPR_INTPEND_TRIGGERED15_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97479   #define VPR_INTPEND_TRIGGERED15_Pending (0x1UL)    /*!< Read: Pending                                                        */
97480 
97481 /* TRIGGERED16 @Bit 16 : Read pending status of interrupt for event TRIGGERED[16] */
97482   #define VPR_INTPEND_TRIGGERED16_Pos (16UL)         /*!< Position of TRIGGERED16 field.                                       */
97483   #define VPR_INTPEND_TRIGGERED16_Msk (0x1UL << VPR_INTPEND_TRIGGERED16_Pos) /*!< Bit mask of TRIGGERED16 field.               */
97484   #define VPR_INTPEND_TRIGGERED16_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED16 field.                           */
97485   #define VPR_INTPEND_TRIGGERED16_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED16 field.                           */
97486   #define VPR_INTPEND_TRIGGERED16_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97487   #define VPR_INTPEND_TRIGGERED16_Pending (0x1UL)    /*!< Read: Pending                                                        */
97488 
97489 /* TRIGGERED17 @Bit 17 : Read pending status of interrupt for event TRIGGERED[17] */
97490   #define VPR_INTPEND_TRIGGERED17_Pos (17UL)         /*!< Position of TRIGGERED17 field.                                       */
97491   #define VPR_INTPEND_TRIGGERED17_Msk (0x1UL << VPR_INTPEND_TRIGGERED17_Pos) /*!< Bit mask of TRIGGERED17 field.               */
97492   #define VPR_INTPEND_TRIGGERED17_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED17 field.                           */
97493   #define VPR_INTPEND_TRIGGERED17_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED17 field.                           */
97494   #define VPR_INTPEND_TRIGGERED17_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97495   #define VPR_INTPEND_TRIGGERED17_Pending (0x1UL)    /*!< Read: Pending                                                        */
97496 
97497 /* TRIGGERED18 @Bit 18 : Read pending status of interrupt for event TRIGGERED[18] */
97498   #define VPR_INTPEND_TRIGGERED18_Pos (18UL)         /*!< Position of TRIGGERED18 field.                                       */
97499   #define VPR_INTPEND_TRIGGERED18_Msk (0x1UL << VPR_INTPEND_TRIGGERED18_Pos) /*!< Bit mask of TRIGGERED18 field.               */
97500   #define VPR_INTPEND_TRIGGERED18_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED18 field.                           */
97501   #define VPR_INTPEND_TRIGGERED18_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED18 field.                           */
97502   #define VPR_INTPEND_TRIGGERED18_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97503   #define VPR_INTPEND_TRIGGERED18_Pending (0x1UL)    /*!< Read: Pending                                                        */
97504 
97505 /* TRIGGERED19 @Bit 19 : Read pending status of interrupt for event TRIGGERED[19] */
97506   #define VPR_INTPEND_TRIGGERED19_Pos (19UL)         /*!< Position of TRIGGERED19 field.                                       */
97507   #define VPR_INTPEND_TRIGGERED19_Msk (0x1UL << VPR_INTPEND_TRIGGERED19_Pos) /*!< Bit mask of TRIGGERED19 field.               */
97508   #define VPR_INTPEND_TRIGGERED19_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED19 field.                           */
97509   #define VPR_INTPEND_TRIGGERED19_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED19 field.                           */
97510   #define VPR_INTPEND_TRIGGERED19_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97511   #define VPR_INTPEND_TRIGGERED19_Pending (0x1UL)    /*!< Read: Pending                                                        */
97512 
97513 /* TRIGGERED20 @Bit 20 : Read pending status of interrupt for event TRIGGERED[20] */
97514   #define VPR_INTPEND_TRIGGERED20_Pos (20UL)         /*!< Position of TRIGGERED20 field.                                       */
97515   #define VPR_INTPEND_TRIGGERED20_Msk (0x1UL << VPR_INTPEND_TRIGGERED20_Pos) /*!< Bit mask of TRIGGERED20 field.               */
97516   #define VPR_INTPEND_TRIGGERED20_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED20 field.                           */
97517   #define VPR_INTPEND_TRIGGERED20_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED20 field.                           */
97518   #define VPR_INTPEND_TRIGGERED20_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97519   #define VPR_INTPEND_TRIGGERED20_Pending (0x1UL)    /*!< Read: Pending                                                        */
97520 
97521 /* TRIGGERED21 @Bit 21 : Read pending status of interrupt for event TRIGGERED[21] */
97522   #define VPR_INTPEND_TRIGGERED21_Pos (21UL)         /*!< Position of TRIGGERED21 field.                                       */
97523   #define VPR_INTPEND_TRIGGERED21_Msk (0x1UL << VPR_INTPEND_TRIGGERED21_Pos) /*!< Bit mask of TRIGGERED21 field.               */
97524   #define VPR_INTPEND_TRIGGERED21_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED21 field.                           */
97525   #define VPR_INTPEND_TRIGGERED21_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED21 field.                           */
97526   #define VPR_INTPEND_TRIGGERED21_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97527   #define VPR_INTPEND_TRIGGERED21_Pending (0x1UL)    /*!< Read: Pending                                                        */
97528 
97529 /* TRIGGERED22 @Bit 22 : Read pending status of interrupt for event TRIGGERED[22] */
97530   #define VPR_INTPEND_TRIGGERED22_Pos (22UL)         /*!< Position of TRIGGERED22 field.                                       */
97531   #define VPR_INTPEND_TRIGGERED22_Msk (0x1UL << VPR_INTPEND_TRIGGERED22_Pos) /*!< Bit mask of TRIGGERED22 field.               */
97532   #define VPR_INTPEND_TRIGGERED22_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED22 field.                           */
97533   #define VPR_INTPEND_TRIGGERED22_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED22 field.                           */
97534   #define VPR_INTPEND_TRIGGERED22_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97535   #define VPR_INTPEND_TRIGGERED22_Pending (0x1UL)    /*!< Read: Pending                                                        */
97536 
97537 /* TRIGGERED23 @Bit 23 : Read pending status of interrupt for event TRIGGERED[23] */
97538   #define VPR_INTPEND_TRIGGERED23_Pos (23UL)         /*!< Position of TRIGGERED23 field.                                       */
97539   #define VPR_INTPEND_TRIGGERED23_Msk (0x1UL << VPR_INTPEND_TRIGGERED23_Pos) /*!< Bit mask of TRIGGERED23 field.               */
97540   #define VPR_INTPEND_TRIGGERED23_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED23 field.                           */
97541   #define VPR_INTPEND_TRIGGERED23_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED23 field.                           */
97542   #define VPR_INTPEND_TRIGGERED23_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97543   #define VPR_INTPEND_TRIGGERED23_Pending (0x1UL)    /*!< Read: Pending                                                        */
97544 
97545 /* TRIGGERED24 @Bit 24 : Read pending status of interrupt for event TRIGGERED[24] */
97546   #define VPR_INTPEND_TRIGGERED24_Pos (24UL)         /*!< Position of TRIGGERED24 field.                                       */
97547   #define VPR_INTPEND_TRIGGERED24_Msk (0x1UL << VPR_INTPEND_TRIGGERED24_Pos) /*!< Bit mask of TRIGGERED24 field.               */
97548   #define VPR_INTPEND_TRIGGERED24_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED24 field.                           */
97549   #define VPR_INTPEND_TRIGGERED24_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED24 field.                           */
97550   #define VPR_INTPEND_TRIGGERED24_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97551   #define VPR_INTPEND_TRIGGERED24_Pending (0x1UL)    /*!< Read: Pending                                                        */
97552 
97553 /* TRIGGERED25 @Bit 25 : Read pending status of interrupt for event TRIGGERED[25] */
97554   #define VPR_INTPEND_TRIGGERED25_Pos (25UL)         /*!< Position of TRIGGERED25 field.                                       */
97555   #define VPR_INTPEND_TRIGGERED25_Msk (0x1UL << VPR_INTPEND_TRIGGERED25_Pos) /*!< Bit mask of TRIGGERED25 field.               */
97556   #define VPR_INTPEND_TRIGGERED25_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED25 field.                           */
97557   #define VPR_INTPEND_TRIGGERED25_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED25 field.                           */
97558   #define VPR_INTPEND_TRIGGERED25_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97559   #define VPR_INTPEND_TRIGGERED25_Pending (0x1UL)    /*!< Read: Pending                                                        */
97560 
97561 /* TRIGGERED26 @Bit 26 : Read pending status of interrupt for event TRIGGERED[26] */
97562   #define VPR_INTPEND_TRIGGERED26_Pos (26UL)         /*!< Position of TRIGGERED26 field.                                       */
97563   #define VPR_INTPEND_TRIGGERED26_Msk (0x1UL << VPR_INTPEND_TRIGGERED26_Pos) /*!< Bit mask of TRIGGERED26 field.               */
97564   #define VPR_INTPEND_TRIGGERED26_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED26 field.                           */
97565   #define VPR_INTPEND_TRIGGERED26_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED26 field.                           */
97566   #define VPR_INTPEND_TRIGGERED26_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97567   #define VPR_INTPEND_TRIGGERED26_Pending (0x1UL)    /*!< Read: Pending                                                        */
97568 
97569 /* TRIGGERED27 @Bit 27 : Read pending status of interrupt for event TRIGGERED[27] */
97570   #define VPR_INTPEND_TRIGGERED27_Pos (27UL)         /*!< Position of TRIGGERED27 field.                                       */
97571   #define VPR_INTPEND_TRIGGERED27_Msk (0x1UL << VPR_INTPEND_TRIGGERED27_Pos) /*!< Bit mask of TRIGGERED27 field.               */
97572   #define VPR_INTPEND_TRIGGERED27_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED27 field.                           */
97573   #define VPR_INTPEND_TRIGGERED27_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED27 field.                           */
97574   #define VPR_INTPEND_TRIGGERED27_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97575   #define VPR_INTPEND_TRIGGERED27_Pending (0x1UL)    /*!< Read: Pending                                                        */
97576 
97577 /* TRIGGERED28 @Bit 28 : Read pending status of interrupt for event TRIGGERED[28] */
97578   #define VPR_INTPEND_TRIGGERED28_Pos (28UL)         /*!< Position of TRIGGERED28 field.                                       */
97579   #define VPR_INTPEND_TRIGGERED28_Msk (0x1UL << VPR_INTPEND_TRIGGERED28_Pos) /*!< Bit mask of TRIGGERED28 field.               */
97580   #define VPR_INTPEND_TRIGGERED28_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED28 field.                           */
97581   #define VPR_INTPEND_TRIGGERED28_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED28 field.                           */
97582   #define VPR_INTPEND_TRIGGERED28_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97583   #define VPR_INTPEND_TRIGGERED28_Pending (0x1UL)    /*!< Read: Pending                                                        */
97584 
97585 /* TRIGGERED29 @Bit 29 : Read pending status of interrupt for event TRIGGERED[29] */
97586   #define VPR_INTPEND_TRIGGERED29_Pos (29UL)         /*!< Position of TRIGGERED29 field.                                       */
97587   #define VPR_INTPEND_TRIGGERED29_Msk (0x1UL << VPR_INTPEND_TRIGGERED29_Pos) /*!< Bit mask of TRIGGERED29 field.               */
97588   #define VPR_INTPEND_TRIGGERED29_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED29 field.                           */
97589   #define VPR_INTPEND_TRIGGERED29_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED29 field.                           */
97590   #define VPR_INTPEND_TRIGGERED29_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97591   #define VPR_INTPEND_TRIGGERED29_Pending (0x1UL)    /*!< Read: Pending                                                        */
97592 
97593 /* TRIGGERED30 @Bit 30 : Read pending status of interrupt for event TRIGGERED[30] */
97594   #define VPR_INTPEND_TRIGGERED30_Pos (30UL)         /*!< Position of TRIGGERED30 field.                                       */
97595   #define VPR_INTPEND_TRIGGERED30_Msk (0x1UL << VPR_INTPEND_TRIGGERED30_Pos) /*!< Bit mask of TRIGGERED30 field.               */
97596   #define VPR_INTPEND_TRIGGERED30_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED30 field.                           */
97597   #define VPR_INTPEND_TRIGGERED30_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED30 field.                           */
97598   #define VPR_INTPEND_TRIGGERED30_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97599   #define VPR_INTPEND_TRIGGERED30_Pending (0x1UL)    /*!< Read: Pending                                                        */
97600 
97601 /* TRIGGERED31 @Bit 31 : Read pending status of interrupt for event TRIGGERED[31] */
97602   #define VPR_INTPEND_TRIGGERED31_Pos (31UL)         /*!< Position of TRIGGERED31 field.                                       */
97603   #define VPR_INTPEND_TRIGGERED31_Msk (0x1UL << VPR_INTPEND_TRIGGERED31_Pos) /*!< Bit mask of TRIGGERED31 field.               */
97604   #define VPR_INTPEND_TRIGGERED31_Min (0x0UL)        /*!< Min enumerator value of TRIGGERED31 field.                           */
97605   #define VPR_INTPEND_TRIGGERED31_Max (0x1UL)        /*!< Max enumerator value of TRIGGERED31 field.                           */
97606   #define VPR_INTPEND_TRIGGERED31_NotPending (0x0UL) /*!< Read: Not pending                                                    */
97607   #define VPR_INTPEND_TRIGGERED31_Pending (0x1UL)    /*!< Read: Pending                                                        */
97608 
97609 
97610 /* VPR_CPURUN: State of the CPU after a core reset */
97611   #define VPR_CPURUN_ResetValue (0x00000000UL)       /*!< Reset value of CPURUN register.                                      */
97612 
97613 /* EN @Bit 0 : Controls CPU running state after a core reset. */
97614   #define VPR_CPURUN_EN_Pos (0UL)                    /*!< Position of EN field.                                                */
97615   #define VPR_CPURUN_EN_Msk (0x1UL << VPR_CPURUN_EN_Pos) /*!< Bit mask of EN field.                                            */
97616   #define VPR_CPURUN_EN_Min (0x0UL)                  /*!< Min enumerator value of EN field.                                    */
97617   #define VPR_CPURUN_EN_Max (0x1UL)                  /*!< Max enumerator value of EN field.                                    */
97618   #define VPR_CPURUN_EN_Stopped (0x0UL)              /*!< CPU stopped. If this is the CPU state after a core reset, setting this
97619                                                           bit will change the CPU state to CPU running.*/
97620   #define VPR_CPURUN_EN_Running (0x1UL)              /*!< CPU running. If this is the CPU state after a core reset, clearing
97621                                                           this bit will change the CPU state to CPU stopped after a core reset.*/
97622 
97623 
97624 /* VPR_INITPC: Initial value of the PC at CPU start. */
97625   #define VPR_INITPC_ResetValue (0x00000000UL)       /*!< Reset value of INITPC register.                                      */
97626 
97627 /* INITPC @Bits 0..31 : Initial value of the PC at CPU start. */
97628   #define VPR_INITPC_INITPC_Pos (0UL)                /*!< Position of INITPC field.                                            */
97629   #define VPR_INITPC_INITPC_Msk (0xFFFFFFFFUL << VPR_INITPC_INITPC_Pos) /*!< Bit mask of INITPC field.                         */
97630 
97631 
97632 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
97633 
97634 /* =========================================================================================================================== */
97635 /* ================                                          VPRCSR                                          ================ */
97636 /* =========================================================================================================================== */
97637 
97638 /**
97639   * @brief VPR CSR registers
97640   */
97641 /**
97642   * @brief  [VPRCSR] (unspecified)
97643   */
97644 
97645 /**
97646   * @brief  [VPRCSR] (unspecified)
97647   */
97648 
97649 /**
97650   * @brief MSTATUS [VPRCSR_MSTATUS] Machine Status
97651   */
97652   #define VPRCSR_MSTATUS (0x00000300ul)
97653   #define VPRCSR_MSTATUS_ResetValue (0x00001800UL)   /*!< Reset value of MSTATUS register.                                     */
97654 
97655 /* MIE @Bit 3 : global interrupt enable for machine privilege mode */
97656   #define VPRCSR_MSTATUS_MIE_Pos (3UL)               /*!< Position of MIE field.                                               */
97657   #define VPRCSR_MSTATUS_MIE_Msk (0x1UL << VPRCSR_MSTATUS_MIE_Pos) /*!< Bit mask of MIE field.                                 */
97658   #define VPRCSR_MSTATUS_MIE_Min (0x0UL)             /*!< Min enumerator value of MIE field.                                   */
97659   #define VPRCSR_MSTATUS_MIE_Max (0x1UL)             /*!< Max enumerator value of MIE field.                                   */
97660   #define VPRCSR_MSTATUS_MIE_Disabled (0x0UL)        /*!< (unspecified)                                                        */
97661   #define VPRCSR_MSTATUS_MIE_Enabled (0x1UL)         /*!< (unspecified)                                                        */
97662 
97663 /* MPIE @Bit 7 : Exists to support nested traps. Value of the interrupt-enable bit active prior to the trap for machine
97664                  privilege mode */
97665 
97666   #define VPRCSR_MSTATUS_MPIE_Pos (7UL)              /*!< Position of MPIE field.                                              */
97667   #define VPRCSR_MSTATUS_MPIE_Msk (0x1UL << VPRCSR_MSTATUS_MPIE_Pos) /*!< Bit mask of MPIE field.                              */
97668   #define VPRCSR_MSTATUS_MPIE_Min (0x0UL)            /*!< Min enumerator value of MPIE field.                                  */
97669   #define VPRCSR_MSTATUS_MPIE_Max (0x1UL)            /*!< Max enumerator value of MPIE field.                                  */
97670   #define VPRCSR_MSTATUS_MPIE_Disabled (0x0UL)       /*!< (unspecified)                                                        */
97671   #define VPRCSR_MSTATUS_MPIE_Enabled (0x1UL)        /*!< (unspecified)                                                        */
97672 
97673 /* MPP @Bits 11..12 : Exists to support nested traps. Value of the privlege mode prior to the trap for machine privilege mode */
97674   #define VPRCSR_MSTATUS_MPP_Pos (11UL)              /*!< Position of MPP field.                                               */
97675   #define VPRCSR_MSTATUS_MPP_Msk (0x3UL << VPRCSR_MSTATUS_MPP_Pos) /*!< Bit mask of MPP field.                                 */
97676 
97677 
97678 /**
97679   * @brief MISA [VPRCSR_MISA] Machine ISA
97680   */
97681   #define VPRCSR_MISA (0x00000301ul)
97682   #define VPRCSR_MISA_ResetValue (0x40001014UL)      /*!< Reset value of MISA register.                                        */
97683 
97684 /* A @Bit 0 : Atomic extension */
97685   #define VPRCSR_MISA_A_Pos (0UL)                    /*!< Position of A field.                                                 */
97686   #define VPRCSR_MISA_A_Msk (0x1UL << VPRCSR_MISA_A_Pos) /*!< Bit mask of A field.                                             */
97687   #define VPRCSR_MISA_A_Min (0x0UL)                  /*!< Min enumerator value of A field.                                     */
97688   #define VPRCSR_MISA_A_Max (0x1UL)                  /*!< Max enumerator value of A field.                                     */
97689   #define VPRCSR_MISA_A_Disabled (0x0UL)             /*!< (unspecified)                                                        */
97690   #define VPRCSR_MISA_A_Enabled (0x1UL)              /*!< (unspecified)                                                        */
97691 
97692 /* B @Bit 1 : Bit-Manipulation extension */
97693   #define VPRCSR_MISA_B_Pos (1UL)                    /*!< Position of B field.                                                 */
97694   #define VPRCSR_MISA_B_Msk (0x1UL << VPRCSR_MISA_B_Pos) /*!< Bit mask of B field.                                             */
97695   #define VPRCSR_MISA_B_Min (0x0UL)                  /*!< Min enumerator value of B field.                                     */
97696   #define VPRCSR_MISA_B_Max (0x1UL)                  /*!< Max enumerator value of B field.                                     */
97697   #define VPRCSR_MISA_B_Disabled (0x0UL)             /*!< (unspecified)                                                        */
97698   #define VPRCSR_MISA_B_Enabled (0x1UL)              /*!< (unspecified)                                                        */
97699 
97700 /* C @Bit 2 : Compressed extension */
97701   #define VPRCSR_MISA_C_Pos (2UL)                    /*!< Position of C field.                                                 */
97702   #define VPRCSR_MISA_C_Msk (0x1UL << VPRCSR_MISA_C_Pos) /*!< Bit mask of C field.                                             */
97703   #define VPRCSR_MISA_C_Min (0x0UL)                  /*!< Min enumerator value of C field.                                     */
97704   #define VPRCSR_MISA_C_Max (0x1UL)                  /*!< Max enumerator value of C field.                                     */
97705   #define VPRCSR_MISA_C_Disabled (0x0UL)             /*!< (unspecified)                                                        */
97706   #define VPRCSR_MISA_C_Enabled (0x1UL)              /*!< (unspecified)                                                        */
97707 
97708 /* E @Bit 4 : RV32E base ISA */
97709   #define VPRCSR_MISA_E_Pos (4UL)                    /*!< Position of E field.                                                 */
97710   #define VPRCSR_MISA_E_Msk (0x1UL << VPRCSR_MISA_E_Pos) /*!< Bit mask of E field.                                             */
97711   #define VPRCSR_MISA_E_Min (0x0UL)                  /*!< Min enumerator value of E field.                                     */
97712   #define VPRCSR_MISA_E_Max (0x1UL)                  /*!< Max enumerator value of E field.                                     */
97713   #define VPRCSR_MISA_E_Disabled (0x0UL)             /*!< (unspecified)                                                        */
97714   #define VPRCSR_MISA_E_Enabled (0x1UL)              /*!< (unspecified)                                                        */
97715 
97716 /* I @Bit 8 : RV32I/64I/128I base ISA */
97717   #define VPRCSR_MISA_I_Pos (8UL)                    /*!< Position of I field.                                                 */
97718   #define VPRCSR_MISA_I_Msk (0x1UL << VPRCSR_MISA_I_Pos) /*!< Bit mask of I field.                                             */
97719   #define VPRCSR_MISA_I_Min (0x0UL)                  /*!< Min enumerator value of I field.                                     */
97720   #define VPRCSR_MISA_I_Max (0x1UL)                  /*!< Max enumerator value of I field.                                     */
97721   #define VPRCSR_MISA_I_Disabled (0x0UL)             /*!< (unspecified)                                                        */
97722   #define VPRCSR_MISA_I_Enabled (0x1UL)              /*!< (unspecified)                                                        */
97723 
97724 /* M @Bit 12 : Integer Multiply/Divide extension */
97725   #define VPRCSR_MISA_M_Pos (12UL)                   /*!< Position of M field.                                                 */
97726   #define VPRCSR_MISA_M_Msk (0x1UL << VPRCSR_MISA_M_Pos) /*!< Bit mask of M field.                                             */
97727   #define VPRCSR_MISA_M_Min (0x0UL)                  /*!< Min enumerator value of M field.                                     */
97728   #define VPRCSR_MISA_M_Max (0x1UL)                  /*!< Max enumerator value of M field.                                     */
97729   #define VPRCSR_MISA_M_Disabled (0x0UL)             /*!< (unspecified)                                                        */
97730   #define VPRCSR_MISA_M_Enabled (0x1UL)              /*!< (unspecified)                                                        */
97731 
97732 /* N @Bit 13 : User-level interrupts supported */
97733   #define VPRCSR_MISA_N_Pos (13UL)                   /*!< Position of N field.                                                 */
97734   #define VPRCSR_MISA_N_Msk (0x1UL << VPRCSR_MISA_N_Pos) /*!< Bit mask of N field.                                             */
97735   #define VPRCSR_MISA_N_Min (0x0UL)                  /*!< Min enumerator value of N field.                                     */
97736   #define VPRCSR_MISA_N_Max (0x1UL)                  /*!< Max enumerator value of N field.                                     */
97737   #define VPRCSR_MISA_N_Disabled (0x0UL)             /*!< (unspecified)                                                        */
97738   #define VPRCSR_MISA_N_Enabled (0x1UL)              /*!< (unspecified)                                                        */
97739 
97740 /* MXL @Bits 30..31 : Machine XLEN */
97741   #define VPRCSR_MISA_MXL_Pos (30UL)                 /*!< Position of MXL field.                                               */
97742   #define VPRCSR_MISA_MXL_Msk (0x3UL << VPRCSR_MISA_MXL_Pos) /*!< Bit mask of MXL field.                                       */
97743   #define VPRCSR_MISA_MXL_Min (0x1UL)                /*!< Min enumerator value of MXL field.                                   */
97744   #define VPRCSR_MISA_MXL_Max (0x3UL)                /*!< Max enumerator value of MXL field.                                   */
97745   #define VPRCSR_MISA_MXL_XLEN32 (0x1UL)             /*!< XLEN is 32 bits                                                      */
97746   #define VPRCSR_MISA_MXL_XLEN64 (0x2UL)             /*!< XLEN is 64 bits                                                      */
97747   #define VPRCSR_MISA_MXL_XLEN128 (0x3UL)            /*!< XLEN is 128 bits                                                     */
97748 
97749 
97750 /**
97751   * @brief MTVEC [VPRCSR_MTVEC] Machine Trap-Vector
97752   */
97753   #define VPRCSR_MTVEC (0x00000305ul)
97754   #define VPRCSR_MTVEC_ResetValue (0x00000003UL)     /*!< Reset value of MTVEC register.                                       */
97755 
97756 /* MODE @Bits 0..1 : Mode */
97757   #define VPRCSR_MTVEC_MODE_Pos (0UL)                /*!< Position of MODE field.                                              */
97758   #define VPRCSR_MTVEC_MODE_Msk (0x3UL << VPRCSR_MTVEC_MODE_Pos) /*!< Bit mask of MODE field.                                  */
97759   #define VPRCSR_MTVEC_MODE_Min (0x3UL)              /*!< Min enumerator value of MODE field.                                  */
97760   #define VPRCSR_MTVEC_MODE_Max (0x3UL)              /*!< Max enumerator value of MODE field.                                  */
97761   #define VPRCSR_MTVEC_MODE_CLIC (0x3UL)             /*!< Core Local Interrupt Controller (CLIC) interrupt handling mode       */
97762 
97763 /* BASE @Bits 2..31 : Vector base address */
97764   #define VPRCSR_MTVEC_BASE_Pos (2UL)                /*!< Position of BASE field.                                              */
97765   #define VPRCSR_MTVEC_BASE_Msk (0x3FFFFFFFUL << VPRCSR_MTVEC_BASE_Pos) /*!< Bit mask of BASE field.                           */
97766 
97767 
97768 /**
97769   * @brief MTVT [VPRCSR_MTVT] Machine Trap Vector Table
97770   */
97771   #define VPRCSR_MTVT (0x00000307ul)
97772   #define VPRCSR_MTVT_ResetValue (0x00000000UL)      /*!< Reset value of MTVT register.                                        */
97773 
97774 /* VAL @Bits 6..31 : Machine Trap Vector Table base address value for CLIC vectored interrupts */
97775   #define VPRCSR_MTVT_VAL_Pos (6UL)                  /*!< Position of VAL field.                                               */
97776   #define VPRCSR_MTVT_VAL_Msk (0x3FFFFFFUL << VPRCSR_MTVT_VAL_Pos) /*!< Bit mask of VAL field.                                 */
97777 
97778 
97779 /**
97780   * @brief MCOUNTINHIBIT [VPRCSR_MCOUNTINHIBIT] Machine Counter-Inhibit
97781   */
97782   #define VPRCSR_MCOUNTINHIBIT (0x00000320ul)
97783   #define VPRCSR_MCOUNTINHIBIT_ResetValue (0x00000005UL) /*!< Reset value of MCOUNTINHIBIT register.                           */
97784 
97785 /* CY @Bit 0 : (unspecified) */
97786   #define VPRCSR_MCOUNTINHIBIT_CY_Pos (0UL)          /*!< Position of CY field.                                                */
97787   #define VPRCSR_MCOUNTINHIBIT_CY_Msk (0x1UL << VPRCSR_MCOUNTINHIBIT_CY_Pos) /*!< Bit mask of CY field.                        */
97788   #define VPRCSR_MCOUNTINHIBIT_CY_Min (0x0UL)        /*!< Min enumerator value of CY field.                                    */
97789   #define VPRCSR_MCOUNTINHIBIT_CY_Max (0x1UL)        /*!< Max enumerator value of CY field.                                    */
97790   #define VPRCSR_MCOUNTINHIBIT_CY_INCREMENT (0x0UL)  /*!< MCYCLE increments as usual                                           */
97791   #define VPRCSR_MCOUNTINHIBIT_CY_INHIBIT (0x1UL)    /*!< MCYCLE doesn't increment                                             */
97792 
97793 /* IR @Bit 2 : (unspecified) */
97794   #define VPRCSR_MCOUNTINHIBIT_IR_Pos (2UL)          /*!< Position of IR field.                                                */
97795   #define VPRCSR_MCOUNTINHIBIT_IR_Msk (0x1UL << VPRCSR_MCOUNTINHIBIT_IR_Pos) /*!< Bit mask of IR field.                        */
97796   #define VPRCSR_MCOUNTINHIBIT_IR_Min (0x0UL)        /*!< Min enumerator value of IR field.                                    */
97797   #define VPRCSR_MCOUNTINHIBIT_IR_Max (0x1UL)        /*!< Max enumerator value of IR field.                                    */
97798   #define VPRCSR_MCOUNTINHIBIT_IR_INCREMENT (0x0UL)  /*!< MINSTRET increments as usual                                         */
97799   #define VPRCSR_MCOUNTINHIBIT_IR_INHIBIT (0x1UL)    /*!< MINSTRET doesn't increment                                           */
97800 
97801 
97802 /**
97803   * @brief MSCRATCH [VPRCSR_MSCRATCH] Machine Scratch
97804   */
97805   #define VPRCSR_MSCRATCH (0x00000340ul)
97806   #define VPRCSR_MSCRATCH_ResetValue (0x00000000UL)  /*!< Reset value of MSCRATCH register.                                    */
97807 
97808 /* VAL @Bits 0..31 : Machine Scratch value */
97809   #define VPRCSR_MSCRATCH_VAL_Pos (0UL)              /*!< Position of VAL field.                                               */
97810   #define VPRCSR_MSCRATCH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MSCRATCH_VAL_Pos) /*!< Bit mask of VAL field.                        */
97811 
97812 
97813 /**
97814   * @brief MEPC [VPRCSR_MEPC] Machine Exception Program Counter
97815   */
97816   #define VPRCSR_MEPC (0x00000341ul)
97817   #define VPRCSR_MEPC_ResetValue (0x00000000UL)      /*!< Reset value of MEPC register.                                        */
97818 
97819 /* VAL @Bits 0..31 : Machine Exception Program Counter value */
97820   #define VPRCSR_MEPC_VAL_Pos (0UL)                  /*!< Position of VAL field.                                               */
97821   #define VPRCSR_MEPC_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MEPC_VAL_Pos) /*!< Bit mask of VAL field.                                */
97822 
97823 
97824 /**
97825   * @brief MCAUSE [VPRCSR_MCAUSE] Machine Cause
97826   */
97827   #define VPRCSR_MCAUSE (0x00000342ul)
97828   #define VPRCSR_MCAUSE_ResetValue (0x30000000UL)    /*!< Reset value of MCAUSE register.                                      */
97829 
97830 /* EXCEPTIONCODE @Bits 0..11 : Exception code */
97831   #define VPRCSR_MCAUSE_EXCEPTIONCODE_Pos (0UL)      /*!< Position of EXCEPTIONCODE field.                                     */
97832   #define VPRCSR_MCAUSE_EXCEPTIONCODE_Msk (0xFFFUL << VPRCSR_MCAUSE_EXCEPTIONCODE_Pos) /*!< Bit mask of EXCEPTIONCODE field.   */
97833   #define VPRCSR_MCAUSE_EXCEPTIONCODE_Min (0x0UL)    /*!< Min enumerator value of EXCEPTIONCODE field.                         */
97834   #define VPRCSR_MCAUSE_EXCEPTIONCODE_Max (0x1FUL)   /*!< Max enumerator value of EXCEPTIONCODE field.                         */
97835   #define VPRCSR_MCAUSE_EXCEPTIONCODE_INSTADDRMISALIGN (0x000UL) /*!< Instruction Address Misaligned                           */
97836   #define VPRCSR_MCAUSE_EXCEPTIONCODE_INSTACCESSFAULT (0x001UL) /*!< Instruction Access Fault                                  */
97837   #define VPRCSR_MCAUSE_EXCEPTIONCODE_ILLEGALINST (0x002UL) /*!< Illegal Instruction                                           */
97838   #define VPRCSR_MCAUSE_EXCEPTIONCODE_BKPT (0x003UL) /*!< Breakpoint                                                           */
97839   #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADADDRMISALIGN (0x004UL) /*!< Load Address Misaligned                                  */
97840   #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADACCESSFAULT (0x005UL) /*!< Load Access Fault                                         */
97841   #define VPRCSR_MCAUSE_EXCEPTIONCODE_STOREADDRMISALIGN (0x006UL) /*!< Store/AMO Address Misaligned                            */
97842   #define VPRCSR_MCAUSE_EXCEPTIONCODE_STOREACCESSFAULT (0x007UL) /*!< Store/AMO Access Fault                                   */
97843   #define VPRCSR_MCAUSE_EXCEPTIONCODE_ECALLMMODE (0x00BUL) /*!< Environment Call M-Mode                                        */
97844   #define VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNSTACKING (0x018UL) /*!< Misaligned Stacking                                      */
97845   #define VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTSTACKING (0x019UL) /*!< Bus Fault on Stacking                                    */
97846   #define VPRCSR_MCAUSE_EXCEPTIONCODE_INTVECTORFAULT (0x01AUL) /*!< Interrupt Vector Fault                                     */
97847   #define VPRCSR_MCAUSE_EXCEPTIONCODE_MISALIGNUNSTACKING (0x01BUL) /*!< Misaligned Unstacking                                  */
97848   #define VPRCSR_MCAUSE_EXCEPTIONCODE_BUSFAULTUNSTACKING (0x01CUL) /*!< Bus Fault on Unstacking                                */
97849   #define VPRCSR_MCAUSE_EXCEPTIONCODE_LOADTIMEOUTFAULT (0x01DUL) /*!< Load Timeout Fault                                       */
97850   #define VPRCSR_MCAUSE_EXCEPTIONCODE_STORETIMEOUTFAULT (0x01EUL) /*!< Store Timeout Fault                                     */
97851   #define VPRCSR_MCAUSE_EXCEPTIONCODE_STACKINGEXCFAULT (0x01FUL) /*!< Fault on Exception Stacking                              */
97852 
97853 /* MPIL @Bits 16..23 : Previous interrupt level */
97854   #define VPRCSR_MCAUSE_MPIL_Pos (16UL)              /*!< Position of MPIL field.                                              */
97855   #define VPRCSR_MCAUSE_MPIL_Msk (0xFFUL << VPRCSR_MCAUSE_MPIL_Pos) /*!< Bit mask of MPIL field.                               */
97856 
97857 /* MPIE @Bit 27 : Previous interrupt enable, same as MSTATUS.MPIE */
97858   #define VPRCSR_MCAUSE_MPIE_Pos (27UL)              /*!< Position of MPIE field.                                              */
97859   #define VPRCSR_MCAUSE_MPIE_Msk (0x1UL << VPRCSR_MCAUSE_MPIE_Pos) /*!< Bit mask of MPIE field.                                */
97860 
97861 /* MPP @Bits 28..29 : Previous privilege mode, same as MSTATUS.MPP */
97862   #define VPRCSR_MCAUSE_MPP_Pos (28UL)               /*!< Position of MPP field.                                               */
97863   #define VPRCSR_MCAUSE_MPP_Msk (0x3UL << VPRCSR_MCAUSE_MPP_Pos) /*!< Bit mask of MPP field.                                   */
97864 
97865 /* MINHV @Bit 30 : In hardware vectoring */
97866   #define VPRCSR_MCAUSE_MINHV_Pos (30UL)             /*!< Position of MINHV field.                                             */
97867   #define VPRCSR_MCAUSE_MINHV_Msk (0x1UL << VPRCSR_MCAUSE_MINHV_Pos) /*!< Bit mask of MINHV field.                             */
97868 
97869 /* INTERRUPT @Bit 31 : Interrupt bit */
97870   #define VPRCSR_MCAUSE_INTERRUPT_Pos (31UL)         /*!< Position of INTERRUPT field.                                         */
97871   #define VPRCSR_MCAUSE_INTERRUPT_Msk (0x1UL << VPRCSR_MCAUSE_INTERRUPT_Pos) /*!< Bit mask of INTERRUPT field.                 */
97872   #define VPRCSR_MCAUSE_INTERRUPT_Min (0x0UL)        /*!< Min enumerator value of INTERRUPT field.                             */
97873   #define VPRCSR_MCAUSE_INTERRUPT_Max (0x1UL)        /*!< Max enumerator value of INTERRUPT field.                             */
97874   #define VPRCSR_MCAUSE_INTERRUPT_EXCEPTION (0x0UL)  /*!< (unspecified)                                                        */
97875   #define VPRCSR_MCAUSE_INTERRUPT_INTERRUPT (0x1UL)  /*!< (unspecified)                                                        */
97876 
97877 
97878 /**
97879   * @brief MTVAL [VPRCSR_MTVAL] Machine Trap Value
97880   */
97881   #define VPRCSR_MTVAL (0x00000343ul)
97882   #define VPRCSR_MTVAL_ResetValue (0x00000000UL)     /*!< Reset value of MTVAL register.                                       */
97883 
97884 /* VAL @Bits 0..31 : Machine Trap Value */
97885   #define VPRCSR_MTVAL_VAL_Pos (0UL)                 /*!< Position of VAL field.                                               */
97886   #define VPRCSR_MTVAL_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MTVAL_VAL_Pos) /*!< Bit mask of VAL field.                              */
97887 
97888 
97889 /**
97890   * @brief MINTSTATUS [VPRCSR_MINTSTATUS] M-mode Interrupt Status
97891   */
97892   #define VPRCSR_MINTSTATUS (0x00000346ul)
97893   #define VPRCSR_MINTSTATUS_ResetValue (0x00000000UL) /*!< Reset value of MINTSTATUS register.                                 */
97894 
97895 /* MIL @Bits 24..31 : M-Mode interrupt level */
97896   #define VPRCSR_MINTSTATUS_MIL_Pos (24UL)           /*!< Position of MIL field.                                               */
97897   #define VPRCSR_MINTSTATUS_MIL_Msk (0xFFUL << VPRCSR_MINTSTATUS_MIL_Pos) /*!< Bit mask of MIL field.                          */
97898 
97899 
97900 /**
97901   * @brief MINTTHRESH [VPRCSR_MINTTHRESH] M-mode Interrupt-level Threshold
97902   */
97903   #define VPRCSR_MINTTHRESH (0x00000347ul)
97904   #define VPRCSR_MINTTHRESH_ResetValue (0x00000000UL) /*!< Reset value of MINTTHRESH register.                                 */
97905 
97906 /* TH @Bits 24..31 : M-Mode Interrupt-level Threshold */
97907   #define VPRCSR_MINTTHRESH_TH_Pos (24UL)            /*!< Position of TH field.                                                */
97908   #define VPRCSR_MINTTHRESH_TH_Msk (0xFFUL << VPRCSR_MINTTHRESH_TH_Pos) /*!< Bit mask of TH field.                             */
97909   #define VPRCSR_MINTTHRESH_TH_Min (0x0UL)           /*!< Min enumerator value of TH field.                                    */
97910   #define VPRCSR_MINTTHRESH_TH_Max (0xFFUL)          /*!< Max enumerator value of TH field.                                    */
97911   #define VPRCSR_MINTTHRESH_TH_DISABLED (0x00UL)     /*!< Threshold disabled                                                   */
97912   #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL0 (0x3FUL) /*!< Threshold level 0                                                    */
97913   #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL1 (0x7FUL) /*!< Threshold level 1                                                    */
97914   #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL2 (0xBFUL) /*!< Threshold level 2                                                    */
97915   #define VPRCSR_MINTTHRESH_TH_THRESHLEVEL3 (0xFFUL) /*!< Threshold level 3                                                    */
97916 
97917 
97918 /**
97919   * @brief MCLICBASE [VPRCSR_MCLICBASE] Machine CLIC Base
97920   */
97921   #define VPRCSR_MCLICBASE (0x00000350ul)
97922   #define VPRCSR_MCLICBASE_ResetValue (0x00001000UL) /*!< Reset value of MCLICBASE register.                                   */
97923 
97924 /* VAL @Bits 0..31 : CLIC base address value */
97925   #define VPRCSR_MCLICBASE_VAL_Pos (0UL)             /*!< Position of VAL field.                                               */
97926   #define VPRCSR_MCLICBASE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCLICBASE_VAL_Pos) /*!< Bit mask of VAL field.                      */
97927 
97928 
97929 /**
97930   * @brief TSELECT [VPRCSR_TSELECT] Trigger Select
97931   */
97932   #define VPRCSR_TSELECT (0x000007A0ul)
97933   #define VPRCSR_TSELECT_ResetValue (0x00000000UL)   /*!< Reset value of TSELECT register.                                     */
97934 
97935 /* VAL @Bits 0..31 : Trigger Select value */
97936   #define VPRCSR_TSELECT_VAL_Pos (0UL)               /*!< Position of VAL field.                                               */
97937   #define VPRCSR_TSELECT_VAL_Msk (0xFFFFFFFFUL << VPRCSR_TSELECT_VAL_Pos) /*!< Bit mask of VAL field.                          */
97938 
97939 
97940 /**
97941   * @brief TDATA1 [VPRCSR_TDATA1] Trigger Data 1
97942   */
97943   #define VPRCSR_TDATA1 (0x000007A1ul)
97944   #define VPRCSR_TDATA1_ResetValue (0x00000000UL)    /*!< Reset value of TDATA1 register.                                      */
97945 
97946 /* DATA @Bits 0..26 : Trigger Specific Data */
97947   #define VPRCSR_TDATA1_DATA_Pos (0UL)               /*!< Position of DATA field.                                              */
97948   #define VPRCSR_TDATA1_DATA_Msk (0x7FFFFFFUL << VPRCSR_TDATA1_DATA_Pos) /*!< Bit mask of DATA field.                          */
97949 
97950 /* DMODE @Bit 27 : Debug Mode */
97951   #define VPRCSR_TDATA1_DMODE_Pos (27UL)             /*!< Position of DMODE field.                                             */
97952   #define VPRCSR_TDATA1_DMODE_Msk (0x1UL << VPRCSR_TDATA1_DMODE_Pos) /*!< Bit mask of DMODE field.                             */
97953   #define VPRCSR_TDATA1_DMODE_Min (0x0UL)            /*!< Min enumerator value of DMODE field.                                 */
97954   #define VPRCSR_TDATA1_DMODE_Max (0x1UL)            /*!< Max enumerator value of DMODE field.                                 */
97955   #define VPRCSR_TDATA1_DMODE_BOTH (0x0UL)           /*!< Both Debug and M-mode can write the tdata registers at the selected
97956                                                           tselect.*/
97957   #define VPRCSR_TDATA1_DMODE_ONLYDEBUG (0x1UL)      /*!< Only Debug Mode can write the tdata registers at the selected tselect.
97958                                                           Writes from other modes are ignored.*/
97959 
97960 /* TYPE @Bits 28..31 : Type */
97961   #define VPRCSR_TDATA1_TYPE_Pos (28UL)              /*!< Position of TYPE field.                                              */
97962   #define VPRCSR_TDATA1_TYPE_Msk (0xFUL << VPRCSR_TDATA1_TYPE_Pos) /*!< Bit mask of TYPE field.                                */
97963   #define VPRCSR_TDATA1_TYPE_Min (0x0UL)             /*!< Min enumerator value of TYPE field.                                  */
97964   #define VPRCSR_TDATA1_TYPE_Max (0xFUL)             /*!< Max enumerator value of TYPE field.                                  */
97965   #define VPRCSR_TDATA1_TYPE_NOTRIGGER (0x0UL)       /*!< There is no trigger at this tselect                                  */
97966   #define VPRCSR_TDATA1_TYPE_MATCH (0x2UL)           /*!< The trigger is an address/data match trigger. The remaining bits in
97967                                                           this register act as described in mcontrol*/
97968   #define VPRCSR_TDATA1_TYPE_REMAP (0xFUL)           /*!< This trigger is a remapping trigger. The remaining bits in this
97969                                                           register behave as described in remapping functionality*/
97970 
97971 
97972 /**
97973   * @brief TDATA2 [VPRCSR_TDATA2] Trigger Data 2
97974   */
97975   #define VPRCSR_TDATA2 (0x000007A2ul)
97976   #define VPRCSR_TDATA2_ResetValue (0x00000000UL)    /*!< Reset value of TDATA2 register.                                      */
97977 
97978 /* DATA @Bits 0..31 : Trigger Specific Data */
97979   #define VPRCSR_TDATA2_DATA_Pos (0UL)               /*!< Position of DATA field.                                              */
97980   #define VPRCSR_TDATA2_DATA_Msk (0xFFFFFFFFUL << VPRCSR_TDATA2_DATA_Pos) /*!< Bit mask of DATA field.                         */
97981 
97982 
97983 /**
97984   * @brief TDATA3 [VPRCSR_TDATA3] Trigger Data 3
97985   */
97986   #define VPRCSR_TDATA3 (0x000007A3ul)
97987   #define VPRCSR_TDATA3_ResetValue (0x00000000UL)    /*!< Reset value of TDATA3 register.                                      */
97988 
97989 /* DATA @Bits 0..31 : Trigger Specific Data */
97990   #define VPRCSR_TDATA3_DATA_Pos (0UL)               /*!< Position of DATA field.                                              */
97991   #define VPRCSR_TDATA3_DATA_Msk (0xFFFFFFFFUL << VPRCSR_TDATA3_DATA_Pos) /*!< Bit mask of DATA field.                         */
97992 
97993 
97994 /**
97995   * @brief TINFO [VPRCSR_TINFO] Trigger Info
97996   */
97997   #define VPRCSR_TINFO (0x000007A4ul)
97998   #define VPRCSR_TINFO_ResetValue (0x00000000UL)     /*!< Reset value of TINFO register.                                       */
97999 
98000 /* INFO @Bits 0..15 : Trigger Info value */
98001   #define VPRCSR_TINFO_INFO_Pos (0UL)                /*!< Position of INFO field.                                              */
98002   #define VPRCSR_TINFO_INFO_Msk (0xFFFFUL << VPRCSR_TINFO_INFO_Pos) /*!< Bit mask of INFO field.                               */
98003 
98004 
98005 /**
98006   * @brief TCONTROL [VPRCSR_TCONTROL] Trigger Control
98007   */
98008   #define VPRCSR_TCONTROL (0x000007A5ul)
98009   #define VPRCSR_TCONTROL_ResetValue (0x00000000UL)  /*!< Reset value of TCONTROL register.                                    */
98010 
98011 /* MTE @Bit 3 : Mode Trigger Enable */
98012   #define VPRCSR_TCONTROL_MTE_Pos (3UL)              /*!< Position of MTE field.                                               */
98013   #define VPRCSR_TCONTROL_MTE_Msk (0x1UL << VPRCSR_TCONTROL_MTE_Pos) /*!< Bit mask of MTE field.                               */
98014   #define VPRCSR_TCONTROL_MTE_Min (0x0UL)            /*!< Min enumerator value of MTE field.                                   */
98015   #define VPRCSR_TCONTROL_MTE_Max (0x1UL)            /*!< Max enumerator value of MTE field.                                   */
98016   #define VPRCSR_TCONTROL_MTE_DONTMATCH (0x0UL)      /*!< Triggers with action=0 do not match/fire while the hart is in M-mode */
98017   #define VPRCSR_TCONTROL_MTE_MATCH (0x1UL)          /*!< Triggers do match/fire while the hart is in M-mode. When a trap into
98018                                                           M-mode is taken, mte is set to 0. When mret is executed, mte is set to
98019                                                           the value of mpte*/
98020 
98021 /* MPTE @Bit 7 : Mode Previous Trigger Enable */
98022   #define VPRCSR_TCONTROL_MPTE_Pos (7UL)             /*!< Position of MPTE field.                                              */
98023   #define VPRCSR_TCONTROL_MPTE_Msk (0x1UL << VPRCSR_TCONTROL_MPTE_Pos) /*!< Bit mask of MPTE field.                            */
98024 
98025 
98026 /**
98027   * @brief DCSR [VPRCSR_DCSR] Debug Control and Status
98028   */
98029   #define VPRCSR_DCSR (0x000007B0ul)
98030   #define VPRCSR_DCSR_ResetValue (0x40000003UL)      /*!< Reset value of DCSR register.                                        */
98031 
98032 /* PRV @Bits 0..1 : Privilege level */
98033   #define VPRCSR_DCSR_PRV_Pos (0UL)                  /*!< Position of PRV field.                                               */
98034   #define VPRCSR_DCSR_PRV_Msk (0x3UL << VPRCSR_DCSR_PRV_Pos) /*!< Bit mask of PRV field.                                       */
98035   #define VPRCSR_DCSR_PRV_Min (0x3UL)                /*!< Min enumerator value of PRV field.                                   */
98036   #define VPRCSR_DCSR_PRV_Max (0x3UL)                /*!< Max enumerator value of PRV field.                                   */
98037   #define VPRCSR_DCSR_PRV_MACHINE (0x3UL)            /*!< (unspecified)                                                        */
98038 
98039 /* STEP @Bit 2 : Step */
98040   #define VPRCSR_DCSR_STEP_Pos (2UL)                 /*!< Position of STEP field.                                              */
98041   #define VPRCSR_DCSR_STEP_Msk (0x1UL << VPRCSR_DCSR_STEP_Pos) /*!< Bit mask of STEP field.                                    */
98042 
98043 /* CAUSE @Bits 6..8 : Debug Mode enter cause */
98044   #define VPRCSR_DCSR_CAUSE_Pos (6UL)                /*!< Position of CAUSE field.                                             */
98045   #define VPRCSR_DCSR_CAUSE_Msk (0x7UL << VPRCSR_DCSR_CAUSE_Pos) /*!< Bit mask of CAUSE field.                                 */
98046   #define VPRCSR_DCSR_CAUSE_Min (0x1UL)              /*!< Min enumerator value of CAUSE field.                                 */
98047   #define VPRCSR_DCSR_CAUSE_Max (0x5UL)              /*!< Max enumerator value of CAUSE field.                                 */
98048   #define VPRCSR_DCSR_CAUSE_EBREAK (0x1UL)           /*!< An ebreak instruction was executed. (priority 3)                     */
98049   #define VPRCSR_DCSR_CAUSE_TRIGGER (0x2UL)          /*!< The Trigger Module caused a breakpoint exception. (priority 4,
98050                                                           highest)*/
98051   #define VPRCSR_DCSR_CAUSE_HALTREQ (0x3UL)          /*!< The debugger requested entry to Debug Mode using haltreq. (priority
98052                                                           1)*/
98053   #define VPRCSR_DCSR_CAUSE_STEP (0x4UL)             /*!< The hart single stepped because step was set. (priority 0, lowest)   */
98054   #define VPRCSR_DCSR_CAUSE_RESETHALTREQ (0x5UL)     /*!< The hart halted directly out of reset due to resethaltreq. It is also
98055                                                           acceptable to report 3 when this happens. (priority 2)*/
98056 
98057 /* STEPIE @Bit 11 : Step Interrupt Enable */
98058   #define VPRCSR_DCSR_STEPIE_Pos (11UL)              /*!< Position of STEPIE field.                                            */
98059   #define VPRCSR_DCSR_STEPIE_Msk (0x1UL << VPRCSR_DCSR_STEPIE_Pos) /*!< Bit mask of STEPIE field.                              */
98060   #define VPRCSR_DCSR_STEPIE_Min (0x0UL)             /*!< Min enumerator value of STEPIE field.                                */
98061   #define VPRCSR_DCSR_STEPIE_Max (0x1UL)             /*!< Max enumerator value of STEPIE field.                                */
98062   #define VPRCSR_DCSR_STEPIE_Disabled (0x0UL)        /*!< Interrupts are disabled during single stepping                       */
98063   #define VPRCSR_DCSR_STEPIE_Enabled (0x1UL)         /*!< Interrupts are enabled during single stepping. Implementations may
98064                                                           hard wire this bit to 0. In that case interrupt behavior can be
98065                                                           emulated by the debugger.*/
98066 
98067 /* EBREAKM @Bit 15 : M-mode ebreak */
98068   #define VPRCSR_DCSR_EBREAKM_Pos (15UL)             /*!< Position of EBREAKM field.                                           */
98069   #define VPRCSR_DCSR_EBREAKM_Msk (0x1UL << VPRCSR_DCSR_EBREAKM_Pos) /*!< Bit mask of EBREAKM field.                           */
98070   #define VPRCSR_DCSR_EBREAKM_Min (0x0UL)            /*!< Min enumerator value of EBREAKM field.                               */
98071   #define VPRCSR_DCSR_EBREAKM_Max (0x1UL)            /*!< Max enumerator value of EBREAKM field.                               */
98072   #define VPRCSR_DCSR_EBREAKM_SPEC (0x0UL)           /*!< ebreak instructions in M-mode behave as described in the Privileged
98073                                                           Spe*/
98074   #define VPRCSR_DCSR_EBREAKM_ENTERDBG (0x1UL)       /*!< ebreak instructions in M-mode enter Debug Mode                       */
98075 
98076 /* XDEBUGVER @Bits 28..31 : External Debug version */
98077   #define VPRCSR_DCSR_XDEBUGVER_Pos (28UL)           /*!< Position of XDEBUGVER field.                                         */
98078   #define VPRCSR_DCSR_XDEBUGVER_Msk (0xFUL << VPRCSR_DCSR_XDEBUGVER_Pos) /*!< Bit mask of XDEBUGVER field.                     */
98079   #define VPRCSR_DCSR_XDEBUGVER_Min (0x4UL)          /*!< Min enumerator value of XDEBUGVER field.                             */
98080   #define VPRCSR_DCSR_XDEBUGVER_Max (0x4UL)          /*!< Max enumerator value of XDEBUGVER field.                             */
98081   #define VPRCSR_DCSR_XDEBUGVER_STDDBG (0x4UL)       /*!< External debug support exists as it is described in this document    */
98082 
98083 
98084 /**
98085   * @brief DPC [VPRCSR_DPC] Debug PC
98086   */
98087   #define VPRCSR_DPC (0x000007B1ul)
98088   #define VPRCSR_DPC_ResetValue (0x00000000UL)       /*!< Reset value of DPC register.                                         */
98089 
98090 /* VAL @Bits 0..31 : Debug PC value */
98091   #define VPRCSR_DPC_VAL_Pos (0UL)                   /*!< Position of VAL field.                                               */
98092   #define VPRCSR_DPC_VAL_Msk (0xFFFFFFFFUL << VPRCSR_DPC_VAL_Pos) /*!< Bit mask of VAL field.                                  */
98093 
98094 
98095 /**
98096   * @brief MCYCLE [VPRCSR_MCYCLE] Machine Cycle Counter
98097   */
98098   #define VPRCSR_MCYCLE (0x00000B00ul)
98099   #define VPRCSR_MCYCLE_ResetValue (0x00000000UL)    /*!< Reset value of MCYCLE register.                                      */
98100 
98101 /* VAL @Bits 0..31 : Machine Cycle Counter value */
98102   #define VPRCSR_MCYCLE_VAL_Pos (0UL)                /*!< Position of VAL field.                                               */
98103   #define VPRCSR_MCYCLE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCYCLE_VAL_Pos) /*!< Bit mask of VAL field.                            */
98104 
98105 
98106 /**
98107   * @brief MINSTRET [VPRCSR_MINSTRET] Machine Instruction Counter
98108   */
98109   #define VPRCSR_MINSTRET (0x00000B02ul)
98110   #define VPRCSR_MINSTRET_ResetValue (0x00000000UL)  /*!< Reset value of MINSTRET register.                                    */
98111 
98112 /* VAL @Bits 0..31 : Machine Instruction Counter value */
98113   #define VPRCSR_MINSTRET_VAL_Pos (0UL)              /*!< Position of VAL field.                                               */
98114   #define VPRCSR_MINSTRET_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MINSTRET_VAL_Pos) /*!< Bit mask of VAL field.                        */
98115 
98116 
98117 /**
98118   * @brief MCYCLEH [VPRCSR_MCYCLEH] Machine Cycle Counter (Upper part)
98119   */
98120   #define VPRCSR_MCYCLEH (0x00000B80ul)
98121   #define VPRCSR_MCYCLEH_ResetValue (0x00000000UL)   /*!< Reset value of MCYCLEH register.                                     */
98122 
98123 /* VAL @Bits 0..31 : Machine Cycle Counter value */
98124   #define VPRCSR_MCYCLEH_VAL_Pos (0UL)               /*!< Position of VAL field.                                               */
98125   #define VPRCSR_MCYCLEH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MCYCLEH_VAL_Pos) /*!< Bit mask of VAL field.                          */
98126 
98127 
98128 /**
98129   * @brief MINSTRETH [VPRCSR_MINSTRETH] Machine Instruction Counter (Upper part)
98130   */
98131   #define VPRCSR_MINSTRETH (0x00000B82ul)
98132   #define VPRCSR_MINSTRETH_ResetValue (0x00000000UL) /*!< Reset value of MINSTRETH register.                                   */
98133 
98134 /* VAL @Bits 0..31 : Machine Instruction Counter (Upper part) value */
98135   #define VPRCSR_MINSTRETH_VAL_Pos (0UL)             /*!< Position of VAL field.                                               */
98136   #define VPRCSR_MINSTRETH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_MINSTRETH_VAL_Pos) /*!< Bit mask of VAL field.                      */
98137 
98138 
98139 /**
98140   * @brief UCYCLE [VPRCSR_UCYCLE] User Cycle Counter
98141   */
98142   #define VPRCSR_UCYCLE (0x00000C00ul)
98143   #define VPRCSR_UCYCLE_ResetValue (0x00000000UL)    /*!< Reset value of UCYCLE register.                                      */
98144 
98145 /* VAL @Bits 0..31 : User Cycle Counter value */
98146   #define VPRCSR_UCYCLE_VAL_Pos (0UL)                /*!< Position of VAL field.                                               */
98147   #define VPRCSR_UCYCLE_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UCYCLE_VAL_Pos) /*!< Bit mask of VAL field.                            */
98148 
98149 
98150 /**
98151   * @brief UINSTRET [VPRCSR_UINSTRET] User Instruction Counter
98152   */
98153   #define VPRCSR_UINSTRET (0x00000C02ul)
98154   #define VPRCSR_UINSTRET_ResetValue (0x00000000UL)  /*!< Reset value of UINSTRET register.                                    */
98155 
98156 /* VAL @Bits 0..31 : User Instruction Counter value */
98157   #define VPRCSR_UINSTRET_VAL_Pos (0UL)              /*!< Position of VAL field.                                               */
98158   #define VPRCSR_UINSTRET_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UINSTRET_VAL_Pos) /*!< Bit mask of VAL field.                        */
98159 
98160 
98161 /**
98162   * @brief UCYCLEH [VPRCSR_UCYCLEH] User Cycle Counter (Upper part)
98163   */
98164   #define VPRCSR_UCYCLEH (0x00000C80ul)
98165   #define VPRCSR_UCYCLEH_ResetValue (0x00000000UL)   /*!< Reset value of UCYCLEH register.                                     */
98166 
98167 /* VAL @Bits 0..31 : User Cycle Counter value */
98168   #define VPRCSR_UCYCLEH_VAL_Pos (0UL)               /*!< Position of VAL field.                                               */
98169   #define VPRCSR_UCYCLEH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UCYCLEH_VAL_Pos) /*!< Bit mask of VAL field.                          */
98170 
98171 
98172 /**
98173   * @brief UINSTRETH [VPRCSR_UINSTRETH] User Instruction Counter (Upper part)
98174   */
98175   #define VPRCSR_UINSTRETH (0x00000C82ul)
98176   #define VPRCSR_UINSTRETH_ResetValue (0x00000000UL) /*!< Reset value of UINSTRETH register.                                   */
98177 
98178 /* VAL @Bits 0..31 : User Instruction Counter (Upper part) value */
98179   #define VPRCSR_UINSTRETH_VAL_Pos (0UL)             /*!< Position of VAL field.                                               */
98180   #define VPRCSR_UINSTRETH_VAL_Msk (0xFFFFFFFFUL << VPRCSR_UINSTRETH_VAL_Pos) /*!< Bit mask of VAL field.                      */
98181 
98182 
98183 /**
98184   * @brief MVENDORID [VPRCSR_MVENDORID] Machine Vendor ID
98185   */
98186   #define VPRCSR_MVENDORID (0x00000F11ul)
98187   #define VPRCSR_MVENDORID_ResetValue (0x00000144UL) /*!< Reset value of MVENDORID register.                                   */
98188 
98189 /* OFFSET @Bits 0..6 : MVENDORID encodes the final byte in the Offset field, discarding the parity bit */
98190   #define VPRCSR_MVENDORID_OFFSET_Pos (0UL)          /*!< Position of OFFSET field.                                            */
98191   #define VPRCSR_MVENDORID_OFFSET_Msk (0x7FUL << VPRCSR_MVENDORID_OFFSET_Pos) /*!< Bit mask of OFFSET field.                   */
98192 
98193 /* BANK @Bits 7..31 : MVENDORID encodes the number of one-byte continuation codes in the Bank field */
98194   #define VPRCSR_MVENDORID_BANK_Pos (7UL)            /*!< Position of BANK field.                                              */
98195   #define VPRCSR_MVENDORID_BANK_Msk (0x1FFFFFFUL << VPRCSR_MVENDORID_BANK_Pos) /*!< Bit mask of BANK field.                    */
98196 
98197 
98198 /**
98199   * @brief MARCHID [VPRCSR_MARCHID] Machine Architecture ID
98200   */
98201   #define VPRCSR_MARCHID (0x00000F12ul)
98202   #define VPRCSR_MARCHID_ResetValue (0x800000AEUL)   /*!< Reset value of MARCHID register.                                     */
98203 
98204 /* MULDIV @Bits 0..1 : Indicates the MULDIV parameter option */
98205   #define VPRCSR_MARCHID_MULDIV_Pos (0UL)            /*!< Position of MULDIV field.                                            */
98206   #define VPRCSR_MARCHID_MULDIV_Msk (0x3UL << VPRCSR_MARCHID_MULDIV_Pos) /*!< Bit mask of MULDIV field.                        */
98207 
98208 /* HIBERNATE @Bit 2 : Indicates the HIBERNATE parameter option */
98209   #define VPRCSR_MARCHID_HIBERNATE_Pos (2UL)         /*!< Position of HIBERNATE field.                                         */
98210   #define VPRCSR_MARCHID_HIBERNATE_Msk (0x1UL << VPRCSR_MARCHID_HIBERNATE_Pos) /*!< Bit mask of HIBERNATE field.               */
98211 
98212 /* DBG @Bit 3 : Indicates the DBG parameter option */
98213   #define VPRCSR_MARCHID_DBG_Pos (3UL)               /*!< Position of DBG field.                                               */
98214   #define VPRCSR_MARCHID_DBG_Msk (0x1UL << VPRCSR_MARCHID_DBG_Pos) /*!< Bit mask of DBG field.                                 */
98215 
98216 /* REMAP @Bit 4 : Indicates the REMAP parameter option */
98217   #define VPRCSR_MARCHID_REMAP_Pos (4UL)             /*!< Position of REMAP field.                                             */
98218   #define VPRCSR_MARCHID_REMAP_Msk (0x1UL << VPRCSR_MARCHID_REMAP_Pos) /*!< Bit mask of REMAP field.                           */
98219 
98220 /* BUSWIDTH @Bit 5 : Indicates the BUS_WIDTH parameter option */
98221   #define VPRCSR_MARCHID_BUSWIDTH_Pos (5UL)          /*!< Position of BUSWIDTH field.                                          */
98222   #define VPRCSR_MARCHID_BUSWIDTH_Msk (0x1UL << VPRCSR_MARCHID_BUSWIDTH_Pos) /*!< Bit mask of BUSWIDTH field.                  */
98223 
98224 /* BKPT @Bits 6..8 : Indicates the BKPT parameter option */
98225   #define VPRCSR_MARCHID_BKPT_Pos (6UL)              /*!< Position of BKPT field.                                              */
98226   #define VPRCSR_MARCHID_BKPT_Msk (0x7UL << VPRCSR_MARCHID_BKPT_Pos) /*!< Bit mask of BKPT field.                              */
98227 
98228 /* IMPLEM @Bit 31 : Indicates a non-open implementation */
98229   #define VPRCSR_MARCHID_IMPLEM_Pos (31UL)           /*!< Position of IMPLEM field.                                            */
98230   #define VPRCSR_MARCHID_IMPLEM_Msk (0x1UL << VPRCSR_MARCHID_IMPLEM_Pos) /*!< Bit mask of IMPLEM field.                        */
98231 
98232 
98233 /**
98234   * @brief MIMPID [VPRCSR_MIMPID] Machine Implementation ID
98235   */
98236   #define VPRCSR_MIMPID (0x00000F13ul)
98237   #define VPRCSR_MIMPID_ResetValue (0x00010201UL)    /*!< Reset value of MIMPID register.                                      */
98238 
98239 /* PATCHREV @Bits 0..7 : Indicates the number of the patch revision */
98240   #define VPRCSR_MIMPID_PATCHREV_Pos (0UL)           /*!< Position of PATCHREV field.                                          */
98241   #define VPRCSR_MIMPID_PATCHREV_Msk (0xFFUL << VPRCSR_MIMPID_PATCHREV_Pos) /*!< Bit mask of PATCHREV field.                   */
98242 
98243 /* MINORREV @Bits 8..15 : Indicates the number of the minor revision */
98244   #define VPRCSR_MIMPID_MINORREV_Pos (8UL)           /*!< Position of MINORREV field.                                          */
98245   #define VPRCSR_MIMPID_MINORREV_Msk (0xFFUL << VPRCSR_MIMPID_MINORREV_Pos) /*!< Bit mask of MINORREV field.                   */
98246 
98247 /* MAJORREV @Bits 16..23 : Indicates the number of the major revison */
98248   #define VPRCSR_MIMPID_MAJORREV_Pos (16UL)          /*!< Position of MAJORREV field.                                          */
98249   #define VPRCSR_MIMPID_MAJORREV_Msk (0xFFUL << VPRCSR_MIMPID_MAJORREV_Pos) /*!< Bit mask of MAJORREV field.                   */
98250 
98251 
98252 /**
98253   * @brief MHARTID [VPRCSR_MHARTID] Machine Hart ID
98254   */
98255   #define VPRCSR_MHARTID (0x00000F14ul)
98256   #define VPRCSR_MHARTID_ResetValue (0x00000000UL)   /*!< Reset value of MHARTID register.                                     */
98257 
98258 /* HARTNUM @Bits 0..31 : Machine Hart ID value */
98259   #define VPRCSR_MHARTID_HARTNUM_Pos (0UL)           /*!< Position of HARTNUM field.                                           */
98260   #define VPRCSR_MHARTID_HARTNUM_Msk (0xFFFFFFFFUL << VPRCSR_MHARTID_HARTNUM_Pos) /*!< Bit mask of HARTNUM field.              */
98261 
98262 
98263 /**
98264   * @brief NORDIC [VPRCSR_NORDIC] (unspecified)
98265   */
98266 
98267 /**
98268   * @brief VPRNORDICCTRL [VPRCSR_NORDIC_VPRNORDICCTRL] Nordic Core Control
98269   */
98270   #define VPRCSR_NORDIC_VPRNORDICCTRL (0x000007C0ul)
98271   #define VPRCSR_NORDIC_VPRNORDICCTRL_ResetValue (0x00000000UL) /*!< Reset value of VPRNORDICCTRL register.                    */
98272 
98273 /* ENABLERTPERIPH @Bit 0 : Control bit to enable Real-Time Peripherals */
98274   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos (0UL) /*!< Position of ENABLERTPERIPH field.                          */
98275   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Pos) /*!< Bit mask
98276                                                                             of ENABLERTPERIPH field.*/
98277   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Min (0x0UL) /*!< Min enumerator value of ENABLERTPERIPH field.            */
98278   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Max (0x1UL) /*!< Max enumerator value of ENABLERTPERIPH field.            */
98279   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Disabled (0x0UL) /*!< (unspecified)                                       */
98280   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLERTPERIPH_Enabled (0x1UL) /*!< (unspecified)                                        */
98281 
98282 /* ENABLEREMAP @Bit 3 : Enable remap feature */
98283   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos (3UL) /*!< Position of ENABLEREMAP field.                                */
98284   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Pos) /*!< Bit mask of
98285                                                                             ENABLEREMAP field.*/
98286   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Min (0x0UL) /*!< Min enumerator value of ENABLEREMAP field.                  */
98287   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Max (0x1UL) /*!< Max enumerator value of ENABLEREMAP field.                  */
98288   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Disabled (0x0UL) /*!< (unspecified)                                          */
98289   #define VPRCSR_NORDIC_VPRNORDICCTRL_ENABLEREMAP_Enabled (0x1UL) /*!< (unspecified)                                           */
98290 
98291 /* CNTIRQENABLE @Bit 6 : Enables the generation of IRQ number COUNTER_IRQ_NUM */
98292   #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos (6UL) /*!< Position of CNTIRQENABLE field.                              */
98293   #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Pos) /*!< Bit mask of
98294                                                                             CNTIRQENABLE field.*/
98295   #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Min (0x0UL) /*!< Min enumerator value of CNTIRQENABLE field.                */
98296   #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Max (0x1UL) /*!< Max enumerator value of CNTIRQENABLE field.                */
98297   #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Disabled (0x0UL) /*!< (unspecified)                                         */
98298   #define VPRCSR_NORDIC_VPRNORDICCTRL_CNTIRQENABLE_Enabled (0x1UL) /*!< (unspecified)                                          */
98299 
98300 /* NORDICKEY @Bits 16..31 : Used in order to protect the write to this register */
98301   #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos (16UL) /*!< Position of NORDICKEY field.                                   */
98302   #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Msk (0xFFFFUL << VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Pos) /*!< Bit mask of
98303                                                                             NORDICKEY field.*/
98304   #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Min (0x507DUL) /*!< Min enumerator value of NORDICKEY field.                   */
98305   #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Max (0x507DUL) /*!< Max enumerator value of NORDICKEY field.                   */
98306   #define VPRCSR_NORDIC_VPRNORDICCTRL_NORDICKEY_Enabled (0x507DUL) /*!< Write enabled                                          */
98307 
98308 
98309 /**
98310   * @brief VPRNORDICSLEEPCTRL [VPRCSR_NORDIC_VPRNORDICSLEEPCTRL] Nordic Sleep Control
98311   */
98312   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL (0x000007C1ul)
98313   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_ResetValue (0x00000002UL) /*!< Reset value of VPRNORDICSLEEPCTRL register.          */
98314 
98315 /* SLEEPSTATE @Bits 0..3 : Sleep State */
98316   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field.                             */
98317   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Msk (0xFUL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Pos) /*!< Bit
98318                                                                             mask of SLEEPSTATE field.*/
98319   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Min (0x0UL) /*!< Min enumerator value of SLEEPSTATE field.               */
98320   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_Max (0xFUL) /*!< Max enumerator value of SLEEPSTATE field.               */
98321   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_WAIT (0x0UL) /*!< Sleep is not turning off the clock                     */
98322   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_RESET (0x2UL) /*!< Sleep state default reset value. Going to sleep with
98323                                                                          sleep state = RESET has the same effect as going to
98324                                                                          sleep with sleep state = WAIT*/
98325   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_SLEEP (0x5UL) /*!< Sleep is turning the clock off                        */
98326   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_DEEPSLEEP (0x7UL) /*!< Sleep is turning the clock off and power is turned
98327                                                                             off*/
98328   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_SLEEPSTATE_HIBERNATE (0xFUL) /*!< sleep is turning the clock off and all the
98329                                                                             registers are saved automatically, restart by a
98330                                                                             reset*/
98331 
98332 /* RETURNTOSLEEP @Bit 16 : Return to Sleep */
98333   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos (16UL) /*!< Position of RETURNTOSLEEP field.                      */
98334   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Pos) /*!<
98335                                                                             Bit mask of RETURNTOSLEEP field.*/
98336   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Min (0x0UL) /*!< Min enumerator value of RETURNTOSLEEP field.         */
98337   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Max (0x1UL) /*!< Max enumerator value of RETURNTOSLEEP field.         */
98338   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Disabled (0x0UL) /*!< (unspecified)                                   */
98339   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_RETURNTOSLEEP_Enabled (0x1UL) /*!< (unspecified)                                    */
98340 
98341 /* STACKONSLEEP @Bit 17 : Stack on Sleep */
98342   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos (17UL) /*!< Position of STACKONSLEEP field.                        */
98343   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Pos) /*!<
98344                                                                             Bit mask of STACKONSLEEP field.*/
98345   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Min (0x0UL) /*!< Min enumerator value of STACKONSLEEP field.           */
98346   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Max (0x1UL) /*!< Max enumerator value of STACKONSLEEP field.           */
98347   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Disabled (0x0UL) /*!< (unspecified)                                    */
98348   #define VPRCSR_NORDIC_VPRNORDICSLEEPCTRL_STACKONSLEEP_Enabled (0x1UL) /*!< (unspecified)                                     */
98349 
98350 
98351 /**
98352   * @brief VPRNORDICFEATURESDISABLE [VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE] (unspecified)
98353   */
98354   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE (0x000007C2ul)
98355   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_ResetValue (0x00000002UL) /*!< Reset value of VPRNORDICFEATURESDISABLE
98356                                                                             register.*/
98357 
98358 /* DISABLECLICROUNDROBIN @Bit 3 : Disable CLIC Round Robin */
98359   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos (3UL) /*!< Position of DISABLECLICROUNDROBIN field. */
98360   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Pos)
98361                                                                             /*!< Bit mask of DISABLECLICROUNDROBIN field.*/
98362   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Min (0x0UL) /*!< Min enumerator value of
98363                                                                             DISABLECLICROUNDROBIN field.*/
98364   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Max (0x1UL) /*!< Max enumerator value of
98365                                                                             DISABLECLICROUNDROBIN field.*/
98366   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Enabled (0x0UL) /*!< (unspecified)                      */
98367   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_DISABLECLICROUNDROBIN_Disabled (0x1UL) /*!< (unspecified)                     */
98368 
98369 /* UNRECOVRETURN @Bit 4 : Unrecoverable Return */
98370   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos (4UL) /*!< Position of UNRECOVRETURN field.                 */
98371   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Msk (0x1UL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Pos)
98372                                                                             /*!< Bit mask of UNRECOVRETURN field.*/
98373   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Min (0x0UL) /*!< Min enumerator value of UNRECOVRETURN field.   */
98374   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Max (0x1UL) /*!< Max enumerator value of UNRECOVRETURN field.   */
98375   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Disabled (0x0UL) /*!< (unspecified)                             */
98376   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_UNRECOVRETURN_Enabled (0x1UL) /*!< (unspecified)                              */
98377 
98378 /* NORDICKEY @Bits 16..31 : Used in order to protect the write to this register */
98379   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Pos (16UL) /*!< Position of NORDICKEY field.                        */
98380   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Msk (0xFFFFUL << VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Pos)
98381                                                                             /*!< Bit mask of NORDICKEY field.*/
98382   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Min (0x507DUL) /*!< Min enumerator value of NORDICKEY field.        */
98383   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Max (0x507DUL) /*!< Max enumerator value of NORDICKEY field.        */
98384   #define VPRCSR_NORDIC_VPRNORDICFEATURESDISABLE_NORDICKEY_Enabled (0x507DUL) /*!< Write enabled                               */
98385 
98386 
98387 /**
98388   * @brief VIOPINS [VPRCSR_NORDIC_VIOPINS] VPR pins used for Real Time Peripherals VIO
98389   */
98390   #define VPRCSR_NORDIC_VIOPINS (0x000007C3ul)
98391   #define VPRCSR_NORDIC_VIOPINS_ResetValue (0x00000000UL) /*!< Reset value of VIOPINS register.                                */
98392 
98393 /* VAL @Bits 0..31 : VPR pins used for Real Time Peripherals VIO */
98394   #define VPRCSR_NORDIC_VIOPINS_VAL_Pos (0UL)        /*!< Position of VAL field.                                               */
98395   #define VPRCSR_NORDIC_VIOPINS_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_VIOPINS_VAL_Pos) /*!< Bit mask of VAL field.            */
98396 
98397 
98398 /**
98399   * @brief EXTPARAMS [VPRCSR_NORDIC_EXTPARAMS] Reads values of external configuration parameters
98400   */
98401   #define VPRCSR_NORDIC_EXTPARAMS (0x000007C4ul)
98402   #define VPRCSR_NORDIC_EXTPARAMS_ResetValue (0x00000016UL) /*!< Reset value of EXTPARAMS register.                            */
98403 
98404 /* MULDIV @Bits 0..1 : value of MULDIV */
98405   #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos (0UL)   /*!< Position of MULDIV field.                                            */
98406   #define VPRCSR_NORDIC_EXTPARAMS_MULDIV_Msk (0x3UL << VPRCSR_NORDIC_EXTPARAMS_MULDIV_Pos) /*!< Bit mask of MULDIV field.      */
98407 
98408 /* DBG @Bit 2 : value of DBG */
98409   #define VPRCSR_NORDIC_EXTPARAMS_DBG_Pos (2UL)      /*!< Position of DBG field.                                               */
98410   #define VPRCSR_NORDIC_EXTPARAMS_DBG_Msk (0x1UL << VPRCSR_NORDIC_EXTPARAMS_DBG_Pos) /*!< Bit mask of DBG field.               */
98411 
98412 /* BKPT @Bits 3..6 : value of BKPT */
98413   #define VPRCSR_NORDIC_EXTPARAMS_BKPT_Pos (3UL)     /*!< Position of BKPT field.                                              */
98414   #define VPRCSR_NORDIC_EXTPARAMS_BKPT_Msk (0xFUL << VPRCSR_NORDIC_EXTPARAMS_BKPT_Pos) /*!< Bit mask of BKPT field.            */
98415 
98416 /* REMAP @Bit 7 : value of REMAP */
98417   #define VPRCSR_NORDIC_EXTPARAMS_REMAP_Pos (7UL)    /*!< Position of REMAP field.                                             */
98418   #define VPRCSR_NORDIC_EXTPARAMS_REMAP_Msk (0x1UL << VPRCSR_NORDIC_EXTPARAMS_REMAP_Pos) /*!< Bit mask of REMAP field.         */
98419 
98420 
98421 /**
98422   * @brief CNTMODE0 [VPRCSR_NORDIC_CNTMODE0] CNT0 Mode
98423   */
98424   #define VPRCSR_NORDIC_CNTMODE0 (0x000007D0ul)
98425   #define VPRCSR_NORDIC_CNTMODE0_ResetValue (0x00000000UL) /*!< Reset value of CNTMODE0 register.                              */
98426 
98427 /* CNTMODE0 @Bits 0..1 : CNT0 Mode */
98428   #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Pos (0UL)  /*!< Position of CNTMODE0 field.                                          */
98429   #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Msk (0x3UL << VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Pos) /*!< Bit mask of CNTMODE0 field.  */
98430   #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Min (0x0UL) /*!< Min enumerator value of CNTMODE0 field.                             */
98431   #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_Max (0x3UL) /*!< Max enumerator value of CNTMODE0 field.                             */
98432   #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_STOP (0x0UL) /*!< CNT0 stops at 0                                                    */
98433   #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_WRAP (0x1UL) /*!< CNT0 will continue counting from 0xFFFF                            */
98434   #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_RELOAD (0x2UL) /*!< CNT0 will continue counting from the value in CNTTOP             */
98435   #define VPRCSR_NORDIC_CNTMODE0_CNTMODE0_TRIGCOMB (0x3UL) /*!< In Trigger mode CNT0 stops counting at 0. Counting will restart
98436                                                                 when a VIO event happens*/
98437 
98438 
98439 /**
98440   * @brief CNTMODE1 [VPRCSR_NORDIC_CNTMODE1] CNT1 Mode
98441   */
98442   #define VPRCSR_NORDIC_CNTMODE1 (0x000007D1ul)
98443   #define VPRCSR_NORDIC_CNTMODE1_ResetValue (0x00000000UL) /*!< Reset value of CNTMODE1 register.                              */
98444 
98445 /* CNTMODE1 @Bits 0..1 : CNT1 Mode */
98446   #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Pos (0UL)  /*!< Position of CNTMODE1 field.                                          */
98447   #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Msk (0x3UL << VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Pos) /*!< Bit mask of CNTMODE1 field.  */
98448   #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Min (0x0UL) /*!< Min enumerator value of CNTMODE1 field.                             */
98449   #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_Max (0x3UL) /*!< Max enumerator value of CNTMODE1 field.                             */
98450   #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_STOP (0x0UL) /*!< CNT1 stops at 0                                                    */
98451   #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_WRAP (0x1UL) /*!< CNT1 will continue counting from 0xFFFF                            */
98452   #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_RELOAD (0x2UL) /*!< CNT1 will continue counting from the value in CNTTOP             */
98453   #define VPRCSR_NORDIC_CNTMODE1_CNTMODE1_TRIGCOMB (0x3UL) /*!< In combine mode mode CNT1 acts as an extension of CNT0 (16 most
98454                                                                 significant bits of the 32-bit CNT)*/
98455 
98456 
98457 /**
98458   * @brief CNT [VPRCSR_NORDIC_CNT] 32-bit Counter
98459   */
98460   #define VPRCSR_NORDIC_CNT (0x000007D2ul)
98461   #define VPRCSR_NORDIC_CNT_ResetValue (0x00000000UL) /*!< Reset value of CNT register.                                        */
98462 
98463 /* CNT0 @Bits 0..15 : 16-bit Counter 0 */
98464   #define VPRCSR_NORDIC_CNT_CNT0_Pos (0UL)           /*!< Position of CNT0 field.                                              */
98465   #define VPRCSR_NORDIC_CNT_CNT0_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT_CNT0_Pos) /*!< Bit mask of CNT0 field.                     */
98466 
98467 /* CNT1 @Bits 16..31 : 16-bit Counter 1 */
98468   #define VPRCSR_NORDIC_CNT_CNT1_Pos (16UL)          /*!< Position of CNT1 field.                                              */
98469   #define VPRCSR_NORDIC_CNT_CNT1_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT_CNT1_Pos) /*!< Bit mask of CNT1 field.                     */
98470 
98471 
98472 /**
98473   * @brief CNTTOP [VPRCSR_NORDIC_CNTTOP] Counter Top
98474   */
98475   #define VPRCSR_NORDIC_CNTTOP (0x000007D3ul)
98476   #define VPRCSR_NORDIC_CNTTOP_ResetValue (0x00000000UL) /*!< Reset value of CNTTOP register.                                  */
98477 
98478 /* CNT0RELOAD @Bits 0..15 : Reload value for CNT0 */
98479   #define VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos (0UL)  /*!< Position of CNT0RELOAD field.                                        */
98480   #define VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Msk (0xFFFFUL << VPRCSR_NORDIC_CNTTOP_CNT0RELOAD_Pos) /*!< Bit mask of CNT0RELOAD
98481                                                                             field.*/
98482 
98483 /* CNT1RELOAD @Bits 16..31 : Reload value for CNT1 */
98484   #define VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos (16UL) /*!< Position of CNT1RELOAD field.                                        */
98485   #define VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Msk (0xFFFFUL << VPRCSR_NORDIC_CNTTOP_CNT1RELOAD_Pos) /*!< Bit mask of CNT1RELOAD
98486                                                                             field.*/
98487 
98488 
98489 /**
98490   * @brief CNTADD [VPRCSR_NORDIC_CNTADD] CNT Add
98491   */
98492   #define VPRCSR_NORDIC_CNTADD (0x000007D4ul)
98493   #define VPRCSR_NORDIC_CNTADD_ResetValue (0x00000000UL) /*!< Reset value of CNTADD register.                                  */
98494 
98495 /* VAL @Bits 0..31 : Value added to CNT */
98496   #define VPRCSR_NORDIC_CNTADD_VAL_Pos (0UL)         /*!< Position of VAL field.                                               */
98497   #define VPRCSR_NORDIC_CNTADD_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD_VAL_Pos) /*!< Bit mask of VAL field.              */
98498 
98499 
98500 /**
98501   * @brief CNT0 [VPRCSR_NORDIC_CNT0] 16 bit Counter 0
98502   */
98503   #define VPRCSR_NORDIC_CNT0 (0x000007D5ul)
98504   #define VPRCSR_NORDIC_CNT0_ResetValue (0x00000000UL) /*!< Reset value of CNT0 register.                                      */
98505 
98506 /* VAL @Bits 0..15 : CNT0 value */
98507   #define VPRCSR_NORDIC_CNT0_VAL_Pos (0UL)           /*!< Position of VAL field.                                               */
98508   #define VPRCSR_NORDIC_CNT0_VAL_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT0_VAL_Pos) /*!< Bit mask of VAL field.                      */
98509 
98510 
98511 /**
98512   * @brief CNTADD0 [VPRCSR_NORDIC_CNTADD0] CNT0 Add
98513   */
98514   #define VPRCSR_NORDIC_CNTADD0 (0x000007D6ul)
98515   #define VPRCSR_NORDIC_CNTADD0_ResetValue (0x00000000UL) /*!< Reset value of CNTADD0 register.                                */
98516 
98517 /* VAL @Bits 0..31 : Value added to CNT0 */
98518   #define VPRCSR_NORDIC_CNTADD0_VAL_Pos (0UL)        /*!< Position of VAL field.                                               */
98519   #define VPRCSR_NORDIC_CNTADD0_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD0_VAL_Pos) /*!< Bit mask of VAL field.            */
98520 
98521 
98522 /**
98523   * @brief CNT1 [VPRCSR_NORDIC_CNT1] 16-bit Counter 1
98524   */
98525   #define VPRCSR_NORDIC_CNT1 (0x000007D7ul)
98526   #define VPRCSR_NORDIC_CNT1_ResetValue (0x00000000UL) /*!< Reset value of CNT1 register.                                      */
98527 
98528 /* VAL @Bits 0..15 : CNT1 value */
98529   #define VPRCSR_NORDIC_CNT1_VAL_Pos (0UL)           /*!< Position of VAL field.                                               */
98530   #define VPRCSR_NORDIC_CNT1_VAL_Msk (0xFFFFUL << VPRCSR_NORDIC_CNT1_VAL_Pos) /*!< Bit mask of VAL field.                      */
98531 
98532 
98533 /**
98534   * @brief CNTADD1 [VPRCSR_NORDIC_CNTADD1] CNT1 Add
98535   */
98536   #define VPRCSR_NORDIC_CNTADD1 (0x000007D8ul)
98537   #define VPRCSR_NORDIC_CNTADD1_ResetValue (0x00000000UL) /*!< Reset value of CNTADD1 register.                                */
98538 
98539 /* VAL @Bits 0..31 : Value added to CNT1 */
98540   #define VPRCSR_NORDIC_CNTADD1_VAL_Pos (0UL)        /*!< Position of VAL field.                                               */
98541   #define VPRCSR_NORDIC_CNTADD1_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_CNTADD1_VAL_Pos) /*!< Bit mask of VAL field.            */
98542 
98543 
98544 /**
98545   * @brief WAIT0 [VPRCSR_NORDIC_WAIT0] Wait 0
98546   */
98547   #define VPRCSR_NORDIC_WAIT0 (0x000007DAul)
98548   #define VPRCSR_NORDIC_WAIT0_ResetValue (0x00000000UL) /*!< Reset value of WAIT0 register.                                    */
98549 
98550 /* DATA @Bits 0..15 : Value to write to CNT0 */
98551   #define VPRCSR_NORDIC_WAIT0_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
98552   #define VPRCSR_NORDIC_WAIT0_DATA_Msk (0xFFFFUL << VPRCSR_NORDIC_WAIT0_DATA_Pos) /*!< Bit mask of DATA field.                 */
98553 
98554 /* WRITEDATA @Bit 16 : (unspecified) */
98555   #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos (16UL)   /*!< Position of WRITEDATA field.                                         */
98556   #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Msk (0x1UL << VPRCSR_NORDIC_WAIT0_WRITEDATA_Pos) /*!< Bit mask of WRITEDATA field.     */
98557   #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Min (0x0UL)  /*!< Min enumerator value of WRITEDATA field.                             */
98558   #define VPRCSR_NORDIC_WAIT0_WRITEDATA_Max (0x1UL)  /*!< Max enumerator value of WRITEDATA field.                             */
98559   #define VPRCSR_NORDIC_WAIT0_WRITEDATA_WAIT (0x0UL) /*!< Wait until CNT0 reaches 0                                            */
98560   #define VPRCSR_NORDIC_WAIT0_WRITEDATA_WRITE (0x1UL) /*!< Write DATA to CNT0 and then wait until CNT0 reaches 0               */
98561 
98562 
98563 /**
98564   * @brief WAIT1 [VPRCSR_NORDIC_WAIT1] Wait 1
98565   */
98566   #define VPRCSR_NORDIC_WAIT1 (0x000007DBul)
98567   #define VPRCSR_NORDIC_WAIT1_ResetValue (0x00000000UL) /*!< Reset value of WAIT1 register.                                    */
98568 
98569 /* DATA @Bits 0..15 : Value to write to CNT1 */
98570   #define VPRCSR_NORDIC_WAIT1_DATA_Pos (0UL)         /*!< Position of DATA field.                                              */
98571   #define VPRCSR_NORDIC_WAIT1_DATA_Msk (0xFFFFUL << VPRCSR_NORDIC_WAIT1_DATA_Pos) /*!< Bit mask of DATA field.                 */
98572 
98573 /* WRITEDATA @Bit 16 : (unspecified) */
98574   #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos (16UL)   /*!< Position of WRITEDATA field.                                         */
98575   #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Msk (0x1UL << VPRCSR_NORDIC_WAIT1_WRITEDATA_Pos) /*!< Bit mask of WRITEDATA field.     */
98576   #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Min (0x0UL)  /*!< Min enumerator value of WRITEDATA field.                             */
98577   #define VPRCSR_NORDIC_WAIT1_WRITEDATA_Max (0x1UL)  /*!< Max enumerator value of WRITEDATA field.                             */
98578   #define VPRCSR_NORDIC_WAIT1_WRITEDATA_WAIT (0x0UL) /*!< Wait until CNT1 reaches 0                                            */
98579   #define VPRCSR_NORDIC_WAIT1_WRITEDATA_WRITE (0x1UL) /*!< Write DATA to CNT1 and then wait until CNT1 reaches 0               */
98580 
98581 
98582 /**
98583   * @brief WAIT [VPRCSR_NORDIC_WAIT] Wait
98584   */
98585   #define VPRCSR_NORDIC_WAIT (0x000007DCul)
98586   #define VPRCSR_NORDIC_WAIT_ResetValue (0x00000000UL) /*!< Reset value of WAIT register.                                      */
98587 
98588 /* VAL @Bits 0..31 : (unspecified) */
98589   #define VPRCSR_NORDIC_WAIT_VAL_Pos (0UL)           /*!< Position of VAL field.                                               */
98590   #define VPRCSR_NORDIC_WAIT_VAL_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_WAIT_VAL_Pos) /*!< Bit mask of VAL field.                  */
98591 
98592 
98593 /**
98594   * @brief TASKS [VPRCSR_NORDIC_TASKS] DPPI Tasks
98595   */
98596   #define VPRCSR_NORDIC_TASKS (0x000007E0ul)
98597   #define VPRCSR_NORDIC_TASKS_ResetValue (0x00000000UL) /*!< Reset value of TASKS register.                                    */
98598 
98599 /* TASKS0 @Bit 0 : (unspecified) */
98600   #define VPRCSR_NORDIC_TASKS_TASKS0_Pos (0UL)       /*!< Position of TASKS0 field.                                            */
98601   #define VPRCSR_NORDIC_TASKS_TASKS0_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS0_Pos) /*!< Bit mask of TASKS0 field.              */
98602   #define VPRCSR_NORDIC_TASKS_TASKS0_Min (0x0UL)     /*!< Min enumerator value of TASKS0 field.                                */
98603   #define VPRCSR_NORDIC_TASKS_TASKS0_Max (0x1UL)     /*!< Max enumerator value of TASKS0 field.                                */
98604   #define VPRCSR_NORDIC_TASKS_TASKS0_Disabled (0x0UL) /*!< TASKS[0] diabled                                                    */
98605   #define VPRCSR_NORDIC_TASKS_TASKS0_Enabled (0x1UL) /*!< TASKS[0] enabled                                                     */
98606 
98607 /* TASKS1 @Bit 1 : (unspecified) */
98608   #define VPRCSR_NORDIC_TASKS_TASKS1_Pos (1UL)       /*!< Position of TASKS1 field.                                            */
98609   #define VPRCSR_NORDIC_TASKS_TASKS1_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS1_Pos) /*!< Bit mask of TASKS1 field.              */
98610   #define VPRCSR_NORDIC_TASKS_TASKS1_Min (0x0UL)     /*!< Min enumerator value of TASKS1 field.                                */
98611   #define VPRCSR_NORDIC_TASKS_TASKS1_Max (0x1UL)     /*!< Max enumerator value of TASKS1 field.                                */
98612   #define VPRCSR_NORDIC_TASKS_TASKS1_Disabled (0x0UL) /*!< TASKS[1] diabled                                                    */
98613   #define VPRCSR_NORDIC_TASKS_TASKS1_Enabled (0x1UL) /*!< TASKS[1] enabled                                                     */
98614 
98615 /* TASKS2 @Bit 2 : (unspecified) */
98616   #define VPRCSR_NORDIC_TASKS_TASKS2_Pos (2UL)       /*!< Position of TASKS2 field.                                            */
98617   #define VPRCSR_NORDIC_TASKS_TASKS2_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS2_Pos) /*!< Bit mask of TASKS2 field.              */
98618   #define VPRCSR_NORDIC_TASKS_TASKS2_Min (0x0UL)     /*!< Min enumerator value of TASKS2 field.                                */
98619   #define VPRCSR_NORDIC_TASKS_TASKS2_Max (0x1UL)     /*!< Max enumerator value of TASKS2 field.                                */
98620   #define VPRCSR_NORDIC_TASKS_TASKS2_Disabled (0x0UL) /*!< TASKS[2] diabled                                                    */
98621   #define VPRCSR_NORDIC_TASKS_TASKS2_Enabled (0x1UL) /*!< TASKS[2] enabled                                                     */
98622 
98623 /* TASKS3 @Bit 3 : (unspecified) */
98624   #define VPRCSR_NORDIC_TASKS_TASKS3_Pos (3UL)       /*!< Position of TASKS3 field.                                            */
98625   #define VPRCSR_NORDIC_TASKS_TASKS3_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS3_Pos) /*!< Bit mask of TASKS3 field.              */
98626   #define VPRCSR_NORDIC_TASKS_TASKS3_Min (0x0UL)     /*!< Min enumerator value of TASKS3 field.                                */
98627   #define VPRCSR_NORDIC_TASKS_TASKS3_Max (0x1UL)     /*!< Max enumerator value of TASKS3 field.                                */
98628   #define VPRCSR_NORDIC_TASKS_TASKS3_Disabled (0x0UL) /*!< TASKS[3] diabled                                                    */
98629   #define VPRCSR_NORDIC_TASKS_TASKS3_Enabled (0x1UL) /*!< TASKS[3] enabled                                                     */
98630 
98631 /* TASKS4 @Bit 4 : (unspecified) */
98632   #define VPRCSR_NORDIC_TASKS_TASKS4_Pos (4UL)       /*!< Position of TASKS4 field.                                            */
98633   #define VPRCSR_NORDIC_TASKS_TASKS4_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS4_Pos) /*!< Bit mask of TASKS4 field.              */
98634   #define VPRCSR_NORDIC_TASKS_TASKS4_Min (0x0UL)     /*!< Min enumerator value of TASKS4 field.                                */
98635   #define VPRCSR_NORDIC_TASKS_TASKS4_Max (0x1UL)     /*!< Max enumerator value of TASKS4 field.                                */
98636   #define VPRCSR_NORDIC_TASKS_TASKS4_Disabled (0x0UL) /*!< TASKS[4] diabled                                                    */
98637   #define VPRCSR_NORDIC_TASKS_TASKS4_Enabled (0x1UL) /*!< TASKS[4] enabled                                                     */
98638 
98639 /* TASKS5 @Bit 5 : (unspecified) */
98640   #define VPRCSR_NORDIC_TASKS_TASKS5_Pos (5UL)       /*!< Position of TASKS5 field.                                            */
98641   #define VPRCSR_NORDIC_TASKS_TASKS5_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS5_Pos) /*!< Bit mask of TASKS5 field.              */
98642   #define VPRCSR_NORDIC_TASKS_TASKS5_Min (0x0UL)     /*!< Min enumerator value of TASKS5 field.                                */
98643   #define VPRCSR_NORDIC_TASKS_TASKS5_Max (0x1UL)     /*!< Max enumerator value of TASKS5 field.                                */
98644   #define VPRCSR_NORDIC_TASKS_TASKS5_Disabled (0x0UL) /*!< TASKS[5] diabled                                                    */
98645   #define VPRCSR_NORDIC_TASKS_TASKS5_Enabled (0x1UL) /*!< TASKS[5] enabled                                                     */
98646 
98647 /* TASKS6 @Bit 6 : (unspecified) */
98648   #define VPRCSR_NORDIC_TASKS_TASKS6_Pos (6UL)       /*!< Position of TASKS6 field.                                            */
98649   #define VPRCSR_NORDIC_TASKS_TASKS6_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS6_Pos) /*!< Bit mask of TASKS6 field.              */
98650   #define VPRCSR_NORDIC_TASKS_TASKS6_Min (0x0UL)     /*!< Min enumerator value of TASKS6 field.                                */
98651   #define VPRCSR_NORDIC_TASKS_TASKS6_Max (0x1UL)     /*!< Max enumerator value of TASKS6 field.                                */
98652   #define VPRCSR_NORDIC_TASKS_TASKS6_Disabled (0x0UL) /*!< TASKS[6] diabled                                                    */
98653   #define VPRCSR_NORDIC_TASKS_TASKS6_Enabled (0x1UL) /*!< TASKS[6] enabled                                                     */
98654 
98655 /* TASKS7 @Bit 7 : (unspecified) */
98656   #define VPRCSR_NORDIC_TASKS_TASKS7_Pos (7UL)       /*!< Position of TASKS7 field.                                            */
98657   #define VPRCSR_NORDIC_TASKS_TASKS7_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS7_Pos) /*!< Bit mask of TASKS7 field.              */
98658   #define VPRCSR_NORDIC_TASKS_TASKS7_Min (0x0UL)     /*!< Min enumerator value of TASKS7 field.                                */
98659   #define VPRCSR_NORDIC_TASKS_TASKS7_Max (0x1UL)     /*!< Max enumerator value of TASKS7 field.                                */
98660   #define VPRCSR_NORDIC_TASKS_TASKS7_Disabled (0x0UL) /*!< TASKS[7] diabled                                                    */
98661   #define VPRCSR_NORDIC_TASKS_TASKS7_Enabled (0x1UL) /*!< TASKS[7] enabled                                                     */
98662 
98663 /* TASKS8 @Bit 8 : (unspecified) */
98664   #define VPRCSR_NORDIC_TASKS_TASKS8_Pos (8UL)       /*!< Position of TASKS8 field.                                            */
98665   #define VPRCSR_NORDIC_TASKS_TASKS8_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS8_Pos) /*!< Bit mask of TASKS8 field.              */
98666   #define VPRCSR_NORDIC_TASKS_TASKS8_Min (0x0UL)     /*!< Min enumerator value of TASKS8 field.                                */
98667   #define VPRCSR_NORDIC_TASKS_TASKS8_Max (0x1UL)     /*!< Max enumerator value of TASKS8 field.                                */
98668   #define VPRCSR_NORDIC_TASKS_TASKS8_Disabled (0x0UL) /*!< TASKS[8] diabled                                                    */
98669   #define VPRCSR_NORDIC_TASKS_TASKS8_Enabled (0x1UL) /*!< TASKS[8] enabled                                                     */
98670 
98671 /* TASKS9 @Bit 9 : (unspecified) */
98672   #define VPRCSR_NORDIC_TASKS_TASKS9_Pos (9UL)       /*!< Position of TASKS9 field.                                            */
98673   #define VPRCSR_NORDIC_TASKS_TASKS9_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS9_Pos) /*!< Bit mask of TASKS9 field.              */
98674   #define VPRCSR_NORDIC_TASKS_TASKS9_Min (0x0UL)     /*!< Min enumerator value of TASKS9 field.                                */
98675   #define VPRCSR_NORDIC_TASKS_TASKS9_Max (0x1UL)     /*!< Max enumerator value of TASKS9 field.                                */
98676   #define VPRCSR_NORDIC_TASKS_TASKS9_Disabled (0x0UL) /*!< TASKS[9] diabled                                                    */
98677   #define VPRCSR_NORDIC_TASKS_TASKS9_Enabled (0x1UL) /*!< TASKS[9] enabled                                                     */
98678 
98679 /* TASKS10 @Bit 10 : (unspecified) */
98680   #define VPRCSR_NORDIC_TASKS_TASKS10_Pos (10UL)     /*!< Position of TASKS10 field.                                           */
98681   #define VPRCSR_NORDIC_TASKS_TASKS10_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS10_Pos) /*!< Bit mask of TASKS10 field.           */
98682   #define VPRCSR_NORDIC_TASKS_TASKS10_Min (0x0UL)    /*!< Min enumerator value of TASKS10 field.                               */
98683   #define VPRCSR_NORDIC_TASKS_TASKS10_Max (0x1UL)    /*!< Max enumerator value of TASKS10 field.                               */
98684   #define VPRCSR_NORDIC_TASKS_TASKS10_Disabled (0x0UL) /*!< TASKS[10] diabled                                                  */
98685   #define VPRCSR_NORDIC_TASKS_TASKS10_Enabled (0x1UL) /*!< TASKS[10] enabled                                                   */
98686 
98687 /* TASKS11 @Bit 11 : (unspecified) */
98688   #define VPRCSR_NORDIC_TASKS_TASKS11_Pos (11UL)     /*!< Position of TASKS11 field.                                           */
98689   #define VPRCSR_NORDIC_TASKS_TASKS11_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS11_Pos) /*!< Bit mask of TASKS11 field.           */
98690   #define VPRCSR_NORDIC_TASKS_TASKS11_Min (0x0UL)    /*!< Min enumerator value of TASKS11 field.                               */
98691   #define VPRCSR_NORDIC_TASKS_TASKS11_Max (0x1UL)    /*!< Max enumerator value of TASKS11 field.                               */
98692   #define VPRCSR_NORDIC_TASKS_TASKS11_Disabled (0x0UL) /*!< TASKS[11] diabled                                                  */
98693   #define VPRCSR_NORDIC_TASKS_TASKS11_Enabled (0x1UL) /*!< TASKS[11] enabled                                                   */
98694 
98695 /* TASKS12 @Bit 12 : (unspecified) */
98696   #define VPRCSR_NORDIC_TASKS_TASKS12_Pos (12UL)     /*!< Position of TASKS12 field.                                           */
98697   #define VPRCSR_NORDIC_TASKS_TASKS12_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS12_Pos) /*!< Bit mask of TASKS12 field.           */
98698   #define VPRCSR_NORDIC_TASKS_TASKS12_Min (0x0UL)    /*!< Min enumerator value of TASKS12 field.                               */
98699   #define VPRCSR_NORDIC_TASKS_TASKS12_Max (0x1UL)    /*!< Max enumerator value of TASKS12 field.                               */
98700   #define VPRCSR_NORDIC_TASKS_TASKS12_Disabled (0x0UL) /*!< TASKS[12] diabled                                                  */
98701   #define VPRCSR_NORDIC_TASKS_TASKS12_Enabled (0x1UL) /*!< TASKS[12] enabled                                                   */
98702 
98703 /* TASKS13 @Bit 13 : (unspecified) */
98704   #define VPRCSR_NORDIC_TASKS_TASKS13_Pos (13UL)     /*!< Position of TASKS13 field.                                           */
98705   #define VPRCSR_NORDIC_TASKS_TASKS13_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS13_Pos) /*!< Bit mask of TASKS13 field.           */
98706   #define VPRCSR_NORDIC_TASKS_TASKS13_Min (0x0UL)    /*!< Min enumerator value of TASKS13 field.                               */
98707   #define VPRCSR_NORDIC_TASKS_TASKS13_Max (0x1UL)    /*!< Max enumerator value of TASKS13 field.                               */
98708   #define VPRCSR_NORDIC_TASKS_TASKS13_Disabled (0x0UL) /*!< TASKS[13] diabled                                                  */
98709   #define VPRCSR_NORDIC_TASKS_TASKS13_Enabled (0x1UL) /*!< TASKS[13] enabled                                                   */
98710 
98711 /* TASKS14 @Bit 14 : (unspecified) */
98712   #define VPRCSR_NORDIC_TASKS_TASKS14_Pos (14UL)     /*!< Position of TASKS14 field.                                           */
98713   #define VPRCSR_NORDIC_TASKS_TASKS14_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS14_Pos) /*!< Bit mask of TASKS14 field.           */
98714   #define VPRCSR_NORDIC_TASKS_TASKS14_Min (0x0UL)    /*!< Min enumerator value of TASKS14 field.                               */
98715   #define VPRCSR_NORDIC_TASKS_TASKS14_Max (0x1UL)    /*!< Max enumerator value of TASKS14 field.                               */
98716   #define VPRCSR_NORDIC_TASKS_TASKS14_Disabled (0x0UL) /*!< TASKS[14] diabled                                                  */
98717   #define VPRCSR_NORDIC_TASKS_TASKS14_Enabled (0x1UL) /*!< TASKS[14] enabled                                                   */
98718 
98719 /* TASKS15 @Bit 15 : (unspecified) */
98720   #define VPRCSR_NORDIC_TASKS_TASKS15_Pos (15UL)     /*!< Position of TASKS15 field.                                           */
98721   #define VPRCSR_NORDIC_TASKS_TASKS15_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS15_Pos) /*!< Bit mask of TASKS15 field.           */
98722   #define VPRCSR_NORDIC_TASKS_TASKS15_Min (0x0UL)    /*!< Min enumerator value of TASKS15 field.                               */
98723   #define VPRCSR_NORDIC_TASKS_TASKS15_Max (0x1UL)    /*!< Max enumerator value of TASKS15 field.                               */
98724   #define VPRCSR_NORDIC_TASKS_TASKS15_Disabled (0x0UL) /*!< TASKS[15] diabled                                                  */
98725   #define VPRCSR_NORDIC_TASKS_TASKS15_Enabled (0x1UL) /*!< TASKS[15] enabled                                                   */
98726 
98727 /* TASKS16 @Bit 16 : (unspecified) */
98728   #define VPRCSR_NORDIC_TASKS_TASKS16_Pos (16UL)     /*!< Position of TASKS16 field.                                           */
98729   #define VPRCSR_NORDIC_TASKS_TASKS16_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS16_Pos) /*!< Bit mask of TASKS16 field.           */
98730   #define VPRCSR_NORDIC_TASKS_TASKS16_Min (0x0UL)    /*!< Min enumerator value of TASKS16 field.                               */
98731   #define VPRCSR_NORDIC_TASKS_TASKS16_Max (0x1UL)    /*!< Max enumerator value of TASKS16 field.                               */
98732   #define VPRCSR_NORDIC_TASKS_TASKS16_Disabled (0x0UL) /*!< TASKS[16] diabled                                                  */
98733   #define VPRCSR_NORDIC_TASKS_TASKS16_Enabled (0x1UL) /*!< TASKS[16] enabled                                                   */
98734 
98735 /* TASKS17 @Bit 17 : (unspecified) */
98736   #define VPRCSR_NORDIC_TASKS_TASKS17_Pos (17UL)     /*!< Position of TASKS17 field.                                           */
98737   #define VPRCSR_NORDIC_TASKS_TASKS17_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS17_Pos) /*!< Bit mask of TASKS17 field.           */
98738   #define VPRCSR_NORDIC_TASKS_TASKS17_Min (0x0UL)    /*!< Min enumerator value of TASKS17 field.                               */
98739   #define VPRCSR_NORDIC_TASKS_TASKS17_Max (0x1UL)    /*!< Max enumerator value of TASKS17 field.                               */
98740   #define VPRCSR_NORDIC_TASKS_TASKS17_Disabled (0x0UL) /*!< TASKS[17] diabled                                                  */
98741   #define VPRCSR_NORDIC_TASKS_TASKS17_Enabled (0x1UL) /*!< TASKS[17] enabled                                                   */
98742 
98743 /* TASKS18 @Bit 18 : (unspecified) */
98744   #define VPRCSR_NORDIC_TASKS_TASKS18_Pos (18UL)     /*!< Position of TASKS18 field.                                           */
98745   #define VPRCSR_NORDIC_TASKS_TASKS18_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS18_Pos) /*!< Bit mask of TASKS18 field.           */
98746   #define VPRCSR_NORDIC_TASKS_TASKS18_Min (0x0UL)    /*!< Min enumerator value of TASKS18 field.                               */
98747   #define VPRCSR_NORDIC_TASKS_TASKS18_Max (0x1UL)    /*!< Max enumerator value of TASKS18 field.                               */
98748   #define VPRCSR_NORDIC_TASKS_TASKS18_Disabled (0x0UL) /*!< TASKS[18] diabled                                                  */
98749   #define VPRCSR_NORDIC_TASKS_TASKS18_Enabled (0x1UL) /*!< TASKS[18] enabled                                                   */
98750 
98751 /* TASKS19 @Bit 19 : (unspecified) */
98752   #define VPRCSR_NORDIC_TASKS_TASKS19_Pos (19UL)     /*!< Position of TASKS19 field.                                           */
98753   #define VPRCSR_NORDIC_TASKS_TASKS19_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS19_Pos) /*!< Bit mask of TASKS19 field.           */
98754   #define VPRCSR_NORDIC_TASKS_TASKS19_Min (0x0UL)    /*!< Min enumerator value of TASKS19 field.                               */
98755   #define VPRCSR_NORDIC_TASKS_TASKS19_Max (0x1UL)    /*!< Max enumerator value of TASKS19 field.                               */
98756   #define VPRCSR_NORDIC_TASKS_TASKS19_Disabled (0x0UL) /*!< TASKS[19] diabled                                                  */
98757   #define VPRCSR_NORDIC_TASKS_TASKS19_Enabled (0x1UL) /*!< TASKS[19] enabled                                                   */
98758 
98759 /* TASKS20 @Bit 20 : (unspecified) */
98760   #define VPRCSR_NORDIC_TASKS_TASKS20_Pos (20UL)     /*!< Position of TASKS20 field.                                           */
98761   #define VPRCSR_NORDIC_TASKS_TASKS20_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS20_Pos) /*!< Bit mask of TASKS20 field.           */
98762   #define VPRCSR_NORDIC_TASKS_TASKS20_Min (0x0UL)    /*!< Min enumerator value of TASKS20 field.                               */
98763   #define VPRCSR_NORDIC_TASKS_TASKS20_Max (0x1UL)    /*!< Max enumerator value of TASKS20 field.                               */
98764   #define VPRCSR_NORDIC_TASKS_TASKS20_Disabled (0x0UL) /*!< TASKS[20] diabled                                                  */
98765   #define VPRCSR_NORDIC_TASKS_TASKS20_Enabled (0x1UL) /*!< TASKS[20] enabled                                                   */
98766 
98767 /* TASKS21 @Bit 21 : (unspecified) */
98768   #define VPRCSR_NORDIC_TASKS_TASKS21_Pos (21UL)     /*!< Position of TASKS21 field.                                           */
98769   #define VPRCSR_NORDIC_TASKS_TASKS21_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS21_Pos) /*!< Bit mask of TASKS21 field.           */
98770   #define VPRCSR_NORDIC_TASKS_TASKS21_Min (0x0UL)    /*!< Min enumerator value of TASKS21 field.                               */
98771   #define VPRCSR_NORDIC_TASKS_TASKS21_Max (0x1UL)    /*!< Max enumerator value of TASKS21 field.                               */
98772   #define VPRCSR_NORDIC_TASKS_TASKS21_Disabled (0x0UL) /*!< TASKS[21] diabled                                                  */
98773   #define VPRCSR_NORDIC_TASKS_TASKS21_Enabled (0x1UL) /*!< TASKS[21] enabled                                                   */
98774 
98775 /* TASKS22 @Bit 22 : (unspecified) */
98776   #define VPRCSR_NORDIC_TASKS_TASKS22_Pos (22UL)     /*!< Position of TASKS22 field.                                           */
98777   #define VPRCSR_NORDIC_TASKS_TASKS22_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS22_Pos) /*!< Bit mask of TASKS22 field.           */
98778   #define VPRCSR_NORDIC_TASKS_TASKS22_Min (0x0UL)    /*!< Min enumerator value of TASKS22 field.                               */
98779   #define VPRCSR_NORDIC_TASKS_TASKS22_Max (0x1UL)    /*!< Max enumerator value of TASKS22 field.                               */
98780   #define VPRCSR_NORDIC_TASKS_TASKS22_Disabled (0x0UL) /*!< TASKS[22] diabled                                                  */
98781   #define VPRCSR_NORDIC_TASKS_TASKS22_Enabled (0x1UL) /*!< TASKS[22] enabled                                                   */
98782 
98783 /* TASKS23 @Bit 23 : (unspecified) */
98784   #define VPRCSR_NORDIC_TASKS_TASKS23_Pos (23UL)     /*!< Position of TASKS23 field.                                           */
98785   #define VPRCSR_NORDIC_TASKS_TASKS23_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS23_Pos) /*!< Bit mask of TASKS23 field.           */
98786   #define VPRCSR_NORDIC_TASKS_TASKS23_Min (0x0UL)    /*!< Min enumerator value of TASKS23 field.                               */
98787   #define VPRCSR_NORDIC_TASKS_TASKS23_Max (0x1UL)    /*!< Max enumerator value of TASKS23 field.                               */
98788   #define VPRCSR_NORDIC_TASKS_TASKS23_Disabled (0x0UL) /*!< TASKS[23] diabled                                                  */
98789   #define VPRCSR_NORDIC_TASKS_TASKS23_Enabled (0x1UL) /*!< TASKS[23] enabled                                                   */
98790 
98791 /* TASKS24 @Bit 24 : (unspecified) */
98792   #define VPRCSR_NORDIC_TASKS_TASKS24_Pos (24UL)     /*!< Position of TASKS24 field.                                           */
98793   #define VPRCSR_NORDIC_TASKS_TASKS24_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS24_Pos) /*!< Bit mask of TASKS24 field.           */
98794   #define VPRCSR_NORDIC_TASKS_TASKS24_Min (0x0UL)    /*!< Min enumerator value of TASKS24 field.                               */
98795   #define VPRCSR_NORDIC_TASKS_TASKS24_Max (0x1UL)    /*!< Max enumerator value of TASKS24 field.                               */
98796   #define VPRCSR_NORDIC_TASKS_TASKS24_Disabled (0x0UL) /*!< TASKS[24] diabled                                                  */
98797   #define VPRCSR_NORDIC_TASKS_TASKS24_Enabled (0x1UL) /*!< TASKS[24] enabled                                                   */
98798 
98799 /* TASKS25 @Bit 25 : (unspecified) */
98800   #define VPRCSR_NORDIC_TASKS_TASKS25_Pos (25UL)     /*!< Position of TASKS25 field.                                           */
98801   #define VPRCSR_NORDIC_TASKS_TASKS25_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS25_Pos) /*!< Bit mask of TASKS25 field.           */
98802   #define VPRCSR_NORDIC_TASKS_TASKS25_Min (0x0UL)    /*!< Min enumerator value of TASKS25 field.                               */
98803   #define VPRCSR_NORDIC_TASKS_TASKS25_Max (0x1UL)    /*!< Max enumerator value of TASKS25 field.                               */
98804   #define VPRCSR_NORDIC_TASKS_TASKS25_Disabled (0x0UL) /*!< TASKS[25] diabled                                                  */
98805   #define VPRCSR_NORDIC_TASKS_TASKS25_Enabled (0x1UL) /*!< TASKS[25] enabled                                                   */
98806 
98807 /* TASKS26 @Bit 26 : (unspecified) */
98808   #define VPRCSR_NORDIC_TASKS_TASKS26_Pos (26UL)     /*!< Position of TASKS26 field.                                           */
98809   #define VPRCSR_NORDIC_TASKS_TASKS26_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS26_Pos) /*!< Bit mask of TASKS26 field.           */
98810   #define VPRCSR_NORDIC_TASKS_TASKS26_Min (0x0UL)    /*!< Min enumerator value of TASKS26 field.                               */
98811   #define VPRCSR_NORDIC_TASKS_TASKS26_Max (0x1UL)    /*!< Max enumerator value of TASKS26 field.                               */
98812   #define VPRCSR_NORDIC_TASKS_TASKS26_Disabled (0x0UL) /*!< TASKS[26] diabled                                                  */
98813   #define VPRCSR_NORDIC_TASKS_TASKS26_Enabled (0x1UL) /*!< TASKS[26] enabled                                                   */
98814 
98815 /* TASKS27 @Bit 27 : (unspecified) */
98816   #define VPRCSR_NORDIC_TASKS_TASKS27_Pos (27UL)     /*!< Position of TASKS27 field.                                           */
98817   #define VPRCSR_NORDIC_TASKS_TASKS27_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS27_Pos) /*!< Bit mask of TASKS27 field.           */
98818   #define VPRCSR_NORDIC_TASKS_TASKS27_Min (0x0UL)    /*!< Min enumerator value of TASKS27 field.                               */
98819   #define VPRCSR_NORDIC_TASKS_TASKS27_Max (0x1UL)    /*!< Max enumerator value of TASKS27 field.                               */
98820   #define VPRCSR_NORDIC_TASKS_TASKS27_Disabled (0x0UL) /*!< TASKS[27] diabled                                                  */
98821   #define VPRCSR_NORDIC_TASKS_TASKS27_Enabled (0x1UL) /*!< TASKS[27] enabled                                                   */
98822 
98823 /* TASKS28 @Bit 28 : (unspecified) */
98824   #define VPRCSR_NORDIC_TASKS_TASKS28_Pos (28UL)     /*!< Position of TASKS28 field.                                           */
98825   #define VPRCSR_NORDIC_TASKS_TASKS28_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS28_Pos) /*!< Bit mask of TASKS28 field.           */
98826   #define VPRCSR_NORDIC_TASKS_TASKS28_Min (0x0UL)    /*!< Min enumerator value of TASKS28 field.                               */
98827   #define VPRCSR_NORDIC_TASKS_TASKS28_Max (0x1UL)    /*!< Max enumerator value of TASKS28 field.                               */
98828   #define VPRCSR_NORDIC_TASKS_TASKS28_Disabled (0x0UL) /*!< TASKS[28] diabled                                                  */
98829   #define VPRCSR_NORDIC_TASKS_TASKS28_Enabled (0x1UL) /*!< TASKS[28] enabled                                                   */
98830 
98831 /* TASKS29 @Bit 29 : (unspecified) */
98832   #define VPRCSR_NORDIC_TASKS_TASKS29_Pos (29UL)     /*!< Position of TASKS29 field.                                           */
98833   #define VPRCSR_NORDIC_TASKS_TASKS29_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS29_Pos) /*!< Bit mask of TASKS29 field.           */
98834   #define VPRCSR_NORDIC_TASKS_TASKS29_Min (0x0UL)    /*!< Min enumerator value of TASKS29 field.                               */
98835   #define VPRCSR_NORDIC_TASKS_TASKS29_Max (0x1UL)    /*!< Max enumerator value of TASKS29 field.                               */
98836   #define VPRCSR_NORDIC_TASKS_TASKS29_Disabled (0x0UL) /*!< TASKS[29] diabled                                                  */
98837   #define VPRCSR_NORDIC_TASKS_TASKS29_Enabled (0x1UL) /*!< TASKS[29] enabled                                                   */
98838 
98839 /* TASKS30 @Bit 30 : (unspecified) */
98840   #define VPRCSR_NORDIC_TASKS_TASKS30_Pos (30UL)     /*!< Position of TASKS30 field.                                           */
98841   #define VPRCSR_NORDIC_TASKS_TASKS30_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS30_Pos) /*!< Bit mask of TASKS30 field.           */
98842   #define VPRCSR_NORDIC_TASKS_TASKS30_Min (0x0UL)    /*!< Min enumerator value of TASKS30 field.                               */
98843   #define VPRCSR_NORDIC_TASKS_TASKS30_Max (0x1UL)    /*!< Max enumerator value of TASKS30 field.                               */
98844   #define VPRCSR_NORDIC_TASKS_TASKS30_Disabled (0x0UL) /*!< TASKS[30] diabled                                                  */
98845   #define VPRCSR_NORDIC_TASKS_TASKS30_Enabled (0x1UL) /*!< TASKS[30] enabled                                                   */
98846 
98847 /* TASKS31 @Bit 31 : (unspecified) */
98848   #define VPRCSR_NORDIC_TASKS_TASKS31_Pos (31UL)     /*!< Position of TASKS31 field.                                           */
98849   #define VPRCSR_NORDIC_TASKS_TASKS31_Msk (0x1UL << VPRCSR_NORDIC_TASKS_TASKS31_Pos) /*!< Bit mask of TASKS31 field.           */
98850   #define VPRCSR_NORDIC_TASKS_TASKS31_Min (0x0UL)    /*!< Min enumerator value of TASKS31 field.                               */
98851   #define VPRCSR_NORDIC_TASKS_TASKS31_Max (0x1UL)    /*!< Max enumerator value of TASKS31 field.                               */
98852   #define VPRCSR_NORDIC_TASKS_TASKS31_Disabled (0x0UL) /*!< TASKS[31] diabled                                                  */
98853   #define VPRCSR_NORDIC_TASKS_TASKS31_Enabled (0x1UL) /*!< TASKS[31] enabled                                                   */
98854 
98855 
98856 /**
98857   * @brief SUBSCRIBE [VPRCSR_NORDIC_SUBSCRIBE] Enable Task Subscription
98858   */
98859   #define VPRCSR_NORDIC_SUBSCRIBE (0x000007E1ul)
98860   #define VPRCSR_NORDIC_SUBSCRIBE_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE register.                            */
98861 
98862 /* SUBSCRIBE0 @Bit 0 : (unspecified) */
98863   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Pos (0UL) /*!< Position of SUBSCRIBE0 field.                                      */
98864   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Pos) /*!< Bit mask of SUBSCRIBE0
98865                                                                             field.*/
98866   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE0 field.                        */
98867   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE0 field.                        */
98868   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Disabled (0x0UL) /*!< Subscribe disabled for TASK[0]                              */
98869   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE0_Enabled (0x1UL) /*!< Subscribe enabled for TASK[0]                                */
98870 
98871 /* SUBSCRIBE1 @Bit 1 : (unspecified) */
98872   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Pos (1UL) /*!< Position of SUBSCRIBE1 field.                                      */
98873   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Pos) /*!< Bit mask of SUBSCRIBE1
98874                                                                             field.*/
98875   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE1 field.                        */
98876   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE1 field.                        */
98877   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Disabled (0x0UL) /*!< Subscribe disabled for TASK[1]                              */
98878   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE1_Enabled (0x1UL) /*!< Subscribe enabled for TASK[1]                                */
98879 
98880 /* SUBSCRIBE2 @Bit 2 : (unspecified) */
98881   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Pos (2UL) /*!< Position of SUBSCRIBE2 field.                                      */
98882   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Pos) /*!< Bit mask of SUBSCRIBE2
98883                                                                             field.*/
98884   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE2 field.                        */
98885   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE2 field.                        */
98886   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Disabled (0x0UL) /*!< Subscribe disabled for TASK[2]                              */
98887   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE2_Enabled (0x1UL) /*!< Subscribe enabled for TASK[2]                                */
98888 
98889 /* SUBSCRIBE3 @Bit 3 : (unspecified) */
98890   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Pos (3UL) /*!< Position of SUBSCRIBE3 field.                                      */
98891   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Pos) /*!< Bit mask of SUBSCRIBE3
98892                                                                             field.*/
98893   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE3 field.                        */
98894   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE3 field.                        */
98895   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Disabled (0x0UL) /*!< Subscribe disabled for TASK[3]                              */
98896   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE3_Enabled (0x1UL) /*!< Subscribe enabled for TASK[3]                                */
98897 
98898 /* SUBSCRIBE4 @Bit 4 : (unspecified) */
98899   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Pos (4UL) /*!< Position of SUBSCRIBE4 field.                                      */
98900   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Pos) /*!< Bit mask of SUBSCRIBE4
98901                                                                             field.*/
98902   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE4 field.                        */
98903   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE4 field.                        */
98904   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Disabled (0x0UL) /*!< Subscribe disabled for TASK[4]                              */
98905   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE4_Enabled (0x1UL) /*!< Subscribe enabled for TASK[4]                                */
98906 
98907 /* SUBSCRIBE5 @Bit 5 : (unspecified) */
98908   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Pos (5UL) /*!< Position of SUBSCRIBE5 field.                                      */
98909   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Pos) /*!< Bit mask of SUBSCRIBE5
98910                                                                             field.*/
98911   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE5 field.                        */
98912   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE5 field.                        */
98913   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Disabled (0x0UL) /*!< Subscribe disabled for TASK[5]                              */
98914   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE5_Enabled (0x1UL) /*!< Subscribe enabled for TASK[5]                                */
98915 
98916 /* SUBSCRIBE6 @Bit 6 : (unspecified) */
98917   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Pos (6UL) /*!< Position of SUBSCRIBE6 field.                                      */
98918   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Pos) /*!< Bit mask of SUBSCRIBE6
98919                                                                             field.*/
98920   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE6 field.                        */
98921   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE6 field.                        */
98922   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Disabled (0x0UL) /*!< Subscribe disabled for TASK[6]                              */
98923   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE6_Enabled (0x1UL) /*!< Subscribe enabled for TASK[6]                                */
98924 
98925 /* SUBSCRIBE7 @Bit 7 : (unspecified) */
98926   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Pos (7UL) /*!< Position of SUBSCRIBE7 field.                                      */
98927   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Pos) /*!< Bit mask of SUBSCRIBE7
98928                                                                             field.*/
98929   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE7 field.                        */
98930   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE7 field.                        */
98931   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Disabled (0x0UL) /*!< Subscribe disabled for TASK[7]                              */
98932   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE7_Enabled (0x1UL) /*!< Subscribe enabled for TASK[7]                                */
98933 
98934 /* SUBSCRIBE8 @Bit 8 : (unspecified) */
98935   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Pos (8UL) /*!< Position of SUBSCRIBE8 field.                                      */
98936   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Pos) /*!< Bit mask of SUBSCRIBE8
98937                                                                             field.*/
98938   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE8 field.                        */
98939   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE8 field.                        */
98940   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Disabled (0x0UL) /*!< Subscribe disabled for TASK[8]                              */
98941   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE8_Enabled (0x1UL) /*!< Subscribe enabled for TASK[8]                                */
98942 
98943 /* SUBSCRIBE9 @Bit 9 : (unspecified) */
98944   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Pos (9UL) /*!< Position of SUBSCRIBE9 field.                                      */
98945   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Pos) /*!< Bit mask of SUBSCRIBE9
98946                                                                             field.*/
98947   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE9 field.                        */
98948   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE9 field.                        */
98949   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Disabled (0x0UL) /*!< Subscribe disabled for TASK[9]                              */
98950   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE9_Enabled (0x1UL) /*!< Subscribe enabled for TASK[9]                                */
98951 
98952 /* SUBSCRIBE10 @Bit 10 : (unspecified) */
98953   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Pos (10UL) /*!< Position of SUBSCRIBE10 field.                                   */
98954   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Pos) /*!< Bit mask of
98955                                                                             SUBSCRIBE10 field.*/
98956   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE10 field.                      */
98957   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE10 field.                      */
98958   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Disabled (0x0UL) /*!< Subscribe disabled for TASK[10]                            */
98959   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE10_Enabled (0x1UL) /*!< Subscribe enabled for TASK[10]                              */
98960 
98961 /* SUBSCRIBE11 @Bit 11 : (unspecified) */
98962   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Pos (11UL) /*!< Position of SUBSCRIBE11 field.                                   */
98963   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Pos) /*!< Bit mask of
98964                                                                             SUBSCRIBE11 field.*/
98965   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE11 field.                      */
98966   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE11 field.                      */
98967   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Disabled (0x0UL) /*!< Subscribe disabled for TASK[11]                            */
98968   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE11_Enabled (0x1UL) /*!< Subscribe enabled for TASK[11]                              */
98969 
98970 /* SUBSCRIBE12 @Bit 12 : (unspecified) */
98971   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Pos (12UL) /*!< Position of SUBSCRIBE12 field.                                   */
98972   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Pos) /*!< Bit mask of
98973                                                                             SUBSCRIBE12 field.*/
98974   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE12 field.                      */
98975   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE12 field.                      */
98976   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Disabled (0x0UL) /*!< Subscribe disabled for TASK[12]                            */
98977   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE12_Enabled (0x1UL) /*!< Subscribe enabled for TASK[12]                              */
98978 
98979 /* SUBSCRIBE13 @Bit 13 : (unspecified) */
98980   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Pos (13UL) /*!< Position of SUBSCRIBE13 field.                                   */
98981   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Pos) /*!< Bit mask of
98982                                                                             SUBSCRIBE13 field.*/
98983   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE13 field.                      */
98984   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE13 field.                      */
98985   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Disabled (0x0UL) /*!< Subscribe disabled for TASK[13]                            */
98986   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE13_Enabled (0x1UL) /*!< Subscribe enabled for TASK[13]                              */
98987 
98988 /* SUBSCRIBE14 @Bit 14 : (unspecified) */
98989   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Pos (14UL) /*!< Position of SUBSCRIBE14 field.                                   */
98990   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Pos) /*!< Bit mask of
98991                                                                             SUBSCRIBE14 field.*/
98992   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE14 field.                      */
98993   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE14 field.                      */
98994   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Disabled (0x0UL) /*!< Subscribe disabled for TASK[14]                            */
98995   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE14_Enabled (0x1UL) /*!< Subscribe enabled for TASK[14]                              */
98996 
98997 /* SUBSCRIBE15 @Bit 15 : (unspecified) */
98998   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Pos (15UL) /*!< Position of SUBSCRIBE15 field.                                   */
98999   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Pos) /*!< Bit mask of
99000                                                                             SUBSCRIBE15 field.*/
99001   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE15 field.                      */
99002   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE15 field.                      */
99003   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Disabled (0x0UL) /*!< Subscribe disabled for TASK[15]                            */
99004   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE15_Enabled (0x1UL) /*!< Subscribe enabled for TASK[15]                              */
99005 
99006 /* SUBSCRIBE16 @Bit 16 : (unspecified) */
99007   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos (16UL) /*!< Position of SUBSCRIBE16 field.                                   */
99008   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Pos) /*!< Bit mask of
99009                                                                             SUBSCRIBE16 field.*/
99010   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE16 field.                      */
99011   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE16 field.                      */
99012   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Disabled (0x0UL) /*!< Subscribe disabled for TASK[16]                            */
99013   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE16_Enabled (0x1UL) /*!< Subscribe enabled for TASK[16]                              */
99014 
99015 /* SUBSCRIBE17 @Bit 17 : (unspecified) */
99016   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos (17UL) /*!< Position of SUBSCRIBE17 field.                                   */
99017   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Pos) /*!< Bit mask of
99018                                                                             SUBSCRIBE17 field.*/
99019   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE17 field.                      */
99020   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE17 field.                      */
99021   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Disabled (0x0UL) /*!< Subscribe disabled for TASK[17]                            */
99022   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE17_Enabled (0x1UL) /*!< Subscribe enabled for TASK[17]                              */
99023 
99024 /* SUBSCRIBE18 @Bit 18 : (unspecified) */
99025   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos (18UL) /*!< Position of SUBSCRIBE18 field.                                   */
99026   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Pos) /*!< Bit mask of
99027                                                                             SUBSCRIBE18 field.*/
99028   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE18 field.                      */
99029   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE18 field.                      */
99030   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Disabled (0x0UL) /*!< Subscribe disabled for TASK[18]                            */
99031   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE18_Enabled (0x1UL) /*!< Subscribe enabled for TASK[18]                              */
99032 
99033 /* SUBSCRIBE19 @Bit 19 : (unspecified) */
99034   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos (19UL) /*!< Position of SUBSCRIBE19 field.                                   */
99035   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Pos) /*!< Bit mask of
99036                                                                             SUBSCRIBE19 field.*/
99037   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE19 field.                      */
99038   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE19 field.                      */
99039   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Disabled (0x0UL) /*!< Subscribe disabled for TASK[19]                            */
99040   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE19_Enabled (0x1UL) /*!< Subscribe enabled for TASK[19]                              */
99041 
99042 /* SUBSCRIBE20 @Bit 20 : (unspecified) */
99043   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Pos (20UL) /*!< Position of SUBSCRIBE20 field.                                   */
99044   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Pos) /*!< Bit mask of
99045                                                                             SUBSCRIBE20 field.*/
99046   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE20 field.                      */
99047   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE20 field.                      */
99048   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Disabled (0x0UL) /*!< Subscribe disabled for TASK[20]                            */
99049   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE20_Enabled (0x1UL) /*!< Subscribe enabled for TASK[20]                              */
99050 
99051 /* SUBSCRIBE21 @Bit 21 : (unspecified) */
99052   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Pos (21UL) /*!< Position of SUBSCRIBE21 field.                                   */
99053   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Pos) /*!< Bit mask of
99054                                                                             SUBSCRIBE21 field.*/
99055   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE21 field.                      */
99056   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE21 field.                      */
99057   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Disabled (0x0UL) /*!< Subscribe disabled for TASK[21]                            */
99058   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE21_Enabled (0x1UL) /*!< Subscribe enabled for TASK[21]                              */
99059 
99060 /* SUBSCRIBE22 @Bit 22 : (unspecified) */
99061   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Pos (22UL) /*!< Position of SUBSCRIBE22 field.                                   */
99062   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Pos) /*!< Bit mask of
99063                                                                             SUBSCRIBE22 field.*/
99064   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE22 field.                      */
99065   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE22 field.                      */
99066   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Disabled (0x0UL) /*!< Subscribe disabled for TASK[22]                            */
99067   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE22_Enabled (0x1UL) /*!< Subscribe enabled for TASK[22]                              */
99068 
99069 /* SUBSCRIBE23 @Bit 23 : (unspecified) */
99070   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Pos (23UL) /*!< Position of SUBSCRIBE23 field.                                   */
99071   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Pos) /*!< Bit mask of
99072                                                                             SUBSCRIBE23 field.*/
99073   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE23 field.                      */
99074   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE23 field.                      */
99075   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Disabled (0x0UL) /*!< Subscribe disabled for TASK[23]                            */
99076   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE23_Enabled (0x1UL) /*!< Subscribe enabled for TASK[23]                              */
99077 
99078 /* SUBSCRIBE24 @Bit 24 : (unspecified) */
99079   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Pos (24UL) /*!< Position of SUBSCRIBE24 field.                                   */
99080   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Pos) /*!< Bit mask of
99081                                                                             SUBSCRIBE24 field.*/
99082   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE24 field.                      */
99083   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE24 field.                      */
99084   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Disabled (0x0UL) /*!< Subscribe disabled for TASK[24]                            */
99085   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE24_Enabled (0x1UL) /*!< Subscribe enabled for TASK[24]                              */
99086 
99087 /* SUBSCRIBE25 @Bit 25 : (unspecified) */
99088   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Pos (25UL) /*!< Position of SUBSCRIBE25 field.                                   */
99089   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Pos) /*!< Bit mask of
99090                                                                             SUBSCRIBE25 field.*/
99091   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE25 field.                      */
99092   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE25 field.                      */
99093   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Disabled (0x0UL) /*!< Subscribe disabled for TASK[25]                            */
99094   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE25_Enabled (0x1UL) /*!< Subscribe enabled for TASK[25]                              */
99095 
99096 /* SUBSCRIBE26 @Bit 26 : (unspecified) */
99097   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Pos (26UL) /*!< Position of SUBSCRIBE26 field.                                   */
99098   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Pos) /*!< Bit mask of
99099                                                                             SUBSCRIBE26 field.*/
99100   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE26 field.                      */
99101   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE26 field.                      */
99102   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Disabled (0x0UL) /*!< Subscribe disabled for TASK[26]                            */
99103   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE26_Enabled (0x1UL) /*!< Subscribe enabled for TASK[26]                              */
99104 
99105 /* SUBSCRIBE27 @Bit 27 : (unspecified) */
99106   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Pos (27UL) /*!< Position of SUBSCRIBE27 field.                                   */
99107   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Pos) /*!< Bit mask of
99108                                                                             SUBSCRIBE27 field.*/
99109   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE27 field.                      */
99110   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE27 field.                      */
99111   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Disabled (0x0UL) /*!< Subscribe disabled for TASK[27]                            */
99112   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE27_Enabled (0x1UL) /*!< Subscribe enabled for TASK[27]                              */
99113 
99114 /* SUBSCRIBE28 @Bit 28 : (unspecified) */
99115   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Pos (28UL) /*!< Position of SUBSCRIBE28 field.                                   */
99116   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Pos) /*!< Bit mask of
99117                                                                             SUBSCRIBE28 field.*/
99118   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE28 field.                      */
99119   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE28 field.                      */
99120   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Disabled (0x0UL) /*!< Subscribe disabled for TASK[28]                            */
99121   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE28_Enabled (0x1UL) /*!< Subscribe enabled for TASK[28]                              */
99122 
99123 /* SUBSCRIBE29 @Bit 29 : (unspecified) */
99124   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Pos (29UL) /*!< Position of SUBSCRIBE29 field.                                   */
99125   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Pos) /*!< Bit mask of
99126                                                                             SUBSCRIBE29 field.*/
99127   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE29 field.                      */
99128   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE29 field.                      */
99129   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Disabled (0x0UL) /*!< Subscribe disabled for TASK[29]                            */
99130   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE29_Enabled (0x1UL) /*!< Subscribe enabled for TASK[29]                              */
99131 
99132 /* SUBSCRIBE30 @Bit 30 : (unspecified) */
99133   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Pos (30UL) /*!< Position of SUBSCRIBE30 field.                                   */
99134   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Pos) /*!< Bit mask of
99135                                                                             SUBSCRIBE30 field.*/
99136   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE30 field.                      */
99137   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE30 field.                      */
99138   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Disabled (0x0UL) /*!< Subscribe disabled for TASK[30]                            */
99139   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE30_Enabled (0x1UL) /*!< Subscribe enabled for TASK[30]                              */
99140 
99141 /* SUBSCRIBE31 @Bit 31 : (unspecified) */
99142   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Pos (31UL) /*!< Position of SUBSCRIBE31 field.                                   */
99143   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Msk (0x1UL << VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Pos) /*!< Bit mask of
99144                                                                             SUBSCRIBE31 field.*/
99145   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Min (0x0UL) /*!< Min enumerator value of SUBSCRIBE31 field.                      */
99146   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Max (0x1UL) /*!< Max enumerator value of SUBSCRIBE31 field.                      */
99147   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Disabled (0x0UL) /*!< Subscribe disabled for TASK[31]                            */
99148   #define VPRCSR_NORDIC_SUBSCRIBE_SUBSCRIBE31_Enabled (0x1UL) /*!< Subscribe enabled for TASK[31]                              */
99149 
99150 
99151 /**
99152   * @brief EVENTS [VPRCSR_NORDIC_EVENTS] DPPI Events
99153   */
99154   #define VPRCSR_NORDIC_EVENTS (0x000007E2ul)
99155   #define VPRCSR_NORDIC_EVENTS_ResetValue (0x00000000UL) /*!< Reset value of EVENTS register.                                  */
99156 
99157 /* EVENTS0 @Bit 0 : (unspecified) */
99158   #define VPRCSR_NORDIC_EVENTS_EVENTS0_Pos (0UL)     /*!< Position of EVENTS0 field.                                           */
99159   #define VPRCSR_NORDIC_EVENTS_EVENTS0_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS0_Pos) /*!< Bit mask of EVENTS0 field.         */
99160   #define VPRCSR_NORDIC_EVENTS_EVENTS0_Min (0x0UL)   /*!< Min enumerator value of EVENTS0 field.                               */
99161   #define VPRCSR_NORDIC_EVENTS_EVENTS0_Max (0x1UL)   /*!< Max enumerator value of EVENTS0 field.                               */
99162   #define VPRCSR_NORDIC_EVENTS_EVENTS0_Disabled (0x0UL) /*!< EVENTS[0] disabled                                                */
99163   #define VPRCSR_NORDIC_EVENTS_EVENTS0_Enabled (0x1UL) /*!< EVENTS[0] enabled                                                  */
99164 
99165 /* EVENTS1 @Bit 1 : (unspecified) */
99166   #define VPRCSR_NORDIC_EVENTS_EVENTS1_Pos (1UL)     /*!< Position of EVENTS1 field.                                           */
99167   #define VPRCSR_NORDIC_EVENTS_EVENTS1_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS1_Pos) /*!< Bit mask of EVENTS1 field.         */
99168   #define VPRCSR_NORDIC_EVENTS_EVENTS1_Min (0x0UL)   /*!< Min enumerator value of EVENTS1 field.                               */
99169   #define VPRCSR_NORDIC_EVENTS_EVENTS1_Max (0x1UL)   /*!< Max enumerator value of EVENTS1 field.                               */
99170   #define VPRCSR_NORDIC_EVENTS_EVENTS1_Disabled (0x0UL) /*!< EVENTS[1] disabled                                                */
99171   #define VPRCSR_NORDIC_EVENTS_EVENTS1_Enabled (0x1UL) /*!< EVENTS[1] enabled                                                  */
99172 
99173 /* EVENTS2 @Bit 2 : (unspecified) */
99174   #define VPRCSR_NORDIC_EVENTS_EVENTS2_Pos (2UL)     /*!< Position of EVENTS2 field.                                           */
99175   #define VPRCSR_NORDIC_EVENTS_EVENTS2_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS2_Pos) /*!< Bit mask of EVENTS2 field.         */
99176   #define VPRCSR_NORDIC_EVENTS_EVENTS2_Min (0x0UL)   /*!< Min enumerator value of EVENTS2 field.                               */
99177   #define VPRCSR_NORDIC_EVENTS_EVENTS2_Max (0x1UL)   /*!< Max enumerator value of EVENTS2 field.                               */
99178   #define VPRCSR_NORDIC_EVENTS_EVENTS2_Disabled (0x0UL) /*!< EVENTS[2] disabled                                                */
99179   #define VPRCSR_NORDIC_EVENTS_EVENTS2_Enabled (0x1UL) /*!< EVENTS[2] enabled                                                  */
99180 
99181 /* EVENTS3 @Bit 3 : (unspecified) */
99182   #define VPRCSR_NORDIC_EVENTS_EVENTS3_Pos (3UL)     /*!< Position of EVENTS3 field.                                           */
99183   #define VPRCSR_NORDIC_EVENTS_EVENTS3_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS3_Pos) /*!< Bit mask of EVENTS3 field.         */
99184   #define VPRCSR_NORDIC_EVENTS_EVENTS3_Min (0x0UL)   /*!< Min enumerator value of EVENTS3 field.                               */
99185   #define VPRCSR_NORDIC_EVENTS_EVENTS3_Max (0x1UL)   /*!< Max enumerator value of EVENTS3 field.                               */
99186   #define VPRCSR_NORDIC_EVENTS_EVENTS3_Disabled (0x0UL) /*!< EVENTS[3] disabled                                                */
99187   #define VPRCSR_NORDIC_EVENTS_EVENTS3_Enabled (0x1UL) /*!< EVENTS[3] enabled                                                  */
99188 
99189 /* EVENTS4 @Bit 4 : (unspecified) */
99190   #define VPRCSR_NORDIC_EVENTS_EVENTS4_Pos (4UL)     /*!< Position of EVENTS4 field.                                           */
99191   #define VPRCSR_NORDIC_EVENTS_EVENTS4_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS4_Pos) /*!< Bit mask of EVENTS4 field.         */
99192   #define VPRCSR_NORDIC_EVENTS_EVENTS4_Min (0x0UL)   /*!< Min enumerator value of EVENTS4 field.                               */
99193   #define VPRCSR_NORDIC_EVENTS_EVENTS4_Max (0x1UL)   /*!< Max enumerator value of EVENTS4 field.                               */
99194   #define VPRCSR_NORDIC_EVENTS_EVENTS4_Disabled (0x0UL) /*!< EVENTS[4] disabled                                                */
99195   #define VPRCSR_NORDIC_EVENTS_EVENTS4_Enabled (0x1UL) /*!< EVENTS[4] enabled                                                  */
99196 
99197 /* EVENTS5 @Bit 5 : (unspecified) */
99198   #define VPRCSR_NORDIC_EVENTS_EVENTS5_Pos (5UL)     /*!< Position of EVENTS5 field.                                           */
99199   #define VPRCSR_NORDIC_EVENTS_EVENTS5_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS5_Pos) /*!< Bit mask of EVENTS5 field.         */
99200   #define VPRCSR_NORDIC_EVENTS_EVENTS5_Min (0x0UL)   /*!< Min enumerator value of EVENTS5 field.                               */
99201   #define VPRCSR_NORDIC_EVENTS_EVENTS5_Max (0x1UL)   /*!< Max enumerator value of EVENTS5 field.                               */
99202   #define VPRCSR_NORDIC_EVENTS_EVENTS5_Disabled (0x0UL) /*!< EVENTS[5] disabled                                                */
99203   #define VPRCSR_NORDIC_EVENTS_EVENTS5_Enabled (0x1UL) /*!< EVENTS[5] enabled                                                  */
99204 
99205 /* EVENTS6 @Bit 6 : (unspecified) */
99206   #define VPRCSR_NORDIC_EVENTS_EVENTS6_Pos (6UL)     /*!< Position of EVENTS6 field.                                           */
99207   #define VPRCSR_NORDIC_EVENTS_EVENTS6_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS6_Pos) /*!< Bit mask of EVENTS6 field.         */
99208   #define VPRCSR_NORDIC_EVENTS_EVENTS6_Min (0x0UL)   /*!< Min enumerator value of EVENTS6 field.                               */
99209   #define VPRCSR_NORDIC_EVENTS_EVENTS6_Max (0x1UL)   /*!< Max enumerator value of EVENTS6 field.                               */
99210   #define VPRCSR_NORDIC_EVENTS_EVENTS6_Disabled (0x0UL) /*!< EVENTS[6] disabled                                                */
99211   #define VPRCSR_NORDIC_EVENTS_EVENTS6_Enabled (0x1UL) /*!< EVENTS[6] enabled                                                  */
99212 
99213 /* EVENTS7 @Bit 7 : (unspecified) */
99214   #define VPRCSR_NORDIC_EVENTS_EVENTS7_Pos (7UL)     /*!< Position of EVENTS7 field.                                           */
99215   #define VPRCSR_NORDIC_EVENTS_EVENTS7_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS7_Pos) /*!< Bit mask of EVENTS7 field.         */
99216   #define VPRCSR_NORDIC_EVENTS_EVENTS7_Min (0x0UL)   /*!< Min enumerator value of EVENTS7 field.                               */
99217   #define VPRCSR_NORDIC_EVENTS_EVENTS7_Max (0x1UL)   /*!< Max enumerator value of EVENTS7 field.                               */
99218   #define VPRCSR_NORDIC_EVENTS_EVENTS7_Disabled (0x0UL) /*!< EVENTS[7] disabled                                                */
99219   #define VPRCSR_NORDIC_EVENTS_EVENTS7_Enabled (0x1UL) /*!< EVENTS[7] enabled                                                  */
99220 
99221 /* EVENTS8 @Bit 8 : (unspecified) */
99222   #define VPRCSR_NORDIC_EVENTS_EVENTS8_Pos (8UL)     /*!< Position of EVENTS8 field.                                           */
99223   #define VPRCSR_NORDIC_EVENTS_EVENTS8_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS8_Pos) /*!< Bit mask of EVENTS8 field.         */
99224   #define VPRCSR_NORDIC_EVENTS_EVENTS8_Min (0x0UL)   /*!< Min enumerator value of EVENTS8 field.                               */
99225   #define VPRCSR_NORDIC_EVENTS_EVENTS8_Max (0x1UL)   /*!< Max enumerator value of EVENTS8 field.                               */
99226   #define VPRCSR_NORDIC_EVENTS_EVENTS8_Disabled (0x0UL) /*!< EVENTS[8] disabled                                                */
99227   #define VPRCSR_NORDIC_EVENTS_EVENTS8_Enabled (0x1UL) /*!< EVENTS[8] enabled                                                  */
99228 
99229 /* EVENTS9 @Bit 9 : (unspecified) */
99230   #define VPRCSR_NORDIC_EVENTS_EVENTS9_Pos (9UL)     /*!< Position of EVENTS9 field.                                           */
99231   #define VPRCSR_NORDIC_EVENTS_EVENTS9_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS9_Pos) /*!< Bit mask of EVENTS9 field.         */
99232   #define VPRCSR_NORDIC_EVENTS_EVENTS9_Min (0x0UL)   /*!< Min enumerator value of EVENTS9 field.                               */
99233   #define VPRCSR_NORDIC_EVENTS_EVENTS9_Max (0x1UL)   /*!< Max enumerator value of EVENTS9 field.                               */
99234   #define VPRCSR_NORDIC_EVENTS_EVENTS9_Disabled (0x0UL) /*!< EVENTS[9] disabled                                                */
99235   #define VPRCSR_NORDIC_EVENTS_EVENTS9_Enabled (0x1UL) /*!< EVENTS[9] enabled                                                  */
99236 
99237 /* EVENTS10 @Bit 10 : (unspecified) */
99238   #define VPRCSR_NORDIC_EVENTS_EVENTS10_Pos (10UL)   /*!< Position of EVENTS10 field.                                          */
99239   #define VPRCSR_NORDIC_EVENTS_EVENTS10_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS10_Pos) /*!< Bit mask of EVENTS10 field.      */
99240   #define VPRCSR_NORDIC_EVENTS_EVENTS10_Min (0x0UL)  /*!< Min enumerator value of EVENTS10 field.                              */
99241   #define VPRCSR_NORDIC_EVENTS_EVENTS10_Max (0x1UL)  /*!< Max enumerator value of EVENTS10 field.                              */
99242   #define VPRCSR_NORDIC_EVENTS_EVENTS10_Disabled (0x0UL) /*!< EVENTS[10] disabled                                              */
99243   #define VPRCSR_NORDIC_EVENTS_EVENTS10_Enabled (0x1UL) /*!< EVENTS[10] enabled                                                */
99244 
99245 /* EVENTS11 @Bit 11 : (unspecified) */
99246   #define VPRCSR_NORDIC_EVENTS_EVENTS11_Pos (11UL)   /*!< Position of EVENTS11 field.                                          */
99247   #define VPRCSR_NORDIC_EVENTS_EVENTS11_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS11_Pos) /*!< Bit mask of EVENTS11 field.      */
99248   #define VPRCSR_NORDIC_EVENTS_EVENTS11_Min (0x0UL)  /*!< Min enumerator value of EVENTS11 field.                              */
99249   #define VPRCSR_NORDIC_EVENTS_EVENTS11_Max (0x1UL)  /*!< Max enumerator value of EVENTS11 field.                              */
99250   #define VPRCSR_NORDIC_EVENTS_EVENTS11_Disabled (0x0UL) /*!< EVENTS[11] disabled                                              */
99251   #define VPRCSR_NORDIC_EVENTS_EVENTS11_Enabled (0x1UL) /*!< EVENTS[11] enabled                                                */
99252 
99253 /* EVENTS12 @Bit 12 : (unspecified) */
99254   #define VPRCSR_NORDIC_EVENTS_EVENTS12_Pos (12UL)   /*!< Position of EVENTS12 field.                                          */
99255   #define VPRCSR_NORDIC_EVENTS_EVENTS12_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS12_Pos) /*!< Bit mask of EVENTS12 field.      */
99256   #define VPRCSR_NORDIC_EVENTS_EVENTS12_Min (0x0UL)  /*!< Min enumerator value of EVENTS12 field.                              */
99257   #define VPRCSR_NORDIC_EVENTS_EVENTS12_Max (0x1UL)  /*!< Max enumerator value of EVENTS12 field.                              */
99258   #define VPRCSR_NORDIC_EVENTS_EVENTS12_Disabled (0x0UL) /*!< EVENTS[12] disabled                                              */
99259   #define VPRCSR_NORDIC_EVENTS_EVENTS12_Enabled (0x1UL) /*!< EVENTS[12] enabled                                                */
99260 
99261 /* EVENTS13 @Bit 13 : (unspecified) */
99262   #define VPRCSR_NORDIC_EVENTS_EVENTS13_Pos (13UL)   /*!< Position of EVENTS13 field.                                          */
99263   #define VPRCSR_NORDIC_EVENTS_EVENTS13_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS13_Pos) /*!< Bit mask of EVENTS13 field.      */
99264   #define VPRCSR_NORDIC_EVENTS_EVENTS13_Min (0x0UL)  /*!< Min enumerator value of EVENTS13 field.                              */
99265   #define VPRCSR_NORDIC_EVENTS_EVENTS13_Max (0x1UL)  /*!< Max enumerator value of EVENTS13 field.                              */
99266   #define VPRCSR_NORDIC_EVENTS_EVENTS13_Disabled (0x0UL) /*!< EVENTS[13] disabled                                              */
99267   #define VPRCSR_NORDIC_EVENTS_EVENTS13_Enabled (0x1UL) /*!< EVENTS[13] enabled                                                */
99268 
99269 /* EVENTS14 @Bit 14 : (unspecified) */
99270   #define VPRCSR_NORDIC_EVENTS_EVENTS14_Pos (14UL)   /*!< Position of EVENTS14 field.                                          */
99271   #define VPRCSR_NORDIC_EVENTS_EVENTS14_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS14_Pos) /*!< Bit mask of EVENTS14 field.      */
99272   #define VPRCSR_NORDIC_EVENTS_EVENTS14_Min (0x0UL)  /*!< Min enumerator value of EVENTS14 field.                              */
99273   #define VPRCSR_NORDIC_EVENTS_EVENTS14_Max (0x1UL)  /*!< Max enumerator value of EVENTS14 field.                              */
99274   #define VPRCSR_NORDIC_EVENTS_EVENTS14_Disabled (0x0UL) /*!< EVENTS[14] disabled                                              */
99275   #define VPRCSR_NORDIC_EVENTS_EVENTS14_Enabled (0x1UL) /*!< EVENTS[14] enabled                                                */
99276 
99277 /* EVENTS15 @Bit 15 : (unspecified) */
99278   #define VPRCSR_NORDIC_EVENTS_EVENTS15_Pos (15UL)   /*!< Position of EVENTS15 field.                                          */
99279   #define VPRCSR_NORDIC_EVENTS_EVENTS15_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS15_Pos) /*!< Bit mask of EVENTS15 field.      */
99280   #define VPRCSR_NORDIC_EVENTS_EVENTS15_Min (0x0UL)  /*!< Min enumerator value of EVENTS15 field.                              */
99281   #define VPRCSR_NORDIC_EVENTS_EVENTS15_Max (0x1UL)  /*!< Max enumerator value of EVENTS15 field.                              */
99282   #define VPRCSR_NORDIC_EVENTS_EVENTS15_Disabled (0x0UL) /*!< EVENTS[15] disabled                                              */
99283   #define VPRCSR_NORDIC_EVENTS_EVENTS15_Enabled (0x1UL) /*!< EVENTS[15] enabled                                                */
99284 
99285 /* EVENTS16 @Bit 16 : (unspecified) */
99286   #define VPRCSR_NORDIC_EVENTS_EVENTS16_Pos (16UL)   /*!< Position of EVENTS16 field.                                          */
99287   #define VPRCSR_NORDIC_EVENTS_EVENTS16_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS16_Pos) /*!< Bit mask of EVENTS16 field.      */
99288   #define VPRCSR_NORDIC_EVENTS_EVENTS16_Min (0x0UL)  /*!< Min enumerator value of EVENTS16 field.                              */
99289   #define VPRCSR_NORDIC_EVENTS_EVENTS16_Max (0x1UL)  /*!< Max enumerator value of EVENTS16 field.                              */
99290   #define VPRCSR_NORDIC_EVENTS_EVENTS16_Disabled (0x0UL) /*!< EVENTS[16] disabled                                              */
99291   #define VPRCSR_NORDIC_EVENTS_EVENTS16_Enabled (0x1UL) /*!< EVENTS[16] enabled                                                */
99292 
99293 /* EVENTS17 @Bit 17 : (unspecified) */
99294   #define VPRCSR_NORDIC_EVENTS_EVENTS17_Pos (17UL)   /*!< Position of EVENTS17 field.                                          */
99295   #define VPRCSR_NORDIC_EVENTS_EVENTS17_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS17_Pos) /*!< Bit mask of EVENTS17 field.      */
99296   #define VPRCSR_NORDIC_EVENTS_EVENTS17_Min (0x0UL)  /*!< Min enumerator value of EVENTS17 field.                              */
99297   #define VPRCSR_NORDIC_EVENTS_EVENTS17_Max (0x1UL)  /*!< Max enumerator value of EVENTS17 field.                              */
99298   #define VPRCSR_NORDIC_EVENTS_EVENTS17_Disabled (0x0UL) /*!< EVENTS[17] disabled                                              */
99299   #define VPRCSR_NORDIC_EVENTS_EVENTS17_Enabled (0x1UL) /*!< EVENTS[17] enabled                                                */
99300 
99301 /* EVENTS18 @Bit 18 : (unspecified) */
99302   #define VPRCSR_NORDIC_EVENTS_EVENTS18_Pos (18UL)   /*!< Position of EVENTS18 field.                                          */
99303   #define VPRCSR_NORDIC_EVENTS_EVENTS18_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS18_Pos) /*!< Bit mask of EVENTS18 field.      */
99304   #define VPRCSR_NORDIC_EVENTS_EVENTS18_Min (0x0UL)  /*!< Min enumerator value of EVENTS18 field.                              */
99305   #define VPRCSR_NORDIC_EVENTS_EVENTS18_Max (0x1UL)  /*!< Max enumerator value of EVENTS18 field.                              */
99306   #define VPRCSR_NORDIC_EVENTS_EVENTS18_Disabled (0x0UL) /*!< EVENTS[18] disabled                                              */
99307   #define VPRCSR_NORDIC_EVENTS_EVENTS18_Enabled (0x1UL) /*!< EVENTS[18] enabled                                                */
99308 
99309 /* EVENTS19 @Bit 19 : (unspecified) */
99310   #define VPRCSR_NORDIC_EVENTS_EVENTS19_Pos (19UL)   /*!< Position of EVENTS19 field.                                          */
99311   #define VPRCSR_NORDIC_EVENTS_EVENTS19_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS19_Pos) /*!< Bit mask of EVENTS19 field.      */
99312   #define VPRCSR_NORDIC_EVENTS_EVENTS19_Min (0x0UL)  /*!< Min enumerator value of EVENTS19 field.                              */
99313   #define VPRCSR_NORDIC_EVENTS_EVENTS19_Max (0x1UL)  /*!< Max enumerator value of EVENTS19 field.                              */
99314   #define VPRCSR_NORDIC_EVENTS_EVENTS19_Disabled (0x0UL) /*!< EVENTS[19] disabled                                              */
99315   #define VPRCSR_NORDIC_EVENTS_EVENTS19_Enabled (0x1UL) /*!< EVENTS[19] enabled                                                */
99316 
99317 /* EVENTS20 @Bit 20 : (unspecified) */
99318   #define VPRCSR_NORDIC_EVENTS_EVENTS20_Pos (20UL)   /*!< Position of EVENTS20 field.                                          */
99319   #define VPRCSR_NORDIC_EVENTS_EVENTS20_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS20_Pos) /*!< Bit mask of EVENTS20 field.      */
99320   #define VPRCSR_NORDIC_EVENTS_EVENTS20_Min (0x0UL)  /*!< Min enumerator value of EVENTS20 field.                              */
99321   #define VPRCSR_NORDIC_EVENTS_EVENTS20_Max (0x1UL)  /*!< Max enumerator value of EVENTS20 field.                              */
99322   #define VPRCSR_NORDIC_EVENTS_EVENTS20_Disabled (0x0UL) /*!< EVENTS[20] disabled                                              */
99323   #define VPRCSR_NORDIC_EVENTS_EVENTS20_Enabled (0x1UL) /*!< EVENTS[20] enabled                                                */
99324 
99325 /* EVENTS21 @Bit 21 : (unspecified) */
99326   #define VPRCSR_NORDIC_EVENTS_EVENTS21_Pos (21UL)   /*!< Position of EVENTS21 field.                                          */
99327   #define VPRCSR_NORDIC_EVENTS_EVENTS21_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS21_Pos) /*!< Bit mask of EVENTS21 field.      */
99328   #define VPRCSR_NORDIC_EVENTS_EVENTS21_Min (0x0UL)  /*!< Min enumerator value of EVENTS21 field.                              */
99329   #define VPRCSR_NORDIC_EVENTS_EVENTS21_Max (0x1UL)  /*!< Max enumerator value of EVENTS21 field.                              */
99330   #define VPRCSR_NORDIC_EVENTS_EVENTS21_Disabled (0x0UL) /*!< EVENTS[21] disabled                                              */
99331   #define VPRCSR_NORDIC_EVENTS_EVENTS21_Enabled (0x1UL) /*!< EVENTS[21] enabled                                                */
99332 
99333 /* EVENTS22 @Bit 22 : (unspecified) */
99334   #define VPRCSR_NORDIC_EVENTS_EVENTS22_Pos (22UL)   /*!< Position of EVENTS22 field.                                          */
99335   #define VPRCSR_NORDIC_EVENTS_EVENTS22_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS22_Pos) /*!< Bit mask of EVENTS22 field.      */
99336   #define VPRCSR_NORDIC_EVENTS_EVENTS22_Min (0x0UL)  /*!< Min enumerator value of EVENTS22 field.                              */
99337   #define VPRCSR_NORDIC_EVENTS_EVENTS22_Max (0x1UL)  /*!< Max enumerator value of EVENTS22 field.                              */
99338   #define VPRCSR_NORDIC_EVENTS_EVENTS22_Disabled (0x0UL) /*!< EVENTS[22] disabled                                              */
99339   #define VPRCSR_NORDIC_EVENTS_EVENTS22_Enabled (0x1UL) /*!< EVENTS[22] enabled                                                */
99340 
99341 /* EVENTS23 @Bit 23 : (unspecified) */
99342   #define VPRCSR_NORDIC_EVENTS_EVENTS23_Pos (23UL)   /*!< Position of EVENTS23 field.                                          */
99343   #define VPRCSR_NORDIC_EVENTS_EVENTS23_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS23_Pos) /*!< Bit mask of EVENTS23 field.      */
99344   #define VPRCSR_NORDIC_EVENTS_EVENTS23_Min (0x0UL)  /*!< Min enumerator value of EVENTS23 field.                              */
99345   #define VPRCSR_NORDIC_EVENTS_EVENTS23_Max (0x1UL)  /*!< Max enumerator value of EVENTS23 field.                              */
99346   #define VPRCSR_NORDIC_EVENTS_EVENTS23_Disabled (0x0UL) /*!< EVENTS[23] disabled                                              */
99347   #define VPRCSR_NORDIC_EVENTS_EVENTS23_Enabled (0x1UL) /*!< EVENTS[23] enabled                                                */
99348 
99349 /* EVENTS24 @Bit 24 : (unspecified) */
99350   #define VPRCSR_NORDIC_EVENTS_EVENTS24_Pos (24UL)   /*!< Position of EVENTS24 field.                                          */
99351   #define VPRCSR_NORDIC_EVENTS_EVENTS24_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS24_Pos) /*!< Bit mask of EVENTS24 field.      */
99352   #define VPRCSR_NORDIC_EVENTS_EVENTS24_Min (0x0UL)  /*!< Min enumerator value of EVENTS24 field.                              */
99353   #define VPRCSR_NORDIC_EVENTS_EVENTS24_Max (0x1UL)  /*!< Max enumerator value of EVENTS24 field.                              */
99354   #define VPRCSR_NORDIC_EVENTS_EVENTS24_Disabled (0x0UL) /*!< EVENTS[24] disabled                                              */
99355   #define VPRCSR_NORDIC_EVENTS_EVENTS24_Enabled (0x1UL) /*!< EVENTS[24] enabled                                                */
99356 
99357 /* EVENTS25 @Bit 25 : (unspecified) */
99358   #define VPRCSR_NORDIC_EVENTS_EVENTS25_Pos (25UL)   /*!< Position of EVENTS25 field.                                          */
99359   #define VPRCSR_NORDIC_EVENTS_EVENTS25_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS25_Pos) /*!< Bit mask of EVENTS25 field.      */
99360   #define VPRCSR_NORDIC_EVENTS_EVENTS25_Min (0x0UL)  /*!< Min enumerator value of EVENTS25 field.                              */
99361   #define VPRCSR_NORDIC_EVENTS_EVENTS25_Max (0x1UL)  /*!< Max enumerator value of EVENTS25 field.                              */
99362   #define VPRCSR_NORDIC_EVENTS_EVENTS25_Disabled (0x0UL) /*!< EVENTS[25] disabled                                              */
99363   #define VPRCSR_NORDIC_EVENTS_EVENTS25_Enabled (0x1UL) /*!< EVENTS[25] enabled                                                */
99364 
99365 /* EVENTS26 @Bit 26 : (unspecified) */
99366   #define VPRCSR_NORDIC_EVENTS_EVENTS26_Pos (26UL)   /*!< Position of EVENTS26 field.                                          */
99367   #define VPRCSR_NORDIC_EVENTS_EVENTS26_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS26_Pos) /*!< Bit mask of EVENTS26 field.      */
99368   #define VPRCSR_NORDIC_EVENTS_EVENTS26_Min (0x0UL)  /*!< Min enumerator value of EVENTS26 field.                              */
99369   #define VPRCSR_NORDIC_EVENTS_EVENTS26_Max (0x1UL)  /*!< Max enumerator value of EVENTS26 field.                              */
99370   #define VPRCSR_NORDIC_EVENTS_EVENTS26_Disabled (0x0UL) /*!< EVENTS[26] disabled                                              */
99371   #define VPRCSR_NORDIC_EVENTS_EVENTS26_Enabled (0x1UL) /*!< EVENTS[26] enabled                                                */
99372 
99373 /* EVENTS27 @Bit 27 : (unspecified) */
99374   #define VPRCSR_NORDIC_EVENTS_EVENTS27_Pos (27UL)   /*!< Position of EVENTS27 field.                                          */
99375   #define VPRCSR_NORDIC_EVENTS_EVENTS27_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS27_Pos) /*!< Bit mask of EVENTS27 field.      */
99376   #define VPRCSR_NORDIC_EVENTS_EVENTS27_Min (0x0UL)  /*!< Min enumerator value of EVENTS27 field.                              */
99377   #define VPRCSR_NORDIC_EVENTS_EVENTS27_Max (0x1UL)  /*!< Max enumerator value of EVENTS27 field.                              */
99378   #define VPRCSR_NORDIC_EVENTS_EVENTS27_Disabled (0x0UL) /*!< EVENTS[27] disabled                                              */
99379   #define VPRCSR_NORDIC_EVENTS_EVENTS27_Enabled (0x1UL) /*!< EVENTS[27] enabled                                                */
99380 
99381 /* EVENTS28 @Bit 28 : (unspecified) */
99382   #define VPRCSR_NORDIC_EVENTS_EVENTS28_Pos (28UL)   /*!< Position of EVENTS28 field.                                          */
99383   #define VPRCSR_NORDIC_EVENTS_EVENTS28_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS28_Pos) /*!< Bit mask of EVENTS28 field.      */
99384   #define VPRCSR_NORDIC_EVENTS_EVENTS28_Min (0x0UL)  /*!< Min enumerator value of EVENTS28 field.                              */
99385   #define VPRCSR_NORDIC_EVENTS_EVENTS28_Max (0x1UL)  /*!< Max enumerator value of EVENTS28 field.                              */
99386   #define VPRCSR_NORDIC_EVENTS_EVENTS28_Disabled (0x0UL) /*!< EVENTS[28] disabled                                              */
99387   #define VPRCSR_NORDIC_EVENTS_EVENTS28_Enabled (0x1UL) /*!< EVENTS[28] enabled                                                */
99388 
99389 /* EVENTS29 @Bit 29 : (unspecified) */
99390   #define VPRCSR_NORDIC_EVENTS_EVENTS29_Pos (29UL)   /*!< Position of EVENTS29 field.                                          */
99391   #define VPRCSR_NORDIC_EVENTS_EVENTS29_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS29_Pos) /*!< Bit mask of EVENTS29 field.      */
99392   #define VPRCSR_NORDIC_EVENTS_EVENTS29_Min (0x0UL)  /*!< Min enumerator value of EVENTS29 field.                              */
99393   #define VPRCSR_NORDIC_EVENTS_EVENTS29_Max (0x1UL)  /*!< Max enumerator value of EVENTS29 field.                              */
99394   #define VPRCSR_NORDIC_EVENTS_EVENTS29_Disabled (0x0UL) /*!< EVENTS[29] disabled                                              */
99395   #define VPRCSR_NORDIC_EVENTS_EVENTS29_Enabled (0x1UL) /*!< EVENTS[29] enabled                                                */
99396 
99397 /* EVENTS30 @Bit 30 : (unspecified) */
99398   #define VPRCSR_NORDIC_EVENTS_EVENTS30_Pos (30UL)   /*!< Position of EVENTS30 field.                                          */
99399   #define VPRCSR_NORDIC_EVENTS_EVENTS30_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS30_Pos) /*!< Bit mask of EVENTS30 field.      */
99400   #define VPRCSR_NORDIC_EVENTS_EVENTS30_Min (0x0UL)  /*!< Min enumerator value of EVENTS30 field.                              */
99401   #define VPRCSR_NORDIC_EVENTS_EVENTS30_Max (0x1UL)  /*!< Max enumerator value of EVENTS30 field.                              */
99402   #define VPRCSR_NORDIC_EVENTS_EVENTS30_Disabled (0x0UL) /*!< EVENTS[30] disabled                                              */
99403   #define VPRCSR_NORDIC_EVENTS_EVENTS30_Enabled (0x1UL) /*!< EVENTS[30] enabled                                                */
99404 
99405 /* EVENTS31 @Bit 31 : (unspecified) */
99406   #define VPRCSR_NORDIC_EVENTS_EVENTS31_Pos (31UL)   /*!< Position of EVENTS31 field.                                          */
99407   #define VPRCSR_NORDIC_EVENTS_EVENTS31_Msk (0x1UL << VPRCSR_NORDIC_EVENTS_EVENTS31_Pos) /*!< Bit mask of EVENTS31 field.      */
99408   #define VPRCSR_NORDIC_EVENTS_EVENTS31_Min (0x0UL)  /*!< Min enumerator value of EVENTS31 field.                              */
99409   #define VPRCSR_NORDIC_EVENTS_EVENTS31_Max (0x1UL)  /*!< Max enumerator value of EVENTS31 field.                              */
99410   #define VPRCSR_NORDIC_EVENTS_EVENTS31_Disabled (0x0UL) /*!< EVENTS[31] disabled                                              */
99411   #define VPRCSR_NORDIC_EVENTS_EVENTS31_Enabled (0x1UL) /*!< EVENTS[31] enabled                                                */
99412 
99413 
99414 /**
99415   * @brief PUBLISH [VPRCSR_NORDIC_PUBLISH] Enable Event Publication
99416   */
99417   #define VPRCSR_NORDIC_PUBLISH (0x000007E3ul)
99418   #define VPRCSR_NORDIC_PUBLISH_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH register.                                */
99419 
99420 /* PUBLISH0 @Bit 0 : (unspecified) */
99421   #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Pos (0UL)   /*!< Position of PUBLISH0 field.                                          */
99422   #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH0_Pos) /*!< Bit mask of PUBLISH0 field.    */
99423   #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Min (0x0UL) /*!< Min enumerator value of PUBLISH0 field.                              */
99424   #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Max (0x1UL) /*!< Max enumerator value of PUBLISH0 field.                              */
99425   #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Disabled (0x0UL) /*!< Publish disabled for EVENTS[0]                                  */
99426   #define VPRCSR_NORDIC_PUBLISH_PUBLISH0_Enabled (0x1UL) /*!< Publish enabled for EVENTS[0]                                    */
99427 
99428 /* PUBLISH1 @Bit 1 : (unspecified) */
99429   #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Pos (1UL)   /*!< Position of PUBLISH1 field.                                          */
99430   #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH1_Pos) /*!< Bit mask of PUBLISH1 field.    */
99431   #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Min (0x0UL) /*!< Min enumerator value of PUBLISH1 field.                              */
99432   #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Max (0x1UL) /*!< Max enumerator value of PUBLISH1 field.                              */
99433   #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Disabled (0x0UL) /*!< Publish disabled for EVENTS[1]                                  */
99434   #define VPRCSR_NORDIC_PUBLISH_PUBLISH1_Enabled (0x1UL) /*!< Publish enabled for EVENTS[1]                                    */
99435 
99436 /* PUBLISH2 @Bit 2 : (unspecified) */
99437   #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Pos (2UL)   /*!< Position of PUBLISH2 field.                                          */
99438   #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH2_Pos) /*!< Bit mask of PUBLISH2 field.    */
99439   #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Min (0x0UL) /*!< Min enumerator value of PUBLISH2 field.                              */
99440   #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Max (0x1UL) /*!< Max enumerator value of PUBLISH2 field.                              */
99441   #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Disabled (0x0UL) /*!< Publish disabled for EVENTS[2]                                  */
99442   #define VPRCSR_NORDIC_PUBLISH_PUBLISH2_Enabled (0x1UL) /*!< Publish enabled for EVENTS[2]                                    */
99443 
99444 /* PUBLISH3 @Bit 3 : (unspecified) */
99445   #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Pos (3UL)   /*!< Position of PUBLISH3 field.                                          */
99446   #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH3_Pos) /*!< Bit mask of PUBLISH3 field.    */
99447   #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Min (0x0UL) /*!< Min enumerator value of PUBLISH3 field.                              */
99448   #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Max (0x1UL) /*!< Max enumerator value of PUBLISH3 field.                              */
99449   #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Disabled (0x0UL) /*!< Publish disabled for EVENTS[3]                                  */
99450   #define VPRCSR_NORDIC_PUBLISH_PUBLISH3_Enabled (0x1UL) /*!< Publish enabled for EVENTS[3]                                    */
99451 
99452 /* PUBLISH4 @Bit 4 : (unspecified) */
99453   #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Pos (4UL)   /*!< Position of PUBLISH4 field.                                          */
99454   #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH4_Pos) /*!< Bit mask of PUBLISH4 field.    */
99455   #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Min (0x0UL) /*!< Min enumerator value of PUBLISH4 field.                              */
99456   #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Max (0x1UL) /*!< Max enumerator value of PUBLISH4 field.                              */
99457   #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Disabled (0x0UL) /*!< Publish disabled for EVENTS[4]                                  */
99458   #define VPRCSR_NORDIC_PUBLISH_PUBLISH4_Enabled (0x1UL) /*!< Publish enabled for EVENTS[4]                                    */
99459 
99460 /* PUBLISH5 @Bit 5 : (unspecified) */
99461   #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Pos (5UL)   /*!< Position of PUBLISH5 field.                                          */
99462   #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH5_Pos) /*!< Bit mask of PUBLISH5 field.    */
99463   #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Min (0x0UL) /*!< Min enumerator value of PUBLISH5 field.                              */
99464   #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Max (0x1UL) /*!< Max enumerator value of PUBLISH5 field.                              */
99465   #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Disabled (0x0UL) /*!< Publish disabled for EVENTS[5]                                  */
99466   #define VPRCSR_NORDIC_PUBLISH_PUBLISH5_Enabled (0x1UL) /*!< Publish enabled for EVENTS[5]                                    */
99467 
99468 /* PUBLISH6 @Bit 6 : (unspecified) */
99469   #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Pos (6UL)   /*!< Position of PUBLISH6 field.                                          */
99470   #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH6_Pos) /*!< Bit mask of PUBLISH6 field.    */
99471   #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Min (0x0UL) /*!< Min enumerator value of PUBLISH6 field.                              */
99472   #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Max (0x1UL) /*!< Max enumerator value of PUBLISH6 field.                              */
99473   #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Disabled (0x0UL) /*!< Publish disabled for EVENTS[6]                                  */
99474   #define VPRCSR_NORDIC_PUBLISH_PUBLISH6_Enabled (0x1UL) /*!< Publish enabled for EVENTS[6]                                    */
99475 
99476 /* PUBLISH7 @Bit 7 : (unspecified) */
99477   #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Pos (7UL)   /*!< Position of PUBLISH7 field.                                          */
99478   #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH7_Pos) /*!< Bit mask of PUBLISH7 field.    */
99479   #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Min (0x0UL) /*!< Min enumerator value of PUBLISH7 field.                              */
99480   #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Max (0x1UL) /*!< Max enumerator value of PUBLISH7 field.                              */
99481   #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Disabled (0x0UL) /*!< Publish disabled for EVENTS[7]                                  */
99482   #define VPRCSR_NORDIC_PUBLISH_PUBLISH7_Enabled (0x1UL) /*!< Publish enabled for EVENTS[7]                                    */
99483 
99484 /* PUBLISH8 @Bit 8 : (unspecified) */
99485   #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Pos (8UL)   /*!< Position of PUBLISH8 field.                                          */
99486   #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH8_Pos) /*!< Bit mask of PUBLISH8 field.    */
99487   #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Min (0x0UL) /*!< Min enumerator value of PUBLISH8 field.                              */
99488   #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Max (0x1UL) /*!< Max enumerator value of PUBLISH8 field.                              */
99489   #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Disabled (0x0UL) /*!< Publish disabled for EVENTS[8]                                  */
99490   #define VPRCSR_NORDIC_PUBLISH_PUBLISH8_Enabled (0x1UL) /*!< Publish enabled for EVENTS[8]                                    */
99491 
99492 /* PUBLISH9 @Bit 9 : (unspecified) */
99493   #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Pos (9UL)   /*!< Position of PUBLISH9 field.                                          */
99494   #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH9_Pos) /*!< Bit mask of PUBLISH9 field.    */
99495   #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Min (0x0UL) /*!< Min enumerator value of PUBLISH9 field.                              */
99496   #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Max (0x1UL) /*!< Max enumerator value of PUBLISH9 field.                              */
99497   #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Disabled (0x0UL) /*!< Publish disabled for EVENTS[9]                                  */
99498   #define VPRCSR_NORDIC_PUBLISH_PUBLISH9_Enabled (0x1UL) /*!< Publish enabled for EVENTS[9]                                    */
99499 
99500 /* PUBLISH10 @Bit 10 : (unspecified) */
99501   #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Pos (10UL) /*!< Position of PUBLISH10 field.                                         */
99502   #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH10_Pos) /*!< Bit mask of PUBLISH10 field. */
99503   #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Min (0x0UL) /*!< Min enumerator value of PUBLISH10 field.                            */
99504   #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Max (0x1UL) /*!< Max enumerator value of PUBLISH10 field.                            */
99505   #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Disabled (0x0UL) /*!< Publish disabled for EVENTS[10]                                */
99506   #define VPRCSR_NORDIC_PUBLISH_PUBLISH10_Enabled (0x1UL) /*!< Publish enabled for EVENTS[10]                                  */
99507 
99508 /* PUBLISH11 @Bit 11 : (unspecified) */
99509   #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Pos (11UL) /*!< Position of PUBLISH11 field.                                         */
99510   #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH11_Pos) /*!< Bit mask of PUBLISH11 field. */
99511   #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Min (0x0UL) /*!< Min enumerator value of PUBLISH11 field.                            */
99512   #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Max (0x1UL) /*!< Max enumerator value of PUBLISH11 field.                            */
99513   #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Disabled (0x0UL) /*!< Publish disabled for EVENTS[11]                                */
99514   #define VPRCSR_NORDIC_PUBLISH_PUBLISH11_Enabled (0x1UL) /*!< Publish enabled for EVENTS[11]                                  */
99515 
99516 /* PUBLISH12 @Bit 12 : (unspecified) */
99517   #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Pos (12UL) /*!< Position of PUBLISH12 field.                                         */
99518   #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH12_Pos) /*!< Bit mask of PUBLISH12 field. */
99519   #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Min (0x0UL) /*!< Min enumerator value of PUBLISH12 field.                            */
99520   #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Max (0x1UL) /*!< Max enumerator value of PUBLISH12 field.                            */
99521   #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Disabled (0x0UL) /*!< Publish disabled for EVENTS[12]                                */
99522   #define VPRCSR_NORDIC_PUBLISH_PUBLISH12_Enabled (0x1UL) /*!< Publish enabled for EVENTS[12]                                  */
99523 
99524 /* PUBLISH13 @Bit 13 : (unspecified) */
99525   #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Pos (13UL) /*!< Position of PUBLISH13 field.                                         */
99526   #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH13_Pos) /*!< Bit mask of PUBLISH13 field. */
99527   #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Min (0x0UL) /*!< Min enumerator value of PUBLISH13 field.                            */
99528   #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Max (0x1UL) /*!< Max enumerator value of PUBLISH13 field.                            */
99529   #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Disabled (0x0UL) /*!< Publish disabled for EVENTS[13]                                */
99530   #define VPRCSR_NORDIC_PUBLISH_PUBLISH13_Enabled (0x1UL) /*!< Publish enabled for EVENTS[13]                                  */
99531 
99532 /* PUBLISH14 @Bit 14 : (unspecified) */
99533   #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Pos (14UL) /*!< Position of PUBLISH14 field.                                         */
99534   #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH14_Pos) /*!< Bit mask of PUBLISH14 field. */
99535   #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Min (0x0UL) /*!< Min enumerator value of PUBLISH14 field.                            */
99536   #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Max (0x1UL) /*!< Max enumerator value of PUBLISH14 field.                            */
99537   #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Disabled (0x0UL) /*!< Publish disabled for EVENTS[14]                                */
99538   #define VPRCSR_NORDIC_PUBLISH_PUBLISH14_Enabled (0x1UL) /*!< Publish enabled for EVENTS[14]                                  */
99539 
99540 /* PUBLISH15 @Bit 15 : (unspecified) */
99541   #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Pos (15UL) /*!< Position of PUBLISH15 field.                                         */
99542   #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH15_Pos) /*!< Bit mask of PUBLISH15 field. */
99543   #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Min (0x0UL) /*!< Min enumerator value of PUBLISH15 field.                            */
99544   #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Max (0x1UL) /*!< Max enumerator value of PUBLISH15 field.                            */
99545   #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Disabled (0x0UL) /*!< Publish disabled for EVENTS[15]                                */
99546   #define VPRCSR_NORDIC_PUBLISH_PUBLISH15_Enabled (0x1UL) /*!< Publish enabled for EVENTS[15]                                  */
99547 
99548 /* PUBLISH16 @Bit 16 : (unspecified) */
99549   #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos (16UL) /*!< Position of PUBLISH16 field.                                         */
99550   #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH16_Pos) /*!< Bit mask of PUBLISH16 field. */
99551   #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Min (0x0UL) /*!< Min enumerator value of PUBLISH16 field.                            */
99552   #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Max (0x1UL) /*!< Max enumerator value of PUBLISH16 field.                            */
99553   #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Disabled (0x0UL) /*!< Publish disabled for EVENTS[16]                                */
99554   #define VPRCSR_NORDIC_PUBLISH_PUBLISH16_Enabled (0x1UL) /*!< Publish enabled for EVENTS[16]                                  */
99555 
99556 /* PUBLISH17 @Bit 17 : (unspecified) */
99557   #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos (17UL) /*!< Position of PUBLISH17 field.                                         */
99558   #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH17_Pos) /*!< Bit mask of PUBLISH17 field. */
99559   #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Min (0x0UL) /*!< Min enumerator value of PUBLISH17 field.                            */
99560   #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Max (0x1UL) /*!< Max enumerator value of PUBLISH17 field.                            */
99561   #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Disabled (0x0UL) /*!< Publish disabled for EVENTS[17]                                */
99562   #define VPRCSR_NORDIC_PUBLISH_PUBLISH17_Enabled (0x1UL) /*!< Publish enabled for EVENTS[17]                                  */
99563 
99564 /* PUBLISH18 @Bit 18 : (unspecified) */
99565   #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos (18UL) /*!< Position of PUBLISH18 field.                                         */
99566   #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH18_Pos) /*!< Bit mask of PUBLISH18 field. */
99567   #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Min (0x0UL) /*!< Min enumerator value of PUBLISH18 field.                            */
99568   #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Max (0x1UL) /*!< Max enumerator value of PUBLISH18 field.                            */
99569   #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Disabled (0x0UL) /*!< Publish disabled for EVENTS[18]                                */
99570   #define VPRCSR_NORDIC_PUBLISH_PUBLISH18_Enabled (0x1UL) /*!< Publish enabled for EVENTS[18]                                  */
99571 
99572 /* PUBLISH19 @Bit 19 : (unspecified) */
99573   #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos (19UL) /*!< Position of PUBLISH19 field.                                         */
99574   #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH19_Pos) /*!< Bit mask of PUBLISH19 field. */
99575   #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Min (0x0UL) /*!< Min enumerator value of PUBLISH19 field.                            */
99576   #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Max (0x1UL) /*!< Max enumerator value of PUBLISH19 field.                            */
99577   #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Disabled (0x0UL) /*!< Publish disabled for EVENTS[19]                                */
99578   #define VPRCSR_NORDIC_PUBLISH_PUBLISH19_Enabled (0x1UL) /*!< Publish enabled for EVENTS[19]                                  */
99579 
99580 /* PUBLISH20 @Bit 20 : (unspecified) */
99581   #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Pos (20UL) /*!< Position of PUBLISH20 field.                                         */
99582   #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH20_Pos) /*!< Bit mask of PUBLISH20 field. */
99583   #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Min (0x0UL) /*!< Min enumerator value of PUBLISH20 field.                            */
99584   #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Max (0x1UL) /*!< Max enumerator value of PUBLISH20 field.                            */
99585   #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Disabled (0x0UL) /*!< Publish disabled for EVENTS[20]                                */
99586   #define VPRCSR_NORDIC_PUBLISH_PUBLISH20_Enabled (0x1UL) /*!< Publish enabled for EVENTS[20]                                  */
99587 
99588 /* PUBLISH21 @Bit 21 : (unspecified) */
99589   #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Pos (21UL) /*!< Position of PUBLISH21 field.                                         */
99590   #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH21_Pos) /*!< Bit mask of PUBLISH21 field. */
99591   #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Min (0x0UL) /*!< Min enumerator value of PUBLISH21 field.                            */
99592   #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Max (0x1UL) /*!< Max enumerator value of PUBLISH21 field.                            */
99593   #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Disabled (0x0UL) /*!< Publish disabled for EVENTS[21]                                */
99594   #define VPRCSR_NORDIC_PUBLISH_PUBLISH21_Enabled (0x1UL) /*!< Publish enabled for EVENTS[21]                                  */
99595 
99596 /* PUBLISH22 @Bit 22 : (unspecified) */
99597   #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Pos (22UL) /*!< Position of PUBLISH22 field.                                         */
99598   #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH22_Pos) /*!< Bit mask of PUBLISH22 field. */
99599   #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Min (0x0UL) /*!< Min enumerator value of PUBLISH22 field.                            */
99600   #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Max (0x1UL) /*!< Max enumerator value of PUBLISH22 field.                            */
99601   #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Disabled (0x0UL) /*!< Publish disabled for EVENTS[22]                                */
99602   #define VPRCSR_NORDIC_PUBLISH_PUBLISH22_Enabled (0x1UL) /*!< Publish enabled for EVENTS[22]                                  */
99603 
99604 /* PUBLISH23 @Bit 23 : (unspecified) */
99605   #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Pos (23UL) /*!< Position of PUBLISH23 field.                                         */
99606   #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH23_Pos) /*!< Bit mask of PUBLISH23 field. */
99607   #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Min (0x0UL) /*!< Min enumerator value of PUBLISH23 field.                            */
99608   #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Max (0x1UL) /*!< Max enumerator value of PUBLISH23 field.                            */
99609   #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Disabled (0x0UL) /*!< Publish disabled for EVENTS[23]                                */
99610   #define VPRCSR_NORDIC_PUBLISH_PUBLISH23_Enabled (0x1UL) /*!< Publish enabled for EVENTS[23]                                  */
99611 
99612 /* PUBLISH24 @Bit 24 : (unspecified) */
99613   #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Pos (24UL) /*!< Position of PUBLISH24 field.                                         */
99614   #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH24_Pos) /*!< Bit mask of PUBLISH24 field. */
99615   #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Min (0x0UL) /*!< Min enumerator value of PUBLISH24 field.                            */
99616   #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Max (0x1UL) /*!< Max enumerator value of PUBLISH24 field.                            */
99617   #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Disabled (0x0UL) /*!< Publish disabled for EVENTS[24]                                */
99618   #define VPRCSR_NORDIC_PUBLISH_PUBLISH24_Enabled (0x1UL) /*!< Publish enabled for EVENTS[24]                                  */
99619 
99620 /* PUBLISH25 @Bit 25 : (unspecified) */
99621   #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Pos (25UL) /*!< Position of PUBLISH25 field.                                         */
99622   #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH25_Pos) /*!< Bit mask of PUBLISH25 field. */
99623   #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Min (0x0UL) /*!< Min enumerator value of PUBLISH25 field.                            */
99624   #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Max (0x1UL) /*!< Max enumerator value of PUBLISH25 field.                            */
99625   #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Disabled (0x0UL) /*!< Publish disabled for EVENTS[25]                                */
99626   #define VPRCSR_NORDIC_PUBLISH_PUBLISH25_Enabled (0x1UL) /*!< Publish enabled for EVENTS[25]                                  */
99627 
99628 /* PUBLISH26 @Bit 26 : (unspecified) */
99629   #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Pos (26UL) /*!< Position of PUBLISH26 field.                                         */
99630   #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH26_Pos) /*!< Bit mask of PUBLISH26 field. */
99631   #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Min (0x0UL) /*!< Min enumerator value of PUBLISH26 field.                            */
99632   #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Max (0x1UL) /*!< Max enumerator value of PUBLISH26 field.                            */
99633   #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Disabled (0x0UL) /*!< Publish disabled for EVENTS[26]                                */
99634   #define VPRCSR_NORDIC_PUBLISH_PUBLISH26_Enabled (0x1UL) /*!< Publish enabled for EVENTS[26]                                  */
99635 
99636 /* PUBLISH27 @Bit 27 : (unspecified) */
99637   #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Pos (27UL) /*!< Position of PUBLISH27 field.                                         */
99638   #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH27_Pos) /*!< Bit mask of PUBLISH27 field. */
99639   #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Min (0x0UL) /*!< Min enumerator value of PUBLISH27 field.                            */
99640   #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Max (0x1UL) /*!< Max enumerator value of PUBLISH27 field.                            */
99641   #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Disabled (0x0UL) /*!< Publish disabled for EVENTS[27]                                */
99642   #define VPRCSR_NORDIC_PUBLISH_PUBLISH27_Enabled (0x1UL) /*!< Publish enabled for EVENTS[27]                                  */
99643 
99644 /* PUBLISH28 @Bit 28 : (unspecified) */
99645   #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Pos (28UL) /*!< Position of PUBLISH28 field.                                         */
99646   #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH28_Pos) /*!< Bit mask of PUBLISH28 field. */
99647   #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Min (0x0UL) /*!< Min enumerator value of PUBLISH28 field.                            */
99648   #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Max (0x1UL) /*!< Max enumerator value of PUBLISH28 field.                            */
99649   #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Disabled (0x0UL) /*!< Publish disabled for EVENTS[28]                                */
99650   #define VPRCSR_NORDIC_PUBLISH_PUBLISH28_Enabled (0x1UL) /*!< Publish enabled for EVENTS[28]                                  */
99651 
99652 /* PUBLISH29 @Bit 29 : (unspecified) */
99653   #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Pos (29UL) /*!< Position of PUBLISH29 field.                                         */
99654   #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH29_Pos) /*!< Bit mask of PUBLISH29 field. */
99655   #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Min (0x0UL) /*!< Min enumerator value of PUBLISH29 field.                            */
99656   #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Max (0x1UL) /*!< Max enumerator value of PUBLISH29 field.                            */
99657   #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Disabled (0x0UL) /*!< Publish disabled for EVENTS[29]                                */
99658   #define VPRCSR_NORDIC_PUBLISH_PUBLISH29_Enabled (0x1UL) /*!< Publish enabled for EVENTS[29]                                  */
99659 
99660 /* PUBLISH30 @Bit 30 : (unspecified) */
99661   #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Pos (30UL) /*!< Position of PUBLISH30 field.                                         */
99662   #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH30_Pos) /*!< Bit mask of PUBLISH30 field. */
99663   #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Min (0x0UL) /*!< Min enumerator value of PUBLISH30 field.                            */
99664   #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Max (0x1UL) /*!< Max enumerator value of PUBLISH30 field.                            */
99665   #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Disabled (0x0UL) /*!< Publish disabled for EVENTS[30]                                */
99666   #define VPRCSR_NORDIC_PUBLISH_PUBLISH30_Enabled (0x1UL) /*!< Publish enabled for EVENTS[30]                                  */
99667 
99668 /* PUBLISH31 @Bit 31 : (unspecified) */
99669   #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Pos (31UL) /*!< Position of PUBLISH31 field.                                         */
99670   #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Msk (0x1UL << VPRCSR_NORDIC_PUBLISH_PUBLISH31_Pos) /*!< Bit mask of PUBLISH31 field. */
99671   #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Min (0x0UL) /*!< Min enumerator value of PUBLISH31 field.                            */
99672   #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Max (0x1UL) /*!< Max enumerator value of PUBLISH31 field.                            */
99673   #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Disabled (0x0UL) /*!< Publish disabled for EVENTS[31]                                */
99674   #define VPRCSR_NORDIC_PUBLISH_PUBLISH31_Enabled (0x1UL) /*!< Publish enabled for EVENTS[31]                                  */
99675 
99676 
99677 /**
99678   * @brief INTEN [VPRCSR_NORDIC_INTEN] DPPI Event Interrupt Enable
99679   */
99680   #define VPRCSR_NORDIC_INTEN (0x000007E4ul)
99681   #define VPRCSR_NORDIC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register.                                    */
99682 
99683 /* INTEN0 @Bit 0 : (unspecified) */
99684   #define VPRCSR_NORDIC_INTEN_INTEN0_Pos (0UL)       /*!< Position of INTEN0 field.                                            */
99685   #define VPRCSR_NORDIC_INTEN_INTEN0_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN0_Pos) /*!< Bit mask of INTEN0 field.              */
99686   #define VPRCSR_NORDIC_INTEN_INTEN0_Min (0x0UL)     /*!< Min enumerator value of INTEN0 field.                                */
99687   #define VPRCSR_NORDIC_INTEN_INTEN0_Max (0x1UL)     /*!< Max enumerator value of INTEN0 field.                                */
99688   #define VPRCSR_NORDIC_INTEN_INTEN0_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[0]                                    */
99689   #define VPRCSR_NORDIC_INTEN_INTEN0_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[0]                                      */
99690 
99691 /* INTEN1 @Bit 1 : (unspecified) */
99692   #define VPRCSR_NORDIC_INTEN_INTEN1_Pos (1UL)       /*!< Position of INTEN1 field.                                            */
99693   #define VPRCSR_NORDIC_INTEN_INTEN1_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN1_Pos) /*!< Bit mask of INTEN1 field.              */
99694   #define VPRCSR_NORDIC_INTEN_INTEN1_Min (0x0UL)     /*!< Min enumerator value of INTEN1 field.                                */
99695   #define VPRCSR_NORDIC_INTEN_INTEN1_Max (0x1UL)     /*!< Max enumerator value of INTEN1 field.                                */
99696   #define VPRCSR_NORDIC_INTEN_INTEN1_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[1]                                    */
99697   #define VPRCSR_NORDIC_INTEN_INTEN1_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[1]                                      */
99698 
99699 /* INTEN2 @Bit 2 : (unspecified) */
99700   #define VPRCSR_NORDIC_INTEN_INTEN2_Pos (2UL)       /*!< Position of INTEN2 field.                                            */
99701   #define VPRCSR_NORDIC_INTEN_INTEN2_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN2_Pos) /*!< Bit mask of INTEN2 field.              */
99702   #define VPRCSR_NORDIC_INTEN_INTEN2_Min (0x0UL)     /*!< Min enumerator value of INTEN2 field.                                */
99703   #define VPRCSR_NORDIC_INTEN_INTEN2_Max (0x1UL)     /*!< Max enumerator value of INTEN2 field.                                */
99704   #define VPRCSR_NORDIC_INTEN_INTEN2_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[2]                                    */
99705   #define VPRCSR_NORDIC_INTEN_INTEN2_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[2]                                      */
99706 
99707 /* INTEN3 @Bit 3 : (unspecified) */
99708   #define VPRCSR_NORDIC_INTEN_INTEN3_Pos (3UL)       /*!< Position of INTEN3 field.                                            */
99709   #define VPRCSR_NORDIC_INTEN_INTEN3_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN3_Pos) /*!< Bit mask of INTEN3 field.              */
99710   #define VPRCSR_NORDIC_INTEN_INTEN3_Min (0x0UL)     /*!< Min enumerator value of INTEN3 field.                                */
99711   #define VPRCSR_NORDIC_INTEN_INTEN3_Max (0x1UL)     /*!< Max enumerator value of INTEN3 field.                                */
99712   #define VPRCSR_NORDIC_INTEN_INTEN3_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[3]                                    */
99713   #define VPRCSR_NORDIC_INTEN_INTEN3_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[3]                                      */
99714 
99715 /* INTEN4 @Bit 4 : (unspecified) */
99716   #define VPRCSR_NORDIC_INTEN_INTEN4_Pos (4UL)       /*!< Position of INTEN4 field.                                            */
99717   #define VPRCSR_NORDIC_INTEN_INTEN4_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN4_Pos) /*!< Bit mask of INTEN4 field.              */
99718   #define VPRCSR_NORDIC_INTEN_INTEN4_Min (0x0UL)     /*!< Min enumerator value of INTEN4 field.                                */
99719   #define VPRCSR_NORDIC_INTEN_INTEN4_Max (0x1UL)     /*!< Max enumerator value of INTEN4 field.                                */
99720   #define VPRCSR_NORDIC_INTEN_INTEN4_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[4]                                    */
99721   #define VPRCSR_NORDIC_INTEN_INTEN4_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[4]                                      */
99722 
99723 /* INTEN5 @Bit 5 : (unspecified) */
99724   #define VPRCSR_NORDIC_INTEN_INTEN5_Pos (5UL)       /*!< Position of INTEN5 field.                                            */
99725   #define VPRCSR_NORDIC_INTEN_INTEN5_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN5_Pos) /*!< Bit mask of INTEN5 field.              */
99726   #define VPRCSR_NORDIC_INTEN_INTEN5_Min (0x0UL)     /*!< Min enumerator value of INTEN5 field.                                */
99727   #define VPRCSR_NORDIC_INTEN_INTEN5_Max (0x1UL)     /*!< Max enumerator value of INTEN5 field.                                */
99728   #define VPRCSR_NORDIC_INTEN_INTEN5_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[5]                                    */
99729   #define VPRCSR_NORDIC_INTEN_INTEN5_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[5]                                      */
99730 
99731 /* INTEN6 @Bit 6 : (unspecified) */
99732   #define VPRCSR_NORDIC_INTEN_INTEN6_Pos (6UL)       /*!< Position of INTEN6 field.                                            */
99733   #define VPRCSR_NORDIC_INTEN_INTEN6_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN6_Pos) /*!< Bit mask of INTEN6 field.              */
99734   #define VPRCSR_NORDIC_INTEN_INTEN6_Min (0x0UL)     /*!< Min enumerator value of INTEN6 field.                                */
99735   #define VPRCSR_NORDIC_INTEN_INTEN6_Max (0x1UL)     /*!< Max enumerator value of INTEN6 field.                                */
99736   #define VPRCSR_NORDIC_INTEN_INTEN6_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[6]                                    */
99737   #define VPRCSR_NORDIC_INTEN_INTEN6_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[6]                                      */
99738 
99739 /* INTEN7 @Bit 7 : (unspecified) */
99740   #define VPRCSR_NORDIC_INTEN_INTEN7_Pos (7UL)       /*!< Position of INTEN7 field.                                            */
99741   #define VPRCSR_NORDIC_INTEN_INTEN7_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN7_Pos) /*!< Bit mask of INTEN7 field.              */
99742   #define VPRCSR_NORDIC_INTEN_INTEN7_Min (0x0UL)     /*!< Min enumerator value of INTEN7 field.                                */
99743   #define VPRCSR_NORDIC_INTEN_INTEN7_Max (0x1UL)     /*!< Max enumerator value of INTEN7 field.                                */
99744   #define VPRCSR_NORDIC_INTEN_INTEN7_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[7]                                    */
99745   #define VPRCSR_NORDIC_INTEN_INTEN7_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[7]                                      */
99746 
99747 /* INTEN8 @Bit 8 : (unspecified) */
99748   #define VPRCSR_NORDIC_INTEN_INTEN8_Pos (8UL)       /*!< Position of INTEN8 field.                                            */
99749   #define VPRCSR_NORDIC_INTEN_INTEN8_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN8_Pos) /*!< Bit mask of INTEN8 field.              */
99750   #define VPRCSR_NORDIC_INTEN_INTEN8_Min (0x0UL)     /*!< Min enumerator value of INTEN8 field.                                */
99751   #define VPRCSR_NORDIC_INTEN_INTEN8_Max (0x1UL)     /*!< Max enumerator value of INTEN8 field.                                */
99752   #define VPRCSR_NORDIC_INTEN_INTEN8_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[8]                                    */
99753   #define VPRCSR_NORDIC_INTEN_INTEN8_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[8]                                      */
99754 
99755 /* INTEN9 @Bit 9 : (unspecified) */
99756   #define VPRCSR_NORDIC_INTEN_INTEN9_Pos (9UL)       /*!< Position of INTEN9 field.                                            */
99757   #define VPRCSR_NORDIC_INTEN_INTEN9_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN9_Pos) /*!< Bit mask of INTEN9 field.              */
99758   #define VPRCSR_NORDIC_INTEN_INTEN9_Min (0x0UL)     /*!< Min enumerator value of INTEN9 field.                                */
99759   #define VPRCSR_NORDIC_INTEN_INTEN9_Max (0x1UL)     /*!< Max enumerator value of INTEN9 field.                                */
99760   #define VPRCSR_NORDIC_INTEN_INTEN9_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[9]                                    */
99761   #define VPRCSR_NORDIC_INTEN_INTEN9_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[9]                                      */
99762 
99763 /* INTEN10 @Bit 10 : (unspecified) */
99764   #define VPRCSR_NORDIC_INTEN_INTEN10_Pos (10UL)     /*!< Position of INTEN10 field.                                           */
99765   #define VPRCSR_NORDIC_INTEN_INTEN10_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN10_Pos) /*!< Bit mask of INTEN10 field.           */
99766   #define VPRCSR_NORDIC_INTEN_INTEN10_Min (0x0UL)    /*!< Min enumerator value of INTEN10 field.                               */
99767   #define VPRCSR_NORDIC_INTEN_INTEN10_Max (0x1UL)    /*!< Max enumerator value of INTEN10 field.                               */
99768   #define VPRCSR_NORDIC_INTEN_INTEN10_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[10]                                  */
99769   #define VPRCSR_NORDIC_INTEN_INTEN10_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[10]                                    */
99770 
99771 /* INTEN11 @Bit 11 : (unspecified) */
99772   #define VPRCSR_NORDIC_INTEN_INTEN11_Pos (11UL)     /*!< Position of INTEN11 field.                                           */
99773   #define VPRCSR_NORDIC_INTEN_INTEN11_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN11_Pos) /*!< Bit mask of INTEN11 field.           */
99774   #define VPRCSR_NORDIC_INTEN_INTEN11_Min (0x0UL)    /*!< Min enumerator value of INTEN11 field.                               */
99775   #define VPRCSR_NORDIC_INTEN_INTEN11_Max (0x1UL)    /*!< Max enumerator value of INTEN11 field.                               */
99776   #define VPRCSR_NORDIC_INTEN_INTEN11_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[11]                                  */
99777   #define VPRCSR_NORDIC_INTEN_INTEN11_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[11]                                    */
99778 
99779 /* INTEN12 @Bit 12 : (unspecified) */
99780   #define VPRCSR_NORDIC_INTEN_INTEN12_Pos (12UL)     /*!< Position of INTEN12 field.                                           */
99781   #define VPRCSR_NORDIC_INTEN_INTEN12_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN12_Pos) /*!< Bit mask of INTEN12 field.           */
99782   #define VPRCSR_NORDIC_INTEN_INTEN12_Min (0x0UL)    /*!< Min enumerator value of INTEN12 field.                               */
99783   #define VPRCSR_NORDIC_INTEN_INTEN12_Max (0x1UL)    /*!< Max enumerator value of INTEN12 field.                               */
99784   #define VPRCSR_NORDIC_INTEN_INTEN12_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[12]                                  */
99785   #define VPRCSR_NORDIC_INTEN_INTEN12_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[12]                                    */
99786 
99787 /* INTEN13 @Bit 13 : (unspecified) */
99788   #define VPRCSR_NORDIC_INTEN_INTEN13_Pos (13UL)     /*!< Position of INTEN13 field.                                           */
99789   #define VPRCSR_NORDIC_INTEN_INTEN13_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN13_Pos) /*!< Bit mask of INTEN13 field.           */
99790   #define VPRCSR_NORDIC_INTEN_INTEN13_Min (0x0UL)    /*!< Min enumerator value of INTEN13 field.                               */
99791   #define VPRCSR_NORDIC_INTEN_INTEN13_Max (0x1UL)    /*!< Max enumerator value of INTEN13 field.                               */
99792   #define VPRCSR_NORDIC_INTEN_INTEN13_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[13]                                  */
99793   #define VPRCSR_NORDIC_INTEN_INTEN13_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[13]                                    */
99794 
99795 /* INTEN14 @Bit 14 : (unspecified) */
99796   #define VPRCSR_NORDIC_INTEN_INTEN14_Pos (14UL)     /*!< Position of INTEN14 field.                                           */
99797   #define VPRCSR_NORDIC_INTEN_INTEN14_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN14_Pos) /*!< Bit mask of INTEN14 field.           */
99798   #define VPRCSR_NORDIC_INTEN_INTEN14_Min (0x0UL)    /*!< Min enumerator value of INTEN14 field.                               */
99799   #define VPRCSR_NORDIC_INTEN_INTEN14_Max (0x1UL)    /*!< Max enumerator value of INTEN14 field.                               */
99800   #define VPRCSR_NORDIC_INTEN_INTEN14_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[14]                                  */
99801   #define VPRCSR_NORDIC_INTEN_INTEN14_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[14]                                    */
99802 
99803 /* INTEN15 @Bit 15 : (unspecified) */
99804   #define VPRCSR_NORDIC_INTEN_INTEN15_Pos (15UL)     /*!< Position of INTEN15 field.                                           */
99805   #define VPRCSR_NORDIC_INTEN_INTEN15_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN15_Pos) /*!< Bit mask of INTEN15 field.           */
99806   #define VPRCSR_NORDIC_INTEN_INTEN15_Min (0x0UL)    /*!< Min enumerator value of INTEN15 field.                               */
99807   #define VPRCSR_NORDIC_INTEN_INTEN15_Max (0x1UL)    /*!< Max enumerator value of INTEN15 field.                               */
99808   #define VPRCSR_NORDIC_INTEN_INTEN15_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[15]                                  */
99809   #define VPRCSR_NORDIC_INTEN_INTEN15_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[15]                                    */
99810 
99811 /* INTEN16 @Bit 16 : (unspecified) */
99812   #define VPRCSR_NORDIC_INTEN_INTEN16_Pos (16UL)     /*!< Position of INTEN16 field.                                           */
99813   #define VPRCSR_NORDIC_INTEN_INTEN16_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN16_Pos) /*!< Bit mask of INTEN16 field.           */
99814   #define VPRCSR_NORDIC_INTEN_INTEN16_Min (0x0UL)    /*!< Min enumerator value of INTEN16 field.                               */
99815   #define VPRCSR_NORDIC_INTEN_INTEN16_Max (0x1UL)    /*!< Max enumerator value of INTEN16 field.                               */
99816   #define VPRCSR_NORDIC_INTEN_INTEN16_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[16]                                  */
99817   #define VPRCSR_NORDIC_INTEN_INTEN16_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[16]                                    */
99818 
99819 /* INTEN17 @Bit 17 : (unspecified) */
99820   #define VPRCSR_NORDIC_INTEN_INTEN17_Pos (17UL)     /*!< Position of INTEN17 field.                                           */
99821   #define VPRCSR_NORDIC_INTEN_INTEN17_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN17_Pos) /*!< Bit mask of INTEN17 field.           */
99822   #define VPRCSR_NORDIC_INTEN_INTEN17_Min (0x0UL)    /*!< Min enumerator value of INTEN17 field.                               */
99823   #define VPRCSR_NORDIC_INTEN_INTEN17_Max (0x1UL)    /*!< Max enumerator value of INTEN17 field.                               */
99824   #define VPRCSR_NORDIC_INTEN_INTEN17_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[17]                                  */
99825   #define VPRCSR_NORDIC_INTEN_INTEN17_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[17]                                    */
99826 
99827 /* INTEN18 @Bit 18 : (unspecified) */
99828   #define VPRCSR_NORDIC_INTEN_INTEN18_Pos (18UL)     /*!< Position of INTEN18 field.                                           */
99829   #define VPRCSR_NORDIC_INTEN_INTEN18_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN18_Pos) /*!< Bit mask of INTEN18 field.           */
99830   #define VPRCSR_NORDIC_INTEN_INTEN18_Min (0x0UL)    /*!< Min enumerator value of INTEN18 field.                               */
99831   #define VPRCSR_NORDIC_INTEN_INTEN18_Max (0x1UL)    /*!< Max enumerator value of INTEN18 field.                               */
99832   #define VPRCSR_NORDIC_INTEN_INTEN18_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[18]                                  */
99833   #define VPRCSR_NORDIC_INTEN_INTEN18_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[18]                                    */
99834 
99835 /* INTEN19 @Bit 19 : (unspecified) */
99836   #define VPRCSR_NORDIC_INTEN_INTEN19_Pos (19UL)     /*!< Position of INTEN19 field.                                           */
99837   #define VPRCSR_NORDIC_INTEN_INTEN19_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN19_Pos) /*!< Bit mask of INTEN19 field.           */
99838   #define VPRCSR_NORDIC_INTEN_INTEN19_Min (0x0UL)    /*!< Min enumerator value of INTEN19 field.                               */
99839   #define VPRCSR_NORDIC_INTEN_INTEN19_Max (0x1UL)    /*!< Max enumerator value of INTEN19 field.                               */
99840   #define VPRCSR_NORDIC_INTEN_INTEN19_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[19]                                  */
99841   #define VPRCSR_NORDIC_INTEN_INTEN19_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[19]                                    */
99842 
99843 /* INTEN20 @Bit 20 : (unspecified) */
99844   #define VPRCSR_NORDIC_INTEN_INTEN20_Pos (20UL)     /*!< Position of INTEN20 field.                                           */
99845   #define VPRCSR_NORDIC_INTEN_INTEN20_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN20_Pos) /*!< Bit mask of INTEN20 field.           */
99846   #define VPRCSR_NORDIC_INTEN_INTEN20_Min (0x0UL)    /*!< Min enumerator value of INTEN20 field.                               */
99847   #define VPRCSR_NORDIC_INTEN_INTEN20_Max (0x1UL)    /*!< Max enumerator value of INTEN20 field.                               */
99848   #define VPRCSR_NORDIC_INTEN_INTEN20_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[20]                                  */
99849   #define VPRCSR_NORDIC_INTEN_INTEN20_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[20]                                    */
99850 
99851 /* INTEN21 @Bit 21 : (unspecified) */
99852   #define VPRCSR_NORDIC_INTEN_INTEN21_Pos (21UL)     /*!< Position of INTEN21 field.                                           */
99853   #define VPRCSR_NORDIC_INTEN_INTEN21_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN21_Pos) /*!< Bit mask of INTEN21 field.           */
99854   #define VPRCSR_NORDIC_INTEN_INTEN21_Min (0x0UL)    /*!< Min enumerator value of INTEN21 field.                               */
99855   #define VPRCSR_NORDIC_INTEN_INTEN21_Max (0x1UL)    /*!< Max enumerator value of INTEN21 field.                               */
99856   #define VPRCSR_NORDIC_INTEN_INTEN21_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[21]                                  */
99857   #define VPRCSR_NORDIC_INTEN_INTEN21_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[21]                                    */
99858 
99859 /* INTEN22 @Bit 22 : (unspecified) */
99860   #define VPRCSR_NORDIC_INTEN_INTEN22_Pos (22UL)     /*!< Position of INTEN22 field.                                           */
99861   #define VPRCSR_NORDIC_INTEN_INTEN22_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN22_Pos) /*!< Bit mask of INTEN22 field.           */
99862   #define VPRCSR_NORDIC_INTEN_INTEN22_Min (0x0UL)    /*!< Min enumerator value of INTEN22 field.                               */
99863   #define VPRCSR_NORDIC_INTEN_INTEN22_Max (0x1UL)    /*!< Max enumerator value of INTEN22 field.                               */
99864   #define VPRCSR_NORDIC_INTEN_INTEN22_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[22]                                  */
99865   #define VPRCSR_NORDIC_INTEN_INTEN22_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[22]                                    */
99866 
99867 /* INTEN23 @Bit 23 : (unspecified) */
99868   #define VPRCSR_NORDIC_INTEN_INTEN23_Pos (23UL)     /*!< Position of INTEN23 field.                                           */
99869   #define VPRCSR_NORDIC_INTEN_INTEN23_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN23_Pos) /*!< Bit mask of INTEN23 field.           */
99870   #define VPRCSR_NORDIC_INTEN_INTEN23_Min (0x0UL)    /*!< Min enumerator value of INTEN23 field.                               */
99871   #define VPRCSR_NORDIC_INTEN_INTEN23_Max (0x1UL)    /*!< Max enumerator value of INTEN23 field.                               */
99872   #define VPRCSR_NORDIC_INTEN_INTEN23_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[23]                                  */
99873   #define VPRCSR_NORDIC_INTEN_INTEN23_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[23]                                    */
99874 
99875 /* INTEN24 @Bit 24 : (unspecified) */
99876   #define VPRCSR_NORDIC_INTEN_INTEN24_Pos (24UL)     /*!< Position of INTEN24 field.                                           */
99877   #define VPRCSR_NORDIC_INTEN_INTEN24_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN24_Pos) /*!< Bit mask of INTEN24 field.           */
99878   #define VPRCSR_NORDIC_INTEN_INTEN24_Min (0x0UL)    /*!< Min enumerator value of INTEN24 field.                               */
99879   #define VPRCSR_NORDIC_INTEN_INTEN24_Max (0x1UL)    /*!< Max enumerator value of INTEN24 field.                               */
99880   #define VPRCSR_NORDIC_INTEN_INTEN24_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[24]                                  */
99881   #define VPRCSR_NORDIC_INTEN_INTEN24_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[24]                                    */
99882 
99883 /* INTEN25 @Bit 25 : (unspecified) */
99884   #define VPRCSR_NORDIC_INTEN_INTEN25_Pos (25UL)     /*!< Position of INTEN25 field.                                           */
99885   #define VPRCSR_NORDIC_INTEN_INTEN25_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN25_Pos) /*!< Bit mask of INTEN25 field.           */
99886   #define VPRCSR_NORDIC_INTEN_INTEN25_Min (0x0UL)    /*!< Min enumerator value of INTEN25 field.                               */
99887   #define VPRCSR_NORDIC_INTEN_INTEN25_Max (0x1UL)    /*!< Max enumerator value of INTEN25 field.                               */
99888   #define VPRCSR_NORDIC_INTEN_INTEN25_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[25]                                  */
99889   #define VPRCSR_NORDIC_INTEN_INTEN25_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[25]                                    */
99890 
99891 /* INTEN26 @Bit 26 : (unspecified) */
99892   #define VPRCSR_NORDIC_INTEN_INTEN26_Pos (26UL)     /*!< Position of INTEN26 field.                                           */
99893   #define VPRCSR_NORDIC_INTEN_INTEN26_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN26_Pos) /*!< Bit mask of INTEN26 field.           */
99894   #define VPRCSR_NORDIC_INTEN_INTEN26_Min (0x0UL)    /*!< Min enumerator value of INTEN26 field.                               */
99895   #define VPRCSR_NORDIC_INTEN_INTEN26_Max (0x1UL)    /*!< Max enumerator value of INTEN26 field.                               */
99896   #define VPRCSR_NORDIC_INTEN_INTEN26_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[26]                                  */
99897   #define VPRCSR_NORDIC_INTEN_INTEN26_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[26]                                    */
99898 
99899 /* INTEN27 @Bit 27 : (unspecified) */
99900   #define VPRCSR_NORDIC_INTEN_INTEN27_Pos (27UL)     /*!< Position of INTEN27 field.                                           */
99901   #define VPRCSR_NORDIC_INTEN_INTEN27_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN27_Pos) /*!< Bit mask of INTEN27 field.           */
99902   #define VPRCSR_NORDIC_INTEN_INTEN27_Min (0x0UL)    /*!< Min enumerator value of INTEN27 field.                               */
99903   #define VPRCSR_NORDIC_INTEN_INTEN27_Max (0x1UL)    /*!< Max enumerator value of INTEN27 field.                               */
99904   #define VPRCSR_NORDIC_INTEN_INTEN27_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[27]                                  */
99905   #define VPRCSR_NORDIC_INTEN_INTEN27_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[27]                                    */
99906 
99907 /* INTEN28 @Bit 28 : (unspecified) */
99908   #define VPRCSR_NORDIC_INTEN_INTEN28_Pos (28UL)     /*!< Position of INTEN28 field.                                           */
99909   #define VPRCSR_NORDIC_INTEN_INTEN28_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN28_Pos) /*!< Bit mask of INTEN28 field.           */
99910   #define VPRCSR_NORDIC_INTEN_INTEN28_Min (0x0UL)    /*!< Min enumerator value of INTEN28 field.                               */
99911   #define VPRCSR_NORDIC_INTEN_INTEN28_Max (0x1UL)    /*!< Max enumerator value of INTEN28 field.                               */
99912   #define VPRCSR_NORDIC_INTEN_INTEN28_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[28]                                  */
99913   #define VPRCSR_NORDIC_INTEN_INTEN28_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[28]                                    */
99914 
99915 /* INTEN29 @Bit 29 : (unspecified) */
99916   #define VPRCSR_NORDIC_INTEN_INTEN29_Pos (29UL)     /*!< Position of INTEN29 field.                                           */
99917   #define VPRCSR_NORDIC_INTEN_INTEN29_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN29_Pos) /*!< Bit mask of INTEN29 field.           */
99918   #define VPRCSR_NORDIC_INTEN_INTEN29_Min (0x0UL)    /*!< Min enumerator value of INTEN29 field.                               */
99919   #define VPRCSR_NORDIC_INTEN_INTEN29_Max (0x1UL)    /*!< Max enumerator value of INTEN29 field.                               */
99920   #define VPRCSR_NORDIC_INTEN_INTEN29_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[29]                                  */
99921   #define VPRCSR_NORDIC_INTEN_INTEN29_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[29]                                    */
99922 
99923 /* INTEN30 @Bit 30 : (unspecified) */
99924   #define VPRCSR_NORDIC_INTEN_INTEN30_Pos (30UL)     /*!< Position of INTEN30 field.                                           */
99925   #define VPRCSR_NORDIC_INTEN_INTEN30_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN30_Pos) /*!< Bit mask of INTEN30 field.           */
99926   #define VPRCSR_NORDIC_INTEN_INTEN30_Min (0x0UL)    /*!< Min enumerator value of INTEN30 field.                               */
99927   #define VPRCSR_NORDIC_INTEN_INTEN30_Max (0x1UL)    /*!< Max enumerator value of INTEN30 field.                               */
99928   #define VPRCSR_NORDIC_INTEN_INTEN30_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[30]                                  */
99929   #define VPRCSR_NORDIC_INTEN_INTEN30_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[30]                                    */
99930 
99931 /* INTEN31 @Bit 31 : (unspecified) */
99932   #define VPRCSR_NORDIC_INTEN_INTEN31_Pos (31UL)     /*!< Position of INTEN31 field.                                           */
99933   #define VPRCSR_NORDIC_INTEN_INTEN31_Msk (0x1UL << VPRCSR_NORDIC_INTEN_INTEN31_Pos) /*!< Bit mask of INTEN31 field.           */
99934   #define VPRCSR_NORDIC_INTEN_INTEN31_Min (0x0UL)    /*!< Min enumerator value of INTEN31 field.                               */
99935   #define VPRCSR_NORDIC_INTEN_INTEN31_Max (0x1UL)    /*!< Max enumerator value of INTEN31 field.                               */
99936   #define VPRCSR_NORDIC_INTEN_INTEN31_Disabled (0x0UL) /*!< Interrupt disabled for EVENTS[31]                                  */
99937   #define VPRCSR_NORDIC_INTEN_INTEN31_Enabled (0x1UL) /*!< Interrupt enabled for EVENTS[31]                                    */
99938 
99939 
99940 /**
99941   * @brief EVENTSB [VPRCSR_NORDIC_EVENTSB] Buffered DPPI Events
99942   */
99943   #define VPRCSR_NORDIC_EVENTSB (0x000007E5ul)
99944   #define VPRCSR_NORDIC_EVENTSB_ResetValue (0x00000000UL) /*!< Reset value of EVENTSB register.                                */
99945 
99946 /* EVENTSB0 @Bit 0 : (unspecified) */
99947   #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Pos (0UL)   /*!< Position of EVENTSB0 field.                                          */
99948   #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB0_Pos) /*!< Bit mask of EVENTSB0 field.    */
99949   #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Min (0x0UL) /*!< Min enumerator value of EVENTSB0 field.                              */
99950   #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Max (0x1UL) /*!< Max enumerator value of EVENTSB0 field.                              */
99951   #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Disabled (0x0UL) /*!< EVENTSB[0] disabled                                             */
99952   #define VPRCSR_NORDIC_EVENTSB_EVENTSB0_Enabled (0x1UL) /*!< EVENTSB[0] enabled                                               */
99953 
99954 /* EVENTSB1 @Bit 1 : (unspecified) */
99955   #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Pos (1UL)   /*!< Position of EVENTSB1 field.                                          */
99956   #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB1_Pos) /*!< Bit mask of EVENTSB1 field.    */
99957   #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Min (0x0UL) /*!< Min enumerator value of EVENTSB1 field.                              */
99958   #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Max (0x1UL) /*!< Max enumerator value of EVENTSB1 field.                              */
99959   #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Disabled (0x0UL) /*!< EVENTSB[1] disabled                                             */
99960   #define VPRCSR_NORDIC_EVENTSB_EVENTSB1_Enabled (0x1UL) /*!< EVENTSB[1] enabled                                               */
99961 
99962 /* EVENTSB2 @Bit 2 : (unspecified) */
99963   #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Pos (2UL)   /*!< Position of EVENTSB2 field.                                          */
99964   #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB2_Pos) /*!< Bit mask of EVENTSB2 field.    */
99965   #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Min (0x0UL) /*!< Min enumerator value of EVENTSB2 field.                              */
99966   #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Max (0x1UL) /*!< Max enumerator value of EVENTSB2 field.                              */
99967   #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Disabled (0x0UL) /*!< EVENTSB[2] disabled                                             */
99968   #define VPRCSR_NORDIC_EVENTSB_EVENTSB2_Enabled (0x1UL) /*!< EVENTSB[2] enabled                                               */
99969 
99970 /* EVENTSB3 @Bit 3 : (unspecified) */
99971   #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Pos (3UL)   /*!< Position of EVENTSB3 field.                                          */
99972   #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB3_Pos) /*!< Bit mask of EVENTSB3 field.    */
99973   #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Min (0x0UL) /*!< Min enumerator value of EVENTSB3 field.                              */
99974   #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Max (0x1UL) /*!< Max enumerator value of EVENTSB3 field.                              */
99975   #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Disabled (0x0UL) /*!< EVENTSB[3] disabled                                             */
99976   #define VPRCSR_NORDIC_EVENTSB_EVENTSB3_Enabled (0x1UL) /*!< EVENTSB[3] enabled                                               */
99977 
99978 /* EVENTSB4 @Bit 4 : (unspecified) */
99979   #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Pos (4UL)   /*!< Position of EVENTSB4 field.                                          */
99980   #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB4_Pos) /*!< Bit mask of EVENTSB4 field.    */
99981   #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Min (0x0UL) /*!< Min enumerator value of EVENTSB4 field.                              */
99982   #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Max (0x1UL) /*!< Max enumerator value of EVENTSB4 field.                              */
99983   #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Disabled (0x0UL) /*!< EVENTSB[4] disabled                                             */
99984   #define VPRCSR_NORDIC_EVENTSB_EVENTSB4_Enabled (0x1UL) /*!< EVENTSB[4] enabled                                               */
99985 
99986 /* EVENTSB5 @Bit 5 : (unspecified) */
99987   #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Pos (5UL)   /*!< Position of EVENTSB5 field.                                          */
99988   #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB5_Pos) /*!< Bit mask of EVENTSB5 field.    */
99989   #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Min (0x0UL) /*!< Min enumerator value of EVENTSB5 field.                              */
99990   #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Max (0x1UL) /*!< Max enumerator value of EVENTSB5 field.                              */
99991   #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Disabled (0x0UL) /*!< EVENTSB[5] disabled                                             */
99992   #define VPRCSR_NORDIC_EVENTSB_EVENTSB5_Enabled (0x1UL) /*!< EVENTSB[5] enabled                                               */
99993 
99994 /* EVENTSB6 @Bit 6 : (unspecified) */
99995   #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Pos (6UL)   /*!< Position of EVENTSB6 field.                                          */
99996   #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB6_Pos) /*!< Bit mask of EVENTSB6 field.    */
99997   #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Min (0x0UL) /*!< Min enumerator value of EVENTSB6 field.                              */
99998   #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Max (0x1UL) /*!< Max enumerator value of EVENTSB6 field.                              */
99999   #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Disabled (0x0UL) /*!< EVENTSB[6] disabled                                             */
100000   #define VPRCSR_NORDIC_EVENTSB_EVENTSB6_Enabled (0x1UL) /*!< EVENTSB[6] enabled                                               */
100001 
100002 /* EVENTSB7 @Bit 7 : (unspecified) */
100003   #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Pos (7UL)   /*!< Position of EVENTSB7 field.                                          */
100004   #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB7_Pos) /*!< Bit mask of EVENTSB7 field.    */
100005   #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Min (0x0UL) /*!< Min enumerator value of EVENTSB7 field.                              */
100006   #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Max (0x1UL) /*!< Max enumerator value of EVENTSB7 field.                              */
100007   #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Disabled (0x0UL) /*!< EVENTSB[7] disabled                                             */
100008   #define VPRCSR_NORDIC_EVENTSB_EVENTSB7_Enabled (0x1UL) /*!< EVENTSB[7] enabled                                               */
100009 
100010 /* EVENTSB8 @Bit 8 : (unspecified) */
100011   #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Pos (8UL)   /*!< Position of EVENTSB8 field.                                          */
100012   #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB8_Pos) /*!< Bit mask of EVENTSB8 field.    */
100013   #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Min (0x0UL) /*!< Min enumerator value of EVENTSB8 field.                              */
100014   #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Max (0x1UL) /*!< Max enumerator value of EVENTSB8 field.                              */
100015   #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Disabled (0x0UL) /*!< EVENTSB[8] disabled                                             */
100016   #define VPRCSR_NORDIC_EVENTSB_EVENTSB8_Enabled (0x1UL) /*!< EVENTSB[8] enabled                                               */
100017 
100018 /* EVENTSB9 @Bit 9 : (unspecified) */
100019   #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Pos (9UL)   /*!< Position of EVENTSB9 field.                                          */
100020   #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB9_Pos) /*!< Bit mask of EVENTSB9 field.    */
100021   #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Min (0x0UL) /*!< Min enumerator value of EVENTSB9 field.                              */
100022   #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Max (0x1UL) /*!< Max enumerator value of EVENTSB9 field.                              */
100023   #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Disabled (0x0UL) /*!< EVENTSB[9] disabled                                             */
100024   #define VPRCSR_NORDIC_EVENTSB_EVENTSB9_Enabled (0x1UL) /*!< EVENTSB[9] enabled                                               */
100025 
100026 /* EVENTSB10 @Bit 10 : (unspecified) */
100027   #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Pos (10UL) /*!< Position of EVENTSB10 field.                                         */
100028   #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB10_Pos) /*!< Bit mask of EVENTSB10 field. */
100029   #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Min (0x0UL) /*!< Min enumerator value of EVENTSB10 field.                            */
100030   #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Max (0x1UL) /*!< Max enumerator value of EVENTSB10 field.                            */
100031   #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Disabled (0x0UL) /*!< EVENTSB[10] disabled                                           */
100032   #define VPRCSR_NORDIC_EVENTSB_EVENTSB10_Enabled (0x1UL) /*!< EVENTSB[10] enabled                                             */
100033 
100034 /* EVENTSB11 @Bit 11 : (unspecified) */
100035   #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Pos (11UL) /*!< Position of EVENTSB11 field.                                         */
100036   #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB11_Pos) /*!< Bit mask of EVENTSB11 field. */
100037   #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Min (0x0UL) /*!< Min enumerator value of EVENTSB11 field.                            */
100038   #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Max (0x1UL) /*!< Max enumerator value of EVENTSB11 field.                            */
100039   #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Disabled (0x0UL) /*!< EVENTSB[11] disabled                                           */
100040   #define VPRCSR_NORDIC_EVENTSB_EVENTSB11_Enabled (0x1UL) /*!< EVENTSB[11] enabled                                             */
100041 
100042 /* EVENTSB12 @Bit 12 : (unspecified) */
100043   #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Pos (12UL) /*!< Position of EVENTSB12 field.                                         */
100044   #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB12_Pos) /*!< Bit mask of EVENTSB12 field. */
100045   #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Min (0x0UL) /*!< Min enumerator value of EVENTSB12 field.                            */
100046   #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Max (0x1UL) /*!< Max enumerator value of EVENTSB12 field.                            */
100047   #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Disabled (0x0UL) /*!< EVENTSB[12] disabled                                           */
100048   #define VPRCSR_NORDIC_EVENTSB_EVENTSB12_Enabled (0x1UL) /*!< EVENTSB[12] enabled                                             */
100049 
100050 /* EVENTSB13 @Bit 13 : (unspecified) */
100051   #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Pos (13UL) /*!< Position of EVENTSB13 field.                                         */
100052   #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB13_Pos) /*!< Bit mask of EVENTSB13 field. */
100053   #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Min (0x0UL) /*!< Min enumerator value of EVENTSB13 field.                            */
100054   #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Max (0x1UL) /*!< Max enumerator value of EVENTSB13 field.                            */
100055   #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Disabled (0x0UL) /*!< EVENTSB[13] disabled                                           */
100056   #define VPRCSR_NORDIC_EVENTSB_EVENTSB13_Enabled (0x1UL) /*!< EVENTSB[13] enabled                                             */
100057 
100058 /* EVENTSB14 @Bit 14 : (unspecified) */
100059   #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Pos (14UL) /*!< Position of EVENTSB14 field.                                         */
100060   #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB14_Pos) /*!< Bit mask of EVENTSB14 field. */
100061   #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Min (0x0UL) /*!< Min enumerator value of EVENTSB14 field.                            */
100062   #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Max (0x1UL) /*!< Max enumerator value of EVENTSB14 field.                            */
100063   #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Disabled (0x0UL) /*!< EVENTSB[14] disabled                                           */
100064   #define VPRCSR_NORDIC_EVENTSB_EVENTSB14_Enabled (0x1UL) /*!< EVENTSB[14] enabled                                             */
100065 
100066 /* EVENTSB15 @Bit 15 : (unspecified) */
100067   #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Pos (15UL) /*!< Position of EVENTSB15 field.                                         */
100068   #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB15_Pos) /*!< Bit mask of EVENTSB15 field. */
100069   #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Min (0x0UL) /*!< Min enumerator value of EVENTSB15 field.                            */
100070   #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Max (0x1UL) /*!< Max enumerator value of EVENTSB15 field.                            */
100071   #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Disabled (0x0UL) /*!< EVENTSB[15] disabled                                           */
100072   #define VPRCSR_NORDIC_EVENTSB_EVENTSB15_Enabled (0x1UL) /*!< EVENTSB[15] enabled                                             */
100073 
100074 /* EVENTSB16 @Bit 16 : (unspecified) */
100075   #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Pos (16UL) /*!< Position of EVENTSB16 field.                                         */
100076   #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB16_Pos) /*!< Bit mask of EVENTSB16 field. */
100077   #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Min (0x0UL) /*!< Min enumerator value of EVENTSB16 field.                            */
100078   #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Max (0x1UL) /*!< Max enumerator value of EVENTSB16 field.                            */
100079   #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Disabled (0x0UL) /*!< EVENTSB[16] disabled                                           */
100080   #define VPRCSR_NORDIC_EVENTSB_EVENTSB16_Enabled (0x1UL) /*!< EVENTSB[16] enabled                                             */
100081 
100082 /* EVENTSB17 @Bit 17 : (unspecified) */
100083   #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Pos (17UL) /*!< Position of EVENTSB17 field.                                         */
100084   #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB17_Pos) /*!< Bit mask of EVENTSB17 field. */
100085   #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Min (0x0UL) /*!< Min enumerator value of EVENTSB17 field.                            */
100086   #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Max (0x1UL) /*!< Max enumerator value of EVENTSB17 field.                            */
100087   #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Disabled (0x0UL) /*!< EVENTSB[17] disabled                                           */
100088   #define VPRCSR_NORDIC_EVENTSB_EVENTSB17_Enabled (0x1UL) /*!< EVENTSB[17] enabled                                             */
100089 
100090 /* EVENTSB18 @Bit 18 : (unspecified) */
100091   #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Pos (18UL) /*!< Position of EVENTSB18 field.                                         */
100092   #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB18_Pos) /*!< Bit mask of EVENTSB18 field. */
100093   #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Min (0x0UL) /*!< Min enumerator value of EVENTSB18 field.                            */
100094   #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Max (0x1UL) /*!< Max enumerator value of EVENTSB18 field.                            */
100095   #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Disabled (0x0UL) /*!< EVENTSB[18] disabled                                           */
100096   #define VPRCSR_NORDIC_EVENTSB_EVENTSB18_Enabled (0x1UL) /*!< EVENTSB[18] enabled                                             */
100097 
100098 /* EVENTSB19 @Bit 19 : (unspecified) */
100099   #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Pos (19UL) /*!< Position of EVENTSB19 field.                                         */
100100   #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB19_Pos) /*!< Bit mask of EVENTSB19 field. */
100101   #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Min (0x0UL) /*!< Min enumerator value of EVENTSB19 field.                            */
100102   #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Max (0x1UL) /*!< Max enumerator value of EVENTSB19 field.                            */
100103   #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Disabled (0x0UL) /*!< EVENTSB[19] disabled                                           */
100104   #define VPRCSR_NORDIC_EVENTSB_EVENTSB19_Enabled (0x1UL) /*!< EVENTSB[19] enabled                                             */
100105 
100106 /* EVENTSB20 @Bit 20 : (unspecified) */
100107   #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Pos (20UL) /*!< Position of EVENTSB20 field.                                         */
100108   #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB20_Pos) /*!< Bit mask of EVENTSB20 field. */
100109   #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Min (0x0UL) /*!< Min enumerator value of EVENTSB20 field.                            */
100110   #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Max (0x1UL) /*!< Max enumerator value of EVENTSB20 field.                            */
100111   #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Disabled (0x0UL) /*!< EVENTSB[20] disabled                                           */
100112   #define VPRCSR_NORDIC_EVENTSB_EVENTSB20_Enabled (0x1UL) /*!< EVENTSB[20] enabled                                             */
100113 
100114 /* EVENTSB21 @Bit 21 : (unspecified) */
100115   #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Pos (21UL) /*!< Position of EVENTSB21 field.                                         */
100116   #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB21_Pos) /*!< Bit mask of EVENTSB21 field. */
100117   #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Min (0x0UL) /*!< Min enumerator value of EVENTSB21 field.                            */
100118   #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Max (0x1UL) /*!< Max enumerator value of EVENTSB21 field.                            */
100119   #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Disabled (0x0UL) /*!< EVENTSB[21] disabled                                           */
100120   #define VPRCSR_NORDIC_EVENTSB_EVENTSB21_Enabled (0x1UL) /*!< EVENTSB[21] enabled                                             */
100121 
100122 /* EVENTSB22 @Bit 22 : (unspecified) */
100123   #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Pos (22UL) /*!< Position of EVENTSB22 field.                                         */
100124   #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB22_Pos) /*!< Bit mask of EVENTSB22 field. */
100125   #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Min (0x0UL) /*!< Min enumerator value of EVENTSB22 field.                            */
100126   #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Max (0x1UL) /*!< Max enumerator value of EVENTSB22 field.                            */
100127   #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Disabled (0x0UL) /*!< EVENTSB[22] disabled                                           */
100128   #define VPRCSR_NORDIC_EVENTSB_EVENTSB22_Enabled (0x1UL) /*!< EVENTSB[22] enabled                                             */
100129 
100130 /* EVENTSB23 @Bit 23 : (unspecified) */
100131   #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Pos (23UL) /*!< Position of EVENTSB23 field.                                         */
100132   #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB23_Pos) /*!< Bit mask of EVENTSB23 field. */
100133   #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Min (0x0UL) /*!< Min enumerator value of EVENTSB23 field.                            */
100134   #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Max (0x1UL) /*!< Max enumerator value of EVENTSB23 field.                            */
100135   #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Disabled (0x0UL) /*!< EVENTSB[23] disabled                                           */
100136   #define VPRCSR_NORDIC_EVENTSB_EVENTSB23_Enabled (0x1UL) /*!< EVENTSB[23] enabled                                             */
100137 
100138 /* EVENTSB24 @Bit 24 : (unspecified) */
100139   #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Pos (24UL) /*!< Position of EVENTSB24 field.                                         */
100140   #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB24_Pos) /*!< Bit mask of EVENTSB24 field. */
100141   #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Min (0x0UL) /*!< Min enumerator value of EVENTSB24 field.                            */
100142   #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Max (0x1UL) /*!< Max enumerator value of EVENTSB24 field.                            */
100143   #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Disabled (0x0UL) /*!< EVENTSB[24] disabled                                           */
100144   #define VPRCSR_NORDIC_EVENTSB_EVENTSB24_Enabled (0x1UL) /*!< EVENTSB[24] enabled                                             */
100145 
100146 /* EVENTSB25 @Bit 25 : (unspecified) */
100147   #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Pos (25UL) /*!< Position of EVENTSB25 field.                                         */
100148   #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB25_Pos) /*!< Bit mask of EVENTSB25 field. */
100149   #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Min (0x0UL) /*!< Min enumerator value of EVENTSB25 field.                            */
100150   #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Max (0x1UL) /*!< Max enumerator value of EVENTSB25 field.                            */
100151   #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Disabled (0x0UL) /*!< EVENTSB[25] disabled                                           */
100152   #define VPRCSR_NORDIC_EVENTSB_EVENTSB25_Enabled (0x1UL) /*!< EVENTSB[25] enabled                                             */
100153 
100154 /* EVENTSB26 @Bit 26 : (unspecified) */
100155   #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Pos (26UL) /*!< Position of EVENTSB26 field.                                         */
100156   #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB26_Pos) /*!< Bit mask of EVENTSB26 field. */
100157   #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Min (0x0UL) /*!< Min enumerator value of EVENTSB26 field.                            */
100158   #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Max (0x1UL) /*!< Max enumerator value of EVENTSB26 field.                            */
100159   #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Disabled (0x0UL) /*!< EVENTSB[26] disabled                                           */
100160   #define VPRCSR_NORDIC_EVENTSB_EVENTSB26_Enabled (0x1UL) /*!< EVENTSB[26] enabled                                             */
100161 
100162 /* EVENTSB27 @Bit 27 : (unspecified) */
100163   #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Pos (27UL) /*!< Position of EVENTSB27 field.                                         */
100164   #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB27_Pos) /*!< Bit mask of EVENTSB27 field. */
100165   #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Min (0x0UL) /*!< Min enumerator value of EVENTSB27 field.                            */
100166   #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Max (0x1UL) /*!< Max enumerator value of EVENTSB27 field.                            */
100167   #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Disabled (0x0UL) /*!< EVENTSB[27] disabled                                           */
100168   #define VPRCSR_NORDIC_EVENTSB_EVENTSB27_Enabled (0x1UL) /*!< EVENTSB[27] enabled                                             */
100169 
100170 /* EVENTSB28 @Bit 28 : (unspecified) */
100171   #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Pos (28UL) /*!< Position of EVENTSB28 field.                                         */
100172   #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB28_Pos) /*!< Bit mask of EVENTSB28 field. */
100173   #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Min (0x0UL) /*!< Min enumerator value of EVENTSB28 field.                            */
100174   #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Max (0x1UL) /*!< Max enumerator value of EVENTSB28 field.                            */
100175   #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Disabled (0x0UL) /*!< EVENTSB[28] disabled                                           */
100176   #define VPRCSR_NORDIC_EVENTSB_EVENTSB28_Enabled (0x1UL) /*!< EVENTSB[28] enabled                                             */
100177 
100178 /* EVENTSB29 @Bit 29 : (unspecified) */
100179   #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Pos (29UL) /*!< Position of EVENTSB29 field.                                         */
100180   #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB29_Pos) /*!< Bit mask of EVENTSB29 field. */
100181   #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Min (0x0UL) /*!< Min enumerator value of EVENTSB29 field.                            */
100182   #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Max (0x1UL) /*!< Max enumerator value of EVENTSB29 field.                            */
100183   #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Disabled (0x0UL) /*!< EVENTSB[29] disabled                                           */
100184   #define VPRCSR_NORDIC_EVENTSB_EVENTSB29_Enabled (0x1UL) /*!< EVENTSB[29] enabled                                             */
100185 
100186 /* EVENTSB30 @Bit 30 : (unspecified) */
100187   #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Pos (30UL) /*!< Position of EVENTSB30 field.                                         */
100188   #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB30_Pos) /*!< Bit mask of EVENTSB30 field. */
100189   #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Min (0x0UL) /*!< Min enumerator value of EVENTSB30 field.                            */
100190   #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Max (0x1UL) /*!< Max enumerator value of EVENTSB30 field.                            */
100191   #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Disabled (0x0UL) /*!< EVENTSB[30] disabled                                           */
100192   #define VPRCSR_NORDIC_EVENTSB_EVENTSB30_Enabled (0x1UL) /*!< EVENTSB[30] enabled                                             */
100193 
100194 /* EVENTSB31 @Bit 31 : (unspecified) */
100195   #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Pos (31UL) /*!< Position of EVENTSB31 field.                                         */
100196   #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Msk (0x1UL << VPRCSR_NORDIC_EVENTSB_EVENTSB31_Pos) /*!< Bit mask of EVENTSB31 field. */
100197   #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Min (0x0UL) /*!< Min enumerator value of EVENTSB31 field.                            */
100198   #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Max (0x1UL) /*!< Max enumerator value of EVENTSB31 field.                            */
100199   #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Disabled (0x0UL) /*!< EVENTSB[31] disabled                                           */
100200   #define VPRCSR_NORDIC_EVENTSB_EVENTSB31_Enabled (0x1UL) /*!< EVENTSB[31] enabled                                             */
100201 
100202 
100203 /**
100204   * @brief EVENTSBS [VPRCSR_NORDIC_EVENTSBS] EVENTSB Dirty Status
100205   */
100206   #define VPRCSR_NORDIC_EVENTSBS (0x000007E6ul)
100207   #define VPRCSR_NORDIC_EVENTSBS_ResetValue (0x00000000UL) /*!< Reset value of EVENTSBS register.                              */
100208 
100209 /* EVENTSB @Bits 0..31 : Write to EVENTSB (if not dirty) */
100210   #define VPRCSR_NORDIC_EVENTSBS_EVENTSB_Pos (0UL)   /*!< Position of EVENTSB field.                                           */
100211   #define VPRCSR_NORDIC_EVENTSBS_EVENTSB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_EVENTSBS_EVENTSB_Pos) /*!< Bit mask of EVENTSB
100212                                                                             field.*/
100213 
100214 /* DIRTYBIT @Bit 0 : Read EVENTSB Dirty status */
100215   #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Pos (0UL)  /*!< Position of DIRTYBIT field.                                          */
100216   #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.  */
100217   #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field.                             */
100218   #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field.                             */
100219   #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                   */
100220   #define VPRCSR_NORDIC_EVENTSBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                   */
100221 
100222 
100223 /**
100224   * @brief OUT [VPRCSR_NORDIC_OUT] GPIO Output value. Real Time Peripherals VIO.
100225   */
100226   #define VPRCSR_NORDIC_OUT (0x00000BC0ul)
100227   #define VPRCSR_NORDIC_OUT_ResetValue (0x00000000UL) /*!< Reset value of OUT register.                                        */
100228 
100229 /* PIN0 @Bit 0 : (unspecified) */
100230   #define VPRCSR_NORDIC_OUT_PIN0_Pos (0UL)           /*!< Position of PIN0 field.                                              */
100231   #define VPRCSR_NORDIC_OUT_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field.                        */
100232   #define VPRCSR_NORDIC_OUT_PIN0_Min (0x0UL)         /*!< Min enumerator value of PIN0 field.                                  */
100233   #define VPRCSR_NORDIC_OUT_PIN0_Max (0x1UL)         /*!< Max enumerator value of PIN0 field.                                  */
100234   #define VPRCSR_NORDIC_OUT_PIN0_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100235   #define VPRCSR_NORDIC_OUT_PIN0_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100236 
100237 /* PIN1 @Bit 1 : (unspecified) */
100238   #define VPRCSR_NORDIC_OUT_PIN1_Pos (1UL)           /*!< Position of PIN1 field.                                              */
100239   #define VPRCSR_NORDIC_OUT_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field.                        */
100240   #define VPRCSR_NORDIC_OUT_PIN1_Min (0x0UL)         /*!< Min enumerator value of PIN1 field.                                  */
100241   #define VPRCSR_NORDIC_OUT_PIN1_Max (0x1UL)         /*!< Max enumerator value of PIN1 field.                                  */
100242   #define VPRCSR_NORDIC_OUT_PIN1_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100243   #define VPRCSR_NORDIC_OUT_PIN1_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100244 
100245 /* PIN2 @Bit 2 : (unspecified) */
100246   #define VPRCSR_NORDIC_OUT_PIN2_Pos (2UL)           /*!< Position of PIN2 field.                                              */
100247   #define VPRCSR_NORDIC_OUT_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field.                        */
100248   #define VPRCSR_NORDIC_OUT_PIN2_Min (0x0UL)         /*!< Min enumerator value of PIN2 field.                                  */
100249   #define VPRCSR_NORDIC_OUT_PIN2_Max (0x1UL)         /*!< Max enumerator value of PIN2 field.                                  */
100250   #define VPRCSR_NORDIC_OUT_PIN2_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100251   #define VPRCSR_NORDIC_OUT_PIN2_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100252 
100253 /* PIN3 @Bit 3 : (unspecified) */
100254   #define VPRCSR_NORDIC_OUT_PIN3_Pos (3UL)           /*!< Position of PIN3 field.                                              */
100255   #define VPRCSR_NORDIC_OUT_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field.                        */
100256   #define VPRCSR_NORDIC_OUT_PIN3_Min (0x0UL)         /*!< Min enumerator value of PIN3 field.                                  */
100257   #define VPRCSR_NORDIC_OUT_PIN3_Max (0x1UL)         /*!< Max enumerator value of PIN3 field.                                  */
100258   #define VPRCSR_NORDIC_OUT_PIN3_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100259   #define VPRCSR_NORDIC_OUT_PIN3_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100260 
100261 /* PIN4 @Bit 4 : (unspecified) */
100262   #define VPRCSR_NORDIC_OUT_PIN4_Pos (4UL)           /*!< Position of PIN4 field.                                              */
100263   #define VPRCSR_NORDIC_OUT_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field.                        */
100264   #define VPRCSR_NORDIC_OUT_PIN4_Min (0x0UL)         /*!< Min enumerator value of PIN4 field.                                  */
100265   #define VPRCSR_NORDIC_OUT_PIN4_Max (0x1UL)         /*!< Max enumerator value of PIN4 field.                                  */
100266   #define VPRCSR_NORDIC_OUT_PIN4_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100267   #define VPRCSR_NORDIC_OUT_PIN4_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100268 
100269 /* PIN5 @Bit 5 : (unspecified) */
100270   #define VPRCSR_NORDIC_OUT_PIN5_Pos (5UL)           /*!< Position of PIN5 field.                                              */
100271   #define VPRCSR_NORDIC_OUT_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field.                        */
100272   #define VPRCSR_NORDIC_OUT_PIN5_Min (0x0UL)         /*!< Min enumerator value of PIN5 field.                                  */
100273   #define VPRCSR_NORDIC_OUT_PIN5_Max (0x1UL)         /*!< Max enumerator value of PIN5 field.                                  */
100274   #define VPRCSR_NORDIC_OUT_PIN5_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100275   #define VPRCSR_NORDIC_OUT_PIN5_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100276 
100277 /* PIN6 @Bit 6 : (unspecified) */
100278   #define VPRCSR_NORDIC_OUT_PIN6_Pos (6UL)           /*!< Position of PIN6 field.                                              */
100279   #define VPRCSR_NORDIC_OUT_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field.                        */
100280   #define VPRCSR_NORDIC_OUT_PIN6_Min (0x0UL)         /*!< Min enumerator value of PIN6 field.                                  */
100281   #define VPRCSR_NORDIC_OUT_PIN6_Max (0x1UL)         /*!< Max enumerator value of PIN6 field.                                  */
100282   #define VPRCSR_NORDIC_OUT_PIN6_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100283   #define VPRCSR_NORDIC_OUT_PIN6_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100284 
100285 /* PIN7 @Bit 7 : (unspecified) */
100286   #define VPRCSR_NORDIC_OUT_PIN7_Pos (7UL)           /*!< Position of PIN7 field.                                              */
100287   #define VPRCSR_NORDIC_OUT_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field.                        */
100288   #define VPRCSR_NORDIC_OUT_PIN7_Min (0x0UL)         /*!< Min enumerator value of PIN7 field.                                  */
100289   #define VPRCSR_NORDIC_OUT_PIN7_Max (0x1UL)         /*!< Max enumerator value of PIN7 field.                                  */
100290   #define VPRCSR_NORDIC_OUT_PIN7_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100291   #define VPRCSR_NORDIC_OUT_PIN7_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100292 
100293 /* PIN8 @Bit 8 : (unspecified) */
100294   #define VPRCSR_NORDIC_OUT_PIN8_Pos (8UL)           /*!< Position of PIN8 field.                                              */
100295   #define VPRCSR_NORDIC_OUT_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field.                        */
100296   #define VPRCSR_NORDIC_OUT_PIN8_Min (0x0UL)         /*!< Min enumerator value of PIN8 field.                                  */
100297   #define VPRCSR_NORDIC_OUT_PIN8_Max (0x1UL)         /*!< Max enumerator value of PIN8 field.                                  */
100298   #define VPRCSR_NORDIC_OUT_PIN8_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100299   #define VPRCSR_NORDIC_OUT_PIN8_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100300 
100301 /* PIN9 @Bit 9 : (unspecified) */
100302   #define VPRCSR_NORDIC_OUT_PIN9_Pos (9UL)           /*!< Position of PIN9 field.                                              */
100303   #define VPRCSR_NORDIC_OUT_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field.                        */
100304   #define VPRCSR_NORDIC_OUT_PIN9_Min (0x0UL)         /*!< Min enumerator value of PIN9 field.                                  */
100305   #define VPRCSR_NORDIC_OUT_PIN9_Max (0x1UL)         /*!< Max enumerator value of PIN9 field.                                  */
100306   #define VPRCSR_NORDIC_OUT_PIN9_LOW (0x0UL)         /*!< Pin driver is low                                                    */
100307   #define VPRCSR_NORDIC_OUT_PIN9_HIGH (0x1UL)        /*!< Pin driver is high                                                   */
100308 
100309 /* PIN10 @Bit 10 : (unspecified) */
100310   #define VPRCSR_NORDIC_OUT_PIN10_Pos (10UL)         /*!< Position of PIN10 field.                                             */
100311   #define VPRCSR_NORDIC_OUT_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field.                     */
100312   #define VPRCSR_NORDIC_OUT_PIN10_Min (0x0UL)        /*!< Min enumerator value of PIN10 field.                                 */
100313   #define VPRCSR_NORDIC_OUT_PIN10_Max (0x1UL)        /*!< Max enumerator value of PIN10 field.                                 */
100314   #define VPRCSR_NORDIC_OUT_PIN10_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100315   #define VPRCSR_NORDIC_OUT_PIN10_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100316 
100317 /* PIN11 @Bit 11 : (unspecified) */
100318   #define VPRCSR_NORDIC_OUT_PIN11_Pos (11UL)         /*!< Position of PIN11 field.                                             */
100319   #define VPRCSR_NORDIC_OUT_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field.                     */
100320   #define VPRCSR_NORDIC_OUT_PIN11_Min (0x0UL)        /*!< Min enumerator value of PIN11 field.                                 */
100321   #define VPRCSR_NORDIC_OUT_PIN11_Max (0x1UL)        /*!< Max enumerator value of PIN11 field.                                 */
100322   #define VPRCSR_NORDIC_OUT_PIN11_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100323   #define VPRCSR_NORDIC_OUT_PIN11_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100324 
100325 /* PIN12 @Bit 12 : (unspecified) */
100326   #define VPRCSR_NORDIC_OUT_PIN12_Pos (12UL)         /*!< Position of PIN12 field.                                             */
100327   #define VPRCSR_NORDIC_OUT_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field.                     */
100328   #define VPRCSR_NORDIC_OUT_PIN12_Min (0x0UL)        /*!< Min enumerator value of PIN12 field.                                 */
100329   #define VPRCSR_NORDIC_OUT_PIN12_Max (0x1UL)        /*!< Max enumerator value of PIN12 field.                                 */
100330   #define VPRCSR_NORDIC_OUT_PIN12_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100331   #define VPRCSR_NORDIC_OUT_PIN12_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100332 
100333 /* PIN13 @Bit 13 : (unspecified) */
100334   #define VPRCSR_NORDIC_OUT_PIN13_Pos (13UL)         /*!< Position of PIN13 field.                                             */
100335   #define VPRCSR_NORDIC_OUT_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field.                     */
100336   #define VPRCSR_NORDIC_OUT_PIN13_Min (0x0UL)        /*!< Min enumerator value of PIN13 field.                                 */
100337   #define VPRCSR_NORDIC_OUT_PIN13_Max (0x1UL)        /*!< Max enumerator value of PIN13 field.                                 */
100338   #define VPRCSR_NORDIC_OUT_PIN13_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100339   #define VPRCSR_NORDIC_OUT_PIN13_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100340 
100341 /* PIN14 @Bit 14 : (unspecified) */
100342   #define VPRCSR_NORDIC_OUT_PIN14_Pos (14UL)         /*!< Position of PIN14 field.                                             */
100343   #define VPRCSR_NORDIC_OUT_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field.                     */
100344   #define VPRCSR_NORDIC_OUT_PIN14_Min (0x0UL)        /*!< Min enumerator value of PIN14 field.                                 */
100345   #define VPRCSR_NORDIC_OUT_PIN14_Max (0x1UL)        /*!< Max enumerator value of PIN14 field.                                 */
100346   #define VPRCSR_NORDIC_OUT_PIN14_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100347   #define VPRCSR_NORDIC_OUT_PIN14_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100348 
100349 /* PIN15 @Bit 15 : (unspecified) */
100350   #define VPRCSR_NORDIC_OUT_PIN15_Pos (15UL)         /*!< Position of PIN15 field.                                             */
100351   #define VPRCSR_NORDIC_OUT_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field.                     */
100352   #define VPRCSR_NORDIC_OUT_PIN15_Min (0x0UL)        /*!< Min enumerator value of PIN15 field.                                 */
100353   #define VPRCSR_NORDIC_OUT_PIN15_Max (0x1UL)        /*!< Max enumerator value of PIN15 field.                                 */
100354   #define VPRCSR_NORDIC_OUT_PIN15_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100355   #define VPRCSR_NORDIC_OUT_PIN15_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100356 
100357 
100358 /**
100359   * @brief DIR [VPRCSR_NORDIC_DIR] GPIO pin Direction. Real Time Peripherals VIO.
100360   */
100361   #define VPRCSR_NORDIC_DIR (0x00000BC1ul)
100362   #define VPRCSR_NORDIC_DIR_ResetValue (0x00000000UL) /*!< Reset value of DIR register.                                        */
100363 
100364 /* PIN0 @Bit 0 : (unspecified) */
100365   #define VPRCSR_NORDIC_DIR_PIN0_Pos (0UL)           /*!< Position of PIN0 field.                                              */
100366   #define VPRCSR_NORDIC_DIR_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field.                        */
100367   #define VPRCSR_NORDIC_DIR_PIN0_Min (0x0UL)         /*!< Min enumerator value of PIN0 field.                                  */
100368   #define VPRCSR_NORDIC_DIR_PIN0_Max (0x1UL)         /*!< Max enumerator value of PIN0 field.                                  */
100369   #define VPRCSR_NORDIC_DIR_PIN0_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100370   #define VPRCSR_NORDIC_DIR_PIN0_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100371 
100372 /* PIN1 @Bit 1 : (unspecified) */
100373   #define VPRCSR_NORDIC_DIR_PIN1_Pos (1UL)           /*!< Position of PIN1 field.                                              */
100374   #define VPRCSR_NORDIC_DIR_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field.                        */
100375   #define VPRCSR_NORDIC_DIR_PIN1_Min (0x0UL)         /*!< Min enumerator value of PIN1 field.                                  */
100376   #define VPRCSR_NORDIC_DIR_PIN1_Max (0x1UL)         /*!< Max enumerator value of PIN1 field.                                  */
100377   #define VPRCSR_NORDIC_DIR_PIN1_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100378   #define VPRCSR_NORDIC_DIR_PIN1_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100379 
100380 /* PIN2 @Bit 2 : (unspecified) */
100381   #define VPRCSR_NORDIC_DIR_PIN2_Pos (2UL)           /*!< Position of PIN2 field.                                              */
100382   #define VPRCSR_NORDIC_DIR_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field.                        */
100383   #define VPRCSR_NORDIC_DIR_PIN2_Min (0x0UL)         /*!< Min enumerator value of PIN2 field.                                  */
100384   #define VPRCSR_NORDIC_DIR_PIN2_Max (0x1UL)         /*!< Max enumerator value of PIN2 field.                                  */
100385   #define VPRCSR_NORDIC_DIR_PIN2_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100386   #define VPRCSR_NORDIC_DIR_PIN2_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100387 
100388 /* PIN3 @Bit 3 : (unspecified) */
100389   #define VPRCSR_NORDIC_DIR_PIN3_Pos (3UL)           /*!< Position of PIN3 field.                                              */
100390   #define VPRCSR_NORDIC_DIR_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field.                        */
100391   #define VPRCSR_NORDIC_DIR_PIN3_Min (0x0UL)         /*!< Min enumerator value of PIN3 field.                                  */
100392   #define VPRCSR_NORDIC_DIR_PIN3_Max (0x1UL)         /*!< Max enumerator value of PIN3 field.                                  */
100393   #define VPRCSR_NORDIC_DIR_PIN3_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100394   #define VPRCSR_NORDIC_DIR_PIN3_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100395 
100396 /* PIN4 @Bit 4 : (unspecified) */
100397   #define VPRCSR_NORDIC_DIR_PIN4_Pos (4UL)           /*!< Position of PIN4 field.                                              */
100398   #define VPRCSR_NORDIC_DIR_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field.                        */
100399   #define VPRCSR_NORDIC_DIR_PIN4_Min (0x0UL)         /*!< Min enumerator value of PIN4 field.                                  */
100400   #define VPRCSR_NORDIC_DIR_PIN4_Max (0x1UL)         /*!< Max enumerator value of PIN4 field.                                  */
100401   #define VPRCSR_NORDIC_DIR_PIN4_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100402   #define VPRCSR_NORDIC_DIR_PIN4_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100403 
100404 /* PIN5 @Bit 5 : (unspecified) */
100405   #define VPRCSR_NORDIC_DIR_PIN5_Pos (5UL)           /*!< Position of PIN5 field.                                              */
100406   #define VPRCSR_NORDIC_DIR_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field.                        */
100407   #define VPRCSR_NORDIC_DIR_PIN5_Min (0x0UL)         /*!< Min enumerator value of PIN5 field.                                  */
100408   #define VPRCSR_NORDIC_DIR_PIN5_Max (0x1UL)         /*!< Max enumerator value of PIN5 field.                                  */
100409   #define VPRCSR_NORDIC_DIR_PIN5_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100410   #define VPRCSR_NORDIC_DIR_PIN5_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100411 
100412 /* PIN6 @Bit 6 : (unspecified) */
100413   #define VPRCSR_NORDIC_DIR_PIN6_Pos (6UL)           /*!< Position of PIN6 field.                                              */
100414   #define VPRCSR_NORDIC_DIR_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field.                        */
100415   #define VPRCSR_NORDIC_DIR_PIN6_Min (0x0UL)         /*!< Min enumerator value of PIN6 field.                                  */
100416   #define VPRCSR_NORDIC_DIR_PIN6_Max (0x1UL)         /*!< Max enumerator value of PIN6 field.                                  */
100417   #define VPRCSR_NORDIC_DIR_PIN6_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100418   #define VPRCSR_NORDIC_DIR_PIN6_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100419 
100420 /* PIN7 @Bit 7 : (unspecified) */
100421   #define VPRCSR_NORDIC_DIR_PIN7_Pos (7UL)           /*!< Position of PIN7 field.                                              */
100422   #define VPRCSR_NORDIC_DIR_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field.                        */
100423   #define VPRCSR_NORDIC_DIR_PIN7_Min (0x0UL)         /*!< Min enumerator value of PIN7 field.                                  */
100424   #define VPRCSR_NORDIC_DIR_PIN7_Max (0x1UL)         /*!< Max enumerator value of PIN7 field.                                  */
100425   #define VPRCSR_NORDIC_DIR_PIN7_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100426   #define VPRCSR_NORDIC_DIR_PIN7_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100427 
100428 /* PIN8 @Bit 8 : (unspecified) */
100429   #define VPRCSR_NORDIC_DIR_PIN8_Pos (8UL)           /*!< Position of PIN8 field.                                              */
100430   #define VPRCSR_NORDIC_DIR_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field.                        */
100431   #define VPRCSR_NORDIC_DIR_PIN8_Min (0x0UL)         /*!< Min enumerator value of PIN8 field.                                  */
100432   #define VPRCSR_NORDIC_DIR_PIN8_Max (0x1UL)         /*!< Max enumerator value of PIN8 field.                                  */
100433   #define VPRCSR_NORDIC_DIR_PIN8_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100434   #define VPRCSR_NORDIC_DIR_PIN8_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100435 
100436 /* PIN9 @Bit 9 : (unspecified) */
100437   #define VPRCSR_NORDIC_DIR_PIN9_Pos (9UL)           /*!< Position of PIN9 field.                                              */
100438   #define VPRCSR_NORDIC_DIR_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field.                        */
100439   #define VPRCSR_NORDIC_DIR_PIN9_Min (0x0UL)         /*!< Min enumerator value of PIN9 field.                                  */
100440   #define VPRCSR_NORDIC_DIR_PIN9_Max (0x1UL)         /*!< Max enumerator value of PIN9 field.                                  */
100441   #define VPRCSR_NORDIC_DIR_PIN9_INPUT (0x0UL)       /*!< Pin is set as input                                                  */
100442   #define VPRCSR_NORDIC_DIR_PIN9_OUTPUT (0x1UL)      /*!< Pin is set as output                                                 */
100443 
100444 /* PIN10 @Bit 10 : (unspecified) */
100445   #define VPRCSR_NORDIC_DIR_PIN10_Pos (10UL)         /*!< Position of PIN10 field.                                             */
100446   #define VPRCSR_NORDIC_DIR_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field.                     */
100447   #define VPRCSR_NORDIC_DIR_PIN10_Min (0x0UL)        /*!< Min enumerator value of PIN10 field.                                 */
100448   #define VPRCSR_NORDIC_DIR_PIN10_Max (0x1UL)        /*!< Max enumerator value of PIN10 field.                                 */
100449   #define VPRCSR_NORDIC_DIR_PIN10_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
100450   #define VPRCSR_NORDIC_DIR_PIN10_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
100451 
100452 /* PIN11 @Bit 11 : (unspecified) */
100453   #define VPRCSR_NORDIC_DIR_PIN11_Pos (11UL)         /*!< Position of PIN11 field.                                             */
100454   #define VPRCSR_NORDIC_DIR_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field.                     */
100455   #define VPRCSR_NORDIC_DIR_PIN11_Min (0x0UL)        /*!< Min enumerator value of PIN11 field.                                 */
100456   #define VPRCSR_NORDIC_DIR_PIN11_Max (0x1UL)        /*!< Max enumerator value of PIN11 field.                                 */
100457   #define VPRCSR_NORDIC_DIR_PIN11_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
100458   #define VPRCSR_NORDIC_DIR_PIN11_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
100459 
100460 /* PIN12 @Bit 12 : (unspecified) */
100461   #define VPRCSR_NORDIC_DIR_PIN12_Pos (12UL)         /*!< Position of PIN12 field.                                             */
100462   #define VPRCSR_NORDIC_DIR_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field.                     */
100463   #define VPRCSR_NORDIC_DIR_PIN12_Min (0x0UL)        /*!< Min enumerator value of PIN12 field.                                 */
100464   #define VPRCSR_NORDIC_DIR_PIN12_Max (0x1UL)        /*!< Max enumerator value of PIN12 field.                                 */
100465   #define VPRCSR_NORDIC_DIR_PIN12_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
100466   #define VPRCSR_NORDIC_DIR_PIN12_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
100467 
100468 /* PIN13 @Bit 13 : (unspecified) */
100469   #define VPRCSR_NORDIC_DIR_PIN13_Pos (13UL)         /*!< Position of PIN13 field.                                             */
100470   #define VPRCSR_NORDIC_DIR_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field.                     */
100471   #define VPRCSR_NORDIC_DIR_PIN13_Min (0x0UL)        /*!< Min enumerator value of PIN13 field.                                 */
100472   #define VPRCSR_NORDIC_DIR_PIN13_Max (0x1UL)        /*!< Max enumerator value of PIN13 field.                                 */
100473   #define VPRCSR_NORDIC_DIR_PIN13_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
100474   #define VPRCSR_NORDIC_DIR_PIN13_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
100475 
100476 /* PIN14 @Bit 14 : (unspecified) */
100477   #define VPRCSR_NORDIC_DIR_PIN14_Pos (14UL)         /*!< Position of PIN14 field.                                             */
100478   #define VPRCSR_NORDIC_DIR_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field.                     */
100479   #define VPRCSR_NORDIC_DIR_PIN14_Min (0x0UL)        /*!< Min enumerator value of PIN14 field.                                 */
100480   #define VPRCSR_NORDIC_DIR_PIN14_Max (0x1UL)        /*!< Max enumerator value of PIN14 field.                                 */
100481   #define VPRCSR_NORDIC_DIR_PIN14_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
100482   #define VPRCSR_NORDIC_DIR_PIN14_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
100483 
100484 /* PIN15 @Bit 15 : (unspecified) */
100485   #define VPRCSR_NORDIC_DIR_PIN15_Pos (15UL)         /*!< Position of PIN15 field.                                             */
100486   #define VPRCSR_NORDIC_DIR_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field.                     */
100487   #define VPRCSR_NORDIC_DIR_PIN15_Min (0x0UL)        /*!< Min enumerator value of PIN15 field.                                 */
100488   #define VPRCSR_NORDIC_DIR_PIN15_Max (0x1UL)        /*!< Max enumerator value of PIN15 field.                                 */
100489   #define VPRCSR_NORDIC_DIR_PIN15_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
100490   #define VPRCSR_NORDIC_DIR_PIN15_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
100491 
100492 
100493 /**
100494   * @brief IN [VPRCSR_NORDIC_IN] GPIO Input. Real Time Peripherals VIO.
100495   */
100496   #define VPRCSR_NORDIC_IN (0x00000BC2ul)
100497   #define VPRCSR_NORDIC_IN_ResetValue (0x00000000UL) /*!< Reset value of IN register.                                          */
100498 
100499 /* PIN0 @Bit 0 : (unspecified) */
100500   #define VPRCSR_NORDIC_IN_PIN0_Pos (0UL)            /*!< Position of PIN0 field.                                              */
100501   #define VPRCSR_NORDIC_IN_PIN0_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN0_Pos) /*!< Bit mask of PIN0 field.                          */
100502   #define VPRCSR_NORDIC_IN_PIN0_Min (0x0UL)          /*!< Min enumerator value of PIN0 field.                                  */
100503   #define VPRCSR_NORDIC_IN_PIN0_Max (0x1UL)          /*!< Max enumerator value of PIN0 field.                                  */
100504   #define VPRCSR_NORDIC_IN_PIN0_LOW (0x0UL)          /*!< Pin is Low                                                           */
100505   #define VPRCSR_NORDIC_IN_PIN0_HIGH (0x1UL)         /*!< Pin is High                                                          */
100506 
100507 /* PIN1 @Bit 1 : (unspecified) */
100508   #define VPRCSR_NORDIC_IN_PIN1_Pos (1UL)            /*!< Position of PIN1 field.                                              */
100509   #define VPRCSR_NORDIC_IN_PIN1_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN1_Pos) /*!< Bit mask of PIN1 field.                          */
100510   #define VPRCSR_NORDIC_IN_PIN1_Min (0x0UL)          /*!< Min enumerator value of PIN1 field.                                  */
100511   #define VPRCSR_NORDIC_IN_PIN1_Max (0x1UL)          /*!< Max enumerator value of PIN1 field.                                  */
100512   #define VPRCSR_NORDIC_IN_PIN1_LOW (0x0UL)          /*!< Pin is Low                                                           */
100513   #define VPRCSR_NORDIC_IN_PIN1_HIGH (0x1UL)         /*!< Pin is High                                                          */
100514 
100515 /* PIN2 @Bit 2 : (unspecified) */
100516   #define VPRCSR_NORDIC_IN_PIN2_Pos (2UL)            /*!< Position of PIN2 field.                                              */
100517   #define VPRCSR_NORDIC_IN_PIN2_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN2_Pos) /*!< Bit mask of PIN2 field.                          */
100518   #define VPRCSR_NORDIC_IN_PIN2_Min (0x0UL)          /*!< Min enumerator value of PIN2 field.                                  */
100519   #define VPRCSR_NORDIC_IN_PIN2_Max (0x1UL)          /*!< Max enumerator value of PIN2 field.                                  */
100520   #define VPRCSR_NORDIC_IN_PIN2_LOW (0x0UL)          /*!< Pin is Low                                                           */
100521   #define VPRCSR_NORDIC_IN_PIN2_HIGH (0x1UL)         /*!< Pin is High                                                          */
100522 
100523 /* PIN3 @Bit 3 : (unspecified) */
100524   #define VPRCSR_NORDIC_IN_PIN3_Pos (3UL)            /*!< Position of PIN3 field.                                              */
100525   #define VPRCSR_NORDIC_IN_PIN3_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN3_Pos) /*!< Bit mask of PIN3 field.                          */
100526   #define VPRCSR_NORDIC_IN_PIN3_Min (0x0UL)          /*!< Min enumerator value of PIN3 field.                                  */
100527   #define VPRCSR_NORDIC_IN_PIN3_Max (0x1UL)          /*!< Max enumerator value of PIN3 field.                                  */
100528   #define VPRCSR_NORDIC_IN_PIN3_LOW (0x0UL)          /*!< Pin is Low                                                           */
100529   #define VPRCSR_NORDIC_IN_PIN3_HIGH (0x1UL)         /*!< Pin is High                                                          */
100530 
100531 /* PIN4 @Bit 4 : (unspecified) */
100532   #define VPRCSR_NORDIC_IN_PIN4_Pos (4UL)            /*!< Position of PIN4 field.                                              */
100533   #define VPRCSR_NORDIC_IN_PIN4_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN4_Pos) /*!< Bit mask of PIN4 field.                          */
100534   #define VPRCSR_NORDIC_IN_PIN4_Min (0x0UL)          /*!< Min enumerator value of PIN4 field.                                  */
100535   #define VPRCSR_NORDIC_IN_PIN4_Max (0x1UL)          /*!< Max enumerator value of PIN4 field.                                  */
100536   #define VPRCSR_NORDIC_IN_PIN4_LOW (0x0UL)          /*!< Pin is Low                                                           */
100537   #define VPRCSR_NORDIC_IN_PIN4_HIGH (0x1UL)         /*!< Pin is High                                                          */
100538 
100539 /* PIN5 @Bit 5 : (unspecified) */
100540   #define VPRCSR_NORDIC_IN_PIN5_Pos (5UL)            /*!< Position of PIN5 field.                                              */
100541   #define VPRCSR_NORDIC_IN_PIN5_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN5_Pos) /*!< Bit mask of PIN5 field.                          */
100542   #define VPRCSR_NORDIC_IN_PIN5_Min (0x0UL)          /*!< Min enumerator value of PIN5 field.                                  */
100543   #define VPRCSR_NORDIC_IN_PIN5_Max (0x1UL)          /*!< Max enumerator value of PIN5 field.                                  */
100544   #define VPRCSR_NORDIC_IN_PIN5_LOW (0x0UL)          /*!< Pin is Low                                                           */
100545   #define VPRCSR_NORDIC_IN_PIN5_HIGH (0x1UL)         /*!< Pin is High                                                          */
100546 
100547 /* PIN6 @Bit 6 : (unspecified) */
100548   #define VPRCSR_NORDIC_IN_PIN6_Pos (6UL)            /*!< Position of PIN6 field.                                              */
100549   #define VPRCSR_NORDIC_IN_PIN6_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN6_Pos) /*!< Bit mask of PIN6 field.                          */
100550   #define VPRCSR_NORDIC_IN_PIN6_Min (0x0UL)          /*!< Min enumerator value of PIN6 field.                                  */
100551   #define VPRCSR_NORDIC_IN_PIN6_Max (0x1UL)          /*!< Max enumerator value of PIN6 field.                                  */
100552   #define VPRCSR_NORDIC_IN_PIN6_LOW (0x0UL)          /*!< Pin is Low                                                           */
100553   #define VPRCSR_NORDIC_IN_PIN6_HIGH (0x1UL)         /*!< Pin is High                                                          */
100554 
100555 /* PIN7 @Bit 7 : (unspecified) */
100556   #define VPRCSR_NORDIC_IN_PIN7_Pos (7UL)            /*!< Position of PIN7 field.                                              */
100557   #define VPRCSR_NORDIC_IN_PIN7_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN7_Pos) /*!< Bit mask of PIN7 field.                          */
100558   #define VPRCSR_NORDIC_IN_PIN7_Min (0x0UL)          /*!< Min enumerator value of PIN7 field.                                  */
100559   #define VPRCSR_NORDIC_IN_PIN7_Max (0x1UL)          /*!< Max enumerator value of PIN7 field.                                  */
100560   #define VPRCSR_NORDIC_IN_PIN7_LOW (0x0UL)          /*!< Pin is Low                                                           */
100561   #define VPRCSR_NORDIC_IN_PIN7_HIGH (0x1UL)         /*!< Pin is High                                                          */
100562 
100563 /* PIN8 @Bit 8 : (unspecified) */
100564   #define VPRCSR_NORDIC_IN_PIN8_Pos (8UL)            /*!< Position of PIN8 field.                                              */
100565   #define VPRCSR_NORDIC_IN_PIN8_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN8_Pos) /*!< Bit mask of PIN8 field.                          */
100566   #define VPRCSR_NORDIC_IN_PIN8_Min (0x0UL)          /*!< Min enumerator value of PIN8 field.                                  */
100567   #define VPRCSR_NORDIC_IN_PIN8_Max (0x1UL)          /*!< Max enumerator value of PIN8 field.                                  */
100568   #define VPRCSR_NORDIC_IN_PIN8_LOW (0x0UL)          /*!< Pin is Low                                                           */
100569   #define VPRCSR_NORDIC_IN_PIN8_HIGH (0x1UL)         /*!< Pin is High                                                          */
100570 
100571 /* PIN9 @Bit 9 : (unspecified) */
100572   #define VPRCSR_NORDIC_IN_PIN9_Pos (9UL)            /*!< Position of PIN9 field.                                              */
100573   #define VPRCSR_NORDIC_IN_PIN9_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN9_Pos) /*!< Bit mask of PIN9 field.                          */
100574   #define VPRCSR_NORDIC_IN_PIN9_Min (0x0UL)          /*!< Min enumerator value of PIN9 field.                                  */
100575   #define VPRCSR_NORDIC_IN_PIN9_Max (0x1UL)          /*!< Max enumerator value of PIN9 field.                                  */
100576   #define VPRCSR_NORDIC_IN_PIN9_LOW (0x0UL)          /*!< Pin is Low                                                           */
100577   #define VPRCSR_NORDIC_IN_PIN9_HIGH (0x1UL)         /*!< Pin is High                                                          */
100578 
100579 /* PIN10 @Bit 10 : (unspecified) */
100580   #define VPRCSR_NORDIC_IN_PIN10_Pos (10UL)          /*!< Position of PIN10 field.                                             */
100581   #define VPRCSR_NORDIC_IN_PIN10_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN10_Pos) /*!< Bit mask of PIN10 field.                       */
100582   #define VPRCSR_NORDIC_IN_PIN10_Min (0x0UL)         /*!< Min enumerator value of PIN10 field.                                 */
100583   #define VPRCSR_NORDIC_IN_PIN10_Max (0x1UL)         /*!< Max enumerator value of PIN10 field.                                 */
100584   #define VPRCSR_NORDIC_IN_PIN10_LOW (0x0UL)         /*!< Pin is Low                                                           */
100585   #define VPRCSR_NORDIC_IN_PIN10_HIGH (0x1UL)        /*!< Pin is High                                                          */
100586 
100587 /* PIN11 @Bit 11 : (unspecified) */
100588   #define VPRCSR_NORDIC_IN_PIN11_Pos (11UL)          /*!< Position of PIN11 field.                                             */
100589   #define VPRCSR_NORDIC_IN_PIN11_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN11_Pos) /*!< Bit mask of PIN11 field.                       */
100590   #define VPRCSR_NORDIC_IN_PIN11_Min (0x0UL)         /*!< Min enumerator value of PIN11 field.                                 */
100591   #define VPRCSR_NORDIC_IN_PIN11_Max (0x1UL)         /*!< Max enumerator value of PIN11 field.                                 */
100592   #define VPRCSR_NORDIC_IN_PIN11_LOW (0x0UL)         /*!< Pin is Low                                                           */
100593   #define VPRCSR_NORDIC_IN_PIN11_HIGH (0x1UL)        /*!< Pin is High                                                          */
100594 
100595 /* PIN12 @Bit 12 : (unspecified) */
100596   #define VPRCSR_NORDIC_IN_PIN12_Pos (12UL)          /*!< Position of PIN12 field.                                             */
100597   #define VPRCSR_NORDIC_IN_PIN12_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN12_Pos) /*!< Bit mask of PIN12 field.                       */
100598   #define VPRCSR_NORDIC_IN_PIN12_Min (0x0UL)         /*!< Min enumerator value of PIN12 field.                                 */
100599   #define VPRCSR_NORDIC_IN_PIN12_Max (0x1UL)         /*!< Max enumerator value of PIN12 field.                                 */
100600   #define VPRCSR_NORDIC_IN_PIN12_LOW (0x0UL)         /*!< Pin is Low                                                           */
100601   #define VPRCSR_NORDIC_IN_PIN12_HIGH (0x1UL)        /*!< Pin is High                                                          */
100602 
100603 /* PIN13 @Bit 13 : (unspecified) */
100604   #define VPRCSR_NORDIC_IN_PIN13_Pos (13UL)          /*!< Position of PIN13 field.                                             */
100605   #define VPRCSR_NORDIC_IN_PIN13_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN13_Pos) /*!< Bit mask of PIN13 field.                       */
100606   #define VPRCSR_NORDIC_IN_PIN13_Min (0x0UL)         /*!< Min enumerator value of PIN13 field.                                 */
100607   #define VPRCSR_NORDIC_IN_PIN13_Max (0x1UL)         /*!< Max enumerator value of PIN13 field.                                 */
100608   #define VPRCSR_NORDIC_IN_PIN13_LOW (0x0UL)         /*!< Pin is Low                                                           */
100609   #define VPRCSR_NORDIC_IN_PIN13_HIGH (0x1UL)        /*!< Pin is High                                                          */
100610 
100611 /* PIN14 @Bit 14 : (unspecified) */
100612   #define VPRCSR_NORDIC_IN_PIN14_Pos (14UL)          /*!< Position of PIN14 field.                                             */
100613   #define VPRCSR_NORDIC_IN_PIN14_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN14_Pos) /*!< Bit mask of PIN14 field.                       */
100614   #define VPRCSR_NORDIC_IN_PIN14_Min (0x0UL)         /*!< Min enumerator value of PIN14 field.                                 */
100615   #define VPRCSR_NORDIC_IN_PIN14_Max (0x1UL)         /*!< Max enumerator value of PIN14 field.                                 */
100616   #define VPRCSR_NORDIC_IN_PIN14_LOW (0x0UL)         /*!< Pin is Low                                                           */
100617   #define VPRCSR_NORDIC_IN_PIN14_HIGH (0x1UL)        /*!< Pin is High                                                          */
100618 
100619 /* PIN15 @Bit 15 : (unspecified) */
100620   #define VPRCSR_NORDIC_IN_PIN15_Pos (15UL)          /*!< Position of PIN15 field.                                             */
100621   #define VPRCSR_NORDIC_IN_PIN15_Msk (0x1UL << VPRCSR_NORDIC_IN_PIN15_Pos) /*!< Bit mask of PIN15 field.                       */
100622   #define VPRCSR_NORDIC_IN_PIN15_Min (0x0UL)         /*!< Min enumerator value of PIN15 field.                                 */
100623   #define VPRCSR_NORDIC_IN_PIN15_Max (0x1UL)         /*!< Max enumerator value of PIN15 field.                                 */
100624   #define VPRCSR_NORDIC_IN_PIN15_LOW (0x0UL)         /*!< Pin is Low                                                           */
100625   #define VPRCSR_NORDIC_IN_PIN15_HIGH (0x1UL)        /*!< Pin is High                                                          */
100626 
100627 
100628 /**
100629   * @brief INMODE [VPRCSR_NORDIC_INMODE] Input Mode
100630   */
100631   #define VPRCSR_NORDIC_INMODE (0x00000BC3ul)
100632   #define VPRCSR_NORDIC_INMODE_ResetValue (0x00000000UL) /*!< Reset value of INMODE register.                                  */
100633 
100634 /* MODE0 @Bit 0 : Input Mode */
100635   #define VPRCSR_NORDIC_INMODE_MODE0_Pos (0UL)       /*!< Position of MODE0 field.                                             */
100636   #define VPRCSR_NORDIC_INMODE_MODE0_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE0_Pos) /*!< Bit mask of MODE0 field.               */
100637   #define VPRCSR_NORDIC_INMODE_MODE0_Min (0x0UL)     /*!< Min enumerator value of MODE0 field.                                 */
100638   #define VPRCSR_NORDIC_INMODE_MODE0_Max (0x1UL)     /*!< Max enumerator value of MODE0 field.                                 */
100639   #define VPRCSR_NORDIC_INMODE_MODE0_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100640   #define VPRCSR_NORDIC_INMODE_MODE0_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100641 
100642 /* MODE1 @Bit 1 : Input Mode */
100643   #define VPRCSR_NORDIC_INMODE_MODE1_Pos (1UL)       /*!< Position of MODE1 field.                                             */
100644   #define VPRCSR_NORDIC_INMODE_MODE1_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE1_Pos) /*!< Bit mask of MODE1 field.               */
100645   #define VPRCSR_NORDIC_INMODE_MODE1_Min (0x0UL)     /*!< Min enumerator value of MODE1 field.                                 */
100646   #define VPRCSR_NORDIC_INMODE_MODE1_Max (0x1UL)     /*!< Max enumerator value of MODE1 field.                                 */
100647   #define VPRCSR_NORDIC_INMODE_MODE1_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100648   #define VPRCSR_NORDIC_INMODE_MODE1_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100649 
100650 /* MODE2 @Bit 2 : Input Mode */
100651   #define VPRCSR_NORDIC_INMODE_MODE2_Pos (2UL)       /*!< Position of MODE2 field.                                             */
100652   #define VPRCSR_NORDIC_INMODE_MODE2_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE2_Pos) /*!< Bit mask of MODE2 field.               */
100653   #define VPRCSR_NORDIC_INMODE_MODE2_Min (0x0UL)     /*!< Min enumerator value of MODE2 field.                                 */
100654   #define VPRCSR_NORDIC_INMODE_MODE2_Max (0x1UL)     /*!< Max enumerator value of MODE2 field.                                 */
100655   #define VPRCSR_NORDIC_INMODE_MODE2_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100656   #define VPRCSR_NORDIC_INMODE_MODE2_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100657 
100658 /* MODE3 @Bit 3 : Input Mode */
100659   #define VPRCSR_NORDIC_INMODE_MODE3_Pos (3UL)       /*!< Position of MODE3 field.                                             */
100660   #define VPRCSR_NORDIC_INMODE_MODE3_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE3_Pos) /*!< Bit mask of MODE3 field.               */
100661   #define VPRCSR_NORDIC_INMODE_MODE3_Min (0x0UL)     /*!< Min enumerator value of MODE3 field.                                 */
100662   #define VPRCSR_NORDIC_INMODE_MODE3_Max (0x1UL)     /*!< Max enumerator value of MODE3 field.                                 */
100663   #define VPRCSR_NORDIC_INMODE_MODE3_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100664   #define VPRCSR_NORDIC_INMODE_MODE3_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100665 
100666 /* MODE4 @Bit 4 : Input Mode */
100667   #define VPRCSR_NORDIC_INMODE_MODE4_Pos (4UL)       /*!< Position of MODE4 field.                                             */
100668   #define VPRCSR_NORDIC_INMODE_MODE4_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE4_Pos) /*!< Bit mask of MODE4 field.               */
100669   #define VPRCSR_NORDIC_INMODE_MODE4_Min (0x0UL)     /*!< Min enumerator value of MODE4 field.                                 */
100670   #define VPRCSR_NORDIC_INMODE_MODE4_Max (0x1UL)     /*!< Max enumerator value of MODE4 field.                                 */
100671   #define VPRCSR_NORDIC_INMODE_MODE4_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100672   #define VPRCSR_NORDIC_INMODE_MODE4_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100673 
100674 /* MODE5 @Bit 5 : Input Mode */
100675   #define VPRCSR_NORDIC_INMODE_MODE5_Pos (5UL)       /*!< Position of MODE5 field.                                             */
100676   #define VPRCSR_NORDIC_INMODE_MODE5_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE5_Pos) /*!< Bit mask of MODE5 field.               */
100677   #define VPRCSR_NORDIC_INMODE_MODE5_Min (0x0UL)     /*!< Min enumerator value of MODE5 field.                                 */
100678   #define VPRCSR_NORDIC_INMODE_MODE5_Max (0x1UL)     /*!< Max enumerator value of MODE5 field.                                 */
100679   #define VPRCSR_NORDIC_INMODE_MODE5_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100680   #define VPRCSR_NORDIC_INMODE_MODE5_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100681 
100682 /* MODE6 @Bit 6 : Input Mode */
100683   #define VPRCSR_NORDIC_INMODE_MODE6_Pos (6UL)       /*!< Position of MODE6 field.                                             */
100684   #define VPRCSR_NORDIC_INMODE_MODE6_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE6_Pos) /*!< Bit mask of MODE6 field.               */
100685   #define VPRCSR_NORDIC_INMODE_MODE6_Min (0x0UL)     /*!< Min enumerator value of MODE6 field.                                 */
100686   #define VPRCSR_NORDIC_INMODE_MODE6_Max (0x1UL)     /*!< Max enumerator value of MODE6 field.                                 */
100687   #define VPRCSR_NORDIC_INMODE_MODE6_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100688   #define VPRCSR_NORDIC_INMODE_MODE6_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100689 
100690 /* MODE7 @Bit 7 : Input Mode */
100691   #define VPRCSR_NORDIC_INMODE_MODE7_Pos (7UL)       /*!< Position of MODE7 field.                                             */
100692   #define VPRCSR_NORDIC_INMODE_MODE7_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE7_Pos) /*!< Bit mask of MODE7 field.               */
100693   #define VPRCSR_NORDIC_INMODE_MODE7_Min (0x0UL)     /*!< Min enumerator value of MODE7 field.                                 */
100694   #define VPRCSR_NORDIC_INMODE_MODE7_Max (0x1UL)     /*!< Max enumerator value of MODE7 field.                                 */
100695   #define VPRCSR_NORDIC_INMODE_MODE7_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100696   #define VPRCSR_NORDIC_INMODE_MODE7_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100697 
100698 /* MODE8 @Bit 8 : Input Mode */
100699   #define VPRCSR_NORDIC_INMODE_MODE8_Pos (8UL)       /*!< Position of MODE8 field.                                             */
100700   #define VPRCSR_NORDIC_INMODE_MODE8_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE8_Pos) /*!< Bit mask of MODE8 field.               */
100701   #define VPRCSR_NORDIC_INMODE_MODE8_Min (0x0UL)     /*!< Min enumerator value of MODE8 field.                                 */
100702   #define VPRCSR_NORDIC_INMODE_MODE8_Max (0x1UL)     /*!< Max enumerator value of MODE8 field.                                 */
100703   #define VPRCSR_NORDIC_INMODE_MODE8_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100704   #define VPRCSR_NORDIC_INMODE_MODE8_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100705 
100706 /* MODE9 @Bit 9 : Input Mode */
100707   #define VPRCSR_NORDIC_INMODE_MODE9_Pos (9UL)       /*!< Position of MODE9 field.                                             */
100708   #define VPRCSR_NORDIC_INMODE_MODE9_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE9_Pos) /*!< Bit mask of MODE9 field.               */
100709   #define VPRCSR_NORDIC_INMODE_MODE9_Min (0x0UL)     /*!< Min enumerator value of MODE9 field.                                 */
100710   #define VPRCSR_NORDIC_INMODE_MODE9_Max (0x1UL)     /*!< Max enumerator value of MODE9 field.                                 */
100711   #define VPRCSR_NORDIC_INMODE_MODE9_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                      */
100712   #define VPRCSR_NORDIC_INMODE_MODE9_EVENT (0x1UL)   /*!< Sampling on Counter1 event                                           */
100713 
100714 /* MODE10 @Bit 10 : Input Mode */
100715   #define VPRCSR_NORDIC_INMODE_MODE10_Pos (10UL)     /*!< Position of MODE10 field.                                            */
100716   #define VPRCSR_NORDIC_INMODE_MODE10_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE10_Pos) /*!< Bit mask of MODE10 field.            */
100717   #define VPRCSR_NORDIC_INMODE_MODE10_Min (0x0UL)    /*!< Min enumerator value of MODE10 field.                                */
100718   #define VPRCSR_NORDIC_INMODE_MODE10_Max (0x1UL)    /*!< Max enumerator value of MODE10 field.                                */
100719   #define VPRCSR_NORDIC_INMODE_MODE10_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                     */
100720   #define VPRCSR_NORDIC_INMODE_MODE10_EVENT (0x1UL)  /*!< Sampling on Counter1 event                                           */
100721 
100722 /* MODE11 @Bit 11 : Input Mode */
100723   #define VPRCSR_NORDIC_INMODE_MODE11_Pos (11UL)     /*!< Position of MODE11 field.                                            */
100724   #define VPRCSR_NORDIC_INMODE_MODE11_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE11_Pos) /*!< Bit mask of MODE11 field.            */
100725   #define VPRCSR_NORDIC_INMODE_MODE11_Min (0x0UL)    /*!< Min enumerator value of MODE11 field.                                */
100726   #define VPRCSR_NORDIC_INMODE_MODE11_Max (0x1UL)    /*!< Max enumerator value of MODE11 field.                                */
100727   #define VPRCSR_NORDIC_INMODE_MODE11_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                     */
100728   #define VPRCSR_NORDIC_INMODE_MODE11_EVENT (0x1UL)  /*!< Sampling on Counter1 event                                           */
100729 
100730 /* MODE12 @Bit 12 : Input Mode */
100731   #define VPRCSR_NORDIC_INMODE_MODE12_Pos (12UL)     /*!< Position of MODE12 field.                                            */
100732   #define VPRCSR_NORDIC_INMODE_MODE12_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE12_Pos) /*!< Bit mask of MODE12 field.            */
100733   #define VPRCSR_NORDIC_INMODE_MODE12_Min (0x0UL)    /*!< Min enumerator value of MODE12 field.                                */
100734   #define VPRCSR_NORDIC_INMODE_MODE12_Max (0x1UL)    /*!< Max enumerator value of MODE12 field.                                */
100735   #define VPRCSR_NORDIC_INMODE_MODE12_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                     */
100736   #define VPRCSR_NORDIC_INMODE_MODE12_EVENT (0x1UL)  /*!< Sampling on Counter1 event                                           */
100737 
100738 /* MODE13 @Bit 13 : Input Mode */
100739   #define VPRCSR_NORDIC_INMODE_MODE13_Pos (13UL)     /*!< Position of MODE13 field.                                            */
100740   #define VPRCSR_NORDIC_INMODE_MODE13_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE13_Pos) /*!< Bit mask of MODE13 field.            */
100741   #define VPRCSR_NORDIC_INMODE_MODE13_Min (0x0UL)    /*!< Min enumerator value of MODE13 field.                                */
100742   #define VPRCSR_NORDIC_INMODE_MODE13_Max (0x1UL)    /*!< Max enumerator value of MODE13 field.                                */
100743   #define VPRCSR_NORDIC_INMODE_MODE13_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                     */
100744   #define VPRCSR_NORDIC_INMODE_MODE13_EVENT (0x1UL)  /*!< Sampling on Counter1 event                                           */
100745 
100746 /* MODE14 @Bit 14 : Input Mode */
100747   #define VPRCSR_NORDIC_INMODE_MODE14_Pos (14UL)     /*!< Position of MODE14 field.                                            */
100748   #define VPRCSR_NORDIC_INMODE_MODE14_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE14_Pos) /*!< Bit mask of MODE14 field.            */
100749   #define VPRCSR_NORDIC_INMODE_MODE14_Min (0x0UL)    /*!< Min enumerator value of MODE14 field.                                */
100750   #define VPRCSR_NORDIC_INMODE_MODE14_Max (0x1UL)    /*!< Max enumerator value of MODE14 field.                                */
100751   #define VPRCSR_NORDIC_INMODE_MODE14_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                     */
100752   #define VPRCSR_NORDIC_INMODE_MODE14_EVENT (0x1UL)  /*!< Sampling on Counter1 event                                           */
100753 
100754 /* MODE15 @Bit 15 : Input Mode */
100755   #define VPRCSR_NORDIC_INMODE_MODE15_Pos (15UL)     /*!< Position of MODE15 field.                                            */
100756   #define VPRCSR_NORDIC_INMODE_MODE15_Msk (0x1UL << VPRCSR_NORDIC_INMODE_MODE15_Pos) /*!< Bit mask of MODE15 field.            */
100757   #define VPRCSR_NORDIC_INMODE_MODE15_Min (0x0UL)    /*!< Min enumerator value of MODE15 field.                                */
100758   #define VPRCSR_NORDIC_INMODE_MODE15_Max (0x1UL)    /*!< Max enumerator value of MODE15 field.                                */
100759   #define VPRCSR_NORDIC_INMODE_MODE15_CONTINUOUS (0x0UL) /*!< Continuous sampling (if CPU is not sleeping)                     */
100760   #define VPRCSR_NORDIC_INMODE_MODE15_EVENT (0x1UL)  /*!< Sampling on Counter1 event                                           */
100761 
100762 
100763 /**
100764   * @brief OUTB [VPRCSR_NORDIC_OUTB] Buffered GPIO Output
100765   */
100766   #define VPRCSR_NORDIC_OUTB (0x00000BC4ul)
100767   #define VPRCSR_NORDIC_OUTB_ResetValue (0x00000000UL) /*!< Reset value of OUTB register.                                      */
100768 
100769 /* PIN0 @Bit 0 : (unspecified) */
100770   #define VPRCSR_NORDIC_OUTB_PIN0_Pos (0UL)          /*!< Position of PIN0 field.                                              */
100771   #define VPRCSR_NORDIC_OUTB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN0_Pos) /*!< Bit mask of PIN0 field.                      */
100772   #define VPRCSR_NORDIC_OUTB_PIN0_Min (0x0UL)        /*!< Min enumerator value of PIN0 field.                                  */
100773   #define VPRCSR_NORDIC_OUTB_PIN0_Max (0x1UL)        /*!< Max enumerator value of PIN0 field.                                  */
100774   #define VPRCSR_NORDIC_OUTB_PIN0_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100775   #define VPRCSR_NORDIC_OUTB_PIN0_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100776 
100777 /* PIN1 @Bit 1 : (unspecified) */
100778   #define VPRCSR_NORDIC_OUTB_PIN1_Pos (1UL)          /*!< Position of PIN1 field.                                              */
100779   #define VPRCSR_NORDIC_OUTB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN1_Pos) /*!< Bit mask of PIN1 field.                      */
100780   #define VPRCSR_NORDIC_OUTB_PIN1_Min (0x0UL)        /*!< Min enumerator value of PIN1 field.                                  */
100781   #define VPRCSR_NORDIC_OUTB_PIN1_Max (0x1UL)        /*!< Max enumerator value of PIN1 field.                                  */
100782   #define VPRCSR_NORDIC_OUTB_PIN1_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100783   #define VPRCSR_NORDIC_OUTB_PIN1_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100784 
100785 /* PIN2 @Bit 2 : (unspecified) */
100786   #define VPRCSR_NORDIC_OUTB_PIN2_Pos (2UL)          /*!< Position of PIN2 field.                                              */
100787   #define VPRCSR_NORDIC_OUTB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN2_Pos) /*!< Bit mask of PIN2 field.                      */
100788   #define VPRCSR_NORDIC_OUTB_PIN2_Min (0x0UL)        /*!< Min enumerator value of PIN2 field.                                  */
100789   #define VPRCSR_NORDIC_OUTB_PIN2_Max (0x1UL)        /*!< Max enumerator value of PIN2 field.                                  */
100790   #define VPRCSR_NORDIC_OUTB_PIN2_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100791   #define VPRCSR_NORDIC_OUTB_PIN2_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100792 
100793 /* PIN3 @Bit 3 : (unspecified) */
100794   #define VPRCSR_NORDIC_OUTB_PIN3_Pos (3UL)          /*!< Position of PIN3 field.                                              */
100795   #define VPRCSR_NORDIC_OUTB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN3_Pos) /*!< Bit mask of PIN3 field.                      */
100796   #define VPRCSR_NORDIC_OUTB_PIN3_Min (0x0UL)        /*!< Min enumerator value of PIN3 field.                                  */
100797   #define VPRCSR_NORDIC_OUTB_PIN3_Max (0x1UL)        /*!< Max enumerator value of PIN3 field.                                  */
100798   #define VPRCSR_NORDIC_OUTB_PIN3_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100799   #define VPRCSR_NORDIC_OUTB_PIN3_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100800 
100801 /* PIN4 @Bit 4 : (unspecified) */
100802   #define VPRCSR_NORDIC_OUTB_PIN4_Pos (4UL)          /*!< Position of PIN4 field.                                              */
100803   #define VPRCSR_NORDIC_OUTB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN4_Pos) /*!< Bit mask of PIN4 field.                      */
100804   #define VPRCSR_NORDIC_OUTB_PIN4_Min (0x0UL)        /*!< Min enumerator value of PIN4 field.                                  */
100805   #define VPRCSR_NORDIC_OUTB_PIN4_Max (0x1UL)        /*!< Max enumerator value of PIN4 field.                                  */
100806   #define VPRCSR_NORDIC_OUTB_PIN4_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100807   #define VPRCSR_NORDIC_OUTB_PIN4_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100808 
100809 /* PIN5 @Bit 5 : (unspecified) */
100810   #define VPRCSR_NORDIC_OUTB_PIN5_Pos (5UL)          /*!< Position of PIN5 field.                                              */
100811   #define VPRCSR_NORDIC_OUTB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN5_Pos) /*!< Bit mask of PIN5 field.                      */
100812   #define VPRCSR_NORDIC_OUTB_PIN5_Min (0x0UL)        /*!< Min enumerator value of PIN5 field.                                  */
100813   #define VPRCSR_NORDIC_OUTB_PIN5_Max (0x1UL)        /*!< Max enumerator value of PIN5 field.                                  */
100814   #define VPRCSR_NORDIC_OUTB_PIN5_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100815   #define VPRCSR_NORDIC_OUTB_PIN5_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100816 
100817 /* PIN6 @Bit 6 : (unspecified) */
100818   #define VPRCSR_NORDIC_OUTB_PIN6_Pos (6UL)          /*!< Position of PIN6 field.                                              */
100819   #define VPRCSR_NORDIC_OUTB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN6_Pos) /*!< Bit mask of PIN6 field.                      */
100820   #define VPRCSR_NORDIC_OUTB_PIN6_Min (0x0UL)        /*!< Min enumerator value of PIN6 field.                                  */
100821   #define VPRCSR_NORDIC_OUTB_PIN6_Max (0x1UL)        /*!< Max enumerator value of PIN6 field.                                  */
100822   #define VPRCSR_NORDIC_OUTB_PIN6_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100823   #define VPRCSR_NORDIC_OUTB_PIN6_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100824 
100825 /* PIN7 @Bit 7 : (unspecified) */
100826   #define VPRCSR_NORDIC_OUTB_PIN7_Pos (7UL)          /*!< Position of PIN7 field.                                              */
100827   #define VPRCSR_NORDIC_OUTB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN7_Pos) /*!< Bit mask of PIN7 field.                      */
100828   #define VPRCSR_NORDIC_OUTB_PIN7_Min (0x0UL)        /*!< Min enumerator value of PIN7 field.                                  */
100829   #define VPRCSR_NORDIC_OUTB_PIN7_Max (0x1UL)        /*!< Max enumerator value of PIN7 field.                                  */
100830   #define VPRCSR_NORDIC_OUTB_PIN7_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100831   #define VPRCSR_NORDIC_OUTB_PIN7_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100832 
100833 /* PIN8 @Bit 8 : (unspecified) */
100834   #define VPRCSR_NORDIC_OUTB_PIN8_Pos (8UL)          /*!< Position of PIN8 field.                                              */
100835   #define VPRCSR_NORDIC_OUTB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN8_Pos) /*!< Bit mask of PIN8 field.                      */
100836   #define VPRCSR_NORDIC_OUTB_PIN8_Min (0x0UL)        /*!< Min enumerator value of PIN8 field.                                  */
100837   #define VPRCSR_NORDIC_OUTB_PIN8_Max (0x1UL)        /*!< Max enumerator value of PIN8 field.                                  */
100838   #define VPRCSR_NORDIC_OUTB_PIN8_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100839   #define VPRCSR_NORDIC_OUTB_PIN8_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100840 
100841 /* PIN9 @Bit 9 : (unspecified) */
100842   #define VPRCSR_NORDIC_OUTB_PIN9_Pos (9UL)          /*!< Position of PIN9 field.                                              */
100843   #define VPRCSR_NORDIC_OUTB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN9_Pos) /*!< Bit mask of PIN9 field.                      */
100844   #define VPRCSR_NORDIC_OUTB_PIN9_Min (0x0UL)        /*!< Min enumerator value of PIN9 field.                                  */
100845   #define VPRCSR_NORDIC_OUTB_PIN9_Max (0x1UL)        /*!< Max enumerator value of PIN9 field.                                  */
100846   #define VPRCSR_NORDIC_OUTB_PIN9_LOW (0x0UL)        /*!< Pin driver is low                                                    */
100847   #define VPRCSR_NORDIC_OUTB_PIN9_HIGH (0x1UL)       /*!< Pin driver is high                                                   */
100848 
100849 /* PIN10 @Bit 10 : (unspecified) */
100850   #define VPRCSR_NORDIC_OUTB_PIN10_Pos (10UL)        /*!< Position of PIN10 field.                                             */
100851   #define VPRCSR_NORDIC_OUTB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN10_Pos) /*!< Bit mask of PIN10 field.                   */
100852   #define VPRCSR_NORDIC_OUTB_PIN10_Min (0x0UL)       /*!< Min enumerator value of PIN10 field.                                 */
100853   #define VPRCSR_NORDIC_OUTB_PIN10_Max (0x1UL)       /*!< Max enumerator value of PIN10 field.                                 */
100854   #define VPRCSR_NORDIC_OUTB_PIN10_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100855   #define VPRCSR_NORDIC_OUTB_PIN10_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100856 
100857 /* PIN11 @Bit 11 : (unspecified) */
100858   #define VPRCSR_NORDIC_OUTB_PIN11_Pos (11UL)        /*!< Position of PIN11 field.                                             */
100859   #define VPRCSR_NORDIC_OUTB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN11_Pos) /*!< Bit mask of PIN11 field.                   */
100860   #define VPRCSR_NORDIC_OUTB_PIN11_Min (0x0UL)       /*!< Min enumerator value of PIN11 field.                                 */
100861   #define VPRCSR_NORDIC_OUTB_PIN11_Max (0x1UL)       /*!< Max enumerator value of PIN11 field.                                 */
100862   #define VPRCSR_NORDIC_OUTB_PIN11_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100863   #define VPRCSR_NORDIC_OUTB_PIN11_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100864 
100865 /* PIN12 @Bit 12 : (unspecified) */
100866   #define VPRCSR_NORDIC_OUTB_PIN12_Pos (12UL)        /*!< Position of PIN12 field.                                             */
100867   #define VPRCSR_NORDIC_OUTB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN12_Pos) /*!< Bit mask of PIN12 field.                   */
100868   #define VPRCSR_NORDIC_OUTB_PIN12_Min (0x0UL)       /*!< Min enumerator value of PIN12 field.                                 */
100869   #define VPRCSR_NORDIC_OUTB_PIN12_Max (0x1UL)       /*!< Max enumerator value of PIN12 field.                                 */
100870   #define VPRCSR_NORDIC_OUTB_PIN12_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100871   #define VPRCSR_NORDIC_OUTB_PIN12_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100872 
100873 /* PIN13 @Bit 13 : (unspecified) */
100874   #define VPRCSR_NORDIC_OUTB_PIN13_Pos (13UL)        /*!< Position of PIN13 field.                                             */
100875   #define VPRCSR_NORDIC_OUTB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN13_Pos) /*!< Bit mask of PIN13 field.                   */
100876   #define VPRCSR_NORDIC_OUTB_PIN13_Min (0x0UL)       /*!< Min enumerator value of PIN13 field.                                 */
100877   #define VPRCSR_NORDIC_OUTB_PIN13_Max (0x1UL)       /*!< Max enumerator value of PIN13 field.                                 */
100878   #define VPRCSR_NORDIC_OUTB_PIN13_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100879   #define VPRCSR_NORDIC_OUTB_PIN13_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100880 
100881 /* PIN14 @Bit 14 : (unspecified) */
100882   #define VPRCSR_NORDIC_OUTB_PIN14_Pos (14UL)        /*!< Position of PIN14 field.                                             */
100883   #define VPRCSR_NORDIC_OUTB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN14_Pos) /*!< Bit mask of PIN14 field.                   */
100884   #define VPRCSR_NORDIC_OUTB_PIN14_Min (0x0UL)       /*!< Min enumerator value of PIN14 field.                                 */
100885   #define VPRCSR_NORDIC_OUTB_PIN14_Max (0x1UL)       /*!< Max enumerator value of PIN14 field.                                 */
100886   #define VPRCSR_NORDIC_OUTB_PIN14_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100887   #define VPRCSR_NORDIC_OUTB_PIN14_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100888 
100889 /* PIN15 @Bit 15 : (unspecified) */
100890   #define VPRCSR_NORDIC_OUTB_PIN15_Pos (15UL)        /*!< Position of PIN15 field.                                             */
100891   #define VPRCSR_NORDIC_OUTB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN15_Pos) /*!< Bit mask of PIN15 field.                   */
100892   #define VPRCSR_NORDIC_OUTB_PIN15_Min (0x0UL)       /*!< Min enumerator value of PIN15 field.                                 */
100893   #define VPRCSR_NORDIC_OUTB_PIN15_Max (0x1UL)       /*!< Max enumerator value of PIN15 field.                                 */
100894   #define VPRCSR_NORDIC_OUTB_PIN15_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100895   #define VPRCSR_NORDIC_OUTB_PIN15_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100896 
100897 /* PIN16 @Bit 16 : (unspecified) */
100898   #define VPRCSR_NORDIC_OUTB_PIN16_Pos (16UL)        /*!< Position of PIN16 field.                                             */
100899   #define VPRCSR_NORDIC_OUTB_PIN16_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN16_Pos) /*!< Bit mask of PIN16 field.                   */
100900   #define VPRCSR_NORDIC_OUTB_PIN16_Min (0x0UL)       /*!< Min enumerator value of PIN16 field.                                 */
100901   #define VPRCSR_NORDIC_OUTB_PIN16_Max (0x1UL)       /*!< Max enumerator value of PIN16 field.                                 */
100902   #define VPRCSR_NORDIC_OUTB_PIN16_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100903   #define VPRCSR_NORDIC_OUTB_PIN16_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100904 
100905 /* PIN17 @Bit 17 : (unspecified) */
100906   #define VPRCSR_NORDIC_OUTB_PIN17_Pos (17UL)        /*!< Position of PIN17 field.                                             */
100907   #define VPRCSR_NORDIC_OUTB_PIN17_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN17_Pos) /*!< Bit mask of PIN17 field.                   */
100908   #define VPRCSR_NORDIC_OUTB_PIN17_Min (0x0UL)       /*!< Min enumerator value of PIN17 field.                                 */
100909   #define VPRCSR_NORDIC_OUTB_PIN17_Max (0x1UL)       /*!< Max enumerator value of PIN17 field.                                 */
100910   #define VPRCSR_NORDIC_OUTB_PIN17_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100911   #define VPRCSR_NORDIC_OUTB_PIN17_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100912 
100913 /* PIN18 @Bit 18 : (unspecified) */
100914   #define VPRCSR_NORDIC_OUTB_PIN18_Pos (18UL)        /*!< Position of PIN18 field.                                             */
100915   #define VPRCSR_NORDIC_OUTB_PIN18_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN18_Pos) /*!< Bit mask of PIN18 field.                   */
100916   #define VPRCSR_NORDIC_OUTB_PIN18_Min (0x0UL)       /*!< Min enumerator value of PIN18 field.                                 */
100917   #define VPRCSR_NORDIC_OUTB_PIN18_Max (0x1UL)       /*!< Max enumerator value of PIN18 field.                                 */
100918   #define VPRCSR_NORDIC_OUTB_PIN18_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100919   #define VPRCSR_NORDIC_OUTB_PIN18_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100920 
100921 /* PIN19 @Bit 19 : (unspecified) */
100922   #define VPRCSR_NORDIC_OUTB_PIN19_Pos (19UL)        /*!< Position of PIN19 field.                                             */
100923   #define VPRCSR_NORDIC_OUTB_PIN19_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN19_Pos) /*!< Bit mask of PIN19 field.                   */
100924   #define VPRCSR_NORDIC_OUTB_PIN19_Min (0x0UL)       /*!< Min enumerator value of PIN19 field.                                 */
100925   #define VPRCSR_NORDIC_OUTB_PIN19_Max (0x1UL)       /*!< Max enumerator value of PIN19 field.                                 */
100926   #define VPRCSR_NORDIC_OUTB_PIN19_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100927   #define VPRCSR_NORDIC_OUTB_PIN19_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100928 
100929 /* PIN20 @Bit 20 : (unspecified) */
100930   #define VPRCSR_NORDIC_OUTB_PIN20_Pos (20UL)        /*!< Position of PIN20 field.                                             */
100931   #define VPRCSR_NORDIC_OUTB_PIN20_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN20_Pos) /*!< Bit mask of PIN20 field.                   */
100932   #define VPRCSR_NORDIC_OUTB_PIN20_Min (0x0UL)       /*!< Min enumerator value of PIN20 field.                                 */
100933   #define VPRCSR_NORDIC_OUTB_PIN20_Max (0x1UL)       /*!< Max enumerator value of PIN20 field.                                 */
100934   #define VPRCSR_NORDIC_OUTB_PIN20_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100935   #define VPRCSR_NORDIC_OUTB_PIN20_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100936 
100937 /* PIN21 @Bit 21 : (unspecified) */
100938   #define VPRCSR_NORDIC_OUTB_PIN21_Pos (21UL)        /*!< Position of PIN21 field.                                             */
100939   #define VPRCSR_NORDIC_OUTB_PIN21_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN21_Pos) /*!< Bit mask of PIN21 field.                   */
100940   #define VPRCSR_NORDIC_OUTB_PIN21_Min (0x0UL)       /*!< Min enumerator value of PIN21 field.                                 */
100941   #define VPRCSR_NORDIC_OUTB_PIN21_Max (0x1UL)       /*!< Max enumerator value of PIN21 field.                                 */
100942   #define VPRCSR_NORDIC_OUTB_PIN21_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100943   #define VPRCSR_NORDIC_OUTB_PIN21_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100944 
100945 /* PIN22 @Bit 22 : (unspecified) */
100946   #define VPRCSR_NORDIC_OUTB_PIN22_Pos (22UL)        /*!< Position of PIN22 field.                                             */
100947   #define VPRCSR_NORDIC_OUTB_PIN22_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN22_Pos) /*!< Bit mask of PIN22 field.                   */
100948   #define VPRCSR_NORDIC_OUTB_PIN22_Min (0x0UL)       /*!< Min enumerator value of PIN22 field.                                 */
100949   #define VPRCSR_NORDIC_OUTB_PIN22_Max (0x1UL)       /*!< Max enumerator value of PIN22 field.                                 */
100950   #define VPRCSR_NORDIC_OUTB_PIN22_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100951   #define VPRCSR_NORDIC_OUTB_PIN22_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100952 
100953 /* PIN23 @Bit 23 : (unspecified) */
100954   #define VPRCSR_NORDIC_OUTB_PIN23_Pos (23UL)        /*!< Position of PIN23 field.                                             */
100955   #define VPRCSR_NORDIC_OUTB_PIN23_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN23_Pos) /*!< Bit mask of PIN23 field.                   */
100956   #define VPRCSR_NORDIC_OUTB_PIN23_Min (0x0UL)       /*!< Min enumerator value of PIN23 field.                                 */
100957   #define VPRCSR_NORDIC_OUTB_PIN23_Max (0x1UL)       /*!< Max enumerator value of PIN23 field.                                 */
100958   #define VPRCSR_NORDIC_OUTB_PIN23_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100959   #define VPRCSR_NORDIC_OUTB_PIN23_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100960 
100961 /* PIN24 @Bit 24 : (unspecified) */
100962   #define VPRCSR_NORDIC_OUTB_PIN24_Pos (24UL)        /*!< Position of PIN24 field.                                             */
100963   #define VPRCSR_NORDIC_OUTB_PIN24_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN24_Pos) /*!< Bit mask of PIN24 field.                   */
100964   #define VPRCSR_NORDIC_OUTB_PIN24_Min (0x0UL)       /*!< Min enumerator value of PIN24 field.                                 */
100965   #define VPRCSR_NORDIC_OUTB_PIN24_Max (0x1UL)       /*!< Max enumerator value of PIN24 field.                                 */
100966   #define VPRCSR_NORDIC_OUTB_PIN24_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100967   #define VPRCSR_NORDIC_OUTB_PIN24_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100968 
100969 /* PIN25 @Bit 25 : (unspecified) */
100970   #define VPRCSR_NORDIC_OUTB_PIN25_Pos (25UL)        /*!< Position of PIN25 field.                                             */
100971   #define VPRCSR_NORDIC_OUTB_PIN25_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN25_Pos) /*!< Bit mask of PIN25 field.                   */
100972   #define VPRCSR_NORDIC_OUTB_PIN25_Min (0x0UL)       /*!< Min enumerator value of PIN25 field.                                 */
100973   #define VPRCSR_NORDIC_OUTB_PIN25_Max (0x1UL)       /*!< Max enumerator value of PIN25 field.                                 */
100974   #define VPRCSR_NORDIC_OUTB_PIN25_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100975   #define VPRCSR_NORDIC_OUTB_PIN25_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100976 
100977 /* PIN26 @Bit 26 : (unspecified) */
100978   #define VPRCSR_NORDIC_OUTB_PIN26_Pos (26UL)        /*!< Position of PIN26 field.                                             */
100979   #define VPRCSR_NORDIC_OUTB_PIN26_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN26_Pos) /*!< Bit mask of PIN26 field.                   */
100980   #define VPRCSR_NORDIC_OUTB_PIN26_Min (0x0UL)       /*!< Min enumerator value of PIN26 field.                                 */
100981   #define VPRCSR_NORDIC_OUTB_PIN26_Max (0x1UL)       /*!< Max enumerator value of PIN26 field.                                 */
100982   #define VPRCSR_NORDIC_OUTB_PIN26_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100983   #define VPRCSR_NORDIC_OUTB_PIN26_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100984 
100985 /* PIN27 @Bit 27 : (unspecified) */
100986   #define VPRCSR_NORDIC_OUTB_PIN27_Pos (27UL)        /*!< Position of PIN27 field.                                             */
100987   #define VPRCSR_NORDIC_OUTB_PIN27_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN27_Pos) /*!< Bit mask of PIN27 field.                   */
100988   #define VPRCSR_NORDIC_OUTB_PIN27_Min (0x0UL)       /*!< Min enumerator value of PIN27 field.                                 */
100989   #define VPRCSR_NORDIC_OUTB_PIN27_Max (0x1UL)       /*!< Max enumerator value of PIN27 field.                                 */
100990   #define VPRCSR_NORDIC_OUTB_PIN27_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100991   #define VPRCSR_NORDIC_OUTB_PIN27_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
100992 
100993 /* PIN28 @Bit 28 : (unspecified) */
100994   #define VPRCSR_NORDIC_OUTB_PIN28_Pos (28UL)        /*!< Position of PIN28 field.                                             */
100995   #define VPRCSR_NORDIC_OUTB_PIN28_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN28_Pos) /*!< Bit mask of PIN28 field.                   */
100996   #define VPRCSR_NORDIC_OUTB_PIN28_Min (0x0UL)       /*!< Min enumerator value of PIN28 field.                                 */
100997   #define VPRCSR_NORDIC_OUTB_PIN28_Max (0x1UL)       /*!< Max enumerator value of PIN28 field.                                 */
100998   #define VPRCSR_NORDIC_OUTB_PIN28_LOW (0x0UL)       /*!< Pin driver is low                                                    */
100999   #define VPRCSR_NORDIC_OUTB_PIN28_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
101000 
101001 /* PIN29 @Bit 29 : (unspecified) */
101002   #define VPRCSR_NORDIC_OUTB_PIN29_Pos (29UL)        /*!< Position of PIN29 field.                                             */
101003   #define VPRCSR_NORDIC_OUTB_PIN29_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN29_Pos) /*!< Bit mask of PIN29 field.                   */
101004   #define VPRCSR_NORDIC_OUTB_PIN29_Min (0x0UL)       /*!< Min enumerator value of PIN29 field.                                 */
101005   #define VPRCSR_NORDIC_OUTB_PIN29_Max (0x1UL)       /*!< Max enumerator value of PIN29 field.                                 */
101006   #define VPRCSR_NORDIC_OUTB_PIN29_LOW (0x0UL)       /*!< Pin driver is low                                                    */
101007   #define VPRCSR_NORDIC_OUTB_PIN29_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
101008 
101009 /* PIN30 @Bit 30 : (unspecified) */
101010   #define VPRCSR_NORDIC_OUTB_PIN30_Pos (30UL)        /*!< Position of PIN30 field.                                             */
101011   #define VPRCSR_NORDIC_OUTB_PIN30_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN30_Pos) /*!< Bit mask of PIN30 field.                   */
101012   #define VPRCSR_NORDIC_OUTB_PIN30_Min (0x0UL)       /*!< Min enumerator value of PIN30 field.                                 */
101013   #define VPRCSR_NORDIC_OUTB_PIN30_Max (0x1UL)       /*!< Max enumerator value of PIN30 field.                                 */
101014   #define VPRCSR_NORDIC_OUTB_PIN30_LOW (0x0UL)       /*!< Pin driver is low                                                    */
101015   #define VPRCSR_NORDIC_OUTB_PIN30_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
101016 
101017 /* PIN31 @Bit 31 : (unspecified) */
101018   #define VPRCSR_NORDIC_OUTB_PIN31_Pos (31UL)        /*!< Position of PIN31 field.                                             */
101019   #define VPRCSR_NORDIC_OUTB_PIN31_Msk (0x1UL << VPRCSR_NORDIC_OUTB_PIN31_Pos) /*!< Bit mask of PIN31 field.                   */
101020   #define VPRCSR_NORDIC_OUTB_PIN31_Min (0x0UL)       /*!< Min enumerator value of PIN31 field.                                 */
101021   #define VPRCSR_NORDIC_OUTB_PIN31_Max (0x1UL)       /*!< Max enumerator value of PIN31 field.                                 */
101022   #define VPRCSR_NORDIC_OUTB_PIN31_LOW (0x0UL)       /*!< Pin driver is low                                                    */
101023   #define VPRCSR_NORDIC_OUTB_PIN31_HIGH (0x1UL)      /*!< Pin driver is high                                                   */
101024 
101025 
101026 /**
101027   * @brief DIRB [VPRCSR_NORDIC_DIRB] Buffered GPIO pin Direction
101028   */
101029   #define VPRCSR_NORDIC_DIRB (0x00000BC5ul)
101030   #define VPRCSR_NORDIC_DIRB_ResetValue (0x00000000UL) /*!< Reset value of DIRB register.                                      */
101031 
101032 /* PIN0 @Bit 0 : (unspecified) */
101033   #define VPRCSR_NORDIC_DIRB_PIN0_Pos (0UL)          /*!< Position of PIN0 field.                                              */
101034   #define VPRCSR_NORDIC_DIRB_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN0_Pos) /*!< Bit mask of PIN0 field.                      */
101035   #define VPRCSR_NORDIC_DIRB_PIN0_Min (0x0UL)        /*!< Min enumerator value of PIN0 field.                                  */
101036   #define VPRCSR_NORDIC_DIRB_PIN0_Max (0x1UL)        /*!< Max enumerator value of PIN0 field.                                  */
101037   #define VPRCSR_NORDIC_DIRB_PIN0_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101038   #define VPRCSR_NORDIC_DIRB_PIN0_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101039 
101040 /* PIN1 @Bit 1 : (unspecified) */
101041   #define VPRCSR_NORDIC_DIRB_PIN1_Pos (1UL)          /*!< Position of PIN1 field.                                              */
101042   #define VPRCSR_NORDIC_DIRB_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN1_Pos) /*!< Bit mask of PIN1 field.                      */
101043   #define VPRCSR_NORDIC_DIRB_PIN1_Min (0x0UL)        /*!< Min enumerator value of PIN1 field.                                  */
101044   #define VPRCSR_NORDIC_DIRB_PIN1_Max (0x1UL)        /*!< Max enumerator value of PIN1 field.                                  */
101045   #define VPRCSR_NORDIC_DIRB_PIN1_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101046   #define VPRCSR_NORDIC_DIRB_PIN1_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101047 
101048 /* PIN2 @Bit 2 : (unspecified) */
101049   #define VPRCSR_NORDIC_DIRB_PIN2_Pos (2UL)          /*!< Position of PIN2 field.                                              */
101050   #define VPRCSR_NORDIC_DIRB_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN2_Pos) /*!< Bit mask of PIN2 field.                      */
101051   #define VPRCSR_NORDIC_DIRB_PIN2_Min (0x0UL)        /*!< Min enumerator value of PIN2 field.                                  */
101052   #define VPRCSR_NORDIC_DIRB_PIN2_Max (0x1UL)        /*!< Max enumerator value of PIN2 field.                                  */
101053   #define VPRCSR_NORDIC_DIRB_PIN2_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101054   #define VPRCSR_NORDIC_DIRB_PIN2_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101055 
101056 /* PIN3 @Bit 3 : (unspecified) */
101057   #define VPRCSR_NORDIC_DIRB_PIN3_Pos (3UL)          /*!< Position of PIN3 field.                                              */
101058   #define VPRCSR_NORDIC_DIRB_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN3_Pos) /*!< Bit mask of PIN3 field.                      */
101059   #define VPRCSR_NORDIC_DIRB_PIN3_Min (0x0UL)        /*!< Min enumerator value of PIN3 field.                                  */
101060   #define VPRCSR_NORDIC_DIRB_PIN3_Max (0x1UL)        /*!< Max enumerator value of PIN3 field.                                  */
101061   #define VPRCSR_NORDIC_DIRB_PIN3_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101062   #define VPRCSR_NORDIC_DIRB_PIN3_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101063 
101064 /* PIN4 @Bit 4 : (unspecified) */
101065   #define VPRCSR_NORDIC_DIRB_PIN4_Pos (4UL)          /*!< Position of PIN4 field.                                              */
101066   #define VPRCSR_NORDIC_DIRB_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN4_Pos) /*!< Bit mask of PIN4 field.                      */
101067   #define VPRCSR_NORDIC_DIRB_PIN4_Min (0x0UL)        /*!< Min enumerator value of PIN4 field.                                  */
101068   #define VPRCSR_NORDIC_DIRB_PIN4_Max (0x1UL)        /*!< Max enumerator value of PIN4 field.                                  */
101069   #define VPRCSR_NORDIC_DIRB_PIN4_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101070   #define VPRCSR_NORDIC_DIRB_PIN4_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101071 
101072 /* PIN5 @Bit 5 : (unspecified) */
101073   #define VPRCSR_NORDIC_DIRB_PIN5_Pos (5UL)          /*!< Position of PIN5 field.                                              */
101074   #define VPRCSR_NORDIC_DIRB_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN5_Pos) /*!< Bit mask of PIN5 field.                      */
101075   #define VPRCSR_NORDIC_DIRB_PIN5_Min (0x0UL)        /*!< Min enumerator value of PIN5 field.                                  */
101076   #define VPRCSR_NORDIC_DIRB_PIN5_Max (0x1UL)        /*!< Max enumerator value of PIN5 field.                                  */
101077   #define VPRCSR_NORDIC_DIRB_PIN5_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101078   #define VPRCSR_NORDIC_DIRB_PIN5_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101079 
101080 /* PIN6 @Bit 6 : (unspecified) */
101081   #define VPRCSR_NORDIC_DIRB_PIN6_Pos (6UL)          /*!< Position of PIN6 field.                                              */
101082   #define VPRCSR_NORDIC_DIRB_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN6_Pos) /*!< Bit mask of PIN6 field.                      */
101083   #define VPRCSR_NORDIC_DIRB_PIN6_Min (0x0UL)        /*!< Min enumerator value of PIN6 field.                                  */
101084   #define VPRCSR_NORDIC_DIRB_PIN6_Max (0x1UL)        /*!< Max enumerator value of PIN6 field.                                  */
101085   #define VPRCSR_NORDIC_DIRB_PIN6_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101086   #define VPRCSR_NORDIC_DIRB_PIN6_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101087 
101088 /* PIN7 @Bit 7 : (unspecified) */
101089   #define VPRCSR_NORDIC_DIRB_PIN7_Pos (7UL)          /*!< Position of PIN7 field.                                              */
101090   #define VPRCSR_NORDIC_DIRB_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN7_Pos) /*!< Bit mask of PIN7 field.                      */
101091   #define VPRCSR_NORDIC_DIRB_PIN7_Min (0x0UL)        /*!< Min enumerator value of PIN7 field.                                  */
101092   #define VPRCSR_NORDIC_DIRB_PIN7_Max (0x1UL)        /*!< Max enumerator value of PIN7 field.                                  */
101093   #define VPRCSR_NORDIC_DIRB_PIN7_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101094   #define VPRCSR_NORDIC_DIRB_PIN7_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101095 
101096 /* PIN8 @Bit 8 : (unspecified) */
101097   #define VPRCSR_NORDIC_DIRB_PIN8_Pos (8UL)          /*!< Position of PIN8 field.                                              */
101098   #define VPRCSR_NORDIC_DIRB_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN8_Pos) /*!< Bit mask of PIN8 field.                      */
101099   #define VPRCSR_NORDIC_DIRB_PIN8_Min (0x0UL)        /*!< Min enumerator value of PIN8 field.                                  */
101100   #define VPRCSR_NORDIC_DIRB_PIN8_Max (0x1UL)        /*!< Max enumerator value of PIN8 field.                                  */
101101   #define VPRCSR_NORDIC_DIRB_PIN8_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101102   #define VPRCSR_NORDIC_DIRB_PIN8_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101103 
101104 /* PIN9 @Bit 9 : (unspecified) */
101105   #define VPRCSR_NORDIC_DIRB_PIN9_Pos (9UL)          /*!< Position of PIN9 field.                                              */
101106   #define VPRCSR_NORDIC_DIRB_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN9_Pos) /*!< Bit mask of PIN9 field.                      */
101107   #define VPRCSR_NORDIC_DIRB_PIN9_Min (0x0UL)        /*!< Min enumerator value of PIN9 field.                                  */
101108   #define VPRCSR_NORDIC_DIRB_PIN9_Max (0x1UL)        /*!< Max enumerator value of PIN9 field.                                  */
101109   #define VPRCSR_NORDIC_DIRB_PIN9_INPUT (0x0UL)      /*!< Pin is set as input                                                  */
101110   #define VPRCSR_NORDIC_DIRB_PIN9_OUTPUT (0x1UL)     /*!< Pin is set as output                                                 */
101111 
101112 /* PIN10 @Bit 10 : (unspecified) */
101113   #define VPRCSR_NORDIC_DIRB_PIN10_Pos (10UL)        /*!< Position of PIN10 field.                                             */
101114   #define VPRCSR_NORDIC_DIRB_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN10_Pos) /*!< Bit mask of PIN10 field.                   */
101115   #define VPRCSR_NORDIC_DIRB_PIN10_Min (0x0UL)       /*!< Min enumerator value of PIN10 field.                                 */
101116   #define VPRCSR_NORDIC_DIRB_PIN10_Max (0x1UL)       /*!< Max enumerator value of PIN10 field.                                 */
101117   #define VPRCSR_NORDIC_DIRB_PIN10_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
101118   #define VPRCSR_NORDIC_DIRB_PIN10_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */
101119 
101120 /* PIN11 @Bit 11 : (unspecified) */
101121   #define VPRCSR_NORDIC_DIRB_PIN11_Pos (11UL)        /*!< Position of PIN11 field.                                             */
101122   #define VPRCSR_NORDIC_DIRB_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN11_Pos) /*!< Bit mask of PIN11 field.                   */
101123   #define VPRCSR_NORDIC_DIRB_PIN11_Min (0x0UL)       /*!< Min enumerator value of PIN11 field.                                 */
101124   #define VPRCSR_NORDIC_DIRB_PIN11_Max (0x1UL)       /*!< Max enumerator value of PIN11 field.                                 */
101125   #define VPRCSR_NORDIC_DIRB_PIN11_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
101126   #define VPRCSR_NORDIC_DIRB_PIN11_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */
101127 
101128 /* PIN12 @Bit 12 : (unspecified) */
101129   #define VPRCSR_NORDIC_DIRB_PIN12_Pos (12UL)        /*!< Position of PIN12 field.                                             */
101130   #define VPRCSR_NORDIC_DIRB_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN12_Pos) /*!< Bit mask of PIN12 field.                   */
101131   #define VPRCSR_NORDIC_DIRB_PIN12_Min (0x0UL)       /*!< Min enumerator value of PIN12 field.                                 */
101132   #define VPRCSR_NORDIC_DIRB_PIN12_Max (0x1UL)       /*!< Max enumerator value of PIN12 field.                                 */
101133   #define VPRCSR_NORDIC_DIRB_PIN12_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
101134   #define VPRCSR_NORDIC_DIRB_PIN12_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */
101135 
101136 /* PIN13 @Bit 13 : (unspecified) */
101137   #define VPRCSR_NORDIC_DIRB_PIN13_Pos (13UL)        /*!< Position of PIN13 field.                                             */
101138   #define VPRCSR_NORDIC_DIRB_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN13_Pos) /*!< Bit mask of PIN13 field.                   */
101139   #define VPRCSR_NORDIC_DIRB_PIN13_Min (0x0UL)       /*!< Min enumerator value of PIN13 field.                                 */
101140   #define VPRCSR_NORDIC_DIRB_PIN13_Max (0x1UL)       /*!< Max enumerator value of PIN13 field.                                 */
101141   #define VPRCSR_NORDIC_DIRB_PIN13_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
101142   #define VPRCSR_NORDIC_DIRB_PIN13_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */
101143 
101144 /* PIN14 @Bit 14 : (unspecified) */
101145   #define VPRCSR_NORDIC_DIRB_PIN14_Pos (14UL)        /*!< Position of PIN14 field.                                             */
101146   #define VPRCSR_NORDIC_DIRB_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN14_Pos) /*!< Bit mask of PIN14 field.                   */
101147   #define VPRCSR_NORDIC_DIRB_PIN14_Min (0x0UL)       /*!< Min enumerator value of PIN14 field.                                 */
101148   #define VPRCSR_NORDIC_DIRB_PIN14_Max (0x1UL)       /*!< Max enumerator value of PIN14 field.                                 */
101149   #define VPRCSR_NORDIC_DIRB_PIN14_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
101150   #define VPRCSR_NORDIC_DIRB_PIN14_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */
101151 
101152 /* PIN15 @Bit 15 : (unspecified) */
101153   #define VPRCSR_NORDIC_DIRB_PIN15_Pos (15UL)        /*!< Position of PIN15 field.                                             */
101154   #define VPRCSR_NORDIC_DIRB_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRB_PIN15_Pos) /*!< Bit mask of PIN15 field.                   */
101155   #define VPRCSR_NORDIC_DIRB_PIN15_Min (0x0UL)       /*!< Min enumerator value of PIN15 field.                                 */
101156   #define VPRCSR_NORDIC_DIRB_PIN15_Max (0x1UL)       /*!< Max enumerator value of PIN15 field.                                 */
101157   #define VPRCSR_NORDIC_DIRB_PIN15_INPUT (0x0UL)     /*!< Pin is set as input                                                  */
101158   #define VPRCSR_NORDIC_DIRB_PIN15_OUTPUT (0x1UL)    /*!< Pin is set as output                                                 */
101159 
101160 
101161 /**
101162   * @brief DIROUT [VPRCSR_NORDIC_DIROUT] DIR and OUT concatenation
101163   */
101164   #define VPRCSR_NORDIC_DIROUT (0x00000BC6ul)
101165   #define VPRCSR_NORDIC_DIROUT_ResetValue (0x00000000UL) /*!< Reset value of DIROUT register.                                  */
101166 
101167 /* OUT @Bits 0..15 : GPIO Output */
101168   #define VPRCSR_NORDIC_DIROUT_OUT_Pos (0UL)         /*!< Position of OUT field.                                               */
101169   #define VPRCSR_NORDIC_DIROUT_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUT_OUT_Pos) /*!< Bit mask of OUT field.                  */
101170 
101171 /* DIR @Bits 16..31 : GPIO pin Direction */
101172   #define VPRCSR_NORDIC_DIROUT_DIR_Pos (16UL)        /*!< Position of DIR field.                                               */
101173   #define VPRCSR_NORDIC_DIROUT_DIR_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUT_DIR_Pos) /*!< Bit mask of DIR field.                  */
101174 
101175 
101176 /**
101177   * @brief DIROUTB [VPRCSR_NORDIC_DIROUTB] Concatenation of DIRB and OUTB
101178   */
101179   #define VPRCSR_NORDIC_DIROUTB (0x00000BC7ul)
101180   #define VPRCSR_NORDIC_DIROUTB_ResetValue (0x00000000UL) /*!< Reset value of DIROUTB register.                                */
101181 
101182 /* OUTB @Bits 0..15 : Buffered GPIO Output */
101183   #define VPRCSR_NORDIC_DIROUTB_OUTB_Pos (0UL)       /*!< Position of OUTB field.                                              */
101184   #define VPRCSR_NORDIC_DIROUTB_OUTB_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUTB_OUTB_Pos) /*!< Bit mask of OUTB field.             */
101185 
101186 /* DIRB @Bits 16..31 : Buffered GPIO pin Direction */
101187   #define VPRCSR_NORDIC_DIROUTB_DIRB_Pos (16UL)      /*!< Position of DIRB field.                                              */
101188   #define VPRCSR_NORDIC_DIROUTB_DIRB_Msk (0xFFFFUL << VPRCSR_NORDIC_DIROUTB_DIRB_Pos) /*!< Bit mask of DIRB field.             */
101189 
101190 
101191 /**
101192   * @brief OUTTGL [VPRCSR_NORDIC_OUTTGL] GPIO Output Toggle
101193   */
101194   #define VPRCSR_NORDIC_OUTTGL (0x00000BD0ul)
101195   #define VPRCSR_NORDIC_OUTTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTTGL register.                                  */
101196 
101197 /* PIN0 @Bit 0 : (unspecified) */
101198   #define VPRCSR_NORDIC_OUTTGL_PIN0_Pos (0UL)        /*!< Position of PIN0 field.                                              */
101199   #define VPRCSR_NORDIC_OUTTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN0_Pos) /*!< Bit mask of PIN0 field.                  */
101200   #define VPRCSR_NORDIC_OUTTGL_PIN0_Min (0x0UL)      /*!< Min enumerator value of PIN0 field.                                  */
101201   #define VPRCSR_NORDIC_OUTTGL_PIN0_Max (0x1UL)      /*!< Max enumerator value of PIN0 field.                                  */
101202   #define VPRCSR_NORDIC_OUTTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101203   #define VPRCSR_NORDIC_OUTTGL_PIN0_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101204 
101205 /* PIN1 @Bit 1 : (unspecified) */
101206   #define VPRCSR_NORDIC_OUTTGL_PIN1_Pos (1UL)        /*!< Position of PIN1 field.                                              */
101207   #define VPRCSR_NORDIC_OUTTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN1_Pos) /*!< Bit mask of PIN1 field.                  */
101208   #define VPRCSR_NORDIC_OUTTGL_PIN1_Min (0x0UL)      /*!< Min enumerator value of PIN1 field.                                  */
101209   #define VPRCSR_NORDIC_OUTTGL_PIN1_Max (0x1UL)      /*!< Max enumerator value of PIN1 field.                                  */
101210   #define VPRCSR_NORDIC_OUTTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101211   #define VPRCSR_NORDIC_OUTTGL_PIN1_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101212 
101213 /* PIN2 @Bit 2 : (unspecified) */
101214   #define VPRCSR_NORDIC_OUTTGL_PIN2_Pos (2UL)        /*!< Position of PIN2 field.                                              */
101215   #define VPRCSR_NORDIC_OUTTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN2_Pos) /*!< Bit mask of PIN2 field.                  */
101216   #define VPRCSR_NORDIC_OUTTGL_PIN2_Min (0x0UL)      /*!< Min enumerator value of PIN2 field.                                  */
101217   #define VPRCSR_NORDIC_OUTTGL_PIN2_Max (0x1UL)      /*!< Max enumerator value of PIN2 field.                                  */
101218   #define VPRCSR_NORDIC_OUTTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101219   #define VPRCSR_NORDIC_OUTTGL_PIN2_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101220 
101221 /* PIN3 @Bit 3 : (unspecified) */
101222   #define VPRCSR_NORDIC_OUTTGL_PIN3_Pos (3UL)        /*!< Position of PIN3 field.                                              */
101223   #define VPRCSR_NORDIC_OUTTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN3_Pos) /*!< Bit mask of PIN3 field.                  */
101224   #define VPRCSR_NORDIC_OUTTGL_PIN3_Min (0x0UL)      /*!< Min enumerator value of PIN3 field.                                  */
101225   #define VPRCSR_NORDIC_OUTTGL_PIN3_Max (0x1UL)      /*!< Max enumerator value of PIN3 field.                                  */
101226   #define VPRCSR_NORDIC_OUTTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101227   #define VPRCSR_NORDIC_OUTTGL_PIN3_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101228 
101229 /* PIN4 @Bit 4 : (unspecified) */
101230   #define VPRCSR_NORDIC_OUTTGL_PIN4_Pos (4UL)        /*!< Position of PIN4 field.                                              */
101231   #define VPRCSR_NORDIC_OUTTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN4_Pos) /*!< Bit mask of PIN4 field.                  */
101232   #define VPRCSR_NORDIC_OUTTGL_PIN4_Min (0x0UL)      /*!< Min enumerator value of PIN4 field.                                  */
101233   #define VPRCSR_NORDIC_OUTTGL_PIN4_Max (0x1UL)      /*!< Max enumerator value of PIN4 field.                                  */
101234   #define VPRCSR_NORDIC_OUTTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101235   #define VPRCSR_NORDIC_OUTTGL_PIN4_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101236 
101237 /* PIN5 @Bit 5 : (unspecified) */
101238   #define VPRCSR_NORDIC_OUTTGL_PIN5_Pos (5UL)        /*!< Position of PIN5 field.                                              */
101239   #define VPRCSR_NORDIC_OUTTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN5_Pos) /*!< Bit mask of PIN5 field.                  */
101240   #define VPRCSR_NORDIC_OUTTGL_PIN5_Min (0x0UL)      /*!< Min enumerator value of PIN5 field.                                  */
101241   #define VPRCSR_NORDIC_OUTTGL_PIN5_Max (0x1UL)      /*!< Max enumerator value of PIN5 field.                                  */
101242   #define VPRCSR_NORDIC_OUTTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101243   #define VPRCSR_NORDIC_OUTTGL_PIN5_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101244 
101245 /* PIN6 @Bit 6 : (unspecified) */
101246   #define VPRCSR_NORDIC_OUTTGL_PIN6_Pos (6UL)        /*!< Position of PIN6 field.                                              */
101247   #define VPRCSR_NORDIC_OUTTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN6_Pos) /*!< Bit mask of PIN6 field.                  */
101248   #define VPRCSR_NORDIC_OUTTGL_PIN6_Min (0x0UL)      /*!< Min enumerator value of PIN6 field.                                  */
101249   #define VPRCSR_NORDIC_OUTTGL_PIN6_Max (0x1UL)      /*!< Max enumerator value of PIN6 field.                                  */
101250   #define VPRCSR_NORDIC_OUTTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101251   #define VPRCSR_NORDIC_OUTTGL_PIN6_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101252 
101253 /* PIN7 @Bit 7 : (unspecified) */
101254   #define VPRCSR_NORDIC_OUTTGL_PIN7_Pos (7UL)        /*!< Position of PIN7 field.                                              */
101255   #define VPRCSR_NORDIC_OUTTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN7_Pos) /*!< Bit mask of PIN7 field.                  */
101256   #define VPRCSR_NORDIC_OUTTGL_PIN7_Min (0x0UL)      /*!< Min enumerator value of PIN7 field.                                  */
101257   #define VPRCSR_NORDIC_OUTTGL_PIN7_Max (0x1UL)      /*!< Max enumerator value of PIN7 field.                                  */
101258   #define VPRCSR_NORDIC_OUTTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101259   #define VPRCSR_NORDIC_OUTTGL_PIN7_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101260 
101261 /* PIN8 @Bit 8 : (unspecified) */
101262   #define VPRCSR_NORDIC_OUTTGL_PIN8_Pos (8UL)        /*!< Position of PIN8 field.                                              */
101263   #define VPRCSR_NORDIC_OUTTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN8_Pos) /*!< Bit mask of PIN8 field.                  */
101264   #define VPRCSR_NORDIC_OUTTGL_PIN8_Min (0x0UL)      /*!< Min enumerator value of PIN8 field.                                  */
101265   #define VPRCSR_NORDIC_OUTTGL_PIN8_Max (0x1UL)      /*!< Max enumerator value of PIN8 field.                                  */
101266   #define VPRCSR_NORDIC_OUTTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101267   #define VPRCSR_NORDIC_OUTTGL_PIN8_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101268 
101269 /* PIN9 @Bit 9 : (unspecified) */
101270   #define VPRCSR_NORDIC_OUTTGL_PIN9_Pos (9UL)        /*!< Position of PIN9 field.                                              */
101271   #define VPRCSR_NORDIC_OUTTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN9_Pos) /*!< Bit mask of PIN9 field.                  */
101272   #define VPRCSR_NORDIC_OUTTGL_PIN9_Min (0x0UL)      /*!< Min enumerator value of PIN9 field.                                  */
101273   #define VPRCSR_NORDIC_OUTTGL_PIN9_Max (0x1UL)      /*!< Max enumerator value of PIN9 field.                                  */
101274   #define VPRCSR_NORDIC_OUTTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101275   #define VPRCSR_NORDIC_OUTTGL_PIN9_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101276 
101277 /* PIN10 @Bit 10 : (unspecified) */
101278   #define VPRCSR_NORDIC_OUTTGL_PIN10_Pos (10UL)      /*!< Position of PIN10 field.                                             */
101279   #define VPRCSR_NORDIC_OUTTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN10_Pos) /*!< Bit mask of PIN10 field.               */
101280   #define VPRCSR_NORDIC_OUTTGL_PIN10_Min (0x0UL)     /*!< Min enumerator value of PIN10 field.                                 */
101281   #define VPRCSR_NORDIC_OUTTGL_PIN10_Max (0x1UL)     /*!< Max enumerator value of PIN10 field.                                 */
101282   #define VPRCSR_NORDIC_OUTTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101283   #define VPRCSR_NORDIC_OUTTGL_PIN10_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101284 
101285 /* PIN11 @Bit 11 : (unspecified) */
101286   #define VPRCSR_NORDIC_OUTTGL_PIN11_Pos (11UL)      /*!< Position of PIN11 field.                                             */
101287   #define VPRCSR_NORDIC_OUTTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN11_Pos) /*!< Bit mask of PIN11 field.               */
101288   #define VPRCSR_NORDIC_OUTTGL_PIN11_Min (0x0UL)     /*!< Min enumerator value of PIN11 field.                                 */
101289   #define VPRCSR_NORDIC_OUTTGL_PIN11_Max (0x1UL)     /*!< Max enumerator value of PIN11 field.                                 */
101290   #define VPRCSR_NORDIC_OUTTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101291   #define VPRCSR_NORDIC_OUTTGL_PIN11_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101292 
101293 /* PIN12 @Bit 12 : (unspecified) */
101294   #define VPRCSR_NORDIC_OUTTGL_PIN12_Pos (12UL)      /*!< Position of PIN12 field.                                             */
101295   #define VPRCSR_NORDIC_OUTTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN12_Pos) /*!< Bit mask of PIN12 field.               */
101296   #define VPRCSR_NORDIC_OUTTGL_PIN12_Min (0x0UL)     /*!< Min enumerator value of PIN12 field.                                 */
101297   #define VPRCSR_NORDIC_OUTTGL_PIN12_Max (0x1UL)     /*!< Max enumerator value of PIN12 field.                                 */
101298   #define VPRCSR_NORDIC_OUTTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101299   #define VPRCSR_NORDIC_OUTTGL_PIN12_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101300 
101301 /* PIN13 @Bit 13 : (unspecified) */
101302   #define VPRCSR_NORDIC_OUTTGL_PIN13_Pos (13UL)      /*!< Position of PIN13 field.                                             */
101303   #define VPRCSR_NORDIC_OUTTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN13_Pos) /*!< Bit mask of PIN13 field.               */
101304   #define VPRCSR_NORDIC_OUTTGL_PIN13_Min (0x0UL)     /*!< Min enumerator value of PIN13 field.                                 */
101305   #define VPRCSR_NORDIC_OUTTGL_PIN13_Max (0x1UL)     /*!< Max enumerator value of PIN13 field.                                 */
101306   #define VPRCSR_NORDIC_OUTTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101307   #define VPRCSR_NORDIC_OUTTGL_PIN13_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101308 
101309 /* PIN14 @Bit 14 : (unspecified) */
101310   #define VPRCSR_NORDIC_OUTTGL_PIN14_Pos (14UL)      /*!< Position of PIN14 field.                                             */
101311   #define VPRCSR_NORDIC_OUTTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN14_Pos) /*!< Bit mask of PIN14 field.               */
101312   #define VPRCSR_NORDIC_OUTTGL_PIN14_Min (0x0UL)     /*!< Min enumerator value of PIN14 field.                                 */
101313   #define VPRCSR_NORDIC_OUTTGL_PIN14_Max (0x1UL)     /*!< Max enumerator value of PIN14 field.                                 */
101314   #define VPRCSR_NORDIC_OUTTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101315   #define VPRCSR_NORDIC_OUTTGL_PIN14_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101316 
101317 /* PIN15 @Bit 15 : (unspecified) */
101318   #define VPRCSR_NORDIC_OUTTGL_PIN15_Pos (15UL)      /*!< Position of PIN15 field.                                             */
101319   #define VPRCSR_NORDIC_OUTTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTTGL_PIN15_Pos) /*!< Bit mask of PIN15 field.               */
101320   #define VPRCSR_NORDIC_OUTTGL_PIN15_Min (0x0UL)     /*!< Min enumerator value of PIN15 field.                                 */
101321   #define VPRCSR_NORDIC_OUTTGL_PIN15_Max (0x1UL)     /*!< Max enumerator value of PIN15 field.                                 */
101322   #define VPRCSR_NORDIC_OUTTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101323   #define VPRCSR_NORDIC_OUTTGL_PIN15_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101324 
101325 
101326 /**
101327   * @brief DIRTGL [VPRCSR_NORDIC_DIRTGL] GPIO pin Direction Toggle
101328   */
101329   #define VPRCSR_NORDIC_DIRTGL (0x00000BD1ul)
101330   #define VPRCSR_NORDIC_DIRTGL_ResetValue (0x00000000UL) /*!< Reset value of DIRTGL register.                                  */
101331 
101332 /* PIN0 @Bit 0 : (unspecified) */
101333   #define VPRCSR_NORDIC_DIRTGL_PIN0_Pos (0UL)        /*!< Position of PIN0 field.                                              */
101334   #define VPRCSR_NORDIC_DIRTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN0_Pos) /*!< Bit mask of PIN0 field.                  */
101335   #define VPRCSR_NORDIC_DIRTGL_PIN0_Min (0x0UL)      /*!< Min enumerator value of PIN0 field.                                  */
101336   #define VPRCSR_NORDIC_DIRTGL_PIN0_Max (0x1UL)      /*!< Max enumerator value of PIN0 field.                                  */
101337   #define VPRCSR_NORDIC_DIRTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101338   #define VPRCSR_NORDIC_DIRTGL_PIN0_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101339 
101340 /* PIN1 @Bit 1 : (unspecified) */
101341   #define VPRCSR_NORDIC_DIRTGL_PIN1_Pos (1UL)        /*!< Position of PIN1 field.                                              */
101342   #define VPRCSR_NORDIC_DIRTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN1_Pos) /*!< Bit mask of PIN1 field.                  */
101343   #define VPRCSR_NORDIC_DIRTGL_PIN1_Min (0x0UL)      /*!< Min enumerator value of PIN1 field.                                  */
101344   #define VPRCSR_NORDIC_DIRTGL_PIN1_Max (0x1UL)      /*!< Max enumerator value of PIN1 field.                                  */
101345   #define VPRCSR_NORDIC_DIRTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101346   #define VPRCSR_NORDIC_DIRTGL_PIN1_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101347 
101348 /* PIN2 @Bit 2 : (unspecified) */
101349   #define VPRCSR_NORDIC_DIRTGL_PIN2_Pos (2UL)        /*!< Position of PIN2 field.                                              */
101350   #define VPRCSR_NORDIC_DIRTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN2_Pos) /*!< Bit mask of PIN2 field.                  */
101351   #define VPRCSR_NORDIC_DIRTGL_PIN2_Min (0x0UL)      /*!< Min enumerator value of PIN2 field.                                  */
101352   #define VPRCSR_NORDIC_DIRTGL_PIN2_Max (0x1UL)      /*!< Max enumerator value of PIN2 field.                                  */
101353   #define VPRCSR_NORDIC_DIRTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101354   #define VPRCSR_NORDIC_DIRTGL_PIN2_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101355 
101356 /* PIN3 @Bit 3 : (unspecified) */
101357   #define VPRCSR_NORDIC_DIRTGL_PIN3_Pos (3UL)        /*!< Position of PIN3 field.                                              */
101358   #define VPRCSR_NORDIC_DIRTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN3_Pos) /*!< Bit mask of PIN3 field.                  */
101359   #define VPRCSR_NORDIC_DIRTGL_PIN3_Min (0x0UL)      /*!< Min enumerator value of PIN3 field.                                  */
101360   #define VPRCSR_NORDIC_DIRTGL_PIN3_Max (0x1UL)      /*!< Max enumerator value of PIN3 field.                                  */
101361   #define VPRCSR_NORDIC_DIRTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101362   #define VPRCSR_NORDIC_DIRTGL_PIN3_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101363 
101364 /* PIN4 @Bit 4 : (unspecified) */
101365   #define VPRCSR_NORDIC_DIRTGL_PIN4_Pos (4UL)        /*!< Position of PIN4 field.                                              */
101366   #define VPRCSR_NORDIC_DIRTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN4_Pos) /*!< Bit mask of PIN4 field.                  */
101367   #define VPRCSR_NORDIC_DIRTGL_PIN4_Min (0x0UL)      /*!< Min enumerator value of PIN4 field.                                  */
101368   #define VPRCSR_NORDIC_DIRTGL_PIN4_Max (0x1UL)      /*!< Max enumerator value of PIN4 field.                                  */
101369   #define VPRCSR_NORDIC_DIRTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101370   #define VPRCSR_NORDIC_DIRTGL_PIN4_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101371 
101372 /* PIN5 @Bit 5 : (unspecified) */
101373   #define VPRCSR_NORDIC_DIRTGL_PIN5_Pos (5UL)        /*!< Position of PIN5 field.                                              */
101374   #define VPRCSR_NORDIC_DIRTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN5_Pos) /*!< Bit mask of PIN5 field.                  */
101375   #define VPRCSR_NORDIC_DIRTGL_PIN5_Min (0x0UL)      /*!< Min enumerator value of PIN5 field.                                  */
101376   #define VPRCSR_NORDIC_DIRTGL_PIN5_Max (0x1UL)      /*!< Max enumerator value of PIN5 field.                                  */
101377   #define VPRCSR_NORDIC_DIRTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101378   #define VPRCSR_NORDIC_DIRTGL_PIN5_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101379 
101380 /* PIN6 @Bit 6 : (unspecified) */
101381   #define VPRCSR_NORDIC_DIRTGL_PIN6_Pos (6UL)        /*!< Position of PIN6 field.                                              */
101382   #define VPRCSR_NORDIC_DIRTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN6_Pos) /*!< Bit mask of PIN6 field.                  */
101383   #define VPRCSR_NORDIC_DIRTGL_PIN6_Min (0x0UL)      /*!< Min enumerator value of PIN6 field.                                  */
101384   #define VPRCSR_NORDIC_DIRTGL_PIN6_Max (0x1UL)      /*!< Max enumerator value of PIN6 field.                                  */
101385   #define VPRCSR_NORDIC_DIRTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101386   #define VPRCSR_NORDIC_DIRTGL_PIN6_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101387 
101388 /* PIN7 @Bit 7 : (unspecified) */
101389   #define VPRCSR_NORDIC_DIRTGL_PIN7_Pos (7UL)        /*!< Position of PIN7 field.                                              */
101390   #define VPRCSR_NORDIC_DIRTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN7_Pos) /*!< Bit mask of PIN7 field.                  */
101391   #define VPRCSR_NORDIC_DIRTGL_PIN7_Min (0x0UL)      /*!< Min enumerator value of PIN7 field.                                  */
101392   #define VPRCSR_NORDIC_DIRTGL_PIN7_Max (0x1UL)      /*!< Max enumerator value of PIN7 field.                                  */
101393   #define VPRCSR_NORDIC_DIRTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101394   #define VPRCSR_NORDIC_DIRTGL_PIN7_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101395 
101396 /* PIN8 @Bit 8 : (unspecified) */
101397   #define VPRCSR_NORDIC_DIRTGL_PIN8_Pos (8UL)        /*!< Position of PIN8 field.                                              */
101398   #define VPRCSR_NORDIC_DIRTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN8_Pos) /*!< Bit mask of PIN8 field.                  */
101399   #define VPRCSR_NORDIC_DIRTGL_PIN8_Min (0x0UL)      /*!< Min enumerator value of PIN8 field.                                  */
101400   #define VPRCSR_NORDIC_DIRTGL_PIN8_Max (0x1UL)      /*!< Max enumerator value of PIN8 field.                                  */
101401   #define VPRCSR_NORDIC_DIRTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101402   #define VPRCSR_NORDIC_DIRTGL_PIN8_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101403 
101404 /* PIN9 @Bit 9 : (unspecified) */
101405   #define VPRCSR_NORDIC_DIRTGL_PIN9_Pos (9UL)        /*!< Position of PIN9 field.                                              */
101406   #define VPRCSR_NORDIC_DIRTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN9_Pos) /*!< Bit mask of PIN9 field.                  */
101407   #define VPRCSR_NORDIC_DIRTGL_PIN9_Min (0x0UL)      /*!< Min enumerator value of PIN9 field.                                  */
101408   #define VPRCSR_NORDIC_DIRTGL_PIN9_Max (0x1UL)      /*!< Max enumerator value of PIN9 field.                                  */
101409   #define VPRCSR_NORDIC_DIRTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                               */
101410   #define VPRCSR_NORDIC_DIRTGL_PIN9_TOGGLE (0x1UL)   /*!< Pin is toggled                                                       */
101411 
101412 /* PIN10 @Bit 10 : (unspecified) */
101413   #define VPRCSR_NORDIC_DIRTGL_PIN10_Pos (10UL)      /*!< Position of PIN10 field.                                             */
101414   #define VPRCSR_NORDIC_DIRTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN10_Pos) /*!< Bit mask of PIN10 field.               */
101415   #define VPRCSR_NORDIC_DIRTGL_PIN10_Min (0x0UL)     /*!< Min enumerator value of PIN10 field.                                 */
101416   #define VPRCSR_NORDIC_DIRTGL_PIN10_Max (0x1UL)     /*!< Max enumerator value of PIN10 field.                                 */
101417   #define VPRCSR_NORDIC_DIRTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101418   #define VPRCSR_NORDIC_DIRTGL_PIN10_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101419 
101420 /* PIN11 @Bit 11 : (unspecified) */
101421   #define VPRCSR_NORDIC_DIRTGL_PIN11_Pos (11UL)      /*!< Position of PIN11 field.                                             */
101422   #define VPRCSR_NORDIC_DIRTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN11_Pos) /*!< Bit mask of PIN11 field.               */
101423   #define VPRCSR_NORDIC_DIRTGL_PIN11_Min (0x0UL)     /*!< Min enumerator value of PIN11 field.                                 */
101424   #define VPRCSR_NORDIC_DIRTGL_PIN11_Max (0x1UL)     /*!< Max enumerator value of PIN11 field.                                 */
101425   #define VPRCSR_NORDIC_DIRTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101426   #define VPRCSR_NORDIC_DIRTGL_PIN11_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101427 
101428 /* PIN12 @Bit 12 : (unspecified) */
101429   #define VPRCSR_NORDIC_DIRTGL_PIN12_Pos (12UL)      /*!< Position of PIN12 field.                                             */
101430   #define VPRCSR_NORDIC_DIRTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN12_Pos) /*!< Bit mask of PIN12 field.               */
101431   #define VPRCSR_NORDIC_DIRTGL_PIN12_Min (0x0UL)     /*!< Min enumerator value of PIN12 field.                                 */
101432   #define VPRCSR_NORDIC_DIRTGL_PIN12_Max (0x1UL)     /*!< Max enumerator value of PIN12 field.                                 */
101433   #define VPRCSR_NORDIC_DIRTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101434   #define VPRCSR_NORDIC_DIRTGL_PIN12_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101435 
101436 /* PIN13 @Bit 13 : (unspecified) */
101437   #define VPRCSR_NORDIC_DIRTGL_PIN13_Pos (13UL)      /*!< Position of PIN13 field.                                             */
101438   #define VPRCSR_NORDIC_DIRTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN13_Pos) /*!< Bit mask of PIN13 field.               */
101439   #define VPRCSR_NORDIC_DIRTGL_PIN13_Min (0x0UL)     /*!< Min enumerator value of PIN13 field.                                 */
101440   #define VPRCSR_NORDIC_DIRTGL_PIN13_Max (0x1UL)     /*!< Max enumerator value of PIN13 field.                                 */
101441   #define VPRCSR_NORDIC_DIRTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101442   #define VPRCSR_NORDIC_DIRTGL_PIN13_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101443 
101444 /* PIN14 @Bit 14 : (unspecified) */
101445   #define VPRCSR_NORDIC_DIRTGL_PIN14_Pos (14UL)      /*!< Position of PIN14 field.                                             */
101446   #define VPRCSR_NORDIC_DIRTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN14_Pos) /*!< Bit mask of PIN14 field.               */
101447   #define VPRCSR_NORDIC_DIRTGL_PIN14_Min (0x0UL)     /*!< Min enumerator value of PIN14 field.                                 */
101448   #define VPRCSR_NORDIC_DIRTGL_PIN14_Max (0x1UL)     /*!< Max enumerator value of PIN14 field.                                 */
101449   #define VPRCSR_NORDIC_DIRTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101450   #define VPRCSR_NORDIC_DIRTGL_PIN14_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101451 
101452 /* PIN15 @Bit 15 : (unspecified) */
101453   #define VPRCSR_NORDIC_DIRTGL_PIN15_Pos (15UL)      /*!< Position of PIN15 field.                                             */
101454   #define VPRCSR_NORDIC_DIRTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRTGL_PIN15_Pos) /*!< Bit mask of PIN15 field.               */
101455   #define VPRCSR_NORDIC_DIRTGL_PIN15_Min (0x0UL)     /*!< Min enumerator value of PIN15 field.                                 */
101456   #define VPRCSR_NORDIC_DIRTGL_PIN15_Max (0x1UL)     /*!< Max enumerator value of PIN15 field.                                 */
101457   #define VPRCSR_NORDIC_DIRTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101458   #define VPRCSR_NORDIC_DIRTGL_PIN15_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101459 
101460 
101461 /**
101462   * @brief OUTBTGL [VPRCSR_NORDIC_OUTBTGL] Buffered GPIO Output Toggle
101463   */
101464   #define VPRCSR_NORDIC_OUTBTGL (0x00000BD2ul)
101465   #define VPRCSR_NORDIC_OUTBTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTBTGL register.                                */
101466 
101467 /* PIN0 @Bit 0 : (unspecified) */
101468   #define VPRCSR_NORDIC_OUTBTGL_PIN0_Pos (0UL)       /*!< Position of PIN0 field.                                              */
101469   #define VPRCSR_NORDIC_OUTBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field.                */
101470   #define VPRCSR_NORDIC_OUTBTGL_PIN0_Min (0x0UL)     /*!< Min enumerator value of PIN0 field.                                  */
101471   #define VPRCSR_NORDIC_OUTBTGL_PIN0_Max (0x1UL)     /*!< Max enumerator value of PIN0 field.                                  */
101472   #define VPRCSR_NORDIC_OUTBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101473   #define VPRCSR_NORDIC_OUTBTGL_PIN0_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101474 
101475 /* PIN1 @Bit 1 : (unspecified) */
101476   #define VPRCSR_NORDIC_OUTBTGL_PIN1_Pos (1UL)       /*!< Position of PIN1 field.                                              */
101477   #define VPRCSR_NORDIC_OUTBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field.                */
101478   #define VPRCSR_NORDIC_OUTBTGL_PIN1_Min (0x0UL)     /*!< Min enumerator value of PIN1 field.                                  */
101479   #define VPRCSR_NORDIC_OUTBTGL_PIN1_Max (0x1UL)     /*!< Max enumerator value of PIN1 field.                                  */
101480   #define VPRCSR_NORDIC_OUTBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101481   #define VPRCSR_NORDIC_OUTBTGL_PIN1_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101482 
101483 /* PIN2 @Bit 2 : (unspecified) */
101484   #define VPRCSR_NORDIC_OUTBTGL_PIN2_Pos (2UL)       /*!< Position of PIN2 field.                                              */
101485   #define VPRCSR_NORDIC_OUTBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field.                */
101486   #define VPRCSR_NORDIC_OUTBTGL_PIN2_Min (0x0UL)     /*!< Min enumerator value of PIN2 field.                                  */
101487   #define VPRCSR_NORDIC_OUTBTGL_PIN2_Max (0x1UL)     /*!< Max enumerator value of PIN2 field.                                  */
101488   #define VPRCSR_NORDIC_OUTBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101489   #define VPRCSR_NORDIC_OUTBTGL_PIN2_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101490 
101491 /* PIN3 @Bit 3 : (unspecified) */
101492   #define VPRCSR_NORDIC_OUTBTGL_PIN3_Pos (3UL)       /*!< Position of PIN3 field.                                              */
101493   #define VPRCSR_NORDIC_OUTBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field.                */
101494   #define VPRCSR_NORDIC_OUTBTGL_PIN3_Min (0x0UL)     /*!< Min enumerator value of PIN3 field.                                  */
101495   #define VPRCSR_NORDIC_OUTBTGL_PIN3_Max (0x1UL)     /*!< Max enumerator value of PIN3 field.                                  */
101496   #define VPRCSR_NORDIC_OUTBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101497   #define VPRCSR_NORDIC_OUTBTGL_PIN3_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101498 
101499 /* PIN4 @Bit 4 : (unspecified) */
101500   #define VPRCSR_NORDIC_OUTBTGL_PIN4_Pos (4UL)       /*!< Position of PIN4 field.                                              */
101501   #define VPRCSR_NORDIC_OUTBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field.                */
101502   #define VPRCSR_NORDIC_OUTBTGL_PIN4_Min (0x0UL)     /*!< Min enumerator value of PIN4 field.                                  */
101503   #define VPRCSR_NORDIC_OUTBTGL_PIN4_Max (0x1UL)     /*!< Max enumerator value of PIN4 field.                                  */
101504   #define VPRCSR_NORDIC_OUTBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101505   #define VPRCSR_NORDIC_OUTBTGL_PIN4_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101506 
101507 /* PIN5 @Bit 5 : (unspecified) */
101508   #define VPRCSR_NORDIC_OUTBTGL_PIN5_Pos (5UL)       /*!< Position of PIN5 field.                                              */
101509   #define VPRCSR_NORDIC_OUTBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field.                */
101510   #define VPRCSR_NORDIC_OUTBTGL_PIN5_Min (0x0UL)     /*!< Min enumerator value of PIN5 field.                                  */
101511   #define VPRCSR_NORDIC_OUTBTGL_PIN5_Max (0x1UL)     /*!< Max enumerator value of PIN5 field.                                  */
101512   #define VPRCSR_NORDIC_OUTBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101513   #define VPRCSR_NORDIC_OUTBTGL_PIN5_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101514 
101515 /* PIN6 @Bit 6 : (unspecified) */
101516   #define VPRCSR_NORDIC_OUTBTGL_PIN6_Pos (6UL)       /*!< Position of PIN6 field.                                              */
101517   #define VPRCSR_NORDIC_OUTBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field.                */
101518   #define VPRCSR_NORDIC_OUTBTGL_PIN6_Min (0x0UL)     /*!< Min enumerator value of PIN6 field.                                  */
101519   #define VPRCSR_NORDIC_OUTBTGL_PIN6_Max (0x1UL)     /*!< Max enumerator value of PIN6 field.                                  */
101520   #define VPRCSR_NORDIC_OUTBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101521   #define VPRCSR_NORDIC_OUTBTGL_PIN6_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101522 
101523 /* PIN7 @Bit 7 : (unspecified) */
101524   #define VPRCSR_NORDIC_OUTBTGL_PIN7_Pos (7UL)       /*!< Position of PIN7 field.                                              */
101525   #define VPRCSR_NORDIC_OUTBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field.                */
101526   #define VPRCSR_NORDIC_OUTBTGL_PIN7_Min (0x0UL)     /*!< Min enumerator value of PIN7 field.                                  */
101527   #define VPRCSR_NORDIC_OUTBTGL_PIN7_Max (0x1UL)     /*!< Max enumerator value of PIN7 field.                                  */
101528   #define VPRCSR_NORDIC_OUTBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101529   #define VPRCSR_NORDIC_OUTBTGL_PIN7_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101530 
101531 /* PIN8 @Bit 8 : (unspecified) */
101532   #define VPRCSR_NORDIC_OUTBTGL_PIN8_Pos (8UL)       /*!< Position of PIN8 field.                                              */
101533   #define VPRCSR_NORDIC_OUTBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field.                */
101534   #define VPRCSR_NORDIC_OUTBTGL_PIN8_Min (0x0UL)     /*!< Min enumerator value of PIN8 field.                                  */
101535   #define VPRCSR_NORDIC_OUTBTGL_PIN8_Max (0x1UL)     /*!< Max enumerator value of PIN8 field.                                  */
101536   #define VPRCSR_NORDIC_OUTBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101537   #define VPRCSR_NORDIC_OUTBTGL_PIN8_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101538 
101539 /* PIN9 @Bit 9 : (unspecified) */
101540   #define VPRCSR_NORDIC_OUTBTGL_PIN9_Pos (9UL)       /*!< Position of PIN9 field.                                              */
101541   #define VPRCSR_NORDIC_OUTBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field.                */
101542   #define VPRCSR_NORDIC_OUTBTGL_PIN9_Min (0x0UL)     /*!< Min enumerator value of PIN9 field.                                  */
101543   #define VPRCSR_NORDIC_OUTBTGL_PIN9_Max (0x1UL)     /*!< Max enumerator value of PIN9 field.                                  */
101544   #define VPRCSR_NORDIC_OUTBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101545   #define VPRCSR_NORDIC_OUTBTGL_PIN9_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101546 
101547 /* PIN10 @Bit 10 : (unspecified) */
101548   #define VPRCSR_NORDIC_OUTBTGL_PIN10_Pos (10UL)     /*!< Position of PIN10 field.                                             */
101549   #define VPRCSR_NORDIC_OUTBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field.             */
101550   #define VPRCSR_NORDIC_OUTBTGL_PIN10_Min (0x0UL)    /*!< Min enumerator value of PIN10 field.                                 */
101551   #define VPRCSR_NORDIC_OUTBTGL_PIN10_Max (0x1UL)    /*!< Max enumerator value of PIN10 field.                                 */
101552   #define VPRCSR_NORDIC_OUTBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101553   #define VPRCSR_NORDIC_OUTBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101554 
101555 /* PIN11 @Bit 11 : (unspecified) */
101556   #define VPRCSR_NORDIC_OUTBTGL_PIN11_Pos (11UL)     /*!< Position of PIN11 field.                                             */
101557   #define VPRCSR_NORDIC_OUTBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field.             */
101558   #define VPRCSR_NORDIC_OUTBTGL_PIN11_Min (0x0UL)    /*!< Min enumerator value of PIN11 field.                                 */
101559   #define VPRCSR_NORDIC_OUTBTGL_PIN11_Max (0x1UL)    /*!< Max enumerator value of PIN11 field.                                 */
101560   #define VPRCSR_NORDIC_OUTBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101561   #define VPRCSR_NORDIC_OUTBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101562 
101563 /* PIN12 @Bit 12 : (unspecified) */
101564   #define VPRCSR_NORDIC_OUTBTGL_PIN12_Pos (12UL)     /*!< Position of PIN12 field.                                             */
101565   #define VPRCSR_NORDIC_OUTBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field.             */
101566   #define VPRCSR_NORDIC_OUTBTGL_PIN12_Min (0x0UL)    /*!< Min enumerator value of PIN12 field.                                 */
101567   #define VPRCSR_NORDIC_OUTBTGL_PIN12_Max (0x1UL)    /*!< Max enumerator value of PIN12 field.                                 */
101568   #define VPRCSR_NORDIC_OUTBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101569   #define VPRCSR_NORDIC_OUTBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101570 
101571 /* PIN13 @Bit 13 : (unspecified) */
101572   #define VPRCSR_NORDIC_OUTBTGL_PIN13_Pos (13UL)     /*!< Position of PIN13 field.                                             */
101573   #define VPRCSR_NORDIC_OUTBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field.             */
101574   #define VPRCSR_NORDIC_OUTBTGL_PIN13_Min (0x0UL)    /*!< Min enumerator value of PIN13 field.                                 */
101575   #define VPRCSR_NORDIC_OUTBTGL_PIN13_Max (0x1UL)    /*!< Max enumerator value of PIN13 field.                                 */
101576   #define VPRCSR_NORDIC_OUTBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101577   #define VPRCSR_NORDIC_OUTBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101578 
101579 /* PIN14 @Bit 14 : (unspecified) */
101580   #define VPRCSR_NORDIC_OUTBTGL_PIN14_Pos (14UL)     /*!< Position of PIN14 field.                                             */
101581   #define VPRCSR_NORDIC_OUTBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field.             */
101582   #define VPRCSR_NORDIC_OUTBTGL_PIN14_Min (0x0UL)    /*!< Min enumerator value of PIN14 field.                                 */
101583   #define VPRCSR_NORDIC_OUTBTGL_PIN14_Max (0x1UL)    /*!< Max enumerator value of PIN14 field.                                 */
101584   #define VPRCSR_NORDIC_OUTBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101585   #define VPRCSR_NORDIC_OUTBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101586 
101587 /* PIN15 @Bit 15 : (unspecified) */
101588   #define VPRCSR_NORDIC_OUTBTGL_PIN15_Pos (15UL)     /*!< Position of PIN15 field.                                             */
101589   #define VPRCSR_NORDIC_OUTBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_OUTBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field.             */
101590   #define VPRCSR_NORDIC_OUTBTGL_PIN15_Min (0x0UL)    /*!< Min enumerator value of PIN15 field.                                 */
101591   #define VPRCSR_NORDIC_OUTBTGL_PIN15_Max (0x1UL)    /*!< Max enumerator value of PIN15 field.                                 */
101592   #define VPRCSR_NORDIC_OUTBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101593   #define VPRCSR_NORDIC_OUTBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101594 
101595 
101596 /**
101597   * @brief DIRBTGL [VPRCSR_NORDIC_DIRBTGL] Buffered GPIO pin Direction Toggle
101598   */
101599   #define VPRCSR_NORDIC_DIRBTGL (0x00000BD3ul)
101600   #define VPRCSR_NORDIC_DIRBTGL_ResetValue (0x00000000UL) /*!< Reset value of DIRBTGL register.                                */
101601 
101602 /* PIN0 @Bit 0 : (unspecified) */
101603   #define VPRCSR_NORDIC_DIRBTGL_PIN0_Pos (0UL)       /*!< Position of PIN0 field.                                              */
101604   #define VPRCSR_NORDIC_DIRBTGL_PIN0_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN0_Pos) /*!< Bit mask of PIN0 field.                */
101605   #define VPRCSR_NORDIC_DIRBTGL_PIN0_Min (0x0UL)     /*!< Min enumerator value of PIN0 field.                                  */
101606   #define VPRCSR_NORDIC_DIRBTGL_PIN0_Max (0x1UL)     /*!< Max enumerator value of PIN0 field.                                  */
101607   #define VPRCSR_NORDIC_DIRBTGL_PIN0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101608   #define VPRCSR_NORDIC_DIRBTGL_PIN0_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101609 
101610 /* PIN1 @Bit 1 : (unspecified) */
101611   #define VPRCSR_NORDIC_DIRBTGL_PIN1_Pos (1UL)       /*!< Position of PIN1 field.                                              */
101612   #define VPRCSR_NORDIC_DIRBTGL_PIN1_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN1_Pos) /*!< Bit mask of PIN1 field.                */
101613   #define VPRCSR_NORDIC_DIRBTGL_PIN1_Min (0x0UL)     /*!< Min enumerator value of PIN1 field.                                  */
101614   #define VPRCSR_NORDIC_DIRBTGL_PIN1_Max (0x1UL)     /*!< Max enumerator value of PIN1 field.                                  */
101615   #define VPRCSR_NORDIC_DIRBTGL_PIN1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101616   #define VPRCSR_NORDIC_DIRBTGL_PIN1_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101617 
101618 /* PIN2 @Bit 2 : (unspecified) */
101619   #define VPRCSR_NORDIC_DIRBTGL_PIN2_Pos (2UL)       /*!< Position of PIN2 field.                                              */
101620   #define VPRCSR_NORDIC_DIRBTGL_PIN2_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN2_Pos) /*!< Bit mask of PIN2 field.                */
101621   #define VPRCSR_NORDIC_DIRBTGL_PIN2_Min (0x0UL)     /*!< Min enumerator value of PIN2 field.                                  */
101622   #define VPRCSR_NORDIC_DIRBTGL_PIN2_Max (0x1UL)     /*!< Max enumerator value of PIN2 field.                                  */
101623   #define VPRCSR_NORDIC_DIRBTGL_PIN2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101624   #define VPRCSR_NORDIC_DIRBTGL_PIN2_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101625 
101626 /* PIN3 @Bit 3 : (unspecified) */
101627   #define VPRCSR_NORDIC_DIRBTGL_PIN3_Pos (3UL)       /*!< Position of PIN3 field.                                              */
101628   #define VPRCSR_NORDIC_DIRBTGL_PIN3_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN3_Pos) /*!< Bit mask of PIN3 field.                */
101629   #define VPRCSR_NORDIC_DIRBTGL_PIN3_Min (0x0UL)     /*!< Min enumerator value of PIN3 field.                                  */
101630   #define VPRCSR_NORDIC_DIRBTGL_PIN3_Max (0x1UL)     /*!< Max enumerator value of PIN3 field.                                  */
101631   #define VPRCSR_NORDIC_DIRBTGL_PIN3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101632   #define VPRCSR_NORDIC_DIRBTGL_PIN3_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101633 
101634 /* PIN4 @Bit 4 : (unspecified) */
101635   #define VPRCSR_NORDIC_DIRBTGL_PIN4_Pos (4UL)       /*!< Position of PIN4 field.                                              */
101636   #define VPRCSR_NORDIC_DIRBTGL_PIN4_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN4_Pos) /*!< Bit mask of PIN4 field.                */
101637   #define VPRCSR_NORDIC_DIRBTGL_PIN4_Min (0x0UL)     /*!< Min enumerator value of PIN4 field.                                  */
101638   #define VPRCSR_NORDIC_DIRBTGL_PIN4_Max (0x1UL)     /*!< Max enumerator value of PIN4 field.                                  */
101639   #define VPRCSR_NORDIC_DIRBTGL_PIN4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101640   #define VPRCSR_NORDIC_DIRBTGL_PIN4_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101641 
101642 /* PIN5 @Bit 5 : (unspecified) */
101643   #define VPRCSR_NORDIC_DIRBTGL_PIN5_Pos (5UL)       /*!< Position of PIN5 field.                                              */
101644   #define VPRCSR_NORDIC_DIRBTGL_PIN5_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN5_Pos) /*!< Bit mask of PIN5 field.                */
101645   #define VPRCSR_NORDIC_DIRBTGL_PIN5_Min (0x0UL)     /*!< Min enumerator value of PIN5 field.                                  */
101646   #define VPRCSR_NORDIC_DIRBTGL_PIN5_Max (0x1UL)     /*!< Max enumerator value of PIN5 field.                                  */
101647   #define VPRCSR_NORDIC_DIRBTGL_PIN5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101648   #define VPRCSR_NORDIC_DIRBTGL_PIN5_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101649 
101650 /* PIN6 @Bit 6 : (unspecified) */
101651   #define VPRCSR_NORDIC_DIRBTGL_PIN6_Pos (6UL)       /*!< Position of PIN6 field.                                              */
101652   #define VPRCSR_NORDIC_DIRBTGL_PIN6_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN6_Pos) /*!< Bit mask of PIN6 field.                */
101653   #define VPRCSR_NORDIC_DIRBTGL_PIN6_Min (0x0UL)     /*!< Min enumerator value of PIN6 field.                                  */
101654   #define VPRCSR_NORDIC_DIRBTGL_PIN6_Max (0x1UL)     /*!< Max enumerator value of PIN6 field.                                  */
101655   #define VPRCSR_NORDIC_DIRBTGL_PIN6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101656   #define VPRCSR_NORDIC_DIRBTGL_PIN6_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101657 
101658 /* PIN7 @Bit 7 : (unspecified) */
101659   #define VPRCSR_NORDIC_DIRBTGL_PIN7_Pos (7UL)       /*!< Position of PIN7 field.                                              */
101660   #define VPRCSR_NORDIC_DIRBTGL_PIN7_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN7_Pos) /*!< Bit mask of PIN7 field.                */
101661   #define VPRCSR_NORDIC_DIRBTGL_PIN7_Min (0x0UL)     /*!< Min enumerator value of PIN7 field.                                  */
101662   #define VPRCSR_NORDIC_DIRBTGL_PIN7_Max (0x1UL)     /*!< Max enumerator value of PIN7 field.                                  */
101663   #define VPRCSR_NORDIC_DIRBTGL_PIN7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101664   #define VPRCSR_NORDIC_DIRBTGL_PIN7_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101665 
101666 /* PIN8 @Bit 8 : (unspecified) */
101667   #define VPRCSR_NORDIC_DIRBTGL_PIN8_Pos (8UL)       /*!< Position of PIN8 field.                                              */
101668   #define VPRCSR_NORDIC_DIRBTGL_PIN8_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN8_Pos) /*!< Bit mask of PIN8 field.                */
101669   #define VPRCSR_NORDIC_DIRBTGL_PIN8_Min (0x0UL)     /*!< Min enumerator value of PIN8 field.                                  */
101670   #define VPRCSR_NORDIC_DIRBTGL_PIN8_Max (0x1UL)     /*!< Max enumerator value of PIN8 field.                                  */
101671   #define VPRCSR_NORDIC_DIRBTGL_PIN8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101672   #define VPRCSR_NORDIC_DIRBTGL_PIN8_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101673 
101674 /* PIN9 @Bit 9 : (unspecified) */
101675   #define VPRCSR_NORDIC_DIRBTGL_PIN9_Pos (9UL)       /*!< Position of PIN9 field.                                              */
101676   #define VPRCSR_NORDIC_DIRBTGL_PIN9_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN9_Pos) /*!< Bit mask of PIN9 field.                */
101677   #define VPRCSR_NORDIC_DIRBTGL_PIN9_Min (0x0UL)     /*!< Min enumerator value of PIN9 field.                                  */
101678   #define VPRCSR_NORDIC_DIRBTGL_PIN9_Max (0x1UL)     /*!< Max enumerator value of PIN9 field.                                  */
101679   #define VPRCSR_NORDIC_DIRBTGL_PIN9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                              */
101680   #define VPRCSR_NORDIC_DIRBTGL_PIN9_TOGGLE (0x1UL)  /*!< Pin is toggled                                                       */
101681 
101682 /* PIN10 @Bit 10 : (unspecified) */
101683   #define VPRCSR_NORDIC_DIRBTGL_PIN10_Pos (10UL)     /*!< Position of PIN10 field.                                             */
101684   #define VPRCSR_NORDIC_DIRBTGL_PIN10_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN10_Pos) /*!< Bit mask of PIN10 field.             */
101685   #define VPRCSR_NORDIC_DIRBTGL_PIN10_Min (0x0UL)    /*!< Min enumerator value of PIN10 field.                                 */
101686   #define VPRCSR_NORDIC_DIRBTGL_PIN10_Max (0x1UL)    /*!< Max enumerator value of PIN10 field.                                 */
101687   #define VPRCSR_NORDIC_DIRBTGL_PIN10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101688   #define VPRCSR_NORDIC_DIRBTGL_PIN10_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101689 
101690 /* PIN11 @Bit 11 : (unspecified) */
101691   #define VPRCSR_NORDIC_DIRBTGL_PIN11_Pos (11UL)     /*!< Position of PIN11 field.                                             */
101692   #define VPRCSR_NORDIC_DIRBTGL_PIN11_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN11_Pos) /*!< Bit mask of PIN11 field.             */
101693   #define VPRCSR_NORDIC_DIRBTGL_PIN11_Min (0x0UL)    /*!< Min enumerator value of PIN11 field.                                 */
101694   #define VPRCSR_NORDIC_DIRBTGL_PIN11_Max (0x1UL)    /*!< Max enumerator value of PIN11 field.                                 */
101695   #define VPRCSR_NORDIC_DIRBTGL_PIN11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101696   #define VPRCSR_NORDIC_DIRBTGL_PIN11_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101697 
101698 /* PIN12 @Bit 12 : (unspecified) */
101699   #define VPRCSR_NORDIC_DIRBTGL_PIN12_Pos (12UL)     /*!< Position of PIN12 field.                                             */
101700   #define VPRCSR_NORDIC_DIRBTGL_PIN12_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN12_Pos) /*!< Bit mask of PIN12 field.             */
101701   #define VPRCSR_NORDIC_DIRBTGL_PIN12_Min (0x0UL)    /*!< Min enumerator value of PIN12 field.                                 */
101702   #define VPRCSR_NORDIC_DIRBTGL_PIN12_Max (0x1UL)    /*!< Max enumerator value of PIN12 field.                                 */
101703   #define VPRCSR_NORDIC_DIRBTGL_PIN12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101704   #define VPRCSR_NORDIC_DIRBTGL_PIN12_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101705 
101706 /* PIN13 @Bit 13 : (unspecified) */
101707   #define VPRCSR_NORDIC_DIRBTGL_PIN13_Pos (13UL)     /*!< Position of PIN13 field.                                             */
101708   #define VPRCSR_NORDIC_DIRBTGL_PIN13_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN13_Pos) /*!< Bit mask of PIN13 field.             */
101709   #define VPRCSR_NORDIC_DIRBTGL_PIN13_Min (0x0UL)    /*!< Min enumerator value of PIN13 field.                                 */
101710   #define VPRCSR_NORDIC_DIRBTGL_PIN13_Max (0x1UL)    /*!< Max enumerator value of PIN13 field.                                 */
101711   #define VPRCSR_NORDIC_DIRBTGL_PIN13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101712   #define VPRCSR_NORDIC_DIRBTGL_PIN13_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101713 
101714 /* PIN14 @Bit 14 : (unspecified) */
101715   #define VPRCSR_NORDIC_DIRBTGL_PIN14_Pos (14UL)     /*!< Position of PIN14 field.                                             */
101716   #define VPRCSR_NORDIC_DIRBTGL_PIN14_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN14_Pos) /*!< Bit mask of PIN14 field.             */
101717   #define VPRCSR_NORDIC_DIRBTGL_PIN14_Min (0x0UL)    /*!< Min enumerator value of PIN14 field.                                 */
101718   #define VPRCSR_NORDIC_DIRBTGL_PIN14_Max (0x1UL)    /*!< Max enumerator value of PIN14 field.                                 */
101719   #define VPRCSR_NORDIC_DIRBTGL_PIN14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101720   #define VPRCSR_NORDIC_DIRBTGL_PIN14_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101721 
101722 /* PIN15 @Bit 15 : (unspecified) */
101723   #define VPRCSR_NORDIC_DIRBTGL_PIN15_Pos (15UL)     /*!< Position of PIN15 field.                                             */
101724   #define VPRCSR_NORDIC_DIRBTGL_PIN15_Msk (0x1UL << VPRCSR_NORDIC_DIRBTGL_PIN15_Pos) /*!< Bit mask of PIN15 field.             */
101725   #define VPRCSR_NORDIC_DIRBTGL_PIN15_Min (0x0UL)    /*!< Min enumerator value of PIN15 field.                                 */
101726   #define VPRCSR_NORDIC_DIRBTGL_PIN15_Max (0x1UL)    /*!< Max enumerator value of PIN15 field.                                 */
101727   #define VPRCSR_NORDIC_DIRBTGL_PIN15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
101728   #define VPRCSR_NORDIC_DIRBTGL_PIN15_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
101729 
101730 
101731 /**
101732   * @brief DIROUTTGL [VPRCSR_NORDIC_DIROUTTGL] DIROUT Toggle
101733   */
101734   #define VPRCSR_NORDIC_DIROUTTGL (0x00000BD4ul)
101735   #define VPRCSR_NORDIC_DIROUTTGL_ResetValue (0x00000000UL) /*!< Reset value of DIROUTTGL register.                            */
101736 
101737 /* OUT0 @Bit 0 : (unspecified) */
101738   #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Pos (0UL)     /*!< Position of OUT0 field.                                              */
101739   #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT0_Pos) /*!< Bit mask of OUT0 field.            */
101740   #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Min (0x0UL)   /*!< Min enumerator value of OUT0 field.                                  */
101741   #define VPRCSR_NORDIC_DIROUTTGL_OUT0_Max (0x1UL)   /*!< Max enumerator value of OUT0 field.                                  */
101742   #define VPRCSR_NORDIC_DIROUTTGL_OUT0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101743   #define VPRCSR_NORDIC_DIROUTTGL_OUT0_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101744 
101745 /* OUT1 @Bit 1 : (unspecified) */
101746   #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Pos (1UL)     /*!< Position of OUT1 field.                                              */
101747   #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT1_Pos) /*!< Bit mask of OUT1 field.            */
101748   #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Min (0x0UL)   /*!< Min enumerator value of OUT1 field.                                  */
101749   #define VPRCSR_NORDIC_DIROUTTGL_OUT1_Max (0x1UL)   /*!< Max enumerator value of OUT1 field.                                  */
101750   #define VPRCSR_NORDIC_DIROUTTGL_OUT1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101751   #define VPRCSR_NORDIC_DIROUTTGL_OUT1_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101752 
101753 /* OUT2 @Bit 2 : (unspecified) */
101754   #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Pos (2UL)     /*!< Position of OUT2 field.                                              */
101755   #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT2_Pos) /*!< Bit mask of OUT2 field.            */
101756   #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Min (0x0UL)   /*!< Min enumerator value of OUT2 field.                                  */
101757   #define VPRCSR_NORDIC_DIROUTTGL_OUT2_Max (0x1UL)   /*!< Max enumerator value of OUT2 field.                                  */
101758   #define VPRCSR_NORDIC_DIROUTTGL_OUT2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101759   #define VPRCSR_NORDIC_DIROUTTGL_OUT2_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101760 
101761 /* OUT3 @Bit 3 : (unspecified) */
101762   #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Pos (3UL)     /*!< Position of OUT3 field.                                              */
101763   #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT3_Pos) /*!< Bit mask of OUT3 field.            */
101764   #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Min (0x0UL)   /*!< Min enumerator value of OUT3 field.                                  */
101765   #define VPRCSR_NORDIC_DIROUTTGL_OUT3_Max (0x1UL)   /*!< Max enumerator value of OUT3 field.                                  */
101766   #define VPRCSR_NORDIC_DIROUTTGL_OUT3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101767   #define VPRCSR_NORDIC_DIROUTTGL_OUT3_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101768 
101769 /* OUT4 @Bit 4 : (unspecified) */
101770   #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Pos (4UL)     /*!< Position of OUT4 field.                                              */
101771   #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT4_Pos) /*!< Bit mask of OUT4 field.            */
101772   #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Min (0x0UL)   /*!< Min enumerator value of OUT4 field.                                  */
101773   #define VPRCSR_NORDIC_DIROUTTGL_OUT4_Max (0x1UL)   /*!< Max enumerator value of OUT4 field.                                  */
101774   #define VPRCSR_NORDIC_DIROUTTGL_OUT4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101775   #define VPRCSR_NORDIC_DIROUTTGL_OUT4_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101776 
101777 /* OUT5 @Bit 5 : (unspecified) */
101778   #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Pos (5UL)     /*!< Position of OUT5 field.                                              */
101779   #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT5_Pos) /*!< Bit mask of OUT5 field.            */
101780   #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Min (0x0UL)   /*!< Min enumerator value of OUT5 field.                                  */
101781   #define VPRCSR_NORDIC_DIROUTTGL_OUT5_Max (0x1UL)   /*!< Max enumerator value of OUT5 field.                                  */
101782   #define VPRCSR_NORDIC_DIROUTTGL_OUT5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101783   #define VPRCSR_NORDIC_DIROUTTGL_OUT5_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101784 
101785 /* OUT6 @Bit 6 : (unspecified) */
101786   #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Pos (6UL)     /*!< Position of OUT6 field.                                              */
101787   #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT6_Pos) /*!< Bit mask of OUT6 field.            */
101788   #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Min (0x0UL)   /*!< Min enumerator value of OUT6 field.                                  */
101789   #define VPRCSR_NORDIC_DIROUTTGL_OUT6_Max (0x1UL)   /*!< Max enumerator value of OUT6 field.                                  */
101790   #define VPRCSR_NORDIC_DIROUTTGL_OUT6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101791   #define VPRCSR_NORDIC_DIROUTTGL_OUT6_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101792 
101793 /* OUT7 @Bit 7 : (unspecified) */
101794   #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Pos (7UL)     /*!< Position of OUT7 field.                                              */
101795   #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT7_Pos) /*!< Bit mask of OUT7 field.            */
101796   #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Min (0x0UL)   /*!< Min enumerator value of OUT7 field.                                  */
101797   #define VPRCSR_NORDIC_DIROUTTGL_OUT7_Max (0x1UL)   /*!< Max enumerator value of OUT7 field.                                  */
101798   #define VPRCSR_NORDIC_DIROUTTGL_OUT7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101799   #define VPRCSR_NORDIC_DIROUTTGL_OUT7_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101800 
101801 /* OUT8 @Bit 8 : (unspecified) */
101802   #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Pos (8UL)     /*!< Position of OUT8 field.                                              */
101803   #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT8_Pos) /*!< Bit mask of OUT8 field.            */
101804   #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Min (0x0UL)   /*!< Min enumerator value of OUT8 field.                                  */
101805   #define VPRCSR_NORDIC_DIROUTTGL_OUT8_Max (0x1UL)   /*!< Max enumerator value of OUT8 field.                                  */
101806   #define VPRCSR_NORDIC_DIROUTTGL_OUT8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101807   #define VPRCSR_NORDIC_DIROUTTGL_OUT8_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101808 
101809 /* OUT9 @Bit 9 : (unspecified) */
101810   #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Pos (9UL)     /*!< Position of OUT9 field.                                              */
101811   #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT9_Pos) /*!< Bit mask of OUT9 field.            */
101812   #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Min (0x0UL)   /*!< Min enumerator value of OUT9 field.                                  */
101813   #define VPRCSR_NORDIC_DIROUTTGL_OUT9_Max (0x1UL)   /*!< Max enumerator value of OUT9 field.                                  */
101814   #define VPRCSR_NORDIC_DIROUTTGL_OUT9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101815   #define VPRCSR_NORDIC_DIROUTTGL_OUT9_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101816 
101817 /* OUT10 @Bit 10 : (unspecified) */
101818   #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Pos (10UL)   /*!< Position of OUT10 field.                                             */
101819   #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT10_Pos) /*!< Bit mask of OUT10 field.         */
101820   #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Min (0x0UL)  /*!< Min enumerator value of OUT10 field.                                 */
101821   #define VPRCSR_NORDIC_DIROUTTGL_OUT10_Max (0x1UL)  /*!< Max enumerator value of OUT10 field.                                 */
101822   #define VPRCSR_NORDIC_DIROUTTGL_OUT10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101823   #define VPRCSR_NORDIC_DIROUTTGL_OUT10_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101824 
101825 /* OUT11 @Bit 11 : (unspecified) */
101826   #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Pos (11UL)   /*!< Position of OUT11 field.                                             */
101827   #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT11_Pos) /*!< Bit mask of OUT11 field.         */
101828   #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Min (0x0UL)  /*!< Min enumerator value of OUT11 field.                                 */
101829   #define VPRCSR_NORDIC_DIROUTTGL_OUT11_Max (0x1UL)  /*!< Max enumerator value of OUT11 field.                                 */
101830   #define VPRCSR_NORDIC_DIROUTTGL_OUT11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101831   #define VPRCSR_NORDIC_DIROUTTGL_OUT11_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101832 
101833 /* OUT12 @Bit 12 : (unspecified) */
101834   #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Pos (12UL)   /*!< Position of OUT12 field.                                             */
101835   #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT12_Pos) /*!< Bit mask of OUT12 field.         */
101836   #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Min (0x0UL)  /*!< Min enumerator value of OUT12 field.                                 */
101837   #define VPRCSR_NORDIC_DIROUTTGL_OUT12_Max (0x1UL)  /*!< Max enumerator value of OUT12 field.                                 */
101838   #define VPRCSR_NORDIC_DIROUTTGL_OUT12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101839   #define VPRCSR_NORDIC_DIROUTTGL_OUT12_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101840 
101841 /* OUT13 @Bit 13 : (unspecified) */
101842   #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Pos (13UL)   /*!< Position of OUT13 field.                                             */
101843   #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT13_Pos) /*!< Bit mask of OUT13 field.         */
101844   #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Min (0x0UL)  /*!< Min enumerator value of OUT13 field.                                 */
101845   #define VPRCSR_NORDIC_DIROUTTGL_OUT13_Max (0x1UL)  /*!< Max enumerator value of OUT13 field.                                 */
101846   #define VPRCSR_NORDIC_DIROUTTGL_OUT13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101847   #define VPRCSR_NORDIC_DIROUTTGL_OUT13_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101848 
101849 /* OUT14 @Bit 14 : (unspecified) */
101850   #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Pos (14UL)   /*!< Position of OUT14 field.                                             */
101851   #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT14_Pos) /*!< Bit mask of OUT14 field.         */
101852   #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Min (0x0UL)  /*!< Min enumerator value of OUT14 field.                                 */
101853   #define VPRCSR_NORDIC_DIROUTTGL_OUT14_Max (0x1UL)  /*!< Max enumerator value of OUT14 field.                                 */
101854   #define VPRCSR_NORDIC_DIROUTTGL_OUT14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101855   #define VPRCSR_NORDIC_DIROUTTGL_OUT14_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101856 
101857 /* OUT15 @Bit 15 : (unspecified) */
101858   #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Pos (15UL)   /*!< Position of OUT15 field.                                             */
101859   #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_OUT15_Pos) /*!< Bit mask of OUT15 field.         */
101860   #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Min (0x0UL)  /*!< Min enumerator value of OUT15 field.                                 */
101861   #define VPRCSR_NORDIC_DIROUTTGL_OUT15_Max (0x1UL)  /*!< Max enumerator value of OUT15 field.                                 */
101862   #define VPRCSR_NORDIC_DIROUTTGL_OUT15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101863   #define VPRCSR_NORDIC_DIROUTTGL_OUT15_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101864 
101865 /* DIR0 @Bit 16 : (unspecified) */
101866   #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Pos (16UL)    /*!< Position of DIR0 field.                                              */
101867   #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR0_Pos) /*!< Bit mask of DIR0 field.            */
101868   #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Min (0x0UL)   /*!< Min enumerator value of DIR0 field.                                  */
101869   #define VPRCSR_NORDIC_DIROUTTGL_DIR0_Max (0x1UL)   /*!< Max enumerator value of DIR0 field.                                  */
101870   #define VPRCSR_NORDIC_DIROUTTGL_DIR0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101871   #define VPRCSR_NORDIC_DIROUTTGL_DIR0_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101872 
101873 /* DIR1 @Bit 17 : (unspecified) */
101874   #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Pos (17UL)    /*!< Position of DIR1 field.                                              */
101875   #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR1_Pos) /*!< Bit mask of DIR1 field.            */
101876   #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Min (0x0UL)   /*!< Min enumerator value of DIR1 field.                                  */
101877   #define VPRCSR_NORDIC_DIROUTTGL_DIR1_Max (0x1UL)   /*!< Max enumerator value of DIR1 field.                                  */
101878   #define VPRCSR_NORDIC_DIROUTTGL_DIR1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101879   #define VPRCSR_NORDIC_DIROUTTGL_DIR1_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101880 
101881 /* DIR2 @Bit 18 : (unspecified) */
101882   #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Pos (18UL)    /*!< Position of DIR2 field.                                              */
101883   #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR2_Pos) /*!< Bit mask of DIR2 field.            */
101884   #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Min (0x0UL)   /*!< Min enumerator value of DIR2 field.                                  */
101885   #define VPRCSR_NORDIC_DIROUTTGL_DIR2_Max (0x1UL)   /*!< Max enumerator value of DIR2 field.                                  */
101886   #define VPRCSR_NORDIC_DIROUTTGL_DIR2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101887   #define VPRCSR_NORDIC_DIROUTTGL_DIR2_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101888 
101889 /* DIR3 @Bit 19 : (unspecified) */
101890   #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Pos (19UL)    /*!< Position of DIR3 field.                                              */
101891   #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR3_Pos) /*!< Bit mask of DIR3 field.            */
101892   #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Min (0x0UL)   /*!< Min enumerator value of DIR3 field.                                  */
101893   #define VPRCSR_NORDIC_DIROUTTGL_DIR3_Max (0x1UL)   /*!< Max enumerator value of DIR3 field.                                  */
101894   #define VPRCSR_NORDIC_DIROUTTGL_DIR3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101895   #define VPRCSR_NORDIC_DIROUTTGL_DIR3_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101896 
101897 /* DIR4 @Bit 20 : (unspecified) */
101898   #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Pos (20UL)    /*!< Position of DIR4 field.                                              */
101899   #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR4_Pos) /*!< Bit mask of DIR4 field.            */
101900   #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Min (0x0UL)   /*!< Min enumerator value of DIR4 field.                                  */
101901   #define VPRCSR_NORDIC_DIROUTTGL_DIR4_Max (0x1UL)   /*!< Max enumerator value of DIR4 field.                                  */
101902   #define VPRCSR_NORDIC_DIROUTTGL_DIR4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101903   #define VPRCSR_NORDIC_DIROUTTGL_DIR4_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101904 
101905 /* DIR5 @Bit 21 : (unspecified) */
101906   #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Pos (21UL)    /*!< Position of DIR5 field.                                              */
101907   #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR5_Pos) /*!< Bit mask of DIR5 field.            */
101908   #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Min (0x0UL)   /*!< Min enumerator value of DIR5 field.                                  */
101909   #define VPRCSR_NORDIC_DIROUTTGL_DIR5_Max (0x1UL)   /*!< Max enumerator value of DIR5 field.                                  */
101910   #define VPRCSR_NORDIC_DIROUTTGL_DIR5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101911   #define VPRCSR_NORDIC_DIROUTTGL_DIR5_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101912 
101913 /* DIR6 @Bit 22 : (unspecified) */
101914   #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Pos (22UL)    /*!< Position of DIR6 field.                                              */
101915   #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR6_Pos) /*!< Bit mask of DIR6 field.            */
101916   #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Min (0x0UL)   /*!< Min enumerator value of DIR6 field.                                  */
101917   #define VPRCSR_NORDIC_DIROUTTGL_DIR6_Max (0x1UL)   /*!< Max enumerator value of DIR6 field.                                  */
101918   #define VPRCSR_NORDIC_DIROUTTGL_DIR6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101919   #define VPRCSR_NORDIC_DIROUTTGL_DIR6_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101920 
101921 /* DIR7 @Bit 23 : (unspecified) */
101922   #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Pos (23UL)    /*!< Position of DIR7 field.                                              */
101923   #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR7_Pos) /*!< Bit mask of DIR7 field.            */
101924   #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Min (0x0UL)   /*!< Min enumerator value of DIR7 field.                                  */
101925   #define VPRCSR_NORDIC_DIROUTTGL_DIR7_Max (0x1UL)   /*!< Max enumerator value of DIR7 field.                                  */
101926   #define VPRCSR_NORDIC_DIROUTTGL_DIR7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101927   #define VPRCSR_NORDIC_DIROUTTGL_DIR7_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101928 
101929 /* DIR8 @Bit 24 : (unspecified) */
101930   #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Pos (24UL)    /*!< Position of DIR8 field.                                              */
101931   #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR8_Pos) /*!< Bit mask of DIR8 field.            */
101932   #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Min (0x0UL)   /*!< Min enumerator value of DIR8 field.                                  */
101933   #define VPRCSR_NORDIC_DIROUTTGL_DIR8_Max (0x1UL)   /*!< Max enumerator value of DIR8 field.                                  */
101934   #define VPRCSR_NORDIC_DIROUTTGL_DIR8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101935   #define VPRCSR_NORDIC_DIROUTTGL_DIR8_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101936 
101937 /* DIR9 @Bit 25 : (unspecified) */
101938   #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Pos (25UL)    /*!< Position of DIR9 field.                                              */
101939   #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR9_Pos) /*!< Bit mask of DIR9 field.            */
101940   #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Min (0x0UL)   /*!< Min enumerator value of DIR9 field.                                  */
101941   #define VPRCSR_NORDIC_DIROUTTGL_DIR9_Max (0x1UL)   /*!< Max enumerator value of DIR9 field.                                  */
101942   #define VPRCSR_NORDIC_DIROUTTGL_DIR9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
101943   #define VPRCSR_NORDIC_DIROUTTGL_DIR9_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
101944 
101945 /* DIR10 @Bit 26 : (unspecified) */
101946   #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Pos (26UL)   /*!< Position of DIR10 field.                                             */
101947   #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR10_Pos) /*!< Bit mask of DIR10 field.         */
101948   #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Min (0x0UL)  /*!< Min enumerator value of DIR10 field.                                 */
101949   #define VPRCSR_NORDIC_DIROUTTGL_DIR10_Max (0x1UL)  /*!< Max enumerator value of DIR10 field.                                 */
101950   #define VPRCSR_NORDIC_DIROUTTGL_DIR10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101951   #define VPRCSR_NORDIC_DIROUTTGL_DIR10_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101952 
101953 /* DIR11 @Bit 27 : (unspecified) */
101954   #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Pos (27UL)   /*!< Position of DIR11 field.                                             */
101955   #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR11_Pos) /*!< Bit mask of DIR11 field.         */
101956   #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Min (0x0UL)  /*!< Min enumerator value of DIR11 field.                                 */
101957   #define VPRCSR_NORDIC_DIROUTTGL_DIR11_Max (0x1UL)  /*!< Max enumerator value of DIR11 field.                                 */
101958   #define VPRCSR_NORDIC_DIROUTTGL_DIR11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101959   #define VPRCSR_NORDIC_DIROUTTGL_DIR11_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101960 
101961 /* DIR12 @Bit 28 : (unspecified) */
101962   #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Pos (28UL)   /*!< Position of DIR12 field.                                             */
101963   #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR12_Pos) /*!< Bit mask of DIR12 field.         */
101964   #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Min (0x0UL)  /*!< Min enumerator value of DIR12 field.                                 */
101965   #define VPRCSR_NORDIC_DIROUTTGL_DIR12_Max (0x1UL)  /*!< Max enumerator value of DIR12 field.                                 */
101966   #define VPRCSR_NORDIC_DIROUTTGL_DIR12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101967   #define VPRCSR_NORDIC_DIROUTTGL_DIR12_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101968 
101969 /* DIR13 @Bit 29 : (unspecified) */
101970   #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Pos (29UL)   /*!< Position of DIR13 field.                                             */
101971   #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR13_Pos) /*!< Bit mask of DIR13 field.         */
101972   #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Min (0x0UL)  /*!< Min enumerator value of DIR13 field.                                 */
101973   #define VPRCSR_NORDIC_DIROUTTGL_DIR13_Max (0x1UL)  /*!< Max enumerator value of DIR13 field.                                 */
101974   #define VPRCSR_NORDIC_DIROUTTGL_DIR13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101975   #define VPRCSR_NORDIC_DIROUTTGL_DIR13_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101976 
101977 /* DIR14 @Bit 30 : (unspecified) */
101978   #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Pos (30UL)   /*!< Position of DIR14 field.                                             */
101979   #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR14_Pos) /*!< Bit mask of DIR14 field.         */
101980   #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Min (0x0UL)  /*!< Min enumerator value of DIR14 field.                                 */
101981   #define VPRCSR_NORDIC_DIROUTTGL_DIR14_Max (0x1UL)  /*!< Max enumerator value of DIR14 field.                                 */
101982   #define VPRCSR_NORDIC_DIROUTTGL_DIR14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101983   #define VPRCSR_NORDIC_DIROUTTGL_DIR14_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101984 
101985 /* DIR15 @Bit 31 : (unspecified) */
101986   #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Pos (31UL)   /*!< Position of DIR15 field.                                             */
101987   #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTTGL_DIR15_Pos) /*!< Bit mask of DIR15 field.         */
101988   #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Min (0x0UL)  /*!< Min enumerator value of DIR15 field.                                 */
101989   #define VPRCSR_NORDIC_DIROUTTGL_DIR15_Max (0x1UL)  /*!< Max enumerator value of DIR15 field.                                 */
101990   #define VPRCSR_NORDIC_DIROUTTGL_DIR15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
101991   #define VPRCSR_NORDIC_DIROUTTGL_DIR15_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
101992 
101993 
101994 /**
101995   * @brief DIROUTBTGL [VPRCSR_NORDIC_DIROUTBTGL] DIROUTB Toggle
101996   */
101997   #define VPRCSR_NORDIC_DIROUTBTGL (0x00000BD5ul)
101998   #define VPRCSR_NORDIC_DIROUTBTGL_ResetValue (0x00000000UL) /*!< Reset value of DIROUTBTGL register.                          */
101999 
102000 /* OUTB0 @Bit 0 : (unspecified) */
102001   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Pos (0UL)   /*!< Position of OUTB0 field.                                             */
102002   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Pos) /*!< Bit mask of OUTB0 field.       */
102003   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Min (0x0UL) /*!< Min enumerator value of OUTB0 field.                                 */
102004   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_Max (0x1UL) /*!< Max enumerator value of OUTB0 field.                                 */
102005   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102006   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB0_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102007 
102008 /* OUTB1 @Bit 1 : (unspecified) */
102009   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Pos (1UL)   /*!< Position of OUTB1 field.                                             */
102010   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Pos) /*!< Bit mask of OUTB1 field.       */
102011   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Min (0x0UL) /*!< Min enumerator value of OUTB1 field.                                 */
102012   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_Max (0x1UL) /*!< Max enumerator value of OUTB1 field.                                 */
102013   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102014   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB1_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102015 
102016 /* OUTB2 @Bit 2 : (unspecified) */
102017   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Pos (2UL)   /*!< Position of OUTB2 field.                                             */
102018   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Pos) /*!< Bit mask of OUTB2 field.       */
102019   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Min (0x0UL) /*!< Min enumerator value of OUTB2 field.                                 */
102020   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_Max (0x1UL) /*!< Max enumerator value of OUTB2 field.                                 */
102021   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102022   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB2_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102023 
102024 /* OUTB3 @Bit 3 : (unspecified) */
102025   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Pos (3UL)   /*!< Position of OUTB3 field.                                             */
102026   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Pos) /*!< Bit mask of OUTB3 field.       */
102027   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Min (0x0UL) /*!< Min enumerator value of OUTB3 field.                                 */
102028   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_Max (0x1UL) /*!< Max enumerator value of OUTB3 field.                                 */
102029   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102030   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB3_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102031 
102032 /* OUTB4 @Bit 4 : (unspecified) */
102033   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Pos (4UL)   /*!< Position of OUTB4 field.                                             */
102034   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Pos) /*!< Bit mask of OUTB4 field.       */
102035   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Min (0x0UL) /*!< Min enumerator value of OUTB4 field.                                 */
102036   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_Max (0x1UL) /*!< Max enumerator value of OUTB4 field.                                 */
102037   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102038   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB4_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102039 
102040 /* OUTB5 @Bit 5 : (unspecified) */
102041   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Pos (5UL)   /*!< Position of OUTB5 field.                                             */
102042   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Pos) /*!< Bit mask of OUTB5 field.       */
102043   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Min (0x0UL) /*!< Min enumerator value of OUTB5 field.                                 */
102044   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_Max (0x1UL) /*!< Max enumerator value of OUTB5 field.                                 */
102045   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102046   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB5_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102047 
102048 /* OUTB6 @Bit 6 : (unspecified) */
102049   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Pos (6UL)   /*!< Position of OUTB6 field.                                             */
102050   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Pos) /*!< Bit mask of OUTB6 field.       */
102051   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Min (0x0UL) /*!< Min enumerator value of OUTB6 field.                                 */
102052   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_Max (0x1UL) /*!< Max enumerator value of OUTB6 field.                                 */
102053   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102054   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB6_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102055 
102056 /* OUTB7 @Bit 7 : (unspecified) */
102057   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Pos (7UL)   /*!< Position of OUTB7 field.                                             */
102058   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Pos) /*!< Bit mask of OUTB7 field.       */
102059   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Min (0x0UL) /*!< Min enumerator value of OUTB7 field.                                 */
102060   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_Max (0x1UL) /*!< Max enumerator value of OUTB7 field.                                 */
102061   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102062   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB7_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102063 
102064 /* OUTB8 @Bit 8 : (unspecified) */
102065   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Pos (8UL)   /*!< Position of OUTB8 field.                                             */
102066   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Pos) /*!< Bit mask of OUTB8 field.       */
102067   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Min (0x0UL) /*!< Min enumerator value of OUTB8 field.                                 */
102068   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_Max (0x1UL) /*!< Max enumerator value of OUTB8 field.                                 */
102069   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102070   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB8_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102071 
102072 /* OUTB9 @Bit 9 : (unspecified) */
102073   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Pos (9UL)   /*!< Position of OUTB9 field.                                             */
102074   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Pos) /*!< Bit mask of OUTB9 field.       */
102075   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Min (0x0UL) /*!< Min enumerator value of OUTB9 field.                                 */
102076   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_Max (0x1UL) /*!< Max enumerator value of OUTB9 field.                                 */
102077   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102078   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB9_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102079 
102080 /* OUTB10 @Bit 10 : (unspecified) */
102081   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Pos (10UL) /*!< Position of OUTB10 field.                                            */
102082   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Pos) /*!< Bit mask of OUTB10 field.    */
102083   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Min (0x0UL) /*!< Min enumerator value of OUTB10 field.                               */
102084   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_Max (0x1UL) /*!< Max enumerator value of OUTB10 field.                               */
102085   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102086   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB10_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102087 
102088 /* OUTB11 @Bit 11 : (unspecified) */
102089   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Pos (11UL) /*!< Position of OUTB11 field.                                            */
102090   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Pos) /*!< Bit mask of OUTB11 field.    */
102091   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Min (0x0UL) /*!< Min enumerator value of OUTB11 field.                               */
102092   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_Max (0x1UL) /*!< Max enumerator value of OUTB11 field.                               */
102093   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102094   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB11_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102095 
102096 /* OUTB12 @Bit 12 : (unspecified) */
102097   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Pos (12UL) /*!< Position of OUTB12 field.                                            */
102098   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Pos) /*!< Bit mask of OUTB12 field.    */
102099   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Min (0x0UL) /*!< Min enumerator value of OUTB12 field.                               */
102100   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_Max (0x1UL) /*!< Max enumerator value of OUTB12 field.                               */
102101   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102102   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB12_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102103 
102104 /* OUTB13 @Bit 13 : (unspecified) */
102105   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Pos (13UL) /*!< Position of OUTB13 field.                                            */
102106   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Pos) /*!< Bit mask of OUTB13 field.    */
102107   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Min (0x0UL) /*!< Min enumerator value of OUTB13 field.                               */
102108   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_Max (0x1UL) /*!< Max enumerator value of OUTB13 field.                               */
102109   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102110   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB13_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102111 
102112 /* OUTB14 @Bit 14 : (unspecified) */
102113   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Pos (14UL) /*!< Position of OUTB14 field.                                            */
102114   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Pos) /*!< Bit mask of OUTB14 field.    */
102115   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Min (0x0UL) /*!< Min enumerator value of OUTB14 field.                               */
102116   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_Max (0x1UL) /*!< Max enumerator value of OUTB14 field.                               */
102117   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102118   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB14_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102119 
102120 /* OUTB15 @Bit 15 : (unspecified) */
102121   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Pos (15UL) /*!< Position of OUTB15 field.                                            */
102122   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Pos) /*!< Bit mask of OUTB15 field.    */
102123   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Min (0x0UL) /*!< Min enumerator value of OUTB15 field.                               */
102124   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_Max (0x1UL) /*!< Max enumerator value of OUTB15 field.                               */
102125   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102126   #define VPRCSR_NORDIC_DIROUTBTGL_OUTB15_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102127 
102128 /* DIRB0 @Bit 16 : (unspecified) */
102129   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Pos (16UL)  /*!< Position of DIRB0 field.                                             */
102130   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Pos) /*!< Bit mask of DIRB0 field.       */
102131   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Min (0x0UL) /*!< Min enumerator value of DIRB0 field.                                 */
102132   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_Max (0x1UL) /*!< Max enumerator value of DIRB0 field.                                 */
102133   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102134   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB0_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102135 
102136 /* DIRB1 @Bit 17 : (unspecified) */
102137   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Pos (17UL)  /*!< Position of DIRB1 field.                                             */
102138   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Pos) /*!< Bit mask of DIRB1 field.       */
102139   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Min (0x0UL) /*!< Min enumerator value of DIRB1 field.                                 */
102140   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_Max (0x1UL) /*!< Max enumerator value of DIRB1 field.                                 */
102141   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102142   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB1_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102143 
102144 /* DIRB2 @Bit 18 : (unspecified) */
102145   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Pos (18UL)  /*!< Position of DIRB2 field.                                             */
102146   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Pos) /*!< Bit mask of DIRB2 field.       */
102147   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Min (0x0UL) /*!< Min enumerator value of DIRB2 field.                                 */
102148   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_Max (0x1UL) /*!< Max enumerator value of DIRB2 field.                                 */
102149   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102150   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB2_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102151 
102152 /* DIRB3 @Bit 19 : (unspecified) */
102153   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Pos (19UL)  /*!< Position of DIRB3 field.                                             */
102154   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Pos) /*!< Bit mask of DIRB3 field.       */
102155   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Min (0x0UL) /*!< Min enumerator value of DIRB3 field.                                 */
102156   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_Max (0x1UL) /*!< Max enumerator value of DIRB3 field.                                 */
102157   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102158   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB3_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102159 
102160 /* DIRB4 @Bit 20 : (unspecified) */
102161   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Pos (20UL)  /*!< Position of DIRB4 field.                                             */
102162   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Pos) /*!< Bit mask of DIRB4 field.       */
102163   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Min (0x0UL) /*!< Min enumerator value of DIRB4 field.                                 */
102164   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_Max (0x1UL) /*!< Max enumerator value of DIRB4 field.                                 */
102165   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102166   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB4_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102167 
102168 /* DIRB5 @Bit 21 : (unspecified) */
102169   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Pos (21UL)  /*!< Position of DIRB5 field.                                             */
102170   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Pos) /*!< Bit mask of DIRB5 field.       */
102171   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Min (0x0UL) /*!< Min enumerator value of DIRB5 field.                                 */
102172   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_Max (0x1UL) /*!< Max enumerator value of DIRB5 field.                                 */
102173   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102174   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB5_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102175 
102176 /* DIRB6 @Bit 22 : (unspecified) */
102177   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Pos (22UL)  /*!< Position of DIRB6 field.                                             */
102178   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Pos) /*!< Bit mask of DIRB6 field.       */
102179   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Min (0x0UL) /*!< Min enumerator value of DIRB6 field.                                 */
102180   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_Max (0x1UL) /*!< Max enumerator value of DIRB6 field.                                 */
102181   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102182   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB6_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102183 
102184 /* DIRB7 @Bit 23 : (unspecified) */
102185   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Pos (23UL)  /*!< Position of DIRB7 field.                                             */
102186   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Pos) /*!< Bit mask of DIRB7 field.       */
102187   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Min (0x0UL) /*!< Min enumerator value of DIRB7 field.                                 */
102188   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_Max (0x1UL) /*!< Max enumerator value of DIRB7 field.                                 */
102189   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102190   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB7_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102191 
102192 /* DIRB8 @Bit 24 : (unspecified) */
102193   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Pos (24UL)  /*!< Position of DIRB8 field.                                             */
102194   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Pos) /*!< Bit mask of DIRB8 field.       */
102195   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Min (0x0UL) /*!< Min enumerator value of DIRB8 field.                                 */
102196   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_Max (0x1UL) /*!< Max enumerator value of DIRB8 field.                                 */
102197   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102198   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB8_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102199 
102200 /* DIRB9 @Bit 25 : (unspecified) */
102201   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Pos (25UL)  /*!< Position of DIRB9 field.                                             */
102202   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Pos) /*!< Bit mask of DIRB9 field.       */
102203   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Min (0x0UL) /*!< Min enumerator value of DIRB9 field.                                 */
102204   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_Max (0x1UL) /*!< Max enumerator value of DIRB9 field.                                 */
102205   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                          */
102206   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB9_TOGGLE (0x1UL) /*!< Pin is toggled                                                    */
102207 
102208 /* DIRB10 @Bit 26 : (unspecified) */
102209   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Pos (26UL) /*!< Position of DIRB10 field.                                            */
102210   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Pos) /*!< Bit mask of DIRB10 field.    */
102211   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Min (0x0UL) /*!< Min enumerator value of DIRB10 field.                               */
102212   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_Max (0x1UL) /*!< Max enumerator value of DIRB10 field.                               */
102213   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102214   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB10_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102215 
102216 /* DIRB11 @Bit 27 : (unspecified) */
102217   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Pos (27UL) /*!< Position of DIRB11 field.                                            */
102218   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Pos) /*!< Bit mask of DIRB11 field.    */
102219   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Min (0x0UL) /*!< Min enumerator value of DIRB11 field.                               */
102220   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_Max (0x1UL) /*!< Max enumerator value of DIRB11 field.                               */
102221   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102222   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB11_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102223 
102224 /* DIRB12 @Bit 28 : (unspecified) */
102225   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Pos (28UL) /*!< Position of DIRB12 field.                                            */
102226   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Pos) /*!< Bit mask of DIRB12 field.    */
102227   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Min (0x0UL) /*!< Min enumerator value of DIRB12 field.                               */
102228   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_Max (0x1UL) /*!< Max enumerator value of DIRB12 field.                               */
102229   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102230   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB12_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102231 
102232 /* DIRB13 @Bit 29 : (unspecified) */
102233   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Pos (29UL) /*!< Position of DIRB13 field.                                            */
102234   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Pos) /*!< Bit mask of DIRB13 field.    */
102235   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Min (0x0UL) /*!< Min enumerator value of DIRB13 field.                               */
102236   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_Max (0x1UL) /*!< Max enumerator value of DIRB13 field.                               */
102237   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102238   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB13_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102239 
102240 /* DIRB14 @Bit 30 : (unspecified) */
102241   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Pos (30UL) /*!< Position of DIRB14 field.                                            */
102242   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Pos) /*!< Bit mask of DIRB14 field.    */
102243   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Min (0x0UL) /*!< Min enumerator value of DIRB14 field.                               */
102244   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_Max (0x1UL) /*!< Max enumerator value of DIRB14 field.                               */
102245   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102246   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB14_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102247 
102248 /* DIRB15 @Bit 31 : (unspecified) */
102249   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Pos (31UL) /*!< Position of DIRB15 field.                                            */
102250   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Pos) /*!< Bit mask of DIRB15 field.    */
102251   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Min (0x0UL) /*!< Min enumerator value of DIRB15 field.                               */
102252   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_Max (0x1UL) /*!< Max enumerator value of DIRB15 field.                               */
102253   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                         */
102254   #define VPRCSR_NORDIC_DIROUTBTGL_DIRB15_TOGGLE (0x1UL) /*!< Pin is toggled                                                   */
102255 
102256 
102257 /**
102258   * @brief OUTBS [VPRCSR_NORDIC_OUTBS] Buffered GPIO Output Dirty Status
102259   */
102260   #define VPRCSR_NORDIC_OUTBS (0x00000BD8ul)
102261   #define VPRCSR_NORDIC_OUTBS_ResetValue (0x00000000UL) /*!< Reset value of OUTBS register.                                    */
102262 
102263 /* OUTB @Bits 0..31 : Write to OUTB (if not dirty) */
102264   #define VPRCSR_NORDIC_OUTBS_OUTB_Pos (0UL)         /*!< Position of OUTB field.                                              */
102265   #define VPRCSR_NORDIC_OUTBS_OUTB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBS_OUTB_Pos) /*!< Bit mask of OUTB field.             */
102266 
102267 /* DIRTYBIT @Bit 0 : Read Buffer Dirty status */
102268   #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Pos (0UL)     /*!< Position of DIRTYBIT field.                                          */
102269   #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.        */
102270   #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Min (0x0UL)   /*!< Min enumerator value of DIRTYBIT field.                              */
102271   #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_Max (0x1UL)   /*!< Max enumerator value of DIRTYBIT field.                              */
102272   #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                      */
102273   #define VPRCSR_NORDIC_OUTBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                      */
102274 
102275 
102276 /**
102277   * @brief DIRBS [VPRCSR_NORDIC_DIRBS] Buffered GPIO pin Direction Dirty Status
102278   */
102279   #define VPRCSR_NORDIC_DIRBS (0x00000BD9ul)
102280   #define VPRCSR_NORDIC_DIRBS_ResetValue (0x00000000UL) /*!< Reset value of DIRBS register.                                    */
102281 
102282 /* DIRB @Bits 0..31 : Write to DIRB (if not dirty) */
102283   #define VPRCSR_NORDIC_DIRBS_DIRB_Pos (0UL)         /*!< Position of DIRB field.                                              */
102284   #define VPRCSR_NORDIC_DIRBS_DIRB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_DIRBS_DIRB_Pos) /*!< Bit mask of DIRB field.             */
102285 
102286 /* DIRTYBIT @Bit 0 : Read Buffer Dirty status */
102287   #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Pos (0UL)     /*!< Position of DIRTYBIT field.                                          */
102288   #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_DIRBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.        */
102289   #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Min (0x0UL)   /*!< Min enumerator value of DIRTYBIT field.                              */
102290   #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_Max (0x1UL)   /*!< Max enumerator value of DIRTYBIT field.                              */
102291   #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                      */
102292   #define VPRCSR_NORDIC_DIRBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                      */
102293 
102294 
102295 /**
102296   * @brief DIROUTBS [VPRCSR_NORDIC_DIROUTBS] Combination of DIRB and OUTB Dirty Status
102297   */
102298   #define VPRCSR_NORDIC_DIROUTBS (0x00000BDAul)
102299   #define VPRCSR_NORDIC_DIROUTBS_ResetValue (0x00000000UL) /*!< Reset value of DIROUTBS register.                              */
102300 
102301 /* DIROUTB @Bits 0..31 : Write to DIROUTB (if not dirty) */
102302   #define VPRCSR_NORDIC_DIROUTBS_DIROUTB_Pos (0UL)   /*!< Position of DIROUTB field.                                           */
102303   #define VPRCSR_NORDIC_DIROUTBS_DIROUTB_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_DIROUTBS_DIROUTB_Pos) /*!< Bit mask of DIROUTB
102304                                                                             field.*/
102305 
102306 /* DIRTYBIT @Bit 0 : Read Combination (OR) of DIRB and OUTB Dirty status */
102307   #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Pos (0UL)  /*!< Position of DIRTYBIT field.                                          */
102308   #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.  */
102309   #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Min (0x0UL) /*!< Min enumerator value of DIRTYBIT field.                             */
102310   #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_Max (0x1UL) /*!< Max enumerator value of DIRTYBIT field.                             */
102311   #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                   */
102312   #define VPRCSR_NORDIC_DIROUTBS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                   */
102313 
102314 
102315 /**
102316   * @brief OUTBD [VPRCSR_NORDIC_OUTBD] Concatenation of Buffered GPIO Output and GPIO Output
102317   */
102318   #define VPRCSR_NORDIC_OUTBD (0x00000BE0ul)
102319   #define VPRCSR_NORDIC_OUTBD_ResetValue (0x00000000UL) /*!< Reset value of OUTBD register.                                    */
102320 
102321 /* OUT @Bits 0..15 : GPIO Output */
102322   #define VPRCSR_NORDIC_OUTBD_OUT_Pos (0UL)          /*!< Position of OUT field.                                               */
102323   #define VPRCSR_NORDIC_OUTBD_OUT_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTBD_OUT_Pos) /*!< Bit mask of OUT field.                    */
102324 
102325 /* OUTB @Bits 16..31 : Buffered GPIO Output */
102326   #define VPRCSR_NORDIC_OUTBD_OUTB_Pos (16UL)        /*!< Position of OUTB field.                                              */
102327   #define VPRCSR_NORDIC_OUTBD_OUTB_Msk (0xFFFFUL << VPRCSR_NORDIC_OUTBD_OUTB_Pos) /*!< Bit mask of OUTB field.                 */
102328 
102329 
102330 /**
102331   * @brief OUTBDTGL [VPRCSR_NORDIC_OUTBDTGL] OUTBD Toggle
102332   */
102333   #define VPRCSR_NORDIC_OUTBDTGL (0x00000BE1ul)
102334   #define VPRCSR_NORDIC_OUTBDTGL_ResetValue (0x00000000UL) /*!< Reset value of OUTBDTGL register.                              */
102335 
102336 /* OUT0 @Bit 0 : (unspecified) */
102337   #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Pos (0UL)      /*!< Position of OUT0 field.                                              */
102338   #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT0_Pos) /*!< Bit mask of OUT0 field.              */
102339   #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Min (0x0UL)    /*!< Min enumerator value of OUT0 field.                                  */
102340   #define VPRCSR_NORDIC_OUTBDTGL_OUT0_Max (0x1UL)    /*!< Max enumerator value of OUT0 field.                                  */
102341   #define VPRCSR_NORDIC_OUTBDTGL_OUT0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102342   #define VPRCSR_NORDIC_OUTBDTGL_OUT0_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102343 
102344 /* OUT1 @Bit 1 : (unspecified) */
102345   #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Pos (1UL)      /*!< Position of OUT1 field.                                              */
102346   #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT1_Pos) /*!< Bit mask of OUT1 field.              */
102347   #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Min (0x0UL)    /*!< Min enumerator value of OUT1 field.                                  */
102348   #define VPRCSR_NORDIC_OUTBDTGL_OUT1_Max (0x1UL)    /*!< Max enumerator value of OUT1 field.                                  */
102349   #define VPRCSR_NORDIC_OUTBDTGL_OUT1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102350   #define VPRCSR_NORDIC_OUTBDTGL_OUT1_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102351 
102352 /* OUT2 @Bit 2 : (unspecified) */
102353   #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Pos (2UL)      /*!< Position of OUT2 field.                                              */
102354   #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT2_Pos) /*!< Bit mask of OUT2 field.              */
102355   #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Min (0x0UL)    /*!< Min enumerator value of OUT2 field.                                  */
102356   #define VPRCSR_NORDIC_OUTBDTGL_OUT2_Max (0x1UL)    /*!< Max enumerator value of OUT2 field.                                  */
102357   #define VPRCSR_NORDIC_OUTBDTGL_OUT2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102358   #define VPRCSR_NORDIC_OUTBDTGL_OUT2_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102359 
102360 /* OUT3 @Bit 3 : (unspecified) */
102361   #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Pos (3UL)      /*!< Position of OUT3 field.                                              */
102362   #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT3_Pos) /*!< Bit mask of OUT3 field.              */
102363   #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Min (0x0UL)    /*!< Min enumerator value of OUT3 field.                                  */
102364   #define VPRCSR_NORDIC_OUTBDTGL_OUT3_Max (0x1UL)    /*!< Max enumerator value of OUT3 field.                                  */
102365   #define VPRCSR_NORDIC_OUTBDTGL_OUT3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102366   #define VPRCSR_NORDIC_OUTBDTGL_OUT3_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102367 
102368 /* OUT4 @Bit 4 : (unspecified) */
102369   #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Pos (4UL)      /*!< Position of OUT4 field.                                              */
102370   #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT4_Pos) /*!< Bit mask of OUT4 field.              */
102371   #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Min (0x0UL)    /*!< Min enumerator value of OUT4 field.                                  */
102372   #define VPRCSR_NORDIC_OUTBDTGL_OUT4_Max (0x1UL)    /*!< Max enumerator value of OUT4 field.                                  */
102373   #define VPRCSR_NORDIC_OUTBDTGL_OUT4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102374   #define VPRCSR_NORDIC_OUTBDTGL_OUT4_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102375 
102376 /* OUT5 @Bit 5 : (unspecified) */
102377   #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Pos (5UL)      /*!< Position of OUT5 field.                                              */
102378   #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT5_Pos) /*!< Bit mask of OUT5 field.              */
102379   #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Min (0x0UL)    /*!< Min enumerator value of OUT5 field.                                  */
102380   #define VPRCSR_NORDIC_OUTBDTGL_OUT5_Max (0x1UL)    /*!< Max enumerator value of OUT5 field.                                  */
102381   #define VPRCSR_NORDIC_OUTBDTGL_OUT5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102382   #define VPRCSR_NORDIC_OUTBDTGL_OUT5_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102383 
102384 /* OUT6 @Bit 6 : (unspecified) */
102385   #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Pos (6UL)      /*!< Position of OUT6 field.                                              */
102386   #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT6_Pos) /*!< Bit mask of OUT6 field.              */
102387   #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Min (0x0UL)    /*!< Min enumerator value of OUT6 field.                                  */
102388   #define VPRCSR_NORDIC_OUTBDTGL_OUT6_Max (0x1UL)    /*!< Max enumerator value of OUT6 field.                                  */
102389   #define VPRCSR_NORDIC_OUTBDTGL_OUT6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102390   #define VPRCSR_NORDIC_OUTBDTGL_OUT6_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102391 
102392 /* OUT7 @Bit 7 : (unspecified) */
102393   #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Pos (7UL)      /*!< Position of OUT7 field.                                              */
102394   #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT7_Pos) /*!< Bit mask of OUT7 field.              */
102395   #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Min (0x0UL)    /*!< Min enumerator value of OUT7 field.                                  */
102396   #define VPRCSR_NORDIC_OUTBDTGL_OUT7_Max (0x1UL)    /*!< Max enumerator value of OUT7 field.                                  */
102397   #define VPRCSR_NORDIC_OUTBDTGL_OUT7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102398   #define VPRCSR_NORDIC_OUTBDTGL_OUT7_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102399 
102400 /* OUT8 @Bit 8 : (unspecified) */
102401   #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Pos (8UL)      /*!< Position of OUT8 field.                                              */
102402   #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT8_Pos) /*!< Bit mask of OUT8 field.              */
102403   #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Min (0x0UL)    /*!< Min enumerator value of OUT8 field.                                  */
102404   #define VPRCSR_NORDIC_OUTBDTGL_OUT8_Max (0x1UL)    /*!< Max enumerator value of OUT8 field.                                  */
102405   #define VPRCSR_NORDIC_OUTBDTGL_OUT8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102406   #define VPRCSR_NORDIC_OUTBDTGL_OUT8_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102407 
102408 /* OUT9 @Bit 9 : (unspecified) */
102409   #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Pos (9UL)      /*!< Position of OUT9 field.                                              */
102410   #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT9_Pos) /*!< Bit mask of OUT9 field.              */
102411   #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Min (0x0UL)    /*!< Min enumerator value of OUT9 field.                                  */
102412   #define VPRCSR_NORDIC_OUTBDTGL_OUT9_Max (0x1UL)    /*!< Max enumerator value of OUT9 field.                                  */
102413   #define VPRCSR_NORDIC_OUTBDTGL_OUT9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                             */
102414   #define VPRCSR_NORDIC_OUTBDTGL_OUT9_TOGGLE (0x1UL) /*!< Pin is toggled                                                       */
102415 
102416 /* OUT10 @Bit 10 : (unspecified) */
102417   #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Pos (10UL)    /*!< Position of OUT10 field.                                             */
102418   #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT10_Pos) /*!< Bit mask of OUT10 field.           */
102419   #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Min (0x0UL)   /*!< Min enumerator value of OUT10 field.                                 */
102420   #define VPRCSR_NORDIC_OUTBDTGL_OUT10_Max (0x1UL)   /*!< Max enumerator value of OUT10 field.                                 */
102421   #define VPRCSR_NORDIC_OUTBDTGL_OUT10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102422   #define VPRCSR_NORDIC_OUTBDTGL_OUT10_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102423 
102424 /* OUT11 @Bit 11 : (unspecified) */
102425   #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Pos (11UL)    /*!< Position of OUT11 field.                                             */
102426   #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT11_Pos) /*!< Bit mask of OUT11 field.           */
102427   #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Min (0x0UL)   /*!< Min enumerator value of OUT11 field.                                 */
102428   #define VPRCSR_NORDIC_OUTBDTGL_OUT11_Max (0x1UL)   /*!< Max enumerator value of OUT11 field.                                 */
102429   #define VPRCSR_NORDIC_OUTBDTGL_OUT11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102430   #define VPRCSR_NORDIC_OUTBDTGL_OUT11_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102431 
102432 /* OUT12 @Bit 12 : (unspecified) */
102433   #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Pos (12UL)    /*!< Position of OUT12 field.                                             */
102434   #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT12_Pos) /*!< Bit mask of OUT12 field.           */
102435   #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Min (0x0UL)   /*!< Min enumerator value of OUT12 field.                                 */
102436   #define VPRCSR_NORDIC_OUTBDTGL_OUT12_Max (0x1UL)   /*!< Max enumerator value of OUT12 field.                                 */
102437   #define VPRCSR_NORDIC_OUTBDTGL_OUT12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102438   #define VPRCSR_NORDIC_OUTBDTGL_OUT12_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102439 
102440 /* OUT13 @Bit 13 : (unspecified) */
102441   #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Pos (13UL)    /*!< Position of OUT13 field.                                             */
102442   #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT13_Pos) /*!< Bit mask of OUT13 field.           */
102443   #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Min (0x0UL)   /*!< Min enumerator value of OUT13 field.                                 */
102444   #define VPRCSR_NORDIC_OUTBDTGL_OUT13_Max (0x1UL)   /*!< Max enumerator value of OUT13 field.                                 */
102445   #define VPRCSR_NORDIC_OUTBDTGL_OUT13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102446   #define VPRCSR_NORDIC_OUTBDTGL_OUT13_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102447 
102448 /* OUT14 @Bit 14 : (unspecified) */
102449   #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Pos (14UL)    /*!< Position of OUT14 field.                                             */
102450   #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT14_Pos) /*!< Bit mask of OUT14 field.           */
102451   #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Min (0x0UL)   /*!< Min enumerator value of OUT14 field.                                 */
102452   #define VPRCSR_NORDIC_OUTBDTGL_OUT14_Max (0x1UL)   /*!< Max enumerator value of OUT14 field.                                 */
102453   #define VPRCSR_NORDIC_OUTBDTGL_OUT14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102454   #define VPRCSR_NORDIC_OUTBDTGL_OUT14_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102455 
102456 /* OUT15 @Bit 15 : (unspecified) */
102457   #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Pos (15UL)    /*!< Position of OUT15 field.                                             */
102458   #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUT15_Pos) /*!< Bit mask of OUT15 field.           */
102459   #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Min (0x0UL)   /*!< Min enumerator value of OUT15 field.                                 */
102460   #define VPRCSR_NORDIC_OUTBDTGL_OUT15_Max (0x1UL)   /*!< Max enumerator value of OUT15 field.                                 */
102461   #define VPRCSR_NORDIC_OUTBDTGL_OUT15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102462   #define VPRCSR_NORDIC_OUTBDTGL_OUT15_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102463 
102464 /* OUTB0 @Bit 16 : (unspecified) */
102465   #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Pos (16UL)    /*!< Position of OUTB0 field.                                             */
102466   #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB0_Pos) /*!< Bit mask of OUTB0 field.           */
102467   #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Min (0x0UL)   /*!< Min enumerator value of OUTB0 field.                                 */
102468   #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_Max (0x1UL)   /*!< Max enumerator value of OUTB0 field.                                 */
102469   #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102470   #define VPRCSR_NORDIC_OUTBDTGL_OUTB0_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102471 
102472 /* OUTB1 @Bit 17 : (unspecified) */
102473   #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Pos (17UL)    /*!< Position of OUTB1 field.                                             */
102474   #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB1_Pos) /*!< Bit mask of OUTB1 field.           */
102475   #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Min (0x0UL)   /*!< Min enumerator value of OUTB1 field.                                 */
102476   #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_Max (0x1UL)   /*!< Max enumerator value of OUTB1 field.                                 */
102477   #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102478   #define VPRCSR_NORDIC_OUTBDTGL_OUTB1_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102479 
102480 /* OUTB2 @Bit 18 : (unspecified) */
102481   #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Pos (18UL)    /*!< Position of OUTB2 field.                                             */
102482   #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB2_Pos) /*!< Bit mask of OUTB2 field.           */
102483   #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Min (0x0UL)   /*!< Min enumerator value of OUTB2 field.                                 */
102484   #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_Max (0x1UL)   /*!< Max enumerator value of OUTB2 field.                                 */
102485   #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102486   #define VPRCSR_NORDIC_OUTBDTGL_OUTB2_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102487 
102488 /* OUTB3 @Bit 19 : (unspecified) */
102489   #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Pos (19UL)    /*!< Position of OUTB3 field.                                             */
102490   #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB3_Pos) /*!< Bit mask of OUTB3 field.           */
102491   #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Min (0x0UL)   /*!< Min enumerator value of OUTB3 field.                                 */
102492   #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_Max (0x1UL)   /*!< Max enumerator value of OUTB3 field.                                 */
102493   #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102494   #define VPRCSR_NORDIC_OUTBDTGL_OUTB3_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102495 
102496 /* OUTB4 @Bit 20 : (unspecified) */
102497   #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Pos (20UL)    /*!< Position of OUTB4 field.                                             */
102498   #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB4_Pos) /*!< Bit mask of OUTB4 field.           */
102499   #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Min (0x0UL)   /*!< Min enumerator value of OUTB4 field.                                 */
102500   #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_Max (0x1UL)   /*!< Max enumerator value of OUTB4 field.                                 */
102501   #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102502   #define VPRCSR_NORDIC_OUTBDTGL_OUTB4_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102503 
102504 /* OUTB5 @Bit 21 : (unspecified) */
102505   #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Pos (21UL)    /*!< Position of OUTB5 field.                                             */
102506   #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB5_Pos) /*!< Bit mask of OUTB5 field.           */
102507   #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Min (0x0UL)   /*!< Min enumerator value of OUTB5 field.                                 */
102508   #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_Max (0x1UL)   /*!< Max enumerator value of OUTB5 field.                                 */
102509   #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102510   #define VPRCSR_NORDIC_OUTBDTGL_OUTB5_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102511 
102512 /* OUTB6 @Bit 22 : (unspecified) */
102513   #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Pos (22UL)    /*!< Position of OUTB6 field.                                             */
102514   #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB6_Pos) /*!< Bit mask of OUTB6 field.           */
102515   #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Min (0x0UL)   /*!< Min enumerator value of OUTB6 field.                                 */
102516   #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_Max (0x1UL)   /*!< Max enumerator value of OUTB6 field.                                 */
102517   #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102518   #define VPRCSR_NORDIC_OUTBDTGL_OUTB6_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102519 
102520 /* OUTB7 @Bit 23 : (unspecified) */
102521   #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Pos (23UL)    /*!< Position of OUTB7 field.                                             */
102522   #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB7_Pos) /*!< Bit mask of OUTB7 field.           */
102523   #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Min (0x0UL)   /*!< Min enumerator value of OUTB7 field.                                 */
102524   #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_Max (0x1UL)   /*!< Max enumerator value of OUTB7 field.                                 */
102525   #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102526   #define VPRCSR_NORDIC_OUTBDTGL_OUTB7_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102527 
102528 /* OUTB8 @Bit 24 : (unspecified) */
102529   #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Pos (24UL)    /*!< Position of OUTB8 field.                                             */
102530   #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB8_Pos) /*!< Bit mask of OUTB8 field.           */
102531   #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Min (0x0UL)   /*!< Min enumerator value of OUTB8 field.                                 */
102532   #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_Max (0x1UL)   /*!< Max enumerator value of OUTB8 field.                                 */
102533   #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102534   #define VPRCSR_NORDIC_OUTBDTGL_OUTB8_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102535 
102536 /* OUTB9 @Bit 25 : (unspecified) */
102537   #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Pos (25UL)    /*!< Position of OUTB9 field.                                             */
102538   #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB9_Pos) /*!< Bit mask of OUTB9 field.           */
102539   #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Min (0x0UL)   /*!< Min enumerator value of OUTB9 field.                                 */
102540   #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_Max (0x1UL)   /*!< Max enumerator value of OUTB9 field.                                 */
102541   #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                            */
102542   #define VPRCSR_NORDIC_OUTBDTGL_OUTB9_TOGGLE (0x1UL) /*!< Pin is toggled                                                      */
102543 
102544 /* OUTB10 @Bit 26 : (unspecified) */
102545   #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Pos (26UL)   /*!< Position of OUTB10 field.                                            */
102546   #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB10_Pos) /*!< Bit mask of OUTB10 field.        */
102547   #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Min (0x0UL)  /*!< Min enumerator value of OUTB10 field.                                */
102548   #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_Max (0x1UL)  /*!< Max enumerator value of OUTB10 field.                                */
102549   #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
102550   #define VPRCSR_NORDIC_OUTBDTGL_OUTB10_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
102551 
102552 /* OUTB11 @Bit 27 : (unspecified) */
102553   #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Pos (27UL)   /*!< Position of OUTB11 field.                                            */
102554   #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB11_Pos) /*!< Bit mask of OUTB11 field.        */
102555   #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Min (0x0UL)  /*!< Min enumerator value of OUTB11 field.                                */
102556   #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_Max (0x1UL)  /*!< Max enumerator value of OUTB11 field.                                */
102557   #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
102558   #define VPRCSR_NORDIC_OUTBDTGL_OUTB11_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
102559 
102560 /* OUTB12 @Bit 28 : (unspecified) */
102561   #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Pos (28UL)   /*!< Position of OUTB12 field.                                            */
102562   #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB12_Pos) /*!< Bit mask of OUTB12 field.        */
102563   #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Min (0x0UL)  /*!< Min enumerator value of OUTB12 field.                                */
102564   #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_Max (0x1UL)  /*!< Max enumerator value of OUTB12 field.                                */
102565   #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
102566   #define VPRCSR_NORDIC_OUTBDTGL_OUTB12_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
102567 
102568 /* OUTB13 @Bit 29 : (unspecified) */
102569   #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Pos (29UL)   /*!< Position of OUTB13 field.                                            */
102570   #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB13_Pos) /*!< Bit mask of OUTB13 field.        */
102571   #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Min (0x0UL)  /*!< Min enumerator value of OUTB13 field.                                */
102572   #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_Max (0x1UL)  /*!< Max enumerator value of OUTB13 field.                                */
102573   #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
102574   #define VPRCSR_NORDIC_OUTBDTGL_OUTB13_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
102575 
102576 /* OUTB14 @Bit 30 : (unspecified) */
102577   #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Pos (30UL)   /*!< Position of OUTB14 field.                                            */
102578   #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB14_Pos) /*!< Bit mask of OUTB14 field.        */
102579   #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Min (0x0UL)  /*!< Min enumerator value of OUTB14 field.                                */
102580   #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_Max (0x1UL)  /*!< Max enumerator value of OUTB14 field.                                */
102581   #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
102582   #define VPRCSR_NORDIC_OUTBDTGL_OUTB14_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
102583 
102584 /* OUTB15 @Bit 31 : (unspecified) */
102585   #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Pos (31UL)   /*!< Position of OUTB15 field.                                            */
102586   #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Msk (0x1UL << VPRCSR_NORDIC_OUTBDTGL_OUTB15_Pos) /*!< Bit mask of OUTB15 field.        */
102587   #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Min (0x0UL)  /*!< Min enumerator value of OUTB15 field.                                */
102588   #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_Max (0x1UL)  /*!< Max enumerator value of OUTB15 field.                                */
102589   #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_UNCHANGED (0x0UL) /*!< Pin remains unchanged                                           */
102590   #define VPRCSR_NORDIC_OUTBDTGL_OUTB15_TOGGLE (0x1UL) /*!< Pin is toggled                                                     */
102591 
102592 
102593 /**
102594   * @brief OUTBDS [VPRCSR_NORDIC_OUTBDS] OUTBD Dirty Status
102595   */
102596   #define VPRCSR_NORDIC_OUTBDS (0x00000BE2ul)
102597   #define VPRCSR_NORDIC_OUTBDS_ResetValue (0x00000000UL) /*!< Reset value of OUTBDS register.                                  */
102598 
102599 /* OUTBD @Bits 0..31 : Write to OUTBD register (if not dirty) */
102600   #define VPRCSR_NORDIC_OUTBDS_OUTBD_Pos (0UL)       /*!< Position of OUTBD field.                                             */
102601   #define VPRCSR_NORDIC_OUTBDS_OUTBD_Msk (0xFFFFFFFFUL << VPRCSR_NORDIC_OUTBDS_OUTBD_Pos) /*!< Bit mask of OUTBD field.        */
102602 
102603 /* DIRTYBIT @Bit 0 : Read OUTB and OUT parallel write Dirty status */
102604   #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Pos (0UL)    /*!< Position of DIRTYBIT field.                                          */
102605   #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Msk (0x1UL << VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Pos) /*!< Bit mask of DIRTYBIT field.      */
102606   #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Min (0x0UL)  /*!< Min enumerator value of DIRTYBIT field.                              */
102607   #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_Max (0x1UL)  /*!< Max enumerator value of DIRTYBIT field.                              */
102608   #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_CLEAN (0x0UL) /*!< Buffer is clean                                                     */
102609   #define VPRCSR_NORDIC_OUTBDS_DIRTYBIT_DIRTY (0x1UL) /*!< Buffer is dirty                                                     */
102610 
102611 
102612 /**
102613   * @brief OUTMODE [VPRCSR_NORDIC_OUTMODE] Serial output mode
102614   */
102615   #define VPRCSR_NORDIC_OUTMODE (0x00000BE3ul)
102616   #define VPRCSR_NORDIC_OUTMODE_ResetValue (0x00000000UL) /*!< Reset value of OUTMODE register.                                */
102617 
102618 /* SHIFTMODE @Bit 0 : Shift mode */
102619   #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Pos (0UL)  /*!< Position of SHIFTMODE field.                                         */
102620   #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Msk (0x1UL << VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Pos) /*!< Bit mask of SHIFTMODE field. */
102621   #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Min (0x0UL) /*!< Min enumerator value of SHIFTMODE field.                            */
102622   #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Max (0x1UL) /*!< Max enumerator value of SHIFTMODE field.                            */
102623   #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Disabled (0x0UL) /*!< Shift mode is disabled                                         */
102624   #define VPRCSR_NORDIC_OUTMODE_SHIFTMODE_Enabled (0x1UL) /*!< Shift mode is enabled                                           */
102625 
102626 /* SHIFSIZE @Bits 16..19 : Shift size. Only applies if Shift mode is enabled */
102627   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Pos (16UL)  /*!< Position of SHIFSIZE field.                                          */
102628   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Msk (0xFUL << VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Pos) /*!< Bit mask of SHIFSIZE field.    */
102629   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Min (0x0UL) /*!< Min enumerator value of SHIFSIZE field.                              */
102630   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_Max (0x4UL) /*!< Max enumerator value of SHIFSIZE field.                              */
102631   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT1 (0x0UL) /*!< Shift OUT by 1 bit                                                */
102632   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT2 (0x1UL) /*!< Shift OUT by 2 bits                                               */
102633   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT4 (0x2UL) /*!< Shift OUT by 4 bits                                               */
102634   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT8 (0x3UL) /*!< Shift OUT by 8 bits                                               */
102635   #define VPRCSR_NORDIC_OUTMODE_SHIFSIZE_SHIFT16 (0x4UL) /*!< Shift OUT by 16 bits                                             */
102636 
102637 
102638 
102639 
102640 /* =========================================================================================================================== */
102641 /* ================                                         VPRPUBLIC                                         ================ */
102642 /* =========================================================================================================================== */
102643 
102644 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
102645 /* ==================================================== Struct VPRPUBLIC ===================================================== */
102646 /**
102647   * @brief VPR peripheral registers
102648   */
102649   typedef struct {                                   /*!< VPRPUBLIC Structure                                                  */
102650     __OM uint32_t TASKS_TRIGGER[32];                 /*!< (@ 0x00000000) VPR task [n] register                                 */
102651   } NRF_VPRPUBLIC_Type;                              /*!< Size = 128 (0x080)                                                   */
102652 
102653 /* VPRPUBLIC_TASKS_TRIGGER: VPR task [n] register */
102654   #define VPRPUBLIC_TASKS_TRIGGER_MaxCount (32UL)    /*!< Max size of TASKS_TRIGGER[32] array.                                 */
102655   #define VPRPUBLIC_TASKS_TRIGGER_MaxIndex (31UL)    /*!< Max index of TASKS_TRIGGER[32] array.                                */
102656   #define VPRPUBLIC_TASKS_TRIGGER_MinIndex (0UL)     /*!< Min index of TASKS_TRIGGER[32] array.                                */
102657   #define VPRPUBLIC_TASKS_TRIGGER_ResetValue (0x00000000UL) /*!< Reset value of TASKS_TRIGGER[32] register.                    */
102658 
102659 /* TASKS_TRIGGER @Bit 0 : VPR task [n] register */
102660   #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field.                                */
102661   #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of
102662                                                                             TASKS_TRIGGER field.*/
102663   #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Min (0x1UL) /*!< Min enumerator value of TASKS_TRIGGER field.                  */
102664   #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Max (0x1UL) /*!< Max enumerator value of TASKS_TRIGGER field.                  */
102665   #define VPRPUBLIC_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task                                              */
102666 
102667 
102668 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
102669 
102670 /* =========================================================================================================================== */
102671 /* ================                                           VTIM                                           ================ */
102672 /* =========================================================================================================================== */
102673 
102674 /**
102675   * @brief VTIM CSR registers
102676   */
102677 
102678 
102679 /* =========================================================================================================================== */
102680 /* ================                                            WDT                                            ================ */
102681 /* =========================================================================================================================== */
102682 
102683 #if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code.                                 */
102684 /* ======================================================= Struct WDT ======================================================== */
102685 /**
102686   * @brief Watchdog Timer
102687   */
102688   typedef struct {                                   /*!< WDT Structure                                                        */
102689     __OM uint32_t TASKS_START;                       /*!< (@ 0x00000000) Start WDT                                             */
102690     __OM uint32_t TASKS_STOP;                        /*!< (@ 0x00000004) Stop WDT                                              */
102691     __IM uint32_t RESERVED[30];
102692     __IOM uint32_t SUBSCRIBE_START;                  /*!< (@ 0x00000080) Subscribe configuration for task START                */
102693     __IOM uint32_t SUBSCRIBE_STOP;                   /*!< (@ 0x00000084) Subscribe configuration for task STOP                 */
102694     __IM uint32_t RESERVED1[30];
102695     __IOM uint32_t EVENTS_TIMEOUT;                   /*!< (@ 0x00000100) Watchdog timeout                                      */
102696     __IOM uint32_t EVENTS_STOPPED;                   /*!< (@ 0x00000104) Watchdog stopped                                      */
102697     __IM uint32_t RESERVED2[30];
102698     __IOM uint32_t PUBLISH_TIMEOUT;                  /*!< (@ 0x00000180) Publish configuration for event TIMEOUT               */
102699     __IOM uint32_t PUBLISH_STOPPED;                  /*!< (@ 0x00000184) Publish configuration for event STOPPED               */
102700     __IM uint32_t RESERVED3[95];
102701     __IOM uint32_t INTENSET;                         /*!< (@ 0x00000304) Enable interrupt                                      */
102702     __IOM uint32_t INTENCLR;                         /*!< (@ 0x00000308) Disable interrupt                                     */
102703     __IM uint32_t RESERVED4[6];
102704     __IOM uint32_t NMIENSET;                         /*!< (@ 0x00000324) Enable interrupt                                      */
102705     __IOM uint32_t NMIENCLR;                         /*!< (@ 0x00000328) Disable interrupt                                     */
102706     __IM uint32_t RESERVED5[53];
102707     __IM uint32_t RUNSTATUS;                         /*!< (@ 0x00000400) Run status                                            */
102708     __IM uint32_t REQSTATUS;                         /*!< (@ 0x00000404) Request status                                        */
102709     __IM uint32_t RESERVED6[63];
102710     __IOM uint32_t CRV;                              /*!< (@ 0x00000504) Counter reload value                                  */
102711     __IOM uint32_t RREN;                             /*!< (@ 0x00000508) Enable register for reload request registers          */
102712     __IOM uint32_t CONFIG;                           /*!< (@ 0x0000050C) Configuration register                                */
102713     __IM uint32_t RESERVED7[4];
102714     __OM uint32_t TSEN;                              /*!< (@ 0x00000520) Task stop enable                                      */
102715     __IM uint32_t RESERVED8[55];
102716     __OM uint32_t RR[8];                             /*!< (@ 0x00000600) Reload request n                                      */
102717   } NRF_WDT_Type;                                    /*!< Size = 1568 (0x620)                                                  */
102718 
102719 /* WDT_TASKS_START: Start WDT */
102720   #define WDT_TASKS_START_ResetValue (0x00000000UL)  /*!< Reset value of TASKS_START register.                                 */
102721 
102722 /* TASKS_START @Bit 0 : Start WDT */
102723   #define WDT_TASKS_START_TASKS_START_Pos (0UL)      /*!< Position of TASKS_START field.                                       */
102724   #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field.       */
102725   #define WDT_TASKS_START_TASKS_START_Min (0x1UL)    /*!< Min enumerator value of TASKS_START field.                           */
102726   #define WDT_TASKS_START_TASKS_START_Max (0x1UL)    /*!< Max enumerator value of TASKS_START field.                           */
102727   #define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task                                                        */
102728 
102729 
102730 /* WDT_TASKS_STOP: Stop WDT */
102731   #define WDT_TASKS_STOP_ResetValue (0x00000000UL)   /*!< Reset value of TASKS_STOP register.                                  */
102732 
102733 /* TASKS_STOP @Bit 0 : Stop WDT */
102734   #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL)        /*!< Position of TASKS_STOP field.                                        */
102735   #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field.            */
102736   #define WDT_TASKS_STOP_TASKS_STOP_Min (0x1UL)      /*!< Min enumerator value of TASKS_STOP field.                            */
102737   #define WDT_TASKS_STOP_TASKS_STOP_Max (0x1UL)      /*!< Max enumerator value of TASKS_STOP field.                            */
102738   #define WDT_TASKS_STOP_TASKS_STOP_Trigger (0x1UL)  /*!< Trigger task                                                         */
102739 
102740 
102741 /* WDT_SUBSCRIBE_START: Subscribe configuration for task START */
102742   #define WDT_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register.                          */
102743 
102744 /* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */
102745   #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
102746   #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
102747   #define WDT_SUBSCRIBE_START_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
102748   #define WDT_SUBSCRIBE_START_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
102749 
102750 /* EN @Bit 31 : (unspecified) */
102751   #define WDT_SUBSCRIBE_START_EN_Pos (31UL)          /*!< Position of EN field.                                                */
102752   #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field.                          */
102753   #define WDT_SUBSCRIBE_START_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
102754   #define WDT_SUBSCRIBE_START_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
102755   #define WDT_SUBSCRIBE_START_EN_Disabled (0x0UL)    /*!< Disable subscription                                                 */
102756   #define WDT_SUBSCRIBE_START_EN_Enabled (0x1UL)     /*!< Enable subscription                                                  */
102757 
102758 
102759 /* WDT_SUBSCRIBE_STOP: Subscribe configuration for task STOP */
102760   #define WDT_SUBSCRIBE_STOP_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_STOP register.                            */
102761 
102762 /* CHIDX @Bits 0..7 : DPPI channel that task STOP will subscribe to */
102763   #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL)         /*!< Position of CHIDX field.                                             */
102764   #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field.                  */
102765   #define WDT_SUBSCRIBE_STOP_CHIDX_Min (0x0UL)       /*!< Min value of CHIDX field.                                            */
102766   #define WDT_SUBSCRIBE_STOP_CHIDX_Max (0xFFUL)      /*!< Max size of CHIDX field.                                             */
102767 
102768 /* EN @Bit 31 : (unspecified) */
102769   #define WDT_SUBSCRIBE_STOP_EN_Pos (31UL)           /*!< Position of EN field.                                                */
102770   #define WDT_SUBSCRIBE_STOP_EN_Msk (0x1UL << WDT_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field.                            */
102771   #define WDT_SUBSCRIBE_STOP_EN_Min (0x0UL)          /*!< Min enumerator value of EN field.                                    */
102772   #define WDT_SUBSCRIBE_STOP_EN_Max (0x1UL)          /*!< Max enumerator value of EN field.                                    */
102773   #define WDT_SUBSCRIBE_STOP_EN_Disabled (0x0UL)     /*!< Disable subscription                                                 */
102774   #define WDT_SUBSCRIBE_STOP_EN_Enabled (0x1UL)      /*!< Enable subscription                                                  */
102775 
102776 
102777 /* WDT_EVENTS_TIMEOUT: Watchdog timeout */
102778   #define WDT_EVENTS_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TIMEOUT register.                            */
102779 
102780 /* EVENTS_TIMEOUT @Bit 0 : Watchdog timeout */
102781   #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field.                                   */
102782   #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT
102783                                                                             field.*/
102784   #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Min (0x0UL) /*!< Min enumerator value of EVENTS_TIMEOUT field.                     */
102785   #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Max (0x1UL) /*!< Max enumerator value of EVENTS_TIMEOUT field.                     */
102786   #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated                                      */
102787   #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated                                             */
102788 
102789 
102790 /* WDT_EVENTS_STOPPED: Watchdog stopped */
102791   #define WDT_EVENTS_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STOPPED register.                            */
102792 
102793 /* EVENTS_STOPPED @Bit 0 : Watchdog stopped */
102794   #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field.                                   */
102795   #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << WDT_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED
102796                                                                             field.*/
102797   #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STOPPED field.                     */
102798   #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STOPPED field.                     */
102799   #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated                                      */
102800   #define WDT_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated                                             */
102801 
102802 
102803 /* WDT_PUBLISH_TIMEOUT: Publish configuration for event TIMEOUT */
102804   #define WDT_PUBLISH_TIMEOUT_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TIMEOUT register.                          */
102805 
102806 /* CHIDX @Bits 0..7 : DPPI channel that event TIMEOUT will publish to */
102807   #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
102808   #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
102809   #define WDT_PUBLISH_TIMEOUT_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
102810   #define WDT_PUBLISH_TIMEOUT_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
102811 
102812 /* EN @Bit 31 : (unspecified) */
102813   #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL)          /*!< Position of EN field.                                                */
102814   #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field.                          */
102815   #define WDT_PUBLISH_TIMEOUT_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
102816   #define WDT_PUBLISH_TIMEOUT_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
102817   #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
102818   #define WDT_PUBLISH_TIMEOUT_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
102819 
102820 
102821 /* WDT_PUBLISH_STOPPED: Publish configuration for event STOPPED */
102822   #define WDT_PUBLISH_STOPPED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STOPPED register.                          */
102823 
102824 /* CHIDX @Bits 0..7 : DPPI channel that event STOPPED will publish to */
102825   #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL)        /*!< Position of CHIDX field.                                             */
102826   #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field.                */
102827   #define WDT_PUBLISH_STOPPED_CHIDX_Min (0x0UL)      /*!< Min value of CHIDX field.                                            */
102828   #define WDT_PUBLISH_STOPPED_CHIDX_Max (0xFFUL)     /*!< Max size of CHIDX field.                                             */
102829 
102830 /* EN @Bit 31 : (unspecified) */
102831   #define WDT_PUBLISH_STOPPED_EN_Pos (31UL)          /*!< Position of EN field.                                                */
102832   #define WDT_PUBLISH_STOPPED_EN_Msk (0x1UL << WDT_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field.                          */
102833   #define WDT_PUBLISH_STOPPED_EN_Min (0x0UL)         /*!< Min enumerator value of EN field.                                    */
102834   #define WDT_PUBLISH_STOPPED_EN_Max (0x1UL)         /*!< Max enumerator value of EN field.                                    */
102835   #define WDT_PUBLISH_STOPPED_EN_Disabled (0x0UL)    /*!< Disable publishing                                                   */
102836   #define WDT_PUBLISH_STOPPED_EN_Enabled (0x1UL)     /*!< Enable publishing                                                    */
102837 
102838 
102839 /* WDT_INTENSET: Enable interrupt */
102840   #define WDT_INTENSET_ResetValue (0x00000000UL)     /*!< Reset value of INTENSET register.                                    */
102841 
102842 /* TIMEOUT @Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
102843   #define WDT_INTENSET_TIMEOUT_Pos (0UL)             /*!< Position of TIMEOUT field.                                           */
102844   #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.                         */
102845   #define WDT_INTENSET_TIMEOUT_Min (0x0UL)           /*!< Min enumerator value of TIMEOUT field.                               */
102846   #define WDT_INTENSET_TIMEOUT_Max (0x1UL)           /*!< Max enumerator value of TIMEOUT field.                               */
102847   #define WDT_INTENSET_TIMEOUT_Set (0x1UL)           /*!< Enable                                                               */
102848   #define WDT_INTENSET_TIMEOUT_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
102849   #define WDT_INTENSET_TIMEOUT_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
102850 
102851 /* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
102852   #define WDT_INTENSET_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
102853   #define WDT_INTENSET_STOPPED_Msk (0x1UL << WDT_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
102854   #define WDT_INTENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
102855   #define WDT_INTENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
102856   #define WDT_INTENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
102857   #define WDT_INTENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
102858   #define WDT_INTENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
102859 
102860 
102861 /* WDT_INTENCLR: Disable interrupt */
102862   #define WDT_INTENCLR_ResetValue (0x00000000UL)     /*!< Reset value of INTENCLR register.                                    */
102863 
102864 /* TIMEOUT @Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
102865   #define WDT_INTENCLR_TIMEOUT_Pos (0UL)             /*!< Position of TIMEOUT field.                                           */
102866   #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.                         */
102867   #define WDT_INTENCLR_TIMEOUT_Min (0x0UL)           /*!< Min enumerator value of TIMEOUT field.                               */
102868   #define WDT_INTENCLR_TIMEOUT_Max (0x1UL)           /*!< Max enumerator value of TIMEOUT field.                               */
102869   #define WDT_INTENCLR_TIMEOUT_Clear (0x1UL)         /*!< Disable                                                              */
102870   #define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
102871   #define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
102872 
102873 /* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
102874   #define WDT_INTENCLR_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
102875   #define WDT_INTENCLR_STOPPED_Msk (0x1UL << WDT_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
102876   #define WDT_INTENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
102877   #define WDT_INTENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
102878   #define WDT_INTENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
102879   #define WDT_INTENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
102880   #define WDT_INTENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
102881 
102882 
102883 /* WDT_NMIENSET: Enable interrupt */
102884   #define WDT_NMIENSET_ResetValue (0x00000000UL)     /*!< Reset value of NMIENSET register.                                    */
102885 
102886 /* TIMEOUT @Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
102887   #define WDT_NMIENSET_TIMEOUT_Pos (0UL)             /*!< Position of TIMEOUT field.                                           */
102888   #define WDT_NMIENSET_TIMEOUT_Msk (0x1UL << WDT_NMIENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.                         */
102889   #define WDT_NMIENSET_TIMEOUT_Min (0x0UL)           /*!< Min enumerator value of TIMEOUT field.                               */
102890   #define WDT_NMIENSET_TIMEOUT_Max (0x1UL)           /*!< Max enumerator value of TIMEOUT field.                               */
102891   #define WDT_NMIENSET_TIMEOUT_Set (0x1UL)           /*!< Enable                                                               */
102892   #define WDT_NMIENSET_TIMEOUT_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
102893   #define WDT_NMIENSET_TIMEOUT_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
102894 
102895 /* STOPPED @Bit 1 : Write '1' to enable interrupt for event STOPPED */
102896   #define WDT_NMIENSET_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
102897   #define WDT_NMIENSET_STOPPED_Msk (0x1UL << WDT_NMIENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
102898   #define WDT_NMIENSET_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
102899   #define WDT_NMIENSET_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
102900   #define WDT_NMIENSET_STOPPED_Set (0x1UL)           /*!< Enable                                                               */
102901   #define WDT_NMIENSET_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
102902   #define WDT_NMIENSET_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
102903 
102904 
102905 /* WDT_NMIENCLR: Disable interrupt */
102906   #define WDT_NMIENCLR_ResetValue (0x00000000UL)     /*!< Reset value of NMIENCLR register.                                    */
102907 
102908 /* TIMEOUT @Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
102909   #define WDT_NMIENCLR_TIMEOUT_Pos (0UL)             /*!< Position of TIMEOUT field.                                           */
102910   #define WDT_NMIENCLR_TIMEOUT_Msk (0x1UL << WDT_NMIENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field.                         */
102911   #define WDT_NMIENCLR_TIMEOUT_Min (0x0UL)           /*!< Min enumerator value of TIMEOUT field.                               */
102912   #define WDT_NMIENCLR_TIMEOUT_Max (0x1UL)           /*!< Max enumerator value of TIMEOUT field.                               */
102913   #define WDT_NMIENCLR_TIMEOUT_Clear (0x1UL)         /*!< Disable                                                              */
102914   #define WDT_NMIENCLR_TIMEOUT_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
102915   #define WDT_NMIENCLR_TIMEOUT_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
102916 
102917 /* STOPPED @Bit 1 : Write '1' to disable interrupt for event STOPPED */
102918   #define WDT_NMIENCLR_STOPPED_Pos (1UL)             /*!< Position of STOPPED field.                                           */
102919   #define WDT_NMIENCLR_STOPPED_Msk (0x1UL << WDT_NMIENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field.                         */
102920   #define WDT_NMIENCLR_STOPPED_Min (0x0UL)           /*!< Min enumerator value of STOPPED field.                               */
102921   #define WDT_NMIENCLR_STOPPED_Max (0x1UL)           /*!< Max enumerator value of STOPPED field.                               */
102922   #define WDT_NMIENCLR_STOPPED_Clear (0x1UL)         /*!< Disable                                                              */
102923   #define WDT_NMIENCLR_STOPPED_Disabled (0x0UL)      /*!< Read: Disabled                                                       */
102924   #define WDT_NMIENCLR_STOPPED_Enabled (0x1UL)       /*!< Read: Enabled                                                        */
102925 
102926 
102927 /* WDT_RUNSTATUS: Run status */
102928   #define WDT_RUNSTATUS_ResetValue (0x00000000UL)    /*!< Reset value of RUNSTATUS register.                                   */
102929 
102930 /* RUNSTATUSWDT @Bit 0 : Indicates whether or not WDT is running */
102931   #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL)       /*!< Position of RUNSTATUSWDT field.                                      */
102932   #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field.        */
102933   #define WDT_RUNSTATUS_RUNSTATUSWDT_Min (0x0UL)     /*!< Min enumerator value of RUNSTATUSWDT field.                          */
102934   #define WDT_RUNSTATUS_RUNSTATUSWDT_Max (0x1UL)     /*!< Max enumerator value of RUNSTATUSWDT field.                          */
102935   #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0x0UL) /*!< Watchdog is not running                                           */
102936   #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (0x1UL) /*!< Watchdog is running                                                  */
102937 
102938 
102939 /* WDT_REQSTATUS: Request status */
102940   #define WDT_REQSTATUS_ResetValue (0x00000001UL)    /*!< Reset value of REQSTATUS register.                                   */
102941 
102942 /* RR0 @Bit 0 : Request status for RR[0] register */
102943   #define WDT_REQSTATUS_RR0_Pos (0UL)                /*!< Position of RR0 field.                                               */
102944   #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field.                                   */
102945   #define WDT_REQSTATUS_RR0_Min (0x0UL)              /*!< Min enumerator value of RR0 field.                                   */
102946   #define WDT_REQSTATUS_RR0_Max (0x1UL)              /*!< Max enumerator value of RR0 field.                                   */
102947   #define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or are already requesting reload   */
102948   #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and are not yet requesting reload    */
102949 
102950 /* RR1 @Bit 1 : Request status for RR[1] register */
102951   #define WDT_REQSTATUS_RR1_Pos (1UL)                /*!< Position of RR1 field.                                               */
102952   #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field.                                   */
102953   #define WDT_REQSTATUS_RR1_Min (0x0UL)              /*!< Min enumerator value of RR1 field.                                   */
102954   #define WDT_REQSTATUS_RR1_Max (0x1UL)              /*!< Max enumerator value of RR1 field.                                   */
102955   #define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or are already requesting reload   */
102956   #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and are not yet requesting reload    */
102957 
102958 /* RR2 @Bit 2 : Request status for RR[2] register */
102959   #define WDT_REQSTATUS_RR2_Pos (2UL)                /*!< Position of RR2 field.                                               */
102960   #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field.                                   */
102961   #define WDT_REQSTATUS_RR2_Min (0x0UL)              /*!< Min enumerator value of RR2 field.                                   */
102962   #define WDT_REQSTATUS_RR2_Max (0x1UL)              /*!< Max enumerator value of RR2 field.                                   */
102963   #define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or are already requesting reload   */
102964   #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and are not yet requesting reload    */
102965 
102966 /* RR3 @Bit 3 : Request status for RR[3] register */
102967   #define WDT_REQSTATUS_RR3_Pos (3UL)                /*!< Position of RR3 field.                                               */
102968   #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field.                                   */
102969   #define WDT_REQSTATUS_RR3_Min (0x0UL)              /*!< Min enumerator value of RR3 field.                                   */
102970   #define WDT_REQSTATUS_RR3_Max (0x1UL)              /*!< Max enumerator value of RR3 field.                                   */
102971   #define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or are already requesting reload   */
102972   #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and are not yet requesting reload    */
102973 
102974 /* RR4 @Bit 4 : Request status for RR[4] register */
102975   #define WDT_REQSTATUS_RR4_Pos (4UL)                /*!< Position of RR4 field.                                               */
102976   #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field.                                   */
102977   #define WDT_REQSTATUS_RR4_Min (0x0UL)              /*!< Min enumerator value of RR4 field.                                   */
102978   #define WDT_REQSTATUS_RR4_Max (0x1UL)              /*!< Max enumerator value of RR4 field.                                   */
102979   #define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or are already requesting reload   */
102980   #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and are not yet requesting reload    */
102981 
102982 /* RR5 @Bit 5 : Request status for RR[5] register */
102983   #define WDT_REQSTATUS_RR5_Pos (5UL)                /*!< Position of RR5 field.                                               */
102984   #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field.                                   */
102985   #define WDT_REQSTATUS_RR5_Min (0x0UL)              /*!< Min enumerator value of RR5 field.                                   */
102986   #define WDT_REQSTATUS_RR5_Max (0x1UL)              /*!< Max enumerator value of RR5 field.                                   */
102987   #define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or are already requesting reload   */
102988   #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and are not yet requesting reload    */
102989 
102990 /* RR6 @Bit 6 : Request status for RR[6] register */
102991   #define WDT_REQSTATUS_RR6_Pos (6UL)                /*!< Position of RR6 field.                                               */
102992   #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field.                                   */
102993   #define WDT_REQSTATUS_RR6_Min (0x0UL)              /*!< Min enumerator value of RR6 field.                                   */
102994   #define WDT_REQSTATUS_RR6_Max (0x1UL)              /*!< Max enumerator value of RR6 field.                                   */
102995   #define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or are already requesting reload   */
102996   #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and are not yet requesting reload    */
102997 
102998 /* RR7 @Bit 7 : Request status for RR[7] register */
102999   #define WDT_REQSTATUS_RR7_Pos (7UL)                /*!< Position of RR7 field.                                               */
103000   #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field.                                   */
103001   #define WDT_REQSTATUS_RR7_Min (0x0UL)              /*!< Min enumerator value of RR7 field.                                   */
103002   #define WDT_REQSTATUS_RR7_Max (0x1UL)              /*!< Max enumerator value of RR7 field.                                   */
103003   #define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or are already requesting reload   */
103004   #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and are not yet requesting reload    */
103005 
103006 
103007 /* WDT_CRV: Counter reload value */
103008   #define WDT_CRV_ResetValue (0xFFFFFFFFUL)          /*!< Reset value of CRV register.                                         */
103009 
103010 /* CRV @Bits 0..31 : Counter reload value in number of cycles of the 32.768 kHz clock */
103011   #define WDT_CRV_CRV_Pos (0UL)                      /*!< Position of CRV field.                                               */
103012   #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field.                                        */
103013   #define WDT_CRV_CRV_Min (0xFUL)                    /*!< Min value of CRV field.                                              */
103014   #define WDT_CRV_CRV_Max (0xFFFFFFFFUL)             /*!< Max size of CRV field.                                               */
103015 
103016 
103017 /* WDT_RREN: Enable register for reload request registers */
103018   #define WDT_RREN_ResetValue (0x00000001UL)         /*!< Reset value of RREN register.                                        */
103019 
103020 /* RR0 @Bit 0 : Enable or disable RR[0] register */
103021   #define WDT_RREN_RR0_Pos (0UL)                     /*!< Position of RR0 field.                                               */
103022   #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field.                                             */
103023   #define WDT_RREN_RR0_Min (0x0UL)                   /*!< Min enumerator value of RR0 field.                                   */
103024   #define WDT_RREN_RR0_Max (0x1UL)                   /*!< Max enumerator value of RR0 field.                                   */
103025   #define WDT_RREN_RR0_Disabled (0x0UL)              /*!< Disable RR[0] register                                               */
103026   #define WDT_RREN_RR0_Enabled (0x1UL)               /*!< Enable RR[0] register                                                */
103027 
103028 /* RR1 @Bit 1 : Enable or disable RR[1] register */
103029   #define WDT_RREN_RR1_Pos (1UL)                     /*!< Position of RR1 field.                                               */
103030   #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field.                                             */
103031   #define WDT_RREN_RR1_Min (0x0UL)                   /*!< Min enumerator value of RR1 field.                                   */
103032   #define WDT_RREN_RR1_Max (0x1UL)                   /*!< Max enumerator value of RR1 field.                                   */
103033   #define WDT_RREN_RR1_Disabled (0x0UL)              /*!< Disable RR[1] register                                               */
103034   #define WDT_RREN_RR1_Enabled (0x1UL)               /*!< Enable RR[1] register                                                */
103035 
103036 /* RR2 @Bit 2 : Enable or disable RR[2] register */
103037   #define WDT_RREN_RR2_Pos (2UL)                     /*!< Position of RR2 field.                                               */
103038   #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field.                                             */
103039   #define WDT_RREN_RR2_Min (0x0UL)                   /*!< Min enumerator value of RR2 field.                                   */
103040   #define WDT_RREN_RR2_Max (0x1UL)                   /*!< Max enumerator value of RR2 field.                                   */
103041   #define WDT_RREN_RR2_Disabled (0x0UL)              /*!< Disable RR[2] register                                               */
103042   #define WDT_RREN_RR2_Enabled (0x1UL)               /*!< Enable RR[2] register                                                */
103043 
103044 /* RR3 @Bit 3 : Enable or disable RR[3] register */
103045   #define WDT_RREN_RR3_Pos (3UL)                     /*!< Position of RR3 field.                                               */
103046   #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field.                                             */
103047   #define WDT_RREN_RR3_Min (0x0UL)                   /*!< Min enumerator value of RR3 field.                                   */
103048   #define WDT_RREN_RR3_Max (0x1UL)                   /*!< Max enumerator value of RR3 field.                                   */
103049   #define WDT_RREN_RR3_Disabled (0x0UL)              /*!< Disable RR[3] register                                               */
103050   #define WDT_RREN_RR3_Enabled (0x1UL)               /*!< Enable RR[3] register                                                */
103051 
103052 /* RR4 @Bit 4 : Enable or disable RR[4] register */
103053   #define WDT_RREN_RR4_Pos (4UL)                     /*!< Position of RR4 field.                                               */
103054   #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field.                                             */
103055   #define WDT_RREN_RR4_Min (0x0UL)                   /*!< Min enumerator value of RR4 field.                                   */
103056   #define WDT_RREN_RR4_Max (0x1UL)                   /*!< Max enumerator value of RR4 field.                                   */
103057   #define WDT_RREN_RR4_Disabled (0x0UL)              /*!< Disable RR[4] register                                               */
103058   #define WDT_RREN_RR4_Enabled (0x1UL)               /*!< Enable RR[4] register                                                */
103059 
103060 /* RR5 @Bit 5 : Enable or disable RR[5] register */
103061   #define WDT_RREN_RR5_Pos (5UL)                     /*!< Position of RR5 field.                                               */
103062   #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field.                                             */
103063   #define WDT_RREN_RR5_Min (0x0UL)                   /*!< Min enumerator value of RR5 field.                                   */
103064   #define WDT_RREN_RR5_Max (0x1UL)                   /*!< Max enumerator value of RR5 field.                                   */
103065   #define WDT_RREN_RR5_Disabled (0x0UL)              /*!< Disable RR[5] register                                               */
103066   #define WDT_RREN_RR5_Enabled (0x1UL)               /*!< Enable RR[5] register                                                */
103067 
103068 /* RR6 @Bit 6 : Enable or disable RR[6] register */
103069   #define WDT_RREN_RR6_Pos (6UL)                     /*!< Position of RR6 field.                                               */
103070   #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field.                                             */
103071   #define WDT_RREN_RR6_Min (0x0UL)                   /*!< Min enumerator value of RR6 field.                                   */
103072   #define WDT_RREN_RR6_Max (0x1UL)                   /*!< Max enumerator value of RR6 field.                                   */
103073   #define WDT_RREN_RR6_Disabled (0x0UL)              /*!< Disable RR[6] register                                               */
103074   #define WDT_RREN_RR6_Enabled (0x1UL)               /*!< Enable RR[6] register                                                */
103075 
103076 /* RR7 @Bit 7 : Enable or disable RR[7] register */
103077   #define WDT_RREN_RR7_Pos (7UL)                     /*!< Position of RR7 field.                                               */
103078   #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field.                                             */
103079   #define WDT_RREN_RR7_Min (0x0UL)                   /*!< Min enumerator value of RR7 field.                                   */
103080   #define WDT_RREN_RR7_Max (0x1UL)                   /*!< Max enumerator value of RR7 field.                                   */
103081   #define WDT_RREN_RR7_Disabled (0x0UL)              /*!< Disable RR[7] register                                               */
103082   #define WDT_RREN_RR7_Enabled (0x1UL)               /*!< Enable RR[7] register                                                */
103083 
103084 
103085 /* WDT_CONFIG: Configuration register */
103086   #define WDT_CONFIG_ResetValue (0x00000001UL)       /*!< Reset value of CONFIG register.                                      */
103087 
103088 /* SLEEP @Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */
103089   #define WDT_CONFIG_SLEEP_Pos (0UL)                 /*!< Position of SLEEP field.                                             */
103090   #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field.                                   */
103091   #define WDT_CONFIG_SLEEP_Min (0x0UL)               /*!< Min enumerator value of SLEEP field.                                 */
103092   #define WDT_CONFIG_SLEEP_Max (0x1UL)               /*!< Max enumerator value of SLEEP field.                                 */
103093   #define WDT_CONFIG_SLEEP_Pause (0x0UL)             /*!< Pause WDT while the CPU is sleeping                                  */
103094   #define WDT_CONFIG_SLEEP_Run (0x1UL)               /*!< Keep WDT running while the CPU is sleeping                           */
103095 
103096 /* HALT @Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */
103097   #define WDT_CONFIG_HALT_Pos (3UL)                  /*!< Position of HALT field.                                              */
103098   #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field.                                      */
103099   #define WDT_CONFIG_HALT_Min (0x0UL)                /*!< Min enumerator value of HALT field.                                  */
103100   #define WDT_CONFIG_HALT_Max (0x1UL)                /*!< Max enumerator value of HALT field.                                  */
103101   #define WDT_CONFIG_HALT_Pause (0x0UL)              /*!< Pause WDT while the CPU is halted by the debugger                    */
103102   #define WDT_CONFIG_HALT_Run (0x1UL)                /*!< Keep WDT running while the CPU is halted by the debugger             */
103103 
103104 /* STOPEN @Bit 6 : Allow stopping WDT */
103105   #define WDT_CONFIG_STOPEN_Pos (6UL)                /*!< Position of STOPEN field.                                            */
103106   #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field.                                */
103107   #define WDT_CONFIG_STOPEN_Min (0x0UL)              /*!< Min enumerator value of STOPEN field.                                */
103108   #define WDT_CONFIG_STOPEN_Max (0x1UL)              /*!< Max enumerator value of STOPEN field.                                */
103109   #define WDT_CONFIG_STOPEN_Disable (0x0UL)          /*!< Do not allow stopping WDT                                            */
103110   #define WDT_CONFIG_STOPEN_Enable (0x1UL)           /*!< Allow stopping WDT                                                   */
103111 
103112 
103113 /* WDT_TSEN: Task stop enable */
103114   #define WDT_TSEN_ResetValue (0x00000000UL)         /*!< Reset value of TSEN register.                                        */
103115 
103116 /* TSEN @Bits 0..31 : Allow stopping WDT */
103117   #define WDT_TSEN_TSEN_Pos (0UL)                    /*!< Position of TSEN field.                                              */
103118   #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field.                                   */
103119   #define WDT_TSEN_TSEN_Min (0x6E524635UL)           /*!< Min enumerator value of TSEN field.                                  */
103120   #define WDT_TSEN_TSEN_Max (0x6E524635UL)           /*!< Max enumerator value of TSEN field.                                  */
103121   #define WDT_TSEN_TSEN_Enable (0x6E524635UL)        /*!< Value to allow stopping WDT                                          */
103122 
103123 
103124 /* WDT_RR: Reload request n */
103125   #define WDT_RR_MaxCount (8UL)                      /*!< Max size of RR[8] array.                                             */
103126   #define WDT_RR_MaxIndex (7UL)                      /*!< Max index of RR[8] array.                                            */
103127   #define WDT_RR_MinIndex (0UL)                      /*!< Min index of RR[8] array.                                            */
103128   #define WDT_RR_ResetValue (0x00000000UL)           /*!< Reset value of RR[8] register.                                       */
103129 
103130 /* RR @Bits 0..31 : Reload request register */
103131   #define WDT_RR_RR_Pos (0UL)                        /*!< Position of RR field.                                                */
103132   #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field.                                             */
103133   #define WDT_RR_RR_Min (0x6E524635UL)               /*!< Min enumerator value of RR field.                                    */
103134   #define WDT_RR_RR_Max (0x6E524635UL)               /*!< Max enumerator value of RR field.                                    */
103135   #define WDT_RR_RR_Reload (0x6E524635UL)            /*!< Value to request a reload of the watchdog timer                      */
103136 
103137 
103138 #endif                                               /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)                    */
103139 
103140 /* ========================================== End of section using anonymous unions ========================================== */
103141 
103142 #if defined (__CC_ARM)
103143   #pragma pop
103144 #elif defined (__ICCARM__)
103145   /* leave anonymous unions enabled */
103146 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
103147   #pragma clang diagnostic pop
103148 #elif defined (__GNUC__)
103149   /* anonymous unions are enabled by default */
103150 #elif defined (__TMS470__)
103151   /* anonymous unions are enabled by default */
103152 #elif defined (__TASKING__)
103153   #pragma warning restore
103154 #elif defined (__CSMC__)
103155   /* anonymous unions are enabled by default */
103156 #endif
103157 
103158 
103159 #ifdef __cplusplus
103160 }
103161 #endif
103162 #endif /* NRF54H20_ENGA_TYPES_H */
103163 
103164